diff --git a/Info.md b/Info.md index 28cd454..24fab5c 100644 --- a/Info.md +++ b/Info.md @@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING). # Details -Last updated on Wed 12 Jun 2019 11:15:19 AM UTC (2019-06-12T11:15:19+00:00). +Last updated on Wed 12 Jun 2019 11:20:54 AM UTC (2019-06-12T11:20:54+00:00). Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [d31319cc](https://github.com/SymbiFlow/prjxray/commit/d31319ccaa6f6fc4d1106890f9d72d908fa03b52). @@ -857,8 +857,8 @@ Results have checksums; * [`be757fb834be7ff84a2873c0ac6621c909a5e85362b397667760edde86616f84 ./zynq7/mask_hclk_cmt_l.db`](./zynq7/mask_hclk_cmt_l.db) * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_l.db`](./zynq7/mask_hclk_l.db) * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_r.db`](./zynq7/mask_hclk_r.db) - * [`13dcba800fad00a8a87930bae3b302b32fd875c1a55e156616eadbb04e92ba58 ./zynq7/mask_liob33.db`](./zynq7/mask_liob33.db) - * [`c45d74a80ffc51ec9ea12767877602de8432be7d5a11b5d1f4d81ad74e159d17 ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db) + * [`6e99ef6017891939248e9f03c630155243a819a2e0c4c51b4d78dc5b248c8dea ./zynq7/mask_liob33.db`](./zynq7/mask_liob33.db) + * [`ec6a38f311c53e65c876693548e585b534afa92f4fbee54d61e06729257cb2ec ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db) * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./zynq7/ppips_bram_int_interface_l.db`](./zynq7/ppips_bram_int_interface_l.db) * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./zynq7/ppips_bram_int_interface_r.db`](./zynq7/ppips_bram_int_interface_r.db) * [`2c68f8b128aeb79197013c3a1774522143a3507a8fa595a98c22dba2553fd5ce ./zynq7/ppips_bram_l.db`](./zynq7/ppips_bram_l.db) @@ -884,27 +884,49 @@ Results have checksums; * [`76c5978b345f11a9e46733a98875a6c419b75cf863a0e42d05e9ac94f9795bfc ./zynq7/ppips_rioi3_tbytesrc.db`](./zynq7/ppips_rioi3_tbytesrc.db) * [`a9705cd0ffc8f972a6c0981d65b200a93f0b0069327133bad2aff80a6fce08ab ./zynq7/ppips_rioi3_tbyteterm.db`](./zynq7/ppips_rioi3_tbyteterm.db) * [`8a2136e564ac92c06b226ef8715a122050fcabbb063f69eeaf46cfee5c89670f ./zynq7/segbits_bram_l.block_ram.db`](./zynq7/segbits_bram_l.block_ram.db) + * [`65b0fa7162231e9d1a9e30c64e9aad87bb3b8feaa40cf76055f96a7750d1e1da ./zynq7/segbits_bram_l.block_ram.origin_info.db`](./zynq7/segbits_bram_l.block_ram.origin_info.db) * [`53d975bf59b763b9f764106db362ee7f6a753e9e72a5e2be334041658a5ea4ba ./zynq7/segbits_bram_l.db`](./zynq7/segbits_bram_l.db) + * [`89afef6aeb8c2450530809968dce1dcafe51d63fdea282df97e7dc5878e375e2 ./zynq7/segbits_bram_l.origin_info.db`](./zynq7/segbits_bram_l.origin_info.db) * [`a635577b55878c69df492c16b67a1dfbd1d4b786a695abe3e95a62d9540ecea5 ./zynq7/segbits_bram_r.block_ram.db`](./zynq7/segbits_bram_r.block_ram.db) + * [`9b40402550b3a34067109372c2217e6bbef0744db204c38e4d7439f3ccba2474 ./zynq7/segbits_bram_r.block_ram.origin_info.db`](./zynq7/segbits_bram_r.block_ram.origin_info.db) * [`b826680f3768091cb345ca6e62e3210ffb53a88ebdfdf4ca70f466f80cdacb1f ./zynq7/segbits_bram_r.db`](./zynq7/segbits_bram_r.db) + * [`83d0ac8050043e2aa67aa0dc2ba60692eef30daf9256503ff70b3e3a6475e3ba ./zynq7/segbits_bram_r.origin_info.db`](./zynq7/segbits_bram_r.origin_info.db) * [`ef6706ef033396c75469738223e66d1b5f38b832e27b5bb80f07efd571e28fb7 ./zynq7/segbits_clbll_l.db`](./zynq7/segbits_clbll_l.db) + * [`4ddab18383430522a3aa8d49688487dd0c3895f36f2b9f1fecabfb695d0105e4 ./zynq7/segbits_clbll_l.origin_info.db`](./zynq7/segbits_clbll_l.origin_info.db) * [`53c0ea2b05a2c4ddf2b6cce38073534d0c21b893fc5783dc777d97de2f2d6a9e ./zynq7/segbits_clbll_r.db`](./zynq7/segbits_clbll_r.db) + * [`50987c8e8ff9a66860f88e0f3531e92c5738a11613bee61720bae862e04b7787 ./zynq7/segbits_clbll_r.origin_info.db`](./zynq7/segbits_clbll_r.origin_info.db) * [`e6459c01d0c1c7724fa02716103fd02a3e2a75d6b7326f4c937f158a264ffe85 ./zynq7/segbits_clblm_l.db`](./zynq7/segbits_clblm_l.db) + * [`467377976169e66212833dd5a92a1b0b19eae348b3fb113f0ea363097872c654 ./zynq7/segbits_clblm_l.origin_info.db`](./zynq7/segbits_clblm_l.origin_info.db) * [`5862b402a5e0a95be5f140112678fd39e1dc039bc339fda0e58111ca1ee9cb6e ./zynq7/segbits_clblm_r.db`](./zynq7/segbits_clblm_r.db) + * [`20c664e6d20851c1b05e851ed278958a8d0f8d06697afb5caa70c62d07622575 ./zynq7/segbits_clblm_r.origin_info.db`](./zynq7/segbits_clblm_r.origin_info.db) * [`8d43bd09b2f7127ff9ed4803b92303d72c827d10b8b8d943c295343257b3e818 ./zynq7/segbits_clk_bufg_bot_r.db`](./zynq7/segbits_clk_bufg_bot_r.db) + * [`8d17f7e9f3cdf3419760d2b74cd23c04ee560f2f2bc942b718201c445a922c34 ./zynq7/segbits_clk_bufg_bot_r.origin_info.db`](./zynq7/segbits_clk_bufg_bot_r.origin_info.db) * [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f ./zynq7/segbits_clk_bufg_rebuf.db`](./zynq7/segbits_clk_bufg_rebuf.db) + * [`8e5cb983e044d31803253720c5496b368d0edb6705008c4cda61c213f9d44511 ./zynq7/segbits_clk_bufg_rebuf.origin_info.db`](./zynq7/segbits_clk_bufg_rebuf.origin_info.db) * [`6da9671e724a74e370b805ddd47e04eefd89daa0af4331e841720f7586d7eb2a ./zynq7/segbits_clk_bufg_top_r.db`](./zynq7/segbits_clk_bufg_top_r.db) + * [`7497f9e1eb6208c157c3c1caeca7b94172a6bb4896e7cd6e3d28cf23c38c2281 ./zynq7/segbits_clk_bufg_top_r.origin_info.db`](./zynq7/segbits_clk_bufg_top_r.origin_info.db) * [`4383aafad32f56f21404c5e6092811874f869c920e23a02b57da8c3e739fe2a9 ./zynq7/segbits_clk_hrow_bot_r.db`](./zynq7/segbits_clk_hrow_bot_r.db) + * [`5b5c62b9cf274038a8f58aee5b1dfa715368a20912e0b909ff062b3a328a41a1 ./zynq7/segbits_clk_hrow_bot_r.origin_info.db`](./zynq7/segbits_clk_hrow_bot_r.origin_info.db) * [`972ea949e0bc360892d15ec0313d04e416a10a10fa594f3c361d37c357d59992 ./zynq7/segbits_clk_hrow_top_r.db`](./zynq7/segbits_clk_hrow_top_r.db) + * [`04051d28841ff3ec719ebae1182d13ca817cf5eadb039f76a2e12647e1abcf85 ./zynq7/segbits_clk_hrow_top_r.origin_info.db`](./zynq7/segbits_clk_hrow_top_r.origin_info.db) * [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e ./zynq7/segbits_dsp_l.db`](./zynq7/segbits_dsp_l.db) + * [`85105e324b53c9b8a3d60a3631e125c2e6dc1329e017636232313c4aa8e1576d ./zynq7/segbits_dsp_l.origin_info.db`](./zynq7/segbits_dsp_l.origin_info.db) * [`b014d7e2b101b0b0540a539cb74a76ccbe3a494e225e8e510bf258a457b18685 ./zynq7/segbits_dsp_r.db`](./zynq7/segbits_dsp_r.db) + * [`ec2c0e9896fc373927b2c1f3028aad90fa7126c76e99c8c29c2a86a35149aa81 ./zynq7/segbits_dsp_r.origin_info.db`](./zynq7/segbits_dsp_r.origin_info.db) * [`65c83253dc05bb790d71edc7f868f2f8c7e4d4c7817f073b9c853c1ac2e075b0 ./zynq7/segbits_hclk_cmt_l.db`](./zynq7/segbits_hclk_cmt_l.db) + * [`b9c2e06ffd7c000cc02ac06dba94ceef3c2cb150b32c4e69e7290b47ff0cbe3b ./zynq7/segbits_hclk_cmt_l.origin_info.db`](./zynq7/segbits_hclk_cmt_l.origin_info.db) * [`1c2c7229781a4a1d51bbbdeea76238b10497c043aaadf2a76de783041a201878 ./zynq7/segbits_hclk_l.db`](./zynq7/segbits_hclk_l.db) + * [`39179dfde43c6dd677c705082e1e7373d1866390cae064062f6eee50e7cd6ef6 ./zynq7/segbits_hclk_l.origin_info.db`](./zynq7/segbits_hclk_l.origin_info.db) * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db) - * [`ebcb17bbb3ae3ea76b20e86ad7efda9a36b2ee024c4b08e6d5e8bbf4bc7838cc ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db) - * [`90ac156ad102fd7f83f22f4cbbef5e1216b057c8c92fc1eec957f3c69c8b4368 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db) + * [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7 ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db) + * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db) + * [`df08da95cd2a0e27b13cb69daed140b50865dd3863d155178a23b85681bf7a39 ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db) + * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db) + * [`51e9f1cfd54a13565e631837d12482bfaf9f0bb29f6c500b7c2aba27a1290387 ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db) * [`d1ad493bd149ba47ac50a68fef57809d21a1ef36db63725317a12df9266ca8d8 ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db) - * [`32cae09e1ab0ba143570d702cfee2a3e04948c131f6511e6040c684638c67ed4 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db) + * [`caaa32eadfca7d6417a09d5357f8c1eea23bdb325164857de03b8798bdf252bb ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db) + * [`a674ba036253f38ac8fd6ab2e10039f3d8ecd2a670c50c0610100a9f2a9028c7 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db) + * [`35c3e42e279228ea12f3e27a874c52d1b1a7169403b3e9a28642698a80b63a3b ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db) * [`ee26e7dbf78c2a37118c49ce7edb5fa44afd51850a24824ba8b68e34366f0787 ./zynq7/settings.sh`](./zynq7/settings.sh) * [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./zynq7/site_type_BSCAN.json`](./zynq7/site_type_BSCAN.json) * [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./zynq7/site_type_BUFGCTRL.json`](./zynq7/site_type_BUFGCTRL.json) @@ -947,98 +969,98 @@ Results have checksums; * [`8e5baf846e629316cefb781c26c09b6a39ca509d03dd381967c3e92f429dbda3 ./zynq7/site_type_TIEOFF.json`](./zynq7/site_type_TIEOFF.json) * [`4a52214be0712e1f5e3746c304d3299fd2bfa9e578956df1d6fcd6128614da12 ./zynq7/site_type_USR_ACCESS.json`](./zynq7/site_type_USR_ACCESS.json) * [`f711f285e16aa11d4827ce8504e9413c8ccf87f9f86d108740738ae6cbb4f388 ./zynq7/site_type_XADC.json`](./zynq7/site_type_XADC.json) - * [`0bfdad62f04128ca4d469aa18b179cbd3bf78e40c6af50450c9ca85bfffd746f ./zynq7/tile_type_BRAM_INT_INTERFACE_L.json`](./zynq7/tile_type_BRAM_INT_INTERFACE_L.json) - * [`fd0b3b31118249e66193fa06633a58aa5d86820bed16d3f85497b886d2282845 ./zynq7/tile_type_BRAM_INT_INTERFACE_R.json`](./zynq7/tile_type_BRAM_INT_INTERFACE_R.json) - * [`23af85ab67092eb90d6b05c3bff539499494eaecb07b5063baa2aa494063a1ec ./zynq7/tile_type_BRAM_L.json`](./zynq7/tile_type_BRAM_L.json) - * [`3f080d03ca1d85aa81c2bae209cb401b8dcddd6e115ea8d16d735f2b4e6fc892 ./zynq7/tile_type_BRAM_R.json`](./zynq7/tile_type_BRAM_R.json) - * [`29e4879a736ff9d43178ba3887ba47b8f1190464dabf4eef7c8fe8d8d23647c2 ./zynq7/tile_type_BRKH_BRAM.json`](./zynq7/tile_type_BRKH_BRAM.json) - * [`1adbede824487b01b77eed4443ff5434c9473a067dae3c620df3ccca800951ac ./zynq7/tile_type_BRKH_CLB.json`](./zynq7/tile_type_BRKH_CLB.json) - * [`d036cb35cb1bb3237b76f2e755fd3e5902e4588b03e565e4c01ecaa6429457fa ./zynq7/tile_type_BRKH_CLK.json`](./zynq7/tile_type_BRKH_CLK.json) - * [`ec60392fdf039d697e2de0b6c856d118a52ac7fb5bc50da206802f98a8967ea6 ./zynq7/tile_type_BRKH_CMT.json`](./zynq7/tile_type_BRKH_CMT.json) - * [`721f0a9fab25908b7ae0da9b94903a8ca1cb63d42dc5119d7b143309d27156fd ./zynq7/tile_type_BRKH_DSP_L.json`](./zynq7/tile_type_BRKH_DSP_L.json) - * [`db175274054c15c1cf7093a5117628fb30f27ddd50a29eabcc894e39236f95d8 ./zynq7/tile_type_BRKH_DSP_R.json`](./zynq7/tile_type_BRKH_DSP_R.json) - * [`68c36646e682266cb3aecade1627160b22112d72b5859f4aae3cd32df488422a ./zynq7/tile_type_BRKH_INT.json`](./zynq7/tile_type_BRKH_INT.json) - * [`b3700d8432a5ea4375fab4419bba143bc79dfd137a7110117ea085d79a2dd766 ./zynq7/tile_type_B_TERM_INT.json`](./zynq7/tile_type_B_TERM_INT.json) - * [`db3f1d44e0db5cf61bc97ee1c2002584e4588c473d412ca6739132fedabfa08b ./zynq7/tile_type_B_TERM_INT_PSS.json`](./zynq7/tile_type_B_TERM_INT_PSS.json) - * [`89e6d861ce30aaeb1df937f32aac00d4121de3089ea2bfa74945f93f1c4303b4 ./zynq7/tile_type_B_TERM_VBRK.json`](./zynq7/tile_type_B_TERM_VBRK.json) - * [`606581f9ab6d5c8ded71371ea6806e741b0739e5e32e69c503e4ebddc9544ec9 ./zynq7/tile_type_CFG_CENTER_BOT.json`](./zynq7/tile_type_CFG_CENTER_BOT.json) - * [`820a133d2cdab23ca7c64570daa391e3329826759fa82b2d12914878676274ce ./zynq7/tile_type_CFG_CENTER_MID.json`](./zynq7/tile_type_CFG_CENTER_MID.json) - * [`cc6b420c4804236a1b2928e5c86cfa6f6143b93843e40081d14c2bfd5d5e76a8 ./zynq7/tile_type_CFG_CENTER_TOP.json`](./zynq7/tile_type_CFG_CENTER_TOP.json) - * [`9fc927b122dbb55a74c48f846abf42ffc92537365d5524866b47d2217f70067f ./zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json) - * [`8eaac15316c7feb9da13a331e52d3c5f140fd92b4bcde5ceb5495fc35bef2c4d ./zynq7/tile_type_CFG_SECURITY_MID_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_MID_PELE1.json) - * [`9f229626a932dd9ea0db5f82d923089f8d14f7495e2db348a9bcd4413528591b ./zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json) - * [`0cf36c0ab629c583c01ae9efa04093e0644da71b7b0dfbc175dfcf9ed56650d5 ./zynq7/tile_type_CLBLL_L.json`](./zynq7/tile_type_CLBLL_L.json) - * [`3607f851807c3b420d21b4fe0c0b26b91db19d1384ba39d45f4c771f7251544e ./zynq7/tile_type_CLBLL_R.json`](./zynq7/tile_type_CLBLL_R.json) - * [`8f91f81d6f549d0f728dbab89baca64bae44491b1b0df30ae6ca4193b6eed951 ./zynq7/tile_type_CLBLM_L.json`](./zynq7/tile_type_CLBLM_L.json) - * [`50812dbe755a110f8e33285728a9b565d46d1e71e76e63085fc6d1dea4f4dee7 ./zynq7/tile_type_CLBLM_R.json`](./zynq7/tile_type_CLBLM_R.json) - * [`3ab28fa68486317ac22e260c8d0ac81bcccc0b214cff21b66cda2cf0974d62bb ./zynq7/tile_type_CLK_BUFG_BOT_R.json`](./zynq7/tile_type_CLK_BUFG_BOT_R.json) - * [`7e7b949435c6724c886ab674148e7a241d7761b63d8b700fbeb2b3f4105329bb ./zynq7/tile_type_CLK_BUFG_REBUF.json`](./zynq7/tile_type_CLK_BUFG_REBUF.json) - * [`b1fdae383da0691975b3836a0a66fa566165de094e4bd416d664dc32f2d010c8 ./zynq7/tile_type_CLK_BUFG_TOP_R.json`](./zynq7/tile_type_CLK_BUFG_TOP_R.json) - * [`9900c1d7c03b75bb765c57b00b20fbefd09efeccb325afba72901b941d5db0de ./zynq7/tile_type_CLK_FEED.json`](./zynq7/tile_type_CLK_FEED.json) - * [`fa0923a2169819ecc93697c7255aef24e9dbee2a3c5d8c1df3f86956e0bc8b08 ./zynq7/tile_type_CLK_HROW_BOT_R.json`](./zynq7/tile_type_CLK_HROW_BOT_R.json) - * [`71f60f081cb9718ca95f3c004034dde427a1323ae4f71f94c68f3ecb961f1d2f ./zynq7/tile_type_CLK_HROW_TOP_R.json`](./zynq7/tile_type_CLK_HROW_TOP_R.json) - * [`3d200f97f5d0608d4577dcaf9ae59c34be18f4d1406aa71815d56327fc2a3564 ./zynq7/tile_type_CLK_MTBF2.json`](./zynq7/tile_type_CLK_MTBF2.json) - * [`0163ab8305f14d439e303fc072bf980549efd65c42494e468bc2b2e0bd3ff0a6 ./zynq7/tile_type_CLK_PMV.json`](./zynq7/tile_type_CLK_PMV.json) - * [`1e08a2d1f2c7e0ec12b0eec202c3759fbfc82fab01b9d0b5d1658299d8ac5506 ./zynq7/tile_type_CLK_PMV2.json`](./zynq7/tile_type_CLK_PMV2.json) - * [`bf52b93861ca5856dab593dde196a21ab8a9522b4eb58f13fe206beaba8c78f2 ./zynq7/tile_type_CLK_PMV2_SVT.json`](./zynq7/tile_type_CLK_PMV2_SVT.json) - * [`e7123b7dbeba2ebbf4a6ae04fb87bd114548befc9bb812d7bf4bee3401aa44fa ./zynq7/tile_type_CLK_PMVIOB.json`](./zynq7/tile_type_CLK_PMVIOB.json) - * [`42236b4ea5a40883822299aef2c5eb6ef2adb30c715145a9c36c5dd9e84e102e ./zynq7/tile_type_CLK_TERM.json`](./zynq7/tile_type_CLK_TERM.json) - * [`f985c5c1c1186eb314e1bd727b4195b88f69739fcb991efbafee963310b880f9 ./zynq7/tile_type_CMT_FIFO_L.json`](./zynq7/tile_type_CMT_FIFO_L.json) - * [`9207ebd19f94b6a3a9d8ea08f1fe78dcf592d3b5b5f541694a23d5dc1a9163e3 ./zynq7/tile_type_CMT_PMV_L.json`](./zynq7/tile_type_CMT_PMV_L.json) - * [`63d8187207a325d174e8d509014200531f3e11236e5064c2675871ca42fbbffa ./zynq7/tile_type_CMT_TOP_L_LOWER_B.json`](./zynq7/tile_type_CMT_TOP_L_LOWER_B.json) - * [`129c5c28dee6d7cc79263d280a391c07b5db326124ad1e973582643d9eadff3a ./zynq7/tile_type_CMT_TOP_L_LOWER_T.json`](./zynq7/tile_type_CMT_TOP_L_LOWER_T.json) - * [`3c645c7e32529af66b278c8c06734bb052d1be00ff801772d28147b1e62da2ff ./zynq7/tile_type_CMT_TOP_L_UPPER_B.json`](./zynq7/tile_type_CMT_TOP_L_UPPER_B.json) - * [`e008d249e1f1dafa57e4ac276826c60e24b7fd29ec4e5acafd078c0604631afc ./zynq7/tile_type_CMT_TOP_L_UPPER_T.json`](./zynq7/tile_type_CMT_TOP_L_UPPER_T.json) - * [`4ddd2c3e96995a4acf4320877f3ab6ade22d9b475eb8b2e46cb64c325b92e386 ./zynq7/tile_type_DSP_L.json`](./zynq7/tile_type_DSP_L.json) - * [`b7f2ec5fcaf13becd7a73baa9271370dd80ccc24a1dc52bbe4ec2a450aabd7ad ./zynq7/tile_type_DSP_R.json`](./zynq7/tile_type_DSP_R.json) - * [`05eb17dc54b29fac95e4b2ac067139b528c1bc7f5cb78b672e6941a2966ec7bb ./zynq7/tile_type_HCLK_BRAM.json`](./zynq7/tile_type_HCLK_BRAM.json) - * [`307db3c561c03036e0460d24af8d435631bbacef7f81c0385f6179673d818d50 ./zynq7/tile_type_HCLK_CLB.json`](./zynq7/tile_type_HCLK_CLB.json) - * [`4af6db5c406dd683670c77fe2dbfcfd64b0d079e59e3082cfc4e578789cddf45 ./zynq7/tile_type_HCLK_CMT_L.json`](./zynq7/tile_type_HCLK_CMT_L.json) - * [`cbcd13d3b6a78888a73e22e1e33e56c80b5fcb23c4d1baf938b4b6daa02173f7 ./zynq7/tile_type_HCLK_DSP_L.json`](./zynq7/tile_type_HCLK_DSP_L.json) - * [`dacc707f9e2db1d6752f833cf0559536423baf915a848b3ff641373f4762793f ./zynq7/tile_type_HCLK_DSP_R.json`](./zynq7/tile_type_HCLK_DSP_R.json) - * [`c1d33fee3af7b2ba311bad50d6f8b771303ebd8241e617ec638b1fcb8d2c4ee0 ./zynq7/tile_type_HCLK_FEEDTHRU_1.json`](./zynq7/tile_type_HCLK_FEEDTHRU_1.json) - * [`2c887222cc585d9f90588029f5076f4a6dc8b7449928f5ba1d919845076c0b9d ./zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json`](./zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json) - * [`0e991e5fc85e54835a7de8da8456ee1300d97d798fb12d16c521a9163500a20c ./zynq7/tile_type_HCLK_FEEDTHRU_2.json`](./zynq7/tile_type_HCLK_FEEDTHRU_2.json) - * [`1631fbdf6e3158d6e372508b55e32e3e638b270e0ca606359b4ad060f6337cea ./zynq7/tile_type_HCLK_FIFO_L.json`](./zynq7/tile_type_HCLK_FIFO_L.json) - * [`6a66fa18fdad81ae738e61f650066415a2adc7d15b15ab87b5080faff3edb9e1 ./zynq7/tile_type_HCLK_INT_INTERFACE.json`](./zynq7/tile_type_HCLK_INT_INTERFACE.json) - * [`51fbaa9613664a08814f372c5791189ceb855720997334f55e52872cc6d4c46f ./zynq7/tile_type_HCLK_IOB.json`](./zynq7/tile_type_HCLK_IOB.json) - * [`5e15b63a15fd7864d838d448599718e5f82e8caafa8fd316eb19374e20c0d89c ./zynq7/tile_type_HCLK_IOI3.json`](./zynq7/tile_type_HCLK_IOI3.json) - * [`2c39172c06f58c30f92d140c6c7c060777b1b3f397a23b9cf82a41a656da82ef ./zynq7/tile_type_HCLK_L.json`](./zynq7/tile_type_HCLK_L.json) - * [`782d62d7a78ca8282570a945739057b1801795271764120ff4f20696a36e9354 ./zynq7/tile_type_HCLK_R.json`](./zynq7/tile_type_HCLK_R.json) - * [`5b459ee856bd5417b0c61831120d27cebb7f5c6ae4952470bdc6dc6bad6c5b49 ./zynq7/tile_type_HCLK_TERM.json`](./zynq7/tile_type_HCLK_TERM.json) - * [`e706c7cf142b8e806283d3cf030f89e30149bad7b2f156e739e2f41247922792 ./zynq7/tile_type_HCLK_VBRK.json`](./zynq7/tile_type_HCLK_VBRK.json) - * [`acabe2c19ef9286451b67f889608af10b57c4149be795c7b9e96c700e673741a ./zynq7/tile_type_HCLK_VFRAME.json`](./zynq7/tile_type_HCLK_VFRAME.json) - * [`fe9a6b9109c94abc0860142566f1d6c292b5313f2ebe641dbd3f4d41671d05a2 ./zynq7/tile_type_INT_FEEDTHRU_1.json`](./zynq7/tile_type_INT_FEEDTHRU_1.json) - * [`1ff618718c404f469eed1fc7499db1a7bcfa90bf152b317b07511d1e070d7622 ./zynq7/tile_type_INT_FEEDTHRU_2.json`](./zynq7/tile_type_INT_FEEDTHRU_2.json) - * [`08db2bc2bc634b16af1988b445a896ffdbe75e2275647657dd44dbc9e436ec9f ./zynq7/tile_type_INT_INTERFACE_L.json`](./zynq7/tile_type_INT_INTERFACE_L.json) - * [`39d9152faf8afe07a8605aaf0e775b2668dca2eed3a46e4c1b6d444f594308db ./zynq7/tile_type_INT_INTERFACE_PSS_L.json`](./zynq7/tile_type_INT_INTERFACE_PSS_L.json) - * [`3f04e660e8a477ae99b5349c70d4bb420ed61c823ead17915a2900cc2210ad46 ./zynq7/tile_type_INT_INTERFACE_R.json`](./zynq7/tile_type_INT_INTERFACE_R.json) - * [`cc47a410209b8beb6140d0216de2b298547116a90f4cd7cf9674785e838f4c36 ./zynq7/tile_type_INT_L.json`](./zynq7/tile_type_INT_L.json) - * [`784502f54f667eb147924b061bc62829588d0e43673f32fd9d45113b6f740457 ./zynq7/tile_type_INT_R.json`](./zynq7/tile_type_INT_R.json) - * [`cf049a6c528634761c6067610f50110102caadc782a33b855f4059df8ed064d9 ./zynq7/tile_type_IO_INT_INTERFACE_R.json`](./zynq7/tile_type_IO_INT_INTERFACE_R.json) - * [`ec029a5a1ca3912c5582864edab9b46e0e955e901a8f08264bf9ec3fba0aca0d ./zynq7/tile_type_MONITOR_BOT_PELE1.json`](./zynq7/tile_type_MONITOR_BOT_PELE1.json) - * [`6ead1217a6413d2ce272c1447b230031b508d1cc897ec80260d4afb03f66dcdf ./zynq7/tile_type_MONITOR_MID_PELE1.json`](./zynq7/tile_type_MONITOR_MID_PELE1.json) - * [`1c88d8e7f113af2e568b2ddaa0f0a7da71bd5fcb97a19aca2caef1d963e60e3a ./zynq7/tile_type_MONITOR_TOP_PELE1.json`](./zynq7/tile_type_MONITOR_TOP_PELE1.json) - * [`880cdcd99af7ea01e4ee142860e0900c6c3503da3b3582837fedba1a2cafa852 ./zynq7/tile_type_NULL.json`](./zynq7/tile_type_NULL.json) - * [`944d9c69913b23cac150f0c80c14284d57fab43f69202a6cc63afaddce23221b ./zynq7/tile_type_PCIE_NULL.json`](./zynq7/tile_type_PCIE_NULL.json) - * [`a122f8026a2a5edab39eabc9117a63bc29fb1d2aeaf7b1afd2b40d1b493afa4d ./zynq7/tile_type_PSS0.json`](./zynq7/tile_type_PSS0.json) - * [`178db0b66318b31f8852f82297ab39d02287feca33c4fd8284f1c0e19791082a ./zynq7/tile_type_PSS1.json`](./zynq7/tile_type_PSS1.json) - * [`930dab9d5b0aab1594cb0ef933495683925bde169d9c1128304d5a0062a7906d ./zynq7/tile_type_PSS2.json`](./zynq7/tile_type_PSS2.json) - * [`a40337531311fa9e1bc0371b0deee86008a7cba18f3924a62b0e684f9f1b4537 ./zynq7/tile_type_PSS3.json`](./zynq7/tile_type_PSS3.json) - * [`bda246d0e8ea8ca946ba6877502428ed0fd52240fb6fc5339d9b263653c0cf93 ./zynq7/tile_type_PSS4.json`](./zynq7/tile_type_PSS4.json) - * [`a01a9bfa1d6ac7762d56b57487ab1f4efa8f53e77c6fa452adfa3aff120811fb ./zynq7/tile_type_RIOB33.json`](./zynq7/tile_type_RIOB33.json) - * [`66ea3a8940b40915699e7e2fa37b3d65403e7f5d51afe0daf14537e662da9385 ./zynq7/tile_type_RIOB33_SING.json`](./zynq7/tile_type_RIOB33_SING.json) - * [`96029c4d8a29149b3aa063bbcd3a64bbbf28f987e8e491d2630f7e78d47354b2 ./zynq7/tile_type_RIOI3.json`](./zynq7/tile_type_RIOI3.json) - * [`6c8c8745a8bcd8ebcf6396dfda55fd7b958b2de19ac1a926e412716b7d8dd2b2 ./zynq7/tile_type_RIOI3_SING.json`](./zynq7/tile_type_RIOI3_SING.json) - * [`89b4d83a435609119ca878a4cdbfc3fc31c8c30d66459bf3d84b4c8c012c1139 ./zynq7/tile_type_RIOI3_TBYTESRC.json`](./zynq7/tile_type_RIOI3_TBYTESRC.json) - * [`e188cfd52a8cd3edb869bd29a02e95e8cfc06688727982f9c364c54b5d20c409 ./zynq7/tile_type_RIOI3_TBYTETERM.json`](./zynq7/tile_type_RIOI3_TBYTETERM.json) - * [`16627ffc9c74acf89474ad03993367d2210f40d4ab07a8c71c98d9ad652f2ca8 ./zynq7/tile_type_R_TERM_INT.json`](./zynq7/tile_type_R_TERM_INT.json) - * [`19503481fb531f7ddc5f92fdc7c97a817ce1cf550e128604041c771f2234b7fa ./zynq7/tile_type_TERM_CMT.json`](./zynq7/tile_type_TERM_CMT.json) - * [`f5ebbeee5575e5fbc1fb5d532f021e4ee8647de21b3874caac655d8c849a9ff3 ./zynq7/tile_type_T_TERM_INT.json`](./zynq7/tile_type_T_TERM_INT.json) - * [`dee783006fa5b5964d20457323cad59171a60397d730e9fe0840389587695727 ./zynq7/tile_type_VBRK.json`](./zynq7/tile_type_VBRK.json) - * [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./zynq7/tile_type_VFRAME.json`](./zynq7/tile_type_VFRAME.json) + * [`f24ee0973df88b1dd73e1937a350b09e1dac35d72e57f3f246c267d2426d63b6 ./zynq7/tile_type_BRAM_INT_INTERFACE_L.json`](./zynq7/tile_type_BRAM_INT_INTERFACE_L.json) + * [`c95ac9e2d604c8cc8783732fd378f5aee563db5161265ee56ba2ae8410e9bdbb ./zynq7/tile_type_BRAM_INT_INTERFACE_R.json`](./zynq7/tile_type_BRAM_INT_INTERFACE_R.json) + * [`73ea54de75eaff030c2ee02aa6791bba283c0a91bf6c37fbdd878fdf3b76f88b ./zynq7/tile_type_BRAM_L.json`](./zynq7/tile_type_BRAM_L.json) + * [`85c92e649e0bb187a1fda5861f5b596a5023db1743824b19f7a2f6d326ba8b06 ./zynq7/tile_type_BRAM_R.json`](./zynq7/tile_type_BRAM_R.json) + * [`5fed21fa51d7da12161c39f1f348bdf80b08df28c01d106959e9125c2bbc2ea6 ./zynq7/tile_type_BRKH_BRAM.json`](./zynq7/tile_type_BRKH_BRAM.json) + * [`f3c6f6f895b114fce5aa917dad371892926a80f34cac8e7a084561ad2fe22579 ./zynq7/tile_type_BRKH_CLB.json`](./zynq7/tile_type_BRKH_CLB.json) + * [`f4a1d3eac4ed9046f4b4df9d925b62080d70ac295cd492c008bdd543b5714a7f ./zynq7/tile_type_BRKH_CLK.json`](./zynq7/tile_type_BRKH_CLK.json) + * [`1a81bf9fbc72eb95ba686a6f0ebdcf5afd305ebc4c45a22d38857e83933ce3c1 ./zynq7/tile_type_BRKH_CMT.json`](./zynq7/tile_type_BRKH_CMT.json) + * [`7865b3f082f74329f8d795eda8497ab16f35436dec393ec60fb827127e6858e7 ./zynq7/tile_type_BRKH_DSP_L.json`](./zynq7/tile_type_BRKH_DSP_L.json) + * [`7b3184855f2fcaf13bc7a835b14fd35bc11c72841f2240e51703434ead3e2da3 ./zynq7/tile_type_BRKH_DSP_R.json`](./zynq7/tile_type_BRKH_DSP_R.json) + * [`6ca4696204303eb6a546a453513c87241480b9a273e99cf2c5512dd7abcca82c ./zynq7/tile_type_BRKH_INT.json`](./zynq7/tile_type_BRKH_INT.json) + * [`569bab17633b363bedb66f1e55da4e36edac937a6653933863ee0a95832c4ccf ./zynq7/tile_type_B_TERM_INT.json`](./zynq7/tile_type_B_TERM_INT.json) + * [`9b10dc51a32b2113193337807fa4bb0ff9e51ffb10e24f96a4e3070fc0a90c6e ./zynq7/tile_type_B_TERM_INT_PSS.json`](./zynq7/tile_type_B_TERM_INT_PSS.json) + * [`8a63872373a1adf0b60871588272f24b946f9b3dfeee7d951159e50f4758b003 ./zynq7/tile_type_B_TERM_VBRK.json`](./zynq7/tile_type_B_TERM_VBRK.json) + * [`ef7ff05b9b709a8d4cd368e264e796b1fcdd774065e247e584f42a746eb48576 ./zynq7/tile_type_CFG_CENTER_BOT.json`](./zynq7/tile_type_CFG_CENTER_BOT.json) + * [`375a0d6b8c33de1436c8efaa580c611874c10ab6b1dc575bad879d3a9bd3700e ./zynq7/tile_type_CFG_CENTER_MID.json`](./zynq7/tile_type_CFG_CENTER_MID.json) + * [`e4aafa355a8534302dd7ba06fd8ece448b09b7c85b148c6374ee555c8174550c ./zynq7/tile_type_CFG_CENTER_TOP.json`](./zynq7/tile_type_CFG_CENTER_TOP.json) + * [`af89c0ce6f4d15929ece7fb2bd3775a1040550a07b4a64b876d4b05e9fb689f9 ./zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json) + * [`88822baff15e6d783118322eddf5a01179e1e1e94dd8a16c0e1c5059d5977ac7 ./zynq7/tile_type_CFG_SECURITY_MID_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_MID_PELE1.json) + * [`a6707c7d0a9e9bb98fe398f6dd70d8327ed9b9c647c3fb6ce7b7959730c1b646 ./zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json`](./zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json) + * [`4abb229d18ed0c58cefd8d2d8955f083e047f92e6367829c0b394ade6ce01f1a ./zynq7/tile_type_CLBLL_L.json`](./zynq7/tile_type_CLBLL_L.json) + * [`88f100fbac0edb7bcbbdbef5daddcc6c4e217826311b395c6d386ff42054f7c4 ./zynq7/tile_type_CLBLL_R.json`](./zynq7/tile_type_CLBLL_R.json) + * [`98ec1f4221138e2d443de313e460541c69dc1ff3708dbaa60b5afcb4b113d94a ./zynq7/tile_type_CLBLM_L.json`](./zynq7/tile_type_CLBLM_L.json) + * [`b0d76a7bd251d5053988f836dc9a3d0bf6aa6b0b88a5ac5da7978884f8568323 ./zynq7/tile_type_CLBLM_R.json`](./zynq7/tile_type_CLBLM_R.json) + * [`f3bd053eac4e788954750834c04cc59fb6b993770b00317b6b00cc1cbed16b44 ./zynq7/tile_type_CLK_BUFG_BOT_R.json`](./zynq7/tile_type_CLK_BUFG_BOT_R.json) + * [`a2670c56315bfa6d2c7b264a00bd9f94fc57707070fafa016723052c2ea6c7c7 ./zynq7/tile_type_CLK_BUFG_REBUF.json`](./zynq7/tile_type_CLK_BUFG_REBUF.json) + * [`92682bfae56bc36eff0dd8e507b4fbf49945f1f612b2951a8a09006f1b947635 ./zynq7/tile_type_CLK_BUFG_TOP_R.json`](./zynq7/tile_type_CLK_BUFG_TOP_R.json) + * [`4511dcbf42306a70f8413845560367a11c4ebef76732738cfe339cc7cbf7a332 ./zynq7/tile_type_CLK_FEED.json`](./zynq7/tile_type_CLK_FEED.json) + * [`9532d9fbc982b2b37d91b08e4cf675ab3c363ab62d0656d341e3a507d51b1d37 ./zynq7/tile_type_CLK_HROW_BOT_R.json`](./zynq7/tile_type_CLK_HROW_BOT_R.json) + * [`34bb254ff5e7d4564d592dfddc57caeb55e26dfd1add81ae47732c1c49324f2b ./zynq7/tile_type_CLK_HROW_TOP_R.json`](./zynq7/tile_type_CLK_HROW_TOP_R.json) + * [`0ab174146714c57d124b00d710e4b61451fd7616330659df7854542a9266cd3f ./zynq7/tile_type_CLK_MTBF2.json`](./zynq7/tile_type_CLK_MTBF2.json) + * [`7465e9e40a7564598e859620faf75bc9c230b5d41a6141c0fc58f1ea7fce7bf2 ./zynq7/tile_type_CLK_PMV.json`](./zynq7/tile_type_CLK_PMV.json) + * [`c7fa3a115807b7a7e26648bfd754df16098aeb40d835cf03355d8ff361f25872 ./zynq7/tile_type_CLK_PMV2.json`](./zynq7/tile_type_CLK_PMV2.json) + * [`b41f19caae976764c738da165f14ee36df6d6c99296fcb829e359b4dce884367 ./zynq7/tile_type_CLK_PMV2_SVT.json`](./zynq7/tile_type_CLK_PMV2_SVT.json) + * [`fbe2edf0894ee5fe23f5aec0e34dce567a2cdaa22805ac6ac1f834b52259522b ./zynq7/tile_type_CLK_PMVIOB.json`](./zynq7/tile_type_CLK_PMVIOB.json) + * [`1dfd3414cd2cd1225ae057f91a904dbac0d868e8a674066e1a0c180743524b9c ./zynq7/tile_type_CLK_TERM.json`](./zynq7/tile_type_CLK_TERM.json) + * [`61eb6b1524330329616ab023459f9e006da8da1d25b64cbbfd48b0b78f6ba4e0 ./zynq7/tile_type_CMT_FIFO_L.json`](./zynq7/tile_type_CMT_FIFO_L.json) + * [`1591ab4ac65220fbd23662787457ece5aa0705bc829a6bdf61b44884809ba811 ./zynq7/tile_type_CMT_PMV_L.json`](./zynq7/tile_type_CMT_PMV_L.json) + * [`e26ded0ddb634d45048c646d1e701c50168c3ec9d675fca06b696290e0e7ac98 ./zynq7/tile_type_CMT_TOP_L_LOWER_B.json`](./zynq7/tile_type_CMT_TOP_L_LOWER_B.json) + * [`f5cf9ae4fdaa79041c8c65dba614a38bae621a8549a095b5c6ee99da05c3a912 ./zynq7/tile_type_CMT_TOP_L_LOWER_T.json`](./zynq7/tile_type_CMT_TOP_L_LOWER_T.json) + * [`bc7de806ba96818d8e1a1a3937467deee3e1377e45afafdeb37bd83a1779da2f ./zynq7/tile_type_CMT_TOP_L_UPPER_B.json`](./zynq7/tile_type_CMT_TOP_L_UPPER_B.json) + * [`2c7422216c30cb832ef5bb6cca33a4a9c2e9825c941b39e576a0d978831c59ea ./zynq7/tile_type_CMT_TOP_L_UPPER_T.json`](./zynq7/tile_type_CMT_TOP_L_UPPER_T.json) + * [`059ef3a432f033abc56178ce73ffbf2c03e6ca623a3db200674f84a11bd9b5e4 ./zynq7/tile_type_DSP_L.json`](./zynq7/tile_type_DSP_L.json) + * [`2aa2188d24628bde1cb14094a0ad8d7bde2c8f09194dccdaa798b83854faac69 ./zynq7/tile_type_DSP_R.json`](./zynq7/tile_type_DSP_R.json) + * [`fe27db14b76b461aa9b21f596df89860456b63da3d040bc1491cc5ebcd9e21c6 ./zynq7/tile_type_HCLK_BRAM.json`](./zynq7/tile_type_HCLK_BRAM.json) + * [`6a207032a32081ca4119b306e1144b4e0e9bfc890413aac65c558ba14c3fb5ca ./zynq7/tile_type_HCLK_CLB.json`](./zynq7/tile_type_HCLK_CLB.json) + * [`c76a6ac4dd79b5f45c574bd050cb4043ba6c03f147c31b7618b3e67f1b519ac6 ./zynq7/tile_type_HCLK_CMT_L.json`](./zynq7/tile_type_HCLK_CMT_L.json) + * [`1ee8f9b2ca6f84824725705c135db8e8f21ee0a0c66c034123c2dae5c7b392ba ./zynq7/tile_type_HCLK_DSP_L.json`](./zynq7/tile_type_HCLK_DSP_L.json) + * [`2a121fb98cb89927421fd60fde2d893ff22d32003b6f79279724fa1230459185 ./zynq7/tile_type_HCLK_DSP_R.json`](./zynq7/tile_type_HCLK_DSP_R.json) + * [`7756e9585aa1e0eb50790b1efa4984474fe16fe01d2a2d243f42d7f36123c0ac ./zynq7/tile_type_HCLK_FEEDTHRU_1.json`](./zynq7/tile_type_HCLK_FEEDTHRU_1.json) + * [`82747ca0ce2ce448e81c2402edbc144fd466ca0e22e566d6a864e45a699cf1c2 ./zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json`](./zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json) + * [`bce1ef5bdc632645054a57fa0bc022a3f3c85717a80c1daba3eb9f777836333d ./zynq7/tile_type_HCLK_FEEDTHRU_2.json`](./zynq7/tile_type_HCLK_FEEDTHRU_2.json) + * [`20ffd03177494bd2a2c4565268c345b76802bfbdf711cf863626c104778991ba ./zynq7/tile_type_HCLK_FIFO_L.json`](./zynq7/tile_type_HCLK_FIFO_L.json) + * [`979fb1ba45151227f96a4b15cc647fcfe3384e36a334cfadb0c60773b09eca78 ./zynq7/tile_type_HCLK_INT_INTERFACE.json`](./zynq7/tile_type_HCLK_INT_INTERFACE.json) + * [`b168549e91632121e51d99b9e681d975bf1aecf04b38600ee834ad318053e3a6 ./zynq7/tile_type_HCLK_IOB.json`](./zynq7/tile_type_HCLK_IOB.json) + * [`9548b7c8b0659ec49597d5502bad6b4040fe8e9e4cb2b560e514cd00ab61f286 ./zynq7/tile_type_HCLK_IOI3.json`](./zynq7/tile_type_HCLK_IOI3.json) + * [`6025a2c09f21c52b05c9c7e73af7b86e742dd7ca542834fc7d242e7a17fb8ac8 ./zynq7/tile_type_HCLK_L.json`](./zynq7/tile_type_HCLK_L.json) + * [`1af49f83d7b2e46a77a0b7f5c2601a68584d85810524c395a35b1eb83b234184 ./zynq7/tile_type_HCLK_R.json`](./zynq7/tile_type_HCLK_R.json) + * [`2df032665e26af5c97a814575440731c0d7b2bac733e1b0dcfe42d3870d9d1d7 ./zynq7/tile_type_HCLK_TERM.json`](./zynq7/tile_type_HCLK_TERM.json) + * [`4b43030e650607a9c5473a03827fdfbf990d241aa48f4093c71572ff86bf0183 ./zynq7/tile_type_HCLK_VBRK.json`](./zynq7/tile_type_HCLK_VBRK.json) + * [`8f70b2cefb458f2d3ff09123e58a891bd7ece80ae7cab637d738659799709318 ./zynq7/tile_type_HCLK_VFRAME.json`](./zynq7/tile_type_HCLK_VFRAME.json) + * [`432c6ad451ebf276da839671059c761584a6092cac75a4e14ff8f8de71bc923c ./zynq7/tile_type_INT_FEEDTHRU_1.json`](./zynq7/tile_type_INT_FEEDTHRU_1.json) + * [`938be9bbb0126fef543f27913c463e26edd5a8031067ff1a0e961e06823ae7f5 ./zynq7/tile_type_INT_FEEDTHRU_2.json`](./zynq7/tile_type_INT_FEEDTHRU_2.json) + * [`312ea0c10c73169aedd6e53a9465c2a597e922067d0c32a7c0f06a341f044f45 ./zynq7/tile_type_INT_INTERFACE_L.json`](./zynq7/tile_type_INT_INTERFACE_L.json) + * [`cbe641b878935eca85afb55a4c3aa3f31d423898bbf3e1826d90ba2472ee6be8 ./zynq7/tile_type_INT_INTERFACE_PSS_L.json`](./zynq7/tile_type_INT_INTERFACE_PSS_L.json) + * [`20258948fa358760722361c879658b898a6739c2ba9c9bd83bf7eb776a15792c ./zynq7/tile_type_INT_INTERFACE_R.json`](./zynq7/tile_type_INT_INTERFACE_R.json) + * [`bd1bd64243d040c0414b7f17007dcde384dfedfd59fa60b795bc8971d04f881c ./zynq7/tile_type_INT_L.json`](./zynq7/tile_type_INT_L.json) + * [`dc8af3f4e2e58cf2f43e234e599c8efaf7a89a7814d2421e60c416ad74bb7e43 ./zynq7/tile_type_INT_R.json`](./zynq7/tile_type_INT_R.json) + * [`eee676d3887fb0d19ba1054ed73fe691745d524b3852053d0a5544f907e240c8 ./zynq7/tile_type_IO_INT_INTERFACE_R.json`](./zynq7/tile_type_IO_INT_INTERFACE_R.json) + * [`8e492b13c6437353e40f655351183be17b9c44f0e1030a3af0c1882ccecd1eab ./zynq7/tile_type_MONITOR_BOT_PELE1.json`](./zynq7/tile_type_MONITOR_BOT_PELE1.json) + * [`016410ef9c50838aa42030a63770c706c7d8e40a29838da88e3f465710461266 ./zynq7/tile_type_MONITOR_MID_PELE1.json`](./zynq7/tile_type_MONITOR_MID_PELE1.json) + * [`26ceeec9bd470c21d8fa3c07beb22cef67c5b373085d2425ec6bf3eacc765a31 ./zynq7/tile_type_MONITOR_TOP_PELE1.json`](./zynq7/tile_type_MONITOR_TOP_PELE1.json) + * [`d430688c70e289f09318774410f2f55e53639c3544fca8a3c98d420f714b0c2f ./zynq7/tile_type_NULL.json`](./zynq7/tile_type_NULL.json) + * [`a246242840607ca7b8e3b45d44d7cf7fcc145fad4c973536575742c8b9bc9a42 ./zynq7/tile_type_PCIE_NULL.json`](./zynq7/tile_type_PCIE_NULL.json) + * [`69f71a0851833685555bbbd829f42f13b9f699f1909591e1fff1a920e86b27d6 ./zynq7/tile_type_PSS0.json`](./zynq7/tile_type_PSS0.json) + * [`7a17b0d5ac0fe2753441a4cd3e3479b7cba2dace3e11b2ac3bc1615cefe6cce0 ./zynq7/tile_type_PSS1.json`](./zynq7/tile_type_PSS1.json) + * [`daec77be7e5c046d4de49cf4c94a804a3c90745ce71f20714bfe764733d21f85 ./zynq7/tile_type_PSS2.json`](./zynq7/tile_type_PSS2.json) + * [`e7dd99a5210eb44a7e2c537447f5feff9c68de8385e1bdde4ef65b20af9deb59 ./zynq7/tile_type_PSS3.json`](./zynq7/tile_type_PSS3.json) + * [`04febdb8b183f1b976da61333fd10c39479390f3d4c7671ae727438f0c517f64 ./zynq7/tile_type_PSS4.json`](./zynq7/tile_type_PSS4.json) + * [`7469d05ba321c92ed72125d2894f717b5741ce7444a8265ae51cc6a2c547a491 ./zynq7/tile_type_RIOB33.json`](./zynq7/tile_type_RIOB33.json) + * [`73eb4020bd019345fcab4dec38d9a2347699435966caa4bd63cecf87a7b8a637 ./zynq7/tile_type_RIOB33_SING.json`](./zynq7/tile_type_RIOB33_SING.json) + * [`dd554abb6ca027deef90d6245a59d7bbc5e5701f3d0e304c434edf0f3f1015ea ./zynq7/tile_type_RIOI3.json`](./zynq7/tile_type_RIOI3.json) + * [`990370b5daec491bb4fb3549436d509ae7ffed104931775a60e4c9adf5000386 ./zynq7/tile_type_RIOI3_SING.json`](./zynq7/tile_type_RIOI3_SING.json) + * [`9d00ddd84a1656989bf77e826b07676f2d6195a521066fa2aac18a7afcdc831b ./zynq7/tile_type_RIOI3_TBYTESRC.json`](./zynq7/tile_type_RIOI3_TBYTESRC.json) + * [`00fc92093158507c654f566d2a18b5206e26e62f1527ef0c790e098c7602ee9e ./zynq7/tile_type_RIOI3_TBYTETERM.json`](./zynq7/tile_type_RIOI3_TBYTETERM.json) + * [`f8636b98f24c07c250ea284be61826439e4557a3d75c8571cc3c00bc47d61f8c ./zynq7/tile_type_R_TERM_INT.json`](./zynq7/tile_type_R_TERM_INT.json) + * [`fc909565278739a6beeb94d5bcb0780a6ec3dfa2d0f83389699974abc3d0427a ./zynq7/tile_type_TERM_CMT.json`](./zynq7/tile_type_TERM_CMT.json) + * [`372e4b47e58b79d8d6d587ee1459a576edbd7eebad7e8a49eba3e2c71cf3a536 ./zynq7/tile_type_T_TERM_INT.json`](./zynq7/tile_type_T_TERM_INT.json) + * [`9d6388021982de6d4a676c2c2fe6543029a2f44db45d290f4e827d35b91a2a6b ./zynq7/tile_type_VBRK.json`](./zynq7/tile_type_VBRK.json) + * [`63851d7ed48855486ee7e04a6332935799e8d2f3524ec6d627ea6e5d2e7cbfa4 ./zynq7/tile_type_VFRAME.json`](./zynq7/tile_type_VFRAME.json) * [`e6d0ebf9b27f60f4afdab85a357bff4d7cf2cd77c3a6c0f2d887022cda874066 ./zynq7/tileconn.json`](./zynq7/tileconn.json) - * [`93ae29cf7cd85ac8baf94a8e98cc7857d3cdd7ac0ad5720a42d6da1597b6d773 ./zynq7/tilegrid.json`](./zynq7/tilegrid.json) + * [`15e8ed87d38b9f9b84b52c768df922e5f5be4d860670a768e9230ad8cdca3787 ./zynq7/tilegrid.json`](./zynq7/tilegrid.json) * [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_INT_INTERFACE_L.sdf`](./zynq7/timings/BRAM_INT_INTERFACE_L.sdf) * [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_INT_INTERFACE_R.sdf`](./zynq7/timings/BRAM_INT_INTERFACE_R.sdf) * [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/BRAM_L.sdf`](./zynq7/timings/BRAM_L.sdf) @@ -1077,7 +1099,7 @@ Results have checksums; * [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CLK_TERM.sdf`](./zynq7/timings/CLK_TERM.sdf) * [`366802adb3810a1cecf1674f01fe1a97f1338a7455d7a6e4796aa004311b9c8a ./zynq7/timings/CMT_FIFO_L.sdf`](./zynq7/timings/CMT_FIFO_L.sdf) * [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/CMT_PMV_L.sdf`](./zynq7/timings/CMT_PMV_L.sdf) - * [`c2e66425da5018d6e7aa2b0aec721bcecfdba26bfa26016598cd28e3112fffc4 ./zynq7/timings/CMT_TOP_L_LOWER_B.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_B.sdf) + * [`8c641a845fdd56842eec7c5fe72ddbd26654593313516137b88dcb5ea83a1920 ./zynq7/timings/CMT_TOP_L_LOWER_B.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_B.sdf) * [`35863307207f2f40fdbf61f5a5065b0112305594d5375a758491ee52e2a848a8 ./zynq7/timings/CMT_TOP_L_LOWER_T.sdf`](./zynq7/timings/CMT_TOP_L_LOWER_T.sdf) * [`e8fdd4747aa8be4e39fe2ae27f51c8442c754485c8506fc5b021150f08289e95 ./zynq7/timings/CMT_TOP_L_UPPER_B.sdf`](./zynq7/timings/CMT_TOP_L_UPPER_B.sdf) * [`5a70eb78c2a91cef8d2322645ac12acef53241d264ce548017620963e396a8a9 ./zynq7/timings/CMT_TOP_L_UPPER_T.sdf`](./zynq7/timings/CMT_TOP_L_UPPER_T.sdf) @@ -1117,17 +1139,17 @@ Results have checksums; * [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/PSS4.sdf`](./zynq7/timings/PSS4.sdf) * [`9313a012de7cbb7120baf15fe30bf8d44b238cad6226ece1a9776746e2857863 ./zynq7/timings/RIOB33.sdf`](./zynq7/timings/RIOB33.sdf) * [`0fdaf6a593346b5cac8899eebf4f62d1732d6d6fb0a17c9f4b6a4e54e03c3523 ./zynq7/timings/RIOB33_SING.sdf`](./zynq7/timings/RIOB33_SING.sdf) - * [`fcde8675e577127516c2362f39a19ae75e6674eb53662a31b42ffddefdd8e8e4 ./zynq7/timings/RIOI3.sdf`](./zynq7/timings/RIOI3.sdf) - * [`fcde8675e577127516c2362f39a19ae75e6674eb53662a31b42ffddefdd8e8e4 ./zynq7/timings/RIOI3_SING.sdf`](./zynq7/timings/RIOI3_SING.sdf) - * [`fcde8675e577127516c2362f39a19ae75e6674eb53662a31b42ffddefdd8e8e4 ./zynq7/timings/RIOI3_TBYTESRC.sdf`](./zynq7/timings/RIOI3_TBYTESRC.sdf) - * [`fcde8675e577127516c2362f39a19ae75e6674eb53662a31b42ffddefdd8e8e4 ./zynq7/timings/RIOI3_TBYTETERM.sdf`](./zynq7/timings/RIOI3_TBYTETERM.sdf) + * [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./zynq7/timings/RIOI3.sdf`](./zynq7/timings/RIOI3.sdf) + * [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./zynq7/timings/RIOI3_SING.sdf`](./zynq7/timings/RIOI3_SING.sdf) + * [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./zynq7/timings/RIOI3_TBYTESRC.sdf`](./zynq7/timings/RIOI3_TBYTESRC.sdf) + * [`582431f616d6cba090545c71cea3ed3de7e1d07ee21820a2258bc9f397bb5083 ./zynq7/timings/RIOI3_TBYTETERM.sdf`](./zynq7/timings/RIOI3_TBYTETERM.sdf) * [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/R_TERM_INT.sdf`](./zynq7/timings/R_TERM_INT.sdf) * [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/TERM_CMT.sdf`](./zynq7/timings/TERM_CMT.sdf) * [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/T_TERM_INT.sdf`](./zynq7/timings/T_TERM_INT.sdf) * [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/VBRK.sdf`](./zynq7/timings/VBRK.sdf) * [`81327800f346931997047359f13f351a0ee95301d3f7ccf894c3335b9b5341a4 ./zynq7/timings/VFRAME.sdf`](./zynq7/timings/VFRAME.sdf) - * [`ca3e3a61d6070397ffa76245f3435a036adefb318e29172580725f7f0b8eb2b6 ./zynq7/timings/slicel.sdf`](./zynq7/timings/slicel.sdf) - * [`0877c0b0d5c6dd87b2a75221fa5245f537605682b67ae4d0a064e005e701de1e ./zynq7/timings/slicem.sdf`](./zynq7/timings/slicem.sdf) + * [`bbdb8b53bb1343cefbc977089069d67ef277fa758ae77e06d50aa8de6e503ae2 ./zynq7/timings/slicel.sdf`](./zynq7/timings/slicel.sdf) + * [`b0a63e17e651071eec70a4048fc3321d79a8b0f6d430ad323eebc8b624418b0a ./zynq7/timings/slicem.sdf`](./zynq7/timings/slicem.sdf) * [`f3704845c7559e0289c9a1c6f42a7874be6d5d7aef3e0f285647b8ca62a154b3 ./zynq7/xc7z010clg400-1.json`](./zynq7/xc7z010clg400-1.json) * [`43a136f26603c51bd97e9489d223bbc80f278fcc234225ed9fde404402f22683 ./zynq7/xc7z010clg400-1.yaml`](./zynq7/xc7z010clg400-1.yaml) * [`d9914c14b3a8d59c76dd5992c4727e4002acd5e14b32c1afe49f7be8798e4db9 ./zynq7/xc7z010clg400-1_package_pins.csv`](./zynq7/xc7z010clg400-1_package_pins.csv) diff --git a/zynq7/mask_liob33.db b/zynq7/mask_liob33.db index c3338c7..6dc8e75 100644 --- a/zynq7/mask_liob33.db +++ b/zynq7/mask_liob33.db @@ -1,3 +1,4 @@ +bit 00_01 bit 00_02 bit 00_03 bit 00_06 @@ -13,7 +14,6 @@ bit 00_35 bit 00_38 bit 00_39 bit 00_42 -bit 00_45 bit 00_46 bit 00_65 bit 00_67 @@ -57,6 +57,8 @@ bit 01_101 bit 01_102 bit 01_104 bit 01_105 +bit 02_02 +bit 02_03 bit 02_05 bit 02_06 bit 02_07 @@ -67,7 +69,6 @@ bit 02_14 bit 02_15 bit 02_22 bit 02_23 -bit 02_26 bit 02_30 bit 02_31 bit 02_42 @@ -96,25 +97,24 @@ bit 02_93 bit 02_94 bit 02_95 bit 02_102 -bit 02_103 bit 02_106 bit 02_110 bit 02_111 -bit 02_118 bit 02_125 bit 02_126 bit 02_127 bit 03_02 bit 03_04 -bit 03_05 bit 03_06 bit 03_10 bit 03_12 bit 03_13 bit 03_14 +bit 03_21 bit 03_29 bit 03_44 bit 03_45 +bit 03_52 bit 03_53 bit 03_60 bit 03_61 @@ -130,6 +130,7 @@ bit 03_93 bit 03_109 bit 03_110 bit 03_116 +bit 03_125 bit 03_126 bit 04_06 bit 04_07 @@ -138,6 +139,7 @@ bit 04_12 bit 04_13 bit 04_14 bit 04_15 +bit 04_19 bit 04_28 bit 04_29 bit 04_30 @@ -149,23 +151,21 @@ bit 04_59 bit 04_60 bit 04_61 bit 04_63 -bit 04_70 +bit 04_71 bit 04_75 bit 04_76 bit 04_77 bit 04_78 bit 04_79 -bit 04_83 bit 04_87 bit 04_92 -bit 04_93 bit 04_94 bit 04_103 bit 04_108 +bit 04_111 bit 04_115 bit 04_119 bit 04_124 -bit 04_125 bit 04_127 bit 05_01 bit 05_02 @@ -173,6 +173,7 @@ bit 05_05 bit 05_07 bit 05_10 bit 05_13 +bit 05_17 bit 05_18 bit 05_42 bit 05_49 @@ -187,13 +188,15 @@ bit 05_65 bit 05_66 bit 05_68 bit 05_69 +bit 05_70 +bit 05_73 bit 05_74 bit 05_76 bit 05_77 +bit 05_78 bit 05_81 bit 05_82 bit 05_86 -bit 05_102 bit 05_110 bit 05_113 bit 05_114 @@ -214,11 +217,10 @@ bit 06_13 bit 06_14 bit 06_15 bit 06_17 +bit 06_20 bit 06_22 -bit 06_23 bit 06_27 bit 06_28 -bit 06_29 bit 06_30 bit 06_31 bit 06_39 @@ -227,14 +229,12 @@ bit 06_44 bit 06_45 bit 06_46 bit 06_49 -bit 06_52 +bit 06_53 bit 06_59 bit 06_60 bit 06_61 -bit 06_63 bit 06_65 bit 06_66 -bit 06_68 bit 06_70 bit 06_71 bit 06_74 @@ -250,18 +250,23 @@ bit 06_91 bit 06_92 bit 06_93 bit 06_94 +bit 06_95 bit 06_103 bit 06_107 bit 06_108 +bit 06_121 bit 06_123 +bit 06_124 bit 06_125 bit 07_00 +bit 07_02 bit 07_03 bit 07_04 bit 07_05 bit 07_06 bit 07_07 bit 07_08 +bit 07_10 bit 07_11 bit 07_13 bit 07_14 @@ -272,8 +277,6 @@ bit 07_20 bit 07_22 bit 07_23 bit 07_24 -bit 07_27 -bit 07_28 bit 07_30 bit 07_31 bit 07_32 @@ -294,6 +297,7 @@ bit 07_59 bit 07_62 bit 07_63 bit 07_64 +bit 07_66 bit 07_67 bit 07_68 bit 07_69 @@ -306,12 +310,12 @@ bit 07_78 bit 07_79 bit 07_80 bit 07_83 -bit 07_84 bit 07_86 bit 07_87 bit 07_88 bit 07_94 bit 07_95 +bit 07_96 bit 07_100 bit 07_102 bit 07_103 @@ -323,7 +327,6 @@ bit 07_111 bit 07_112 bit 07_115 bit 07_118 -bit 07_119 bit 07_120 bit 07_126 bit 07_127 @@ -352,6 +355,7 @@ bit 08_25 bit 08_26 bit 08_27 bit 08_28 +bit 08_29 bit 08_30 bit 08_31 bit 08_32 @@ -365,7 +369,6 @@ bit 08_43 bit 08_46 bit 08_47 bit 08_49 -bit 08_53 bit 08_54 bit 08_55 bit 08_56 @@ -377,7 +380,6 @@ bit 08_63 bit 08_64 bit 08_65 bit 08_66 -bit 08_68 bit 08_69 bit 08_70 bit 08_71 @@ -397,6 +399,7 @@ bit 08_87 bit 08_88 bit 08_89 bit 08_90 +bit 08_91 bit 08_92 bit 08_93 bit 08_94 @@ -421,6 +424,7 @@ bit 08_120 bit 08_121 bit 08_122 bit 08_123 +bit 08_125 bit 08_126 bit 08_127 bit 09_00 @@ -432,13 +436,13 @@ bit 09_05 bit 09_06 bit 09_07 bit 09_08 +bit 09_10 bit 09_11 bit 09_13 bit 09_15 bit 09_16 bit 09_19 bit 09_20 -bit 09_21 bit 09_22 bit 09_23 bit 09_24 @@ -459,7 +463,6 @@ bit 09_53 bit 09_56 bit 09_57 bit 09_58 -bit 09_59 bit 09_63 bit 09_64 bit 09_65 @@ -470,10 +473,10 @@ bit 09_69 bit 09_75 bit 09_77 bit 09_79 +bit 09_80 bit 09_82 bit 09_83 bit 09_84 -bit 09_89 bit 09_91 bit 09_98 bit 09_99 @@ -486,15 +489,17 @@ bit 09_114 bit 09_115 bit 09_116 bit 09_120 +bit 09_121 bit 09_122 bit 09_123 bit 09_127 bit 10_00 +bit 10_01 bit 10_02 bit 10_03 bit 10_05 -bit 10_06 bit 10_07 +bit 10_08 bit 10_09 bit 10_10 bit 10_11 @@ -522,11 +527,11 @@ bit 10_42 bit 10_43 bit 10_46 bit 10_47 +bit 10_49 bit 10_50 -bit 10_52 +bit 10_51 bit 10_53 bit 10_55 -bit 10_56 bit 10_57 bit 10_58 bit 10_59 @@ -548,12 +553,12 @@ bit 10_79 bit 10_80 bit 10_81 bit 10_82 +bit 10_83 bit 10_85 bit 10_87 bit 10_88 bit 10_89 bit 10_90 -bit 10_91 bit 10_92 bit 10_94 bit 10_95 @@ -566,7 +571,6 @@ bit 10_107 bit 10_110 bit 10_111 bit 10_114 -bit 10_115 bit 10_117 bit 10_119 bit 10_120 @@ -587,6 +591,7 @@ bit 11_15 bit 11_17 bit 11_18 bit 11_19 +bit 11_20 bit 11_21 bit 11_23 bit 11_24 @@ -595,12 +600,14 @@ bit 11_26 bit 11_27 bit 11_31 bit 11_33 +bit 11_36 bit 11_37 bit 11_39 bit 11_40 bit 11_41 bit 11_42 bit 11_43 +bit 11_44 bit 11_47 bit 11_49 bit 11_50 @@ -616,7 +623,6 @@ bit 11_63 bit 11_65 bit 11_66 bit 11_67 -bit 11_68 bit 11_69 bit 11_71 bit 11_73 @@ -626,16 +632,13 @@ bit 11_77 bit 11_79 bit 11_81 bit 11_82 -bit 11_83 bit 11_87 bit 11_90 bit 11_91 bit 11_95 bit 11_97 -bit 11_100 bit 11_101 bit 11_103 -bit 11_104 bit 11_105 bit 11_106 bit 11_107 @@ -644,11 +647,9 @@ bit 11_113 bit 11_116 bit 11_117 bit 11_119 -bit 11_120 bit 11_121 bit 11_122 bit 11_123 -bit 11_125 bit 11_127 bit 12_00 bit 12_01 @@ -665,12 +666,13 @@ bit 12_14 bit 12_15 bit 12_16 bit 12_17 -bit 12_20 bit 12_21 bit 12_23 +bit 12_24 bit 12_25 bit 12_26 bit 12_27 +bit 12_29 bit 12_30 bit 12_31 bit 12_33 @@ -684,7 +686,8 @@ bit 12_46 bit 12_47 bit 12_48 bit 12_49 -bit 12_52 +bit 12_50 +bit 12_51 bit 12_53 bit 12_55 bit 12_57 @@ -704,13 +707,12 @@ bit 12_78 bit 12_79 bit 12_81 bit 12_82 +bit 12_83 bit 12_85 bit 12_87 -bit 12_88 bit 12_89 bit 12_90 bit 12_91 -bit 12_93 bit 12_94 bit 12_95 bit 12_97 @@ -725,7 +727,6 @@ bit 12_110 bit 12_111 bit 12_113 bit 12_114 -bit 12_115 bit 12_117 bit 12_119 bit 12_120 @@ -749,16 +750,17 @@ bit 13_12 bit 13_13 bit 13_14 bit 13_15 +bit 13_16 bit 13_17 bit 13_18 bit 13_19 +bit 13_20 bit 13_22 bit 13_23 bit 13_24 bit 13_25 bit 13_26 -bit 13_28 -bit 13_29 +bit 13_30 bit 13_31 bit 13_33 bit 13_34 @@ -781,10 +783,12 @@ bit 13_57 bit 13_58 bit 13_59 bit 13_60 +bit 13_62 bit 13_63 bit 13_64 bit 13_65 bit 13_66 +bit 13_67 bit 13_68 bit 13_69 bit 13_70 @@ -797,9 +801,9 @@ bit 13_76 bit 13_77 bit 13_78 bit 13_79 +bit 13_80 bit 13_81 bit 13_82 -bit 13_83 bit 13_86 bit 13_87 bit 13_88 @@ -811,7 +815,6 @@ bit 13_94 bit 13_95 bit 13_97 bit 13_98 -bit 13_100 bit 13_101 bit 13_102 bit 13_103 @@ -829,13 +832,16 @@ bit 13_120 bit 13_121 bit 13_122 bit 13_123 -bit 13_126 +bit 13_124 +bit 13_125 bit 13_127 bit 14_00 bit 14_01 bit 14_02 bit 14_03 bit 14_04 +bit 14_05 +bit 14_07 bit 14_09 bit 14_10 bit 14_11 @@ -847,19 +853,17 @@ bit 14_16 bit 14_18 bit 14_19 bit 14_20 -bit 14_23 bit 14_25 bit 14_26 -bit 14_28 bit 14_29 bit 14_30 bit 14_31 bit 14_34 bit 14_36 bit 14_42 +bit 14_46 bit 14_50 bit 14_52 -bit 14_56 bit 14_58 bit 14_64 bit 14_66 @@ -869,6 +873,7 @@ bit 14_69 bit 14_71 bit 14_73 bit 14_74 +bit 14_76 bit 14_77 bit 14_78 bit 14_79 @@ -878,25 +883,27 @@ bit 14_84 bit 14_87 bit 14_88 bit 14_89 -bit 14_90 bit 14_93 bit 14_94 bit 14_95 bit 14_98 bit 14_100 +bit 14_106 bit 14_114 bit 14_116 -bit 14_120 bit 14_122 +bit 14_126 bit 15_00 bit 15_01 bit 15_02 bit 15_03 +bit 15_04 bit 15_05 +bit 15_06 bit 15_07 +bit 15_08 bit 15_09 bit 15_10 -bit 15_11 bit 15_12 bit 15_13 bit 15_14 @@ -927,7 +934,6 @@ bit 15_63 bit 15_64 bit 15_65 bit 15_66 -bit 15_68 bit 15_69 bit 15_71 bit 15_72 @@ -941,7 +947,6 @@ bit 15_79 bit 15_80 bit 15_81 bit 15_82 -bit 15_85 bit 15_87 bit 15_89 bit 15_90 @@ -960,7 +965,6 @@ bit 15_113 bit 15_119 bit 15_121 bit 15_123 -bit 15_125 bit 15_127 bit 16_02 bit 16_06 @@ -973,6 +977,7 @@ bit 16_23 bit 16_24 bit 16_30 bit 16_31 +bit 16_32 bit 16_35 bit 16_38 bit 16_40 @@ -1002,7 +1007,6 @@ bit 16_94 bit 16_95 bit 16_99 bit 16_102 -bit 16_103 bit 16_104 bit 16_106 bit 16_107 @@ -1029,9 +1033,9 @@ bit 17_23 bit 17_24 bit 17_30 bit 17_31 +bit 17_32 bit 17_35 bit 17_38 -bit 17_39 bit 17_40 bit 17_42 bit 17_43 @@ -1048,11 +1052,14 @@ bit 17_60 bit 17_62 bit 17_66 bit 17_70 +bit 17_71 bit 17_73 bit 17_79 +bit 17_80 bit 17_85 bit 17_86 bit 17_87 +bit 17_88 bit 17_94 bit 17_95 bit 17_99 @@ -1084,7 +1091,6 @@ bit 18_23 bit 18_25 bit 18_30 bit 18_31 -bit 18_33 bit 18_34 bit 18_38 bit 18_39 @@ -1116,6 +1122,7 @@ bit 18_97 bit 18_98 bit 18_102 bit 18_103 +bit 18_105 bit 18_106 bit 18_107 bit 18_109 @@ -1133,6 +1140,7 @@ bit 19_01 bit 19_03 bit 19_07 bit 19_08 +bit 19_09 bit 19_14 bit 19_17 bit 19_20 @@ -1152,6 +1160,7 @@ bit 19_46 bit 19_47 bit 19_49 bit 19_50 +bit 19_54 bit 19_55 bit 19_56 bit 19_57 @@ -1182,6 +1191,7 @@ bit 19_113 bit 19_114 bit 19_119 bit 19_120 +bit 19_121 bit 19_123 bit 19_125 bit 19_127 @@ -1256,6 +1266,7 @@ bit 21_85 bit 21_86 bit 21_94 bit 21_98 +bit 21_99 bit 21_102 bit 21_106 bit 21_107 @@ -1277,8 +1288,10 @@ bit 22_22 bit 22_23 bit 22_30 bit 22_31 +bit 22_32 bit 22_35 bit 22_38 +bit 22_40 bit 22_42 bit 22_43 bit 22_44 @@ -1287,6 +1300,7 @@ bit 22_47 bit 22_48 bit 22_51 bit 22_54 +bit 22_55 bit 22_56 bit 22_57 bit 22_58 @@ -1294,21 +1308,22 @@ bit 22_60 bit 22_62 bit 22_66 bit 22_70 -bit 22_71 bit 22_73 +bit 22_79 bit 22_85 bit 22_86 bit 22_87 bit 22_94 bit 22_95 +bit 22_96 bit 22_99 bit 22_102 -bit 22_103 bit 22_106 bit 22_107 bit 22_108 bit 22_110 bit 22_111 +bit 22_112 bit 22_115 bit 22_118 bit 22_121 @@ -1330,7 +1345,6 @@ bit 23_31 bit 23_32 bit 23_35 bit 23_38 -bit 23_39 bit 23_40 bit 23_42 bit 23_43 @@ -1421,6 +1435,7 @@ bit 24_84 bit 24_85 bit 24_86 bit 24_87 +bit 24_88 bit 24_94 bit 24_95 bit 24_96 @@ -1446,6 +1461,7 @@ bit 25_00 bit 25_02 bit 25_06 bit 25_07 +bit 25_08 bit 25_09 bit 25_15 bit 25_16 @@ -1471,6 +1487,7 @@ bit 25_48 bit 25_51 bit 25_52 bit 25_54 +bit 25_55 bit 25_56 bit 25_57 bit 25_58 diff --git a/zynq7/mask_riob33.db b/zynq7/mask_riob33.db index be6cd61..53cd71c 100644 --- a/zynq7/mask_riob33.db +++ b/zynq7/mask_riob33.db @@ -1,3 +1,4 @@ +bit 00_01 bit 00_02 bit 00_03 bit 00_06 @@ -13,7 +14,6 @@ bit 00_35 bit 00_38 bit 00_39 bit 00_42 -bit 00_45 bit 00_46 bit 00_65 bit 00_67 @@ -57,6 +57,8 @@ bit 01_101 bit 01_102 bit 01_104 bit 01_105 +bit 02_02 +bit 02_03 bit 02_05 bit 02_06 bit 02_07 @@ -67,7 +69,6 @@ bit 02_14 bit 02_15 bit 02_22 bit 02_23 -bit 02_26 bit 02_30 bit 02_31 bit 02_42 @@ -96,25 +97,24 @@ bit 02_93 bit 02_94 bit 02_95 bit 02_102 -bit 02_103 bit 02_106 bit 02_110 bit 02_111 -bit 02_118 bit 02_125 bit 02_126 bit 02_127 bit 03_02 bit 03_04 -bit 03_05 bit 03_06 bit 03_10 bit 03_12 bit 03_13 bit 03_14 +bit 03_21 bit 03_29 bit 03_44 bit 03_45 +bit 03_52 bit 03_53 bit 03_60 bit 03_61 @@ -130,6 +130,7 @@ bit 03_93 bit 03_109 bit 03_110 bit 03_116 +bit 03_125 bit 03_126 bit 04_06 bit 04_07 @@ -138,6 +139,7 @@ bit 04_12 bit 04_13 bit 04_14 bit 04_15 +bit 04_19 bit 04_28 bit 04_29 bit 04_30 @@ -149,23 +151,21 @@ bit 04_59 bit 04_60 bit 04_61 bit 04_63 -bit 04_70 +bit 04_71 bit 04_75 bit 04_76 bit 04_77 bit 04_78 bit 04_79 -bit 04_83 bit 04_87 bit 04_92 -bit 04_93 bit 04_94 bit 04_103 bit 04_108 +bit 04_111 bit 04_115 bit 04_119 bit 04_124 -bit 04_125 bit 04_127 bit 05_01 bit 05_02 @@ -173,6 +173,7 @@ bit 05_05 bit 05_07 bit 05_10 bit 05_13 +bit 05_17 bit 05_18 bit 05_42 bit 05_49 @@ -187,13 +188,15 @@ bit 05_65 bit 05_66 bit 05_68 bit 05_69 +bit 05_70 +bit 05_73 bit 05_74 bit 05_76 bit 05_77 +bit 05_78 bit 05_81 bit 05_82 bit 05_86 -bit 05_102 bit 05_110 bit 05_113 bit 05_114 @@ -214,11 +217,10 @@ bit 06_13 bit 06_14 bit 06_15 bit 06_17 +bit 06_20 bit 06_22 -bit 06_23 bit 06_27 bit 06_28 -bit 06_29 bit 06_30 bit 06_31 bit 06_39 @@ -227,14 +229,12 @@ bit 06_44 bit 06_45 bit 06_46 bit 06_49 -bit 06_52 +bit 06_53 bit 06_59 bit 06_60 bit 06_61 -bit 06_63 bit 06_65 bit 06_66 -bit 06_68 bit 06_70 bit 06_71 bit 06_74 @@ -250,18 +250,23 @@ bit 06_91 bit 06_92 bit 06_93 bit 06_94 +bit 06_95 bit 06_103 bit 06_107 bit 06_108 +bit 06_121 bit 06_123 +bit 06_124 bit 06_125 bit 07_00 +bit 07_02 bit 07_03 bit 07_04 bit 07_05 bit 07_06 bit 07_07 bit 07_08 +bit 07_10 bit 07_11 bit 07_13 bit 07_14 @@ -272,8 +277,6 @@ bit 07_20 bit 07_22 bit 07_23 bit 07_24 -bit 07_27 -bit 07_28 bit 07_30 bit 07_31 bit 07_32 @@ -294,6 +297,7 @@ bit 07_59 bit 07_62 bit 07_63 bit 07_64 +bit 07_66 bit 07_67 bit 07_68 bit 07_69 @@ -306,12 +310,12 @@ bit 07_78 bit 07_79 bit 07_80 bit 07_83 -bit 07_84 bit 07_86 bit 07_87 bit 07_88 bit 07_94 bit 07_95 +bit 07_96 bit 07_100 bit 07_102 bit 07_103 @@ -323,7 +327,6 @@ bit 07_111 bit 07_112 bit 07_115 bit 07_118 -bit 07_119 bit 07_120 bit 07_126 bit 07_127 @@ -352,6 +355,7 @@ bit 08_25 bit 08_26 bit 08_27 bit 08_28 +bit 08_29 bit 08_30 bit 08_31 bit 08_32 @@ -365,7 +369,6 @@ bit 08_43 bit 08_46 bit 08_47 bit 08_49 -bit 08_53 bit 08_54 bit 08_55 bit 08_56 @@ -377,7 +380,6 @@ bit 08_63 bit 08_64 bit 08_65 bit 08_66 -bit 08_68 bit 08_69 bit 08_70 bit 08_71 @@ -397,6 +399,7 @@ bit 08_87 bit 08_88 bit 08_89 bit 08_90 +bit 08_91 bit 08_92 bit 08_93 bit 08_94 @@ -421,6 +424,7 @@ bit 08_120 bit 08_121 bit 08_122 bit 08_123 +bit 08_125 bit 08_126 bit 08_127 bit 09_00 @@ -432,13 +436,13 @@ bit 09_05 bit 09_06 bit 09_07 bit 09_08 +bit 09_10 bit 09_11 bit 09_13 bit 09_15 bit 09_16 bit 09_19 bit 09_20 -bit 09_21 bit 09_22 bit 09_23 bit 09_24 @@ -459,7 +463,6 @@ bit 09_53 bit 09_56 bit 09_57 bit 09_58 -bit 09_59 bit 09_63 bit 09_64 bit 09_65 @@ -470,10 +473,10 @@ bit 09_69 bit 09_75 bit 09_77 bit 09_79 +bit 09_80 bit 09_82 bit 09_83 bit 09_84 -bit 09_89 bit 09_91 bit 09_98 bit 09_99 @@ -486,15 +489,17 @@ bit 09_114 bit 09_115 bit 09_116 bit 09_120 +bit 09_121 bit 09_122 bit 09_123 bit 09_127 bit 10_00 +bit 10_01 bit 10_02 bit 10_03 bit 10_05 -bit 10_06 bit 10_07 +bit 10_08 bit 10_09 bit 10_10 bit 10_11 @@ -522,11 +527,11 @@ bit 10_42 bit 10_43 bit 10_46 bit 10_47 +bit 10_49 bit 10_50 -bit 10_52 +bit 10_51 bit 10_53 bit 10_55 -bit 10_56 bit 10_57 bit 10_58 bit 10_59 @@ -548,12 +553,12 @@ bit 10_79 bit 10_80 bit 10_81 bit 10_82 +bit 10_83 bit 10_85 bit 10_87 bit 10_88 bit 10_89 bit 10_90 -bit 10_91 bit 10_92 bit 10_94 bit 10_95 @@ -566,7 +571,6 @@ bit 10_107 bit 10_110 bit 10_111 bit 10_114 -bit 10_115 bit 10_117 bit 10_119 bit 10_120 @@ -587,6 +591,7 @@ bit 11_15 bit 11_17 bit 11_18 bit 11_19 +bit 11_20 bit 11_21 bit 11_23 bit 11_24 @@ -595,12 +600,14 @@ bit 11_26 bit 11_27 bit 11_31 bit 11_33 +bit 11_36 bit 11_37 bit 11_39 bit 11_40 bit 11_41 bit 11_42 bit 11_43 +bit 11_44 bit 11_47 bit 11_49 bit 11_50 @@ -616,7 +623,6 @@ bit 11_63 bit 11_65 bit 11_66 bit 11_67 -bit 11_68 bit 11_69 bit 11_71 bit 11_73 @@ -626,16 +632,13 @@ bit 11_77 bit 11_79 bit 11_81 bit 11_82 -bit 11_83 bit 11_87 bit 11_90 bit 11_91 bit 11_95 bit 11_97 -bit 11_100 bit 11_101 bit 11_103 -bit 11_104 bit 11_105 bit 11_106 bit 11_107 @@ -644,11 +647,9 @@ bit 11_113 bit 11_116 bit 11_117 bit 11_119 -bit 11_120 bit 11_121 bit 11_122 bit 11_123 -bit 11_125 bit 11_127 bit 12_00 bit 12_01 @@ -665,12 +666,13 @@ bit 12_14 bit 12_15 bit 12_16 bit 12_17 -bit 12_20 bit 12_21 bit 12_23 +bit 12_24 bit 12_25 bit 12_26 bit 12_27 +bit 12_29 bit 12_30 bit 12_31 bit 12_33 @@ -684,7 +686,8 @@ bit 12_46 bit 12_47 bit 12_48 bit 12_49 -bit 12_52 +bit 12_50 +bit 12_51 bit 12_53 bit 12_55 bit 12_57 @@ -704,13 +707,12 @@ bit 12_78 bit 12_79 bit 12_81 bit 12_82 +bit 12_83 bit 12_85 bit 12_87 -bit 12_88 bit 12_89 bit 12_90 bit 12_91 -bit 12_93 bit 12_94 bit 12_95 bit 12_97 @@ -725,7 +727,6 @@ bit 12_110 bit 12_111 bit 12_113 bit 12_114 -bit 12_115 bit 12_117 bit 12_119 bit 12_120 @@ -749,16 +750,17 @@ bit 13_12 bit 13_13 bit 13_14 bit 13_15 +bit 13_16 bit 13_17 bit 13_18 bit 13_19 +bit 13_20 bit 13_22 bit 13_23 bit 13_24 bit 13_25 bit 13_26 -bit 13_28 -bit 13_29 +bit 13_30 bit 13_31 bit 13_33 bit 13_34 @@ -781,10 +783,12 @@ bit 13_57 bit 13_58 bit 13_59 bit 13_60 +bit 13_62 bit 13_63 bit 13_64 bit 13_65 bit 13_66 +bit 13_67 bit 13_68 bit 13_69 bit 13_70 @@ -797,9 +801,9 @@ bit 13_76 bit 13_77 bit 13_78 bit 13_79 +bit 13_80 bit 13_81 bit 13_82 -bit 13_83 bit 13_86 bit 13_87 bit 13_88 @@ -811,7 +815,6 @@ bit 13_94 bit 13_95 bit 13_97 bit 13_98 -bit 13_100 bit 13_101 bit 13_102 bit 13_103 @@ -829,13 +832,16 @@ bit 13_120 bit 13_121 bit 13_122 bit 13_123 -bit 13_126 +bit 13_124 +bit 13_125 bit 13_127 bit 14_00 bit 14_01 bit 14_02 bit 14_03 bit 14_04 +bit 14_05 +bit 14_07 bit 14_09 bit 14_10 bit 14_11 @@ -847,19 +853,17 @@ bit 14_16 bit 14_18 bit 14_19 bit 14_20 -bit 14_23 bit 14_25 bit 14_26 -bit 14_28 bit 14_29 bit 14_30 bit 14_31 bit 14_34 bit 14_36 bit 14_42 +bit 14_46 bit 14_50 bit 14_52 -bit 14_56 bit 14_58 bit 14_64 bit 14_66 @@ -869,6 +873,7 @@ bit 14_69 bit 14_71 bit 14_73 bit 14_74 +bit 14_76 bit 14_77 bit 14_78 bit 14_79 @@ -878,25 +883,27 @@ bit 14_84 bit 14_87 bit 14_88 bit 14_89 -bit 14_90 bit 14_93 bit 14_94 bit 14_95 bit 14_98 bit 14_100 +bit 14_106 bit 14_114 bit 14_116 -bit 14_120 bit 14_122 +bit 14_126 bit 15_00 bit 15_01 bit 15_02 bit 15_03 +bit 15_04 bit 15_05 +bit 15_06 bit 15_07 +bit 15_08 bit 15_09 bit 15_10 -bit 15_11 bit 15_12 bit 15_13 bit 15_14 @@ -927,7 +934,6 @@ bit 15_63 bit 15_64 bit 15_65 bit 15_66 -bit 15_68 bit 15_69 bit 15_71 bit 15_72 @@ -941,7 +947,6 @@ bit 15_79 bit 15_80 bit 15_81 bit 15_82 -bit 15_85 bit 15_87 bit 15_89 bit 15_90 @@ -960,7 +965,6 @@ bit 15_113 bit 15_119 bit 15_121 bit 15_123 -bit 15_125 bit 15_127 bit 16_02 bit 16_06 @@ -973,6 +977,7 @@ bit 16_23 bit 16_24 bit 16_30 bit 16_31 +bit 16_32 bit 16_35 bit 16_38 bit 16_40 @@ -1002,7 +1007,6 @@ bit 16_94 bit 16_95 bit 16_99 bit 16_102 -bit 16_103 bit 16_104 bit 16_106 bit 16_107 @@ -1029,9 +1033,9 @@ bit 17_23 bit 17_24 bit 17_30 bit 17_31 +bit 17_32 bit 17_35 bit 17_38 -bit 17_39 bit 17_40 bit 17_42 bit 17_43 @@ -1048,11 +1052,14 @@ bit 17_60 bit 17_62 bit 17_66 bit 17_70 +bit 17_71 bit 17_73 bit 17_79 +bit 17_80 bit 17_85 bit 17_86 bit 17_87 +bit 17_88 bit 17_94 bit 17_95 bit 17_99 @@ -1084,7 +1091,6 @@ bit 18_23 bit 18_25 bit 18_30 bit 18_31 -bit 18_33 bit 18_34 bit 18_38 bit 18_39 @@ -1116,6 +1122,7 @@ bit 18_97 bit 18_98 bit 18_102 bit 18_103 +bit 18_105 bit 18_106 bit 18_107 bit 18_109 @@ -1133,6 +1140,7 @@ bit 19_01 bit 19_03 bit 19_07 bit 19_08 +bit 19_09 bit 19_14 bit 19_17 bit 19_20 @@ -1152,6 +1160,7 @@ bit 19_46 bit 19_47 bit 19_49 bit 19_50 +bit 19_54 bit 19_55 bit 19_56 bit 19_57 @@ -1182,6 +1191,7 @@ bit 19_113 bit 19_114 bit 19_119 bit 19_120 +bit 19_121 bit 19_123 bit 19_125 bit 19_127 @@ -1256,6 +1266,7 @@ bit 21_85 bit 21_86 bit 21_94 bit 21_98 +bit 21_99 bit 21_102 bit 21_106 bit 21_107 @@ -1277,8 +1288,10 @@ bit 22_22 bit 22_23 bit 22_30 bit 22_31 +bit 22_32 bit 22_35 bit 22_38 +bit 22_40 bit 22_42 bit 22_43 bit 22_44 @@ -1287,6 +1300,7 @@ bit 22_47 bit 22_48 bit 22_51 bit 22_54 +bit 22_55 bit 22_56 bit 22_57 bit 22_58 @@ -1294,21 +1308,22 @@ bit 22_60 bit 22_62 bit 22_66 bit 22_70 -bit 22_71 bit 22_73 +bit 22_79 bit 22_85 bit 22_86 bit 22_87 bit 22_94 bit 22_95 +bit 22_96 bit 22_99 bit 22_102 -bit 22_103 bit 22_106 bit 22_107 bit 22_108 bit 22_110 bit 22_111 +bit 22_112 bit 22_115 bit 22_118 bit 22_121 @@ -1330,7 +1345,6 @@ bit 23_31 bit 23_32 bit 23_35 bit 23_38 -bit 23_39 bit 23_40 bit 23_42 bit 23_43 @@ -1421,6 +1435,7 @@ bit 24_84 bit 24_85 bit 24_86 bit 24_87 +bit 24_88 bit 24_94 bit 24_95 bit 24_96 @@ -1446,6 +1461,7 @@ bit 25_00 bit 25_02 bit 25_06 bit 25_07 +bit 25_08 bit 25_09 bit 25_15 bit 25_16 @@ -1471,6 +1487,7 @@ bit 25_48 bit 25_51 bit 25_52 bit 25_54 +bit 25_55 bit 25_56 bit 25_57 bit 25_58 diff --git a/zynq7/segbits_bram_l.block_ram.origin_info.db b/zynq7/segbits_bram_l.block_ram.origin_info.db new file mode 100644 index 0000000..5be83f6 --- /dev/null +++ b/zynq7/segbits_bram_l.block_ram.origin_info.db @@ -0,0 +1,36864 @@ +BRAM_L.RAMB18_Y0.INITP_00[000] origin:026-bram-data 00_64 +BRAM_L.RAMB18_Y0.INITP_00[001] origin:026-bram-data 00_72 +BRAM_L.RAMB18_Y0.INITP_00[002] origin:026-bram-data 00_68 +BRAM_L.RAMB18_Y0.INITP_00[003] origin:026-bram-data 00_76 +BRAM_L.RAMB18_Y0.INITP_00[004] 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b/zynq7/segbits_bram_l.origin_info.db new file mode 100644 index 0000000..d8170a7 --- /dev/null +++ b/zynq7/segbits_bram_l.origin_info.db @@ -0,0 +1,452 @@ +BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINBOT_ADDRARDADDRU0 origin:060-bram-cascades !26_33 26_32 26_35 +BRAM_L.BRAM_ADDRARDADDRL0.BRAM_CASCINTOP_ADDRARDADDRU0 origin:060-bram-cascades !26_35 26_32 26_33 +BRAM_L.BRAM_ADDRARDADDRL0.BRAM_IMUX_ADDRARDADDRL0 origin:060-bram-cascades !26_32 !26_33 !26_35 +BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINBOT_ADDRARDADDRU1 origin:060-bram-cascades !26_49 26_48 26_51 +BRAM_L.BRAM_ADDRARDADDRL1.BRAM_CASCINTOP_ADDRARDADDRU1 origin:060-bram-cascades !26_51 26_48 26_49 +BRAM_L.BRAM_ADDRARDADDRL1.BRAM_IMUX_ADDRARDADDRL1 origin:060-bram-cascades !26_48 !26_49 !26_51 +BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_145 26_144 26_147 +BRAM_L.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_147 26_144 26_145 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origin:060-bram-cascades !26_117 !26_118 !26_119 +BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINBOT_ADDRARDADDRU12 origin:060-bram-cascades !26_246 26_245 26_247 +BRAM_L.BRAM_ADDRARDADDRU12.BRAM_CASCINTOP_ADDRARDADDRU12 origin:060-bram-cascades !26_245 26_246 26_247 +BRAM_L.BRAM_ADDRARDADDRU12.BRAM_IMUX_ADDRARDADDRU12 origin:060-bram-cascades !26_245 !26_246 !26_247 +BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINBOT_ADDRARDADDRU13 origin:060-bram-cascades !26_134 26_133 26_135 +BRAM_L.BRAM_ADDRARDADDRU13.BRAM_CASCINTOP_ADDRARDADDRU13 origin:060-bram-cascades !26_133 26_134 26_135 +BRAM_L.BRAM_ADDRARDADDRU13.BRAM_IMUX_ADDRARDADDRU13 origin:060-bram-cascades !26_133 !26_134 !26_135 +BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINBOT_ADDRARDADDRU14 origin:060-bram-cascades !26_262 26_261 26_263 +BRAM_L.BRAM_ADDRARDADDRU14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_261 26_262 26_263 +BRAM_L.BRAM_ADDRARDADDRU14.BRAM_IMUX_ADDRARDADDRU14 origin:060-bram-cascades !26_261 !26_262 !26_263 +BRAM_L.BRAM_ADDRARDADDRU2.BRAM_CASCINBOT_ADDRARDADDRU2 origin:060-bram-cascades !26_70 26_69 26_71 +BRAM_L.BRAM_ADDRARDADDRU2.BRAM_CASCINTOP_ADDRARDADDRU2 origin:060-bram-cascades !26_69 26_70 26_71 +BRAM_L.BRAM_ADDRARDADDRU2.BRAM_IMUX_ADDRARDADDRU2 origin:060-bram-cascades !26_69 !26_70 !26_71 +BRAM_L.BRAM_ADDRARDADDRU3.BRAM_CASCINBOT_ADDRARDADDRU3 origin:060-bram-cascades !26_198 26_197 26_199 +BRAM_L.BRAM_ADDRARDADDRU3.BRAM_CASCINTOP_ADDRARDADDRU3 origin:060-bram-cascades !26_197 26_198 26_199 +BRAM_L.BRAM_ADDRARDADDRU3.BRAM_IMUX_ADDRARDADDRU3 origin:060-bram-cascades !26_197 !26_198 !26_199 +BRAM_L.BRAM_ADDRARDADDRU4.BRAM_CASCINBOT_ADDRARDADDRU4 origin:060-bram-cascades !26_102 26_101 26_103 +BRAM_L.BRAM_ADDRARDADDRU4.BRAM_CASCINTOP_ADDRARDADDRU4 origin:060-bram-cascades !26_101 26_102 26_103 +BRAM_L.BRAM_ADDRARDADDRU4.BRAM_IMUX_ADDRARDADDRU4 origin:060-bram-cascades !26_101 !26_102 !26_103 +BRAM_L.BRAM_ADDRARDADDRU5.BRAM_CASCINBOT_ADDRARDADDRU5 origin:060-bram-cascades !26_230 26_229 26_231 +BRAM_L.BRAM_ADDRARDADDRU5.BRAM_CASCINTOP_ADDRARDADDRU5 origin:060-bram-cascades !26_229 26_230 26_231 +BRAM_L.BRAM_ADDRARDADDRU5.BRAM_IMUX_ADDRARDADDRU5 origin:060-bram-cascades !26_229 !26_230 !26_231 +BRAM_L.BRAM_ADDRARDADDRU6.BRAM_CASCINBOT_ADDRARDADDRU6 origin:060-bram-cascades !26_166 26_165 26_167 +BRAM_L.BRAM_ADDRARDADDRU6.BRAM_CASCINTOP_ADDRARDADDRU6 origin:060-bram-cascades !26_165 26_166 26_167 +BRAM_L.BRAM_ADDRARDADDRU6.BRAM_IMUX_ADDRARDADDRU6 origin:060-bram-cascades !26_165 !26_166 !26_167 +BRAM_L.BRAM_ADDRARDADDRU7.BRAM_CASCINBOT_ADDRARDADDRU7 origin:060-bram-cascades !26_182 26_181 26_183 +BRAM_L.BRAM_ADDRARDADDRU7.BRAM_CASCINTOP_ADDRARDADDRU7 origin:060-bram-cascades !26_181 26_182 26_183 +BRAM_L.BRAM_ADDRARDADDRU7.BRAM_IMUX_ADDRARDADDRU7 origin:060-bram-cascades !26_181 !26_182 !26_183 +BRAM_L.BRAM_ADDRARDADDRU8.BRAM_CASCINBOT_ADDRARDADDRU8 origin:060-bram-cascades !26_86 26_85 26_87 +BRAM_L.BRAM_ADDRARDADDRU8.BRAM_CASCINTOP_ADDRARDADDRU8 origin:060-bram-cascades !26_85 26_86 26_87 +BRAM_L.BRAM_ADDRARDADDRU8.BRAM_IMUX_ADDRARDADDRU8 origin:060-bram-cascades !26_85 !26_86 !26_87 +BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINBOT_ADDRARDADDRU9 origin:060-bram-cascades !26_214 26_213 26_215 +BRAM_L.BRAM_ADDRARDADDRU9.BRAM_CASCINTOP_ADDRARDADDRU9 origin:060-bram-cascades !26_213 26_214 26_215 +BRAM_L.BRAM_ADDRARDADDRU9.BRAM_IMUX_ADDRARDADDRU9 origin:060-bram-cascades !26_213 !26_214 !26_215 +BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINBOT_ADDRBWRADDRU0 origin:060-bram-cascades !26_41 26_40 26_43 +BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_CASCINTOP_ADDRBWRADDRU0 origin:060-bram-cascades !26_43 26_40 26_41 +BRAM_L.BRAM_ADDRBWRADDRL0.BRAM_IMUX_ADDRBWRADDRL0 origin:060-bram-cascades !26_40 !26_41 !26_43 +BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINBOT_ADDRBWRADDRU1 origin:060-bram-cascades !26_57 26_56 26_59 +BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_CASCINTOP_ADDRBWRADDRU1 origin:060-bram-cascades !26_59 26_56 26_57 +BRAM_L.BRAM_ADDRBWRADDRL1.BRAM_IMUX_ADDRBWRADDRL1 origin:060-bram-cascades !26_56 !26_57 !26_59 +BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_153 26_152 26_155 +BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_155 26_152 26_153 +BRAM_L.BRAM_ADDRBWRADDRL10.BRAM_IMUX_ADDRBWRADDRL10 origin:060-bram-cascades !26_152 !26_153 !26_155 +BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_121 26_120 26_123 +BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_123 26_120 26_121 +BRAM_L.BRAM_ADDRBWRADDRL11.BRAM_IMUX_ADDRBWRADDRL11 origin:060-bram-cascades !26_120 !26_121 !26_123 +BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_249 26_248 26_251 +BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_251 26_248 26_249 +BRAM_L.BRAM_ADDRBWRADDRL12.BRAM_IMUX_ADDRBWRADDRL12 origin:060-bram-cascades !26_248 !26_249 !26_251 +BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_137 26_136 26_139 +BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_139 26_136 26_137 +BRAM_L.BRAM_ADDRBWRADDRL13.BRAM_IMUX_ADDRBWRADDRL13 origin:060-bram-cascades !26_136 !26_137 !26_139 +BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_265 26_264 26_267 +BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_267 26_264 26_265 +BRAM_L.BRAM_ADDRBWRADDRL14.BRAM_IMUX_ADDRBWRADDRL14 origin:060-bram-cascades !26_264 !26_265 !26_267 +BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_CASCINBOT_ADDRBWRADDRU2 origin:060-bram-cascades !26_73 26_72 26_75 +BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_CASCINTOP_ADDRBWRADDRU2 origin:060-bram-cascades !26_75 26_72 26_73 +BRAM_L.BRAM_ADDRBWRADDRL2.BRAM_IMUX_ADDRBWRADDRL2 origin:060-bram-cascades !26_72 !26_73 !26_75 +BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_CASCINBOT_ADDRBWRADDRU3 origin:060-bram-cascades !26_201 26_200 26_203 +BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_CASCINTOP_ADDRBWRADDRU3 origin:060-bram-cascades !26_203 26_200 26_201 +BRAM_L.BRAM_ADDRBWRADDRL3.BRAM_IMUX_ADDRBWRADDRL3 origin:060-bram-cascades !26_200 !26_201 !26_203 +BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_CASCINBOT_ADDRBWRADDRU4 origin:060-bram-cascades !26_105 26_104 26_107 +BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_CASCINTOP_ADDRBWRADDRU4 origin:060-bram-cascades !26_107 26_104 26_105 +BRAM_L.BRAM_ADDRBWRADDRL4.BRAM_IMUX_ADDRBWRADDRL4 origin:060-bram-cascades !26_104 !26_105 !26_107 +BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_CASCINBOT_ADDRBWRADDRU5 origin:060-bram-cascades !26_233 26_232 26_235 +BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_CASCINTOP_ADDRBWRADDRU5 origin:060-bram-cascades !26_235 26_232 26_233 +BRAM_L.BRAM_ADDRBWRADDRL5.BRAM_IMUX_ADDRBWRADDRL5 origin:060-bram-cascades !26_232 !26_233 !26_235 +BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_CASCINBOT_ADDRBWRADDRU6 origin:060-bram-cascades !26_169 26_168 26_171 +BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_CASCINTOP_ADDRBWRADDRU6 origin:060-bram-cascades !26_171 26_168 26_169 +BRAM_L.BRAM_ADDRBWRADDRL6.BRAM_IMUX_ADDRBWRADDRL6 origin:060-bram-cascades !26_168 !26_169 !26_171 +BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_CASCINBOT_ADDRBWRADDRU7 origin:060-bram-cascades !26_185 26_184 26_187 +BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_CASCINTOP_ADDRBWRADDRU7 origin:060-bram-cascades !26_187 26_184 26_185 +BRAM_L.BRAM_ADDRBWRADDRL7.BRAM_IMUX_ADDRBWRADDRL7 origin:060-bram-cascades !26_184 !26_185 !26_187 +BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_CASCINBOT_ADDRBWRADDRU8 origin:060-bram-cascades !26_89 26_88 26_91 +BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_CASCINTOP_ADDRBWRADDRU8 origin:060-bram-cascades !26_91 26_88 26_89 +BRAM_L.BRAM_ADDRBWRADDRL8.BRAM_IMUX_ADDRBWRADDRL8 origin:060-bram-cascades !26_88 !26_89 !26_91 +BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_217 26_216 26_219 +BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_219 26_216 26_217 +BRAM_L.BRAM_ADDRBWRADDRL9.BRAM_IMUX_ADDRBWRADDRL9 origin:060-bram-cascades !26_216 !26_217 !26_219 +BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINBOT_ADDRBWRADDRU0 origin:060-bram-cascades !26_46 26_45 26_47 +BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_CASCINTOP_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 26_46 26_47 +BRAM_L.BRAM_ADDRBWRADDRU0.BRAM_IMUX_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 !26_46 !26_47 +BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINBOT_ADDRBWRADDRU1 origin:060-bram-cascades !26_62 26_61 26_63 +BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_CASCINTOP_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 26_62 26_63 +BRAM_L.BRAM_ADDRBWRADDRU1.BRAM_IMUX_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 !26_62 !26_63 +BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_158 26_157 26_159 +BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 26_158 26_159 +BRAM_L.BRAM_ADDRBWRADDRU10.BRAM_IMUX_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 !26_158 !26_159 +BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_126 26_125 26_127 +BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 26_126 26_127 +BRAM_L.BRAM_ADDRBWRADDRU11.BRAM_IMUX_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 !26_126 !26_127 +BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_254 26_253 26_255 +BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 26_254 26_255 +BRAM_L.BRAM_ADDRBWRADDRU12.BRAM_IMUX_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 !26_254 !26_255 +BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_142 26_141 26_143 +BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 26_142 26_143 +BRAM_L.BRAM_ADDRBWRADDRU13.BRAM_IMUX_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 !26_142 !26_143 +BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_270 26_269 26_271 +BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 26_270 26_271 +BRAM_L.BRAM_ADDRBWRADDRU14.BRAM_IMUX_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 !26_270 !26_271 +BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_CASCINBOT_ADDRBWRADDRU2 origin:060-bram-cascades !26_78 26_77 26_79 +BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_CASCINTOP_ADDRBWRADDRU2 origin:060-bram-cascades !26_77 26_78 26_79 +BRAM_L.BRAM_ADDRBWRADDRU2.BRAM_IMUX_ADDRBWRADDRU2 origin:060-bram-cascades !26_77 !26_78 !26_79 +BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_CASCINBOT_ADDRBWRADDRU3 origin:060-bram-cascades !26_206 26_205 26_207 +BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_CASCINTOP_ADDRBWRADDRU3 origin:060-bram-cascades !26_205 26_206 26_207 +BRAM_L.BRAM_ADDRBWRADDRU3.BRAM_IMUX_ADDRBWRADDRU3 origin:060-bram-cascades !26_205 !26_206 !26_207 +BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_CASCINBOT_ADDRBWRADDRU4 origin:060-bram-cascades !26_110 26_109 26_111 +BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_CASCINTOP_ADDRBWRADDRU4 origin:060-bram-cascades !26_109 26_110 26_111 +BRAM_L.BRAM_ADDRBWRADDRU4.BRAM_IMUX_ADDRBWRADDRU4 origin:060-bram-cascades !26_109 !26_110 !26_111 +BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_CASCINBOT_ADDRBWRADDRU5 origin:060-bram-cascades !26_238 26_237 26_239 +BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_CASCINTOP_ADDRBWRADDRU5 origin:060-bram-cascades !26_237 26_238 26_239 +BRAM_L.BRAM_ADDRBWRADDRU5.BRAM_IMUX_ADDRBWRADDRU5 origin:060-bram-cascades !26_237 !26_238 !26_239 +BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_CASCINBOT_ADDRBWRADDRU6 origin:060-bram-cascades !26_174 26_173 26_175 +BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_CASCINTOP_ADDRBWRADDRU6 origin:060-bram-cascades !26_173 26_174 26_175 +BRAM_L.BRAM_ADDRBWRADDRU6.BRAM_IMUX_ADDRBWRADDRU6 origin:060-bram-cascades !26_173 !26_174 !26_175 +BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_CASCINBOT_ADDRBWRADDRU7 origin:060-bram-cascades !26_190 26_189 26_191 +BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_CASCINTOP_ADDRBWRADDRU7 origin:060-bram-cascades !26_189 26_190 26_191 +BRAM_L.BRAM_ADDRBWRADDRU7.BRAM_IMUX_ADDRBWRADDRU7 origin:060-bram-cascades !26_189 !26_190 !26_191 +BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_CASCINBOT_ADDRBWRADDRU8 origin:060-bram-cascades !26_94 26_93 26_95 +BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_CASCINTOP_ADDRBWRADDRU8 origin:060-bram-cascades !26_93 26_94 26_95 +BRAM_L.BRAM_ADDRBWRADDRU8.BRAM_IMUX_ADDRBWRADDRU8 origin:060-bram-cascades !26_93 !26_94 !26_95 +BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_222 26_221 26_223 +BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 26_222 26_223 +BRAM_L.BRAM_ADDRBWRADDRU9.BRAM_IMUX_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 !26_222 !26_223 +BRAM_L.CASCOUT_ARD_ACTIVE origin:060-bram-cascades 26_170 +BRAM_L.CASCOUT_BWR_ACTIVE origin:060-bram-cascades 26_172 +BRAM_L.EN_SYN origin:028-fifo-config 27_171 +BRAM_L.FIRST_WORD_FALL_THROUGH origin:028-fifo-config 27_170 +BRAM_L.RAMB18_Y0.DOA_REG origin:025-bram-config 27_69 +BRAM_L.RAMB18_Y0.DOB_REG origin:025-bram-config 27_72 +BRAM_L.RAMB18_Y0.FIFO_MODE origin:029-bram-fifo-config 27_150 +BRAM_L.RAMB18_Y0.IN_USE origin:029-bram-fifo-config 27_100 27_99 +BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_96 +BRAM_L.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_96 +BRAM_L.RAMB18_Y0.READ_WIDTH_A_1 origin:025-bram-config !27_35 !27_36 !27_37 +BRAM_L.RAMB18_Y0.READ_WIDTH_A_18 origin:025-bram-config !27_35 !27_36 27_37 +BRAM_L.RAMB18_Y0.READ_WIDTH_A_2 origin:025-bram-config !27_36 !27_37 27_35 +BRAM_L.RAMB18_Y0.READ_WIDTH_A_4 origin:025-bram-config !27_35 !27_37 27_36 +BRAM_L.RAMB18_Y0.READ_WIDTH_A_9 origin:025-bram-config !27_37 27_35 27_36 +BRAM_L.RAMB18_Y0.READ_WIDTH_B_1 origin:025-bram-config !27_43 !27_44 !27_45 +BRAM_L.RAMB18_Y0.READ_WIDTH_B_18 origin:025-bram-config !27_43 !27_44 27_45 +BRAM_L.RAMB18_Y0.READ_WIDTH_B_2 origin:025-bram-config !27_44 !27_45 27_43 +BRAM_L.RAMB18_Y0.READ_WIDTH_B_4 origin:025-bram-config !27_43 !27_45 27_44 +BRAM_L.RAMB18_Y0.READ_WIDTH_B_9 origin:025-bram-config !27_45 27_43 27_44 +BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_124 +BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_124 +BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_125 +BRAM_L.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG origin:025-bram-config !27_125 +BRAM_L.RAMB18_Y0.SDP_READ_WIDTH_36 origin:025-bram-config 27_48 +BRAM_L.RAMB18_Y0.SDP_WRITE_WIDTH_36 origin:025-bram-config 27_40 +BRAM_L.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_64 +BRAM_L.RAMB18_Y0.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_56 +BRAM_L.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_68 +BRAM_L.RAMB18_Y0.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_67 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_1 origin:025-bram-config !27_51 !27_52 !27_53 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_18 origin:025-bram-config !27_51 !27_52 27_53 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_2 origin:025-bram-config !27_52 !27_53 27_51 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_4 origin:025-bram-config !27_51 !27_53 27_52 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_A_9 origin:025-bram-config !27_53 27_51 27_52 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_1 origin:025-bram-config !27_59 !27_60 !27_61 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_18 origin:025-bram-config !27_59 !27_60 27_61 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_2 origin:025-bram-config !27_60 !27_61 27_59 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_4 origin:025-bram-config !27_59 !27_61 27_60 +BRAM_L.RAMB18_Y0.WRITE_WIDTH_B_9 origin:025-bram-config !27_61 27_59 27_60 +BRAM_L.RAMB18_Y0.ZINIT_A[0] origin:025-bram-config 27_73 +BRAM_L.RAMB18_Y0.ZINIT_A[10] origin:025-bram-config 27_129 +BRAM_L.RAMB18_Y0.ZINIT_A[11] origin:025-bram-config 27_113 +BRAM_L.RAMB18_Y0.ZINIT_A[12] origin:025-bram-config 27_97 +BRAM_L.RAMB18_Y0.ZINIT_A[13] origin:025-bram-config 27_81 +BRAM_L.RAMB18_Y0.ZINIT_A[14] origin:025-bram-config 27_49 +BRAM_L.RAMB18_Y0.ZINIT_A[15] origin:025-bram-config 27_33 +BRAM_L.RAMB18_Y0.ZINIT_A[16] origin:025-bram-config 27_17 +BRAM_L.RAMB18_Y0.ZINIT_A[17] origin:025-bram-config 27_01 +BRAM_L.RAMB18_Y0.ZINIT_A[1] origin:025-bram-config 27_65 +BRAM_L.RAMB18_Y0.ZINIT_A[2] origin:025-bram-config 27_137 +BRAM_L.RAMB18_Y0.ZINIT_A[3] origin:025-bram-config 27_121 +BRAM_L.RAMB18_Y0.ZINIT_A[4] origin:025-bram-config 27_105 +BRAM_L.RAMB18_Y0.ZINIT_A[5] origin:025-bram-config 27_89 +BRAM_L.RAMB18_Y0.ZINIT_A[6] origin:025-bram-config 27_57 +BRAM_L.RAMB18_Y0.ZINIT_A[7] origin:025-bram-config 27_41 +BRAM_L.RAMB18_Y0.ZINIT_A[8] origin:025-bram-config 27_25 +BRAM_L.RAMB18_Y0.ZINIT_A[9] origin:025-bram-config 27_09 +BRAM_L.RAMB18_Y0.ZINIT_B[0] origin:025-bram-config 27_79 +BRAM_L.RAMB18_Y0.ZINIT_B[10] origin:025-bram-config 27_135 +BRAM_L.RAMB18_Y0.ZINIT_B[11] origin:025-bram-config 27_119 +BRAM_L.RAMB18_Y0.ZINIT_B[12] origin:025-bram-config 27_103 +BRAM_L.RAMB18_Y0.ZINIT_B[13] origin:025-bram-config 27_87 +BRAM_L.RAMB18_Y0.ZINIT_B[14] origin:025-bram-config 27_55 +BRAM_L.RAMB18_Y0.ZINIT_B[15] origin:025-bram-config 27_39 +BRAM_L.RAMB18_Y0.ZINIT_B[16] origin:025-bram-config 27_23 +BRAM_L.RAMB18_Y0.ZINIT_B[17] origin:025-bram-config 27_07 +BRAM_L.RAMB18_Y0.ZINIT_B[1] origin:025-bram-config 27_71 +BRAM_L.RAMB18_Y0.ZINIT_B[2] origin:025-bram-config 27_143 +BRAM_L.RAMB18_Y0.ZINIT_B[3] origin:025-bram-config 27_127 +BRAM_L.RAMB18_Y0.ZINIT_B[4] origin:025-bram-config 27_111 +BRAM_L.RAMB18_Y0.ZINIT_B[5] origin:025-bram-config 27_95 +BRAM_L.RAMB18_Y0.ZINIT_B[6] origin:025-bram-config 27_63 +BRAM_L.RAMB18_Y0.ZINIT_B[7] origin:025-bram-config 27_47 +BRAM_L.RAMB18_Y0.ZINIT_B[8] origin:025-bram-config 27_31 +BRAM_L.RAMB18_Y0.ZINIT_B[9] origin:025-bram-config 27_15 +BRAM_L.RAMB18_Y0.ZINV_CLKARDCLK origin:025-bram-config 27_107 +BRAM_L.RAMB18_Y0.ZINV_CLKBWRCLK origin:025-bram-config 27_109 +BRAM_L.RAMB18_Y0.ZINV_ENARDEN origin:025-bram-config 27_112 +BRAM_L.RAMB18_Y0.ZINV_ENBWREN origin:025-bram-config 27_115 +BRAM_L.RAMB18_Y0.ZINV_REGCLKARDRCLK origin:025-bram-config 27_104 +BRAM_L.RAMB18_Y0.ZINV_REGCLKB origin:025-bram-config 27_108 +BRAM_L.RAMB18_Y0.ZINV_RSTRAMARSTRAM origin:025-bram-config 27_116 +BRAM_L.RAMB18_Y0.ZINV_RSTRAMB origin:025-bram-config 27_117 +BRAM_L.RAMB18_Y0.ZINV_RSTREGARSTREG origin:025-bram-config 27_120 +BRAM_L.RAMB18_Y0.ZINV_RSTREGB origin:025-bram-config 27_123 +BRAM_L.RAMB18_Y0.ZSRVAL_A[0] origin:025-bram-config 27_74 +BRAM_L.RAMB18_Y0.ZSRVAL_A[10] origin:025-bram-config 27_130 +BRAM_L.RAMB18_Y0.ZSRVAL_A[11] origin:025-bram-config 27_114 +BRAM_L.RAMB18_Y0.ZSRVAL_A[12] origin:025-bram-config 27_98 +BRAM_L.RAMB18_Y0.ZSRVAL_A[13] origin:025-bram-config 27_82 +BRAM_L.RAMB18_Y0.ZSRVAL_A[14] origin:025-bram-config 27_50 +BRAM_L.RAMB18_Y0.ZSRVAL_A[15] origin:025-bram-config 27_34 +BRAM_L.RAMB18_Y0.ZSRVAL_A[16] origin:025-bram-config 27_18 +BRAM_L.RAMB18_Y0.ZSRVAL_A[17] origin:025-bram-config 27_02 +BRAM_L.RAMB18_Y0.ZSRVAL_A[1] origin:025-bram-config 27_66 +BRAM_L.RAMB18_Y0.ZSRVAL_A[2] origin:025-bram-config 27_138 +BRAM_L.RAMB18_Y0.ZSRVAL_A[3] origin:025-bram-config 27_122 +BRAM_L.RAMB18_Y0.ZSRVAL_A[4] origin:025-bram-config 27_106 +BRAM_L.RAMB18_Y0.ZSRVAL_A[5] origin:025-bram-config 27_90 +BRAM_L.RAMB18_Y0.ZSRVAL_A[6] origin:025-bram-config 27_58 +BRAM_L.RAMB18_Y0.ZSRVAL_A[7] origin:025-bram-config 27_42 +BRAM_L.RAMB18_Y0.ZSRVAL_A[8] origin:025-bram-config 27_26 +BRAM_L.RAMB18_Y0.ZSRVAL_A[9] origin:025-bram-config 27_10 +BRAM_L.RAMB18_Y0.ZSRVAL_B[0] origin:025-bram-config 27_78 +BRAM_L.RAMB18_Y0.ZSRVAL_B[10] origin:025-bram-config 27_134 +BRAM_L.RAMB18_Y0.ZSRVAL_B[11] origin:025-bram-config 27_118 +BRAM_L.RAMB18_Y0.ZSRVAL_B[12] origin:025-bram-config 27_102 +BRAM_L.RAMB18_Y0.ZSRVAL_B[13] origin:025-bram-config 27_86 +BRAM_L.RAMB18_Y0.ZSRVAL_B[14] origin:025-bram-config 27_54 +BRAM_L.RAMB18_Y0.ZSRVAL_B[15] origin:025-bram-config 27_38 +BRAM_L.RAMB18_Y0.ZSRVAL_B[16] origin:025-bram-config 27_22 +BRAM_L.RAMB18_Y0.ZSRVAL_B[17] origin:025-bram-config 27_06 +BRAM_L.RAMB18_Y0.ZSRVAL_B[1] origin:025-bram-config 27_70 +BRAM_L.RAMB18_Y0.ZSRVAL_B[2] origin:025-bram-config 27_142 +BRAM_L.RAMB18_Y0.ZSRVAL_B[3] origin:025-bram-config 27_126 +BRAM_L.RAMB18_Y0.ZSRVAL_B[4] origin:025-bram-config 27_110 +BRAM_L.RAMB18_Y0.ZSRVAL_B[5] origin:025-bram-config 27_94 +BRAM_L.RAMB18_Y0.ZSRVAL_B[6] origin:025-bram-config 27_62 +BRAM_L.RAMB18_Y0.ZSRVAL_B[7] origin:025-bram-config 27_46 +BRAM_L.RAMB18_Y0.ZSRVAL_B[8] origin:025-bram-config 27_30 +BRAM_L.RAMB18_Y0.ZSRVAL_B[9] origin:025-bram-config 27_14 +BRAM_L.RAMB18_Y1.DOA_REG origin:025-bram-config 27_251 +BRAM_L.RAMB18_Y1.DOB_REG origin:025-bram-config 27_248 +BRAM_L.RAMB18_Y1.FIFO_MODE origin:029-bram-fifo-config 27_169 +BRAM_L.RAMB18_Y1.IN_USE origin:029-bram-fifo-config 27_220 27_221 +BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_224 +BRAM_L.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_224 +BRAM_L.RAMB18_Y1.READ_WIDTH_A_1 origin:025-bram-config !27_283 !27_284 !27_285 +BRAM_L.RAMB18_Y1.READ_WIDTH_A_18 origin:025-bram-config !27_284 !27_285 27_283 +BRAM_L.RAMB18_Y1.READ_WIDTH_A_2 origin:025-bram-config !27_283 !27_284 27_285 +BRAM_L.RAMB18_Y1.READ_WIDTH_A_4 origin:025-bram-config !27_283 !27_285 27_284 +BRAM_L.RAMB18_Y1.READ_WIDTH_A_9 origin:025-bram-config !27_283 27_284 27_285 +BRAM_L.RAMB18_Y1.READ_WIDTH_B_1 origin:025-bram-config !27_275 !27_276 !27_277 +BRAM_L.RAMB18_Y1.READ_WIDTH_B_18 origin:025-bram-config !27_276 !27_277 27_275 +BRAM_L.RAMB18_Y1.READ_WIDTH_B_2 origin:025-bram-config !27_275 !27_276 27_277 +BRAM_L.RAMB18_Y1.READ_WIDTH_B_4 origin:025-bram-config !27_275 !27_277 27_276 +BRAM_L.RAMB18_Y1.READ_WIDTH_B_9 origin:025-bram-config !27_275 27_276 27_277 +BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_196 +BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_196 +BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_195 +BRAM_L.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG origin:025-bram-config !27_195 +BRAM_L.RAMB18_Y1.SDP_READ_WIDTH_36 origin:025-bram-config 27_272 +BRAM_L.RAMB18_Y1.SDP_WRITE_WIDTH_36 origin:025-bram-config 27_280 +BRAM_L.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_256 +BRAM_L.RAMB18_Y1.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_264 +BRAM_L.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_252 +BRAM_L.RAMB18_Y1.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_253 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_1 origin:025-bram-config !27_267 !27_268 !27_269 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_18 origin:025-bram-config !27_268 !27_269 27_267 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_2 origin:025-bram-config !27_267 !27_268 27_269 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_4 origin:025-bram-config !27_267 !27_269 27_268 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_A_9 origin:025-bram-config !27_267 27_268 27_269 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_1 origin:025-bram-config !27_259 !27_260 !27_261 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_18 origin:025-bram-config !27_260 !27_261 27_259 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_2 origin:025-bram-config !27_259 !27_260 27_261 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_4 origin:025-bram-config !27_259 !27_261 27_260 +BRAM_L.RAMB18_Y1.WRITE_WIDTH_B_9 origin:025-bram-config !27_259 27_260 27_261 +BRAM_L.RAMB18_Y1.ZINIT_A[0] origin:025-bram-config 27_249 +BRAM_L.RAMB18_Y1.ZINIT_A[10] origin:025-bram-config 27_305 +BRAM_L.RAMB18_Y1.ZINIT_A[11] origin:025-bram-config 27_289 +BRAM_L.RAMB18_Y1.ZINIT_A[12] origin:025-bram-config 27_273 +BRAM_L.RAMB18_Y1.ZINIT_A[13] origin:025-bram-config 27_257 +BRAM_L.RAMB18_Y1.ZINIT_A[14] origin:025-bram-config 27_225 +BRAM_L.RAMB18_Y1.ZINIT_A[15] origin:025-bram-config 27_209 +BRAM_L.RAMB18_Y1.ZINIT_A[16] origin:025-bram-config 27_193 +BRAM_L.RAMB18_Y1.ZINIT_A[17] origin:025-bram-config 27_177 +BRAM_L.RAMB18_Y1.ZINIT_A[1] origin:025-bram-config 27_241 +BRAM_L.RAMB18_Y1.ZINIT_A[2] origin:025-bram-config 27_313 +BRAM_L.RAMB18_Y1.ZINIT_A[3] origin:025-bram-config 27_297 +BRAM_L.RAMB18_Y1.ZINIT_A[4] origin:025-bram-config 27_281 +BRAM_L.RAMB18_Y1.ZINIT_A[5] origin:025-bram-config 27_265 +BRAM_L.RAMB18_Y1.ZINIT_A[6] origin:025-bram-config 27_233 +BRAM_L.RAMB18_Y1.ZINIT_A[7] origin:025-bram-config 27_217 +BRAM_L.RAMB18_Y1.ZINIT_A[8] origin:025-bram-config 27_201 +BRAM_L.RAMB18_Y1.ZINIT_A[9] origin:025-bram-config 27_185 +BRAM_L.RAMB18_Y1.ZINIT_B[0] origin:025-bram-config 27_255 +BRAM_L.RAMB18_Y1.ZINIT_B[10] origin:025-bram-config 27_311 +BRAM_L.RAMB18_Y1.ZINIT_B[11] origin:025-bram-config 27_295 +BRAM_L.RAMB18_Y1.ZINIT_B[12] origin:025-bram-config 27_279 +BRAM_L.RAMB18_Y1.ZINIT_B[13] origin:025-bram-config 27_263 +BRAM_L.RAMB18_Y1.ZINIT_B[14] origin:025-bram-config 27_231 +BRAM_L.RAMB18_Y1.ZINIT_B[15] origin:025-bram-config 27_215 +BRAM_L.RAMB18_Y1.ZINIT_B[16] origin:025-bram-config 27_199 +BRAM_L.RAMB18_Y1.ZINIT_B[17] origin:025-bram-config 27_183 +BRAM_L.RAMB18_Y1.ZINIT_B[1] origin:025-bram-config 27_247 +BRAM_L.RAMB18_Y1.ZINIT_B[2] origin:025-bram-config 27_319 +BRAM_L.RAMB18_Y1.ZINIT_B[3] origin:025-bram-config 27_303 +BRAM_L.RAMB18_Y1.ZINIT_B[4] origin:025-bram-config 27_287 +BRAM_L.RAMB18_Y1.ZINIT_B[5] origin:025-bram-config 27_271 +BRAM_L.RAMB18_Y1.ZINIT_B[6] origin:025-bram-config 27_239 +BRAM_L.RAMB18_Y1.ZINIT_B[7] origin:025-bram-config 27_223 +BRAM_L.RAMB18_Y1.ZINIT_B[8] origin:025-bram-config 27_207 +BRAM_L.RAMB18_Y1.ZINIT_B[9] origin:025-bram-config 27_191 +BRAM_L.RAMB18_Y1.ZINV_CLKARDCLK origin:025-bram-config 27_213 +BRAM_L.RAMB18_Y1.ZINV_CLKBWRCLK origin:025-bram-config 27_211 +BRAM_L.RAMB18_Y1.ZINV_ENARDEN origin:025-bram-config 27_208 +BRAM_L.RAMB18_Y1.ZINV_ENBWREN origin:025-bram-config 27_205 +BRAM_L.RAMB18_Y1.ZINV_REGCLKARDRCLK origin:025-bram-config 27_216 +BRAM_L.RAMB18_Y1.ZINV_REGCLKB origin:025-bram-config 27_212 +BRAM_L.RAMB18_Y1.ZINV_RSTRAMARSTRAM origin:025-bram-config 27_204 +BRAM_L.RAMB18_Y1.ZINV_RSTRAMB origin:025-bram-config 27_203 +BRAM_L.RAMB18_Y1.ZINV_RSTREGARSTREG origin:025-bram-config 27_200 +BRAM_L.RAMB18_Y1.ZINV_RSTREGB origin:025-bram-config 27_197 +BRAM_L.RAMB18_Y1.ZSRVAL_A[0] origin:025-bram-config 27_250 +BRAM_L.RAMB18_Y1.ZSRVAL_A[10] origin:025-bram-config 27_306 +BRAM_L.RAMB18_Y1.ZSRVAL_A[11] origin:025-bram-config 27_290 +BRAM_L.RAMB18_Y1.ZSRVAL_A[12] origin:025-bram-config 27_274 +BRAM_L.RAMB18_Y1.ZSRVAL_A[13] origin:025-bram-config 27_258 +BRAM_L.RAMB18_Y1.ZSRVAL_A[14] origin:025-bram-config 27_226 +BRAM_L.RAMB18_Y1.ZSRVAL_A[15] origin:025-bram-config 27_210 +BRAM_L.RAMB18_Y1.ZSRVAL_A[16] origin:025-bram-config 27_194 +BRAM_L.RAMB18_Y1.ZSRVAL_A[17] origin:025-bram-config 27_178 +BRAM_L.RAMB18_Y1.ZSRVAL_A[1] origin:025-bram-config 27_242 +BRAM_L.RAMB18_Y1.ZSRVAL_A[2] origin:025-bram-config 27_314 +BRAM_L.RAMB18_Y1.ZSRVAL_A[3] origin:025-bram-config 27_298 +BRAM_L.RAMB18_Y1.ZSRVAL_A[4] origin:025-bram-config 27_282 +BRAM_L.RAMB18_Y1.ZSRVAL_A[5] origin:025-bram-config 27_266 +BRAM_L.RAMB18_Y1.ZSRVAL_A[6] origin:025-bram-config 27_234 +BRAM_L.RAMB18_Y1.ZSRVAL_A[7] origin:025-bram-config 27_218 +BRAM_L.RAMB18_Y1.ZSRVAL_A[8] origin:025-bram-config 27_202 +BRAM_L.RAMB18_Y1.ZSRVAL_A[9] origin:025-bram-config 27_186 +BRAM_L.RAMB18_Y1.ZSRVAL_B[0] origin:025-bram-config 27_254 +BRAM_L.RAMB18_Y1.ZSRVAL_B[10] origin:025-bram-config 27_310 +BRAM_L.RAMB18_Y1.ZSRVAL_B[11] origin:025-bram-config 27_294 +BRAM_L.RAMB18_Y1.ZSRVAL_B[12] origin:025-bram-config 27_278 +BRAM_L.RAMB18_Y1.ZSRVAL_B[13] origin:025-bram-config 27_262 +BRAM_L.RAMB18_Y1.ZSRVAL_B[14] origin:025-bram-config 27_230 +BRAM_L.RAMB18_Y1.ZSRVAL_B[15] origin:025-bram-config 27_214 +BRAM_L.RAMB18_Y1.ZSRVAL_B[16] origin:025-bram-config 27_198 +BRAM_L.RAMB18_Y1.ZSRVAL_B[17] origin:025-bram-config 27_182 +BRAM_L.RAMB18_Y1.ZSRVAL_B[1] origin:025-bram-config 27_246 +BRAM_L.RAMB18_Y1.ZSRVAL_B[2] origin:025-bram-config 27_318 +BRAM_L.RAMB18_Y1.ZSRVAL_B[3] origin:025-bram-config 27_302 +BRAM_L.RAMB18_Y1.ZSRVAL_B[4] origin:025-bram-config 27_286 +BRAM_L.RAMB18_Y1.ZSRVAL_B[5] origin:025-bram-config 27_270 +BRAM_L.RAMB18_Y1.ZSRVAL_B[6] origin:025-bram-config 27_238 +BRAM_L.RAMB18_Y1.ZSRVAL_B[7] origin:025-bram-config 27_222 +BRAM_L.RAMB18_Y1.ZSRVAL_B[8] origin:025-bram-config 27_206 +BRAM_L.RAMB18_Y1.ZSRVAL_B[9] origin:025-bram-config 27_190 +BRAM_L.RAMB36.EN_ECC_READ origin:027-bram36-config 27_175 +BRAM_L.RAMB36.EN_ECC_WRITE origin:027-bram36-config 27_162 +BRAM_L.RAMB36.RAM_EXTENSION_A_LOWER origin:027-bram36-config 27_188 +BRAM_L.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER origin:027-bram36-config !27_188 +BRAM_L.RAMB36.RAM_EXTENSION_B_LOWER origin:027-bram36-config 27_187 +BRAM_L.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER origin:027-bram36-config !27_187 +BRAM_L.ZALMOST_EMPTY_OFFSET[0] origin:028-fifo-config 27_288 +BRAM_L.ZALMOST_EMPTY_OFFSET[10] origin:028-fifo-config 27_308 +BRAM_L.ZALMOST_EMPTY_OFFSET[11] origin:028-fifo-config 27_309 +BRAM_L.ZALMOST_EMPTY_OFFSET[12] origin:028-fifo-config 27_312 +BRAM_L.ZALMOST_EMPTY_OFFSET[1] origin:028-fifo-config 27_291 +BRAM_L.ZALMOST_EMPTY_OFFSET[2] origin:028-fifo-config 27_292 +BRAM_L.ZALMOST_EMPTY_OFFSET[3] origin:028-fifo-config 27_293 +BRAM_L.ZALMOST_EMPTY_OFFSET[4] origin:028-fifo-config 27_296 +BRAM_L.ZALMOST_EMPTY_OFFSET[5] origin:028-fifo-config 27_299 +BRAM_L.ZALMOST_EMPTY_OFFSET[6] origin:028-fifo-config 27_300 +BRAM_L.ZALMOST_EMPTY_OFFSET[7] origin:028-fifo-config 27_301 +BRAM_L.ZALMOST_EMPTY_OFFSET[8] origin:028-fifo-config 27_304 +BRAM_L.ZALMOST_EMPTY_OFFSET[9] origin:028-fifo-config 27_307 +BRAM_L.ZALMOST_FULL_OFFSET[0] origin:028-fifo-config 27_32 +BRAM_L.ZALMOST_FULL_OFFSET[10] origin:028-fifo-config 27_12 +BRAM_L.ZALMOST_FULL_OFFSET[11] origin:028-fifo-config 27_11 +BRAM_L.ZALMOST_FULL_OFFSET[12] origin:028-fifo-config 27_08 +BRAM_L.ZALMOST_FULL_OFFSET[1] origin:028-fifo-config 27_29 +BRAM_L.ZALMOST_FULL_OFFSET[2] origin:028-fifo-config 27_28 +BRAM_L.ZALMOST_FULL_OFFSET[3] origin:028-fifo-config 27_27 +BRAM_L.ZALMOST_FULL_OFFSET[4] origin:028-fifo-config 27_24 +BRAM_L.ZALMOST_FULL_OFFSET[5] origin:028-fifo-config 27_21 +BRAM_L.ZALMOST_FULL_OFFSET[6] origin:028-fifo-config 27_20 +BRAM_L.ZALMOST_FULL_OFFSET[7] origin:028-fifo-config 27_19 +BRAM_L.ZALMOST_FULL_OFFSET[8] origin:028-fifo-config 27_16 +BRAM_L.ZALMOST_FULL_OFFSET[9] origin:028-fifo-config 27_13 diff --git a/zynq7/segbits_bram_r.block_ram.origin_info.db b/zynq7/segbits_bram_r.block_ram.origin_info.db new file mode 100644 index 0000000..f1fbad9 --- /dev/null +++ b/zynq7/segbits_bram_r.block_ram.origin_info.db @@ -0,0 +1,36864 @@ +BRAM_R.RAMB18_Y0.INITP_00[000] origin:026-bram-data 00_64 +BRAM_R.RAMB18_Y0.INITP_00[001] origin:026-bram-data 00_72 +BRAM_R.RAMB18_Y0.INITP_00[002] origin:026-bram-data 00_68 +BRAM_R.RAMB18_Y0.INITP_00[003] origin:026-bram-data 00_76 +BRAM_R.RAMB18_Y0.INITP_00[004] origin:026-bram-data 00_65 +BRAM_R.RAMB18_Y0.INITP_00[005] origin:026-bram-data 00_73 +BRAM_R.RAMB18_Y0.INITP_00[006] origin:026-bram-data 00_69 +BRAM_R.RAMB18_Y0.INITP_00[007] origin:026-bram-data 00_77 +BRAM_R.RAMB18_Y0.INITP_00[008] origin:026-bram-data 00_66 +BRAM_R.RAMB18_Y0.INITP_00[009] origin:026-bram-data 00_74 +BRAM_R.RAMB18_Y0.INITP_00[010] origin:026-bram-data 00_70 +BRAM_R.RAMB18_Y0.INITP_00[011] origin:026-bram-data 00_78 +BRAM_R.RAMB18_Y0.INITP_00[012] origin:026-bram-data 00_67 +BRAM_R.RAMB18_Y0.INITP_00[013] origin:026-bram-data 00_75 +BRAM_R.RAMB18_Y0.INITP_00[014] origin:026-bram-data 00_71 +BRAM_R.RAMB18_Y0.INITP_00[015] origin:026-bram-data 00_79 +BRAM_R.RAMB18_Y0.INITP_00[016] origin:026-bram-data 01_64 +BRAM_R.RAMB18_Y0.INITP_00[017] origin:026-bram-data 01_72 +BRAM_R.RAMB18_Y0.INITP_00[018] origin:026-bram-data 01_68 +BRAM_R.RAMB18_Y0.INITP_00[019] origin:026-bram-data 01_76 +BRAM_R.RAMB18_Y0.INITP_00[020] origin:026-bram-data 01_65 +BRAM_R.RAMB18_Y0.INITP_00[021] origin:026-bram-data 01_73 +BRAM_R.RAMB18_Y0.INITP_00[022] origin:026-bram-data 01_69 +BRAM_R.RAMB18_Y0.INITP_00[023] origin:026-bram-data 01_77 +BRAM_R.RAMB18_Y0.INITP_00[024] origin:026-bram-data 01_66 +BRAM_R.RAMB18_Y0.INITP_00[025] origin:026-bram-data 01_74 +BRAM_R.RAMB18_Y0.INITP_00[026] origin:026-bram-data 01_70 +BRAM_R.RAMB18_Y0.INITP_00[027] origin:026-bram-data 01_78 +BRAM_R.RAMB18_Y0.INITP_00[028] origin:026-bram-data 01_67 +BRAM_R.RAMB18_Y0.INITP_00[029] origin:026-bram-data 01_75 +BRAM_R.RAMB18_Y0.INITP_00[030] origin:026-bram-data 01_71 +BRAM_R.RAMB18_Y0.INITP_00[031] origin:026-bram-data 01_79 +BRAM_R.RAMB18_Y0.INITP_00[032] origin:026-bram-data 02_64 +BRAM_R.RAMB18_Y0.INITP_00[033] origin:026-bram-data 02_72 +BRAM_R.RAMB18_Y0.INITP_00[034] origin:026-bram-data 02_68 +BRAM_R.RAMB18_Y0.INITP_00[035] origin:026-bram-data 02_76 +BRAM_R.RAMB18_Y0.INITP_00[036] origin:026-bram-data 02_65 +BRAM_R.RAMB18_Y0.INITP_00[037] origin:026-bram-data 02_73 +BRAM_R.RAMB18_Y0.INITP_00[038] origin:026-bram-data 02_69 +BRAM_R.RAMB18_Y0.INITP_00[039] origin:026-bram-data 02_77 +BRAM_R.RAMB18_Y0.INITP_00[040] origin:026-bram-data 02_66 +BRAM_R.RAMB18_Y0.INITP_00[041] origin:026-bram-data 02_74 +BRAM_R.RAMB18_Y0.INITP_00[042] origin:026-bram-data 02_70 +BRAM_R.RAMB18_Y0.INITP_00[043] origin:026-bram-data 02_78 +BRAM_R.RAMB18_Y0.INITP_00[044] origin:026-bram-data 02_67 +BRAM_R.RAMB18_Y0.INITP_00[045] origin:026-bram-data 02_75 +BRAM_R.RAMB18_Y0.INITP_00[046] origin:026-bram-data 02_71 +BRAM_R.RAMB18_Y0.INITP_00[047] origin:026-bram-data 02_79 +BRAM_R.RAMB18_Y0.INITP_00[048] origin:026-bram-data 03_64 +BRAM_R.RAMB18_Y0.INITP_00[049] origin:026-bram-data 03_72 +BRAM_R.RAMB18_Y0.INITP_00[050] origin:026-bram-data 03_68 +BRAM_R.RAMB18_Y0.INITP_00[051] origin:026-bram-data 03_76 +BRAM_R.RAMB18_Y0.INITP_00[052] origin:026-bram-data 03_65 +BRAM_R.RAMB18_Y0.INITP_00[053] origin:026-bram-data 03_73 +BRAM_R.RAMB18_Y0.INITP_00[054] origin:026-bram-data 03_69 +BRAM_R.RAMB18_Y0.INITP_00[055] origin:026-bram-data 03_77 +BRAM_R.RAMB18_Y0.INITP_00[056] origin:026-bram-data 03_66 +BRAM_R.RAMB18_Y0.INITP_00[057] origin:026-bram-data 03_74 +BRAM_R.RAMB18_Y0.INITP_00[058] origin:026-bram-data 03_70 +BRAM_R.RAMB18_Y0.INITP_00[059] origin:026-bram-data 03_78 +BRAM_R.RAMB18_Y0.INITP_00[060] origin:026-bram-data 03_67 +BRAM_R.RAMB18_Y0.INITP_00[061] origin:026-bram-data 03_75 +BRAM_R.RAMB18_Y0.INITP_00[062] origin:026-bram-data 03_71 +BRAM_R.RAMB18_Y0.INITP_00[063] origin:026-bram-data 03_79 +BRAM_R.RAMB18_Y0.INITP_00[064] origin:026-bram-data 04_64 +BRAM_R.RAMB18_Y0.INITP_00[065] origin:026-bram-data 04_72 +BRAM_R.RAMB18_Y0.INITP_00[066] origin:026-bram-data 04_68 +BRAM_R.RAMB18_Y0.INITP_00[067] origin:026-bram-data 04_76 +BRAM_R.RAMB18_Y0.INITP_00[068] origin:026-bram-data 04_65 +BRAM_R.RAMB18_Y0.INITP_00[069] origin:026-bram-data 04_73 +BRAM_R.RAMB18_Y0.INITP_00[070] origin:026-bram-data 04_69 +BRAM_R.RAMB18_Y0.INITP_00[071] origin:026-bram-data 04_77 +BRAM_R.RAMB18_Y0.INITP_00[072] origin:026-bram-data 04_66 +BRAM_R.RAMB18_Y0.INITP_00[073] origin:026-bram-data 04_74 +BRAM_R.RAMB18_Y0.INITP_00[074] origin:026-bram-data 04_70 +BRAM_R.RAMB18_Y0.INITP_00[075] origin:026-bram-data 04_78 +BRAM_R.RAMB18_Y0.INITP_00[076] origin:026-bram-data 04_67 +BRAM_R.RAMB18_Y0.INITP_00[077] origin:026-bram-data 04_75 +BRAM_R.RAMB18_Y0.INITP_00[078] origin:026-bram-data 04_71 +BRAM_R.RAMB18_Y0.INITP_00[079] origin:026-bram-data 04_79 +BRAM_R.RAMB18_Y0.INITP_00[080] origin:026-bram-data 05_64 +BRAM_R.RAMB18_Y0.INITP_00[081] origin:026-bram-data 05_72 +BRAM_R.RAMB18_Y0.INITP_00[082] origin:026-bram-data 05_68 +BRAM_R.RAMB18_Y0.INITP_00[083] origin:026-bram-data 05_76 +BRAM_R.RAMB18_Y0.INITP_00[084] origin:026-bram-data 05_65 +BRAM_R.RAMB18_Y0.INITP_00[085] origin:026-bram-data 05_73 +BRAM_R.RAMB18_Y0.INITP_00[086] origin:026-bram-data 05_69 +BRAM_R.RAMB18_Y0.INITP_00[087] origin:026-bram-data 05_77 +BRAM_R.RAMB18_Y0.INITP_00[088] origin:026-bram-data 05_66 +BRAM_R.RAMB18_Y0.INITP_00[089] origin:026-bram-data 05_74 +BRAM_R.RAMB18_Y0.INITP_00[090] origin:026-bram-data 05_70 +BRAM_R.RAMB18_Y0.INITP_00[091] origin:026-bram-data 05_78 +BRAM_R.RAMB18_Y0.INITP_00[092] origin:026-bram-data 05_67 +BRAM_R.RAMB18_Y0.INITP_00[093] origin:026-bram-data 05_75 +BRAM_R.RAMB18_Y0.INITP_00[094] origin:026-bram-data 05_71 +BRAM_R.RAMB18_Y0.INITP_00[095] origin:026-bram-data 05_79 +BRAM_R.RAMB18_Y0.INITP_00[096] origin:026-bram-data 06_64 +BRAM_R.RAMB18_Y0.INITP_00[097] origin:026-bram-data 06_72 +BRAM_R.RAMB18_Y0.INITP_00[098] origin:026-bram-data 06_68 +BRAM_R.RAMB18_Y0.INITP_00[099] origin:026-bram-data 06_76 +BRAM_R.RAMB18_Y0.INITP_00[100] origin:026-bram-data 06_65 +BRAM_R.RAMB18_Y0.INITP_00[101] origin:026-bram-data 06_73 +BRAM_R.RAMB18_Y0.INITP_00[102] origin:026-bram-data 06_69 +BRAM_R.RAMB18_Y0.INITP_00[103] origin:026-bram-data 06_77 +BRAM_R.RAMB18_Y0.INITP_00[104] origin:026-bram-data 06_66 +BRAM_R.RAMB18_Y0.INITP_00[105] origin:026-bram-data 06_74 +BRAM_R.RAMB18_Y0.INITP_00[106] origin:026-bram-data 06_70 +BRAM_R.RAMB18_Y0.INITP_00[107] origin:026-bram-data 06_78 +BRAM_R.RAMB18_Y0.INITP_00[108] origin:026-bram-data 06_67 +BRAM_R.RAMB18_Y0.INITP_00[109] origin:026-bram-data 06_75 +BRAM_R.RAMB18_Y0.INITP_00[110] origin:026-bram-data 06_71 +BRAM_R.RAMB18_Y0.INITP_00[111] origin:026-bram-data 06_79 +BRAM_R.RAMB18_Y0.INITP_00[112] origin:026-bram-data 07_64 +BRAM_R.RAMB18_Y0.INITP_00[113] origin:026-bram-data 07_72 +BRAM_R.RAMB18_Y0.INITP_00[114] origin:026-bram-data 07_68 +BRAM_R.RAMB18_Y0.INITP_00[115] origin:026-bram-data 07_76 +BRAM_R.RAMB18_Y0.INITP_00[116] origin:026-bram-data 07_65 +BRAM_R.RAMB18_Y0.INITP_00[117] origin:026-bram-data 07_73 +BRAM_R.RAMB18_Y0.INITP_00[118] origin:026-bram-data 07_69 +BRAM_R.RAMB18_Y0.INITP_00[119] origin:026-bram-data 07_77 +BRAM_R.RAMB18_Y0.INITP_00[120] origin:026-bram-data 07_66 +BRAM_R.RAMB18_Y0.INITP_00[121] origin:026-bram-data 07_74 +BRAM_R.RAMB18_Y0.INITP_00[122] origin:026-bram-data 07_70 +BRAM_R.RAMB18_Y0.INITP_00[123] origin:026-bram-data 07_78 +BRAM_R.RAMB18_Y0.INITP_00[124] origin:026-bram-data 07_67 +BRAM_R.RAMB18_Y0.INITP_00[125] origin:026-bram-data 07_75 +BRAM_R.RAMB18_Y0.INITP_00[126] origin:026-bram-data 07_71 +BRAM_R.RAMB18_Y0.INITP_00[127] origin:026-bram-data 07_79 +BRAM_R.RAMB18_Y0.INITP_00[128] origin:026-bram-data 08_64 +BRAM_R.RAMB18_Y0.INITP_00[129] origin:026-bram-data 08_72 +BRAM_R.RAMB18_Y0.INITP_00[130] origin:026-bram-data 08_68 +BRAM_R.RAMB18_Y0.INITP_00[131] origin:026-bram-data 08_76 +BRAM_R.RAMB18_Y0.INITP_00[132] origin:026-bram-data 08_65 +BRAM_R.RAMB18_Y0.INITP_00[133] origin:026-bram-data 08_73 +BRAM_R.RAMB18_Y0.INITP_00[134] origin:026-bram-data 08_69 +BRAM_R.RAMB18_Y0.INITP_00[135] origin:026-bram-data 08_77 +BRAM_R.RAMB18_Y0.INITP_00[136] origin:026-bram-data 08_66 +BRAM_R.RAMB18_Y0.INITP_00[137] origin:026-bram-data 08_74 +BRAM_R.RAMB18_Y0.INITP_00[138] origin:026-bram-data 08_70 +BRAM_R.RAMB18_Y0.INITP_00[139] origin:026-bram-data 08_78 +BRAM_R.RAMB18_Y0.INITP_00[140] origin:026-bram-data 08_67 +BRAM_R.RAMB18_Y0.INITP_00[141] origin:026-bram-data 08_75 +BRAM_R.RAMB18_Y0.INITP_00[142] origin:026-bram-data 08_71 +BRAM_R.RAMB18_Y0.INITP_00[143] origin:026-bram-data 08_79 +BRAM_R.RAMB18_Y0.INITP_00[144] origin:026-bram-data 09_64 +BRAM_R.RAMB18_Y0.INITP_00[145] origin:026-bram-data 09_72 +BRAM_R.RAMB18_Y0.INITP_00[146] origin:026-bram-data 09_68 +BRAM_R.RAMB18_Y0.INITP_00[147] origin:026-bram-data 09_76 +BRAM_R.RAMB18_Y0.INITP_00[148] origin:026-bram-data 09_65 +BRAM_R.RAMB18_Y0.INITP_00[149] origin:026-bram-data 09_73 +BRAM_R.RAMB18_Y0.INITP_00[150] origin:026-bram-data 09_69 +BRAM_R.RAMB18_Y0.INITP_00[151] origin:026-bram-data 09_77 +BRAM_R.RAMB18_Y0.INITP_00[152] origin:026-bram-data 09_66 +BRAM_R.RAMB18_Y0.INITP_00[153] origin:026-bram-data 09_74 +BRAM_R.RAMB18_Y0.INITP_00[154] origin:026-bram-data 09_70 +BRAM_R.RAMB18_Y0.INITP_00[155] origin:026-bram-data 09_78 +BRAM_R.RAMB18_Y0.INITP_00[156] origin:026-bram-data 09_67 +BRAM_R.RAMB18_Y0.INITP_00[157] origin:026-bram-data 09_75 +BRAM_R.RAMB18_Y0.INITP_00[158] origin:026-bram-data 09_71 +BRAM_R.RAMB18_Y0.INITP_00[159] origin:026-bram-data 09_79 +BRAM_R.RAMB18_Y0.INITP_00[160] origin:026-bram-data 10_64 +BRAM_R.RAMB18_Y0.INITP_00[161] origin:026-bram-data 10_72 +BRAM_R.RAMB18_Y0.INITP_00[162] origin:026-bram-data 10_68 +BRAM_R.RAMB18_Y0.INITP_00[163] origin:026-bram-data 10_76 +BRAM_R.RAMB18_Y0.INITP_00[164] origin:026-bram-data 10_65 +BRAM_R.RAMB18_Y0.INITP_00[165] origin:026-bram-data 10_73 +BRAM_R.RAMB18_Y0.INITP_00[166] origin:026-bram-data 10_69 +BRAM_R.RAMB18_Y0.INITP_00[167] origin:026-bram-data 10_77 +BRAM_R.RAMB18_Y0.INITP_00[168] origin:026-bram-data 10_66 +BRAM_R.RAMB18_Y0.INITP_00[169] origin:026-bram-data 10_74 +BRAM_R.RAMB18_Y0.INITP_00[170] origin:026-bram-data 10_70 +BRAM_R.RAMB18_Y0.INITP_00[171] origin:026-bram-data 10_78 +BRAM_R.RAMB18_Y0.INITP_00[172] origin:026-bram-data 10_67 +BRAM_R.RAMB18_Y0.INITP_00[173] origin:026-bram-data 10_75 +BRAM_R.RAMB18_Y0.INITP_00[174] origin:026-bram-data 10_71 +BRAM_R.RAMB18_Y0.INITP_00[175] origin:026-bram-data 10_79 +BRAM_R.RAMB18_Y0.INITP_00[176] origin:026-bram-data 11_64 +BRAM_R.RAMB18_Y0.INITP_00[177] origin:026-bram-data 11_72 +BRAM_R.RAMB18_Y0.INITP_00[178] origin:026-bram-data 11_68 +BRAM_R.RAMB18_Y0.INITP_00[179] origin:026-bram-data 11_76 +BRAM_R.RAMB18_Y0.INITP_00[180] origin:026-bram-data 11_65 +BRAM_R.RAMB18_Y0.INITP_00[181] origin:026-bram-data 11_73 +BRAM_R.RAMB18_Y0.INITP_00[182] origin:026-bram-data 11_69 +BRAM_R.RAMB18_Y0.INITP_00[183] origin:026-bram-data 11_77 +BRAM_R.RAMB18_Y0.INITP_00[184] origin:026-bram-data 11_66 +BRAM_R.RAMB18_Y0.INITP_00[185] origin:026-bram-data 11_74 +BRAM_R.RAMB18_Y0.INITP_00[186] origin:026-bram-data 11_70 +BRAM_R.RAMB18_Y0.INITP_00[187] origin:026-bram-data 11_78 +BRAM_R.RAMB18_Y0.INITP_00[188] origin:026-bram-data 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origin:026-bram-data 127_199 +BRAM_R.RAMB18_Y1.INIT_3F[242] origin:026-bram-data 127_215 +BRAM_R.RAMB18_Y1.INIT_3F[243] origin:026-bram-data 127_231 +BRAM_R.RAMB18_Y1.INIT_3F[244] origin:026-bram-data 127_263 +BRAM_R.RAMB18_Y1.INIT_3F[245] origin:026-bram-data 127_279 +BRAM_R.RAMB18_Y1.INIT_3F[246] origin:026-bram-data 127_295 +BRAM_R.RAMB18_Y1.INIT_3F[247] origin:026-bram-data 127_311 +BRAM_R.RAMB18_Y1.INIT_3F[248] origin:026-bram-data 127_191 +BRAM_R.RAMB18_Y1.INIT_3F[249] origin:026-bram-data 127_207 +BRAM_R.RAMB18_Y1.INIT_3F[250] origin:026-bram-data 127_223 +BRAM_R.RAMB18_Y1.INIT_3F[251] origin:026-bram-data 127_239 +BRAM_R.RAMB18_Y1.INIT_3F[252] origin:026-bram-data 127_271 +BRAM_R.RAMB18_Y1.INIT_3F[253] origin:026-bram-data 127_287 +BRAM_R.RAMB18_Y1.INIT_3F[254] origin:026-bram-data 127_303 +BRAM_R.RAMB18_Y1.INIT_3F[255] origin:026-bram-data 127_319 diff --git a/zynq7/segbits_bram_r.origin_info.db b/zynq7/segbits_bram_r.origin_info.db new file mode 100644 index 0000000..fa01759 --- /dev/null +++ b/zynq7/segbits_bram_r.origin_info.db @@ -0,0 +1,452 @@ +BRAM_R.BRAM_ADDRARDADDRL0.BRAM_CASCINBOT_ADDRARDADDRU0 origin:060-bram-cascades !26_33 26_32 26_35 +BRAM_R.BRAM_ADDRARDADDRL0.BRAM_CASCINTOP_ADDRARDADDRU0 origin:060-bram-cascades !26_35 26_32 26_33 +BRAM_R.BRAM_ADDRARDADDRL0.BRAM_R_IMUX_ADDRARDADDRL0 origin:060-bram-cascades !26_32 !26_33 !26_35 +BRAM_R.BRAM_ADDRARDADDRL1.BRAM_CASCINBOT_ADDRARDADDRU1 origin:060-bram-cascades !26_49 26_48 26_51 +BRAM_R.BRAM_ADDRARDADDRL1.BRAM_CASCINTOP_ADDRARDADDRU1 origin:060-bram-cascades !26_51 26_48 26_49 +BRAM_R.BRAM_ADDRARDADDRL1.BRAM_R_IMUX_ADDRARDADDRL1 origin:060-bram-cascades !26_48 !26_49 !26_51 +BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINBOT_ADDRARDADDRU10 origin:060-bram-cascades !26_145 26_144 26_147 +BRAM_R.BRAM_ADDRARDADDRL10.BRAM_CASCINTOP_ADDRARDADDRU10 origin:060-bram-cascades !26_147 26_144 26_145 +BRAM_R.BRAM_ADDRARDADDRL10.BRAM_R_IMUX_ADDRARDADDRL10 origin:060-bram-cascades !26_144 !26_145 !26_147 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origin:060-bram-cascades !26_257 26_256 26_259 +BRAM_R.BRAM_ADDRARDADDRL14.BRAM_CASCINTOP_ADDRARDADDRU14 origin:060-bram-cascades !26_259 26_256 26_257 +BRAM_R.BRAM_ADDRARDADDRL14.BRAM_R_IMUX_ADDRARDADDRL14 origin:060-bram-cascades !26_256 !26_257 !26_259 +BRAM_R.BRAM_ADDRARDADDRL2.BRAM_CASCINBOT_ADDRARDADDRU2 origin:060-bram-cascades !26_65 26_64 26_67 +BRAM_R.BRAM_ADDRARDADDRL2.BRAM_CASCINTOP_ADDRARDADDRU2 origin:060-bram-cascades !26_67 26_64 26_65 +BRAM_R.BRAM_ADDRARDADDRL2.BRAM_R_IMUX_ADDRARDADDRL2 origin:060-bram-cascades !26_64 !26_65 !26_67 +BRAM_R.BRAM_ADDRARDADDRL3.BRAM_CASCINBOT_ADDRARDADDRU3 origin:060-bram-cascades !26_193 26_192 26_195 +BRAM_R.BRAM_ADDRARDADDRL3.BRAM_CASCINTOP_ADDRARDADDRU3 origin:060-bram-cascades !26_195 26_192 26_193 +BRAM_R.BRAM_ADDRARDADDRL3.BRAM_R_IMUX_ADDRARDADDRL3 origin:060-bram-cascades !26_192 !26_193 !26_195 +BRAM_R.BRAM_ADDRARDADDRL4.BRAM_CASCINBOT_ADDRARDADDRU4 origin:060-bram-cascades !26_97 26_96 26_99 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!26_179 26_176 26_177 +BRAM_R.BRAM_ADDRARDADDRL7.BRAM_R_IMUX_ADDRARDADDRL7 origin:060-bram-cascades !26_176 !26_177 !26_179 +BRAM_R.BRAM_ADDRARDADDRL8.BRAM_CASCINBOT_ADDRARDADDRU8 origin:060-bram-cascades !26_81 26_80 26_83 +BRAM_R.BRAM_ADDRARDADDRL8.BRAM_CASCINTOP_ADDRARDADDRU8 origin:060-bram-cascades !26_83 26_80 26_81 +BRAM_R.BRAM_ADDRARDADDRL8.BRAM_R_IMUX_ADDRARDADDRL8 origin:060-bram-cascades !26_80 !26_81 !26_83 +BRAM_R.BRAM_ADDRARDADDRL9.BRAM_CASCINBOT_ADDRARDADDRU9 origin:060-bram-cascades !26_209 26_208 26_211 +BRAM_R.BRAM_ADDRARDADDRL9.BRAM_CASCINTOP_ADDRARDADDRU9 origin:060-bram-cascades !26_211 26_208 26_209 +BRAM_R.BRAM_ADDRARDADDRL9.BRAM_R_IMUX_ADDRARDADDRL9 origin:060-bram-cascades !26_208 !26_209 !26_211 +BRAM_R.BRAM_ADDRARDADDRU0.BRAM_CASCINBOT_ADDRARDADDRU0 origin:060-bram-cascades !26_38 26_37 26_39 +BRAM_R.BRAM_ADDRARDADDRU0.BRAM_CASCINTOP_ADDRARDADDRU0 origin:060-bram-cascades !26_37 26_38 26_39 +BRAM_R.BRAM_ADDRARDADDRU0.BRAM_R_IMUX_ADDRARDADDRU0 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origin:060-bram-cascades !26_248 !26_249 !26_251 +BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_137 26_136 26_139 +BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_139 26_136 26_137 +BRAM_R.BRAM_ADDRBWRADDRL13.BRAM_R_IMUX_ADDRBWRADDRL13 origin:060-bram-cascades !26_136 !26_137 !26_139 +BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_265 26_264 26_267 +BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_267 26_264 26_265 +BRAM_R.BRAM_ADDRBWRADDRL14.BRAM_R_IMUX_ADDRBWRADDRL14 origin:060-bram-cascades !26_264 !26_265 !26_267 +BRAM_R.BRAM_ADDRBWRADDRL2.BRAM_CASCINBOT_ADDRBWRADDRU2 origin:060-bram-cascades !26_73 26_72 26_75 +BRAM_R.BRAM_ADDRBWRADDRL2.BRAM_CASCINTOP_ADDRBWRADDRU2 origin:060-bram-cascades !26_75 26_72 26_73 +BRAM_R.BRAM_ADDRBWRADDRL2.BRAM_R_IMUX_ADDRBWRADDRL2 origin:060-bram-cascades !26_72 !26_73 !26_75 +BRAM_R.BRAM_ADDRBWRADDRL3.BRAM_CASCINBOT_ADDRBWRADDRU3 origin:060-bram-cascades !26_201 26_200 26_203 +BRAM_R.BRAM_ADDRBWRADDRL3.BRAM_CASCINTOP_ADDRBWRADDRU3 origin:060-bram-cascades !26_203 26_200 26_201 +BRAM_R.BRAM_ADDRBWRADDRL3.BRAM_R_IMUX_ADDRBWRADDRL3 origin:060-bram-cascades !26_200 !26_201 !26_203 +BRAM_R.BRAM_ADDRBWRADDRL4.BRAM_CASCINBOT_ADDRBWRADDRU4 origin:060-bram-cascades !26_105 26_104 26_107 +BRAM_R.BRAM_ADDRBWRADDRL4.BRAM_CASCINTOP_ADDRBWRADDRU4 origin:060-bram-cascades !26_107 26_104 26_105 +BRAM_R.BRAM_ADDRBWRADDRL4.BRAM_R_IMUX_ADDRBWRADDRL4 origin:060-bram-cascades !26_104 !26_105 !26_107 +BRAM_R.BRAM_ADDRBWRADDRL5.BRAM_CASCINBOT_ADDRBWRADDRU5 origin:060-bram-cascades !26_233 26_232 26_235 +BRAM_R.BRAM_ADDRBWRADDRL5.BRAM_CASCINTOP_ADDRBWRADDRU5 origin:060-bram-cascades !26_235 26_232 26_233 +BRAM_R.BRAM_ADDRBWRADDRL5.BRAM_R_IMUX_ADDRBWRADDRL5 origin:060-bram-cascades !26_232 !26_233 !26_235 +BRAM_R.BRAM_ADDRBWRADDRL6.BRAM_CASCINBOT_ADDRBWRADDRU6 origin:060-bram-cascades !26_169 26_168 26_171 +BRAM_R.BRAM_ADDRBWRADDRL6.BRAM_CASCINTOP_ADDRBWRADDRU6 origin:060-bram-cascades !26_171 26_168 26_169 +BRAM_R.BRAM_ADDRBWRADDRL6.BRAM_R_IMUX_ADDRBWRADDRL6 origin:060-bram-cascades !26_168 !26_169 !26_171 +BRAM_R.BRAM_ADDRBWRADDRL7.BRAM_CASCINBOT_ADDRBWRADDRU7 origin:060-bram-cascades !26_185 26_184 26_187 +BRAM_R.BRAM_ADDRBWRADDRL7.BRAM_CASCINTOP_ADDRBWRADDRU7 origin:060-bram-cascades !26_187 26_184 26_185 +BRAM_R.BRAM_ADDRBWRADDRL7.BRAM_R_IMUX_ADDRBWRADDRL7 origin:060-bram-cascades !26_184 !26_185 !26_187 +BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_CASCINBOT_ADDRBWRADDRU8 origin:060-bram-cascades !26_89 26_88 26_91 +BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_CASCINTOP_ADDRBWRADDRU8 origin:060-bram-cascades !26_91 26_88 26_89 +BRAM_R.BRAM_ADDRBWRADDRL8.BRAM_R_IMUX_ADDRBWRADDRL8 origin:060-bram-cascades !26_88 !26_89 !26_91 +BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_217 26_216 26_219 +BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_219 26_216 26_217 +BRAM_R.BRAM_ADDRBWRADDRL9.BRAM_R_IMUX_ADDRBWRADDRL9 origin:060-bram-cascades !26_216 !26_217 !26_219 +BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_CASCINBOT_ADDRBWRADDRU0 origin:060-bram-cascades !26_46 26_45 26_47 +BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_CASCINTOP_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 26_46 26_47 +BRAM_R.BRAM_ADDRBWRADDRU0.BRAM_R_IMUX_ADDRBWRADDRU0 origin:060-bram-cascades !26_45 !26_46 !26_47 +BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_CASCINBOT_ADDRBWRADDRU1 origin:060-bram-cascades !26_62 26_61 26_63 +BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_CASCINTOP_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 26_62 26_63 +BRAM_R.BRAM_ADDRBWRADDRU1.BRAM_R_IMUX_ADDRBWRADDRU1 origin:060-bram-cascades !26_61 !26_62 !26_63 +BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINBOT_ADDRBWRADDRU10 origin:060-bram-cascades !26_158 26_157 26_159 +BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_CASCINTOP_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 26_158 26_159 +BRAM_R.BRAM_ADDRBWRADDRU10.BRAM_R_IMUX_ADDRBWRADDRU10 origin:060-bram-cascades !26_157 !26_158 !26_159 +BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINBOT_ADDRBWRADDRU11 origin:060-bram-cascades !26_126 26_125 26_127 +BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_CASCINTOP_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 26_126 26_127 +BRAM_R.BRAM_ADDRBWRADDRU11.BRAM_R_IMUX_ADDRBWRADDRU11 origin:060-bram-cascades !26_125 !26_126 !26_127 +BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINBOT_ADDRBWRADDRU12 origin:060-bram-cascades !26_254 26_253 26_255 +BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_CASCINTOP_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 26_254 26_255 +BRAM_R.BRAM_ADDRBWRADDRU12.BRAM_R_IMUX_ADDRBWRADDRU12 origin:060-bram-cascades !26_253 !26_254 !26_255 +BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINBOT_ADDRBWRADDRU13 origin:060-bram-cascades !26_142 26_141 26_143 +BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_CASCINTOP_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 26_142 26_143 +BRAM_R.BRAM_ADDRBWRADDRU13.BRAM_R_IMUX_ADDRBWRADDRU13 origin:060-bram-cascades !26_141 !26_142 !26_143 +BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINBOT_ADDRBWRADDRU14 origin:060-bram-cascades !26_270 26_269 26_271 +BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_CASCINTOP_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 26_270 26_271 +BRAM_R.BRAM_ADDRBWRADDRU14.BRAM_R_IMUX_ADDRBWRADDRU14 origin:060-bram-cascades !26_269 !26_270 !26_271 +BRAM_R.BRAM_ADDRBWRADDRU2.BRAM_CASCINBOT_ADDRBWRADDRU2 origin:060-bram-cascades !26_78 26_77 26_79 +BRAM_R.BRAM_ADDRBWRADDRU2.BRAM_CASCINTOP_ADDRBWRADDRU2 origin:060-bram-cascades !26_77 26_78 26_79 +BRAM_R.BRAM_ADDRBWRADDRU2.BRAM_R_IMUX_ADDRBWRADDRU2 origin:060-bram-cascades !26_77 !26_78 !26_79 +BRAM_R.BRAM_ADDRBWRADDRU3.BRAM_CASCINBOT_ADDRBWRADDRU3 origin:060-bram-cascades !26_206 26_205 26_207 +BRAM_R.BRAM_ADDRBWRADDRU3.BRAM_CASCINTOP_ADDRBWRADDRU3 origin:060-bram-cascades !26_205 26_206 26_207 +BRAM_R.BRAM_ADDRBWRADDRU3.BRAM_R_IMUX_ADDRBWRADDRU3 origin:060-bram-cascades !26_205 !26_206 !26_207 +BRAM_R.BRAM_ADDRBWRADDRU4.BRAM_CASCINBOT_ADDRBWRADDRU4 origin:060-bram-cascades !26_110 26_109 26_111 +BRAM_R.BRAM_ADDRBWRADDRU4.BRAM_CASCINTOP_ADDRBWRADDRU4 origin:060-bram-cascades !26_109 26_110 26_111 +BRAM_R.BRAM_ADDRBWRADDRU4.BRAM_R_IMUX_ADDRBWRADDRU4 origin:060-bram-cascades !26_109 !26_110 !26_111 +BRAM_R.BRAM_ADDRBWRADDRU5.BRAM_CASCINBOT_ADDRBWRADDRU5 origin:060-bram-cascades !26_238 26_237 26_239 +BRAM_R.BRAM_ADDRBWRADDRU5.BRAM_CASCINTOP_ADDRBWRADDRU5 origin:060-bram-cascades !26_237 26_238 26_239 +BRAM_R.BRAM_ADDRBWRADDRU5.BRAM_R_IMUX_ADDRBWRADDRU5 origin:060-bram-cascades !26_237 !26_238 !26_239 +BRAM_R.BRAM_ADDRBWRADDRU6.BRAM_CASCINBOT_ADDRBWRADDRU6 origin:060-bram-cascades !26_174 26_173 26_175 +BRAM_R.BRAM_ADDRBWRADDRU6.BRAM_CASCINTOP_ADDRBWRADDRU6 origin:060-bram-cascades !26_173 26_174 26_175 +BRAM_R.BRAM_ADDRBWRADDRU6.BRAM_R_IMUX_ADDRBWRADDRU6 origin:060-bram-cascades !26_173 !26_174 !26_175 +BRAM_R.BRAM_ADDRBWRADDRU7.BRAM_CASCINBOT_ADDRBWRADDRU7 origin:060-bram-cascades !26_190 26_189 26_191 +BRAM_R.BRAM_ADDRBWRADDRU7.BRAM_CASCINTOP_ADDRBWRADDRU7 origin:060-bram-cascades !26_189 26_190 26_191 +BRAM_R.BRAM_ADDRBWRADDRU7.BRAM_R_IMUX_ADDRBWRADDRU7 origin:060-bram-cascades !26_189 !26_190 !26_191 +BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_CASCINBOT_ADDRBWRADDRU8 origin:060-bram-cascades !26_94 26_93 26_95 +BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_CASCINTOP_ADDRBWRADDRU8 origin:060-bram-cascades !26_93 26_94 26_95 +BRAM_R.BRAM_ADDRBWRADDRU8.BRAM_R_IMUX_ADDRBWRADDRU8 origin:060-bram-cascades !26_93 !26_94 !26_95 +BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_CASCINBOT_ADDRBWRADDRU9 origin:060-bram-cascades !26_222 26_221 26_223 +BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_CASCINTOP_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 26_222 26_223 +BRAM_R.BRAM_ADDRBWRADDRU9.BRAM_R_IMUX_ADDRBWRADDRU9 origin:060-bram-cascades !26_221 !26_222 !26_223 +BRAM_R.CASCOUT_ARD_ACTIVE origin:060-bram-cascades 26_170 +BRAM_R.CASCOUT_BWR_ACTIVE origin:060-bram-cascades 26_172 +BRAM_R.EN_SYN origin:028-fifo-config 27_171 +BRAM_R.FIRST_WORD_FALL_THROUGH origin:028-fifo-config 27_170 +BRAM_R.RAMB18_Y0.DOA_REG origin:025-bram-config 27_69 +BRAM_R.RAMB18_Y0.DOB_REG origin:025-bram-config 27_72 +BRAM_R.RAMB18_Y0.FIFO_MODE origin:029-bram-fifo-config 27_150 +BRAM_R.RAMB18_Y0.IN_USE origin:029-bram-fifo-config 27_100 27_99 +BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_96 +BRAM_R.RAMB18_Y0.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_96 +BRAM_R.RAMB18_Y0.READ_WIDTH_A_1 origin:025-bram-config !27_35 !27_36 !27_37 +BRAM_R.RAMB18_Y0.READ_WIDTH_A_18 origin:025-bram-config !27_35 !27_36 27_37 +BRAM_R.RAMB18_Y0.READ_WIDTH_A_2 origin:025-bram-config !27_36 !27_37 27_35 +BRAM_R.RAMB18_Y0.READ_WIDTH_A_4 origin:025-bram-config !27_35 !27_37 27_36 +BRAM_R.RAMB18_Y0.READ_WIDTH_A_9 origin:025-bram-config !27_37 27_35 27_36 +BRAM_R.RAMB18_Y0.READ_WIDTH_B_1 origin:025-bram-config !27_43 !27_44 !27_45 +BRAM_R.RAMB18_Y0.READ_WIDTH_B_18 origin:025-bram-config !27_43 !27_44 27_45 +BRAM_R.RAMB18_Y0.READ_WIDTH_B_2 origin:025-bram-config !27_44 !27_45 27_43 +BRAM_R.RAMB18_Y0.READ_WIDTH_B_4 origin:025-bram-config !27_43 !27_45 27_44 +BRAM_R.RAMB18_Y0.READ_WIDTH_B_9 origin:025-bram-config !27_45 27_43 27_44 +BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_124 +BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_124 +BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_125 +BRAM_R.RAMB18_Y0.RSTREG_PRIORITY_B_RSTREG origin:025-bram-config !27_125 +BRAM_R.RAMB18_Y0.SDP_READ_WIDTH_36 origin:025-bram-config 27_48 +BRAM_R.RAMB18_Y0.SDP_WRITE_WIDTH_36 origin:025-bram-config 27_40 +BRAM_R.RAMB18_Y0.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_64 +BRAM_R.RAMB18_Y0.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_56 +BRAM_R.RAMB18_Y0.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_68 +BRAM_R.RAMB18_Y0.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_67 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_1 origin:025-bram-config !27_51 !27_52 !27_53 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_18 origin:025-bram-config !27_51 !27_52 27_53 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_2 origin:025-bram-config !27_52 !27_53 27_51 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_4 origin:025-bram-config !27_51 !27_53 27_52 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_A_9 origin:025-bram-config !27_53 27_51 27_52 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_1 origin:025-bram-config !27_59 !27_60 !27_61 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_18 origin:025-bram-config !27_59 !27_60 27_61 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_2 origin:025-bram-config !27_60 !27_61 27_59 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_4 origin:025-bram-config !27_59 !27_61 27_60 +BRAM_R.RAMB18_Y0.WRITE_WIDTH_B_9 origin:025-bram-config !27_61 27_59 27_60 +BRAM_R.RAMB18_Y0.ZINIT_A[0] origin:025-bram-config 27_73 +BRAM_R.RAMB18_Y0.ZINIT_A[10] origin:025-bram-config 27_129 +BRAM_R.RAMB18_Y0.ZINIT_A[11] origin:025-bram-config 27_113 +BRAM_R.RAMB18_Y0.ZINIT_A[12] origin:025-bram-config 27_97 +BRAM_R.RAMB18_Y0.ZINIT_A[13] origin:025-bram-config 27_81 +BRAM_R.RAMB18_Y0.ZINIT_A[14] origin:025-bram-config 27_49 +BRAM_R.RAMB18_Y0.ZINIT_A[15] origin:025-bram-config 27_33 +BRAM_R.RAMB18_Y0.ZINIT_A[16] origin:025-bram-config 27_17 +BRAM_R.RAMB18_Y0.ZINIT_A[17] origin:025-bram-config 27_01 +BRAM_R.RAMB18_Y0.ZINIT_A[1] origin:025-bram-config 27_65 +BRAM_R.RAMB18_Y0.ZINIT_A[2] origin:025-bram-config 27_137 +BRAM_R.RAMB18_Y0.ZINIT_A[3] origin:025-bram-config 27_121 +BRAM_R.RAMB18_Y0.ZINIT_A[4] origin:025-bram-config 27_105 +BRAM_R.RAMB18_Y0.ZINIT_A[5] origin:025-bram-config 27_89 +BRAM_R.RAMB18_Y0.ZINIT_A[6] origin:025-bram-config 27_57 +BRAM_R.RAMB18_Y0.ZINIT_A[7] origin:025-bram-config 27_41 +BRAM_R.RAMB18_Y0.ZINIT_A[8] origin:025-bram-config 27_25 +BRAM_R.RAMB18_Y0.ZINIT_A[9] origin:025-bram-config 27_09 +BRAM_R.RAMB18_Y0.ZINIT_B[0] origin:025-bram-config 27_79 +BRAM_R.RAMB18_Y0.ZINIT_B[10] origin:025-bram-config 27_135 +BRAM_R.RAMB18_Y0.ZINIT_B[11] origin:025-bram-config 27_119 +BRAM_R.RAMB18_Y0.ZINIT_B[12] origin:025-bram-config 27_103 +BRAM_R.RAMB18_Y0.ZINIT_B[13] origin:025-bram-config 27_87 +BRAM_R.RAMB18_Y0.ZINIT_B[14] origin:025-bram-config 27_55 +BRAM_R.RAMB18_Y0.ZINIT_B[15] origin:025-bram-config 27_39 +BRAM_R.RAMB18_Y0.ZINIT_B[16] origin:025-bram-config 27_23 +BRAM_R.RAMB18_Y0.ZINIT_B[17] origin:025-bram-config 27_07 +BRAM_R.RAMB18_Y0.ZINIT_B[1] origin:025-bram-config 27_71 +BRAM_R.RAMB18_Y0.ZINIT_B[2] origin:025-bram-config 27_143 +BRAM_R.RAMB18_Y0.ZINIT_B[3] origin:025-bram-config 27_127 +BRAM_R.RAMB18_Y0.ZINIT_B[4] origin:025-bram-config 27_111 +BRAM_R.RAMB18_Y0.ZINIT_B[5] origin:025-bram-config 27_95 +BRAM_R.RAMB18_Y0.ZINIT_B[6] origin:025-bram-config 27_63 +BRAM_R.RAMB18_Y0.ZINIT_B[7] origin:025-bram-config 27_47 +BRAM_R.RAMB18_Y0.ZINIT_B[8] origin:025-bram-config 27_31 +BRAM_R.RAMB18_Y0.ZINIT_B[9] origin:025-bram-config 27_15 +BRAM_R.RAMB18_Y0.ZINV_CLKARDCLK origin:025-bram-config 27_107 +BRAM_R.RAMB18_Y0.ZINV_CLKBWRCLK origin:025-bram-config 27_109 +BRAM_R.RAMB18_Y0.ZINV_ENARDEN origin:025-bram-config 27_112 +BRAM_R.RAMB18_Y0.ZINV_ENBWREN origin:025-bram-config 27_115 +BRAM_R.RAMB18_Y0.ZINV_REGCLKARDRCLK origin:025-bram-config 27_104 +BRAM_R.RAMB18_Y0.ZINV_REGCLKB origin:025-bram-config 27_108 +BRAM_R.RAMB18_Y0.ZINV_RSTRAMARSTRAM origin:025-bram-config 27_116 +BRAM_R.RAMB18_Y0.ZINV_RSTRAMB origin:025-bram-config 27_117 +BRAM_R.RAMB18_Y0.ZINV_RSTREGARSTREG origin:025-bram-config 27_120 +BRAM_R.RAMB18_Y0.ZINV_RSTREGB origin:025-bram-config 27_123 +BRAM_R.RAMB18_Y0.ZSRVAL_A[0] origin:025-bram-config 27_74 +BRAM_R.RAMB18_Y0.ZSRVAL_A[10] origin:025-bram-config 27_130 +BRAM_R.RAMB18_Y0.ZSRVAL_A[11] origin:025-bram-config 27_114 +BRAM_R.RAMB18_Y0.ZSRVAL_A[12] origin:025-bram-config 27_98 +BRAM_R.RAMB18_Y0.ZSRVAL_A[13] origin:025-bram-config 27_82 +BRAM_R.RAMB18_Y0.ZSRVAL_A[14] origin:025-bram-config 27_50 +BRAM_R.RAMB18_Y0.ZSRVAL_A[15] origin:025-bram-config 27_34 +BRAM_R.RAMB18_Y0.ZSRVAL_A[16] origin:025-bram-config 27_18 +BRAM_R.RAMB18_Y0.ZSRVAL_A[17] origin:025-bram-config 27_02 +BRAM_R.RAMB18_Y0.ZSRVAL_A[1] origin:025-bram-config 27_66 +BRAM_R.RAMB18_Y0.ZSRVAL_A[2] origin:025-bram-config 27_138 +BRAM_R.RAMB18_Y0.ZSRVAL_A[3] origin:025-bram-config 27_122 +BRAM_R.RAMB18_Y0.ZSRVAL_A[4] origin:025-bram-config 27_106 +BRAM_R.RAMB18_Y0.ZSRVAL_A[5] origin:025-bram-config 27_90 +BRAM_R.RAMB18_Y0.ZSRVAL_A[6] origin:025-bram-config 27_58 +BRAM_R.RAMB18_Y0.ZSRVAL_A[7] origin:025-bram-config 27_42 +BRAM_R.RAMB18_Y0.ZSRVAL_A[8] origin:025-bram-config 27_26 +BRAM_R.RAMB18_Y0.ZSRVAL_A[9] origin:025-bram-config 27_10 +BRAM_R.RAMB18_Y0.ZSRVAL_B[0] origin:025-bram-config 27_78 +BRAM_R.RAMB18_Y0.ZSRVAL_B[10] origin:025-bram-config 27_134 +BRAM_R.RAMB18_Y0.ZSRVAL_B[11] origin:025-bram-config 27_118 +BRAM_R.RAMB18_Y0.ZSRVAL_B[12] origin:025-bram-config 27_102 +BRAM_R.RAMB18_Y0.ZSRVAL_B[13] origin:025-bram-config 27_86 +BRAM_R.RAMB18_Y0.ZSRVAL_B[14] origin:025-bram-config 27_54 +BRAM_R.RAMB18_Y0.ZSRVAL_B[15] origin:025-bram-config 27_38 +BRAM_R.RAMB18_Y0.ZSRVAL_B[16] origin:025-bram-config 27_22 +BRAM_R.RAMB18_Y0.ZSRVAL_B[17] origin:025-bram-config 27_06 +BRAM_R.RAMB18_Y0.ZSRVAL_B[1] origin:025-bram-config 27_70 +BRAM_R.RAMB18_Y0.ZSRVAL_B[2] origin:025-bram-config 27_142 +BRAM_R.RAMB18_Y0.ZSRVAL_B[3] origin:025-bram-config 27_126 +BRAM_R.RAMB18_Y0.ZSRVAL_B[4] origin:025-bram-config 27_110 +BRAM_R.RAMB18_Y0.ZSRVAL_B[5] origin:025-bram-config 27_94 +BRAM_R.RAMB18_Y0.ZSRVAL_B[6] origin:025-bram-config 27_62 +BRAM_R.RAMB18_Y0.ZSRVAL_B[7] origin:025-bram-config 27_46 +BRAM_R.RAMB18_Y0.ZSRVAL_B[8] origin:025-bram-config 27_30 +BRAM_R.RAMB18_Y0.ZSRVAL_B[9] origin:025-bram-config 27_14 +BRAM_R.RAMB18_Y1.DOA_REG origin:025-bram-config 27_251 +BRAM_R.RAMB18_Y1.DOB_REG origin:025-bram-config 27_248 +BRAM_R.RAMB18_Y1.FIFO_MODE origin:029-bram-fifo-config 27_169 +BRAM_R.RAMB18_Y1.IN_USE origin:029-bram-fifo-config 27_220 27_221 +BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_DELAYED_WRITE origin:025-bram-config !27_224 +BRAM_R.RAMB18_Y1.RDADDR_COLLISION_HWCONFIG_PERFORMANCE origin:025-bram-config 27_224 +BRAM_R.RAMB18_Y1.READ_WIDTH_A_1 origin:025-bram-config !27_283 !27_284 !27_285 +BRAM_R.RAMB18_Y1.READ_WIDTH_A_18 origin:025-bram-config !27_284 !27_285 27_283 +BRAM_R.RAMB18_Y1.READ_WIDTH_A_2 origin:025-bram-config !27_283 !27_284 27_285 +BRAM_R.RAMB18_Y1.READ_WIDTH_A_4 origin:025-bram-config !27_283 !27_285 27_284 +BRAM_R.RAMB18_Y1.READ_WIDTH_A_9 origin:025-bram-config !27_283 27_284 27_285 +BRAM_R.RAMB18_Y1.READ_WIDTH_B_1 origin:025-bram-config !27_275 !27_276 !27_277 +BRAM_R.RAMB18_Y1.READ_WIDTH_B_18 origin:025-bram-config !27_276 !27_277 27_275 +BRAM_R.RAMB18_Y1.READ_WIDTH_B_2 origin:025-bram-config !27_275 !27_276 27_277 +BRAM_R.RAMB18_Y1.READ_WIDTH_B_4 origin:025-bram-config !27_275 !27_277 27_276 +BRAM_R.RAMB18_Y1.READ_WIDTH_B_9 origin:025-bram-config !27_275 27_276 27_277 +BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_REGCE origin:025-bram-config 27_196 +BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_A_RSTREG origin:025-bram-config !27_196 +BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_REGCE origin:025-bram-config 27_195 +BRAM_R.RAMB18_Y1.RSTREG_PRIORITY_B_RSTREG origin:025-bram-config !27_195 +BRAM_R.RAMB18_Y1.SDP_READ_WIDTH_36 origin:025-bram-config 27_272 +BRAM_R.RAMB18_Y1.SDP_WRITE_WIDTH_36 origin:025-bram-config 27_280 +BRAM_R.RAMB18_Y1.WRITE_MODE_A_NO_CHANGE origin:025-bram-config 27_256 +BRAM_R.RAMB18_Y1.WRITE_MODE_A_READ_FIRST origin:025-bram-config 27_264 +BRAM_R.RAMB18_Y1.WRITE_MODE_B_NO_CHANGE origin:025-bram-config 27_252 +BRAM_R.RAMB18_Y1.WRITE_MODE_B_READ_FIRST origin:025-bram-config 27_253 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_1 origin:025-bram-config !27_267 !27_268 !27_269 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_18 origin:025-bram-config !27_268 !27_269 27_267 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_2 origin:025-bram-config !27_267 !27_268 27_269 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_4 origin:025-bram-config !27_267 !27_269 27_268 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_A_9 origin:025-bram-config !27_267 27_268 27_269 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_1 origin:025-bram-config !27_259 !27_260 !27_261 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_18 origin:025-bram-config !27_260 !27_261 27_259 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_2 origin:025-bram-config !27_259 !27_260 27_261 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_4 origin:025-bram-config !27_259 !27_261 27_260 +BRAM_R.RAMB18_Y1.WRITE_WIDTH_B_9 origin:025-bram-config !27_259 27_260 27_261 +BRAM_R.RAMB18_Y1.ZINIT_A[0] origin:025-bram-config 27_249 +BRAM_R.RAMB18_Y1.ZINIT_A[10] origin:025-bram-config 27_305 +BRAM_R.RAMB18_Y1.ZINIT_A[11] origin:025-bram-config 27_289 +BRAM_R.RAMB18_Y1.ZINIT_A[12] origin:025-bram-config 27_273 +BRAM_R.RAMB18_Y1.ZINIT_A[13] origin:025-bram-config 27_257 +BRAM_R.RAMB18_Y1.ZINIT_A[14] origin:025-bram-config 27_225 +BRAM_R.RAMB18_Y1.ZINIT_A[15] origin:025-bram-config 27_209 +BRAM_R.RAMB18_Y1.ZINIT_A[16] origin:025-bram-config 27_193 +BRAM_R.RAMB18_Y1.ZINIT_A[17] origin:025-bram-config 27_177 +BRAM_R.RAMB18_Y1.ZINIT_A[1] origin:025-bram-config 27_241 +BRAM_R.RAMB18_Y1.ZINIT_A[2] origin:025-bram-config 27_313 +BRAM_R.RAMB18_Y1.ZINIT_A[3] origin:025-bram-config 27_297 +BRAM_R.RAMB18_Y1.ZINIT_A[4] origin:025-bram-config 27_281 +BRAM_R.RAMB18_Y1.ZINIT_A[5] origin:025-bram-config 27_265 +BRAM_R.RAMB18_Y1.ZINIT_A[6] origin:025-bram-config 27_233 +BRAM_R.RAMB18_Y1.ZINIT_A[7] origin:025-bram-config 27_217 +BRAM_R.RAMB18_Y1.ZINIT_A[8] origin:025-bram-config 27_201 +BRAM_R.RAMB18_Y1.ZINIT_A[9] origin:025-bram-config 27_185 +BRAM_R.RAMB18_Y1.ZINIT_B[0] origin:025-bram-config 27_255 +BRAM_R.RAMB18_Y1.ZINIT_B[10] origin:025-bram-config 27_311 +BRAM_R.RAMB18_Y1.ZINIT_B[11] origin:025-bram-config 27_295 +BRAM_R.RAMB18_Y1.ZINIT_B[12] origin:025-bram-config 27_279 +BRAM_R.RAMB18_Y1.ZINIT_B[13] origin:025-bram-config 27_263 +BRAM_R.RAMB18_Y1.ZINIT_B[14] origin:025-bram-config 27_231 +BRAM_R.RAMB18_Y1.ZINIT_B[15] origin:025-bram-config 27_215 +BRAM_R.RAMB18_Y1.ZINIT_B[16] origin:025-bram-config 27_199 +BRAM_R.RAMB18_Y1.ZINIT_B[17] origin:025-bram-config 27_183 +BRAM_R.RAMB18_Y1.ZINIT_B[1] origin:025-bram-config 27_247 +BRAM_R.RAMB18_Y1.ZINIT_B[2] origin:025-bram-config 27_319 +BRAM_R.RAMB18_Y1.ZINIT_B[3] origin:025-bram-config 27_303 +BRAM_R.RAMB18_Y1.ZINIT_B[4] origin:025-bram-config 27_287 +BRAM_R.RAMB18_Y1.ZINIT_B[5] origin:025-bram-config 27_271 +BRAM_R.RAMB18_Y1.ZINIT_B[6] origin:025-bram-config 27_239 +BRAM_R.RAMB18_Y1.ZINIT_B[7] origin:025-bram-config 27_223 +BRAM_R.RAMB18_Y1.ZINIT_B[8] origin:025-bram-config 27_207 +BRAM_R.RAMB18_Y1.ZINIT_B[9] origin:025-bram-config 27_191 +BRAM_R.RAMB18_Y1.ZINV_CLKARDCLK origin:025-bram-config 27_213 +BRAM_R.RAMB18_Y1.ZINV_CLKBWRCLK origin:025-bram-config 27_211 +BRAM_R.RAMB18_Y1.ZINV_ENARDEN origin:025-bram-config 27_208 +BRAM_R.RAMB18_Y1.ZINV_ENBWREN origin:025-bram-config 27_205 +BRAM_R.RAMB18_Y1.ZINV_REGCLKARDRCLK origin:025-bram-config 27_216 +BRAM_R.RAMB18_Y1.ZINV_REGCLKB origin:025-bram-config 27_212 +BRAM_R.RAMB18_Y1.ZINV_RSTRAMARSTRAM origin:025-bram-config 27_204 +BRAM_R.RAMB18_Y1.ZINV_RSTRAMB origin:025-bram-config 27_203 +BRAM_R.RAMB18_Y1.ZINV_RSTREGARSTREG origin:025-bram-config 27_200 +BRAM_R.RAMB18_Y1.ZINV_RSTREGB origin:025-bram-config 27_197 +BRAM_R.RAMB18_Y1.ZSRVAL_A[0] origin:025-bram-config 27_250 +BRAM_R.RAMB18_Y1.ZSRVAL_A[10] origin:025-bram-config 27_306 +BRAM_R.RAMB18_Y1.ZSRVAL_A[11] origin:025-bram-config 27_290 +BRAM_R.RAMB18_Y1.ZSRVAL_A[12] origin:025-bram-config 27_274 +BRAM_R.RAMB18_Y1.ZSRVAL_A[13] origin:025-bram-config 27_258 +BRAM_R.RAMB18_Y1.ZSRVAL_A[14] origin:025-bram-config 27_226 +BRAM_R.RAMB18_Y1.ZSRVAL_A[15] origin:025-bram-config 27_210 +BRAM_R.RAMB18_Y1.ZSRVAL_A[16] origin:025-bram-config 27_194 +BRAM_R.RAMB18_Y1.ZSRVAL_A[17] origin:025-bram-config 27_178 +BRAM_R.RAMB18_Y1.ZSRVAL_A[1] origin:025-bram-config 27_242 +BRAM_R.RAMB18_Y1.ZSRVAL_A[2] origin:025-bram-config 27_314 +BRAM_R.RAMB18_Y1.ZSRVAL_A[3] origin:025-bram-config 27_298 +BRAM_R.RAMB18_Y1.ZSRVAL_A[4] origin:025-bram-config 27_282 +BRAM_R.RAMB18_Y1.ZSRVAL_A[5] origin:025-bram-config 27_266 +BRAM_R.RAMB18_Y1.ZSRVAL_A[6] origin:025-bram-config 27_234 +BRAM_R.RAMB18_Y1.ZSRVAL_A[7] origin:025-bram-config 27_218 +BRAM_R.RAMB18_Y1.ZSRVAL_A[8] origin:025-bram-config 27_202 +BRAM_R.RAMB18_Y1.ZSRVAL_A[9] origin:025-bram-config 27_186 +BRAM_R.RAMB18_Y1.ZSRVAL_B[0] origin:025-bram-config 27_254 +BRAM_R.RAMB18_Y1.ZSRVAL_B[10] origin:025-bram-config 27_310 +BRAM_R.RAMB18_Y1.ZSRVAL_B[11] origin:025-bram-config 27_294 +BRAM_R.RAMB18_Y1.ZSRVAL_B[12] origin:025-bram-config 27_278 +BRAM_R.RAMB18_Y1.ZSRVAL_B[13] origin:025-bram-config 27_262 +BRAM_R.RAMB18_Y1.ZSRVAL_B[14] origin:025-bram-config 27_230 +BRAM_R.RAMB18_Y1.ZSRVAL_B[15] origin:025-bram-config 27_214 +BRAM_R.RAMB18_Y1.ZSRVAL_B[16] origin:025-bram-config 27_198 +BRAM_R.RAMB18_Y1.ZSRVAL_B[17] origin:025-bram-config 27_182 +BRAM_R.RAMB18_Y1.ZSRVAL_B[1] origin:025-bram-config 27_246 +BRAM_R.RAMB18_Y1.ZSRVAL_B[2] origin:025-bram-config 27_318 +BRAM_R.RAMB18_Y1.ZSRVAL_B[3] origin:025-bram-config 27_302 +BRAM_R.RAMB18_Y1.ZSRVAL_B[4] origin:025-bram-config 27_286 +BRAM_R.RAMB18_Y1.ZSRVAL_B[5] origin:025-bram-config 27_270 +BRAM_R.RAMB18_Y1.ZSRVAL_B[6] origin:025-bram-config 27_238 +BRAM_R.RAMB18_Y1.ZSRVAL_B[7] origin:025-bram-config 27_222 +BRAM_R.RAMB18_Y1.ZSRVAL_B[8] origin:025-bram-config 27_206 +BRAM_R.RAMB18_Y1.ZSRVAL_B[9] origin:025-bram-config 27_190 +BRAM_R.RAMB36.EN_ECC_READ origin:027-bram36-config 27_175 +BRAM_R.RAMB36.EN_ECC_WRITE origin:027-bram36-config 27_162 +BRAM_R.RAMB36.RAM_EXTENSION_A_LOWER origin:027-bram36-config 27_188 +BRAM_R.RAMB36.RAM_EXTENSION_A_NONE_OR_UPPER origin:027-bram36-config !27_188 +BRAM_R.RAMB36.RAM_EXTENSION_B_LOWER origin:027-bram36-config 27_187 +BRAM_R.RAMB36.RAM_EXTENSION_B_NONE_OR_UPPER origin:027-bram36-config !27_187 +BRAM_R.ZALMOST_EMPTY_OFFSET[0] origin:028-fifo-config 27_288 +BRAM_R.ZALMOST_EMPTY_OFFSET[10] origin:028-fifo-config 27_308 +BRAM_R.ZALMOST_EMPTY_OFFSET[11] origin:028-fifo-config 27_309 +BRAM_R.ZALMOST_EMPTY_OFFSET[12] origin:028-fifo-config 27_312 +BRAM_R.ZALMOST_EMPTY_OFFSET[1] origin:028-fifo-config 27_291 +BRAM_R.ZALMOST_EMPTY_OFFSET[2] origin:028-fifo-config 27_292 +BRAM_R.ZALMOST_EMPTY_OFFSET[3] origin:028-fifo-config 27_293 +BRAM_R.ZALMOST_EMPTY_OFFSET[4] origin:028-fifo-config 27_296 +BRAM_R.ZALMOST_EMPTY_OFFSET[5] origin:028-fifo-config 27_299 +BRAM_R.ZALMOST_EMPTY_OFFSET[6] origin:028-fifo-config 27_300 +BRAM_R.ZALMOST_EMPTY_OFFSET[7] origin:028-fifo-config 27_301 +BRAM_R.ZALMOST_EMPTY_OFFSET[8] origin:028-fifo-config 27_304 +BRAM_R.ZALMOST_EMPTY_OFFSET[9] origin:028-fifo-config 27_307 +BRAM_R.ZALMOST_FULL_OFFSET[0] origin:028-fifo-config 27_32 +BRAM_R.ZALMOST_FULL_OFFSET[10] origin:028-fifo-config 27_12 +BRAM_R.ZALMOST_FULL_OFFSET[11] origin:028-fifo-config 27_11 +BRAM_R.ZALMOST_FULL_OFFSET[12] origin:028-fifo-config 27_08 +BRAM_R.ZALMOST_FULL_OFFSET[1] origin:028-fifo-config 27_29 +BRAM_R.ZALMOST_FULL_OFFSET[2] origin:028-fifo-config 27_28 +BRAM_R.ZALMOST_FULL_OFFSET[3] origin:028-fifo-config 27_27 +BRAM_R.ZALMOST_FULL_OFFSET[4] origin:028-fifo-config 27_24 +BRAM_R.ZALMOST_FULL_OFFSET[5] origin:028-fifo-config 27_21 +BRAM_R.ZALMOST_FULL_OFFSET[6] origin:028-fifo-config 27_20 +BRAM_R.ZALMOST_FULL_OFFSET[7] origin:028-fifo-config 27_19 +BRAM_R.ZALMOST_FULL_OFFSET[8] origin:028-fifo-config 27_16 +BRAM_R.ZALMOST_FULL_OFFSET[9] origin:028-fifo-config 27_13 diff --git a/zynq7/segbits_clbll_l.origin_info.db b/zynq7/segbits_clbll_l.origin_info.db new file mode 100644 index 0000000..1c2d84c --- /dev/null +++ b/zynq7/segbits_clbll_l.origin_info.db @@ -0,0 +1,678 @@ +CLBLL_L.SLICEL_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06 +CLBLL_L.SLICEL_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07 +CLBLL_L.SLICEL_X0.A5FFMUX.IN_A origin:012-clb-n5ffmux 30_09 +CLBLL_L.SLICEL_X0.A5FFMUX.IN_B origin:012-clb-n5ffmux 30_10 +CLBLL_L.SLICEL_X0.AFF.ZINI origin:011-clb-ffconfig 31_03 +CLBLL_L.SLICEL_X0.AFF.ZRST origin:011-clb-ffconfig 30_12 +CLBLL_L.SLICEL_X0.AFFMUX.AX origin:015-clb-nffmux !30_00 !30_02 !30_03 30_01 +CLBLL_L.SLICEL_X0.AFFMUX.CY origin:015-clb-nffmux !30_01 !30_03 30_00 30_02 +CLBLL_L.SLICEL_X0.AFFMUX.F7 origin:015-clb-nffmux !30_02 !30_03 30_00 30_01 +CLBLL_L.SLICEL_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03 +CLBLL_L.SLICEL_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03 +CLBLL_L.SLICEL_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02 +CLBLL_L.SLICEL_X0.ALUT.INIT[00] origin:010-clb-lutinit 32_15 +CLBLL_L.SLICEL_X0.ALUT.INIT[01] origin:010-clb-lutinit 33_15 +CLBLL_L.SLICEL_X0.ALUT.INIT[02] origin:010-clb-lutinit 32_14 +CLBLL_L.SLICEL_X0.ALUT.INIT[03] origin:010-clb-lutinit 33_14 +CLBLL_L.SLICEL_X0.ALUT.INIT[04] origin:010-clb-lutinit 32_13 +CLBLL_L.SLICEL_X0.ALUT.INIT[05] origin:010-clb-lutinit 33_13 +CLBLL_L.SLICEL_X0.ALUT.INIT[06] origin:010-clb-lutinit 32_12 +CLBLL_L.SLICEL_X0.ALUT.INIT[07] origin:010-clb-lutinit 33_12 +CLBLL_L.SLICEL_X0.ALUT.INIT[08] origin:010-clb-lutinit 35_15 +CLBLL_L.SLICEL_X0.ALUT.INIT[09] origin:010-clb-lutinit 34_15 +CLBLL_L.SLICEL_X0.ALUT.INIT[10] origin:010-clb-lutinit 35_14 +CLBLL_L.SLICEL_X0.ALUT.INIT[11] origin:010-clb-lutinit 34_14 +CLBLL_L.SLICEL_X0.ALUT.INIT[12] origin:010-clb-lutinit 35_13 +CLBLL_L.SLICEL_X0.ALUT.INIT[13] origin:010-clb-lutinit 34_13 +CLBLL_L.SLICEL_X0.ALUT.INIT[14] origin:010-clb-lutinit 35_12 +CLBLL_L.SLICEL_X0.ALUT.INIT[15] origin:010-clb-lutinit 34_12 +CLBLL_L.SLICEL_X0.ALUT.INIT[16] origin:010-clb-lutinit 32_11 +CLBLL_L.SLICEL_X0.ALUT.INIT[17] origin:010-clb-lutinit 33_11 +CLBLL_L.SLICEL_X0.ALUT.INIT[18] origin:010-clb-lutinit 32_10 +CLBLL_L.SLICEL_X0.ALUT.INIT[19] origin:010-clb-lutinit 33_10 +CLBLL_L.SLICEL_X0.ALUT.INIT[20] origin:010-clb-lutinit 32_09 +CLBLL_L.SLICEL_X0.ALUT.INIT[21] origin:010-clb-lutinit 33_09 +CLBLL_L.SLICEL_X0.ALUT.INIT[22] origin:010-clb-lutinit 32_08 +CLBLL_L.SLICEL_X0.ALUT.INIT[23] origin:010-clb-lutinit 33_08 +CLBLL_L.SLICEL_X0.ALUT.INIT[24] origin:010-clb-lutinit 35_11 +CLBLL_L.SLICEL_X0.ALUT.INIT[25] origin:010-clb-lutinit 34_11 +CLBLL_L.SLICEL_X0.ALUT.INIT[26] origin:010-clb-lutinit 35_10 +CLBLL_L.SLICEL_X0.ALUT.INIT[27] origin:010-clb-lutinit 34_10 +CLBLL_L.SLICEL_X0.ALUT.INIT[28] origin:010-clb-lutinit 35_09 +CLBLL_L.SLICEL_X0.ALUT.INIT[29] origin:010-clb-lutinit 34_09 +CLBLL_L.SLICEL_X0.ALUT.INIT[30] origin:010-clb-lutinit 35_08 +CLBLL_L.SLICEL_X0.ALUT.INIT[31] origin:010-clb-lutinit 34_08 +CLBLL_L.SLICEL_X0.ALUT.INIT[32] origin:010-clb-lutinit 32_07 +CLBLL_L.SLICEL_X0.ALUT.INIT[33] origin:010-clb-lutinit 33_07 +CLBLL_L.SLICEL_X0.ALUT.INIT[34] origin:010-clb-lutinit 32_06 +CLBLL_L.SLICEL_X0.ALUT.INIT[35] origin:010-clb-lutinit 33_06 +CLBLL_L.SLICEL_X0.ALUT.INIT[36] origin:010-clb-lutinit 32_05 +CLBLL_L.SLICEL_X0.ALUT.INIT[37] origin:010-clb-lutinit 33_05 +CLBLL_L.SLICEL_X0.ALUT.INIT[38] origin:010-clb-lutinit 32_04 +CLBLL_L.SLICEL_X0.ALUT.INIT[39] origin:010-clb-lutinit 33_04 +CLBLL_L.SLICEL_X0.ALUT.INIT[40] origin:010-clb-lutinit 35_07 +CLBLL_L.SLICEL_X0.ALUT.INIT[41] origin:010-clb-lutinit 34_07 +CLBLL_L.SLICEL_X0.ALUT.INIT[42] origin:010-clb-lutinit 35_06 +CLBLL_L.SLICEL_X0.ALUT.INIT[43] origin:010-clb-lutinit 34_06 +CLBLL_L.SLICEL_X0.ALUT.INIT[44] origin:010-clb-lutinit 35_05 +CLBLL_L.SLICEL_X0.ALUT.INIT[45] origin:010-clb-lutinit 34_05 +CLBLL_L.SLICEL_X0.ALUT.INIT[46] origin:010-clb-lutinit 35_04 +CLBLL_L.SLICEL_X0.ALUT.INIT[47] origin:010-clb-lutinit 34_04 +CLBLL_L.SLICEL_X0.ALUT.INIT[48] origin:010-clb-lutinit 32_03 +CLBLL_L.SLICEL_X0.ALUT.INIT[49] origin:010-clb-lutinit 33_03 +CLBLL_L.SLICEL_X0.ALUT.INIT[50] origin:010-clb-lutinit 32_02 +CLBLL_L.SLICEL_X0.ALUT.INIT[51] origin:010-clb-lutinit 33_02 +CLBLL_L.SLICEL_X0.ALUT.INIT[52] origin:010-clb-lutinit 32_01 +CLBLL_L.SLICEL_X0.ALUT.INIT[53] origin:010-clb-lutinit 33_01 +CLBLL_L.SLICEL_X0.ALUT.INIT[54] origin:010-clb-lutinit 32_00 +CLBLL_L.SLICEL_X0.ALUT.INIT[55] origin:010-clb-lutinit 33_00 +CLBLL_L.SLICEL_X0.ALUT.INIT[56] origin:010-clb-lutinit 35_03 +CLBLL_L.SLICEL_X0.ALUT.INIT[57] origin:010-clb-lutinit 34_03 +CLBLL_L.SLICEL_X0.ALUT.INIT[58] origin:010-clb-lutinit 35_02 +CLBLL_L.SLICEL_X0.ALUT.INIT[59] origin:010-clb-lutinit 34_02 +CLBLL_L.SLICEL_X0.ALUT.INIT[60] origin:010-clb-lutinit 35_01 +CLBLL_L.SLICEL_X0.ALUT.INIT[61] origin:010-clb-lutinit 34_01 +CLBLL_L.SLICEL_X0.ALUT.INIT[62] origin:010-clb-lutinit 35_00 +CLBLL_L.SLICEL_X0.ALUT.INIT[63] origin:010-clb-lutinit 34_00 +CLBLL_L.SLICEL_X0.AOUTMUX.A5Q origin:016-clb-noutmux !30_06 !30_08 !30_11 30_07 +CLBLL_L.SLICEL_X0.AOUTMUX.CY origin:016-clb-noutmux !30_07 !30_11 30_06 30_08 +CLBLL_L.SLICEL_X0.AOUTMUX.F7 origin:016-clb-noutmux !30_08 !30_11 30_06 30_07 +CLBLL_L.SLICEL_X0.AOUTMUX.O5 origin:016-clb-noutmux !30_07 !30_08 30_06 30_11 +CLBLL_L.SLICEL_X0.AOUTMUX.O6 origin:016-clb-noutmux !30_06 !30_07 !30_08 30_11 +CLBLL_L.SLICEL_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08 +CLBLL_L.SLICEL_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22 +CLBLL_L.SLICEL_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19 +CLBLL_L.SLICEL_X0.B5FFMUX.IN_A origin:012-clb-n5ffmux 30_19 +CLBLL_L.SLICEL_X0.B5FFMUX.IN_B origin:012-clb-n5ffmux 30_18 +CLBLL_L.SLICEL_X0.BFF.ZINI origin:011-clb-ffconfig 31_28 +CLBLL_L.SLICEL_X0.BFF.ZRST origin:011-clb-ffconfig 30_30 +CLBLL_L.SLICEL_X0.BFFMUX.BX origin:015-clb-nffmux !30_24 !30_25 !30_27 30_26 +CLBLL_L.SLICEL_X0.BFFMUX.CY origin:015-clb-nffmux !30_24 !30_26 30_25 30_27 +CLBLL_L.SLICEL_X0.BFFMUX.F8 origin:015-clb-nffmux !30_24 !30_25 30_26 30_27 +CLBLL_L.SLICEL_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27 +CLBLL_L.SLICEL_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24 +CLBLL_L.SLICEL_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25 +CLBLL_L.SLICEL_X0.BLUT.INIT[00] origin:010-clb-lutinit 32_31 +CLBLL_L.SLICEL_X0.BLUT.INIT[01] origin:010-clb-lutinit 33_31 +CLBLL_L.SLICEL_X0.BLUT.INIT[02] origin:010-clb-lutinit 32_30 +CLBLL_L.SLICEL_X0.BLUT.INIT[03] origin:010-clb-lutinit 33_30 +CLBLL_L.SLICEL_X0.BLUT.INIT[04] origin:010-clb-lutinit 32_29 +CLBLL_L.SLICEL_X0.BLUT.INIT[05] origin:010-clb-lutinit 33_29 +CLBLL_L.SLICEL_X0.BLUT.INIT[06] origin:010-clb-lutinit 32_28 +CLBLL_L.SLICEL_X0.BLUT.INIT[07] origin:010-clb-lutinit 33_28 +CLBLL_L.SLICEL_X0.BLUT.INIT[08] origin:010-clb-lutinit 35_31 +CLBLL_L.SLICEL_X0.BLUT.INIT[09] origin:010-clb-lutinit 34_31 +CLBLL_L.SLICEL_X0.BLUT.INIT[10] origin:010-clb-lutinit 35_30 +CLBLL_L.SLICEL_X0.BLUT.INIT[11] origin:010-clb-lutinit 34_30 +CLBLL_L.SLICEL_X0.BLUT.INIT[12] origin:010-clb-lutinit 35_29 +CLBLL_L.SLICEL_X0.BLUT.INIT[13] origin:010-clb-lutinit 34_29 +CLBLL_L.SLICEL_X0.BLUT.INIT[14] origin:010-clb-lutinit 35_28 +CLBLL_L.SLICEL_X0.BLUT.INIT[15] origin:010-clb-lutinit 34_28 +CLBLL_L.SLICEL_X0.BLUT.INIT[16] origin:010-clb-lutinit 32_27 +CLBLL_L.SLICEL_X0.BLUT.INIT[17] origin:010-clb-lutinit 33_27 +CLBLL_L.SLICEL_X0.BLUT.INIT[18] origin:010-clb-lutinit 32_26 +CLBLL_L.SLICEL_X0.BLUT.INIT[19] origin:010-clb-lutinit 33_26 +CLBLL_L.SLICEL_X0.BLUT.INIT[20] origin:010-clb-lutinit 32_25 +CLBLL_L.SLICEL_X0.BLUT.INIT[21] origin:010-clb-lutinit 33_25 +CLBLL_L.SLICEL_X0.BLUT.INIT[22] origin:010-clb-lutinit 32_24 +CLBLL_L.SLICEL_X0.BLUT.INIT[23] origin:010-clb-lutinit 33_24 +CLBLL_L.SLICEL_X0.BLUT.INIT[24] origin:010-clb-lutinit 35_27 +CLBLL_L.SLICEL_X0.BLUT.INIT[25] origin:010-clb-lutinit 34_27 +CLBLL_L.SLICEL_X0.BLUT.INIT[26] origin:010-clb-lutinit 35_26 +CLBLL_L.SLICEL_X0.BLUT.INIT[27] origin:010-clb-lutinit 34_26 +CLBLL_L.SLICEL_X0.BLUT.INIT[28] origin:010-clb-lutinit 35_25 +CLBLL_L.SLICEL_X0.BLUT.INIT[29] origin:010-clb-lutinit 34_25 +CLBLL_L.SLICEL_X0.BLUT.INIT[30] origin:010-clb-lutinit 35_24 +CLBLL_L.SLICEL_X0.BLUT.INIT[31] origin:010-clb-lutinit 34_24 +CLBLL_L.SLICEL_X0.BLUT.INIT[32] origin:010-clb-lutinit 32_23 +CLBLL_L.SLICEL_X0.BLUT.INIT[33] origin:010-clb-lutinit 33_23 +CLBLL_L.SLICEL_X0.BLUT.INIT[34] origin:010-clb-lutinit 32_22 +CLBLL_L.SLICEL_X0.BLUT.INIT[35] origin:010-clb-lutinit 33_22 +CLBLL_L.SLICEL_X0.BLUT.INIT[36] origin:010-clb-lutinit 32_21 +CLBLL_L.SLICEL_X0.BLUT.INIT[37] origin:010-clb-lutinit 33_21 +CLBLL_L.SLICEL_X0.BLUT.INIT[38] origin:010-clb-lutinit 32_20 +CLBLL_L.SLICEL_X0.BLUT.INIT[39] origin:010-clb-lutinit 33_20 +CLBLL_L.SLICEL_X0.BLUT.INIT[40] origin:010-clb-lutinit 35_23 +CLBLL_L.SLICEL_X0.BLUT.INIT[41] origin:010-clb-lutinit 34_23 +CLBLL_L.SLICEL_X0.BLUT.INIT[42] origin:010-clb-lutinit 35_22 +CLBLL_L.SLICEL_X0.BLUT.INIT[43] origin:010-clb-lutinit 34_22 +CLBLL_L.SLICEL_X0.BLUT.INIT[44] origin:010-clb-lutinit 35_21 +CLBLL_L.SLICEL_X0.BLUT.INIT[45] origin:010-clb-lutinit 34_21 +CLBLL_L.SLICEL_X0.BLUT.INIT[46] origin:010-clb-lutinit 35_20 +CLBLL_L.SLICEL_X0.BLUT.INIT[47] origin:010-clb-lutinit 34_20 +CLBLL_L.SLICEL_X0.BLUT.INIT[48] origin:010-clb-lutinit 32_19 +CLBLL_L.SLICEL_X0.BLUT.INIT[49] origin:010-clb-lutinit 33_19 +CLBLL_L.SLICEL_X0.BLUT.INIT[50] origin:010-clb-lutinit 32_18 +CLBLL_L.SLICEL_X0.BLUT.INIT[51] origin:010-clb-lutinit 33_18 +CLBLL_L.SLICEL_X0.BLUT.INIT[52] origin:010-clb-lutinit 32_17 +CLBLL_L.SLICEL_X0.BLUT.INIT[53] origin:010-clb-lutinit 33_17 +CLBLL_L.SLICEL_X0.BLUT.INIT[54] origin:010-clb-lutinit 32_16 +CLBLL_L.SLICEL_X0.BLUT.INIT[55] origin:010-clb-lutinit 33_16 +CLBLL_L.SLICEL_X0.BLUT.INIT[56] origin:010-clb-lutinit 35_19 +CLBLL_L.SLICEL_X0.BLUT.INIT[57] origin:010-clb-lutinit 34_19 +CLBLL_L.SLICEL_X0.BLUT.INIT[58] origin:010-clb-lutinit 35_18 +CLBLL_L.SLICEL_X0.BLUT.INIT[59] origin:010-clb-lutinit 34_18 +CLBLL_L.SLICEL_X0.BLUT.INIT[60] origin:010-clb-lutinit 35_17 +CLBLL_L.SLICEL_X0.BLUT.INIT[61] origin:010-clb-lutinit 34_17 +CLBLL_L.SLICEL_X0.BLUT.INIT[62] origin:010-clb-lutinit 35_16 +CLBLL_L.SLICEL_X0.BLUT.INIT[63] origin:010-clb-lutinit 34_16 +CLBLL_L.SLICEL_X0.BOUTMUX.B5Q origin:016-clb-noutmux !30_20 !30_21 !30_22 30_23 +CLBLL_L.SLICEL_X0.BOUTMUX.CY origin:016-clb-noutmux !30_20 !30_23 30_21 30_22 +CLBLL_L.SLICEL_X0.BOUTMUX.F8 origin:016-clb-noutmux !30_20 !30_21 30_22 30_23 +CLBLL_L.SLICEL_X0.BOUTMUX.O5 origin:016-clb-noutmux !30_21 !30_23 30_20 30_22 +CLBLL_L.SLICEL_X0.BOUTMUX.O6 origin:016-clb-noutmux !30_21 !30_22 !30_23 30_20 +CLBLL_L.SLICEL_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21 +CLBLL_L.SLICEL_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41 +CLBLL_L.SLICEL_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47 +CLBLL_L.SLICEL_X0.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_45 +CLBLL_L.SLICEL_X0.C5FFMUX.IN_B origin:012-clb-n5ffmux 30_39 +CLBLL_L.SLICEL_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15 +CLBLL_L.SLICEL_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15 +CLBLL_L.SLICEL_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48 +CLBLL_L.SLICEL_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49 +CLBLL_L.SLICEL_X0.CEUSEDMUX origin:014-clb-ffsrcemux 01_39 +CLBLL_L.SLICEL_X0.CFF.ZINI origin:011-clb-ffconfig 31_33 +CLBLL_L.SLICEL_X0.CFF.ZRST origin:011-clb-ffconfig 30_33 +CLBLL_L.SLICEL_X0.CFFMUX.CX origin:015-clb-nffmux !30_35 !30_37 !30_38 30_36 +CLBLL_L.SLICEL_X0.CFFMUX.CY origin:015-clb-nffmux !30_36 !30_38 30_35 30_37 +CLBLL_L.SLICEL_X0.CFFMUX.F7 origin:015-clb-nffmux !30_37 !30_38 30_35 30_36 +CLBLL_L.SLICEL_X0.CFFMUX.O5 origin:015-clb-nffmux !30_36 !30_37 30_35 30_38 +CLBLL_L.SLICEL_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38 +CLBLL_L.SLICEL_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37 +CLBLL_L.SLICEL_X0.CLKINV origin:011-clb-ffconfig 01_51 +CLBLL_L.SLICEL_X0.CLUT.INIT[00] origin:010-clb-lutinit 32_47 +CLBLL_L.SLICEL_X0.CLUT.INIT[01] origin:010-clb-lutinit 33_47 +CLBLL_L.SLICEL_X0.CLUT.INIT[02] origin:010-clb-lutinit 32_46 +CLBLL_L.SLICEL_X0.CLUT.INIT[03] origin:010-clb-lutinit 33_46 +CLBLL_L.SLICEL_X0.CLUT.INIT[04] origin:010-clb-lutinit 32_45 +CLBLL_L.SLICEL_X0.CLUT.INIT[05] origin:010-clb-lutinit 33_45 +CLBLL_L.SLICEL_X0.CLUT.INIT[06] origin:010-clb-lutinit 32_44 +CLBLL_L.SLICEL_X0.CLUT.INIT[07] origin:010-clb-lutinit 33_44 +CLBLL_L.SLICEL_X0.CLUT.INIT[08] origin:010-clb-lutinit 35_47 +CLBLL_L.SLICEL_X0.CLUT.INIT[09] origin:010-clb-lutinit 34_47 +CLBLL_L.SLICEL_X0.CLUT.INIT[10] origin:010-clb-lutinit 35_46 +CLBLL_L.SLICEL_X0.CLUT.INIT[11] origin:010-clb-lutinit 34_46 +CLBLL_L.SLICEL_X0.CLUT.INIT[12] origin:010-clb-lutinit 35_45 +CLBLL_L.SLICEL_X0.CLUT.INIT[13] origin:010-clb-lutinit 34_45 +CLBLL_L.SLICEL_X0.CLUT.INIT[14] origin:010-clb-lutinit 35_44 +CLBLL_L.SLICEL_X0.CLUT.INIT[15] origin:010-clb-lutinit 34_44 +CLBLL_L.SLICEL_X0.CLUT.INIT[16] origin:010-clb-lutinit 32_43 +CLBLL_L.SLICEL_X0.CLUT.INIT[17] origin:010-clb-lutinit 33_43 +CLBLL_L.SLICEL_X0.CLUT.INIT[18] origin:010-clb-lutinit 32_42 +CLBLL_L.SLICEL_X0.CLUT.INIT[19] origin:010-clb-lutinit 33_42 +CLBLL_L.SLICEL_X0.CLUT.INIT[20] origin:010-clb-lutinit 32_41 +CLBLL_L.SLICEL_X0.CLUT.INIT[21] origin:010-clb-lutinit 33_41 +CLBLL_L.SLICEL_X0.CLUT.INIT[22] origin:010-clb-lutinit 32_40 +CLBLL_L.SLICEL_X0.CLUT.INIT[23] origin:010-clb-lutinit 33_40 +CLBLL_L.SLICEL_X0.CLUT.INIT[24] origin:010-clb-lutinit 35_43 +CLBLL_L.SLICEL_X0.CLUT.INIT[25] origin:010-clb-lutinit 34_43 +CLBLL_L.SLICEL_X0.CLUT.INIT[26] origin:010-clb-lutinit 35_42 +CLBLL_L.SLICEL_X0.CLUT.INIT[27] origin:010-clb-lutinit 34_42 +CLBLL_L.SLICEL_X0.CLUT.INIT[28] origin:010-clb-lutinit 35_41 +CLBLL_L.SLICEL_X0.CLUT.INIT[29] origin:010-clb-lutinit 34_41 +CLBLL_L.SLICEL_X0.CLUT.INIT[30] origin:010-clb-lutinit 35_40 +CLBLL_L.SLICEL_X0.CLUT.INIT[31] origin:010-clb-lutinit 34_40 +CLBLL_L.SLICEL_X0.CLUT.INIT[32] origin:010-clb-lutinit 32_39 +CLBLL_L.SLICEL_X0.CLUT.INIT[33] origin:010-clb-lutinit 33_39 +CLBLL_L.SLICEL_X0.CLUT.INIT[34] origin:010-clb-lutinit 32_38 +CLBLL_L.SLICEL_X0.CLUT.INIT[35] origin:010-clb-lutinit 33_38 +CLBLL_L.SLICEL_X0.CLUT.INIT[36] origin:010-clb-lutinit 32_37 +CLBLL_L.SLICEL_X0.CLUT.INIT[37] origin:010-clb-lutinit 33_37 +CLBLL_L.SLICEL_X0.CLUT.INIT[38] origin:010-clb-lutinit 32_36 +CLBLL_L.SLICEL_X0.CLUT.INIT[39] origin:010-clb-lutinit 33_36 +CLBLL_L.SLICEL_X0.CLUT.INIT[40] origin:010-clb-lutinit 35_39 +CLBLL_L.SLICEL_X0.CLUT.INIT[41] origin:010-clb-lutinit 34_39 +CLBLL_L.SLICEL_X0.CLUT.INIT[42] origin:010-clb-lutinit 35_38 +CLBLL_L.SLICEL_X0.CLUT.INIT[43] origin:010-clb-lutinit 34_38 +CLBLL_L.SLICEL_X0.CLUT.INIT[44] origin:010-clb-lutinit 35_37 +CLBLL_L.SLICEL_X0.CLUT.INIT[45] origin:010-clb-lutinit 34_37 +CLBLL_L.SLICEL_X0.CLUT.INIT[46] origin:010-clb-lutinit 35_36 +CLBLL_L.SLICEL_X0.CLUT.INIT[47] origin:010-clb-lutinit 34_36 +CLBLL_L.SLICEL_X0.CLUT.INIT[48] origin:010-clb-lutinit 32_35 +CLBLL_L.SLICEL_X0.CLUT.INIT[49] origin:010-clb-lutinit 33_35 +CLBLL_L.SLICEL_X0.CLUT.INIT[50] origin:010-clb-lutinit 32_34 +CLBLL_L.SLICEL_X0.CLUT.INIT[51] origin:010-clb-lutinit 33_34 +CLBLL_L.SLICEL_X0.CLUT.INIT[52] origin:010-clb-lutinit 32_33 +CLBLL_L.SLICEL_X0.CLUT.INIT[53] origin:010-clb-lutinit 33_33 +CLBLL_L.SLICEL_X0.CLUT.INIT[54] origin:010-clb-lutinit 32_32 +CLBLL_L.SLICEL_X0.CLUT.INIT[55] origin:010-clb-lutinit 33_32 +CLBLL_L.SLICEL_X0.CLUT.INIT[56] origin:010-clb-lutinit 35_35 +CLBLL_L.SLICEL_X0.CLUT.INIT[57] origin:010-clb-lutinit 34_35 +CLBLL_L.SLICEL_X0.CLUT.INIT[58] origin:010-clb-lutinit 35_34 +CLBLL_L.SLICEL_X0.CLUT.INIT[59] origin:010-clb-lutinit 34_34 +CLBLL_L.SLICEL_X0.CLUT.INIT[60] origin:010-clb-lutinit 35_33 +CLBLL_L.SLICEL_X0.CLUT.INIT[61] origin:010-clb-lutinit 34_33 +CLBLL_L.SLICEL_X0.CLUT.INIT[62] origin:010-clb-lutinit 35_32 +CLBLL_L.SLICEL_X0.CLUT.INIT[63] origin:010-clb-lutinit 34_32 +CLBLL_L.SLICEL_X0.COUTMUX.C5Q origin:016-clb-noutmux !30_40 !30_44 !30_45 30_43 +CLBLL_L.SLICEL_X0.COUTMUX.CY origin:016-clb-noutmux !30_43 !30_45 30_40 30_44 +CLBLL_L.SLICEL_X0.COUTMUX.F7 origin:016-clb-noutmux !30_44 !30_45 30_40 30_43 +CLBLL_L.SLICEL_X0.COUTMUX.O5 origin:016-clb-noutmux !30_43 !30_44 30_40 30_45 +CLBLL_L.SLICEL_X0.COUTMUX.O6 origin:016-clb-noutmux !30_40 !30_43 !30_44 30_45 +CLBLL_L.SLICEL_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44 +CLBLL_L.SLICEL_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51 +CLBLL_L.SLICEL_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55 +CLBLL_L.SLICEL_X0.D5FFMUX.IN_A origin:012-clb-n5ffmux 30_55 +CLBLL_L.SLICEL_X0.D5FFMUX.IN_B origin:012-clb-n5ffmux 30_54 +CLBLL_L.SLICEL_X0.DFF.ZINI origin:011-clb-ffconfig 31_58 +CLBLL_L.SLICEL_X0.DFF.ZRST origin:011-clb-ffconfig 30_50 +CLBLL_L.SLICEL_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62 +CLBLL_L.SLICEL_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61 +CLBLL_L.SLICEL_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62 +CLBLL_L.SLICEL_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59 +CLBLL_L.SLICEL_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60 +CLBLL_L.SLICEL_X0.DLUT.INIT[00] origin:010-clb-lutinit 32_63 +CLBLL_L.SLICEL_X0.DLUT.INIT[01] origin:010-clb-lutinit 33_63 +CLBLL_L.SLICEL_X0.DLUT.INIT[02] origin:010-clb-lutinit 32_62 +CLBLL_L.SLICEL_X0.DLUT.INIT[03] origin:010-clb-lutinit 33_62 +CLBLL_L.SLICEL_X0.DLUT.INIT[04] origin:010-clb-lutinit 32_61 +CLBLL_L.SLICEL_X0.DLUT.INIT[05] origin:010-clb-lutinit 33_61 +CLBLL_L.SLICEL_X0.DLUT.INIT[06] origin:010-clb-lutinit 32_60 +CLBLL_L.SLICEL_X0.DLUT.INIT[07] origin:010-clb-lutinit 33_60 +CLBLL_L.SLICEL_X0.DLUT.INIT[08] origin:010-clb-lutinit 35_63 +CLBLL_L.SLICEL_X0.DLUT.INIT[09] origin:010-clb-lutinit 34_63 +CLBLL_L.SLICEL_X0.DLUT.INIT[10] origin:010-clb-lutinit 35_62 +CLBLL_L.SLICEL_X0.DLUT.INIT[11] origin:010-clb-lutinit 34_62 +CLBLL_L.SLICEL_X0.DLUT.INIT[12] origin:010-clb-lutinit 35_61 +CLBLL_L.SLICEL_X0.DLUT.INIT[13] origin:010-clb-lutinit 34_61 +CLBLL_L.SLICEL_X0.DLUT.INIT[14] origin:010-clb-lutinit 35_60 +CLBLL_L.SLICEL_X0.DLUT.INIT[15] origin:010-clb-lutinit 34_60 +CLBLL_L.SLICEL_X0.DLUT.INIT[16] origin:010-clb-lutinit 32_59 +CLBLL_L.SLICEL_X0.DLUT.INIT[17] origin:010-clb-lutinit 33_59 +CLBLL_L.SLICEL_X0.DLUT.INIT[18] origin:010-clb-lutinit 32_58 +CLBLL_L.SLICEL_X0.DLUT.INIT[19] origin:010-clb-lutinit 33_58 +CLBLL_L.SLICEL_X0.DLUT.INIT[20] origin:010-clb-lutinit 32_57 +CLBLL_L.SLICEL_X0.DLUT.INIT[21] origin:010-clb-lutinit 33_57 +CLBLL_L.SLICEL_X0.DLUT.INIT[22] origin:010-clb-lutinit 32_56 +CLBLL_L.SLICEL_X0.DLUT.INIT[23] origin:010-clb-lutinit 33_56 +CLBLL_L.SLICEL_X0.DLUT.INIT[24] origin:010-clb-lutinit 35_59 +CLBLL_L.SLICEL_X0.DLUT.INIT[25] origin:010-clb-lutinit 34_59 +CLBLL_L.SLICEL_X0.DLUT.INIT[26] origin:010-clb-lutinit 35_58 +CLBLL_L.SLICEL_X0.DLUT.INIT[27] origin:010-clb-lutinit 34_58 +CLBLL_L.SLICEL_X0.DLUT.INIT[28] origin:010-clb-lutinit 35_57 +CLBLL_L.SLICEL_X0.DLUT.INIT[29] origin:010-clb-lutinit 34_57 +CLBLL_L.SLICEL_X0.DLUT.INIT[30] origin:010-clb-lutinit 35_56 +CLBLL_L.SLICEL_X0.DLUT.INIT[31] origin:010-clb-lutinit 34_56 +CLBLL_L.SLICEL_X0.DLUT.INIT[32] origin:010-clb-lutinit 32_55 +CLBLL_L.SLICEL_X0.DLUT.INIT[33] origin:010-clb-lutinit 33_55 +CLBLL_L.SLICEL_X0.DLUT.INIT[34] origin:010-clb-lutinit 32_54 +CLBLL_L.SLICEL_X0.DLUT.INIT[35] origin:010-clb-lutinit 33_54 +CLBLL_L.SLICEL_X0.DLUT.INIT[36] origin:010-clb-lutinit 32_53 +CLBLL_L.SLICEL_X0.DLUT.INIT[37] origin:010-clb-lutinit 33_53 +CLBLL_L.SLICEL_X0.DLUT.INIT[38] origin:010-clb-lutinit 32_52 +CLBLL_L.SLICEL_X0.DLUT.INIT[39] origin:010-clb-lutinit 33_52 +CLBLL_L.SLICEL_X0.DLUT.INIT[40] origin:010-clb-lutinit 35_55 +CLBLL_L.SLICEL_X0.DLUT.INIT[41] origin:010-clb-lutinit 34_55 +CLBLL_L.SLICEL_X0.DLUT.INIT[42] origin:010-clb-lutinit 35_54 +CLBLL_L.SLICEL_X0.DLUT.INIT[43] origin:010-clb-lutinit 34_54 +CLBLL_L.SLICEL_X0.DLUT.INIT[44] origin:010-clb-lutinit 35_53 +CLBLL_L.SLICEL_X0.DLUT.INIT[45] origin:010-clb-lutinit 34_53 +CLBLL_L.SLICEL_X0.DLUT.INIT[46] origin:010-clb-lutinit 35_52 +CLBLL_L.SLICEL_X0.DLUT.INIT[47] origin:010-clb-lutinit 34_52 +CLBLL_L.SLICEL_X0.DLUT.INIT[48] origin:010-clb-lutinit 32_51 +CLBLL_L.SLICEL_X0.DLUT.INIT[49] origin:010-clb-lutinit 33_51 +CLBLL_L.SLICEL_X0.DLUT.INIT[50] origin:010-clb-lutinit 32_50 +CLBLL_L.SLICEL_X0.DLUT.INIT[51] origin:010-clb-lutinit 33_50 +CLBLL_L.SLICEL_X0.DLUT.INIT[52] origin:010-clb-lutinit 32_49 +CLBLL_L.SLICEL_X0.DLUT.INIT[53] origin:010-clb-lutinit 33_49 +CLBLL_L.SLICEL_X0.DLUT.INIT[54] origin:010-clb-lutinit 32_48 +CLBLL_L.SLICEL_X0.DLUT.INIT[55] origin:010-clb-lutinit 33_48 +CLBLL_L.SLICEL_X0.DLUT.INIT[56] origin:010-clb-lutinit 35_51 +CLBLL_L.SLICEL_X0.DLUT.INIT[57] origin:010-clb-lutinit 34_51 +CLBLL_L.SLICEL_X0.DLUT.INIT[58] origin:010-clb-lutinit 35_50 +CLBLL_L.SLICEL_X0.DLUT.INIT[59] origin:010-clb-lutinit 34_50 +CLBLL_L.SLICEL_X0.DLUT.INIT[60] origin:010-clb-lutinit 35_49 +CLBLL_L.SLICEL_X0.DLUT.INIT[61] origin:010-clb-lutinit 34_49 +CLBLL_L.SLICEL_X0.DLUT.INIT[62] origin:010-clb-lutinit 35_48 +CLBLL_L.SLICEL_X0.DLUT.INIT[63] origin:010-clb-lutinit 34_48 +CLBLL_L.SLICEL_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52 +CLBLL_L.SLICEL_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57 +CLBLL_L.SLICEL_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56 +CLBLL_L.SLICEL_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56 +CLBLL_L.SLICEL_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51 +CLBLL_L.SLICEL_X0.FFSYNC origin:011-clb-ffconfig 00_48 +CLBLL_L.SLICEL_X0.LATCH origin:011-clb-ffconfig 30_32 +CLBLL_L.SLICEL_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14 +CLBLL_L.SLICEL_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14 +CLBLL_L.SLICEL_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12 +CLBLL_L.SLICEL_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13 +CLBLL_L.SLICEL_X0.SRUSEDMUX origin:014-clb-ffsrcemux 01_35 +CLBLL_L.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05 +CLBLL_L.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03 +CLBLL_L.SLICEL_X1.A5FFMUX.IN_A origin:012-clb-n5ffmux 31_08 +CLBLL_L.SLICEL_X1.A5FFMUX.IN_B origin:012-clb-n5ffmux 31_11 +CLBLL_L.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04 +CLBLL_L.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15 +CLBLL_L.SLICEL_X1.AFFMUX.AX origin:015-clb-nffmux !30_04 !31_00 !31_02 31_01 +CLBLL_L.SLICEL_X1.AFFMUX.CY origin:015-clb-nffmux !30_04 !31_01 31_00 31_02 +CLBLL_L.SLICEL_X1.AFFMUX.F7 origin:015-clb-nffmux !30_04 !31_02 31_00 31_01 +CLBLL_L.SLICEL_X1.AFFMUX.O5 origin:015-clb-nffmux !31_01 !31_02 30_04 31_00 +CLBLL_L.SLICEL_X1.AFFMUX.O6 origin:015-clb-nffmux !31_00 !31_01 !31_02 30_04 +CLBLL_L.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02 +CLBLL_L.SLICEL_X1.ALUT.INIT[00] origin:010-clb-lutinit 26_15 +CLBLL_L.SLICEL_X1.ALUT.INIT[01] origin:010-clb-lutinit 27_15 +CLBLL_L.SLICEL_X1.ALUT.INIT[02] origin:010-clb-lutinit 26_14 +CLBLL_L.SLICEL_X1.ALUT.INIT[03] origin:010-clb-lutinit 27_14 +CLBLL_L.SLICEL_X1.ALUT.INIT[04] origin:010-clb-lutinit 26_13 +CLBLL_L.SLICEL_X1.ALUT.INIT[05] origin:010-clb-lutinit 27_13 +CLBLL_L.SLICEL_X1.ALUT.INIT[06] origin:010-clb-lutinit 26_12 +CLBLL_L.SLICEL_X1.ALUT.INIT[07] origin:010-clb-lutinit 27_12 +CLBLL_L.SLICEL_X1.ALUT.INIT[08] origin:010-clb-lutinit 29_15 +CLBLL_L.SLICEL_X1.ALUT.INIT[09] origin:010-clb-lutinit 28_15 +CLBLL_L.SLICEL_X1.ALUT.INIT[10] origin:010-clb-lutinit 29_14 +CLBLL_L.SLICEL_X1.ALUT.INIT[11] origin:010-clb-lutinit 28_14 +CLBLL_L.SLICEL_X1.ALUT.INIT[12] origin:010-clb-lutinit 29_13 +CLBLL_L.SLICEL_X1.ALUT.INIT[13] origin:010-clb-lutinit 28_13 +CLBLL_L.SLICEL_X1.ALUT.INIT[14] origin:010-clb-lutinit 29_12 +CLBLL_L.SLICEL_X1.ALUT.INIT[15] origin:010-clb-lutinit 28_12 +CLBLL_L.SLICEL_X1.ALUT.INIT[16] origin:010-clb-lutinit 26_11 +CLBLL_L.SLICEL_X1.ALUT.INIT[17] origin:010-clb-lutinit 27_11 +CLBLL_L.SLICEL_X1.ALUT.INIT[18] origin:010-clb-lutinit 26_10 +CLBLL_L.SLICEL_X1.ALUT.INIT[19] origin:010-clb-lutinit 27_10 +CLBLL_L.SLICEL_X1.ALUT.INIT[20] origin:010-clb-lutinit 26_09 +CLBLL_L.SLICEL_X1.ALUT.INIT[21] origin:010-clb-lutinit 27_09 +CLBLL_L.SLICEL_X1.ALUT.INIT[22] origin:010-clb-lutinit 26_08 +CLBLL_L.SLICEL_X1.ALUT.INIT[23] origin:010-clb-lutinit 27_08 +CLBLL_L.SLICEL_X1.ALUT.INIT[24] origin:010-clb-lutinit 29_11 +CLBLL_L.SLICEL_X1.ALUT.INIT[25] origin:010-clb-lutinit 28_11 +CLBLL_L.SLICEL_X1.ALUT.INIT[26] origin:010-clb-lutinit 29_10 +CLBLL_L.SLICEL_X1.ALUT.INIT[27] origin:010-clb-lutinit 28_10 +CLBLL_L.SLICEL_X1.ALUT.INIT[28] origin:010-clb-lutinit 29_09 +CLBLL_L.SLICEL_X1.ALUT.INIT[29] origin:010-clb-lutinit 28_09 +CLBLL_L.SLICEL_X1.ALUT.INIT[30] origin:010-clb-lutinit 29_08 +CLBLL_L.SLICEL_X1.ALUT.INIT[31] origin:010-clb-lutinit 28_08 +CLBLL_L.SLICEL_X1.ALUT.INIT[32] origin:010-clb-lutinit 26_07 +CLBLL_L.SLICEL_X1.ALUT.INIT[33] origin:010-clb-lutinit 27_07 +CLBLL_L.SLICEL_X1.ALUT.INIT[34] origin:010-clb-lutinit 26_06 +CLBLL_L.SLICEL_X1.ALUT.INIT[35] origin:010-clb-lutinit 27_06 +CLBLL_L.SLICEL_X1.ALUT.INIT[36] origin:010-clb-lutinit 26_05 +CLBLL_L.SLICEL_X1.ALUT.INIT[37] origin:010-clb-lutinit 27_05 +CLBLL_L.SLICEL_X1.ALUT.INIT[38] origin:010-clb-lutinit 26_04 +CLBLL_L.SLICEL_X1.ALUT.INIT[39] origin:010-clb-lutinit 27_04 +CLBLL_L.SLICEL_X1.ALUT.INIT[40] origin:010-clb-lutinit 29_07 +CLBLL_L.SLICEL_X1.ALUT.INIT[41] origin:010-clb-lutinit 28_07 +CLBLL_L.SLICEL_X1.ALUT.INIT[42] origin:010-clb-lutinit 29_06 +CLBLL_L.SLICEL_X1.ALUT.INIT[43] origin:010-clb-lutinit 28_06 +CLBLL_L.SLICEL_X1.ALUT.INIT[44] origin:010-clb-lutinit 29_05 +CLBLL_L.SLICEL_X1.ALUT.INIT[45] origin:010-clb-lutinit 28_05 +CLBLL_L.SLICEL_X1.ALUT.INIT[46] origin:010-clb-lutinit 29_04 +CLBLL_L.SLICEL_X1.ALUT.INIT[47] origin:010-clb-lutinit 28_04 +CLBLL_L.SLICEL_X1.ALUT.INIT[48] origin:010-clb-lutinit 26_03 +CLBLL_L.SLICEL_X1.ALUT.INIT[49] origin:010-clb-lutinit 27_03 +CLBLL_L.SLICEL_X1.ALUT.INIT[50] origin:010-clb-lutinit 26_02 +CLBLL_L.SLICEL_X1.ALUT.INIT[51] origin:010-clb-lutinit 27_02 +CLBLL_L.SLICEL_X1.ALUT.INIT[52] origin:010-clb-lutinit 26_01 +CLBLL_L.SLICEL_X1.ALUT.INIT[53] origin:010-clb-lutinit 27_01 +CLBLL_L.SLICEL_X1.ALUT.INIT[54] origin:010-clb-lutinit 26_00 +CLBLL_L.SLICEL_X1.ALUT.INIT[55] origin:010-clb-lutinit 27_00 +CLBLL_L.SLICEL_X1.ALUT.INIT[56] origin:010-clb-lutinit 29_03 +CLBLL_L.SLICEL_X1.ALUT.INIT[57] origin:010-clb-lutinit 28_03 +CLBLL_L.SLICEL_X1.ALUT.INIT[58] origin:010-clb-lutinit 29_02 +CLBLL_L.SLICEL_X1.ALUT.INIT[59] origin:010-clb-lutinit 28_02 +CLBLL_L.SLICEL_X1.ALUT.INIT[60] origin:010-clb-lutinit 29_01 +CLBLL_L.SLICEL_X1.ALUT.INIT[61] origin:010-clb-lutinit 28_01 +CLBLL_L.SLICEL_X1.ALUT.INIT[62] origin:010-clb-lutinit 29_00 +CLBLL_L.SLICEL_X1.ALUT.INIT[63] origin:010-clb-lutinit 28_00 +CLBLL_L.SLICEL_X1.AOUTMUX.A5Q origin:016-clb-noutmux !31_07 !31_09 !31_10 30_05 +CLBLL_L.SLICEL_X1.AOUTMUX.CY origin:016-clb-noutmux !30_05 !31_09 31_07 31_10 +CLBLL_L.SLICEL_X1.AOUTMUX.F7 origin:016-clb-noutmux !31_07 !31_09 30_05 31_10 +CLBLL_L.SLICEL_X1.AOUTMUX.O5 origin:016-clb-noutmux !30_05 !31_07 31_09 31_10 +CLBLL_L.SLICEL_X1.AOUTMUX.O6 origin:016-clb-noutmux !30_05 !31_07 !31_10 31_09 +CLBLL_L.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07 +CLBLL_L.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23 +CLBLL_L.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16 +CLBLL_L.SLICEL_X1.B5FFMUX.IN_A origin:012-clb-n5ffmux 31_19 +CLBLL_L.SLICEL_X1.B5FFMUX.IN_B origin:012-clb-n5ffmux 31_18 +CLBLL_L.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29 +CLBLL_L.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30 +CLBLL_L.SLICEL_X1.BFFMUX.BX origin:015-clb-nffmux !31_24 !31_25 !31_26 31_27 +CLBLL_L.SLICEL_X1.BFFMUX.CY origin:015-clb-nffmux !31_24 !31_27 31_25 31_26 +CLBLL_L.SLICEL_X1.BFFMUX.F8 origin:015-clb-nffmux !31_24 !31_26 31_25 31_27 +CLBLL_L.SLICEL_X1.BFFMUX.O5 origin:015-clb-nffmux !31_26 !31_27 31_24 31_25 +CLBLL_L.SLICEL_X1.BFFMUX.O6 origin:015-clb-nffmux !31_25 !31_26 !31_27 31_24 +CLBLL_L.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26 +CLBLL_L.SLICEL_X1.BLUT.INIT[00] origin:010-clb-lutinit 26_31 +CLBLL_L.SLICEL_X1.BLUT.INIT[01] origin:010-clb-lutinit 27_31 +CLBLL_L.SLICEL_X1.BLUT.INIT[02] origin:010-clb-lutinit 26_30 +CLBLL_L.SLICEL_X1.BLUT.INIT[03] origin:010-clb-lutinit 27_30 +CLBLL_L.SLICEL_X1.BLUT.INIT[04] origin:010-clb-lutinit 26_29 +CLBLL_L.SLICEL_X1.BLUT.INIT[05] origin:010-clb-lutinit 27_29 +CLBLL_L.SLICEL_X1.BLUT.INIT[06] origin:010-clb-lutinit 26_28 +CLBLL_L.SLICEL_X1.BLUT.INIT[07] origin:010-clb-lutinit 27_28 +CLBLL_L.SLICEL_X1.BLUT.INIT[08] origin:010-clb-lutinit 29_31 +CLBLL_L.SLICEL_X1.BLUT.INIT[09] origin:010-clb-lutinit 28_31 +CLBLL_L.SLICEL_X1.BLUT.INIT[10] origin:010-clb-lutinit 29_30 +CLBLL_L.SLICEL_X1.BLUT.INIT[11] origin:010-clb-lutinit 28_30 +CLBLL_L.SLICEL_X1.BLUT.INIT[12] origin:010-clb-lutinit 29_29 +CLBLL_L.SLICEL_X1.BLUT.INIT[13] origin:010-clb-lutinit 28_29 +CLBLL_L.SLICEL_X1.BLUT.INIT[14] origin:010-clb-lutinit 29_28 +CLBLL_L.SLICEL_X1.BLUT.INIT[15] origin:010-clb-lutinit 28_28 +CLBLL_L.SLICEL_X1.BLUT.INIT[16] origin:010-clb-lutinit 26_27 +CLBLL_L.SLICEL_X1.BLUT.INIT[17] origin:010-clb-lutinit 27_27 +CLBLL_L.SLICEL_X1.BLUT.INIT[18] origin:010-clb-lutinit 26_26 +CLBLL_L.SLICEL_X1.BLUT.INIT[19] origin:010-clb-lutinit 27_26 +CLBLL_L.SLICEL_X1.BLUT.INIT[20] origin:010-clb-lutinit 26_25 +CLBLL_L.SLICEL_X1.BLUT.INIT[21] origin:010-clb-lutinit 27_25 +CLBLL_L.SLICEL_X1.BLUT.INIT[22] origin:010-clb-lutinit 26_24 +CLBLL_L.SLICEL_X1.BLUT.INIT[23] origin:010-clb-lutinit 27_24 +CLBLL_L.SLICEL_X1.BLUT.INIT[24] origin:010-clb-lutinit 29_27 +CLBLL_L.SLICEL_X1.BLUT.INIT[25] origin:010-clb-lutinit 28_27 +CLBLL_L.SLICEL_X1.BLUT.INIT[26] origin:010-clb-lutinit 29_26 +CLBLL_L.SLICEL_X1.BLUT.INIT[27] origin:010-clb-lutinit 28_26 +CLBLL_L.SLICEL_X1.BLUT.INIT[28] origin:010-clb-lutinit 29_25 +CLBLL_L.SLICEL_X1.BLUT.INIT[29] origin:010-clb-lutinit 28_25 +CLBLL_L.SLICEL_X1.BLUT.INIT[30] origin:010-clb-lutinit 29_24 +CLBLL_L.SLICEL_X1.BLUT.INIT[31] origin:010-clb-lutinit 28_24 +CLBLL_L.SLICEL_X1.BLUT.INIT[32] origin:010-clb-lutinit 26_23 +CLBLL_L.SLICEL_X1.BLUT.INIT[33] origin:010-clb-lutinit 27_23 +CLBLL_L.SLICEL_X1.BLUT.INIT[34] origin:010-clb-lutinit 26_22 +CLBLL_L.SLICEL_X1.BLUT.INIT[35] origin:010-clb-lutinit 27_22 +CLBLL_L.SLICEL_X1.BLUT.INIT[36] origin:010-clb-lutinit 26_21 +CLBLL_L.SLICEL_X1.BLUT.INIT[37] origin:010-clb-lutinit 27_21 +CLBLL_L.SLICEL_X1.BLUT.INIT[38] origin:010-clb-lutinit 26_20 +CLBLL_L.SLICEL_X1.BLUT.INIT[39] origin:010-clb-lutinit 27_20 +CLBLL_L.SLICEL_X1.BLUT.INIT[40] origin:010-clb-lutinit 29_23 +CLBLL_L.SLICEL_X1.BLUT.INIT[41] origin:010-clb-lutinit 28_23 +CLBLL_L.SLICEL_X1.BLUT.INIT[42] origin:010-clb-lutinit 29_22 +CLBLL_L.SLICEL_X1.BLUT.INIT[43] origin:010-clb-lutinit 28_22 +CLBLL_L.SLICEL_X1.BLUT.INIT[44] origin:010-clb-lutinit 29_21 +CLBLL_L.SLICEL_X1.BLUT.INIT[45] origin:010-clb-lutinit 28_21 +CLBLL_L.SLICEL_X1.BLUT.INIT[46] origin:010-clb-lutinit 29_20 +CLBLL_L.SLICEL_X1.BLUT.INIT[47] origin:010-clb-lutinit 28_20 +CLBLL_L.SLICEL_X1.BLUT.INIT[48] origin:010-clb-lutinit 26_19 +CLBLL_L.SLICEL_X1.BLUT.INIT[49] origin:010-clb-lutinit 27_19 +CLBLL_L.SLICEL_X1.BLUT.INIT[50] origin:010-clb-lutinit 26_18 +CLBLL_L.SLICEL_X1.BLUT.INIT[51] origin:010-clb-lutinit 27_18 +CLBLL_L.SLICEL_X1.BLUT.INIT[52] origin:010-clb-lutinit 26_17 +CLBLL_L.SLICEL_X1.BLUT.INIT[53] origin:010-clb-lutinit 27_17 +CLBLL_L.SLICEL_X1.BLUT.INIT[54] origin:010-clb-lutinit 26_16 +CLBLL_L.SLICEL_X1.BLUT.INIT[55] origin:010-clb-lutinit 27_16 +CLBLL_L.SLICEL_X1.BLUT.INIT[56] origin:010-clb-lutinit 29_19 +CLBLL_L.SLICEL_X1.BLUT.INIT[57] origin:010-clb-lutinit 28_19 +CLBLL_L.SLICEL_X1.BLUT.INIT[58] origin:010-clb-lutinit 29_18 +CLBLL_L.SLICEL_X1.BLUT.INIT[59] origin:010-clb-lutinit 28_18 +CLBLL_L.SLICEL_X1.BLUT.INIT[60] origin:010-clb-lutinit 29_17 +CLBLL_L.SLICEL_X1.BLUT.INIT[61] origin:010-clb-lutinit 28_17 +CLBLL_L.SLICEL_X1.BLUT.INIT[62] origin:010-clb-lutinit 29_16 +CLBLL_L.SLICEL_X1.BLUT.INIT[63] origin:010-clb-lutinit 28_16 +CLBLL_L.SLICEL_X1.BOUTMUX.B5Q origin:016-clb-noutmux !30_28 !31_20 !31_21 30_29 +CLBLL_L.SLICEL_X1.BOUTMUX.CY origin:016-clb-noutmux !30_29 !31_20 30_28 31_21 +CLBLL_L.SLICEL_X1.BOUTMUX.F8 origin:016-clb-noutmux !30_28 !31_20 30_29 31_21 +CLBLL_L.SLICEL_X1.BOUTMUX.O5 origin:016-clb-noutmux !30_28 !30_29 31_20 31_21 +CLBLL_L.SLICEL_X1.BOUTMUX.O6 origin:016-clb-noutmux !30_28 !30_29 !31_21 31_20 +CLBLL_L.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28 +CLBLL_L.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42 +CLBLL_L.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44 +CLBLL_L.SLICEL_X1.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_44 +CLBLL_L.SLICEL_X1.C5FFMUX.IN_B origin:012-clb-n5ffmux 31_39 +CLBLL_L.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14 +CLBLL_L.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08 +CLBLL_L.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48 +CLBLL_L.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49 +CLBLL_L.SLICEL_X1.CEUSEDMUX origin:014-clb-ffsrcemux 00_36 +CLBLL_L.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34 +CLBLL_L.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34 +CLBLL_L.SLICEL_X1.CFFMUX.CX origin:015-clb-nffmux !31_35 !31_36 !31_37 31_38 +CLBLL_L.SLICEL_X1.CFFMUX.CY origin:015-clb-nffmux !31_36 !31_38 31_35 31_37 +CLBLL_L.SLICEL_X1.CFFMUX.F7 origin:015-clb-nffmux !31_36 !31_37 31_35 31_38 +CLBLL_L.SLICEL_X1.CFFMUX.O5 origin:015-clb-nffmux !31_37 !31_38 31_35 31_36 +CLBLL_L.SLICEL_X1.CFFMUX.O6 origin:015-clb-nffmux !31_35 !31_37 !31_38 31_36 +CLBLL_L.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37 +CLBLL_L.SLICEL_X1.CLKINV origin:011-clb-ffconfig 00_52 +CLBLL_L.SLICEL_X1.CLUT.INIT[00] origin:010-clb-lutinit 26_47 +CLBLL_L.SLICEL_X1.CLUT.INIT[01] origin:010-clb-lutinit 27_47 +CLBLL_L.SLICEL_X1.CLUT.INIT[02] origin:010-clb-lutinit 26_46 +CLBLL_L.SLICEL_X1.CLUT.INIT[03] origin:010-clb-lutinit 27_46 +CLBLL_L.SLICEL_X1.CLUT.INIT[04] origin:010-clb-lutinit 26_45 +CLBLL_L.SLICEL_X1.CLUT.INIT[05] origin:010-clb-lutinit 27_45 +CLBLL_L.SLICEL_X1.CLUT.INIT[06] origin:010-clb-lutinit 26_44 +CLBLL_L.SLICEL_X1.CLUT.INIT[07] origin:010-clb-lutinit 27_44 +CLBLL_L.SLICEL_X1.CLUT.INIT[08] origin:010-clb-lutinit 29_47 +CLBLL_L.SLICEL_X1.CLUT.INIT[09] origin:010-clb-lutinit 28_47 +CLBLL_L.SLICEL_X1.CLUT.INIT[10] origin:010-clb-lutinit 29_46 +CLBLL_L.SLICEL_X1.CLUT.INIT[11] origin:010-clb-lutinit 28_46 +CLBLL_L.SLICEL_X1.CLUT.INIT[12] origin:010-clb-lutinit 29_45 +CLBLL_L.SLICEL_X1.CLUT.INIT[13] origin:010-clb-lutinit 28_45 +CLBLL_L.SLICEL_X1.CLUT.INIT[14] origin:010-clb-lutinit 29_44 +CLBLL_L.SLICEL_X1.CLUT.INIT[15] origin:010-clb-lutinit 28_44 +CLBLL_L.SLICEL_X1.CLUT.INIT[16] origin:010-clb-lutinit 26_43 +CLBLL_L.SLICEL_X1.CLUT.INIT[17] origin:010-clb-lutinit 27_43 +CLBLL_L.SLICEL_X1.CLUT.INIT[18] origin:010-clb-lutinit 26_42 +CLBLL_L.SLICEL_X1.CLUT.INIT[19] origin:010-clb-lutinit 27_42 +CLBLL_L.SLICEL_X1.CLUT.INIT[20] origin:010-clb-lutinit 26_41 +CLBLL_L.SLICEL_X1.CLUT.INIT[21] origin:010-clb-lutinit 27_41 +CLBLL_L.SLICEL_X1.CLUT.INIT[22] origin:010-clb-lutinit 26_40 +CLBLL_L.SLICEL_X1.CLUT.INIT[23] origin:010-clb-lutinit 27_40 +CLBLL_L.SLICEL_X1.CLUT.INIT[24] origin:010-clb-lutinit 29_43 +CLBLL_L.SLICEL_X1.CLUT.INIT[25] origin:010-clb-lutinit 28_43 +CLBLL_L.SLICEL_X1.CLUT.INIT[26] origin:010-clb-lutinit 29_42 +CLBLL_L.SLICEL_X1.CLUT.INIT[27] origin:010-clb-lutinit 28_42 +CLBLL_L.SLICEL_X1.CLUT.INIT[28] origin:010-clb-lutinit 29_41 +CLBLL_L.SLICEL_X1.CLUT.INIT[29] origin:010-clb-lutinit 28_41 +CLBLL_L.SLICEL_X1.CLUT.INIT[30] origin:010-clb-lutinit 29_40 +CLBLL_L.SLICEL_X1.CLUT.INIT[31] origin:010-clb-lutinit 28_40 +CLBLL_L.SLICEL_X1.CLUT.INIT[32] origin:010-clb-lutinit 26_39 +CLBLL_L.SLICEL_X1.CLUT.INIT[33] origin:010-clb-lutinit 27_39 +CLBLL_L.SLICEL_X1.CLUT.INIT[34] origin:010-clb-lutinit 26_38 +CLBLL_L.SLICEL_X1.CLUT.INIT[35] origin:010-clb-lutinit 27_38 +CLBLL_L.SLICEL_X1.CLUT.INIT[36] origin:010-clb-lutinit 26_37 +CLBLL_L.SLICEL_X1.CLUT.INIT[37] origin:010-clb-lutinit 27_37 +CLBLL_L.SLICEL_X1.CLUT.INIT[38] origin:010-clb-lutinit 26_36 +CLBLL_L.SLICEL_X1.CLUT.INIT[39] origin:010-clb-lutinit 27_36 +CLBLL_L.SLICEL_X1.CLUT.INIT[40] origin:010-clb-lutinit 29_39 +CLBLL_L.SLICEL_X1.CLUT.INIT[41] origin:010-clb-lutinit 28_39 +CLBLL_L.SLICEL_X1.CLUT.INIT[42] origin:010-clb-lutinit 29_38 +CLBLL_L.SLICEL_X1.CLUT.INIT[43] origin:010-clb-lutinit 28_38 +CLBLL_L.SLICEL_X1.CLUT.INIT[44] origin:010-clb-lutinit 29_37 +CLBLL_L.SLICEL_X1.CLUT.INIT[45] origin:010-clb-lutinit 28_37 +CLBLL_L.SLICEL_X1.CLUT.INIT[46] origin:010-clb-lutinit 29_36 +CLBLL_L.SLICEL_X1.CLUT.INIT[47] origin:010-clb-lutinit 28_36 +CLBLL_L.SLICEL_X1.CLUT.INIT[48] origin:010-clb-lutinit 26_35 +CLBLL_L.SLICEL_X1.CLUT.INIT[49] origin:010-clb-lutinit 27_35 +CLBLL_L.SLICEL_X1.CLUT.INIT[50] origin:010-clb-lutinit 26_34 +CLBLL_L.SLICEL_X1.CLUT.INIT[51] origin:010-clb-lutinit 27_34 +CLBLL_L.SLICEL_X1.CLUT.INIT[52] origin:010-clb-lutinit 26_33 +CLBLL_L.SLICEL_X1.CLUT.INIT[53] origin:010-clb-lutinit 27_33 +CLBLL_L.SLICEL_X1.CLUT.INIT[54] origin:010-clb-lutinit 26_32 +CLBLL_L.SLICEL_X1.CLUT.INIT[55] origin:010-clb-lutinit 27_32 +CLBLL_L.SLICEL_X1.CLUT.INIT[56] origin:010-clb-lutinit 29_35 +CLBLL_L.SLICEL_X1.CLUT.INIT[57] origin:010-clb-lutinit 28_35 +CLBLL_L.SLICEL_X1.CLUT.INIT[58] origin:010-clb-lutinit 29_34 +CLBLL_L.SLICEL_X1.CLUT.INIT[59] origin:010-clb-lutinit 28_34 +CLBLL_L.SLICEL_X1.CLUT.INIT[60] origin:010-clb-lutinit 29_33 +CLBLL_L.SLICEL_X1.CLUT.INIT[61] origin:010-clb-lutinit 28_33 +CLBLL_L.SLICEL_X1.CLUT.INIT[62] origin:010-clb-lutinit 29_32 +CLBLL_L.SLICEL_X1.CLUT.INIT[63] origin:010-clb-lutinit 28_32 +CLBLL_L.SLICEL_X1.COUTMUX.C5Q origin:016-clb-noutmux !30_42 !31_40 !31_43 30_41 +CLBLL_L.SLICEL_X1.COUTMUX.CY origin:016-clb-noutmux !30_41 !31_43 30_42 31_40 +CLBLL_L.SLICEL_X1.COUTMUX.F7 origin:016-clb-noutmux !30_42 !31_43 30_41 31_40 +CLBLL_L.SLICEL_X1.COUTMUX.O5 origin:016-clb-noutmux !30_41 !30_42 31_40 31_43 +CLBLL_L.SLICEL_X1.COUTMUX.O6 origin:016-clb-noutmux !30_41 !30_42 !31_40 31_43 +CLBLL_L.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42 +CLBLL_L.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52 +CLBLL_L.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56 +CLBLL_L.SLICEL_X1.D5FFMUX.IN_A origin:012-clb-n5ffmux 31_55 +CLBLL_L.SLICEL_X1.D5FFMUX.IN_B origin:012-clb-n5ffmux 31_54 +CLBLL_L.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59 +CLBLL_L.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50 +CLBLL_L.SLICEL_X1.DFFMUX.CY origin:015-clb-nffmux !31_60 !31_61 30_58 31_62 +CLBLL_L.SLICEL_X1.DFFMUX.DX origin:015-clb-nffmux !30_58 !31_60 !31_62 31_61 +CLBLL_L.SLICEL_X1.DFFMUX.O5 origin:015-clb-nffmux !31_61 !31_62 30_58 31_60 +CLBLL_L.SLICEL_X1.DFFMUX.O6 origin:015-clb-nffmux !30_58 !31_61 !31_62 31_60 +CLBLL_L.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62 +CLBLL_L.SLICEL_X1.DLUT.INIT[00] origin:010-clb-lutinit 26_63 +CLBLL_L.SLICEL_X1.DLUT.INIT[01] origin:010-clb-lutinit 27_63 +CLBLL_L.SLICEL_X1.DLUT.INIT[02] origin:010-clb-lutinit 26_62 +CLBLL_L.SLICEL_X1.DLUT.INIT[03] origin:010-clb-lutinit 27_62 +CLBLL_L.SLICEL_X1.DLUT.INIT[04] origin:010-clb-lutinit 26_61 +CLBLL_L.SLICEL_X1.DLUT.INIT[05] origin:010-clb-lutinit 27_61 +CLBLL_L.SLICEL_X1.DLUT.INIT[06] origin:010-clb-lutinit 26_60 +CLBLL_L.SLICEL_X1.DLUT.INIT[07] origin:010-clb-lutinit 27_60 +CLBLL_L.SLICEL_X1.DLUT.INIT[08] origin:010-clb-lutinit 29_63 +CLBLL_L.SLICEL_X1.DLUT.INIT[09] origin:010-clb-lutinit 28_63 +CLBLL_L.SLICEL_X1.DLUT.INIT[10] origin:010-clb-lutinit 29_62 +CLBLL_L.SLICEL_X1.DLUT.INIT[11] origin:010-clb-lutinit 28_62 +CLBLL_L.SLICEL_X1.DLUT.INIT[12] origin:010-clb-lutinit 29_61 +CLBLL_L.SLICEL_X1.DLUT.INIT[13] origin:010-clb-lutinit 28_61 +CLBLL_L.SLICEL_X1.DLUT.INIT[14] origin:010-clb-lutinit 29_60 +CLBLL_L.SLICEL_X1.DLUT.INIT[15] origin:010-clb-lutinit 28_60 +CLBLL_L.SLICEL_X1.DLUT.INIT[16] origin:010-clb-lutinit 26_59 +CLBLL_L.SLICEL_X1.DLUT.INIT[17] origin:010-clb-lutinit 27_59 +CLBLL_L.SLICEL_X1.DLUT.INIT[18] origin:010-clb-lutinit 26_58 +CLBLL_L.SLICEL_X1.DLUT.INIT[19] origin:010-clb-lutinit 27_58 +CLBLL_L.SLICEL_X1.DLUT.INIT[20] origin:010-clb-lutinit 26_57 +CLBLL_L.SLICEL_X1.DLUT.INIT[21] origin:010-clb-lutinit 27_57 +CLBLL_L.SLICEL_X1.DLUT.INIT[22] origin:010-clb-lutinit 26_56 +CLBLL_L.SLICEL_X1.DLUT.INIT[23] origin:010-clb-lutinit 27_56 +CLBLL_L.SLICEL_X1.DLUT.INIT[24] origin:010-clb-lutinit 29_59 +CLBLL_L.SLICEL_X1.DLUT.INIT[25] origin:010-clb-lutinit 28_59 +CLBLL_L.SLICEL_X1.DLUT.INIT[26] origin:010-clb-lutinit 29_58 +CLBLL_L.SLICEL_X1.DLUT.INIT[27] origin:010-clb-lutinit 28_58 +CLBLL_L.SLICEL_X1.DLUT.INIT[28] origin:010-clb-lutinit 29_57 +CLBLL_L.SLICEL_X1.DLUT.INIT[29] origin:010-clb-lutinit 28_57 +CLBLL_L.SLICEL_X1.DLUT.INIT[30] origin:010-clb-lutinit 29_56 +CLBLL_L.SLICEL_X1.DLUT.INIT[31] origin:010-clb-lutinit 28_56 +CLBLL_L.SLICEL_X1.DLUT.INIT[32] origin:010-clb-lutinit 26_55 +CLBLL_L.SLICEL_X1.DLUT.INIT[33] origin:010-clb-lutinit 27_55 +CLBLL_L.SLICEL_X1.DLUT.INIT[34] origin:010-clb-lutinit 26_54 +CLBLL_L.SLICEL_X1.DLUT.INIT[35] origin:010-clb-lutinit 27_54 +CLBLL_L.SLICEL_X1.DLUT.INIT[36] origin:010-clb-lutinit 26_53 +CLBLL_L.SLICEL_X1.DLUT.INIT[37] origin:010-clb-lutinit 27_53 +CLBLL_L.SLICEL_X1.DLUT.INIT[38] origin:010-clb-lutinit 26_52 +CLBLL_L.SLICEL_X1.DLUT.INIT[39] origin:010-clb-lutinit 27_52 +CLBLL_L.SLICEL_X1.DLUT.INIT[40] origin:010-clb-lutinit 29_55 +CLBLL_L.SLICEL_X1.DLUT.INIT[41] origin:010-clb-lutinit 28_55 +CLBLL_L.SLICEL_X1.DLUT.INIT[42] origin:010-clb-lutinit 29_54 +CLBLL_L.SLICEL_X1.DLUT.INIT[43] origin:010-clb-lutinit 28_54 +CLBLL_L.SLICEL_X1.DLUT.INIT[44] origin:010-clb-lutinit 29_53 +CLBLL_L.SLICEL_X1.DLUT.INIT[45] origin:010-clb-lutinit 28_53 +CLBLL_L.SLICEL_X1.DLUT.INIT[46] origin:010-clb-lutinit 29_52 +CLBLL_L.SLICEL_X1.DLUT.INIT[47] origin:010-clb-lutinit 28_52 +CLBLL_L.SLICEL_X1.DLUT.INIT[48] origin:010-clb-lutinit 26_51 +CLBLL_L.SLICEL_X1.DLUT.INIT[49] origin:010-clb-lutinit 27_51 +CLBLL_L.SLICEL_X1.DLUT.INIT[50] origin:010-clb-lutinit 26_50 +CLBLL_L.SLICEL_X1.DLUT.INIT[51] origin:010-clb-lutinit 27_50 +CLBLL_L.SLICEL_X1.DLUT.INIT[52] origin:010-clb-lutinit 26_49 +CLBLL_L.SLICEL_X1.DLUT.INIT[53] origin:010-clb-lutinit 27_49 +CLBLL_L.SLICEL_X1.DLUT.INIT[54] origin:010-clb-lutinit 26_48 +CLBLL_L.SLICEL_X1.DLUT.INIT[55] origin:010-clb-lutinit 27_48 +CLBLL_L.SLICEL_X1.DLUT.INIT[56] origin:010-clb-lutinit 29_51 +CLBLL_L.SLICEL_X1.DLUT.INIT[57] origin:010-clb-lutinit 28_51 +CLBLL_L.SLICEL_X1.DLUT.INIT[58] origin:010-clb-lutinit 29_50 +CLBLL_L.SLICEL_X1.DLUT.INIT[59] origin:010-clb-lutinit 28_50 +CLBLL_L.SLICEL_X1.DLUT.INIT[60] origin:010-clb-lutinit 29_49 +CLBLL_L.SLICEL_X1.DLUT.INIT[61] origin:010-clb-lutinit 28_49 +CLBLL_L.SLICEL_X1.DLUT.INIT[62] origin:010-clb-lutinit 29_48 +CLBLL_L.SLICEL_X1.DLUT.INIT[63] origin:010-clb-lutinit 28_48 +CLBLL_L.SLICEL_X1.DOUTMUX.CY origin:016-clb-noutmux !31_53 !31_56 30_53 31_57 +CLBLL_L.SLICEL_X1.DOUTMUX.D5Q origin:016-clb-noutmux !30_53 !31_56 !31_57 31_53 +CLBLL_L.SLICEL_X1.DOUTMUX.O5 origin:016-clb-noutmux !30_53 !31_53 31_56 31_57 +CLBLL_L.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56 +CLBLL_L.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53 +CLBLL_L.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31 +CLBLL_L.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32 +CLBLL_L.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13 +CLBLL_L.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13 +CLBLL_L.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11 +CLBLL_L.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12 +CLBLL_L.SLICEL_X1.SRUSEDMUX origin:014-clb-ffsrcemux 00_32 diff --git a/zynq7/segbits_clbll_r.origin_info.db b/zynq7/segbits_clbll_r.origin_info.db new file mode 100644 index 0000000..522bb1e --- /dev/null +++ b/zynq7/segbits_clbll_r.origin_info.db @@ -0,0 +1,678 @@ +CLBLL_R.SLICEL_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06 +CLBLL_R.SLICEL_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07 +CLBLL_R.SLICEL_X0.A5FFMUX.IN_A origin:012-clb-n5ffmux 30_09 +CLBLL_R.SLICEL_X0.A5FFMUX.IN_B origin:012-clb-n5ffmux 30_10 +CLBLL_R.SLICEL_X0.AFF.ZINI origin:011-clb-ffconfig 31_03 +CLBLL_R.SLICEL_X0.AFF.ZRST origin:011-clb-ffconfig 30_12 +CLBLL_R.SLICEL_X0.AFFMUX.AX origin:015-clb-nffmux !30_00 !30_02 !30_03 30_01 +CLBLL_R.SLICEL_X0.AFFMUX.CY origin:015-clb-nffmux !30_01 !30_03 30_00 30_02 +CLBLL_R.SLICEL_X0.AFFMUX.F7 origin:015-clb-nffmux !30_02 !30_03 30_00 30_01 +CLBLL_R.SLICEL_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03 +CLBLL_R.SLICEL_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03 +CLBLL_R.SLICEL_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02 +CLBLL_R.SLICEL_X0.ALUT.INIT[00] origin:010-clb-lutinit 32_15 +CLBLL_R.SLICEL_X0.ALUT.INIT[01] origin:010-clb-lutinit 33_15 +CLBLL_R.SLICEL_X0.ALUT.INIT[02] origin:010-clb-lutinit 32_14 +CLBLL_R.SLICEL_X0.ALUT.INIT[03] origin:010-clb-lutinit 33_14 +CLBLL_R.SLICEL_X0.ALUT.INIT[04] origin:010-clb-lutinit 32_13 +CLBLL_R.SLICEL_X0.ALUT.INIT[05] origin:010-clb-lutinit 33_13 +CLBLL_R.SLICEL_X0.ALUT.INIT[06] origin:010-clb-lutinit 32_12 +CLBLL_R.SLICEL_X0.ALUT.INIT[07] origin:010-clb-lutinit 33_12 +CLBLL_R.SLICEL_X0.ALUT.INIT[08] origin:010-clb-lutinit 35_15 +CLBLL_R.SLICEL_X0.ALUT.INIT[09] origin:010-clb-lutinit 34_15 +CLBLL_R.SLICEL_X0.ALUT.INIT[10] origin:010-clb-lutinit 35_14 +CLBLL_R.SLICEL_X0.ALUT.INIT[11] origin:010-clb-lutinit 34_14 +CLBLL_R.SLICEL_X0.ALUT.INIT[12] origin:010-clb-lutinit 35_13 +CLBLL_R.SLICEL_X0.ALUT.INIT[13] origin:010-clb-lutinit 34_13 +CLBLL_R.SLICEL_X0.ALUT.INIT[14] origin:010-clb-lutinit 35_12 +CLBLL_R.SLICEL_X0.ALUT.INIT[15] origin:010-clb-lutinit 34_12 +CLBLL_R.SLICEL_X0.ALUT.INIT[16] origin:010-clb-lutinit 32_11 +CLBLL_R.SLICEL_X0.ALUT.INIT[17] origin:010-clb-lutinit 33_11 +CLBLL_R.SLICEL_X0.ALUT.INIT[18] origin:010-clb-lutinit 32_10 +CLBLL_R.SLICEL_X0.ALUT.INIT[19] origin:010-clb-lutinit 33_10 +CLBLL_R.SLICEL_X0.ALUT.INIT[20] origin:010-clb-lutinit 32_09 +CLBLL_R.SLICEL_X0.ALUT.INIT[21] origin:010-clb-lutinit 33_09 +CLBLL_R.SLICEL_X0.ALUT.INIT[22] origin:010-clb-lutinit 32_08 +CLBLL_R.SLICEL_X0.ALUT.INIT[23] origin:010-clb-lutinit 33_08 +CLBLL_R.SLICEL_X0.ALUT.INIT[24] origin:010-clb-lutinit 35_11 +CLBLL_R.SLICEL_X0.ALUT.INIT[25] origin:010-clb-lutinit 34_11 +CLBLL_R.SLICEL_X0.ALUT.INIT[26] origin:010-clb-lutinit 35_10 +CLBLL_R.SLICEL_X0.ALUT.INIT[27] origin:010-clb-lutinit 34_10 +CLBLL_R.SLICEL_X0.ALUT.INIT[28] origin:010-clb-lutinit 35_09 +CLBLL_R.SLICEL_X0.ALUT.INIT[29] origin:010-clb-lutinit 34_09 +CLBLL_R.SLICEL_X0.ALUT.INIT[30] origin:010-clb-lutinit 35_08 +CLBLL_R.SLICEL_X0.ALUT.INIT[31] origin:010-clb-lutinit 34_08 +CLBLL_R.SLICEL_X0.ALUT.INIT[32] origin:010-clb-lutinit 32_07 +CLBLL_R.SLICEL_X0.ALUT.INIT[33] origin:010-clb-lutinit 33_07 +CLBLL_R.SLICEL_X0.ALUT.INIT[34] origin:010-clb-lutinit 32_06 +CLBLL_R.SLICEL_X0.ALUT.INIT[35] origin:010-clb-lutinit 33_06 +CLBLL_R.SLICEL_X0.ALUT.INIT[36] origin:010-clb-lutinit 32_05 +CLBLL_R.SLICEL_X0.ALUT.INIT[37] origin:010-clb-lutinit 33_05 +CLBLL_R.SLICEL_X0.ALUT.INIT[38] origin:010-clb-lutinit 32_04 +CLBLL_R.SLICEL_X0.ALUT.INIT[39] origin:010-clb-lutinit 33_04 +CLBLL_R.SLICEL_X0.ALUT.INIT[40] origin:010-clb-lutinit 35_07 +CLBLL_R.SLICEL_X0.ALUT.INIT[41] origin:010-clb-lutinit 34_07 +CLBLL_R.SLICEL_X0.ALUT.INIT[42] origin:010-clb-lutinit 35_06 +CLBLL_R.SLICEL_X0.ALUT.INIT[43] origin:010-clb-lutinit 34_06 +CLBLL_R.SLICEL_X0.ALUT.INIT[44] origin:010-clb-lutinit 35_05 +CLBLL_R.SLICEL_X0.ALUT.INIT[45] origin:010-clb-lutinit 34_05 +CLBLL_R.SLICEL_X0.ALUT.INIT[46] origin:010-clb-lutinit 35_04 +CLBLL_R.SLICEL_X0.ALUT.INIT[47] origin:010-clb-lutinit 34_04 +CLBLL_R.SLICEL_X0.ALUT.INIT[48] origin:010-clb-lutinit 32_03 +CLBLL_R.SLICEL_X0.ALUT.INIT[49] origin:010-clb-lutinit 33_03 +CLBLL_R.SLICEL_X0.ALUT.INIT[50] origin:010-clb-lutinit 32_02 +CLBLL_R.SLICEL_X0.ALUT.INIT[51] origin:010-clb-lutinit 33_02 +CLBLL_R.SLICEL_X0.ALUT.INIT[52] origin:010-clb-lutinit 32_01 +CLBLL_R.SLICEL_X0.ALUT.INIT[53] origin:010-clb-lutinit 33_01 +CLBLL_R.SLICEL_X0.ALUT.INIT[54] origin:010-clb-lutinit 32_00 +CLBLL_R.SLICEL_X0.ALUT.INIT[55] origin:010-clb-lutinit 33_00 +CLBLL_R.SLICEL_X0.ALUT.INIT[56] origin:010-clb-lutinit 35_03 +CLBLL_R.SLICEL_X0.ALUT.INIT[57] origin:010-clb-lutinit 34_03 +CLBLL_R.SLICEL_X0.ALUT.INIT[58] origin:010-clb-lutinit 35_02 +CLBLL_R.SLICEL_X0.ALUT.INIT[59] origin:010-clb-lutinit 34_02 +CLBLL_R.SLICEL_X0.ALUT.INIT[60] origin:010-clb-lutinit 35_01 +CLBLL_R.SLICEL_X0.ALUT.INIT[61] origin:010-clb-lutinit 34_01 +CLBLL_R.SLICEL_X0.ALUT.INIT[62] origin:010-clb-lutinit 35_00 +CLBLL_R.SLICEL_X0.ALUT.INIT[63] origin:010-clb-lutinit 34_00 +CLBLL_R.SLICEL_X0.AOUTMUX.A5Q origin:016-clb-noutmux !30_06 !30_08 !30_11 30_07 +CLBLL_R.SLICEL_X0.AOUTMUX.CY origin:016-clb-noutmux !30_07 !30_11 30_06 30_08 +CLBLL_R.SLICEL_X0.AOUTMUX.F7 origin:016-clb-noutmux !30_08 !30_11 30_06 30_07 +CLBLL_R.SLICEL_X0.AOUTMUX.O5 origin:016-clb-noutmux !30_07 !30_08 30_06 30_11 +CLBLL_R.SLICEL_X0.AOUTMUX.O6 origin:016-clb-noutmux !30_06 !30_07 !30_08 30_11 +CLBLL_R.SLICEL_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08 +CLBLL_R.SLICEL_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22 +CLBLL_R.SLICEL_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19 +CLBLL_R.SLICEL_X0.B5FFMUX.IN_A origin:012-clb-n5ffmux 30_19 +CLBLL_R.SLICEL_X0.B5FFMUX.IN_B origin:012-clb-n5ffmux 30_18 +CLBLL_R.SLICEL_X0.BFF.ZINI origin:011-clb-ffconfig 31_28 +CLBLL_R.SLICEL_X0.BFF.ZRST origin:011-clb-ffconfig 30_30 +CLBLL_R.SLICEL_X0.BFFMUX.BX origin:015-clb-nffmux !30_24 !30_25 !30_27 30_26 +CLBLL_R.SLICEL_X0.BFFMUX.CY origin:015-clb-nffmux !30_24 !30_26 30_25 30_27 +CLBLL_R.SLICEL_X0.BFFMUX.F8 origin:015-clb-nffmux !30_24 !30_25 30_26 30_27 +CLBLL_R.SLICEL_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27 +CLBLL_R.SLICEL_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24 +CLBLL_R.SLICEL_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25 +CLBLL_R.SLICEL_X0.BLUT.INIT[00] origin:010-clb-lutinit 32_31 +CLBLL_R.SLICEL_X0.BLUT.INIT[01] origin:010-clb-lutinit 33_31 +CLBLL_R.SLICEL_X0.BLUT.INIT[02] origin:010-clb-lutinit 32_30 +CLBLL_R.SLICEL_X0.BLUT.INIT[03] origin:010-clb-lutinit 33_30 +CLBLL_R.SLICEL_X0.BLUT.INIT[04] origin:010-clb-lutinit 32_29 +CLBLL_R.SLICEL_X0.BLUT.INIT[05] origin:010-clb-lutinit 33_29 +CLBLL_R.SLICEL_X0.BLUT.INIT[06] origin:010-clb-lutinit 32_28 +CLBLL_R.SLICEL_X0.BLUT.INIT[07] origin:010-clb-lutinit 33_28 +CLBLL_R.SLICEL_X0.BLUT.INIT[08] origin:010-clb-lutinit 35_31 +CLBLL_R.SLICEL_X0.BLUT.INIT[09] origin:010-clb-lutinit 34_31 +CLBLL_R.SLICEL_X0.BLUT.INIT[10] origin:010-clb-lutinit 35_30 +CLBLL_R.SLICEL_X0.BLUT.INIT[11] origin:010-clb-lutinit 34_30 +CLBLL_R.SLICEL_X0.BLUT.INIT[12] origin:010-clb-lutinit 35_29 +CLBLL_R.SLICEL_X0.BLUT.INIT[13] origin:010-clb-lutinit 34_29 +CLBLL_R.SLICEL_X0.BLUT.INIT[14] origin:010-clb-lutinit 35_28 +CLBLL_R.SLICEL_X0.BLUT.INIT[15] origin:010-clb-lutinit 34_28 +CLBLL_R.SLICEL_X0.BLUT.INIT[16] origin:010-clb-lutinit 32_27 +CLBLL_R.SLICEL_X0.BLUT.INIT[17] origin:010-clb-lutinit 33_27 +CLBLL_R.SLICEL_X0.BLUT.INIT[18] origin:010-clb-lutinit 32_26 +CLBLL_R.SLICEL_X0.BLUT.INIT[19] origin:010-clb-lutinit 33_26 +CLBLL_R.SLICEL_X0.BLUT.INIT[20] origin:010-clb-lutinit 32_25 +CLBLL_R.SLICEL_X0.BLUT.INIT[21] origin:010-clb-lutinit 33_25 +CLBLL_R.SLICEL_X0.BLUT.INIT[22] origin:010-clb-lutinit 32_24 +CLBLL_R.SLICEL_X0.BLUT.INIT[23] origin:010-clb-lutinit 33_24 +CLBLL_R.SLICEL_X0.BLUT.INIT[24] origin:010-clb-lutinit 35_27 +CLBLL_R.SLICEL_X0.BLUT.INIT[25] origin:010-clb-lutinit 34_27 +CLBLL_R.SLICEL_X0.BLUT.INIT[26] origin:010-clb-lutinit 35_26 +CLBLL_R.SLICEL_X0.BLUT.INIT[27] origin:010-clb-lutinit 34_26 +CLBLL_R.SLICEL_X0.BLUT.INIT[28] origin:010-clb-lutinit 35_25 +CLBLL_R.SLICEL_X0.BLUT.INIT[29] origin:010-clb-lutinit 34_25 +CLBLL_R.SLICEL_X0.BLUT.INIT[30] origin:010-clb-lutinit 35_24 +CLBLL_R.SLICEL_X0.BLUT.INIT[31] origin:010-clb-lutinit 34_24 +CLBLL_R.SLICEL_X0.BLUT.INIT[32] origin:010-clb-lutinit 32_23 +CLBLL_R.SLICEL_X0.BLUT.INIT[33] origin:010-clb-lutinit 33_23 +CLBLL_R.SLICEL_X0.BLUT.INIT[34] origin:010-clb-lutinit 32_22 +CLBLL_R.SLICEL_X0.BLUT.INIT[35] origin:010-clb-lutinit 33_22 +CLBLL_R.SLICEL_X0.BLUT.INIT[36] origin:010-clb-lutinit 32_21 +CLBLL_R.SLICEL_X0.BLUT.INIT[37] origin:010-clb-lutinit 33_21 +CLBLL_R.SLICEL_X0.BLUT.INIT[38] origin:010-clb-lutinit 32_20 +CLBLL_R.SLICEL_X0.BLUT.INIT[39] origin:010-clb-lutinit 33_20 +CLBLL_R.SLICEL_X0.BLUT.INIT[40] origin:010-clb-lutinit 35_23 +CLBLL_R.SLICEL_X0.BLUT.INIT[41] origin:010-clb-lutinit 34_23 +CLBLL_R.SLICEL_X0.BLUT.INIT[42] origin:010-clb-lutinit 35_22 +CLBLL_R.SLICEL_X0.BLUT.INIT[43] origin:010-clb-lutinit 34_22 +CLBLL_R.SLICEL_X0.BLUT.INIT[44] origin:010-clb-lutinit 35_21 +CLBLL_R.SLICEL_X0.BLUT.INIT[45] origin:010-clb-lutinit 34_21 +CLBLL_R.SLICEL_X0.BLUT.INIT[46] origin:010-clb-lutinit 35_20 +CLBLL_R.SLICEL_X0.BLUT.INIT[47] origin:010-clb-lutinit 34_20 +CLBLL_R.SLICEL_X0.BLUT.INIT[48] origin:010-clb-lutinit 32_19 +CLBLL_R.SLICEL_X0.BLUT.INIT[49] origin:010-clb-lutinit 33_19 +CLBLL_R.SLICEL_X0.BLUT.INIT[50] origin:010-clb-lutinit 32_18 +CLBLL_R.SLICEL_X0.BLUT.INIT[51] origin:010-clb-lutinit 33_18 +CLBLL_R.SLICEL_X0.BLUT.INIT[52] origin:010-clb-lutinit 32_17 +CLBLL_R.SLICEL_X0.BLUT.INIT[53] origin:010-clb-lutinit 33_17 +CLBLL_R.SLICEL_X0.BLUT.INIT[54] origin:010-clb-lutinit 32_16 +CLBLL_R.SLICEL_X0.BLUT.INIT[55] origin:010-clb-lutinit 33_16 +CLBLL_R.SLICEL_X0.BLUT.INIT[56] origin:010-clb-lutinit 35_19 +CLBLL_R.SLICEL_X0.BLUT.INIT[57] origin:010-clb-lutinit 34_19 +CLBLL_R.SLICEL_X0.BLUT.INIT[58] origin:010-clb-lutinit 35_18 +CLBLL_R.SLICEL_X0.BLUT.INIT[59] origin:010-clb-lutinit 34_18 +CLBLL_R.SLICEL_X0.BLUT.INIT[60] origin:010-clb-lutinit 35_17 +CLBLL_R.SLICEL_X0.BLUT.INIT[61] origin:010-clb-lutinit 34_17 +CLBLL_R.SLICEL_X0.BLUT.INIT[62] origin:010-clb-lutinit 35_16 +CLBLL_R.SLICEL_X0.BLUT.INIT[63] origin:010-clb-lutinit 34_16 +CLBLL_R.SLICEL_X0.BOUTMUX.B5Q origin:016-clb-noutmux !30_20 !30_21 !30_22 30_23 +CLBLL_R.SLICEL_X0.BOUTMUX.CY origin:016-clb-noutmux !30_20 !30_23 30_21 30_22 +CLBLL_R.SLICEL_X0.BOUTMUX.F8 origin:016-clb-noutmux !30_20 !30_21 30_22 30_23 +CLBLL_R.SLICEL_X0.BOUTMUX.O5 origin:016-clb-noutmux !30_21 !30_23 30_20 30_22 +CLBLL_R.SLICEL_X0.BOUTMUX.O6 origin:016-clb-noutmux !30_21 !30_22 !30_23 30_20 +CLBLL_R.SLICEL_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21 +CLBLL_R.SLICEL_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41 +CLBLL_R.SLICEL_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47 +CLBLL_R.SLICEL_X0.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_45 +CLBLL_R.SLICEL_X0.C5FFMUX.IN_B origin:012-clb-n5ffmux 30_39 +CLBLL_R.SLICEL_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15 +CLBLL_R.SLICEL_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15 +CLBLL_R.SLICEL_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48 +CLBLL_R.SLICEL_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49 +CLBLL_R.SLICEL_X0.CEUSEDMUX origin:014-clb-ffsrcemux 01_39 +CLBLL_R.SLICEL_X0.CFF.ZINI origin:011-clb-ffconfig 31_33 +CLBLL_R.SLICEL_X0.CFF.ZRST origin:011-clb-ffconfig 30_33 +CLBLL_R.SLICEL_X0.CFFMUX.CX origin:015-clb-nffmux !30_35 !30_37 !30_38 30_36 +CLBLL_R.SLICEL_X0.CFFMUX.CY origin:015-clb-nffmux !30_36 !30_38 30_35 30_37 +CLBLL_R.SLICEL_X0.CFFMUX.F7 origin:015-clb-nffmux !30_37 !30_38 30_35 30_36 +CLBLL_R.SLICEL_X0.CFFMUX.O5 origin:015-clb-nffmux !30_36 !30_37 30_35 30_38 +CLBLL_R.SLICEL_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38 +CLBLL_R.SLICEL_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37 +CLBLL_R.SLICEL_X0.CLKINV origin:011-clb-ffconfig 01_51 +CLBLL_R.SLICEL_X0.CLUT.INIT[00] origin:010-clb-lutinit 32_47 +CLBLL_R.SLICEL_X0.CLUT.INIT[01] origin:010-clb-lutinit 33_47 +CLBLL_R.SLICEL_X0.CLUT.INIT[02] origin:010-clb-lutinit 32_46 +CLBLL_R.SLICEL_X0.CLUT.INIT[03] origin:010-clb-lutinit 33_46 +CLBLL_R.SLICEL_X0.CLUT.INIT[04] origin:010-clb-lutinit 32_45 +CLBLL_R.SLICEL_X0.CLUT.INIT[05] origin:010-clb-lutinit 33_45 +CLBLL_R.SLICEL_X0.CLUT.INIT[06] origin:010-clb-lutinit 32_44 +CLBLL_R.SLICEL_X0.CLUT.INIT[07] origin:010-clb-lutinit 33_44 +CLBLL_R.SLICEL_X0.CLUT.INIT[08] origin:010-clb-lutinit 35_47 +CLBLL_R.SLICEL_X0.CLUT.INIT[09] origin:010-clb-lutinit 34_47 +CLBLL_R.SLICEL_X0.CLUT.INIT[10] origin:010-clb-lutinit 35_46 +CLBLL_R.SLICEL_X0.CLUT.INIT[11] origin:010-clb-lutinit 34_46 +CLBLL_R.SLICEL_X0.CLUT.INIT[12] origin:010-clb-lutinit 35_45 +CLBLL_R.SLICEL_X0.CLUT.INIT[13] origin:010-clb-lutinit 34_45 +CLBLL_R.SLICEL_X0.CLUT.INIT[14] origin:010-clb-lutinit 35_44 +CLBLL_R.SLICEL_X0.CLUT.INIT[15] origin:010-clb-lutinit 34_44 +CLBLL_R.SLICEL_X0.CLUT.INIT[16] origin:010-clb-lutinit 32_43 +CLBLL_R.SLICEL_X0.CLUT.INIT[17] origin:010-clb-lutinit 33_43 +CLBLL_R.SLICEL_X0.CLUT.INIT[18] origin:010-clb-lutinit 32_42 +CLBLL_R.SLICEL_X0.CLUT.INIT[19] origin:010-clb-lutinit 33_42 +CLBLL_R.SLICEL_X0.CLUT.INIT[20] origin:010-clb-lutinit 32_41 +CLBLL_R.SLICEL_X0.CLUT.INIT[21] origin:010-clb-lutinit 33_41 +CLBLL_R.SLICEL_X0.CLUT.INIT[22] origin:010-clb-lutinit 32_40 +CLBLL_R.SLICEL_X0.CLUT.INIT[23] origin:010-clb-lutinit 33_40 +CLBLL_R.SLICEL_X0.CLUT.INIT[24] origin:010-clb-lutinit 35_43 +CLBLL_R.SLICEL_X0.CLUT.INIT[25] origin:010-clb-lutinit 34_43 +CLBLL_R.SLICEL_X0.CLUT.INIT[26] origin:010-clb-lutinit 35_42 +CLBLL_R.SLICEL_X0.CLUT.INIT[27] origin:010-clb-lutinit 34_42 +CLBLL_R.SLICEL_X0.CLUT.INIT[28] origin:010-clb-lutinit 35_41 +CLBLL_R.SLICEL_X0.CLUT.INIT[29] origin:010-clb-lutinit 34_41 +CLBLL_R.SLICEL_X0.CLUT.INIT[30] origin:010-clb-lutinit 35_40 +CLBLL_R.SLICEL_X0.CLUT.INIT[31] origin:010-clb-lutinit 34_40 +CLBLL_R.SLICEL_X0.CLUT.INIT[32] origin:010-clb-lutinit 32_39 +CLBLL_R.SLICEL_X0.CLUT.INIT[33] origin:010-clb-lutinit 33_39 +CLBLL_R.SLICEL_X0.CLUT.INIT[34] origin:010-clb-lutinit 32_38 +CLBLL_R.SLICEL_X0.CLUT.INIT[35] origin:010-clb-lutinit 33_38 +CLBLL_R.SLICEL_X0.CLUT.INIT[36] origin:010-clb-lutinit 32_37 +CLBLL_R.SLICEL_X0.CLUT.INIT[37] origin:010-clb-lutinit 33_37 +CLBLL_R.SLICEL_X0.CLUT.INIT[38] origin:010-clb-lutinit 32_36 +CLBLL_R.SLICEL_X0.CLUT.INIT[39] origin:010-clb-lutinit 33_36 +CLBLL_R.SLICEL_X0.CLUT.INIT[40] origin:010-clb-lutinit 35_39 +CLBLL_R.SLICEL_X0.CLUT.INIT[41] origin:010-clb-lutinit 34_39 +CLBLL_R.SLICEL_X0.CLUT.INIT[42] origin:010-clb-lutinit 35_38 +CLBLL_R.SLICEL_X0.CLUT.INIT[43] origin:010-clb-lutinit 34_38 +CLBLL_R.SLICEL_X0.CLUT.INIT[44] origin:010-clb-lutinit 35_37 +CLBLL_R.SLICEL_X0.CLUT.INIT[45] origin:010-clb-lutinit 34_37 +CLBLL_R.SLICEL_X0.CLUT.INIT[46] origin:010-clb-lutinit 35_36 +CLBLL_R.SLICEL_X0.CLUT.INIT[47] origin:010-clb-lutinit 34_36 +CLBLL_R.SLICEL_X0.CLUT.INIT[48] origin:010-clb-lutinit 32_35 +CLBLL_R.SLICEL_X0.CLUT.INIT[49] origin:010-clb-lutinit 33_35 +CLBLL_R.SLICEL_X0.CLUT.INIT[50] origin:010-clb-lutinit 32_34 +CLBLL_R.SLICEL_X0.CLUT.INIT[51] origin:010-clb-lutinit 33_34 +CLBLL_R.SLICEL_X0.CLUT.INIT[52] origin:010-clb-lutinit 32_33 +CLBLL_R.SLICEL_X0.CLUT.INIT[53] origin:010-clb-lutinit 33_33 +CLBLL_R.SLICEL_X0.CLUT.INIT[54] origin:010-clb-lutinit 32_32 +CLBLL_R.SLICEL_X0.CLUT.INIT[55] origin:010-clb-lutinit 33_32 +CLBLL_R.SLICEL_X0.CLUT.INIT[56] origin:010-clb-lutinit 35_35 +CLBLL_R.SLICEL_X0.CLUT.INIT[57] origin:010-clb-lutinit 34_35 +CLBLL_R.SLICEL_X0.CLUT.INIT[58] origin:010-clb-lutinit 35_34 +CLBLL_R.SLICEL_X0.CLUT.INIT[59] origin:010-clb-lutinit 34_34 +CLBLL_R.SLICEL_X0.CLUT.INIT[60] origin:010-clb-lutinit 35_33 +CLBLL_R.SLICEL_X0.CLUT.INIT[61] origin:010-clb-lutinit 34_33 +CLBLL_R.SLICEL_X0.CLUT.INIT[62] origin:010-clb-lutinit 35_32 +CLBLL_R.SLICEL_X0.CLUT.INIT[63] origin:010-clb-lutinit 34_32 +CLBLL_R.SLICEL_X0.COUTMUX.C5Q origin:016-clb-noutmux !30_40 !30_44 !30_45 30_43 +CLBLL_R.SLICEL_X0.COUTMUX.CY origin:016-clb-noutmux !30_43 !30_45 30_40 30_44 +CLBLL_R.SLICEL_X0.COUTMUX.F7 origin:016-clb-noutmux !30_44 !30_45 30_40 30_43 +CLBLL_R.SLICEL_X0.COUTMUX.O5 origin:016-clb-noutmux !30_43 !30_44 30_40 30_45 +CLBLL_R.SLICEL_X0.COUTMUX.O6 origin:016-clb-noutmux !30_40 !30_43 !30_44 30_45 +CLBLL_R.SLICEL_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44 +CLBLL_R.SLICEL_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51 +CLBLL_R.SLICEL_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55 +CLBLL_R.SLICEL_X0.D5FFMUX.IN_A origin:012-clb-n5ffmux 30_55 +CLBLL_R.SLICEL_X0.D5FFMUX.IN_B origin:012-clb-n5ffmux 30_54 +CLBLL_R.SLICEL_X0.DFF.ZINI origin:011-clb-ffconfig 31_58 +CLBLL_R.SLICEL_X0.DFF.ZRST origin:011-clb-ffconfig 30_50 +CLBLL_R.SLICEL_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62 +CLBLL_R.SLICEL_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61 +CLBLL_R.SLICEL_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62 +CLBLL_R.SLICEL_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59 +CLBLL_R.SLICEL_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60 +CLBLL_R.SLICEL_X0.DLUT.INIT[00] origin:010-clb-lutinit 32_63 +CLBLL_R.SLICEL_X0.DLUT.INIT[01] origin:010-clb-lutinit 33_63 +CLBLL_R.SLICEL_X0.DLUT.INIT[02] origin:010-clb-lutinit 32_62 +CLBLL_R.SLICEL_X0.DLUT.INIT[03] origin:010-clb-lutinit 33_62 +CLBLL_R.SLICEL_X0.DLUT.INIT[04] origin:010-clb-lutinit 32_61 +CLBLL_R.SLICEL_X0.DLUT.INIT[05] origin:010-clb-lutinit 33_61 +CLBLL_R.SLICEL_X0.DLUT.INIT[06] origin:010-clb-lutinit 32_60 +CLBLL_R.SLICEL_X0.DLUT.INIT[07] origin:010-clb-lutinit 33_60 +CLBLL_R.SLICEL_X0.DLUT.INIT[08] origin:010-clb-lutinit 35_63 +CLBLL_R.SLICEL_X0.DLUT.INIT[09] origin:010-clb-lutinit 34_63 +CLBLL_R.SLICEL_X0.DLUT.INIT[10] origin:010-clb-lutinit 35_62 +CLBLL_R.SLICEL_X0.DLUT.INIT[11] origin:010-clb-lutinit 34_62 +CLBLL_R.SLICEL_X0.DLUT.INIT[12] origin:010-clb-lutinit 35_61 +CLBLL_R.SLICEL_X0.DLUT.INIT[13] origin:010-clb-lutinit 34_61 +CLBLL_R.SLICEL_X0.DLUT.INIT[14] origin:010-clb-lutinit 35_60 +CLBLL_R.SLICEL_X0.DLUT.INIT[15] origin:010-clb-lutinit 34_60 +CLBLL_R.SLICEL_X0.DLUT.INIT[16] origin:010-clb-lutinit 32_59 +CLBLL_R.SLICEL_X0.DLUT.INIT[17] origin:010-clb-lutinit 33_59 +CLBLL_R.SLICEL_X0.DLUT.INIT[18] origin:010-clb-lutinit 32_58 +CLBLL_R.SLICEL_X0.DLUT.INIT[19] origin:010-clb-lutinit 33_58 +CLBLL_R.SLICEL_X0.DLUT.INIT[20] origin:010-clb-lutinit 32_57 +CLBLL_R.SLICEL_X0.DLUT.INIT[21] origin:010-clb-lutinit 33_57 +CLBLL_R.SLICEL_X0.DLUT.INIT[22] origin:010-clb-lutinit 32_56 +CLBLL_R.SLICEL_X0.DLUT.INIT[23] origin:010-clb-lutinit 33_56 +CLBLL_R.SLICEL_X0.DLUT.INIT[24] origin:010-clb-lutinit 35_59 +CLBLL_R.SLICEL_X0.DLUT.INIT[25] origin:010-clb-lutinit 34_59 +CLBLL_R.SLICEL_X0.DLUT.INIT[26] origin:010-clb-lutinit 35_58 +CLBLL_R.SLICEL_X0.DLUT.INIT[27] origin:010-clb-lutinit 34_58 +CLBLL_R.SLICEL_X0.DLUT.INIT[28] origin:010-clb-lutinit 35_57 +CLBLL_R.SLICEL_X0.DLUT.INIT[29] origin:010-clb-lutinit 34_57 +CLBLL_R.SLICEL_X0.DLUT.INIT[30] origin:010-clb-lutinit 35_56 +CLBLL_R.SLICEL_X0.DLUT.INIT[31] origin:010-clb-lutinit 34_56 +CLBLL_R.SLICEL_X0.DLUT.INIT[32] origin:010-clb-lutinit 32_55 +CLBLL_R.SLICEL_X0.DLUT.INIT[33] origin:010-clb-lutinit 33_55 +CLBLL_R.SLICEL_X0.DLUT.INIT[34] origin:010-clb-lutinit 32_54 +CLBLL_R.SLICEL_X0.DLUT.INIT[35] origin:010-clb-lutinit 33_54 +CLBLL_R.SLICEL_X0.DLUT.INIT[36] origin:010-clb-lutinit 32_53 +CLBLL_R.SLICEL_X0.DLUT.INIT[37] origin:010-clb-lutinit 33_53 +CLBLL_R.SLICEL_X0.DLUT.INIT[38] origin:010-clb-lutinit 32_52 +CLBLL_R.SLICEL_X0.DLUT.INIT[39] origin:010-clb-lutinit 33_52 +CLBLL_R.SLICEL_X0.DLUT.INIT[40] origin:010-clb-lutinit 35_55 +CLBLL_R.SLICEL_X0.DLUT.INIT[41] origin:010-clb-lutinit 34_55 +CLBLL_R.SLICEL_X0.DLUT.INIT[42] origin:010-clb-lutinit 35_54 +CLBLL_R.SLICEL_X0.DLUT.INIT[43] origin:010-clb-lutinit 34_54 +CLBLL_R.SLICEL_X0.DLUT.INIT[44] origin:010-clb-lutinit 35_53 +CLBLL_R.SLICEL_X0.DLUT.INIT[45] origin:010-clb-lutinit 34_53 +CLBLL_R.SLICEL_X0.DLUT.INIT[46] origin:010-clb-lutinit 35_52 +CLBLL_R.SLICEL_X0.DLUT.INIT[47] origin:010-clb-lutinit 34_52 +CLBLL_R.SLICEL_X0.DLUT.INIT[48] origin:010-clb-lutinit 32_51 +CLBLL_R.SLICEL_X0.DLUT.INIT[49] origin:010-clb-lutinit 33_51 +CLBLL_R.SLICEL_X0.DLUT.INIT[50] origin:010-clb-lutinit 32_50 +CLBLL_R.SLICEL_X0.DLUT.INIT[51] origin:010-clb-lutinit 33_50 +CLBLL_R.SLICEL_X0.DLUT.INIT[52] origin:010-clb-lutinit 32_49 +CLBLL_R.SLICEL_X0.DLUT.INIT[53] origin:010-clb-lutinit 33_49 +CLBLL_R.SLICEL_X0.DLUT.INIT[54] origin:010-clb-lutinit 32_48 +CLBLL_R.SLICEL_X0.DLUT.INIT[55] origin:010-clb-lutinit 33_48 +CLBLL_R.SLICEL_X0.DLUT.INIT[56] origin:010-clb-lutinit 35_51 +CLBLL_R.SLICEL_X0.DLUT.INIT[57] origin:010-clb-lutinit 34_51 +CLBLL_R.SLICEL_X0.DLUT.INIT[58] origin:010-clb-lutinit 35_50 +CLBLL_R.SLICEL_X0.DLUT.INIT[59] origin:010-clb-lutinit 34_50 +CLBLL_R.SLICEL_X0.DLUT.INIT[60] origin:010-clb-lutinit 35_49 +CLBLL_R.SLICEL_X0.DLUT.INIT[61] origin:010-clb-lutinit 34_49 +CLBLL_R.SLICEL_X0.DLUT.INIT[62] origin:010-clb-lutinit 35_48 +CLBLL_R.SLICEL_X0.DLUT.INIT[63] origin:010-clb-lutinit 34_48 +CLBLL_R.SLICEL_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52 +CLBLL_R.SLICEL_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57 +CLBLL_R.SLICEL_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56 +CLBLL_R.SLICEL_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56 +CLBLL_R.SLICEL_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51 +CLBLL_R.SLICEL_X0.FFSYNC origin:011-clb-ffconfig 00_48 +CLBLL_R.SLICEL_X0.LATCH origin:011-clb-ffconfig 30_32 +CLBLL_R.SLICEL_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14 +CLBLL_R.SLICEL_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14 +CLBLL_R.SLICEL_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12 +CLBLL_R.SLICEL_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13 +CLBLL_R.SLICEL_X0.SRUSEDMUX origin:014-clb-ffsrcemux 01_35 +CLBLL_R.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05 +CLBLL_R.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03 +CLBLL_R.SLICEL_X1.A5FFMUX.IN_A origin:012-clb-n5ffmux 31_08 +CLBLL_R.SLICEL_X1.A5FFMUX.IN_B origin:012-clb-n5ffmux 31_11 +CLBLL_R.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04 +CLBLL_R.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15 +CLBLL_R.SLICEL_X1.AFFMUX.AX origin:015-clb-nffmux !30_04 !31_00 !31_02 31_01 +CLBLL_R.SLICEL_X1.AFFMUX.CY origin:015-clb-nffmux !30_04 !31_01 31_00 31_02 +CLBLL_R.SLICEL_X1.AFFMUX.F7 origin:015-clb-nffmux !30_04 !31_02 31_00 31_01 +CLBLL_R.SLICEL_X1.AFFMUX.O5 origin:015-clb-nffmux !31_01 !31_02 30_04 31_00 +CLBLL_R.SLICEL_X1.AFFMUX.O6 origin:015-clb-nffmux !31_00 !31_01 !31_02 30_04 +CLBLL_R.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02 +CLBLL_R.SLICEL_X1.ALUT.INIT[00] origin:010-clb-lutinit 26_15 +CLBLL_R.SLICEL_X1.ALUT.INIT[01] origin:010-clb-lutinit 27_15 +CLBLL_R.SLICEL_X1.ALUT.INIT[02] origin:010-clb-lutinit 26_14 +CLBLL_R.SLICEL_X1.ALUT.INIT[03] origin:010-clb-lutinit 27_14 +CLBLL_R.SLICEL_X1.ALUT.INIT[04] origin:010-clb-lutinit 26_13 +CLBLL_R.SLICEL_X1.ALUT.INIT[05] origin:010-clb-lutinit 27_13 +CLBLL_R.SLICEL_X1.ALUT.INIT[06] origin:010-clb-lutinit 26_12 +CLBLL_R.SLICEL_X1.ALUT.INIT[07] origin:010-clb-lutinit 27_12 +CLBLL_R.SLICEL_X1.ALUT.INIT[08] origin:010-clb-lutinit 29_15 +CLBLL_R.SLICEL_X1.ALUT.INIT[09] origin:010-clb-lutinit 28_15 +CLBLL_R.SLICEL_X1.ALUT.INIT[10] origin:010-clb-lutinit 29_14 +CLBLL_R.SLICEL_X1.ALUT.INIT[11] origin:010-clb-lutinit 28_14 +CLBLL_R.SLICEL_X1.ALUT.INIT[12] origin:010-clb-lutinit 29_13 +CLBLL_R.SLICEL_X1.ALUT.INIT[13] origin:010-clb-lutinit 28_13 +CLBLL_R.SLICEL_X1.ALUT.INIT[14] origin:010-clb-lutinit 29_12 +CLBLL_R.SLICEL_X1.ALUT.INIT[15] origin:010-clb-lutinit 28_12 +CLBLL_R.SLICEL_X1.ALUT.INIT[16] origin:010-clb-lutinit 26_11 +CLBLL_R.SLICEL_X1.ALUT.INIT[17] origin:010-clb-lutinit 27_11 +CLBLL_R.SLICEL_X1.ALUT.INIT[18] origin:010-clb-lutinit 26_10 +CLBLL_R.SLICEL_X1.ALUT.INIT[19] origin:010-clb-lutinit 27_10 +CLBLL_R.SLICEL_X1.ALUT.INIT[20] origin:010-clb-lutinit 26_09 +CLBLL_R.SLICEL_X1.ALUT.INIT[21] origin:010-clb-lutinit 27_09 +CLBLL_R.SLICEL_X1.ALUT.INIT[22] origin:010-clb-lutinit 26_08 +CLBLL_R.SLICEL_X1.ALUT.INIT[23] origin:010-clb-lutinit 27_08 +CLBLL_R.SLICEL_X1.ALUT.INIT[24] origin:010-clb-lutinit 29_11 +CLBLL_R.SLICEL_X1.ALUT.INIT[25] origin:010-clb-lutinit 28_11 +CLBLL_R.SLICEL_X1.ALUT.INIT[26] origin:010-clb-lutinit 29_10 +CLBLL_R.SLICEL_X1.ALUT.INIT[27] origin:010-clb-lutinit 28_10 +CLBLL_R.SLICEL_X1.ALUT.INIT[28] origin:010-clb-lutinit 29_09 +CLBLL_R.SLICEL_X1.ALUT.INIT[29] origin:010-clb-lutinit 28_09 +CLBLL_R.SLICEL_X1.ALUT.INIT[30] origin:010-clb-lutinit 29_08 +CLBLL_R.SLICEL_X1.ALUT.INIT[31] origin:010-clb-lutinit 28_08 +CLBLL_R.SLICEL_X1.ALUT.INIT[32] origin:010-clb-lutinit 26_07 +CLBLL_R.SLICEL_X1.ALUT.INIT[33] origin:010-clb-lutinit 27_07 +CLBLL_R.SLICEL_X1.ALUT.INIT[34] origin:010-clb-lutinit 26_06 +CLBLL_R.SLICEL_X1.ALUT.INIT[35] origin:010-clb-lutinit 27_06 +CLBLL_R.SLICEL_X1.ALUT.INIT[36] origin:010-clb-lutinit 26_05 +CLBLL_R.SLICEL_X1.ALUT.INIT[37] origin:010-clb-lutinit 27_05 +CLBLL_R.SLICEL_X1.ALUT.INIT[38] origin:010-clb-lutinit 26_04 +CLBLL_R.SLICEL_X1.ALUT.INIT[39] origin:010-clb-lutinit 27_04 +CLBLL_R.SLICEL_X1.ALUT.INIT[40] origin:010-clb-lutinit 29_07 +CLBLL_R.SLICEL_X1.ALUT.INIT[41] origin:010-clb-lutinit 28_07 +CLBLL_R.SLICEL_X1.ALUT.INIT[42] origin:010-clb-lutinit 29_06 +CLBLL_R.SLICEL_X1.ALUT.INIT[43] origin:010-clb-lutinit 28_06 +CLBLL_R.SLICEL_X1.ALUT.INIT[44] origin:010-clb-lutinit 29_05 +CLBLL_R.SLICEL_X1.ALUT.INIT[45] origin:010-clb-lutinit 28_05 +CLBLL_R.SLICEL_X1.ALUT.INIT[46] origin:010-clb-lutinit 29_04 +CLBLL_R.SLICEL_X1.ALUT.INIT[47] origin:010-clb-lutinit 28_04 +CLBLL_R.SLICEL_X1.ALUT.INIT[48] origin:010-clb-lutinit 26_03 +CLBLL_R.SLICEL_X1.ALUT.INIT[49] origin:010-clb-lutinit 27_03 +CLBLL_R.SLICEL_X1.ALUT.INIT[50] origin:010-clb-lutinit 26_02 +CLBLL_R.SLICEL_X1.ALUT.INIT[51] origin:010-clb-lutinit 27_02 +CLBLL_R.SLICEL_X1.ALUT.INIT[52] origin:010-clb-lutinit 26_01 +CLBLL_R.SLICEL_X1.ALUT.INIT[53] origin:010-clb-lutinit 27_01 +CLBLL_R.SLICEL_X1.ALUT.INIT[54] origin:010-clb-lutinit 26_00 +CLBLL_R.SLICEL_X1.ALUT.INIT[55] origin:010-clb-lutinit 27_00 +CLBLL_R.SLICEL_X1.ALUT.INIT[56] origin:010-clb-lutinit 29_03 +CLBLL_R.SLICEL_X1.ALUT.INIT[57] origin:010-clb-lutinit 28_03 +CLBLL_R.SLICEL_X1.ALUT.INIT[58] origin:010-clb-lutinit 29_02 +CLBLL_R.SLICEL_X1.ALUT.INIT[59] origin:010-clb-lutinit 28_02 +CLBLL_R.SLICEL_X1.ALUT.INIT[60] origin:010-clb-lutinit 29_01 +CLBLL_R.SLICEL_X1.ALUT.INIT[61] origin:010-clb-lutinit 28_01 +CLBLL_R.SLICEL_X1.ALUT.INIT[62] origin:010-clb-lutinit 29_00 +CLBLL_R.SLICEL_X1.ALUT.INIT[63] origin:010-clb-lutinit 28_00 +CLBLL_R.SLICEL_X1.AOUTMUX.A5Q origin:016-clb-noutmux !31_07 !31_09 !31_10 30_05 +CLBLL_R.SLICEL_X1.AOUTMUX.CY origin:016-clb-noutmux !30_05 !31_09 31_07 31_10 +CLBLL_R.SLICEL_X1.AOUTMUX.F7 origin:016-clb-noutmux !31_07 !31_09 30_05 31_10 +CLBLL_R.SLICEL_X1.AOUTMUX.O5 origin:016-clb-noutmux !30_05 !31_07 31_09 31_10 +CLBLL_R.SLICEL_X1.AOUTMUX.O6 origin:016-clb-noutmux !30_05 !31_07 !31_10 31_09 +CLBLL_R.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07 +CLBLL_R.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23 +CLBLL_R.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16 +CLBLL_R.SLICEL_X1.B5FFMUX.IN_A origin:012-clb-n5ffmux 31_19 +CLBLL_R.SLICEL_X1.B5FFMUX.IN_B origin:012-clb-n5ffmux 31_18 +CLBLL_R.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29 +CLBLL_R.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30 +CLBLL_R.SLICEL_X1.BFFMUX.BX origin:015-clb-nffmux !31_24 !31_25 !31_26 31_27 +CLBLL_R.SLICEL_X1.BFFMUX.CY origin:015-clb-nffmux !31_24 !31_27 31_25 31_26 +CLBLL_R.SLICEL_X1.BFFMUX.F8 origin:015-clb-nffmux !31_24 !31_26 31_25 31_27 +CLBLL_R.SLICEL_X1.BFFMUX.O5 origin:015-clb-nffmux !31_26 !31_27 31_24 31_25 +CLBLL_R.SLICEL_X1.BFFMUX.O6 origin:015-clb-nffmux !31_25 !31_26 !31_27 31_24 +CLBLL_R.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26 +CLBLL_R.SLICEL_X1.BLUT.INIT[00] origin:010-clb-lutinit 26_31 +CLBLL_R.SLICEL_X1.BLUT.INIT[01] origin:010-clb-lutinit 27_31 +CLBLL_R.SLICEL_X1.BLUT.INIT[02] origin:010-clb-lutinit 26_30 +CLBLL_R.SLICEL_X1.BLUT.INIT[03] origin:010-clb-lutinit 27_30 +CLBLL_R.SLICEL_X1.BLUT.INIT[04] origin:010-clb-lutinit 26_29 +CLBLL_R.SLICEL_X1.BLUT.INIT[05] origin:010-clb-lutinit 27_29 +CLBLL_R.SLICEL_X1.BLUT.INIT[06] origin:010-clb-lutinit 26_28 +CLBLL_R.SLICEL_X1.BLUT.INIT[07] origin:010-clb-lutinit 27_28 +CLBLL_R.SLICEL_X1.BLUT.INIT[08] origin:010-clb-lutinit 29_31 +CLBLL_R.SLICEL_X1.BLUT.INIT[09] origin:010-clb-lutinit 28_31 +CLBLL_R.SLICEL_X1.BLUT.INIT[10] origin:010-clb-lutinit 29_30 +CLBLL_R.SLICEL_X1.BLUT.INIT[11] origin:010-clb-lutinit 28_30 +CLBLL_R.SLICEL_X1.BLUT.INIT[12] origin:010-clb-lutinit 29_29 +CLBLL_R.SLICEL_X1.BLUT.INIT[13] origin:010-clb-lutinit 28_29 +CLBLL_R.SLICEL_X1.BLUT.INIT[14] origin:010-clb-lutinit 29_28 +CLBLL_R.SLICEL_X1.BLUT.INIT[15] origin:010-clb-lutinit 28_28 +CLBLL_R.SLICEL_X1.BLUT.INIT[16] origin:010-clb-lutinit 26_27 +CLBLL_R.SLICEL_X1.BLUT.INIT[17] origin:010-clb-lutinit 27_27 +CLBLL_R.SLICEL_X1.BLUT.INIT[18] origin:010-clb-lutinit 26_26 +CLBLL_R.SLICEL_X1.BLUT.INIT[19] origin:010-clb-lutinit 27_26 +CLBLL_R.SLICEL_X1.BLUT.INIT[20] origin:010-clb-lutinit 26_25 +CLBLL_R.SLICEL_X1.BLUT.INIT[21] origin:010-clb-lutinit 27_25 +CLBLL_R.SLICEL_X1.BLUT.INIT[22] origin:010-clb-lutinit 26_24 +CLBLL_R.SLICEL_X1.BLUT.INIT[23] origin:010-clb-lutinit 27_24 +CLBLL_R.SLICEL_X1.BLUT.INIT[24] origin:010-clb-lutinit 29_27 +CLBLL_R.SLICEL_X1.BLUT.INIT[25] origin:010-clb-lutinit 28_27 +CLBLL_R.SLICEL_X1.BLUT.INIT[26] origin:010-clb-lutinit 29_26 +CLBLL_R.SLICEL_X1.BLUT.INIT[27] origin:010-clb-lutinit 28_26 +CLBLL_R.SLICEL_X1.BLUT.INIT[28] origin:010-clb-lutinit 29_25 +CLBLL_R.SLICEL_X1.BLUT.INIT[29] origin:010-clb-lutinit 28_25 +CLBLL_R.SLICEL_X1.BLUT.INIT[30] origin:010-clb-lutinit 29_24 +CLBLL_R.SLICEL_X1.BLUT.INIT[31] origin:010-clb-lutinit 28_24 +CLBLL_R.SLICEL_X1.BLUT.INIT[32] origin:010-clb-lutinit 26_23 +CLBLL_R.SLICEL_X1.BLUT.INIT[33] origin:010-clb-lutinit 27_23 +CLBLL_R.SLICEL_X1.BLUT.INIT[34] origin:010-clb-lutinit 26_22 +CLBLL_R.SLICEL_X1.BLUT.INIT[35] origin:010-clb-lutinit 27_22 +CLBLL_R.SLICEL_X1.BLUT.INIT[36] origin:010-clb-lutinit 26_21 +CLBLL_R.SLICEL_X1.BLUT.INIT[37] origin:010-clb-lutinit 27_21 +CLBLL_R.SLICEL_X1.BLUT.INIT[38] origin:010-clb-lutinit 26_20 +CLBLL_R.SLICEL_X1.BLUT.INIT[39] origin:010-clb-lutinit 27_20 +CLBLL_R.SLICEL_X1.BLUT.INIT[40] origin:010-clb-lutinit 29_23 +CLBLL_R.SLICEL_X1.BLUT.INIT[41] origin:010-clb-lutinit 28_23 +CLBLL_R.SLICEL_X1.BLUT.INIT[42] origin:010-clb-lutinit 29_22 +CLBLL_R.SLICEL_X1.BLUT.INIT[43] origin:010-clb-lutinit 28_22 +CLBLL_R.SLICEL_X1.BLUT.INIT[44] origin:010-clb-lutinit 29_21 +CLBLL_R.SLICEL_X1.BLUT.INIT[45] origin:010-clb-lutinit 28_21 +CLBLL_R.SLICEL_X1.BLUT.INIT[46] origin:010-clb-lutinit 29_20 +CLBLL_R.SLICEL_X1.BLUT.INIT[47] origin:010-clb-lutinit 28_20 +CLBLL_R.SLICEL_X1.BLUT.INIT[48] origin:010-clb-lutinit 26_19 +CLBLL_R.SLICEL_X1.BLUT.INIT[49] origin:010-clb-lutinit 27_19 +CLBLL_R.SLICEL_X1.BLUT.INIT[50] origin:010-clb-lutinit 26_18 +CLBLL_R.SLICEL_X1.BLUT.INIT[51] origin:010-clb-lutinit 27_18 +CLBLL_R.SLICEL_X1.BLUT.INIT[52] origin:010-clb-lutinit 26_17 +CLBLL_R.SLICEL_X1.BLUT.INIT[53] origin:010-clb-lutinit 27_17 +CLBLL_R.SLICEL_X1.BLUT.INIT[54] origin:010-clb-lutinit 26_16 +CLBLL_R.SLICEL_X1.BLUT.INIT[55] origin:010-clb-lutinit 27_16 +CLBLL_R.SLICEL_X1.BLUT.INIT[56] origin:010-clb-lutinit 29_19 +CLBLL_R.SLICEL_X1.BLUT.INIT[57] origin:010-clb-lutinit 28_19 +CLBLL_R.SLICEL_X1.BLUT.INIT[58] origin:010-clb-lutinit 29_18 +CLBLL_R.SLICEL_X1.BLUT.INIT[59] origin:010-clb-lutinit 28_18 +CLBLL_R.SLICEL_X1.BLUT.INIT[60] origin:010-clb-lutinit 29_17 +CLBLL_R.SLICEL_X1.BLUT.INIT[61] origin:010-clb-lutinit 28_17 +CLBLL_R.SLICEL_X1.BLUT.INIT[62] origin:010-clb-lutinit 29_16 +CLBLL_R.SLICEL_X1.BLUT.INIT[63] origin:010-clb-lutinit 28_16 +CLBLL_R.SLICEL_X1.BOUTMUX.B5Q origin:016-clb-noutmux !30_28 !31_20 !31_21 30_29 +CLBLL_R.SLICEL_X1.BOUTMUX.CY origin:016-clb-noutmux !30_29 !31_20 30_28 31_21 +CLBLL_R.SLICEL_X1.BOUTMUX.F8 origin:016-clb-noutmux !30_28 !31_20 30_29 31_21 +CLBLL_R.SLICEL_X1.BOUTMUX.O5 origin:016-clb-noutmux !30_28 !30_29 31_20 31_21 +CLBLL_R.SLICEL_X1.BOUTMUX.O6 origin:016-clb-noutmux !30_28 !30_29 !31_21 31_20 +CLBLL_R.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28 +CLBLL_R.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42 +CLBLL_R.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44 +CLBLL_R.SLICEL_X1.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_44 +CLBLL_R.SLICEL_X1.C5FFMUX.IN_B origin:012-clb-n5ffmux 31_39 +CLBLL_R.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14 +CLBLL_R.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08 +CLBLL_R.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48 +CLBLL_R.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49 +CLBLL_R.SLICEL_X1.CEUSEDMUX origin:014-clb-ffsrcemux 00_36 +CLBLL_R.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34 +CLBLL_R.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34 +CLBLL_R.SLICEL_X1.CFFMUX.CX origin:015-clb-nffmux !31_35 !31_36 !31_37 31_38 +CLBLL_R.SLICEL_X1.CFFMUX.CY origin:015-clb-nffmux !31_36 !31_38 31_35 31_37 +CLBLL_R.SLICEL_X1.CFFMUX.F7 origin:015-clb-nffmux !31_36 !31_37 31_35 31_38 +CLBLL_R.SLICEL_X1.CFFMUX.O5 origin:015-clb-nffmux !31_37 !31_38 31_35 31_36 +CLBLL_R.SLICEL_X1.CFFMUX.O6 origin:015-clb-nffmux !31_35 !31_37 !31_38 31_36 +CLBLL_R.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37 +CLBLL_R.SLICEL_X1.CLKINV origin:011-clb-ffconfig 00_52 +CLBLL_R.SLICEL_X1.CLUT.INIT[00] origin:010-clb-lutinit 26_47 +CLBLL_R.SLICEL_X1.CLUT.INIT[01] origin:010-clb-lutinit 27_47 +CLBLL_R.SLICEL_X1.CLUT.INIT[02] origin:010-clb-lutinit 26_46 +CLBLL_R.SLICEL_X1.CLUT.INIT[03] origin:010-clb-lutinit 27_46 +CLBLL_R.SLICEL_X1.CLUT.INIT[04] origin:010-clb-lutinit 26_45 +CLBLL_R.SLICEL_X1.CLUT.INIT[05] origin:010-clb-lutinit 27_45 +CLBLL_R.SLICEL_X1.CLUT.INIT[06] origin:010-clb-lutinit 26_44 +CLBLL_R.SLICEL_X1.CLUT.INIT[07] origin:010-clb-lutinit 27_44 +CLBLL_R.SLICEL_X1.CLUT.INIT[08] origin:010-clb-lutinit 29_47 +CLBLL_R.SLICEL_X1.CLUT.INIT[09] origin:010-clb-lutinit 28_47 +CLBLL_R.SLICEL_X1.CLUT.INIT[10] origin:010-clb-lutinit 29_46 +CLBLL_R.SLICEL_X1.CLUT.INIT[11] origin:010-clb-lutinit 28_46 +CLBLL_R.SLICEL_X1.CLUT.INIT[12] origin:010-clb-lutinit 29_45 +CLBLL_R.SLICEL_X1.CLUT.INIT[13] origin:010-clb-lutinit 28_45 +CLBLL_R.SLICEL_X1.CLUT.INIT[14] origin:010-clb-lutinit 29_44 +CLBLL_R.SLICEL_X1.CLUT.INIT[15] origin:010-clb-lutinit 28_44 +CLBLL_R.SLICEL_X1.CLUT.INIT[16] origin:010-clb-lutinit 26_43 +CLBLL_R.SLICEL_X1.CLUT.INIT[17] origin:010-clb-lutinit 27_43 +CLBLL_R.SLICEL_X1.CLUT.INIT[18] origin:010-clb-lutinit 26_42 +CLBLL_R.SLICEL_X1.CLUT.INIT[19] origin:010-clb-lutinit 27_42 +CLBLL_R.SLICEL_X1.CLUT.INIT[20] origin:010-clb-lutinit 26_41 +CLBLL_R.SLICEL_X1.CLUT.INIT[21] origin:010-clb-lutinit 27_41 +CLBLL_R.SLICEL_X1.CLUT.INIT[22] origin:010-clb-lutinit 26_40 +CLBLL_R.SLICEL_X1.CLUT.INIT[23] origin:010-clb-lutinit 27_40 +CLBLL_R.SLICEL_X1.CLUT.INIT[24] origin:010-clb-lutinit 29_43 +CLBLL_R.SLICEL_X1.CLUT.INIT[25] origin:010-clb-lutinit 28_43 +CLBLL_R.SLICEL_X1.CLUT.INIT[26] origin:010-clb-lutinit 29_42 +CLBLL_R.SLICEL_X1.CLUT.INIT[27] origin:010-clb-lutinit 28_42 +CLBLL_R.SLICEL_X1.CLUT.INIT[28] origin:010-clb-lutinit 29_41 +CLBLL_R.SLICEL_X1.CLUT.INIT[29] origin:010-clb-lutinit 28_41 +CLBLL_R.SLICEL_X1.CLUT.INIT[30] origin:010-clb-lutinit 29_40 +CLBLL_R.SLICEL_X1.CLUT.INIT[31] origin:010-clb-lutinit 28_40 +CLBLL_R.SLICEL_X1.CLUT.INIT[32] origin:010-clb-lutinit 26_39 +CLBLL_R.SLICEL_X1.CLUT.INIT[33] origin:010-clb-lutinit 27_39 +CLBLL_R.SLICEL_X1.CLUT.INIT[34] origin:010-clb-lutinit 26_38 +CLBLL_R.SLICEL_X1.CLUT.INIT[35] origin:010-clb-lutinit 27_38 +CLBLL_R.SLICEL_X1.CLUT.INIT[36] origin:010-clb-lutinit 26_37 +CLBLL_R.SLICEL_X1.CLUT.INIT[37] origin:010-clb-lutinit 27_37 +CLBLL_R.SLICEL_X1.CLUT.INIT[38] origin:010-clb-lutinit 26_36 +CLBLL_R.SLICEL_X1.CLUT.INIT[39] origin:010-clb-lutinit 27_36 +CLBLL_R.SLICEL_X1.CLUT.INIT[40] origin:010-clb-lutinit 29_39 +CLBLL_R.SLICEL_X1.CLUT.INIT[41] origin:010-clb-lutinit 28_39 +CLBLL_R.SLICEL_X1.CLUT.INIT[42] origin:010-clb-lutinit 29_38 +CLBLL_R.SLICEL_X1.CLUT.INIT[43] origin:010-clb-lutinit 28_38 +CLBLL_R.SLICEL_X1.CLUT.INIT[44] origin:010-clb-lutinit 29_37 +CLBLL_R.SLICEL_X1.CLUT.INIT[45] origin:010-clb-lutinit 28_37 +CLBLL_R.SLICEL_X1.CLUT.INIT[46] origin:010-clb-lutinit 29_36 +CLBLL_R.SLICEL_X1.CLUT.INIT[47] origin:010-clb-lutinit 28_36 +CLBLL_R.SLICEL_X1.CLUT.INIT[48] origin:010-clb-lutinit 26_35 +CLBLL_R.SLICEL_X1.CLUT.INIT[49] origin:010-clb-lutinit 27_35 +CLBLL_R.SLICEL_X1.CLUT.INIT[50] origin:010-clb-lutinit 26_34 +CLBLL_R.SLICEL_X1.CLUT.INIT[51] origin:010-clb-lutinit 27_34 +CLBLL_R.SLICEL_X1.CLUT.INIT[52] origin:010-clb-lutinit 26_33 +CLBLL_R.SLICEL_X1.CLUT.INIT[53] origin:010-clb-lutinit 27_33 +CLBLL_R.SLICEL_X1.CLUT.INIT[54] origin:010-clb-lutinit 26_32 +CLBLL_R.SLICEL_X1.CLUT.INIT[55] origin:010-clb-lutinit 27_32 +CLBLL_R.SLICEL_X1.CLUT.INIT[56] origin:010-clb-lutinit 29_35 +CLBLL_R.SLICEL_X1.CLUT.INIT[57] origin:010-clb-lutinit 28_35 +CLBLL_R.SLICEL_X1.CLUT.INIT[58] origin:010-clb-lutinit 29_34 +CLBLL_R.SLICEL_X1.CLUT.INIT[59] origin:010-clb-lutinit 28_34 +CLBLL_R.SLICEL_X1.CLUT.INIT[60] origin:010-clb-lutinit 29_33 +CLBLL_R.SLICEL_X1.CLUT.INIT[61] origin:010-clb-lutinit 28_33 +CLBLL_R.SLICEL_X1.CLUT.INIT[62] origin:010-clb-lutinit 29_32 +CLBLL_R.SLICEL_X1.CLUT.INIT[63] origin:010-clb-lutinit 28_32 +CLBLL_R.SLICEL_X1.COUTMUX.C5Q origin:016-clb-noutmux !30_42 !31_40 !31_43 30_41 +CLBLL_R.SLICEL_X1.COUTMUX.CY origin:016-clb-noutmux !30_41 !31_43 30_42 31_40 +CLBLL_R.SLICEL_X1.COUTMUX.F7 origin:016-clb-noutmux !30_42 !31_43 30_41 31_40 +CLBLL_R.SLICEL_X1.COUTMUX.O5 origin:016-clb-noutmux !30_41 !30_42 31_40 31_43 +CLBLL_R.SLICEL_X1.COUTMUX.O6 origin:016-clb-noutmux !30_41 !30_42 !31_40 31_43 +CLBLL_R.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42 +CLBLL_R.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52 +CLBLL_R.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56 +CLBLL_R.SLICEL_X1.D5FFMUX.IN_A origin:012-clb-n5ffmux 31_55 +CLBLL_R.SLICEL_X1.D5FFMUX.IN_B origin:012-clb-n5ffmux 31_54 +CLBLL_R.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59 +CLBLL_R.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50 +CLBLL_R.SLICEL_X1.DFFMUX.CY origin:015-clb-nffmux !31_60 !31_61 30_58 31_62 +CLBLL_R.SLICEL_X1.DFFMUX.DX origin:015-clb-nffmux !30_58 !31_60 !31_62 31_61 +CLBLL_R.SLICEL_X1.DFFMUX.O5 origin:015-clb-nffmux !31_61 !31_62 30_58 31_60 +CLBLL_R.SLICEL_X1.DFFMUX.O6 origin:015-clb-nffmux !30_58 !31_61 !31_62 31_60 +CLBLL_R.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62 +CLBLL_R.SLICEL_X1.DLUT.INIT[00] origin:010-clb-lutinit 26_63 +CLBLL_R.SLICEL_X1.DLUT.INIT[01] origin:010-clb-lutinit 27_63 +CLBLL_R.SLICEL_X1.DLUT.INIT[02] origin:010-clb-lutinit 26_62 +CLBLL_R.SLICEL_X1.DLUT.INIT[03] origin:010-clb-lutinit 27_62 +CLBLL_R.SLICEL_X1.DLUT.INIT[04] origin:010-clb-lutinit 26_61 +CLBLL_R.SLICEL_X1.DLUT.INIT[05] origin:010-clb-lutinit 27_61 +CLBLL_R.SLICEL_X1.DLUT.INIT[06] origin:010-clb-lutinit 26_60 +CLBLL_R.SLICEL_X1.DLUT.INIT[07] origin:010-clb-lutinit 27_60 +CLBLL_R.SLICEL_X1.DLUT.INIT[08] origin:010-clb-lutinit 29_63 +CLBLL_R.SLICEL_X1.DLUT.INIT[09] origin:010-clb-lutinit 28_63 +CLBLL_R.SLICEL_X1.DLUT.INIT[10] origin:010-clb-lutinit 29_62 +CLBLL_R.SLICEL_X1.DLUT.INIT[11] origin:010-clb-lutinit 28_62 +CLBLL_R.SLICEL_X1.DLUT.INIT[12] origin:010-clb-lutinit 29_61 +CLBLL_R.SLICEL_X1.DLUT.INIT[13] origin:010-clb-lutinit 28_61 +CLBLL_R.SLICEL_X1.DLUT.INIT[14] origin:010-clb-lutinit 29_60 +CLBLL_R.SLICEL_X1.DLUT.INIT[15] origin:010-clb-lutinit 28_60 +CLBLL_R.SLICEL_X1.DLUT.INIT[16] origin:010-clb-lutinit 26_59 +CLBLL_R.SLICEL_X1.DLUT.INIT[17] origin:010-clb-lutinit 27_59 +CLBLL_R.SLICEL_X1.DLUT.INIT[18] origin:010-clb-lutinit 26_58 +CLBLL_R.SLICEL_X1.DLUT.INIT[19] origin:010-clb-lutinit 27_58 +CLBLL_R.SLICEL_X1.DLUT.INIT[20] origin:010-clb-lutinit 26_57 +CLBLL_R.SLICEL_X1.DLUT.INIT[21] origin:010-clb-lutinit 27_57 +CLBLL_R.SLICEL_X1.DLUT.INIT[22] origin:010-clb-lutinit 26_56 +CLBLL_R.SLICEL_X1.DLUT.INIT[23] origin:010-clb-lutinit 27_56 +CLBLL_R.SLICEL_X1.DLUT.INIT[24] origin:010-clb-lutinit 29_59 +CLBLL_R.SLICEL_X1.DLUT.INIT[25] origin:010-clb-lutinit 28_59 +CLBLL_R.SLICEL_X1.DLUT.INIT[26] origin:010-clb-lutinit 29_58 +CLBLL_R.SLICEL_X1.DLUT.INIT[27] origin:010-clb-lutinit 28_58 +CLBLL_R.SLICEL_X1.DLUT.INIT[28] origin:010-clb-lutinit 29_57 +CLBLL_R.SLICEL_X1.DLUT.INIT[29] origin:010-clb-lutinit 28_57 +CLBLL_R.SLICEL_X1.DLUT.INIT[30] origin:010-clb-lutinit 29_56 +CLBLL_R.SLICEL_X1.DLUT.INIT[31] origin:010-clb-lutinit 28_56 +CLBLL_R.SLICEL_X1.DLUT.INIT[32] origin:010-clb-lutinit 26_55 +CLBLL_R.SLICEL_X1.DLUT.INIT[33] origin:010-clb-lutinit 27_55 +CLBLL_R.SLICEL_X1.DLUT.INIT[34] origin:010-clb-lutinit 26_54 +CLBLL_R.SLICEL_X1.DLUT.INIT[35] origin:010-clb-lutinit 27_54 +CLBLL_R.SLICEL_X1.DLUT.INIT[36] origin:010-clb-lutinit 26_53 +CLBLL_R.SLICEL_X1.DLUT.INIT[37] origin:010-clb-lutinit 27_53 +CLBLL_R.SLICEL_X1.DLUT.INIT[38] origin:010-clb-lutinit 26_52 +CLBLL_R.SLICEL_X1.DLUT.INIT[39] origin:010-clb-lutinit 27_52 +CLBLL_R.SLICEL_X1.DLUT.INIT[40] origin:010-clb-lutinit 29_55 +CLBLL_R.SLICEL_X1.DLUT.INIT[41] origin:010-clb-lutinit 28_55 +CLBLL_R.SLICEL_X1.DLUT.INIT[42] origin:010-clb-lutinit 29_54 +CLBLL_R.SLICEL_X1.DLUT.INIT[43] origin:010-clb-lutinit 28_54 +CLBLL_R.SLICEL_X1.DLUT.INIT[44] origin:010-clb-lutinit 29_53 +CLBLL_R.SLICEL_X1.DLUT.INIT[45] origin:010-clb-lutinit 28_53 +CLBLL_R.SLICEL_X1.DLUT.INIT[46] origin:010-clb-lutinit 29_52 +CLBLL_R.SLICEL_X1.DLUT.INIT[47] origin:010-clb-lutinit 28_52 +CLBLL_R.SLICEL_X1.DLUT.INIT[48] origin:010-clb-lutinit 26_51 +CLBLL_R.SLICEL_X1.DLUT.INIT[49] origin:010-clb-lutinit 27_51 +CLBLL_R.SLICEL_X1.DLUT.INIT[50] origin:010-clb-lutinit 26_50 +CLBLL_R.SLICEL_X1.DLUT.INIT[51] origin:010-clb-lutinit 27_50 +CLBLL_R.SLICEL_X1.DLUT.INIT[52] origin:010-clb-lutinit 26_49 +CLBLL_R.SLICEL_X1.DLUT.INIT[53] origin:010-clb-lutinit 27_49 +CLBLL_R.SLICEL_X1.DLUT.INIT[54] origin:010-clb-lutinit 26_48 +CLBLL_R.SLICEL_X1.DLUT.INIT[55] origin:010-clb-lutinit 27_48 +CLBLL_R.SLICEL_X1.DLUT.INIT[56] origin:010-clb-lutinit 29_51 +CLBLL_R.SLICEL_X1.DLUT.INIT[57] origin:010-clb-lutinit 28_51 +CLBLL_R.SLICEL_X1.DLUT.INIT[58] origin:010-clb-lutinit 29_50 +CLBLL_R.SLICEL_X1.DLUT.INIT[59] origin:010-clb-lutinit 28_50 +CLBLL_R.SLICEL_X1.DLUT.INIT[60] origin:010-clb-lutinit 29_49 +CLBLL_R.SLICEL_X1.DLUT.INIT[61] origin:010-clb-lutinit 28_49 +CLBLL_R.SLICEL_X1.DLUT.INIT[62] origin:010-clb-lutinit 29_48 +CLBLL_R.SLICEL_X1.DLUT.INIT[63] origin:010-clb-lutinit 28_48 +CLBLL_R.SLICEL_X1.DOUTMUX.CY origin:016-clb-noutmux !31_53 !31_56 30_53 31_57 +CLBLL_R.SLICEL_X1.DOUTMUX.D5Q origin:016-clb-noutmux !30_53 !31_56 !31_57 31_53 +CLBLL_R.SLICEL_X1.DOUTMUX.O5 origin:016-clb-noutmux !30_53 !31_53 31_56 31_57 +CLBLL_R.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56 +CLBLL_R.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53 +CLBLL_R.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31 +CLBLL_R.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32 +CLBLL_R.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13 +CLBLL_R.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13 +CLBLL_R.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11 +CLBLL_R.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12 +CLBLL_R.SLICEL_X1.SRUSEDMUX origin:014-clb-ffsrcemux 00_32 diff --git a/zynq7/segbits_clblm_l.origin_info.db b/zynq7/segbits_clblm_l.origin_info.db new file mode 100644 index 0000000..3773a5d --- /dev/null +++ b/zynq7/segbits_clblm_l.origin_info.db @@ -0,0 +1,696 @@ +CLBLM_L.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05 +CLBLM_L.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03 +CLBLM_L.SLICEL_X1.A5FFMUX.IN_A origin:012-clb-n5ffmux 31_08 +CLBLM_L.SLICEL_X1.A5FFMUX.IN_B origin:012-clb-n5ffmux 31_11 +CLBLM_L.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04 +CLBLM_L.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15 +CLBLM_L.SLICEL_X1.AFFMUX.AX origin:015-clb-nffmux !30_04 !31_00 !31_02 31_01 +CLBLM_L.SLICEL_X1.AFFMUX.CY origin:015-clb-nffmux !30_04 !31_01 31_00 31_02 +CLBLM_L.SLICEL_X1.AFFMUX.F7 origin:015-clb-nffmux !30_04 !31_02 31_00 31_01 +CLBLM_L.SLICEL_X1.AFFMUX.O5 origin:015-clb-nffmux !31_01 !31_02 30_04 31_00 +CLBLM_L.SLICEL_X1.AFFMUX.O6 origin:015-clb-nffmux !31_00 !31_01 !31_02 30_04 +CLBLM_L.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02 +CLBLM_L.SLICEL_X1.ALUT.INIT[00] origin:010-clb-lutinit 26_15 +CLBLM_L.SLICEL_X1.ALUT.INIT[01] origin:010-clb-lutinit 27_15 +CLBLM_L.SLICEL_X1.ALUT.INIT[02] origin:010-clb-lutinit 26_14 +CLBLM_L.SLICEL_X1.ALUT.INIT[03] origin:010-clb-lutinit 27_14 +CLBLM_L.SLICEL_X1.ALUT.INIT[04] origin:010-clb-lutinit 26_13 +CLBLM_L.SLICEL_X1.ALUT.INIT[05] origin:010-clb-lutinit 27_13 +CLBLM_L.SLICEL_X1.ALUT.INIT[06] origin:010-clb-lutinit 26_12 +CLBLM_L.SLICEL_X1.ALUT.INIT[07] origin:010-clb-lutinit 27_12 +CLBLM_L.SLICEL_X1.ALUT.INIT[08] origin:010-clb-lutinit 29_15 +CLBLM_L.SLICEL_X1.ALUT.INIT[09] origin:010-clb-lutinit 28_15 +CLBLM_L.SLICEL_X1.ALUT.INIT[10] origin:010-clb-lutinit 29_14 +CLBLM_L.SLICEL_X1.ALUT.INIT[11] origin:010-clb-lutinit 28_14 +CLBLM_L.SLICEL_X1.ALUT.INIT[12] origin:010-clb-lutinit 29_13 +CLBLM_L.SLICEL_X1.ALUT.INIT[13] origin:010-clb-lutinit 28_13 +CLBLM_L.SLICEL_X1.ALUT.INIT[14] origin:010-clb-lutinit 29_12 +CLBLM_L.SLICEL_X1.ALUT.INIT[15] origin:010-clb-lutinit 28_12 +CLBLM_L.SLICEL_X1.ALUT.INIT[16] origin:010-clb-lutinit 26_11 +CLBLM_L.SLICEL_X1.ALUT.INIT[17] origin:010-clb-lutinit 27_11 +CLBLM_L.SLICEL_X1.ALUT.INIT[18] origin:010-clb-lutinit 26_10 +CLBLM_L.SLICEL_X1.ALUT.INIT[19] origin:010-clb-lutinit 27_10 +CLBLM_L.SLICEL_X1.ALUT.INIT[20] origin:010-clb-lutinit 26_09 +CLBLM_L.SLICEL_X1.ALUT.INIT[21] origin:010-clb-lutinit 27_09 +CLBLM_L.SLICEL_X1.ALUT.INIT[22] origin:010-clb-lutinit 26_08 +CLBLM_L.SLICEL_X1.ALUT.INIT[23] origin:010-clb-lutinit 27_08 +CLBLM_L.SLICEL_X1.ALUT.INIT[24] origin:010-clb-lutinit 29_11 +CLBLM_L.SLICEL_X1.ALUT.INIT[25] origin:010-clb-lutinit 28_11 +CLBLM_L.SLICEL_X1.ALUT.INIT[26] origin:010-clb-lutinit 29_10 +CLBLM_L.SLICEL_X1.ALUT.INIT[27] origin:010-clb-lutinit 28_10 +CLBLM_L.SLICEL_X1.ALUT.INIT[28] origin:010-clb-lutinit 29_09 +CLBLM_L.SLICEL_X1.ALUT.INIT[29] origin:010-clb-lutinit 28_09 +CLBLM_L.SLICEL_X1.ALUT.INIT[30] origin:010-clb-lutinit 29_08 +CLBLM_L.SLICEL_X1.ALUT.INIT[31] origin:010-clb-lutinit 28_08 +CLBLM_L.SLICEL_X1.ALUT.INIT[32] origin:010-clb-lutinit 26_07 +CLBLM_L.SLICEL_X1.ALUT.INIT[33] origin:010-clb-lutinit 27_07 +CLBLM_L.SLICEL_X1.ALUT.INIT[34] origin:010-clb-lutinit 26_06 +CLBLM_L.SLICEL_X1.ALUT.INIT[35] origin:010-clb-lutinit 27_06 +CLBLM_L.SLICEL_X1.ALUT.INIT[36] origin:010-clb-lutinit 26_05 +CLBLM_L.SLICEL_X1.ALUT.INIT[37] origin:010-clb-lutinit 27_05 +CLBLM_L.SLICEL_X1.ALUT.INIT[38] origin:010-clb-lutinit 26_04 +CLBLM_L.SLICEL_X1.ALUT.INIT[39] origin:010-clb-lutinit 27_04 +CLBLM_L.SLICEL_X1.ALUT.INIT[40] origin:010-clb-lutinit 29_07 +CLBLM_L.SLICEL_X1.ALUT.INIT[41] origin:010-clb-lutinit 28_07 +CLBLM_L.SLICEL_X1.ALUT.INIT[42] origin:010-clb-lutinit 29_06 +CLBLM_L.SLICEL_X1.ALUT.INIT[43] origin:010-clb-lutinit 28_06 +CLBLM_L.SLICEL_X1.ALUT.INIT[44] origin:010-clb-lutinit 29_05 +CLBLM_L.SLICEL_X1.ALUT.INIT[45] origin:010-clb-lutinit 28_05 +CLBLM_L.SLICEL_X1.ALUT.INIT[46] origin:010-clb-lutinit 29_04 +CLBLM_L.SLICEL_X1.ALUT.INIT[47] origin:010-clb-lutinit 28_04 +CLBLM_L.SLICEL_X1.ALUT.INIT[48] origin:010-clb-lutinit 26_03 +CLBLM_L.SLICEL_X1.ALUT.INIT[49] origin:010-clb-lutinit 27_03 +CLBLM_L.SLICEL_X1.ALUT.INIT[50] origin:010-clb-lutinit 26_02 +CLBLM_L.SLICEL_X1.ALUT.INIT[51] origin:010-clb-lutinit 27_02 +CLBLM_L.SLICEL_X1.ALUT.INIT[52] origin:010-clb-lutinit 26_01 +CLBLM_L.SLICEL_X1.ALUT.INIT[53] origin:010-clb-lutinit 27_01 +CLBLM_L.SLICEL_X1.ALUT.INIT[54] origin:010-clb-lutinit 26_00 +CLBLM_L.SLICEL_X1.ALUT.INIT[55] origin:010-clb-lutinit 27_00 +CLBLM_L.SLICEL_X1.ALUT.INIT[56] origin:010-clb-lutinit 29_03 +CLBLM_L.SLICEL_X1.ALUT.INIT[57] origin:010-clb-lutinit 28_03 +CLBLM_L.SLICEL_X1.ALUT.INIT[58] origin:010-clb-lutinit 29_02 +CLBLM_L.SLICEL_X1.ALUT.INIT[59] origin:010-clb-lutinit 28_02 +CLBLM_L.SLICEL_X1.ALUT.INIT[60] origin:010-clb-lutinit 29_01 +CLBLM_L.SLICEL_X1.ALUT.INIT[61] origin:010-clb-lutinit 28_01 +CLBLM_L.SLICEL_X1.ALUT.INIT[62] origin:010-clb-lutinit 29_00 +CLBLM_L.SLICEL_X1.ALUT.INIT[63] origin:010-clb-lutinit 28_00 +CLBLM_L.SLICEL_X1.AOUTMUX.A5Q origin:016-clb-noutmux !31_07 !31_09 !31_10 30_05 +CLBLM_L.SLICEL_X1.AOUTMUX.CY origin:016-clb-noutmux !30_05 !31_09 31_07 31_10 +CLBLM_L.SLICEL_X1.AOUTMUX.F7 origin:016-clb-noutmux !31_07 !31_09 30_05 31_10 +CLBLM_L.SLICEL_X1.AOUTMUX.O5 origin:016-clb-noutmux !30_05 !31_07 31_09 31_10 +CLBLM_L.SLICEL_X1.AOUTMUX.O6 origin:016-clb-noutmux !30_05 !31_07 !31_10 31_09 +CLBLM_L.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07 +CLBLM_L.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23 +CLBLM_L.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16 +CLBLM_L.SLICEL_X1.B5FFMUX.IN_A origin:012-clb-n5ffmux 31_19 +CLBLM_L.SLICEL_X1.B5FFMUX.IN_B origin:012-clb-n5ffmux 31_18 +CLBLM_L.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29 +CLBLM_L.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30 +CLBLM_L.SLICEL_X1.BFFMUX.BX origin:015-clb-nffmux !31_24 !31_25 !31_26 31_27 +CLBLM_L.SLICEL_X1.BFFMUX.CY origin:015-clb-nffmux !31_24 !31_27 31_25 31_26 +CLBLM_L.SLICEL_X1.BFFMUX.F8 origin:015-clb-nffmux !31_24 !31_26 31_25 31_27 +CLBLM_L.SLICEL_X1.BFFMUX.O5 origin:015-clb-nffmux !31_26 !31_27 31_24 31_25 +CLBLM_L.SLICEL_X1.BFFMUX.O6 origin:015-clb-nffmux !31_25 !31_26 !31_27 31_24 +CLBLM_L.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26 +CLBLM_L.SLICEL_X1.BLUT.INIT[00] origin:010-clb-lutinit 26_31 +CLBLM_L.SLICEL_X1.BLUT.INIT[01] origin:010-clb-lutinit 27_31 +CLBLM_L.SLICEL_X1.BLUT.INIT[02] origin:010-clb-lutinit 26_30 +CLBLM_L.SLICEL_X1.BLUT.INIT[03] origin:010-clb-lutinit 27_30 +CLBLM_L.SLICEL_X1.BLUT.INIT[04] origin:010-clb-lutinit 26_29 +CLBLM_L.SLICEL_X1.BLUT.INIT[05] origin:010-clb-lutinit 27_29 +CLBLM_L.SLICEL_X1.BLUT.INIT[06] origin:010-clb-lutinit 26_28 +CLBLM_L.SLICEL_X1.BLUT.INIT[07] origin:010-clb-lutinit 27_28 +CLBLM_L.SLICEL_X1.BLUT.INIT[08] origin:010-clb-lutinit 29_31 +CLBLM_L.SLICEL_X1.BLUT.INIT[09] origin:010-clb-lutinit 28_31 +CLBLM_L.SLICEL_X1.BLUT.INIT[10] origin:010-clb-lutinit 29_30 +CLBLM_L.SLICEL_X1.BLUT.INIT[11] origin:010-clb-lutinit 28_30 +CLBLM_L.SLICEL_X1.BLUT.INIT[12] origin:010-clb-lutinit 29_29 +CLBLM_L.SLICEL_X1.BLUT.INIT[13] origin:010-clb-lutinit 28_29 +CLBLM_L.SLICEL_X1.BLUT.INIT[14] origin:010-clb-lutinit 29_28 +CLBLM_L.SLICEL_X1.BLUT.INIT[15] origin:010-clb-lutinit 28_28 +CLBLM_L.SLICEL_X1.BLUT.INIT[16] origin:010-clb-lutinit 26_27 +CLBLM_L.SLICEL_X1.BLUT.INIT[17] origin:010-clb-lutinit 27_27 +CLBLM_L.SLICEL_X1.BLUT.INIT[18] origin:010-clb-lutinit 26_26 +CLBLM_L.SLICEL_X1.BLUT.INIT[19] origin:010-clb-lutinit 27_26 +CLBLM_L.SLICEL_X1.BLUT.INIT[20] origin:010-clb-lutinit 26_25 +CLBLM_L.SLICEL_X1.BLUT.INIT[21] origin:010-clb-lutinit 27_25 +CLBLM_L.SLICEL_X1.BLUT.INIT[22] origin:010-clb-lutinit 26_24 +CLBLM_L.SLICEL_X1.BLUT.INIT[23] origin:010-clb-lutinit 27_24 +CLBLM_L.SLICEL_X1.BLUT.INIT[24] origin:010-clb-lutinit 29_27 +CLBLM_L.SLICEL_X1.BLUT.INIT[25] origin:010-clb-lutinit 28_27 +CLBLM_L.SLICEL_X1.BLUT.INIT[26] origin:010-clb-lutinit 29_26 +CLBLM_L.SLICEL_X1.BLUT.INIT[27] origin:010-clb-lutinit 28_26 +CLBLM_L.SLICEL_X1.BLUT.INIT[28] origin:010-clb-lutinit 29_25 +CLBLM_L.SLICEL_X1.BLUT.INIT[29] origin:010-clb-lutinit 28_25 +CLBLM_L.SLICEL_X1.BLUT.INIT[30] origin:010-clb-lutinit 29_24 +CLBLM_L.SLICEL_X1.BLUT.INIT[31] origin:010-clb-lutinit 28_24 +CLBLM_L.SLICEL_X1.BLUT.INIT[32] origin:010-clb-lutinit 26_23 +CLBLM_L.SLICEL_X1.BLUT.INIT[33] origin:010-clb-lutinit 27_23 +CLBLM_L.SLICEL_X1.BLUT.INIT[34] origin:010-clb-lutinit 26_22 +CLBLM_L.SLICEL_X1.BLUT.INIT[35] origin:010-clb-lutinit 27_22 +CLBLM_L.SLICEL_X1.BLUT.INIT[36] origin:010-clb-lutinit 26_21 +CLBLM_L.SLICEL_X1.BLUT.INIT[37] origin:010-clb-lutinit 27_21 +CLBLM_L.SLICEL_X1.BLUT.INIT[38] origin:010-clb-lutinit 26_20 +CLBLM_L.SLICEL_X1.BLUT.INIT[39] origin:010-clb-lutinit 27_20 +CLBLM_L.SLICEL_X1.BLUT.INIT[40] origin:010-clb-lutinit 29_23 +CLBLM_L.SLICEL_X1.BLUT.INIT[41] origin:010-clb-lutinit 28_23 +CLBLM_L.SLICEL_X1.BLUT.INIT[42] origin:010-clb-lutinit 29_22 +CLBLM_L.SLICEL_X1.BLUT.INIT[43] origin:010-clb-lutinit 28_22 +CLBLM_L.SLICEL_X1.BLUT.INIT[44] origin:010-clb-lutinit 29_21 +CLBLM_L.SLICEL_X1.BLUT.INIT[45] origin:010-clb-lutinit 28_21 +CLBLM_L.SLICEL_X1.BLUT.INIT[46] origin:010-clb-lutinit 29_20 +CLBLM_L.SLICEL_X1.BLUT.INIT[47] origin:010-clb-lutinit 28_20 +CLBLM_L.SLICEL_X1.BLUT.INIT[48] origin:010-clb-lutinit 26_19 +CLBLM_L.SLICEL_X1.BLUT.INIT[49] origin:010-clb-lutinit 27_19 +CLBLM_L.SLICEL_X1.BLUT.INIT[50] origin:010-clb-lutinit 26_18 +CLBLM_L.SLICEL_X1.BLUT.INIT[51] origin:010-clb-lutinit 27_18 +CLBLM_L.SLICEL_X1.BLUT.INIT[52] origin:010-clb-lutinit 26_17 +CLBLM_L.SLICEL_X1.BLUT.INIT[53] origin:010-clb-lutinit 27_17 +CLBLM_L.SLICEL_X1.BLUT.INIT[54] origin:010-clb-lutinit 26_16 +CLBLM_L.SLICEL_X1.BLUT.INIT[55] origin:010-clb-lutinit 27_16 +CLBLM_L.SLICEL_X1.BLUT.INIT[56] origin:010-clb-lutinit 29_19 +CLBLM_L.SLICEL_X1.BLUT.INIT[57] origin:010-clb-lutinit 28_19 +CLBLM_L.SLICEL_X1.BLUT.INIT[58] origin:010-clb-lutinit 29_18 +CLBLM_L.SLICEL_X1.BLUT.INIT[59] origin:010-clb-lutinit 28_18 +CLBLM_L.SLICEL_X1.BLUT.INIT[60] origin:010-clb-lutinit 29_17 +CLBLM_L.SLICEL_X1.BLUT.INIT[61] origin:010-clb-lutinit 28_17 +CLBLM_L.SLICEL_X1.BLUT.INIT[62] origin:010-clb-lutinit 29_16 +CLBLM_L.SLICEL_X1.BLUT.INIT[63] origin:010-clb-lutinit 28_16 +CLBLM_L.SLICEL_X1.BOUTMUX.B5Q origin:016-clb-noutmux !30_28 !31_20 !31_21 30_29 +CLBLM_L.SLICEL_X1.BOUTMUX.CY origin:016-clb-noutmux !30_29 !31_20 30_28 31_21 +CLBLM_L.SLICEL_X1.BOUTMUX.F8 origin:016-clb-noutmux !30_28 !31_20 30_29 31_21 +CLBLM_L.SLICEL_X1.BOUTMUX.O5 origin:016-clb-noutmux !30_28 !30_29 31_20 31_21 +CLBLM_L.SLICEL_X1.BOUTMUX.O6 origin:016-clb-noutmux !30_28 !30_29 !31_21 31_20 +CLBLM_L.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28 +CLBLM_L.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42 +CLBLM_L.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44 +CLBLM_L.SLICEL_X1.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_44 +CLBLM_L.SLICEL_X1.C5FFMUX.IN_B origin:012-clb-n5ffmux 31_39 +CLBLM_L.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14 +CLBLM_L.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08 +CLBLM_L.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48 +CLBLM_L.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49 +CLBLM_L.SLICEL_X1.CEUSEDMUX origin:014-clb-ffsrcemux 00_36 +CLBLM_L.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34 +CLBLM_L.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34 +CLBLM_L.SLICEL_X1.CFFMUX.CX origin:015-clb-nffmux !31_35 !31_36 !31_37 31_38 +CLBLM_L.SLICEL_X1.CFFMUX.CY origin:015-clb-nffmux !31_36 !31_38 31_35 31_37 +CLBLM_L.SLICEL_X1.CFFMUX.F7 origin:015-clb-nffmux !31_36 !31_37 31_35 31_38 +CLBLM_L.SLICEL_X1.CFFMUX.O5 origin:015-clb-nffmux !31_37 !31_38 31_35 31_36 +CLBLM_L.SLICEL_X1.CFFMUX.O6 origin:015-clb-nffmux !31_35 !31_37 !31_38 31_36 +CLBLM_L.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37 +CLBLM_L.SLICEL_X1.CLKINV origin:011-clb-ffconfig 00_52 +CLBLM_L.SLICEL_X1.CLUT.INIT[00] origin:010-clb-lutinit 26_47 +CLBLM_L.SLICEL_X1.CLUT.INIT[01] origin:010-clb-lutinit 27_47 +CLBLM_L.SLICEL_X1.CLUT.INIT[02] origin:010-clb-lutinit 26_46 +CLBLM_L.SLICEL_X1.CLUT.INIT[03] origin:010-clb-lutinit 27_46 +CLBLM_L.SLICEL_X1.CLUT.INIT[04] origin:010-clb-lutinit 26_45 +CLBLM_L.SLICEL_X1.CLUT.INIT[05] origin:010-clb-lutinit 27_45 +CLBLM_L.SLICEL_X1.CLUT.INIT[06] origin:010-clb-lutinit 26_44 +CLBLM_L.SLICEL_X1.CLUT.INIT[07] origin:010-clb-lutinit 27_44 +CLBLM_L.SLICEL_X1.CLUT.INIT[08] origin:010-clb-lutinit 29_47 +CLBLM_L.SLICEL_X1.CLUT.INIT[09] origin:010-clb-lutinit 28_47 +CLBLM_L.SLICEL_X1.CLUT.INIT[10] origin:010-clb-lutinit 29_46 +CLBLM_L.SLICEL_X1.CLUT.INIT[11] origin:010-clb-lutinit 28_46 +CLBLM_L.SLICEL_X1.CLUT.INIT[12] origin:010-clb-lutinit 29_45 +CLBLM_L.SLICEL_X1.CLUT.INIT[13] origin:010-clb-lutinit 28_45 +CLBLM_L.SLICEL_X1.CLUT.INIT[14] origin:010-clb-lutinit 29_44 +CLBLM_L.SLICEL_X1.CLUT.INIT[15] origin:010-clb-lutinit 28_44 +CLBLM_L.SLICEL_X1.CLUT.INIT[16] origin:010-clb-lutinit 26_43 +CLBLM_L.SLICEL_X1.CLUT.INIT[17] origin:010-clb-lutinit 27_43 +CLBLM_L.SLICEL_X1.CLUT.INIT[18] origin:010-clb-lutinit 26_42 +CLBLM_L.SLICEL_X1.CLUT.INIT[19] origin:010-clb-lutinit 27_42 +CLBLM_L.SLICEL_X1.CLUT.INIT[20] origin:010-clb-lutinit 26_41 +CLBLM_L.SLICEL_X1.CLUT.INIT[21] origin:010-clb-lutinit 27_41 +CLBLM_L.SLICEL_X1.CLUT.INIT[22] origin:010-clb-lutinit 26_40 +CLBLM_L.SLICEL_X1.CLUT.INIT[23] origin:010-clb-lutinit 27_40 +CLBLM_L.SLICEL_X1.CLUT.INIT[24] origin:010-clb-lutinit 29_43 +CLBLM_L.SLICEL_X1.CLUT.INIT[25] origin:010-clb-lutinit 28_43 +CLBLM_L.SLICEL_X1.CLUT.INIT[26] origin:010-clb-lutinit 29_42 +CLBLM_L.SLICEL_X1.CLUT.INIT[27] origin:010-clb-lutinit 28_42 +CLBLM_L.SLICEL_X1.CLUT.INIT[28] origin:010-clb-lutinit 29_41 +CLBLM_L.SLICEL_X1.CLUT.INIT[29] origin:010-clb-lutinit 28_41 +CLBLM_L.SLICEL_X1.CLUT.INIT[30] origin:010-clb-lutinit 29_40 +CLBLM_L.SLICEL_X1.CLUT.INIT[31] origin:010-clb-lutinit 28_40 +CLBLM_L.SLICEL_X1.CLUT.INIT[32] origin:010-clb-lutinit 26_39 +CLBLM_L.SLICEL_X1.CLUT.INIT[33] origin:010-clb-lutinit 27_39 +CLBLM_L.SLICEL_X1.CLUT.INIT[34] origin:010-clb-lutinit 26_38 +CLBLM_L.SLICEL_X1.CLUT.INIT[35] origin:010-clb-lutinit 27_38 +CLBLM_L.SLICEL_X1.CLUT.INIT[36] origin:010-clb-lutinit 26_37 +CLBLM_L.SLICEL_X1.CLUT.INIT[37] origin:010-clb-lutinit 27_37 +CLBLM_L.SLICEL_X1.CLUT.INIT[38] origin:010-clb-lutinit 26_36 +CLBLM_L.SLICEL_X1.CLUT.INIT[39] origin:010-clb-lutinit 27_36 +CLBLM_L.SLICEL_X1.CLUT.INIT[40] origin:010-clb-lutinit 29_39 +CLBLM_L.SLICEL_X1.CLUT.INIT[41] origin:010-clb-lutinit 28_39 +CLBLM_L.SLICEL_X1.CLUT.INIT[42] origin:010-clb-lutinit 29_38 +CLBLM_L.SLICEL_X1.CLUT.INIT[43] origin:010-clb-lutinit 28_38 +CLBLM_L.SLICEL_X1.CLUT.INIT[44] origin:010-clb-lutinit 29_37 +CLBLM_L.SLICEL_X1.CLUT.INIT[45] origin:010-clb-lutinit 28_37 +CLBLM_L.SLICEL_X1.CLUT.INIT[46] origin:010-clb-lutinit 29_36 +CLBLM_L.SLICEL_X1.CLUT.INIT[47] origin:010-clb-lutinit 28_36 +CLBLM_L.SLICEL_X1.CLUT.INIT[48] origin:010-clb-lutinit 26_35 +CLBLM_L.SLICEL_X1.CLUT.INIT[49] origin:010-clb-lutinit 27_35 +CLBLM_L.SLICEL_X1.CLUT.INIT[50] origin:010-clb-lutinit 26_34 +CLBLM_L.SLICEL_X1.CLUT.INIT[51] origin:010-clb-lutinit 27_34 +CLBLM_L.SLICEL_X1.CLUT.INIT[52] origin:010-clb-lutinit 26_33 +CLBLM_L.SLICEL_X1.CLUT.INIT[53] origin:010-clb-lutinit 27_33 +CLBLM_L.SLICEL_X1.CLUT.INIT[54] origin:010-clb-lutinit 26_32 +CLBLM_L.SLICEL_X1.CLUT.INIT[55] origin:010-clb-lutinit 27_32 +CLBLM_L.SLICEL_X1.CLUT.INIT[56] origin:010-clb-lutinit 29_35 +CLBLM_L.SLICEL_X1.CLUT.INIT[57] origin:010-clb-lutinit 28_35 +CLBLM_L.SLICEL_X1.CLUT.INIT[58] origin:010-clb-lutinit 29_34 +CLBLM_L.SLICEL_X1.CLUT.INIT[59] origin:010-clb-lutinit 28_34 +CLBLM_L.SLICEL_X1.CLUT.INIT[60] origin:010-clb-lutinit 29_33 +CLBLM_L.SLICEL_X1.CLUT.INIT[61] origin:010-clb-lutinit 28_33 +CLBLM_L.SLICEL_X1.CLUT.INIT[62] origin:010-clb-lutinit 29_32 +CLBLM_L.SLICEL_X1.CLUT.INIT[63] origin:010-clb-lutinit 28_32 +CLBLM_L.SLICEL_X1.COUTMUX.C5Q origin:016-clb-noutmux !30_42 !31_40 !31_43 30_41 +CLBLM_L.SLICEL_X1.COUTMUX.CY origin:016-clb-noutmux !30_41 !31_43 30_42 31_40 +CLBLM_L.SLICEL_X1.COUTMUX.F7 origin:016-clb-noutmux !30_42 !31_43 30_41 31_40 +CLBLM_L.SLICEL_X1.COUTMUX.O5 origin:016-clb-noutmux !30_41 !30_42 31_40 31_43 +CLBLM_L.SLICEL_X1.COUTMUX.O6 origin:016-clb-noutmux !30_41 !30_42 !31_40 31_43 +CLBLM_L.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42 +CLBLM_L.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52 +CLBLM_L.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56 +CLBLM_L.SLICEL_X1.D5FFMUX.IN_A origin:012-clb-n5ffmux 31_55 +CLBLM_L.SLICEL_X1.D5FFMUX.IN_B origin:012-clb-n5ffmux 31_54 +CLBLM_L.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59 +CLBLM_L.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50 +CLBLM_L.SLICEL_X1.DFFMUX.CY origin:015-clb-nffmux !31_60 !31_61 30_58 31_62 +CLBLM_L.SLICEL_X1.DFFMUX.DX origin:015-clb-nffmux !30_58 !31_60 !31_62 31_61 +CLBLM_L.SLICEL_X1.DFFMUX.O5 origin:015-clb-nffmux !31_61 !31_62 30_58 31_60 +CLBLM_L.SLICEL_X1.DFFMUX.O6 origin:015-clb-nffmux !30_58 !31_61 !31_62 31_60 +CLBLM_L.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62 +CLBLM_L.SLICEL_X1.DLUT.INIT[00] origin:010-clb-lutinit 26_63 +CLBLM_L.SLICEL_X1.DLUT.INIT[01] origin:010-clb-lutinit 27_63 +CLBLM_L.SLICEL_X1.DLUT.INIT[02] origin:010-clb-lutinit 26_62 +CLBLM_L.SLICEL_X1.DLUT.INIT[03] origin:010-clb-lutinit 27_62 +CLBLM_L.SLICEL_X1.DLUT.INIT[04] origin:010-clb-lutinit 26_61 +CLBLM_L.SLICEL_X1.DLUT.INIT[05] origin:010-clb-lutinit 27_61 +CLBLM_L.SLICEL_X1.DLUT.INIT[06] origin:010-clb-lutinit 26_60 +CLBLM_L.SLICEL_X1.DLUT.INIT[07] origin:010-clb-lutinit 27_60 +CLBLM_L.SLICEL_X1.DLUT.INIT[08] origin:010-clb-lutinit 29_63 +CLBLM_L.SLICEL_X1.DLUT.INIT[09] origin:010-clb-lutinit 28_63 +CLBLM_L.SLICEL_X1.DLUT.INIT[10] origin:010-clb-lutinit 29_62 +CLBLM_L.SLICEL_X1.DLUT.INIT[11] origin:010-clb-lutinit 28_62 +CLBLM_L.SLICEL_X1.DLUT.INIT[12] origin:010-clb-lutinit 29_61 +CLBLM_L.SLICEL_X1.DLUT.INIT[13] origin:010-clb-lutinit 28_61 +CLBLM_L.SLICEL_X1.DLUT.INIT[14] origin:010-clb-lutinit 29_60 +CLBLM_L.SLICEL_X1.DLUT.INIT[15] origin:010-clb-lutinit 28_60 +CLBLM_L.SLICEL_X1.DLUT.INIT[16] origin:010-clb-lutinit 26_59 +CLBLM_L.SLICEL_X1.DLUT.INIT[17] origin:010-clb-lutinit 27_59 +CLBLM_L.SLICEL_X1.DLUT.INIT[18] origin:010-clb-lutinit 26_58 +CLBLM_L.SLICEL_X1.DLUT.INIT[19] origin:010-clb-lutinit 27_58 +CLBLM_L.SLICEL_X1.DLUT.INIT[20] origin:010-clb-lutinit 26_57 +CLBLM_L.SLICEL_X1.DLUT.INIT[21] origin:010-clb-lutinit 27_57 +CLBLM_L.SLICEL_X1.DLUT.INIT[22] origin:010-clb-lutinit 26_56 +CLBLM_L.SLICEL_X1.DLUT.INIT[23] origin:010-clb-lutinit 27_56 +CLBLM_L.SLICEL_X1.DLUT.INIT[24] origin:010-clb-lutinit 29_59 +CLBLM_L.SLICEL_X1.DLUT.INIT[25] origin:010-clb-lutinit 28_59 +CLBLM_L.SLICEL_X1.DLUT.INIT[26] origin:010-clb-lutinit 29_58 +CLBLM_L.SLICEL_X1.DLUT.INIT[27] origin:010-clb-lutinit 28_58 +CLBLM_L.SLICEL_X1.DLUT.INIT[28] origin:010-clb-lutinit 29_57 +CLBLM_L.SLICEL_X1.DLUT.INIT[29] origin:010-clb-lutinit 28_57 +CLBLM_L.SLICEL_X1.DLUT.INIT[30] origin:010-clb-lutinit 29_56 +CLBLM_L.SLICEL_X1.DLUT.INIT[31] origin:010-clb-lutinit 28_56 +CLBLM_L.SLICEL_X1.DLUT.INIT[32] origin:010-clb-lutinit 26_55 +CLBLM_L.SLICEL_X1.DLUT.INIT[33] origin:010-clb-lutinit 27_55 +CLBLM_L.SLICEL_X1.DLUT.INIT[34] origin:010-clb-lutinit 26_54 +CLBLM_L.SLICEL_X1.DLUT.INIT[35] origin:010-clb-lutinit 27_54 +CLBLM_L.SLICEL_X1.DLUT.INIT[36] origin:010-clb-lutinit 26_53 +CLBLM_L.SLICEL_X1.DLUT.INIT[37] origin:010-clb-lutinit 27_53 +CLBLM_L.SLICEL_X1.DLUT.INIT[38] origin:010-clb-lutinit 26_52 +CLBLM_L.SLICEL_X1.DLUT.INIT[39] origin:010-clb-lutinit 27_52 +CLBLM_L.SLICEL_X1.DLUT.INIT[40] origin:010-clb-lutinit 29_55 +CLBLM_L.SLICEL_X1.DLUT.INIT[41] origin:010-clb-lutinit 28_55 +CLBLM_L.SLICEL_X1.DLUT.INIT[42] origin:010-clb-lutinit 29_54 +CLBLM_L.SLICEL_X1.DLUT.INIT[43] origin:010-clb-lutinit 28_54 +CLBLM_L.SLICEL_X1.DLUT.INIT[44] origin:010-clb-lutinit 29_53 +CLBLM_L.SLICEL_X1.DLUT.INIT[45] origin:010-clb-lutinit 28_53 +CLBLM_L.SLICEL_X1.DLUT.INIT[46] origin:010-clb-lutinit 29_52 +CLBLM_L.SLICEL_X1.DLUT.INIT[47] origin:010-clb-lutinit 28_52 +CLBLM_L.SLICEL_X1.DLUT.INIT[48] origin:010-clb-lutinit 26_51 +CLBLM_L.SLICEL_X1.DLUT.INIT[49] origin:010-clb-lutinit 27_51 +CLBLM_L.SLICEL_X1.DLUT.INIT[50] origin:010-clb-lutinit 26_50 +CLBLM_L.SLICEL_X1.DLUT.INIT[51] origin:010-clb-lutinit 27_50 +CLBLM_L.SLICEL_X1.DLUT.INIT[52] origin:010-clb-lutinit 26_49 +CLBLM_L.SLICEL_X1.DLUT.INIT[53] origin:010-clb-lutinit 27_49 +CLBLM_L.SLICEL_X1.DLUT.INIT[54] origin:010-clb-lutinit 26_48 +CLBLM_L.SLICEL_X1.DLUT.INIT[55] origin:010-clb-lutinit 27_48 +CLBLM_L.SLICEL_X1.DLUT.INIT[56] origin:010-clb-lutinit 29_51 +CLBLM_L.SLICEL_X1.DLUT.INIT[57] origin:010-clb-lutinit 28_51 +CLBLM_L.SLICEL_X1.DLUT.INIT[58] origin:010-clb-lutinit 29_50 +CLBLM_L.SLICEL_X1.DLUT.INIT[59] origin:010-clb-lutinit 28_50 +CLBLM_L.SLICEL_X1.DLUT.INIT[60] origin:010-clb-lutinit 29_49 +CLBLM_L.SLICEL_X1.DLUT.INIT[61] origin:010-clb-lutinit 28_49 +CLBLM_L.SLICEL_X1.DLUT.INIT[62] origin:010-clb-lutinit 29_48 +CLBLM_L.SLICEL_X1.DLUT.INIT[63] origin:010-clb-lutinit 28_48 +CLBLM_L.SLICEL_X1.DOUTMUX.CY origin:016-clb-noutmux !31_53 !31_56 30_53 31_57 +CLBLM_L.SLICEL_X1.DOUTMUX.D5Q origin:016-clb-noutmux !30_53 !31_56 !31_57 31_53 +CLBLM_L.SLICEL_X1.DOUTMUX.O5 origin:016-clb-noutmux !30_53 !31_53 31_56 31_57 +CLBLM_L.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56 +CLBLM_L.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53 +CLBLM_L.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31 +CLBLM_L.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32 +CLBLM_L.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13 +CLBLM_L.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13 +CLBLM_L.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11 +CLBLM_L.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12 +CLBLM_L.SLICEL_X1.SRUSEDMUX origin:014-clb-ffsrcemux 00_32 +CLBLM_L.SLICEM_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06 +CLBLM_L.SLICEM_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07 +CLBLM_L.SLICEM_X0.A5FFMUX.IN_A origin:012-clb-n5ffmux 30_09 +CLBLM_L.SLICEM_X0.A5FFMUX.IN_B origin:012-clb-n5ffmux 30_10 +CLBLM_L.SLICEM_X0.AFF.ZINI origin:011-clb-ffconfig 31_03 +CLBLM_L.SLICEM_X0.AFF.ZRST origin:011-clb-ffconfig 30_12 +CLBLM_L.SLICEM_X0.AFFMUX.AX origin:015-clb-nffmux !30_00 !30_02 !30_03 30_01 +CLBLM_L.SLICEM_X0.AFFMUX.CY origin:015-clb-nffmux !30_01 !30_03 30_00 30_02 +CLBLM_L.SLICEM_X0.AFFMUX.F7 origin:015-clb-nffmux !30_02 !30_03 30_00 30_01 +CLBLM_L.SLICEM_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03 +CLBLM_L.SLICEM_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03 +CLBLM_L.SLICEM_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02 +CLBLM_L.SLICEM_X0.ALUT.DI1MUX.AI origin:019-clb-ndi1mux 00_00 +CLBLM_L.SLICEM_X0.ALUT.INIT[00] origin:010-clb-lutinit 34_15 +CLBLM_L.SLICEM_X0.ALUT.INIT[01] origin:010-clb-lutinit 35_15 +CLBLM_L.SLICEM_X0.ALUT.INIT[02] origin:010-clb-lutinit 34_14 +CLBLM_L.SLICEM_X0.ALUT.INIT[03] origin:010-clb-lutinit 35_14 +CLBLM_L.SLICEM_X0.ALUT.INIT[04] origin:010-clb-lutinit 34_13 +CLBLM_L.SLICEM_X0.ALUT.INIT[05] origin:010-clb-lutinit 35_13 +CLBLM_L.SLICEM_X0.ALUT.INIT[06] origin:010-clb-lutinit 34_12 +CLBLM_L.SLICEM_X0.ALUT.INIT[07] origin:010-clb-lutinit 35_12 +CLBLM_L.SLICEM_X0.ALUT.INIT[08] origin:010-clb-lutinit 32_15 +CLBLM_L.SLICEM_X0.ALUT.INIT[09] origin:010-clb-lutinit 33_15 +CLBLM_L.SLICEM_X0.ALUT.INIT[10] origin:010-clb-lutinit 32_14 +CLBLM_L.SLICEM_X0.ALUT.INIT[11] origin:010-clb-lutinit 33_14 +CLBLM_L.SLICEM_X0.ALUT.INIT[12] origin:010-clb-lutinit 32_13 +CLBLM_L.SLICEM_X0.ALUT.INIT[13] origin:010-clb-lutinit 33_13 +CLBLM_L.SLICEM_X0.ALUT.INIT[14] origin:010-clb-lutinit 32_12 +CLBLM_L.SLICEM_X0.ALUT.INIT[15] origin:010-clb-lutinit 33_12 +CLBLM_L.SLICEM_X0.ALUT.INIT[16] origin:010-clb-lutinit 34_11 +CLBLM_L.SLICEM_X0.ALUT.INIT[17] origin:010-clb-lutinit 35_11 +CLBLM_L.SLICEM_X0.ALUT.INIT[18] origin:010-clb-lutinit 34_10 +CLBLM_L.SLICEM_X0.ALUT.INIT[19] origin:010-clb-lutinit 35_10 +CLBLM_L.SLICEM_X0.ALUT.INIT[20] origin:010-clb-lutinit 34_09 +CLBLM_L.SLICEM_X0.ALUT.INIT[21] origin:010-clb-lutinit 35_09 +CLBLM_L.SLICEM_X0.ALUT.INIT[22] origin:010-clb-lutinit 34_08 +CLBLM_L.SLICEM_X0.ALUT.INIT[23] origin:010-clb-lutinit 35_08 +CLBLM_L.SLICEM_X0.ALUT.INIT[24] origin:010-clb-lutinit 32_11 +CLBLM_L.SLICEM_X0.ALUT.INIT[25] origin:010-clb-lutinit 33_11 +CLBLM_L.SLICEM_X0.ALUT.INIT[26] origin:010-clb-lutinit 32_10 +CLBLM_L.SLICEM_X0.ALUT.INIT[27] origin:010-clb-lutinit 33_10 +CLBLM_L.SLICEM_X0.ALUT.INIT[28] origin:010-clb-lutinit 32_09 +CLBLM_L.SLICEM_X0.ALUT.INIT[29] origin:010-clb-lutinit 33_09 +CLBLM_L.SLICEM_X0.ALUT.INIT[30] origin:010-clb-lutinit 32_08 +CLBLM_L.SLICEM_X0.ALUT.INIT[31] origin:010-clb-lutinit 33_08 +CLBLM_L.SLICEM_X0.ALUT.INIT[32] origin:010-clb-lutinit 34_07 +CLBLM_L.SLICEM_X0.ALUT.INIT[33] origin:010-clb-lutinit 35_07 +CLBLM_L.SLICEM_X0.ALUT.INIT[34] origin:010-clb-lutinit 34_06 +CLBLM_L.SLICEM_X0.ALUT.INIT[35] origin:010-clb-lutinit 35_06 +CLBLM_L.SLICEM_X0.ALUT.INIT[36] origin:010-clb-lutinit 34_05 +CLBLM_L.SLICEM_X0.ALUT.INIT[37] origin:010-clb-lutinit 35_05 +CLBLM_L.SLICEM_X0.ALUT.INIT[38] origin:010-clb-lutinit 34_04 +CLBLM_L.SLICEM_X0.ALUT.INIT[39] origin:010-clb-lutinit 35_04 +CLBLM_L.SLICEM_X0.ALUT.INIT[40] origin:010-clb-lutinit 32_07 +CLBLM_L.SLICEM_X0.ALUT.INIT[41] origin:010-clb-lutinit 33_07 +CLBLM_L.SLICEM_X0.ALUT.INIT[42] origin:010-clb-lutinit 32_06 +CLBLM_L.SLICEM_X0.ALUT.INIT[43] origin:010-clb-lutinit 33_06 +CLBLM_L.SLICEM_X0.ALUT.INIT[44] origin:010-clb-lutinit 32_05 +CLBLM_L.SLICEM_X0.ALUT.INIT[45] origin:010-clb-lutinit 33_05 +CLBLM_L.SLICEM_X0.ALUT.INIT[46] origin:010-clb-lutinit 32_04 +CLBLM_L.SLICEM_X0.ALUT.INIT[47] origin:010-clb-lutinit 33_04 +CLBLM_L.SLICEM_X0.ALUT.INIT[48] origin:010-clb-lutinit 34_03 +CLBLM_L.SLICEM_X0.ALUT.INIT[49] origin:010-clb-lutinit 35_03 +CLBLM_L.SLICEM_X0.ALUT.INIT[50] origin:010-clb-lutinit 34_02 +CLBLM_L.SLICEM_X0.ALUT.INIT[51] origin:010-clb-lutinit 35_02 +CLBLM_L.SLICEM_X0.ALUT.INIT[52] origin:010-clb-lutinit 34_01 +CLBLM_L.SLICEM_X0.ALUT.INIT[53] origin:010-clb-lutinit 35_01 +CLBLM_L.SLICEM_X0.ALUT.INIT[54] origin:010-clb-lutinit 34_00 +CLBLM_L.SLICEM_X0.ALUT.INIT[55] origin:010-clb-lutinit 35_00 +CLBLM_L.SLICEM_X0.ALUT.INIT[56] origin:010-clb-lutinit 32_03 +CLBLM_L.SLICEM_X0.ALUT.INIT[57] origin:010-clb-lutinit 33_03 +CLBLM_L.SLICEM_X0.ALUT.INIT[58] origin:010-clb-lutinit 32_02 +CLBLM_L.SLICEM_X0.ALUT.INIT[59] origin:010-clb-lutinit 33_02 +CLBLM_L.SLICEM_X0.ALUT.INIT[60] origin:010-clb-lutinit 32_01 +CLBLM_L.SLICEM_X0.ALUT.INIT[61] origin:010-clb-lutinit 33_01 +CLBLM_L.SLICEM_X0.ALUT.INIT[62] origin:010-clb-lutinit 32_00 +CLBLM_L.SLICEM_X0.ALUT.INIT[63] origin:010-clb-lutinit 33_00 +CLBLM_L.SLICEM_X0.ALUT.RAM origin:018-clb-ram 31_16 +CLBLM_L.SLICEM_X0.ALUT.SMALL origin:018-clb-ram 00_04 +CLBLM_L.SLICEM_X0.ALUT.SRL origin:018-clb-ram 30_16 +CLBLM_L.SLICEM_X0.AOUTMUX.A5Q origin:016-clb-noutmux !30_06 !30_08 !30_11 30_07 +CLBLM_L.SLICEM_X0.AOUTMUX.CY origin:016-clb-noutmux !30_07 !30_11 30_06 30_08 +CLBLM_L.SLICEM_X0.AOUTMUX.F7 origin:016-clb-noutmux !30_08 !30_11 30_06 30_07 +CLBLM_L.SLICEM_X0.AOUTMUX.O5 origin:016-clb-noutmux !30_07 !30_08 30_06 30_11 +CLBLM_L.SLICEM_X0.AOUTMUX.O6 origin:016-clb-noutmux !30_06 !30_07 !30_08 30_11 +CLBLM_L.SLICEM_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08 +CLBLM_L.SLICEM_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22 +CLBLM_L.SLICEM_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19 +CLBLM_L.SLICEM_X0.B5FFMUX.IN_A origin:012-clb-n5ffmux 30_19 +CLBLM_L.SLICEM_X0.B5FFMUX.IN_B origin:012-clb-n5ffmux 30_18 +CLBLM_L.SLICEM_X0.BFF.ZINI origin:011-clb-ffconfig 31_28 +CLBLM_L.SLICEM_X0.BFF.ZRST origin:011-clb-ffconfig 30_30 +CLBLM_L.SLICEM_X0.BFFMUX.BX origin:015-clb-nffmux !30_24 !30_25 !30_27 30_26 +CLBLM_L.SLICEM_X0.BFFMUX.CY origin:015-clb-nffmux !30_24 !30_26 30_25 30_27 +CLBLM_L.SLICEM_X0.BFFMUX.F8 origin:015-clb-nffmux !30_24 !30_25 30_26 30_27 +CLBLM_L.SLICEM_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27 +CLBLM_L.SLICEM_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24 +CLBLM_L.SLICEM_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25 +CLBLM_L.SLICEM_X0.BLUT.DI1MUX.BI origin:019-clb-ndi1mux 00_20 +CLBLM_L.SLICEM_X0.BLUT.INIT[00] origin:010-clb-lutinit 34_31 +CLBLM_L.SLICEM_X0.BLUT.INIT[01] origin:010-clb-lutinit 35_31 +CLBLM_L.SLICEM_X0.BLUT.INIT[02] origin:010-clb-lutinit 34_30 +CLBLM_L.SLICEM_X0.BLUT.INIT[03] origin:010-clb-lutinit 35_30 +CLBLM_L.SLICEM_X0.BLUT.INIT[04] origin:010-clb-lutinit 34_29 +CLBLM_L.SLICEM_X0.BLUT.INIT[05] origin:010-clb-lutinit 35_29 +CLBLM_L.SLICEM_X0.BLUT.INIT[06] origin:010-clb-lutinit 34_28 +CLBLM_L.SLICEM_X0.BLUT.INIT[07] origin:010-clb-lutinit 35_28 +CLBLM_L.SLICEM_X0.BLUT.INIT[08] origin:010-clb-lutinit 32_31 +CLBLM_L.SLICEM_X0.BLUT.INIT[09] origin:010-clb-lutinit 33_31 +CLBLM_L.SLICEM_X0.BLUT.INIT[10] origin:010-clb-lutinit 32_30 +CLBLM_L.SLICEM_X0.BLUT.INIT[11] origin:010-clb-lutinit 33_30 +CLBLM_L.SLICEM_X0.BLUT.INIT[12] origin:010-clb-lutinit 32_29 +CLBLM_L.SLICEM_X0.BLUT.INIT[13] origin:010-clb-lutinit 33_29 +CLBLM_L.SLICEM_X0.BLUT.INIT[14] origin:010-clb-lutinit 32_28 +CLBLM_L.SLICEM_X0.BLUT.INIT[15] origin:010-clb-lutinit 33_28 +CLBLM_L.SLICEM_X0.BLUT.INIT[16] origin:010-clb-lutinit 34_27 +CLBLM_L.SLICEM_X0.BLUT.INIT[17] origin:010-clb-lutinit 35_27 +CLBLM_L.SLICEM_X0.BLUT.INIT[18] origin:010-clb-lutinit 34_26 +CLBLM_L.SLICEM_X0.BLUT.INIT[19] origin:010-clb-lutinit 35_26 +CLBLM_L.SLICEM_X0.BLUT.INIT[20] origin:010-clb-lutinit 34_25 +CLBLM_L.SLICEM_X0.BLUT.INIT[21] origin:010-clb-lutinit 35_25 +CLBLM_L.SLICEM_X0.BLUT.INIT[22] origin:010-clb-lutinit 34_24 +CLBLM_L.SLICEM_X0.BLUT.INIT[23] origin:010-clb-lutinit 35_24 +CLBLM_L.SLICEM_X0.BLUT.INIT[24] origin:010-clb-lutinit 32_27 +CLBLM_L.SLICEM_X0.BLUT.INIT[25] origin:010-clb-lutinit 33_27 +CLBLM_L.SLICEM_X0.BLUT.INIT[26] origin:010-clb-lutinit 32_26 +CLBLM_L.SLICEM_X0.BLUT.INIT[27] origin:010-clb-lutinit 33_26 +CLBLM_L.SLICEM_X0.BLUT.INIT[28] origin:010-clb-lutinit 32_25 +CLBLM_L.SLICEM_X0.BLUT.INIT[29] origin:010-clb-lutinit 33_25 +CLBLM_L.SLICEM_X0.BLUT.INIT[30] origin:010-clb-lutinit 32_24 +CLBLM_L.SLICEM_X0.BLUT.INIT[31] origin:010-clb-lutinit 33_24 +CLBLM_L.SLICEM_X0.BLUT.INIT[32] origin:010-clb-lutinit 34_23 +CLBLM_L.SLICEM_X0.BLUT.INIT[33] origin:010-clb-lutinit 35_23 +CLBLM_L.SLICEM_X0.BLUT.INIT[34] origin:010-clb-lutinit 34_22 +CLBLM_L.SLICEM_X0.BLUT.INIT[35] origin:010-clb-lutinit 35_22 +CLBLM_L.SLICEM_X0.BLUT.INIT[36] origin:010-clb-lutinit 34_21 +CLBLM_L.SLICEM_X0.BLUT.INIT[37] origin:010-clb-lutinit 35_21 +CLBLM_L.SLICEM_X0.BLUT.INIT[38] origin:010-clb-lutinit 34_20 +CLBLM_L.SLICEM_X0.BLUT.INIT[39] origin:010-clb-lutinit 35_20 +CLBLM_L.SLICEM_X0.BLUT.INIT[40] origin:010-clb-lutinit 32_23 +CLBLM_L.SLICEM_X0.BLUT.INIT[41] origin:010-clb-lutinit 33_23 +CLBLM_L.SLICEM_X0.BLUT.INIT[42] origin:010-clb-lutinit 32_22 +CLBLM_L.SLICEM_X0.BLUT.INIT[43] origin:010-clb-lutinit 33_22 +CLBLM_L.SLICEM_X0.BLUT.INIT[44] origin:010-clb-lutinit 32_21 +CLBLM_L.SLICEM_X0.BLUT.INIT[45] origin:010-clb-lutinit 33_21 +CLBLM_L.SLICEM_X0.BLUT.INIT[46] origin:010-clb-lutinit 32_20 +CLBLM_L.SLICEM_X0.BLUT.INIT[47] origin:010-clb-lutinit 33_20 +CLBLM_L.SLICEM_X0.BLUT.INIT[48] origin:010-clb-lutinit 34_19 +CLBLM_L.SLICEM_X0.BLUT.INIT[49] origin:010-clb-lutinit 35_19 +CLBLM_L.SLICEM_X0.BLUT.INIT[50] origin:010-clb-lutinit 34_18 +CLBLM_L.SLICEM_X0.BLUT.INIT[51] origin:010-clb-lutinit 35_18 +CLBLM_L.SLICEM_X0.BLUT.INIT[52] origin:010-clb-lutinit 34_17 +CLBLM_L.SLICEM_X0.BLUT.INIT[53] origin:010-clb-lutinit 35_17 +CLBLM_L.SLICEM_X0.BLUT.INIT[54] origin:010-clb-lutinit 34_16 +CLBLM_L.SLICEM_X0.BLUT.INIT[55] origin:010-clb-lutinit 35_16 +CLBLM_L.SLICEM_X0.BLUT.INIT[56] origin:010-clb-lutinit 32_19 +CLBLM_L.SLICEM_X0.BLUT.INIT[57] origin:010-clb-lutinit 33_19 +CLBLM_L.SLICEM_X0.BLUT.INIT[58] origin:010-clb-lutinit 32_18 +CLBLM_L.SLICEM_X0.BLUT.INIT[59] origin:010-clb-lutinit 33_18 +CLBLM_L.SLICEM_X0.BLUT.INIT[60] origin:010-clb-lutinit 32_17 +CLBLM_L.SLICEM_X0.BLUT.INIT[61] origin:010-clb-lutinit 33_17 +CLBLM_L.SLICEM_X0.BLUT.INIT[62] origin:010-clb-lutinit 32_16 +CLBLM_L.SLICEM_X0.BLUT.INIT[63] origin:010-clb-lutinit 33_16 +CLBLM_L.SLICEM_X0.BLUT.RAM origin:018-clb-ram 31_17 +CLBLM_L.SLICEM_X0.BLUT.SMALL origin:018-clb-ram 00_24 +CLBLM_L.SLICEM_X0.BLUT.SRL origin:018-clb-ram 30_17 +CLBLM_L.SLICEM_X0.BOUTMUX.B5Q origin:016-clb-noutmux !30_20 !30_21 !30_22 30_23 +CLBLM_L.SLICEM_X0.BOUTMUX.CY origin:016-clb-noutmux !30_20 !30_23 30_21 30_22 +CLBLM_L.SLICEM_X0.BOUTMUX.F8 origin:016-clb-noutmux !30_20 !30_21 30_22 30_23 +CLBLM_L.SLICEM_X0.BOUTMUX.O5 origin:016-clb-noutmux !30_21 !30_23 30_20 30_22 +CLBLM_L.SLICEM_X0.BOUTMUX.O6 origin:016-clb-noutmux !30_21 !30_22 !30_23 30_20 +CLBLM_L.SLICEM_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21 +CLBLM_L.SLICEM_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41 +CLBLM_L.SLICEM_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47 +CLBLM_L.SLICEM_X0.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_45 +CLBLM_L.SLICEM_X0.C5FFMUX.IN_B origin:012-clb-n5ffmux 30_39 +CLBLM_L.SLICEM_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15 +CLBLM_L.SLICEM_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15 +CLBLM_L.SLICEM_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48 +CLBLM_L.SLICEM_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49 +CLBLM_L.SLICEM_X0.CEUSEDMUX origin:014-clb-ffsrcemux 01_39 +CLBLM_L.SLICEM_X0.CFF.ZINI origin:011-clb-ffconfig 31_33 +CLBLM_L.SLICEM_X0.CFF.ZRST origin:011-clb-ffconfig 30_33 +CLBLM_L.SLICEM_X0.CFFMUX.CX origin:015-clb-nffmux !30_35 !30_37 !30_38 30_36 +CLBLM_L.SLICEM_X0.CFFMUX.CY origin:015-clb-nffmux !30_36 !30_38 30_35 30_37 +CLBLM_L.SLICEM_X0.CFFMUX.F7 origin:015-clb-nffmux !30_37 !30_38 30_35 30_36 +CLBLM_L.SLICEM_X0.CFFMUX.O5 origin:015-clb-nffmux !30_36 !30_37 30_35 30_38 +CLBLM_L.SLICEM_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38 +CLBLM_L.SLICEM_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37 +CLBLM_L.SLICEM_X0.CLKINV origin:011-clb-ffconfig 01_51 +CLBLM_L.SLICEM_X0.CLUT.DI1MUX.CI origin:019-clb-ndi1mux 01_43 +CLBLM_L.SLICEM_X0.CLUT.INIT[00] origin:010-clb-lutinit 34_47 +CLBLM_L.SLICEM_X0.CLUT.INIT[01] origin:010-clb-lutinit 35_47 +CLBLM_L.SLICEM_X0.CLUT.INIT[02] origin:010-clb-lutinit 34_46 +CLBLM_L.SLICEM_X0.CLUT.INIT[03] origin:010-clb-lutinit 35_46 +CLBLM_L.SLICEM_X0.CLUT.INIT[04] origin:010-clb-lutinit 34_45 +CLBLM_L.SLICEM_X0.CLUT.INIT[05] origin:010-clb-lutinit 35_45 +CLBLM_L.SLICEM_X0.CLUT.INIT[06] origin:010-clb-lutinit 34_44 +CLBLM_L.SLICEM_X0.CLUT.INIT[07] origin:010-clb-lutinit 35_44 +CLBLM_L.SLICEM_X0.CLUT.INIT[08] origin:010-clb-lutinit 32_47 +CLBLM_L.SLICEM_X0.CLUT.INIT[09] origin:010-clb-lutinit 33_47 +CLBLM_L.SLICEM_X0.CLUT.INIT[10] origin:010-clb-lutinit 32_46 +CLBLM_L.SLICEM_X0.CLUT.INIT[11] origin:010-clb-lutinit 33_46 +CLBLM_L.SLICEM_X0.CLUT.INIT[12] origin:010-clb-lutinit 32_45 +CLBLM_L.SLICEM_X0.CLUT.INIT[13] origin:010-clb-lutinit 33_45 +CLBLM_L.SLICEM_X0.CLUT.INIT[14] origin:010-clb-lutinit 32_44 +CLBLM_L.SLICEM_X0.CLUT.INIT[15] origin:010-clb-lutinit 33_44 +CLBLM_L.SLICEM_X0.CLUT.INIT[16] origin:010-clb-lutinit 34_43 +CLBLM_L.SLICEM_X0.CLUT.INIT[17] origin:010-clb-lutinit 35_43 +CLBLM_L.SLICEM_X0.CLUT.INIT[18] origin:010-clb-lutinit 34_42 +CLBLM_L.SLICEM_X0.CLUT.INIT[19] origin:010-clb-lutinit 35_42 +CLBLM_L.SLICEM_X0.CLUT.INIT[20] origin:010-clb-lutinit 34_41 +CLBLM_L.SLICEM_X0.CLUT.INIT[21] origin:010-clb-lutinit 35_41 +CLBLM_L.SLICEM_X0.CLUT.INIT[22] origin:010-clb-lutinit 34_40 +CLBLM_L.SLICEM_X0.CLUT.INIT[23] origin:010-clb-lutinit 35_40 +CLBLM_L.SLICEM_X0.CLUT.INIT[24] origin:010-clb-lutinit 32_43 +CLBLM_L.SLICEM_X0.CLUT.INIT[25] origin:010-clb-lutinit 33_43 +CLBLM_L.SLICEM_X0.CLUT.INIT[26] origin:010-clb-lutinit 32_42 +CLBLM_L.SLICEM_X0.CLUT.INIT[27] origin:010-clb-lutinit 33_42 +CLBLM_L.SLICEM_X0.CLUT.INIT[28] origin:010-clb-lutinit 32_41 +CLBLM_L.SLICEM_X0.CLUT.INIT[29] origin:010-clb-lutinit 33_41 +CLBLM_L.SLICEM_X0.CLUT.INIT[30] origin:010-clb-lutinit 32_40 +CLBLM_L.SLICEM_X0.CLUT.INIT[31] origin:010-clb-lutinit 33_40 +CLBLM_L.SLICEM_X0.CLUT.INIT[32] origin:010-clb-lutinit 34_39 +CLBLM_L.SLICEM_X0.CLUT.INIT[33] origin:010-clb-lutinit 35_39 +CLBLM_L.SLICEM_X0.CLUT.INIT[34] origin:010-clb-lutinit 34_38 +CLBLM_L.SLICEM_X0.CLUT.INIT[35] origin:010-clb-lutinit 35_38 +CLBLM_L.SLICEM_X0.CLUT.INIT[36] origin:010-clb-lutinit 34_37 +CLBLM_L.SLICEM_X0.CLUT.INIT[37] origin:010-clb-lutinit 35_37 +CLBLM_L.SLICEM_X0.CLUT.INIT[38] origin:010-clb-lutinit 34_36 +CLBLM_L.SLICEM_X0.CLUT.INIT[39] origin:010-clb-lutinit 35_36 +CLBLM_L.SLICEM_X0.CLUT.INIT[40] origin:010-clb-lutinit 32_39 +CLBLM_L.SLICEM_X0.CLUT.INIT[41] origin:010-clb-lutinit 33_39 +CLBLM_L.SLICEM_X0.CLUT.INIT[42] origin:010-clb-lutinit 32_38 +CLBLM_L.SLICEM_X0.CLUT.INIT[43] origin:010-clb-lutinit 33_38 +CLBLM_L.SLICEM_X0.CLUT.INIT[44] origin:010-clb-lutinit 32_37 +CLBLM_L.SLICEM_X0.CLUT.INIT[45] origin:010-clb-lutinit 33_37 +CLBLM_L.SLICEM_X0.CLUT.INIT[46] origin:010-clb-lutinit 32_36 +CLBLM_L.SLICEM_X0.CLUT.INIT[47] origin:010-clb-lutinit 33_36 +CLBLM_L.SLICEM_X0.CLUT.INIT[48] origin:010-clb-lutinit 34_35 +CLBLM_L.SLICEM_X0.CLUT.INIT[49] origin:010-clb-lutinit 35_35 +CLBLM_L.SLICEM_X0.CLUT.INIT[50] origin:010-clb-lutinit 34_34 +CLBLM_L.SLICEM_X0.CLUT.INIT[51] origin:010-clb-lutinit 35_34 +CLBLM_L.SLICEM_X0.CLUT.INIT[52] origin:010-clb-lutinit 34_33 +CLBLM_L.SLICEM_X0.CLUT.INIT[53] origin:010-clb-lutinit 35_33 +CLBLM_L.SLICEM_X0.CLUT.INIT[54] origin:010-clb-lutinit 34_32 +CLBLM_L.SLICEM_X0.CLUT.INIT[55] origin:010-clb-lutinit 35_32 +CLBLM_L.SLICEM_X0.CLUT.INIT[56] origin:010-clb-lutinit 32_35 +CLBLM_L.SLICEM_X0.CLUT.INIT[57] origin:010-clb-lutinit 33_35 +CLBLM_L.SLICEM_X0.CLUT.INIT[58] origin:010-clb-lutinit 32_34 +CLBLM_L.SLICEM_X0.CLUT.INIT[59] origin:010-clb-lutinit 33_34 +CLBLM_L.SLICEM_X0.CLUT.INIT[60] origin:010-clb-lutinit 32_33 +CLBLM_L.SLICEM_X0.CLUT.INIT[61] origin:010-clb-lutinit 33_33 +CLBLM_L.SLICEM_X0.CLUT.INIT[62] origin:010-clb-lutinit 32_32 +CLBLM_L.SLICEM_X0.CLUT.INIT[63] origin:010-clb-lutinit 33_32 +CLBLM_L.SLICEM_X0.CLUT.RAM origin:018-clb-ram 31_46 +CLBLM_L.SLICEM_X0.CLUT.SMALL origin:018-clb-ram 00_28 +CLBLM_L.SLICEM_X0.CLUT.SRL origin:018-clb-ram 30_46 +CLBLM_L.SLICEM_X0.COUTMUX.C5Q origin:016-clb-noutmux !30_40 !30_44 !30_45 30_43 +CLBLM_L.SLICEM_X0.COUTMUX.CY origin:016-clb-noutmux !30_43 !30_45 30_40 30_44 +CLBLM_L.SLICEM_X0.COUTMUX.F7 origin:016-clb-noutmux !30_44 !30_45 30_40 30_43 +CLBLM_L.SLICEM_X0.COUTMUX.O5 origin:016-clb-noutmux !30_43 !30_44 30_40 30_45 +CLBLM_L.SLICEM_X0.COUTMUX.O6 origin:016-clb-noutmux !30_40 !30_43 !30_44 30_45 +CLBLM_L.SLICEM_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44 +CLBLM_L.SLICEM_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51 +CLBLM_L.SLICEM_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55 +CLBLM_L.SLICEM_X0.D5FFMUX.IN_A origin:012-clb-n5ffmux 30_55 +CLBLM_L.SLICEM_X0.D5FFMUX.IN_B origin:012-clb-n5ffmux 30_54 +CLBLM_L.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58 +CLBLM_L.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50 +CLBLM_L.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62 +CLBLM_L.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61 +CLBLM_L.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62 +CLBLM_L.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59 +CLBLM_L.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60 +CLBLM_L.SLICEM_X0.DLUT.INIT[00] origin:010-clb-lutinit 34_63 +CLBLM_L.SLICEM_X0.DLUT.INIT[01] origin:010-clb-lutinit 35_63 +CLBLM_L.SLICEM_X0.DLUT.INIT[02] origin:010-clb-lutinit 34_62 +CLBLM_L.SLICEM_X0.DLUT.INIT[03] origin:010-clb-lutinit 35_62 +CLBLM_L.SLICEM_X0.DLUT.INIT[04] origin:010-clb-lutinit 34_61 +CLBLM_L.SLICEM_X0.DLUT.INIT[05] origin:010-clb-lutinit 35_61 +CLBLM_L.SLICEM_X0.DLUT.INIT[06] origin:010-clb-lutinit 34_60 +CLBLM_L.SLICEM_X0.DLUT.INIT[07] origin:010-clb-lutinit 35_60 +CLBLM_L.SLICEM_X0.DLUT.INIT[08] origin:010-clb-lutinit 32_63 +CLBLM_L.SLICEM_X0.DLUT.INIT[09] origin:010-clb-lutinit 33_63 +CLBLM_L.SLICEM_X0.DLUT.INIT[10] origin:010-clb-lutinit 32_62 +CLBLM_L.SLICEM_X0.DLUT.INIT[11] origin:010-clb-lutinit 33_62 +CLBLM_L.SLICEM_X0.DLUT.INIT[12] origin:010-clb-lutinit 32_61 +CLBLM_L.SLICEM_X0.DLUT.INIT[13] origin:010-clb-lutinit 33_61 +CLBLM_L.SLICEM_X0.DLUT.INIT[14] origin:010-clb-lutinit 32_60 +CLBLM_L.SLICEM_X0.DLUT.INIT[15] origin:010-clb-lutinit 33_60 +CLBLM_L.SLICEM_X0.DLUT.INIT[16] origin:010-clb-lutinit 34_59 +CLBLM_L.SLICEM_X0.DLUT.INIT[17] origin:010-clb-lutinit 35_59 +CLBLM_L.SLICEM_X0.DLUT.INIT[18] origin:010-clb-lutinit 34_58 +CLBLM_L.SLICEM_X0.DLUT.INIT[19] origin:010-clb-lutinit 35_58 +CLBLM_L.SLICEM_X0.DLUT.INIT[20] origin:010-clb-lutinit 34_57 +CLBLM_L.SLICEM_X0.DLUT.INIT[21] origin:010-clb-lutinit 35_57 +CLBLM_L.SLICEM_X0.DLUT.INIT[22] origin:010-clb-lutinit 34_56 +CLBLM_L.SLICEM_X0.DLUT.INIT[23] origin:010-clb-lutinit 35_56 +CLBLM_L.SLICEM_X0.DLUT.INIT[24] origin:010-clb-lutinit 32_59 +CLBLM_L.SLICEM_X0.DLUT.INIT[25] origin:010-clb-lutinit 33_59 +CLBLM_L.SLICEM_X0.DLUT.INIT[26] origin:010-clb-lutinit 32_58 +CLBLM_L.SLICEM_X0.DLUT.INIT[27] origin:010-clb-lutinit 33_58 +CLBLM_L.SLICEM_X0.DLUT.INIT[28] origin:010-clb-lutinit 32_57 +CLBLM_L.SLICEM_X0.DLUT.INIT[29] origin:010-clb-lutinit 33_57 +CLBLM_L.SLICEM_X0.DLUT.INIT[30] origin:010-clb-lutinit 32_56 +CLBLM_L.SLICEM_X0.DLUT.INIT[31] origin:010-clb-lutinit 33_56 +CLBLM_L.SLICEM_X0.DLUT.INIT[32] origin:010-clb-lutinit 34_55 +CLBLM_L.SLICEM_X0.DLUT.INIT[33] origin:010-clb-lutinit 35_55 +CLBLM_L.SLICEM_X0.DLUT.INIT[34] origin:010-clb-lutinit 34_54 +CLBLM_L.SLICEM_X0.DLUT.INIT[35] origin:010-clb-lutinit 35_54 +CLBLM_L.SLICEM_X0.DLUT.INIT[36] origin:010-clb-lutinit 34_53 +CLBLM_L.SLICEM_X0.DLUT.INIT[37] origin:010-clb-lutinit 35_53 +CLBLM_L.SLICEM_X0.DLUT.INIT[38] origin:010-clb-lutinit 34_52 +CLBLM_L.SLICEM_X0.DLUT.INIT[39] origin:010-clb-lutinit 35_52 +CLBLM_L.SLICEM_X0.DLUT.INIT[40] origin:010-clb-lutinit 32_55 +CLBLM_L.SLICEM_X0.DLUT.INIT[41] origin:010-clb-lutinit 33_55 +CLBLM_L.SLICEM_X0.DLUT.INIT[42] origin:010-clb-lutinit 32_54 +CLBLM_L.SLICEM_X0.DLUT.INIT[43] origin:010-clb-lutinit 33_54 +CLBLM_L.SLICEM_X0.DLUT.INIT[44] origin:010-clb-lutinit 32_53 +CLBLM_L.SLICEM_X0.DLUT.INIT[45] origin:010-clb-lutinit 33_53 +CLBLM_L.SLICEM_X0.DLUT.INIT[46] origin:010-clb-lutinit 32_52 +CLBLM_L.SLICEM_X0.DLUT.INIT[47] origin:010-clb-lutinit 33_52 +CLBLM_L.SLICEM_X0.DLUT.INIT[48] origin:010-clb-lutinit 34_51 +CLBLM_L.SLICEM_X0.DLUT.INIT[49] origin:010-clb-lutinit 35_51 +CLBLM_L.SLICEM_X0.DLUT.INIT[50] origin:010-clb-lutinit 34_50 +CLBLM_L.SLICEM_X0.DLUT.INIT[51] origin:010-clb-lutinit 35_50 +CLBLM_L.SLICEM_X0.DLUT.INIT[52] origin:010-clb-lutinit 34_49 +CLBLM_L.SLICEM_X0.DLUT.INIT[53] origin:010-clb-lutinit 35_49 +CLBLM_L.SLICEM_X0.DLUT.INIT[54] origin:010-clb-lutinit 34_48 +CLBLM_L.SLICEM_X0.DLUT.INIT[55] origin:010-clb-lutinit 35_48 +CLBLM_L.SLICEM_X0.DLUT.INIT[56] origin:010-clb-lutinit 32_51 +CLBLM_L.SLICEM_X0.DLUT.INIT[57] origin:010-clb-lutinit 33_51 +CLBLM_L.SLICEM_X0.DLUT.INIT[58] origin:010-clb-lutinit 32_50 +CLBLM_L.SLICEM_X0.DLUT.INIT[59] origin:010-clb-lutinit 33_50 +CLBLM_L.SLICEM_X0.DLUT.INIT[60] origin:010-clb-lutinit 32_49 +CLBLM_L.SLICEM_X0.DLUT.INIT[61] origin:010-clb-lutinit 33_49 +CLBLM_L.SLICEM_X0.DLUT.INIT[62] origin:010-clb-lutinit 32_48 +CLBLM_L.SLICEM_X0.DLUT.INIT[63] origin:010-clb-lutinit 33_48 +CLBLM_L.SLICEM_X0.DLUT.RAM origin:018-clb-ram 31_47 +CLBLM_L.SLICEM_X0.DLUT.SMALL origin:018-clb-ram 01_59 +CLBLM_L.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47 +CLBLM_L.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52 +CLBLM_L.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57 +CLBLM_L.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56 +CLBLM_L.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56 +CLBLM_L.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51 +CLBLM_L.SLICEM_X0.FFSYNC origin:011-clb-ffconfig 00_48 +CLBLM_L.SLICEM_X0.LATCH origin:011-clb-ffconfig 30_32 +CLBLM_L.SLICEM_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14 +CLBLM_L.SLICEM_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14 +CLBLM_L.SLICEM_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12 +CLBLM_L.SLICEM_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13 +CLBLM_L.SLICEM_X0.SRUSEDMUX origin:014-clb-ffsrcemux 01_35 +CLBLM_L.SLICEM_X0.WA7USED origin:018-clb-ram 00_40 +CLBLM_L.SLICEM_X0.WA8USED origin:018-clb-ram 01_27 +CLBLM_L.SLICEM_X0.WEMUX.CE origin:018-clb-ram 01_23 diff --git a/zynq7/segbits_clblm_r.origin_info.db b/zynq7/segbits_clblm_r.origin_info.db new file mode 100644 index 0000000..68662d5 --- /dev/null +++ b/zynq7/segbits_clblm_r.origin_info.db @@ -0,0 +1,696 @@ +CLBLM_R.SLICEL_X1.A5FF.ZINI origin:011-clb-ffconfig 31_05 +CLBLM_R.SLICEL_X1.A5FF.ZRST origin:011-clb-ffconfig 01_03 +CLBLM_R.SLICEL_X1.A5FFMUX.IN_A origin:012-clb-n5ffmux 31_08 +CLBLM_R.SLICEL_X1.A5FFMUX.IN_B origin:012-clb-n5ffmux 31_11 +CLBLM_R.SLICEL_X1.AFF.ZINI origin:011-clb-ffconfig 31_04 +CLBLM_R.SLICEL_X1.AFF.ZRST origin:011-clb-ffconfig 31_15 +CLBLM_R.SLICEL_X1.AFFMUX.AX origin:015-clb-nffmux !30_04 !31_00 !31_02 31_01 +CLBLM_R.SLICEL_X1.AFFMUX.CY origin:015-clb-nffmux !30_04 !31_01 31_00 31_02 +CLBLM_R.SLICEL_X1.AFFMUX.F7 origin:015-clb-nffmux !30_04 !31_02 31_00 31_01 +CLBLM_R.SLICEL_X1.AFFMUX.O5 origin:015-clb-nffmux !31_01 !31_02 30_04 31_00 +CLBLM_R.SLICEL_X1.AFFMUX.O6 origin:015-clb-nffmux !31_00 !31_01 !31_02 30_04 +CLBLM_R.SLICEL_X1.AFFMUX.XOR origin:015-clb-nffmux !30_04 !31_00 !31_01 31_02 +CLBLM_R.SLICEL_X1.ALUT.INIT[00] origin:010-clb-lutinit 26_15 +CLBLM_R.SLICEL_X1.ALUT.INIT[01] origin:010-clb-lutinit 27_15 +CLBLM_R.SLICEL_X1.ALUT.INIT[02] origin:010-clb-lutinit 26_14 +CLBLM_R.SLICEL_X1.ALUT.INIT[03] origin:010-clb-lutinit 27_14 +CLBLM_R.SLICEL_X1.ALUT.INIT[04] origin:010-clb-lutinit 26_13 +CLBLM_R.SLICEL_X1.ALUT.INIT[05] origin:010-clb-lutinit 27_13 +CLBLM_R.SLICEL_X1.ALUT.INIT[06] origin:010-clb-lutinit 26_12 +CLBLM_R.SLICEL_X1.ALUT.INIT[07] origin:010-clb-lutinit 27_12 +CLBLM_R.SLICEL_X1.ALUT.INIT[08] origin:010-clb-lutinit 29_15 +CLBLM_R.SLICEL_X1.ALUT.INIT[09] origin:010-clb-lutinit 28_15 +CLBLM_R.SLICEL_X1.ALUT.INIT[10] origin:010-clb-lutinit 29_14 +CLBLM_R.SLICEL_X1.ALUT.INIT[11] origin:010-clb-lutinit 28_14 +CLBLM_R.SLICEL_X1.ALUT.INIT[12] origin:010-clb-lutinit 29_13 +CLBLM_R.SLICEL_X1.ALUT.INIT[13] origin:010-clb-lutinit 28_13 +CLBLM_R.SLICEL_X1.ALUT.INIT[14] origin:010-clb-lutinit 29_12 +CLBLM_R.SLICEL_X1.ALUT.INIT[15] origin:010-clb-lutinit 28_12 +CLBLM_R.SLICEL_X1.ALUT.INIT[16] origin:010-clb-lutinit 26_11 +CLBLM_R.SLICEL_X1.ALUT.INIT[17] origin:010-clb-lutinit 27_11 +CLBLM_R.SLICEL_X1.ALUT.INIT[18] origin:010-clb-lutinit 26_10 +CLBLM_R.SLICEL_X1.ALUT.INIT[19] origin:010-clb-lutinit 27_10 +CLBLM_R.SLICEL_X1.ALUT.INIT[20] origin:010-clb-lutinit 26_09 +CLBLM_R.SLICEL_X1.ALUT.INIT[21] origin:010-clb-lutinit 27_09 +CLBLM_R.SLICEL_X1.ALUT.INIT[22] origin:010-clb-lutinit 26_08 +CLBLM_R.SLICEL_X1.ALUT.INIT[23] origin:010-clb-lutinit 27_08 +CLBLM_R.SLICEL_X1.ALUT.INIT[24] origin:010-clb-lutinit 29_11 +CLBLM_R.SLICEL_X1.ALUT.INIT[25] origin:010-clb-lutinit 28_11 +CLBLM_R.SLICEL_X1.ALUT.INIT[26] origin:010-clb-lutinit 29_10 +CLBLM_R.SLICEL_X1.ALUT.INIT[27] origin:010-clb-lutinit 28_10 +CLBLM_R.SLICEL_X1.ALUT.INIT[28] origin:010-clb-lutinit 29_09 +CLBLM_R.SLICEL_X1.ALUT.INIT[29] origin:010-clb-lutinit 28_09 +CLBLM_R.SLICEL_X1.ALUT.INIT[30] origin:010-clb-lutinit 29_08 +CLBLM_R.SLICEL_X1.ALUT.INIT[31] origin:010-clb-lutinit 28_08 +CLBLM_R.SLICEL_X1.ALUT.INIT[32] origin:010-clb-lutinit 26_07 +CLBLM_R.SLICEL_X1.ALUT.INIT[33] origin:010-clb-lutinit 27_07 +CLBLM_R.SLICEL_X1.ALUT.INIT[34] origin:010-clb-lutinit 26_06 +CLBLM_R.SLICEL_X1.ALUT.INIT[35] origin:010-clb-lutinit 27_06 +CLBLM_R.SLICEL_X1.ALUT.INIT[36] origin:010-clb-lutinit 26_05 +CLBLM_R.SLICEL_X1.ALUT.INIT[37] origin:010-clb-lutinit 27_05 +CLBLM_R.SLICEL_X1.ALUT.INIT[38] origin:010-clb-lutinit 26_04 +CLBLM_R.SLICEL_X1.ALUT.INIT[39] origin:010-clb-lutinit 27_04 +CLBLM_R.SLICEL_X1.ALUT.INIT[40] origin:010-clb-lutinit 29_07 +CLBLM_R.SLICEL_X1.ALUT.INIT[41] origin:010-clb-lutinit 28_07 +CLBLM_R.SLICEL_X1.ALUT.INIT[42] origin:010-clb-lutinit 29_06 +CLBLM_R.SLICEL_X1.ALUT.INIT[43] origin:010-clb-lutinit 28_06 +CLBLM_R.SLICEL_X1.ALUT.INIT[44] origin:010-clb-lutinit 29_05 +CLBLM_R.SLICEL_X1.ALUT.INIT[45] origin:010-clb-lutinit 28_05 +CLBLM_R.SLICEL_X1.ALUT.INIT[46] origin:010-clb-lutinit 29_04 +CLBLM_R.SLICEL_X1.ALUT.INIT[47] origin:010-clb-lutinit 28_04 +CLBLM_R.SLICEL_X1.ALUT.INIT[48] origin:010-clb-lutinit 26_03 +CLBLM_R.SLICEL_X1.ALUT.INIT[49] origin:010-clb-lutinit 27_03 +CLBLM_R.SLICEL_X1.ALUT.INIT[50] origin:010-clb-lutinit 26_02 +CLBLM_R.SLICEL_X1.ALUT.INIT[51] origin:010-clb-lutinit 27_02 +CLBLM_R.SLICEL_X1.ALUT.INIT[52] origin:010-clb-lutinit 26_01 +CLBLM_R.SLICEL_X1.ALUT.INIT[53] origin:010-clb-lutinit 27_01 +CLBLM_R.SLICEL_X1.ALUT.INIT[54] origin:010-clb-lutinit 26_00 +CLBLM_R.SLICEL_X1.ALUT.INIT[55] origin:010-clb-lutinit 27_00 +CLBLM_R.SLICEL_X1.ALUT.INIT[56] origin:010-clb-lutinit 29_03 +CLBLM_R.SLICEL_X1.ALUT.INIT[57] origin:010-clb-lutinit 28_03 +CLBLM_R.SLICEL_X1.ALUT.INIT[58] origin:010-clb-lutinit 29_02 +CLBLM_R.SLICEL_X1.ALUT.INIT[59] origin:010-clb-lutinit 28_02 +CLBLM_R.SLICEL_X1.ALUT.INIT[60] origin:010-clb-lutinit 29_01 +CLBLM_R.SLICEL_X1.ALUT.INIT[61] origin:010-clb-lutinit 28_01 +CLBLM_R.SLICEL_X1.ALUT.INIT[62] origin:010-clb-lutinit 29_00 +CLBLM_R.SLICEL_X1.ALUT.INIT[63] origin:010-clb-lutinit 28_00 +CLBLM_R.SLICEL_X1.AOUTMUX.A5Q origin:016-clb-noutmux !31_07 !31_09 !31_10 30_05 +CLBLM_R.SLICEL_X1.AOUTMUX.CY origin:016-clb-noutmux !30_05 !31_09 31_07 31_10 +CLBLM_R.SLICEL_X1.AOUTMUX.F7 origin:016-clb-noutmux !31_07 !31_09 30_05 31_10 +CLBLM_R.SLICEL_X1.AOUTMUX.O5 origin:016-clb-noutmux !30_05 !31_07 31_09 31_10 +CLBLM_R.SLICEL_X1.AOUTMUX.O6 origin:016-clb-noutmux !30_05 !31_07 !31_10 31_09 +CLBLM_R.SLICEL_X1.AOUTMUX.XOR origin:016-clb-noutmux !30_05 !31_09 !31_10 31_07 +CLBLM_R.SLICEL_X1.B5FF.ZINI origin:011-clb-ffconfig 31_23 +CLBLM_R.SLICEL_X1.B5FF.ZRST origin:011-clb-ffconfig 00_16 +CLBLM_R.SLICEL_X1.B5FFMUX.IN_A origin:012-clb-n5ffmux 31_19 +CLBLM_R.SLICEL_X1.B5FFMUX.IN_B origin:012-clb-n5ffmux 31_18 +CLBLM_R.SLICEL_X1.BFF.ZINI origin:011-clb-ffconfig 31_29 +CLBLM_R.SLICEL_X1.BFF.ZRST origin:011-clb-ffconfig 31_30 +CLBLM_R.SLICEL_X1.BFFMUX.BX origin:015-clb-nffmux !31_24 !31_25 !31_26 31_27 +CLBLM_R.SLICEL_X1.BFFMUX.CY origin:015-clb-nffmux !31_24 !31_27 31_25 31_26 +CLBLM_R.SLICEL_X1.BFFMUX.F8 origin:015-clb-nffmux !31_24 !31_26 31_25 31_27 +CLBLM_R.SLICEL_X1.BFFMUX.O5 origin:015-clb-nffmux !31_26 !31_27 31_24 31_25 +CLBLM_R.SLICEL_X1.BFFMUX.O6 origin:015-clb-nffmux !31_25 !31_26 !31_27 31_24 +CLBLM_R.SLICEL_X1.BFFMUX.XOR origin:015-clb-nffmux !31_24 !31_25 !31_27 31_26 +CLBLM_R.SLICEL_X1.BLUT.INIT[00] origin:010-clb-lutinit 26_31 +CLBLM_R.SLICEL_X1.BLUT.INIT[01] origin:010-clb-lutinit 27_31 +CLBLM_R.SLICEL_X1.BLUT.INIT[02] origin:010-clb-lutinit 26_30 +CLBLM_R.SLICEL_X1.BLUT.INIT[03] origin:010-clb-lutinit 27_30 +CLBLM_R.SLICEL_X1.BLUT.INIT[04] origin:010-clb-lutinit 26_29 +CLBLM_R.SLICEL_X1.BLUT.INIT[05] origin:010-clb-lutinit 27_29 +CLBLM_R.SLICEL_X1.BLUT.INIT[06] origin:010-clb-lutinit 26_28 +CLBLM_R.SLICEL_X1.BLUT.INIT[07] origin:010-clb-lutinit 27_28 +CLBLM_R.SLICEL_X1.BLUT.INIT[08] origin:010-clb-lutinit 29_31 +CLBLM_R.SLICEL_X1.BLUT.INIT[09] origin:010-clb-lutinit 28_31 +CLBLM_R.SLICEL_X1.BLUT.INIT[10] origin:010-clb-lutinit 29_30 +CLBLM_R.SLICEL_X1.BLUT.INIT[11] origin:010-clb-lutinit 28_30 +CLBLM_R.SLICEL_X1.BLUT.INIT[12] origin:010-clb-lutinit 29_29 +CLBLM_R.SLICEL_X1.BLUT.INIT[13] origin:010-clb-lutinit 28_29 +CLBLM_R.SLICEL_X1.BLUT.INIT[14] origin:010-clb-lutinit 29_28 +CLBLM_R.SLICEL_X1.BLUT.INIT[15] origin:010-clb-lutinit 28_28 +CLBLM_R.SLICEL_X1.BLUT.INIT[16] origin:010-clb-lutinit 26_27 +CLBLM_R.SLICEL_X1.BLUT.INIT[17] origin:010-clb-lutinit 27_27 +CLBLM_R.SLICEL_X1.BLUT.INIT[18] origin:010-clb-lutinit 26_26 +CLBLM_R.SLICEL_X1.BLUT.INIT[19] origin:010-clb-lutinit 27_26 +CLBLM_R.SLICEL_X1.BLUT.INIT[20] origin:010-clb-lutinit 26_25 +CLBLM_R.SLICEL_X1.BLUT.INIT[21] origin:010-clb-lutinit 27_25 +CLBLM_R.SLICEL_X1.BLUT.INIT[22] origin:010-clb-lutinit 26_24 +CLBLM_R.SLICEL_X1.BLUT.INIT[23] origin:010-clb-lutinit 27_24 +CLBLM_R.SLICEL_X1.BLUT.INIT[24] origin:010-clb-lutinit 29_27 +CLBLM_R.SLICEL_X1.BLUT.INIT[25] origin:010-clb-lutinit 28_27 +CLBLM_R.SLICEL_X1.BLUT.INIT[26] origin:010-clb-lutinit 29_26 +CLBLM_R.SLICEL_X1.BLUT.INIT[27] origin:010-clb-lutinit 28_26 +CLBLM_R.SLICEL_X1.BLUT.INIT[28] origin:010-clb-lutinit 29_25 +CLBLM_R.SLICEL_X1.BLUT.INIT[29] origin:010-clb-lutinit 28_25 +CLBLM_R.SLICEL_X1.BLUT.INIT[30] origin:010-clb-lutinit 29_24 +CLBLM_R.SLICEL_X1.BLUT.INIT[31] origin:010-clb-lutinit 28_24 +CLBLM_R.SLICEL_X1.BLUT.INIT[32] origin:010-clb-lutinit 26_23 +CLBLM_R.SLICEL_X1.BLUT.INIT[33] origin:010-clb-lutinit 27_23 +CLBLM_R.SLICEL_X1.BLUT.INIT[34] origin:010-clb-lutinit 26_22 +CLBLM_R.SLICEL_X1.BLUT.INIT[35] origin:010-clb-lutinit 27_22 +CLBLM_R.SLICEL_X1.BLUT.INIT[36] origin:010-clb-lutinit 26_21 +CLBLM_R.SLICEL_X1.BLUT.INIT[37] origin:010-clb-lutinit 27_21 +CLBLM_R.SLICEL_X1.BLUT.INIT[38] origin:010-clb-lutinit 26_20 +CLBLM_R.SLICEL_X1.BLUT.INIT[39] origin:010-clb-lutinit 27_20 +CLBLM_R.SLICEL_X1.BLUT.INIT[40] origin:010-clb-lutinit 29_23 +CLBLM_R.SLICEL_X1.BLUT.INIT[41] origin:010-clb-lutinit 28_23 +CLBLM_R.SLICEL_X1.BLUT.INIT[42] origin:010-clb-lutinit 29_22 +CLBLM_R.SLICEL_X1.BLUT.INIT[43] origin:010-clb-lutinit 28_22 +CLBLM_R.SLICEL_X1.BLUT.INIT[44] origin:010-clb-lutinit 29_21 +CLBLM_R.SLICEL_X1.BLUT.INIT[45] origin:010-clb-lutinit 28_21 +CLBLM_R.SLICEL_X1.BLUT.INIT[46] origin:010-clb-lutinit 29_20 +CLBLM_R.SLICEL_X1.BLUT.INIT[47] origin:010-clb-lutinit 28_20 +CLBLM_R.SLICEL_X1.BLUT.INIT[48] origin:010-clb-lutinit 26_19 +CLBLM_R.SLICEL_X1.BLUT.INIT[49] origin:010-clb-lutinit 27_19 +CLBLM_R.SLICEL_X1.BLUT.INIT[50] origin:010-clb-lutinit 26_18 +CLBLM_R.SLICEL_X1.BLUT.INIT[51] origin:010-clb-lutinit 27_18 +CLBLM_R.SLICEL_X1.BLUT.INIT[52] origin:010-clb-lutinit 26_17 +CLBLM_R.SLICEL_X1.BLUT.INIT[53] origin:010-clb-lutinit 27_17 +CLBLM_R.SLICEL_X1.BLUT.INIT[54] origin:010-clb-lutinit 26_16 +CLBLM_R.SLICEL_X1.BLUT.INIT[55] origin:010-clb-lutinit 27_16 +CLBLM_R.SLICEL_X1.BLUT.INIT[56] origin:010-clb-lutinit 29_19 +CLBLM_R.SLICEL_X1.BLUT.INIT[57] origin:010-clb-lutinit 28_19 +CLBLM_R.SLICEL_X1.BLUT.INIT[58] origin:010-clb-lutinit 29_18 +CLBLM_R.SLICEL_X1.BLUT.INIT[59] origin:010-clb-lutinit 28_18 +CLBLM_R.SLICEL_X1.BLUT.INIT[60] origin:010-clb-lutinit 29_17 +CLBLM_R.SLICEL_X1.BLUT.INIT[61] origin:010-clb-lutinit 28_17 +CLBLM_R.SLICEL_X1.BLUT.INIT[62] origin:010-clb-lutinit 29_16 +CLBLM_R.SLICEL_X1.BLUT.INIT[63] origin:010-clb-lutinit 28_16 +CLBLM_R.SLICEL_X1.BOUTMUX.B5Q origin:016-clb-noutmux !30_28 !31_20 !31_21 30_29 +CLBLM_R.SLICEL_X1.BOUTMUX.CY origin:016-clb-noutmux !30_29 !31_20 30_28 31_21 +CLBLM_R.SLICEL_X1.BOUTMUX.F8 origin:016-clb-noutmux !30_28 !31_20 30_29 31_21 +CLBLM_R.SLICEL_X1.BOUTMUX.O5 origin:016-clb-noutmux !30_28 !30_29 31_20 31_21 +CLBLM_R.SLICEL_X1.BOUTMUX.O6 origin:016-clb-noutmux !30_28 !30_29 !31_21 31_20 +CLBLM_R.SLICEL_X1.BOUTMUX.XOR origin:016-clb-noutmux !30_29 !31_20 !31_21 30_28 +CLBLM_R.SLICEL_X1.C5FF.ZINI origin:011-clb-ffconfig 31_42 +CLBLM_R.SLICEL_X1.C5FF.ZRST origin:011-clb-ffconfig 00_44 +CLBLM_R.SLICEL_X1.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_44 +CLBLM_R.SLICEL_X1.C5FFMUX.IN_B origin:012-clb-n5ffmux 31_39 +CLBLM_R.SLICEL_X1.CARRY4.ACY0 origin:013-clb-ncy0 31_14 +CLBLM_R.SLICEL_X1.CARRY4.BCY0 origin:013-clb-ncy0 00_08 +CLBLM_R.SLICEL_X1.CARRY4.CCY0 origin:013-clb-ncy0 31_48 +CLBLM_R.SLICEL_X1.CARRY4.DCY0 origin:013-clb-ncy0 31_49 +CLBLM_R.SLICEL_X1.CEUSEDMUX origin:014-clb-ffsrcemux 00_36 +CLBLM_R.SLICEL_X1.CFF.ZINI origin:011-clb-ffconfig 31_34 +CLBLM_R.SLICEL_X1.CFF.ZRST origin:011-clb-ffconfig 30_34 +CLBLM_R.SLICEL_X1.CFFMUX.CX origin:015-clb-nffmux !31_35 !31_36 !31_37 31_38 +CLBLM_R.SLICEL_X1.CFFMUX.CY origin:015-clb-nffmux !31_36 !31_38 31_35 31_37 +CLBLM_R.SLICEL_X1.CFFMUX.F7 origin:015-clb-nffmux !31_36 !31_37 31_35 31_38 +CLBLM_R.SLICEL_X1.CFFMUX.O5 origin:015-clb-nffmux !31_37 !31_38 31_35 31_36 +CLBLM_R.SLICEL_X1.CFFMUX.O6 origin:015-clb-nffmux !31_35 !31_37 !31_38 31_36 +CLBLM_R.SLICEL_X1.CFFMUX.XOR origin:015-clb-nffmux !31_35 !31_36 !31_38 31_37 +CLBLM_R.SLICEL_X1.CLKINV origin:011-clb-ffconfig 00_52 +CLBLM_R.SLICEL_X1.CLUT.INIT[00] origin:010-clb-lutinit 26_47 +CLBLM_R.SLICEL_X1.CLUT.INIT[01] origin:010-clb-lutinit 27_47 +CLBLM_R.SLICEL_X1.CLUT.INIT[02] origin:010-clb-lutinit 26_46 +CLBLM_R.SLICEL_X1.CLUT.INIT[03] origin:010-clb-lutinit 27_46 +CLBLM_R.SLICEL_X1.CLUT.INIT[04] origin:010-clb-lutinit 26_45 +CLBLM_R.SLICEL_X1.CLUT.INIT[05] origin:010-clb-lutinit 27_45 +CLBLM_R.SLICEL_X1.CLUT.INIT[06] origin:010-clb-lutinit 26_44 +CLBLM_R.SLICEL_X1.CLUT.INIT[07] origin:010-clb-lutinit 27_44 +CLBLM_R.SLICEL_X1.CLUT.INIT[08] origin:010-clb-lutinit 29_47 +CLBLM_R.SLICEL_X1.CLUT.INIT[09] origin:010-clb-lutinit 28_47 +CLBLM_R.SLICEL_X1.CLUT.INIT[10] origin:010-clb-lutinit 29_46 +CLBLM_R.SLICEL_X1.CLUT.INIT[11] origin:010-clb-lutinit 28_46 +CLBLM_R.SLICEL_X1.CLUT.INIT[12] origin:010-clb-lutinit 29_45 +CLBLM_R.SLICEL_X1.CLUT.INIT[13] origin:010-clb-lutinit 28_45 +CLBLM_R.SLICEL_X1.CLUT.INIT[14] origin:010-clb-lutinit 29_44 +CLBLM_R.SLICEL_X1.CLUT.INIT[15] origin:010-clb-lutinit 28_44 +CLBLM_R.SLICEL_X1.CLUT.INIT[16] origin:010-clb-lutinit 26_43 +CLBLM_R.SLICEL_X1.CLUT.INIT[17] origin:010-clb-lutinit 27_43 +CLBLM_R.SLICEL_X1.CLUT.INIT[18] origin:010-clb-lutinit 26_42 +CLBLM_R.SLICEL_X1.CLUT.INIT[19] origin:010-clb-lutinit 27_42 +CLBLM_R.SLICEL_X1.CLUT.INIT[20] origin:010-clb-lutinit 26_41 +CLBLM_R.SLICEL_X1.CLUT.INIT[21] origin:010-clb-lutinit 27_41 +CLBLM_R.SLICEL_X1.CLUT.INIT[22] origin:010-clb-lutinit 26_40 +CLBLM_R.SLICEL_X1.CLUT.INIT[23] origin:010-clb-lutinit 27_40 +CLBLM_R.SLICEL_X1.CLUT.INIT[24] origin:010-clb-lutinit 29_43 +CLBLM_R.SLICEL_X1.CLUT.INIT[25] origin:010-clb-lutinit 28_43 +CLBLM_R.SLICEL_X1.CLUT.INIT[26] origin:010-clb-lutinit 29_42 +CLBLM_R.SLICEL_X1.CLUT.INIT[27] origin:010-clb-lutinit 28_42 +CLBLM_R.SLICEL_X1.CLUT.INIT[28] origin:010-clb-lutinit 29_41 +CLBLM_R.SLICEL_X1.CLUT.INIT[29] origin:010-clb-lutinit 28_41 +CLBLM_R.SLICEL_X1.CLUT.INIT[30] origin:010-clb-lutinit 29_40 +CLBLM_R.SLICEL_X1.CLUT.INIT[31] origin:010-clb-lutinit 28_40 +CLBLM_R.SLICEL_X1.CLUT.INIT[32] origin:010-clb-lutinit 26_39 +CLBLM_R.SLICEL_X1.CLUT.INIT[33] origin:010-clb-lutinit 27_39 +CLBLM_R.SLICEL_X1.CLUT.INIT[34] origin:010-clb-lutinit 26_38 +CLBLM_R.SLICEL_X1.CLUT.INIT[35] origin:010-clb-lutinit 27_38 +CLBLM_R.SLICEL_X1.CLUT.INIT[36] origin:010-clb-lutinit 26_37 +CLBLM_R.SLICEL_X1.CLUT.INIT[37] origin:010-clb-lutinit 27_37 +CLBLM_R.SLICEL_X1.CLUT.INIT[38] origin:010-clb-lutinit 26_36 +CLBLM_R.SLICEL_X1.CLUT.INIT[39] origin:010-clb-lutinit 27_36 +CLBLM_R.SLICEL_X1.CLUT.INIT[40] origin:010-clb-lutinit 29_39 +CLBLM_R.SLICEL_X1.CLUT.INIT[41] origin:010-clb-lutinit 28_39 +CLBLM_R.SLICEL_X1.CLUT.INIT[42] origin:010-clb-lutinit 29_38 +CLBLM_R.SLICEL_X1.CLUT.INIT[43] origin:010-clb-lutinit 28_38 +CLBLM_R.SLICEL_X1.CLUT.INIT[44] origin:010-clb-lutinit 29_37 +CLBLM_R.SLICEL_X1.CLUT.INIT[45] origin:010-clb-lutinit 28_37 +CLBLM_R.SLICEL_X1.CLUT.INIT[46] origin:010-clb-lutinit 29_36 +CLBLM_R.SLICEL_X1.CLUT.INIT[47] origin:010-clb-lutinit 28_36 +CLBLM_R.SLICEL_X1.CLUT.INIT[48] origin:010-clb-lutinit 26_35 +CLBLM_R.SLICEL_X1.CLUT.INIT[49] origin:010-clb-lutinit 27_35 +CLBLM_R.SLICEL_X1.CLUT.INIT[50] origin:010-clb-lutinit 26_34 +CLBLM_R.SLICEL_X1.CLUT.INIT[51] origin:010-clb-lutinit 27_34 +CLBLM_R.SLICEL_X1.CLUT.INIT[52] origin:010-clb-lutinit 26_33 +CLBLM_R.SLICEL_X1.CLUT.INIT[53] origin:010-clb-lutinit 27_33 +CLBLM_R.SLICEL_X1.CLUT.INIT[54] origin:010-clb-lutinit 26_32 +CLBLM_R.SLICEL_X1.CLUT.INIT[55] origin:010-clb-lutinit 27_32 +CLBLM_R.SLICEL_X1.CLUT.INIT[56] origin:010-clb-lutinit 29_35 +CLBLM_R.SLICEL_X1.CLUT.INIT[57] origin:010-clb-lutinit 28_35 +CLBLM_R.SLICEL_X1.CLUT.INIT[58] origin:010-clb-lutinit 29_34 +CLBLM_R.SLICEL_X1.CLUT.INIT[59] origin:010-clb-lutinit 28_34 +CLBLM_R.SLICEL_X1.CLUT.INIT[60] origin:010-clb-lutinit 29_33 +CLBLM_R.SLICEL_X1.CLUT.INIT[61] origin:010-clb-lutinit 28_33 +CLBLM_R.SLICEL_X1.CLUT.INIT[62] origin:010-clb-lutinit 29_32 +CLBLM_R.SLICEL_X1.CLUT.INIT[63] origin:010-clb-lutinit 28_32 +CLBLM_R.SLICEL_X1.COUTMUX.C5Q origin:016-clb-noutmux !30_42 !31_40 !31_43 30_41 +CLBLM_R.SLICEL_X1.COUTMUX.CY origin:016-clb-noutmux !30_41 !31_43 30_42 31_40 +CLBLM_R.SLICEL_X1.COUTMUX.F7 origin:016-clb-noutmux !30_42 !31_43 30_41 31_40 +CLBLM_R.SLICEL_X1.COUTMUX.O5 origin:016-clb-noutmux !30_41 !30_42 31_40 31_43 +CLBLM_R.SLICEL_X1.COUTMUX.O6 origin:016-clb-noutmux !30_41 !30_42 !31_40 31_43 +CLBLM_R.SLICEL_X1.COUTMUX.XOR origin:016-clb-noutmux !30_41 !31_40 !31_43 30_42 +CLBLM_R.SLICEL_X1.D5FF.ZINI origin:011-clb-ffconfig 31_52 +CLBLM_R.SLICEL_X1.D5FF.ZRST origin:011-clb-ffconfig 00_56 +CLBLM_R.SLICEL_X1.D5FFMUX.IN_A origin:012-clb-n5ffmux 31_55 +CLBLM_R.SLICEL_X1.D5FFMUX.IN_B origin:012-clb-n5ffmux 31_54 +CLBLM_R.SLICEL_X1.DFF.ZINI origin:011-clb-ffconfig 31_59 +CLBLM_R.SLICEL_X1.DFF.ZRST origin:011-clb-ffconfig 31_50 +CLBLM_R.SLICEL_X1.DFFMUX.CY origin:015-clb-nffmux !31_60 !31_61 30_58 31_62 +CLBLM_R.SLICEL_X1.DFFMUX.DX origin:015-clb-nffmux !30_58 !31_60 !31_62 31_61 +CLBLM_R.SLICEL_X1.DFFMUX.O5 origin:015-clb-nffmux !31_61 !31_62 30_58 31_60 +CLBLM_R.SLICEL_X1.DFFMUX.O6 origin:015-clb-nffmux !30_58 !31_61 !31_62 31_60 +CLBLM_R.SLICEL_X1.DFFMUX.XOR origin:015-clb-nffmux !30_58 !31_60 !31_61 31_62 +CLBLM_R.SLICEL_X1.DLUT.INIT[00] origin:010-clb-lutinit 26_63 +CLBLM_R.SLICEL_X1.DLUT.INIT[01] origin:010-clb-lutinit 27_63 +CLBLM_R.SLICEL_X1.DLUT.INIT[02] origin:010-clb-lutinit 26_62 +CLBLM_R.SLICEL_X1.DLUT.INIT[03] origin:010-clb-lutinit 27_62 +CLBLM_R.SLICEL_X1.DLUT.INIT[04] origin:010-clb-lutinit 26_61 +CLBLM_R.SLICEL_X1.DLUT.INIT[05] origin:010-clb-lutinit 27_61 +CLBLM_R.SLICEL_X1.DLUT.INIT[06] origin:010-clb-lutinit 26_60 +CLBLM_R.SLICEL_X1.DLUT.INIT[07] origin:010-clb-lutinit 27_60 +CLBLM_R.SLICEL_X1.DLUT.INIT[08] origin:010-clb-lutinit 29_63 +CLBLM_R.SLICEL_X1.DLUT.INIT[09] origin:010-clb-lutinit 28_63 +CLBLM_R.SLICEL_X1.DLUT.INIT[10] origin:010-clb-lutinit 29_62 +CLBLM_R.SLICEL_X1.DLUT.INIT[11] origin:010-clb-lutinit 28_62 +CLBLM_R.SLICEL_X1.DLUT.INIT[12] origin:010-clb-lutinit 29_61 +CLBLM_R.SLICEL_X1.DLUT.INIT[13] origin:010-clb-lutinit 28_61 +CLBLM_R.SLICEL_X1.DLUT.INIT[14] origin:010-clb-lutinit 29_60 +CLBLM_R.SLICEL_X1.DLUT.INIT[15] origin:010-clb-lutinit 28_60 +CLBLM_R.SLICEL_X1.DLUT.INIT[16] origin:010-clb-lutinit 26_59 +CLBLM_R.SLICEL_X1.DLUT.INIT[17] origin:010-clb-lutinit 27_59 +CLBLM_R.SLICEL_X1.DLUT.INIT[18] origin:010-clb-lutinit 26_58 +CLBLM_R.SLICEL_X1.DLUT.INIT[19] origin:010-clb-lutinit 27_58 +CLBLM_R.SLICEL_X1.DLUT.INIT[20] origin:010-clb-lutinit 26_57 +CLBLM_R.SLICEL_X1.DLUT.INIT[21] origin:010-clb-lutinit 27_57 +CLBLM_R.SLICEL_X1.DLUT.INIT[22] origin:010-clb-lutinit 26_56 +CLBLM_R.SLICEL_X1.DLUT.INIT[23] origin:010-clb-lutinit 27_56 +CLBLM_R.SLICEL_X1.DLUT.INIT[24] origin:010-clb-lutinit 29_59 +CLBLM_R.SLICEL_X1.DLUT.INIT[25] origin:010-clb-lutinit 28_59 +CLBLM_R.SLICEL_X1.DLUT.INIT[26] origin:010-clb-lutinit 29_58 +CLBLM_R.SLICEL_X1.DLUT.INIT[27] origin:010-clb-lutinit 28_58 +CLBLM_R.SLICEL_X1.DLUT.INIT[28] origin:010-clb-lutinit 29_57 +CLBLM_R.SLICEL_X1.DLUT.INIT[29] origin:010-clb-lutinit 28_57 +CLBLM_R.SLICEL_X1.DLUT.INIT[30] origin:010-clb-lutinit 29_56 +CLBLM_R.SLICEL_X1.DLUT.INIT[31] origin:010-clb-lutinit 28_56 +CLBLM_R.SLICEL_X1.DLUT.INIT[32] origin:010-clb-lutinit 26_55 +CLBLM_R.SLICEL_X1.DLUT.INIT[33] origin:010-clb-lutinit 27_55 +CLBLM_R.SLICEL_X1.DLUT.INIT[34] origin:010-clb-lutinit 26_54 +CLBLM_R.SLICEL_X1.DLUT.INIT[35] origin:010-clb-lutinit 27_54 +CLBLM_R.SLICEL_X1.DLUT.INIT[36] origin:010-clb-lutinit 26_53 +CLBLM_R.SLICEL_X1.DLUT.INIT[37] origin:010-clb-lutinit 27_53 +CLBLM_R.SLICEL_X1.DLUT.INIT[38] origin:010-clb-lutinit 26_52 +CLBLM_R.SLICEL_X1.DLUT.INIT[39] origin:010-clb-lutinit 27_52 +CLBLM_R.SLICEL_X1.DLUT.INIT[40] origin:010-clb-lutinit 29_55 +CLBLM_R.SLICEL_X1.DLUT.INIT[41] origin:010-clb-lutinit 28_55 +CLBLM_R.SLICEL_X1.DLUT.INIT[42] origin:010-clb-lutinit 29_54 +CLBLM_R.SLICEL_X1.DLUT.INIT[43] origin:010-clb-lutinit 28_54 +CLBLM_R.SLICEL_X1.DLUT.INIT[44] origin:010-clb-lutinit 29_53 +CLBLM_R.SLICEL_X1.DLUT.INIT[45] origin:010-clb-lutinit 28_53 +CLBLM_R.SLICEL_X1.DLUT.INIT[46] origin:010-clb-lutinit 29_52 +CLBLM_R.SLICEL_X1.DLUT.INIT[47] origin:010-clb-lutinit 28_52 +CLBLM_R.SLICEL_X1.DLUT.INIT[48] origin:010-clb-lutinit 26_51 +CLBLM_R.SLICEL_X1.DLUT.INIT[49] origin:010-clb-lutinit 27_51 +CLBLM_R.SLICEL_X1.DLUT.INIT[50] origin:010-clb-lutinit 26_50 +CLBLM_R.SLICEL_X1.DLUT.INIT[51] origin:010-clb-lutinit 27_50 +CLBLM_R.SLICEL_X1.DLUT.INIT[52] origin:010-clb-lutinit 26_49 +CLBLM_R.SLICEL_X1.DLUT.INIT[53] origin:010-clb-lutinit 27_49 +CLBLM_R.SLICEL_X1.DLUT.INIT[54] origin:010-clb-lutinit 26_48 +CLBLM_R.SLICEL_X1.DLUT.INIT[55] origin:010-clb-lutinit 27_48 +CLBLM_R.SLICEL_X1.DLUT.INIT[56] origin:010-clb-lutinit 29_51 +CLBLM_R.SLICEL_X1.DLUT.INIT[57] origin:010-clb-lutinit 28_51 +CLBLM_R.SLICEL_X1.DLUT.INIT[58] origin:010-clb-lutinit 29_50 +CLBLM_R.SLICEL_X1.DLUT.INIT[59] origin:010-clb-lutinit 28_50 +CLBLM_R.SLICEL_X1.DLUT.INIT[60] origin:010-clb-lutinit 29_49 +CLBLM_R.SLICEL_X1.DLUT.INIT[61] origin:010-clb-lutinit 28_49 +CLBLM_R.SLICEL_X1.DLUT.INIT[62] origin:010-clb-lutinit 29_48 +CLBLM_R.SLICEL_X1.DLUT.INIT[63] origin:010-clb-lutinit 28_48 +CLBLM_R.SLICEL_X1.DOUTMUX.CY origin:016-clb-noutmux !31_53 !31_56 30_53 31_57 +CLBLM_R.SLICEL_X1.DOUTMUX.D5Q origin:016-clb-noutmux !30_53 !31_56 !31_57 31_53 +CLBLM_R.SLICEL_X1.DOUTMUX.O5 origin:016-clb-noutmux !30_53 !31_53 31_56 31_57 +CLBLM_R.SLICEL_X1.DOUTMUX.O6 origin:016-clb-noutmux !30_53 !31_53 !31_57 31_56 +CLBLM_R.SLICEL_X1.DOUTMUX.XOR origin:016-clb-noutmux !31_53 !31_56 !31_57 30_53 +CLBLM_R.SLICEL_X1.FFSYNC origin:011-clb-ffconfig 01_31 +CLBLM_R.SLICEL_X1.LATCH origin:011-clb-ffconfig 31_32 +CLBLM_R.SLICEL_X1.PRECYINIT.AX origin:017-clb-precyinit !01_11 !31_12 31_13 +CLBLM_R.SLICEL_X1.PRECYINIT.C0 origin:017-clb-precyinit !01_11 !31_12 !31_13 +CLBLM_R.SLICEL_X1.PRECYINIT.C1 origin:017-clb-precyinit !31_12 !31_13 01_11 +CLBLM_R.SLICEL_X1.PRECYINIT.CIN origin:017-clb-precyinit !01_11 !31_13 31_12 +CLBLM_R.SLICEL_X1.SRUSEDMUX origin:014-clb-ffsrcemux 00_32 +CLBLM_R.SLICEM_X0.A5FF.ZINI origin:011-clb-ffconfig 31_06 +CLBLM_R.SLICEM_X0.A5FF.ZRST origin:011-clb-ffconfig 01_07 +CLBLM_R.SLICEM_X0.A5FFMUX.IN_A origin:012-clb-n5ffmux 30_09 +CLBLM_R.SLICEM_X0.A5FFMUX.IN_B origin:012-clb-n5ffmux 30_10 +CLBLM_R.SLICEM_X0.AFF.ZINI origin:011-clb-ffconfig 31_03 +CLBLM_R.SLICEM_X0.AFF.ZRST origin:011-clb-ffconfig 30_12 +CLBLM_R.SLICEM_X0.AFFMUX.AX origin:015-clb-nffmux !30_00 !30_02 !30_03 30_01 +CLBLM_R.SLICEM_X0.AFFMUX.CY origin:015-clb-nffmux !30_01 !30_03 30_00 30_02 +CLBLM_R.SLICEM_X0.AFFMUX.F7 origin:015-clb-nffmux !30_02 !30_03 30_00 30_01 +CLBLM_R.SLICEM_X0.AFFMUX.O5 origin:015-clb-nffmux !30_01 !30_02 30_00 30_03 +CLBLM_R.SLICEM_X0.AFFMUX.O6 origin:015-clb-nffmux !30_00 !30_01 !30_02 30_03 +CLBLM_R.SLICEM_X0.AFFMUX.XOR origin:015-clb-nffmux !30_00 !30_01 !30_03 30_02 +CLBLM_R.SLICEM_X0.ALUT.DI1MUX.AI origin:019-clb-ndi1mux 00_00 +CLBLM_R.SLICEM_X0.ALUT.INIT[00] origin:010-clb-lutinit 34_15 +CLBLM_R.SLICEM_X0.ALUT.INIT[01] origin:010-clb-lutinit 35_15 +CLBLM_R.SLICEM_X0.ALUT.INIT[02] origin:010-clb-lutinit 34_14 +CLBLM_R.SLICEM_X0.ALUT.INIT[03] origin:010-clb-lutinit 35_14 +CLBLM_R.SLICEM_X0.ALUT.INIT[04] origin:010-clb-lutinit 34_13 +CLBLM_R.SLICEM_X0.ALUT.INIT[05] origin:010-clb-lutinit 35_13 +CLBLM_R.SLICEM_X0.ALUT.INIT[06] origin:010-clb-lutinit 34_12 +CLBLM_R.SLICEM_X0.ALUT.INIT[07] origin:010-clb-lutinit 35_12 +CLBLM_R.SLICEM_X0.ALUT.INIT[08] origin:010-clb-lutinit 32_15 +CLBLM_R.SLICEM_X0.ALUT.INIT[09] origin:010-clb-lutinit 33_15 +CLBLM_R.SLICEM_X0.ALUT.INIT[10] origin:010-clb-lutinit 32_14 +CLBLM_R.SLICEM_X0.ALUT.INIT[11] origin:010-clb-lutinit 33_14 +CLBLM_R.SLICEM_X0.ALUT.INIT[12] origin:010-clb-lutinit 32_13 +CLBLM_R.SLICEM_X0.ALUT.INIT[13] origin:010-clb-lutinit 33_13 +CLBLM_R.SLICEM_X0.ALUT.INIT[14] origin:010-clb-lutinit 32_12 +CLBLM_R.SLICEM_X0.ALUT.INIT[15] origin:010-clb-lutinit 33_12 +CLBLM_R.SLICEM_X0.ALUT.INIT[16] origin:010-clb-lutinit 34_11 +CLBLM_R.SLICEM_X0.ALUT.INIT[17] origin:010-clb-lutinit 35_11 +CLBLM_R.SLICEM_X0.ALUT.INIT[18] origin:010-clb-lutinit 34_10 +CLBLM_R.SLICEM_X0.ALUT.INIT[19] origin:010-clb-lutinit 35_10 +CLBLM_R.SLICEM_X0.ALUT.INIT[20] origin:010-clb-lutinit 34_09 +CLBLM_R.SLICEM_X0.ALUT.INIT[21] origin:010-clb-lutinit 35_09 +CLBLM_R.SLICEM_X0.ALUT.INIT[22] origin:010-clb-lutinit 34_08 +CLBLM_R.SLICEM_X0.ALUT.INIT[23] origin:010-clb-lutinit 35_08 +CLBLM_R.SLICEM_X0.ALUT.INIT[24] origin:010-clb-lutinit 32_11 +CLBLM_R.SLICEM_X0.ALUT.INIT[25] origin:010-clb-lutinit 33_11 +CLBLM_R.SLICEM_X0.ALUT.INIT[26] origin:010-clb-lutinit 32_10 +CLBLM_R.SLICEM_X0.ALUT.INIT[27] origin:010-clb-lutinit 33_10 +CLBLM_R.SLICEM_X0.ALUT.INIT[28] origin:010-clb-lutinit 32_09 +CLBLM_R.SLICEM_X0.ALUT.INIT[29] origin:010-clb-lutinit 33_09 +CLBLM_R.SLICEM_X0.ALUT.INIT[30] origin:010-clb-lutinit 32_08 +CLBLM_R.SLICEM_X0.ALUT.INIT[31] origin:010-clb-lutinit 33_08 +CLBLM_R.SLICEM_X0.ALUT.INIT[32] origin:010-clb-lutinit 34_07 +CLBLM_R.SLICEM_X0.ALUT.INIT[33] origin:010-clb-lutinit 35_07 +CLBLM_R.SLICEM_X0.ALUT.INIT[34] origin:010-clb-lutinit 34_06 +CLBLM_R.SLICEM_X0.ALUT.INIT[35] origin:010-clb-lutinit 35_06 +CLBLM_R.SLICEM_X0.ALUT.INIT[36] origin:010-clb-lutinit 34_05 +CLBLM_R.SLICEM_X0.ALUT.INIT[37] origin:010-clb-lutinit 35_05 +CLBLM_R.SLICEM_X0.ALUT.INIT[38] origin:010-clb-lutinit 34_04 +CLBLM_R.SLICEM_X0.ALUT.INIT[39] origin:010-clb-lutinit 35_04 +CLBLM_R.SLICEM_X0.ALUT.INIT[40] origin:010-clb-lutinit 32_07 +CLBLM_R.SLICEM_X0.ALUT.INIT[41] origin:010-clb-lutinit 33_07 +CLBLM_R.SLICEM_X0.ALUT.INIT[42] origin:010-clb-lutinit 32_06 +CLBLM_R.SLICEM_X0.ALUT.INIT[43] origin:010-clb-lutinit 33_06 +CLBLM_R.SLICEM_X0.ALUT.INIT[44] origin:010-clb-lutinit 32_05 +CLBLM_R.SLICEM_X0.ALUT.INIT[45] origin:010-clb-lutinit 33_05 +CLBLM_R.SLICEM_X0.ALUT.INIT[46] origin:010-clb-lutinit 32_04 +CLBLM_R.SLICEM_X0.ALUT.INIT[47] origin:010-clb-lutinit 33_04 +CLBLM_R.SLICEM_X0.ALUT.INIT[48] origin:010-clb-lutinit 34_03 +CLBLM_R.SLICEM_X0.ALUT.INIT[49] origin:010-clb-lutinit 35_03 +CLBLM_R.SLICEM_X0.ALUT.INIT[50] origin:010-clb-lutinit 34_02 +CLBLM_R.SLICEM_X0.ALUT.INIT[51] origin:010-clb-lutinit 35_02 +CLBLM_R.SLICEM_X0.ALUT.INIT[52] origin:010-clb-lutinit 34_01 +CLBLM_R.SLICEM_X0.ALUT.INIT[53] origin:010-clb-lutinit 35_01 +CLBLM_R.SLICEM_X0.ALUT.INIT[54] origin:010-clb-lutinit 34_00 +CLBLM_R.SLICEM_X0.ALUT.INIT[55] origin:010-clb-lutinit 35_00 +CLBLM_R.SLICEM_X0.ALUT.INIT[56] origin:010-clb-lutinit 32_03 +CLBLM_R.SLICEM_X0.ALUT.INIT[57] origin:010-clb-lutinit 33_03 +CLBLM_R.SLICEM_X0.ALUT.INIT[58] origin:010-clb-lutinit 32_02 +CLBLM_R.SLICEM_X0.ALUT.INIT[59] origin:010-clb-lutinit 33_02 +CLBLM_R.SLICEM_X0.ALUT.INIT[60] origin:010-clb-lutinit 32_01 +CLBLM_R.SLICEM_X0.ALUT.INIT[61] origin:010-clb-lutinit 33_01 +CLBLM_R.SLICEM_X0.ALUT.INIT[62] origin:010-clb-lutinit 32_00 +CLBLM_R.SLICEM_X0.ALUT.INIT[63] origin:010-clb-lutinit 33_00 +CLBLM_R.SLICEM_X0.ALUT.RAM origin:018-clb-ram 31_16 +CLBLM_R.SLICEM_X0.ALUT.SMALL origin:018-clb-ram 00_04 +CLBLM_R.SLICEM_X0.ALUT.SRL origin:018-clb-ram 30_16 +CLBLM_R.SLICEM_X0.AOUTMUX.A5Q origin:016-clb-noutmux !30_06 !30_08 !30_11 30_07 +CLBLM_R.SLICEM_X0.AOUTMUX.CY origin:016-clb-noutmux !30_07 !30_11 30_06 30_08 +CLBLM_R.SLICEM_X0.AOUTMUX.F7 origin:016-clb-noutmux !30_08 !30_11 30_06 30_07 +CLBLM_R.SLICEM_X0.AOUTMUX.O5 origin:016-clb-noutmux !30_07 !30_08 30_06 30_11 +CLBLM_R.SLICEM_X0.AOUTMUX.O6 origin:016-clb-noutmux !30_06 !30_07 !30_08 30_11 +CLBLM_R.SLICEM_X0.AOUTMUX.XOR origin:016-clb-noutmux !30_06 !30_07 !30_11 30_08 +CLBLM_R.SLICEM_X0.B5FF.ZINI origin:011-clb-ffconfig 31_22 +CLBLM_R.SLICEM_X0.B5FF.ZRST origin:011-clb-ffconfig 01_19 +CLBLM_R.SLICEM_X0.B5FFMUX.IN_A origin:012-clb-n5ffmux 30_19 +CLBLM_R.SLICEM_X0.B5FFMUX.IN_B origin:012-clb-n5ffmux 30_18 +CLBLM_R.SLICEM_X0.BFF.ZINI origin:011-clb-ffconfig 31_28 +CLBLM_R.SLICEM_X0.BFF.ZRST origin:011-clb-ffconfig 30_30 +CLBLM_R.SLICEM_X0.BFFMUX.BX origin:015-clb-nffmux !30_24 !30_25 !30_27 30_26 +CLBLM_R.SLICEM_X0.BFFMUX.CY origin:015-clb-nffmux !30_24 !30_26 30_25 30_27 +CLBLM_R.SLICEM_X0.BFFMUX.F8 origin:015-clb-nffmux !30_24 !30_25 30_26 30_27 +CLBLM_R.SLICEM_X0.BFFMUX.O5 origin:015-clb-nffmux !30_25 !30_26 30_24 30_27 +CLBLM_R.SLICEM_X0.BFFMUX.O6 origin:015-clb-nffmux !30_25 !30_26 !30_27 30_24 +CLBLM_R.SLICEM_X0.BFFMUX.XOR origin:015-clb-nffmux !30_24 !30_26 !30_27 30_25 +CLBLM_R.SLICEM_X0.BLUT.DI1MUX.BI origin:019-clb-ndi1mux 00_20 +CLBLM_R.SLICEM_X0.BLUT.INIT[00] origin:010-clb-lutinit 34_31 +CLBLM_R.SLICEM_X0.BLUT.INIT[01] origin:010-clb-lutinit 35_31 +CLBLM_R.SLICEM_X0.BLUT.INIT[02] origin:010-clb-lutinit 34_30 +CLBLM_R.SLICEM_X0.BLUT.INIT[03] origin:010-clb-lutinit 35_30 +CLBLM_R.SLICEM_X0.BLUT.INIT[04] origin:010-clb-lutinit 34_29 +CLBLM_R.SLICEM_X0.BLUT.INIT[05] origin:010-clb-lutinit 35_29 +CLBLM_R.SLICEM_X0.BLUT.INIT[06] origin:010-clb-lutinit 34_28 +CLBLM_R.SLICEM_X0.BLUT.INIT[07] origin:010-clb-lutinit 35_28 +CLBLM_R.SLICEM_X0.BLUT.INIT[08] origin:010-clb-lutinit 32_31 +CLBLM_R.SLICEM_X0.BLUT.INIT[09] origin:010-clb-lutinit 33_31 +CLBLM_R.SLICEM_X0.BLUT.INIT[10] origin:010-clb-lutinit 32_30 +CLBLM_R.SLICEM_X0.BLUT.INIT[11] origin:010-clb-lutinit 33_30 +CLBLM_R.SLICEM_X0.BLUT.INIT[12] origin:010-clb-lutinit 32_29 +CLBLM_R.SLICEM_X0.BLUT.INIT[13] origin:010-clb-lutinit 33_29 +CLBLM_R.SLICEM_X0.BLUT.INIT[14] origin:010-clb-lutinit 32_28 +CLBLM_R.SLICEM_X0.BLUT.INIT[15] origin:010-clb-lutinit 33_28 +CLBLM_R.SLICEM_X0.BLUT.INIT[16] origin:010-clb-lutinit 34_27 +CLBLM_R.SLICEM_X0.BLUT.INIT[17] origin:010-clb-lutinit 35_27 +CLBLM_R.SLICEM_X0.BLUT.INIT[18] origin:010-clb-lutinit 34_26 +CLBLM_R.SLICEM_X0.BLUT.INIT[19] origin:010-clb-lutinit 35_26 +CLBLM_R.SLICEM_X0.BLUT.INIT[20] origin:010-clb-lutinit 34_25 +CLBLM_R.SLICEM_X0.BLUT.INIT[21] origin:010-clb-lutinit 35_25 +CLBLM_R.SLICEM_X0.BLUT.INIT[22] origin:010-clb-lutinit 34_24 +CLBLM_R.SLICEM_X0.BLUT.INIT[23] origin:010-clb-lutinit 35_24 +CLBLM_R.SLICEM_X0.BLUT.INIT[24] origin:010-clb-lutinit 32_27 +CLBLM_R.SLICEM_X0.BLUT.INIT[25] origin:010-clb-lutinit 33_27 +CLBLM_R.SLICEM_X0.BLUT.INIT[26] origin:010-clb-lutinit 32_26 +CLBLM_R.SLICEM_X0.BLUT.INIT[27] origin:010-clb-lutinit 33_26 +CLBLM_R.SLICEM_X0.BLUT.INIT[28] origin:010-clb-lutinit 32_25 +CLBLM_R.SLICEM_X0.BLUT.INIT[29] origin:010-clb-lutinit 33_25 +CLBLM_R.SLICEM_X0.BLUT.INIT[30] origin:010-clb-lutinit 32_24 +CLBLM_R.SLICEM_X0.BLUT.INIT[31] origin:010-clb-lutinit 33_24 +CLBLM_R.SLICEM_X0.BLUT.INIT[32] origin:010-clb-lutinit 34_23 +CLBLM_R.SLICEM_X0.BLUT.INIT[33] origin:010-clb-lutinit 35_23 +CLBLM_R.SLICEM_X0.BLUT.INIT[34] origin:010-clb-lutinit 34_22 +CLBLM_R.SLICEM_X0.BLUT.INIT[35] origin:010-clb-lutinit 35_22 +CLBLM_R.SLICEM_X0.BLUT.INIT[36] origin:010-clb-lutinit 34_21 +CLBLM_R.SLICEM_X0.BLUT.INIT[37] origin:010-clb-lutinit 35_21 +CLBLM_R.SLICEM_X0.BLUT.INIT[38] origin:010-clb-lutinit 34_20 +CLBLM_R.SLICEM_X0.BLUT.INIT[39] origin:010-clb-lutinit 35_20 +CLBLM_R.SLICEM_X0.BLUT.INIT[40] origin:010-clb-lutinit 32_23 +CLBLM_R.SLICEM_X0.BLUT.INIT[41] origin:010-clb-lutinit 33_23 +CLBLM_R.SLICEM_X0.BLUT.INIT[42] origin:010-clb-lutinit 32_22 +CLBLM_R.SLICEM_X0.BLUT.INIT[43] origin:010-clb-lutinit 33_22 +CLBLM_R.SLICEM_X0.BLUT.INIT[44] origin:010-clb-lutinit 32_21 +CLBLM_R.SLICEM_X0.BLUT.INIT[45] origin:010-clb-lutinit 33_21 +CLBLM_R.SLICEM_X0.BLUT.INIT[46] origin:010-clb-lutinit 32_20 +CLBLM_R.SLICEM_X0.BLUT.INIT[47] origin:010-clb-lutinit 33_20 +CLBLM_R.SLICEM_X0.BLUT.INIT[48] origin:010-clb-lutinit 34_19 +CLBLM_R.SLICEM_X0.BLUT.INIT[49] origin:010-clb-lutinit 35_19 +CLBLM_R.SLICEM_X0.BLUT.INIT[50] origin:010-clb-lutinit 34_18 +CLBLM_R.SLICEM_X0.BLUT.INIT[51] origin:010-clb-lutinit 35_18 +CLBLM_R.SLICEM_X0.BLUT.INIT[52] origin:010-clb-lutinit 34_17 +CLBLM_R.SLICEM_X0.BLUT.INIT[53] origin:010-clb-lutinit 35_17 +CLBLM_R.SLICEM_X0.BLUT.INIT[54] origin:010-clb-lutinit 34_16 +CLBLM_R.SLICEM_X0.BLUT.INIT[55] origin:010-clb-lutinit 35_16 +CLBLM_R.SLICEM_X0.BLUT.INIT[56] origin:010-clb-lutinit 32_19 +CLBLM_R.SLICEM_X0.BLUT.INIT[57] origin:010-clb-lutinit 33_19 +CLBLM_R.SLICEM_X0.BLUT.INIT[58] origin:010-clb-lutinit 32_18 +CLBLM_R.SLICEM_X0.BLUT.INIT[59] origin:010-clb-lutinit 33_18 +CLBLM_R.SLICEM_X0.BLUT.INIT[60] origin:010-clb-lutinit 32_17 +CLBLM_R.SLICEM_X0.BLUT.INIT[61] origin:010-clb-lutinit 33_17 +CLBLM_R.SLICEM_X0.BLUT.INIT[62] origin:010-clb-lutinit 32_16 +CLBLM_R.SLICEM_X0.BLUT.INIT[63] origin:010-clb-lutinit 33_16 +CLBLM_R.SLICEM_X0.BLUT.RAM origin:018-clb-ram 31_17 +CLBLM_R.SLICEM_X0.BLUT.SMALL origin:018-clb-ram 00_24 +CLBLM_R.SLICEM_X0.BLUT.SRL origin:018-clb-ram 30_17 +CLBLM_R.SLICEM_X0.BOUTMUX.B5Q origin:016-clb-noutmux !30_20 !30_21 !30_22 30_23 +CLBLM_R.SLICEM_X0.BOUTMUX.CY origin:016-clb-noutmux !30_20 !30_23 30_21 30_22 +CLBLM_R.SLICEM_X0.BOUTMUX.F8 origin:016-clb-noutmux !30_20 !30_21 30_22 30_23 +CLBLM_R.SLICEM_X0.BOUTMUX.O5 origin:016-clb-noutmux !30_21 !30_23 30_20 30_22 +CLBLM_R.SLICEM_X0.BOUTMUX.O6 origin:016-clb-noutmux !30_21 !30_22 !30_23 30_20 +CLBLM_R.SLICEM_X0.BOUTMUX.XOR origin:016-clb-noutmux !30_20 !30_22 !30_23 30_21 +CLBLM_R.SLICEM_X0.C5FF.ZINI origin:011-clb-ffconfig 31_41 +CLBLM_R.SLICEM_X0.C5FF.ZRST origin:011-clb-ffconfig 01_47 +CLBLM_R.SLICEM_X0.C5FFMUX.IN_A origin:012-clb-n5ffmux 31_45 +CLBLM_R.SLICEM_X0.C5FFMUX.IN_B origin:012-clb-n5ffmux 30_39 +CLBLM_R.SLICEM_X0.CARRY4.ACY0 origin:013-clb-ncy0 30_15 +CLBLM_R.SLICEM_X0.CARRY4.BCY0 origin:013-clb-ncy0 01_15 +CLBLM_R.SLICEM_X0.CARRY4.CCY0 origin:013-clb-ncy0 30_48 +CLBLM_R.SLICEM_X0.CARRY4.DCY0 origin:013-clb-ncy0 30_49 +CLBLM_R.SLICEM_X0.CEUSEDMUX origin:014-clb-ffsrcemux 01_39 +CLBLM_R.SLICEM_X0.CFF.ZINI origin:011-clb-ffconfig 31_33 +CLBLM_R.SLICEM_X0.CFF.ZRST origin:011-clb-ffconfig 30_33 +CLBLM_R.SLICEM_X0.CFFMUX.CX origin:015-clb-nffmux !30_35 !30_37 !30_38 30_36 +CLBLM_R.SLICEM_X0.CFFMUX.CY origin:015-clb-nffmux !30_36 !30_38 30_35 30_37 +CLBLM_R.SLICEM_X0.CFFMUX.F7 origin:015-clb-nffmux !30_37 !30_38 30_35 30_36 +CLBLM_R.SLICEM_X0.CFFMUX.O5 origin:015-clb-nffmux !30_36 !30_37 30_35 30_38 +CLBLM_R.SLICEM_X0.CFFMUX.O6 origin:015-clb-nffmux !30_35 !30_36 !30_37 30_38 +CLBLM_R.SLICEM_X0.CFFMUX.XOR origin:015-clb-nffmux !30_35 !30_36 !30_38 30_37 +CLBLM_R.SLICEM_X0.CLKINV origin:011-clb-ffconfig 01_51 +CLBLM_R.SLICEM_X0.CLUT.DI1MUX.CI origin:019-clb-ndi1mux 01_43 +CLBLM_R.SLICEM_X0.CLUT.INIT[00] origin:010-clb-lutinit 34_47 +CLBLM_R.SLICEM_X0.CLUT.INIT[01] origin:010-clb-lutinit 35_47 +CLBLM_R.SLICEM_X0.CLUT.INIT[02] origin:010-clb-lutinit 34_46 +CLBLM_R.SLICEM_X0.CLUT.INIT[03] origin:010-clb-lutinit 35_46 +CLBLM_R.SLICEM_X0.CLUT.INIT[04] origin:010-clb-lutinit 34_45 +CLBLM_R.SLICEM_X0.CLUT.INIT[05] origin:010-clb-lutinit 35_45 +CLBLM_R.SLICEM_X0.CLUT.INIT[06] origin:010-clb-lutinit 34_44 +CLBLM_R.SLICEM_X0.CLUT.INIT[07] origin:010-clb-lutinit 35_44 +CLBLM_R.SLICEM_X0.CLUT.INIT[08] origin:010-clb-lutinit 32_47 +CLBLM_R.SLICEM_X0.CLUT.INIT[09] origin:010-clb-lutinit 33_47 +CLBLM_R.SLICEM_X0.CLUT.INIT[10] origin:010-clb-lutinit 32_46 +CLBLM_R.SLICEM_X0.CLUT.INIT[11] origin:010-clb-lutinit 33_46 +CLBLM_R.SLICEM_X0.CLUT.INIT[12] origin:010-clb-lutinit 32_45 +CLBLM_R.SLICEM_X0.CLUT.INIT[13] origin:010-clb-lutinit 33_45 +CLBLM_R.SLICEM_X0.CLUT.INIT[14] origin:010-clb-lutinit 32_44 +CLBLM_R.SLICEM_X0.CLUT.INIT[15] origin:010-clb-lutinit 33_44 +CLBLM_R.SLICEM_X0.CLUT.INIT[16] origin:010-clb-lutinit 34_43 +CLBLM_R.SLICEM_X0.CLUT.INIT[17] origin:010-clb-lutinit 35_43 +CLBLM_R.SLICEM_X0.CLUT.INIT[18] origin:010-clb-lutinit 34_42 +CLBLM_R.SLICEM_X0.CLUT.INIT[19] origin:010-clb-lutinit 35_42 +CLBLM_R.SLICEM_X0.CLUT.INIT[20] origin:010-clb-lutinit 34_41 +CLBLM_R.SLICEM_X0.CLUT.INIT[21] origin:010-clb-lutinit 35_41 +CLBLM_R.SLICEM_X0.CLUT.INIT[22] origin:010-clb-lutinit 34_40 +CLBLM_R.SLICEM_X0.CLUT.INIT[23] origin:010-clb-lutinit 35_40 +CLBLM_R.SLICEM_X0.CLUT.INIT[24] origin:010-clb-lutinit 32_43 +CLBLM_R.SLICEM_X0.CLUT.INIT[25] origin:010-clb-lutinit 33_43 +CLBLM_R.SLICEM_X0.CLUT.INIT[26] origin:010-clb-lutinit 32_42 +CLBLM_R.SLICEM_X0.CLUT.INIT[27] origin:010-clb-lutinit 33_42 +CLBLM_R.SLICEM_X0.CLUT.INIT[28] origin:010-clb-lutinit 32_41 +CLBLM_R.SLICEM_X0.CLUT.INIT[29] origin:010-clb-lutinit 33_41 +CLBLM_R.SLICEM_X0.CLUT.INIT[30] origin:010-clb-lutinit 32_40 +CLBLM_R.SLICEM_X0.CLUT.INIT[31] origin:010-clb-lutinit 33_40 +CLBLM_R.SLICEM_X0.CLUT.INIT[32] origin:010-clb-lutinit 34_39 +CLBLM_R.SLICEM_X0.CLUT.INIT[33] origin:010-clb-lutinit 35_39 +CLBLM_R.SLICEM_X0.CLUT.INIT[34] origin:010-clb-lutinit 34_38 +CLBLM_R.SLICEM_X0.CLUT.INIT[35] origin:010-clb-lutinit 35_38 +CLBLM_R.SLICEM_X0.CLUT.INIT[36] origin:010-clb-lutinit 34_37 +CLBLM_R.SLICEM_X0.CLUT.INIT[37] origin:010-clb-lutinit 35_37 +CLBLM_R.SLICEM_X0.CLUT.INIT[38] origin:010-clb-lutinit 34_36 +CLBLM_R.SLICEM_X0.CLUT.INIT[39] origin:010-clb-lutinit 35_36 +CLBLM_R.SLICEM_X0.CLUT.INIT[40] origin:010-clb-lutinit 32_39 +CLBLM_R.SLICEM_X0.CLUT.INIT[41] origin:010-clb-lutinit 33_39 +CLBLM_R.SLICEM_X0.CLUT.INIT[42] origin:010-clb-lutinit 32_38 +CLBLM_R.SLICEM_X0.CLUT.INIT[43] origin:010-clb-lutinit 33_38 +CLBLM_R.SLICEM_X0.CLUT.INIT[44] origin:010-clb-lutinit 32_37 +CLBLM_R.SLICEM_X0.CLUT.INIT[45] origin:010-clb-lutinit 33_37 +CLBLM_R.SLICEM_X0.CLUT.INIT[46] origin:010-clb-lutinit 32_36 +CLBLM_R.SLICEM_X0.CLUT.INIT[47] origin:010-clb-lutinit 33_36 +CLBLM_R.SLICEM_X0.CLUT.INIT[48] origin:010-clb-lutinit 34_35 +CLBLM_R.SLICEM_X0.CLUT.INIT[49] origin:010-clb-lutinit 35_35 +CLBLM_R.SLICEM_X0.CLUT.INIT[50] origin:010-clb-lutinit 34_34 +CLBLM_R.SLICEM_X0.CLUT.INIT[51] origin:010-clb-lutinit 35_34 +CLBLM_R.SLICEM_X0.CLUT.INIT[52] origin:010-clb-lutinit 34_33 +CLBLM_R.SLICEM_X0.CLUT.INIT[53] origin:010-clb-lutinit 35_33 +CLBLM_R.SLICEM_X0.CLUT.INIT[54] origin:010-clb-lutinit 34_32 +CLBLM_R.SLICEM_X0.CLUT.INIT[55] origin:010-clb-lutinit 35_32 +CLBLM_R.SLICEM_X0.CLUT.INIT[56] origin:010-clb-lutinit 32_35 +CLBLM_R.SLICEM_X0.CLUT.INIT[57] origin:010-clb-lutinit 33_35 +CLBLM_R.SLICEM_X0.CLUT.INIT[58] origin:010-clb-lutinit 32_34 +CLBLM_R.SLICEM_X0.CLUT.INIT[59] origin:010-clb-lutinit 33_34 +CLBLM_R.SLICEM_X0.CLUT.INIT[60] origin:010-clb-lutinit 32_33 +CLBLM_R.SLICEM_X0.CLUT.INIT[61] origin:010-clb-lutinit 33_33 +CLBLM_R.SLICEM_X0.CLUT.INIT[62] origin:010-clb-lutinit 32_32 +CLBLM_R.SLICEM_X0.CLUT.INIT[63] origin:010-clb-lutinit 33_32 +CLBLM_R.SLICEM_X0.CLUT.RAM origin:018-clb-ram 31_46 +CLBLM_R.SLICEM_X0.CLUT.SMALL origin:018-clb-ram 00_28 +CLBLM_R.SLICEM_X0.CLUT.SRL origin:018-clb-ram 30_46 +CLBLM_R.SLICEM_X0.COUTMUX.C5Q origin:016-clb-noutmux !30_40 !30_44 !30_45 30_43 +CLBLM_R.SLICEM_X0.COUTMUX.CY origin:016-clb-noutmux !30_43 !30_45 30_40 30_44 +CLBLM_R.SLICEM_X0.COUTMUX.F7 origin:016-clb-noutmux !30_44 !30_45 30_40 30_43 +CLBLM_R.SLICEM_X0.COUTMUX.O5 origin:016-clb-noutmux !30_43 !30_44 30_40 30_45 +CLBLM_R.SLICEM_X0.COUTMUX.O6 origin:016-clb-noutmux !30_40 !30_43 !30_44 30_45 +CLBLM_R.SLICEM_X0.COUTMUX.XOR origin:016-clb-noutmux !30_40 !30_43 !30_45 30_44 +CLBLM_R.SLICEM_X0.D5FF.ZINI origin:011-clb-ffconfig 31_51 +CLBLM_R.SLICEM_X0.D5FF.ZRST origin:011-clb-ffconfig 01_55 +CLBLM_R.SLICEM_X0.D5FFMUX.IN_A origin:012-clb-n5ffmux 30_55 +CLBLM_R.SLICEM_X0.D5FFMUX.IN_B origin:012-clb-n5ffmux 30_54 +CLBLM_R.SLICEM_X0.DFF.ZINI origin:011-clb-ffconfig 31_58 +CLBLM_R.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50 +CLBLM_R.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62 +CLBLM_R.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61 +CLBLM_R.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62 +CLBLM_R.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59 +CLBLM_R.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60 +CLBLM_R.SLICEM_X0.DLUT.INIT[00] origin:010-clb-lutinit 34_63 +CLBLM_R.SLICEM_X0.DLUT.INIT[01] origin:010-clb-lutinit 35_63 +CLBLM_R.SLICEM_X0.DLUT.INIT[02] origin:010-clb-lutinit 34_62 +CLBLM_R.SLICEM_X0.DLUT.INIT[03] origin:010-clb-lutinit 35_62 +CLBLM_R.SLICEM_X0.DLUT.INIT[04] origin:010-clb-lutinit 34_61 +CLBLM_R.SLICEM_X0.DLUT.INIT[05] origin:010-clb-lutinit 35_61 +CLBLM_R.SLICEM_X0.DLUT.INIT[06] origin:010-clb-lutinit 34_60 +CLBLM_R.SLICEM_X0.DLUT.INIT[07] origin:010-clb-lutinit 35_60 +CLBLM_R.SLICEM_X0.DLUT.INIT[08] origin:010-clb-lutinit 32_63 +CLBLM_R.SLICEM_X0.DLUT.INIT[09] origin:010-clb-lutinit 33_63 +CLBLM_R.SLICEM_X0.DLUT.INIT[10] origin:010-clb-lutinit 32_62 +CLBLM_R.SLICEM_X0.DLUT.INIT[11] origin:010-clb-lutinit 33_62 +CLBLM_R.SLICEM_X0.DLUT.INIT[12] origin:010-clb-lutinit 32_61 +CLBLM_R.SLICEM_X0.DLUT.INIT[13] origin:010-clb-lutinit 33_61 +CLBLM_R.SLICEM_X0.DLUT.INIT[14] origin:010-clb-lutinit 32_60 +CLBLM_R.SLICEM_X0.DLUT.INIT[15] origin:010-clb-lutinit 33_60 +CLBLM_R.SLICEM_X0.DLUT.INIT[16] origin:010-clb-lutinit 34_59 +CLBLM_R.SLICEM_X0.DLUT.INIT[17] origin:010-clb-lutinit 35_59 +CLBLM_R.SLICEM_X0.DLUT.INIT[18] origin:010-clb-lutinit 34_58 +CLBLM_R.SLICEM_X0.DLUT.INIT[19] origin:010-clb-lutinit 35_58 +CLBLM_R.SLICEM_X0.DLUT.INIT[20] origin:010-clb-lutinit 34_57 +CLBLM_R.SLICEM_X0.DLUT.INIT[21] origin:010-clb-lutinit 35_57 +CLBLM_R.SLICEM_X0.DLUT.INIT[22] origin:010-clb-lutinit 34_56 +CLBLM_R.SLICEM_X0.DLUT.INIT[23] origin:010-clb-lutinit 35_56 +CLBLM_R.SLICEM_X0.DLUT.INIT[24] origin:010-clb-lutinit 32_59 +CLBLM_R.SLICEM_X0.DLUT.INIT[25] origin:010-clb-lutinit 33_59 +CLBLM_R.SLICEM_X0.DLUT.INIT[26] origin:010-clb-lutinit 32_58 +CLBLM_R.SLICEM_X0.DLUT.INIT[27] origin:010-clb-lutinit 33_58 +CLBLM_R.SLICEM_X0.DLUT.INIT[28] origin:010-clb-lutinit 32_57 +CLBLM_R.SLICEM_X0.DLUT.INIT[29] origin:010-clb-lutinit 33_57 +CLBLM_R.SLICEM_X0.DLUT.INIT[30] origin:010-clb-lutinit 32_56 +CLBLM_R.SLICEM_X0.DLUT.INIT[31] origin:010-clb-lutinit 33_56 +CLBLM_R.SLICEM_X0.DLUT.INIT[32] origin:010-clb-lutinit 34_55 +CLBLM_R.SLICEM_X0.DLUT.INIT[33] origin:010-clb-lutinit 35_55 +CLBLM_R.SLICEM_X0.DLUT.INIT[34] origin:010-clb-lutinit 34_54 +CLBLM_R.SLICEM_X0.DLUT.INIT[35] origin:010-clb-lutinit 35_54 +CLBLM_R.SLICEM_X0.DLUT.INIT[36] origin:010-clb-lutinit 34_53 +CLBLM_R.SLICEM_X0.DLUT.INIT[37] origin:010-clb-lutinit 35_53 +CLBLM_R.SLICEM_X0.DLUT.INIT[38] origin:010-clb-lutinit 34_52 +CLBLM_R.SLICEM_X0.DLUT.INIT[39] origin:010-clb-lutinit 35_52 +CLBLM_R.SLICEM_X0.DLUT.INIT[40] origin:010-clb-lutinit 32_55 +CLBLM_R.SLICEM_X0.DLUT.INIT[41] origin:010-clb-lutinit 33_55 +CLBLM_R.SLICEM_X0.DLUT.INIT[42] origin:010-clb-lutinit 32_54 +CLBLM_R.SLICEM_X0.DLUT.INIT[43] origin:010-clb-lutinit 33_54 +CLBLM_R.SLICEM_X0.DLUT.INIT[44] origin:010-clb-lutinit 32_53 +CLBLM_R.SLICEM_X0.DLUT.INIT[45] origin:010-clb-lutinit 33_53 +CLBLM_R.SLICEM_X0.DLUT.INIT[46] origin:010-clb-lutinit 32_52 +CLBLM_R.SLICEM_X0.DLUT.INIT[47] origin:010-clb-lutinit 33_52 +CLBLM_R.SLICEM_X0.DLUT.INIT[48] origin:010-clb-lutinit 34_51 +CLBLM_R.SLICEM_X0.DLUT.INIT[49] origin:010-clb-lutinit 35_51 +CLBLM_R.SLICEM_X0.DLUT.INIT[50] origin:010-clb-lutinit 34_50 +CLBLM_R.SLICEM_X0.DLUT.INIT[51] origin:010-clb-lutinit 35_50 +CLBLM_R.SLICEM_X0.DLUT.INIT[52] origin:010-clb-lutinit 34_49 +CLBLM_R.SLICEM_X0.DLUT.INIT[53] origin:010-clb-lutinit 35_49 +CLBLM_R.SLICEM_X0.DLUT.INIT[54] origin:010-clb-lutinit 34_48 +CLBLM_R.SLICEM_X0.DLUT.INIT[55] origin:010-clb-lutinit 35_48 +CLBLM_R.SLICEM_X0.DLUT.INIT[56] origin:010-clb-lutinit 32_51 +CLBLM_R.SLICEM_X0.DLUT.INIT[57] origin:010-clb-lutinit 33_51 +CLBLM_R.SLICEM_X0.DLUT.INIT[58] origin:010-clb-lutinit 32_50 +CLBLM_R.SLICEM_X0.DLUT.INIT[59] origin:010-clb-lutinit 33_50 +CLBLM_R.SLICEM_X0.DLUT.INIT[60] origin:010-clb-lutinit 32_49 +CLBLM_R.SLICEM_X0.DLUT.INIT[61] origin:010-clb-lutinit 33_49 +CLBLM_R.SLICEM_X0.DLUT.INIT[62] origin:010-clb-lutinit 32_48 +CLBLM_R.SLICEM_X0.DLUT.INIT[63] origin:010-clb-lutinit 33_48 +CLBLM_R.SLICEM_X0.DLUT.RAM origin:018-clb-ram 31_47 +CLBLM_R.SLICEM_X0.DLUT.SMALL origin:018-clb-ram 01_59 +CLBLM_R.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47 +CLBLM_R.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52 +CLBLM_R.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57 +CLBLM_R.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56 +CLBLM_R.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56 +CLBLM_R.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51 +CLBLM_R.SLICEM_X0.FFSYNC origin:011-clb-ffconfig 00_48 +CLBLM_R.SLICEM_X0.LATCH origin:011-clb-ffconfig 30_32 +CLBLM_R.SLICEM_X0.PRECYINIT.AX origin:017-clb-precyinit !00_12 !30_13 30_14 +CLBLM_R.SLICEM_X0.PRECYINIT.C0 origin:017-clb-precyinit !00_12 !30_13 !30_14 +CLBLM_R.SLICEM_X0.PRECYINIT.C1 origin:017-clb-precyinit !30_13 !30_14 00_12 +CLBLM_R.SLICEM_X0.PRECYINIT.CIN origin:017-clb-precyinit !00_12 !30_14 30_13 +CLBLM_R.SLICEM_X0.SRUSEDMUX origin:014-clb-ffsrcemux 01_35 +CLBLM_R.SLICEM_X0.WA7USED origin:018-clb-ram 00_40 +CLBLM_R.SLICEM_X0.WA8USED origin:018-clb-ram 01_27 +CLBLM_R.SLICEM_X0.WEMUX.CE origin:018-clb-ram 01_23 diff --git a/zynq7/segbits_clk_bufg_bot_r.origin_info.db b/zynq7/segbits_clk_bufg_bot_r.origin_info.db new file mode 100644 index 0000000..96b2ddd --- /dev/null +++ b/zynq7/segbits_clk_bufg_bot_r.origin_info.db @@ -0,0 +1,336 @@ +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.INIT_OUT origin:042-clk-bufg-config 27_13 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE origin:042-clk-bufg-config 27_00 27_15 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_01 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_12 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.PRESELECT_I1 origin:042-clk-bufg-config 26_12 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0 origin:042-clk-bufg-config 27_02 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE1 origin:042-clk-bufg-config 27_11 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0 origin:042-clk-bufg-config 27_03 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S1 origin:042-clk-bufg-config 26_11 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y0.ZPRESELECT_I0 origin:042-clk-bufg-config 26_02 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT origin:042-clk-bufg-config 27_29 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE origin:042-clk-bufg-config 27_16 27_31 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_17 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_28 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 origin:042-clk-bufg-config 26_28 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 origin:042-clk-bufg-config 27_18 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 origin:042-clk-bufg-config 27_27 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 origin:042-clk-bufg-config 27_19 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 origin:042-clk-bufg-config 26_27 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 origin:042-clk-bufg-config 26_18 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.INIT_OUT origin:042-clk-bufg-config 27_173 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE origin:042-clk-bufg-config 27_160 27_175 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_161 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_172 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.PRESELECT_I1 origin:042-clk-bufg-config 26_172 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE0 origin:042-clk-bufg-config 27_162 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE1 origin:042-clk-bufg-config 27_171 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S0 origin:042-clk-bufg-config 27_163 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S1 origin:042-clk-bufg-config 26_171 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y10.ZPRESELECT_I0 origin:042-clk-bufg-config 26_162 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.INIT_OUT origin:042-clk-bufg-config 27_189 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE origin:042-clk-bufg-config 27_176 27_191 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_177 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_188 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.PRESELECT_I1 origin:042-clk-bufg-config 26_188 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE0 origin:042-clk-bufg-config 27_178 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE1 origin:042-clk-bufg-config 27_187 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S0 origin:042-clk-bufg-config 27_179 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S1 origin:042-clk-bufg-config 26_187 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y11.ZPRESELECT_I0 origin:042-clk-bufg-config 26_178 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.INIT_OUT origin:042-clk-bufg-config 27_205 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE origin:042-clk-bufg-config 27_192 27_207 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_193 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_204 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.PRESELECT_I1 origin:042-clk-bufg-config 26_204 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE0 origin:042-clk-bufg-config 27_194 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE1 origin:042-clk-bufg-config 27_203 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S0 origin:042-clk-bufg-config 27_195 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S1 origin:042-clk-bufg-config 26_203 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y12.ZPRESELECT_I0 origin:042-clk-bufg-config 26_194 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.INIT_OUT origin:042-clk-bufg-config 27_221 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE origin:042-clk-bufg-config 27_208 27_223 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_209 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_220 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.PRESELECT_I1 origin:042-clk-bufg-config 26_220 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE0 origin:042-clk-bufg-config 27_210 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE1 origin:042-clk-bufg-config 27_219 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S0 origin:042-clk-bufg-config 27_211 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S1 origin:042-clk-bufg-config 26_219 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y13.ZPRESELECT_I0 origin:042-clk-bufg-config 26_210 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.INIT_OUT origin:042-clk-bufg-config 27_237 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE origin:042-clk-bufg-config 27_224 27_239 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_225 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_236 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.PRESELECT_I1 origin:042-clk-bufg-config 26_236 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE0 origin:042-clk-bufg-config 27_226 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE1 origin:042-clk-bufg-config 27_235 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S0 origin:042-clk-bufg-config 27_227 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S1 origin:042-clk-bufg-config 26_235 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y14.ZPRESELECT_I0 origin:042-clk-bufg-config 26_226 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.INIT_OUT origin:042-clk-bufg-config 27_253 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE origin:042-clk-bufg-config 27_240 27_255 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_241 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_252 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 origin:042-clk-bufg-config 26_252 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE0 origin:042-clk-bufg-config 27_242 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE1 origin:042-clk-bufg-config 27_251 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S0 origin:042-clk-bufg-config 27_243 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S1 origin:042-clk-bufg-config 26_251 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y15.ZPRESELECT_I0 origin:042-clk-bufg-config 26_242 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT origin:042-clk-bufg-config 27_45 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE origin:042-clk-bufg-config 27_32 27_47 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_33 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_44 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 origin:042-clk-bufg-config 26_44 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 origin:042-clk-bufg-config 27_34 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 origin:042-clk-bufg-config 27_43 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 origin:042-clk-bufg-config 27_35 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 origin:042-clk-bufg-config 26_43 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 origin:042-clk-bufg-config 26_34 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT origin:042-clk-bufg-config 27_61 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE origin:042-clk-bufg-config 27_48 27_63 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_49 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_60 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 origin:042-clk-bufg-config 26_60 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 origin:042-clk-bufg-config 27_50 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 origin:042-clk-bufg-config 27_59 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 origin:042-clk-bufg-config 27_51 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 origin:042-clk-bufg-config 26_59 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 origin:042-clk-bufg-config 26_50 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT origin:042-clk-bufg-config 27_77 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE origin:042-clk-bufg-config 27_64 27_79 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_65 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_76 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 origin:042-clk-bufg-config 26_76 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 origin:042-clk-bufg-config 27_66 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 origin:042-clk-bufg-config 27_75 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 origin:042-clk-bufg-config 27_67 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 origin:042-clk-bufg-config 26_75 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 origin:042-clk-bufg-config 26_66 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT origin:042-clk-bufg-config 27_93 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE origin:042-clk-bufg-config 27_80 27_95 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_81 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_92 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 origin:042-clk-bufg-config 26_92 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 origin:042-clk-bufg-config 27_82 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 origin:042-clk-bufg-config 27_91 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 origin:042-clk-bufg-config 27_83 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 origin:042-clk-bufg-config 26_91 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 origin:042-clk-bufg-config 26_82 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT origin:042-clk-bufg-config 27_109 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE origin:042-clk-bufg-config 27_111 27_96 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_97 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_108 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 origin:042-clk-bufg-config 26_108 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 origin:042-clk-bufg-config 27_98 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 origin:042-clk-bufg-config 27_107 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 origin:042-clk-bufg-config 27_99 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 origin:042-clk-bufg-config 26_107 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 origin:042-clk-bufg-config 26_98 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT origin:042-clk-bufg-config 27_125 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE origin:042-clk-bufg-config 27_112 27_127 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_113 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_124 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 origin:042-clk-bufg-config 26_124 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 origin:042-clk-bufg-config 27_114 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 origin:042-clk-bufg-config 27_123 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 origin:042-clk-bufg-config 27_115 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 origin:042-clk-bufg-config 26_123 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 origin:042-clk-bufg-config 26_114 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT origin:042-clk-bufg-config 27_141 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE origin:042-clk-bufg-config 27_128 27_143 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_129 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_140 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 origin:042-clk-bufg-config 26_140 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 origin:042-clk-bufg-config 27_130 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 origin:042-clk-bufg-config 27_139 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 origin:042-clk-bufg-config 27_131 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 origin:042-clk-bufg-config 26_139 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 origin:042-clk-bufg-config 26_130 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT origin:042-clk-bufg-config 27_157 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE origin:042-clk-bufg-config 27_144 27_159 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_145 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_156 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 origin:042-clk-bufg-config 26_156 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 origin:042-clk-bufg-config 27_146 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 origin:042-clk-bufg-config 27_155 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 origin:042-clk-bufg-config 27_147 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 origin:042-clk-bufg-config 26_155 +CLK_BUFG_BOT_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 origin:042-clk-bufg-config 26_146 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_BOT_R_CK_MUXED0 origin:044-clk-bufg-pips !26_07 !27_06 26_08 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_07 !26_08 !27_06 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_08 26_07 27_06 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_BOT_R_CK_MUXED1 origin:044-clk-bufg-pips !26_05 !27_05 26_04 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_04 !26_05 !27_05 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_BOT_R_CK_MUXED20 origin:044-clk-bufg-pips !26_167 !27_166 26_168 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_167 !26_168 !27_166 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_BOT_R_CK_MUXED21 origin:044-clk-bufg-pips !26_165 !27_165 26_164 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_164 !26_165 !27_165 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_BOT_R_CK_MUXED22 origin:044-clk-bufg-pips !26_183 !27_182 26_184 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_183 !26_184 !27_182 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_BOT_R_CK_MUXED23 origin:044-clk-bufg-pips !26_181 !27_181 26_180 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_180 !26_181 !27_181 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_BOT_R_CK_MUXED24 origin:044-clk-bufg-pips !26_199 !27_198 26_200 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_199 !26_200 !27_198 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_BOT_R_CK_MUXED25 origin:044-clk-bufg-pips !26_197 !27_197 26_196 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_196 !26_197 !27_197 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_BOT_R_CK_MUXED26 origin:044-clk-bufg-pips !26_215 !27_214 26_216 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_215 !26_216 !27_214 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_BOT_R_CK_MUXED27 origin:044-clk-bufg-pips !26_213 !27_213 26_212 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_212 !26_213 !27_213 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_BOT_R_CK_MUXED28 origin:044-clk-bufg-pips !26_231 !27_230 26_232 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_231 !26_232 !27_230 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_BOT_R_CK_MUXED29 origin:044-clk-bufg-pips !26_229 !27_229 26_228 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_228 !26_229 !27_229 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_BOT_R_CK_MUXED30 origin:044-clk-bufg-pips !26_247 !27_246 26_248 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_247 !26_248 !27_246 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_BOT_R_CK_MUXED31 origin:044-clk-bufg-pips !26_245 !27_245 26_244 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_244 !26_245 !27_245 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_BOT_R_CK_MUXED2 origin:044-clk-bufg-pips !26_23 !27_22 26_24 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_23 !26_24 !27_22 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_BOT_R_CK_MUXED3 origin:044-clk-bufg-pips !26_21 !27_21 26_20 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_20 !26_21 !27_21 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_BOT_R_CK_MUXED4 origin:044-clk-bufg-pips !26_39 !27_38 26_40 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_39 !26_40 !27_38 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_BOT_R_CK_MUXED5 origin:044-clk-bufg-pips !26_37 !27_37 26_36 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_36 !26_37 !27_37 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_BOT_R_CK_MUXED6 origin:044-clk-bufg-pips !26_55 !27_54 26_56 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_55 !26_56 !27_54 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_BOT_R_CK_MUXED7 origin:044-clk-bufg-pips !26_53 !27_53 26_52 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_52 !26_53 !27_53 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_BOT_R_CK_MUXED8 origin:044-clk-bufg-pips !26_71 !27_70 26_72 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_71 !26_72 !27_70 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_BOT_R_CK_MUXED9 origin:044-clk-bufg-pips !26_69 !27_69 26_68 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_68 !26_69 !27_69 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_BOT_R_CK_MUXED10 origin:044-clk-bufg-pips !26_87 !27_86 26_88 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_87 !26_88 !27_86 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_BOT_R_CK_MUXED11 origin:044-clk-bufg-pips !26_85 !27_85 26_84 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_84 !26_85 !27_85 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_BOT_R_CK_MUXED12 origin:044-clk-bufg-pips !26_103 !27_102 26_104 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_103 !26_104 !27_102 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_BOT_R_CK_MUXED13 origin:044-clk-bufg-pips !26_101 !27_101 26_100 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_100 !26_101 !27_101 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_BOT_R_CK_MUXED14 origin:044-clk-bufg-pips !26_119 !27_118 26_120 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_119 !26_120 !27_118 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_BOT_R_CK_MUXED15 origin:044-clk-bufg-pips !26_117 !27_117 26_116 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_116 !26_117 !27_117 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_BOT_R_CK_MUXED16 origin:044-clk-bufg-pips !26_135 !27_134 26_136 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_135 !26_136 !27_134 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_BOT_R_CK_MUXED17 origin:044-clk-bufg-pips !26_133 !27_133 26_132 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_132 !26_133 !27_133 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_BOT_R_CK_MUXED18 origin:044-clk-bufg-pips !26_151 !27_150 26_152 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_151 !26_152 !27_150 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_BOT_R_CK_MUXED19 origin:044-clk-bufg-pips !26_149 !27_149 26_148 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_148 !26_149 !27_149 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149 +CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK0.CLK_BUFG_BUFGCTRL0_O origin:044-clk-bufg-pips 27_14 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK1.CLK_BUFG_BUFGCTRL1_O origin:044-clk-bufg-pips 27_30 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK10.CLK_BUFG_BUFGCTRL10_O origin:044-clk-bufg-pips 27_174 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK11.CLK_BUFG_BUFGCTRL11_O origin:044-clk-bufg-pips 27_190 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK12.CLK_BUFG_BUFGCTRL12_O origin:044-clk-bufg-pips 27_206 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK13.CLK_BUFG_BUFGCTRL13_O origin:044-clk-bufg-pips 27_222 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK14.CLK_BUFG_BUFGCTRL14_O origin:044-clk-bufg-pips 27_238 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK15.CLK_BUFG_BUFGCTRL15_O origin:044-clk-bufg-pips 27_254 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK2.CLK_BUFG_BUFGCTRL2_O origin:044-clk-bufg-pips 27_46 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK3.CLK_BUFG_BUFGCTRL3_O origin:044-clk-bufg-pips 27_62 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK4.CLK_BUFG_BUFGCTRL4_O origin:044-clk-bufg-pips 27_78 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK5.CLK_BUFG_BUFGCTRL5_O origin:044-clk-bufg-pips 27_94 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK6.CLK_BUFG_BUFGCTRL6_O origin:044-clk-bufg-pips 27_110 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK7.CLK_BUFG_BUFGCTRL7_O origin:044-clk-bufg-pips 27_126 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK8.CLK_BUFG_BUFGCTRL8_O origin:044-clk-bufg-pips 27_142 +CLK_BUFG_BOT_R.CLK_BUFG_CK_GCLK9.CLK_BUFG_BUFGCTRL9_O origin:044-clk-bufg-pips 27_158 diff --git a/zynq7/segbits_clk_bufg_rebuf.origin_info.db b/zynq7/segbits_clk_bufg_rebuf.origin_info.db new file mode 100644 index 0000000..86845c2 --- /dev/null +++ b/zynq7/segbits_clk_bufg_rebuf.origin_info.db @@ -0,0 +1,128 @@ +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT.CLK_BUFG_REBUF_R_CK_GCLK0_TOP origin:043-clk-rebuf-pips 27_15 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT origin:043-clk-rebuf-pips 27_13 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT.CLK_BUFG_REBUF_R_CK_GCLK10_TOP origin:043-clk-rebuf-pips 26_47 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_TOP.CLK_BUFG_REBUF_R_CK_GCLK10_BOT origin:043-clk-rebuf-pips 26_45 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_BOT.CLK_BUFG_REBUF_R_CK_GCLK11_TOP origin:043-clk-rebuf-pips 26_63 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_TOP.CLK_BUFG_REBUF_R_CK_GCLK11_BOT origin:043-clk-rebuf-pips 26_61 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_BOT.CLK_BUFG_REBUF_R_CK_GCLK12_TOP origin:043-clk-rebuf-pips 26_79 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_TOP.CLK_BUFG_REBUF_R_CK_GCLK12_BOT origin:043-clk-rebuf-pips 26_77 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_BOT.CLK_BUFG_REBUF_R_CK_GCLK13_TOP origin:043-clk-rebuf-pips 26_95 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_TOP.CLK_BUFG_REBUF_R_CK_GCLK13_BOT origin:043-clk-rebuf-pips 26_93 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_BOT.CLK_BUFG_REBUF_R_CK_GCLK14_TOP origin:043-clk-rebuf-pips 26_111 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_TOP.CLK_BUFG_REBUF_R_CK_GCLK14_BOT origin:043-clk-rebuf-pips 26_109 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_BOT.CLK_BUFG_REBUF_R_CK_GCLK15_TOP origin:043-clk-rebuf-pips 26_127 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_TOP.CLK_BUFG_REBUF_R_CK_GCLK15_BOT origin:043-clk-rebuf-pips 26_125 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_BOT.CLK_BUFG_REBUF_R_CK_GCLK16_TOP origin:043-clk-rebuf-pips 27_14 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT origin:043-clk-rebuf-pips 27_12 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_BOT.CLK_BUFG_REBUF_R_CK_GCLK17_TOP origin:043-clk-rebuf-pips 27_30 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_TOP.CLK_BUFG_REBUF_R_CK_GCLK17_BOT origin:043-clk-rebuf-pips 27_28 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT.CLK_BUFG_REBUF_R_CK_GCLK18_TOP origin:043-clk-rebuf-pips 27_46 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_TOP.CLK_BUFG_REBUF_R_CK_GCLK18_BOT origin:043-clk-rebuf-pips 27_44 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_BOT.CLK_BUFG_REBUF_R_CK_GCLK19_TOP origin:043-clk-rebuf-pips 27_62 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_TOP.CLK_BUFG_REBUF_R_CK_GCLK19_BOT origin:043-clk-rebuf-pips 27_60 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_BOT.CLK_BUFG_REBUF_R_CK_GCLK1_TOP origin:043-clk-rebuf-pips 27_31 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_TOP.CLK_BUFG_REBUF_R_CK_GCLK1_BOT origin:043-clk-rebuf-pips 27_29 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT.CLK_BUFG_REBUF_R_CK_GCLK20_TOP origin:043-clk-rebuf-pips 27_78 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_TOP.CLK_BUFG_REBUF_R_CK_GCLK20_BOT origin:043-clk-rebuf-pips 27_76 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_BOT.CLK_BUFG_REBUF_R_CK_GCLK21_TOP origin:043-clk-rebuf-pips 27_94 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_TOP.CLK_BUFG_REBUF_R_CK_GCLK21_BOT origin:043-clk-rebuf-pips 27_92 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_BOT.CLK_BUFG_REBUF_R_CK_GCLK22_TOP origin:043-clk-rebuf-pips 27_110 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_TOP.CLK_BUFG_REBUF_R_CK_GCLK22_BOT origin:043-clk-rebuf-pips 27_108 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_BOT.CLK_BUFG_REBUF_R_CK_GCLK23_TOP origin:043-clk-rebuf-pips 27_126 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_TOP.CLK_BUFG_REBUF_R_CK_GCLK23_BOT origin:043-clk-rebuf-pips 27_124 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_BOT.CLK_BUFG_REBUF_R_CK_GCLK24_TOP origin:043-clk-rebuf-pips 26_14 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_TOP.CLK_BUFG_REBUF_R_CK_GCLK24_BOT origin:043-clk-rebuf-pips 26_12 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_BOT.CLK_BUFG_REBUF_R_CK_GCLK25_TOP origin:043-clk-rebuf-pips 26_30 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_TOP.CLK_BUFG_REBUF_R_CK_GCLK25_BOT origin:043-clk-rebuf-pips 26_28 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_BOT.CLK_BUFG_REBUF_R_CK_GCLK26_TOP origin:043-clk-rebuf-pips 26_46 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_TOP.CLK_BUFG_REBUF_R_CK_GCLK26_BOT origin:043-clk-rebuf-pips 26_44 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_BOT.CLK_BUFG_REBUF_R_CK_GCLK27_TOP origin:043-clk-rebuf-pips 26_62 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_TOP.CLK_BUFG_REBUF_R_CK_GCLK27_BOT origin:043-clk-rebuf-pips 26_60 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT.CLK_BUFG_REBUF_R_CK_GCLK28_TOP origin:043-clk-rebuf-pips 26_78 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_TOP.CLK_BUFG_REBUF_R_CK_GCLK28_BOT origin:043-clk-rebuf-pips 26_76 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_BOT.CLK_BUFG_REBUF_R_CK_GCLK29_TOP origin:043-clk-rebuf-pips 26_94 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_TOP.CLK_BUFG_REBUF_R_CK_GCLK29_BOT origin:043-clk-rebuf-pips 26_92 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT.CLK_BUFG_REBUF_R_CK_GCLK2_TOP origin:043-clk-rebuf-pips 27_47 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_TOP.CLK_BUFG_REBUF_R_CK_GCLK2_BOT origin:043-clk-rebuf-pips 27_45 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT.CLK_BUFG_REBUF_R_CK_GCLK30_TOP origin:043-clk-rebuf-pips 26_110 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_TOP.CLK_BUFG_REBUF_R_CK_GCLK30_BOT origin:043-clk-rebuf-pips 26_108 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_BOT.CLK_BUFG_REBUF_R_CK_GCLK31_TOP origin:043-clk-rebuf-pips 26_126 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_TOP.CLK_BUFG_REBUF_R_CK_GCLK31_BOT origin:043-clk-rebuf-pips 26_124 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_BOT.CLK_BUFG_REBUF_R_CK_GCLK3_TOP origin:043-clk-rebuf-pips 27_63 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_TOP.CLK_BUFG_REBUF_R_CK_GCLK3_BOT origin:043-clk-rebuf-pips 27_61 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT.CLK_BUFG_REBUF_R_CK_GCLK4_TOP origin:043-clk-rebuf-pips 27_79 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_TOP.CLK_BUFG_REBUF_R_CK_GCLK4_BOT origin:043-clk-rebuf-pips 27_77 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_BOT.CLK_BUFG_REBUF_R_CK_GCLK5_TOP origin:043-clk-rebuf-pips 27_95 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_TOP.CLK_BUFG_REBUF_R_CK_GCLK5_BOT origin:043-clk-rebuf-pips 27_93 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT.CLK_BUFG_REBUF_R_CK_GCLK6_TOP origin:043-clk-rebuf-pips 27_111 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_TOP.CLK_BUFG_REBUF_R_CK_GCLK6_BOT origin:043-clk-rebuf-pips 27_109 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_BOT.CLK_BUFG_REBUF_R_CK_GCLK7_TOP origin:043-clk-rebuf-pips 27_127 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_TOP.CLK_BUFG_REBUF_R_CK_GCLK7_BOT origin:043-clk-rebuf-pips 27_125 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT.CLK_BUFG_REBUF_R_CK_GCLK8_TOP origin:043-clk-rebuf-pips 26_15 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_TOP.CLK_BUFG_REBUF_R_CK_GCLK8_BOT origin:043-clk-rebuf-pips 26_13 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_BOT.CLK_BUFG_REBUF_R_CK_GCLK9_TOP origin:043-clk-rebuf-pips 26_31 +CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_TOP.CLK_BUFG_REBUF_R_CK_GCLK9_BOT origin:043-clk-rebuf-pips 26_29 +CLK_BUFG_REBUF.GCLK0_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_03 +CLK_BUFG_REBUF.GCLK0_ENABLE_BELOW origin:043-clk-rebuf-pips 27_01 +CLK_BUFG_REBUF.GCLK10_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_35 +CLK_BUFG_REBUF.GCLK10_ENABLE_BELOW origin:043-clk-rebuf-pips 26_33 +CLK_BUFG_REBUF.GCLK11_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_51 +CLK_BUFG_REBUF.GCLK11_ENABLE_BELOW origin:043-clk-rebuf-pips 26_49 +CLK_BUFG_REBUF.GCLK12_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_67 +CLK_BUFG_REBUF.GCLK12_ENABLE_BELOW origin:043-clk-rebuf-pips 26_65 +CLK_BUFG_REBUF.GCLK13_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_83 +CLK_BUFG_REBUF.GCLK13_ENABLE_BELOW origin:043-clk-rebuf-pips 26_81 +CLK_BUFG_REBUF.GCLK14_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_99 +CLK_BUFG_REBUF.GCLK14_ENABLE_BELOW origin:043-clk-rebuf-pips 26_97 +CLK_BUFG_REBUF.GCLK15_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_115 +CLK_BUFG_REBUF.GCLK15_ENABLE_BELOW origin:043-clk-rebuf-pips 26_113 +CLK_BUFG_REBUF.GCLK16_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_02 +CLK_BUFG_REBUF.GCLK16_ENABLE_BELOW origin:043-clk-rebuf-pips 27_00 +CLK_BUFG_REBUF.GCLK17_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_18 +CLK_BUFG_REBUF.GCLK17_ENABLE_BELOW origin:043-clk-rebuf-pips 27_16 +CLK_BUFG_REBUF.GCLK18_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_34 +CLK_BUFG_REBUF.GCLK18_ENABLE_BELOW origin:043-clk-rebuf-pips 27_32 +CLK_BUFG_REBUF.GCLK19_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_50 +CLK_BUFG_REBUF.GCLK19_ENABLE_BELOW origin:043-clk-rebuf-pips 27_48 +CLK_BUFG_REBUF.GCLK1_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_19 +CLK_BUFG_REBUF.GCLK1_ENABLE_BELOW origin:043-clk-rebuf-pips 27_17 +CLK_BUFG_REBUF.GCLK20_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_66 +CLK_BUFG_REBUF.GCLK20_ENABLE_BELOW origin:043-clk-rebuf-pips 27_64 +CLK_BUFG_REBUF.GCLK21_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_82 +CLK_BUFG_REBUF.GCLK21_ENABLE_BELOW origin:043-clk-rebuf-pips 27_80 +CLK_BUFG_REBUF.GCLK22_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_98 +CLK_BUFG_REBUF.GCLK22_ENABLE_BELOW origin:043-clk-rebuf-pips 27_96 +CLK_BUFG_REBUF.GCLK23_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_114 +CLK_BUFG_REBUF.GCLK23_ENABLE_BELOW origin:043-clk-rebuf-pips 27_112 +CLK_BUFG_REBUF.GCLK24_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_02 +CLK_BUFG_REBUF.GCLK24_ENABLE_BELOW origin:043-clk-rebuf-pips 26_00 +CLK_BUFG_REBUF.GCLK25_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_18 +CLK_BUFG_REBUF.GCLK25_ENABLE_BELOW origin:043-clk-rebuf-pips 26_16 +CLK_BUFG_REBUF.GCLK26_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_34 +CLK_BUFG_REBUF.GCLK26_ENABLE_BELOW origin:043-clk-rebuf-pips 26_32 +CLK_BUFG_REBUF.GCLK27_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_50 +CLK_BUFG_REBUF.GCLK27_ENABLE_BELOW origin:043-clk-rebuf-pips 26_48 +CLK_BUFG_REBUF.GCLK28_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_66 +CLK_BUFG_REBUF.GCLK28_ENABLE_BELOW origin:043-clk-rebuf-pips 26_64 +CLK_BUFG_REBUF.GCLK29_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_82 +CLK_BUFG_REBUF.GCLK29_ENABLE_BELOW origin:043-clk-rebuf-pips 26_80 +CLK_BUFG_REBUF.GCLK2_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_35 +CLK_BUFG_REBUF.GCLK2_ENABLE_BELOW origin:043-clk-rebuf-pips 27_33 +CLK_BUFG_REBUF.GCLK30_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_98 +CLK_BUFG_REBUF.GCLK30_ENABLE_BELOW origin:043-clk-rebuf-pips 26_96 +CLK_BUFG_REBUF.GCLK31_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_114 +CLK_BUFG_REBUF.GCLK31_ENABLE_BELOW origin:043-clk-rebuf-pips 26_112 +CLK_BUFG_REBUF.GCLK3_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_51 +CLK_BUFG_REBUF.GCLK3_ENABLE_BELOW origin:043-clk-rebuf-pips 27_49 +CLK_BUFG_REBUF.GCLK4_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_67 +CLK_BUFG_REBUF.GCLK4_ENABLE_BELOW origin:043-clk-rebuf-pips 27_65 +CLK_BUFG_REBUF.GCLK5_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_83 +CLK_BUFG_REBUF.GCLK5_ENABLE_BELOW origin:043-clk-rebuf-pips 27_81 +CLK_BUFG_REBUF.GCLK6_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_99 +CLK_BUFG_REBUF.GCLK6_ENABLE_BELOW origin:043-clk-rebuf-pips 27_97 +CLK_BUFG_REBUF.GCLK7_ENABLE_ABOVE origin:043-clk-rebuf-pips 27_115 +CLK_BUFG_REBUF.GCLK7_ENABLE_BELOW origin:043-clk-rebuf-pips 27_113 +CLK_BUFG_REBUF.GCLK8_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_03 +CLK_BUFG_REBUF.GCLK8_ENABLE_BELOW origin:043-clk-rebuf-pips 26_01 +CLK_BUFG_REBUF.GCLK9_ENABLE_ABOVE origin:043-clk-rebuf-pips 26_19 +CLK_BUFG_REBUF.GCLK9_ENABLE_BELOW origin:043-clk-rebuf-pips 26_17 diff --git a/zynq7/segbits_clk_bufg_top_r.origin_info.db b/zynq7/segbits_clk_bufg_top_r.origin_info.db new file mode 100644 index 0000000..bc53725 --- /dev/null +++ b/zynq7/segbits_clk_bufg_top_r.origin_info.db @@ -0,0 +1,336 @@ +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.INIT_OUT origin:042-clk-bufg-config 27_13 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE origin:042-clk-bufg-config 27_00 27_15 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_01 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_12 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.PRESELECT_I1 origin:042-clk-bufg-config 26_12 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0 origin:042-clk-bufg-config 27_02 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE1 origin:042-clk-bufg-config 27_11 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0 origin:042-clk-bufg-config 27_03 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S1 origin:042-clk-bufg-config 26_11 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y0.ZPRESELECT_I0 origin:042-clk-bufg-config 26_02 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.INIT_OUT origin:042-clk-bufg-config 27_29 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IN_USE origin:042-clk-bufg-config 27_16 27_31 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_17 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_28 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.PRESELECT_I1 origin:042-clk-bufg-config 26_28 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE0 origin:042-clk-bufg-config 27_18 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_CE1 origin:042-clk-bufg-config 27_27 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S0 origin:042-clk-bufg-config 27_19 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZINV_S1 origin:042-clk-bufg-config 26_27 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y1.ZPRESELECT_I0 origin:042-clk-bufg-config 26_18 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.INIT_OUT origin:042-clk-bufg-config 27_173 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IN_USE origin:042-clk-bufg-config 27_160 27_175 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_161 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_172 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.PRESELECT_I1 origin:042-clk-bufg-config 26_172 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE0 origin:042-clk-bufg-config 27_162 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_CE1 origin:042-clk-bufg-config 27_171 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S0 origin:042-clk-bufg-config 27_163 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZINV_S1 origin:042-clk-bufg-config 26_171 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y10.ZPRESELECT_I0 origin:042-clk-bufg-config 26_162 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.INIT_OUT origin:042-clk-bufg-config 27_189 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IN_USE origin:042-clk-bufg-config 27_176 27_191 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_177 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_188 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.PRESELECT_I1 origin:042-clk-bufg-config 26_188 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE0 origin:042-clk-bufg-config 27_178 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_CE1 origin:042-clk-bufg-config 27_187 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S0 origin:042-clk-bufg-config 27_179 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZINV_S1 origin:042-clk-bufg-config 26_187 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y11.ZPRESELECT_I0 origin:042-clk-bufg-config 26_178 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.INIT_OUT origin:042-clk-bufg-config 27_205 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IN_USE origin:042-clk-bufg-config 27_192 27_207 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_193 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_204 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.PRESELECT_I1 origin:042-clk-bufg-config 26_204 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE0 origin:042-clk-bufg-config 27_194 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_CE1 origin:042-clk-bufg-config 27_203 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S0 origin:042-clk-bufg-config 27_195 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZINV_S1 origin:042-clk-bufg-config 26_203 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y12.ZPRESELECT_I0 origin:042-clk-bufg-config 26_194 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.INIT_OUT origin:042-clk-bufg-config 27_221 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IN_USE origin:042-clk-bufg-config 27_208 27_223 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_209 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_220 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.PRESELECT_I1 origin:042-clk-bufg-config 26_220 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE0 origin:042-clk-bufg-config 27_210 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_CE1 origin:042-clk-bufg-config 27_219 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S0 origin:042-clk-bufg-config 27_211 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZINV_S1 origin:042-clk-bufg-config 26_219 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y13.ZPRESELECT_I0 origin:042-clk-bufg-config 26_210 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.INIT_OUT origin:042-clk-bufg-config 27_237 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IN_USE origin:042-clk-bufg-config 27_224 27_239 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_225 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_236 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.PRESELECT_I1 origin:042-clk-bufg-config 26_236 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE0 origin:042-clk-bufg-config 27_226 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_CE1 origin:042-clk-bufg-config 27_235 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S0 origin:042-clk-bufg-config 27_227 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZINV_S1 origin:042-clk-bufg-config 26_235 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y14.ZPRESELECT_I0 origin:042-clk-bufg-config 26_226 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.INIT_OUT origin:042-clk-bufg-config 27_253 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IN_USE origin:042-clk-bufg-config 27_240 27_255 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_241 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_252 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.PRESELECT_I1 origin:042-clk-bufg-config 26_252 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE0 origin:042-clk-bufg-config 27_242 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_CE1 origin:042-clk-bufg-config 27_251 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S0 origin:042-clk-bufg-config 27_243 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZINV_S1 origin:042-clk-bufg-config 26_251 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y15.ZPRESELECT_I0 origin:042-clk-bufg-config 26_242 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.INIT_OUT origin:042-clk-bufg-config 27_45 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IN_USE origin:042-clk-bufg-config 27_32 27_47 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_33 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_44 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.PRESELECT_I1 origin:042-clk-bufg-config 26_44 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE0 origin:042-clk-bufg-config 27_34 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_CE1 origin:042-clk-bufg-config 27_43 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S0 origin:042-clk-bufg-config 27_35 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZINV_S1 origin:042-clk-bufg-config 26_43 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y2.ZPRESELECT_I0 origin:042-clk-bufg-config 26_34 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.INIT_OUT origin:042-clk-bufg-config 27_61 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IN_USE origin:042-clk-bufg-config 27_48 27_63 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_49 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_60 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.PRESELECT_I1 origin:042-clk-bufg-config 26_60 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE0 origin:042-clk-bufg-config 27_50 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_CE1 origin:042-clk-bufg-config 27_59 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S0 origin:042-clk-bufg-config 27_51 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZINV_S1 origin:042-clk-bufg-config 26_59 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y3.ZPRESELECT_I0 origin:042-clk-bufg-config 26_50 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.INIT_OUT origin:042-clk-bufg-config 27_77 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IN_USE origin:042-clk-bufg-config 27_64 27_79 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_65 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_76 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.PRESELECT_I1 origin:042-clk-bufg-config 26_76 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE0 origin:042-clk-bufg-config 27_66 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_CE1 origin:042-clk-bufg-config 27_75 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S0 origin:042-clk-bufg-config 27_67 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZINV_S1 origin:042-clk-bufg-config 26_75 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y4.ZPRESELECT_I0 origin:042-clk-bufg-config 26_66 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.INIT_OUT origin:042-clk-bufg-config 27_93 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IN_USE origin:042-clk-bufg-config 27_80 27_95 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_81 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_92 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.PRESELECT_I1 origin:042-clk-bufg-config 26_92 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE0 origin:042-clk-bufg-config 27_82 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_CE1 origin:042-clk-bufg-config 27_91 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S0 origin:042-clk-bufg-config 27_83 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZINV_S1 origin:042-clk-bufg-config 26_91 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y5.ZPRESELECT_I0 origin:042-clk-bufg-config 26_82 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.INIT_OUT origin:042-clk-bufg-config 27_109 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IN_USE origin:042-clk-bufg-config 27_111 27_96 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_97 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_108 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.PRESELECT_I1 origin:042-clk-bufg-config 26_108 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE0 origin:042-clk-bufg-config 27_98 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_CE1 origin:042-clk-bufg-config 27_107 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S0 origin:042-clk-bufg-config 27_99 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZINV_S1 origin:042-clk-bufg-config 26_107 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y6.ZPRESELECT_I0 origin:042-clk-bufg-config 26_98 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.INIT_OUT origin:042-clk-bufg-config 27_125 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IN_USE origin:042-clk-bufg-config 27_112 27_127 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_113 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_124 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.PRESELECT_I1 origin:042-clk-bufg-config 26_124 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE0 origin:042-clk-bufg-config 27_114 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_CE1 origin:042-clk-bufg-config 27_123 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S0 origin:042-clk-bufg-config 27_115 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZINV_S1 origin:042-clk-bufg-config 26_123 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y7.ZPRESELECT_I0 origin:042-clk-bufg-config 26_114 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.INIT_OUT origin:042-clk-bufg-config 27_141 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IN_USE origin:042-clk-bufg-config 27_128 27_143 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_129 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_140 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.PRESELECT_I1 origin:042-clk-bufg-config 26_140 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE0 origin:042-clk-bufg-config 27_130 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_CE1 origin:042-clk-bufg-config 27_139 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S0 origin:042-clk-bufg-config 27_131 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZINV_S1 origin:042-clk-bufg-config 26_139 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y8.ZPRESELECT_I0 origin:042-clk-bufg-config 26_130 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.INIT_OUT origin:042-clk-bufg-config 27_157 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IN_USE origin:042-clk-bufg-config 27_144 27_159 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE0_INVERTED origin:042-clk-bufg-config 26_145 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.IS_IGNORE1_INVERTED origin:042-clk-bufg-config 27_156 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.PRESELECT_I1 origin:042-clk-bufg-config 26_156 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE0 origin:042-clk-bufg-config 27_146 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_CE1 origin:042-clk-bufg-config 27_155 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S0 origin:042-clk-bufg-config 27_147 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZINV_S1 origin:042-clk-bufg-config 26_155 +CLK_BUFG_TOP_R.BUFGCTRL.BUFGCTRL_X0Y9.ZPRESELECT_I0 origin:042-clk-bufg-config 26_146 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_07 !26_08 27_06 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_07 !26_08 !27_06 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_08 26_07 27_06 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_08 !27_06 26_07 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0 origin:044-clk-bufg-pips !26_07 !27_06 26_08 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX24_0 origin:044-clk-bufg-pips !26_04 !27_05 26_05 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0 origin:044-clk-bufg-pips !26_04 !26_05 !27_05 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_04 26_05 27_05 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_04 !26_05 27_05 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_TOP_R_CK_MUXED1 origin:044-clk-bufg-pips !26_05 !27_05 26_04 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_167 !26_168 27_166 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_167 !26_168 !27_166 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_168 26_167 27_166 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_168 !27_166 26_167 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_TOP_R_CK_MUXED20 origin:044-clk-bufg-pips !26_167 !27_166 26_168 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX26_2 origin:044-clk-bufg-pips !26_164 !27_165 26_165 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2 origin:044-clk-bufg-pips !26_164 !26_165 !27_165 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_164 26_165 27_165 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_164 !26_165 27_165 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_TOP_R_CK_MUXED21 origin:044-clk-bufg-pips !26_165 !27_165 26_164 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_183 !26_184 27_182 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_183 !26_184 !27_182 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_184 !27_182 26_183 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_184 26_183 27_182 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_TOP_R_CK_MUXED22 origin:044-clk-bufg-pips !26_183 !27_182 26_184 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX27_2 origin:044-clk-bufg-pips !26_180 !27_181 26_181 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2 origin:044-clk-bufg-pips !26_180 !26_181 !27_181 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_180 !26_181 27_181 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_180 26_181 27_181 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_TOP_R_CK_MUXED23 origin:044-clk-bufg-pips !26_181 !27_181 26_180 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_199 !26_200 27_198 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_199 !26_200 !27_198 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_200 !27_198 26_199 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_200 26_199 27_198 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_TOP_R_CK_MUXED24 origin:044-clk-bufg-pips !26_199 !27_198 26_200 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX24_3 origin:044-clk-bufg-pips !26_196 !27_197 26_197 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3 origin:044-clk-bufg-pips !26_196 !26_197 !27_197 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT11 origin:044-clk-bufg-pips !26_196 !26_197 27_197 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_196 26_197 27_197 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_TOP_R_CK_MUXED25 origin:044-clk-bufg-pips !26_197 !27_197 26_196 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_215 !26_216 27_214 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_215 !26_216 !27_214 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_216 !27_214 26_215 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_216 26_215 27_214 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_TOP_R_CK_MUXED26 origin:044-clk-bufg-pips !26_215 !27_214 26_216 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX25_3 origin:044-clk-bufg-pips !26_212 !27_213 26_213 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3 origin:044-clk-bufg-pips !26_212 !26_213 !27_213 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT12 origin:044-clk-bufg-pips !26_212 !26_213 27_213 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_212 26_213 27_213 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_TOP_R_CK_MUXED27 origin:044-clk-bufg-pips !26_213 !27_213 26_212 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_231 !26_232 27_230 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_231 !26_232 !27_230 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_232 !27_230 26_231 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_232 26_231 27_230 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_TOP_R_CK_MUXED28 origin:044-clk-bufg-pips !26_231 !27_230 26_232 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX26_3 origin:044-clk-bufg-pips !26_228 !27_229 26_229 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3 origin:044-clk-bufg-pips !26_228 !26_229 !27_229 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT13 origin:044-clk-bufg-pips !26_228 !26_229 27_229 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_R_FBG_OUT15 origin:044-clk-bufg-pips !26_228 26_229 27_229 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_TOP_R_CK_MUXED29 origin:044-clk-bufg-pips !26_229 !27_229 26_228 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_247 !26_248 27_246 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_247 !26_248 !27_246 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_248 26_247 27_246 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_248 !27_246 26_247 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_TOP_R_CK_MUXED30 origin:044-clk-bufg-pips !26_247 !27_246 26_248 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX27_3 origin:044-clk-bufg-pips !26_244 !27_245 26_245 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3 origin:044-clk-bufg-pips !26_244 !26_245 !27_245 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_244 26_245 27_245 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_R_FBG_OUT14 origin:044-clk-bufg-pips !26_244 !26_245 27_245 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_TOP_R_CK_MUXED31 origin:044-clk-bufg-pips !26_245 !27_245 26_244 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_23 !26_24 27_22 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_23 !26_24 !27_22 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_24 !27_22 26_23 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_24 26_23 27_22 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_TOP_R_CK_MUXED2 origin:044-clk-bufg-pips !26_23 !27_22 26_24 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX25_0 origin:044-clk-bufg-pips !26_20 !27_21 26_21 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0 origin:044-clk-bufg-pips !26_20 !26_21 !27_21 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT0 origin:044-clk-bufg-pips !26_20 !26_21 27_21 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_20 26_21 27_21 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_TOP_R_CK_MUXED3 origin:044-clk-bufg-pips !26_21 !27_21 26_20 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_39 !26_40 27_38 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_39 !26_40 !27_38 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_40 !27_38 26_39 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_40 26_39 27_38 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_TOP_R_CK_MUXED4 origin:044-clk-bufg-pips !26_39 !27_38 26_40 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX26_0 origin:044-clk-bufg-pips !26_36 !27_37 26_37 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0 origin:044-clk-bufg-pips !26_36 !26_37 !27_37 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT1 origin:044-clk-bufg-pips !26_36 !26_37 27_37 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_36 26_37 27_37 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_TOP_R_CK_MUXED5 origin:044-clk-bufg-pips !26_37 !27_37 26_36 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_55 !26_56 27_54 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_55 !26_56 !27_54 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_56 !27_54 26_55 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_56 26_55 27_54 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_TOP_R_CK_MUXED6 origin:044-clk-bufg-pips !26_55 !27_54 26_56 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX27_0 origin:044-clk-bufg-pips !26_52 !27_53 26_53 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0 origin:044-clk-bufg-pips !26_52 !26_53 !27_53 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT2 origin:044-clk-bufg-pips !26_52 !26_53 27_53 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_52 26_53 27_53 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_TOP_R_CK_MUXED7 origin:044-clk-bufg-pips !26_53 !27_53 26_52 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_71 !26_72 27_70 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_71 !26_72 !27_70 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_72 !27_70 26_71 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_72 26_71 27_70 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_TOP_R_CK_MUXED8 origin:044-clk-bufg-pips !26_71 !27_70 26_72 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX24_1 origin:044-clk-bufg-pips !26_68 !27_69 26_69 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1 origin:044-clk-bufg-pips !26_68 !26_69 !27_69 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT3 origin:044-clk-bufg-pips !26_68 !26_69 27_69 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_68 26_69 27_69 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_TOP_R_CK_MUXED9 origin:044-clk-bufg-pips !26_69 !27_69 26_68 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_87 !26_88 27_86 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_87 !26_88 !27_86 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_88 !27_86 26_87 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_88 26_87 27_86 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_TOP_R_CK_MUXED10 origin:044-clk-bufg-pips !26_87 !27_86 26_88 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX25_1 origin:044-clk-bufg-pips !26_84 !27_85 26_85 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1 origin:044-clk-bufg-pips !26_84 !26_85 !27_85 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT4 origin:044-clk-bufg-pips !26_84 !26_85 27_85 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_84 26_85 27_85 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_TOP_R_CK_MUXED11 origin:044-clk-bufg-pips !26_85 !27_85 26_84 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_103 !26_104 27_102 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_103 !26_104 !27_102 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_104 !27_102 26_103 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_104 26_103 27_102 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_TOP_R_CK_MUXED12 origin:044-clk-bufg-pips !26_103 !27_102 26_104 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX26_1 origin:044-clk-bufg-pips !26_100 !27_101 26_101 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1 origin:044-clk-bufg-pips !26_100 !26_101 !27_101 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT5 origin:044-clk-bufg-pips !26_100 !26_101 27_101 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_100 26_101 27_101 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_TOP_R_CK_MUXED13 origin:044-clk-bufg-pips !26_101 !27_101 26_100 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_119 !26_120 27_118 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_119 !26_120 !27_118 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_120 !27_118 26_119 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_120 26_119 27_118 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_TOP_R_CK_MUXED14 origin:044-clk-bufg-pips !26_119 !27_118 26_120 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX27_1 origin:044-clk-bufg-pips !26_116 !27_117 26_117 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1 origin:044-clk-bufg-pips !26_116 !26_117 !27_117 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT6 origin:044-clk-bufg-pips !26_116 !26_117 27_117 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_116 26_117 27_117 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_TOP_R_CK_MUXED15 origin:044-clk-bufg-pips !26_117 !27_117 26_116 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_135 !26_136 27_134 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_135 !26_136 !27_134 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_136 !27_134 26_135 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_136 26_135 27_134 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_TOP_R_CK_MUXED16 origin:044-clk-bufg-pips !26_135 !27_134 26_136 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX24_2 origin:044-clk-bufg-pips !26_132 !27_133 26_133 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2 origin:044-clk-bufg-pips !26_132 !26_133 !27_133 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT7 origin:044-clk-bufg-pips !26_132 !26_133 27_133 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_R_FBG_OUT9 origin:044-clk-bufg-pips !26_132 26_133 27_133 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_TOP_R_CK_MUXED17 origin:044-clk-bufg-pips !26_133 !27_133 26_132 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_151 !26_152 27_150 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_151 !26_152 !27_150 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_152 26_151 27_150 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_152 !27_150 26_151 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_TOP_R_CK_MUXED18 origin:044-clk-bufg-pips !26_151 !27_150 26_152 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX25_2 origin:044-clk-bufg-pips !26_148 !27_149 26_149 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2 origin:044-clk-bufg-pips !26_148 !26_149 !27_149 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT10 origin:044-clk-bufg-pips !26_148 26_149 27_149 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_R_FBG_OUT8 origin:044-clk-bufg-pips !26_148 !26_149 27_149 +CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_TOP_R_CK_MUXED19 origin:044-clk-bufg-pips !26_149 !27_149 26_148 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK16.CLK_BUFG_BUFGCTRL0_O origin:044-clk-bufg-pips 27_14 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK17.CLK_BUFG_BUFGCTRL1_O origin:044-clk-bufg-pips 27_30 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK18.CLK_BUFG_BUFGCTRL2_O origin:044-clk-bufg-pips 27_46 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK19.CLK_BUFG_BUFGCTRL3_O origin:044-clk-bufg-pips 27_62 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK20.CLK_BUFG_BUFGCTRL4_O origin:044-clk-bufg-pips 27_78 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK21.CLK_BUFG_BUFGCTRL5_O origin:044-clk-bufg-pips 27_94 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK22.CLK_BUFG_BUFGCTRL6_O origin:044-clk-bufg-pips 27_110 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK23.CLK_BUFG_BUFGCTRL7_O origin:044-clk-bufg-pips 27_126 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK24.CLK_BUFG_BUFGCTRL8_O origin:044-clk-bufg-pips 27_142 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK25.CLK_BUFG_BUFGCTRL9_O origin:044-clk-bufg-pips 27_158 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK26.CLK_BUFG_BUFGCTRL10_O origin:044-clk-bufg-pips 27_174 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK27.CLK_BUFG_BUFGCTRL11_O origin:044-clk-bufg-pips 27_190 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK28.CLK_BUFG_BUFGCTRL12_O origin:044-clk-bufg-pips 27_206 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK29.CLK_BUFG_BUFGCTRL13_O origin:044-clk-bufg-pips 27_222 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK30.CLK_BUFG_BUFGCTRL14_O origin:044-clk-bufg-pips 27_238 +CLK_BUFG_TOP_R.CLK_BUFG_CK_GCLK31.CLK_BUFG_BUFGCTRL15_O origin:044-clk-bufg-pips 27_254 diff --git a/zynq7/segbits_clk_hrow_bot_r.origin_info.db b/zynq7/segbits_clk_hrow_bot_r.origin_info.db new file mode 100644 index 0000000..d4996ee --- /dev/null +++ b/zynq7/segbits_clk_hrow_bot_r.origin_info.db @@ -0,0 +1,96 @@ +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y0.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_214 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y0.INIT_OUT origin:040-clk-hrow-config 26_211 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y0.IN_USE origin:040-clk-hrow-config 27_215 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y0.ZINV_CE origin:040-clk-hrow-config 27_211 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y1.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_214 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y1.INIT_OUT origin:040-clk-hrow-config 28_211 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y1.IN_USE origin:040-clk-hrow-config 29_215 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y1.ZINV_CE origin:040-clk-hrow-config 29_211 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y10.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_326 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y10.INIT_OUT origin:040-clk-hrow-config 26_323 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y10.IN_USE origin:040-clk-hrow-config 27_327 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y10.ZINV_CE origin:040-clk-hrow-config 27_323 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y11.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_326 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y11.INIT_OUT origin:040-clk-hrow-config 28_323 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y11.IN_USE origin:040-clk-hrow-config 29_327 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y11.ZINV_CE origin:040-clk-hrow-config 29_323 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y2.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_230 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y2.INIT_OUT origin:040-clk-hrow-config 26_227 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y2.IN_USE origin:040-clk-hrow-config 27_231 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y2.ZINV_CE origin:040-clk-hrow-config 27_227 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y3.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_230 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y3.INIT_OUT origin:040-clk-hrow-config 28_227 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y3.IN_USE origin:040-clk-hrow-config 29_231 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y3.ZINV_CE origin:040-clk-hrow-config 29_227 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y4.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_246 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y4.INIT_OUT origin:040-clk-hrow-config 26_243 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y4.IN_USE origin:040-clk-hrow-config 27_247 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y4.ZINV_CE origin:040-clk-hrow-config 27_243 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y5.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_246 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y5.INIT_OUT origin:040-clk-hrow-config 28_243 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y5.IN_USE origin:040-clk-hrow-config 29_247 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y5.ZINV_CE origin:040-clk-hrow-config 27_359 29_243 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y6.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_294 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y6.INIT_OUT origin:040-clk-hrow-config 26_291 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y6.IN_USE origin:040-clk-hrow-config 27_295 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y6.ZINV_CE origin:040-clk-hrow-config 27_291 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y7.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_294 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y7.INIT_OUT origin:040-clk-hrow-config 28_291 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y7.IN_USE origin:040-clk-hrow-config 29_295 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y7.ZINV_CE origin:040-clk-hrow-config 29_291 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y8.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_310 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y8.INIT_OUT origin:040-clk-hrow-config 26_307 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y8.IN_USE origin:040-clk-hrow-config 27_311 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y8.ZINV_CE origin:040-clk-hrow-config 27_307 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y9.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_310 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y9.INIT_OUT origin:040-clk-hrow-config 28_307 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y9.IN_USE origin:040-clk-hrow-config 29_311 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X0Y9.ZINV_CE origin:040-clk-hrow-config 29_307 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y0.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_166 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y0.INIT_OUT origin:040-clk-hrow-config 26_163 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y0.IN_USE origin:040-clk-hrow-config 27_167 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y0.ZINV_CE origin:040-clk-hrow-config 27_163 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y1.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_166 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y1.INIT_OUT origin:040-clk-hrow-config 28_163 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y1.IN_USE origin:040-clk-hrow-config 29_167 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y1.ZINV_CE origin:040-clk-hrow-config 29_163 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y10.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_374 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y10.INIT_OUT origin:040-clk-hrow-config 26_371 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y10.IN_USE origin:040-clk-hrow-config 27_375 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y10.ZINV_CE origin:040-clk-hrow-config 27_371 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y11.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_374 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y11.INIT_OUT origin:040-clk-hrow-config 28_371 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y11.IN_USE origin:040-clk-hrow-config 29_375 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y11.ZINV_CE origin:040-clk-hrow-config 29_371 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y2.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_182 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y2.INIT_OUT origin:040-clk-hrow-config 26_179 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y2.IN_USE origin:040-clk-hrow-config 27_183 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y2.ZINV_CE origin:040-clk-hrow-config 27_179 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y3.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_182 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y3.INIT_OUT origin:040-clk-hrow-config 28_179 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y3.IN_USE origin:040-clk-hrow-config 29_183 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y3.ZINV_CE origin:040-clk-hrow-config 29_179 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y4.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_198 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y4.INIT_OUT origin:040-clk-hrow-config 26_195 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y4.IN_USE origin:040-clk-hrow-config 27_199 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y4.ZINV_CE origin:040-clk-hrow-config 27_195 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y5.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_198 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y5.INIT_OUT origin:040-clk-hrow-config 28_195 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y5.IN_USE origin:040-clk-hrow-config 29_199 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y5.ZINV_CE origin:040-clk-hrow-config 29_195 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y6.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_342 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y6.INIT_OUT origin:040-clk-hrow-config 26_339 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y6.IN_USE origin:040-clk-hrow-config 27_343 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y6.ZINV_CE origin:040-clk-hrow-config 27_339 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y7.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_342 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y7.INIT_OUT origin:040-clk-hrow-config 28_339 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y7.IN_USE origin:040-clk-hrow-config 29_343 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y7.ZINV_CE origin:040-clk-hrow-config 29_339 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y8.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_358 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y8.INIT_OUT origin:040-clk-hrow-config 26_355 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y8.IN_USE origin:040-clk-hrow-config 27_359 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y8.ZINV_CE origin:040-clk-hrow-config 27_355 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y9.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_358 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y9.INIT_OUT origin:040-clk-hrow-config 28_355 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y9.IN_USE origin:040-clk-hrow-config 29_359 +CLK_HROW_BOT_R.BUFHCE.BUFHCE_X1Y9.ZINV_CE origin:040-clk-hrow-config 29_355 diff --git a/zynq7/segbits_clk_hrow_top_r.origin_info.db b/zynq7/segbits_clk_hrow_top_r.origin_info.db new file mode 100644 index 0000000..0aaa4a7 --- /dev/null +++ b/zynq7/segbits_clk_hrow_top_r.origin_info.db @@ -0,0 +1,96 @@ +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y0.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_214 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y0.INIT_OUT origin:040-clk-hrow-config 26_211 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y0.IN_USE origin:040-clk-hrow-config 27_215 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y0.ZINV_CE origin:040-clk-hrow-config 27_211 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y1.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_214 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y1.INIT_OUT origin:040-clk-hrow-config 28_211 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y1.IN_USE origin:040-clk-hrow-config 29_215 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y1.ZINV_CE origin:040-clk-hrow-config 29_211 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y10.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_326 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y10.INIT_OUT origin:040-clk-hrow-config 26_323 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y10.IN_USE origin:040-clk-hrow-config 27_327 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y10.ZINV_CE origin:040-clk-hrow-config 27_323 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y11.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_326 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y11.INIT_OUT origin:040-clk-hrow-config 28_323 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y11.IN_USE origin:040-clk-hrow-config 29_327 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y11.ZINV_CE origin:040-clk-hrow-config 29_323 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y2.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_230 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y2.INIT_OUT origin:040-clk-hrow-config 26_227 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y2.IN_USE origin:040-clk-hrow-config 27_231 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y2.ZINV_CE origin:040-clk-hrow-config 27_227 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y3.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_230 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y3.INIT_OUT origin:040-clk-hrow-config 28_227 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y3.IN_USE origin:040-clk-hrow-config 29_231 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y3.ZINV_CE origin:040-clk-hrow-config 29_227 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y4.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_246 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y4.INIT_OUT origin:040-clk-hrow-config 26_243 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y4.IN_USE origin:040-clk-hrow-config 27_247 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y4.ZINV_CE origin:040-clk-hrow-config 27_243 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y5.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_246 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y5.INIT_OUT origin:040-clk-hrow-config 28_243 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y5.IN_USE origin:040-clk-hrow-config 29_247 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y5.ZINV_CE origin:040-clk-hrow-config 27_359 29_243 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y6.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_294 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y6.INIT_OUT origin:040-clk-hrow-config 26_291 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y6.IN_USE origin:040-clk-hrow-config 27_295 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y6.ZINV_CE origin:040-clk-hrow-config 27_291 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y7.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_294 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y7.INIT_OUT origin:040-clk-hrow-config 28_291 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y7.IN_USE origin:040-clk-hrow-config 29_295 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y7.ZINV_CE origin:040-clk-hrow-config 29_291 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y8.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_310 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y8.INIT_OUT origin:040-clk-hrow-config 26_307 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y8.IN_USE origin:040-clk-hrow-config 27_311 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y8.ZINV_CE origin:040-clk-hrow-config 27_307 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y9.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_310 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y9.INIT_OUT origin:040-clk-hrow-config 28_307 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y9.IN_USE origin:040-clk-hrow-config 29_311 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X0Y9.ZINV_CE origin:040-clk-hrow-config 29_307 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y0.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_166 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y0.INIT_OUT origin:040-clk-hrow-config 26_163 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y0.IN_USE origin:040-clk-hrow-config 27_167 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y0.ZINV_CE origin:040-clk-hrow-config 27_163 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y1.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_166 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y1.INIT_OUT origin:040-clk-hrow-config 28_163 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y1.IN_USE origin:040-clk-hrow-config 29_167 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y1.ZINV_CE origin:040-clk-hrow-config 29_163 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y10.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_374 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y10.INIT_OUT origin:040-clk-hrow-config 26_371 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y10.IN_USE origin:040-clk-hrow-config 27_375 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y10.ZINV_CE origin:040-clk-hrow-config 27_371 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y11.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_374 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y11.INIT_OUT origin:040-clk-hrow-config 28_371 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y11.IN_USE origin:040-clk-hrow-config 29_375 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y11.ZINV_CE origin:040-clk-hrow-config 29_371 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y2.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_182 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y2.INIT_OUT origin:040-clk-hrow-config 26_179 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y2.IN_USE origin:040-clk-hrow-config 27_183 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y2.ZINV_CE origin:040-clk-hrow-config 27_179 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y3.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_182 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y3.INIT_OUT origin:040-clk-hrow-config 28_179 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y3.IN_USE origin:040-clk-hrow-config 29_183 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y3.ZINV_CE origin:040-clk-hrow-config 29_179 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y4.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_198 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y4.INIT_OUT origin:040-clk-hrow-config 26_195 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y4.IN_USE origin:040-clk-hrow-config 27_199 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y4.ZINV_CE origin:040-clk-hrow-config 27_195 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y5.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_198 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y5.INIT_OUT origin:040-clk-hrow-config 28_195 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y5.IN_USE origin:040-clk-hrow-config 29_199 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y5.ZINV_CE origin:040-clk-hrow-config 29_195 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y6.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_342 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y6.INIT_OUT origin:040-clk-hrow-config 26_339 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y6.IN_USE origin:040-clk-hrow-config 27_343 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y6.ZINV_CE origin:040-clk-hrow-config 27_339 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y7.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_342 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y7.INIT_OUT origin:040-clk-hrow-config 28_339 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y7.IN_USE origin:040-clk-hrow-config 29_343 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y7.ZINV_CE origin:040-clk-hrow-config 29_339 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y8.CE_TYPE.ASYNC origin:040-clk-hrow-config 27_358 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y8.INIT_OUT origin:040-clk-hrow-config 26_355 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y8.IN_USE origin:040-clk-hrow-config 27_359 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y8.ZINV_CE origin:040-clk-hrow-config 27_355 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y9.CE_TYPE.ASYNC origin:040-clk-hrow-config 29_358 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y9.INIT_OUT origin:040-clk-hrow-config 28_355 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y9.IN_USE origin:040-clk-hrow-config 29_359 +CLK_HROW_TOP_R.BUFHCE.BUFHCE_X1Y9.ZINV_CE origin:040-clk-hrow-config 29_355 diff --git a/zynq7/segbits_dsp_l.origin_info.db b/zynq7/segbits_dsp_l.origin_info.db new file mode 100644 index 0000000..b96d449 --- /dev/null +++ b/zynq7/segbits_dsp_l.origin_info.db @@ -0,0 +1,192 @@ +DSP_L.DSP48.DSP_0.MASK[0] origin:100-dsp-mskpat 27_01 +DSP_L.DSP48.DSP_0.MASK[10] origin:100-dsp-mskpat 27_26 +DSP_L.DSP48.DSP_0.MASK[11] origin:100-dsp-mskpat 26_28 +DSP_L.DSP48.DSP_0.MASK[12] origin:100-dsp-mskpat 26_41 +DSP_L.DSP48.DSP_0.MASK[13] origin:100-dsp-mskpat 27_42 +DSP_L.DSP48.DSP_0.MASK[14] origin:100-dsp-mskpat 26_45 +DSP_L.DSP48.DSP_0.MASK[15] origin:100-dsp-mskpat 27_46 +DSP_L.DSP48.DSP_0.MASK[16] origin:100-dsp-mskpat 26_49 +DSP_L.DSP48.DSP_0.MASK[17] origin:100-dsp-mskpat 27_50 +DSP_L.DSP48.DSP_0.MASK[18] origin:100-dsp-mskpat 27_57 +DSP_L.DSP48.DSP_0.MASK[19] origin:100-dsp-mskpat 26_59 +DSP_L.DSP48.DSP_0.MASK[1] origin:100-dsp-mskpat 26_03 +DSP_L.DSP48.DSP_0.MASK[20] origin:100-dsp-mskpat 26_62 +DSP_L.DSP48.DSP_0.MASK[21] origin:100-dsp-mskpat 27_63 +DSP_L.DSP48.DSP_0.MASK[22] origin:100-dsp-mskpat 26_66 +DSP_L.DSP48.DSP_0.MASK[23] origin:100-dsp-mskpat 27_67 +DSP_L.DSP48.DSP_0.MASK[24] origin:100-dsp-mskpat 27_86 +DSP_L.DSP48.DSP_0.MASK[25] origin:100-dsp-mskpat 26_88 +DSP_L.DSP48.DSP_0.MASK[26] origin:100-dsp-mskpat 27_90 +DSP_L.DSP48.DSP_0.MASK[27] origin:100-dsp-mskpat 26_92 +DSP_L.DSP48.DSP_0.MASK[28] origin:100-dsp-mskpat 27_94 +DSP_L.DSP48.DSP_0.MASK[29] origin:100-dsp-mskpat 26_96 +DSP_L.DSP48.DSP_0.MASK[2] origin:100-dsp-mskpat 27_06 +DSP_L.DSP48.DSP_0.MASK[30] origin:100-dsp-mskpat 27_102 +DSP_L.DSP48.DSP_0.MASK[31] origin:100-dsp-mskpat 26_104 +DSP_L.DSP48.DSP_0.MASK[32] origin:100-dsp-mskpat 27_106 +DSP_L.DSP48.DSP_0.MASK[33] origin:100-dsp-mskpat 26_108 +DSP_L.DSP48.DSP_0.MASK[34] origin:100-dsp-mskpat 27_110 +DSP_L.DSP48.DSP_0.MASK[35] origin:100-dsp-mskpat 26_112 +DSP_L.DSP48.DSP_0.MASK[36] origin:100-dsp-mskpat 27_127 +DSP_L.DSP48.DSP_0.MASK[37] origin:100-dsp-mskpat 26_129 +DSP_L.DSP48.DSP_0.MASK[38] origin:100-dsp-mskpat 26_132 +DSP_L.DSP48.DSP_0.MASK[39] origin:100-dsp-mskpat 27_133 +DSP_L.DSP48.DSP_0.MASK[3] origin:100-dsp-mskpat 26_07 +DSP_L.DSP48.DSP_0.MASK[40] origin:100-dsp-mskpat 26_136 +DSP_L.DSP48.DSP_0.MASK[41] origin:100-dsp-mskpat 27_137 +DSP_L.DSP48.DSP_0.MASK[42] origin:100-dsp-mskpat 27_144 +DSP_L.DSP48.DSP_0.MASK[43] origin:100-dsp-mskpat 26_146 +DSP_L.DSP48.DSP_0.MASK[44] origin:100-dsp-mskpat 26_149 +DSP_L.DSP48.DSP_0.MASK[45] origin:100-dsp-mskpat 27_150 +DSP_L.DSP48.DSP_0.MASK[46] origin:100-dsp-mskpat 26_153 +DSP_L.DSP48.DSP_0.MASK[47] origin:100-dsp-mskpat 26_154 +DSP_L.DSP48.DSP_0.MASK[4] origin:100-dsp-mskpat 26_10 +DSP_L.DSP48.DSP_0.MASK[5] origin:100-dsp-mskpat 27_11 +DSP_L.DSP48.DSP_0.MASK[6] origin:100-dsp-mskpat 26_18 +DSP_L.DSP48.DSP_0.MASK[7] origin:100-dsp-mskpat 27_19 +DSP_L.DSP48.DSP_0.MASK[8] origin:100-dsp-mskpat 26_22 +DSP_L.DSP48.DSP_0.MASK[9] origin:100-dsp-mskpat 27_23 +DSP_L.DSP48.DSP_0.PATTERN[0] origin:100-dsp-mskpat 26_01 +DSP_L.DSP48.DSP_0.PATTERN[10] origin:100-dsp-mskpat 26_26 +DSP_L.DSP48.DSP_0.PATTERN[11] origin:100-dsp-mskpat 26_29 +DSP_L.DSP48.DSP_0.PATTERN[12] origin:100-dsp-mskpat 27_40 +DSP_L.DSP48.DSP_0.PATTERN[13] origin:100-dsp-mskpat 26_43 +DSP_L.DSP48.DSP_0.PATTERN[14] origin:100-dsp-mskpat 27_44 +DSP_L.DSP48.DSP_0.PATTERN[15] origin:100-dsp-mskpat 26_47 +DSP_L.DSP48.DSP_0.PATTERN[16] origin:100-dsp-mskpat 27_48 +DSP_L.DSP48.DSP_0.PATTERN[17] origin:100-dsp-mskpat 26_51 +DSP_L.DSP48.DSP_0.PATTERN[18] origin:100-dsp-mskpat 26_57 +DSP_L.DSP48.DSP_0.PATTERN[19] origin:100-dsp-mskpat 26_60 +DSP_L.DSP48.DSP_0.PATTERN[1] origin:100-dsp-mskpat 26_04 +DSP_L.DSP48.DSP_0.PATTERN[20] origin:100-dsp-mskpat 27_61 +DSP_L.DSP48.DSP_0.PATTERN[21] origin:100-dsp-mskpat 26_64 +DSP_L.DSP48.DSP_0.PATTERN[22] origin:100-dsp-mskpat 27_65 +DSP_L.DSP48.DSP_0.PATTERN[23] origin:100-dsp-mskpat 26_68 +DSP_L.DSP48.DSP_0.PATTERN[24] origin:100-dsp-mskpat 26_86 +DSP_L.DSP48.DSP_0.PATTERN[25] origin:100-dsp-mskpat 27_88 +DSP_L.DSP48.DSP_0.PATTERN[26] origin:100-dsp-mskpat 26_90 +DSP_L.DSP48.DSP_0.PATTERN[27] origin:100-dsp-mskpat 27_92 +DSP_L.DSP48.DSP_0.PATTERN[28] origin:100-dsp-mskpat 26_94 +DSP_L.DSP48.DSP_0.PATTERN[29] origin:100-dsp-mskpat 26_97 +DSP_L.DSP48.DSP_0.PATTERN[2] origin:100-dsp-mskpat 26_05 +DSP_L.DSP48.DSP_0.PATTERN[30] origin:100-dsp-mskpat 27_101 +DSP_L.DSP48.DSP_0.PATTERN[31] origin:100-dsp-mskpat 27_104 +DSP_L.DSP48.DSP_0.PATTERN[32] origin:100-dsp-mskpat 26_106 +DSP_L.DSP48.DSP_0.PATTERN[33] origin:100-dsp-mskpat 27_108 +DSP_L.DSP48.DSP_0.PATTERN[34] origin:100-dsp-mskpat 26_110 +DSP_L.DSP48.DSP_0.PATTERN[35] origin:100-dsp-mskpat 27_112 +DSP_L.DSP48.DSP_0.PATTERN[36] origin:100-dsp-mskpat 26_127 +DSP_L.DSP48.DSP_0.PATTERN[37] origin:100-dsp-mskpat 26_130 +DSP_L.DSP48.DSP_0.PATTERN[38] origin:100-dsp-mskpat 27_131 +DSP_L.DSP48.DSP_0.PATTERN[39] origin:100-dsp-mskpat 26_134 +DSP_L.DSP48.DSP_0.PATTERN[3] origin:100-dsp-mskpat 27_08 +DSP_L.DSP48.DSP_0.PATTERN[40] origin:100-dsp-mskpat 27_135 +DSP_L.DSP48.DSP_0.PATTERN[41] origin:100-dsp-mskpat 26_138 +DSP_L.DSP48.DSP_0.PATTERN[42] origin:100-dsp-mskpat 26_144 +DSP_L.DSP48.DSP_0.PATTERN[43] origin:100-dsp-mskpat 27_146 +DSP_L.DSP48.DSP_0.PATTERN[44] origin:100-dsp-mskpat 26_148 +DSP_L.DSP48.DSP_0.PATTERN[45] origin:100-dsp-mskpat 26_151 +DSP_L.DSP48.DSP_0.PATTERN[46] origin:100-dsp-mskpat 27_152 +DSP_L.DSP48.DSP_0.PATTERN[47] origin:100-dsp-mskpat 26_155 +DSP_L.DSP48.DSP_0.PATTERN[4] origin:100-dsp-mskpat 26_09 +DSP_L.DSP48.DSP_0.PATTERN[5] origin:100-dsp-mskpat 26_12 +DSP_L.DSP48.DSP_0.PATTERN[6] origin:100-dsp-mskpat 27_17 +DSP_L.DSP48.DSP_0.PATTERN[7] origin:100-dsp-mskpat 26_20 +DSP_L.DSP48.DSP_0.PATTERN[8] origin:100-dsp-mskpat 27_21 +DSP_L.DSP48.DSP_0.PATTERN[9] origin:100-dsp-mskpat 27_24 +DSP_L.DSP48.DSP_1.MASK[0] origin:100-dsp-mskpat 27_161 +DSP_L.DSP48.DSP_1.MASK[10] origin:100-dsp-mskpat 27_186 +DSP_L.DSP48.DSP_1.MASK[11] origin:100-dsp-mskpat 26_188 +DSP_L.DSP48.DSP_1.MASK[12] origin:100-dsp-mskpat 26_201 +DSP_L.DSP48.DSP_1.MASK[13] origin:100-dsp-mskpat 27_202 +DSP_L.DSP48.DSP_1.MASK[14] origin:100-dsp-mskpat 26_205 +DSP_L.DSP48.DSP_1.MASK[15] origin:100-dsp-mskpat 27_206 +DSP_L.DSP48.DSP_1.MASK[16] origin:100-dsp-mskpat 26_209 +DSP_L.DSP48.DSP_1.MASK[17] origin:100-dsp-mskpat 27_210 +DSP_L.DSP48.DSP_1.MASK[18] origin:100-dsp-mskpat 27_217 +DSP_L.DSP48.DSP_1.MASK[19] origin:100-dsp-mskpat 26_219 +DSP_L.DSP48.DSP_1.MASK[1] origin:100-dsp-mskpat 26_163 +DSP_L.DSP48.DSP_1.MASK[20] origin:100-dsp-mskpat 26_222 +DSP_L.DSP48.DSP_1.MASK[21] origin:100-dsp-mskpat 27_223 +DSP_L.DSP48.DSP_1.MASK[22] origin:100-dsp-mskpat 26_226 +DSP_L.DSP48.DSP_1.MASK[23] origin:100-dsp-mskpat 27_227 +DSP_L.DSP48.DSP_1.MASK[24] origin:100-dsp-mskpat 27_246 +DSP_L.DSP48.DSP_1.MASK[25] origin:100-dsp-mskpat 26_248 +DSP_L.DSP48.DSP_1.MASK[26] origin:100-dsp-mskpat 27_250 +DSP_L.DSP48.DSP_1.MASK[27] origin:100-dsp-mskpat 26_252 +DSP_L.DSP48.DSP_1.MASK[28] origin:100-dsp-mskpat 27_254 +DSP_L.DSP48.DSP_1.MASK[29] origin:100-dsp-mskpat 26_256 +DSP_L.DSP48.DSP_1.MASK[2] origin:100-dsp-mskpat 27_166 +DSP_L.DSP48.DSP_1.MASK[30] origin:100-dsp-mskpat 27_262 +DSP_L.DSP48.DSP_1.MASK[31] origin:100-dsp-mskpat 26_264 +DSP_L.DSP48.DSP_1.MASK[32] origin:100-dsp-mskpat 27_266 +DSP_L.DSP48.DSP_1.MASK[33] origin:100-dsp-mskpat 26_268 +DSP_L.DSP48.DSP_1.MASK[34] origin:100-dsp-mskpat 27_270 +DSP_L.DSP48.DSP_1.MASK[35] origin:100-dsp-mskpat 26_272 +DSP_L.DSP48.DSP_1.MASK[36] origin:100-dsp-mskpat 27_287 +DSP_L.DSP48.DSP_1.MASK[37] origin:100-dsp-mskpat 26_289 +DSP_L.DSP48.DSP_1.MASK[38] origin:100-dsp-mskpat 26_292 +DSP_L.DSP48.DSP_1.MASK[39] origin:100-dsp-mskpat 27_293 +DSP_L.DSP48.DSP_1.MASK[3] origin:100-dsp-mskpat 26_167 +DSP_L.DSP48.DSP_1.MASK[40] origin:100-dsp-mskpat 26_296 +DSP_L.DSP48.DSP_1.MASK[41] origin:100-dsp-mskpat 27_297 +DSP_L.DSP48.DSP_1.MASK[42] origin:100-dsp-mskpat 27_304 +DSP_L.DSP48.DSP_1.MASK[43] origin:100-dsp-mskpat 26_306 +DSP_L.DSP48.DSP_1.MASK[44] origin:100-dsp-mskpat 26_309 +DSP_L.DSP48.DSP_1.MASK[45] origin:100-dsp-mskpat 27_310 +DSP_L.DSP48.DSP_1.MASK[46] origin:100-dsp-mskpat 26_313 +DSP_L.DSP48.DSP_1.MASK[47] origin:100-dsp-mskpat 26_314 +DSP_L.DSP48.DSP_1.MASK[4] origin:100-dsp-mskpat 26_170 +DSP_L.DSP48.DSP_1.MASK[5] origin:100-dsp-mskpat 27_171 +DSP_L.DSP48.DSP_1.MASK[6] origin:100-dsp-mskpat 26_178 +DSP_L.DSP48.DSP_1.MASK[7] origin:100-dsp-mskpat 27_179 +DSP_L.DSP48.DSP_1.MASK[8] origin:100-dsp-mskpat 26_182 +DSP_L.DSP48.DSP_1.MASK[9] origin:100-dsp-mskpat 27_183 +DSP_L.DSP48.DSP_1.PATTERN[0] origin:100-dsp-mskpat 26_161 +DSP_L.DSP48.DSP_1.PATTERN[10] origin:100-dsp-mskpat 26_186 +DSP_L.DSP48.DSP_1.PATTERN[11] origin:100-dsp-mskpat 26_189 +DSP_L.DSP48.DSP_1.PATTERN[12] origin:100-dsp-mskpat 27_200 +DSP_L.DSP48.DSP_1.PATTERN[13] origin:100-dsp-mskpat 26_203 +DSP_L.DSP48.DSP_1.PATTERN[14] origin:100-dsp-mskpat 27_204 +DSP_L.DSP48.DSP_1.PATTERN[15] origin:100-dsp-mskpat 26_207 +DSP_L.DSP48.DSP_1.PATTERN[16] origin:100-dsp-mskpat 27_208 +DSP_L.DSP48.DSP_1.PATTERN[17] origin:100-dsp-mskpat 26_211 +DSP_L.DSP48.DSP_1.PATTERN[18] origin:100-dsp-mskpat 26_217 +DSP_L.DSP48.DSP_1.PATTERN[19] origin:100-dsp-mskpat 26_220 +DSP_L.DSP48.DSP_1.PATTERN[1] origin:100-dsp-mskpat 26_164 +DSP_L.DSP48.DSP_1.PATTERN[20] origin:100-dsp-mskpat 27_221 +DSP_L.DSP48.DSP_1.PATTERN[21] origin:100-dsp-mskpat 26_224 +DSP_L.DSP48.DSP_1.PATTERN[22] origin:100-dsp-mskpat 27_225 +DSP_L.DSP48.DSP_1.PATTERN[23] origin:100-dsp-mskpat 26_228 +DSP_L.DSP48.DSP_1.PATTERN[24] origin:100-dsp-mskpat 26_246 +DSP_L.DSP48.DSP_1.PATTERN[25] origin:100-dsp-mskpat 27_248 +DSP_L.DSP48.DSP_1.PATTERN[26] origin:100-dsp-mskpat 26_250 +DSP_L.DSP48.DSP_1.PATTERN[27] origin:100-dsp-mskpat 27_252 +DSP_L.DSP48.DSP_1.PATTERN[28] origin:100-dsp-mskpat 26_254 +DSP_L.DSP48.DSP_1.PATTERN[29] origin:100-dsp-mskpat 26_257 +DSP_L.DSP48.DSP_1.PATTERN[2] origin:100-dsp-mskpat 26_165 +DSP_L.DSP48.DSP_1.PATTERN[30] origin:100-dsp-mskpat 27_261 +DSP_L.DSP48.DSP_1.PATTERN[31] origin:100-dsp-mskpat 27_264 +DSP_L.DSP48.DSP_1.PATTERN[32] origin:100-dsp-mskpat 26_266 +DSP_L.DSP48.DSP_1.PATTERN[33] origin:100-dsp-mskpat 27_268 +DSP_L.DSP48.DSP_1.PATTERN[34] origin:100-dsp-mskpat 26_270 +DSP_L.DSP48.DSP_1.PATTERN[35] origin:100-dsp-mskpat 27_272 +DSP_L.DSP48.DSP_1.PATTERN[36] origin:100-dsp-mskpat 26_287 +DSP_L.DSP48.DSP_1.PATTERN[37] origin:100-dsp-mskpat 26_290 +DSP_L.DSP48.DSP_1.PATTERN[38] origin:100-dsp-mskpat 27_291 +DSP_L.DSP48.DSP_1.PATTERN[39] origin:100-dsp-mskpat 26_294 +DSP_L.DSP48.DSP_1.PATTERN[3] origin:100-dsp-mskpat 27_168 +DSP_L.DSP48.DSP_1.PATTERN[40] origin:100-dsp-mskpat 27_295 +DSP_L.DSP48.DSP_1.PATTERN[41] origin:100-dsp-mskpat 26_298 +DSP_L.DSP48.DSP_1.PATTERN[42] origin:100-dsp-mskpat 26_304 +DSP_L.DSP48.DSP_1.PATTERN[43] origin:100-dsp-mskpat 27_306 +DSP_L.DSP48.DSP_1.PATTERN[44] origin:100-dsp-mskpat 26_308 +DSP_L.DSP48.DSP_1.PATTERN[45] origin:100-dsp-mskpat 26_311 +DSP_L.DSP48.DSP_1.PATTERN[46] origin:100-dsp-mskpat 27_312 +DSP_L.DSP48.DSP_1.PATTERN[47] origin:100-dsp-mskpat 26_315 +DSP_L.DSP48.DSP_1.PATTERN[4] origin:100-dsp-mskpat 26_169 +DSP_L.DSP48.DSP_1.PATTERN[5] origin:100-dsp-mskpat 26_172 +DSP_L.DSP48.DSP_1.PATTERN[6] origin:100-dsp-mskpat 27_177 +DSP_L.DSP48.DSP_1.PATTERN[7] origin:100-dsp-mskpat 26_180 +DSP_L.DSP48.DSP_1.PATTERN[8] origin:100-dsp-mskpat 27_181 +DSP_L.DSP48.DSP_1.PATTERN[9] origin:100-dsp-mskpat 27_184 diff --git a/zynq7/segbits_dsp_r.origin_info.db b/zynq7/segbits_dsp_r.origin_info.db new file mode 100644 index 0000000..b2686fc --- /dev/null +++ b/zynq7/segbits_dsp_r.origin_info.db @@ -0,0 +1,192 @@ +DSP_R.DSP48.DSP_0.MASK[0] origin:100-dsp-mskpat 27_01 +DSP_R.DSP48.DSP_0.MASK[10] origin:100-dsp-mskpat 27_26 +DSP_R.DSP48.DSP_0.MASK[11] origin:100-dsp-mskpat 26_28 +DSP_R.DSP48.DSP_0.MASK[12] origin:100-dsp-mskpat 26_41 +DSP_R.DSP48.DSP_0.MASK[13] origin:100-dsp-mskpat 27_42 +DSP_R.DSP48.DSP_0.MASK[14] origin:100-dsp-mskpat 26_45 +DSP_R.DSP48.DSP_0.MASK[15] origin:100-dsp-mskpat 27_46 +DSP_R.DSP48.DSP_0.MASK[16] origin:100-dsp-mskpat 26_49 +DSP_R.DSP48.DSP_0.MASK[17] origin:100-dsp-mskpat 27_50 +DSP_R.DSP48.DSP_0.MASK[18] origin:100-dsp-mskpat 27_57 +DSP_R.DSP48.DSP_0.MASK[19] origin:100-dsp-mskpat 26_59 +DSP_R.DSP48.DSP_0.MASK[1] origin:100-dsp-mskpat 26_03 +DSP_R.DSP48.DSP_0.MASK[20] origin:100-dsp-mskpat 26_62 +DSP_R.DSP48.DSP_0.MASK[21] origin:100-dsp-mskpat 27_63 +DSP_R.DSP48.DSP_0.MASK[22] origin:100-dsp-mskpat 26_66 +DSP_R.DSP48.DSP_0.MASK[23] origin:100-dsp-mskpat 27_67 +DSP_R.DSP48.DSP_0.MASK[24] origin:100-dsp-mskpat 27_86 +DSP_R.DSP48.DSP_0.MASK[25] origin:100-dsp-mskpat 26_88 +DSP_R.DSP48.DSP_0.MASK[26] origin:100-dsp-mskpat 27_90 +DSP_R.DSP48.DSP_0.MASK[27] origin:100-dsp-mskpat 26_92 +DSP_R.DSP48.DSP_0.MASK[28] origin:100-dsp-mskpat 27_94 +DSP_R.DSP48.DSP_0.MASK[29] origin:100-dsp-mskpat 26_96 +DSP_R.DSP48.DSP_0.MASK[2] origin:100-dsp-mskpat 27_06 +DSP_R.DSP48.DSP_0.MASK[30] origin:100-dsp-mskpat 27_102 +DSP_R.DSP48.DSP_0.MASK[31] origin:100-dsp-mskpat 26_104 +DSP_R.DSP48.DSP_0.MASK[32] origin:100-dsp-mskpat 27_106 +DSP_R.DSP48.DSP_0.MASK[33] origin:100-dsp-mskpat 26_108 +DSP_R.DSP48.DSP_0.MASK[34] origin:100-dsp-mskpat 27_110 +DSP_R.DSP48.DSP_0.MASK[35] origin:100-dsp-mskpat 26_112 +DSP_R.DSP48.DSP_0.MASK[36] origin:100-dsp-mskpat 27_127 +DSP_R.DSP48.DSP_0.MASK[37] origin:100-dsp-mskpat 26_129 +DSP_R.DSP48.DSP_0.MASK[38] origin:100-dsp-mskpat 26_132 +DSP_R.DSP48.DSP_0.MASK[39] origin:100-dsp-mskpat 27_133 +DSP_R.DSP48.DSP_0.MASK[3] origin:100-dsp-mskpat 26_07 +DSP_R.DSP48.DSP_0.MASK[40] origin:100-dsp-mskpat 26_136 +DSP_R.DSP48.DSP_0.MASK[41] origin:100-dsp-mskpat 27_137 +DSP_R.DSP48.DSP_0.MASK[42] origin:100-dsp-mskpat 27_144 +DSP_R.DSP48.DSP_0.MASK[43] origin:100-dsp-mskpat 26_146 +DSP_R.DSP48.DSP_0.MASK[44] origin:100-dsp-mskpat 26_149 +DSP_R.DSP48.DSP_0.MASK[45] origin:100-dsp-mskpat 27_150 +DSP_R.DSP48.DSP_0.MASK[46] origin:100-dsp-mskpat 26_153 +DSP_R.DSP48.DSP_0.MASK[47] origin:100-dsp-mskpat 26_154 +DSP_R.DSP48.DSP_0.MASK[4] origin:100-dsp-mskpat 26_10 +DSP_R.DSP48.DSP_0.MASK[5] origin:100-dsp-mskpat 27_11 +DSP_R.DSP48.DSP_0.MASK[6] origin:100-dsp-mskpat 26_18 +DSP_R.DSP48.DSP_0.MASK[7] origin:100-dsp-mskpat 27_19 +DSP_R.DSP48.DSP_0.MASK[8] origin:100-dsp-mskpat 26_22 +DSP_R.DSP48.DSP_0.MASK[9] origin:100-dsp-mskpat 27_23 +DSP_R.DSP48.DSP_0.PATTERN[0] origin:100-dsp-mskpat 26_01 +DSP_R.DSP48.DSP_0.PATTERN[10] origin:100-dsp-mskpat 26_26 +DSP_R.DSP48.DSP_0.PATTERN[11] origin:100-dsp-mskpat 26_29 +DSP_R.DSP48.DSP_0.PATTERN[12] origin:100-dsp-mskpat 27_40 +DSP_R.DSP48.DSP_0.PATTERN[13] origin:100-dsp-mskpat 26_43 +DSP_R.DSP48.DSP_0.PATTERN[14] origin:100-dsp-mskpat 27_44 +DSP_R.DSP48.DSP_0.PATTERN[15] origin:100-dsp-mskpat 26_47 +DSP_R.DSP48.DSP_0.PATTERN[16] origin:100-dsp-mskpat 27_48 +DSP_R.DSP48.DSP_0.PATTERN[17] origin:100-dsp-mskpat 26_51 +DSP_R.DSP48.DSP_0.PATTERN[18] origin:100-dsp-mskpat 26_57 +DSP_R.DSP48.DSP_0.PATTERN[19] origin:100-dsp-mskpat 26_60 +DSP_R.DSP48.DSP_0.PATTERN[1] origin:100-dsp-mskpat 26_04 +DSP_R.DSP48.DSP_0.PATTERN[20] origin:100-dsp-mskpat 27_61 +DSP_R.DSP48.DSP_0.PATTERN[21] origin:100-dsp-mskpat 26_64 +DSP_R.DSP48.DSP_0.PATTERN[22] origin:100-dsp-mskpat 27_65 +DSP_R.DSP48.DSP_0.PATTERN[23] origin:100-dsp-mskpat 26_68 +DSP_R.DSP48.DSP_0.PATTERN[24] origin:100-dsp-mskpat 26_86 +DSP_R.DSP48.DSP_0.PATTERN[25] origin:100-dsp-mskpat 27_88 +DSP_R.DSP48.DSP_0.PATTERN[26] origin:100-dsp-mskpat 26_90 +DSP_R.DSP48.DSP_0.PATTERN[27] origin:100-dsp-mskpat 27_92 +DSP_R.DSP48.DSP_0.PATTERN[28] origin:100-dsp-mskpat 26_94 +DSP_R.DSP48.DSP_0.PATTERN[29] origin:100-dsp-mskpat 26_97 +DSP_R.DSP48.DSP_0.PATTERN[2] origin:100-dsp-mskpat 26_05 +DSP_R.DSP48.DSP_0.PATTERN[30] origin:100-dsp-mskpat 27_101 +DSP_R.DSP48.DSP_0.PATTERN[31] origin:100-dsp-mskpat 27_104 +DSP_R.DSP48.DSP_0.PATTERN[32] origin:100-dsp-mskpat 26_106 +DSP_R.DSP48.DSP_0.PATTERN[33] origin:100-dsp-mskpat 27_108 +DSP_R.DSP48.DSP_0.PATTERN[34] origin:100-dsp-mskpat 26_110 +DSP_R.DSP48.DSP_0.PATTERN[35] origin:100-dsp-mskpat 27_112 +DSP_R.DSP48.DSP_0.PATTERN[36] origin:100-dsp-mskpat 26_127 +DSP_R.DSP48.DSP_0.PATTERN[37] origin:100-dsp-mskpat 26_130 +DSP_R.DSP48.DSP_0.PATTERN[38] origin:100-dsp-mskpat 27_131 +DSP_R.DSP48.DSP_0.PATTERN[39] origin:100-dsp-mskpat 26_134 +DSP_R.DSP48.DSP_0.PATTERN[3] origin:100-dsp-mskpat 27_08 +DSP_R.DSP48.DSP_0.PATTERN[40] origin:100-dsp-mskpat 27_135 +DSP_R.DSP48.DSP_0.PATTERN[41] origin:100-dsp-mskpat 26_138 +DSP_R.DSP48.DSP_0.PATTERN[42] origin:100-dsp-mskpat 26_144 +DSP_R.DSP48.DSP_0.PATTERN[43] origin:100-dsp-mskpat 27_146 +DSP_R.DSP48.DSP_0.PATTERN[44] origin:100-dsp-mskpat 26_148 +DSP_R.DSP48.DSP_0.PATTERN[45] origin:100-dsp-mskpat 26_151 +DSP_R.DSP48.DSP_0.PATTERN[46] origin:100-dsp-mskpat 27_152 +DSP_R.DSP48.DSP_0.PATTERN[47] origin:100-dsp-mskpat 26_155 +DSP_R.DSP48.DSP_0.PATTERN[4] origin:100-dsp-mskpat 26_09 +DSP_R.DSP48.DSP_0.PATTERN[5] origin:100-dsp-mskpat 26_12 +DSP_R.DSP48.DSP_0.PATTERN[6] origin:100-dsp-mskpat 27_17 +DSP_R.DSP48.DSP_0.PATTERN[7] origin:100-dsp-mskpat 26_20 +DSP_R.DSP48.DSP_0.PATTERN[8] origin:100-dsp-mskpat 27_21 +DSP_R.DSP48.DSP_0.PATTERN[9] origin:100-dsp-mskpat 27_24 +DSP_R.DSP48.DSP_1.MASK[0] origin:100-dsp-mskpat 27_161 +DSP_R.DSP48.DSP_1.MASK[10] origin:100-dsp-mskpat 27_186 +DSP_R.DSP48.DSP_1.MASK[11] origin:100-dsp-mskpat 26_188 +DSP_R.DSP48.DSP_1.MASK[12] origin:100-dsp-mskpat 26_201 +DSP_R.DSP48.DSP_1.MASK[13] origin:100-dsp-mskpat 27_202 +DSP_R.DSP48.DSP_1.MASK[14] origin:100-dsp-mskpat 26_205 +DSP_R.DSP48.DSP_1.MASK[15] origin:100-dsp-mskpat 27_206 +DSP_R.DSP48.DSP_1.MASK[16] origin:100-dsp-mskpat 26_209 +DSP_R.DSP48.DSP_1.MASK[17] origin:100-dsp-mskpat 27_210 +DSP_R.DSP48.DSP_1.MASK[18] origin:100-dsp-mskpat 27_217 +DSP_R.DSP48.DSP_1.MASK[19] origin:100-dsp-mskpat 26_219 +DSP_R.DSP48.DSP_1.MASK[1] origin:100-dsp-mskpat 26_163 +DSP_R.DSP48.DSP_1.MASK[20] origin:100-dsp-mskpat 26_222 +DSP_R.DSP48.DSP_1.MASK[21] origin:100-dsp-mskpat 27_223 +DSP_R.DSP48.DSP_1.MASK[22] origin:100-dsp-mskpat 26_226 +DSP_R.DSP48.DSP_1.MASK[23] origin:100-dsp-mskpat 27_227 +DSP_R.DSP48.DSP_1.MASK[24] origin:100-dsp-mskpat 27_246 +DSP_R.DSP48.DSP_1.MASK[25] origin:100-dsp-mskpat 26_248 +DSP_R.DSP48.DSP_1.MASK[26] origin:100-dsp-mskpat 27_250 +DSP_R.DSP48.DSP_1.MASK[27] origin:100-dsp-mskpat 26_252 +DSP_R.DSP48.DSP_1.MASK[28] origin:100-dsp-mskpat 27_254 +DSP_R.DSP48.DSP_1.MASK[29] origin:100-dsp-mskpat 26_256 +DSP_R.DSP48.DSP_1.MASK[2] origin:100-dsp-mskpat 27_166 +DSP_R.DSP48.DSP_1.MASK[30] origin:100-dsp-mskpat 27_262 +DSP_R.DSP48.DSP_1.MASK[31] origin:100-dsp-mskpat 26_264 +DSP_R.DSP48.DSP_1.MASK[32] origin:100-dsp-mskpat 27_266 +DSP_R.DSP48.DSP_1.MASK[33] origin:100-dsp-mskpat 26_268 +DSP_R.DSP48.DSP_1.MASK[34] origin:100-dsp-mskpat 27_270 +DSP_R.DSP48.DSP_1.MASK[35] origin:100-dsp-mskpat 26_272 +DSP_R.DSP48.DSP_1.MASK[36] origin:100-dsp-mskpat 27_287 +DSP_R.DSP48.DSP_1.MASK[37] origin:100-dsp-mskpat 26_289 +DSP_R.DSP48.DSP_1.MASK[38] origin:100-dsp-mskpat 26_292 +DSP_R.DSP48.DSP_1.MASK[39] origin:100-dsp-mskpat 27_293 +DSP_R.DSP48.DSP_1.MASK[3] origin:100-dsp-mskpat 26_167 +DSP_R.DSP48.DSP_1.MASK[40] origin:100-dsp-mskpat 26_296 +DSP_R.DSP48.DSP_1.MASK[41] origin:100-dsp-mskpat 27_297 +DSP_R.DSP48.DSP_1.MASK[42] origin:100-dsp-mskpat 27_304 +DSP_R.DSP48.DSP_1.MASK[43] origin:100-dsp-mskpat 26_306 +DSP_R.DSP48.DSP_1.MASK[44] origin:100-dsp-mskpat 26_309 +DSP_R.DSP48.DSP_1.MASK[45] origin:100-dsp-mskpat 27_310 +DSP_R.DSP48.DSP_1.MASK[46] origin:100-dsp-mskpat 26_313 +DSP_R.DSP48.DSP_1.MASK[47] origin:100-dsp-mskpat 26_314 +DSP_R.DSP48.DSP_1.MASK[4] origin:100-dsp-mskpat 26_170 +DSP_R.DSP48.DSP_1.MASK[5] origin:100-dsp-mskpat 27_171 +DSP_R.DSP48.DSP_1.MASK[6] origin:100-dsp-mskpat 26_178 +DSP_R.DSP48.DSP_1.MASK[7] origin:100-dsp-mskpat 27_179 +DSP_R.DSP48.DSP_1.MASK[8] origin:100-dsp-mskpat 26_182 +DSP_R.DSP48.DSP_1.MASK[9] origin:100-dsp-mskpat 27_183 +DSP_R.DSP48.DSP_1.PATTERN[0] origin:100-dsp-mskpat 26_161 +DSP_R.DSP48.DSP_1.PATTERN[10] origin:100-dsp-mskpat 26_186 +DSP_R.DSP48.DSP_1.PATTERN[11] origin:100-dsp-mskpat 26_189 +DSP_R.DSP48.DSP_1.PATTERN[12] origin:100-dsp-mskpat 27_200 +DSP_R.DSP48.DSP_1.PATTERN[13] origin:100-dsp-mskpat 26_203 +DSP_R.DSP48.DSP_1.PATTERN[14] origin:100-dsp-mskpat 27_204 +DSP_R.DSP48.DSP_1.PATTERN[15] origin:100-dsp-mskpat 26_207 +DSP_R.DSP48.DSP_1.PATTERN[16] origin:100-dsp-mskpat 27_208 +DSP_R.DSP48.DSP_1.PATTERN[17] origin:100-dsp-mskpat 26_211 +DSP_R.DSP48.DSP_1.PATTERN[18] origin:100-dsp-mskpat 26_217 +DSP_R.DSP48.DSP_1.PATTERN[19] origin:100-dsp-mskpat 26_220 +DSP_R.DSP48.DSP_1.PATTERN[1] origin:100-dsp-mskpat 26_164 +DSP_R.DSP48.DSP_1.PATTERN[20] origin:100-dsp-mskpat 27_221 +DSP_R.DSP48.DSP_1.PATTERN[21] origin:100-dsp-mskpat 26_224 +DSP_R.DSP48.DSP_1.PATTERN[22] origin:100-dsp-mskpat 27_225 +DSP_R.DSP48.DSP_1.PATTERN[23] origin:100-dsp-mskpat 26_228 +DSP_R.DSP48.DSP_1.PATTERN[24] origin:100-dsp-mskpat 26_246 +DSP_R.DSP48.DSP_1.PATTERN[25] origin:100-dsp-mskpat 27_248 +DSP_R.DSP48.DSP_1.PATTERN[26] origin:100-dsp-mskpat 26_250 +DSP_R.DSP48.DSP_1.PATTERN[27] origin:100-dsp-mskpat 27_252 +DSP_R.DSP48.DSP_1.PATTERN[28] origin:100-dsp-mskpat 26_254 +DSP_R.DSP48.DSP_1.PATTERN[29] origin:100-dsp-mskpat 26_257 +DSP_R.DSP48.DSP_1.PATTERN[2] origin:100-dsp-mskpat 26_165 +DSP_R.DSP48.DSP_1.PATTERN[30] origin:100-dsp-mskpat 27_261 +DSP_R.DSP48.DSP_1.PATTERN[31] origin:100-dsp-mskpat 27_264 +DSP_R.DSP48.DSP_1.PATTERN[32] origin:100-dsp-mskpat 26_266 +DSP_R.DSP48.DSP_1.PATTERN[33] origin:100-dsp-mskpat 27_268 +DSP_R.DSP48.DSP_1.PATTERN[34] origin:100-dsp-mskpat 26_270 +DSP_R.DSP48.DSP_1.PATTERN[35] origin:100-dsp-mskpat 27_272 +DSP_R.DSP48.DSP_1.PATTERN[36] origin:100-dsp-mskpat 26_287 +DSP_R.DSP48.DSP_1.PATTERN[37] origin:100-dsp-mskpat 26_290 +DSP_R.DSP48.DSP_1.PATTERN[38] origin:100-dsp-mskpat 27_291 +DSP_R.DSP48.DSP_1.PATTERN[39] origin:100-dsp-mskpat 26_294 +DSP_R.DSP48.DSP_1.PATTERN[3] origin:100-dsp-mskpat 27_168 +DSP_R.DSP48.DSP_1.PATTERN[40] origin:100-dsp-mskpat 27_295 +DSP_R.DSP48.DSP_1.PATTERN[41] origin:100-dsp-mskpat 26_298 +DSP_R.DSP48.DSP_1.PATTERN[42] origin:100-dsp-mskpat 26_304 +DSP_R.DSP48.DSP_1.PATTERN[43] origin:100-dsp-mskpat 27_306 +DSP_R.DSP48.DSP_1.PATTERN[44] origin:100-dsp-mskpat 26_308 +DSP_R.DSP48.DSP_1.PATTERN[45] origin:100-dsp-mskpat 26_311 +DSP_R.DSP48.DSP_1.PATTERN[46] origin:100-dsp-mskpat 27_312 +DSP_R.DSP48.DSP_1.PATTERN[47] origin:100-dsp-mskpat 26_315 +DSP_R.DSP48.DSP_1.PATTERN[4] origin:100-dsp-mskpat 26_169 +DSP_R.DSP48.DSP_1.PATTERN[5] origin:100-dsp-mskpat 26_172 +DSP_R.DSP48.DSP_1.PATTERN[6] origin:100-dsp-mskpat 27_177 +DSP_R.DSP48.DSP_1.PATTERN[7] origin:100-dsp-mskpat 26_180 +DSP_R.DSP48.DSP_1.PATTERN[8] origin:100-dsp-mskpat 27_181 +DSP_R.DSP48.DSP_1.PATTERN[9] origin:100-dsp-mskpat 27_184 diff --git a/zynq7/segbits_hclk_cmt_l.origin_info.db b/zynq7/segbits_hclk_cmt_l.origin_info.db new file mode 100644 index 0000000..af04bc6 --- /dev/null +++ b/zynq7/segbits_hclk_cmt_l.origin_info.db @@ -0,0 +1,644 @@ +HCLK_CMT_L.HCLK_CMT_CCIO0_ACTIVE origin:045-hclk-cmt-pips 27_157 27_159 +HCLK_CMT_L.HCLK_CMT_CCIO1_ACTIVE origin:045-hclk-cmt-pips 26_156 26_159 +HCLK_CMT_L.HCLK_CMT_CCIO2_ACTIVE origin:045-hclk-cmt-pips 27_158 28_217 +HCLK_CMT_L.HCLK_CMT_CCIO3_ACTIVE origin:045-hclk-cmt-pips 26_158 29_218 +HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0_ACTIVE origin:045-hclk-cmt-pips 27_185 +HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK10_ACTIVE origin:045-hclk-cmt-pips 28_186 +HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK11_ACTIVE origin:045-hclk-cmt-pips 29_186 +HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK1_ACTIVE origin:045-hclk-cmt-pips 26_185 +HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK2_ACTIVE origin:045-hclk-cmt-pips 27_184 +HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3_ACTIVE origin:045-hclk-cmt-pips 26_184 +HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4_ACTIVE origin:045-hclk-cmt-pips 27_183 +HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5_ACTIVE origin:045-hclk-cmt-pips 26_183 +HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK6_ACTIVE origin:045-hclk-cmt-pips 27_182 +HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK7_ACTIVE origin:045-hclk-cmt-pips 26_182 +HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8_ACTIVE origin:045-hclk-cmt-pips 27_181 +HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK9_ACTIVE origin:045-hclk-cmt-pips 26_181 +HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK0_ACTIVE origin:045-hclk-cmt-pips 28_174 +HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK1_ACTIVE origin:045-hclk-cmt-pips 29_174 +HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK2_ACTIVE origin:045-hclk-cmt-pips 28_175 +HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3_ACTIVE origin:045-hclk-cmt-pips 29_175 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 27_151 27_153 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_153 27_151 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_152 27_153 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 26_152 26_153 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 27_150 27_155 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_155 27_150 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_151 27_153 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 26_151 26_153 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 27_150 27_154 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_154 27_150 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 27_150 27_153 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_153 27_150 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_151 27_155 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 26_151 26_155 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_151 27_154 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 26_151 26_154 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 27_149 27_154 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_154 27_149 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 27_151 27_155 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_155 27_151 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 27_151 27_154 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 27_149 27_153 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_153 27_149 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_150 27_155 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 26_150 26_155 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_150 27_154 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 26_150 26_154 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_150 27_153 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 26_150 26_153 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_149 27_155 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 26_149 26_155 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_149 27_154 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 26_149 26_154 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_149 27_153 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 26_149 26_153 +HCLK_CMT_L.HCLK_CMT_CK_IN0.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 27_149 27_155 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 29_151 29_153 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_153 29_151 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_152 29_153 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 28_152 28_153 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 29_150 29_155 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_155 29_150 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_151 29_153 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 28_151 28_153 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 29_150 29_154 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_154 29_150 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 29_150 29_153 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_153 29_150 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_151 29_155 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 28_151 28_155 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_151 29_154 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 28_151 28_154 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 29_149 29_154 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 28_154 29_149 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 29_151 29_155 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 28_155 29_151 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 29_151 29_154 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 29_149 29_153 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 28_153 29_149 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 28_150 29_155 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 28_150 28_155 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 28_150 29_154 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 28_150 28_154 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 28_150 29_153 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 28_150 28_153 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 28_149 29_155 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 28_149 28_155 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 28_149 29_154 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 28_149 28_154 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 28_149 29_153 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 28_149 28_153 +HCLK_CMT_L.HCLK_CMT_CK_IN1.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 29_149 29_155 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 28_205 28_207 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_207 29_205 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_205 29_206 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 29_205 29_206 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 28_203 28_208 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_208 29_203 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_205 29_207 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 29_205 29_207 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 28_204 28_208 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_208 29_204 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 28_205 28_208 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_208 29_205 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_203 29_207 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 29_203 29_207 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_204 29_207 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 29_204 29_207 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 28_204 28_209 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 28_209 29_204 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 28_203 28_207 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 28_207 29_203 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 28_204 28_207 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 28_205 28_209 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 28_209 29_205 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 28_203 29_208 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 29_203 29_208 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 28_204 29_208 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 29_204 29_208 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 28_205 29_208 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 29_205 29_208 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 28_203 29_209 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 29_203 29_209 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 28_204 29_209 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 29_204 29_209 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 28_205 29_209 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 29_205 29_209 +HCLK_CMT_L.HCLK_CMT_CK_IN10.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 28_203 28_209 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 26_212 26_214 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_214 27_212 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_212 27_213 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 27_212 27_213 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 26_210 26_215 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_215 27_210 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_212 27_214 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 27_212 27_214 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 26_211 26_215 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_215 27_211 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 26_212 26_215 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_215 27_212 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_210 27_214 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 27_210 27_214 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_211 27_214 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 27_211 27_214 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 26_211 26_216 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_216 27_211 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 26_210 26_214 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_214 27_210 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 26_211 26_214 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 26_212 26_216 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_216 27_212 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_210 27_215 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 27_210 27_215 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_211 27_215 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 27_211 27_215 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_212 27_215 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 27_212 27_215 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_210 27_216 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 27_210 27_216 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_211 27_216 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 27_211 27_216 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_212 27_216 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 27_212 27_216 +HCLK_CMT_L.HCLK_CMT_CK_IN11.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 26_210 26_216 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 28_212 28_214 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_214 29_212 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_212 29_213 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 29_212 29_213 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 28_210 28_215 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_215 29_210 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_212 29_214 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 29_212 29_214 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 28_211 28_215 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_215 29_211 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 28_212 28_215 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_215 29_212 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_210 29_214 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 29_210 29_214 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_211 29_214 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 29_211 29_214 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 28_211 28_216 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 28_216 29_211 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 28_210 28_214 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 28_214 29_210 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 28_211 28_214 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 28_212 28_216 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 28_216 29_212 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 28_210 29_215 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 29_210 29_215 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 28_211 29_215 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 29_211 29_215 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 28_212 29_215 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 29_212 29_215 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 28_210 29_216 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 29_210 29_216 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 28_211 29_216 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 29_211 29_216 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 28_212 29_216 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 29_212 29_216 +HCLK_CMT_L.HCLK_CMT_CK_IN12.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 28_210 28_216 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 26_219 26_221 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_221 27_219 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_219 27_220 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 27_219 27_220 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 26_217 26_222 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_222 27_217 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_219 27_221 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 27_219 27_221 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 26_218 26_222 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_222 27_218 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 26_219 26_222 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_222 27_219 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_217 27_221 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 27_217 27_221 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_218 27_221 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 27_218 27_221 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 26_218 26_223 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_223 27_218 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 26_217 26_221 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_221 27_217 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 26_218 26_221 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 26_219 26_223 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_223 27_219 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_217 27_222 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 27_217 27_222 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_218 27_222 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 27_218 27_222 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_219 27_222 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 27_219 27_222 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_217 27_223 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 27_217 27_223 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_218 27_223 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 27_218 27_223 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_219 27_223 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 27_219 27_223 +HCLK_CMT_L.HCLK_CMT_CK_IN13.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 26_217 26_223 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 27_144 27_146 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_146 27_144 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_145 27_146 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 26_145 26_146 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 27_143 27_148 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_148 27_143 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_144 27_146 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 26_144 26_146 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 27_143 27_147 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_147 27_143 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 27_143 27_146 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_146 27_143 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_144 27_148 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 26_144 26_148 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_144 27_147 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 26_144 26_147 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 27_142 27_147 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_147 27_142 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 27_144 27_148 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_148 27_144 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 27_144 27_147 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 27_142 27_146 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_146 27_142 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_143 27_148 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 26_143 26_148 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_143 27_147 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 26_143 26_147 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_143 27_146 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 26_143 26_146 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_142 27_148 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 26_142 26_148 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_142 27_147 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 26_142 26_147 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_142 27_146 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 26_142 26_146 +HCLK_CMT_L.HCLK_CMT_CK_IN2.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 27_142 27_148 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 29_144 29_146 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_146 29_144 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_145 29_146 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 28_145 28_146 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 29_143 29_148 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_148 29_143 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_144 29_146 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 28_144 28_146 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 29_143 29_147 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_147 29_143 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 29_143 29_146 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_146 29_143 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_144 29_148 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 28_144 28_148 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_144 29_147 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 28_144 28_147 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 29_142 29_147 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 28_147 29_142 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 29_144 29_148 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 28_148 29_144 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 29_144 29_147 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 29_142 29_146 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 28_146 29_142 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 28_143 29_148 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 28_143 28_148 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 28_143 29_147 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 28_143 28_147 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 28_143 29_146 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 28_143 28_146 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 28_142 29_148 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 28_142 28_148 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 28_142 29_147 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 28_142 28_147 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 28_142 29_146 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 28_142 28_146 +HCLK_CMT_L.HCLK_CMT_CK_IN3.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 29_142 29_148 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 27_137 27_139 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_139 27_137 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_138 27_139 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 26_138 26_139 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 27_136 27_141 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_141 27_136 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_137 27_139 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 26_137 26_139 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 27_136 27_140 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_140 27_136 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 27_136 27_139 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_139 27_136 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_137 27_141 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 26_137 26_141 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_137 27_140 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 26_137 26_140 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 27_135 27_140 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_140 27_135 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 27_137 27_141 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_141 27_137 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 27_137 27_140 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 27_135 27_139 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_139 27_135 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_136 27_141 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 26_136 26_141 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_136 27_140 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 26_136 26_140 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_136 27_139 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 26_136 26_139 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_135 27_141 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 26_135 26_141 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_135 27_140 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 26_135 26_140 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_135 27_139 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 26_135 26_139 +HCLK_CMT_L.HCLK_CMT_CK_IN4.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 27_135 27_141 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 29_137 29_139 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_139 29_137 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_138 29_139 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 28_138 28_139 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 29_136 29_141 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_141 29_136 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_137 29_139 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 28_137 28_139 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 29_136 29_140 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_140 29_136 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 29_136 29_139 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_139 29_136 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_137 29_141 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 28_137 28_141 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_137 29_140 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 28_137 28_140 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 29_135 29_140 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 28_140 29_135 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 29_137 29_141 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 28_141 29_137 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 29_137 29_140 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 29_135 29_139 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 28_139 29_135 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 28_136 29_141 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 28_136 28_141 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 28_136 29_140 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 28_136 28_140 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 28_136 29_139 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 28_136 28_139 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 28_135 29_141 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 28_135 28_141 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 28_135 29_140 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 28_135 28_140 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 28_135 29_139 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 28_135 28_139 +HCLK_CMT_L.HCLK_CMT_CK_IN5.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 29_135 29_141 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 27_130 27_132 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_132 27_130 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_131 27_132 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 26_131 26_132 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 27_129 27_134 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_134 27_129 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_130 27_132 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 26_130 26_132 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 27_129 27_133 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_133 27_129 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 27_129 27_132 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_132 27_129 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_130 27_134 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 26_130 26_134 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_130 27_133 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 26_130 26_133 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 27_128 27_133 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_133 27_128 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 27_130 27_134 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_134 27_130 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 27_130 27_133 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 27_128 27_132 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_132 27_128 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_129 27_134 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 26_129 26_134 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_129 27_133 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 26_129 26_133 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_129 27_132 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 26_129 26_132 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_128 27_134 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 26_128 26_134 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_128 27_133 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 26_128 26_133 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_128 27_132 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 26_128 26_132 +HCLK_CMT_L.HCLK_CMT_CK_IN6.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 27_128 27_134 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 26_198 26_200 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_200 27_198 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_198 27_199 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 27_198 27_199 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 26_196 26_201 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_201 27_196 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_198 27_200 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 27_198 27_200 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 26_197 26_201 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_201 27_197 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 26_198 26_201 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_201 27_198 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_196 27_200 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 27_196 27_200 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_197 27_200 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 27_197 27_200 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 26_197 26_202 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_202 27_197 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 26_196 26_200 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_200 27_196 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 26_197 26_200 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 26_198 26_202 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_202 27_198 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_196 27_201 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 27_196 27_201 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_197 27_201 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 27_197 27_201 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_198 27_201 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 27_198 27_201 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_196 27_202 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 27_196 27_202 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_197 27_202 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 27_197 27_202 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_198 27_202 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 27_198 27_202 +HCLK_CMT_L.HCLK_CMT_CK_IN7.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 26_196 26_202 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 28_198 28_200 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_200 29_198 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_198 29_199 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 29_198 29_199 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 28_196 28_201 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_201 29_196 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_198 29_200 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 29_198 29_200 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 28_197 28_201 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_201 29_197 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 28_198 28_201 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_201 29_198 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_196 29_200 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 29_196 29_200 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_197 29_200 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 29_197 29_200 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 28_197 28_202 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 28_202 29_197 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 28_196 28_200 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 28_200 29_196 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 28_197 28_200 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 28_198 28_202 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 28_202 29_198 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 28_196 29_201 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 29_196 29_201 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 28_197 29_201 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 29_197 29_201 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 28_198 29_201 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 29_198 29_201 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 28_196 29_202 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 29_196 29_202 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 28_197 29_202 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 29_197 29_202 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 28_198 29_202 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 29_198 29_202 +HCLK_CMT_L.HCLK_CMT_CK_IN8.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 28_196 28_202 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 26_205 26_207 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_207 27_205 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_205 27_206 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 27_205 27_206 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 26_203 26_208 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_208 27_203 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_205 27_207 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 27_205 27_207 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 26_204 26_208 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_208 27_204 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 26_205 26_208 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_208 27_205 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_203 27_207 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 27_203 27_207 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_204 27_207 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 27_204 27_207 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM0 origin:045-hclk-cmt-pips 26_204 26_209 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM1 origin:045-hclk-cmt-pips 26_209 27_204 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM10 origin:045-hclk-cmt-pips 26_203 26_207 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM11 origin:045-hclk-cmt-pips 26_207 27_203 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM12 origin:045-hclk-cmt-pips 26_204 26_207 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM2 origin:045-hclk-cmt-pips 26_205 26_209 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM3 origin:045-hclk-cmt-pips 26_209 27_205 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM4 origin:045-hclk-cmt-pips 26_203 27_208 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM5 origin:045-hclk-cmt-pips 27_203 27_208 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM6 origin:045-hclk-cmt-pips 26_204 27_208 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM7 origin:045-hclk-cmt-pips 27_204 27_208 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM8 origin:045-hclk-cmt-pips 26_205 27_208 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_MMCM9 origin:045-hclk-cmt-pips 27_205 27_208 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL0 origin:045-hclk-cmt-pips 26_203 27_209 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL1 origin:045-hclk-cmt-pips 27_203 27_209 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL2 origin:045-hclk-cmt-pips 26_204 27_209 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL3 origin:045-hclk-cmt-pips 27_204 27_209 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL4 origin:045-hclk-cmt-pips 26_205 27_209 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL5 origin:045-hclk-cmt-pips 27_205 27_209 +HCLK_CMT_L.HCLK_CMT_CK_IN9.HCLK_CMT_MUX_CLK_PLL6 origin:045-hclk-cmt-pips 26_203 26_209 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 27_123 27_125 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_125 27_123 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_124 27_125 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 26_124 26_125 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 27_122 27_127 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_127 27_122 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_123 27_125 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 26_123 26_125 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 27_122 27_126 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_126 27_122 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 27_122 27_125 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_125 27_122 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_123 27_127 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 26_123 26_127 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_123 27_126 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 26_123 26_126 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFRCLK0 origin:045-hclk-cmt-pips 27_123 27_127 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFRCLK1 origin:045-hclk-cmt-pips 26_127 27_123 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFRCLK2 origin:045-hclk-cmt-pips 27_123 27_126 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKFBIN.HCLK_CMT_CK_BUFRCLK3 origin:045-hclk-cmt-pips 26_126 27_123 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 28_118 28_120 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_118 29_119 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_120 29_118 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 29_118 29_119 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 28_117 28_122 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_117 29_121 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_120 29_117 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 29_117 29_119 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 28_117 28_121 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_117 29_120 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 28_117 28_120 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_117 29_119 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_122 29_117 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 29_117 29_121 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_121 29_117 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 29_117 29_120 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFRCLK0 origin:045-hclk-cmt-pips 28_118 28_122 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFRCLK1 origin:045-hclk-cmt-pips 28_118 29_121 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFRCLK2 origin:045-hclk-cmt-pips 28_118 28_121 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN1.HCLK_CMT_CK_BUFRCLK3 origin:045-hclk-cmt-pips 28_118 29_120 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 26_118 26_120 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_118 27_119 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_120 27_118 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 27_118 27_119 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 26_117 26_122 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_117 27_121 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_120 27_117 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 27_117 27_119 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 26_117 26_121 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_117 27_120 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 26_117 26_120 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_117 27_119 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_122 27_117 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 27_117 27_121 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_121 27_117 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 27_117 27_120 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFRCLK0 origin:045-hclk-cmt-pips 26_118 26_122 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFRCLK1 origin:045-hclk-cmt-pips 26_118 27_121 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFRCLK2 origin:045-hclk-cmt-pips 26_118 26_121 +HCLK_CMT_L.HCLK_CMT_MUX_MMCM_CLKIN2.HCLK_CMT_CK_BUFRCLK3 origin:045-hclk-cmt-pips 26_118 27_120 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 26_226 26_228 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_228 27_226 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_226 27_227 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 27_226 27_227 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 26_224 26_229 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_229 27_224 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_226 27_228 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 27_226 27_228 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 26_225 26_229 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_229 27_225 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 26_226 26_229 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_229 27_226 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_224 27_228 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 27_224 27_228 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_225 27_228 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 27_225 27_228 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFRCLK0 origin:045-hclk-cmt-pips 26_224 26_228 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFRCLK1 origin:045-hclk-cmt-pips 26_228 27_224 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFRCLK2 origin:045-hclk-cmt-pips 26_225 26_228 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKFBIN.HCLK_CMT_CK_BUFRCLK3 origin:045-hclk-cmt-pips 26_228 27_225 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 29_231 29_233 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 28_232 29_233 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 28_233 29_231 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 28_232 28_233 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 29_229 29_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 28_230 29_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 28_234 29_231 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 28_232 28_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 29_230 29_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 28_231 29_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 29_231 29_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 28_232 29_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 28_234 29_229 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 28_230 28_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 28_234 29_230 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 28_231 28_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFRCLK0 origin:045-hclk-cmt-pips 29_229 29_233 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFRCLK1 origin:045-hclk-cmt-pips 28_230 29_233 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFRCLK2 origin:045-hclk-cmt-pips 29_230 29_233 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN1.HCLK_CMT_CK_BUFRCLK3 origin:045-hclk-cmt-pips 28_231 29_233 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CCIO0 origin:045-hclk-cmt-pips 27_231 27_233 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CCIO1 origin:045-hclk-cmt-pips 26_232 27_233 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CCIO2 origin:045-hclk-cmt-pips 26_233 27_231 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CCIO3 origin:045-hclk-cmt-pips 26_232 26_233 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK0 origin:045-hclk-cmt-pips 27_229 27_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK1 origin:045-hclk-cmt-pips 26_230 27_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK10 origin:045-hclk-cmt-pips 26_234 27_231 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK11 origin:045-hclk-cmt-pips 26_232 26_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK2 origin:045-hclk-cmt-pips 27_230 27_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK3 origin:045-hclk-cmt-pips 26_231 27_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK4 origin:045-hclk-cmt-pips 27_231 27_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK5 origin:045-hclk-cmt-pips 26_232 27_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK6 origin:045-hclk-cmt-pips 26_234 27_229 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK7 origin:045-hclk-cmt-pips 26_230 26_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK8 origin:045-hclk-cmt-pips 26_234 27_230 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFHCLK9 origin:045-hclk-cmt-pips 26_231 26_234 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFRCLK0 origin:045-hclk-cmt-pips 27_229 27_233 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFRCLK1 origin:045-hclk-cmt-pips 26_230 27_233 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFRCLK2 origin:045-hclk-cmt-pips 27_230 27_233 +HCLK_CMT_L.HCLK_CMT_MUX_PLLE2_CLKIN2.HCLK_CMT_CK_BUFRCLK3 origin:045-hclk-cmt-pips 26_231 27_233 diff --git a/zynq7/segbits_hclk_l.origin_info.db b/zynq7/segbits_hclk_l.origin_info.db new file mode 100644 index 0000000..90356ae --- /dev/null +++ b/zynq7/segbits_hclk_l.origin_info.db @@ -0,0 +1,196 @@ +HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 00_22 +HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 01_22 +HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 00_14 +HCLK_L.ENABLE_BUFFER.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 01_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 01_15 04_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 01_15 03_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 01_15 04_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 01_15 03_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 00_16 04_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 00_16 03_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 00_16 04_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 00_16 03_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 01_14 04_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 01_14 03_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 01_14 04_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 01_14 03_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 00_15 04_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 00_15 03_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 00_15 04_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL0.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 00_15 03_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 02_15 04_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 04_16 05_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 02_14 04_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 04_16 05_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 02_14 02_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 02_16 05_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 02_15 02_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 02_16 05_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 02_14 03_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 03_16 05_14 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 02_15 03_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 03_16 05_15 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 02_14 05_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 05_14 05_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 02_15 05_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL1.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 05_15 05_16 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 00_17 05_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 00_17 02_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 00_17 05_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 00_17 02_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 01_16 05_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 01_16 02_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 01_16 05_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 01_16 02_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 00_18 05_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 00_18 02_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 00_18 05_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 00_18 02_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 01_17 05_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 01_17 02_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 01_17 05_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL2.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 01_17 02_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 03_18 05_17 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 04_18 05_17 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 03_19 05_17 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 04_19 05_17 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 03_17 03_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 03_17 04_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 03_17 03_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 03_17 04_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 02_17 03_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 02_17 04_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 02_17 03_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 02_17 04_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 03_19 04_17 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 04_17 04_19 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 03_18 04_17 +HCLK_L.HCLK_LEAF_CLK_B_BOTL3.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 04_17 04_18 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 00_21 04_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 00_21 03_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 00_21 04_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 00_21 03_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 01_21 04_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 01_21 03_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 01_21 04_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 01_21 03_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 00_20 04_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 00_20 03_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 00_20 04_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 00_20 03_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 01_20 04_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 01_20 03_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 01_20 04_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL4.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 01_20 03_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 02_21 04_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 04_22 05_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 02_20 04_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 04_22 05_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 02_20 02_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 02_22 05_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 02_21 02_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 02_22 05_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 02_20 03_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 03_22 05_20 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 02_21 03_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 03_22 05_21 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 02_20 05_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 05_20 05_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 02_21 05_22 +HCLK_L.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 05_21 05_22 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 01_29 05_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 01_29 02_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 01_29 05_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 01_29 02_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 00_29 05_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 00_29 02_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 00_29 05_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 00_29 02_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 01_30 05_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 01_30 02_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 01_30 05_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 01_30 02_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 00_30 05_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 00_30 02_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 00_30 05_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL0.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 00_30 02_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 03_30 05_29 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 04_30 05_29 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 03_31 05_29 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 04_31 05_29 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 03_29 03_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 03_29 04_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 03_29 03_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 03_29 04_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 02_29 03_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 02_29 04_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 02_29 03_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 02_29 04_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 03_31 04_29 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 04_29 04_31 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 03_30 04_29 +HCLK_L.HCLK_LEAF_CLK_B_TOPL1.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 04_29 04_30 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 00_28 04_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 00_28 03_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 00_28 04_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 00_28 03_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 01_28 04_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 01_28 03_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 01_28 04_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 01_28 03_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 00_26 04_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 00_26 03_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 00_26 04_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 00_26 03_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 01_26 04_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 01_26 03_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 01_26 04_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL2.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 01_26 03_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 02_27 04_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 04_28 05_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 02_26 04_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 04_28 05_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 02_26 02_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 02_28 05_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 02_27 02_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 02_28 05_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 02_26 03_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 03_28 05_26 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 02_27 03_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 03_28 05_27 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 02_26 05_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 05_26 05_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 02_27 05_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL3.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 05_27 05_28 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 01_24 05_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 01_24 02_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 01_24 05_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 01_24 02_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 00_24 05_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 00_24 02_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 00_24 05_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 00_24 02_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 01_25 05_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 01_25 02_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 01_25 05_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 01_25 02_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 00_25 05_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 00_25 02_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 00_25 05_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL4.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 00_25 02_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK10 origin:058-pip-hclk 03_24 05_23 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK11 origin:058-pip-hclk 04_24 05_23 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK8 origin:058-pip-hclk 03_25 05_23 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFHCLK9 origin:058-pip-hclk 04_25 05_23 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK0 origin:058-pip-hclk 03_23 03_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK1 origin:058-pip-hclk 03_23 04_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK2 origin:058-pip-hclk 03_23 03_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_BUFRCLK3 origin:058-pip-hclk 03_23 04_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L0 origin:058-pip-hclk 02_23 03_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L1 origin:058-pip-hclk 02_23 04_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L2 origin:058-pip-hclk 02_23 03_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L3 origin:058-pip-hclk 02_23 04_24 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L4 origin:058-pip-hclk 03_25 04_23 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L5 origin:058-pip-hclk 04_23 04_25 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L6 origin:058-pip-hclk 03_24 04_23 +HCLK_L.HCLK_LEAF_CLK_B_TOPL5.HCLK_CK_OUTIN_L7 origin:058-pip-hclk 04_23 04_24 diff --git a/zynq7/segbits_hclk_r.origin_info.db b/zynq7/segbits_hclk_r.origin_info.db new file mode 100644 index 0000000..ee13faf --- /dev/null +++ b/zynq7/segbits_hclk_r.origin_info.db @@ -0,0 +1,200 @@ +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 00_14 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 01_19 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 00_22 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 01_22 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 00_23 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 01_23 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 00_31 +HCLK_R.ENABLE_BUFFER.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 01_31 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 01_14 04_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 01_14 03_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 01_14 04_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 01_14 03_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 00_15 04_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 00_15 03_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 00_15 04_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 00_15 03_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT0.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 00_16 04_14 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origin:058-pip-hclk 05_14 05_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 02_15 05_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 05_15 05_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 02_14 02_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 02_16 05_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 02_15 02_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 02_16 05_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 02_14 04_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 04_16 05_14 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 02_15 04_16 +HCLK_R.HCLK_LEAF_CLK_B_BOT1.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 04_16 05_15 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 00_18 05_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 00_18 02_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 00_18 05_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 00_18 02_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 01_17 05_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 01_17 02_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 01_17 05_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 01_17 02_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 01_16 05_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 01_16 02_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 01_16 05_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 01_16 02_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 00_17 05_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 00_17 02_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 00_17 05_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT2.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 00_17 02_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 02_17 03_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 02_17 04_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 02_17 03_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 02_17 04_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 03_19 04_17 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 04_17 04_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 03_18 04_17 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 04_17 04_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 03_17 03_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 03_17 04_19 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 03_17 03_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 03_17 04_18 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 03_19 05_17 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 04_19 05_17 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 03_18 05_17 +HCLK_R.HCLK_LEAF_CLK_B_BOT3.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 04_18 05_17 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 00_20 04_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 00_20 03_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 00_20 04_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 00_20 03_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 01_20 04_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 01_20 03_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 01_20 04_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 01_20 03_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 01_21 04_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 01_21 03_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 01_21 04_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 01_21 03_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 00_21 04_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 00_21 03_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 00_21 04_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT4.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 00_21 03_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 02_20 03_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 03_22 05_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 02_21 03_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 03_22 05_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 02_20 05_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 05_20 05_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 02_21 05_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 05_21 05_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 02_20 02_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 02_22 05_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 02_21 02_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 02_22 05_21 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 02_20 04_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 04_22 05_20 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 02_21 04_22 +HCLK_R.HCLK_LEAF_CLK_B_BOT5.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 04_22 05_21 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 01_30 05_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 01_30 02_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 01_30 05_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 01_30 02_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 00_30 05_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 00_30 02_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 00_30 05_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 00_30 02_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 00_29 05_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 00_29 02_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 00_29 05_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 00_29 02_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 01_29 05_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 01_29 02_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 01_29 05_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP0.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 01_29 02_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 02_29 03_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 02_29 04_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 02_29 03_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 02_29 04_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 03_31 04_29 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 04_29 04_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 03_30 04_29 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 04_29 04_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 03_29 03_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 03_29 04_31 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 03_29 03_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 03_29 04_30 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 03_31 05_29 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 04_31 05_29 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 03_30 05_29 +HCLK_R.HCLK_LEAF_CLK_B_TOP1.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 04_30 05_29 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 00_26 04_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 00_26 03_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 00_26 04_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 00_26 03_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 01_26 04_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 01_26 03_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 01_26 04_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 01_26 03_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 01_28 04_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 01_28 03_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 01_28 04_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 01_28 03_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 00_28 04_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 00_28 03_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 00_28 04_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP2.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 00_28 03_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 02_26 03_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 03_28 05_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 02_27 03_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 03_28 05_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 02_26 05_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 05_26 05_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 02_27 05_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 05_27 05_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 02_26 02_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 02_28 05_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 02_27 02_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 02_28 05_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 02_26 04_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 04_28 05_26 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 02_27 04_28 +HCLK_R.HCLK_LEAF_CLK_B_TOP3.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 04_28 05_27 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 01_25 05_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 01_25 02_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 01_25 05_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 01_25 02_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 00_25 05_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 00_25 02_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 00_25 05_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 00_25 02_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 00_24 05_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 00_24 02_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 00_24 05_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 00_24 02_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 01_24 05_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 01_24 02_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 01_24 05_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP4.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 01_24 02_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK0 origin:058-pip-hclk 02_23 03_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK1 origin:058-pip-hclk 02_23 04_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK2 origin:058-pip-hclk 02_23 03_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK3 origin:058-pip-hclk 02_23 04_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK4 origin:058-pip-hclk 03_25 04_23 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK5 origin:058-pip-hclk 04_23 04_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK6 origin:058-pip-hclk 03_24 04_23 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_BUFHCLK7 origin:058-pip-hclk 04_23 04_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R0 origin:058-pip-hclk 03_23 03_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R1 origin:058-pip-hclk 03_23 04_25 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R2 origin:058-pip-hclk 03_23 03_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R3 origin:058-pip-hclk 03_23 04_24 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R4 origin:058-pip-hclk 03_25 05_23 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R5 origin:058-pip-hclk 04_25 05_23 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R6 origin:058-pip-hclk 03_24 05_23 +HCLK_R.HCLK_LEAF_CLK_B_TOP5.HCLK_CK_OUTIN_R7 origin:058-pip-hclk 04_24 05_23 diff --git a/zynq7/segbits_int_l.db b/zynq7/segbits_int_l.db index 2e45a95..43670e7 100644 --- a/zynq7/segbits_int_l.db +++ b/zynq7/segbits_int_l.db @@ -1638,18 +1638,24 @@ INT_L.IMUX_L47.SS2END3 17_62 !22_62 !23_62 !24_62 25_62 INT_L.IMUX_L47.SW2END3 17_62 !22_62 !23_62 24_62 !25_62 INT_L.IMUX_L47.WL1END3 18_63 !22_62 23_62 24_62 25_62 INT_L.IMUX_L47.WW2END3 16_62 !22_62 !23_62 !24_62 25_62 +INT_L.LV_L0.LV_L18 00_09 01_06 INT_L.LV_L0.SR1BEG_S0 00_05 01_05 INT_L.LV_L0.ER1END0 01_04 01_05 +INT_L.LV_L0.LH0 00_02 01_06 INT_L.LV_L0.LH6 01_04 01_06 +INT_L.LV_L0.LH12 00_05 01_06 INT_L.LV_L0.NN6END0 00_07 00_09 INT_L.LV_L0.NR1END0 00_02 01_05 INT_L.LV_L0.NW6END0 00_07 01_04 INT_L.LV_L0.SW6END0 00_09 01_05 INT_L.LV_L0.WR1END0 00_02 00_07 INT_L.LV_L0.WW4END0 00_05 00_07 +INT_L.LV_L18.LV_L0 01_00 01_01 INT_L.LV_L18.SR1BEG_S0 00_03 01_08 INT_L.LV_L18.ER1END0 00_03 00_06 +INT_L.LV_L18.LH0 00_01 01_02 INT_L.LV_L18.LH6 00_06 01_02 +INT_L.LV_L18.LH12 01_02 01_08 INT_L.LV_L18.NN6END0 00_03 01_00 INT_L.LV_L18.NR1END0 00_01 00_03 INT_L.LV_L18.NW6END0 00_06 01_01 @@ -1658,6 +1664,7 @@ INT_L.LV_L18.WR1END0 00_01 01_01 INT_L.LV_L18.WW4END0 01_01 01_08 INT_L.LVB_L0.LV_L0 00_47 01_52 INT_L.LVB_L0.LV_L18 01_42 01_52 +INT_L.LVB_L0.LVB_L12 00_51 00_54 INT_L.LVB_L0.LH0 00_43 00_51 INT_L.LVB_L0.LH6 00_51 00_53 INT_L.LVB_L0.LH12 00_50 00_51 @@ -1675,6 +1682,7 @@ INT_L.LVB_L0.WR1END3 01_42 01_50 INT_L.LVB_L0.WW4END3 00_53 01_50 INT_L.LVB_L12.LV_L0 00_45 01_44 INT_L.LVB_L12.LV_L18 00_45 01_48 +INT_L.LVB_L12.LVB_L0 00_45 01_45 INT_L.LVB_L12.LH0 00_46 00_49 INT_L.LVB_L12.LH6 00_46 01_49 INT_L.LVB_L12.LH12 00_46 01_53 @@ -2082,18 +2090,24 @@ INT_L.GFAN1.GCLK_L_B11_WEST !00_14 !00_18 !00_19 01_13 01_17 INT_L.GFAN1.GND_WIRE !00_14 00_17 !00_18 !00_19 01_13 INT_L.GFAN1.NR1END1 00_14 00_17 !00_18 00_19 01_13 INT_L.GFAN1.WW4END1 00_14 00_17 !00_18 !00_19 !01_13 +INT_L.LH0.LV_L0 01_56 01_58 INT_L.LH0.LV_L9 00_59 01_56 +INT_L.LH0.LV_L18 01_56 01_61 INT_L.LH0.EE4END3 00_58 01_61 INT_L.LH0.ER1END3 00_57 01_54 +INT_L.LH0.LH12 01_54 01_56 INT_L.LH0.NE2END3 00_58 00_59 INT_L.LH0.NE6END3 00_58 01_58 INT_L.LH0.NW2END3 00_58 01_54 INT_L.LH0.SR1END3 00_57 00_59 INT_L.LH0.SS6END3 00_57 01_58 INT_L.LH0.SW6END3 00_57 01_61 +INT_L.LH12.LV_L0 00_55 00_62 INT_L.LH12.LV_L9 00_62 01_57 +INT_L.LH12.LV_L18 00_62 01_62 INT_L.LH12.EE4END3 01_60 01_62 INT_L.LH12.ER1END3 00_63 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17_55 24_55 +INT_L.BYP_ALT7.BYP_BOUNCE2 origin:050-pip-seed !22_63 !23_63 !24_63 21_63 25_63 +INT_L.BYP_ALT7.BYP_BOUNCE6 origin:050-pip-seed !22_63 !23_63 !25_63 21_63 24_63 +INT_L.BYP_ALT7.EE2END3 origin:050-pip-seed !22_63 !23_63 !25_63 17_63 24_63 +INT_L.BYP_ALT7.EL1END_S3_0 origin:050-pip-seed !23_63 17_63 22_63 24_63 25_63 +INT_L.BYP_ALT7.ER1END3 origin:050-pip-seed !22_63 16_63 23_63 24_63 25_63 +INT_L.BYP_ALT7.FAN_BOUNCE_S3_4 origin:050-pip-seed !23_63 21_63 22_63 24_63 25_63 +INT_L.BYP_ALT7.FAN_BOUNCE_S3_6 origin:050-pip-seed !22_63 21_63 23_63 24_63 25_63 +INT_L.BYP_ALT7.GFAN1 origin:054-pip-fan-alt !22_63 !23_63 !25_63 20_63 24_63 +INT_L.BYP_ALT7.LOGIC_OUTS_L15 origin:050-pip-seed,051-pip-imuxlout-bypalts !23_63 20_63 22_63 24_63 25_63 +INT_L.BYP_ALT7.LOGIC_OUTS_L21 origin:050-pip-seed,051-pip-imuxlout-bypalts !22_63 !23_63 !24_63 20_63 25_63 +INT_L.BYP_ALT7.LOGIC_OUTS_L3 origin:051-pip-imuxlout-bypalts !22_63 20_63 23_63 24_63 25_63 +INT_L.BYP_ALT7.NE2END_S3_0 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origin:050-pip-seed 03_48 04_49 +INT_L.WW4BEG3.SS6END2 origin:050-pip-seed 04_49 06_48 +INT_L.WW4BEG3.SW2END2 origin:050-pip-seed 02_49 04_49 +INT_L.WW4BEG3.SW6END2 origin:050-pip-seed 04_49 05_48 +INT_L.WW4BEG3.WW2END2 origin:050-pip-seed 03_48 03_49 +INT_L.WW4BEG3.WW4END3 origin:050-pip-seed 03_49 05_48 diff --git a/zynq7/segbits_int_r.db b/zynq7/segbits_int_r.db index 3705a37..549b5d8 100644 --- a/zynq7/segbits_int_r.db +++ b/zynq7/segbits_int_r.db @@ -2032,7 +2032,10 @@ INT_R.IMUX47.WL1END3 18_63 !22_62 23_62 24_62 25_62 INT_R.IMUX47.WW2END3 16_62 !22_62 !23_62 !24_62 25_62 INT_R.LH0.EE4END3 00_58 01_61 INT_R.LH0.ER1END3 00_57 01_54 +INT_R.LH0.LH12 01_54 01_56 +INT_R.LH0.LV0 01_56 01_58 INT_R.LH0.LV9 00_59 01_56 +INT_R.LH0.LV18 01_56 01_61 INT_R.LH0.NE2END3 00_58 00_59 INT_R.LH0.NE6END3 00_58 01_58 INT_R.LH0.NW2END3 00_58 01_54 @@ -2041,7 +2044,10 @@ INT_R.LH0.SS6END3 00_57 01_58 INT_R.LH0.SW6END3 00_57 01_61 INT_R.LH12.EE4END3 01_60 01_62 INT_R.LH12.ER1END3 00_63 01_60 +INT_R.LH12.LH0 00_61 00_63 +INT_R.LH12.LV0 00_55 00_62 INT_R.LH12.LV9 00_62 01_57 +INT_R.LH12.LV18 00_62 01_62 INT_R.LH12.NE2END3 01_57 01_60 INT_R.LH12.NE6END3 00_55 01_60 INT_R.LH12.NW2END3 00_62 00_63 @@ -2050,7 +2056,10 @@ INT_R.LH12.SS6END3 00_55 00_61 INT_R.LH12.SW6END3 00_61 01_62 INT_R.LV0.SR1BEG_S0 00_05 01_05 INT_R.LV0.ER1END0 01_04 01_05 +INT_R.LV0.LH0 00_02 01_06 INT_R.LV0.LH6 01_04 01_06 +INT_R.LV0.LH12 00_05 01_06 +INT_R.LV0.LV18 00_09 01_06 INT_R.LV0.NN6END0 00_07 00_09 INT_R.LV0.NR1END0 00_02 01_05 INT_R.LV0.NW6END0 00_07 01_04 @@ -2059,7 +2068,10 @@ INT_R.LV0.WR1END0 00_02 00_07 INT_R.LV0.WW4END0 00_05 00_07 INT_R.LV18.SR1BEG_S0 00_03 01_08 INT_R.LV18.ER1END0 00_03 00_06 +INT_R.LV18.LH0 00_01 01_02 INT_R.LV18.LH6 00_06 01_02 +INT_R.LV18.LH12 01_02 01_08 +INT_R.LV18.LV0 01_00 01_01 INT_R.LV18.NN6END0 00_03 01_00 INT_R.LV18.NR1END0 00_01 00_03 INT_R.LV18.NW6END0 00_06 01_01 @@ -2071,6 +2083,7 @@ INT_R.LVB0.LH6 00_51 00_53 INT_R.LVB0.LH12 00_50 00_51 INT_R.LVB0.LV0 00_47 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origin:036-iob-ologic 33_57 +LIOB33.IOB_Y1.OSERDESE.DATA_RATE_TQ.SDR origin:036-iob-ologic 32_58 +LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.2 origin:036-iob-ologic 31_00 +LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.3 origin:036-iob-ologic 30_01 +LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.4 origin:036-iob-ologic 30_03 +LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.5 origin:036-iob-ologic 31_06 +LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.6 origin:036-iob-ologic 30_07 +LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.7 origin:036-iob-ologic 31_04 +LIOB33.IOB_Y1.OSERDESE.DATA_WIDTH.8 origin:036-iob-ologic 30_11 +LIOB33.IOB_Y1.TFF.ZINIT_Q origin:036-iob-ologic 31_52 +LIOB33.IOB_Y1.ZINV_D origin:035-iob-ilogic 28_18 diff --git a/zynq7/segbits_riob33.db b/zynq7/segbits_riob33.db index 955caa1..27f4e9c 100644 --- a/zynq7/segbits_riob33.db +++ b/zynq7/segbits_riob33.db @@ -76,13 +76,13 @@ RIOB33.IOB_Y1.IFF.ZSRVAL_Q1 28_56 RIOB33.IOB_Y1.IFF.ZSRVAL_Q2 28_52 RIOB33.IOB_Y1.IFF.ZSRVAL_Q3 28_42 RIOB33.IOB_Y1.IFF.ZSRVAL_Q4 28_34 -RIOB33.IOB_Y1.IN_ONLY 38_02 38_08 39_09 +RIOB33.IOB_Y1.IN_ONLY 38_02 38_08 38_14 38_40 38_42 39_09 39_41 RIOB33.IOB_Y1.INOUT 31_60 RIOB33.IOB_Y1.INTERMDISABLE.I 38_38 RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12 -RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63 +RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 !38_40 !38_42 38_62 39_01 !39_09 !39_15 !39_41 39_63 RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35 RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35 RIOB33.IOB_Y1.OFF.ZINIT_Q 32_30 @@ -106,23 +106,23 @@ RIOB33.IOB_Y1.TFF.ZINIT_Q 31_52 RIOB33.IOB_Y1.ZINV_D 28_18 RIOB33.IOB_Y1.IDELMUXE3.0 28_26 RIOB33.IOB_Y1.IFFDELMUXE3.0 29_11 -RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 30_41 32_16 33_61 !38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63 -RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63 -RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63 +RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 30_41 32_16 33_61 !38_00 38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 39_09 39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 !39_01 !39_09 39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63 RIOB33.IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN 38_14 !38_40 38_42 39_41 -RIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 30_41 32_16 33_61 38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63 -RIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 !39_09 39_15 39_63 -RIOB33.IOB_Y1.LVCMOS15.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 38_14 38_32 38_62 39_01 39_09 39_15 39_63 -RIOB33.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 !39_01 39_09 39_15 39_63 -RIOB33.IOB_Y1.LVCMOS18.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63 -RIOB33.IOB_Y1.LVCMOS18.DRIVE.I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63 -RIOB33.IOB_Y1.LVCMOS18.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 38_14 38_32 38_62 39_01 !39_09 39_15 39_63 -RIOB33.IOB_Y1.LVCMOS25.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 39_09 39_15 39_63 -RIOB33.IOB_Y1.LVCMOS25.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63 -RIOB33.IOB_Y1.LVCMOS25.DRIVE.I12 30_41 32_16 33_61 !38_00 !38_02 !38_08 !38_10 38_14 !38_32 38_62 !39_01 !39_09 39_15 39_63 -RIOB33.IOB_Y1.LVCMOS25.DRIVE.I16 30_41 32_16 33_61 !38_00 !38_02 !38_08 38_10 38_14 !38_32 38_62 39_01 39_09 39_15 39_63 +RIOB33.IOB_Y1.LVCMOS15.DRIVE.I8 30_41 32_16 33_61 38_00 38_02 38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS15.DRIVE.I12 30_41 32_16 33_61 38_00 !38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 !39_01 !39_09 39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS15.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 39_09 39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS15_LVCMOS18.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 !39_01 39_09 39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS18.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS18.DRIVE.I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS18.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 38_14 38_32 !38_40 !38_42 38_62 39_01 !39_09 39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS25.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 38_14 !38_32 !38_40 !38_42 38_62 !39_01 39_09 39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS25.DRIVE.I8 30_41 32_16 33_61 !38_00 !38_02 38_08 !38_10 38_14 !38_32 !38_40 !38_42 38_62 !39_01 !39_09 39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS25.DRIVE.I12 30_41 32_16 33_61 !38_00 !38_02 !38_08 !38_10 38_14 !38_32 !38_40 !38_42 38_62 !39_01 !39_09 39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS25.DRIVE.I16 30_41 32_16 33_61 !38_00 !38_02 !38_08 38_10 38_14 !38_32 !38_40 !38_42 38_62 39_01 39_09 39_15 !39_41 39_63 RIOB33.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN 38_14 38_40 38_42 39_41 -RIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63 -RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 !39_01 39_09 !39_15 39_63 -RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63 -RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63 +RIOB33.IOB_Y1.LVCMOS33.DRIVE.I16 30_41 32_16 33_61 38_00 !38_02 !38_08 38_10 !38_14 !38_32 !38_40 !38_42 38_62 !39_01 39_09 !39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I4 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 !38_40 !38_42 38_62 !39_01 39_09 !39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I8 30_41 32_16 33_61 !38_00 38_02 38_08 !38_10 !38_14 !38_32 !38_40 !38_42 38_62 39_01 !39_09 !39_15 !39_41 39_63 +RIOB33.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16 30_41 32_16 33_61 38_00 38_02 !38_08 !38_10 !38_14 !38_32 !38_40 !38_42 38_62 39_01 !39_09 !39_15 !39_41 39_63 diff --git a/zynq7/segbits_riob33.origin_info.db b/zynq7/segbits_riob33.origin_info.db new file mode 100644 index 0000000..f0005ba --- /dev/null +++ b/zynq7/segbits_riob33.origin_info.db @@ -0,0 +1,128 @@ +RIOB33.IOB_Y0.IBUFDISABLE.I origin:030-iob 38_82 +RIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101 +RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98 +RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99 +RIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67 +RIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72 +RIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76 +RIOB33.IOB_Y0.IFF.ZINIT_Q3 origin:035-iob-ilogic 28_86 +RIOB33.IOB_Y0.IFF.ZINIT_Q4 origin:035-iob-ilogic 28_94 +RIOB33.IOB_Y0.IFF.ZINV_C origin:035-iob-ilogic 28_126 29_123 29_125 +RIOB33.IOB_Y0.IFF.ZINV_OCLK origin:035-iob-ilogic 28_64 +RIOB33.IOB_Y0.IFF.ZSRVAL_Q1 origin:035-iob-ilogic 29_71 +RIOB33.IOB_Y0.IFF.ZSRVAL_Q2 origin:035-iob-ilogic 29_75 +RIOB33.IOB_Y0.IFF.ZSRVAL_Q3 origin:035-iob-ilogic 29_85 +RIOB33.IOB_Y0.IFF.ZSRVAL_Q4 origin:035-iob-ilogic 29_93 +RIOB33.IOB_Y0.IFFDELMUXE3.0 origin:035-iob-ilogic 28_116 +RIOB33.IOB_Y0.INOUT origin:030-iob 30_67 +RIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89 +RIOB33.IOB_Y0.IN_ONLY origin:030-iob 38_118 39_119 39_125 +RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115 +RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_127 39_65 39_95 +RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_113 39_125 39_65 39_95 +RIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 31_86 32_66 33_111 38_112 38_64 39_113 39_119 39_65 39_95 +RIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN origin:030-iob !39_87 38_86 39_113 39_85 +RIOB33.IOB_Y0.LVCMOS15.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_64 39_113 39_127 39_65 39_95 +RIOB33.IOB_Y0.LVCMOS15.DRIVE.I16 origin:030-iob !39_119 !39_125 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_113 39_117 39_127 39_65 39_95 +RIOB33.IOB_Y0.LVCMOS15.DRIVE.I8 origin:030-iob !38_118 !39_117 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_119 39_125 39_127 39_65 39_95 +RIOB33.IOB_Y0.LVCMOS15_LVCMOS18.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 31_86 32_66 33_111 38_112 38_118 38_64 39_113 39_125 39_127 39_65 39_95 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I12_I8 origin:030-iob !38_118 !39_117 !39_127 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_119 39_125 39_65 39_95 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I16 origin:030-iob !38_118 !39_117 !39_119 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_125 39_127 39_65 39_95 +RIOB33.IOB_Y0.LVCMOS18.DRIVE.I24 origin:030-iob !38_118 !39_125 !39_127 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_117 39_119 39_65 39_95 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I12 origin:030-iob !38_118 !38_126 !39_117 !39_119 !39_125 !39_127 !39_95 31_86 32_66 33_111 38_112 38_64 39_113 39_65 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I16 origin:030-iob !39_119 !39_125 !39_127 !39_95 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_113 39_117 39_65 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I4 origin:030-iob !38_126 !39_117 !39_119 !39_95 31_86 32_66 33_111 38_112 38_118 38_64 39_113 39_125 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS25.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 !39_95 31_86 32_66 33_111 38_112 38_64 39_113 39_119 39_65 +RIOB33.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN origin:030-iob 38_86 39_113 39_85 39_87 +RIOB33.IOB_Y0.LVCMOS33.DRIVE.I16 origin:030-iob !38_112 !38_126 !39_113 !39_119 !39_125 !39_95 31_86 32_66 33_111 38_118 38_64 39_117 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 origin:030-iob !38_112 !38_118 !39_113 !39_117 !39_119 !39_95 31_86 32_66 33_111 38_126 38_64 39_125 39_127 39_65 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 origin:030-iob !38_112 !38_118 !39_113 !39_117 !39_127 !39_95 31_86 32_66 33_111 38_126 38_64 39_119 39_125 39_65 +RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I4 origin:030-iob !38_112 !38_126 !39_113 !39_117 !39_119 !39_95 31_86 32_66 33_111 38_118 38_64 39_125 39_127 39_65 +RIOB33.IOB_Y0.LVTTL.DRIVE.I24 origin:030-iob !38_112 !38_118 !39_113 !39_125 !39_127 !39_95 31_86 32_66 33_111 38_126 38_64 39_117 39_119 39_65 +RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE origin:036-iob-ologic !31_92 +RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92 +RIOB33.IOB_Y0.OFF.ZINIT_Q origin:036-iob-ologic 33_97 +RIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF origin:036-iob-ologic 32_66 +RIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.DDR origin:036-iob-ologic 32_70 +RIOB33.IOB_Y0.OSERDESE.DATA_RATE_TQ.SDR origin:036-iob-ologic 33_69 +RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.2 origin:036-iob-ologic 30_127 +RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.3 origin:036-iob-ologic 31_126 +RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.4 origin:036-iob-ologic 31_124 +RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.5 origin:036-iob-ologic 30_121 +RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.6 origin:036-iob-ologic 31_120 +RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.7 origin:036-iob-ologic 30_123 +RIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.8 origin:036-iob-ologic 31_116 +RIOB33.IOB_Y0.PULLTYPE.KEEPER origin:030-iob !39_93 38_92 38_94 +RIOB33.IOB_Y0.PULLTYPE.NONE origin:030-iob !38_92 !39_93 38_94 +RIOB33.IOB_Y0.PULLTYPE.PULLDOWN origin:030-iob !38_92 !38_94 !39_93 +RIOB33.IOB_Y0.PULLTYPE.PULLUP origin:030-iob !38_92 38_94 39_93 +RIOB33.IOB_Y0.SLEW.FAST origin:030-iob !38_106 !38_110 !39_105 !39_109 +RIOB33.IOB_Y0.SLEW.SLOW origin:030-iob 38_106 38_110 39_105 39_109 +RIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75 +RIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109 +RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45 +RIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26 +RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29 +RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28 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"INT_INTERFACE_NW4END1", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_PHASER_TO_IO_ICLK", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", - "INT_INTERFACE_PHASER_TO_IO_OCLK", - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WL1END3", - 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"INT_INTERFACE_WW2END2": null, + "INT_INTERFACE_WW2END3": null, + "INT_INTERFACE_WW4A0": null, + "INT_INTERFACE_WW4A1": null, + "INT_INTERFACE_WW4A2": null, + "INT_INTERFACE_WW4A3": null, + "INT_INTERFACE_WW4B0": null, + "INT_INTERFACE_WW4B1": null, + "INT_INTERFACE_WW4B2": null, + "INT_INTERFACE_WW4B3": null, + "INT_INTERFACE_WW4C0": null, + "INT_INTERFACE_WW4C1": null, + "INT_INTERFACE_WW4C2": null, + "INT_INTERFACE_WW4C3": null, + "INT_INTERFACE_WW4END0": null, + "INT_INTERFACE_WW4END1": null, + "INT_INTERFACE_WW4END2": null, + "INT_INTERFACE_WW4END3": null, + "L_INT_INTER_DQS_IOTOPHASER": null + } } diff --git a/zynq7/tile_type_BRAM_INT_INTERFACE_R.json b/zynq7/tile_type_BRAM_INT_INTERFACE_R.json index 6def0d9..bd39be9 100644 --- a/zynq7/tile_type_BRAM_INT_INTERFACE_R.json +++ b/zynq7/tile_type_BRAM_INT_INTERFACE_R.json @@ -2,475 +2,979 @@ "pips": { "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + 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"INT_INTERFACE_BRAM_IMUX8", - "INT_INTERFACE_BRAM_IMUX9", - "INT_INTERFACE_BRAM_UTURN_R_IMUX0", - "INT_INTERFACE_BRAM_UTURN_R_IMUX1", - "INT_INTERFACE_BRAM_UTURN_R_IMUX10", - "INT_INTERFACE_BRAM_UTURN_R_IMUX11", - "INT_INTERFACE_BRAM_UTURN_R_IMUX12", - "INT_INTERFACE_BRAM_UTURN_R_IMUX13", - "INT_INTERFACE_BRAM_UTURN_R_IMUX14", - "INT_INTERFACE_BRAM_UTURN_R_IMUX15", - "INT_INTERFACE_BRAM_UTURN_R_IMUX16", - "INT_INTERFACE_BRAM_UTURN_R_IMUX17", - "INT_INTERFACE_BRAM_UTURN_R_IMUX18", - "INT_INTERFACE_BRAM_UTURN_R_IMUX19", - "INT_INTERFACE_BRAM_UTURN_R_IMUX2", - "INT_INTERFACE_BRAM_UTURN_R_IMUX20", - "INT_INTERFACE_BRAM_UTURN_R_IMUX21", - "INT_INTERFACE_BRAM_UTURN_R_IMUX22", - "INT_INTERFACE_BRAM_UTURN_R_IMUX23", - "INT_INTERFACE_BRAM_UTURN_R_IMUX24", - "INT_INTERFACE_BRAM_UTURN_R_IMUX25", - "INT_INTERFACE_BRAM_UTURN_R_IMUX26", - "INT_INTERFACE_BRAM_UTURN_R_IMUX27", - "INT_INTERFACE_BRAM_UTURN_R_IMUX28", - "INT_INTERFACE_BRAM_UTURN_R_IMUX29", - "INT_INTERFACE_BRAM_UTURN_R_IMUX3", - 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"INT_INTERFACE_ER1BEG2", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_FAN0", - "INT_INTERFACE_FAN1", - "INT_INTERFACE_FAN2", - "INT_INTERFACE_FAN3", - "INT_INTERFACE_FAN4", - "INT_INTERFACE_FAN5", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_FAN7", - "INT_INTERFACE_LH1", - "INT_INTERFACE_LH10", - "INT_INTERFACE_LH11", - "INT_INTERFACE_LH12", - "INT_INTERFACE_LH2", - "INT_INTERFACE_LH3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_LH5", - "INT_INTERFACE_LH6", - "INT_INTERFACE_LH7", - "INT_INTERFACE_LH8", - "INT_INTERFACE_LH9", - "INT_INTERFACE_LOGIC_OUTS0", - "INT_INTERFACE_LOGIC_OUTS1", - "INT_INTERFACE_LOGIC_OUTS10", - "INT_INTERFACE_LOGIC_OUTS11", - "INT_INTERFACE_LOGIC_OUTS12", - "INT_INTERFACE_LOGIC_OUTS13", - "INT_INTERFACE_LOGIC_OUTS14", - "INT_INTERFACE_LOGIC_OUTS15", - "INT_INTERFACE_LOGIC_OUTS16", - "INT_INTERFACE_LOGIC_OUTS17", - "INT_INTERFACE_LOGIC_OUTS18", - "INT_INTERFACE_LOGIC_OUTS19", - "INT_INTERFACE_LOGIC_OUTS2", - "INT_INTERFACE_LOGIC_OUTS20", - "INT_INTERFACE_LOGIC_OUTS21", - "INT_INTERFACE_LOGIC_OUTS22", - "INT_INTERFACE_LOGIC_OUTS23", - "INT_INTERFACE_LOGIC_OUTS3", - "INT_INTERFACE_LOGIC_OUTS4", - "INT_INTERFACE_LOGIC_OUTS5", - "INT_INTERFACE_LOGIC_OUTS6", - "INT_INTERFACE_LOGIC_OUTS7", - "INT_INTERFACE_LOGIC_OUTS8", - "INT_INTERFACE_LOGIC_OUTS9", - "INT_INTERFACE_LOGIC_OUTS_B0", - "INT_INTERFACE_LOGIC_OUTS_B1", - "INT_INTERFACE_LOGIC_OUTS_B10", - "INT_INTERFACE_LOGIC_OUTS_B11", - "INT_INTERFACE_LOGIC_OUTS_B12", - "INT_INTERFACE_LOGIC_OUTS_B13", - "INT_INTERFACE_LOGIC_OUTS_B14", - "INT_INTERFACE_LOGIC_OUTS_B15", - "INT_INTERFACE_LOGIC_OUTS_B16", - "INT_INTERFACE_LOGIC_OUTS_B17", - "INT_INTERFACE_LOGIC_OUTS_B18", - "INT_INTERFACE_LOGIC_OUTS_B19", - "INT_INTERFACE_LOGIC_OUTS_B2", - "INT_INTERFACE_LOGIC_OUTS_B20", - "INT_INTERFACE_LOGIC_OUTS_B21", - "INT_INTERFACE_LOGIC_OUTS_B22", - "INT_INTERFACE_LOGIC_OUTS_B23", - "INT_INTERFACE_LOGIC_OUTS_B3", - "INT_INTERFACE_LOGIC_OUTS_B4", - "INT_INTERFACE_LOGIC_OUTS_B5", - "INT_INTERFACE_LOGIC_OUTS_B6", - "INT_INTERFACE_LOGIC_OUTS_B7", - "INT_INTERFACE_LOGIC_OUTS_B8", - "INT_INTERFACE_LOGIC_OUTS_B9", - "INT_INTERFACE_MONITOR_N", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_NE2A1", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_NE4BEG2", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_NE4C1", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_NW4A1", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_PHASER_TO_IO_ICLK", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", - "INT_INTERFACE_PHASER_TO_IO_OCLK", - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_WW4A0", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_WW4END3", - "L_INT_INTER_DQS_IOTOPHASER" - ] + "wires": { + "INT_INTERFACE_BLOCK_OUTS_B0": null, + "INT_INTERFACE_BLOCK_OUTS_B1": null, + "INT_INTERFACE_BLOCK_OUTS_B2": null, + "INT_INTERFACE_BLOCK_OUTS_B3": null, + "INT_INTERFACE_BRAM_IMUX0": null, + "INT_INTERFACE_BRAM_IMUX1": null, + "INT_INTERFACE_BRAM_IMUX10": null, + "INT_INTERFACE_BRAM_IMUX11": null, + "INT_INTERFACE_BRAM_IMUX12": null, + "INT_INTERFACE_BRAM_IMUX13": null, + "INT_INTERFACE_BRAM_IMUX14": null, + "INT_INTERFACE_BRAM_IMUX15": null, + "INT_INTERFACE_BRAM_IMUX16": null, + "INT_INTERFACE_BRAM_IMUX17": null, + "INT_INTERFACE_BRAM_IMUX18": null, + "INT_INTERFACE_BRAM_IMUX19": null, + "INT_INTERFACE_BRAM_IMUX2": null, + "INT_INTERFACE_BRAM_IMUX20": null, + "INT_INTERFACE_BRAM_IMUX21": null, + "INT_INTERFACE_BRAM_IMUX22": null, + "INT_INTERFACE_BRAM_IMUX23": null, + "INT_INTERFACE_BRAM_IMUX24": null, + "INT_INTERFACE_BRAM_IMUX25": null, + "INT_INTERFACE_BRAM_IMUX26": null, + "INT_INTERFACE_BRAM_IMUX27": null, + "INT_INTERFACE_BRAM_IMUX28": null, + "INT_INTERFACE_BRAM_IMUX29": null, + "INT_INTERFACE_BRAM_IMUX3": null, + "INT_INTERFACE_BRAM_IMUX30": null, + "INT_INTERFACE_BRAM_IMUX31": null, + "INT_INTERFACE_BRAM_IMUX32": null, + "INT_INTERFACE_BRAM_IMUX33": null, + "INT_INTERFACE_BRAM_IMUX34": null, + "INT_INTERFACE_BRAM_IMUX35": null, + "INT_INTERFACE_BRAM_IMUX36": null, + "INT_INTERFACE_BRAM_IMUX37": null, + "INT_INTERFACE_BRAM_IMUX38": null, + "INT_INTERFACE_BRAM_IMUX39": null, + "INT_INTERFACE_BRAM_IMUX4": null, + "INT_INTERFACE_BRAM_IMUX40": null, + "INT_INTERFACE_BRAM_IMUX41": null, + "INT_INTERFACE_BRAM_IMUX42": null, + "INT_INTERFACE_BRAM_IMUX43": null, + "INT_INTERFACE_BRAM_IMUX44": null, + "INT_INTERFACE_BRAM_IMUX45": null, + "INT_INTERFACE_BRAM_IMUX46": null, + "INT_INTERFACE_BRAM_IMUX47": null, + "INT_INTERFACE_BRAM_IMUX5": null, + "INT_INTERFACE_BRAM_IMUX6": null, + "INT_INTERFACE_BRAM_IMUX7": null, + "INT_INTERFACE_BRAM_IMUX8": null, + "INT_INTERFACE_BRAM_IMUX9": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX0": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX1": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX10": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX11": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX12": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX13": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX14": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX15": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX16": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX17": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX18": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX19": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX2": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX20": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX21": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX22": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX23": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX24": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX25": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX26": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX27": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX28": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX29": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX3": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX30": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX31": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX32": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX33": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX34": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX35": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX36": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX37": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX38": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX39": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX4": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX40": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX41": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX42": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX43": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX44": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX45": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX46": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX47": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX5": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX6": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX7": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX8": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX9": null, + "INT_INTERFACE_BYP0": null, + "INT_INTERFACE_BYP1": null, + "INT_INTERFACE_BYP2": null, + "INT_INTERFACE_BYP3": null, + "INT_INTERFACE_BYP4": null, + "INT_INTERFACE_BYP5": null, + "INT_INTERFACE_BYP6": null, + "INT_INTERFACE_BYP7": null, + "INT_INTERFACE_CLK0": null, + "INT_INTERFACE_CLK1": null, + "INT_INTERFACE_CTRL0": null, + "INT_INTERFACE_CTRL1": null, + "INT_INTERFACE_EE2A0": null, + "INT_INTERFACE_EE2A1": null, + "INT_INTERFACE_EE2A2": null, + "INT_INTERFACE_EE2A3": null, + "INT_INTERFACE_EE2BEG0": null, + "INT_INTERFACE_EE2BEG1": null, + "INT_INTERFACE_EE2BEG2": null, + "INT_INTERFACE_EE2BEG3": null, + "INT_INTERFACE_EE4A0": null, + "INT_INTERFACE_EE4A1": null, + "INT_INTERFACE_EE4A2": null, + "INT_INTERFACE_EE4A3": null, + "INT_INTERFACE_EE4B0": null, + "INT_INTERFACE_EE4B1": null, + "INT_INTERFACE_EE4B2": null, + "INT_INTERFACE_EE4B3": null, + "INT_INTERFACE_EE4BEG0": null, + "INT_INTERFACE_EE4BEG1": null, + "INT_INTERFACE_EE4BEG2": null, + "INT_INTERFACE_EE4BEG3": null, + "INT_INTERFACE_EE4C0": null, + "INT_INTERFACE_EE4C1": null, + "INT_INTERFACE_EE4C2": null, + "INT_INTERFACE_EE4C3": null, + "INT_INTERFACE_EL1BEG0": null, + "INT_INTERFACE_EL1BEG1": null, + "INT_INTERFACE_EL1BEG2": null, + "INT_INTERFACE_EL1BEG3": null, + "INT_INTERFACE_ER1BEG0": null, + "INT_INTERFACE_ER1BEG1": null, + "INT_INTERFACE_ER1BEG2": null, + "INT_INTERFACE_ER1BEG3": null, + "INT_INTERFACE_FAN0": null, + "INT_INTERFACE_FAN1": null, + "INT_INTERFACE_FAN2": null, + "INT_INTERFACE_FAN3": null, + "INT_INTERFACE_FAN4": null, + "INT_INTERFACE_FAN5": null, + "INT_INTERFACE_FAN6": null, + "INT_INTERFACE_FAN7": null, + "INT_INTERFACE_LH1": null, + "INT_INTERFACE_LH10": null, + "INT_INTERFACE_LH11": null, + "INT_INTERFACE_LH12": null, + "INT_INTERFACE_LH2": null, + "INT_INTERFACE_LH3": null, + "INT_INTERFACE_LH4": null, + "INT_INTERFACE_LH5": null, + "INT_INTERFACE_LH6": null, + "INT_INTERFACE_LH7": null, + "INT_INTERFACE_LH8": null, + "INT_INTERFACE_LH9": null, + "INT_INTERFACE_LOGIC_OUTS0": null, + "INT_INTERFACE_LOGIC_OUTS1": null, + "INT_INTERFACE_LOGIC_OUTS10": null, + "INT_INTERFACE_LOGIC_OUTS11": null, + "INT_INTERFACE_LOGIC_OUTS12": null, + "INT_INTERFACE_LOGIC_OUTS13": null, + "INT_INTERFACE_LOGIC_OUTS14": null, + "INT_INTERFACE_LOGIC_OUTS15": null, + "INT_INTERFACE_LOGIC_OUTS16": null, + "INT_INTERFACE_LOGIC_OUTS17": null, + "INT_INTERFACE_LOGIC_OUTS18": null, + "INT_INTERFACE_LOGIC_OUTS19": null, + "INT_INTERFACE_LOGIC_OUTS2": null, + "INT_INTERFACE_LOGIC_OUTS20": null, + "INT_INTERFACE_LOGIC_OUTS21": null, + "INT_INTERFACE_LOGIC_OUTS22": null, + "INT_INTERFACE_LOGIC_OUTS23": null, + "INT_INTERFACE_LOGIC_OUTS3": null, + "INT_INTERFACE_LOGIC_OUTS4": null, + "INT_INTERFACE_LOGIC_OUTS5": null, + "INT_INTERFACE_LOGIC_OUTS6": null, + "INT_INTERFACE_LOGIC_OUTS7": null, + "INT_INTERFACE_LOGIC_OUTS8": null, + "INT_INTERFACE_LOGIC_OUTS9": null, + "INT_INTERFACE_LOGIC_OUTS_B0": null, + "INT_INTERFACE_LOGIC_OUTS_B1": null, + "INT_INTERFACE_LOGIC_OUTS_B10": null, + "INT_INTERFACE_LOGIC_OUTS_B11": null, + "INT_INTERFACE_LOGIC_OUTS_B12": null, + "INT_INTERFACE_LOGIC_OUTS_B13": null, + "INT_INTERFACE_LOGIC_OUTS_B14": null, + "INT_INTERFACE_LOGIC_OUTS_B15": null, + "INT_INTERFACE_LOGIC_OUTS_B16": null, + "INT_INTERFACE_LOGIC_OUTS_B17": null, + "INT_INTERFACE_LOGIC_OUTS_B18": null, + "INT_INTERFACE_LOGIC_OUTS_B19": null, + "INT_INTERFACE_LOGIC_OUTS_B2": null, + "INT_INTERFACE_LOGIC_OUTS_B20": null, + "INT_INTERFACE_LOGIC_OUTS_B21": null, + "INT_INTERFACE_LOGIC_OUTS_B22": null, + "INT_INTERFACE_LOGIC_OUTS_B23": null, + "INT_INTERFACE_LOGIC_OUTS_B3": null, + "INT_INTERFACE_LOGIC_OUTS_B4": null, + "INT_INTERFACE_LOGIC_OUTS_B5": null, + "INT_INTERFACE_LOGIC_OUTS_B6": null, + "INT_INTERFACE_LOGIC_OUTS_B7": null, + "INT_INTERFACE_LOGIC_OUTS_B8": null, + "INT_INTERFACE_LOGIC_OUTS_B9": null, + "INT_INTERFACE_MONITOR_N": null, + "INT_INTERFACE_MONITOR_P": null, + "INT_INTERFACE_NE2A0": null, + "INT_INTERFACE_NE2A1": null, + "INT_INTERFACE_NE2A2": null, + "INT_INTERFACE_NE2A3": null, + "INT_INTERFACE_NE4BEG0": null, + "INT_INTERFACE_NE4BEG1": null, + "INT_INTERFACE_NE4BEG2": null, + "INT_INTERFACE_NE4BEG3": null, + "INT_INTERFACE_NE4C0": null, + "INT_INTERFACE_NE4C1": null, + "INT_INTERFACE_NE4C2": null, + "INT_INTERFACE_NE4C3": null, + "INT_INTERFACE_NW2A0": null, + "INT_INTERFACE_NW2A1": null, + "INT_INTERFACE_NW2A2": null, + "INT_INTERFACE_NW2A3": null, + "INT_INTERFACE_NW4A0": null, + "INT_INTERFACE_NW4A1": null, + "INT_INTERFACE_NW4A2": null, + "INT_INTERFACE_NW4A3": null, + "INT_INTERFACE_NW4END0": null, + "INT_INTERFACE_NW4END1": null, + "INT_INTERFACE_NW4END2": null, + "INT_INTERFACE_NW4END3": null, + "INT_INTERFACE_PHASER_TO_IO_ICLK": null, + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90": null, + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV": null, + "INT_INTERFACE_SE2A0": null, + "INT_INTERFACE_SE2A1": null, + "INT_INTERFACE_SE2A2": null, + "INT_INTERFACE_SE2A3": null, + "INT_INTERFACE_SE4BEG0": null, + "INT_INTERFACE_SE4BEG1": null, + "INT_INTERFACE_SE4BEG2": null, + "INT_INTERFACE_SE4BEG3": null, + "INT_INTERFACE_SE4C0": null, + "INT_INTERFACE_SE4C1": null, + "INT_INTERFACE_SE4C2": null, + "INT_INTERFACE_SE4C3": null, + "INT_INTERFACE_SW2A0": null, + "INT_INTERFACE_SW2A1": null, + "INT_INTERFACE_SW2A2": null, + "INT_INTERFACE_SW2A3": null, + "INT_INTERFACE_SW4A0": null, + "INT_INTERFACE_SW4A1": null, + "INT_INTERFACE_SW4A2": null, + "INT_INTERFACE_SW4A3": null, + "INT_INTERFACE_SW4END0": null, + "INT_INTERFACE_SW4END1": null, + "INT_INTERFACE_SW4END2": null, + "INT_INTERFACE_SW4END3": null, + "INT_INTERFACE_WL1END0": null, + "INT_INTERFACE_WL1END1": null, + "INT_INTERFACE_WL1END2": null, + "INT_INTERFACE_WL1END3": null, + "INT_INTERFACE_WR1END0": null, + "INT_INTERFACE_WR1END1": null, + "INT_INTERFACE_WR1END2": null, + "INT_INTERFACE_WR1END3": null, + "INT_INTERFACE_WW2A0": null, + "INT_INTERFACE_WW2A1": null, + "INT_INTERFACE_WW2A2": null, + "INT_INTERFACE_WW2A3": null, + "INT_INTERFACE_WW2END0": null, + "INT_INTERFACE_WW2END1": null, + "INT_INTERFACE_WW2END2": null, + "INT_INTERFACE_WW2END3": null, + "INT_INTERFACE_WW4A0": null, + "INT_INTERFACE_WW4A1": null, + "INT_INTERFACE_WW4A2": null, + "INT_INTERFACE_WW4A3": null, + "INT_INTERFACE_WW4B0": null, + "INT_INTERFACE_WW4B1": null, + "INT_INTERFACE_WW4B2": null, + "INT_INTERFACE_WW4B3": null, + "INT_INTERFACE_WW4C0": null, + "INT_INTERFACE_WW4C1": null, + "INT_INTERFACE_WW4C2": null, + "INT_INTERFACE_WW4C3": null, + "INT_INTERFACE_WW4END0": null, + "INT_INTERFACE_WW4END1": null, + "INT_INTERFACE_WW4END2": null, + "INT_INTERFACE_WW4END3": null, + "L_INT_INTER_DQS_IOTOPHASER": null + } } diff --git a/zynq7/tile_type_BRAM_L.json b/zynq7/tile_type_BRAM_L.json index 35370eb..9e1feae 100644 --- a/zynq7/tile_type_BRAM_L.json +++ b/zynq7/tile_type_BRAM_L.json @@ -2,6820 +2,19714 @@ "pips": { "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_FIFO18_ADDRATIEHIGH0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_ADDRARDADDRL0" }, "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_FIFO36_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_ADDRARDADDRL0" }, "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_UTURN_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_ADDRARDADDRL0" }, "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_FIFO18_ADDRARDADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_FIFO18_ADDRARDADDR0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_ADDRARDADDRL1" }, "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_FIFO36_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_ADDRARDADDRL1" }, "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_UTURN_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", 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"is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9" }, "BRAM_L.BRAM_CLK0_0->BRAM_FIFO18_REGCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_0" }, "BRAM_L.BRAM_CLK0_0->BRAM_FIFO36_REGCLKBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_0" }, "BRAM_L.BRAM_CLK0_1->BRAM_FIFO18_CLKBWRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_CLKBWRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_1" }, "BRAM_L.BRAM_CLK0_1->BRAM_FIFO36_CLKBWRCLKL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKBWRCLKL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_1" }, "BRAM_L.BRAM_CLK0_3->BRAM_FIFO18_CLKARDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_CLKARDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_3" }, "BRAM_L.BRAM_CLK0_3->BRAM_FIFO36_CLKARDCLKL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKARDCLKL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_3" }, "BRAM_L.BRAM_CLK0_4->BRAM_FIFO18_REGCLKARDRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCLKARDRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_4" }, "BRAM_L.BRAM_CLK0_4->BRAM_FIFO36_REGCLKARDRCLKL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_4" }, "BRAM_L.BRAM_CLK1_0->BRAM_FIFO36_REGCLKBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_0" }, "BRAM_L.BRAM_CLK1_0->BRAM_RAMB18_REGCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_0" }, "BRAM_L.BRAM_CLK1_1->BRAM_FIFO36_CLKBWRCLKU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKBWRCLKU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_1" }, "BRAM_L.BRAM_CLK1_1->BRAM_RAMB18_CLKBWRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_CLKBWRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_1" }, "BRAM_L.BRAM_CLK1_3->BRAM_FIFO36_CLKARDCLKU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKARDCLKU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_3" }, "BRAM_L.BRAM_CLK1_3->BRAM_RAMB18_CLKARDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_CLKARDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_3" }, "BRAM_L.BRAM_CLK1_4->BRAM_FIFO36_REGCLKARDRCLKU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_4" }, "BRAM_L.BRAM_CLK1_4->BRAM_RAMB18_REGCLKARDRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCLKARDRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_4" }, "BRAM_L.BRAM_CTRL0_0->BRAM_FIFO18_RSTREGB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTREGB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_0" }, "BRAM_L.BRAM_CTRL0_0->BRAM_FIFO36_RSTREGBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_0" }, "BRAM_L.BRAM_CTRL0_1->BRAM_FIFO18_RSTRAMB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTRAMB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_1" }, "BRAM_L.BRAM_CTRL0_1->BRAM_FIFO36_RSTRAMBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_1" }, "BRAM_L.BRAM_CTRL0_3->BRAM_FIFO18_RSTRAMARSTRAM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTRAMARSTRAM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_3" }, "BRAM_L.BRAM_CTRL0_3->BRAM_FIFO36_RSTRAMARSTRAMLRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMLRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_3" }, "BRAM_L.BRAM_CTRL0_4->BRAM_FIFO18_RSTREGARSTREG": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTREGARSTREG", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_4" }, "BRAM_L.BRAM_CTRL0_4->BRAM_FIFO36_RSTREGARSTREGL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGARSTREGL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_4" }, "BRAM_L.BRAM_CTRL1_0->BRAM_FIFO36_RSTREGBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_0" }, "BRAM_L.BRAM_CTRL1_0->BRAM_RAMB18_RSTREGB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTREGB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_0" }, "BRAM_L.BRAM_CTRL1_1->BRAM_FIFO36_RSTRAMBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_1" }, "BRAM_L.BRAM_CTRL1_1->BRAM_RAMB18_RSTRAMB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTRAMB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_1" }, "BRAM_L.BRAM_CTRL1_3->BRAM_FIFO36_RSTRAMARSTRAMU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_3" }, "BRAM_L.BRAM_CTRL1_3->BRAM_RAMB18_RSTRAMARSTRAM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTRAMARSTRAM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_3" }, "BRAM_L.BRAM_CTRL1_4->BRAM_FIFO36_RSTREGARSTREGU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGARSTREGU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_4" }, "BRAM_L.BRAM_CTRL1_4->BRAM_RAMB18_RSTREGARSTREG": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTREGARSTREG", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_4" }, "BRAM_L.BRAM_FAN1_2->BRAM_FIFO36_WEBWEU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN1_2" }, "BRAM_L.BRAM_FAN1_2->BRAM_RAMB18_WEBWE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN1_2" }, "BRAM_L.BRAM_FAN5_2->BRAM_FIFO36_WEBWEU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN5_2" }, "BRAM_L.BRAM_FAN5_2->BRAM_RAMB18_WEBWE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN5_2" }, "BRAM_L.BRAM_FIFO18_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_ALMOSTEMPTY" }, "BRAM_L.BRAM_FIFO18_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_ALMOSTFULL" }, "BRAM_L.BRAM_FIFO18_DOADO0->BRAM_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO0" }, "BRAM_L.BRAM_FIFO18_DOADO1->BRAM_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO1" }, "BRAM_L.BRAM_FIFO18_DOADO10->BRAM_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO10" }, "BRAM_L.BRAM_FIFO18_DOADO11->BRAM_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO11" }, "BRAM_L.BRAM_FIFO18_DOADO12->BRAM_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO12" }, "BRAM_L.BRAM_FIFO18_DOADO13->BRAM_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO13" }, "BRAM_L.BRAM_FIFO18_DOADO14->BRAM_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO14" }, "BRAM_L.BRAM_FIFO18_DOADO15->BRAM_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO15" }, "BRAM_L.BRAM_FIFO18_DOADO2->BRAM_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO2" }, "BRAM_L.BRAM_FIFO18_DOADO3->BRAM_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO3" }, "BRAM_L.BRAM_FIFO18_DOADO4->BRAM_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO4" }, "BRAM_L.BRAM_FIFO18_DOADO5->BRAM_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO5" }, "BRAM_L.BRAM_FIFO18_DOADO6->BRAM_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO6" }, "BRAM_L.BRAM_FIFO18_DOADO7->BRAM_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO7" }, "BRAM_L.BRAM_FIFO18_DOADO8->BRAM_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO8" }, "BRAM_L.BRAM_FIFO18_DOADO9->BRAM_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO9" }, "BRAM_L.BRAM_FIFO18_DOBDO0->BRAM_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO0" }, "BRAM_L.BRAM_FIFO18_DOBDO1->BRAM_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO1" }, "BRAM_L.BRAM_FIFO18_DOBDO10->BRAM_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO10" }, "BRAM_L.BRAM_FIFO18_DOBDO11->BRAM_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO11" }, "BRAM_L.BRAM_FIFO18_DOBDO12->BRAM_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO12" }, "BRAM_L.BRAM_FIFO18_DOBDO13->BRAM_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO13" }, "BRAM_L.BRAM_FIFO18_DOBDO14->BRAM_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO14" }, "BRAM_L.BRAM_FIFO18_DOBDO15->BRAM_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO15" }, "BRAM_L.BRAM_FIFO18_DOBDO2->BRAM_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO2" }, "BRAM_L.BRAM_FIFO18_DOBDO3->BRAM_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO3" }, "BRAM_L.BRAM_FIFO18_DOBDO4->BRAM_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO4" }, "BRAM_L.BRAM_FIFO18_DOBDO5->BRAM_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO5" }, "BRAM_L.BRAM_FIFO18_DOBDO6->BRAM_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO6" }, "BRAM_L.BRAM_FIFO18_DOBDO7->BRAM_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO7" }, "BRAM_L.BRAM_FIFO18_DOBDO8->BRAM_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO8" }, "BRAM_L.BRAM_FIFO18_DOBDO9->BRAM_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO9" }, "BRAM_L.BRAM_FIFO18_DOPADOP0->BRAM_LOGIC_OUTS_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPADOP0" }, "BRAM_L.BRAM_FIFO18_DOPADOP1->BRAM_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPADOP1" }, "BRAM_L.BRAM_FIFO18_DOPBDOP0->BRAM_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPBDOP0" }, "BRAM_L.BRAM_FIFO18_DOPBDOP1->BRAM_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPBDOP1" }, "BRAM_L.BRAM_FIFO18_EMPTY->BRAM_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_EMPTY" }, "BRAM_L.BRAM_FIFO18_FULL->BRAM_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_FULL" }, "BRAM_L.BRAM_FIFO18_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT0" }, "BRAM_L.BRAM_FIFO18_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT1" }, "BRAM_L.BRAM_FIFO18_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT10" }, "BRAM_L.BRAM_FIFO18_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT11" }, "BRAM_L.BRAM_FIFO18_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT2" }, "BRAM_L.BRAM_FIFO18_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT3" }, "BRAM_L.BRAM_FIFO18_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT4" }, "BRAM_L.BRAM_FIFO18_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT5" }, "BRAM_L.BRAM_FIFO18_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT6" }, "BRAM_L.BRAM_FIFO18_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT7" }, "BRAM_L.BRAM_FIFO18_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT8" }, "BRAM_L.BRAM_FIFO18_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT9" }, "BRAM_L.BRAM_FIFO18_RDERR->BRAM_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDERR" }, "BRAM_L.BRAM_FIFO18_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT0" }, "BRAM_L.BRAM_FIFO18_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT1" }, "BRAM_L.BRAM_FIFO18_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT10" }, "BRAM_L.BRAM_FIFO18_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT11" }, "BRAM_L.BRAM_FIFO18_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT2" }, "BRAM_L.BRAM_FIFO18_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT3" }, "BRAM_L.BRAM_FIFO18_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT4" }, "BRAM_L.BRAM_FIFO18_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT5" }, "BRAM_L.BRAM_FIFO18_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT6" }, "BRAM_L.BRAM_FIFO18_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT7" }, "BRAM_L.BRAM_FIFO18_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT8" }, "BRAM_L.BRAM_FIFO18_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT9" }, "BRAM_L.BRAM_FIFO18_WRERR->BRAM_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRERR" }, "BRAM_L.BRAM_FIFO36_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ALMOSTEMPTY" }, "BRAM_L.BRAM_FIFO36_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ALMOSTFULL" }, "BRAM_L.BRAM_FIFO36_CASCADEOUTA->BRAM_FIFO36_CASCADEOUTA_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CASCADEOUTA_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_CASCADEOUTA" }, "BRAM_L.BRAM_FIFO36_CASCADEOUTB->BRAM_FIFO36_CASCADEOUTB_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CASCADEOUTB_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_CASCADEOUTB" }, "BRAM_L.BRAM_FIFO36_DBITERR->BRAM_LOGIC_OUTS_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DBITERR" }, "BRAM_L.BRAM_FIFO36_DOADOL0->BRAM_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL0" }, "BRAM_L.BRAM_FIFO36_DOADOL1->BRAM_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL1" }, "BRAM_L.BRAM_FIFO36_DOADOL10->BRAM_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL10" }, "BRAM_L.BRAM_FIFO36_DOADOL11->BRAM_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL11" }, "BRAM_L.BRAM_FIFO36_DOADOL12->BRAM_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL12" }, "BRAM_L.BRAM_FIFO36_DOADOL13->BRAM_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL13" }, "BRAM_L.BRAM_FIFO36_DOADOL14->BRAM_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL14" }, "BRAM_L.BRAM_FIFO36_DOADOL15->BRAM_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL15" }, "BRAM_L.BRAM_FIFO36_DOADOL2->BRAM_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL2" }, "BRAM_L.BRAM_FIFO36_DOADOL3->BRAM_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL3" }, "BRAM_L.BRAM_FIFO36_DOADOL4->BRAM_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL4" }, "BRAM_L.BRAM_FIFO36_DOADOL5->BRAM_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL5" }, "BRAM_L.BRAM_FIFO36_DOADOL6->BRAM_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL6" }, "BRAM_L.BRAM_FIFO36_DOADOL7->BRAM_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL7" }, "BRAM_L.BRAM_FIFO36_DOADOL8->BRAM_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL8" }, "BRAM_L.BRAM_FIFO36_DOADOL9->BRAM_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL9" }, "BRAM_L.BRAM_FIFO36_DOADOU0->BRAM_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU0" }, "BRAM_L.BRAM_FIFO36_DOADOU1->BRAM_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU1" }, "BRAM_L.BRAM_FIFO36_DOADOU10->BRAM_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU10" }, "BRAM_L.BRAM_FIFO36_DOADOU11->BRAM_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU11" }, "BRAM_L.BRAM_FIFO36_DOADOU12->BRAM_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU12" }, "BRAM_L.BRAM_FIFO36_DOADOU13->BRAM_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU13" }, "BRAM_L.BRAM_FIFO36_DOADOU14->BRAM_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU14" }, "BRAM_L.BRAM_FIFO36_DOADOU15->BRAM_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU15" }, "BRAM_L.BRAM_FIFO36_DOADOU2->BRAM_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU2" }, "BRAM_L.BRAM_FIFO36_DOADOU3->BRAM_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU3" }, "BRAM_L.BRAM_FIFO36_DOADOU4->BRAM_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU4" }, "BRAM_L.BRAM_FIFO36_DOADOU5->BRAM_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU5" }, "BRAM_L.BRAM_FIFO36_DOADOU6->BRAM_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU6" }, "BRAM_L.BRAM_FIFO36_DOADOU7->BRAM_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU7" }, "BRAM_L.BRAM_FIFO36_DOADOU8->BRAM_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU8" }, "BRAM_L.BRAM_FIFO36_DOADOU9->BRAM_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU9" }, "BRAM_L.BRAM_FIFO36_DOBDOL0->BRAM_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL0" }, "BRAM_L.BRAM_FIFO36_DOBDOL1->BRAM_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL1" }, "BRAM_L.BRAM_FIFO36_DOBDOL10->BRAM_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL10" }, "BRAM_L.BRAM_FIFO36_DOBDOL11->BRAM_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL11" }, "BRAM_L.BRAM_FIFO36_DOBDOL12->BRAM_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL12" }, "BRAM_L.BRAM_FIFO36_DOBDOL13->BRAM_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL13" }, "BRAM_L.BRAM_FIFO36_DOBDOL14->BRAM_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL14" }, "BRAM_L.BRAM_FIFO36_DOBDOL15->BRAM_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL15" }, "BRAM_L.BRAM_FIFO36_DOBDOL2->BRAM_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL2" }, "BRAM_L.BRAM_FIFO36_DOBDOL3->BRAM_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL3" }, "BRAM_L.BRAM_FIFO36_DOBDOL4->BRAM_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL4" }, "BRAM_L.BRAM_FIFO36_DOBDOL5->BRAM_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL5" }, "BRAM_L.BRAM_FIFO36_DOBDOL6->BRAM_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL6" }, "BRAM_L.BRAM_FIFO36_DOBDOL7->BRAM_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL7" }, "BRAM_L.BRAM_FIFO36_DOBDOL8->BRAM_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL8" }, "BRAM_L.BRAM_FIFO36_DOBDOL9->BRAM_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL9" }, "BRAM_L.BRAM_FIFO36_DOBDOU0->BRAM_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU0" }, "BRAM_L.BRAM_FIFO36_DOBDOU1->BRAM_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU1" }, "BRAM_L.BRAM_FIFO36_DOBDOU10->BRAM_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU10" }, "BRAM_L.BRAM_FIFO36_DOBDOU11->BRAM_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU11" }, "BRAM_L.BRAM_FIFO36_DOBDOU12->BRAM_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU12" }, "BRAM_L.BRAM_FIFO36_DOBDOU13->BRAM_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU13" }, "BRAM_L.BRAM_FIFO36_DOBDOU14->BRAM_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU14" }, "BRAM_L.BRAM_FIFO36_DOBDOU15->BRAM_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU15" }, "BRAM_L.BRAM_FIFO36_DOBDOU2->BRAM_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU2" }, "BRAM_L.BRAM_FIFO36_DOBDOU3->BRAM_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU3" }, "BRAM_L.BRAM_FIFO36_DOBDOU4->BRAM_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU4" }, "BRAM_L.BRAM_FIFO36_DOBDOU5->BRAM_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU5" }, "BRAM_L.BRAM_FIFO36_DOBDOU6->BRAM_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU6" }, "BRAM_L.BRAM_FIFO36_DOBDOU7->BRAM_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU7" }, "BRAM_L.BRAM_FIFO36_DOBDOU8->BRAM_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU8" }, "BRAM_L.BRAM_FIFO36_DOBDOU9->BRAM_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU9" }, "BRAM_L.BRAM_FIFO36_DOPADOPL0->BRAM_LOGIC_OUTS_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPL0" }, "BRAM_L.BRAM_FIFO36_DOPADOPL1->BRAM_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPL1" }, "BRAM_L.BRAM_FIFO36_DOPADOPU0->BRAM_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPU0" }, "BRAM_L.BRAM_FIFO36_DOPADOPU1->BRAM_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPU1" }, "BRAM_L.BRAM_FIFO36_DOPBDOPL0->BRAM_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPL0" }, "BRAM_L.BRAM_FIFO36_DOPBDOPL1->BRAM_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPL1" }, "BRAM_L.BRAM_FIFO36_DOPBDOPU0->BRAM_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPU0" }, "BRAM_L.BRAM_FIFO36_DOPBDOPU1->BRAM_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPU1" }, "BRAM_L.BRAM_FIFO36_ECCPARITY0->BRAM_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY0" }, "BRAM_L.BRAM_FIFO36_ECCPARITY1->BRAM_LOGIC_OUTS_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY1" }, "BRAM_L.BRAM_FIFO36_ECCPARITY2->BRAM_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY2" }, "BRAM_L.BRAM_FIFO36_ECCPARITY3->BRAM_LOGIC_OUTS_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY3" }, "BRAM_L.BRAM_FIFO36_ECCPARITY4->BRAM_LOGIC_OUTS_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY4" }, "BRAM_L.BRAM_FIFO36_ECCPARITY5->BRAM_LOGIC_OUTS_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY5" }, "BRAM_L.BRAM_FIFO36_ECCPARITY6->BRAM_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY6" }, "BRAM_L.BRAM_FIFO36_ECCPARITY7->BRAM_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY7" }, "BRAM_L.BRAM_FIFO36_EMPTY->BRAM_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_EMPTY" }, "BRAM_L.BRAM_FIFO36_FULL->BRAM_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_FULL" }, "BRAM_L.BRAM_FIFO36_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT0" }, "BRAM_L.BRAM_FIFO36_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT1" }, "BRAM_L.BRAM_FIFO36_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT10" }, "BRAM_L.BRAM_FIFO36_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT11" }, "BRAM_L.BRAM_FIFO36_RDCOUNT12->BRAM_LOGIC_OUTS_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT12" }, "BRAM_L.BRAM_FIFO36_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT2" }, "BRAM_L.BRAM_FIFO36_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT3" }, "BRAM_L.BRAM_FIFO36_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT4" }, "BRAM_L.BRAM_FIFO36_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT5" }, "BRAM_L.BRAM_FIFO36_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT6" }, "BRAM_L.BRAM_FIFO36_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT7" }, "BRAM_L.BRAM_FIFO36_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT8" }, "BRAM_L.BRAM_FIFO36_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT9" }, "BRAM_L.BRAM_FIFO36_RDERR->BRAM_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDERR" }, "BRAM_L.BRAM_FIFO36_SBITERR->BRAM_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_SBITERR" }, "BRAM_L.BRAM_FIFO36_TSTOUT0->BRAM_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT0" }, "BRAM_L.BRAM_FIFO36_TSTOUT1->BRAM_LOGIC_OUTS_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT1" }, "BRAM_L.BRAM_FIFO36_TSTOUT2->BRAM_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT2" }, "BRAM_L.BRAM_FIFO36_TSTOUT3->BRAM_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT3" }, "BRAM_L.BRAM_FIFO36_TSTOUT4->BRAM_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT4" }, "BRAM_L.BRAM_FIFO36_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT0" }, "BRAM_L.BRAM_FIFO36_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT1" }, "BRAM_L.BRAM_FIFO36_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT10" }, "BRAM_L.BRAM_FIFO36_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT11" }, "BRAM_L.BRAM_FIFO36_WRCOUNT12->BRAM_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT12" }, "BRAM_L.BRAM_FIFO36_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT2" }, "BRAM_L.BRAM_FIFO36_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT3" }, "BRAM_L.BRAM_FIFO36_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT4" }, "BRAM_L.BRAM_FIFO36_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT5" }, "BRAM_L.BRAM_FIFO36_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT6" }, "BRAM_L.BRAM_FIFO36_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT7" }, "BRAM_L.BRAM_FIFO36_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT8" }, "BRAM_L.BRAM_FIFO36_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT9" }, "BRAM_L.BRAM_FIFO36_WRERR->BRAM_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRERR" }, "BRAM_L.BRAM_IMUX0_0->BRAM_FIFO36_TSTBRAMRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTBRAMRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX0_0" }, "BRAM_L.BRAM_IMUX10_0->BRAM_FIFO36_TSTCNT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_0" }, "BRAM_L.BRAM_IMUX10_1->BRAM_IMUX_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_1" }, "BRAM_L.BRAM_IMUX10_2->BRAM_FIFO36_ENARDENU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENARDENU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_2" }, "BRAM_L.BRAM_IMUX10_2->BRAM_RAMB18_ENARDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_ENARDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_2" }, "BRAM_L.BRAM_IMUX10_3->BRAM_IMUX_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_3" }, "BRAM_L.BRAM_IMUX10_4->BRAM_FIFO36_DIADIU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_4" }, "BRAM_L.BRAM_IMUX10_4->BRAM_RAMB18_DIADI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_4" }, "BRAM_L.BRAM_IMUX11_0->BRAM_FIFO36_TSTCNT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_0" }, "BRAM_L.BRAM_IMUX11_1->BRAM_IMUX_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_1" }, "BRAM_L.BRAM_IMUX11_2->BRAM_FIFO36_REGCEAREGCEU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEAREGCEU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_2" }, "BRAM_L.BRAM_IMUX11_2->BRAM_RAMB18_REGCEAREGCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCEAREGCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_2" }, "BRAM_L.BRAM_IMUX11_3->BRAM_IMUX_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_3" }, "BRAM_L.BRAM_IMUX11_4->BRAM_FIFO36_DIADIU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_4" }, "BRAM_L.BRAM_IMUX11_4->BRAM_RAMB18_DIADI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_4" }, "BRAM_L.BRAM_IMUX12_0->BRAM_FIFO36_TSTCNT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_0" }, "BRAM_L.BRAM_IMUX12_1->BRAM_IMUX_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_1" }, "BRAM_L.BRAM_IMUX12_2->BRAM_IMUX_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_2" }, "BRAM_L.BRAM_IMUX12_3->BRAM_IMUX_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_3" }, "BRAM_L.BRAM_IMUX12_4->BRAM_FIFO36_DIADIU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_4" }, "BRAM_L.BRAM_IMUX12_4->BRAM_RAMB18_DIADI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_4" }, "BRAM_L.BRAM_IMUX13_0->BRAM_FIFO36_TSTCNT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_0" }, "BRAM_L.BRAM_IMUX13_1->BRAM_IMUX_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_1" }, "BRAM_L.BRAM_IMUX13_2->BRAM_FIFO36_WEBWEU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_2" }, "BRAM_L.BRAM_IMUX13_2->BRAM_RAMB18_WEBWE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_2" }, "BRAM_L.BRAM_IMUX13_3->BRAM_IMUX_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_3" }, "BRAM_L.BRAM_IMUX13_4->BRAM_FIFO36_DIADIU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_4" }, "BRAM_L.BRAM_IMUX13_4->BRAM_RAMB18_DIADI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_4" }, "BRAM_L.BRAM_IMUX14_0->BRAM_FIFO36_TSTCNT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_0" }, "BRAM_L.BRAM_IMUX14_1->BRAM_IMUX_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_1" }, "BRAM_L.BRAM_IMUX14_2->BRAM_FIFO36_WEBWEU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_2" }, "BRAM_L.BRAM_IMUX14_2->BRAM_RAMB18_WEBWE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_2" }, "BRAM_L.BRAM_IMUX14_3->BRAM_IMUX_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_3" }, "BRAM_L.BRAM_IMUX14_4->BRAM_FIFO36_DIADIU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_4" }, "BRAM_L.BRAM_IMUX14_4->BRAM_RAMB18_DIADI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_4" }, "BRAM_L.BRAM_IMUX15_0->BRAM_FIFO36_TSTCNT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_0" }, "BRAM_L.BRAM_IMUX15_1->BRAM_IMUX_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_1" }, "BRAM_L.BRAM_IMUX15_2->BRAM_FIFO36_DIADIU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_2" }, "BRAM_L.BRAM_IMUX15_2->BRAM_RAMB18_DIADI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_2" }, "BRAM_L.BRAM_IMUX15_3->BRAM_FIFO36_DIPADIPU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_3" }, "BRAM_L.BRAM_IMUX15_3->BRAM_RAMB18_DIPADIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPADIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_3" }, "BRAM_L.BRAM_IMUX15_4->BRAM_FIFO36_DIADIU15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_4" }, "BRAM_L.BRAM_IMUX15_4->BRAM_RAMB18_DIADI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_4" }, "BRAM_L.BRAM_IMUX16_0->BRAM_FIFO36_TSTIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_0" }, "BRAM_L.BRAM_IMUX16_1->BRAM_FIFO18_DIADI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_1" }, "BRAM_L.BRAM_IMUX16_1->BRAM_FIFO36_DIADIL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_1" }, "BRAM_L.BRAM_IMUX16_2->BRAM_FIFO18_WEA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_2" }, "BRAM_L.BRAM_IMUX16_2->BRAM_FIFO36_WEAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_2" }, "BRAM_L.BRAM_IMUX16_3->BRAM_IMUX_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_3" }, "BRAM_L.BRAM_IMUX16_4->BRAM_FIFO36_DIBDIU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_4" }, "BRAM_L.BRAM_IMUX16_4->BRAM_RAMB18_DIBDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_4" }, "BRAM_L.BRAM_IMUX17_1->BRAM_IMUX_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_1" }, "BRAM_L.BRAM_IMUX17_2->BRAM_FIFO18_WEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_2" }, "BRAM_L.BRAM_IMUX17_2->BRAM_FIFO36_WEAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_2" }, "BRAM_L.BRAM_IMUX17_3->BRAM_IMUX_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_3" }, "BRAM_L.BRAM_IMUX17_4->BRAM_FIFO36_DIBDIU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_4" }, "BRAM_L.BRAM_IMUX17_4->BRAM_RAMB18_DIBDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_4" }, "BRAM_L.BRAM_IMUX18_0->BRAM_FIFO36_TSTRDOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_0" }, "BRAM_L.BRAM_IMUX18_1->BRAM_IMUX_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_1" }, "BRAM_L.BRAM_IMUX18_2->BRAM_FIFO18_ENARDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_ENARDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_2" }, "BRAM_L.BRAM_IMUX18_2->BRAM_FIFO36_ENARDENL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENARDENL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_2" }, "BRAM_L.BRAM_IMUX18_3->BRAM_IMUX_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_3" }, "BRAM_L.BRAM_IMUX18_4->BRAM_FIFO36_DIBDIU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_4" }, "BRAM_L.BRAM_IMUX18_4->BRAM_RAMB18_DIBDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_4" }, "BRAM_L.BRAM_IMUX19_0->BRAM_FIFO36_TSTRDOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_0" }, "BRAM_L.BRAM_IMUX19_1->BRAM_IMUX_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_1" }, "BRAM_L.BRAM_IMUX19_2->BRAM_FIFO18_REGCEAREGCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCEAREGCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_2" }, "BRAM_L.BRAM_IMUX19_2->BRAM_FIFO36_REGCEAREGCEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEAREGCEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_2" }, "BRAM_L.BRAM_IMUX19_3->BRAM_IMUX_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_3" }, "BRAM_L.BRAM_IMUX19_4->BRAM_FIFO36_DIBDIU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_4" }, "BRAM_L.BRAM_IMUX19_4->BRAM_RAMB18_DIBDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_4" }, "BRAM_L.BRAM_IMUX1_1->BRAM_FIFO18_DIPBDIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPBDIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_1" }, "BRAM_L.BRAM_IMUX1_1->BRAM_FIFO36_DIPBDIPL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_1" }, "BRAM_L.BRAM_IMUX1_2->BRAM_FIFO18_DIBDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_2" }, "BRAM_L.BRAM_IMUX1_2->BRAM_FIFO36_DIBDIL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_2" }, "BRAM_L.BRAM_IMUX1_3->BRAM_FIFO36_DIBDIU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_3" }, "BRAM_L.BRAM_IMUX1_3->BRAM_RAMB18_DIBDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_3" }, "BRAM_L.BRAM_IMUX20_0->BRAM_FIFO36_TSTRDOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_0" }, "BRAM_L.BRAM_IMUX20_1->BRAM_IMUX_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_1" }, "BRAM_L.BRAM_IMUX20_2->BRAM_IMUX_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_2" }, "BRAM_L.BRAM_IMUX20_3->BRAM_IMUX_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_3" }, "BRAM_L.BRAM_IMUX20_4->BRAM_FIFO36_DIBDIU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_4" }, "BRAM_L.BRAM_IMUX20_4->BRAM_RAMB18_DIBDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_4" }, "BRAM_L.BRAM_IMUX21_0->BRAM_FIFO36_TSTRDOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_0" }, "BRAM_L.BRAM_IMUX21_1->BRAM_IMUX_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_1" }, "BRAM_L.BRAM_IMUX21_2->BRAM_FIFO18_WEBWE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_2" }, "BRAM_L.BRAM_IMUX21_2->BRAM_FIFO36_WEBWEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_2" }, "BRAM_L.BRAM_IMUX21_3->BRAM_IMUX_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_3" }, "BRAM_L.BRAM_IMUX21_4->BRAM_FIFO36_DIBDIU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_4" }, "BRAM_L.BRAM_IMUX21_4->BRAM_RAMB18_DIBDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_4" }, "BRAM_L.BRAM_IMUX22_0->BRAM_FIFO36_TSTRDOS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_0" }, "BRAM_L.BRAM_IMUX22_1->BRAM_IMUX_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_1" }, "BRAM_L.BRAM_IMUX22_2->BRAM_FIFO18_WEBWE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_2" }, "BRAM_L.BRAM_IMUX22_2->BRAM_FIFO36_WEBWEL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_2" }, "BRAM_L.BRAM_IMUX22_3->BRAM_IMUX_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_3" }, "BRAM_L.BRAM_IMUX22_4->BRAM_FIFO36_DIBDIU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_4" }, "BRAM_L.BRAM_IMUX22_4->BRAM_RAMB18_DIBDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_4" }, "BRAM_L.BRAM_IMUX23_0->BRAM_FIFO36_TSTRDOS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_0" }, "BRAM_L.BRAM_IMUX23_1->BRAM_IMUX_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_1" }, "BRAM_L.BRAM_IMUX23_2->BRAM_FIFO36_DIBDIU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_2" }, "BRAM_L.BRAM_IMUX23_2->BRAM_RAMB18_DIBDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_2" }, "BRAM_L.BRAM_IMUX23_3->BRAM_FIFO36_DIPBDIPU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_3" }, "BRAM_L.BRAM_IMUX23_3->BRAM_RAMB18_DIPBDIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPBDIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_3" }, "BRAM_L.BRAM_IMUX23_4->BRAM_FIFO36_DIBDIU15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_4" }, "BRAM_L.BRAM_IMUX23_4->BRAM_RAMB18_DIBDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_4" }, "BRAM_L.BRAM_IMUX24_1->BRAM_FIFO36_DIBDIU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_1" }, "BRAM_L.BRAM_IMUX24_1->BRAM_RAMB18_DIBDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_1" }, "BRAM_L.BRAM_IMUX24_2->BRAM_FIFO36_WEAU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_2" }, "BRAM_L.BRAM_IMUX24_2->BRAM_RAMB18_WEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_2" }, "BRAM_L.BRAM_IMUX24_3->BRAM_IMUX_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_3" }, "BRAM_L.BRAM_IMUX24_4->BRAM_FIFO36_TSTCNT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_4" }, "BRAM_L.BRAM_IMUX25_0->BRAM_FIFO18_DIADI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_0" }, "BRAM_L.BRAM_IMUX25_0->BRAM_FIFO36_DIADIL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_0" }, "BRAM_L.BRAM_IMUX25_1->BRAM_IMUX_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_1" }, "BRAM_L.BRAM_IMUX25_2->BRAM_FIFO36_WEAU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_2" }, "BRAM_L.BRAM_IMUX25_2->BRAM_RAMB18_WEA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_2" }, "BRAM_L.BRAM_IMUX25_3->BRAM_IMUX_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_3" }, "BRAM_L.BRAM_IMUX25_4->BRAM_FIFO36_TSTCNT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_4" }, "BRAM_L.BRAM_IMUX26_0->BRAM_FIFO18_DIADI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_0" }, "BRAM_L.BRAM_IMUX26_0->BRAM_FIFO36_DIADIL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_0" }, "BRAM_L.BRAM_IMUX26_1->BRAM_IMUX_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_1" }, "BRAM_L.BRAM_IMUX26_2->BRAM_FIFO36_ENBWRENU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENBWRENU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_2" }, "BRAM_L.BRAM_IMUX26_2->BRAM_RAMB18_ENBWREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_ENBWREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_2" }, "BRAM_L.BRAM_IMUX26_3->BRAM_IMUX_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_3" }, "BRAM_L.BRAM_IMUX26_4->BRAM_FIFO36_TSTCNT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_4" }, "BRAM_L.BRAM_IMUX27_0->BRAM_FIFO18_DIADI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_0" }, "BRAM_L.BRAM_IMUX27_0->BRAM_FIFO36_DIADIL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_0" }, "BRAM_L.BRAM_IMUX27_1->BRAM_IMUX_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_1" }, "BRAM_L.BRAM_IMUX27_2->BRAM_FIFO36_REGCEBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_2" }, "BRAM_L.BRAM_IMUX27_2->BRAM_RAMB18_REGCEB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCEB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_2" }, "BRAM_L.BRAM_IMUX27_3->BRAM_IMUX_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_3" }, "BRAM_L.BRAM_IMUX27_4->BRAM_FIFO36_TSTCNT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_4" }, "BRAM_L.BRAM_IMUX28_0->BRAM_FIFO18_DIADI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_0" }, "BRAM_L.BRAM_IMUX28_0->BRAM_FIFO36_DIADIL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_0" }, "BRAM_L.BRAM_IMUX28_1->BRAM_IMUX_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_1" }, "BRAM_L.BRAM_IMUX28_2->BRAM_IMUX_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_2" }, "BRAM_L.BRAM_IMUX28_3->BRAM_IMUX_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_3" }, "BRAM_L.BRAM_IMUX28_4->BRAM_FIFO36_TSTCNT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_4" }, "BRAM_L.BRAM_IMUX29_0->BRAM_FIFO18_DIADI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_0" }, "BRAM_L.BRAM_IMUX29_0->BRAM_FIFO36_DIADIL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_0" }, "BRAM_L.BRAM_IMUX29_1->BRAM_IMUX_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_1" }, "BRAM_L.BRAM_IMUX29_2->BRAM_FIFO36_WEBWEU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_2" }, "BRAM_L.BRAM_IMUX29_2->BRAM_RAMB18_WEBWE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_2" }, "BRAM_L.BRAM_IMUX29_3->BRAM_IMUX_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_3" }, "BRAM_L.BRAM_IMUX29_4->BRAM_FIFO36_TSTCNT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_4" }, "BRAM_L.BRAM_IMUX2_0->BRAM_FIFO36_TSTRDCNTOFF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDCNTOFF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_0" }, "BRAM_L.BRAM_IMUX2_1->BRAM_FIFO18_DIBDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_1" }, "BRAM_L.BRAM_IMUX2_1->BRAM_FIFO36_DIBDIL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_1" }, "BRAM_L.BRAM_IMUX2_2->BRAM_FIFO18_DIBDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_2" }, "BRAM_L.BRAM_IMUX2_2->BRAM_FIFO36_DIBDIL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_2" }, "BRAM_L.BRAM_IMUX2_3->BRAM_FIFO36_DIBDIU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_3" }, "BRAM_L.BRAM_IMUX2_3->BRAM_RAMB18_DIBDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_3" }, "BRAM_L.BRAM_IMUX30_0->BRAM_FIFO18_DIADI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_0" }, "BRAM_L.BRAM_IMUX30_0->BRAM_FIFO36_DIADIL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_0" }, "BRAM_L.BRAM_IMUX30_1->BRAM_IMUX_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_1" }, "BRAM_L.BRAM_IMUX30_2->BRAM_FIFO36_WEBWEU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_2" }, "BRAM_L.BRAM_IMUX30_2->BRAM_RAMB18_WEBWE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_2" }, "BRAM_L.BRAM_IMUX30_3->BRAM_IMUX_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_3" }, "BRAM_L.BRAM_IMUX30_4->BRAM_FIFO36_TSTCNT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_4" }, "BRAM_L.BRAM_IMUX31_0->BRAM_FIFO18_DIADI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_0" }, "BRAM_L.BRAM_IMUX31_0->BRAM_FIFO36_DIADIL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_0" }, "BRAM_L.BRAM_IMUX31_1->BRAM_IMUX_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_1" }, "BRAM_L.BRAM_IMUX31_2->BRAM_FIFO36_INJECTDBITERR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_INJECTDBITERR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_2" }, "BRAM_L.BRAM_IMUX31_3->BRAM_IMUX_ADDRARDADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_3" }, "BRAM_L.BRAM_IMUX32_1->BRAM_FIFO18_DIBDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_1" }, "BRAM_L.BRAM_IMUX32_1->BRAM_FIFO36_DIBDIL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_1" }, "BRAM_L.BRAM_IMUX32_2->BRAM_FIFO18_WEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_2" }, "BRAM_L.BRAM_IMUX32_2->BRAM_FIFO36_WEAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_2" }, "BRAM_L.BRAM_IMUX32_3->BRAM_IMUX_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_3" }, "BRAM_L.BRAM_IMUX32_4->BRAM_FIFO36_TSTRDOS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_4" }, "BRAM_L.BRAM_IMUX33_0->BRAM_FIFO18_DIBDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_0" }, "BRAM_L.BRAM_IMUX33_0->BRAM_FIFO36_DIBDIL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_0" }, "BRAM_L.BRAM_IMUX33_1->BRAM_IMUX_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_1" }, "BRAM_L.BRAM_IMUX33_2->BRAM_FIFO18_WEA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_2" }, "BRAM_L.BRAM_IMUX33_2->BRAM_FIFO36_WEAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_2" }, "BRAM_L.BRAM_IMUX33_3->BRAM_IMUX_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_3" }, "BRAM_L.BRAM_IMUX33_4->BRAM_FIFO36_TSTRDOS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_4" }, "BRAM_L.BRAM_IMUX34_0->BRAM_FIFO18_DIBDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_0" }, "BRAM_L.BRAM_IMUX34_0->BRAM_FIFO36_DIBDIL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_0" }, "BRAM_L.BRAM_IMUX34_1->BRAM_IMUX_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_1" }, "BRAM_L.BRAM_IMUX34_2->BRAM_FIFO18_ENBWREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_ENBWREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_2" }, "BRAM_L.BRAM_IMUX34_2->BRAM_FIFO36_ENBWRENL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENBWRENL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_2" }, "BRAM_L.BRAM_IMUX34_3->BRAM_IMUX_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_3" }, "BRAM_L.BRAM_IMUX34_4->BRAM_FIFO36_TSTRDOS8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_4" }, "BRAM_L.BRAM_IMUX35_0->BRAM_FIFO18_DIBDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_0" }, "BRAM_L.BRAM_IMUX35_0->BRAM_FIFO36_DIBDIL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_0" }, "BRAM_L.BRAM_IMUX35_1->BRAM_IMUX_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_1" }, "BRAM_L.BRAM_IMUX35_2->BRAM_FIFO18_REGCEB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCEB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_2" }, "BRAM_L.BRAM_IMUX35_2->BRAM_FIFO36_REGCEBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_2" }, "BRAM_L.BRAM_IMUX35_3->BRAM_IMUX_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_3" }, "BRAM_L.BRAM_IMUX35_4->BRAM_FIFO36_TSTRDOS9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_4" }, "BRAM_L.BRAM_IMUX36_0->BRAM_FIFO18_DIBDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_0" }, "BRAM_L.BRAM_IMUX36_0->BRAM_FIFO36_DIBDIL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_0" }, "BRAM_L.BRAM_IMUX36_1->BRAM_IMUX_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_1" }, "BRAM_L.BRAM_IMUX36_2->BRAM_IMUX_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_2" }, "BRAM_L.BRAM_IMUX36_3->BRAM_IMUX_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_3" }, "BRAM_L.BRAM_IMUX36_4->BRAM_FIFO36_TSTRDOS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_4" }, "BRAM_L.BRAM_IMUX37_0->BRAM_FIFO18_DIBDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_0" }, "BRAM_L.BRAM_IMUX37_0->BRAM_FIFO36_DIBDIL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_0" }, "BRAM_L.BRAM_IMUX37_1->BRAM_IMUX_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_1" }, "BRAM_L.BRAM_IMUX37_2->BRAM_FIFO18_WEBWE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_2" }, "BRAM_L.BRAM_IMUX37_2->BRAM_FIFO36_WEBWEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_2" }, "BRAM_L.BRAM_IMUX37_3->BRAM_IMUX_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_3" }, "BRAM_L.BRAM_IMUX37_4->BRAM_FIFO36_TSTRDOS11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_4" }, "BRAM_L.BRAM_IMUX38_0->BRAM_FIFO18_DIBDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_0" }, "BRAM_L.BRAM_IMUX38_0->BRAM_FIFO36_DIBDIL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_0" }, "BRAM_L.BRAM_IMUX38_1->BRAM_IMUX_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_1" }, "BRAM_L.BRAM_IMUX38_2->BRAM_FIFO18_WEBWE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_2" }, "BRAM_L.BRAM_IMUX38_2->BRAM_FIFO36_WEBWEL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_2" }, "BRAM_L.BRAM_IMUX38_3->BRAM_IMUX_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_3" }, "BRAM_L.BRAM_IMUX38_4->BRAM_FIFO36_TSTRDOS12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_4" }, "BRAM_L.BRAM_IMUX39_0->BRAM_FIFO18_DIBDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_0" }, "BRAM_L.BRAM_IMUX39_0->BRAM_FIFO36_DIBDIL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_0" }, "BRAM_L.BRAM_IMUX39_1->BRAM_IMUX_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_1" }, "BRAM_L.BRAM_IMUX39_2->BRAM_FIFO36_INJECTSBITERR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_INJECTSBITERR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_2" }, "BRAM_L.BRAM_IMUX39_3->BRAM_IMUX_ADDRBWRADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_3" }, "BRAM_L.BRAM_IMUX3_0->BRAM_FIFO36_TSTWRCNTOFF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWRCNTOFF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_0" }, "BRAM_L.BRAM_IMUX3_1->BRAM_FIFO18_DIBDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_1" }, "BRAM_L.BRAM_IMUX3_1->BRAM_FIFO36_DIBDIL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_1" }, "BRAM_L.BRAM_IMUX3_2->BRAM_FIFO18_DIPADIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPADIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_2" }, "BRAM_L.BRAM_IMUX3_2->BRAM_FIFO36_DIPADIPL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_2" }, "BRAM_L.BRAM_IMUX3_3->BRAM_FIFO36_DIBDIU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_3" }, "BRAM_L.BRAM_IMUX3_3->BRAM_RAMB18_DIBDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_3" }, "BRAM_L.BRAM_IMUX40_1->BRAM_FIFO18_DIPADIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPADIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_1" }, "BRAM_L.BRAM_IMUX40_1->BRAM_FIFO36_DIPADIPL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_1" }, "BRAM_L.BRAM_IMUX40_2->BRAM_FIFO18_DIADI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_2" }, "BRAM_L.BRAM_IMUX40_2->BRAM_FIFO36_DIADIL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_2" }, "BRAM_L.BRAM_IMUX40_3->BRAM_FIFO36_DIADIU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_3" }, "BRAM_L.BRAM_IMUX40_3->BRAM_RAMB18_DIADI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_3" }, "BRAM_L.BRAM_IMUX40_4->BRAM_FIFO36_TSTWROS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_4" }, "BRAM_L.BRAM_IMUX41_0->BRAM_FIFO36_TSTIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_0" }, "BRAM_L.BRAM_IMUX41_1->BRAM_FIFO18_DIADI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_1" }, "BRAM_L.BRAM_IMUX41_1->BRAM_FIFO36_DIADIL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_1" }, "BRAM_L.BRAM_IMUX41_2->BRAM_FIFO18_DIADI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_2" }, "BRAM_L.BRAM_IMUX41_2->BRAM_FIFO36_DIADIL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_2" }, "BRAM_L.BRAM_IMUX41_3->BRAM_FIFO36_DIADIU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_3" }, "BRAM_L.BRAM_IMUX41_3->BRAM_RAMB18_DIADI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_3" }, 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+ "res": "0.000" + }, "src_wire": "BRAM_IMUX42_1" }, "BRAM_L.BRAM_IMUX42_1->BRAM_FIFO36_DIADIL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_1" }, "BRAM_L.BRAM_IMUX42_2->BRAM_FIFO36_DIPADIPU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_2" }, "BRAM_L.BRAM_IMUX42_2->BRAM_RAMB18_DIPADIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPADIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_2" }, "BRAM_L.BRAM_IMUX42_3->BRAM_FIFO36_DIADIU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_3" }, "BRAM_L.BRAM_IMUX42_3->BRAM_RAMB18_DIADI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_3" }, "BRAM_L.BRAM_IMUX42_4->BRAM_FIFO36_TSTWROS8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_4" }, "BRAM_L.BRAM_IMUX43_0->BRAM_FIFO36_TSTWROS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_0" }, "BRAM_L.BRAM_IMUX43_1->BRAM_FIFO18_DIADI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_1" }, "BRAM_L.BRAM_IMUX43_1->BRAM_FIFO36_DIADIL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_1" }, "BRAM_L.BRAM_IMUX43_2->BRAM_FIFO36_DIPBDIPU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_2" }, "BRAM_L.BRAM_IMUX43_2->BRAM_RAMB18_DIPBDIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPBDIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_2" }, "BRAM_L.BRAM_IMUX43_3->BRAM_FIFO36_DIADIU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_3" }, "BRAM_L.BRAM_IMUX43_3->BRAM_RAMB18_DIADI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_3" }, "BRAM_L.BRAM_IMUX43_4->BRAM_FIFO36_TSTWROS9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_4" }, "BRAM_L.BRAM_IMUX44_0->BRAM_FIFO36_TSTWROS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_0" }, "BRAM_L.BRAM_IMUX44_1->BRAM_FIFO18_DIADI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_1" }, "BRAM_L.BRAM_IMUX44_1->BRAM_FIFO36_DIADIL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_1" }, "BRAM_L.BRAM_IMUX44_3->BRAM_FIFO36_DIADIU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_3" }, "BRAM_L.BRAM_IMUX44_3->BRAM_RAMB18_DIADI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_3" }, "BRAM_L.BRAM_IMUX44_4->BRAM_FIFO36_TSTWROS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_4" }, "BRAM_L.BRAM_IMUX45_0->BRAM_FIFO36_TSTWROS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_0" }, "BRAM_L.BRAM_IMUX45_1->BRAM_FIFO18_DIADI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_1" }, "BRAM_L.BRAM_IMUX45_1->BRAM_FIFO36_DIADIL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_1" }, "BRAM_L.BRAM_IMUX45_2->BRAM_FIFO36_WEBWEU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_2" }, "BRAM_L.BRAM_IMUX45_2->BRAM_RAMB18_WEBWE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_2" }, "BRAM_L.BRAM_IMUX45_3->BRAM_FIFO36_DIADIU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_3" }, "BRAM_L.BRAM_IMUX45_3->BRAM_RAMB18_DIADI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_3" }, "BRAM_L.BRAM_IMUX45_4->BRAM_FIFO36_TSTWROS11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_4" }, "BRAM_L.BRAM_IMUX46_0->BRAM_FIFO36_TSTWROS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_0" }, "BRAM_L.BRAM_IMUX46_1->BRAM_FIFO18_DIADI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_1" }, "BRAM_L.BRAM_IMUX46_1->BRAM_FIFO36_DIADIL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_1" }, "BRAM_L.BRAM_IMUX46_2->BRAM_FIFO36_WEBWEU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_2" }, "BRAM_L.BRAM_IMUX46_2->BRAM_RAMB18_WEBWE7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_2" }, "BRAM_L.BRAM_IMUX46_4->BRAM_FIFO36_TSTWROS12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_4" }, "BRAM_L.BRAM_IMUX47_0->BRAM_FIFO36_TSTWROS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX47_0" }, "BRAM_L.BRAM_IMUX4_0->BRAM_FIFO36_TSTOFF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTOFF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_0" }, "BRAM_L.BRAM_IMUX4_1->BRAM_FIFO18_DIBDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_1" }, "BRAM_L.BRAM_IMUX4_1->BRAM_FIFO36_DIBDIL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_1" }, "BRAM_L.BRAM_IMUX4_2->BRAM_FIFO18_DIPBDIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPBDIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_2" }, "BRAM_L.BRAM_IMUX4_2->BRAM_FIFO36_DIPBDIPL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_2" }, "BRAM_L.BRAM_IMUX4_3->BRAM_FIFO36_DIBDIU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_3" }, "BRAM_L.BRAM_IMUX4_3->BRAM_RAMB18_DIBDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_3" }, "BRAM_L.BRAM_IMUX4_4->BRAM_FIFO36_TSTIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_4" }, "BRAM_L.BRAM_IMUX5_0->BRAM_FIFO36_TSTFLAGIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTFLAGIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_0" }, "BRAM_L.BRAM_IMUX5_1->BRAM_FIFO18_DIBDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_1" }, "BRAM_L.BRAM_IMUX5_1->BRAM_FIFO36_DIBDIL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_1" }, "BRAM_L.BRAM_IMUX5_2->BRAM_FIFO18_WEBWE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_2" }, "BRAM_L.BRAM_IMUX5_2->BRAM_FIFO36_WEBWEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_2" }, "BRAM_L.BRAM_IMUX5_3->BRAM_FIFO36_DIBDIU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_3" }, "BRAM_L.BRAM_IMUX5_3->BRAM_RAMB18_DIBDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_3" }, "BRAM_L.BRAM_IMUX5_4->BRAM_FIFO36_TSTIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_4" }, "BRAM_L.BRAM_IMUX6_1->BRAM_FIFO18_DIBDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_1" }, "BRAM_L.BRAM_IMUX6_1->BRAM_FIFO36_DIBDIL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_1" }, "BRAM_L.BRAM_IMUX6_2->BRAM_FIFO18_WEBWE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_2" }, "BRAM_L.BRAM_IMUX6_2->BRAM_FIFO36_WEBWEL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_2" }, "BRAM_L.BRAM_IMUX6_3->BRAM_FIFO36_DIBDIU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_3" }, "BRAM_L.BRAM_IMUX6_3->BRAM_RAMB18_DIBDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_3" }, "BRAM_L.BRAM_IMUX7_1->BRAM_FIFO18_DIBDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX7_1" }, "BRAM_L.BRAM_IMUX7_1->BRAM_FIFO36_DIBDIL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX7_1" }, "BRAM_L.BRAM_IMUX8_0->BRAM_FIFO36_TSTIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_0" }, "BRAM_L.BRAM_IMUX8_1->BRAM_FIFO36_DIADIU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_1" }, "BRAM_L.BRAM_IMUX8_1->BRAM_RAMB18_DIADI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_1" }, "BRAM_L.BRAM_IMUX8_2->BRAM_FIFO36_WEAU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_2" }, "BRAM_L.BRAM_IMUX8_2->BRAM_RAMB18_WEA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_2" }, "BRAM_L.BRAM_IMUX8_3->BRAM_IMUX_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_3" }, "BRAM_L.BRAM_IMUX8_4->BRAM_FIFO36_DIADIU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_4" }, "BRAM_L.BRAM_IMUX8_4->BRAM_RAMB18_DIADI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_4" }, "BRAM_L.BRAM_IMUX9_1->BRAM_IMUX_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_1" }, "BRAM_L.BRAM_IMUX9_2->BRAM_FIFO36_WEAU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_2" }, "BRAM_L.BRAM_IMUX9_2->BRAM_RAMB18_WEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_2" }, "BRAM_L.BRAM_IMUX9_3->BRAM_IMUX_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_3" }, "BRAM_L.BRAM_IMUX9_4->BRAM_FIFO36_DIADIU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_4" }, "BRAM_L.BRAM_IMUX9_4->BRAM_RAMB18_DIADI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_4" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL0->BRAM_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL0" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL1->BRAM_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL1" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL10->BRAM_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL10" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL11->BRAM_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL11" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL12->BRAM_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL12" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL13->BRAM_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL13" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL14->BRAM_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL14" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_FIFO18_ADDRATIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_FIFO36_ADDRARDADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_RAMB18_ADDRATIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_UTURN_ADDRARDADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL2->BRAM_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL2" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL3->BRAM_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL3" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL4->BRAM_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL4" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL5->BRAM_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL5" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL6->BRAM_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL6" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL7->BRAM_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL7" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL8->BRAM_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL8" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL9->BRAM_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL9" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU0" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU1" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU10" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU11" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU12" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU13" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU14" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU2" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU3" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU4" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU5" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU6" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU7" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU8" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU9" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL0" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL1" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL10" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL11" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL12" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL13" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL14" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_FIFO18_ADDRBTIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_FIFO36_ADDRBWRADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_RAMB18_ADDRBTIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_UTURN_ADDRBWRADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL2" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL3" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL4" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL5" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL6" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL7" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL8" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL9" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU0" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU1" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU10" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU11" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU12" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU13" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU14" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU2" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU3" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU4" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU5" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU6" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU7" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU8" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU9" }, "BRAM_L.BRAM_RAMB18_DOADO0->BRAM_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO0" }, "BRAM_L.BRAM_RAMB18_DOADO1->BRAM_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO1" }, "BRAM_L.BRAM_RAMB18_DOADO10->BRAM_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO10" }, "BRAM_L.BRAM_RAMB18_DOADO11->BRAM_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO11" }, "BRAM_L.BRAM_RAMB18_DOADO12->BRAM_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO12" }, "BRAM_L.BRAM_RAMB18_DOADO13->BRAM_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO13" }, "BRAM_L.BRAM_RAMB18_DOADO14->BRAM_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO14" }, "BRAM_L.BRAM_RAMB18_DOADO15->BRAM_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO15" }, "BRAM_L.BRAM_RAMB18_DOADO2->BRAM_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO2" }, "BRAM_L.BRAM_RAMB18_DOADO3->BRAM_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO3" }, "BRAM_L.BRAM_RAMB18_DOADO4->BRAM_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO4" }, "BRAM_L.BRAM_RAMB18_DOADO5->BRAM_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO5" }, "BRAM_L.BRAM_RAMB18_DOADO6->BRAM_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO6" }, "BRAM_L.BRAM_RAMB18_DOADO7->BRAM_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO7" }, "BRAM_L.BRAM_RAMB18_DOADO8->BRAM_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO8" }, "BRAM_L.BRAM_RAMB18_DOADO9->BRAM_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO9" }, "BRAM_L.BRAM_RAMB18_DOBDO0->BRAM_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO0" }, "BRAM_L.BRAM_RAMB18_DOBDO1->BRAM_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO1" }, "BRAM_L.BRAM_RAMB18_DOBDO10->BRAM_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO10" }, "BRAM_L.BRAM_RAMB18_DOBDO11->BRAM_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO11" }, "BRAM_L.BRAM_RAMB18_DOBDO12->BRAM_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO12" }, "BRAM_L.BRAM_RAMB18_DOBDO13->BRAM_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO13" }, "BRAM_L.BRAM_RAMB18_DOBDO14->BRAM_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO14" }, "BRAM_L.BRAM_RAMB18_DOBDO15->BRAM_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO15" }, "BRAM_L.BRAM_RAMB18_DOBDO2->BRAM_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO2" }, "BRAM_L.BRAM_RAMB18_DOBDO3->BRAM_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO3" }, "BRAM_L.BRAM_RAMB18_DOBDO4->BRAM_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO4" }, "BRAM_L.BRAM_RAMB18_DOBDO5->BRAM_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO5" }, "BRAM_L.BRAM_RAMB18_DOBDO6->BRAM_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO6" }, "BRAM_L.BRAM_RAMB18_DOBDO7->BRAM_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO7" }, "BRAM_L.BRAM_RAMB18_DOBDO8->BRAM_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO8" }, "BRAM_L.BRAM_RAMB18_DOBDO9->BRAM_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO9" }, "BRAM_L.BRAM_RAMB18_DOPADOP0->BRAM_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPADOP0" }, "BRAM_L.BRAM_RAMB18_DOPADOP1->BRAM_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPADOP1" }, "BRAM_L.BRAM_RAMB18_DOPBDOP0->BRAM_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPBDOP0" }, "BRAM_L.BRAM_RAMB18_DOPBDOP1->BRAM_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPBDOP1" } }, @@ -6824,362 +19718,3566 @@ "name": "X0Y0", "prefix": "RAMB36", "site_pins": { - "ADDRARDADDRL0": "BRAM_FIFO36_ADDRARDADDRL0", - "ADDRARDADDRL1": "BRAM_FIFO36_ADDRARDADDRL1", - "ADDRARDADDRL10": "BRAM_FIFO36_ADDRARDADDRL10", - "ADDRARDADDRL11": "BRAM_FIFO36_ADDRARDADDRL11", - "ADDRARDADDRL12": "BRAM_FIFO36_ADDRARDADDRL12", - "ADDRARDADDRL13": "BRAM_FIFO36_ADDRARDADDRL13", - "ADDRARDADDRL14": "BRAM_FIFO36_ADDRARDADDRL14", - "ADDRARDADDRL15": "BRAM_FIFO36_ADDRARDADDRL15", - "ADDRARDADDRL2": "BRAM_FIFO36_ADDRARDADDRL2", - "ADDRARDADDRL3": "BRAM_FIFO36_ADDRARDADDRL3", - "ADDRARDADDRL4": "BRAM_FIFO36_ADDRARDADDRL4", - "ADDRARDADDRL5": "BRAM_FIFO36_ADDRARDADDRL5", - "ADDRARDADDRL6": "BRAM_FIFO36_ADDRARDADDRL6", - "ADDRARDADDRL7": "BRAM_FIFO36_ADDRARDADDRL7", - "ADDRARDADDRL8": "BRAM_FIFO36_ADDRARDADDRL8", - "ADDRARDADDRL9": "BRAM_FIFO36_ADDRARDADDRL9", - "ADDRARDADDRU0": "BRAM_FIFO36_ADDRARDADDRU0", - "ADDRARDADDRU1": "BRAM_FIFO36_ADDRARDADDRU1", - "ADDRARDADDRU10": "BRAM_FIFO36_ADDRARDADDRU10", - "ADDRARDADDRU11": "BRAM_FIFO36_ADDRARDADDRU11", - "ADDRARDADDRU12": "BRAM_FIFO36_ADDRARDADDRU12", - "ADDRARDADDRU13": "BRAM_FIFO36_ADDRARDADDRU13", - "ADDRARDADDRU14": "BRAM_FIFO36_ADDRARDADDRU14", - "ADDRARDADDRU2": "BRAM_FIFO36_ADDRARDADDRU2", - "ADDRARDADDRU3": "BRAM_FIFO36_ADDRARDADDRU3", - "ADDRARDADDRU4": "BRAM_FIFO36_ADDRARDADDRU4", - "ADDRARDADDRU5": "BRAM_FIFO36_ADDRARDADDRU5", - "ADDRARDADDRU6": "BRAM_FIFO36_ADDRARDADDRU6", - "ADDRARDADDRU7": "BRAM_FIFO36_ADDRARDADDRU7", - "ADDRARDADDRU8": "BRAM_FIFO36_ADDRARDADDRU8", - "ADDRARDADDRU9": "BRAM_FIFO36_ADDRARDADDRU9", - "ADDRBWRADDRL0": "BRAM_FIFO36_ADDRBWRADDRL0", - "ADDRBWRADDRL1": "BRAM_FIFO36_ADDRBWRADDRL1", - "ADDRBWRADDRL10": "BRAM_FIFO36_ADDRBWRADDRL10", - "ADDRBWRADDRL11": "BRAM_FIFO36_ADDRBWRADDRL11", - "ADDRBWRADDRL12": "BRAM_FIFO36_ADDRBWRADDRL12", - "ADDRBWRADDRL13": "BRAM_FIFO36_ADDRBWRADDRL13", - "ADDRBWRADDRL14": "BRAM_FIFO36_ADDRBWRADDRL14", - "ADDRBWRADDRL15": "BRAM_FIFO36_ADDRBWRADDRL15", - "ADDRBWRADDRL2": "BRAM_FIFO36_ADDRBWRADDRL2", - "ADDRBWRADDRL3": "BRAM_FIFO36_ADDRBWRADDRL3", - "ADDRBWRADDRL4": "BRAM_FIFO36_ADDRBWRADDRL4", - "ADDRBWRADDRL5": "BRAM_FIFO36_ADDRBWRADDRL5", - "ADDRBWRADDRL6": "BRAM_FIFO36_ADDRBWRADDRL6", - "ADDRBWRADDRL7": "BRAM_FIFO36_ADDRBWRADDRL7", - "ADDRBWRADDRL8": "BRAM_FIFO36_ADDRBWRADDRL8", - "ADDRBWRADDRL9": "BRAM_FIFO36_ADDRBWRADDRL9", - "ADDRBWRADDRU0": "BRAM_FIFO36_ADDRBWRADDRU0", - "ADDRBWRADDRU1": "BRAM_FIFO36_ADDRBWRADDRU1", - "ADDRBWRADDRU10": "BRAM_FIFO36_ADDRBWRADDRU10", - "ADDRBWRADDRU11": "BRAM_FIFO36_ADDRBWRADDRU11", - "ADDRBWRADDRU12": "BRAM_FIFO36_ADDRBWRADDRU12", - "ADDRBWRADDRU13": "BRAM_FIFO36_ADDRBWRADDRU13", - "ADDRBWRADDRU14": "BRAM_FIFO36_ADDRBWRADDRU14", - "ADDRBWRADDRU2": "BRAM_FIFO36_ADDRBWRADDRU2", - "ADDRBWRADDRU3": "BRAM_FIFO36_ADDRBWRADDRU3", - "ADDRBWRADDRU4": "BRAM_FIFO36_ADDRBWRADDRU4", - "ADDRBWRADDRU5": "BRAM_FIFO36_ADDRBWRADDRU5", - "ADDRBWRADDRU6": "BRAM_FIFO36_ADDRBWRADDRU6", - "ADDRBWRADDRU7": "BRAM_FIFO36_ADDRBWRADDRU7", - "ADDRBWRADDRU8": "BRAM_FIFO36_ADDRBWRADDRU8", - "ADDRBWRADDRU9": "BRAM_FIFO36_ADDRBWRADDRU9", - "ALMOSTEMPTY": "BRAM_FIFO36_ALMOSTEMPTY", - "ALMOSTFULL": "BRAM_FIFO36_ALMOSTFULL", - "CASCADEINA": "BRAM_FIFO36_CASCADEINA", - "CASCADEINB": "BRAM_FIFO36_CASCADEINB", - "CASCADEOUTA": "BRAM_FIFO36_CASCADEOUTA", - "CASCADEOUTB": "BRAM_FIFO36_CASCADEOUTB", - "CLKARDCLKL": "BRAM_FIFO36_CLKARDCLKL", - "CLKARDCLKU": "BRAM_FIFO36_CLKARDCLKU", - "CLKBWRCLKL": "BRAM_FIFO36_CLKBWRCLKL", - "CLKBWRCLKU": "BRAM_FIFO36_CLKBWRCLKU", - "DBITERR": "BRAM_FIFO36_DBITERR", - "DIADI0": "BRAM_FIFO36_DIADIL0", - "DIADI1": "BRAM_FIFO36_DIADIU0", - "DIADI10": "BRAM_FIFO36_DIADIL5", - "DIADI11": "BRAM_FIFO36_DIADIU5", - "DIADI12": "BRAM_FIFO36_DIADIL6", - "DIADI13": "BRAM_FIFO36_DIADIU6", - "DIADI14": "BRAM_FIFO36_DIADIL7", - "DIADI15": "BRAM_FIFO36_DIADIU7", - "DIADI16": "BRAM_FIFO36_DIADIL8", - "DIADI17": "BRAM_FIFO36_DIADIU8", - "DIADI18": "BRAM_FIFO36_DIADIL9", - "DIADI19": "BRAM_FIFO36_DIADIU9", - "DIADI2": "BRAM_FIFO36_DIADIL1", - "DIADI20": "BRAM_FIFO36_DIADIL10", - "DIADI21": "BRAM_FIFO36_DIADIU10", - "DIADI22": "BRAM_FIFO36_DIADIL11", - "DIADI23": "BRAM_FIFO36_DIADIU11", - "DIADI24": "BRAM_FIFO36_DIADIL12", - "DIADI25": "BRAM_FIFO36_DIADIU12", - "DIADI26": "BRAM_FIFO36_DIADIL13", - "DIADI27": "BRAM_FIFO36_DIADIU13", - "DIADI28": "BRAM_FIFO36_DIADIL14", - "DIADI29": "BRAM_FIFO36_DIADIU14", - "DIADI3": "BRAM_FIFO36_DIADIU1", - "DIADI30": "BRAM_FIFO36_DIADIL15", - "DIADI31": "BRAM_FIFO36_DIADIU15", - "DIADI4": "BRAM_FIFO36_DIADIL2", - "DIADI5": "BRAM_FIFO36_DIADIU2", - "DIADI6": "BRAM_FIFO36_DIADIL3", - "DIADI7": "BRAM_FIFO36_DIADIU3", - "DIADI8": "BRAM_FIFO36_DIADIL4", - "DIADI9": "BRAM_FIFO36_DIADIU4", - "DIBDI0": "BRAM_FIFO36_DIBDIL0", - "DIBDI1": "BRAM_FIFO36_DIBDIU0", - "DIBDI10": "BRAM_FIFO36_DIBDIL5", - "DIBDI11": "BRAM_FIFO36_DIBDIU5", - "DIBDI12": "BRAM_FIFO36_DIBDIL6", - "DIBDI13": "BRAM_FIFO36_DIBDIU6", - "DIBDI14": "BRAM_FIFO36_DIBDIL7", - "DIBDI15": "BRAM_FIFO36_DIBDIU7", - "DIBDI16": "BRAM_FIFO36_DIBDIL8", - "DIBDI17": "BRAM_FIFO36_DIBDIU8", - "DIBDI18": "BRAM_FIFO36_DIBDIL9", - "DIBDI19": "BRAM_FIFO36_DIBDIU9", - "DIBDI2": "BRAM_FIFO36_DIBDIL1", - "DIBDI20": "BRAM_FIFO36_DIBDIL10", - "DIBDI21": "BRAM_FIFO36_DIBDIU10", - "DIBDI22": "BRAM_FIFO36_DIBDIL11", - "DIBDI23": "BRAM_FIFO36_DIBDIU11", - "DIBDI24": "BRAM_FIFO36_DIBDIL12", - "DIBDI25": "BRAM_FIFO36_DIBDIU12", - "DIBDI26": "BRAM_FIFO36_DIBDIL13", - "DIBDI27": "BRAM_FIFO36_DIBDIU13", - "DIBDI28": "BRAM_FIFO36_DIBDIL14", - "DIBDI29": "BRAM_FIFO36_DIBDIU14", - "DIBDI3": "BRAM_FIFO36_DIBDIU1", - "DIBDI30": "BRAM_FIFO36_DIBDIL15", - "DIBDI31": "BRAM_FIFO36_DIBDIU15", - "DIBDI4": "BRAM_FIFO36_DIBDIL2", - "DIBDI5": "BRAM_FIFO36_DIBDIU2", - "DIBDI6": "BRAM_FIFO36_DIBDIL3", - "DIBDI7": "BRAM_FIFO36_DIBDIU3", - "DIBDI8": "BRAM_FIFO36_DIBDIL4", - "DIBDI9": "BRAM_FIFO36_DIBDIU4", - "DIPADIP0": "BRAM_FIFO36_DIPADIPL0", - "DIPADIP1": "BRAM_FIFO36_DIPADIPU0", - "DIPADIP2": "BRAM_FIFO36_DIPADIPL1", - "DIPADIP3": "BRAM_FIFO36_DIPADIPU1", - "DIPBDIP0": "BRAM_FIFO36_DIPBDIPL0", - "DIPBDIP1": "BRAM_FIFO36_DIPBDIPU0", - "DIPBDIP2": "BRAM_FIFO36_DIPBDIPL1", - "DIPBDIP3": "BRAM_FIFO36_DIPBDIPU1", - "DOADO0": "BRAM_FIFO36_DOADOL0", - "DOADO1": "BRAM_FIFO36_DOADOU0", - "DOADO10": "BRAM_FIFO36_DOADOL5", - "DOADO11": "BRAM_FIFO36_DOADOU5", - "DOADO12": "BRAM_FIFO36_DOADOL6", - "DOADO13": "BRAM_FIFO36_DOADOU6", - "DOADO14": "BRAM_FIFO36_DOADOL7", - "DOADO15": "BRAM_FIFO36_DOADOU7", - "DOADO16": "BRAM_FIFO36_DOADOL8", - "DOADO17": "BRAM_FIFO36_DOADOU8", - "DOADO18": "BRAM_FIFO36_DOADOL9", - "DOADO19": "BRAM_FIFO36_DOADOU9", - "DOADO2": "BRAM_FIFO36_DOADOL1", - "DOADO20": "BRAM_FIFO36_DOADOL10", - "DOADO21": "BRAM_FIFO36_DOADOU10", - "DOADO22": "BRAM_FIFO36_DOADOL11", - "DOADO23": "BRAM_FIFO36_DOADOU11", - "DOADO24": "BRAM_FIFO36_DOADOL12", - "DOADO25": "BRAM_FIFO36_DOADOU12", - "DOADO26": "BRAM_FIFO36_DOADOL13", - "DOADO27": "BRAM_FIFO36_DOADOU13", - "DOADO28": "BRAM_FIFO36_DOADOL14", - "DOADO29": "BRAM_FIFO36_DOADOU14", - "DOADO3": "BRAM_FIFO36_DOADOU1", - "DOADO30": "BRAM_FIFO36_DOADOL15", - "DOADO31": "BRAM_FIFO36_DOADOU15", - "DOADO4": "BRAM_FIFO36_DOADOL2", - "DOADO5": "BRAM_FIFO36_DOADOU2", - "DOADO6": "BRAM_FIFO36_DOADOL3", - "DOADO7": "BRAM_FIFO36_DOADOU3", - "DOADO8": "BRAM_FIFO36_DOADOL4", - "DOADO9": "BRAM_FIFO36_DOADOU4", - "DOBDO0": "BRAM_FIFO36_DOBDOL0", - "DOBDO1": "BRAM_FIFO36_DOBDOU0", - "DOBDO10": "BRAM_FIFO36_DOBDOL5", - "DOBDO11": "BRAM_FIFO36_DOBDOU5", - "DOBDO12": "BRAM_FIFO36_DOBDOL6", - "DOBDO13": "BRAM_FIFO36_DOBDOU6", - "DOBDO14": "BRAM_FIFO36_DOBDOL7", - "DOBDO15": "BRAM_FIFO36_DOBDOU7", - "DOBDO16": "BRAM_FIFO36_DOBDOL8", - "DOBDO17": "BRAM_FIFO36_DOBDOU8", - "DOBDO18": "BRAM_FIFO36_DOBDOL9", - "DOBDO19": "BRAM_FIFO36_DOBDOU9", - "DOBDO2": "BRAM_FIFO36_DOBDOL1", - "DOBDO20": "BRAM_FIFO36_DOBDOL10", - "DOBDO21": "BRAM_FIFO36_DOBDOU10", - "DOBDO22": "BRAM_FIFO36_DOBDOL11", - "DOBDO23": "BRAM_FIFO36_DOBDOU11", - "DOBDO24": "BRAM_FIFO36_DOBDOL12", - "DOBDO25": "BRAM_FIFO36_DOBDOU12", - "DOBDO26": "BRAM_FIFO36_DOBDOL13", - "DOBDO27": "BRAM_FIFO36_DOBDOU13", - "DOBDO28": "BRAM_FIFO36_DOBDOL14", - "DOBDO29": "BRAM_FIFO36_DOBDOU14", - "DOBDO3": "BRAM_FIFO36_DOBDOU1", - "DOBDO30": "BRAM_FIFO36_DOBDOL15", - "DOBDO31": "BRAM_FIFO36_DOBDOU15", - "DOBDO4": "BRAM_FIFO36_DOBDOL2", - "DOBDO5": "BRAM_FIFO36_DOBDOU2", - "DOBDO6": "BRAM_FIFO36_DOBDOL3", - "DOBDO7": "BRAM_FIFO36_DOBDOU3", - "DOBDO8": "BRAM_FIFO36_DOBDOL4", - "DOBDO9": "BRAM_FIFO36_DOBDOU4", - "DOPADOP0": "BRAM_FIFO36_DOPADOPL0", - "DOPADOP1": "BRAM_FIFO36_DOPADOPU0", - "DOPADOP2": "BRAM_FIFO36_DOPADOPL1", - "DOPADOP3": "BRAM_FIFO36_DOPADOPU1", - "DOPBDOP0": "BRAM_FIFO36_DOPBDOPL0", - "DOPBDOP1": "BRAM_FIFO36_DOPBDOPU0", - "DOPBDOP2": "BRAM_FIFO36_DOPBDOPL1", - "DOPBDOP3": "BRAM_FIFO36_DOPBDOPU1", - "ECCPARITY0": "BRAM_FIFO36_ECCPARITY0", - "ECCPARITY1": "BRAM_FIFO36_ECCPARITY1", - "ECCPARITY2": "BRAM_FIFO36_ECCPARITY2", - "ECCPARITY3": "BRAM_FIFO36_ECCPARITY3", - "ECCPARITY4": "BRAM_FIFO36_ECCPARITY4", - "ECCPARITY5": "BRAM_FIFO36_ECCPARITY5", - "ECCPARITY6": "BRAM_FIFO36_ECCPARITY6", - "ECCPARITY7": "BRAM_FIFO36_ECCPARITY7", - "EMPTY": "BRAM_FIFO36_EMPTY", - "ENARDENL": "BRAM_FIFO36_ENARDENL", - "ENARDENU": "BRAM_FIFO36_ENARDENU", - "ENBWRENL": "BRAM_FIFO36_ENBWRENL", - "ENBWRENU": "BRAM_FIFO36_ENBWRENU", - "FULL": "BRAM_FIFO36_FULL", - "INJECTDBITERR": "BRAM_FIFO36_INJECTDBITERR", - "INJECTSBITERR": "BRAM_FIFO36_INJECTSBITERR", - "RDCOUNT0": "BRAM_FIFO36_RDCOUNT0", - "RDCOUNT1": "BRAM_FIFO36_RDCOUNT1", - "RDCOUNT10": "BRAM_FIFO36_RDCOUNT10", - "RDCOUNT11": "BRAM_FIFO36_RDCOUNT11", - "RDCOUNT12": "BRAM_FIFO36_RDCOUNT12", - "RDCOUNT2": "BRAM_FIFO36_RDCOUNT2", - "RDCOUNT3": "BRAM_FIFO36_RDCOUNT3", - "RDCOUNT4": "BRAM_FIFO36_RDCOUNT4", - "RDCOUNT5": "BRAM_FIFO36_RDCOUNT5", - "RDCOUNT6": "BRAM_FIFO36_RDCOUNT6", - "RDCOUNT7": "BRAM_FIFO36_RDCOUNT7", - "RDCOUNT8": "BRAM_FIFO36_RDCOUNT8", - "RDCOUNT9": "BRAM_FIFO36_RDCOUNT9", - "RDERR": "BRAM_FIFO36_RDERR", - "REGCEAREGCEL": "BRAM_FIFO36_REGCEAREGCEL", - "REGCEAREGCEU": "BRAM_FIFO36_REGCEAREGCEU", - "REGCEBL": "BRAM_FIFO36_REGCEBL", - "REGCEBU": "BRAM_FIFO36_REGCEBU", - "REGCLKARDRCLKL": "BRAM_FIFO36_REGCLKARDRCLKL", - "REGCLKARDRCLKU": "BRAM_FIFO36_REGCLKARDRCLKU", - "REGCLKBL": "BRAM_FIFO36_REGCLKBL", - "REGCLKBU": "BRAM_FIFO36_REGCLKBU", - "RSTRAMARSTRAMLRST": "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "RSTRAMARSTRAMU": "BRAM_FIFO36_RSTRAMARSTRAMU", - "RSTRAMBL": "BRAM_FIFO36_RSTRAMBL", - "RSTRAMBU": "BRAM_FIFO36_RSTRAMBU", - "RSTREGARSTREGL": "BRAM_FIFO36_RSTREGARSTREGL", - "RSTREGARSTREGU": "BRAM_FIFO36_RSTREGARSTREGU", - "RSTREGBL": "BRAM_FIFO36_RSTREGBL", - "RSTREGBU": "BRAM_FIFO36_RSTREGBU", - "SBITERR": "BRAM_FIFO36_SBITERR", - "TSTBRAMRST": "BRAM_FIFO36_TSTBRAMRST", - "TSTCNT0": "BRAM_FIFO36_TSTCNT0", - "TSTCNT1": "BRAM_FIFO36_TSTCNT1", - "TSTCNT10": "BRAM_FIFO36_TSTCNT10", - "TSTCNT11": "BRAM_FIFO36_TSTCNT11", - "TSTCNT12": "BRAM_FIFO36_TSTCNT12", - "TSTCNT2": "BRAM_FIFO36_TSTCNT2", - "TSTCNT3": "BRAM_FIFO36_TSTCNT3", - "TSTCNT4": "BRAM_FIFO36_TSTCNT4", - "TSTCNT5": "BRAM_FIFO36_TSTCNT5", - "TSTCNT6": "BRAM_FIFO36_TSTCNT6", - "TSTCNT7": "BRAM_FIFO36_TSTCNT7", - "TSTCNT8": "BRAM_FIFO36_TSTCNT8", - "TSTCNT9": "BRAM_FIFO36_TSTCNT9", - "TSTFLAGIN": "BRAM_FIFO36_TSTFLAGIN", - "TSTIN0": "BRAM_FIFO36_TSTIN0", - "TSTIN1": "BRAM_FIFO36_TSTIN1", - "TSTIN2": "BRAM_FIFO36_TSTIN2", - "TSTIN3": "BRAM_FIFO36_TSTIN3", - "TSTIN4": "BRAM_FIFO36_TSTIN4", - "TSTOFF": "BRAM_FIFO36_TSTOFF", - "TSTOUT0": "BRAM_FIFO36_TSTOUT0", - "TSTOUT1": "BRAM_FIFO36_TSTOUT1", - "TSTOUT2": "BRAM_FIFO36_TSTOUT2", - "TSTOUT3": "BRAM_FIFO36_TSTOUT3", - "TSTOUT4": "BRAM_FIFO36_TSTOUT4", - "TSTRDCNTOFF": "BRAM_FIFO36_TSTRDCNTOFF", - "TSTRDOS0": "BRAM_FIFO36_TSTRDOS0", - "TSTRDOS1": "BRAM_FIFO36_TSTRDOS1", - "TSTRDOS10": "BRAM_FIFO36_TSTRDOS10", - "TSTRDOS11": "BRAM_FIFO36_TSTRDOS11", - "TSTRDOS12": "BRAM_FIFO36_TSTRDOS12", - "TSTRDOS2": "BRAM_FIFO36_TSTRDOS2", - "TSTRDOS3": "BRAM_FIFO36_TSTRDOS3", - "TSTRDOS4": "BRAM_FIFO36_TSTRDOS4", - "TSTRDOS5": "BRAM_FIFO36_TSTRDOS5", - "TSTRDOS6": "BRAM_FIFO36_TSTRDOS6", - "TSTRDOS7": "BRAM_FIFO36_TSTRDOS7", - "TSTRDOS8": "BRAM_FIFO36_TSTRDOS8", - "TSTRDOS9": "BRAM_FIFO36_TSTRDOS9", - "TSTWRCNTOFF": "BRAM_FIFO36_TSTWRCNTOFF", - "TSTWROS0": "BRAM_FIFO36_TSTWROS0", - "TSTWROS1": "BRAM_FIFO36_TSTWROS1", - "TSTWROS10": "BRAM_FIFO36_TSTWROS10", - "TSTWROS11": "BRAM_FIFO36_TSTWROS11", - "TSTWROS12": "BRAM_FIFO36_TSTWROS12", - "TSTWROS2": "BRAM_FIFO36_TSTWROS2", - "TSTWROS3": "BRAM_FIFO36_TSTWROS3", - "TSTWROS4": "BRAM_FIFO36_TSTWROS4", - "TSTWROS5": "BRAM_FIFO36_TSTWROS5", - "TSTWROS6": "BRAM_FIFO36_TSTWROS6", - "TSTWROS7": "BRAM_FIFO36_TSTWROS7", - "TSTWROS8": "BRAM_FIFO36_TSTWROS8", - "TSTWROS9": "BRAM_FIFO36_TSTWROS9", - "WEAL0": "BRAM_FIFO36_WEAL0", - "WEAL1": "BRAM_FIFO36_WEAL1", - "WEAL2": "BRAM_FIFO36_WEAL2", - "WEAL3": "BRAM_FIFO36_WEAL3", - "WEAU0": "BRAM_FIFO36_WEAU0", - "WEAU1": "BRAM_FIFO36_WEAU1", - "WEAU2": "BRAM_FIFO36_WEAU2", - "WEAU3": "BRAM_FIFO36_WEAU3", - "WEBWEL0": "BRAM_FIFO36_WEBWEL0", - "WEBWEL1": "BRAM_FIFO36_WEBWEL1", - "WEBWEL2": "BRAM_FIFO36_WEBWEL2", - "WEBWEL3": "BRAM_FIFO36_WEBWEL3", - "WEBWEL4": "BRAM_FIFO36_WEBWEL4", - "WEBWEL5": "BRAM_FIFO36_WEBWEL5", - "WEBWEL6": "BRAM_FIFO36_WEBWEL6", - "WEBWEL7": "BRAM_FIFO36_WEBWEL7", - "WEBWEU0": "BRAM_FIFO36_WEBWEU0", - "WEBWEU1": "BRAM_FIFO36_WEBWEU1", - "WEBWEU2": "BRAM_FIFO36_WEBWEU2", - "WEBWEU3": "BRAM_FIFO36_WEBWEU3", - "WEBWEU4": "BRAM_FIFO36_WEBWEU4", - "WEBWEU5": "BRAM_FIFO36_WEBWEU5", - "WEBWEU6": "BRAM_FIFO36_WEBWEU6", - "WEBWEU7": "BRAM_FIFO36_WEBWEU7", - "WRCOUNT0": "BRAM_FIFO36_WRCOUNT0", - "WRCOUNT1": "BRAM_FIFO36_WRCOUNT1", - "WRCOUNT10": "BRAM_FIFO36_WRCOUNT10", - "WRCOUNT11": "BRAM_FIFO36_WRCOUNT11", - "WRCOUNT12": "BRAM_FIFO36_WRCOUNT12", - "WRCOUNT2": "BRAM_FIFO36_WRCOUNT2", - "WRCOUNT3": "BRAM_FIFO36_WRCOUNT3", - "WRCOUNT4": "BRAM_FIFO36_WRCOUNT4", - "WRCOUNT5": "BRAM_FIFO36_WRCOUNT5", - "WRCOUNT6": "BRAM_FIFO36_WRCOUNT6", - "WRCOUNT7": "BRAM_FIFO36_WRCOUNT7", - "WRCOUNT8": "BRAM_FIFO36_WRCOUNT8", - "WRCOUNT9": "BRAM_FIFO36_WRCOUNT9", - "WRERR": "BRAM_FIFO36_WRERR" + "ADDRARDADDRL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL0" + }, + "ADDRARDADDRL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL1" + }, + "ADDRARDADDRL10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL10" + }, + "ADDRARDADDRL11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL11" + }, + "ADDRARDADDRL12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL12" + }, + "ADDRARDADDRL13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL13" + }, + "ADDRARDADDRL14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL14" + }, + "ADDRARDADDRL15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL15" + }, + "ADDRARDADDRL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL2" + }, + "ADDRARDADDRL3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL3" + }, + "ADDRARDADDRL4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL4" + }, + "ADDRARDADDRL5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL5" + }, + "ADDRARDADDRL6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL6" + }, + "ADDRARDADDRL7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL7" + }, + "ADDRARDADDRL8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL8" + }, + "ADDRARDADDRL9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL9" + }, + "ADDRARDADDRU0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU0" + }, + "ADDRARDADDRU1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU1" + }, + "ADDRARDADDRU10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU10" + }, + "ADDRARDADDRU11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU11" + }, + "ADDRARDADDRU12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU12" + }, + "ADDRARDADDRU13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU13" + }, + "ADDRARDADDRU14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU14" + }, + "ADDRARDADDRU2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU2" + }, + "ADDRARDADDRU3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU3" + }, + "ADDRARDADDRU4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU4" + }, + "ADDRARDADDRU5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU5" + }, + "ADDRARDADDRU6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU6" + }, + "ADDRARDADDRU7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU7" + }, + "ADDRARDADDRU8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU8" + }, + "ADDRARDADDRU9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU9" + }, + "ADDRBWRADDRL0": { + "cap": "0.000", + "delay": [ + "0.000", + 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"BRAM_FIFO18_ADDRARDADDR0", - "ADDRARDADDR1": "BRAM_FIFO18_ADDRARDADDR1", - "ADDRARDADDR10": "BRAM_FIFO18_ADDRARDADDR10", - "ADDRARDADDR11": "BRAM_FIFO18_ADDRARDADDR11", - "ADDRARDADDR12": "BRAM_FIFO18_ADDRARDADDR12", - "ADDRARDADDR13": "BRAM_FIFO18_ADDRARDADDR13", - "ADDRARDADDR2": "BRAM_FIFO18_ADDRARDADDR2", - "ADDRARDADDR3": "BRAM_FIFO18_ADDRARDADDR3", - "ADDRARDADDR4": "BRAM_FIFO18_ADDRARDADDR4", - "ADDRARDADDR5": "BRAM_FIFO18_ADDRARDADDR5", - "ADDRARDADDR6": "BRAM_FIFO18_ADDRARDADDR6", - "ADDRARDADDR7": "BRAM_FIFO18_ADDRARDADDR7", - "ADDRARDADDR8": "BRAM_FIFO18_ADDRARDADDR8", - "ADDRARDADDR9": "BRAM_FIFO18_ADDRARDADDR9", - "ADDRATIEHIGH0": "BRAM_FIFO18_ADDRATIEHIGH0", - "ADDRATIEHIGH1": "BRAM_FIFO18_ADDRATIEHIGH1", - "ADDRBTIEHIGH0": "BRAM_FIFO18_ADDRBTIEHIGH0", - "ADDRBTIEHIGH1": "BRAM_FIFO18_ADDRBTIEHIGH1", - "ADDRBWRADDR0": "BRAM_FIFO18_ADDRBWRADDR0", - "ADDRBWRADDR1": "BRAM_FIFO18_ADDRBWRADDR1", - "ADDRBWRADDR10": "BRAM_FIFO18_ADDRBWRADDR10", - "ADDRBWRADDR11": "BRAM_FIFO18_ADDRBWRADDR11", - "ADDRBWRADDR12": "BRAM_FIFO18_ADDRBWRADDR12", - "ADDRBWRADDR13": "BRAM_FIFO18_ADDRBWRADDR13", - "ADDRBWRADDR2": "BRAM_FIFO18_ADDRBWRADDR2", - "ADDRBWRADDR3": "BRAM_FIFO18_ADDRBWRADDR3", - "ADDRBWRADDR4": "BRAM_FIFO18_ADDRBWRADDR4", - "ADDRBWRADDR5": "BRAM_FIFO18_ADDRBWRADDR5", - "ADDRBWRADDR6": "BRAM_FIFO18_ADDRBWRADDR6", - "ADDRBWRADDR7": "BRAM_FIFO18_ADDRBWRADDR7", - "ADDRBWRADDR8": "BRAM_FIFO18_ADDRBWRADDR8", - "ADDRBWRADDR9": "BRAM_FIFO18_ADDRBWRADDR9", - "ALMOSTEMPTY": "BRAM_FIFO18_ALMOSTEMPTY", - "ALMOSTFULL": "BRAM_FIFO18_ALMOSTFULL", - "DIADI0": "BRAM_FIFO18_DIADI0", - "DIADI1": "BRAM_FIFO18_DIADI1", - "DIADI10": "BRAM_FIFO18_DIADI10", - "DIADI11": "BRAM_FIFO18_DIADI11", - "DIADI12": "BRAM_FIFO18_DIADI12", - "DIADI13": "BRAM_FIFO18_DIADI13", - "DIADI14": "BRAM_FIFO18_DIADI14", - "DIADI15": "BRAM_FIFO18_DIADI15", - "DIADI2": "BRAM_FIFO18_DIADI2", - "DIADI3": "BRAM_FIFO18_DIADI3", - "DIADI4": "BRAM_FIFO18_DIADI4", - "DIADI5": "BRAM_FIFO18_DIADI5", - "DIADI6": "BRAM_FIFO18_DIADI6", - "DIADI7": "BRAM_FIFO18_DIADI7", - "DIADI8": "BRAM_FIFO18_DIADI8", - "DIADI9": "BRAM_FIFO18_DIADI9", - "DIBDI0": "BRAM_FIFO18_DIBDI0", - "DIBDI1": "BRAM_FIFO18_DIBDI1", - "DIBDI10": "BRAM_FIFO18_DIBDI10", - "DIBDI11": "BRAM_FIFO18_DIBDI11", - "DIBDI12": "BRAM_FIFO18_DIBDI12", - "DIBDI13": "BRAM_FIFO18_DIBDI13", - "DIBDI14": "BRAM_FIFO18_DIBDI14", - "DIBDI15": "BRAM_FIFO18_DIBDI15", - "DIBDI2": "BRAM_FIFO18_DIBDI2", - "DIBDI3": "BRAM_FIFO18_DIBDI3", - "DIBDI4": "BRAM_FIFO18_DIBDI4", - "DIBDI5": "BRAM_FIFO18_DIBDI5", - "DIBDI6": "BRAM_FIFO18_DIBDI6", - "DIBDI7": "BRAM_FIFO18_DIBDI7", - "DIBDI8": "BRAM_FIFO18_DIBDI8", - "DIBDI9": "BRAM_FIFO18_DIBDI9", - "DIPADIP0": "BRAM_FIFO18_DIPADIP0", - "DIPADIP1": "BRAM_FIFO18_DIPADIP1", - "DIPBDIP0": "BRAM_FIFO18_DIPBDIP0", - "DIPBDIP1": "BRAM_FIFO18_DIPBDIP1", - "DO0": "BRAM_FIFO18_DOADO0", - "DO1": "BRAM_FIFO18_DOADO1", - "DO10": "BRAM_FIFO18_DOADO10", - "DO11": "BRAM_FIFO18_DOADO11", - "DO12": "BRAM_FIFO18_DOADO12", - "DO13": "BRAM_FIFO18_DOADO13", - "DO14": "BRAM_FIFO18_DOADO14", - "DO15": "BRAM_FIFO18_DOADO15", - "DO16": "BRAM_FIFO18_DOBDO0", - "DO17": "BRAM_FIFO18_DOBDO1", - "DO18": "BRAM_FIFO18_DOBDO2", - "DO19": "BRAM_FIFO18_DOBDO3", - "DO2": "BRAM_FIFO18_DOADO2", - "DO20": "BRAM_FIFO18_DOBDO4", - "DO21": "BRAM_FIFO18_DOBDO5", - "DO22": "BRAM_FIFO18_DOBDO6", - "DO23": "BRAM_FIFO18_DOBDO7", - "DO24": "BRAM_FIFO18_DOBDO8", - "DO25": "BRAM_FIFO18_DOBDO9", - "DO26": "BRAM_FIFO18_DOBDO10", - "DO27": "BRAM_FIFO18_DOBDO11", - "DO28": "BRAM_FIFO18_DOBDO12", - "DO29": "BRAM_FIFO18_DOBDO13", - "DO3": "BRAM_FIFO18_DOADO3", - "DO30": "BRAM_FIFO18_DOBDO14", - "DO31": "BRAM_FIFO18_DOBDO15", - "DO4": "BRAM_FIFO18_DOADO4", - "DO5": "BRAM_FIFO18_DOADO5", - "DO6": "BRAM_FIFO18_DOADO6", - "DO7": "BRAM_FIFO18_DOADO7", - "DO8": "BRAM_FIFO18_DOADO8", - "DO9": "BRAM_FIFO18_DOADO9", - "DOP0": "BRAM_FIFO18_DOPADOP0", - "DOP1": "BRAM_FIFO18_DOPADOP1", - "DOP2": "BRAM_FIFO18_DOPBDOP0", - "DOP3": "BRAM_FIFO18_DOPBDOP1", - "EMPTY": "BRAM_FIFO18_EMPTY", - "FULL": "BRAM_FIFO18_FULL", - "RDCLK": "BRAM_FIFO18_CLKARDCLK", - "RDCOUNT0": "BRAM_FIFO18_RDCOUNT0", - "RDCOUNT1": "BRAM_FIFO18_RDCOUNT1", - "RDCOUNT10": "BRAM_FIFO18_RDCOUNT10", - "RDCOUNT11": "BRAM_FIFO18_RDCOUNT11", - "RDCOUNT2": "BRAM_FIFO18_RDCOUNT2", - "RDCOUNT3": "BRAM_FIFO18_RDCOUNT3", - "RDCOUNT4": "BRAM_FIFO18_RDCOUNT4", - "RDCOUNT5": "BRAM_FIFO18_RDCOUNT5", - "RDCOUNT6": "BRAM_FIFO18_RDCOUNT6", - "RDCOUNT7": "BRAM_FIFO18_RDCOUNT7", - "RDCOUNT8": "BRAM_FIFO18_RDCOUNT8", - "RDCOUNT9": "BRAM_FIFO18_RDCOUNT9", - "RDEN": "BRAM_FIFO18_ENARDEN", - "RDERR": "BRAM_FIFO18_RDERR", - "RDRCLK": "BRAM_FIFO18_REGCLKARDRCLK", - "REGCE": "BRAM_FIFO18_REGCEAREGCE", - "REGCEB": "BRAM_FIFO18_REGCEB", - "REGCLKB": "BRAM_FIFO18_REGCLKB", - "RST": "BRAM_FIFO18_RSTRAMARSTRAM", - "RSTRAMB": "BRAM_FIFO18_RSTRAMB", - "RSTREG": "BRAM_FIFO18_RSTREGARSTREG", - "RSTREGB": "BRAM_FIFO18_RSTREGB", - "WEA0": "BRAM_FIFO18_WEA0", - "WEA1": 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"WRCOUNT7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT7" + }, + "WRCOUNT8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT8" + }, + "WRCOUNT9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT9" + }, + "WRERR": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRERR" + } }, "type": "RAMB18E1", "x_coord": 0, @@ -7521,2314 +26463,6136 @@ } ], "tile_type": "BRAM_L", - "wires": [ - "BRAM_ADDRARDADDRL0", - "BRAM_ADDRARDADDRL1", - "BRAM_ADDRARDADDRL10", - "BRAM_ADDRARDADDRL11", - "BRAM_ADDRARDADDRL12", - "BRAM_ADDRARDADDRL13", - "BRAM_ADDRARDADDRL14", - "BRAM_ADDRARDADDRL2", - "BRAM_ADDRARDADDRL3", - "BRAM_ADDRARDADDRL4", - "BRAM_ADDRARDADDRL5", - "BRAM_ADDRARDADDRL6", - "BRAM_ADDRARDADDRL7", - "BRAM_ADDRARDADDRL8", - "BRAM_ADDRARDADDRL9", - "BRAM_ADDRARDADDRU0", - "BRAM_ADDRARDADDRU1", - "BRAM_ADDRARDADDRU10", - "BRAM_ADDRARDADDRU11", - "BRAM_ADDRARDADDRU12", - "BRAM_ADDRARDADDRU13", - "BRAM_ADDRARDADDRU14", - "BRAM_ADDRARDADDRU2", - "BRAM_ADDRARDADDRU3", - "BRAM_ADDRARDADDRU4", - "BRAM_ADDRARDADDRU5", - "BRAM_ADDRARDADDRU6", - "BRAM_ADDRARDADDRU7", - "BRAM_ADDRARDADDRU8", - "BRAM_ADDRARDADDRU9", - "BRAM_ADDRBWRADDRL0", - "BRAM_ADDRBWRADDRL1", - "BRAM_ADDRBWRADDRL10", - "BRAM_ADDRBWRADDRL11", - "BRAM_ADDRBWRADDRL12", - "BRAM_ADDRBWRADDRL13", - "BRAM_ADDRBWRADDRL14", - "BRAM_ADDRBWRADDRL2", - "BRAM_ADDRBWRADDRL3", - "BRAM_ADDRBWRADDRL4", - "BRAM_ADDRBWRADDRL5", - "BRAM_ADDRBWRADDRL6", - "BRAM_ADDRBWRADDRL7", - "BRAM_ADDRBWRADDRL8", - "BRAM_ADDRBWRADDRL9", - "BRAM_ADDRBWRADDRU0", - "BRAM_ADDRBWRADDRU1", - "BRAM_ADDRBWRADDRU10", - "BRAM_ADDRBWRADDRU11", - "BRAM_ADDRBWRADDRU12", - "BRAM_ADDRBWRADDRU13", - "BRAM_ADDRBWRADDRU14", - "BRAM_ADDRBWRADDRU2", - "BRAM_ADDRBWRADDRU3", - "BRAM_ADDRBWRADDRU4", - "BRAM_ADDRBWRADDRU5", - "BRAM_ADDRBWRADDRU6", - "BRAM_ADDRBWRADDRU7", - "BRAM_ADDRBWRADDRU8", - "BRAM_ADDRBWRADDRU9", - "BRAM_BLOCK_OUTS_L_B0_0", - "BRAM_BLOCK_OUTS_L_B0_1", - "BRAM_BLOCK_OUTS_L_B0_2", - "BRAM_BLOCK_OUTS_L_B0_3", - "BRAM_BLOCK_OUTS_L_B0_4", - "BRAM_BLOCK_OUTS_L_B1_0", - "BRAM_BLOCK_OUTS_L_B1_1", - "BRAM_BLOCK_OUTS_L_B1_2", - "BRAM_BLOCK_OUTS_L_B1_3", - "BRAM_BLOCK_OUTS_L_B1_4", - "BRAM_BLOCK_OUTS_L_B2_0", - "BRAM_BLOCK_OUTS_L_B2_1", - "BRAM_BLOCK_OUTS_L_B2_2", - "BRAM_BLOCK_OUTS_L_B2_3", - "BRAM_BLOCK_OUTS_L_B2_4", - "BRAM_BLOCK_OUTS_L_B3_0", - "BRAM_BLOCK_OUTS_L_B3_1", - "BRAM_BLOCK_OUTS_L_B3_2", - "BRAM_BLOCK_OUTS_L_B3_3", - "BRAM_BLOCK_OUTS_L_B3_4", - "BRAM_BYP0_0", - "BRAM_BYP0_1", - "BRAM_BYP0_2", - "BRAM_BYP0_3", - "BRAM_BYP0_4", - "BRAM_BYP1_0", - "BRAM_BYP1_1", - "BRAM_BYP1_2", - "BRAM_BYP1_3", - "BRAM_BYP1_4", - "BRAM_BYP2_0", - "BRAM_BYP2_1", - "BRAM_BYP2_2", - "BRAM_BYP2_3", - "BRAM_BYP2_4", - "BRAM_BYP3_0", - "BRAM_BYP3_1", - "BRAM_BYP3_2", - "BRAM_BYP3_3", - "BRAM_BYP3_4", - "BRAM_BYP4_0", - "BRAM_BYP4_1", - "BRAM_BYP4_2", - "BRAM_BYP4_3", - "BRAM_BYP4_4", - "BRAM_BYP5_0", - "BRAM_BYP5_1", - "BRAM_BYP5_2", - "BRAM_BYP5_3", - "BRAM_BYP5_4", - "BRAM_BYP6_0", - "BRAM_BYP6_1", - "BRAM_BYP6_2", - "BRAM_BYP6_3", - "BRAM_BYP6_4", - "BRAM_BYP7_0", - "BRAM_BYP7_1", - "BRAM_BYP7_2", - "BRAM_BYP7_3", - "BRAM_BYP7_4", - "BRAM_CASCINBOT_ADDRARDADDRU0", - "BRAM_CASCINBOT_ADDRARDADDRU1", - "BRAM_CASCINBOT_ADDRARDADDRU10", - "BRAM_CASCINBOT_ADDRARDADDRU11", - "BRAM_CASCINBOT_ADDRARDADDRU12", - "BRAM_CASCINBOT_ADDRARDADDRU13", - "BRAM_CASCINBOT_ADDRARDADDRU14", - "BRAM_CASCINBOT_ADDRARDADDRU2", - "BRAM_CASCINBOT_ADDRARDADDRU3", - "BRAM_CASCINBOT_ADDRARDADDRU4", - "BRAM_CASCINBOT_ADDRARDADDRU5", - "BRAM_CASCINBOT_ADDRARDADDRU6", - "BRAM_CASCINBOT_ADDRARDADDRU7", - "BRAM_CASCINBOT_ADDRARDADDRU8", - "BRAM_CASCINBOT_ADDRARDADDRU9", - "BRAM_CASCINBOT_ADDRBWRADDRU0", - "BRAM_CASCINBOT_ADDRBWRADDRU1", - "BRAM_CASCINBOT_ADDRBWRADDRU10", - "BRAM_CASCINBOT_ADDRBWRADDRU11", - "BRAM_CASCINBOT_ADDRBWRADDRU12", - "BRAM_CASCINBOT_ADDRBWRADDRU13", - "BRAM_CASCINBOT_ADDRBWRADDRU14", - "BRAM_CASCINBOT_ADDRBWRADDRU2", - "BRAM_CASCINBOT_ADDRBWRADDRU3", - "BRAM_CASCINBOT_ADDRBWRADDRU4", - "BRAM_CASCINBOT_ADDRBWRADDRU5", - "BRAM_CASCINBOT_ADDRBWRADDRU6", - "BRAM_CASCINBOT_ADDRBWRADDRU7", - "BRAM_CASCINBOT_ADDRBWRADDRU8", - "BRAM_CASCINBOT_ADDRBWRADDRU9", - "BRAM_CASCINTOP_ADDRARDADDRU0", - "BRAM_CASCINTOP_ADDRARDADDRU1", - "BRAM_CASCINTOP_ADDRARDADDRU10", - "BRAM_CASCINTOP_ADDRARDADDRU11", - "BRAM_CASCINTOP_ADDRARDADDRU12", - "BRAM_CASCINTOP_ADDRARDADDRU13", - "BRAM_CASCINTOP_ADDRARDADDRU14", - "BRAM_CASCINTOP_ADDRARDADDRU2", - "BRAM_CASCINTOP_ADDRARDADDRU3", - "BRAM_CASCINTOP_ADDRARDADDRU4", - "BRAM_CASCINTOP_ADDRARDADDRU5", - "BRAM_CASCINTOP_ADDRARDADDRU6", - "BRAM_CASCINTOP_ADDRARDADDRU7", - "BRAM_CASCINTOP_ADDRARDADDRU8", - "BRAM_CASCINTOP_ADDRARDADDRU9", - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "BRAM_CASCINTOP_ADDRBWRADDRU7", - "BRAM_CASCINTOP_ADDRBWRADDRU8", - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "BRAM_CASCOUT_ADDRARDADDRU0", - "BRAM_CASCOUT_ADDRARDADDRU1", - "BRAM_CASCOUT_ADDRARDADDRU10", - "BRAM_CASCOUT_ADDRARDADDRU11", - "BRAM_CASCOUT_ADDRARDADDRU12", - "BRAM_CASCOUT_ADDRARDADDRU13", - "BRAM_CASCOUT_ADDRARDADDRU14", - "BRAM_CASCOUT_ADDRARDADDRU2", - "BRAM_CASCOUT_ADDRARDADDRU3", - "BRAM_CASCOUT_ADDRARDADDRU4", - "BRAM_CASCOUT_ADDRARDADDRU5", - "BRAM_CASCOUT_ADDRARDADDRU6", - "BRAM_CASCOUT_ADDRARDADDRU7", - "BRAM_CASCOUT_ADDRARDADDRU8", - "BRAM_CASCOUT_ADDRARDADDRU9", - "BRAM_CASCOUT_ADDRBWRADDRU0", - "BRAM_CASCOUT_ADDRBWRADDRU1", - "BRAM_CASCOUT_ADDRBWRADDRU10", - "BRAM_CASCOUT_ADDRBWRADDRU11", - "BRAM_CASCOUT_ADDRBWRADDRU12", - "BRAM_CASCOUT_ADDRBWRADDRU13", - "BRAM_CASCOUT_ADDRBWRADDRU14", - "BRAM_CASCOUT_ADDRBWRADDRU2", - "BRAM_CASCOUT_ADDRBWRADDRU3", - "BRAM_CASCOUT_ADDRBWRADDRU4", - "BRAM_CASCOUT_ADDRBWRADDRU5", - "BRAM_CASCOUT_ADDRBWRADDRU6", - "BRAM_CASCOUT_ADDRBWRADDRU7", - "BRAM_CASCOUT_ADDRBWRADDRU8", - "BRAM_CASCOUT_ADDRBWRADDRU9", - "BRAM_CLK0_0", - "BRAM_CLK0_1", - "BRAM_CLK0_2", - "BRAM_CLK0_3", - "BRAM_CLK0_4", - "BRAM_CLK1_0", - "BRAM_CLK1_1", - "BRAM_CLK1_2", - "BRAM_CLK1_3", - "BRAM_CLK1_4", - "BRAM_CTRL0_0", - "BRAM_CTRL0_1", - "BRAM_CTRL0_2", - "BRAM_CTRL0_3", - "BRAM_CTRL0_4", - "BRAM_CTRL1_0", - "BRAM_CTRL1_1", - "BRAM_CTRL1_2", - "BRAM_CTRL1_3", - "BRAM_CTRL1_4", - "BRAM_EE2A0_0", - "BRAM_EE2A0_1", - "BRAM_EE2A0_2", - "BRAM_EE2A0_3", - "BRAM_EE2A0_4", - "BRAM_EE2A1_0", - "BRAM_EE2A1_1", - "BRAM_EE2A1_2", - "BRAM_EE2A1_3", - "BRAM_EE2A1_4", - "BRAM_EE2A2_0", - "BRAM_EE2A2_1", - "BRAM_EE2A2_2", - "BRAM_EE2A2_3", - "BRAM_EE2A2_4", - "BRAM_EE2A3_0", - "BRAM_EE2A3_1", - "BRAM_EE2A3_2", - "BRAM_EE2A3_3", - "BRAM_EE2A3_4", - "BRAM_EE2BEG0_0", - "BRAM_EE2BEG0_1", - "BRAM_EE2BEG0_2", - "BRAM_EE2BEG0_3", - "BRAM_EE2BEG0_4", - "BRAM_EE2BEG1_0", - "BRAM_EE2BEG1_1", - "BRAM_EE2BEG1_2", - "BRAM_EE2BEG1_3", - "BRAM_EE2BEG1_4", - "BRAM_EE2BEG2_0", - "BRAM_EE2BEG2_1", - "BRAM_EE2BEG2_2", - "BRAM_EE2BEG2_3", - "BRAM_EE2BEG2_4", - "BRAM_EE2BEG3_0", - "BRAM_EE2BEG3_1", - "BRAM_EE2BEG3_2", - "BRAM_EE2BEG3_3", - "BRAM_EE2BEG3_4", - "BRAM_EE4A0_0", - "BRAM_EE4A0_1", - "BRAM_EE4A0_2", - "BRAM_EE4A0_3", - "BRAM_EE4A0_4", - "BRAM_EE4A1_0", - "BRAM_EE4A1_1", - "BRAM_EE4A1_2", - "BRAM_EE4A1_3", - "BRAM_EE4A1_4", - "BRAM_EE4A2_0", - "BRAM_EE4A2_1", - "BRAM_EE4A2_2", - "BRAM_EE4A2_3", - "BRAM_EE4A2_4", - "BRAM_EE4A3_0", - "BRAM_EE4A3_1", - "BRAM_EE4A3_2", - "BRAM_EE4A3_3", - "BRAM_EE4A3_4", - "BRAM_EE4B0_0", - "BRAM_EE4B0_1", - "BRAM_EE4B0_2", - "BRAM_EE4B0_3", - "BRAM_EE4B0_4", - "BRAM_EE4B1_0", - "BRAM_EE4B1_1", - "BRAM_EE4B1_2", - "BRAM_EE4B1_3", - "BRAM_EE4B1_4", - "BRAM_EE4B2_0", - "BRAM_EE4B2_1", - "BRAM_EE4B2_2", - "BRAM_EE4B2_3", - "BRAM_EE4B2_4", - "BRAM_EE4B3_0", - "BRAM_EE4B3_1", - "BRAM_EE4B3_2", - "BRAM_EE4B3_3", - "BRAM_EE4B3_4", - "BRAM_EE4BEG0_0", - "BRAM_EE4BEG0_1", - "BRAM_EE4BEG0_2", - "BRAM_EE4BEG0_3", - "BRAM_EE4BEG0_4", - "BRAM_EE4BEG1_0", - "BRAM_EE4BEG1_1", - "BRAM_EE4BEG1_2", - "BRAM_EE4BEG1_3", - "BRAM_EE4BEG1_4", - "BRAM_EE4BEG2_0", - "BRAM_EE4BEG2_1", - "BRAM_EE4BEG2_2", - "BRAM_EE4BEG2_3", - "BRAM_EE4BEG2_4", - "BRAM_EE4BEG3_0", - "BRAM_EE4BEG3_1", - "BRAM_EE4BEG3_2", - "BRAM_EE4BEG3_3", - "BRAM_EE4BEG3_4", - "BRAM_EE4C0_0", - "BRAM_EE4C0_1", - "BRAM_EE4C0_2", - "BRAM_EE4C0_3", - "BRAM_EE4C0_4", - "BRAM_EE4C1_0", - "BRAM_EE4C1_1", - "BRAM_EE4C1_2", - "BRAM_EE4C1_3", - "BRAM_EE4C1_4", - "BRAM_EE4C2_0", - "BRAM_EE4C2_1", - "BRAM_EE4C2_2", - "BRAM_EE4C2_3", - "BRAM_EE4C2_4", - "BRAM_EE4C3_0", - "BRAM_EE4C3_1", - "BRAM_EE4C3_2", - "BRAM_EE4C3_3", - "BRAM_EE4C3_4", - "BRAM_EL1BEG0_0", - "BRAM_EL1BEG0_1", - "BRAM_EL1BEG0_2", - "BRAM_EL1BEG0_3", - "BRAM_EL1BEG0_4", - "BRAM_EL1BEG1_0", - "BRAM_EL1BEG1_1", - "BRAM_EL1BEG1_2", - "BRAM_EL1BEG1_3", - "BRAM_EL1BEG1_4", - "BRAM_EL1BEG2_0", - "BRAM_EL1BEG2_1", - "BRAM_EL1BEG2_2", - "BRAM_EL1BEG2_3", - "BRAM_EL1BEG2_4", - "BRAM_EL1BEG3_0", - "BRAM_EL1BEG3_1", - "BRAM_EL1BEG3_2", - "BRAM_EL1BEG3_3", - "BRAM_EL1BEG3_4", - "BRAM_ER1BEG0_0", - "BRAM_ER1BEG0_1", - "BRAM_ER1BEG0_2", - "BRAM_ER1BEG0_3", - "BRAM_ER1BEG0_4", - "BRAM_ER1BEG1_0", - "BRAM_ER1BEG1_1", - "BRAM_ER1BEG1_2", - "BRAM_ER1BEG1_3", - "BRAM_ER1BEG1_4", - "BRAM_ER1BEG2_0", - "BRAM_ER1BEG2_1", - "BRAM_ER1BEG2_2", - "BRAM_ER1BEG2_3", - "BRAM_ER1BEG2_4", - "BRAM_ER1BEG3_0", - "BRAM_ER1BEG3_1", - "BRAM_ER1BEG3_2", - "BRAM_ER1BEG3_3", - "BRAM_ER1BEG3_4", - "BRAM_FAN0_0", - "BRAM_FAN0_1", - "BRAM_FAN0_2", - "BRAM_FAN0_3", - "BRAM_FAN0_4", - "BRAM_FAN1_0", - "BRAM_FAN1_1", - "BRAM_FAN1_2", - "BRAM_FAN1_3", - "BRAM_FAN1_4", - "BRAM_FAN2_0", - "BRAM_FAN2_1", - "BRAM_FAN2_2", - "BRAM_FAN2_3", - "BRAM_FAN2_4", - "BRAM_FAN3_0", - "BRAM_FAN3_1", - "BRAM_FAN3_2", - "BRAM_FAN3_3", - "BRAM_FAN3_4", - "BRAM_FAN4_0", - "BRAM_FAN4_1", - "BRAM_FAN4_2", - "BRAM_FAN4_3", - "BRAM_FAN4_4", - "BRAM_FAN5_0", - "BRAM_FAN5_1", - "BRAM_FAN5_2", - "BRAM_FAN5_3", - "BRAM_FAN5_4", - "BRAM_FAN6_0", - "BRAM_FAN6_1", - "BRAM_FAN6_2", - "BRAM_FAN6_3", - "BRAM_FAN6_4", - "BRAM_FAN7_0", - "BRAM_FAN7_1", - "BRAM_FAN7_2", - "BRAM_FAN7_3", - "BRAM_FAN7_4", - "BRAM_FIFO18_ADDRARDADDR0", - "BRAM_FIFO18_ADDRARDADDR1", - "BRAM_FIFO18_ADDRARDADDR10", - "BRAM_FIFO18_ADDRARDADDR11", - "BRAM_FIFO18_ADDRARDADDR12", - "BRAM_FIFO18_ADDRARDADDR13", - "BRAM_FIFO18_ADDRARDADDR2", - "BRAM_FIFO18_ADDRARDADDR3", - "BRAM_FIFO18_ADDRARDADDR4", - "BRAM_FIFO18_ADDRARDADDR5", - "BRAM_FIFO18_ADDRARDADDR6", - "BRAM_FIFO18_ADDRARDADDR7", - "BRAM_FIFO18_ADDRARDADDR8", - "BRAM_FIFO18_ADDRARDADDR9", - "BRAM_FIFO18_ADDRATIEHIGH0", - "BRAM_FIFO18_ADDRATIEHIGH1", - "BRAM_FIFO18_ADDRBTIEHIGH0", - "BRAM_FIFO18_ADDRBTIEHIGH1", - "BRAM_FIFO18_ADDRBWRADDR0", - "BRAM_FIFO18_ADDRBWRADDR1", - "BRAM_FIFO18_ADDRBWRADDR10", - "BRAM_FIFO18_ADDRBWRADDR11", - "BRAM_FIFO18_ADDRBWRADDR12", - "BRAM_FIFO18_ADDRBWRADDR13", - "BRAM_FIFO18_ADDRBWRADDR2", - "BRAM_FIFO18_ADDRBWRADDR3", - "BRAM_FIFO18_ADDRBWRADDR4", - "BRAM_FIFO18_ADDRBWRADDR5", - "BRAM_FIFO18_ADDRBWRADDR6", - "BRAM_FIFO18_ADDRBWRADDR7", - "BRAM_FIFO18_ADDRBWRADDR8", - "BRAM_FIFO18_ADDRBWRADDR9", - "BRAM_FIFO18_ALMOSTEMPTY", - "BRAM_FIFO18_ALMOSTFULL", - "BRAM_FIFO18_CLKARDCLK", - "BRAM_FIFO18_CLKBWRCLK", - "BRAM_FIFO18_DIADI0", - "BRAM_FIFO18_DIADI1", - "BRAM_FIFO18_DIADI10", - "BRAM_FIFO18_DIADI11", - "BRAM_FIFO18_DIADI12", - "BRAM_FIFO18_DIADI13", - "BRAM_FIFO18_DIADI14", - "BRAM_FIFO18_DIADI15", - "BRAM_FIFO18_DIADI2", - "BRAM_FIFO18_DIADI3", - "BRAM_FIFO18_DIADI4", - "BRAM_FIFO18_DIADI5", - "BRAM_FIFO18_DIADI6", - "BRAM_FIFO18_DIADI7", - "BRAM_FIFO18_DIADI8", - "BRAM_FIFO18_DIADI9", - "BRAM_FIFO18_DIBDI0", - "BRAM_FIFO18_DIBDI1", - "BRAM_FIFO18_DIBDI10", - "BRAM_FIFO18_DIBDI11", - "BRAM_FIFO18_DIBDI12", - "BRAM_FIFO18_DIBDI13", - "BRAM_FIFO18_DIBDI14", - "BRAM_FIFO18_DIBDI15", - "BRAM_FIFO18_DIBDI2", - "BRAM_FIFO18_DIBDI3", - "BRAM_FIFO18_DIBDI4", - "BRAM_FIFO18_DIBDI5", - "BRAM_FIFO18_DIBDI6", - "BRAM_FIFO18_DIBDI7", - "BRAM_FIFO18_DIBDI8", - "BRAM_FIFO18_DIBDI9", - "BRAM_FIFO18_DIPADIP0", - "BRAM_FIFO18_DIPADIP1", - "BRAM_FIFO18_DIPBDIP0", - "BRAM_FIFO18_DIPBDIP1", - "BRAM_FIFO18_DOADO0", - "BRAM_FIFO18_DOADO1", - "BRAM_FIFO18_DOADO10", - "BRAM_FIFO18_DOADO11", - "BRAM_FIFO18_DOADO12", - "BRAM_FIFO18_DOADO13", - "BRAM_FIFO18_DOADO14", - "BRAM_FIFO18_DOADO15", - "BRAM_FIFO18_DOADO2", - "BRAM_FIFO18_DOADO3", - "BRAM_FIFO18_DOADO4", - "BRAM_FIFO18_DOADO5", - "BRAM_FIFO18_DOADO6", - "BRAM_FIFO18_DOADO7", - "BRAM_FIFO18_DOADO8", - "BRAM_FIFO18_DOADO9", - "BRAM_FIFO18_DOBDO0", - "BRAM_FIFO18_DOBDO1", - "BRAM_FIFO18_DOBDO10", - "BRAM_FIFO18_DOBDO11", - "BRAM_FIFO18_DOBDO12", - "BRAM_FIFO18_DOBDO13", - "BRAM_FIFO18_DOBDO14", - "BRAM_FIFO18_DOBDO15", - "BRAM_FIFO18_DOBDO2", - "BRAM_FIFO18_DOBDO3", - "BRAM_FIFO18_DOBDO4", - "BRAM_FIFO18_DOBDO5", - "BRAM_FIFO18_DOBDO6", - "BRAM_FIFO18_DOBDO7", - "BRAM_FIFO18_DOBDO8", - "BRAM_FIFO18_DOBDO9", - "BRAM_FIFO18_DOPADOP0", - "BRAM_FIFO18_DOPADOP1", - "BRAM_FIFO18_DOPBDOP0", - "BRAM_FIFO18_DOPBDOP1", - "BRAM_FIFO18_EMPTY", - "BRAM_FIFO18_ENARDEN", - "BRAM_FIFO18_ENBWREN", - "BRAM_FIFO18_FULL", - "BRAM_FIFO18_RDCOUNT0", - "BRAM_FIFO18_RDCOUNT1", - "BRAM_FIFO18_RDCOUNT10", - "BRAM_FIFO18_RDCOUNT11", - "BRAM_FIFO18_RDCOUNT2", - "BRAM_FIFO18_RDCOUNT3", - "BRAM_FIFO18_RDCOUNT4", - "BRAM_FIFO18_RDCOUNT5", - "BRAM_FIFO18_RDCOUNT6", - "BRAM_FIFO18_RDCOUNT7", - "BRAM_FIFO18_RDCOUNT8", - "BRAM_FIFO18_RDCOUNT9", - "BRAM_FIFO18_RDERR", - "BRAM_FIFO18_REGCEAREGCE", - "BRAM_FIFO18_REGCEB", - "BRAM_FIFO18_REGCLKARDRCLK", - "BRAM_FIFO18_REGCLKB", - "BRAM_FIFO18_RSTRAMARSTRAM", - "BRAM_FIFO18_RSTRAMB", - "BRAM_FIFO18_RSTREGARSTREG", - "BRAM_FIFO18_RSTREGB", - "BRAM_FIFO18_WEA0", - "BRAM_FIFO18_WEA1", - "BRAM_FIFO18_WEA2", - "BRAM_FIFO18_WEA3", - "BRAM_FIFO18_WEBWE0", - "BRAM_FIFO18_WEBWE1", - "BRAM_FIFO18_WEBWE2", - "BRAM_FIFO18_WEBWE3", - "BRAM_FIFO18_WEBWE4", - "BRAM_FIFO18_WEBWE5", - "BRAM_FIFO18_WEBWE6", - "BRAM_FIFO18_WEBWE7", - "BRAM_FIFO18_WRCOUNT0", - "BRAM_FIFO18_WRCOUNT1", - "BRAM_FIFO18_WRCOUNT10", - "BRAM_FIFO18_WRCOUNT11", - "BRAM_FIFO18_WRCOUNT2", - "BRAM_FIFO18_WRCOUNT3", - "BRAM_FIFO18_WRCOUNT4", - "BRAM_FIFO18_WRCOUNT5", - "BRAM_FIFO18_WRCOUNT6", - "BRAM_FIFO18_WRCOUNT7", - "BRAM_FIFO18_WRCOUNT8", - "BRAM_FIFO18_WRCOUNT9", - "BRAM_FIFO18_WRERR", - "BRAM_FIFO36_ADDRARDADDRL0", - "BRAM_FIFO36_ADDRARDADDRL1", - "BRAM_FIFO36_ADDRARDADDRL10", - "BRAM_FIFO36_ADDRARDADDRL11", - "BRAM_FIFO36_ADDRARDADDRL12", - "BRAM_FIFO36_ADDRARDADDRL13", - "BRAM_FIFO36_ADDRARDADDRL14", - "BRAM_FIFO36_ADDRARDADDRL15", - "BRAM_FIFO36_ADDRARDADDRL2", - "BRAM_FIFO36_ADDRARDADDRL3", - "BRAM_FIFO36_ADDRARDADDRL4", - "BRAM_FIFO36_ADDRARDADDRL5", - "BRAM_FIFO36_ADDRARDADDRL6", - "BRAM_FIFO36_ADDRARDADDRL7", - "BRAM_FIFO36_ADDRARDADDRL8", - "BRAM_FIFO36_ADDRARDADDRL9", - "BRAM_FIFO36_ADDRARDADDRU0", - "BRAM_FIFO36_ADDRARDADDRU1", - "BRAM_FIFO36_ADDRARDADDRU10", - "BRAM_FIFO36_ADDRARDADDRU11", - "BRAM_FIFO36_ADDRARDADDRU12", - "BRAM_FIFO36_ADDRARDADDRU13", - "BRAM_FIFO36_ADDRARDADDRU14", - "BRAM_FIFO36_ADDRARDADDRU2", - "BRAM_FIFO36_ADDRARDADDRU3", - "BRAM_FIFO36_ADDRARDADDRU4", - "BRAM_FIFO36_ADDRARDADDRU5", - "BRAM_FIFO36_ADDRARDADDRU6", - "BRAM_FIFO36_ADDRARDADDRU7", - "BRAM_FIFO36_ADDRARDADDRU8", - "BRAM_FIFO36_ADDRARDADDRU9", - "BRAM_FIFO36_ADDRBWRADDRL0", - "BRAM_FIFO36_ADDRBWRADDRL1", - "BRAM_FIFO36_ADDRBWRADDRL10", - "BRAM_FIFO36_ADDRBWRADDRL11", - "BRAM_FIFO36_ADDRBWRADDRL12", - "BRAM_FIFO36_ADDRBWRADDRL13", - "BRAM_FIFO36_ADDRBWRADDRL14", - "BRAM_FIFO36_ADDRBWRADDRL15", - "BRAM_FIFO36_ADDRBWRADDRL2", - "BRAM_FIFO36_ADDRBWRADDRL3", - "BRAM_FIFO36_ADDRBWRADDRL4", - "BRAM_FIFO36_ADDRBWRADDRL5", - "BRAM_FIFO36_ADDRBWRADDRL6", - "BRAM_FIFO36_ADDRBWRADDRL7", - "BRAM_FIFO36_ADDRBWRADDRL8", - "BRAM_FIFO36_ADDRBWRADDRL9", - "BRAM_FIFO36_ADDRBWRADDRU0", - "BRAM_FIFO36_ADDRBWRADDRU1", - "BRAM_FIFO36_ADDRBWRADDRU10", - "BRAM_FIFO36_ADDRBWRADDRU11", - "BRAM_FIFO36_ADDRBWRADDRU12", - "BRAM_FIFO36_ADDRBWRADDRU13", - "BRAM_FIFO36_ADDRBWRADDRU14", - "BRAM_FIFO36_ADDRBWRADDRU2", - "BRAM_FIFO36_ADDRBWRADDRU3", - "BRAM_FIFO36_ADDRBWRADDRU4", - "BRAM_FIFO36_ADDRBWRADDRU5", - "BRAM_FIFO36_ADDRBWRADDRU6", - "BRAM_FIFO36_ADDRBWRADDRU7", - "BRAM_FIFO36_ADDRBWRADDRU8", - "BRAM_FIFO36_ADDRBWRADDRU9", - "BRAM_FIFO36_ALMOSTEMPTY", - "BRAM_FIFO36_ALMOSTFULL", - "BRAM_FIFO36_CASCADEINA", - "BRAM_FIFO36_CASCADEINB", - "BRAM_FIFO36_CASCADEOUTA", - "BRAM_FIFO36_CASCADEOUTA_1", - "BRAM_FIFO36_CASCADEOUTB", - "BRAM_FIFO36_CASCADEOUTB_1", - "BRAM_FIFO36_CLKARDCLKL", - "BRAM_FIFO36_CLKARDCLKU", - "BRAM_FIFO36_CLKBWRCLKL", - "BRAM_FIFO36_CLKBWRCLKU", - "BRAM_FIFO36_DBITERR", - "BRAM_FIFO36_DIADIL0", - "BRAM_FIFO36_DIADIL1", - "BRAM_FIFO36_DIADIL10", - "BRAM_FIFO36_DIADIL11", - "BRAM_FIFO36_DIADIL12", - "BRAM_FIFO36_DIADIL13", - "BRAM_FIFO36_DIADIL14", - "BRAM_FIFO36_DIADIL15", - "BRAM_FIFO36_DIADIL2", - "BRAM_FIFO36_DIADIL3", - "BRAM_FIFO36_DIADIL4", - "BRAM_FIFO36_DIADIL5", - "BRAM_FIFO36_DIADIL6", - "BRAM_FIFO36_DIADIL7", - "BRAM_FIFO36_DIADIL8", - "BRAM_FIFO36_DIADIL9", - "BRAM_FIFO36_DIADIU0", - "BRAM_FIFO36_DIADIU1", - "BRAM_FIFO36_DIADIU10", - "BRAM_FIFO36_DIADIU11", - "BRAM_FIFO36_DIADIU12", - "BRAM_FIFO36_DIADIU13", - "BRAM_FIFO36_DIADIU14", - "BRAM_FIFO36_DIADIU15", - "BRAM_FIFO36_DIADIU2", - "BRAM_FIFO36_DIADIU3", - "BRAM_FIFO36_DIADIU4", - "BRAM_FIFO36_DIADIU5", - "BRAM_FIFO36_DIADIU6", - "BRAM_FIFO36_DIADIU7", - "BRAM_FIFO36_DIADIU8", - "BRAM_FIFO36_DIADIU9", - "BRAM_FIFO36_DIBDIL0", - "BRAM_FIFO36_DIBDIL1", - "BRAM_FIFO36_DIBDIL10", - "BRAM_FIFO36_DIBDIL11", - "BRAM_FIFO36_DIBDIL12", - "BRAM_FIFO36_DIBDIL13", - "BRAM_FIFO36_DIBDIL14", - "BRAM_FIFO36_DIBDIL15", - "BRAM_FIFO36_DIBDIL2", - "BRAM_FIFO36_DIBDIL3", - "BRAM_FIFO36_DIBDIL4", - "BRAM_FIFO36_DIBDIL5", - "BRAM_FIFO36_DIBDIL6", - "BRAM_FIFO36_DIBDIL7", - "BRAM_FIFO36_DIBDIL8", - "BRAM_FIFO36_DIBDIL9", - "BRAM_FIFO36_DIBDIU0", - "BRAM_FIFO36_DIBDIU1", - "BRAM_FIFO36_DIBDIU10", - "BRAM_FIFO36_DIBDIU11", - "BRAM_FIFO36_DIBDIU12", - "BRAM_FIFO36_DIBDIU13", - "BRAM_FIFO36_DIBDIU14", - "BRAM_FIFO36_DIBDIU15", - "BRAM_FIFO36_DIBDIU2", - "BRAM_FIFO36_DIBDIU3", - "BRAM_FIFO36_DIBDIU4", - "BRAM_FIFO36_DIBDIU5", - "BRAM_FIFO36_DIBDIU6", - "BRAM_FIFO36_DIBDIU7", - "BRAM_FIFO36_DIBDIU8", - "BRAM_FIFO36_DIBDIU9", - "BRAM_FIFO36_DIPADIPL0", - "BRAM_FIFO36_DIPADIPL1", - "BRAM_FIFO36_DIPADIPU0", - "BRAM_FIFO36_DIPADIPU1", - "BRAM_FIFO36_DIPBDIPL0", - "BRAM_FIFO36_DIPBDIPL1", - "BRAM_FIFO36_DIPBDIPU0", - "BRAM_FIFO36_DIPBDIPU1", - "BRAM_FIFO36_DOADOL0", - "BRAM_FIFO36_DOADOL1", - "BRAM_FIFO36_DOADOL10", - "BRAM_FIFO36_DOADOL11", - "BRAM_FIFO36_DOADOL12", - "BRAM_FIFO36_DOADOL13", - "BRAM_FIFO36_DOADOL14", - "BRAM_FIFO36_DOADOL15", - "BRAM_FIFO36_DOADOL2", - "BRAM_FIFO36_DOADOL3", - "BRAM_FIFO36_DOADOL4", - "BRAM_FIFO36_DOADOL5", - "BRAM_FIFO36_DOADOL6", - "BRAM_FIFO36_DOADOL7", - "BRAM_FIFO36_DOADOL8", - "BRAM_FIFO36_DOADOL9", - "BRAM_FIFO36_DOADOU0", - "BRAM_FIFO36_DOADOU1", - "BRAM_FIFO36_DOADOU10", - "BRAM_FIFO36_DOADOU11", - "BRAM_FIFO36_DOADOU12", - "BRAM_FIFO36_DOADOU13", - "BRAM_FIFO36_DOADOU14", - "BRAM_FIFO36_DOADOU15", - "BRAM_FIFO36_DOADOU2", - "BRAM_FIFO36_DOADOU3", - "BRAM_FIFO36_DOADOU4", - "BRAM_FIFO36_DOADOU5", - "BRAM_FIFO36_DOADOU6", - "BRAM_FIFO36_DOADOU7", - "BRAM_FIFO36_DOADOU8", - "BRAM_FIFO36_DOADOU9", - "BRAM_FIFO36_DOBDOL0", - "BRAM_FIFO36_DOBDOL1", - "BRAM_FIFO36_DOBDOL10", - "BRAM_FIFO36_DOBDOL11", - "BRAM_FIFO36_DOBDOL12", - "BRAM_FIFO36_DOBDOL13", - "BRAM_FIFO36_DOBDOL14", - "BRAM_FIFO36_DOBDOL15", - "BRAM_FIFO36_DOBDOL2", - "BRAM_FIFO36_DOBDOL3", - "BRAM_FIFO36_DOBDOL4", - "BRAM_FIFO36_DOBDOL5", - "BRAM_FIFO36_DOBDOL6", - "BRAM_FIFO36_DOBDOL7", - "BRAM_FIFO36_DOBDOL8", - "BRAM_FIFO36_DOBDOL9", - "BRAM_FIFO36_DOBDOU0", - "BRAM_FIFO36_DOBDOU1", - "BRAM_FIFO36_DOBDOU10", - "BRAM_FIFO36_DOBDOU11", - "BRAM_FIFO36_DOBDOU12", - "BRAM_FIFO36_DOBDOU13", - "BRAM_FIFO36_DOBDOU14", - "BRAM_FIFO36_DOBDOU15", - "BRAM_FIFO36_DOBDOU2", - "BRAM_FIFO36_DOBDOU3", - "BRAM_FIFO36_DOBDOU4", - "BRAM_FIFO36_DOBDOU5", - "BRAM_FIFO36_DOBDOU6", - "BRAM_FIFO36_DOBDOU7", - "BRAM_FIFO36_DOBDOU8", - "BRAM_FIFO36_DOBDOU9", - "BRAM_FIFO36_DOPADOPL0", - "BRAM_FIFO36_DOPADOPL1", - "BRAM_FIFO36_DOPADOPU0", - "BRAM_FIFO36_DOPADOPU1", - "BRAM_FIFO36_DOPBDOPL0", - "BRAM_FIFO36_DOPBDOPL1", - "BRAM_FIFO36_DOPBDOPU0", - "BRAM_FIFO36_DOPBDOPU1", - "BRAM_FIFO36_ECCPARITY0", - "BRAM_FIFO36_ECCPARITY1", - "BRAM_FIFO36_ECCPARITY2", - "BRAM_FIFO36_ECCPARITY3", - "BRAM_FIFO36_ECCPARITY4", - "BRAM_FIFO36_ECCPARITY5", - "BRAM_FIFO36_ECCPARITY6", - "BRAM_FIFO36_ECCPARITY7", - "BRAM_FIFO36_EMPTY", - "BRAM_FIFO36_ENARDENL", - "BRAM_FIFO36_ENARDENU", - "BRAM_FIFO36_ENBWRENL", - "BRAM_FIFO36_ENBWRENU", - "BRAM_FIFO36_FULL", - "BRAM_FIFO36_INJECTDBITERR", - "BRAM_FIFO36_INJECTSBITERR", - "BRAM_FIFO36_RDCOUNT0", - "BRAM_FIFO36_RDCOUNT1", - "BRAM_FIFO36_RDCOUNT10", - "BRAM_FIFO36_RDCOUNT11", - "BRAM_FIFO36_RDCOUNT12", - "BRAM_FIFO36_RDCOUNT2", - "BRAM_FIFO36_RDCOUNT3", - "BRAM_FIFO36_RDCOUNT4", - "BRAM_FIFO36_RDCOUNT5", - "BRAM_FIFO36_RDCOUNT6", - "BRAM_FIFO36_RDCOUNT7", - "BRAM_FIFO36_RDCOUNT8", - "BRAM_FIFO36_RDCOUNT9", - "BRAM_FIFO36_RDERR", - "BRAM_FIFO36_REGCEAREGCEL", - "BRAM_FIFO36_REGCEAREGCEU", - "BRAM_FIFO36_REGCEBL", - "BRAM_FIFO36_REGCEBU", - "BRAM_FIFO36_REGCLKARDRCLKL", - "BRAM_FIFO36_REGCLKARDRCLKU", - "BRAM_FIFO36_REGCLKBL", - "BRAM_FIFO36_REGCLKBU", - "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "BRAM_FIFO36_RSTRAMARSTRAMU", - "BRAM_FIFO36_RSTRAMBL", - "BRAM_FIFO36_RSTRAMBU", - "BRAM_FIFO36_RSTREGARSTREGL", - "BRAM_FIFO36_RSTREGARSTREGU", - "BRAM_FIFO36_RSTREGBL", - "BRAM_FIFO36_RSTREGBU", - "BRAM_FIFO36_SBITERR", - "BRAM_FIFO36_TSTBRAMRST", - "BRAM_FIFO36_TSTCNT0", - "BRAM_FIFO36_TSTCNT1", - "BRAM_FIFO36_TSTCNT10", - "BRAM_FIFO36_TSTCNT11", - "BRAM_FIFO36_TSTCNT12", - "BRAM_FIFO36_TSTCNT2", - "BRAM_FIFO36_TSTCNT3", - "BRAM_FIFO36_TSTCNT4", - "BRAM_FIFO36_TSTCNT5", - "BRAM_FIFO36_TSTCNT6", - "BRAM_FIFO36_TSTCNT7", - "BRAM_FIFO36_TSTCNT8", - "BRAM_FIFO36_TSTCNT9", - "BRAM_FIFO36_TSTFLAGIN", - "BRAM_FIFO36_TSTIN0", - "BRAM_FIFO36_TSTIN1", - "BRAM_FIFO36_TSTIN2", - "BRAM_FIFO36_TSTIN3", - "BRAM_FIFO36_TSTIN4", - "BRAM_FIFO36_TSTOFF", - "BRAM_FIFO36_TSTOUT0", - "BRAM_FIFO36_TSTOUT1", - "BRAM_FIFO36_TSTOUT2", - "BRAM_FIFO36_TSTOUT3", - "BRAM_FIFO36_TSTOUT4", - "BRAM_FIFO36_TSTRDCNTOFF", - "BRAM_FIFO36_TSTRDOS0", - "BRAM_FIFO36_TSTRDOS1", - "BRAM_FIFO36_TSTRDOS10", - "BRAM_FIFO36_TSTRDOS11", - "BRAM_FIFO36_TSTRDOS12", - "BRAM_FIFO36_TSTRDOS2", - "BRAM_FIFO36_TSTRDOS3", - "BRAM_FIFO36_TSTRDOS4", - "BRAM_FIFO36_TSTRDOS5", - "BRAM_FIFO36_TSTRDOS6", - "BRAM_FIFO36_TSTRDOS7", - "BRAM_FIFO36_TSTRDOS8", - "BRAM_FIFO36_TSTRDOS9", - "BRAM_FIFO36_TSTWRCNTOFF", - "BRAM_FIFO36_TSTWROS0", - "BRAM_FIFO36_TSTWROS1", - "BRAM_FIFO36_TSTWROS10", - "BRAM_FIFO36_TSTWROS11", - "BRAM_FIFO36_TSTWROS12", - "BRAM_FIFO36_TSTWROS2", - "BRAM_FIFO36_TSTWROS3", - "BRAM_FIFO36_TSTWROS4", - "BRAM_FIFO36_TSTWROS5", - "BRAM_FIFO36_TSTWROS6", - "BRAM_FIFO36_TSTWROS7", - "BRAM_FIFO36_TSTWROS8", - "BRAM_FIFO36_TSTWROS9", - "BRAM_FIFO36_WEAL0", - "BRAM_FIFO36_WEAL1", - "BRAM_FIFO36_WEAL2", - "BRAM_FIFO36_WEAL3", - "BRAM_FIFO36_WEAU0", - "BRAM_FIFO36_WEAU1", - "BRAM_FIFO36_WEAU2", - "BRAM_FIFO36_WEAU3", - "BRAM_FIFO36_WEBWEL0", - "BRAM_FIFO36_WEBWEL1", - "BRAM_FIFO36_WEBWEL2", - "BRAM_FIFO36_WEBWEL3", - "BRAM_FIFO36_WEBWEL4", - "BRAM_FIFO36_WEBWEL5", - "BRAM_FIFO36_WEBWEL6", - "BRAM_FIFO36_WEBWEL7", - "BRAM_FIFO36_WEBWEU0", - "BRAM_FIFO36_WEBWEU1", - "BRAM_FIFO36_WEBWEU2", - "BRAM_FIFO36_WEBWEU3", - "BRAM_FIFO36_WEBWEU4", - "BRAM_FIFO36_WEBWEU5", - "BRAM_FIFO36_WEBWEU6", - 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"BRAM_LOGIC_OUTS_B10_3", - "BRAM_LOGIC_OUTS_B10_4", - "BRAM_LOGIC_OUTS_B11_0", - "BRAM_LOGIC_OUTS_B11_1", - "BRAM_LOGIC_OUTS_B11_2", - "BRAM_LOGIC_OUTS_B11_3", - "BRAM_LOGIC_OUTS_B11_4", - "BRAM_LOGIC_OUTS_B12_0", - "BRAM_LOGIC_OUTS_B12_1", - "BRAM_LOGIC_OUTS_B12_2", - "BRAM_LOGIC_OUTS_B12_3", - "BRAM_LOGIC_OUTS_B12_4", - "BRAM_LOGIC_OUTS_B13_0", - "BRAM_LOGIC_OUTS_B13_1", - "BRAM_LOGIC_OUTS_B13_2", - "BRAM_LOGIC_OUTS_B13_3", - "BRAM_LOGIC_OUTS_B13_4", - "BRAM_LOGIC_OUTS_B14_0", - "BRAM_LOGIC_OUTS_B14_1", - "BRAM_LOGIC_OUTS_B14_2", - "BRAM_LOGIC_OUTS_B14_3", - "BRAM_LOGIC_OUTS_B14_4", - "BRAM_LOGIC_OUTS_B15_0", - "BRAM_LOGIC_OUTS_B15_1", - "BRAM_LOGIC_OUTS_B15_2", - "BRAM_LOGIC_OUTS_B15_3", - "BRAM_LOGIC_OUTS_B15_4", - "BRAM_LOGIC_OUTS_B16_0", - "BRAM_LOGIC_OUTS_B16_1", - "BRAM_LOGIC_OUTS_B16_2", - "BRAM_LOGIC_OUTS_B16_3", - "BRAM_LOGIC_OUTS_B16_4", - "BRAM_LOGIC_OUTS_B17_0", - "BRAM_LOGIC_OUTS_B17_1", - "BRAM_LOGIC_OUTS_B17_2", - "BRAM_LOGIC_OUTS_B17_3", - "BRAM_LOGIC_OUTS_B17_4", - "BRAM_LOGIC_OUTS_B18_0", - "BRAM_LOGIC_OUTS_B18_1", - "BRAM_LOGIC_OUTS_B18_2", - "BRAM_LOGIC_OUTS_B18_3", - "BRAM_LOGIC_OUTS_B18_4", - "BRAM_LOGIC_OUTS_B19_0", - "BRAM_LOGIC_OUTS_B19_1", - "BRAM_LOGIC_OUTS_B19_2", - "BRAM_LOGIC_OUTS_B19_3", - "BRAM_LOGIC_OUTS_B19_4", - "BRAM_LOGIC_OUTS_B1_0", - "BRAM_LOGIC_OUTS_B1_1", - "BRAM_LOGIC_OUTS_B1_2", - "BRAM_LOGIC_OUTS_B1_3", - "BRAM_LOGIC_OUTS_B1_4", - "BRAM_LOGIC_OUTS_B20_0", - "BRAM_LOGIC_OUTS_B20_1", - "BRAM_LOGIC_OUTS_B20_2", - "BRAM_LOGIC_OUTS_B20_3", - "BRAM_LOGIC_OUTS_B20_4", - "BRAM_LOGIC_OUTS_B21_0", - "BRAM_LOGIC_OUTS_B21_1", - "BRAM_LOGIC_OUTS_B21_2", - "BRAM_LOGIC_OUTS_B21_3", - "BRAM_LOGIC_OUTS_B21_4", - "BRAM_LOGIC_OUTS_B22_0", - "BRAM_LOGIC_OUTS_B22_1", - "BRAM_LOGIC_OUTS_B22_2", - "BRAM_LOGIC_OUTS_B22_3", - "BRAM_LOGIC_OUTS_B22_4", - "BRAM_LOGIC_OUTS_B23_0", - "BRAM_LOGIC_OUTS_B23_1", - "BRAM_LOGIC_OUTS_B23_2", - "BRAM_LOGIC_OUTS_B23_3", - "BRAM_LOGIC_OUTS_B23_4", - "BRAM_LOGIC_OUTS_B2_0", - "BRAM_LOGIC_OUTS_B2_1", - "BRAM_LOGIC_OUTS_B2_2", - "BRAM_LOGIC_OUTS_B2_3", - "BRAM_LOGIC_OUTS_B2_4", - "BRAM_LOGIC_OUTS_B3_0", - "BRAM_LOGIC_OUTS_B3_1", - "BRAM_LOGIC_OUTS_B3_2", - "BRAM_LOGIC_OUTS_B3_3", - "BRAM_LOGIC_OUTS_B3_4", - "BRAM_LOGIC_OUTS_B4_0", - "BRAM_LOGIC_OUTS_B4_1", - "BRAM_LOGIC_OUTS_B4_2", - "BRAM_LOGIC_OUTS_B4_3", - "BRAM_LOGIC_OUTS_B4_4", - "BRAM_LOGIC_OUTS_B5_0", - "BRAM_LOGIC_OUTS_B5_1", - "BRAM_LOGIC_OUTS_B5_2", - "BRAM_LOGIC_OUTS_B5_3", - "BRAM_LOGIC_OUTS_B5_4", - "BRAM_LOGIC_OUTS_B6_0", - "BRAM_LOGIC_OUTS_B6_1", - "BRAM_LOGIC_OUTS_B6_2", - "BRAM_LOGIC_OUTS_B6_3", - "BRAM_LOGIC_OUTS_B6_4", - "BRAM_LOGIC_OUTS_B7_0", - "BRAM_LOGIC_OUTS_B7_1", - "BRAM_LOGIC_OUTS_B7_2", - "BRAM_LOGIC_OUTS_B7_3", - "BRAM_LOGIC_OUTS_B7_4", - "BRAM_LOGIC_OUTS_B8_0", - "BRAM_LOGIC_OUTS_B8_1", - "BRAM_LOGIC_OUTS_B8_2", - "BRAM_LOGIC_OUTS_B8_3", - "BRAM_LOGIC_OUTS_B8_4", - "BRAM_LOGIC_OUTS_B9_0", - "BRAM_LOGIC_OUTS_B9_1", - "BRAM_LOGIC_OUTS_B9_2", - "BRAM_LOGIC_OUTS_B9_3", - "BRAM_LOGIC_OUTS_B9_4", - "BRAM_MONITOR_N_0", - "BRAM_MONITOR_N_1", - "BRAM_MONITOR_N_2", - "BRAM_MONITOR_N_3", - "BRAM_MONITOR_N_4", - "BRAM_MONITOR_P_0", - "BRAM_MONITOR_P_1", - "BRAM_MONITOR_P_2", - "BRAM_MONITOR_P_3", - "BRAM_MONITOR_P_4", - "BRAM_NE2A0_0", - "BRAM_NE2A0_1", - "BRAM_NE2A0_2", - "BRAM_NE2A0_3", - "BRAM_NE2A0_4", - "BRAM_NE2A1_0", - "BRAM_NE2A1_1", - "BRAM_NE2A1_2", - "BRAM_NE2A1_3", - "BRAM_NE2A1_4", - "BRAM_NE2A2_0", - "BRAM_NE2A2_1", - "BRAM_NE2A2_2", - "BRAM_NE2A2_3", - "BRAM_NE2A2_4", - "BRAM_NE2A3_0", - "BRAM_NE2A3_1", - "BRAM_NE2A3_2", - "BRAM_NE2A3_3", - "BRAM_NE2A3_4", - "BRAM_NE4BEG0_0", - "BRAM_NE4BEG0_1", - "BRAM_NE4BEG0_2", - "BRAM_NE4BEG0_3", - "BRAM_NE4BEG0_4", - "BRAM_NE4BEG1_0", - "BRAM_NE4BEG1_1", - "BRAM_NE4BEG1_2", - "BRAM_NE4BEG1_3", - "BRAM_NE4BEG1_4", - "BRAM_NE4BEG2_0", - "BRAM_NE4BEG2_1", - "BRAM_NE4BEG2_2", - "BRAM_NE4BEG2_3", - "BRAM_NE4BEG2_4", - "BRAM_NE4BEG3_0", - "BRAM_NE4BEG3_1", - "BRAM_NE4BEG3_2", - "BRAM_NE4BEG3_3", - "BRAM_NE4BEG3_4", - "BRAM_NE4C0_0", - "BRAM_NE4C0_1", - "BRAM_NE4C0_2", - "BRAM_NE4C0_3", - "BRAM_NE4C0_4", - "BRAM_NE4C1_0", - "BRAM_NE4C1_1", - "BRAM_NE4C1_2", - "BRAM_NE4C1_3", - "BRAM_NE4C1_4", - "BRAM_NE4C2_0", - "BRAM_NE4C2_1", - "BRAM_NE4C2_2", - "BRAM_NE4C2_3", - "BRAM_NE4C2_4", - "BRAM_NE4C3_0", - "BRAM_NE4C3_1", - "BRAM_NE4C3_2", - "BRAM_NE4C3_3", - "BRAM_NE4C3_4", - "BRAM_NW2A0_0", - "BRAM_NW2A0_1", - "BRAM_NW2A0_2", - "BRAM_NW2A0_3", - "BRAM_NW2A0_4", - "BRAM_NW2A1_0", - "BRAM_NW2A1_1", - "BRAM_NW2A1_2", - "BRAM_NW2A1_3", - "BRAM_NW2A1_4", - "BRAM_NW2A2_0", - "BRAM_NW2A2_1", - "BRAM_NW2A2_2", - "BRAM_NW2A2_3", - "BRAM_NW2A2_4", - "BRAM_NW2A3_0", - "BRAM_NW2A3_1", - "BRAM_NW2A3_2", - "BRAM_NW2A3_3", - "BRAM_NW2A3_4", - "BRAM_NW4A0_0", - "BRAM_NW4A0_1", - "BRAM_NW4A0_2", - "BRAM_NW4A0_3", - "BRAM_NW4A0_4", - "BRAM_NW4A1_0", - "BRAM_NW4A1_1", - "BRAM_NW4A1_2", - "BRAM_NW4A1_3", - "BRAM_NW4A1_4", - "BRAM_NW4A2_0", - "BRAM_NW4A2_1", - "BRAM_NW4A2_2", - "BRAM_NW4A2_3", - "BRAM_NW4A2_4", - "BRAM_NW4A3_0", - "BRAM_NW4A3_1", - "BRAM_NW4A3_2", - "BRAM_NW4A3_3", - "BRAM_NW4A3_4", - "BRAM_NW4END0_0", - "BRAM_NW4END0_1", - "BRAM_NW4END0_2", - "BRAM_NW4END0_3", - "BRAM_NW4END0_4", - "BRAM_NW4END1_0", - "BRAM_NW4END1_1", - "BRAM_NW4END1_2", - "BRAM_NW4END1_3", - "BRAM_NW4END1_4", - "BRAM_NW4END2_0", - "BRAM_NW4END2_1", - "BRAM_NW4END2_2", - "BRAM_NW4END2_3", - "BRAM_NW4END2_4", - "BRAM_NW4END3_0", - "BRAM_NW4END3_1", - "BRAM_NW4END3_2", - "BRAM_NW4END3_3", - "BRAM_NW4END3_4", - "BRAM_PMVBRAM_O", - "BRAM_PMVBRAM_ODIV2", - "BRAM_PMVBRAM_ODIV2_1", - "BRAM_PMVBRAM_ODIV4", - "BRAM_PMVBRAM_O_1", - "BRAM_PMVBRAM_O_2", - "BRAM_PMVBRAM_SELECT1", - "BRAM_PMVBRAM_SELECT2", - "BRAM_PMVBRAM_SELECT3", - "BRAM_PMVBRAM_SELECT4", - "BRAM_RAMB18_ADDRARDADDR0", - "BRAM_RAMB18_ADDRARDADDR1", - "BRAM_RAMB18_ADDRARDADDR10", - "BRAM_RAMB18_ADDRARDADDR11", - "BRAM_RAMB18_ADDRARDADDR12", - "BRAM_RAMB18_ADDRARDADDR13", - "BRAM_RAMB18_ADDRARDADDR2", - "BRAM_RAMB18_ADDRARDADDR3", - "BRAM_RAMB18_ADDRARDADDR4", - "BRAM_RAMB18_ADDRARDADDR5", - "BRAM_RAMB18_ADDRARDADDR6", - "BRAM_RAMB18_ADDRARDADDR7", - "BRAM_RAMB18_ADDRARDADDR8", - "BRAM_RAMB18_ADDRARDADDR9", - "BRAM_RAMB18_ADDRATIEHIGH0", - "BRAM_RAMB18_ADDRATIEHIGH1", - "BRAM_RAMB18_ADDRBTIEHIGH0", - "BRAM_RAMB18_ADDRBTIEHIGH1", - "BRAM_RAMB18_ADDRBWRADDR0", - "BRAM_RAMB18_ADDRBWRADDR1", - "BRAM_RAMB18_ADDRBWRADDR10", - "BRAM_RAMB18_ADDRBWRADDR11", - "BRAM_RAMB18_ADDRBWRADDR12", - "BRAM_RAMB18_ADDRBWRADDR13", - "BRAM_RAMB18_ADDRBWRADDR2", - "BRAM_RAMB18_ADDRBWRADDR3", - "BRAM_RAMB18_ADDRBWRADDR4", - "BRAM_RAMB18_ADDRBWRADDR5", - "BRAM_RAMB18_ADDRBWRADDR6", - "BRAM_RAMB18_ADDRBWRADDR7", - "BRAM_RAMB18_ADDRBWRADDR8", - "BRAM_RAMB18_ADDRBWRADDR9", - "BRAM_RAMB18_ALMOSTEMPTY", - "BRAM_RAMB18_ALMOSTFULL", - "BRAM_RAMB18_CLKARDCLK", - "BRAM_RAMB18_CLKBWRCLK", - "BRAM_RAMB18_DIADI0", - "BRAM_RAMB18_DIADI1", - "BRAM_RAMB18_DIADI10", - "BRAM_RAMB18_DIADI11", - "BRAM_RAMB18_DIADI12", - "BRAM_RAMB18_DIADI13", - "BRAM_RAMB18_DIADI14", - "BRAM_RAMB18_DIADI15", - "BRAM_RAMB18_DIADI2", - "BRAM_RAMB18_DIADI3", - "BRAM_RAMB18_DIADI4", - "BRAM_RAMB18_DIADI5", - "BRAM_RAMB18_DIADI6", - "BRAM_RAMB18_DIADI7", - "BRAM_RAMB18_DIADI8", - "BRAM_RAMB18_DIADI9", - "BRAM_RAMB18_DIBDI0", - "BRAM_RAMB18_DIBDI1", - "BRAM_RAMB18_DIBDI10", - "BRAM_RAMB18_DIBDI11", - "BRAM_RAMB18_DIBDI12", - "BRAM_RAMB18_DIBDI13", - "BRAM_RAMB18_DIBDI14", - "BRAM_RAMB18_DIBDI15", - "BRAM_RAMB18_DIBDI2", - "BRAM_RAMB18_DIBDI3", - "BRAM_RAMB18_DIBDI4", - "BRAM_RAMB18_DIBDI5", - "BRAM_RAMB18_DIBDI6", - "BRAM_RAMB18_DIBDI7", - "BRAM_RAMB18_DIBDI8", - "BRAM_RAMB18_DIBDI9", - "BRAM_RAMB18_DIPADIP0", - "BRAM_RAMB18_DIPADIP1", - "BRAM_RAMB18_DIPBDIP0", - "BRAM_RAMB18_DIPBDIP1", - "BRAM_RAMB18_DOADO0", - "BRAM_RAMB18_DOADO1", - "BRAM_RAMB18_DOADO10", - "BRAM_RAMB18_DOADO11", - "BRAM_RAMB18_DOADO12", - "BRAM_RAMB18_DOADO13", - "BRAM_RAMB18_DOADO14", - "BRAM_RAMB18_DOADO15", - "BRAM_RAMB18_DOADO2", - "BRAM_RAMB18_DOADO3", - "BRAM_RAMB18_DOADO4", - "BRAM_RAMB18_DOADO5", - "BRAM_RAMB18_DOADO6", - "BRAM_RAMB18_DOADO7", - "BRAM_RAMB18_DOADO8", - "BRAM_RAMB18_DOADO9", - "BRAM_RAMB18_DOBDO0", - "BRAM_RAMB18_DOBDO1", - "BRAM_RAMB18_DOBDO10", - "BRAM_RAMB18_DOBDO11", - "BRAM_RAMB18_DOBDO12", - "BRAM_RAMB18_DOBDO13", - "BRAM_RAMB18_DOBDO14", - "BRAM_RAMB18_DOBDO15", - "BRAM_RAMB18_DOBDO2", - "BRAM_RAMB18_DOBDO3", - "BRAM_RAMB18_DOBDO4", - "BRAM_RAMB18_DOBDO5", - "BRAM_RAMB18_DOBDO6", - "BRAM_RAMB18_DOBDO7", - "BRAM_RAMB18_DOBDO8", - "BRAM_RAMB18_DOBDO9", - "BRAM_RAMB18_DOPADOP0", - "BRAM_RAMB18_DOPADOP1", - "BRAM_RAMB18_DOPBDOP0", - "BRAM_RAMB18_DOPBDOP1", - "BRAM_RAMB18_EMPTY", - "BRAM_RAMB18_ENARDEN", - "BRAM_RAMB18_ENBWREN", - "BRAM_RAMB18_FULL", - "BRAM_RAMB18_RDCOUNT0", - "BRAM_RAMB18_RDCOUNT1", - "BRAM_RAMB18_RDCOUNT10", - "BRAM_RAMB18_RDCOUNT11", - "BRAM_RAMB18_RDCOUNT2", - "BRAM_RAMB18_RDCOUNT3", - "BRAM_RAMB18_RDCOUNT4", - "BRAM_RAMB18_RDCOUNT5", - "BRAM_RAMB18_RDCOUNT6", - "BRAM_RAMB18_RDCOUNT7", - "BRAM_RAMB18_RDCOUNT8", - "BRAM_RAMB18_RDCOUNT9", - "BRAM_RAMB18_RDERR", - "BRAM_RAMB18_REGCEAREGCE", - "BRAM_RAMB18_REGCEB", - "BRAM_RAMB18_REGCLKARDRCLK", - "BRAM_RAMB18_REGCLKB", - "BRAM_RAMB18_RSTRAMARSTRAM", - "BRAM_RAMB18_RSTRAMB", - "BRAM_RAMB18_RSTREGARSTREG", - "BRAM_RAMB18_RSTREGB", - "BRAM_RAMB18_WEA0", - "BRAM_RAMB18_WEA1", - "BRAM_RAMB18_WEA2", - "BRAM_RAMB18_WEA3", - "BRAM_RAMB18_WEBWE0", - "BRAM_RAMB18_WEBWE1", - "BRAM_RAMB18_WEBWE2", - "BRAM_RAMB18_WEBWE3", - "BRAM_RAMB18_WEBWE4", - "BRAM_RAMB18_WEBWE5", - "BRAM_RAMB18_WEBWE6", - "BRAM_RAMB18_WEBWE7", - "BRAM_RAMB18_WRCOUNT0", - "BRAM_RAMB18_WRCOUNT1", - "BRAM_RAMB18_WRCOUNT10", - "BRAM_RAMB18_WRCOUNT11", - "BRAM_RAMB18_WRCOUNT2", - "BRAM_RAMB18_WRCOUNT3", - "BRAM_RAMB18_WRCOUNT4", - "BRAM_RAMB18_WRCOUNT5", - "BRAM_RAMB18_WRCOUNT6", - "BRAM_RAMB18_WRCOUNT7", - "BRAM_RAMB18_WRCOUNT8", - "BRAM_RAMB18_WRCOUNT9", - "BRAM_RAMB18_WRERR", - "BRAM_SE2A0_0", - "BRAM_SE2A0_1", - "BRAM_SE2A0_2", - "BRAM_SE2A0_3", - "BRAM_SE2A0_4", - "BRAM_SE2A1_0", - "BRAM_SE2A1_1", - "BRAM_SE2A1_2", - "BRAM_SE2A1_3", - "BRAM_SE2A1_4", - "BRAM_SE2A2_0", - "BRAM_SE2A2_1", - "BRAM_SE2A2_2", - "BRAM_SE2A2_3", - "BRAM_SE2A2_4", - "BRAM_SE2A3_0", - "BRAM_SE2A3_1", - "BRAM_SE2A3_2", - "BRAM_SE2A3_3", - "BRAM_SE2A3_4", - "BRAM_SE4BEG0_0", - "BRAM_SE4BEG0_1", - "BRAM_SE4BEG0_2", - "BRAM_SE4BEG0_3", - "BRAM_SE4BEG0_4", - "BRAM_SE4BEG1_0", - "BRAM_SE4BEG1_1", - "BRAM_SE4BEG1_2", - "BRAM_SE4BEG1_3", - "BRAM_SE4BEG1_4", - "BRAM_SE4BEG2_0", - "BRAM_SE4BEG2_1", - "BRAM_SE4BEG2_2", - "BRAM_SE4BEG2_3", - "BRAM_SE4BEG2_4", - "BRAM_SE4BEG3_0", - "BRAM_SE4BEG3_1", - "BRAM_SE4BEG3_2", - "BRAM_SE4BEG3_3", - "BRAM_SE4BEG3_4", - "BRAM_SE4C0_0", - "BRAM_SE4C0_1", - "BRAM_SE4C0_2", - "BRAM_SE4C0_3", - "BRAM_SE4C0_4", - "BRAM_SE4C1_0", - "BRAM_SE4C1_1", - "BRAM_SE4C1_2", - "BRAM_SE4C1_3", - "BRAM_SE4C1_4", - "BRAM_SE4C2_0", - "BRAM_SE4C2_1", - "BRAM_SE4C2_2", - "BRAM_SE4C2_3", - "BRAM_SE4C2_4", - "BRAM_SE4C3_0", - "BRAM_SE4C3_1", - "BRAM_SE4C3_2", - "BRAM_SE4C3_3", - "BRAM_SE4C3_4", - "BRAM_SW2A0_0", - "BRAM_SW2A0_1", - "BRAM_SW2A0_2", - "BRAM_SW2A0_3", - "BRAM_SW2A0_4", - "BRAM_SW2A1_0", - "BRAM_SW2A1_1", - "BRAM_SW2A1_2", - "BRAM_SW2A1_3", - "BRAM_SW2A1_4", - "BRAM_SW2A2_0", - "BRAM_SW2A2_1", - "BRAM_SW2A2_2", - "BRAM_SW2A2_3", - "BRAM_SW2A2_4", - "BRAM_SW2A3_0", - "BRAM_SW2A3_1", - "BRAM_SW2A3_2", - "BRAM_SW2A3_3", - "BRAM_SW2A3_4", - "BRAM_SW4A0_0", - "BRAM_SW4A0_1", - "BRAM_SW4A0_2", - "BRAM_SW4A0_3", - "BRAM_SW4A0_4", - "BRAM_SW4A1_0", - "BRAM_SW4A1_1", - "BRAM_SW4A1_2", - "BRAM_SW4A1_3", - "BRAM_SW4A1_4", - "BRAM_SW4A2_0", - "BRAM_SW4A2_1", - "BRAM_SW4A2_2", - "BRAM_SW4A2_3", - "BRAM_SW4A2_4", - "BRAM_SW4A3_0", - "BRAM_SW4A3_1", - "BRAM_SW4A3_2", - "BRAM_SW4A3_3", - "BRAM_SW4A3_4", - "BRAM_SW4END0_0", - "BRAM_SW4END0_1", - "BRAM_SW4END0_2", - "BRAM_SW4END0_3", - "BRAM_SW4END0_4", - "BRAM_SW4END1_0", - "BRAM_SW4END1_1", - "BRAM_SW4END1_2", - "BRAM_SW4END1_3", - "BRAM_SW4END1_4", - "BRAM_SW4END2_0", - "BRAM_SW4END2_1", - "BRAM_SW4END2_2", - "BRAM_SW4END2_3", - "BRAM_SW4END2_4", - "BRAM_SW4END3_0", - "BRAM_SW4END3_1", - "BRAM_SW4END3_2", - "BRAM_SW4END3_3", - "BRAM_SW4END3_4", - "BRAM_UTURN_ADDRARDADDRL0", - "BRAM_UTURN_ADDRARDADDRL1", - "BRAM_UTURN_ADDRARDADDRL10", - "BRAM_UTURN_ADDRARDADDRL11", - "BRAM_UTURN_ADDRARDADDRL12", - "BRAM_UTURN_ADDRARDADDRL13", - "BRAM_UTURN_ADDRARDADDRL14", - "BRAM_UTURN_ADDRARDADDRL15", - "BRAM_UTURN_ADDRARDADDRL2", - "BRAM_UTURN_ADDRARDADDRL3", - "BRAM_UTURN_ADDRARDADDRL4", - "BRAM_UTURN_ADDRARDADDRL5", - "BRAM_UTURN_ADDRARDADDRL6", - "BRAM_UTURN_ADDRARDADDRL7", - "BRAM_UTURN_ADDRARDADDRL8", - "BRAM_UTURN_ADDRARDADDRL9", - "BRAM_UTURN_ADDRARDADDRU0", - "BRAM_UTURN_ADDRARDADDRU1", - "BRAM_UTURN_ADDRARDADDRU10", - "BRAM_UTURN_ADDRARDADDRU11", - "BRAM_UTURN_ADDRARDADDRU12", - "BRAM_UTURN_ADDRARDADDRU13", - "BRAM_UTURN_ADDRARDADDRU14", - "BRAM_UTURN_ADDRARDADDRU2", - "BRAM_UTURN_ADDRARDADDRU3", - "BRAM_UTURN_ADDRARDADDRU4", - "BRAM_UTURN_ADDRARDADDRU5", - "BRAM_UTURN_ADDRARDADDRU6", - "BRAM_UTURN_ADDRARDADDRU7", - "BRAM_UTURN_ADDRARDADDRU8", - "BRAM_UTURN_ADDRARDADDRU9", - "BRAM_UTURN_ADDRBWRADDRL0", - "BRAM_UTURN_ADDRBWRADDRL1", - "BRAM_UTURN_ADDRBWRADDRL10", - "BRAM_UTURN_ADDRBWRADDRL11", - "BRAM_UTURN_ADDRBWRADDRL12", - "BRAM_UTURN_ADDRBWRADDRL13", - "BRAM_UTURN_ADDRBWRADDRL14", - "BRAM_UTURN_ADDRBWRADDRL15", - "BRAM_UTURN_ADDRBWRADDRL2", - "BRAM_UTURN_ADDRBWRADDRL3", - "BRAM_UTURN_ADDRBWRADDRL4", - "BRAM_UTURN_ADDRBWRADDRL5", - "BRAM_UTURN_ADDRBWRADDRL6", - "BRAM_UTURN_ADDRBWRADDRL7", - "BRAM_UTURN_ADDRBWRADDRL8", - "BRAM_UTURN_ADDRBWRADDRL9", - "BRAM_UTURN_ADDRBWRADDRU0", - "BRAM_UTURN_ADDRBWRADDRU1", - "BRAM_UTURN_ADDRBWRADDRU10", - "BRAM_UTURN_ADDRBWRADDRU11", - "BRAM_UTURN_ADDRBWRADDRU12", - "BRAM_UTURN_ADDRBWRADDRU13", - "BRAM_UTURN_ADDRBWRADDRU14", - "BRAM_UTURN_ADDRBWRADDRU2", - "BRAM_UTURN_ADDRBWRADDRU3", - "BRAM_UTURN_ADDRBWRADDRU4", - "BRAM_UTURN_ADDRBWRADDRU5", - "BRAM_UTURN_ADDRBWRADDRU6", - "BRAM_UTURN_ADDRBWRADDRU7", - "BRAM_UTURN_ADDRBWRADDRU8", - "BRAM_UTURN_ADDRBWRADDRU9", - "BRAM_WL1END0_0", - "BRAM_WL1END0_1", - "BRAM_WL1END0_2", - "BRAM_WL1END0_3", - "BRAM_WL1END0_4", - "BRAM_WL1END1_0", - "BRAM_WL1END1_1", - "BRAM_WL1END1_2", - "BRAM_WL1END1_3", - "BRAM_WL1END1_4", - "BRAM_WL1END2_0", - "BRAM_WL1END2_1", - "BRAM_WL1END2_2", - "BRAM_WL1END2_3", - "BRAM_WL1END2_4", - "BRAM_WL1END3_0", - "BRAM_WL1END3_1", - "BRAM_WL1END3_2", - "BRAM_WL1END3_3", - "BRAM_WL1END3_4", - "BRAM_WR1END0_0", - "BRAM_WR1END0_1", - "BRAM_WR1END0_2", - "BRAM_WR1END0_3", - "BRAM_WR1END0_4", - "BRAM_WR1END1_0", - "BRAM_WR1END1_1", - "BRAM_WR1END1_2", - "BRAM_WR1END1_3", - "BRAM_WR1END1_4", - "BRAM_WR1END2_0", - "BRAM_WR1END2_1", - "BRAM_WR1END2_2", - "BRAM_WR1END2_3", - "BRAM_WR1END2_4", - "BRAM_WR1END3_0", - "BRAM_WR1END3_1", - "BRAM_WR1END3_2", - "BRAM_WR1END3_3", - "BRAM_WR1END3_4", - "BRAM_WW2A0_0", - "BRAM_WW2A0_1", - "BRAM_WW2A0_2", - "BRAM_WW2A0_3", - "BRAM_WW2A0_4", - "BRAM_WW2A1_0", - "BRAM_WW2A1_1", - "BRAM_WW2A1_2", - "BRAM_WW2A1_3", - "BRAM_WW2A1_4", - "BRAM_WW2A2_0", - "BRAM_WW2A2_1", - "BRAM_WW2A2_2", - "BRAM_WW2A2_3", - "BRAM_WW2A2_4", - "BRAM_WW2A3_0", - "BRAM_WW2A3_1", - "BRAM_WW2A3_2", - "BRAM_WW2A3_3", - "BRAM_WW2A3_4", - "BRAM_WW2END0_0", - "BRAM_WW2END0_1", - "BRAM_WW2END0_2", - "BRAM_WW2END0_3", - "BRAM_WW2END0_4", - "BRAM_WW2END1_0", - "BRAM_WW2END1_1", - "BRAM_WW2END1_2", - "BRAM_WW2END1_3", - "BRAM_WW2END1_4", - "BRAM_WW2END2_0", - "BRAM_WW2END2_1", - "BRAM_WW2END2_2", - "BRAM_WW2END2_3", - "BRAM_WW2END2_4", - "BRAM_WW2END3_0", - "BRAM_WW2END3_1", - "BRAM_WW2END3_2", - "BRAM_WW2END3_3", - "BRAM_WW2END3_4", - "BRAM_WW4A0_0", - "BRAM_WW4A0_1", - "BRAM_WW4A0_2", - "BRAM_WW4A0_3", - "BRAM_WW4A0_4", - "BRAM_WW4A1_0", - "BRAM_WW4A1_1", - "BRAM_WW4A1_2", - "BRAM_WW4A1_3", - "BRAM_WW4A1_4", - "BRAM_WW4A2_0", - "BRAM_WW4A2_1", - "BRAM_WW4A2_2", - "BRAM_WW4A2_3", - "BRAM_WW4A2_4", - "BRAM_WW4A3_0", - "BRAM_WW4A3_1", - "BRAM_WW4A3_2", - "BRAM_WW4A3_3", - "BRAM_WW4A3_4", - "BRAM_WW4B0_0", - "BRAM_WW4B0_1", - "BRAM_WW4B0_2", - "BRAM_WW4B0_3", - "BRAM_WW4B0_4", - "BRAM_WW4B1_0", - "BRAM_WW4B1_1", - "BRAM_WW4B1_2", - "BRAM_WW4B1_3", - "BRAM_WW4B1_4", - "BRAM_WW4B2_0", - "BRAM_WW4B2_1", - "BRAM_WW4B2_2", - "BRAM_WW4B2_3", - "BRAM_WW4B2_4", - "BRAM_WW4B3_0", - "BRAM_WW4B3_1", - "BRAM_WW4B3_2", - "BRAM_WW4B3_3", - "BRAM_WW4B3_4", - "BRAM_WW4C0_0", - "BRAM_WW4C0_1", - "BRAM_WW4C0_2", - "BRAM_WW4C0_3", - "BRAM_WW4C0_4", - "BRAM_WW4C1_0", - "BRAM_WW4C1_1", - "BRAM_WW4C1_2", - "BRAM_WW4C1_3", - "BRAM_WW4C1_4", - "BRAM_WW4C2_0", - "BRAM_WW4C2_1", - "BRAM_WW4C2_2", - "BRAM_WW4C2_3", - "BRAM_WW4C2_4", - "BRAM_WW4C3_0", - "BRAM_WW4C3_1", - "BRAM_WW4C3_2", - "BRAM_WW4C3_3", - "BRAM_WW4C3_4", - "BRAM_WW4END0_0", - "BRAM_WW4END0_1", - "BRAM_WW4END0_2", - "BRAM_WW4END0_3", - "BRAM_WW4END0_4", - "BRAM_WW4END1_0", - "BRAM_WW4END1_1", - "BRAM_WW4END1_2", - "BRAM_WW4END1_3", - "BRAM_WW4END1_4", - "BRAM_WW4END2_0", - "BRAM_WW4END2_1", - "BRAM_WW4END2_2", - "BRAM_WW4END2_3", - "BRAM_WW4END2_4", - "BRAM_WW4END3_0", - "BRAM_WW4END3_1", - "BRAM_WW4END3_2", - "BRAM_WW4END3_3", - "BRAM_WW4END3_4" - ] + "wires": { + "BRAM_ADDRARDADDRL0": null, + "BRAM_ADDRARDADDRL1": null, + "BRAM_ADDRARDADDRL10": null, + "BRAM_ADDRARDADDRL11": null, + "BRAM_ADDRARDADDRL12": null, + "BRAM_ADDRARDADDRL13": null, + "BRAM_ADDRARDADDRL14": null, + "BRAM_ADDRARDADDRL2": null, + "BRAM_ADDRARDADDRL3": null, + "BRAM_ADDRARDADDRL4": null, + "BRAM_ADDRARDADDRL5": null, + "BRAM_ADDRARDADDRL6": null, + "BRAM_ADDRARDADDRL7": null, + "BRAM_ADDRARDADDRL8": null, + "BRAM_ADDRARDADDRL9": null, + "BRAM_ADDRARDADDRU0": null, + "BRAM_ADDRARDADDRU1": null, + "BRAM_ADDRARDADDRU10": null, + "BRAM_ADDRARDADDRU11": null, + "BRAM_ADDRARDADDRU12": null, + "BRAM_ADDRARDADDRU13": null, + "BRAM_ADDRARDADDRU14": null, + "BRAM_ADDRARDADDRU2": null, + "BRAM_ADDRARDADDRU3": null, + "BRAM_ADDRARDADDRU4": null, + "BRAM_ADDRARDADDRU5": null, + "BRAM_ADDRARDADDRU6": null, + "BRAM_ADDRARDADDRU7": null, + "BRAM_ADDRARDADDRU8": null, + "BRAM_ADDRARDADDRU9": null, + "BRAM_ADDRBWRADDRL0": null, + "BRAM_ADDRBWRADDRL1": null, + "BRAM_ADDRBWRADDRL10": null, + "BRAM_ADDRBWRADDRL11": null, + "BRAM_ADDRBWRADDRL12": null, + "BRAM_ADDRBWRADDRL13": null, + "BRAM_ADDRBWRADDRL14": null, + "BRAM_ADDRBWRADDRL2": null, + "BRAM_ADDRBWRADDRL3": null, + "BRAM_ADDRBWRADDRL4": null, + "BRAM_ADDRBWRADDRL5": null, + "BRAM_ADDRBWRADDRL6": null, + "BRAM_ADDRBWRADDRL7": null, + "BRAM_ADDRBWRADDRL8": null, + "BRAM_ADDRBWRADDRL9": null, + "BRAM_ADDRBWRADDRU0": null, + "BRAM_ADDRBWRADDRU1": null, + "BRAM_ADDRBWRADDRU10": null, + "BRAM_ADDRBWRADDRU11": null, + "BRAM_ADDRBWRADDRU12": null, + "BRAM_ADDRBWRADDRU13": null, + "BRAM_ADDRBWRADDRU14": null, + "BRAM_ADDRBWRADDRU2": null, + "BRAM_ADDRBWRADDRU3": null, + "BRAM_ADDRBWRADDRU4": null, + "BRAM_ADDRBWRADDRU5": null, + "BRAM_ADDRBWRADDRU6": null, + "BRAM_ADDRBWRADDRU7": null, + "BRAM_ADDRBWRADDRU8": null, + "BRAM_ADDRBWRADDRU9": null, + "BRAM_BLOCK_OUTS_L_B0_0": null, + "BRAM_BLOCK_OUTS_L_B0_1": null, + "BRAM_BLOCK_OUTS_L_B0_2": null, + "BRAM_BLOCK_OUTS_L_B0_3": null, + "BRAM_BLOCK_OUTS_L_B0_4": null, + "BRAM_BLOCK_OUTS_L_B1_0": null, + "BRAM_BLOCK_OUTS_L_B1_1": null, + "BRAM_BLOCK_OUTS_L_B1_2": null, + "BRAM_BLOCK_OUTS_L_B1_3": null, + "BRAM_BLOCK_OUTS_L_B1_4": null, + "BRAM_BLOCK_OUTS_L_B2_0": null, + "BRAM_BLOCK_OUTS_L_B2_1": null, + "BRAM_BLOCK_OUTS_L_B2_2": null, + "BRAM_BLOCK_OUTS_L_B2_3": null, + "BRAM_BLOCK_OUTS_L_B2_4": null, + "BRAM_BLOCK_OUTS_L_B3_0": null, + "BRAM_BLOCK_OUTS_L_B3_1": null, + "BRAM_BLOCK_OUTS_L_B3_2": null, + "BRAM_BLOCK_OUTS_L_B3_3": null, + "BRAM_BLOCK_OUTS_L_B3_4": null, + "BRAM_BYP0_0": null, + "BRAM_BYP0_1": null, + "BRAM_BYP0_2": null, + "BRAM_BYP0_3": null, + "BRAM_BYP0_4": null, + "BRAM_BYP1_0": null, + "BRAM_BYP1_1": null, + "BRAM_BYP1_2": null, + "BRAM_BYP1_3": null, + "BRAM_BYP1_4": null, + "BRAM_BYP2_0": null, + "BRAM_BYP2_1": null, + "BRAM_BYP2_2": null, + "BRAM_BYP2_3": null, + "BRAM_BYP2_4": null, + "BRAM_BYP3_0": null, + "BRAM_BYP3_1": null, + "BRAM_BYP3_2": null, + "BRAM_BYP3_3": null, + "BRAM_BYP3_4": null, + "BRAM_BYP4_0": null, + "BRAM_BYP4_1": null, + "BRAM_BYP4_2": null, + "BRAM_BYP4_3": null, + "BRAM_BYP4_4": null, + "BRAM_BYP5_0": null, + "BRAM_BYP5_1": null, + "BRAM_BYP5_2": null, + "BRAM_BYP5_3": null, + "BRAM_BYP5_4": null, + "BRAM_BYP6_0": null, + "BRAM_BYP6_1": null, + "BRAM_BYP6_2": null, + "BRAM_BYP6_3": null, + "BRAM_BYP6_4": null, + "BRAM_BYP7_0": null, + "BRAM_BYP7_1": null, + "BRAM_BYP7_2": null, + "BRAM_BYP7_3": null, + "BRAM_BYP7_4": null, + "BRAM_CASCINBOT_ADDRARDADDRU0": null, + "BRAM_CASCINBOT_ADDRARDADDRU1": null, + "BRAM_CASCINBOT_ADDRARDADDRU10": null, + "BRAM_CASCINBOT_ADDRARDADDRU11": null, + "BRAM_CASCINBOT_ADDRARDADDRU12": null, + "BRAM_CASCINBOT_ADDRARDADDRU13": null, + "BRAM_CASCINBOT_ADDRARDADDRU14": null, + "BRAM_CASCINBOT_ADDRARDADDRU2": null, + "BRAM_CASCINBOT_ADDRARDADDRU3": null, + "BRAM_CASCINBOT_ADDRARDADDRU4": null, + "BRAM_CASCINBOT_ADDRARDADDRU5": null, + "BRAM_CASCINBOT_ADDRARDADDRU6": null, + "BRAM_CASCINBOT_ADDRARDADDRU7": null, + "BRAM_CASCINBOT_ADDRARDADDRU8": null, + "BRAM_CASCINBOT_ADDRARDADDRU9": null, + "BRAM_CASCINBOT_ADDRBWRADDRU0": null, + "BRAM_CASCINBOT_ADDRBWRADDRU1": null, + "BRAM_CASCINBOT_ADDRBWRADDRU10": null, + "BRAM_CASCINBOT_ADDRBWRADDRU11": null, + "BRAM_CASCINBOT_ADDRBWRADDRU12": null, + "BRAM_CASCINBOT_ADDRBWRADDRU13": null, + "BRAM_CASCINBOT_ADDRBWRADDRU14": null, + "BRAM_CASCINBOT_ADDRBWRADDRU2": null, + "BRAM_CASCINBOT_ADDRBWRADDRU3": null, + "BRAM_CASCINBOT_ADDRBWRADDRU4": null, + "BRAM_CASCINBOT_ADDRBWRADDRU5": null, + "BRAM_CASCINBOT_ADDRBWRADDRU6": null, + "BRAM_CASCINBOT_ADDRBWRADDRU7": null, + "BRAM_CASCINBOT_ADDRBWRADDRU8": null, + "BRAM_CASCINBOT_ADDRBWRADDRU9": null, + "BRAM_CASCINTOP_ADDRARDADDRU0": null, + "BRAM_CASCINTOP_ADDRARDADDRU1": null, + "BRAM_CASCINTOP_ADDRARDADDRU10": null, + "BRAM_CASCINTOP_ADDRARDADDRU11": null, + "BRAM_CASCINTOP_ADDRARDADDRU12": null, + "BRAM_CASCINTOP_ADDRARDADDRU13": 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"dst_wire": "BRAM_FIFO36_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_ADDRBWRADDRU8" }, "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_RAMB18_ADDRBWRADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_ADDRBWRADDRU8" }, "BRAM_R.BRAM_ADDRBWRADDRU8->>BRAM_UTURN_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_ADDRBWRADDRU8" }, "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_CASCOUT_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.106", + "0.129", + "0.280", + "0.338" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_CASCOUT_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.106", + "0.129", + "0.280", + "0.338" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_ADDRBWRADDRU9" }, "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_FIFO36_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_ADDRBWRADDRU9" }, "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_RAMB18_ADDRBWRADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_RAMB18_ADDRBWRADDR8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_ADDRBWRADDRU9" }, "BRAM_R.BRAM_ADDRBWRADDRU9->>BRAM_UTURN_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_ADDRBWRADDRU9" }, "BRAM_R.BRAM_BYP3_2->BRAM_FIFO18_WEBWE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_BYP3_2" }, "BRAM_R.BRAM_BYP3_2->BRAM_FIFO36_WEBWEL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_BYP3_2" }, "BRAM_R.BRAM_BYP6_2->BRAM_FIFO18_WEBWE7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_BYP6_2" }, "BRAM_R.BRAM_BYP6_2->BRAM_FIFO36_WEBWEL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_BYP6_2" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9" }, "BRAM_R.BRAM_CLK0_0->BRAM_FIFO18_REGCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_0" }, "BRAM_R.BRAM_CLK0_0->BRAM_FIFO36_REGCLKBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_0" }, "BRAM_R.BRAM_CLK0_1->BRAM_FIFO18_CLKBWRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_CLKBWRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_1" }, "BRAM_R.BRAM_CLK0_1->BRAM_FIFO36_CLKBWRCLKL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKBWRCLKL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_1" }, "BRAM_R.BRAM_CLK0_3->BRAM_FIFO18_CLKARDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_CLKARDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_3" }, "BRAM_R.BRAM_CLK0_3->BRAM_FIFO36_CLKARDCLKL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKARDCLKL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_3" }, "BRAM_R.BRAM_CLK0_4->BRAM_FIFO18_REGCLKARDRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCLKARDRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_4" }, "BRAM_R.BRAM_CLK0_4->BRAM_FIFO36_REGCLKARDRCLKL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_4" }, "BRAM_R.BRAM_CLK1_0->BRAM_FIFO36_REGCLKBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_0" }, "BRAM_R.BRAM_CLK1_0->BRAM_RAMB18_REGCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_0" }, "BRAM_R.BRAM_CLK1_1->BRAM_FIFO36_CLKBWRCLKU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKBWRCLKU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_1" }, "BRAM_R.BRAM_CLK1_1->BRAM_RAMB18_CLKBWRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_CLKBWRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_1" }, "BRAM_R.BRAM_CLK1_3->BRAM_FIFO36_CLKARDCLKU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKARDCLKU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_3" }, "BRAM_R.BRAM_CLK1_3->BRAM_RAMB18_CLKARDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_CLKARDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_3" }, "BRAM_R.BRAM_CLK1_4->BRAM_FIFO36_REGCLKARDRCLKU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_4" }, "BRAM_R.BRAM_CLK1_4->BRAM_RAMB18_REGCLKARDRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCLKARDRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_4" }, "BRAM_R.BRAM_CTRL0_0->BRAM_FIFO18_RSTREGB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTREGB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_0" }, "BRAM_R.BRAM_CTRL0_0->BRAM_FIFO36_RSTREGBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_0" }, "BRAM_R.BRAM_CTRL0_1->BRAM_FIFO18_RSTRAMB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTRAMB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_1" }, "BRAM_R.BRAM_CTRL0_1->BRAM_FIFO36_RSTRAMBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_1" }, "BRAM_R.BRAM_CTRL0_3->BRAM_FIFO18_RSTRAMARSTRAM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTRAMARSTRAM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_3" }, "BRAM_R.BRAM_CTRL0_3->BRAM_FIFO36_RSTRAMARSTRAMLRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMLRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_3" }, "BRAM_R.BRAM_CTRL0_4->BRAM_FIFO18_RSTREGARSTREG": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTREGARSTREG", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_4" }, "BRAM_R.BRAM_CTRL0_4->BRAM_FIFO36_RSTREGARSTREGL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGARSTREGL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_4" }, "BRAM_R.BRAM_CTRL1_0->BRAM_FIFO36_RSTREGBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_0" }, "BRAM_R.BRAM_CTRL1_0->BRAM_RAMB18_RSTREGB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTREGB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_0" }, "BRAM_R.BRAM_CTRL1_1->BRAM_FIFO36_RSTRAMBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_1" }, "BRAM_R.BRAM_CTRL1_1->BRAM_RAMB18_RSTRAMB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTRAMB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_1" }, "BRAM_R.BRAM_CTRL1_3->BRAM_FIFO36_RSTRAMARSTRAMU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_3" }, "BRAM_R.BRAM_CTRL1_3->BRAM_RAMB18_RSTRAMARSTRAM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTRAMARSTRAM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_3" }, "BRAM_R.BRAM_CTRL1_4->BRAM_FIFO36_RSTREGARSTREGU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGARSTREGU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_4" }, "BRAM_R.BRAM_CTRL1_4->BRAM_RAMB18_RSTREGARSTREG": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTREGARSTREG", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_4" }, "BRAM_R.BRAM_FAN1_2->BRAM_FIFO36_WEBWEU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN1_2" }, "BRAM_R.BRAM_FAN1_2->BRAM_RAMB18_WEBWE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN1_2" }, "BRAM_R.BRAM_FAN5_2->BRAM_FIFO36_WEBWEU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN5_2" }, "BRAM_R.BRAM_FAN5_2->BRAM_RAMB18_WEBWE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN5_2" }, "BRAM_R.BRAM_FIFO18_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_ALMOSTEMPTY" }, "BRAM_R.BRAM_FIFO18_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_ALMOSTFULL" }, "BRAM_R.BRAM_FIFO18_DOADO0->BRAM_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO0" }, "BRAM_R.BRAM_FIFO18_DOADO1->BRAM_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO1" }, "BRAM_R.BRAM_FIFO18_DOADO10->BRAM_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO10" }, "BRAM_R.BRAM_FIFO18_DOADO11->BRAM_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO11" }, "BRAM_R.BRAM_FIFO18_DOADO12->BRAM_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO12" }, "BRAM_R.BRAM_FIFO18_DOADO13->BRAM_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO13" }, "BRAM_R.BRAM_FIFO18_DOADO14->BRAM_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO14" }, "BRAM_R.BRAM_FIFO18_DOADO15->BRAM_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO15" }, "BRAM_R.BRAM_FIFO18_DOADO2->BRAM_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO2" }, "BRAM_R.BRAM_FIFO18_DOADO3->BRAM_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO3" }, "BRAM_R.BRAM_FIFO18_DOADO4->BRAM_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO4" }, "BRAM_R.BRAM_FIFO18_DOADO5->BRAM_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO5" }, "BRAM_R.BRAM_FIFO18_DOADO6->BRAM_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO6" }, "BRAM_R.BRAM_FIFO18_DOADO7->BRAM_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO7" }, "BRAM_R.BRAM_FIFO18_DOADO8->BRAM_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO8" }, "BRAM_R.BRAM_FIFO18_DOADO9->BRAM_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO9" }, "BRAM_R.BRAM_FIFO18_DOBDO0->BRAM_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO0" }, "BRAM_R.BRAM_FIFO18_DOBDO1->BRAM_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO1" }, "BRAM_R.BRAM_FIFO18_DOBDO10->BRAM_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO10" }, "BRAM_R.BRAM_FIFO18_DOBDO11->BRAM_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO11" }, "BRAM_R.BRAM_FIFO18_DOBDO12->BRAM_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO12" }, "BRAM_R.BRAM_FIFO18_DOBDO13->BRAM_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO13" }, "BRAM_R.BRAM_FIFO18_DOBDO14->BRAM_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO14" }, "BRAM_R.BRAM_FIFO18_DOBDO15->BRAM_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO15" }, "BRAM_R.BRAM_FIFO18_DOBDO2->BRAM_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO2" }, "BRAM_R.BRAM_FIFO18_DOBDO3->BRAM_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO3" }, "BRAM_R.BRAM_FIFO18_DOBDO4->BRAM_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO4" }, "BRAM_R.BRAM_FIFO18_DOBDO5->BRAM_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO5" }, "BRAM_R.BRAM_FIFO18_DOBDO6->BRAM_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO6" }, "BRAM_R.BRAM_FIFO18_DOBDO7->BRAM_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO7" }, "BRAM_R.BRAM_FIFO18_DOBDO8->BRAM_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO8" }, "BRAM_R.BRAM_FIFO18_DOBDO9->BRAM_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO9" }, "BRAM_R.BRAM_FIFO18_DOPADOP0->BRAM_LOGIC_OUTS_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPADOP0" }, "BRAM_R.BRAM_FIFO18_DOPADOP1->BRAM_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPADOP1" }, "BRAM_R.BRAM_FIFO18_DOPBDOP0->BRAM_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPBDOP0" }, "BRAM_R.BRAM_FIFO18_DOPBDOP1->BRAM_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPBDOP1" }, "BRAM_R.BRAM_FIFO18_EMPTY->BRAM_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_EMPTY" }, "BRAM_R.BRAM_FIFO18_FULL->BRAM_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_FULL" }, "BRAM_R.BRAM_FIFO18_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT0" }, "BRAM_R.BRAM_FIFO18_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT1" }, "BRAM_R.BRAM_FIFO18_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT10" }, "BRAM_R.BRAM_FIFO18_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT11" }, "BRAM_R.BRAM_FIFO18_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT2" }, "BRAM_R.BRAM_FIFO18_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT3" }, "BRAM_R.BRAM_FIFO18_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT4" }, "BRAM_R.BRAM_FIFO18_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT5" }, "BRAM_R.BRAM_FIFO18_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT6" }, "BRAM_R.BRAM_FIFO18_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT7" }, "BRAM_R.BRAM_FIFO18_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT8" }, "BRAM_R.BRAM_FIFO18_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT9" }, "BRAM_R.BRAM_FIFO18_RDERR->BRAM_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDERR" }, "BRAM_R.BRAM_FIFO18_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT0" }, "BRAM_R.BRAM_FIFO18_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT1" }, "BRAM_R.BRAM_FIFO18_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT10" }, "BRAM_R.BRAM_FIFO18_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT11" }, "BRAM_R.BRAM_FIFO18_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT2" }, "BRAM_R.BRAM_FIFO18_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT3" }, "BRAM_R.BRAM_FIFO18_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT4" }, "BRAM_R.BRAM_FIFO18_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT5" }, "BRAM_R.BRAM_FIFO18_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT6" }, "BRAM_R.BRAM_FIFO18_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT7" }, "BRAM_R.BRAM_FIFO18_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT8" }, "BRAM_R.BRAM_FIFO18_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT9" }, "BRAM_R.BRAM_FIFO18_WRERR->BRAM_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRERR" }, "BRAM_R.BRAM_FIFO36_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ALMOSTEMPTY" }, "BRAM_R.BRAM_FIFO36_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ALMOSTFULL" }, "BRAM_R.BRAM_FIFO36_CASCADEOUTA->BRAM_FIFO36_CASCADEOUTA_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CASCADEOUTA_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_CASCADEOUTA" }, "BRAM_R.BRAM_FIFO36_CASCADEOUTB->BRAM_FIFO36_CASCADEOUTB_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CASCADEOUTB_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_CASCADEOUTB" }, "BRAM_R.BRAM_FIFO36_DBITERR->BRAM_LOGIC_OUTS_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DBITERR" }, "BRAM_R.BRAM_FIFO36_DOADOL0->BRAM_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL0" }, "BRAM_R.BRAM_FIFO36_DOADOL1->BRAM_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL1" }, "BRAM_R.BRAM_FIFO36_DOADOL10->BRAM_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL10" }, "BRAM_R.BRAM_FIFO36_DOADOL11->BRAM_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL11" }, "BRAM_R.BRAM_FIFO36_DOADOL12->BRAM_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL12" }, "BRAM_R.BRAM_FIFO36_DOADOL13->BRAM_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL13" }, "BRAM_R.BRAM_FIFO36_DOADOL14->BRAM_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL14" }, "BRAM_R.BRAM_FIFO36_DOADOL15->BRAM_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL15" }, "BRAM_R.BRAM_FIFO36_DOADOL2->BRAM_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL2" }, "BRAM_R.BRAM_FIFO36_DOADOL3->BRAM_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL3" }, "BRAM_R.BRAM_FIFO36_DOADOL4->BRAM_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL4" }, "BRAM_R.BRAM_FIFO36_DOADOL5->BRAM_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL5" }, "BRAM_R.BRAM_FIFO36_DOADOL6->BRAM_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL6" }, "BRAM_R.BRAM_FIFO36_DOADOL7->BRAM_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL7" }, "BRAM_R.BRAM_FIFO36_DOADOL8->BRAM_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL8" }, "BRAM_R.BRAM_FIFO36_DOADOL9->BRAM_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL9" }, "BRAM_R.BRAM_FIFO36_DOADOU0->BRAM_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU0" }, "BRAM_R.BRAM_FIFO36_DOADOU1->BRAM_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU1" }, "BRAM_R.BRAM_FIFO36_DOADOU10->BRAM_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU10" }, "BRAM_R.BRAM_FIFO36_DOADOU11->BRAM_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU11" }, "BRAM_R.BRAM_FIFO36_DOADOU12->BRAM_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU12" }, "BRAM_R.BRAM_FIFO36_DOADOU13->BRAM_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU13" }, "BRAM_R.BRAM_FIFO36_DOADOU14->BRAM_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU14" }, "BRAM_R.BRAM_FIFO36_DOADOU15->BRAM_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU15" }, "BRAM_R.BRAM_FIFO36_DOADOU2->BRAM_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU2" }, "BRAM_R.BRAM_FIFO36_DOADOU3->BRAM_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU3" }, "BRAM_R.BRAM_FIFO36_DOADOU4->BRAM_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU4" }, "BRAM_R.BRAM_FIFO36_DOADOU5->BRAM_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU5" }, "BRAM_R.BRAM_FIFO36_DOADOU6->BRAM_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU6" }, "BRAM_R.BRAM_FIFO36_DOADOU7->BRAM_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU7" }, "BRAM_R.BRAM_FIFO36_DOADOU8->BRAM_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU8" }, "BRAM_R.BRAM_FIFO36_DOADOU9->BRAM_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU9" }, "BRAM_R.BRAM_FIFO36_DOBDOL0->BRAM_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL0" }, "BRAM_R.BRAM_FIFO36_DOBDOL1->BRAM_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL1" }, "BRAM_R.BRAM_FIFO36_DOBDOL10->BRAM_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL10" }, "BRAM_R.BRAM_FIFO36_DOBDOL11->BRAM_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL11" }, "BRAM_R.BRAM_FIFO36_DOBDOL12->BRAM_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL12" }, "BRAM_R.BRAM_FIFO36_DOBDOL13->BRAM_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL13" }, "BRAM_R.BRAM_FIFO36_DOBDOL14->BRAM_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL14" }, "BRAM_R.BRAM_FIFO36_DOBDOL15->BRAM_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL15" }, "BRAM_R.BRAM_FIFO36_DOBDOL2->BRAM_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL2" }, "BRAM_R.BRAM_FIFO36_DOBDOL3->BRAM_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL3" }, "BRAM_R.BRAM_FIFO36_DOBDOL4->BRAM_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL4" }, "BRAM_R.BRAM_FIFO36_DOBDOL5->BRAM_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL5" }, "BRAM_R.BRAM_FIFO36_DOBDOL6->BRAM_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL6" }, "BRAM_R.BRAM_FIFO36_DOBDOL7->BRAM_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL7" }, "BRAM_R.BRAM_FIFO36_DOBDOL8->BRAM_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL8" }, "BRAM_R.BRAM_FIFO36_DOBDOL9->BRAM_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL9" }, "BRAM_R.BRAM_FIFO36_DOBDOU0->BRAM_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU0" }, "BRAM_R.BRAM_FIFO36_DOBDOU1->BRAM_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU1" }, "BRAM_R.BRAM_FIFO36_DOBDOU10->BRAM_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU10" }, "BRAM_R.BRAM_FIFO36_DOBDOU11->BRAM_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU11" }, "BRAM_R.BRAM_FIFO36_DOBDOU12->BRAM_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU12" }, "BRAM_R.BRAM_FIFO36_DOBDOU13->BRAM_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU13" }, "BRAM_R.BRAM_FIFO36_DOBDOU14->BRAM_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU14" }, "BRAM_R.BRAM_FIFO36_DOBDOU15->BRAM_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU15" }, "BRAM_R.BRAM_FIFO36_DOBDOU2->BRAM_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU2" }, "BRAM_R.BRAM_FIFO36_DOBDOU3->BRAM_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU3" }, "BRAM_R.BRAM_FIFO36_DOBDOU4->BRAM_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU4" }, "BRAM_R.BRAM_FIFO36_DOBDOU5->BRAM_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU5" }, "BRAM_R.BRAM_FIFO36_DOBDOU6->BRAM_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU6" }, "BRAM_R.BRAM_FIFO36_DOBDOU7->BRAM_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU7" }, "BRAM_R.BRAM_FIFO36_DOBDOU8->BRAM_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU8" }, "BRAM_R.BRAM_FIFO36_DOBDOU9->BRAM_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU9" }, "BRAM_R.BRAM_FIFO36_DOPADOPL0->BRAM_LOGIC_OUTS_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPL0" }, "BRAM_R.BRAM_FIFO36_DOPADOPL1->BRAM_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPL1" }, "BRAM_R.BRAM_FIFO36_DOPADOPU0->BRAM_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPU0" }, "BRAM_R.BRAM_FIFO36_DOPADOPU1->BRAM_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPU1" }, "BRAM_R.BRAM_FIFO36_DOPBDOPL0->BRAM_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPL0" }, "BRAM_R.BRAM_FIFO36_DOPBDOPL1->BRAM_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPL1" }, "BRAM_R.BRAM_FIFO36_DOPBDOPU0->BRAM_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPU0" }, "BRAM_R.BRAM_FIFO36_DOPBDOPU1->BRAM_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPU1" }, "BRAM_R.BRAM_FIFO36_ECCPARITY0->BRAM_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY0" }, "BRAM_R.BRAM_FIFO36_ECCPARITY1->BRAM_LOGIC_OUTS_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY1" }, "BRAM_R.BRAM_FIFO36_ECCPARITY2->BRAM_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY2" }, "BRAM_R.BRAM_FIFO36_ECCPARITY3->BRAM_LOGIC_OUTS_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY3" }, "BRAM_R.BRAM_FIFO36_ECCPARITY4->BRAM_LOGIC_OUTS_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY4" }, "BRAM_R.BRAM_FIFO36_ECCPARITY5->BRAM_LOGIC_OUTS_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY5" }, "BRAM_R.BRAM_FIFO36_ECCPARITY6->BRAM_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY6" }, "BRAM_R.BRAM_FIFO36_ECCPARITY7->BRAM_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY7" }, "BRAM_R.BRAM_FIFO36_EMPTY->BRAM_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_EMPTY" }, "BRAM_R.BRAM_FIFO36_FULL->BRAM_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_FULL" }, "BRAM_R.BRAM_FIFO36_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT0" }, "BRAM_R.BRAM_FIFO36_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT1" }, "BRAM_R.BRAM_FIFO36_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT10" }, "BRAM_R.BRAM_FIFO36_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT11" }, "BRAM_R.BRAM_FIFO36_RDCOUNT12->BRAM_LOGIC_OUTS_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT12" }, "BRAM_R.BRAM_FIFO36_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT2" }, "BRAM_R.BRAM_FIFO36_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT3" }, "BRAM_R.BRAM_FIFO36_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT4" }, "BRAM_R.BRAM_FIFO36_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT5" }, "BRAM_R.BRAM_FIFO36_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT6" }, "BRAM_R.BRAM_FIFO36_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT7" }, "BRAM_R.BRAM_FIFO36_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT8" }, "BRAM_R.BRAM_FIFO36_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT9" }, "BRAM_R.BRAM_FIFO36_RDERR->BRAM_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDERR" }, "BRAM_R.BRAM_FIFO36_SBITERR->BRAM_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_SBITERR" }, "BRAM_R.BRAM_FIFO36_TSTOUT0->BRAM_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT0" }, "BRAM_R.BRAM_FIFO36_TSTOUT1->BRAM_LOGIC_OUTS_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT1" }, "BRAM_R.BRAM_FIFO36_TSTOUT2->BRAM_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT2" }, "BRAM_R.BRAM_FIFO36_TSTOUT3->BRAM_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT3" }, "BRAM_R.BRAM_FIFO36_TSTOUT4->BRAM_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT4" }, "BRAM_R.BRAM_FIFO36_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT0" }, "BRAM_R.BRAM_FIFO36_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT1" }, "BRAM_R.BRAM_FIFO36_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT10" }, "BRAM_R.BRAM_FIFO36_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT11" }, "BRAM_R.BRAM_FIFO36_WRCOUNT12->BRAM_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT12" }, "BRAM_R.BRAM_FIFO36_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT2" }, "BRAM_R.BRAM_FIFO36_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT3" }, "BRAM_R.BRAM_FIFO36_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT4" }, "BRAM_R.BRAM_FIFO36_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT5" }, "BRAM_R.BRAM_FIFO36_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT6" }, "BRAM_R.BRAM_FIFO36_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT7" }, "BRAM_R.BRAM_FIFO36_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT8" }, "BRAM_R.BRAM_FIFO36_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT9" }, "BRAM_R.BRAM_FIFO36_WRERR->BRAM_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRERR" }, "BRAM_R.BRAM_IMUX0_0->BRAM_FIFO36_TSTBRAMRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTBRAMRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX0_0" }, "BRAM_R.BRAM_IMUX10_0->BRAM_FIFO36_TSTCNT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_0" }, "BRAM_R.BRAM_IMUX10_1->BRAM_R_IMUX_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_1" }, "BRAM_R.BRAM_IMUX10_2->BRAM_FIFO36_ENARDENU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENARDENU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_2" }, "BRAM_R.BRAM_IMUX10_2->BRAM_RAMB18_ENARDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_ENARDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_2" }, "BRAM_R.BRAM_IMUX10_3->BRAM_R_IMUX_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_3" }, "BRAM_R.BRAM_IMUX10_4->BRAM_FIFO36_DIADIU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_4" }, "BRAM_R.BRAM_IMUX10_4->BRAM_RAMB18_DIADI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_4" }, "BRAM_R.BRAM_IMUX11_0->BRAM_FIFO36_TSTCNT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_0" }, "BRAM_R.BRAM_IMUX11_1->BRAM_R_IMUX_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_1" }, "BRAM_R.BRAM_IMUX11_2->BRAM_FIFO36_REGCEAREGCEU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEAREGCEU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_2" }, "BRAM_R.BRAM_IMUX11_2->BRAM_RAMB18_REGCEAREGCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCEAREGCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_2" }, "BRAM_R.BRAM_IMUX11_3->BRAM_R_IMUX_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_3" }, "BRAM_R.BRAM_IMUX11_4->BRAM_FIFO36_DIADIU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_4" }, "BRAM_R.BRAM_IMUX11_4->BRAM_RAMB18_DIADI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_4" }, "BRAM_R.BRAM_IMUX12_0->BRAM_FIFO36_TSTCNT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_0" }, "BRAM_R.BRAM_IMUX12_1->BRAM_R_IMUX_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_1" }, "BRAM_R.BRAM_IMUX12_2->BRAM_R_IMUX_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_2" }, "BRAM_R.BRAM_IMUX12_3->BRAM_R_IMUX_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_3" }, "BRAM_R.BRAM_IMUX12_4->BRAM_FIFO36_DIADIU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_4" }, "BRAM_R.BRAM_IMUX12_4->BRAM_RAMB18_DIADI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_4" }, "BRAM_R.BRAM_IMUX13_0->BRAM_FIFO36_TSTCNT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_0" }, "BRAM_R.BRAM_IMUX13_1->BRAM_R_IMUX_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_1" }, "BRAM_R.BRAM_IMUX13_2->BRAM_FIFO36_WEBWEU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_2" }, "BRAM_R.BRAM_IMUX13_2->BRAM_RAMB18_WEBWE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_2" }, "BRAM_R.BRAM_IMUX13_3->BRAM_R_IMUX_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_3" }, "BRAM_R.BRAM_IMUX13_4->BRAM_FIFO36_DIADIU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_4" }, "BRAM_R.BRAM_IMUX13_4->BRAM_RAMB18_DIADI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_4" }, "BRAM_R.BRAM_IMUX14_0->BRAM_FIFO36_TSTCNT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_0" }, "BRAM_R.BRAM_IMUX14_1->BRAM_R_IMUX_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_1" }, "BRAM_R.BRAM_IMUX14_2->BRAM_FIFO36_WEBWEU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_2" }, "BRAM_R.BRAM_IMUX14_2->BRAM_RAMB18_WEBWE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_2" }, "BRAM_R.BRAM_IMUX14_3->BRAM_R_IMUX_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_3" }, "BRAM_R.BRAM_IMUX14_4->BRAM_FIFO36_DIADIU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_4" }, "BRAM_R.BRAM_IMUX14_4->BRAM_RAMB18_DIADI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_4" }, "BRAM_R.BRAM_IMUX15_0->BRAM_FIFO36_TSTCNT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_0" }, "BRAM_R.BRAM_IMUX15_1->BRAM_R_IMUX_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_1" }, "BRAM_R.BRAM_IMUX15_2->BRAM_FIFO36_DIADIU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_2" }, "BRAM_R.BRAM_IMUX15_2->BRAM_RAMB18_DIADI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_2" }, "BRAM_R.BRAM_IMUX15_3->BRAM_FIFO36_DIPADIPU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_3" }, "BRAM_R.BRAM_IMUX15_3->BRAM_RAMB18_DIPADIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPADIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_3" }, "BRAM_R.BRAM_IMUX15_4->BRAM_FIFO36_DIADIU15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_4" }, "BRAM_R.BRAM_IMUX15_4->BRAM_RAMB18_DIADI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_4" }, "BRAM_R.BRAM_IMUX16_0->BRAM_FIFO36_TSTIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_0" }, "BRAM_R.BRAM_IMUX16_1->BRAM_FIFO18_DIADI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_1" }, "BRAM_R.BRAM_IMUX16_1->BRAM_FIFO36_DIADIL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_1" }, "BRAM_R.BRAM_IMUX16_2->BRAM_FIFO18_WEA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_2" }, "BRAM_R.BRAM_IMUX16_2->BRAM_FIFO36_WEAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_2" }, "BRAM_R.BRAM_IMUX16_3->BRAM_R_IMUX_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_3" }, "BRAM_R.BRAM_IMUX16_4->BRAM_FIFO36_DIBDIU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_4" }, "BRAM_R.BRAM_IMUX16_4->BRAM_RAMB18_DIBDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_4" }, "BRAM_R.BRAM_IMUX17_1->BRAM_R_IMUX_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_1" }, "BRAM_R.BRAM_IMUX17_2->BRAM_FIFO18_WEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_2" }, "BRAM_R.BRAM_IMUX17_2->BRAM_FIFO36_WEAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_2" }, "BRAM_R.BRAM_IMUX17_3->BRAM_R_IMUX_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_3" }, "BRAM_R.BRAM_IMUX17_4->BRAM_FIFO36_DIBDIU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_4" }, "BRAM_R.BRAM_IMUX17_4->BRAM_RAMB18_DIBDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_4" }, "BRAM_R.BRAM_IMUX18_0->BRAM_FIFO36_TSTRDOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_0" }, "BRAM_R.BRAM_IMUX18_1->BRAM_R_IMUX_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_1" }, "BRAM_R.BRAM_IMUX18_2->BRAM_FIFO18_ENARDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_ENARDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_2" }, "BRAM_R.BRAM_IMUX18_2->BRAM_FIFO36_ENARDENL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENARDENL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_2" }, "BRAM_R.BRAM_IMUX18_3->BRAM_R_IMUX_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_3" }, "BRAM_R.BRAM_IMUX18_4->BRAM_FIFO36_DIBDIU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_4" }, "BRAM_R.BRAM_IMUX18_4->BRAM_RAMB18_DIBDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_4" }, "BRAM_R.BRAM_IMUX19_0->BRAM_FIFO36_TSTRDOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_0" }, "BRAM_R.BRAM_IMUX19_1->BRAM_R_IMUX_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_1" }, "BRAM_R.BRAM_IMUX19_2->BRAM_FIFO18_REGCEAREGCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCEAREGCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_2" }, "BRAM_R.BRAM_IMUX19_2->BRAM_FIFO36_REGCEAREGCEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEAREGCEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_2" }, "BRAM_R.BRAM_IMUX19_3->BRAM_R_IMUX_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_3" }, "BRAM_R.BRAM_IMUX19_4->BRAM_FIFO36_DIBDIU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_4" }, "BRAM_R.BRAM_IMUX19_4->BRAM_RAMB18_DIBDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_4" }, "BRAM_R.BRAM_IMUX1_1->BRAM_FIFO18_DIPBDIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPBDIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_1" }, "BRAM_R.BRAM_IMUX1_1->BRAM_FIFO36_DIPBDIPL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_1" }, "BRAM_R.BRAM_IMUX1_2->BRAM_FIFO18_DIBDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_2" }, "BRAM_R.BRAM_IMUX1_2->BRAM_FIFO36_DIBDIL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_2" }, "BRAM_R.BRAM_IMUX1_3->BRAM_FIFO36_DIBDIU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_3" }, "BRAM_R.BRAM_IMUX1_3->BRAM_RAMB18_DIBDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_3" }, "BRAM_R.BRAM_IMUX20_0->BRAM_FIFO36_TSTRDOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_0" }, "BRAM_R.BRAM_IMUX20_1->BRAM_R_IMUX_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_1" }, "BRAM_R.BRAM_IMUX20_2->BRAM_R_IMUX_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_2" }, "BRAM_R.BRAM_IMUX20_3->BRAM_R_IMUX_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_3" }, "BRAM_R.BRAM_IMUX20_4->BRAM_FIFO36_DIBDIU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_4" }, "BRAM_R.BRAM_IMUX20_4->BRAM_RAMB18_DIBDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_4" }, "BRAM_R.BRAM_IMUX21_0->BRAM_FIFO36_TSTRDOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_0" }, "BRAM_R.BRAM_IMUX21_1->BRAM_R_IMUX_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_1" }, "BRAM_R.BRAM_IMUX21_2->BRAM_FIFO18_WEBWE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_2" }, "BRAM_R.BRAM_IMUX21_2->BRAM_FIFO36_WEBWEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_2" }, "BRAM_R.BRAM_IMUX21_3->BRAM_R_IMUX_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_3" }, "BRAM_R.BRAM_IMUX21_4->BRAM_FIFO36_DIBDIU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_4" }, "BRAM_R.BRAM_IMUX21_4->BRAM_RAMB18_DIBDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_4" }, "BRAM_R.BRAM_IMUX22_0->BRAM_FIFO36_TSTRDOS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_0" }, "BRAM_R.BRAM_IMUX22_1->BRAM_R_IMUX_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_1" }, "BRAM_R.BRAM_IMUX22_2->BRAM_FIFO18_WEBWE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_2" }, "BRAM_R.BRAM_IMUX22_2->BRAM_FIFO36_WEBWEL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_2" }, "BRAM_R.BRAM_IMUX22_3->BRAM_R_IMUX_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_3" }, "BRAM_R.BRAM_IMUX22_4->BRAM_FIFO36_DIBDIU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_4" }, "BRAM_R.BRAM_IMUX22_4->BRAM_RAMB18_DIBDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_4" }, "BRAM_R.BRAM_IMUX23_0->BRAM_FIFO36_TSTRDOS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_0" }, "BRAM_R.BRAM_IMUX23_1->BRAM_R_IMUX_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_1" }, "BRAM_R.BRAM_IMUX23_2->BRAM_FIFO36_DIBDIU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_2" }, "BRAM_R.BRAM_IMUX23_2->BRAM_RAMB18_DIBDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_2" }, "BRAM_R.BRAM_IMUX23_3->BRAM_FIFO36_DIPBDIPU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_3" }, "BRAM_R.BRAM_IMUX23_3->BRAM_RAMB18_DIPBDIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPBDIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_3" }, "BRAM_R.BRAM_IMUX23_4->BRAM_FIFO36_DIBDIU15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_4" }, "BRAM_R.BRAM_IMUX23_4->BRAM_RAMB18_DIBDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_4" }, "BRAM_R.BRAM_IMUX24_1->BRAM_FIFO36_DIBDIU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_1" }, "BRAM_R.BRAM_IMUX24_1->BRAM_RAMB18_DIBDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_1" }, "BRAM_R.BRAM_IMUX24_2->BRAM_FIFO36_WEAU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_2" }, "BRAM_R.BRAM_IMUX24_2->BRAM_RAMB18_WEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_2" }, "BRAM_R.BRAM_IMUX24_3->BRAM_R_IMUX_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_3" }, "BRAM_R.BRAM_IMUX24_4->BRAM_FIFO36_TSTCNT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_4" }, "BRAM_R.BRAM_IMUX25_0->BRAM_FIFO18_DIADI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_0" }, "BRAM_R.BRAM_IMUX25_0->BRAM_FIFO36_DIADIL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_0" }, "BRAM_R.BRAM_IMUX25_1->BRAM_R_IMUX_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_1" }, "BRAM_R.BRAM_IMUX25_2->BRAM_FIFO36_WEAU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_2" }, "BRAM_R.BRAM_IMUX25_2->BRAM_RAMB18_WEA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_2" }, "BRAM_R.BRAM_IMUX25_3->BRAM_R_IMUX_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_3" }, "BRAM_R.BRAM_IMUX25_4->BRAM_FIFO36_TSTCNT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_4" }, "BRAM_R.BRAM_IMUX26_0->BRAM_FIFO18_DIADI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_0" }, "BRAM_R.BRAM_IMUX26_0->BRAM_FIFO36_DIADIL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_0" }, "BRAM_R.BRAM_IMUX26_1->BRAM_R_IMUX_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_1" }, "BRAM_R.BRAM_IMUX26_2->BRAM_FIFO36_ENBWRENU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENBWRENU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_2" }, "BRAM_R.BRAM_IMUX26_2->BRAM_RAMB18_ENBWREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_ENBWREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_2" }, "BRAM_R.BRAM_IMUX26_3->BRAM_R_IMUX_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_3" }, "BRAM_R.BRAM_IMUX26_4->BRAM_FIFO36_TSTCNT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_4" }, "BRAM_R.BRAM_IMUX27_0->BRAM_FIFO18_DIADI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_0" }, "BRAM_R.BRAM_IMUX27_0->BRAM_FIFO36_DIADIL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_0" }, "BRAM_R.BRAM_IMUX27_1->BRAM_R_IMUX_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_1" }, "BRAM_R.BRAM_IMUX27_2->BRAM_FIFO36_REGCEBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_2" }, "BRAM_R.BRAM_IMUX27_2->BRAM_RAMB18_REGCEB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCEB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_2" }, "BRAM_R.BRAM_IMUX27_3->BRAM_R_IMUX_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_3" }, "BRAM_R.BRAM_IMUX27_4->BRAM_FIFO36_TSTCNT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_4" }, "BRAM_R.BRAM_IMUX28_0->BRAM_FIFO18_DIADI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_0" }, "BRAM_R.BRAM_IMUX28_0->BRAM_FIFO36_DIADIL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_0" }, "BRAM_R.BRAM_IMUX28_1->BRAM_R_IMUX_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_1" }, "BRAM_R.BRAM_IMUX28_2->BRAM_R_IMUX_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_2" }, "BRAM_R.BRAM_IMUX28_3->BRAM_R_IMUX_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_3" }, "BRAM_R.BRAM_IMUX28_4->BRAM_FIFO36_TSTCNT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_4" }, "BRAM_R.BRAM_IMUX29_0->BRAM_FIFO18_DIADI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_0" }, "BRAM_R.BRAM_IMUX29_0->BRAM_FIFO36_DIADIL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_0" }, "BRAM_R.BRAM_IMUX29_1->BRAM_R_IMUX_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_1" }, "BRAM_R.BRAM_IMUX29_2->BRAM_FIFO36_WEBWEU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_2" }, "BRAM_R.BRAM_IMUX29_2->BRAM_RAMB18_WEBWE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_2" }, "BRAM_R.BRAM_IMUX29_3->BRAM_R_IMUX_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_3" }, "BRAM_R.BRAM_IMUX29_4->BRAM_FIFO36_TSTCNT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_4" }, "BRAM_R.BRAM_IMUX2_0->BRAM_FIFO36_TSTRDCNTOFF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDCNTOFF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_0" }, "BRAM_R.BRAM_IMUX2_1->BRAM_FIFO18_DIBDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_1" }, "BRAM_R.BRAM_IMUX2_1->BRAM_FIFO36_DIBDIL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_1" }, "BRAM_R.BRAM_IMUX2_2->BRAM_FIFO18_DIBDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_2" }, "BRAM_R.BRAM_IMUX2_2->BRAM_FIFO36_DIBDIL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_2" }, "BRAM_R.BRAM_IMUX2_3->BRAM_FIFO36_DIBDIU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_3" }, "BRAM_R.BRAM_IMUX2_3->BRAM_RAMB18_DIBDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_3" }, "BRAM_R.BRAM_IMUX30_0->BRAM_FIFO18_DIADI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_0" }, "BRAM_R.BRAM_IMUX30_0->BRAM_FIFO36_DIADIL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_0" }, "BRAM_R.BRAM_IMUX30_1->BRAM_R_IMUX_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_1" }, "BRAM_R.BRAM_IMUX30_2->BRAM_FIFO36_WEBWEU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_2" }, "BRAM_R.BRAM_IMUX30_2->BRAM_RAMB18_WEBWE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_2" }, "BRAM_R.BRAM_IMUX30_3->BRAM_R_IMUX_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_3" }, "BRAM_R.BRAM_IMUX30_4->BRAM_FIFO36_TSTCNT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_4" }, "BRAM_R.BRAM_IMUX31_0->BRAM_FIFO18_DIADI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_0" }, "BRAM_R.BRAM_IMUX31_0->BRAM_FIFO36_DIADIL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_0" }, "BRAM_R.BRAM_IMUX31_1->BRAM_R_IMUX_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_1" }, "BRAM_R.BRAM_IMUX31_2->BRAM_FIFO36_INJECTDBITERR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_INJECTDBITERR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_2" }, "BRAM_R.BRAM_IMUX31_3->BRAM_IMUX_R_ADDRARDADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_R_ADDRARDADDRL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_3" }, "BRAM_R.BRAM_IMUX32_1->BRAM_FIFO18_DIBDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_1" }, "BRAM_R.BRAM_IMUX32_1->BRAM_FIFO36_DIBDIL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_1" }, "BRAM_R.BRAM_IMUX32_2->BRAM_FIFO18_WEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_2" }, "BRAM_R.BRAM_IMUX32_2->BRAM_FIFO36_WEAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_2" }, "BRAM_R.BRAM_IMUX32_3->BRAM_R_IMUX_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_3" }, "BRAM_R.BRAM_IMUX32_4->BRAM_FIFO36_TSTRDOS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_4" }, "BRAM_R.BRAM_IMUX33_0->BRAM_FIFO18_DIBDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_0" }, "BRAM_R.BRAM_IMUX33_0->BRAM_FIFO36_DIBDIL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_0" }, "BRAM_R.BRAM_IMUX33_1->BRAM_R_IMUX_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_1" }, "BRAM_R.BRAM_IMUX33_2->BRAM_FIFO18_WEA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_2" }, "BRAM_R.BRAM_IMUX33_2->BRAM_FIFO36_WEAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_2" }, "BRAM_R.BRAM_IMUX33_3->BRAM_R_IMUX_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_3" }, "BRAM_R.BRAM_IMUX33_4->BRAM_FIFO36_TSTRDOS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_4" }, "BRAM_R.BRAM_IMUX34_0->BRAM_FIFO18_DIBDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_0" }, "BRAM_R.BRAM_IMUX34_0->BRAM_FIFO36_DIBDIL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_0" }, "BRAM_R.BRAM_IMUX34_1->BRAM_R_IMUX_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_1" }, "BRAM_R.BRAM_IMUX34_2->BRAM_FIFO18_ENBWREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_ENBWREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_2" }, "BRAM_R.BRAM_IMUX34_2->BRAM_FIFO36_ENBWRENL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENBWRENL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_2" }, "BRAM_R.BRAM_IMUX34_3->BRAM_R_IMUX_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_3" }, "BRAM_R.BRAM_IMUX34_4->BRAM_FIFO36_TSTRDOS8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_4" }, "BRAM_R.BRAM_IMUX35_0->BRAM_FIFO18_DIBDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_0" }, "BRAM_R.BRAM_IMUX35_0->BRAM_FIFO36_DIBDIL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_0" }, "BRAM_R.BRAM_IMUX35_1->BRAM_R_IMUX_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_1" }, "BRAM_R.BRAM_IMUX35_2->BRAM_FIFO18_REGCEB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCEB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_2" }, "BRAM_R.BRAM_IMUX35_2->BRAM_FIFO36_REGCEBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_2" }, "BRAM_R.BRAM_IMUX35_3->BRAM_R_IMUX_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_3" }, "BRAM_R.BRAM_IMUX35_4->BRAM_FIFO36_TSTRDOS9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_4" }, "BRAM_R.BRAM_IMUX36_0->BRAM_FIFO18_DIBDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_0" }, "BRAM_R.BRAM_IMUX36_0->BRAM_FIFO36_DIBDIL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_0" }, "BRAM_R.BRAM_IMUX36_1->BRAM_R_IMUX_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_1" }, "BRAM_R.BRAM_IMUX36_2->BRAM_R_IMUX_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_2" }, "BRAM_R.BRAM_IMUX36_3->BRAM_R_IMUX_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_3" }, "BRAM_R.BRAM_IMUX36_4->BRAM_FIFO36_TSTRDOS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_4" }, "BRAM_R.BRAM_IMUX37_0->BRAM_FIFO18_DIBDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_0" }, "BRAM_R.BRAM_IMUX37_0->BRAM_FIFO36_DIBDIL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_0" }, "BRAM_R.BRAM_IMUX37_1->BRAM_R_IMUX_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_1" }, "BRAM_R.BRAM_IMUX37_2->BRAM_FIFO18_WEBWE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_2" }, "BRAM_R.BRAM_IMUX37_2->BRAM_FIFO36_WEBWEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_2" }, "BRAM_R.BRAM_IMUX37_3->BRAM_R_IMUX_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_3" }, "BRAM_R.BRAM_IMUX37_4->BRAM_FIFO36_TSTRDOS11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_4" }, "BRAM_R.BRAM_IMUX38_0->BRAM_FIFO18_DIBDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_0" }, "BRAM_R.BRAM_IMUX38_0->BRAM_FIFO36_DIBDIL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_0" }, "BRAM_R.BRAM_IMUX38_1->BRAM_R_IMUX_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_1" }, "BRAM_R.BRAM_IMUX38_2->BRAM_FIFO18_WEBWE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_2" }, "BRAM_R.BRAM_IMUX38_2->BRAM_FIFO36_WEBWEL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_2" }, "BRAM_R.BRAM_IMUX38_3->BRAM_R_IMUX_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_3" }, "BRAM_R.BRAM_IMUX38_4->BRAM_FIFO36_TSTRDOS12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_4" }, "BRAM_R.BRAM_IMUX39_0->BRAM_FIFO18_DIBDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_0" }, "BRAM_R.BRAM_IMUX39_0->BRAM_FIFO36_DIBDIL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_0" }, "BRAM_R.BRAM_IMUX39_1->BRAM_R_IMUX_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_1" }, "BRAM_R.BRAM_IMUX39_2->BRAM_FIFO36_INJECTSBITERR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_INJECTSBITERR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_2" }, "BRAM_R.BRAM_IMUX39_3->BRAM_IMUX_R_ADDRBWRADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_3" }, "BRAM_R.BRAM_IMUX3_0->BRAM_FIFO36_TSTWRCNTOFF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWRCNTOFF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_0" }, "BRAM_R.BRAM_IMUX3_1->BRAM_FIFO18_DIBDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_1" }, "BRAM_R.BRAM_IMUX3_1->BRAM_FIFO36_DIBDIL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_1" }, "BRAM_R.BRAM_IMUX3_2->BRAM_FIFO18_DIPADIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPADIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_2" }, "BRAM_R.BRAM_IMUX3_2->BRAM_FIFO36_DIPADIPL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_2" }, "BRAM_R.BRAM_IMUX3_3->BRAM_FIFO36_DIBDIU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_3" }, "BRAM_R.BRAM_IMUX3_3->BRAM_RAMB18_DIBDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_3" }, "BRAM_R.BRAM_IMUX40_1->BRAM_FIFO18_DIPADIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPADIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_1" }, "BRAM_R.BRAM_IMUX40_1->BRAM_FIFO36_DIPADIPL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_1" }, "BRAM_R.BRAM_IMUX40_2->BRAM_FIFO18_DIADI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_2" }, "BRAM_R.BRAM_IMUX40_2->BRAM_FIFO36_DIADIL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_2" }, "BRAM_R.BRAM_IMUX40_3->BRAM_FIFO36_DIADIU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_3" }, "BRAM_R.BRAM_IMUX40_3->BRAM_RAMB18_DIADI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_3" }, "BRAM_R.BRAM_IMUX40_4->BRAM_FIFO36_TSTWROS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_4" }, "BRAM_R.BRAM_IMUX41_0->BRAM_FIFO36_TSTIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_0" }, "BRAM_R.BRAM_IMUX41_1->BRAM_FIFO18_DIADI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_1" }, "BRAM_R.BRAM_IMUX41_1->BRAM_FIFO36_DIADIL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_1" }, "BRAM_R.BRAM_IMUX41_2->BRAM_FIFO18_DIADI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_2" }, "BRAM_R.BRAM_IMUX41_2->BRAM_FIFO36_DIADIL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_2" }, "BRAM_R.BRAM_IMUX41_3->BRAM_FIFO36_DIADIU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_3" }, "BRAM_R.BRAM_IMUX41_3->BRAM_RAMB18_DIADI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_3" }, "BRAM_R.BRAM_IMUX41_4->BRAM_FIFO36_TSTWROS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_4" }, "BRAM_R.BRAM_IMUX42_0->BRAM_FIFO36_TSTWROS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_0" }, "BRAM_R.BRAM_IMUX42_1->BRAM_FIFO18_DIADI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_1" }, "BRAM_R.BRAM_IMUX42_1->BRAM_FIFO36_DIADIL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_1" }, "BRAM_R.BRAM_IMUX42_2->BRAM_FIFO36_DIPADIPU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_2" }, "BRAM_R.BRAM_IMUX42_2->BRAM_RAMB18_DIPADIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPADIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_2" }, "BRAM_R.BRAM_IMUX42_3->BRAM_FIFO36_DIADIU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_3" }, "BRAM_R.BRAM_IMUX42_3->BRAM_RAMB18_DIADI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_3" }, "BRAM_R.BRAM_IMUX42_4->BRAM_FIFO36_TSTWROS8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_4" }, "BRAM_R.BRAM_IMUX43_0->BRAM_FIFO36_TSTWROS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_0" }, "BRAM_R.BRAM_IMUX43_1->BRAM_FIFO18_DIADI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_1" }, "BRAM_R.BRAM_IMUX43_1->BRAM_FIFO36_DIADIL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_1" }, "BRAM_R.BRAM_IMUX43_2->BRAM_FIFO36_DIPBDIPU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_2" }, "BRAM_R.BRAM_IMUX43_2->BRAM_RAMB18_DIPBDIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPBDIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_2" }, "BRAM_R.BRAM_IMUX43_3->BRAM_FIFO36_DIADIU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_3" }, "BRAM_R.BRAM_IMUX43_3->BRAM_RAMB18_DIADI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_3" }, "BRAM_R.BRAM_IMUX43_4->BRAM_FIFO36_TSTWROS9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_4" }, "BRAM_R.BRAM_IMUX44_0->BRAM_FIFO36_TSTWROS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_0" }, "BRAM_R.BRAM_IMUX44_1->BRAM_FIFO18_DIADI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_1" }, "BRAM_R.BRAM_IMUX44_1->BRAM_FIFO36_DIADIL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_1" }, "BRAM_R.BRAM_IMUX44_3->BRAM_FIFO36_DIADIU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_3" }, "BRAM_R.BRAM_IMUX44_3->BRAM_RAMB18_DIADI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_3" }, "BRAM_R.BRAM_IMUX44_4->BRAM_FIFO36_TSTWROS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_4" }, "BRAM_R.BRAM_IMUX45_0->BRAM_FIFO36_TSTWROS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_0" }, "BRAM_R.BRAM_IMUX45_1->BRAM_FIFO18_DIADI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_1" }, "BRAM_R.BRAM_IMUX45_1->BRAM_FIFO36_DIADIL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_1" }, "BRAM_R.BRAM_IMUX45_2->BRAM_FIFO36_WEBWEU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_2" }, "BRAM_R.BRAM_IMUX45_2->BRAM_RAMB18_WEBWE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_2" }, "BRAM_R.BRAM_IMUX45_3->BRAM_FIFO36_DIADIU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_3" }, "BRAM_R.BRAM_IMUX45_3->BRAM_RAMB18_DIADI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_3" }, "BRAM_R.BRAM_IMUX45_4->BRAM_FIFO36_TSTWROS11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_4" }, "BRAM_R.BRAM_IMUX46_0->BRAM_FIFO36_TSTWROS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_0" }, "BRAM_R.BRAM_IMUX46_1->BRAM_FIFO18_DIADI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_1" }, "BRAM_R.BRAM_IMUX46_1->BRAM_FIFO36_DIADIL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_1" }, "BRAM_R.BRAM_IMUX46_2->BRAM_FIFO36_WEBWEU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_2" }, "BRAM_R.BRAM_IMUX46_2->BRAM_RAMB18_WEBWE7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_2" }, "BRAM_R.BRAM_IMUX46_4->BRAM_FIFO36_TSTWROS12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_4" }, "BRAM_R.BRAM_IMUX47_0->BRAM_FIFO36_TSTWROS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX47_0" }, "BRAM_R.BRAM_IMUX4_0->BRAM_FIFO36_TSTOFF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTOFF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_0" }, "BRAM_R.BRAM_IMUX4_1->BRAM_FIFO18_DIBDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_1" }, "BRAM_R.BRAM_IMUX4_1->BRAM_FIFO36_DIBDIL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_1" }, "BRAM_R.BRAM_IMUX4_2->BRAM_FIFO18_DIPBDIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPBDIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_2" }, "BRAM_R.BRAM_IMUX4_2->BRAM_FIFO36_DIPBDIPL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_2" }, "BRAM_R.BRAM_IMUX4_3->BRAM_FIFO36_DIBDIU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_3" }, "BRAM_R.BRAM_IMUX4_3->BRAM_RAMB18_DIBDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_3" }, "BRAM_R.BRAM_IMUX4_4->BRAM_FIFO36_TSTIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_4" }, "BRAM_R.BRAM_IMUX5_0->BRAM_FIFO36_TSTFLAGIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTFLAGIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_0" }, "BRAM_R.BRAM_IMUX5_1->BRAM_FIFO18_DIBDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_1" }, "BRAM_R.BRAM_IMUX5_1->BRAM_FIFO36_DIBDIL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_1" }, "BRAM_R.BRAM_IMUX5_2->BRAM_FIFO18_WEBWE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_2" }, "BRAM_R.BRAM_IMUX5_2->BRAM_FIFO36_WEBWEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_2" }, "BRAM_R.BRAM_IMUX5_3->BRAM_FIFO36_DIBDIU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_3" }, "BRAM_R.BRAM_IMUX5_3->BRAM_RAMB18_DIBDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_3" }, "BRAM_R.BRAM_IMUX5_4->BRAM_FIFO36_TSTIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_4" }, "BRAM_R.BRAM_IMUX6_1->BRAM_FIFO18_DIBDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_1" }, "BRAM_R.BRAM_IMUX6_1->BRAM_FIFO36_DIBDIL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_1" }, "BRAM_R.BRAM_IMUX6_2->BRAM_FIFO18_WEBWE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_2" }, "BRAM_R.BRAM_IMUX6_2->BRAM_FIFO36_WEBWEL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_2" }, "BRAM_R.BRAM_IMUX6_3->BRAM_FIFO36_DIBDIU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_3" }, "BRAM_R.BRAM_IMUX6_3->BRAM_RAMB18_DIBDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_3" }, "BRAM_R.BRAM_IMUX7_1->BRAM_FIFO18_DIBDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX7_1" }, "BRAM_R.BRAM_IMUX7_1->BRAM_FIFO36_DIBDIL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX7_1" }, "BRAM_R.BRAM_IMUX8_0->BRAM_FIFO36_TSTIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_0" }, "BRAM_R.BRAM_IMUX8_1->BRAM_FIFO36_DIADIU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_1" }, "BRAM_R.BRAM_IMUX8_1->BRAM_RAMB18_DIADI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_1" }, "BRAM_R.BRAM_IMUX8_2->BRAM_FIFO36_WEAU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_2" }, "BRAM_R.BRAM_IMUX8_2->BRAM_RAMB18_WEA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_2" }, "BRAM_R.BRAM_IMUX8_3->BRAM_R_IMUX_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_3" }, "BRAM_R.BRAM_IMUX8_4->BRAM_FIFO36_DIADIU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_4" }, "BRAM_R.BRAM_IMUX8_4->BRAM_RAMB18_DIADI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_4" }, "BRAM_R.BRAM_IMUX9_1->BRAM_R_IMUX_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_1" }, "BRAM_R.BRAM_IMUX9_2->BRAM_FIFO36_WEAU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_2" }, "BRAM_R.BRAM_IMUX9_2->BRAM_RAMB18_WEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_2" }, "BRAM_R.BRAM_IMUX9_3->BRAM_R_IMUX_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_3" }, "BRAM_R.BRAM_IMUX9_4->BRAM_FIFO36_DIADIU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_4" }, "BRAM_R.BRAM_IMUX9_4->BRAM_RAMB18_DIADI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_4" }, "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_FIFO18_ADDRATIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_FIFO36_ADDRARDADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_RAMB18_ADDRATIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_UTURN_ADDRARDADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_FIFO18_ADDRBTIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_FIFO36_ADDRBWRADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_RAMB18_ADDRBTIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.111", + "0.134" + ], + "in_cap": "0.000", + "res": "737.319" + }, "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_UTURN_ADDRBWRADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15" }, "BRAM_R.BRAM_RAMB18_DOADO0->BRAM_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO0" }, "BRAM_R.BRAM_RAMB18_DOADO1->BRAM_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO1" }, "BRAM_R.BRAM_RAMB18_DOADO10->BRAM_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO10" }, "BRAM_R.BRAM_RAMB18_DOADO11->BRAM_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO11" }, "BRAM_R.BRAM_RAMB18_DOADO12->BRAM_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO12" }, "BRAM_R.BRAM_RAMB18_DOADO13->BRAM_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO13" }, "BRAM_R.BRAM_RAMB18_DOADO14->BRAM_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO14" }, "BRAM_R.BRAM_RAMB18_DOADO15->BRAM_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO15" }, "BRAM_R.BRAM_RAMB18_DOADO2->BRAM_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO2" }, "BRAM_R.BRAM_RAMB18_DOADO3->BRAM_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO3" }, "BRAM_R.BRAM_RAMB18_DOADO4->BRAM_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO4" }, "BRAM_R.BRAM_RAMB18_DOADO5->BRAM_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO5" }, "BRAM_R.BRAM_RAMB18_DOADO6->BRAM_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO6" }, "BRAM_R.BRAM_RAMB18_DOADO7->BRAM_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO7" }, "BRAM_R.BRAM_RAMB18_DOADO8->BRAM_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO8" }, "BRAM_R.BRAM_RAMB18_DOADO9->BRAM_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO9" }, "BRAM_R.BRAM_RAMB18_DOBDO0->BRAM_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO0" }, "BRAM_R.BRAM_RAMB18_DOBDO1->BRAM_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO1" }, "BRAM_R.BRAM_RAMB18_DOBDO10->BRAM_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO10" }, "BRAM_R.BRAM_RAMB18_DOBDO11->BRAM_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO11" }, "BRAM_R.BRAM_RAMB18_DOBDO12->BRAM_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO12" }, "BRAM_R.BRAM_RAMB18_DOBDO13->BRAM_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO13" }, "BRAM_R.BRAM_RAMB18_DOBDO14->BRAM_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO14" }, "BRAM_R.BRAM_RAMB18_DOBDO15->BRAM_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO15" }, "BRAM_R.BRAM_RAMB18_DOBDO2->BRAM_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO2" }, "BRAM_R.BRAM_RAMB18_DOBDO3->BRAM_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO3" }, "BRAM_R.BRAM_RAMB18_DOBDO4->BRAM_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO4" }, "BRAM_R.BRAM_RAMB18_DOBDO5->BRAM_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO5" }, "BRAM_R.BRAM_RAMB18_DOBDO6->BRAM_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO6" }, "BRAM_R.BRAM_RAMB18_DOBDO7->BRAM_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO7" }, "BRAM_R.BRAM_RAMB18_DOBDO8->BRAM_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO8" }, "BRAM_R.BRAM_RAMB18_DOBDO9->BRAM_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO9" }, "BRAM_R.BRAM_RAMB18_DOPADOP0->BRAM_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPADOP0" }, "BRAM_R.BRAM_RAMB18_DOPADOP1->BRAM_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPADOP1" }, "BRAM_R.BRAM_RAMB18_DOPBDOP0->BRAM_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPBDOP0" }, "BRAM_R.BRAM_RAMB18_DOPBDOP1->BRAM_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPBDOP1" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL0->BRAM_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL0" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL1->BRAM_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL1" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL10->BRAM_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL10" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL11->BRAM_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL11" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL12->BRAM_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL12" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL13->BRAM_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL13" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL14->BRAM_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL14" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL2->BRAM_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL2" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL3->BRAM_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL3" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL4->BRAM_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL4" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL5->BRAM_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL5" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL6->BRAM_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL6" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL7->BRAM_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL7" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL8->BRAM_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL8" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL9->BRAM_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL9" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU0" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU1" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU10" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU11" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU12" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU13" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU14" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU2" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU3" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU4" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU5" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU6" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU7" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU8" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU9" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL0" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL1" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL10" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL11" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL12" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL13" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL14" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL2" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL3" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL4" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL5" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL6" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL7" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL8" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL9" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU0" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU1" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU10" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU11" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU12" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU13" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU14" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU2" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU3" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU4" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU5" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU6" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU7" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU8" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU9" } }, @@ -6824,164 +19718,1586 @@ "name": "X0Y0", "prefix": "RAMB18", "site_pins": { - "ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0", - "ADDRARDADDR1": "BRAM_FIFO18_ADDRARDADDR1", - "ADDRARDADDR10": "BRAM_FIFO18_ADDRARDADDR10", - "ADDRARDADDR11": "BRAM_FIFO18_ADDRARDADDR11", - "ADDRARDADDR12": "BRAM_FIFO18_ADDRARDADDR12", - "ADDRARDADDR13": "BRAM_FIFO18_ADDRARDADDR13", - "ADDRARDADDR2": "BRAM_FIFO18_ADDRARDADDR2", - "ADDRARDADDR3": "BRAM_FIFO18_ADDRARDADDR3", - "ADDRARDADDR4": "BRAM_FIFO18_ADDRARDADDR4", - "ADDRARDADDR5": "BRAM_FIFO18_ADDRARDADDR5", - "ADDRARDADDR6": "BRAM_FIFO18_ADDRARDADDR6", - "ADDRARDADDR7": "BRAM_FIFO18_ADDRARDADDR7", - "ADDRARDADDR8": "BRAM_FIFO18_ADDRARDADDR8", - "ADDRARDADDR9": "BRAM_FIFO18_ADDRARDADDR9", - "ADDRATIEHIGH0": "BRAM_FIFO18_ADDRATIEHIGH0", - "ADDRATIEHIGH1": "BRAM_FIFO18_ADDRATIEHIGH1", - "ADDRBTIEHIGH0": "BRAM_FIFO18_ADDRBTIEHIGH0", - "ADDRBTIEHIGH1": "BRAM_FIFO18_ADDRBTIEHIGH1", - "ADDRBWRADDR0": "BRAM_FIFO18_ADDRBWRADDR0", - "ADDRBWRADDR1": "BRAM_FIFO18_ADDRBWRADDR1", - "ADDRBWRADDR10": "BRAM_FIFO18_ADDRBWRADDR10", - "ADDRBWRADDR11": "BRAM_FIFO18_ADDRBWRADDR11", - "ADDRBWRADDR12": "BRAM_FIFO18_ADDRBWRADDR12", - "ADDRBWRADDR13": "BRAM_FIFO18_ADDRBWRADDR13", - "ADDRBWRADDR2": "BRAM_FIFO18_ADDRBWRADDR2", - "ADDRBWRADDR3": "BRAM_FIFO18_ADDRBWRADDR3", - "ADDRBWRADDR4": "BRAM_FIFO18_ADDRBWRADDR4", - "ADDRBWRADDR5": "BRAM_FIFO18_ADDRBWRADDR5", - "ADDRBWRADDR6": "BRAM_FIFO18_ADDRBWRADDR6", - "ADDRBWRADDR7": "BRAM_FIFO18_ADDRBWRADDR7", - "ADDRBWRADDR8": "BRAM_FIFO18_ADDRBWRADDR8", - "ADDRBWRADDR9": "BRAM_FIFO18_ADDRBWRADDR9", - "ALMOSTEMPTY": "BRAM_FIFO18_ALMOSTEMPTY", - "ALMOSTFULL": "BRAM_FIFO18_ALMOSTFULL", - "DIADI0": "BRAM_FIFO18_DIADI0", - "DIADI1": "BRAM_FIFO18_DIADI1", - "DIADI10": "BRAM_FIFO18_DIADI10", - "DIADI11": "BRAM_FIFO18_DIADI11", - "DIADI12": "BRAM_FIFO18_DIADI12", - "DIADI13": "BRAM_FIFO18_DIADI13", - "DIADI14": "BRAM_FIFO18_DIADI14", - "DIADI15": "BRAM_FIFO18_DIADI15", - "DIADI2": "BRAM_FIFO18_DIADI2", - "DIADI3": "BRAM_FIFO18_DIADI3", - "DIADI4": "BRAM_FIFO18_DIADI4", - "DIADI5": "BRAM_FIFO18_DIADI5", - "DIADI6": "BRAM_FIFO18_DIADI6", - "DIADI7": "BRAM_FIFO18_DIADI7", - "DIADI8": "BRAM_FIFO18_DIADI8", - "DIADI9": "BRAM_FIFO18_DIADI9", - "DIBDI0": "BRAM_FIFO18_DIBDI0", - "DIBDI1": "BRAM_FIFO18_DIBDI1", - "DIBDI10": "BRAM_FIFO18_DIBDI10", - "DIBDI11": "BRAM_FIFO18_DIBDI11", - "DIBDI12": "BRAM_FIFO18_DIBDI12", - "DIBDI13": "BRAM_FIFO18_DIBDI13", - "DIBDI14": "BRAM_FIFO18_DIBDI14", - "DIBDI15": "BRAM_FIFO18_DIBDI15", - "DIBDI2": "BRAM_FIFO18_DIBDI2", - "DIBDI3": "BRAM_FIFO18_DIBDI3", - "DIBDI4": "BRAM_FIFO18_DIBDI4", - "DIBDI5": "BRAM_FIFO18_DIBDI5", - "DIBDI6": "BRAM_FIFO18_DIBDI6", - "DIBDI7": "BRAM_FIFO18_DIBDI7", - "DIBDI8": "BRAM_FIFO18_DIBDI8", - "DIBDI9": "BRAM_FIFO18_DIBDI9", - "DIPADIP0": "BRAM_FIFO18_DIPADIP0", - "DIPADIP1": "BRAM_FIFO18_DIPADIP1", - "DIPBDIP0": "BRAM_FIFO18_DIPBDIP0", - "DIPBDIP1": "BRAM_FIFO18_DIPBDIP1", - "DO0": "BRAM_FIFO18_DOADO0", - "DO1": "BRAM_FIFO18_DOADO1", - "DO10": "BRAM_FIFO18_DOADO10", - "DO11": "BRAM_FIFO18_DOADO11", - "DO12": "BRAM_FIFO18_DOADO12", - "DO13": "BRAM_FIFO18_DOADO13", - "DO14": "BRAM_FIFO18_DOADO14", - "DO15": "BRAM_FIFO18_DOADO15", - "DO16": "BRAM_FIFO18_DOBDO0", - "DO17": "BRAM_FIFO18_DOBDO1", - "DO18": "BRAM_FIFO18_DOBDO2", - "DO19": "BRAM_FIFO18_DOBDO3", - "DO2": "BRAM_FIFO18_DOADO2", - "DO20": "BRAM_FIFO18_DOBDO4", - "DO21": "BRAM_FIFO18_DOBDO5", - "DO22": "BRAM_FIFO18_DOBDO6", - "DO23": "BRAM_FIFO18_DOBDO7", - "DO24": "BRAM_FIFO18_DOBDO8", - "DO25": "BRAM_FIFO18_DOBDO9", - "DO26": "BRAM_FIFO18_DOBDO10", - "DO27": "BRAM_FIFO18_DOBDO11", - "DO28": "BRAM_FIFO18_DOBDO12", - "DO29": "BRAM_FIFO18_DOBDO13", - "DO3": "BRAM_FIFO18_DOADO3", - "DO30": "BRAM_FIFO18_DOBDO14", - "DO31": "BRAM_FIFO18_DOBDO15", - "DO4": "BRAM_FIFO18_DOADO4", - "DO5": "BRAM_FIFO18_DOADO5", - "DO6": "BRAM_FIFO18_DOADO6", - "DO7": "BRAM_FIFO18_DOADO7", - "DO8": "BRAM_FIFO18_DOADO8", - "DO9": "BRAM_FIFO18_DOADO9", - "DOP0": "BRAM_FIFO18_DOPADOP0", - "DOP1": "BRAM_FIFO18_DOPADOP1", - "DOP2": "BRAM_FIFO18_DOPBDOP0", - "DOP3": "BRAM_FIFO18_DOPBDOP1", - "EMPTY": "BRAM_FIFO18_EMPTY", - "FULL": "BRAM_FIFO18_FULL", - "RDCLK": "BRAM_FIFO18_CLKARDCLK", - "RDCOUNT0": "BRAM_FIFO18_RDCOUNT0", - "RDCOUNT1": "BRAM_FIFO18_RDCOUNT1", - "RDCOUNT10": "BRAM_FIFO18_RDCOUNT10", - "RDCOUNT11": "BRAM_FIFO18_RDCOUNT11", - "RDCOUNT2": "BRAM_FIFO18_RDCOUNT2", - "RDCOUNT3": "BRAM_FIFO18_RDCOUNT3", - "RDCOUNT4": "BRAM_FIFO18_RDCOUNT4", - "RDCOUNT5": "BRAM_FIFO18_RDCOUNT5", - "RDCOUNT6": "BRAM_FIFO18_RDCOUNT6", - "RDCOUNT7": "BRAM_FIFO18_RDCOUNT7", - "RDCOUNT8": "BRAM_FIFO18_RDCOUNT8", - "RDCOUNT9": "BRAM_FIFO18_RDCOUNT9", - "RDEN": "BRAM_FIFO18_ENARDEN", - "RDERR": "BRAM_FIFO18_RDERR", - "RDRCLK": "BRAM_FIFO18_REGCLKARDRCLK", - "REGCE": "BRAM_FIFO18_REGCEAREGCE", - "REGCEB": "BRAM_FIFO18_REGCEB", - "REGCLKB": "BRAM_FIFO18_REGCLKB", - "RST": "BRAM_FIFO18_RSTRAMARSTRAM", - "RSTRAMB": "BRAM_FIFO18_RSTRAMB", - "RSTREG": "BRAM_FIFO18_RSTREGARSTREG", - "RSTREGB": "BRAM_FIFO18_RSTREGB", - "WEA0": "BRAM_FIFO18_WEA0", - "WEA1": "BRAM_FIFO18_WEA1", - "WEA2": "BRAM_FIFO18_WEA2", - "WEA3": "BRAM_FIFO18_WEA3", - "WEBWE0": "BRAM_FIFO18_WEBWE0", - "WEBWE1": "BRAM_FIFO18_WEBWE1", - "WEBWE2": "BRAM_FIFO18_WEBWE2", - "WEBWE3": "BRAM_FIFO18_WEBWE3", - "WEBWE4": "BRAM_FIFO18_WEBWE4", - "WEBWE5": "BRAM_FIFO18_WEBWE5", - "WEBWE6": "BRAM_FIFO18_WEBWE6", - "WEBWE7": "BRAM_FIFO18_WEBWE7", - "WRCLK": "BRAM_FIFO18_CLKBWRCLK", - "WRCOUNT0": "BRAM_FIFO18_WRCOUNT0", - "WRCOUNT1": "BRAM_FIFO18_WRCOUNT1", - "WRCOUNT10": "BRAM_FIFO18_WRCOUNT10", - "WRCOUNT11": "BRAM_FIFO18_WRCOUNT11", - "WRCOUNT2": "BRAM_FIFO18_WRCOUNT2", - "WRCOUNT3": "BRAM_FIFO18_WRCOUNT3", - "WRCOUNT4": "BRAM_FIFO18_WRCOUNT4", - "WRCOUNT5": "BRAM_FIFO18_WRCOUNT5", - "WRCOUNT6": "BRAM_FIFO18_WRCOUNT6", - "WRCOUNT7": "BRAM_FIFO18_WRCOUNT7", - "WRCOUNT8": "BRAM_FIFO18_WRCOUNT8", - "WRCOUNT9": "BRAM_FIFO18_WRCOUNT9", - "WREN": "BRAM_FIFO18_ENBWREN", - "WRERR": "BRAM_FIFO18_WRERR" + "ADDRARDADDR0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR0" + }, + "ADDRARDADDR1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR1" + }, + "ADDRARDADDR10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR10" + }, + "ADDRARDADDR11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR11" + }, + "ADDRARDADDR12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR12" + }, + "ADDRARDADDR13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR13" + }, + "ADDRARDADDR2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR2" + }, + "ADDRARDADDR3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR3" + }, + "ADDRARDADDR4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR4" + }, + "ADDRARDADDR5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR5" + }, + "ADDRARDADDR6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR6" + }, + "ADDRARDADDR7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR7" + }, + "ADDRARDADDR8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR8" + }, + "ADDRARDADDR9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR9" + }, + "ADDRATIEHIGH0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], 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+ "res": "855.9375", + "wire": "BRAM_FIFO18_WRERR" + } }, "type": "FIFO18E1", "x_coord": 0, @@ -6991,164 +21307,1586 @@ "name": "X0Y1", "prefix": "RAMB18", "site_pins": { - "ADDRARDADDR0": "BRAM_RAMB18_ADDRARDADDR0", - "ADDRARDADDR1": "BRAM_RAMB18_ADDRARDADDR1", - "ADDRARDADDR10": "BRAM_RAMB18_ADDRARDADDR10", - "ADDRARDADDR11": "BRAM_RAMB18_ADDRARDADDR11", - "ADDRARDADDR12": "BRAM_RAMB18_ADDRARDADDR12", - "ADDRARDADDR13": "BRAM_RAMB18_ADDRARDADDR13", - "ADDRARDADDR2": "BRAM_RAMB18_ADDRARDADDR2", - "ADDRARDADDR3": "BRAM_RAMB18_ADDRARDADDR3", - "ADDRARDADDR4": "BRAM_RAMB18_ADDRARDADDR4", - "ADDRARDADDR5": "BRAM_RAMB18_ADDRARDADDR5", - "ADDRARDADDR6": "BRAM_RAMB18_ADDRARDADDR6", - "ADDRARDADDR7": "BRAM_RAMB18_ADDRARDADDR7", - "ADDRARDADDR8": "BRAM_RAMB18_ADDRARDADDR8", - "ADDRARDADDR9": "BRAM_RAMB18_ADDRARDADDR9", - "ADDRATIEHIGH0": "BRAM_RAMB18_ADDRATIEHIGH0", - "ADDRATIEHIGH1": "BRAM_RAMB18_ADDRATIEHIGH1", - "ADDRBTIEHIGH0": "BRAM_RAMB18_ADDRBTIEHIGH0", - "ADDRBTIEHIGH1": "BRAM_RAMB18_ADDRBTIEHIGH1", - "ADDRBWRADDR0": "BRAM_RAMB18_ADDRBWRADDR0", - "ADDRBWRADDR1": "BRAM_RAMB18_ADDRBWRADDR1", - "ADDRBWRADDR10": "BRAM_RAMB18_ADDRBWRADDR10", - "ADDRBWRADDR11": "BRAM_RAMB18_ADDRBWRADDR11", - "ADDRBWRADDR12": "BRAM_RAMB18_ADDRBWRADDR12", - "ADDRBWRADDR13": "BRAM_RAMB18_ADDRBWRADDR13", - "ADDRBWRADDR2": "BRAM_RAMB18_ADDRBWRADDR2", - "ADDRBWRADDR3": "BRAM_RAMB18_ADDRBWRADDR3", - "ADDRBWRADDR4": "BRAM_RAMB18_ADDRBWRADDR4", - "ADDRBWRADDR5": "BRAM_RAMB18_ADDRBWRADDR5", - "ADDRBWRADDR6": "BRAM_RAMB18_ADDRBWRADDR6", - "ADDRBWRADDR7": "BRAM_RAMB18_ADDRBWRADDR7", - "ADDRBWRADDR8": "BRAM_RAMB18_ADDRBWRADDR8", - "ADDRBWRADDR9": "BRAM_RAMB18_ADDRBWRADDR9", - "ALMOSTEMPTY": "BRAM_RAMB18_ALMOSTEMPTY", - "ALMOSTFULL": "BRAM_RAMB18_ALMOSTFULL", - "CLKARDCLK": "BRAM_RAMB18_CLKARDCLK", - "CLKBWRCLK": "BRAM_RAMB18_CLKBWRCLK", - "DIADI0": "BRAM_RAMB18_DIADI0", - "DIADI1": "BRAM_RAMB18_DIADI1", - "DIADI10": "BRAM_RAMB18_DIADI10", - "DIADI11": "BRAM_RAMB18_DIADI11", - "DIADI12": "BRAM_RAMB18_DIADI12", - "DIADI13": "BRAM_RAMB18_DIADI13", - "DIADI14": "BRAM_RAMB18_DIADI14", - "DIADI15": "BRAM_RAMB18_DIADI15", - "DIADI2": "BRAM_RAMB18_DIADI2", - "DIADI3": "BRAM_RAMB18_DIADI3", - "DIADI4": "BRAM_RAMB18_DIADI4", - "DIADI5": "BRAM_RAMB18_DIADI5", - "DIADI6": "BRAM_RAMB18_DIADI6", - "DIADI7": "BRAM_RAMB18_DIADI7", - "DIADI8": "BRAM_RAMB18_DIADI8", - "DIADI9": "BRAM_RAMB18_DIADI9", - "DIBDI0": "BRAM_RAMB18_DIBDI0", - "DIBDI1": "BRAM_RAMB18_DIBDI1", - "DIBDI10": "BRAM_RAMB18_DIBDI10", - "DIBDI11": "BRAM_RAMB18_DIBDI11", - "DIBDI12": "BRAM_RAMB18_DIBDI12", - "DIBDI13": "BRAM_RAMB18_DIBDI13", - "DIBDI14": "BRAM_RAMB18_DIBDI14", - "DIBDI15": "BRAM_RAMB18_DIBDI15", - "DIBDI2": "BRAM_RAMB18_DIBDI2", - "DIBDI3": "BRAM_RAMB18_DIBDI3", - "DIBDI4": "BRAM_RAMB18_DIBDI4", - "DIBDI5": "BRAM_RAMB18_DIBDI5", - "DIBDI6": "BRAM_RAMB18_DIBDI6", - "DIBDI7": "BRAM_RAMB18_DIBDI7", - "DIBDI8": "BRAM_RAMB18_DIBDI8", - "DIBDI9": "BRAM_RAMB18_DIBDI9", - "DIPADIP0": "BRAM_RAMB18_DIPADIP0", - "DIPADIP1": "BRAM_RAMB18_DIPADIP1", - "DIPBDIP0": "BRAM_RAMB18_DIPBDIP0", - "DIPBDIP1": "BRAM_RAMB18_DIPBDIP1", - "DOADO0": "BRAM_RAMB18_DOADO0", - "DOADO1": "BRAM_RAMB18_DOADO1", - "DOADO10": "BRAM_RAMB18_DOADO10", - "DOADO11": "BRAM_RAMB18_DOADO11", - "DOADO12": "BRAM_RAMB18_DOADO12", - "DOADO13": "BRAM_RAMB18_DOADO13", - "DOADO14": "BRAM_RAMB18_DOADO14", - "DOADO15": "BRAM_RAMB18_DOADO15", - "DOADO2": "BRAM_RAMB18_DOADO2", - "DOADO3": "BRAM_RAMB18_DOADO3", - "DOADO4": "BRAM_RAMB18_DOADO4", - "DOADO5": "BRAM_RAMB18_DOADO5", - "DOADO6": "BRAM_RAMB18_DOADO6", - "DOADO7": "BRAM_RAMB18_DOADO7", - "DOADO8": "BRAM_RAMB18_DOADO8", - "DOADO9": "BRAM_RAMB18_DOADO9", - "DOBDO0": "BRAM_RAMB18_DOBDO0", - "DOBDO1": "BRAM_RAMB18_DOBDO1", - "DOBDO10": "BRAM_RAMB18_DOBDO10", - "DOBDO11": "BRAM_RAMB18_DOBDO11", - "DOBDO12": "BRAM_RAMB18_DOBDO12", - "DOBDO13": "BRAM_RAMB18_DOBDO13", - "DOBDO14": "BRAM_RAMB18_DOBDO14", - "DOBDO15": "BRAM_RAMB18_DOBDO15", - "DOBDO2": "BRAM_RAMB18_DOBDO2", - "DOBDO3": "BRAM_RAMB18_DOBDO3", - "DOBDO4": "BRAM_RAMB18_DOBDO4", - "DOBDO5": "BRAM_RAMB18_DOBDO5", - "DOBDO6": "BRAM_RAMB18_DOBDO6", - "DOBDO7": "BRAM_RAMB18_DOBDO7", - "DOBDO8": "BRAM_RAMB18_DOBDO8", - "DOBDO9": "BRAM_RAMB18_DOBDO9", - "DOPADOP0": "BRAM_RAMB18_DOPADOP0", - "DOPADOP1": "BRAM_RAMB18_DOPADOP1", - "DOPBDOP0": "BRAM_RAMB18_DOPBDOP0", - "DOPBDOP1": "BRAM_RAMB18_DOPBDOP1", - "EMPTY": "BRAM_RAMB18_EMPTY", - "ENARDEN": "BRAM_RAMB18_ENARDEN", - "ENBWREN": "BRAM_RAMB18_ENBWREN", - "FULL": "BRAM_RAMB18_FULL", - "RDCOUNT0": "BRAM_RAMB18_RDCOUNT0", - "RDCOUNT1": "BRAM_RAMB18_RDCOUNT1", - "RDCOUNT10": "BRAM_RAMB18_RDCOUNT10", - "RDCOUNT11": "BRAM_RAMB18_RDCOUNT11", - "RDCOUNT2": "BRAM_RAMB18_RDCOUNT2", - "RDCOUNT3": "BRAM_RAMB18_RDCOUNT3", - "RDCOUNT4": "BRAM_RAMB18_RDCOUNT4", - "RDCOUNT5": "BRAM_RAMB18_RDCOUNT5", - "RDCOUNT6": "BRAM_RAMB18_RDCOUNT6", - "RDCOUNT7": "BRAM_RAMB18_RDCOUNT7", - "RDCOUNT8": "BRAM_RAMB18_RDCOUNT8", - "RDCOUNT9": "BRAM_RAMB18_RDCOUNT9", - "RDERR": "BRAM_RAMB18_RDERR", - "REGCEAREGCE": "BRAM_RAMB18_REGCEAREGCE", - "REGCEB": "BRAM_RAMB18_REGCEB", - "REGCLKARDRCLK": "BRAM_RAMB18_REGCLKARDRCLK", - "REGCLKB": "BRAM_RAMB18_REGCLKB", - "RSTRAMARSTRAM": "BRAM_RAMB18_RSTRAMARSTRAM", - "RSTRAMB": "BRAM_RAMB18_RSTRAMB", - "RSTREGARSTREG": "BRAM_RAMB18_RSTREGARSTREG", - "RSTREGB": "BRAM_RAMB18_RSTREGB", - "WEA0": "BRAM_RAMB18_WEA0", - "WEA1": "BRAM_RAMB18_WEA1", - "WEA2": "BRAM_RAMB18_WEA2", - "WEA3": "BRAM_RAMB18_WEA3", - "WEBWE0": "BRAM_RAMB18_WEBWE0", - "WEBWE1": "BRAM_RAMB18_WEBWE1", - "WEBWE2": "BRAM_RAMB18_WEBWE2", - "WEBWE3": "BRAM_RAMB18_WEBWE3", - "WEBWE4": "BRAM_RAMB18_WEBWE4", - "WEBWE5": "BRAM_RAMB18_WEBWE5", - "WEBWE6": "BRAM_RAMB18_WEBWE6", - "WEBWE7": "BRAM_RAMB18_WEBWE7", - "WRCOUNT0": "BRAM_RAMB18_WRCOUNT0", - "WRCOUNT1": "BRAM_RAMB18_WRCOUNT1", - "WRCOUNT10": "BRAM_RAMB18_WRCOUNT10", - "WRCOUNT11": "BRAM_RAMB18_WRCOUNT11", - "WRCOUNT2": "BRAM_RAMB18_WRCOUNT2", - "WRCOUNT3": "BRAM_RAMB18_WRCOUNT3", - "WRCOUNT4": "BRAM_RAMB18_WRCOUNT4", - "WRCOUNT5": "BRAM_RAMB18_WRCOUNT5", - "WRCOUNT6": "BRAM_RAMB18_WRCOUNT6", - "WRCOUNT7": "BRAM_RAMB18_WRCOUNT7", - "WRCOUNT8": "BRAM_RAMB18_WRCOUNT8", - "WRCOUNT9": "BRAM_RAMB18_WRCOUNT9", - "WRERR": "BRAM_RAMB18_WRERR" + "ADDRARDADDR0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_RAMB18_ADDRARDADDR0" + }, + "ADDRARDADDR1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_RAMB18_ADDRARDADDR1" + }, + "ADDRARDADDR10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_RAMB18_ADDRARDADDR10" + }, + "ADDRARDADDR11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_RAMB18_ADDRARDADDR11" + }, + "ADDRARDADDR12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_RAMB18_ADDRARDADDR12" + }, + "ADDRARDADDR13": { + "cap": "0.000", + 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"cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_RAMB18_WEBWE2" + }, + "WEBWE3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_RAMB18_WEBWE3" + }, + "WEBWE4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_RAMB18_WEBWE4" + }, + "WEBWE5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_RAMB18_WEBWE5" + }, + "WEBWE6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_RAMB18_WEBWE6" + }, + "WEBWE7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_RAMB18_WEBWE7" + }, + "WRCOUNT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT0" + }, + "WRCOUNT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT1" + }, + "WRCOUNT10": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT10" + }, + "WRCOUNT11": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT11" + }, + "WRCOUNT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT2" + }, + "WRCOUNT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT3" + }, + "WRCOUNT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT4" + }, + "WRCOUNT5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT5" + }, + "WRCOUNT6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT6" + }, + "WRCOUNT7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT7" + }, + "WRCOUNT8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT8" + }, + "WRCOUNT9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT9" + }, + "WRERR": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRERR" + } }, "type": "RAMB18E1", "x_coord": 0, @@ -7158,362 +22896,3566 @@ "name": "X0Y0", "prefix": "RAMB36", "site_pins": { - "ADDRARDADDRL0": "BRAM_FIFO36_ADDRARDADDRL0", - "ADDRARDADDRL1": "BRAM_FIFO36_ADDRARDADDRL1", - "ADDRARDADDRL10": "BRAM_FIFO36_ADDRARDADDRL10", - "ADDRARDADDRL11": "BRAM_FIFO36_ADDRARDADDRL11", - "ADDRARDADDRL12": "BRAM_FIFO36_ADDRARDADDRL12", - "ADDRARDADDRL13": "BRAM_FIFO36_ADDRARDADDRL13", - "ADDRARDADDRL14": "BRAM_FIFO36_ADDRARDADDRL14", - "ADDRARDADDRL15": "BRAM_FIFO36_ADDRARDADDRL15", - "ADDRARDADDRL2": "BRAM_FIFO36_ADDRARDADDRL2", - "ADDRARDADDRL3": "BRAM_FIFO36_ADDRARDADDRL3", - "ADDRARDADDRL4": "BRAM_FIFO36_ADDRARDADDRL4", - "ADDRARDADDRL5": "BRAM_FIFO36_ADDRARDADDRL5", - "ADDRARDADDRL6": "BRAM_FIFO36_ADDRARDADDRL6", - "ADDRARDADDRL7": "BRAM_FIFO36_ADDRARDADDRL7", - "ADDRARDADDRL8": "BRAM_FIFO36_ADDRARDADDRL8", - "ADDRARDADDRL9": "BRAM_FIFO36_ADDRARDADDRL9", - "ADDRARDADDRU0": "BRAM_FIFO36_ADDRARDADDRU0", - "ADDRARDADDRU1": "BRAM_FIFO36_ADDRARDADDRU1", - "ADDRARDADDRU10": "BRAM_FIFO36_ADDRARDADDRU10", - "ADDRARDADDRU11": "BRAM_FIFO36_ADDRARDADDRU11", - "ADDRARDADDRU12": "BRAM_FIFO36_ADDRARDADDRU12", - "ADDRARDADDRU13": "BRAM_FIFO36_ADDRARDADDRU13", - "ADDRARDADDRU14": "BRAM_FIFO36_ADDRARDADDRU14", - "ADDRARDADDRU2": "BRAM_FIFO36_ADDRARDADDRU2", - "ADDRARDADDRU3": "BRAM_FIFO36_ADDRARDADDRU3", - "ADDRARDADDRU4": "BRAM_FIFO36_ADDRARDADDRU4", - "ADDRARDADDRU5": "BRAM_FIFO36_ADDRARDADDRU5", - "ADDRARDADDRU6": "BRAM_FIFO36_ADDRARDADDRU6", - "ADDRARDADDRU7": "BRAM_FIFO36_ADDRARDADDRU7", - "ADDRARDADDRU8": "BRAM_FIFO36_ADDRARDADDRU8", - "ADDRARDADDRU9": "BRAM_FIFO36_ADDRARDADDRU9", - "ADDRBWRADDRL0": "BRAM_FIFO36_ADDRBWRADDRL0", - "ADDRBWRADDRL1": "BRAM_FIFO36_ADDRBWRADDRL1", - "ADDRBWRADDRL10": "BRAM_FIFO36_ADDRBWRADDRL10", - "ADDRBWRADDRL11": "BRAM_FIFO36_ADDRBWRADDRL11", - "ADDRBWRADDRL12": "BRAM_FIFO36_ADDRBWRADDRL12", - "ADDRBWRADDRL13": "BRAM_FIFO36_ADDRBWRADDRL13", - "ADDRBWRADDRL14": "BRAM_FIFO36_ADDRBWRADDRL14", - "ADDRBWRADDRL15": "BRAM_FIFO36_ADDRBWRADDRL15", - "ADDRBWRADDRL2": "BRAM_FIFO36_ADDRBWRADDRL2", - "ADDRBWRADDRL3": "BRAM_FIFO36_ADDRBWRADDRL3", - "ADDRBWRADDRL4": "BRAM_FIFO36_ADDRBWRADDRL4", - "ADDRBWRADDRL5": "BRAM_FIFO36_ADDRBWRADDRL5", - "ADDRBWRADDRL6": "BRAM_FIFO36_ADDRBWRADDRL6", - "ADDRBWRADDRL7": "BRAM_FIFO36_ADDRBWRADDRL7", - "ADDRBWRADDRL8": "BRAM_FIFO36_ADDRBWRADDRL8", - "ADDRBWRADDRL9": "BRAM_FIFO36_ADDRBWRADDRL9", - "ADDRBWRADDRU0": "BRAM_FIFO36_ADDRBWRADDRU0", - "ADDRBWRADDRU1": "BRAM_FIFO36_ADDRBWRADDRU1", - "ADDRBWRADDRU10": "BRAM_FIFO36_ADDRBWRADDRU10", - "ADDRBWRADDRU11": "BRAM_FIFO36_ADDRBWRADDRU11", - "ADDRBWRADDRU12": "BRAM_FIFO36_ADDRBWRADDRU12", - "ADDRBWRADDRU13": "BRAM_FIFO36_ADDRBWRADDRU13", - "ADDRBWRADDRU14": "BRAM_FIFO36_ADDRBWRADDRU14", - "ADDRBWRADDRU2": "BRAM_FIFO36_ADDRBWRADDRU2", - "ADDRBWRADDRU3": "BRAM_FIFO36_ADDRBWRADDRU3", - "ADDRBWRADDRU4": "BRAM_FIFO36_ADDRBWRADDRU4", - "ADDRBWRADDRU5": "BRAM_FIFO36_ADDRBWRADDRU5", - "ADDRBWRADDRU6": "BRAM_FIFO36_ADDRBWRADDRU6", - "ADDRBWRADDRU7": "BRAM_FIFO36_ADDRBWRADDRU7", - "ADDRBWRADDRU8": "BRAM_FIFO36_ADDRBWRADDRU8", - "ADDRBWRADDRU9": "BRAM_FIFO36_ADDRBWRADDRU9", - "ALMOSTEMPTY": "BRAM_FIFO36_ALMOSTEMPTY", - "ALMOSTFULL": "BRAM_FIFO36_ALMOSTFULL", - "CASCADEINA": "BRAM_FIFO36_CASCADEINB", - "CASCADEINB": "BRAM_FIFO36_CASCADEINA", - "CASCADEOUTA": "BRAM_FIFO36_CASCADEOUTB", - "CASCADEOUTB": "BRAM_FIFO36_CASCADEOUTA", - "CLKARDCLKL": "BRAM_FIFO36_CLKARDCLKL", - "CLKARDCLKU": "BRAM_FIFO36_CLKARDCLKU", - "CLKBWRCLKL": "BRAM_FIFO36_CLKBWRCLKL", - "CLKBWRCLKU": "BRAM_FIFO36_CLKBWRCLKU", - "DBITERR": "BRAM_FIFO36_DBITERR", - "DIADI0": "BRAM_FIFO36_DIADIL0", - "DIADI1": "BRAM_FIFO36_DIADIU0", - "DIADI10": "BRAM_FIFO36_DIADIL5", - "DIADI11": "BRAM_FIFO36_DIADIU5", - "DIADI12": "BRAM_FIFO36_DIADIL6", - "DIADI13": "BRAM_FIFO36_DIADIU6", - "DIADI14": "BRAM_FIFO36_DIADIL7", - "DIADI15": "BRAM_FIFO36_DIADIU7", - "DIADI16": "BRAM_FIFO36_DIADIL8", - "DIADI17": "BRAM_FIFO36_DIADIU8", - "DIADI18": "BRAM_FIFO36_DIADIL9", - "DIADI19": "BRAM_FIFO36_DIADIU9", - "DIADI2": "BRAM_FIFO36_DIADIL1", - "DIADI20": "BRAM_FIFO36_DIADIL10", - "DIADI21": "BRAM_FIFO36_DIADIU10", - "DIADI22": "BRAM_FIFO36_DIADIL11", - "DIADI23": "BRAM_FIFO36_DIADIU11", - "DIADI24": "BRAM_FIFO36_DIADIL12", - "DIADI25": "BRAM_FIFO36_DIADIU12", - "DIADI26": "BRAM_FIFO36_DIADIL13", - "DIADI27": "BRAM_FIFO36_DIADIU13", - "DIADI28": "BRAM_FIFO36_DIADIL14", - "DIADI29": "BRAM_FIFO36_DIADIU14", - "DIADI3": "BRAM_FIFO36_DIADIU1", - "DIADI30": "BRAM_FIFO36_DIADIL15", - "DIADI31": "BRAM_FIFO36_DIADIU15", - "DIADI4": "BRAM_FIFO36_DIADIL2", - "DIADI5": "BRAM_FIFO36_DIADIU2", - "DIADI6": "BRAM_FIFO36_DIADIL3", - "DIADI7": "BRAM_FIFO36_DIADIU3", - "DIADI8": "BRAM_FIFO36_DIADIL4", - "DIADI9": "BRAM_FIFO36_DIADIU4", - "DIBDI0": "BRAM_FIFO36_DIBDIL0", - "DIBDI1": "BRAM_FIFO36_DIBDIU0", - "DIBDI10": "BRAM_FIFO36_DIBDIL5", - "DIBDI11": "BRAM_FIFO36_DIBDIU5", - "DIBDI12": "BRAM_FIFO36_DIBDIL6", - "DIBDI13": "BRAM_FIFO36_DIBDIU6", - "DIBDI14": "BRAM_FIFO36_DIBDIL7", - "DIBDI15": "BRAM_FIFO36_DIBDIU7", - "DIBDI16": "BRAM_FIFO36_DIBDIL8", - "DIBDI17": "BRAM_FIFO36_DIBDIU8", - "DIBDI18": "BRAM_FIFO36_DIBDIL9", - "DIBDI19": "BRAM_FIFO36_DIBDIU9", - "DIBDI2": "BRAM_FIFO36_DIBDIL1", - "DIBDI20": "BRAM_FIFO36_DIBDIL10", - "DIBDI21": "BRAM_FIFO36_DIBDIU10", - "DIBDI22": "BRAM_FIFO36_DIBDIL11", - "DIBDI23": "BRAM_FIFO36_DIBDIU11", - "DIBDI24": "BRAM_FIFO36_DIBDIL12", - "DIBDI25": "BRAM_FIFO36_DIBDIU12", - "DIBDI26": "BRAM_FIFO36_DIBDIL13", - "DIBDI27": "BRAM_FIFO36_DIBDIU13", - "DIBDI28": "BRAM_FIFO36_DIBDIL14", - "DIBDI29": "BRAM_FIFO36_DIBDIU14", - "DIBDI3": "BRAM_FIFO36_DIBDIU1", - "DIBDI30": "BRAM_FIFO36_DIBDIL15", - "DIBDI31": "BRAM_FIFO36_DIBDIU15", - "DIBDI4": "BRAM_FIFO36_DIBDIL2", - "DIBDI5": "BRAM_FIFO36_DIBDIU2", - "DIBDI6": "BRAM_FIFO36_DIBDIL3", - "DIBDI7": "BRAM_FIFO36_DIBDIU3", - "DIBDI8": "BRAM_FIFO36_DIBDIL4", - "DIBDI9": "BRAM_FIFO36_DIBDIU4", - "DIPADIP0": "BRAM_FIFO36_DIPADIPL0", - "DIPADIP1": "BRAM_FIFO36_DIPADIPU0", - "DIPADIP2": "BRAM_FIFO36_DIPADIPL1", - "DIPADIP3": "BRAM_FIFO36_DIPADIPU1", - "DIPBDIP0": "BRAM_FIFO36_DIPBDIPL0", - "DIPBDIP1": "BRAM_FIFO36_DIPBDIPU0", - "DIPBDIP2": "BRAM_FIFO36_DIPBDIPL1", - "DIPBDIP3": "BRAM_FIFO36_DIPBDIPU1", - "DOADO0": "BRAM_FIFO36_DOADOL0", - "DOADO1": "BRAM_FIFO36_DOADOU0", - "DOADO10": "BRAM_FIFO36_DOADOL5", - "DOADO11": "BRAM_FIFO36_DOADOU5", - "DOADO12": "BRAM_FIFO36_DOADOL6", - "DOADO13": "BRAM_FIFO36_DOADOU6", - "DOADO14": "BRAM_FIFO36_DOADOL7", - "DOADO15": "BRAM_FIFO36_DOADOU7", - "DOADO16": "BRAM_FIFO36_DOADOL8", - "DOADO17": "BRAM_FIFO36_DOADOU8", - "DOADO18": "BRAM_FIFO36_DOADOL9", - "DOADO19": "BRAM_FIFO36_DOADOU9", - "DOADO2": "BRAM_FIFO36_DOADOL1", - "DOADO20": "BRAM_FIFO36_DOADOL10", - "DOADO21": "BRAM_FIFO36_DOADOU10", - "DOADO22": "BRAM_FIFO36_DOADOL11", - "DOADO23": "BRAM_FIFO36_DOADOU11", - "DOADO24": "BRAM_FIFO36_DOADOL12", - "DOADO25": "BRAM_FIFO36_DOADOU12", - "DOADO26": "BRAM_FIFO36_DOADOL13", - "DOADO27": "BRAM_FIFO36_DOADOU13", - "DOADO28": "BRAM_FIFO36_DOADOL14", - "DOADO29": "BRAM_FIFO36_DOADOU14", - "DOADO3": "BRAM_FIFO36_DOADOU1", - "DOADO30": "BRAM_FIFO36_DOADOL15", - "DOADO31": "BRAM_FIFO36_DOADOU15", - "DOADO4": "BRAM_FIFO36_DOADOL2", - "DOADO5": "BRAM_FIFO36_DOADOU2", - "DOADO6": "BRAM_FIFO36_DOADOL3", - "DOADO7": "BRAM_FIFO36_DOADOU3", - "DOADO8": "BRAM_FIFO36_DOADOL4", - "DOADO9": "BRAM_FIFO36_DOADOU4", - "DOBDO0": "BRAM_FIFO36_DOBDOL0", - "DOBDO1": "BRAM_FIFO36_DOBDOU0", - "DOBDO10": "BRAM_FIFO36_DOBDOL5", - "DOBDO11": "BRAM_FIFO36_DOBDOU5", - "DOBDO12": "BRAM_FIFO36_DOBDOL6", - "DOBDO13": "BRAM_FIFO36_DOBDOU6", - "DOBDO14": "BRAM_FIFO36_DOBDOL7", - "DOBDO15": "BRAM_FIFO36_DOBDOU7", - "DOBDO16": "BRAM_FIFO36_DOBDOL8", - "DOBDO17": "BRAM_FIFO36_DOBDOU8", - "DOBDO18": "BRAM_FIFO36_DOBDOL9", - "DOBDO19": "BRAM_FIFO36_DOBDOU9", - "DOBDO2": "BRAM_FIFO36_DOBDOL1", - "DOBDO20": "BRAM_FIFO36_DOBDOL10", - "DOBDO21": "BRAM_FIFO36_DOBDOU10", - "DOBDO22": "BRAM_FIFO36_DOBDOL11", - "DOBDO23": "BRAM_FIFO36_DOBDOU11", - "DOBDO24": "BRAM_FIFO36_DOBDOL12", - "DOBDO25": "BRAM_FIFO36_DOBDOU12", - "DOBDO26": "BRAM_FIFO36_DOBDOL13", - "DOBDO27": "BRAM_FIFO36_DOBDOU13", - "DOBDO28": "BRAM_FIFO36_DOBDOL14", - "DOBDO29": "BRAM_FIFO36_DOBDOU14", - "DOBDO3": "BRAM_FIFO36_DOBDOU1", - "DOBDO30": "BRAM_FIFO36_DOBDOL15", - "DOBDO31": "BRAM_FIFO36_DOBDOU15", - "DOBDO4": "BRAM_FIFO36_DOBDOL2", - "DOBDO5": "BRAM_FIFO36_DOBDOU2", - "DOBDO6": "BRAM_FIFO36_DOBDOL3", - "DOBDO7": "BRAM_FIFO36_DOBDOU3", - "DOBDO8": "BRAM_FIFO36_DOBDOL4", - "DOBDO9": "BRAM_FIFO36_DOBDOU4", - "DOPADOP0": "BRAM_FIFO36_DOPADOPL0", - "DOPADOP1": "BRAM_FIFO36_DOPADOPU0", - "DOPADOP2": "BRAM_FIFO36_DOPADOPL1", - "DOPADOP3": "BRAM_FIFO36_DOPADOPU1", - "DOPBDOP0": "BRAM_FIFO36_DOPBDOPL0", - "DOPBDOP1": "BRAM_FIFO36_DOPBDOPU0", - "DOPBDOP2": "BRAM_FIFO36_DOPBDOPL1", - "DOPBDOP3": "BRAM_FIFO36_DOPBDOPU1", - "ECCPARITY0": "BRAM_FIFO36_ECCPARITY0", - "ECCPARITY1": "BRAM_FIFO36_ECCPARITY1", - "ECCPARITY2": "BRAM_FIFO36_ECCPARITY2", - "ECCPARITY3": "BRAM_FIFO36_ECCPARITY3", - "ECCPARITY4": "BRAM_FIFO36_ECCPARITY4", - "ECCPARITY5": "BRAM_FIFO36_ECCPARITY5", - "ECCPARITY6": "BRAM_FIFO36_ECCPARITY6", - "ECCPARITY7": "BRAM_FIFO36_ECCPARITY7", - "EMPTY": "BRAM_FIFO36_EMPTY", - "ENARDENL": "BRAM_FIFO36_ENARDENL", - "ENARDENU": "BRAM_FIFO36_ENARDENU", - "ENBWRENL": "BRAM_FIFO36_ENBWRENL", - "ENBWRENU": "BRAM_FIFO36_ENBWRENU", - "FULL": "BRAM_FIFO36_FULL", - "INJECTDBITERR": "BRAM_FIFO36_INJECTDBITERR", - "INJECTSBITERR": "BRAM_FIFO36_INJECTSBITERR", - "RDCOUNT0": "BRAM_FIFO36_RDCOUNT0", - "RDCOUNT1": "BRAM_FIFO36_RDCOUNT1", - "RDCOUNT10": "BRAM_FIFO36_RDCOUNT10", - "RDCOUNT11": "BRAM_FIFO36_RDCOUNT11", - "RDCOUNT12": "BRAM_FIFO36_RDCOUNT12", - "RDCOUNT2": "BRAM_FIFO36_RDCOUNT2", - "RDCOUNT3": "BRAM_FIFO36_RDCOUNT3", - "RDCOUNT4": "BRAM_FIFO36_RDCOUNT4", - "RDCOUNT5": "BRAM_FIFO36_RDCOUNT5", - "RDCOUNT6": "BRAM_FIFO36_RDCOUNT6", - "RDCOUNT7": "BRAM_FIFO36_RDCOUNT7", - "RDCOUNT8": "BRAM_FIFO36_RDCOUNT8", - "RDCOUNT9": "BRAM_FIFO36_RDCOUNT9", - "RDERR": "BRAM_FIFO36_RDERR", - "REGCEAREGCEL": "BRAM_FIFO36_REGCEAREGCEL", - "REGCEAREGCEU": "BRAM_FIFO36_REGCEAREGCEU", - "REGCEBL": "BRAM_FIFO36_REGCEBL", - "REGCEBU": "BRAM_FIFO36_REGCEBU", - "REGCLKARDRCLKL": "BRAM_FIFO36_REGCLKARDRCLKL", - "REGCLKARDRCLKU": "BRAM_FIFO36_REGCLKARDRCLKU", - "REGCLKBL": "BRAM_FIFO36_REGCLKBL", - "REGCLKBU": "BRAM_FIFO36_REGCLKBU", - "RSTRAMARSTRAMLRST": "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "RSTRAMARSTRAMU": "BRAM_FIFO36_RSTRAMARSTRAMU", - "RSTRAMBL": "BRAM_FIFO36_RSTRAMBL", - "RSTRAMBU": "BRAM_FIFO36_RSTRAMBU", - "RSTREGARSTREGL": "BRAM_FIFO36_RSTREGARSTREGL", - "RSTREGARSTREGU": "BRAM_FIFO36_RSTREGARSTREGU", - "RSTREGBL": "BRAM_FIFO36_RSTREGBL", - "RSTREGBU": "BRAM_FIFO36_RSTREGBU", - "SBITERR": "BRAM_FIFO36_SBITERR", - "TSTBRAMRST": "BRAM_FIFO36_TSTBRAMRST", - "TSTCNT0": "BRAM_FIFO36_TSTCNT0", - "TSTCNT1": "BRAM_FIFO36_TSTCNT1", - "TSTCNT10": "BRAM_FIFO36_TSTCNT10", - "TSTCNT11": "BRAM_FIFO36_TSTCNT11", - "TSTCNT12": "BRAM_FIFO36_TSTCNT12", - "TSTCNT2": "BRAM_FIFO36_TSTCNT2", - "TSTCNT3": "BRAM_FIFO36_TSTCNT3", - "TSTCNT4": "BRAM_FIFO36_TSTCNT4", - "TSTCNT5": "BRAM_FIFO36_TSTCNT5", - "TSTCNT6": "BRAM_FIFO36_TSTCNT6", - "TSTCNT7": "BRAM_FIFO36_TSTCNT7", - "TSTCNT8": "BRAM_FIFO36_TSTCNT8", - "TSTCNT9": "BRAM_FIFO36_TSTCNT9", - "TSTFLAGIN": "BRAM_FIFO36_TSTFLAGIN", - "TSTIN0": "BRAM_FIFO36_TSTIN0", - "TSTIN1": "BRAM_FIFO36_TSTIN1", - "TSTIN2": "BRAM_FIFO36_TSTIN2", - "TSTIN3": "BRAM_FIFO36_TSTIN3", - "TSTIN4": "BRAM_FIFO36_TSTIN4", - "TSTOFF": "BRAM_FIFO36_TSTOFF", - "TSTOUT0": "BRAM_FIFO36_TSTOUT0", - "TSTOUT1": "BRAM_FIFO36_TSTOUT1", - "TSTOUT2": "BRAM_FIFO36_TSTOUT2", - "TSTOUT3": "BRAM_FIFO36_TSTOUT3", - "TSTOUT4": "BRAM_FIFO36_TSTOUT4", - "TSTRDCNTOFF": "BRAM_FIFO36_TSTRDCNTOFF", - "TSTRDOS0": "BRAM_FIFO36_TSTRDOS0", - "TSTRDOS1": "BRAM_FIFO36_TSTRDOS1", - "TSTRDOS10": "BRAM_FIFO36_TSTRDOS10", - "TSTRDOS11": "BRAM_FIFO36_TSTRDOS11", - "TSTRDOS12": "BRAM_FIFO36_TSTRDOS12", - "TSTRDOS2": "BRAM_FIFO36_TSTRDOS2", - "TSTRDOS3": "BRAM_FIFO36_TSTRDOS3", - "TSTRDOS4": "BRAM_FIFO36_TSTRDOS4", - "TSTRDOS5": "BRAM_FIFO36_TSTRDOS5", - "TSTRDOS6": "BRAM_FIFO36_TSTRDOS6", - "TSTRDOS7": "BRAM_FIFO36_TSTRDOS7", - "TSTRDOS8": "BRAM_FIFO36_TSTRDOS8", - "TSTRDOS9": "BRAM_FIFO36_TSTRDOS9", - "TSTWRCNTOFF": "BRAM_FIFO36_TSTWRCNTOFF", - "TSTWROS0": "BRAM_FIFO36_TSTWROS0", - "TSTWROS1": "BRAM_FIFO36_TSTWROS1", - "TSTWROS10": "BRAM_FIFO36_TSTWROS10", - "TSTWROS11": "BRAM_FIFO36_TSTWROS11", - "TSTWROS12": "BRAM_FIFO36_TSTWROS12", - "TSTWROS2": "BRAM_FIFO36_TSTWROS2", - "TSTWROS3": "BRAM_FIFO36_TSTWROS3", - "TSTWROS4": "BRAM_FIFO36_TSTWROS4", - "TSTWROS5": "BRAM_FIFO36_TSTWROS5", - "TSTWROS6": "BRAM_FIFO36_TSTWROS6", - "TSTWROS7": "BRAM_FIFO36_TSTWROS7", - "TSTWROS8": "BRAM_FIFO36_TSTWROS8", - "TSTWROS9": "BRAM_FIFO36_TSTWROS9", - "WEAL0": "BRAM_FIFO36_WEAL0", - "WEAL1": "BRAM_FIFO36_WEAL1", - "WEAL2": "BRAM_FIFO36_WEAL2", - "WEAL3": "BRAM_FIFO36_WEAL3", - "WEAU0": "BRAM_FIFO36_WEAU0", - "WEAU1": "BRAM_FIFO36_WEAU1", - "WEAU2": "BRAM_FIFO36_WEAU2", - "WEAU3": "BRAM_FIFO36_WEAU3", - "WEBWEL0": "BRAM_FIFO36_WEBWEL0", - "WEBWEL1": "BRAM_FIFO36_WEBWEL1", - "WEBWEL2": "BRAM_FIFO36_WEBWEL2", - "WEBWEL3": "BRAM_FIFO36_WEBWEL3", - "WEBWEL4": "BRAM_FIFO36_WEBWEL4", - "WEBWEL5": "BRAM_FIFO36_WEBWEL5", - "WEBWEL6": "BRAM_FIFO36_WEBWEL6", - "WEBWEL7": "BRAM_FIFO36_WEBWEL7", - "WEBWEU0": "BRAM_FIFO36_WEBWEU0", - "WEBWEU1": "BRAM_FIFO36_WEBWEU1", - "WEBWEU2": "BRAM_FIFO36_WEBWEU2", - "WEBWEU3": "BRAM_FIFO36_WEBWEU3", - "WEBWEU4": "BRAM_FIFO36_WEBWEU4", - "WEBWEU5": "BRAM_FIFO36_WEBWEU5", - "WEBWEU6": "BRAM_FIFO36_WEBWEU6", - "WEBWEU7": "BRAM_FIFO36_WEBWEU7", - "WRCOUNT0": "BRAM_FIFO36_WRCOUNT0", - "WRCOUNT1": "BRAM_FIFO36_WRCOUNT1", - "WRCOUNT10": "BRAM_FIFO36_WRCOUNT10", - "WRCOUNT11": "BRAM_FIFO36_WRCOUNT11", - "WRCOUNT12": "BRAM_FIFO36_WRCOUNT12", - "WRCOUNT2": "BRAM_FIFO36_WRCOUNT2", - "WRCOUNT3": "BRAM_FIFO36_WRCOUNT3", - "WRCOUNT4": "BRAM_FIFO36_WRCOUNT4", - "WRCOUNT5": "BRAM_FIFO36_WRCOUNT5", - "WRCOUNT6": "BRAM_FIFO36_WRCOUNT6", - "WRCOUNT7": "BRAM_FIFO36_WRCOUNT7", - "WRCOUNT8": "BRAM_FIFO36_WRCOUNT8", - "WRCOUNT9": "BRAM_FIFO36_WRCOUNT9", - "WRERR": "BRAM_FIFO36_WRERR" + "ADDRARDADDRL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL0" + }, + "ADDRARDADDRL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL1" + }, + "ADDRARDADDRL10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL10" + }, + "ADDRARDADDRL11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL11" + }, + "ADDRARDADDRL12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL12" + }, + "ADDRARDADDRL13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL13" + }, + "ADDRARDADDRL14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL14" + }, + "ADDRARDADDRL15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL15" + }, + "ADDRARDADDRL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL2" + }, + "ADDRARDADDRL3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL3" + }, + "ADDRARDADDRL4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL4" + }, + "ADDRARDADDRL5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL5" + }, + "ADDRARDADDRL6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL6" + }, + "ADDRARDADDRL7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL7" + }, + "ADDRARDADDRL8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL8" + }, + "ADDRARDADDRL9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL9" + }, + "ADDRARDADDRU0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU0" + }, + "ADDRARDADDRU1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU1" + }, + "ADDRARDADDRU10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU10" + }, + "ADDRARDADDRU11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU11" + }, + "ADDRARDADDRU12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU12" + }, + "ADDRARDADDRU13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU13" + }, + "ADDRARDADDRU14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU14" + }, + "ADDRARDADDRU2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU2" + }, + "ADDRARDADDRU3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU3" + }, + "ADDRARDADDRU4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU4" + }, + "ADDRARDADDRU5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU5" + }, + "ADDRARDADDRU6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU6" + }, + "ADDRARDADDRU7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU7" + }, + "ADDRARDADDRU8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU8" + }, + "ADDRARDADDRU9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRU9" + }, + "ADDRBWRADDRL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL0" + }, + "ADDRBWRADDRL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL1" + }, + "ADDRBWRADDRL10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL10" + }, + "ADDRBWRADDRL11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL11" + }, + "ADDRBWRADDRL12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL12" + }, + "ADDRBWRADDRL13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL13" + }, + "ADDRBWRADDRL14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL14" + }, + "ADDRBWRADDRL15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL15" + }, + "ADDRBWRADDRL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL2" + }, + "ADDRBWRADDRL3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL3" + }, + "ADDRBWRADDRL4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL4" + }, + "ADDRBWRADDRL5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL5" + }, + "ADDRBWRADDRL6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL6" + }, + "ADDRBWRADDRL7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL7" + }, + "ADDRBWRADDRL8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL8" + }, + "ADDRBWRADDRL9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRL9" + }, + "ADDRBWRADDRU0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRU0" + }, + "ADDRBWRADDRU1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRU1" + }, + "ADDRBWRADDRU10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRU10" + }, + "ADDRBWRADDRU11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRU11" + }, + "ADDRBWRADDRU12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRU12" + }, + "ADDRBWRADDRU13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRU13" + }, + "ADDRBWRADDRU14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRU14" + }, + "ADDRBWRADDRU2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRU2" + }, + "ADDRBWRADDRU3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRU3" + }, + "ADDRBWRADDRU4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRBWRADDRU4" + }, + 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"BRAM_ADDRBWRADDRL1", - "BRAM_ADDRBWRADDRL10", - "BRAM_ADDRBWRADDRL11", - "BRAM_ADDRBWRADDRL12", - "BRAM_ADDRBWRADDRL13", - "BRAM_ADDRBWRADDRL14", - "BRAM_ADDRBWRADDRL2", - "BRAM_ADDRBWRADDRL3", - "BRAM_ADDRBWRADDRL4", - "BRAM_ADDRBWRADDRL5", - "BRAM_ADDRBWRADDRL6", - "BRAM_ADDRBWRADDRL7", - "BRAM_ADDRBWRADDRL8", - "BRAM_ADDRBWRADDRL9", - "BRAM_ADDRBWRADDRU0", - "BRAM_ADDRBWRADDRU1", - "BRAM_ADDRBWRADDRU10", - "BRAM_ADDRBWRADDRU11", - "BRAM_ADDRBWRADDRU12", - "BRAM_ADDRBWRADDRU13", - "BRAM_ADDRBWRADDRU14", - "BRAM_ADDRBWRADDRU2", - "BRAM_ADDRBWRADDRU3", - "BRAM_ADDRBWRADDRU4", - "BRAM_ADDRBWRADDRU5", - "BRAM_ADDRBWRADDRU6", - "BRAM_ADDRBWRADDRU7", - "BRAM_ADDRBWRADDRU8", - "BRAM_ADDRBWRADDRU9", - "BRAM_BLOCK_OUTS_L_B0_0", - "BRAM_BLOCK_OUTS_L_B0_1", - "BRAM_BLOCK_OUTS_L_B0_2", - "BRAM_BLOCK_OUTS_L_B0_3", - "BRAM_BLOCK_OUTS_L_B0_4", - "BRAM_BLOCK_OUTS_L_B1_0", - "BRAM_BLOCK_OUTS_L_B1_1", - "BRAM_BLOCK_OUTS_L_B1_2", - "BRAM_BLOCK_OUTS_L_B1_3", - "BRAM_BLOCK_OUTS_L_B1_4", - "BRAM_BLOCK_OUTS_L_B2_0", - "BRAM_BLOCK_OUTS_L_B2_1", - "BRAM_BLOCK_OUTS_L_B2_2", - "BRAM_BLOCK_OUTS_L_B2_3", - "BRAM_BLOCK_OUTS_L_B2_4", - "BRAM_BLOCK_OUTS_L_B3_0", - "BRAM_BLOCK_OUTS_L_B3_1", - "BRAM_BLOCK_OUTS_L_B3_2", - "BRAM_BLOCK_OUTS_L_B3_3", - "BRAM_BLOCK_OUTS_L_B3_4", - "BRAM_BYP0_0", - "BRAM_BYP0_1", - "BRAM_BYP0_2", - "BRAM_BYP0_3", - "BRAM_BYP0_4", - "BRAM_BYP1_0", - "BRAM_BYP1_1", - "BRAM_BYP1_2", - "BRAM_BYP1_3", - "BRAM_BYP1_4", - "BRAM_BYP2_0", - "BRAM_BYP2_1", - "BRAM_BYP2_2", - "BRAM_BYP2_3", - "BRAM_BYP2_4", - "BRAM_BYP3_0", - "BRAM_BYP3_1", - "BRAM_BYP3_2", - "BRAM_BYP3_3", - "BRAM_BYP3_4", - "BRAM_BYP4_0", - "BRAM_BYP4_1", - "BRAM_BYP4_2", - "BRAM_BYP4_3", - "BRAM_BYP4_4", - "BRAM_BYP5_0", - "BRAM_BYP5_1", - "BRAM_BYP5_2", - "BRAM_BYP5_3", - "BRAM_BYP5_4", - "BRAM_BYP6_0", - "BRAM_BYP6_1", - "BRAM_BYP6_2", - "BRAM_BYP6_3", - "BRAM_BYP6_4", - "BRAM_BYP7_0", - "BRAM_BYP7_1", - "BRAM_BYP7_2", - "BRAM_BYP7_3", - "BRAM_BYP7_4", - "BRAM_CASCINBOT_ADDRARDADDRU0", - "BRAM_CASCINBOT_ADDRARDADDRU1", - "BRAM_CASCINBOT_ADDRARDADDRU10", - "BRAM_CASCINBOT_ADDRARDADDRU11", - "BRAM_CASCINBOT_ADDRARDADDRU12", - "BRAM_CASCINBOT_ADDRARDADDRU13", - "BRAM_CASCINBOT_ADDRARDADDRU14", - "BRAM_CASCINBOT_ADDRARDADDRU2", - "BRAM_CASCINBOT_ADDRARDADDRU3", - "BRAM_CASCINBOT_ADDRARDADDRU4", - "BRAM_CASCINBOT_ADDRARDADDRU5", - "BRAM_CASCINBOT_ADDRARDADDRU6", - "BRAM_CASCINBOT_ADDRARDADDRU7", - "BRAM_CASCINBOT_ADDRARDADDRU8", - "BRAM_CASCINBOT_ADDRARDADDRU9", - "BRAM_CASCINBOT_ADDRBWRADDRU0", - "BRAM_CASCINBOT_ADDRBWRADDRU1", - "BRAM_CASCINBOT_ADDRBWRADDRU10", - "BRAM_CASCINBOT_ADDRBWRADDRU11", - "BRAM_CASCINBOT_ADDRBWRADDRU12", - "BRAM_CASCINBOT_ADDRBWRADDRU13", - "BRAM_CASCINBOT_ADDRBWRADDRU14", - "BRAM_CASCINBOT_ADDRBWRADDRU2", - "BRAM_CASCINBOT_ADDRBWRADDRU3", - "BRAM_CASCINBOT_ADDRBWRADDRU4", - "BRAM_CASCINBOT_ADDRBWRADDRU5", - "BRAM_CASCINBOT_ADDRBWRADDRU6", - "BRAM_CASCINBOT_ADDRBWRADDRU7", - "BRAM_CASCINBOT_ADDRBWRADDRU8", - "BRAM_CASCINBOT_ADDRBWRADDRU9", - "BRAM_CASCINTOP_ADDRARDADDRU0", - "BRAM_CASCINTOP_ADDRARDADDRU1", - "BRAM_CASCINTOP_ADDRARDADDRU10", - "BRAM_CASCINTOP_ADDRARDADDRU11", - "BRAM_CASCINTOP_ADDRARDADDRU12", - "BRAM_CASCINTOP_ADDRARDADDRU13", - "BRAM_CASCINTOP_ADDRARDADDRU14", - "BRAM_CASCINTOP_ADDRARDADDRU2", - "BRAM_CASCINTOP_ADDRARDADDRU3", - "BRAM_CASCINTOP_ADDRARDADDRU4", - "BRAM_CASCINTOP_ADDRARDADDRU5", - "BRAM_CASCINTOP_ADDRARDADDRU6", - "BRAM_CASCINTOP_ADDRARDADDRU7", - "BRAM_CASCINTOP_ADDRARDADDRU8", - "BRAM_CASCINTOP_ADDRARDADDRU9", - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "BRAM_CASCINTOP_ADDRBWRADDRU7", - "BRAM_CASCINTOP_ADDRBWRADDRU8", - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "BRAM_CASCOUT_ADDRARDADDRU0", - "BRAM_CASCOUT_ADDRARDADDRU1", - "BRAM_CASCOUT_ADDRARDADDRU10", - "BRAM_CASCOUT_ADDRARDADDRU11", - "BRAM_CASCOUT_ADDRARDADDRU12", - "BRAM_CASCOUT_ADDRARDADDRU13", - "BRAM_CASCOUT_ADDRARDADDRU14", - "BRAM_CASCOUT_ADDRARDADDRU2", - "BRAM_CASCOUT_ADDRARDADDRU3", - "BRAM_CASCOUT_ADDRARDADDRU4", - "BRAM_CASCOUT_ADDRARDADDRU5", - "BRAM_CASCOUT_ADDRARDADDRU6", - "BRAM_CASCOUT_ADDRARDADDRU7", - "BRAM_CASCOUT_ADDRARDADDRU8", - "BRAM_CASCOUT_ADDRARDADDRU9", - "BRAM_CASCOUT_ADDRBWRADDRU0", - "BRAM_CASCOUT_ADDRBWRADDRU1", - "BRAM_CASCOUT_ADDRBWRADDRU10", - "BRAM_CASCOUT_ADDRBWRADDRU11", - "BRAM_CASCOUT_ADDRBWRADDRU12", - "BRAM_CASCOUT_ADDRBWRADDRU13", - "BRAM_CASCOUT_ADDRBWRADDRU14", - "BRAM_CASCOUT_ADDRBWRADDRU2", - "BRAM_CASCOUT_ADDRBWRADDRU3", - "BRAM_CASCOUT_ADDRBWRADDRU4", - "BRAM_CASCOUT_ADDRBWRADDRU5", - "BRAM_CASCOUT_ADDRBWRADDRU6", - "BRAM_CASCOUT_ADDRBWRADDRU7", - "BRAM_CASCOUT_ADDRBWRADDRU8", - "BRAM_CASCOUT_ADDRBWRADDRU9", - "BRAM_CLK0_0", - "BRAM_CLK0_1", - "BRAM_CLK0_2", - "BRAM_CLK0_3", - "BRAM_CLK0_4", - "BRAM_CLK1_0", - "BRAM_CLK1_1", - "BRAM_CLK1_2", - "BRAM_CLK1_3", - "BRAM_CLK1_4", - "BRAM_CTRL0_0", - "BRAM_CTRL0_1", - "BRAM_CTRL0_2", - "BRAM_CTRL0_3", - "BRAM_CTRL0_4", - "BRAM_CTRL1_0", - "BRAM_CTRL1_1", - "BRAM_CTRL1_2", - "BRAM_CTRL1_3", - "BRAM_CTRL1_4", - "BRAM_EE2A0_0", - "BRAM_EE2A0_1", - "BRAM_EE2A0_2", - "BRAM_EE2A0_3", - "BRAM_EE2A0_4", - "BRAM_EE2A1_0", - "BRAM_EE2A1_1", - "BRAM_EE2A1_2", - "BRAM_EE2A1_3", - "BRAM_EE2A1_4", - "BRAM_EE2A2_0", - "BRAM_EE2A2_1", - "BRAM_EE2A2_2", - "BRAM_EE2A2_3", - "BRAM_EE2A2_4", - "BRAM_EE2A3_0", - "BRAM_EE2A3_1", - "BRAM_EE2A3_2", - "BRAM_EE2A3_3", - "BRAM_EE2A3_4", - "BRAM_EE2BEG0_0", - "BRAM_EE2BEG0_1", - "BRAM_EE2BEG0_2", - "BRAM_EE2BEG0_3", - "BRAM_EE2BEG0_4", - "BRAM_EE2BEG1_0", - "BRAM_EE2BEG1_1", - "BRAM_EE2BEG1_2", - "BRAM_EE2BEG1_3", - "BRAM_EE2BEG1_4", - "BRAM_EE2BEG2_0", - "BRAM_EE2BEG2_1", - "BRAM_EE2BEG2_2", - "BRAM_EE2BEG2_3", - "BRAM_EE2BEG2_4", - "BRAM_EE2BEG3_0", - "BRAM_EE2BEG3_1", - "BRAM_EE2BEG3_2", - "BRAM_EE2BEG3_3", - "BRAM_EE2BEG3_4", - "BRAM_EE4A0_0", - "BRAM_EE4A0_1", - "BRAM_EE4A0_2", - "BRAM_EE4A0_3", - "BRAM_EE4A0_4", - "BRAM_EE4A1_0", - "BRAM_EE4A1_1", - "BRAM_EE4A1_2", - "BRAM_EE4A1_3", - "BRAM_EE4A1_4", - "BRAM_EE4A2_0", - "BRAM_EE4A2_1", - "BRAM_EE4A2_2", - "BRAM_EE4A2_3", - "BRAM_EE4A2_4", - "BRAM_EE4A3_0", - "BRAM_EE4A3_1", - "BRAM_EE4A3_2", - "BRAM_EE4A3_3", - "BRAM_EE4A3_4", - "BRAM_EE4B0_0", - "BRAM_EE4B0_1", - "BRAM_EE4B0_2", - "BRAM_EE4B0_3", - "BRAM_EE4B0_4", - "BRAM_EE4B1_0", - "BRAM_EE4B1_1", - "BRAM_EE4B1_2", - "BRAM_EE4B1_3", - "BRAM_EE4B1_4", - "BRAM_EE4B2_0", - "BRAM_EE4B2_1", - "BRAM_EE4B2_2", - "BRAM_EE4B2_3", - "BRAM_EE4B2_4", - "BRAM_EE4B3_0", - "BRAM_EE4B3_1", - "BRAM_EE4B3_2", - "BRAM_EE4B3_3", - "BRAM_EE4B3_4", - "BRAM_EE4BEG0_0", - "BRAM_EE4BEG0_1", - "BRAM_EE4BEG0_2", - "BRAM_EE4BEG0_3", - "BRAM_EE4BEG0_4", - "BRAM_EE4BEG1_0", - "BRAM_EE4BEG1_1", - "BRAM_EE4BEG1_2", - "BRAM_EE4BEG1_3", - "BRAM_EE4BEG1_4", - "BRAM_EE4BEG2_0", - "BRAM_EE4BEG2_1", - "BRAM_EE4BEG2_2", - "BRAM_EE4BEG2_3", - "BRAM_EE4BEG2_4", - "BRAM_EE4BEG3_0", - "BRAM_EE4BEG3_1", - "BRAM_EE4BEG3_2", - "BRAM_EE4BEG3_3", - "BRAM_EE4BEG3_4", - "BRAM_EE4C0_0", - "BRAM_EE4C0_1", - "BRAM_EE4C0_2", - "BRAM_EE4C0_3", - "BRAM_EE4C0_4", - "BRAM_EE4C1_0", - "BRAM_EE4C1_1", - "BRAM_EE4C1_2", - "BRAM_EE4C1_3", - "BRAM_EE4C1_4", - "BRAM_EE4C2_0", - "BRAM_EE4C2_1", - "BRAM_EE4C2_2", - "BRAM_EE4C2_3", - "BRAM_EE4C2_4", - "BRAM_EE4C3_0", - "BRAM_EE4C3_1", - "BRAM_EE4C3_2", - "BRAM_EE4C3_3", - "BRAM_EE4C3_4", - "BRAM_EL1BEG0_0", - "BRAM_EL1BEG0_1", - "BRAM_EL1BEG0_2", - "BRAM_EL1BEG0_3", - "BRAM_EL1BEG0_4", - "BRAM_EL1BEG1_0", - "BRAM_EL1BEG1_1", - "BRAM_EL1BEG1_2", - "BRAM_EL1BEG1_3", - "BRAM_EL1BEG1_4", - "BRAM_EL1BEG2_0", - "BRAM_EL1BEG2_1", - "BRAM_EL1BEG2_2", - "BRAM_EL1BEG2_3", - "BRAM_EL1BEG2_4", - "BRAM_EL1BEG3_0", - "BRAM_EL1BEG3_1", - "BRAM_EL1BEG3_2", - "BRAM_EL1BEG3_3", - "BRAM_EL1BEG3_4", - "BRAM_ER1BEG0_0", - "BRAM_ER1BEG0_1", - "BRAM_ER1BEG0_2", - "BRAM_ER1BEG0_3", - "BRAM_ER1BEG0_4", - "BRAM_ER1BEG1_0", - "BRAM_ER1BEG1_1", - "BRAM_ER1BEG1_2", - "BRAM_ER1BEG1_3", - "BRAM_ER1BEG1_4", - "BRAM_ER1BEG2_0", - "BRAM_ER1BEG2_1", - "BRAM_ER1BEG2_2", - "BRAM_ER1BEG2_3", - "BRAM_ER1BEG2_4", - "BRAM_ER1BEG3_0", - "BRAM_ER1BEG3_1", - "BRAM_ER1BEG3_2", - "BRAM_ER1BEG3_3", - "BRAM_ER1BEG3_4", - "BRAM_FAN0_0", - "BRAM_FAN0_1", - "BRAM_FAN0_2", - "BRAM_FAN0_3", - "BRAM_FAN0_4", - "BRAM_FAN1_0", - "BRAM_FAN1_1", - "BRAM_FAN1_2", - "BRAM_FAN1_3", - "BRAM_FAN1_4", - "BRAM_FAN2_0", - "BRAM_FAN2_1", - "BRAM_FAN2_2", - "BRAM_FAN2_3", - "BRAM_FAN2_4", - "BRAM_FAN3_0", - "BRAM_FAN3_1", - "BRAM_FAN3_2", - "BRAM_FAN3_3", - "BRAM_FAN3_4", - "BRAM_FAN4_0", - "BRAM_FAN4_1", - "BRAM_FAN4_2", - "BRAM_FAN4_3", - "BRAM_FAN4_4", - "BRAM_FAN5_0", - "BRAM_FAN5_1", - "BRAM_FAN5_2", - "BRAM_FAN5_3", - "BRAM_FAN5_4", - "BRAM_FAN6_0", - "BRAM_FAN6_1", - "BRAM_FAN6_2", - "BRAM_FAN6_3", - "BRAM_FAN6_4", - "BRAM_FAN7_0", - "BRAM_FAN7_1", - "BRAM_FAN7_2", - "BRAM_FAN7_3", - "BRAM_FAN7_4", - "BRAM_FIFO18_ADDRARDADDR0", - "BRAM_FIFO18_ADDRARDADDR1", - "BRAM_FIFO18_ADDRARDADDR10", - "BRAM_FIFO18_ADDRARDADDR11", - "BRAM_FIFO18_ADDRARDADDR12", - "BRAM_FIFO18_ADDRARDADDR13", - "BRAM_FIFO18_ADDRARDADDR2", - "BRAM_FIFO18_ADDRARDADDR3", - "BRAM_FIFO18_ADDRARDADDR4", - "BRAM_FIFO18_ADDRARDADDR5", - "BRAM_FIFO18_ADDRARDADDR6", - "BRAM_FIFO18_ADDRARDADDR7", - "BRAM_FIFO18_ADDRARDADDR8", - "BRAM_FIFO18_ADDRARDADDR9", - "BRAM_FIFO18_ADDRATIEHIGH0", - "BRAM_FIFO18_ADDRATIEHIGH1", - "BRAM_FIFO18_ADDRBTIEHIGH0", - "BRAM_FIFO18_ADDRBTIEHIGH1", - "BRAM_FIFO18_ADDRBWRADDR0", - "BRAM_FIFO18_ADDRBWRADDR1", - "BRAM_FIFO18_ADDRBWRADDR10", - "BRAM_FIFO18_ADDRBWRADDR11", - "BRAM_FIFO18_ADDRBWRADDR12", - "BRAM_FIFO18_ADDRBWRADDR13", - "BRAM_FIFO18_ADDRBWRADDR2", - "BRAM_FIFO18_ADDRBWRADDR3", - "BRAM_FIFO18_ADDRBWRADDR4", - "BRAM_FIFO18_ADDRBWRADDR5", - "BRAM_FIFO18_ADDRBWRADDR6", - "BRAM_FIFO18_ADDRBWRADDR7", - "BRAM_FIFO18_ADDRBWRADDR8", - "BRAM_FIFO18_ADDRBWRADDR9", - "BRAM_FIFO18_ALMOSTEMPTY", - "BRAM_FIFO18_ALMOSTFULL", - "BRAM_FIFO18_CLKARDCLK", - "BRAM_FIFO18_CLKBWRCLK", - "BRAM_FIFO18_DIADI0", - "BRAM_FIFO18_DIADI1", - "BRAM_FIFO18_DIADI10", - "BRAM_FIFO18_DIADI11", - "BRAM_FIFO18_DIADI12", - "BRAM_FIFO18_DIADI13", - "BRAM_FIFO18_DIADI14", - "BRAM_FIFO18_DIADI15", - "BRAM_FIFO18_DIADI2", - "BRAM_FIFO18_DIADI3", - "BRAM_FIFO18_DIADI4", - "BRAM_FIFO18_DIADI5", - "BRAM_FIFO18_DIADI6", - "BRAM_FIFO18_DIADI7", - "BRAM_FIFO18_DIADI8", - "BRAM_FIFO18_DIADI9", - "BRAM_FIFO18_DIBDI0", - "BRAM_FIFO18_DIBDI1", - "BRAM_FIFO18_DIBDI10", - "BRAM_FIFO18_DIBDI11", - "BRAM_FIFO18_DIBDI12", - "BRAM_FIFO18_DIBDI13", - "BRAM_FIFO18_DIBDI14", - "BRAM_FIFO18_DIBDI15", - "BRAM_FIFO18_DIBDI2", - "BRAM_FIFO18_DIBDI3", - "BRAM_FIFO18_DIBDI4", - "BRAM_FIFO18_DIBDI5", - "BRAM_FIFO18_DIBDI6", - "BRAM_FIFO18_DIBDI7", - "BRAM_FIFO18_DIBDI8", - "BRAM_FIFO18_DIBDI9", - "BRAM_FIFO18_DIPADIP0", - "BRAM_FIFO18_DIPADIP1", - "BRAM_FIFO18_DIPBDIP0", - "BRAM_FIFO18_DIPBDIP1", - "BRAM_FIFO18_DOADO0", - "BRAM_FIFO18_DOADO1", - "BRAM_FIFO18_DOADO10", - "BRAM_FIFO18_DOADO11", - "BRAM_FIFO18_DOADO12", - "BRAM_FIFO18_DOADO13", - "BRAM_FIFO18_DOADO14", - "BRAM_FIFO18_DOADO15", - "BRAM_FIFO18_DOADO2", - "BRAM_FIFO18_DOADO3", - "BRAM_FIFO18_DOADO4", - "BRAM_FIFO18_DOADO5", - "BRAM_FIFO18_DOADO6", - "BRAM_FIFO18_DOADO7", - "BRAM_FIFO18_DOADO8", - "BRAM_FIFO18_DOADO9", - "BRAM_FIFO18_DOBDO0", - "BRAM_FIFO18_DOBDO1", - "BRAM_FIFO18_DOBDO10", - "BRAM_FIFO18_DOBDO11", - "BRAM_FIFO18_DOBDO12", - "BRAM_FIFO18_DOBDO13", - "BRAM_FIFO18_DOBDO14", - "BRAM_FIFO18_DOBDO15", - "BRAM_FIFO18_DOBDO2", - "BRAM_FIFO18_DOBDO3", - "BRAM_FIFO18_DOBDO4", - "BRAM_FIFO18_DOBDO5", - "BRAM_FIFO18_DOBDO6", - "BRAM_FIFO18_DOBDO7", - "BRAM_FIFO18_DOBDO8", - "BRAM_FIFO18_DOBDO9", - "BRAM_FIFO18_DOPADOP0", - "BRAM_FIFO18_DOPADOP1", - "BRAM_FIFO18_DOPBDOP0", - "BRAM_FIFO18_DOPBDOP1", - "BRAM_FIFO18_EMPTY", - "BRAM_FIFO18_ENARDEN", - "BRAM_FIFO18_ENBWREN", - "BRAM_FIFO18_FULL", - "BRAM_FIFO18_RDCOUNT0", - "BRAM_FIFO18_RDCOUNT1", - "BRAM_FIFO18_RDCOUNT10", - "BRAM_FIFO18_RDCOUNT11", - "BRAM_FIFO18_RDCOUNT2", - "BRAM_FIFO18_RDCOUNT3", - "BRAM_FIFO18_RDCOUNT4", - "BRAM_FIFO18_RDCOUNT5", - "BRAM_FIFO18_RDCOUNT6", - "BRAM_FIFO18_RDCOUNT7", - "BRAM_FIFO18_RDCOUNT8", - "BRAM_FIFO18_RDCOUNT9", - "BRAM_FIFO18_RDERR", - "BRAM_FIFO18_REGCEAREGCE", - "BRAM_FIFO18_REGCEB", - "BRAM_FIFO18_REGCLKARDRCLK", - "BRAM_FIFO18_REGCLKB", - "BRAM_FIFO18_RSTRAMARSTRAM", - "BRAM_FIFO18_RSTRAMB", - "BRAM_FIFO18_RSTREGARSTREG", - "BRAM_FIFO18_RSTREGB", - "BRAM_FIFO18_WEA0", - "BRAM_FIFO18_WEA1", - "BRAM_FIFO18_WEA2", - "BRAM_FIFO18_WEA3", - "BRAM_FIFO18_WEBWE0", - "BRAM_FIFO18_WEBWE1", - "BRAM_FIFO18_WEBWE2", - "BRAM_FIFO18_WEBWE3", - "BRAM_FIFO18_WEBWE4", - "BRAM_FIFO18_WEBWE5", - "BRAM_FIFO18_WEBWE6", - "BRAM_FIFO18_WEBWE7", - "BRAM_FIFO18_WRCOUNT0", - "BRAM_FIFO18_WRCOUNT1", - "BRAM_FIFO18_WRCOUNT10", - "BRAM_FIFO18_WRCOUNT11", - "BRAM_FIFO18_WRCOUNT2", - "BRAM_FIFO18_WRCOUNT3", - "BRAM_FIFO18_WRCOUNT4", - "BRAM_FIFO18_WRCOUNT5", - "BRAM_FIFO18_WRCOUNT6", - "BRAM_FIFO18_WRCOUNT7", - "BRAM_FIFO18_WRCOUNT8", - "BRAM_FIFO18_WRCOUNT9", - "BRAM_FIFO18_WRERR", - "BRAM_FIFO36_ADDRARDADDRL0", - "BRAM_FIFO36_ADDRARDADDRL1", - "BRAM_FIFO36_ADDRARDADDRL10", - "BRAM_FIFO36_ADDRARDADDRL11", - "BRAM_FIFO36_ADDRARDADDRL12", - "BRAM_FIFO36_ADDRARDADDRL13", - "BRAM_FIFO36_ADDRARDADDRL14", - "BRAM_FIFO36_ADDRARDADDRL15", - "BRAM_FIFO36_ADDRARDADDRL2", - "BRAM_FIFO36_ADDRARDADDRL3", - "BRAM_FIFO36_ADDRARDADDRL4", - "BRAM_FIFO36_ADDRARDADDRL5", - "BRAM_FIFO36_ADDRARDADDRL6", - "BRAM_FIFO36_ADDRARDADDRL7", - "BRAM_FIFO36_ADDRARDADDRL8", - "BRAM_FIFO36_ADDRARDADDRL9", - "BRAM_FIFO36_ADDRARDADDRU0", - "BRAM_FIFO36_ADDRARDADDRU1", - "BRAM_FIFO36_ADDRARDADDRU10", - "BRAM_FIFO36_ADDRARDADDRU11", - "BRAM_FIFO36_ADDRARDADDRU12", - "BRAM_FIFO36_ADDRARDADDRU13", - "BRAM_FIFO36_ADDRARDADDRU14", - "BRAM_FIFO36_ADDRARDADDRU2", - "BRAM_FIFO36_ADDRARDADDRU3", - "BRAM_FIFO36_ADDRARDADDRU4", - "BRAM_FIFO36_ADDRARDADDRU5", - "BRAM_FIFO36_ADDRARDADDRU6", - "BRAM_FIFO36_ADDRARDADDRU7", - "BRAM_FIFO36_ADDRARDADDRU8", - "BRAM_FIFO36_ADDRARDADDRU9", - "BRAM_FIFO36_ADDRBWRADDRL0", - "BRAM_FIFO36_ADDRBWRADDRL1", - "BRAM_FIFO36_ADDRBWRADDRL10", - "BRAM_FIFO36_ADDRBWRADDRL11", - "BRAM_FIFO36_ADDRBWRADDRL12", - "BRAM_FIFO36_ADDRBWRADDRL13", - "BRAM_FIFO36_ADDRBWRADDRL14", - "BRAM_FIFO36_ADDRBWRADDRL15", - "BRAM_FIFO36_ADDRBWRADDRL2", - "BRAM_FIFO36_ADDRBWRADDRL3", - "BRAM_FIFO36_ADDRBWRADDRL4", - "BRAM_FIFO36_ADDRBWRADDRL5", - "BRAM_FIFO36_ADDRBWRADDRL6", - "BRAM_FIFO36_ADDRBWRADDRL7", - "BRAM_FIFO36_ADDRBWRADDRL8", - "BRAM_FIFO36_ADDRBWRADDRL9", - "BRAM_FIFO36_ADDRBWRADDRU0", - "BRAM_FIFO36_ADDRBWRADDRU1", - "BRAM_FIFO36_ADDRBWRADDRU10", - "BRAM_FIFO36_ADDRBWRADDRU11", - "BRAM_FIFO36_ADDRBWRADDRU12", - "BRAM_FIFO36_ADDRBWRADDRU13", - "BRAM_FIFO36_ADDRBWRADDRU14", - "BRAM_FIFO36_ADDRBWRADDRU2", - "BRAM_FIFO36_ADDRBWRADDRU3", - "BRAM_FIFO36_ADDRBWRADDRU4", - "BRAM_FIFO36_ADDRBWRADDRU5", - "BRAM_FIFO36_ADDRBWRADDRU6", - "BRAM_FIFO36_ADDRBWRADDRU7", - "BRAM_FIFO36_ADDRBWRADDRU8", - "BRAM_FIFO36_ADDRBWRADDRU9", - "BRAM_FIFO36_ALMOSTEMPTY", - "BRAM_FIFO36_ALMOSTFULL", - "BRAM_FIFO36_CASCADEINA", - "BRAM_FIFO36_CASCADEINB", - "BRAM_FIFO36_CASCADEOUTA", - "BRAM_FIFO36_CASCADEOUTA_1", - "BRAM_FIFO36_CASCADEOUTB", - "BRAM_FIFO36_CASCADEOUTB_1", - "BRAM_FIFO36_CLKARDCLKL", - "BRAM_FIFO36_CLKARDCLKU", - "BRAM_FIFO36_CLKBWRCLKL", - "BRAM_FIFO36_CLKBWRCLKU", - "BRAM_FIFO36_DBITERR", - "BRAM_FIFO36_DIADIL0", - "BRAM_FIFO36_DIADIL1", - "BRAM_FIFO36_DIADIL10", - "BRAM_FIFO36_DIADIL11", - "BRAM_FIFO36_DIADIL12", - "BRAM_FIFO36_DIADIL13", - "BRAM_FIFO36_DIADIL14", - "BRAM_FIFO36_DIADIL15", - "BRAM_FIFO36_DIADIL2", - "BRAM_FIFO36_DIADIL3", - "BRAM_FIFO36_DIADIL4", - "BRAM_FIFO36_DIADIL5", - "BRAM_FIFO36_DIADIL6", - "BRAM_FIFO36_DIADIL7", - "BRAM_FIFO36_DIADIL8", - "BRAM_FIFO36_DIADIL9", - "BRAM_FIFO36_DIADIU0", - "BRAM_FIFO36_DIADIU1", - "BRAM_FIFO36_DIADIU10", - "BRAM_FIFO36_DIADIU11", - "BRAM_FIFO36_DIADIU12", - "BRAM_FIFO36_DIADIU13", - "BRAM_FIFO36_DIADIU14", - "BRAM_FIFO36_DIADIU15", - "BRAM_FIFO36_DIADIU2", - "BRAM_FIFO36_DIADIU3", - "BRAM_FIFO36_DIADIU4", - "BRAM_FIFO36_DIADIU5", - "BRAM_FIFO36_DIADIU6", - "BRAM_FIFO36_DIADIU7", - "BRAM_FIFO36_DIADIU8", - "BRAM_FIFO36_DIADIU9", - "BRAM_FIFO36_DIBDIL0", - "BRAM_FIFO36_DIBDIL1", - "BRAM_FIFO36_DIBDIL10", - "BRAM_FIFO36_DIBDIL11", - "BRAM_FIFO36_DIBDIL12", - "BRAM_FIFO36_DIBDIL13", - "BRAM_FIFO36_DIBDIL14", - "BRAM_FIFO36_DIBDIL15", - "BRAM_FIFO36_DIBDIL2", - "BRAM_FIFO36_DIBDIL3", - "BRAM_FIFO36_DIBDIL4", - "BRAM_FIFO36_DIBDIL5", - "BRAM_FIFO36_DIBDIL6", - "BRAM_FIFO36_DIBDIL7", - "BRAM_FIFO36_DIBDIL8", - "BRAM_FIFO36_DIBDIL9", - "BRAM_FIFO36_DIBDIU0", - "BRAM_FIFO36_DIBDIU1", - "BRAM_FIFO36_DIBDIU10", - "BRAM_FIFO36_DIBDIU11", - "BRAM_FIFO36_DIBDIU12", - "BRAM_FIFO36_DIBDIU13", - "BRAM_FIFO36_DIBDIU14", - "BRAM_FIFO36_DIBDIU15", - "BRAM_FIFO36_DIBDIU2", - "BRAM_FIFO36_DIBDIU3", - "BRAM_FIFO36_DIBDIU4", - "BRAM_FIFO36_DIBDIU5", - "BRAM_FIFO36_DIBDIU6", - "BRAM_FIFO36_DIBDIU7", - "BRAM_FIFO36_DIBDIU8", - "BRAM_FIFO36_DIBDIU9", - "BRAM_FIFO36_DIPADIPL0", - "BRAM_FIFO36_DIPADIPL1", - "BRAM_FIFO36_DIPADIPU0", - "BRAM_FIFO36_DIPADIPU1", - "BRAM_FIFO36_DIPBDIPL0", - "BRAM_FIFO36_DIPBDIPL1", - "BRAM_FIFO36_DIPBDIPU0", - "BRAM_FIFO36_DIPBDIPU1", - "BRAM_FIFO36_DOADOL0", - "BRAM_FIFO36_DOADOL1", - "BRAM_FIFO36_DOADOL10", - "BRAM_FIFO36_DOADOL11", - "BRAM_FIFO36_DOADOL12", - "BRAM_FIFO36_DOADOL13", - "BRAM_FIFO36_DOADOL14", - "BRAM_FIFO36_DOADOL15", - "BRAM_FIFO36_DOADOL2", - "BRAM_FIFO36_DOADOL3", - "BRAM_FIFO36_DOADOL4", - "BRAM_FIFO36_DOADOL5", - "BRAM_FIFO36_DOADOL6", - "BRAM_FIFO36_DOADOL7", - "BRAM_FIFO36_DOADOL8", - "BRAM_FIFO36_DOADOL9", - "BRAM_FIFO36_DOADOU0", - "BRAM_FIFO36_DOADOU1", - "BRAM_FIFO36_DOADOU10", - "BRAM_FIFO36_DOADOU11", - "BRAM_FIFO36_DOADOU12", - "BRAM_FIFO36_DOADOU13", - "BRAM_FIFO36_DOADOU14", - "BRAM_FIFO36_DOADOU15", - "BRAM_FIFO36_DOADOU2", - "BRAM_FIFO36_DOADOU3", - "BRAM_FIFO36_DOADOU4", - "BRAM_FIFO36_DOADOU5", - "BRAM_FIFO36_DOADOU6", - "BRAM_FIFO36_DOADOU7", - "BRAM_FIFO36_DOADOU8", - "BRAM_FIFO36_DOADOU9", - "BRAM_FIFO36_DOBDOL0", - "BRAM_FIFO36_DOBDOL1", - "BRAM_FIFO36_DOBDOL10", - "BRAM_FIFO36_DOBDOL11", - "BRAM_FIFO36_DOBDOL12", - "BRAM_FIFO36_DOBDOL13", - "BRAM_FIFO36_DOBDOL14", - "BRAM_FIFO36_DOBDOL15", - "BRAM_FIFO36_DOBDOL2", - "BRAM_FIFO36_DOBDOL3", - "BRAM_FIFO36_DOBDOL4", - "BRAM_FIFO36_DOBDOL5", - "BRAM_FIFO36_DOBDOL6", - "BRAM_FIFO36_DOBDOL7", - "BRAM_FIFO36_DOBDOL8", - "BRAM_FIFO36_DOBDOL9", - "BRAM_FIFO36_DOBDOU0", - "BRAM_FIFO36_DOBDOU1", - "BRAM_FIFO36_DOBDOU10", - "BRAM_FIFO36_DOBDOU11", - "BRAM_FIFO36_DOBDOU12", - "BRAM_FIFO36_DOBDOU13", - "BRAM_FIFO36_DOBDOU14", - "BRAM_FIFO36_DOBDOU15", - "BRAM_FIFO36_DOBDOU2", - "BRAM_FIFO36_DOBDOU3", - "BRAM_FIFO36_DOBDOU4", - "BRAM_FIFO36_DOBDOU5", - "BRAM_FIFO36_DOBDOU6", - "BRAM_FIFO36_DOBDOU7", - "BRAM_FIFO36_DOBDOU8", - "BRAM_FIFO36_DOBDOU9", - "BRAM_FIFO36_DOPADOPL0", - "BRAM_FIFO36_DOPADOPL1", - "BRAM_FIFO36_DOPADOPU0", - "BRAM_FIFO36_DOPADOPU1", - "BRAM_FIFO36_DOPBDOPL0", - "BRAM_FIFO36_DOPBDOPL1", - "BRAM_FIFO36_DOPBDOPU0", - "BRAM_FIFO36_DOPBDOPU1", - "BRAM_FIFO36_ECCPARITY0", - "BRAM_FIFO36_ECCPARITY1", - "BRAM_FIFO36_ECCPARITY2", - "BRAM_FIFO36_ECCPARITY3", - "BRAM_FIFO36_ECCPARITY4", - "BRAM_FIFO36_ECCPARITY5", - "BRAM_FIFO36_ECCPARITY6", - "BRAM_FIFO36_ECCPARITY7", - "BRAM_FIFO36_EMPTY", - "BRAM_FIFO36_ENARDENL", - "BRAM_FIFO36_ENARDENU", - "BRAM_FIFO36_ENBWRENL", - "BRAM_FIFO36_ENBWRENU", - "BRAM_FIFO36_FULL", - "BRAM_FIFO36_INJECTDBITERR", - "BRAM_FIFO36_INJECTSBITERR", - "BRAM_FIFO36_RDCOUNT0", - "BRAM_FIFO36_RDCOUNT1", - "BRAM_FIFO36_RDCOUNT10", - "BRAM_FIFO36_RDCOUNT11", - "BRAM_FIFO36_RDCOUNT12", - "BRAM_FIFO36_RDCOUNT2", - "BRAM_FIFO36_RDCOUNT3", - "BRAM_FIFO36_RDCOUNT4", - "BRAM_FIFO36_RDCOUNT5", - "BRAM_FIFO36_RDCOUNT6", - "BRAM_FIFO36_RDCOUNT7", - "BRAM_FIFO36_RDCOUNT8", - "BRAM_FIFO36_RDCOUNT9", - "BRAM_FIFO36_RDERR", - "BRAM_FIFO36_REGCEAREGCEL", - "BRAM_FIFO36_REGCEAREGCEU", - "BRAM_FIFO36_REGCEBL", - "BRAM_FIFO36_REGCEBU", - "BRAM_FIFO36_REGCLKARDRCLKL", - "BRAM_FIFO36_REGCLKARDRCLKU", - "BRAM_FIFO36_REGCLKBL", - "BRAM_FIFO36_REGCLKBU", - "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "BRAM_FIFO36_RSTRAMARSTRAMU", - "BRAM_FIFO36_RSTRAMBL", - "BRAM_FIFO36_RSTRAMBU", - "BRAM_FIFO36_RSTREGARSTREGL", - "BRAM_FIFO36_RSTREGARSTREGU", - "BRAM_FIFO36_RSTREGBL", - "BRAM_FIFO36_RSTREGBU", - "BRAM_FIFO36_SBITERR", - "BRAM_FIFO36_TSTBRAMRST", - "BRAM_FIFO36_TSTCNT0", - "BRAM_FIFO36_TSTCNT1", - "BRAM_FIFO36_TSTCNT10", - "BRAM_FIFO36_TSTCNT11", - "BRAM_FIFO36_TSTCNT12", - "BRAM_FIFO36_TSTCNT2", - "BRAM_FIFO36_TSTCNT3", - "BRAM_FIFO36_TSTCNT4", - "BRAM_FIFO36_TSTCNT5", - "BRAM_FIFO36_TSTCNT6", - "BRAM_FIFO36_TSTCNT7", - "BRAM_FIFO36_TSTCNT8", - "BRAM_FIFO36_TSTCNT9", - "BRAM_FIFO36_TSTFLAGIN", - "BRAM_FIFO36_TSTIN0", - "BRAM_FIFO36_TSTIN1", - "BRAM_FIFO36_TSTIN2", - "BRAM_FIFO36_TSTIN3", - "BRAM_FIFO36_TSTIN4", - "BRAM_FIFO36_TSTOFF", - "BRAM_FIFO36_TSTOUT0", - "BRAM_FIFO36_TSTOUT1", - "BRAM_FIFO36_TSTOUT2", - "BRAM_FIFO36_TSTOUT3", - "BRAM_FIFO36_TSTOUT4", - "BRAM_FIFO36_TSTRDCNTOFF", - "BRAM_FIFO36_TSTRDOS0", - "BRAM_FIFO36_TSTRDOS1", - "BRAM_FIFO36_TSTRDOS10", - "BRAM_FIFO36_TSTRDOS11", - "BRAM_FIFO36_TSTRDOS12", - "BRAM_FIFO36_TSTRDOS2", - "BRAM_FIFO36_TSTRDOS3", - "BRAM_FIFO36_TSTRDOS4", - "BRAM_FIFO36_TSTRDOS5", - "BRAM_FIFO36_TSTRDOS6", - "BRAM_FIFO36_TSTRDOS7", - "BRAM_FIFO36_TSTRDOS8", - "BRAM_FIFO36_TSTRDOS9", - "BRAM_FIFO36_TSTWRCNTOFF", - "BRAM_FIFO36_TSTWROS0", - "BRAM_FIFO36_TSTWROS1", - "BRAM_FIFO36_TSTWROS10", - "BRAM_FIFO36_TSTWROS11", - "BRAM_FIFO36_TSTWROS12", - "BRAM_FIFO36_TSTWROS2", - "BRAM_FIFO36_TSTWROS3", - "BRAM_FIFO36_TSTWROS4", - "BRAM_FIFO36_TSTWROS5", - "BRAM_FIFO36_TSTWROS6", - "BRAM_FIFO36_TSTWROS7", - "BRAM_FIFO36_TSTWROS8", - "BRAM_FIFO36_TSTWROS9", - "BRAM_FIFO36_WEAL0", - "BRAM_FIFO36_WEAL1", - "BRAM_FIFO36_WEAL2", - "BRAM_FIFO36_WEAL3", - "BRAM_FIFO36_WEAU0", - "BRAM_FIFO36_WEAU1", - "BRAM_FIFO36_WEAU2", - "BRAM_FIFO36_WEAU3", - "BRAM_FIFO36_WEBWEL0", - "BRAM_FIFO36_WEBWEL1", - "BRAM_FIFO36_WEBWEL2", - "BRAM_FIFO36_WEBWEL3", - "BRAM_FIFO36_WEBWEL4", - "BRAM_FIFO36_WEBWEL5", - "BRAM_FIFO36_WEBWEL6", - "BRAM_FIFO36_WEBWEL7", - "BRAM_FIFO36_WEBWEU0", - "BRAM_FIFO36_WEBWEU1", - "BRAM_FIFO36_WEBWEU2", - "BRAM_FIFO36_WEBWEU3", - "BRAM_FIFO36_WEBWEU4", - "BRAM_FIFO36_WEBWEU5", - "BRAM_FIFO36_WEBWEU6", - "BRAM_FIFO36_WEBWEU7", - "BRAM_FIFO36_WRCOUNT0", - "BRAM_FIFO36_WRCOUNT1", - "BRAM_FIFO36_WRCOUNT10", - "BRAM_FIFO36_WRCOUNT11", - "BRAM_FIFO36_WRCOUNT12", - "BRAM_FIFO36_WRCOUNT2", - "BRAM_FIFO36_WRCOUNT3", - "BRAM_FIFO36_WRCOUNT4", - "BRAM_FIFO36_WRCOUNT5", - "BRAM_FIFO36_WRCOUNT6", - "BRAM_FIFO36_WRCOUNT7", - "BRAM_FIFO36_WRCOUNT8", - "BRAM_FIFO36_WRCOUNT9", - "BRAM_FIFO36_WRERR", - "BRAM_IMUX0_0", - "BRAM_IMUX0_1", - "BRAM_IMUX0_2", - "BRAM_IMUX0_3", - "BRAM_IMUX0_4", - "BRAM_IMUX0_UTURN_0", - "BRAM_IMUX0_UTURN_1", - "BRAM_IMUX0_UTURN_2", - "BRAM_IMUX0_UTURN_3", - "BRAM_IMUX0_UTURN_4", - "BRAM_IMUX10_0", - "BRAM_IMUX10_1", - "BRAM_IMUX10_2", - "BRAM_IMUX10_3", - "BRAM_IMUX10_4", - "BRAM_IMUX10_UTURN_0", - "BRAM_IMUX10_UTURN_1", - "BRAM_IMUX10_UTURN_2", - "BRAM_IMUX10_UTURN_3", - "BRAM_IMUX10_UTURN_4", - "BRAM_IMUX11_0", - "BRAM_IMUX11_1", - "BRAM_IMUX11_2", - "BRAM_IMUX11_3", - "BRAM_IMUX11_4", - "BRAM_IMUX11_UTURN_0", - "BRAM_IMUX11_UTURN_1", - "BRAM_IMUX11_UTURN_2", - "BRAM_IMUX11_UTURN_3", - "BRAM_IMUX11_UTURN_4", - "BRAM_IMUX12_0", - "BRAM_IMUX12_1", - "BRAM_IMUX12_2", - "BRAM_IMUX12_3", - "BRAM_IMUX12_4", - "BRAM_IMUX12_UTURN_0", - "BRAM_IMUX12_UTURN_1", - "BRAM_IMUX12_UTURN_2", - "BRAM_IMUX12_UTURN_3", - "BRAM_IMUX12_UTURN_4", - "BRAM_IMUX13_0", - "BRAM_IMUX13_1", - "BRAM_IMUX13_2", - "BRAM_IMUX13_3", - "BRAM_IMUX13_4", - "BRAM_IMUX13_UTURN_0", - "BRAM_IMUX13_UTURN_1", - "BRAM_IMUX13_UTURN_2", - "BRAM_IMUX13_UTURN_3", - "BRAM_IMUX13_UTURN_4", - "BRAM_IMUX14_0", - "BRAM_IMUX14_1", - "BRAM_IMUX14_2", - "BRAM_IMUX14_3", - "BRAM_IMUX14_4", - "BRAM_IMUX14_UTURN_0", - "BRAM_IMUX14_UTURN_1", - "BRAM_IMUX14_UTURN_2", - "BRAM_IMUX14_UTURN_3", - "BRAM_IMUX14_UTURN_4", - "BRAM_IMUX15_0", - "BRAM_IMUX15_1", - "BRAM_IMUX15_2", - "BRAM_IMUX15_3", - "BRAM_IMUX15_4", - "BRAM_IMUX15_UTURN_0", - "BRAM_IMUX15_UTURN_1", - "BRAM_IMUX15_UTURN_2", - "BRAM_IMUX15_UTURN_3", - "BRAM_IMUX15_UTURN_4", - "BRAM_IMUX16_0", - "BRAM_IMUX16_1", - "BRAM_IMUX16_2", - "BRAM_IMUX16_3", - "BRAM_IMUX16_4", - "BRAM_IMUX16_UTURN_0", - "BRAM_IMUX16_UTURN_1", - "BRAM_IMUX16_UTURN_2", - "BRAM_IMUX16_UTURN_3", - "BRAM_IMUX16_UTURN_4", - "BRAM_IMUX17_0", - "BRAM_IMUX17_1", - "BRAM_IMUX17_2", - "BRAM_IMUX17_3", - "BRAM_IMUX17_4", - "BRAM_IMUX17_UTURN_0", - "BRAM_IMUX17_UTURN_1", - "BRAM_IMUX17_UTURN_2", - "BRAM_IMUX17_UTURN_3", - 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"BRAM_MONITOR_P_1", - "BRAM_MONITOR_P_2", - "BRAM_MONITOR_P_3", - "BRAM_MONITOR_P_4", - "BRAM_NE2A0_0", - "BRAM_NE2A0_1", - "BRAM_NE2A0_2", - "BRAM_NE2A0_3", - "BRAM_NE2A0_4", - "BRAM_NE2A1_0", - "BRAM_NE2A1_1", - "BRAM_NE2A1_2", - "BRAM_NE2A1_3", - "BRAM_NE2A1_4", - "BRAM_NE2A2_0", - "BRAM_NE2A2_1", - "BRAM_NE2A2_2", - "BRAM_NE2A2_3", - "BRAM_NE2A2_4", - "BRAM_NE2A3_0", - "BRAM_NE2A3_1", - "BRAM_NE2A3_2", - "BRAM_NE2A3_3", - "BRAM_NE2A3_4", - "BRAM_NE4BEG0_0", - "BRAM_NE4BEG0_1", - "BRAM_NE4BEG0_2", - "BRAM_NE4BEG0_3", - "BRAM_NE4BEG0_4", - "BRAM_NE4BEG1_0", - "BRAM_NE4BEG1_1", - "BRAM_NE4BEG1_2", - "BRAM_NE4BEG1_3", - "BRAM_NE4BEG1_4", - "BRAM_NE4BEG2_0", - "BRAM_NE4BEG2_1", - "BRAM_NE4BEG2_2", - "BRAM_NE4BEG2_3", - "BRAM_NE4BEG2_4", - "BRAM_NE4BEG3_0", - "BRAM_NE4BEG3_1", - "BRAM_NE4BEG3_2", - "BRAM_NE4BEG3_3", - "BRAM_NE4BEG3_4", - "BRAM_NE4C0_0", - "BRAM_NE4C0_1", - "BRAM_NE4C0_2", - "BRAM_NE4C0_3", - "BRAM_NE4C0_4", - "BRAM_NE4C1_0", - "BRAM_NE4C1_1", - "BRAM_NE4C1_2", - "BRAM_NE4C1_3", - "BRAM_NE4C1_4", - "BRAM_NE4C2_0", - "BRAM_NE4C2_1", - "BRAM_NE4C2_2", - "BRAM_NE4C2_3", - "BRAM_NE4C2_4", - "BRAM_NE4C3_0", - "BRAM_NE4C3_1", - "BRAM_NE4C3_2", - "BRAM_NE4C3_3", - "BRAM_NE4C3_4", - "BRAM_NW2A0_0", - "BRAM_NW2A0_1", - "BRAM_NW2A0_2", - "BRAM_NW2A0_3", - "BRAM_NW2A0_4", - "BRAM_NW2A1_0", - "BRAM_NW2A1_1", - "BRAM_NW2A1_2", - "BRAM_NW2A1_3", - "BRAM_NW2A1_4", - "BRAM_NW2A2_0", - "BRAM_NW2A2_1", - "BRAM_NW2A2_2", - "BRAM_NW2A2_3", - "BRAM_NW2A2_4", - "BRAM_NW2A3_0", - "BRAM_NW2A3_1", - "BRAM_NW2A3_2", - "BRAM_NW2A3_3", - "BRAM_NW2A3_4", - "BRAM_NW4A0_0", - "BRAM_NW4A0_1", - "BRAM_NW4A0_2", - "BRAM_NW4A0_3", - "BRAM_NW4A0_4", - "BRAM_NW4A1_0", - "BRAM_NW4A1_1", - "BRAM_NW4A1_2", - "BRAM_NW4A1_3", - "BRAM_NW4A1_4", - "BRAM_NW4A2_0", - "BRAM_NW4A2_1", - "BRAM_NW4A2_2", - "BRAM_NW4A2_3", - "BRAM_NW4A2_4", - "BRAM_NW4A3_0", - "BRAM_NW4A3_1", - "BRAM_NW4A3_2", - "BRAM_NW4A3_3", - "BRAM_NW4A3_4", - "BRAM_NW4END0_0", - "BRAM_NW4END0_1", - "BRAM_NW4END0_2", - "BRAM_NW4END0_3", - "BRAM_NW4END0_4", - "BRAM_NW4END1_0", - "BRAM_NW4END1_1", - "BRAM_NW4END1_2", - "BRAM_NW4END1_3", - "BRAM_NW4END1_4", - "BRAM_NW4END2_0", - "BRAM_NW4END2_1", - "BRAM_NW4END2_2", - "BRAM_NW4END2_3", - "BRAM_NW4END2_4", - "BRAM_NW4END3_0", - "BRAM_NW4END3_1", - "BRAM_NW4END3_2", - "BRAM_NW4END3_3", - "BRAM_NW4END3_4", - "BRAM_PMVBRAM_O", - "BRAM_PMVBRAM_ODIV2", - "BRAM_PMVBRAM_ODIV2_1", - "BRAM_PMVBRAM_ODIV4", - "BRAM_PMVBRAM_O_1", - "BRAM_PMVBRAM_O_2", - "BRAM_PMVBRAM_SELECT1", - "BRAM_PMVBRAM_SELECT2", - "BRAM_PMVBRAM_SELECT3", - "BRAM_PMVBRAM_SELECT4", - "BRAM_RAMB18_ADDRARDADDR0", - "BRAM_RAMB18_ADDRARDADDR1", - "BRAM_RAMB18_ADDRARDADDR10", - "BRAM_RAMB18_ADDRARDADDR11", - "BRAM_RAMB18_ADDRARDADDR12", - "BRAM_RAMB18_ADDRARDADDR13", - "BRAM_RAMB18_ADDRARDADDR2", - "BRAM_RAMB18_ADDRARDADDR3", - "BRAM_RAMB18_ADDRARDADDR4", - "BRAM_RAMB18_ADDRARDADDR5", - "BRAM_RAMB18_ADDRARDADDR6", - "BRAM_RAMB18_ADDRARDADDR7", - "BRAM_RAMB18_ADDRARDADDR8", - "BRAM_RAMB18_ADDRARDADDR9", - "BRAM_RAMB18_ADDRATIEHIGH0", - "BRAM_RAMB18_ADDRATIEHIGH1", - "BRAM_RAMB18_ADDRBTIEHIGH0", - "BRAM_RAMB18_ADDRBTIEHIGH1", - "BRAM_RAMB18_ADDRBWRADDR0", - "BRAM_RAMB18_ADDRBWRADDR1", - "BRAM_RAMB18_ADDRBWRADDR10", - "BRAM_RAMB18_ADDRBWRADDR11", - "BRAM_RAMB18_ADDRBWRADDR12", - "BRAM_RAMB18_ADDRBWRADDR13", - "BRAM_RAMB18_ADDRBWRADDR2", - "BRAM_RAMB18_ADDRBWRADDR3", - "BRAM_RAMB18_ADDRBWRADDR4", - "BRAM_RAMB18_ADDRBWRADDR5", - "BRAM_RAMB18_ADDRBWRADDR6", - "BRAM_RAMB18_ADDRBWRADDR7", - "BRAM_RAMB18_ADDRBWRADDR8", - "BRAM_RAMB18_ADDRBWRADDR9", - "BRAM_RAMB18_ALMOSTEMPTY", - "BRAM_RAMB18_ALMOSTFULL", - "BRAM_RAMB18_CLKARDCLK", - "BRAM_RAMB18_CLKBWRCLK", - "BRAM_RAMB18_DIADI0", - "BRAM_RAMB18_DIADI1", - "BRAM_RAMB18_DIADI10", - "BRAM_RAMB18_DIADI11", - "BRAM_RAMB18_DIADI12", - "BRAM_RAMB18_DIADI13", - "BRAM_RAMB18_DIADI14", - "BRAM_RAMB18_DIADI15", - "BRAM_RAMB18_DIADI2", - "BRAM_RAMB18_DIADI3", - "BRAM_RAMB18_DIADI4", - "BRAM_RAMB18_DIADI5", - "BRAM_RAMB18_DIADI6", - "BRAM_RAMB18_DIADI7", - "BRAM_RAMB18_DIADI8", - "BRAM_RAMB18_DIADI9", - "BRAM_RAMB18_DIBDI0", - "BRAM_RAMB18_DIBDI1", - "BRAM_RAMB18_DIBDI10", - "BRAM_RAMB18_DIBDI11", - "BRAM_RAMB18_DIBDI12", - "BRAM_RAMB18_DIBDI13", - "BRAM_RAMB18_DIBDI14", - "BRAM_RAMB18_DIBDI15", - "BRAM_RAMB18_DIBDI2", - "BRAM_RAMB18_DIBDI3", - "BRAM_RAMB18_DIBDI4", - "BRAM_RAMB18_DIBDI5", - "BRAM_RAMB18_DIBDI6", - "BRAM_RAMB18_DIBDI7", - "BRAM_RAMB18_DIBDI8", - "BRAM_RAMB18_DIBDI9", - "BRAM_RAMB18_DIPADIP0", - "BRAM_RAMB18_DIPADIP1", - "BRAM_RAMB18_DIPBDIP0", - "BRAM_RAMB18_DIPBDIP1", - "BRAM_RAMB18_DOADO0", - "BRAM_RAMB18_DOADO1", - "BRAM_RAMB18_DOADO10", - "BRAM_RAMB18_DOADO11", - "BRAM_RAMB18_DOADO12", - "BRAM_RAMB18_DOADO13", - "BRAM_RAMB18_DOADO14", - "BRAM_RAMB18_DOADO15", - "BRAM_RAMB18_DOADO2", - "BRAM_RAMB18_DOADO3", - "BRAM_RAMB18_DOADO4", - "BRAM_RAMB18_DOADO5", - "BRAM_RAMB18_DOADO6", - "BRAM_RAMB18_DOADO7", - "BRAM_RAMB18_DOADO8", - "BRAM_RAMB18_DOADO9", - "BRAM_RAMB18_DOBDO0", - "BRAM_RAMB18_DOBDO1", - "BRAM_RAMB18_DOBDO10", - "BRAM_RAMB18_DOBDO11", - "BRAM_RAMB18_DOBDO12", - "BRAM_RAMB18_DOBDO13", - "BRAM_RAMB18_DOBDO14", - "BRAM_RAMB18_DOBDO15", - "BRAM_RAMB18_DOBDO2", - "BRAM_RAMB18_DOBDO3", - "BRAM_RAMB18_DOBDO4", - "BRAM_RAMB18_DOBDO5", - "BRAM_RAMB18_DOBDO6", - "BRAM_RAMB18_DOBDO7", - "BRAM_RAMB18_DOBDO8", - "BRAM_RAMB18_DOBDO9", - "BRAM_RAMB18_DOPADOP0", - "BRAM_RAMB18_DOPADOP1", - "BRAM_RAMB18_DOPBDOP0", - "BRAM_RAMB18_DOPBDOP1", - "BRAM_RAMB18_EMPTY", - "BRAM_RAMB18_ENARDEN", - "BRAM_RAMB18_ENBWREN", - "BRAM_RAMB18_FULL", - "BRAM_RAMB18_RDCOUNT0", - "BRAM_RAMB18_RDCOUNT1", - "BRAM_RAMB18_RDCOUNT10", - "BRAM_RAMB18_RDCOUNT11", - "BRAM_RAMB18_RDCOUNT2", - "BRAM_RAMB18_RDCOUNT3", - "BRAM_RAMB18_RDCOUNT4", - "BRAM_RAMB18_RDCOUNT5", - "BRAM_RAMB18_RDCOUNT6", - "BRAM_RAMB18_RDCOUNT7", - "BRAM_RAMB18_RDCOUNT8", - "BRAM_RAMB18_RDCOUNT9", - "BRAM_RAMB18_RDERR", - "BRAM_RAMB18_REGCEAREGCE", - "BRAM_RAMB18_REGCEB", - "BRAM_RAMB18_REGCLKARDRCLK", - "BRAM_RAMB18_REGCLKB", - "BRAM_RAMB18_RSTRAMARSTRAM", - "BRAM_RAMB18_RSTRAMB", - "BRAM_RAMB18_RSTREGARSTREG", - "BRAM_RAMB18_RSTREGB", - "BRAM_RAMB18_WEA0", - "BRAM_RAMB18_WEA1", - "BRAM_RAMB18_WEA2", - "BRAM_RAMB18_WEA3", - "BRAM_RAMB18_WEBWE0", - "BRAM_RAMB18_WEBWE1", - "BRAM_RAMB18_WEBWE2", - "BRAM_RAMB18_WEBWE3", - "BRAM_RAMB18_WEBWE4", - "BRAM_RAMB18_WEBWE5", - "BRAM_RAMB18_WEBWE6", - "BRAM_RAMB18_WEBWE7", - "BRAM_RAMB18_WRCOUNT0", - "BRAM_RAMB18_WRCOUNT1", - "BRAM_RAMB18_WRCOUNT10", - "BRAM_RAMB18_WRCOUNT11", - "BRAM_RAMB18_WRCOUNT2", - "BRAM_RAMB18_WRCOUNT3", - "BRAM_RAMB18_WRCOUNT4", - "BRAM_RAMB18_WRCOUNT5", - "BRAM_RAMB18_WRCOUNT6", - "BRAM_RAMB18_WRCOUNT7", - "BRAM_RAMB18_WRCOUNT8", - "BRAM_RAMB18_WRCOUNT9", - "BRAM_RAMB18_WRERR", - "BRAM_R_IMUX_ADDRARDADDRL0", - "BRAM_R_IMUX_ADDRARDADDRL1", - "BRAM_R_IMUX_ADDRARDADDRL10", - "BRAM_R_IMUX_ADDRARDADDRL11", - "BRAM_R_IMUX_ADDRARDADDRL12", - "BRAM_R_IMUX_ADDRARDADDRL13", - "BRAM_R_IMUX_ADDRARDADDRL14", - "BRAM_R_IMUX_ADDRARDADDRL2", - "BRAM_R_IMUX_ADDRARDADDRL3", - "BRAM_R_IMUX_ADDRARDADDRL4", - "BRAM_R_IMUX_ADDRARDADDRL5", - "BRAM_R_IMUX_ADDRARDADDRL6", - "BRAM_R_IMUX_ADDRARDADDRL7", - "BRAM_R_IMUX_ADDRARDADDRL8", - "BRAM_R_IMUX_ADDRARDADDRL9", - "BRAM_R_IMUX_ADDRARDADDRU0", - "BRAM_R_IMUX_ADDRARDADDRU1", - "BRAM_R_IMUX_ADDRARDADDRU10", - "BRAM_R_IMUX_ADDRARDADDRU11", - "BRAM_R_IMUX_ADDRARDADDRU12", - "BRAM_R_IMUX_ADDRARDADDRU13", - "BRAM_R_IMUX_ADDRARDADDRU14", - "BRAM_R_IMUX_ADDRARDADDRU2", - "BRAM_R_IMUX_ADDRARDADDRU3", - "BRAM_R_IMUX_ADDRARDADDRU4", - "BRAM_R_IMUX_ADDRARDADDRU5", - "BRAM_R_IMUX_ADDRARDADDRU6", - "BRAM_R_IMUX_ADDRARDADDRU7", - "BRAM_R_IMUX_ADDRARDADDRU8", - "BRAM_R_IMUX_ADDRARDADDRU9", - "BRAM_R_IMUX_ADDRBWRADDRL0", - "BRAM_R_IMUX_ADDRBWRADDRL1", - "BRAM_R_IMUX_ADDRBWRADDRL10", - "BRAM_R_IMUX_ADDRBWRADDRL11", - "BRAM_R_IMUX_ADDRBWRADDRL12", - "BRAM_R_IMUX_ADDRBWRADDRL13", - "BRAM_R_IMUX_ADDRBWRADDRL14", - "BRAM_R_IMUX_ADDRBWRADDRL2", - "BRAM_R_IMUX_ADDRBWRADDRL3", - "BRAM_R_IMUX_ADDRBWRADDRL4", - "BRAM_R_IMUX_ADDRBWRADDRL5", - "BRAM_R_IMUX_ADDRBWRADDRL6", - "BRAM_R_IMUX_ADDRBWRADDRL7", - "BRAM_R_IMUX_ADDRBWRADDRL8", - "BRAM_R_IMUX_ADDRBWRADDRL9", - "BRAM_R_IMUX_ADDRBWRADDRU0", - "BRAM_R_IMUX_ADDRBWRADDRU1", - "BRAM_R_IMUX_ADDRBWRADDRU10", - "BRAM_R_IMUX_ADDRBWRADDRU11", - "BRAM_R_IMUX_ADDRBWRADDRU12", - "BRAM_R_IMUX_ADDRBWRADDRU13", - "BRAM_R_IMUX_ADDRBWRADDRU14", - "BRAM_R_IMUX_ADDRBWRADDRU2", - "BRAM_R_IMUX_ADDRBWRADDRU3", - "BRAM_R_IMUX_ADDRBWRADDRU4", - "BRAM_R_IMUX_ADDRBWRADDRU5", - "BRAM_R_IMUX_ADDRBWRADDRU6", - "BRAM_R_IMUX_ADDRBWRADDRU7", - "BRAM_R_IMUX_ADDRBWRADDRU8", - "BRAM_R_IMUX_ADDRBWRADDRU9", - "BRAM_SE2A0_0", - "BRAM_SE2A0_1", - "BRAM_SE2A0_2", - "BRAM_SE2A0_3", - "BRAM_SE2A0_4", - "BRAM_SE2A1_0", - "BRAM_SE2A1_1", - "BRAM_SE2A1_2", - "BRAM_SE2A1_3", - "BRAM_SE2A1_4", - "BRAM_SE2A2_0", - "BRAM_SE2A2_1", - "BRAM_SE2A2_2", - "BRAM_SE2A2_3", - "BRAM_SE2A2_4", - "BRAM_SE2A3_0", - "BRAM_SE2A3_1", - "BRAM_SE2A3_2", - "BRAM_SE2A3_3", - "BRAM_SE2A3_4", - "BRAM_SE4BEG0_0", - "BRAM_SE4BEG0_1", - "BRAM_SE4BEG0_2", - "BRAM_SE4BEG0_3", - "BRAM_SE4BEG0_4", - "BRAM_SE4BEG1_0", - "BRAM_SE4BEG1_1", - "BRAM_SE4BEG1_2", - "BRAM_SE4BEG1_3", - "BRAM_SE4BEG1_4", - "BRAM_SE4BEG2_0", - "BRAM_SE4BEG2_1", - "BRAM_SE4BEG2_2", - "BRAM_SE4BEG2_3", - "BRAM_SE4BEG2_4", - "BRAM_SE4BEG3_0", - "BRAM_SE4BEG3_1", - "BRAM_SE4BEG3_2", - "BRAM_SE4BEG3_3", - "BRAM_SE4BEG3_4", - "BRAM_SE4C0_0", - "BRAM_SE4C0_1", - "BRAM_SE4C0_2", - "BRAM_SE4C0_3", - "BRAM_SE4C0_4", - "BRAM_SE4C1_0", - "BRAM_SE4C1_1", - "BRAM_SE4C1_2", - "BRAM_SE4C1_3", - "BRAM_SE4C1_4", - "BRAM_SE4C2_0", - "BRAM_SE4C2_1", - "BRAM_SE4C2_2", - "BRAM_SE4C2_3", - "BRAM_SE4C2_4", - "BRAM_SE4C3_0", - "BRAM_SE4C3_1", - "BRAM_SE4C3_2", - "BRAM_SE4C3_3", - "BRAM_SE4C3_4", - "BRAM_SW2A0_0", - "BRAM_SW2A0_1", - "BRAM_SW2A0_2", - "BRAM_SW2A0_3", - "BRAM_SW2A0_4", - "BRAM_SW2A1_0", - "BRAM_SW2A1_1", - "BRAM_SW2A1_2", - "BRAM_SW2A1_3", - "BRAM_SW2A1_4", - "BRAM_SW2A2_0", - "BRAM_SW2A2_1", - "BRAM_SW2A2_2", - "BRAM_SW2A2_3", - "BRAM_SW2A2_4", - "BRAM_SW2A3_0", - "BRAM_SW2A3_1", - "BRAM_SW2A3_2", - "BRAM_SW2A3_3", - "BRAM_SW2A3_4", - "BRAM_SW4A0_0", - "BRAM_SW4A0_1", - "BRAM_SW4A0_2", - "BRAM_SW4A0_3", - "BRAM_SW4A0_4", - "BRAM_SW4A1_0", - "BRAM_SW4A1_1", - "BRAM_SW4A1_2", - "BRAM_SW4A1_3", - "BRAM_SW4A1_4", - "BRAM_SW4A2_0", - "BRAM_SW4A2_1", - "BRAM_SW4A2_2", - "BRAM_SW4A2_3", - "BRAM_SW4A2_4", - "BRAM_SW4A3_0", - "BRAM_SW4A3_1", - "BRAM_SW4A3_2", - "BRAM_SW4A3_3", - "BRAM_SW4A3_4", - "BRAM_SW4END0_0", - "BRAM_SW4END0_1", - "BRAM_SW4END0_2", - "BRAM_SW4END0_3", - "BRAM_SW4END0_4", - "BRAM_SW4END1_0", - "BRAM_SW4END1_1", - "BRAM_SW4END1_2", - "BRAM_SW4END1_3", - "BRAM_SW4END1_4", - "BRAM_SW4END2_0", - "BRAM_SW4END2_1", - "BRAM_SW4END2_2", - "BRAM_SW4END2_3", - "BRAM_SW4END2_4", - "BRAM_SW4END3_0", - "BRAM_SW4END3_1", - "BRAM_SW4END3_2", - "BRAM_SW4END3_3", - "BRAM_SW4END3_4", - "BRAM_UTURN_ADDRARDADDRL0", - "BRAM_UTURN_ADDRARDADDRL1", - "BRAM_UTURN_ADDRARDADDRL10", - "BRAM_UTURN_ADDRARDADDRL11", - "BRAM_UTURN_ADDRARDADDRL12", - "BRAM_UTURN_ADDRARDADDRL13", - "BRAM_UTURN_ADDRARDADDRL14", - "BRAM_UTURN_ADDRARDADDRL15", - "BRAM_UTURN_ADDRARDADDRL2", - "BRAM_UTURN_ADDRARDADDRL3", - "BRAM_UTURN_ADDRARDADDRL4", - "BRAM_UTURN_ADDRARDADDRL5", - "BRAM_UTURN_ADDRARDADDRL6", - "BRAM_UTURN_ADDRARDADDRL7", - "BRAM_UTURN_ADDRARDADDRL8", - "BRAM_UTURN_ADDRARDADDRL9", - "BRAM_UTURN_ADDRARDADDRU0", - "BRAM_UTURN_ADDRARDADDRU1", - "BRAM_UTURN_ADDRARDADDRU10", - "BRAM_UTURN_ADDRARDADDRU11", - "BRAM_UTURN_ADDRARDADDRU12", - "BRAM_UTURN_ADDRARDADDRU13", - "BRAM_UTURN_ADDRARDADDRU14", - "BRAM_UTURN_ADDRARDADDRU2", - "BRAM_UTURN_ADDRARDADDRU3", - "BRAM_UTURN_ADDRARDADDRU4", - "BRAM_UTURN_ADDRARDADDRU5", - "BRAM_UTURN_ADDRARDADDRU6", - "BRAM_UTURN_ADDRARDADDRU7", - "BRAM_UTURN_ADDRARDADDRU8", - "BRAM_UTURN_ADDRARDADDRU9", - "BRAM_UTURN_ADDRBWRADDRL0", - "BRAM_UTURN_ADDRBWRADDRL1", - "BRAM_UTURN_ADDRBWRADDRL10", - "BRAM_UTURN_ADDRBWRADDRL11", - "BRAM_UTURN_ADDRBWRADDRL12", - "BRAM_UTURN_ADDRBWRADDRL13", - "BRAM_UTURN_ADDRBWRADDRL14", - "BRAM_UTURN_ADDRBWRADDRL15", - "BRAM_UTURN_ADDRBWRADDRL2", - "BRAM_UTURN_ADDRBWRADDRL3", - "BRAM_UTURN_ADDRBWRADDRL4", - "BRAM_UTURN_ADDRBWRADDRL5", - "BRAM_UTURN_ADDRBWRADDRL6", - "BRAM_UTURN_ADDRBWRADDRL7", - "BRAM_UTURN_ADDRBWRADDRL8", - "BRAM_UTURN_ADDRBWRADDRL9", - "BRAM_UTURN_ADDRBWRADDRU0", - "BRAM_UTURN_ADDRBWRADDRU1", - "BRAM_UTURN_ADDRBWRADDRU10", - "BRAM_UTURN_ADDRBWRADDRU11", - "BRAM_UTURN_ADDRBWRADDRU12", - "BRAM_UTURN_ADDRBWRADDRU13", - "BRAM_UTURN_ADDRBWRADDRU14", - "BRAM_UTURN_ADDRBWRADDRU2", - "BRAM_UTURN_ADDRBWRADDRU3", - "BRAM_UTURN_ADDRBWRADDRU4", - "BRAM_UTURN_ADDRBWRADDRU5", - "BRAM_UTURN_ADDRBWRADDRU6", - "BRAM_UTURN_ADDRBWRADDRU7", - "BRAM_UTURN_ADDRBWRADDRU8", - "BRAM_UTURN_ADDRBWRADDRU9", - "BRAM_WL1END0_0", - "BRAM_WL1END0_1", - "BRAM_WL1END0_2", - "BRAM_WL1END0_3", - "BRAM_WL1END0_4", - "BRAM_WL1END1_0", - "BRAM_WL1END1_1", - "BRAM_WL1END1_2", - "BRAM_WL1END1_3", - "BRAM_WL1END1_4", - "BRAM_WL1END2_0", - "BRAM_WL1END2_1", - "BRAM_WL1END2_2", - "BRAM_WL1END2_3", - "BRAM_WL1END2_4", - "BRAM_WL1END3_0", - "BRAM_WL1END3_1", - "BRAM_WL1END3_2", - "BRAM_WL1END3_3", - "BRAM_WL1END3_4", - "BRAM_WR1END0_0", - "BRAM_WR1END0_1", - "BRAM_WR1END0_2", - "BRAM_WR1END0_3", - "BRAM_WR1END0_4", - "BRAM_WR1END1_0", - "BRAM_WR1END1_1", - "BRAM_WR1END1_2", - "BRAM_WR1END1_3", - "BRAM_WR1END1_4", - "BRAM_WR1END2_0", - "BRAM_WR1END2_1", - "BRAM_WR1END2_2", - "BRAM_WR1END2_3", - "BRAM_WR1END2_4", - "BRAM_WR1END3_0", - "BRAM_WR1END3_1", - "BRAM_WR1END3_2", - "BRAM_WR1END3_3", - "BRAM_WR1END3_4", - "BRAM_WW2A0_0", - "BRAM_WW2A0_1", - "BRAM_WW2A0_2", - "BRAM_WW2A0_3", - "BRAM_WW2A0_4", - "BRAM_WW2A1_0", - "BRAM_WW2A1_1", - "BRAM_WW2A1_2", - "BRAM_WW2A1_3", - "BRAM_WW2A1_4", - "BRAM_WW2A2_0", - "BRAM_WW2A2_1", - "BRAM_WW2A2_2", - "BRAM_WW2A2_3", - "BRAM_WW2A2_4", - "BRAM_WW2A3_0", - "BRAM_WW2A3_1", - "BRAM_WW2A3_2", - "BRAM_WW2A3_3", - "BRAM_WW2A3_4", - "BRAM_WW2END0_0", - "BRAM_WW2END0_1", - "BRAM_WW2END0_2", - "BRAM_WW2END0_3", - "BRAM_WW2END0_4", - "BRAM_WW2END1_0", - "BRAM_WW2END1_1", - "BRAM_WW2END1_2", - "BRAM_WW2END1_3", - "BRAM_WW2END1_4", - "BRAM_WW2END2_0", - "BRAM_WW2END2_1", - "BRAM_WW2END2_2", - "BRAM_WW2END2_3", - "BRAM_WW2END2_4", - "BRAM_WW2END3_0", - "BRAM_WW2END3_1", - "BRAM_WW2END3_2", - "BRAM_WW2END3_3", - "BRAM_WW2END3_4", - "BRAM_WW4A0_0", - "BRAM_WW4A0_1", - "BRAM_WW4A0_2", - "BRAM_WW4A0_3", - "BRAM_WW4A0_4", - "BRAM_WW4A1_0", - "BRAM_WW4A1_1", - "BRAM_WW4A1_2", - "BRAM_WW4A1_3", - "BRAM_WW4A1_4", - "BRAM_WW4A2_0", - "BRAM_WW4A2_1", - "BRAM_WW4A2_2", - "BRAM_WW4A2_3", - "BRAM_WW4A2_4", - "BRAM_WW4A3_0", - "BRAM_WW4A3_1", - "BRAM_WW4A3_2", - "BRAM_WW4A3_3", - "BRAM_WW4A3_4", - "BRAM_WW4B0_0", - "BRAM_WW4B0_1", - "BRAM_WW4B0_2", - "BRAM_WW4B0_3", - "BRAM_WW4B0_4", - "BRAM_WW4B1_0", - "BRAM_WW4B1_1", - "BRAM_WW4B1_2", - "BRAM_WW4B1_3", - "BRAM_WW4B1_4", - "BRAM_WW4B2_0", - "BRAM_WW4B2_1", - "BRAM_WW4B2_2", - "BRAM_WW4B2_3", - "BRAM_WW4B2_4", - "BRAM_WW4B3_0", - "BRAM_WW4B3_1", - "BRAM_WW4B3_2", - "BRAM_WW4B3_3", - "BRAM_WW4B3_4", - "BRAM_WW4C0_0", - "BRAM_WW4C0_1", - "BRAM_WW4C0_2", - "BRAM_WW4C0_3", - "BRAM_WW4C0_4", - "BRAM_WW4C1_0", - "BRAM_WW4C1_1", - "BRAM_WW4C1_2", - "BRAM_WW4C1_3", - "BRAM_WW4C1_4", - "BRAM_WW4C2_0", - "BRAM_WW4C2_1", - "BRAM_WW4C2_2", - "BRAM_WW4C2_3", - "BRAM_WW4C2_4", - "BRAM_WW4C3_0", - "BRAM_WW4C3_1", - "BRAM_WW4C3_2", - "BRAM_WW4C3_3", - "BRAM_WW4C3_4", - "BRAM_WW4END0_0", - "BRAM_WW4END0_1", - "BRAM_WW4END0_2", - "BRAM_WW4END0_3", - "BRAM_WW4END0_4", - "BRAM_WW4END1_0", - "BRAM_WW4END1_1", - "BRAM_WW4END1_2", - "BRAM_WW4END1_3", - "BRAM_WW4END1_4", - "BRAM_WW4END2_0", - "BRAM_WW4END2_1", - "BRAM_WW4END2_2", - "BRAM_WW4END2_3", - "BRAM_WW4END2_4", - "BRAM_WW4END3_0", - "BRAM_WW4END3_1", - "BRAM_WW4END3_2", - "BRAM_WW4END3_3", - "BRAM_WW4END3_4" - ] + "wires": { + "BRAM_ADDRARDADDRL0": null, + "BRAM_ADDRARDADDRL1": null, + "BRAM_ADDRARDADDRL10": null, + "BRAM_ADDRARDADDRL11": null, + "BRAM_ADDRARDADDRL12": null, + "BRAM_ADDRARDADDRL13": null, + "BRAM_ADDRARDADDRL14": null, + "BRAM_ADDRARDADDRL2": null, + "BRAM_ADDRARDADDRL3": null, + "BRAM_ADDRARDADDRL4": null, + "BRAM_ADDRARDADDRL5": null, + "BRAM_ADDRARDADDRL6": null, + "BRAM_ADDRARDADDRL7": null, + "BRAM_ADDRARDADDRL8": null, + "BRAM_ADDRARDADDRL9": null, + "BRAM_ADDRARDADDRU0": null, + "BRAM_ADDRARDADDRU1": null, + "BRAM_ADDRARDADDRU10": null, + "BRAM_ADDRARDADDRU11": null, + "BRAM_ADDRARDADDRU12": null, + "BRAM_ADDRARDADDRU13": null, + "BRAM_ADDRARDADDRU14": null, + "BRAM_ADDRARDADDRU2": null, + "BRAM_ADDRARDADDRU3": null, + "BRAM_ADDRARDADDRU4": null, + "BRAM_ADDRARDADDRU5": null, + "BRAM_ADDRARDADDRU6": null, + "BRAM_ADDRARDADDRU7": null, + "BRAM_ADDRARDADDRU8": null, + "BRAM_ADDRARDADDRU9": null, + "BRAM_ADDRBWRADDRL0": null, + "BRAM_ADDRBWRADDRL1": null, + "BRAM_ADDRBWRADDRL10": null, + "BRAM_ADDRBWRADDRL11": null, + "BRAM_ADDRBWRADDRL12": null, + "BRAM_ADDRBWRADDRL13": null, + "BRAM_ADDRBWRADDRL14": null, + "BRAM_ADDRBWRADDRL2": null, + "BRAM_ADDRBWRADDRL3": null, + "BRAM_ADDRBWRADDRL4": null, + "BRAM_ADDRBWRADDRL5": null, + "BRAM_ADDRBWRADDRL6": null, + "BRAM_ADDRBWRADDRL7": null, + "BRAM_ADDRBWRADDRL8": null, + "BRAM_ADDRBWRADDRL9": null, + "BRAM_ADDRBWRADDRU0": null, + "BRAM_ADDRBWRADDRU1": null, + "BRAM_ADDRBWRADDRU10": null, + "BRAM_ADDRBWRADDRU11": null, + "BRAM_ADDRBWRADDRU12": null, + "BRAM_ADDRBWRADDRU13": null, + "BRAM_ADDRBWRADDRU14": null, + "BRAM_ADDRBWRADDRU2": null, + "BRAM_ADDRBWRADDRU3": null, + "BRAM_ADDRBWRADDRU4": null, + "BRAM_ADDRBWRADDRU5": null, + "BRAM_ADDRBWRADDRU6": null, + "BRAM_ADDRBWRADDRU7": null, + "BRAM_ADDRBWRADDRU8": null, + "BRAM_ADDRBWRADDRU9": null, + "BRAM_BLOCK_OUTS_L_B0_0": null, + "BRAM_BLOCK_OUTS_L_B0_1": null, + "BRAM_BLOCK_OUTS_L_B0_2": null, + "BRAM_BLOCK_OUTS_L_B0_3": null, + "BRAM_BLOCK_OUTS_L_B0_4": null, + "BRAM_BLOCK_OUTS_L_B1_0": null, + "BRAM_BLOCK_OUTS_L_B1_1": null, + "BRAM_BLOCK_OUTS_L_B1_2": null, + "BRAM_BLOCK_OUTS_L_B1_3": null, + "BRAM_BLOCK_OUTS_L_B1_4": null, + "BRAM_BLOCK_OUTS_L_B2_0": null, + "BRAM_BLOCK_OUTS_L_B2_1": null, + "BRAM_BLOCK_OUTS_L_B2_2": null, + "BRAM_BLOCK_OUTS_L_B2_3": null, + "BRAM_BLOCK_OUTS_L_B2_4": null, + "BRAM_BLOCK_OUTS_L_B3_0": null, + "BRAM_BLOCK_OUTS_L_B3_1": null, + "BRAM_BLOCK_OUTS_L_B3_2": null, + "BRAM_BLOCK_OUTS_L_B3_3": null, + "BRAM_BLOCK_OUTS_L_B3_4": null, + "BRAM_BYP0_0": null, + "BRAM_BYP0_1": null, + "BRAM_BYP0_2": null, + "BRAM_BYP0_3": null, + "BRAM_BYP0_4": null, + "BRAM_BYP1_0": null, + "BRAM_BYP1_1": null, + "BRAM_BYP1_2": null, + "BRAM_BYP1_3": null, + "BRAM_BYP1_4": null, + "BRAM_BYP2_0": null, + "BRAM_BYP2_1": null, + "BRAM_BYP2_2": null, + "BRAM_BYP2_3": null, + "BRAM_BYP2_4": null, + "BRAM_BYP3_0": null, + "BRAM_BYP3_1": null, + "BRAM_BYP3_2": null, + "BRAM_BYP3_3": null, + "BRAM_BYP3_4": null, + "BRAM_BYP4_0": null, + "BRAM_BYP4_1": null, + "BRAM_BYP4_2": null, + "BRAM_BYP4_3": null, + "BRAM_BYP4_4": null, + "BRAM_BYP5_0": null, + "BRAM_BYP5_1": null, + "BRAM_BYP5_2": null, + "BRAM_BYP5_3": null, + "BRAM_BYP5_4": null, + "BRAM_BYP6_0": null, + "BRAM_BYP6_1": null, + "BRAM_BYP6_2": null, + "BRAM_BYP6_3": null, + "BRAM_BYP6_4": null, + "BRAM_BYP7_0": null, + "BRAM_BYP7_1": null, + "BRAM_BYP7_2": null, + "BRAM_BYP7_3": null, + "BRAM_BYP7_4": null, + "BRAM_CASCINBOT_ADDRARDADDRU0": null, + "BRAM_CASCINBOT_ADDRARDADDRU1": null, + "BRAM_CASCINBOT_ADDRARDADDRU10": null, + "BRAM_CASCINBOT_ADDRARDADDRU11": null, + "BRAM_CASCINBOT_ADDRARDADDRU12": null, + "BRAM_CASCINBOT_ADDRARDADDRU13": null, + "BRAM_CASCINBOT_ADDRARDADDRU14": null, + "BRAM_CASCINBOT_ADDRARDADDRU2": null, + "BRAM_CASCINBOT_ADDRARDADDRU3": null, + "BRAM_CASCINBOT_ADDRARDADDRU4": null, + "BRAM_CASCINBOT_ADDRARDADDRU5": null, + "BRAM_CASCINBOT_ADDRARDADDRU6": null, + "BRAM_CASCINBOT_ADDRARDADDRU7": null, + "BRAM_CASCINBOT_ADDRARDADDRU8": null, + "BRAM_CASCINBOT_ADDRARDADDRU9": null, + "BRAM_CASCINBOT_ADDRBWRADDRU0": null, + "BRAM_CASCINBOT_ADDRBWRADDRU1": null, + "BRAM_CASCINBOT_ADDRBWRADDRU10": null, + "BRAM_CASCINBOT_ADDRBWRADDRU11": null, + "BRAM_CASCINBOT_ADDRBWRADDRU12": null, + "BRAM_CASCINBOT_ADDRBWRADDRU13": null, + "BRAM_CASCINBOT_ADDRBWRADDRU14": null, + "BRAM_CASCINBOT_ADDRBWRADDRU2": null, + "BRAM_CASCINBOT_ADDRBWRADDRU3": null, + "BRAM_CASCINBOT_ADDRBWRADDRU4": null, + "BRAM_CASCINBOT_ADDRBWRADDRU5": null, + "BRAM_CASCINBOT_ADDRBWRADDRU6": null, + "BRAM_CASCINBOT_ADDRBWRADDRU7": null, + "BRAM_CASCINBOT_ADDRBWRADDRU8": null, + "BRAM_CASCINBOT_ADDRBWRADDRU9": null, + "BRAM_CASCINTOP_ADDRARDADDRU0": null, + "BRAM_CASCINTOP_ADDRARDADDRU1": null, + "BRAM_CASCINTOP_ADDRARDADDRU10": null, + "BRAM_CASCINTOP_ADDRARDADDRU11": null, + "BRAM_CASCINTOP_ADDRARDADDRU12": null, + "BRAM_CASCINTOP_ADDRARDADDRU13": null, + "BRAM_CASCINTOP_ADDRARDADDRU14": null, + "BRAM_CASCINTOP_ADDRARDADDRU2": null, + "BRAM_CASCINTOP_ADDRARDADDRU3": null, + "BRAM_CASCINTOP_ADDRARDADDRU4": null, + "BRAM_CASCINTOP_ADDRARDADDRU5": null, + "BRAM_CASCINTOP_ADDRARDADDRU6": null, + "BRAM_CASCINTOP_ADDRARDADDRU7": null, + "BRAM_CASCINTOP_ADDRARDADDRU8": null, + "BRAM_CASCINTOP_ADDRARDADDRU9": null, + "BRAM_CASCINTOP_ADDRBWRADDRU0": null, + "BRAM_CASCINTOP_ADDRBWRADDRU1": null, + "BRAM_CASCINTOP_ADDRBWRADDRU10": null, + "BRAM_CASCINTOP_ADDRBWRADDRU11": null, + "BRAM_CASCINTOP_ADDRBWRADDRU12": null, + "BRAM_CASCINTOP_ADDRBWRADDRU13": null, + "BRAM_CASCINTOP_ADDRBWRADDRU14": null, + "BRAM_CASCINTOP_ADDRBWRADDRU2": null, + "BRAM_CASCINTOP_ADDRBWRADDRU3": null, + "BRAM_CASCINTOP_ADDRBWRADDRU4": null, + "BRAM_CASCINTOP_ADDRBWRADDRU5": null, + "BRAM_CASCINTOP_ADDRBWRADDRU6": null, + "BRAM_CASCINTOP_ADDRBWRADDRU7": null, + "BRAM_CASCINTOP_ADDRBWRADDRU8": null, + "BRAM_CASCINTOP_ADDRBWRADDRU9": null, + "BRAM_CASCOUT_ADDRARDADDRU0": null, + "BRAM_CASCOUT_ADDRARDADDRU1": null, + "BRAM_CASCOUT_ADDRARDADDRU10": null, + "BRAM_CASCOUT_ADDRARDADDRU11": null, + "BRAM_CASCOUT_ADDRARDADDRU12": null, + "BRAM_CASCOUT_ADDRARDADDRU13": null, + "BRAM_CASCOUT_ADDRARDADDRU14": null, + "BRAM_CASCOUT_ADDRARDADDRU2": null, + "BRAM_CASCOUT_ADDRARDADDRU3": null, + "BRAM_CASCOUT_ADDRARDADDRU4": null, + "BRAM_CASCOUT_ADDRARDADDRU5": null, + "BRAM_CASCOUT_ADDRARDADDRU6": null, + "BRAM_CASCOUT_ADDRARDADDRU7": null, + "BRAM_CASCOUT_ADDRARDADDRU8": null, + "BRAM_CASCOUT_ADDRARDADDRU9": null, + "BRAM_CASCOUT_ADDRBWRADDRU0": null, + "BRAM_CASCOUT_ADDRBWRADDRU1": null, + "BRAM_CASCOUT_ADDRBWRADDRU10": null, + "BRAM_CASCOUT_ADDRBWRADDRU11": null, + "BRAM_CASCOUT_ADDRBWRADDRU12": null, + "BRAM_CASCOUT_ADDRBWRADDRU13": null, + "BRAM_CASCOUT_ADDRBWRADDRU14": null, + "BRAM_CASCOUT_ADDRBWRADDRU2": null, + "BRAM_CASCOUT_ADDRBWRADDRU3": null, + "BRAM_CASCOUT_ADDRBWRADDRU4": null, + "BRAM_CASCOUT_ADDRBWRADDRU5": null, + "BRAM_CASCOUT_ADDRBWRADDRU6": null, + "BRAM_CASCOUT_ADDRBWRADDRU7": null, + "BRAM_CASCOUT_ADDRBWRADDRU8": null, + "BRAM_CASCOUT_ADDRBWRADDRU9": null, + "BRAM_CLK0_0": null, + "BRAM_CLK0_1": null, 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"BRAM_WW4C2_4": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4C3_0": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4C3_1": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4C3_2": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4C3_3": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4C3_4": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END0_0": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END0_1": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END0_2": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END0_3": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END0_4": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END1_0": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END1_1": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END1_2": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END1_3": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END1_4": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END2_0": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END2_1": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END2_2": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END2_3": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END2_4": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END3_0": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END3_1": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END3_2": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END3_3": { + "cap": "55.660", + "res": "268.920" + }, + "BRAM_WW4END3_4": { + "cap": "55.660", + "res": "268.920" + } + } } diff --git a/zynq7/tile_type_BRKH_BRAM.json b/zynq7/tile_type_BRKH_BRAM.json index 0314f62..be8ea32 100644 --- a/zynq7/tile_type_BRKH_BRAM.json +++ b/zynq7/tile_type_BRKH_BRAM.json @@ -2,70 +2,70 @@ "pips": {}, "sites": [], "tile_type": "BRKH_BRAM", - "wires": [ - "BRKH_BRAM_CASCADEA_L", - "BRKH_BRAM_CASCADEA_R", - "BRKH_BRAM_CASCADEB_L", - "BRKH_BRAM_CASCADEB_R", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" - ] + "wires": { + "BRKH_BRAM_CASCADEA_L": null, + "BRKH_BRAM_CASCADEA_R": null, + "BRKH_BRAM_CASCADEB_L": null, + "BRKH_BRAM_CASCADEB_R": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9": null + } } diff --git a/zynq7/tile_type_BRKH_CLB.json b/zynq7/tile_type_BRKH_CLB.json index 272811f..a128285 100644 --- a/zynq7/tile_type_BRKH_CLB.json +++ b/zynq7/tile_type_BRKH_CLB.json @@ -2,10 +2,22 @@ "pips": {}, "sites": [], "tile_type": "BRKH_CLB", - "wires": [ - "BRKH_CLB_COUT0_L", - "BRKH_CLB_COUT0_R", - "BRKH_CLB_COUT1_L", - "BRKH_CLB_COUT1_R" - ] + "wires": { + "BRKH_CLB_COUT0_L": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_CLB_COUT0_R": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_CLB_COUT1_L": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_CLB_COUT1_R": { + "cap": "1.000", + "res": "0.000" + } + } } diff --git a/zynq7/tile_type_BRKH_CLK.json b/zynq7/tile_type_BRKH_CLK.json index 1d51dea..bae9469 100644 --- a/zynq7/tile_type_BRKH_CLK.json +++ b/zynq7/tile_type_BRKH_CLK.json @@ -2,134 +2,134 @@ "pips": {}, "sites": [], "tile_type": "BRKH_CLK", - "wires": [ - "BRKH_CLK_CK_BUFG_CASC0", - "BRKH_CLK_CK_BUFG_CASC1", - "BRKH_CLK_CK_BUFG_CASC10", - "BRKH_CLK_CK_BUFG_CASC11", - "BRKH_CLK_CK_BUFG_CASC12", - "BRKH_CLK_CK_BUFG_CASC13", - "BRKH_CLK_CK_BUFG_CASC14", - "BRKH_CLK_CK_BUFG_CASC15", - "BRKH_CLK_CK_BUFG_CASC16", - "BRKH_CLK_CK_BUFG_CASC17", - "BRKH_CLK_CK_BUFG_CASC18", - "BRKH_CLK_CK_BUFG_CASC19", - "BRKH_CLK_CK_BUFG_CASC2", - "BRKH_CLK_CK_BUFG_CASC20", - "BRKH_CLK_CK_BUFG_CASC21", - "BRKH_CLK_CK_BUFG_CASC22", - "BRKH_CLK_CK_BUFG_CASC23", - "BRKH_CLK_CK_BUFG_CASC24", - "BRKH_CLK_CK_BUFG_CASC25", - "BRKH_CLK_CK_BUFG_CASC26", - "BRKH_CLK_CK_BUFG_CASC27", - "BRKH_CLK_CK_BUFG_CASC28", - "BRKH_CLK_CK_BUFG_CASC29", - "BRKH_CLK_CK_BUFG_CASC3", - "BRKH_CLK_CK_BUFG_CASC30", - "BRKH_CLK_CK_BUFG_CASC31", - "BRKH_CLK_CK_BUFG_CASC4", - "BRKH_CLK_CK_BUFG_CASC5", - "BRKH_CLK_CK_BUFG_CASC6", - "BRKH_CLK_CK_BUFG_CASC7", - "BRKH_CLK_CK_BUFG_CASC8", - "BRKH_CLK_CK_BUFG_CASC9", - "BRKH_CLK_CK_GCLK0", - "BRKH_CLK_CK_GCLK1", - "BRKH_CLK_CK_GCLK10", - "BRKH_CLK_CK_GCLK11", - "BRKH_CLK_CK_GCLK12", - "BRKH_CLK_CK_GCLK13", - "BRKH_CLK_CK_GCLK14", - "BRKH_CLK_CK_GCLK15", - "BRKH_CLK_CK_GCLK16", - "BRKH_CLK_CK_GCLK17", - "BRKH_CLK_CK_GCLK18", - "BRKH_CLK_CK_GCLK19", - "BRKH_CLK_CK_GCLK2", - "BRKH_CLK_CK_GCLK20", - "BRKH_CLK_CK_GCLK21", - "BRKH_CLK_CK_GCLK22", - "BRKH_CLK_CK_GCLK23", - "BRKH_CLK_CK_GCLK24", - "BRKH_CLK_CK_GCLK25", - "BRKH_CLK_CK_GCLK26", - "BRKH_CLK_CK_GCLK27", - "BRKH_CLK_CK_GCLK28", - "BRKH_CLK_CK_GCLK29", - "BRKH_CLK_CK_GCLK3", - "BRKH_CLK_CK_GCLK30", - "BRKH_CLK_CK_GCLK31", - "BRKH_CLK_CK_GCLK4", - "BRKH_CLK_CK_GCLK5", - "BRKH_CLK_CK_GCLK6", - "BRKH_CLK_CK_GCLK7", - "BRKH_CLK_CK_GCLK8", - "BRKH_CLK_CK_GCLK9", - "BRKH_CLK_R_CK_BUFG_CASC0", - "BRKH_CLK_R_CK_BUFG_CASC1", - "BRKH_CLK_R_CK_BUFG_CASC10", - "BRKH_CLK_R_CK_BUFG_CASC11", - "BRKH_CLK_R_CK_BUFG_CASC12", - "BRKH_CLK_R_CK_BUFG_CASC13", - "BRKH_CLK_R_CK_BUFG_CASC14", - "BRKH_CLK_R_CK_BUFG_CASC15", - "BRKH_CLK_R_CK_BUFG_CASC16", - "BRKH_CLK_R_CK_BUFG_CASC17", - "BRKH_CLK_R_CK_BUFG_CASC18", - "BRKH_CLK_R_CK_BUFG_CASC19", - "BRKH_CLK_R_CK_BUFG_CASC2", - "BRKH_CLK_R_CK_BUFG_CASC20", - "BRKH_CLK_R_CK_BUFG_CASC21", - "BRKH_CLK_R_CK_BUFG_CASC22", - "BRKH_CLK_R_CK_BUFG_CASC23", - "BRKH_CLK_R_CK_BUFG_CASC24", - "BRKH_CLK_R_CK_BUFG_CASC25", - "BRKH_CLK_R_CK_BUFG_CASC26", - "BRKH_CLK_R_CK_BUFG_CASC27", - "BRKH_CLK_R_CK_BUFG_CASC28", - "BRKH_CLK_R_CK_BUFG_CASC29", - "BRKH_CLK_R_CK_BUFG_CASC3", - "BRKH_CLK_R_CK_BUFG_CASC30", - "BRKH_CLK_R_CK_BUFG_CASC31", - "BRKH_CLK_R_CK_BUFG_CASC4", - "BRKH_CLK_R_CK_BUFG_CASC5", - "BRKH_CLK_R_CK_BUFG_CASC6", - "BRKH_CLK_R_CK_BUFG_CASC7", - "BRKH_CLK_R_CK_BUFG_CASC8", - "BRKH_CLK_R_CK_BUFG_CASC9", - "BRKH_CLK_R_CK_GCLK0", - "BRKH_CLK_R_CK_GCLK1", - "BRKH_CLK_R_CK_GCLK10", - "BRKH_CLK_R_CK_GCLK11", - "BRKH_CLK_R_CK_GCLK12", - "BRKH_CLK_R_CK_GCLK13", - "BRKH_CLK_R_CK_GCLK14", - "BRKH_CLK_R_CK_GCLK15", - "BRKH_CLK_R_CK_GCLK16", - "BRKH_CLK_R_CK_GCLK17", - "BRKH_CLK_R_CK_GCLK18", - "BRKH_CLK_R_CK_GCLK19", - "BRKH_CLK_R_CK_GCLK2", - "BRKH_CLK_R_CK_GCLK20", - "BRKH_CLK_R_CK_GCLK21", - "BRKH_CLK_R_CK_GCLK22", - "BRKH_CLK_R_CK_GCLK23", - "BRKH_CLK_R_CK_GCLK24", - "BRKH_CLK_R_CK_GCLK25", - "BRKH_CLK_R_CK_GCLK26", - "BRKH_CLK_R_CK_GCLK27", - "BRKH_CLK_R_CK_GCLK28", - "BRKH_CLK_R_CK_GCLK29", - "BRKH_CLK_R_CK_GCLK3", - "BRKH_CLK_R_CK_GCLK30", - "BRKH_CLK_R_CK_GCLK31", - "BRKH_CLK_R_CK_GCLK4", - "BRKH_CLK_R_CK_GCLK5", - "BRKH_CLK_R_CK_GCLK6", - "BRKH_CLK_R_CK_GCLK7", - "BRKH_CLK_R_CK_GCLK8", - "BRKH_CLK_R_CK_GCLK9" - ] + "wires": { + "BRKH_CLK_CK_BUFG_CASC0": null, + "BRKH_CLK_CK_BUFG_CASC1": null, + "BRKH_CLK_CK_BUFG_CASC10": null, + "BRKH_CLK_CK_BUFG_CASC11": null, + "BRKH_CLK_CK_BUFG_CASC12": null, + "BRKH_CLK_CK_BUFG_CASC13": null, + "BRKH_CLK_CK_BUFG_CASC14": null, + "BRKH_CLK_CK_BUFG_CASC15": null, + "BRKH_CLK_CK_BUFG_CASC16": null, + "BRKH_CLK_CK_BUFG_CASC17": null, + "BRKH_CLK_CK_BUFG_CASC18": null, + "BRKH_CLK_CK_BUFG_CASC19": null, + "BRKH_CLK_CK_BUFG_CASC2": null, + "BRKH_CLK_CK_BUFG_CASC20": null, + "BRKH_CLK_CK_BUFG_CASC21": null, + "BRKH_CLK_CK_BUFG_CASC22": null, + "BRKH_CLK_CK_BUFG_CASC23": null, + "BRKH_CLK_CK_BUFG_CASC24": null, + "BRKH_CLK_CK_BUFG_CASC25": null, + "BRKH_CLK_CK_BUFG_CASC26": null, + "BRKH_CLK_CK_BUFG_CASC27": null, + "BRKH_CLK_CK_BUFG_CASC28": null, + "BRKH_CLK_CK_BUFG_CASC29": null, + "BRKH_CLK_CK_BUFG_CASC3": null, + "BRKH_CLK_CK_BUFG_CASC30": null, + "BRKH_CLK_CK_BUFG_CASC31": null, + "BRKH_CLK_CK_BUFG_CASC4": null, + "BRKH_CLK_CK_BUFG_CASC5": null, + "BRKH_CLK_CK_BUFG_CASC6": null, + "BRKH_CLK_CK_BUFG_CASC7": null, + "BRKH_CLK_CK_BUFG_CASC8": null, + "BRKH_CLK_CK_BUFG_CASC9": null, + "BRKH_CLK_CK_GCLK0": null, + "BRKH_CLK_CK_GCLK1": null, + "BRKH_CLK_CK_GCLK10": null, + "BRKH_CLK_CK_GCLK11": null, + "BRKH_CLK_CK_GCLK12": null, + "BRKH_CLK_CK_GCLK13": null, + "BRKH_CLK_CK_GCLK14": null, + "BRKH_CLK_CK_GCLK15": null, + "BRKH_CLK_CK_GCLK16": null, + "BRKH_CLK_CK_GCLK17": null, + "BRKH_CLK_CK_GCLK18": null, + "BRKH_CLK_CK_GCLK19": null, + "BRKH_CLK_CK_GCLK2": null, + "BRKH_CLK_CK_GCLK20": null, + "BRKH_CLK_CK_GCLK21": null, + "BRKH_CLK_CK_GCLK22": null, + "BRKH_CLK_CK_GCLK23": null, + "BRKH_CLK_CK_GCLK24": null, + "BRKH_CLK_CK_GCLK25": null, + "BRKH_CLK_CK_GCLK26": null, + "BRKH_CLK_CK_GCLK27": null, + "BRKH_CLK_CK_GCLK28": null, + "BRKH_CLK_CK_GCLK29": null, + "BRKH_CLK_CK_GCLK3": null, + "BRKH_CLK_CK_GCLK30": null, + "BRKH_CLK_CK_GCLK31": null, + "BRKH_CLK_CK_GCLK4": null, + "BRKH_CLK_CK_GCLK5": null, + "BRKH_CLK_CK_GCLK6": null, + "BRKH_CLK_CK_GCLK7": null, + "BRKH_CLK_CK_GCLK8": null, + "BRKH_CLK_CK_GCLK9": null, + "BRKH_CLK_R_CK_BUFG_CASC0": null, + "BRKH_CLK_R_CK_BUFG_CASC1": null, + "BRKH_CLK_R_CK_BUFG_CASC10": null, + "BRKH_CLK_R_CK_BUFG_CASC11": null, + "BRKH_CLK_R_CK_BUFG_CASC12": null, + "BRKH_CLK_R_CK_BUFG_CASC13": null, + "BRKH_CLK_R_CK_BUFG_CASC14": null, + "BRKH_CLK_R_CK_BUFG_CASC15": null, + "BRKH_CLK_R_CK_BUFG_CASC16": null, + "BRKH_CLK_R_CK_BUFG_CASC17": null, + "BRKH_CLK_R_CK_BUFG_CASC18": null, + "BRKH_CLK_R_CK_BUFG_CASC19": null, + "BRKH_CLK_R_CK_BUFG_CASC2": null, + "BRKH_CLK_R_CK_BUFG_CASC20": null, + "BRKH_CLK_R_CK_BUFG_CASC21": null, + "BRKH_CLK_R_CK_BUFG_CASC22": null, + "BRKH_CLK_R_CK_BUFG_CASC23": null, + "BRKH_CLK_R_CK_BUFG_CASC24": null, + "BRKH_CLK_R_CK_BUFG_CASC25": null, + "BRKH_CLK_R_CK_BUFG_CASC26": null, + "BRKH_CLK_R_CK_BUFG_CASC27": null, + "BRKH_CLK_R_CK_BUFG_CASC28": null, + "BRKH_CLK_R_CK_BUFG_CASC29": null, + "BRKH_CLK_R_CK_BUFG_CASC3": null, + "BRKH_CLK_R_CK_BUFG_CASC30": null, + "BRKH_CLK_R_CK_BUFG_CASC31": null, + "BRKH_CLK_R_CK_BUFG_CASC4": null, + "BRKH_CLK_R_CK_BUFG_CASC5": null, + "BRKH_CLK_R_CK_BUFG_CASC6": null, + "BRKH_CLK_R_CK_BUFG_CASC7": null, + "BRKH_CLK_R_CK_BUFG_CASC8": null, + "BRKH_CLK_R_CK_BUFG_CASC9": null, + "BRKH_CLK_R_CK_GCLK0": null, + "BRKH_CLK_R_CK_GCLK1": null, + "BRKH_CLK_R_CK_GCLK10": null, + "BRKH_CLK_R_CK_GCLK11": null, + "BRKH_CLK_R_CK_GCLK12": null, + "BRKH_CLK_R_CK_GCLK13": null, + "BRKH_CLK_R_CK_GCLK14": null, + "BRKH_CLK_R_CK_GCLK15": null, + "BRKH_CLK_R_CK_GCLK16": null, + "BRKH_CLK_R_CK_GCLK17": null, + "BRKH_CLK_R_CK_GCLK18": null, + "BRKH_CLK_R_CK_GCLK19": null, + "BRKH_CLK_R_CK_GCLK2": null, + "BRKH_CLK_R_CK_GCLK20": null, + "BRKH_CLK_R_CK_GCLK21": null, + "BRKH_CLK_R_CK_GCLK22": null, + "BRKH_CLK_R_CK_GCLK23": null, + "BRKH_CLK_R_CK_GCLK24": null, + "BRKH_CLK_R_CK_GCLK25": null, + "BRKH_CLK_R_CK_GCLK26": null, + "BRKH_CLK_R_CK_GCLK27": null, + "BRKH_CLK_R_CK_GCLK28": null, + "BRKH_CLK_R_CK_GCLK29": null, + "BRKH_CLK_R_CK_GCLK3": null, + "BRKH_CLK_R_CK_GCLK30": null, + "BRKH_CLK_R_CK_GCLK31": null, + "BRKH_CLK_R_CK_GCLK4": null, + "BRKH_CLK_R_CK_GCLK5": null, + "BRKH_CLK_R_CK_GCLK6": null, + "BRKH_CLK_R_CK_GCLK7": null, + "BRKH_CLK_R_CK_GCLK8": null, + "BRKH_CLK_R_CK_GCLK9": null + } } diff --git a/zynq7/tile_type_BRKH_CMT.json b/zynq7/tile_type_BRKH_CMT.json index 6c4fd76..ef7cb17 100644 --- a/zynq7/tile_type_BRKH_CMT.json +++ b/zynq7/tile_type_BRKH_CMT.json @@ -2,15 +2,15 @@ "pips": {}, "sites": [], "tile_type": "BRKH_CMT", - "wires": [ - "BRKH_CMT_FREQ_REF_NS0", - "BRKH_CMT_FREQ_REF_NS1", - "BRKH_CMT_FREQ_REF_NS2", - "BRKH_CMT_FREQ_REF_NS3", - "BRKH_CMT_PHASEREF0", - "BRKH_CMT_PHASEREF1", - "BRKH_CMT_PHASEREF_BELOW0", - "BRKH_CMT_PHASEREF_BELOW1", - "BRKH_CMT_PHYCTRL_SYNC_BB" - ] + "wires": { + "BRKH_CMT_FREQ_REF_NS0": null, + "BRKH_CMT_FREQ_REF_NS1": null, + "BRKH_CMT_FREQ_REF_NS2": null, + "BRKH_CMT_FREQ_REF_NS3": null, + "BRKH_CMT_PHASEREF0": null, + "BRKH_CMT_PHASEREF1": null, + "BRKH_CMT_PHASEREF_BELOW0": null, + "BRKH_CMT_PHASEREF_BELOW1": null, + "BRKH_CMT_PHYCTRL_SYNC_BB": null + } } diff --git a/zynq7/tile_type_BRKH_DSP_L.json b/zynq7/tile_type_BRKH_DSP_L.json index c975252..edfe4f3 100644 --- a/zynq7/tile_type_BRKH_DSP_L.json +++ b/zynq7/tile_type_BRKH_DSP_L.json @@ -2,104 +2,104 @@ "pips": {}, "sites": [], "tile_type": "BRKH_DSP_L", - "wires": [ - "BRKH_DSP_ACIN0", - "BRKH_DSP_ACIN1", - "BRKH_DSP_ACIN10", - "BRKH_DSP_ACIN11", - "BRKH_DSP_ACIN12", - "BRKH_DSP_ACIN13", - "BRKH_DSP_ACIN14", - "BRKH_DSP_ACIN15", - "BRKH_DSP_ACIN16", - "BRKH_DSP_ACIN17", - "BRKH_DSP_ACIN18", - "BRKH_DSP_ACIN19", - "BRKH_DSP_ACIN2", - "BRKH_DSP_ACIN20", - "BRKH_DSP_ACIN21", - "BRKH_DSP_ACIN22", - "BRKH_DSP_ACIN23", - "BRKH_DSP_ACIN24", - "BRKH_DSP_ACIN25", - "BRKH_DSP_ACIN26", - "BRKH_DSP_ACIN27", - "BRKH_DSP_ACIN28", - "BRKH_DSP_ACIN29", - "BRKH_DSP_ACIN3", - "BRKH_DSP_ACIN4", - "BRKH_DSP_ACIN5", - "BRKH_DSP_ACIN6", - "BRKH_DSP_ACIN7", - "BRKH_DSP_ACIN8", - "BRKH_DSP_ACIN9", - "BRKH_DSP_BCIN0", - "BRKH_DSP_BCIN1", - "BRKH_DSP_BCIN10", - "BRKH_DSP_BCIN11", - "BRKH_DSP_BCIN12", - "BRKH_DSP_BCIN13", - "BRKH_DSP_BCIN14", - "BRKH_DSP_BCIN15", - "BRKH_DSP_BCIN16", - "BRKH_DSP_BCIN17", - "BRKH_DSP_BCIN2", - "BRKH_DSP_BCIN3", - "BRKH_DSP_BCIN4", - "BRKH_DSP_BCIN5", - "BRKH_DSP_BCIN6", - "BRKH_DSP_BCIN7", - "BRKH_DSP_BCIN8", - "BRKH_DSP_BCIN9", - "BRKH_DSP_CARRYCASCIN", - "BRKH_DSP_MULTSIGNIN", - "BRKH_DSP_PCIN0", - "BRKH_DSP_PCIN1", - "BRKH_DSP_PCIN10", - "BRKH_DSP_PCIN11", - "BRKH_DSP_PCIN12", - "BRKH_DSP_PCIN13", - "BRKH_DSP_PCIN14", - "BRKH_DSP_PCIN15", - "BRKH_DSP_PCIN16", - "BRKH_DSP_PCIN17", - "BRKH_DSP_PCIN18", - "BRKH_DSP_PCIN19", - "BRKH_DSP_PCIN2", - "BRKH_DSP_PCIN20", - "BRKH_DSP_PCIN21", - "BRKH_DSP_PCIN22", - "BRKH_DSP_PCIN23", - "BRKH_DSP_PCIN24", - "BRKH_DSP_PCIN25", - "BRKH_DSP_PCIN26", - "BRKH_DSP_PCIN27", - "BRKH_DSP_PCIN28", - "BRKH_DSP_PCIN29", - "BRKH_DSP_PCIN3", - "BRKH_DSP_PCIN30", - "BRKH_DSP_PCIN31", - "BRKH_DSP_PCIN32", - "BRKH_DSP_PCIN33", - "BRKH_DSP_PCIN34", - "BRKH_DSP_PCIN35", - "BRKH_DSP_PCIN36", - "BRKH_DSP_PCIN37", - "BRKH_DSP_PCIN38", - "BRKH_DSP_PCIN39", - "BRKH_DSP_PCIN4", - "BRKH_DSP_PCIN40", - "BRKH_DSP_PCIN41", - "BRKH_DSP_PCIN42", - "BRKH_DSP_PCIN43", - "BRKH_DSP_PCIN44", - "BRKH_DSP_PCIN45", - "BRKH_DSP_PCIN46", - "BRKH_DSP_PCIN47", - "BRKH_DSP_PCIN5", - "BRKH_DSP_PCIN6", - "BRKH_DSP_PCIN7", - "BRKH_DSP_PCIN8", - "BRKH_DSP_PCIN9" - ] + "wires": { + "BRKH_DSP_ACIN0": null, + "BRKH_DSP_ACIN1": null, + "BRKH_DSP_ACIN10": null, + "BRKH_DSP_ACIN11": null, + "BRKH_DSP_ACIN12": null, + "BRKH_DSP_ACIN13": null, + "BRKH_DSP_ACIN14": null, + "BRKH_DSP_ACIN15": null, + "BRKH_DSP_ACIN16": null, + "BRKH_DSP_ACIN17": null, + "BRKH_DSP_ACIN18": null, + "BRKH_DSP_ACIN19": null, + "BRKH_DSP_ACIN2": null, + "BRKH_DSP_ACIN20": null, + "BRKH_DSP_ACIN21": null, + "BRKH_DSP_ACIN22": null, + "BRKH_DSP_ACIN23": null, + "BRKH_DSP_ACIN24": null, + "BRKH_DSP_ACIN25": null, + "BRKH_DSP_ACIN26": null, + "BRKH_DSP_ACIN27": null, + "BRKH_DSP_ACIN28": null, + "BRKH_DSP_ACIN29": null, + "BRKH_DSP_ACIN3": null, + "BRKH_DSP_ACIN4": null, + "BRKH_DSP_ACIN5": null, + "BRKH_DSP_ACIN6": null, + "BRKH_DSP_ACIN7": null, + "BRKH_DSP_ACIN8": null, + "BRKH_DSP_ACIN9": null, + "BRKH_DSP_BCIN0": null, + "BRKH_DSP_BCIN1": null, + "BRKH_DSP_BCIN10": null, + "BRKH_DSP_BCIN11": null, + "BRKH_DSP_BCIN12": null, + "BRKH_DSP_BCIN13": null, + "BRKH_DSP_BCIN14": null, + "BRKH_DSP_BCIN15": null, + "BRKH_DSP_BCIN16": null, + "BRKH_DSP_BCIN17": null, + "BRKH_DSP_BCIN2": null, + "BRKH_DSP_BCIN3": null, + "BRKH_DSP_BCIN4": null, + "BRKH_DSP_BCIN5": null, + "BRKH_DSP_BCIN6": null, + "BRKH_DSP_BCIN7": null, + "BRKH_DSP_BCIN8": null, + "BRKH_DSP_BCIN9": null, + "BRKH_DSP_CARRYCASCIN": null, + "BRKH_DSP_MULTSIGNIN": null, + "BRKH_DSP_PCIN0": null, + "BRKH_DSP_PCIN1": null, + "BRKH_DSP_PCIN10": null, + "BRKH_DSP_PCIN11": null, + "BRKH_DSP_PCIN12": null, + "BRKH_DSP_PCIN13": null, + "BRKH_DSP_PCIN14": null, + "BRKH_DSP_PCIN15": null, + "BRKH_DSP_PCIN16": null, + "BRKH_DSP_PCIN17": null, + "BRKH_DSP_PCIN18": null, + "BRKH_DSP_PCIN19": null, + "BRKH_DSP_PCIN2": null, + "BRKH_DSP_PCIN20": null, + "BRKH_DSP_PCIN21": null, + "BRKH_DSP_PCIN22": null, + "BRKH_DSP_PCIN23": null, + "BRKH_DSP_PCIN24": null, + "BRKH_DSP_PCIN25": null, + "BRKH_DSP_PCIN26": null, + "BRKH_DSP_PCIN27": null, + "BRKH_DSP_PCIN28": null, + "BRKH_DSP_PCIN29": null, + "BRKH_DSP_PCIN3": null, + "BRKH_DSP_PCIN30": null, + "BRKH_DSP_PCIN31": null, + "BRKH_DSP_PCIN32": null, + "BRKH_DSP_PCIN33": null, + "BRKH_DSP_PCIN34": null, + "BRKH_DSP_PCIN35": null, + "BRKH_DSP_PCIN36": null, + "BRKH_DSP_PCIN37": null, + "BRKH_DSP_PCIN38": null, + "BRKH_DSP_PCIN39": null, + "BRKH_DSP_PCIN4": null, + "BRKH_DSP_PCIN40": null, + "BRKH_DSP_PCIN41": null, + "BRKH_DSP_PCIN42": null, + "BRKH_DSP_PCIN43": null, + "BRKH_DSP_PCIN44": null, + "BRKH_DSP_PCIN45": null, + "BRKH_DSP_PCIN46": null, + "BRKH_DSP_PCIN47": null, + "BRKH_DSP_PCIN5": null, + "BRKH_DSP_PCIN6": null, + "BRKH_DSP_PCIN7": null, + "BRKH_DSP_PCIN8": null, + "BRKH_DSP_PCIN9": null + } } diff --git a/zynq7/tile_type_BRKH_DSP_R.json b/zynq7/tile_type_BRKH_DSP_R.json index b7ac207..42d27f4 100644 --- a/zynq7/tile_type_BRKH_DSP_R.json +++ b/zynq7/tile_type_BRKH_DSP_R.json @@ -2,104 +2,104 @@ "pips": {}, "sites": [], "tile_type": "BRKH_DSP_R", - "wires": [ - "BRKH_DSP_ACIN0", - "BRKH_DSP_ACIN1", - "BRKH_DSP_ACIN10", - "BRKH_DSP_ACIN11", - "BRKH_DSP_ACIN12", - "BRKH_DSP_ACIN13", - "BRKH_DSP_ACIN14", - "BRKH_DSP_ACIN15", - "BRKH_DSP_ACIN16", - "BRKH_DSP_ACIN17", - "BRKH_DSP_ACIN18", - "BRKH_DSP_ACIN19", - "BRKH_DSP_ACIN2", - "BRKH_DSP_ACIN20", - "BRKH_DSP_ACIN21", - "BRKH_DSP_ACIN22", - "BRKH_DSP_ACIN23", - "BRKH_DSP_ACIN24", - "BRKH_DSP_ACIN25", - "BRKH_DSP_ACIN26", - "BRKH_DSP_ACIN27", - "BRKH_DSP_ACIN28", - "BRKH_DSP_ACIN29", - "BRKH_DSP_ACIN3", - "BRKH_DSP_ACIN4", - "BRKH_DSP_ACIN5", - "BRKH_DSP_ACIN6", - "BRKH_DSP_ACIN7", - "BRKH_DSP_ACIN8", - "BRKH_DSP_ACIN9", - "BRKH_DSP_BCIN0", - "BRKH_DSP_BCIN1", - "BRKH_DSP_BCIN10", - "BRKH_DSP_BCIN11", - "BRKH_DSP_BCIN12", - "BRKH_DSP_BCIN13", - "BRKH_DSP_BCIN14", - "BRKH_DSP_BCIN15", - "BRKH_DSP_BCIN16", - "BRKH_DSP_BCIN17", - "BRKH_DSP_BCIN2", - "BRKH_DSP_BCIN3", - "BRKH_DSP_BCIN4", - "BRKH_DSP_BCIN5", - "BRKH_DSP_BCIN6", - "BRKH_DSP_BCIN7", - "BRKH_DSP_BCIN8", - "BRKH_DSP_BCIN9", - "BRKH_DSP_CARRYCASCIN", - "BRKH_DSP_MULTSIGNIN", - "BRKH_DSP_PCIN0", - "BRKH_DSP_PCIN1", - "BRKH_DSP_PCIN10", - "BRKH_DSP_PCIN11", - "BRKH_DSP_PCIN12", - "BRKH_DSP_PCIN13", - "BRKH_DSP_PCIN14", - "BRKH_DSP_PCIN15", - "BRKH_DSP_PCIN16", - "BRKH_DSP_PCIN17", - "BRKH_DSP_PCIN18", - "BRKH_DSP_PCIN19", - "BRKH_DSP_PCIN2", - "BRKH_DSP_PCIN20", - "BRKH_DSP_PCIN21", - "BRKH_DSP_PCIN22", - "BRKH_DSP_PCIN23", - "BRKH_DSP_PCIN24", - "BRKH_DSP_PCIN25", - "BRKH_DSP_PCIN26", - "BRKH_DSP_PCIN27", - "BRKH_DSP_PCIN28", - "BRKH_DSP_PCIN29", - "BRKH_DSP_PCIN3", - "BRKH_DSP_PCIN30", - "BRKH_DSP_PCIN31", - "BRKH_DSP_PCIN32", - "BRKH_DSP_PCIN33", - "BRKH_DSP_PCIN34", - "BRKH_DSP_PCIN35", - "BRKH_DSP_PCIN36", - "BRKH_DSP_PCIN37", - "BRKH_DSP_PCIN38", - "BRKH_DSP_PCIN39", - "BRKH_DSP_PCIN4", - "BRKH_DSP_PCIN40", - "BRKH_DSP_PCIN41", - "BRKH_DSP_PCIN42", - "BRKH_DSP_PCIN43", - "BRKH_DSP_PCIN44", - "BRKH_DSP_PCIN45", - "BRKH_DSP_PCIN46", - "BRKH_DSP_PCIN47", - "BRKH_DSP_PCIN5", - "BRKH_DSP_PCIN6", - "BRKH_DSP_PCIN7", - "BRKH_DSP_PCIN8", - "BRKH_DSP_PCIN9" - ] + "wires": { + "BRKH_DSP_ACIN0": null, + "BRKH_DSP_ACIN1": null, + "BRKH_DSP_ACIN10": null, + "BRKH_DSP_ACIN11": null, + "BRKH_DSP_ACIN12": null, + "BRKH_DSP_ACIN13": null, + "BRKH_DSP_ACIN14": null, + "BRKH_DSP_ACIN15": null, + "BRKH_DSP_ACIN16": null, + "BRKH_DSP_ACIN17": null, + "BRKH_DSP_ACIN18": null, + "BRKH_DSP_ACIN19": null, + "BRKH_DSP_ACIN2": null, + "BRKH_DSP_ACIN20": null, + "BRKH_DSP_ACIN21": null, + "BRKH_DSP_ACIN22": null, + "BRKH_DSP_ACIN23": null, + "BRKH_DSP_ACIN24": null, + "BRKH_DSP_ACIN25": null, + "BRKH_DSP_ACIN26": null, + "BRKH_DSP_ACIN27": null, + "BRKH_DSP_ACIN28": null, + "BRKH_DSP_ACIN29": null, + "BRKH_DSP_ACIN3": null, + "BRKH_DSP_ACIN4": null, + "BRKH_DSP_ACIN5": null, + "BRKH_DSP_ACIN6": null, + "BRKH_DSP_ACIN7": null, + "BRKH_DSP_ACIN8": null, + "BRKH_DSP_ACIN9": null, + "BRKH_DSP_BCIN0": null, + "BRKH_DSP_BCIN1": null, + "BRKH_DSP_BCIN10": null, + "BRKH_DSP_BCIN11": null, + "BRKH_DSP_BCIN12": null, + "BRKH_DSP_BCIN13": null, + "BRKH_DSP_BCIN14": null, + "BRKH_DSP_BCIN15": null, + "BRKH_DSP_BCIN16": null, + "BRKH_DSP_BCIN17": null, + "BRKH_DSP_BCIN2": null, + "BRKH_DSP_BCIN3": null, + "BRKH_DSP_BCIN4": null, + "BRKH_DSP_BCIN5": null, + "BRKH_DSP_BCIN6": null, + "BRKH_DSP_BCIN7": null, + "BRKH_DSP_BCIN8": null, + "BRKH_DSP_BCIN9": null, + "BRKH_DSP_CARRYCASCIN": null, + "BRKH_DSP_MULTSIGNIN": null, + "BRKH_DSP_PCIN0": null, + "BRKH_DSP_PCIN1": null, + "BRKH_DSP_PCIN10": null, + "BRKH_DSP_PCIN11": null, + "BRKH_DSP_PCIN12": null, + "BRKH_DSP_PCIN13": null, + "BRKH_DSP_PCIN14": null, + "BRKH_DSP_PCIN15": null, + "BRKH_DSP_PCIN16": null, + "BRKH_DSP_PCIN17": null, + "BRKH_DSP_PCIN18": null, + "BRKH_DSP_PCIN19": null, + "BRKH_DSP_PCIN2": null, + "BRKH_DSP_PCIN20": null, + "BRKH_DSP_PCIN21": null, + "BRKH_DSP_PCIN22": null, + "BRKH_DSP_PCIN23": null, + "BRKH_DSP_PCIN24": null, + "BRKH_DSP_PCIN25": null, + "BRKH_DSP_PCIN26": null, + "BRKH_DSP_PCIN27": null, + "BRKH_DSP_PCIN28": null, + "BRKH_DSP_PCIN29": null, + "BRKH_DSP_PCIN3": null, + "BRKH_DSP_PCIN30": null, + "BRKH_DSP_PCIN31": null, + "BRKH_DSP_PCIN32": null, + "BRKH_DSP_PCIN33": null, + "BRKH_DSP_PCIN34": null, + "BRKH_DSP_PCIN35": null, + "BRKH_DSP_PCIN36": null, + "BRKH_DSP_PCIN37": null, + "BRKH_DSP_PCIN38": null, + "BRKH_DSP_PCIN39": null, + "BRKH_DSP_PCIN4": null, + "BRKH_DSP_PCIN40": null, + "BRKH_DSP_PCIN41": null, + "BRKH_DSP_PCIN42": null, + "BRKH_DSP_PCIN43": null, + "BRKH_DSP_PCIN44": null, + "BRKH_DSP_PCIN45": null, + "BRKH_DSP_PCIN46": null, + "BRKH_DSP_PCIN47": null, + "BRKH_DSP_PCIN5": null, + "BRKH_DSP_PCIN6": null, + "BRKH_DSP_PCIN7": null, + "BRKH_DSP_PCIN8": null, + "BRKH_DSP_PCIN9": null + } } diff --git a/zynq7/tile_type_BRKH_INT.json b/zynq7/tile_type_BRKH_INT.json index 124110a..49ba5f9 100644 --- a/zynq7/tile_type_BRKH_INT.json +++ b/zynq7/tile_type_BRKH_INT.json @@ -2,366 +2,1353 @@ "pips": { "BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_NL1BEG0_SLOW", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_NL1BEG0" }, "BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_NL1BEG1_SLOW", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_NL1BEG1" }, "BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_NL1BEG2_SLOW", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_NL1BEG2" }, "BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_NR1BEG0_SLOW", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_NR1BEG0" }, "BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_NR1BEG1_SLOW", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_NR1BEG1" }, "BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_NR1BEG2_SLOW", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_NR1BEG2" }, "BRKH_INT.BRKH_INT_NR1BEG3->>BRKH_INT_NR1BEG3_SLOW": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_NR1BEG3_SLOW", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_NR1BEG3" }, "BRKH_INT.BRKH_INT_SL1END0_SLOW->>BRKH_INT_SL1END0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_SL1END0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_SL1END0_SLOW" }, "BRKH_INT.BRKH_INT_SL1END1_SLOW->>BRKH_INT_SL1END1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_SL1END1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_SL1END1_SLOW" }, "BRKH_INT.BRKH_INT_SL1END2_SLOW->>BRKH_INT_SL1END2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_SL1END2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_SL1END2_SLOW" }, "BRKH_INT.BRKH_INT_SL1END3_SLOW->>BRKH_INT_SL1END3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_SL1END3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_SL1END3_SLOW" }, "BRKH_INT.BRKH_INT_SR1END1_SLOW->>BRKH_INT_SR1END1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_SR1END1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_SR1END1_SLOW" }, "BRKH_INT.BRKH_INT_SR1END2_SLOW->>BRKH_INT_SR1END2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_SR1END2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_SR1END2_SLOW" }, "BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "dst_wire": "BRKH_INT_SR1END3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.202", + "0.231", + "0.312" + ], + "in_cap": "1.111", + "res": "424.875" + }, "src_wire": "BRKH_INT_SR1END3_SLOW" } }, "sites": [], "tile_type": "BRKH_INT", - "wires": [ - "BRKH_INT_BYP_BOUNCE2", - "BRKH_INT_BYP_BOUNCE3", - "BRKH_INT_BYP_BOUNCE6", - "BRKH_INT_BYP_BOUNCE7", - "BRKH_INT_EL1BEG3", - "BRKH_INT_EL1END_S3_0", - "BRKH_INT_ER1BEG_S0", - "BRKH_INT_ER1END3", - "BRKH_INT_FAN_BOUNCE_S3_0", - "BRKH_INT_FAN_BOUNCE_S3_2", - "BRKH_INT_FAN_BOUNCE_S3_4", - "BRKH_INT_FAN_BOUNCE_S3_6", - "BRKH_INT_LV0", - "BRKH_INT_LV1", - "BRKH_INT_LV10", - "BRKH_INT_LV11", - "BRKH_INT_LV12", - "BRKH_INT_LV13", - "BRKH_INT_LV14", - "BRKH_INT_LV15", - "BRKH_INT_LV16", - "BRKH_INT_LV17", - "BRKH_INT_LV2", - "BRKH_INT_LV3", - "BRKH_INT_LV4", - "BRKH_INT_LV5", - "BRKH_INT_LV6", - "BRKH_INT_LV7", - "BRKH_INT_LV8", - "BRKH_INT_LV9", - "BRKH_INT_LVB1", - "BRKH_INT_LVB10", - "BRKH_INT_LVB11", - "BRKH_INT_LVB12", - "BRKH_INT_LVB2", - "BRKH_INT_LVB3", - "BRKH_INT_LVB4", - "BRKH_INT_LVB5", - "BRKH_INT_LVB6", - "BRKH_INT_LVB7", - "BRKH_INT_LVB8", - "BRKH_INT_LVB9", - "BRKH_INT_LVB_L1", - "BRKH_INT_LVB_L10", - "BRKH_INT_LVB_L11", - "BRKH_INT_LVB_L12", - "BRKH_INT_LVB_L2", - "BRKH_INT_LVB_L3", - "BRKH_INT_LVB_L4", - "BRKH_INT_LVB_L5", - "BRKH_INT_LVB_L6", - "BRKH_INT_LVB_L7", - "BRKH_INT_LVB_L8", - "BRKH_INT_LVB_L9", - "BRKH_INT_L_LV0", - "BRKH_INT_L_LV1", - "BRKH_INT_L_LV10", - "BRKH_INT_L_LV11", - "BRKH_INT_L_LV12", - "BRKH_INT_L_LV13", - "BRKH_INT_L_LV14", - "BRKH_INT_L_LV15", - "BRKH_INT_L_LV16", - "BRKH_INT_L_LV17", - "BRKH_INT_L_LV2", - "BRKH_INT_L_LV3", - "BRKH_INT_L_LV4", - "BRKH_INT_L_LV5", - "BRKH_INT_L_LV6", - "BRKH_INT_L_LV7", - "BRKH_INT_L_LV8", - "BRKH_INT_L_LV9", - "BRKH_INT_NE2BEG0", - "BRKH_INT_NE2BEG1", - "BRKH_INT_NE2BEG2", - "BRKH_INT_NE2BEG3", - "BRKH_INT_NE2END_S3_0", - "BRKH_INT_NE6A0", - "BRKH_INT_NE6A1", - "BRKH_INT_NE6A2", - "BRKH_INT_NE6A3", - "BRKH_INT_NE6B0", - "BRKH_INT_NE6B1", - "BRKH_INT_NE6B2", - "BRKH_INT_NE6B3", - "BRKH_INT_NE6C0", - "BRKH_INT_NE6C1", - "BRKH_INT_NE6C2", - "BRKH_INT_NE6C3", - "BRKH_INT_NE6D0", - "BRKH_INT_NE6D1", - "BRKH_INT_NE6D2", - "BRKH_INT_NE6D3", - "BRKH_INT_NL1BEG0", - "BRKH_INT_NL1BEG0_SLOW", - "BRKH_INT_NL1BEG1", - "BRKH_INT_NL1BEG1_SLOW", - "BRKH_INT_NL1BEG2", - "BRKH_INT_NL1BEG2_SLOW", - "BRKH_INT_NL1END_S3_0", - "BRKH_INT_NN2A0", - "BRKH_INT_NN2A1", - "BRKH_INT_NN2A2", - "BRKH_INT_NN2A3", - "BRKH_INT_NN2BEG0", - "BRKH_INT_NN2BEG1", - "BRKH_INT_NN2BEG2", - "BRKH_INT_NN2BEG3", - "BRKH_INT_NN2END_S2_0", - "BRKH_INT_NN6A0", - "BRKH_INT_NN6A1", - "BRKH_INT_NN6A2", - "BRKH_INT_NN6A3", - "BRKH_INT_NN6B0", - "BRKH_INT_NN6B1", - "BRKH_INT_NN6B2", - "BRKH_INT_NN6B3", - "BRKH_INT_NN6BEG0", - "BRKH_INT_NN6BEG1", - "BRKH_INT_NN6BEG2", - "BRKH_INT_NN6BEG3", - "BRKH_INT_NN6C0", - "BRKH_INT_NN6C1", - "BRKH_INT_NN6C2", - "BRKH_INT_NN6C3", - "BRKH_INT_NN6D0", - "BRKH_INT_NN6D1", - "BRKH_INT_NN6D2", - "BRKH_INT_NN6D3", - "BRKH_INT_NN6E0", - "BRKH_INT_NN6E1", - "BRKH_INT_NN6E2", - "BRKH_INT_NN6E3", - "BRKH_INT_NN6END_S1_0", - "BRKH_INT_NR1BEG0", - "BRKH_INT_NR1BEG0_SLOW", - "BRKH_INT_NR1BEG1", - "BRKH_INT_NR1BEG1_SLOW", - "BRKH_INT_NR1BEG2", - "BRKH_INT_NR1BEG2_SLOW", - "BRKH_INT_NR1BEG3", - "BRKH_INT_NR1BEG3_SLOW", - "BRKH_INT_NW2BEG0", - "BRKH_INT_NW2BEG1", - "BRKH_INT_NW2BEG2", - "BRKH_INT_NW2BEG3", - "BRKH_INT_NW2END_S0_0", - "BRKH_INT_NW6A0", - "BRKH_INT_NW6A1", - "BRKH_INT_NW6A2", - "BRKH_INT_NW6A3", - "BRKH_INT_NW6B0", - "BRKH_INT_NW6B1", - "BRKH_INT_NW6B2", - "BRKH_INT_NW6B3", - "BRKH_INT_NW6C0", - "BRKH_INT_NW6C1", - "BRKH_INT_NW6C2", - "BRKH_INT_NW6C3", - "BRKH_INT_NW6D0", - "BRKH_INT_NW6D1", - "BRKH_INT_NW6D2", - "BRKH_INT_NW6D3", - "BRKH_INT_NW6END_S0_0", - "BRKH_INT_SE2A0", - "BRKH_INT_SE2A1", - "BRKH_INT_SE2A2", - "BRKH_INT_SE2A3", - "BRKH_INT_SE6B0", - "BRKH_INT_SE6B1", - "BRKH_INT_SE6B2", - "BRKH_INT_SE6B3", - "BRKH_INT_SE6C0", - "BRKH_INT_SE6C1", - "BRKH_INT_SE6C2", - "BRKH_INT_SE6C3", - "BRKH_INT_SE6D0", - "BRKH_INT_SE6D1", - "BRKH_INT_SE6D2", - "BRKH_INT_SE6D3", - "BRKH_INT_SE6E0", - "BRKH_INT_SE6E1", - "BRKH_INT_SE6E2", - "BRKH_INT_SE6E3", - "BRKH_INT_SL1END0", - "BRKH_INT_SL1END0_SLOW", - "BRKH_INT_SL1END1", - "BRKH_INT_SL1END1_SLOW", - "BRKH_INT_SL1END2", - "BRKH_INT_SL1END2_SLOW", - "BRKH_INT_SL1END3", - "BRKH_INT_SL1END3_SLOW", - "BRKH_INT_SR1END1", - "BRKH_INT_SR1END1_SLOW", - "BRKH_INT_SR1END2", - "BRKH_INT_SR1END2_SLOW", - "BRKH_INT_SR1END3", - "BRKH_INT_SR1END3_SLOW", - "BRKH_INT_SR1END_N3_3", - "BRKH_INT_SS2A0", - "BRKH_INT_SS2A1", - "BRKH_INT_SS2A2", - "BRKH_INT_SS2A3", - "BRKH_INT_SS2END0", - "BRKH_INT_SS2END1", - "BRKH_INT_SS2END2", - "BRKH_INT_SS2END3", - "BRKH_INT_SS2END_N0_3", - "BRKH_INT_SS6A0", - "BRKH_INT_SS6A1", - "BRKH_INT_SS6A2", - "BRKH_INT_SS6A3", - "BRKH_INT_SS6B0", - "BRKH_INT_SS6B1", - "BRKH_INT_SS6B2", - "BRKH_INT_SS6B3", - "BRKH_INT_SS6C0", - "BRKH_INT_SS6C1", - "BRKH_INT_SS6C2", - "BRKH_INT_SS6C3", - "BRKH_INT_SS6D0", - "BRKH_INT_SS6D1", - "BRKH_INT_SS6D2", - "BRKH_INT_SS6D3", - "BRKH_INT_SS6E0", - "BRKH_INT_SS6E1", - "BRKH_INT_SS6E2", - "BRKH_INT_SS6E3", - "BRKH_INT_SS6END0", - "BRKH_INT_SS6END1", - "BRKH_INT_SS6END2", - "BRKH_INT_SS6END3", - "BRKH_INT_SS6END_N0_3", - "BRKH_INT_SW2A0", - "BRKH_INT_SW2A1", - "BRKH_INT_SW2A2", - "BRKH_INT_SW2A3", - "BRKH_INT_SW2END3", - "BRKH_INT_SW6B0", - "BRKH_INT_SW6B1", - "BRKH_INT_SW6B2", - "BRKH_INT_SW6B3", - "BRKH_INT_SW6C0", - "BRKH_INT_SW6C1", - "BRKH_INT_SW6C2", - "BRKH_INT_SW6C3", - "BRKH_INT_SW6D0", - "BRKH_INT_SW6D1", - "BRKH_INT_SW6D2", - "BRKH_INT_SW6D3", - "BRKH_INT_SW6E0", - "BRKH_INT_SW6E1", - "BRKH_INT_SW6E2", - "BRKH_INT_SW6E3", - "BRKH_INT_SW6END3", - "BRKH_INT_WL1BEG3", - "BRKH_INT_WL1END3", - "BRKH_INT_WR1BEG_S0", - "BRKH_INT_WR1END_S1_0", - "BRKH_INT_WW2END3", - "BRKH_INT_WW4END_S0_0" - ] + "wires": { + "BRKH_INT_BYP_BOUNCE2": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_BYP_BOUNCE3": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_BYP_BOUNCE6": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_BYP_BOUNCE7": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_EL1BEG3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_EL1END_S3_0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_ER1BEG_S0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_ER1END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_FAN_BOUNCE_S3_0": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_FAN_BOUNCE_S3_2": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_FAN_BOUNCE_S3_4": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_FAN_BOUNCE_S3_6": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_LV0": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV1": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV10": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV11": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV12": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV13": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV14": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV15": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV16": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV17": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV2": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV3": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV4": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV5": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV6": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV7": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV8": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV9": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB1": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB10": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB11": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB12": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB2": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB3": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB4": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB5": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB6": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB7": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB8": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB9": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB_L1": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB_L10": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB_L11": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB_L12": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB_L2": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB_L3": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB_L4": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB_L5": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB_L6": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB_L7": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB_L8": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LVB_L9": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV0": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV1": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV10": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV11": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV12": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV13": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV14": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV15": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV16": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV17": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV2": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV3": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV4": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV5": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV6": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV7": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV8": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_L_LV9": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_NE2BEG0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE2BEG1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE2BEG2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE2BEG3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE2END_S3_0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6A0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6A1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6A2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6A3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6B0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6B1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6B2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6B3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6C0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6C1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6C2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6C3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6D0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6D1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6D2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NE6D3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NL1BEG0": null, + "BRKH_INT_NL1BEG0_SLOW": null, + "BRKH_INT_NL1BEG1": null, + "BRKH_INT_NL1BEG1_SLOW": null, + "BRKH_INT_NL1BEG2": null, + "BRKH_INT_NL1BEG2_SLOW": null, + "BRKH_INT_NL1END_S3_0": null, + "BRKH_INT_NN2A0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN2A1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN2A2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN2A3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN2BEG0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN2BEG1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN2BEG2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN2BEG3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN2END_S2_0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6A0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6A1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6A2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6A3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6B0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6B1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6B2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6B3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6BEG0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6BEG1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6BEG2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6BEG3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6C0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6C1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6C2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6C3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6D0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6D1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6D2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6D3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6E0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6E1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6E2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6E3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6END_S1_0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NR1BEG0": null, + "BRKH_INT_NR1BEG0_SLOW": null, + "BRKH_INT_NR1BEG1": null, + "BRKH_INT_NR1BEG1_SLOW": null, + "BRKH_INT_NR1BEG2": null, + "BRKH_INT_NR1BEG2_SLOW": null, + "BRKH_INT_NR1BEG3": null, + "BRKH_INT_NR1BEG3_SLOW": null, + "BRKH_INT_NW2BEG0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW2BEG1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW2BEG2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW2BEG3": { + "cap": "1.000", + "res": "5.230" + }, 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"BRKH_INT_SE6D2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6D3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6E0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6E1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6E2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6E3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SL1END0": null, + "BRKH_INT_SL1END0_SLOW": null, + "BRKH_INT_SL1END1": null, + "BRKH_INT_SL1END1_SLOW": null, + "BRKH_INT_SL1END2": null, + "BRKH_INT_SL1END2_SLOW": null, + "BRKH_INT_SL1END3": null, + "BRKH_INT_SL1END3_SLOW": null, + "BRKH_INT_SR1END1": null, + "BRKH_INT_SR1END1_SLOW": null, + "BRKH_INT_SR1END2": null, + "BRKH_INT_SR1END2_SLOW": null, + "BRKH_INT_SR1END3": null, + "BRKH_INT_SR1END3_SLOW": null, + "BRKH_INT_SR1END_N3_3": null, + "BRKH_INT_SS2A0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2A1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2A2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2A3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2END0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2END1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2END2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2END_N0_3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6A0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6A1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6A2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6A3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6B0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6B1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6B2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6B3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6C0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6C1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6C2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6C3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6D0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6D1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6D2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6D3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6E0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6E1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6E2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6E3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6END0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6END1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6END2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6END_N0_3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW2A0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW2A1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW2A2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW2A3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW2END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6B0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6B1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6B2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6B3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6C0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6C1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6C2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6C3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6D0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6D1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6D2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6D3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6E0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6E1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6E2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6E3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_WL1BEG3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_WL1END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_WR1BEG_S0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_WR1END_S1_0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_WW2END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_WW4END_S0_0": { + "cap": "1.000", + "res": "5.230" + } + } } diff --git a/zynq7/tile_type_B_TERM_INT.json b/zynq7/tile_type_B_TERM_INT.json index 8ce2278..73bd2de 100644 --- a/zynq7/tile_type_B_TERM_INT.json +++ b/zynq7/tile_type_B_TERM_INT.json @@ -2,124 +2,214 @@ "pips": {}, "sites": [], "tile_type": "B_TERM_INT", - "wires": [ - "B_TERM_UTURN_INT_ER1BEG0", - "B_TERM_UTURN_INT_ER1END_N3_3", - "B_TERM_UTURN_INT_FAN_BOUNCE0", - "B_TERM_UTURN_INT_FAN_BOUNCE2", - "B_TERM_UTURN_INT_FAN_BOUNCE4", - "B_TERM_UTURN_INT_FAN_BOUNCE6", - "B_TERM_UTURN_INT_LV18", - "B_TERM_UTURN_INT_LV2", - "B_TERM_UTURN_INT_LV3", - "B_TERM_UTURN_INT_LV4", - "B_TERM_UTURN_INT_LV5", - "B_TERM_UTURN_INT_LV6", - "B_TERM_UTURN_INT_LV7", - "B_TERM_UTURN_INT_LV8", - "B_TERM_UTURN_INT_LV9", - "B_TERM_UTURN_INT_LVB0", - "B_TERM_UTURN_INT_LVB1", - "B_TERM_UTURN_INT_LVB2", - "B_TERM_UTURN_INT_LVB3", - "B_TERM_UTURN_INT_LVB4", - "B_TERM_UTURN_INT_LVB5", - "B_TERM_UTURN_INT_LVB_L0", - "B_TERM_UTURN_INT_LVB_L1", - "B_TERM_UTURN_INT_LVB_L2", - "B_TERM_UTURN_INT_LVB_L3", - "B_TERM_UTURN_INT_LVB_L4", - "B_TERM_UTURN_INT_LVB_L5", - "B_TERM_UTURN_INT_LV_L18", - "B_TERM_UTURN_INT_LV_L2", - "B_TERM_UTURN_INT_LV_L3", - "B_TERM_UTURN_INT_LV_L4", - "B_TERM_UTURN_INT_LV_L5", - "B_TERM_UTURN_INT_LV_L6", - "B_TERM_UTURN_INT_LV_L7", - "B_TERM_UTURN_INT_LV_L8", - "B_TERM_UTURN_INT_LV_L9", - "B_TERM_UTURN_INT_SE2BEG0", - "B_TERM_UTURN_INT_SE2BEG1", - "B_TERM_UTURN_INT_SE2BEG2", - "B_TERM_UTURN_INT_SE2BEG3", - "B_TERM_UTURN_INT_SE6A0", - "B_TERM_UTURN_INT_SE6A1", - "B_TERM_UTURN_INT_SE6A2", - "B_TERM_UTURN_INT_SE6A3", - "B_TERM_UTURN_INT_SE6B0", - "B_TERM_UTURN_INT_SE6B1", - "B_TERM_UTURN_INT_SE6B2", - "B_TERM_UTURN_INT_SE6B3", - "B_TERM_UTURN_INT_SE6C0", - "B_TERM_UTURN_INT_SE6C1", - "B_TERM_UTURN_INT_SE6C2", - "B_TERM_UTURN_INT_SE6C3", - "B_TERM_UTURN_INT_SE6D0", - "B_TERM_UTURN_INT_SE6D1", - "B_TERM_UTURN_INT_SE6D2", - "B_TERM_UTURN_INT_SE6D3", - "B_TERM_UTURN_INT_SL1BEG0", - "B_TERM_UTURN_INT_SL1BEG1", - "B_TERM_UTURN_INT_SL1BEG2", - "B_TERM_UTURN_INT_SL1BEG3", - "B_TERM_UTURN_INT_SR1BEG1", - "B_TERM_UTURN_INT_SR1BEG2", - "B_TERM_UTURN_INT_SR1BEG3", - "B_TERM_UTURN_INT_SS2A0", - "B_TERM_UTURN_INT_SS2A1", - "B_TERM_UTURN_INT_SS2A2", - "B_TERM_UTURN_INT_SS2A3", - "B_TERM_UTURN_INT_SS2BEG0", - "B_TERM_UTURN_INT_SS2BEG1", - "B_TERM_UTURN_INT_SS2BEG2", - "B_TERM_UTURN_INT_SS2BEG3", - "B_TERM_UTURN_INT_SS6A0", - "B_TERM_UTURN_INT_SS6A1", - "B_TERM_UTURN_INT_SS6A2", - "B_TERM_UTURN_INT_SS6A3", - "B_TERM_UTURN_INT_SS6B0", - "B_TERM_UTURN_INT_SS6B1", - "B_TERM_UTURN_INT_SS6B2", - "B_TERM_UTURN_INT_SS6B3", - "B_TERM_UTURN_INT_SS6BEG0", - "B_TERM_UTURN_INT_SS6BEG1", - "B_TERM_UTURN_INT_SS6BEG2", - "B_TERM_UTURN_INT_SS6BEG3", - "B_TERM_UTURN_INT_SS6C0", - "B_TERM_UTURN_INT_SS6C1", - "B_TERM_UTURN_INT_SS6C2", - "B_TERM_UTURN_INT_SS6C3", - "B_TERM_UTURN_INT_SS6D0", - "B_TERM_UTURN_INT_SS6D1", - "B_TERM_UTURN_INT_SS6D2", - "B_TERM_UTURN_INT_SS6D3", - "B_TERM_UTURN_INT_SS6E0", - "B_TERM_UTURN_INT_SS6E1", - "B_TERM_UTURN_INT_SS6E2", - "B_TERM_UTURN_INT_SS6E3", - "B_TERM_UTURN_INT_SW2BEG0", - "B_TERM_UTURN_INT_SW2BEG1", - "B_TERM_UTURN_INT_SW2BEG2", - "B_TERM_UTURN_INT_SW2BEG3", - "B_TERM_UTURN_INT_SW6A0", - "B_TERM_UTURN_INT_SW6A1", - "B_TERM_UTURN_INT_SW6A2", - "B_TERM_UTURN_INT_SW6A3", - "B_TERM_UTURN_INT_SW6B0", - "B_TERM_UTURN_INT_SW6B1", - "B_TERM_UTURN_INT_SW6B2", - "B_TERM_UTURN_INT_SW6B3", - "B_TERM_UTURN_INT_SW6C0", - "B_TERM_UTURN_INT_SW6C1", - "B_TERM_UTURN_INT_SW6C2", - "B_TERM_UTURN_INT_SW6C3", - "B_TERM_UTURN_INT_SW6D0", - "B_TERM_UTURN_INT_SW6D1", - "B_TERM_UTURN_INT_SW6D2", - "B_TERM_UTURN_INT_SW6D3", - "B_TERM_UTURN_INT_SW6END_N0_3", - "B_TERM_UTURN_INT_WR1BEG0", - "B_TERM_UTURN_INT_WR1END0" - ] + "wires": { + "B_TERM_UTURN_INT_ER1BEG0": null, + "B_TERM_UTURN_INT_ER1END_N3_3": null, + "B_TERM_UTURN_INT_FAN_BOUNCE0": null, + "B_TERM_UTURN_INT_FAN_BOUNCE2": null, + "B_TERM_UTURN_INT_FAN_BOUNCE4": null, + "B_TERM_UTURN_INT_FAN_BOUNCE6": null, + "B_TERM_UTURN_INT_LV18": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV6": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV7": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV8": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV9": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB0": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB1": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L0": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L1": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L18": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L6": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L7": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L8": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L9": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_SE2BEG0": null, + "B_TERM_UTURN_INT_SE2BEG1": null, + "B_TERM_UTURN_INT_SE2BEG2": null, + "B_TERM_UTURN_INT_SE2BEG3": null, + "B_TERM_UTURN_INT_SE6A0": null, + "B_TERM_UTURN_INT_SE6A1": null, + "B_TERM_UTURN_INT_SE6A2": null, + "B_TERM_UTURN_INT_SE6A3": null, + "B_TERM_UTURN_INT_SE6B0": null, + "B_TERM_UTURN_INT_SE6B1": null, + "B_TERM_UTURN_INT_SE6B2": null, + "B_TERM_UTURN_INT_SE6B3": null, + "B_TERM_UTURN_INT_SE6C0": null, + "B_TERM_UTURN_INT_SE6C1": null, + "B_TERM_UTURN_INT_SE6C2": null, + "B_TERM_UTURN_INT_SE6C3": null, + "B_TERM_UTURN_INT_SE6D0": null, + "B_TERM_UTURN_INT_SE6D1": null, + "B_TERM_UTURN_INT_SE6D2": null, + "B_TERM_UTURN_INT_SE6D3": null, + "B_TERM_UTURN_INT_SL1BEG0": null, + "B_TERM_UTURN_INT_SL1BEG1": null, + "B_TERM_UTURN_INT_SL1BEG2": null, + "B_TERM_UTURN_INT_SL1BEG3": null, + "B_TERM_UTURN_INT_SR1BEG1": null, + "B_TERM_UTURN_INT_SR1BEG2": null, + "B_TERM_UTURN_INT_SR1BEG3": null, + "B_TERM_UTURN_INT_SS2A0": null, + "B_TERM_UTURN_INT_SS2A1": null, + "B_TERM_UTURN_INT_SS2A2": null, + "B_TERM_UTURN_INT_SS2A3": null, + "B_TERM_UTURN_INT_SS2BEG0": null, + "B_TERM_UTURN_INT_SS2BEG1": null, + "B_TERM_UTURN_INT_SS2BEG2": null, + "B_TERM_UTURN_INT_SS2BEG3": null, + "B_TERM_UTURN_INT_SS6A0": null, + "B_TERM_UTURN_INT_SS6A1": null, + "B_TERM_UTURN_INT_SS6A2": null, + "B_TERM_UTURN_INT_SS6A3": null, + "B_TERM_UTURN_INT_SS6B0": null, + "B_TERM_UTURN_INT_SS6B1": null, + "B_TERM_UTURN_INT_SS6B2": null, + "B_TERM_UTURN_INT_SS6B3": null, + "B_TERM_UTURN_INT_SS6BEG0": null, + "B_TERM_UTURN_INT_SS6BEG1": null, + "B_TERM_UTURN_INT_SS6BEG2": null, + "B_TERM_UTURN_INT_SS6BEG3": null, + "B_TERM_UTURN_INT_SS6C0": null, + "B_TERM_UTURN_INT_SS6C1": null, + "B_TERM_UTURN_INT_SS6C2": null, + "B_TERM_UTURN_INT_SS6C3": null, + "B_TERM_UTURN_INT_SS6D0": null, + "B_TERM_UTURN_INT_SS6D1": null, + "B_TERM_UTURN_INT_SS6D2": null, + "B_TERM_UTURN_INT_SS6D3": null, + "B_TERM_UTURN_INT_SS6E0": null, + "B_TERM_UTURN_INT_SS6E1": null, + "B_TERM_UTURN_INT_SS6E2": null, + "B_TERM_UTURN_INT_SS6E3": null, + "B_TERM_UTURN_INT_SW2BEG0": null, + "B_TERM_UTURN_INT_SW2BEG1": null, + "B_TERM_UTURN_INT_SW2BEG2": null, + "B_TERM_UTURN_INT_SW2BEG3": null, + "B_TERM_UTURN_INT_SW6A0": null, + "B_TERM_UTURN_INT_SW6A1": null, + "B_TERM_UTURN_INT_SW6A2": null, + "B_TERM_UTURN_INT_SW6A3": null, + "B_TERM_UTURN_INT_SW6B0": null, + "B_TERM_UTURN_INT_SW6B1": null, + "B_TERM_UTURN_INT_SW6B2": null, + "B_TERM_UTURN_INT_SW6B3": null, + "B_TERM_UTURN_INT_SW6C0": null, + "B_TERM_UTURN_INT_SW6C1": null, + "B_TERM_UTURN_INT_SW6C2": null, + "B_TERM_UTURN_INT_SW6C3": null, + "B_TERM_UTURN_INT_SW6D0": null, + "B_TERM_UTURN_INT_SW6D1": null, + "B_TERM_UTURN_INT_SW6D2": null, + "B_TERM_UTURN_INT_SW6D3": null, + "B_TERM_UTURN_INT_SW6END_N0_3": null, + "B_TERM_UTURN_INT_WR1BEG0": null, + "B_TERM_UTURN_INT_WR1END0": null + } } diff --git a/zynq7/tile_type_B_TERM_INT_PSS.json b/zynq7/tile_type_B_TERM_INT_PSS.json index 93f760c..6e86432 100644 --- a/zynq7/tile_type_B_TERM_INT_PSS.json +++ b/zynq7/tile_type_B_TERM_INT_PSS.json @@ -2,7 +2,7 @@ "pips": {}, "sites": [], "tile_type": "B_TERM_INT_PSS", - "wires": [ - "DUMMYFOO" - ] + "wires": { + "DUMMYFOO": null + } } diff --git a/zynq7/tile_type_B_TERM_VBRK.json b/zynq7/tile_type_B_TERM_VBRK.json index 8c3dacf..06424d2 100644 --- a/zynq7/tile_type_B_TERM_VBRK.json +++ b/zynq7/tile_type_B_TERM_VBRK.json @@ -2,7 +2,7 @@ "pips": {}, "sites": [], "tile_type": "B_TERM_VBRK", - "wires": [ - "DUMMYFOO" - ] + "wires": { + "DUMMYFOO": null + } } diff --git a/zynq7/tile_type_CFG_CENTER_BOT.json b/zynq7/tile_type_CFG_CENTER_BOT.json index 0fe8bfe..37f2b39 100644 --- a/zynq7/tile_type_CFG_CENTER_BOT.json +++ b/zynq7/tile_type_CFG_CENTER_BOT.json @@ -2,4512 +2,16895 @@ "pips": { "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA10->CFG_CENTER_LOGIC_OUTS_B21_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA10" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA11->CFG_CENTER_LOGIC_OUTS_B22_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA11" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA12->CFG_CENTER_LOGIC_OUTS_B23_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA12" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA13->CFG_CENTER_LOGIC_OUTS_B10_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA13" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA14->CFG_CENTER_LOGIC_OUTS_B11_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA14" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA2->CFG_CENTER_LOGIC_OUTS_B13_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA2" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA3->CFG_CENTER_LOGIC_OUTS_B14_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA3" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA4->CFG_CENTER_LOGIC_OUTS_B15_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA4" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA5->CFG_CENTER_LOGIC_OUTS_B16_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA5" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA6->CFG_CENTER_LOGIC_OUTS_B17_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA6" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA7->CFG_CENTER_LOGIC_OUTS_B18_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA7" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA8->CFG_CENTER_LOGIC_OUTS_B19_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA8" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA9->CFG_CENTER_LOGIC_OUTS_B20_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA9" } }, "sites": [], "tile_type": "CFG_CENTER_BOT", - "wires": [ - "CFG_CENTER_BLOCK_OUTS_B0_0", - "CFG_CENTER_BLOCK_OUTS_B0_1", - "CFG_CENTER_BLOCK_OUTS_B0_10", - "CFG_CENTER_BLOCK_OUTS_B0_11", - "CFG_CENTER_BLOCK_OUTS_B0_12", - "CFG_CENTER_BLOCK_OUTS_B0_13", - "CFG_CENTER_BLOCK_OUTS_B0_14", - "CFG_CENTER_BLOCK_OUTS_B0_15", - "CFG_CENTER_BLOCK_OUTS_B0_16", - "CFG_CENTER_BLOCK_OUTS_B0_17", - "CFG_CENTER_BLOCK_OUTS_B0_18", - "CFG_CENTER_BLOCK_OUTS_B0_19", - "CFG_CENTER_BLOCK_OUTS_B0_2", - "CFG_CENTER_BLOCK_OUTS_B0_3", - "CFG_CENTER_BLOCK_OUTS_B0_4", - "CFG_CENTER_BLOCK_OUTS_B0_5", - "CFG_CENTER_BLOCK_OUTS_B0_6", - "CFG_CENTER_BLOCK_OUTS_B0_7", - "CFG_CENTER_BLOCK_OUTS_B0_8", - "CFG_CENTER_BLOCK_OUTS_B0_9", - "CFG_CENTER_BLOCK_OUTS_B1_0", - "CFG_CENTER_BLOCK_OUTS_B1_1", - "CFG_CENTER_BLOCK_OUTS_B1_10", - "CFG_CENTER_BLOCK_OUTS_B1_11", - "CFG_CENTER_BLOCK_OUTS_B1_12", - "CFG_CENTER_BLOCK_OUTS_B1_13", - "CFG_CENTER_BLOCK_OUTS_B1_14", - "CFG_CENTER_BLOCK_OUTS_B1_15", - "CFG_CENTER_BLOCK_OUTS_B1_16", - "CFG_CENTER_BLOCK_OUTS_B1_17", - "CFG_CENTER_BLOCK_OUTS_B1_18", - "CFG_CENTER_BLOCK_OUTS_B1_19", - "CFG_CENTER_BLOCK_OUTS_B1_2", - "CFG_CENTER_BLOCK_OUTS_B1_3", - "CFG_CENTER_BLOCK_OUTS_B1_4", - "CFG_CENTER_BLOCK_OUTS_B1_5", - "CFG_CENTER_BLOCK_OUTS_B1_6", - "CFG_CENTER_BLOCK_OUTS_B1_7", - "CFG_CENTER_BLOCK_OUTS_B1_8", - "CFG_CENTER_BLOCK_OUTS_B1_9", - "CFG_CENTER_BLOCK_OUTS_B2_0", - "CFG_CENTER_BLOCK_OUTS_B2_1", - "CFG_CENTER_BLOCK_OUTS_B2_10", - "CFG_CENTER_BLOCK_OUTS_B2_11", - "CFG_CENTER_BLOCK_OUTS_B2_12", - "CFG_CENTER_BLOCK_OUTS_B2_13", - "CFG_CENTER_BLOCK_OUTS_B2_14", - "CFG_CENTER_BLOCK_OUTS_B2_15", - "CFG_CENTER_BLOCK_OUTS_B2_16", - "CFG_CENTER_BLOCK_OUTS_B2_17", - "CFG_CENTER_BLOCK_OUTS_B2_18", - "CFG_CENTER_BLOCK_OUTS_B2_19", - "CFG_CENTER_BLOCK_OUTS_B2_2", - "CFG_CENTER_BLOCK_OUTS_B2_3", - "CFG_CENTER_BLOCK_OUTS_B2_4", - "CFG_CENTER_BLOCK_OUTS_B2_5", - "CFG_CENTER_BLOCK_OUTS_B2_6", - "CFG_CENTER_BLOCK_OUTS_B2_7", - "CFG_CENTER_BLOCK_OUTS_B2_8", - "CFG_CENTER_BLOCK_OUTS_B2_9", - "CFG_CENTER_BLOCK_OUTS_B3_0", - "CFG_CENTER_BLOCK_OUTS_B3_1", - "CFG_CENTER_BLOCK_OUTS_B3_10", - "CFG_CENTER_BLOCK_OUTS_B3_11", - "CFG_CENTER_BLOCK_OUTS_B3_12", - "CFG_CENTER_BLOCK_OUTS_B3_13", - "CFG_CENTER_BLOCK_OUTS_B3_14", - "CFG_CENTER_BLOCK_OUTS_B3_15", - "CFG_CENTER_BLOCK_OUTS_B3_16", - "CFG_CENTER_BLOCK_OUTS_B3_17", - "CFG_CENTER_BLOCK_OUTS_B3_18", - "CFG_CENTER_BLOCK_OUTS_B3_19", - "CFG_CENTER_BLOCK_OUTS_B3_2", - "CFG_CENTER_BLOCK_OUTS_B3_3", - "CFG_CENTER_BLOCK_OUTS_B3_4", - "CFG_CENTER_BLOCK_OUTS_B3_5", - "CFG_CENTER_BLOCK_OUTS_B3_6", - "CFG_CENTER_BLOCK_OUTS_B3_7", - "CFG_CENTER_BLOCK_OUTS_B3_8", - "CFG_CENTER_BLOCK_OUTS_B3_9", - "CFG_CENTER_BOT_CFG_IO_ACCESS_VGGCOMPOUT", - "CFG_CENTER_BOT_USR_ACCESS_DATA10", - "CFG_CENTER_BOT_USR_ACCESS_DATA11", - "CFG_CENTER_BOT_USR_ACCESS_DATA12", - "CFG_CENTER_BOT_USR_ACCESS_DATA13", - "CFG_CENTER_BOT_USR_ACCESS_DATA14", - "CFG_CENTER_BOT_USR_ACCESS_DATA2", - "CFG_CENTER_BOT_USR_ACCESS_DATA3", - "CFG_CENTER_BOT_USR_ACCESS_DATA4", - "CFG_CENTER_BOT_USR_ACCESS_DATA5", - "CFG_CENTER_BOT_USR_ACCESS_DATA6", - "CFG_CENTER_BOT_USR_ACCESS_DATA7", - "CFG_CENTER_BOT_USR_ACCESS_DATA8", - "CFG_CENTER_BOT_USR_ACCESS_DATA9", - "CFG_CENTER_BYP0_0", - "CFG_CENTER_BYP0_1", - "CFG_CENTER_BYP0_10", - "CFG_CENTER_BYP0_11", - "CFG_CENTER_BYP0_12", - "CFG_CENTER_BYP0_13", - "CFG_CENTER_BYP0_14", - "CFG_CENTER_BYP0_15", - "CFG_CENTER_BYP0_16", - "CFG_CENTER_BYP0_17", - "CFG_CENTER_BYP0_18", - "CFG_CENTER_BYP0_19", - "CFG_CENTER_BYP0_2", - "CFG_CENTER_BYP0_3", - "CFG_CENTER_BYP0_4", - "CFG_CENTER_BYP0_5", - "CFG_CENTER_BYP0_6", - "CFG_CENTER_BYP0_7", - "CFG_CENTER_BYP0_8", - "CFG_CENTER_BYP0_9", - "CFG_CENTER_BYP1_0", - "CFG_CENTER_BYP1_1", - "CFG_CENTER_BYP1_10", - "CFG_CENTER_BYP1_11", - "CFG_CENTER_BYP1_12", - "CFG_CENTER_BYP1_13", - "CFG_CENTER_BYP1_14", - "CFG_CENTER_BYP1_15", - "CFG_CENTER_BYP1_16", - "CFG_CENTER_BYP1_17", - "CFG_CENTER_BYP1_18", - "CFG_CENTER_BYP1_19", - "CFG_CENTER_BYP1_2", - "CFG_CENTER_BYP1_3", - "CFG_CENTER_BYP1_4", - "CFG_CENTER_BYP1_5", - "CFG_CENTER_BYP1_6", - "CFG_CENTER_BYP1_7", - "CFG_CENTER_BYP1_8", - "CFG_CENTER_BYP1_9", - "CFG_CENTER_BYP2_0", - "CFG_CENTER_BYP2_1", - "CFG_CENTER_BYP2_10", - "CFG_CENTER_BYP2_11", - "CFG_CENTER_BYP2_12", - "CFG_CENTER_BYP2_13", - "CFG_CENTER_BYP2_14", - "CFG_CENTER_BYP2_15", - "CFG_CENTER_BYP2_16", - "CFG_CENTER_BYP2_17", - "CFG_CENTER_BYP2_18", - "CFG_CENTER_BYP2_19", - "CFG_CENTER_BYP2_2", - "CFG_CENTER_BYP2_3", - "CFG_CENTER_BYP2_4", - "CFG_CENTER_BYP2_5", - "CFG_CENTER_BYP2_6", - "CFG_CENTER_BYP2_7", - "CFG_CENTER_BYP2_8", - "CFG_CENTER_BYP2_9", - "CFG_CENTER_BYP3_0", - "CFG_CENTER_BYP3_1", - "CFG_CENTER_BYP3_10", - "CFG_CENTER_BYP3_11", - "CFG_CENTER_BYP3_12", - "CFG_CENTER_BYP3_13", - "CFG_CENTER_BYP3_14", - "CFG_CENTER_BYP3_15", - "CFG_CENTER_BYP3_16", - "CFG_CENTER_BYP3_17", - "CFG_CENTER_BYP3_18", - "CFG_CENTER_BYP3_19", - "CFG_CENTER_BYP3_2", - "CFG_CENTER_BYP3_3", - "CFG_CENTER_BYP3_4", - "CFG_CENTER_BYP3_5", - "CFG_CENTER_BYP3_6", - "CFG_CENTER_BYP3_7", - "CFG_CENTER_BYP3_8", - "CFG_CENTER_BYP3_9", - "CFG_CENTER_BYP4_0", - "CFG_CENTER_BYP4_1", - "CFG_CENTER_BYP4_10", - "CFG_CENTER_BYP4_11", - "CFG_CENTER_BYP4_12", - "CFG_CENTER_BYP4_13", - "CFG_CENTER_BYP4_14", - "CFG_CENTER_BYP4_15", - "CFG_CENTER_BYP4_16", - "CFG_CENTER_BYP4_17", - "CFG_CENTER_BYP4_18", - "CFG_CENTER_BYP4_19", - "CFG_CENTER_BYP4_2", - "CFG_CENTER_BYP4_3", - "CFG_CENTER_BYP4_4", - "CFG_CENTER_BYP4_5", - "CFG_CENTER_BYP4_6", - "CFG_CENTER_BYP4_7", - "CFG_CENTER_BYP4_8", - "CFG_CENTER_BYP4_9", - "CFG_CENTER_BYP5_0", - "CFG_CENTER_BYP5_1", - "CFG_CENTER_BYP5_10", - "CFG_CENTER_BYP5_11", - "CFG_CENTER_BYP5_12", - "CFG_CENTER_BYP5_13", - "CFG_CENTER_BYP5_14", - "CFG_CENTER_BYP5_15", - "CFG_CENTER_BYP5_16", - "CFG_CENTER_BYP5_17", - "CFG_CENTER_BYP5_18", - "CFG_CENTER_BYP5_19", - "CFG_CENTER_BYP5_2", - "CFG_CENTER_BYP5_3", - "CFG_CENTER_BYP5_4", - "CFG_CENTER_BYP5_5", - "CFG_CENTER_BYP5_6", - "CFG_CENTER_BYP5_7", - "CFG_CENTER_BYP5_8", - "CFG_CENTER_BYP5_9", - "CFG_CENTER_BYP6_0", - "CFG_CENTER_BYP6_1", - "CFG_CENTER_BYP6_10", - "CFG_CENTER_BYP6_11", - "CFG_CENTER_BYP6_12", - "CFG_CENTER_BYP6_13", - "CFG_CENTER_BYP6_14", - "CFG_CENTER_BYP6_15", - "CFG_CENTER_BYP6_16", - "CFG_CENTER_BYP6_17", - "CFG_CENTER_BYP6_18", - "CFG_CENTER_BYP6_19", - "CFG_CENTER_BYP6_2", - "CFG_CENTER_BYP6_3", - "CFG_CENTER_BYP6_4", - "CFG_CENTER_BYP6_5", - "CFG_CENTER_BYP6_6", - "CFG_CENTER_BYP6_7", - "CFG_CENTER_BYP6_8", - "CFG_CENTER_BYP6_9", - "CFG_CENTER_BYP7_0", - "CFG_CENTER_BYP7_1", - "CFG_CENTER_BYP7_10", - "CFG_CENTER_BYP7_11", - "CFG_CENTER_BYP7_12", - "CFG_CENTER_BYP7_13", - "CFG_CENTER_BYP7_14", - "CFG_CENTER_BYP7_15", - "CFG_CENTER_BYP7_16", - "CFG_CENTER_BYP7_17", - "CFG_CENTER_BYP7_18", - "CFG_CENTER_BYP7_19", - "CFG_CENTER_BYP7_2", - "CFG_CENTER_BYP7_3", - "CFG_CENTER_BYP7_4", - "CFG_CENTER_BYP7_5", - "CFG_CENTER_BYP7_6", - "CFG_CENTER_BYP7_7", - "CFG_CENTER_BYP7_8", - "CFG_CENTER_BYP7_9", - "CFG_CENTER_CLK0_0", - "CFG_CENTER_CLK0_1", - "CFG_CENTER_CLK0_10", - "CFG_CENTER_CLK0_11", - "CFG_CENTER_CLK0_12", - "CFG_CENTER_CLK0_13", - "CFG_CENTER_CLK0_14", - "CFG_CENTER_CLK0_15", - "CFG_CENTER_CLK0_16", - "CFG_CENTER_CLK0_17", - "CFG_CENTER_CLK0_18", - "CFG_CENTER_CLK0_19", - "CFG_CENTER_CLK0_2", - "CFG_CENTER_CLK0_3", - "CFG_CENTER_CLK0_4", - "CFG_CENTER_CLK0_5", - "CFG_CENTER_CLK0_6", - "CFG_CENTER_CLK0_7", - "CFG_CENTER_CLK0_8", - "CFG_CENTER_CLK0_9", - "CFG_CENTER_CLK1_0", - "CFG_CENTER_CLK1_1", - "CFG_CENTER_CLK1_10", - "CFG_CENTER_CLK1_11", - "CFG_CENTER_CLK1_12", - "CFG_CENTER_CLK1_13", - "CFG_CENTER_CLK1_14", - "CFG_CENTER_CLK1_15", - "CFG_CENTER_CLK1_16", - "CFG_CENTER_CLK1_17", - "CFG_CENTER_CLK1_18", - "CFG_CENTER_CLK1_19", - "CFG_CENTER_CLK1_2", - "CFG_CENTER_CLK1_3", - "CFG_CENTER_CLK1_4", - "CFG_CENTER_CLK1_5", - "CFG_CENTER_CLK1_6", - "CFG_CENTER_CLK1_7", - "CFG_CENTER_CLK1_8", - "CFG_CENTER_CLK1_9", - "CFG_CENTER_CTRL0_0", - "CFG_CENTER_CTRL0_1", - "CFG_CENTER_CTRL0_10", - "CFG_CENTER_CTRL0_11", - "CFG_CENTER_CTRL0_12", - "CFG_CENTER_CTRL0_13", - "CFG_CENTER_CTRL0_14", - "CFG_CENTER_CTRL0_15", - "CFG_CENTER_CTRL0_16", - "CFG_CENTER_CTRL0_17", - "CFG_CENTER_CTRL0_18", - "CFG_CENTER_CTRL0_19", - "CFG_CENTER_CTRL0_2", - "CFG_CENTER_CTRL0_3", - "CFG_CENTER_CTRL0_4", - "CFG_CENTER_CTRL0_5", - "CFG_CENTER_CTRL0_6", - "CFG_CENTER_CTRL0_7", - "CFG_CENTER_CTRL0_8", - "CFG_CENTER_CTRL0_9", - "CFG_CENTER_CTRL1_0", - "CFG_CENTER_CTRL1_1", - "CFG_CENTER_CTRL1_10", - "CFG_CENTER_CTRL1_11", - "CFG_CENTER_CTRL1_12", - "CFG_CENTER_CTRL1_13", - "CFG_CENTER_CTRL1_14", - "CFG_CENTER_CTRL1_15", - "CFG_CENTER_CTRL1_16", - "CFG_CENTER_CTRL1_17", - "CFG_CENTER_CTRL1_18", - "CFG_CENTER_CTRL1_19", - "CFG_CENTER_CTRL1_2", - "CFG_CENTER_CTRL1_3", - "CFG_CENTER_CTRL1_4", - "CFG_CENTER_CTRL1_5", - "CFG_CENTER_CTRL1_6", - "CFG_CENTER_CTRL1_7", - "CFG_CENTER_CTRL1_8", - "CFG_CENTER_CTRL1_9", - "CFG_CENTER_EE2A0_0", - "CFG_CENTER_EE2A0_1", - "CFG_CENTER_EE2A0_10", - "CFG_CENTER_EE2A0_11", - "CFG_CENTER_EE2A0_12", - "CFG_CENTER_EE2A0_13", - "CFG_CENTER_EE2A0_14", - "CFG_CENTER_EE2A0_15", - "CFG_CENTER_EE2A0_16", - "CFG_CENTER_EE2A0_17", - "CFG_CENTER_EE2A0_18", - "CFG_CENTER_EE2A0_19", - "CFG_CENTER_EE2A0_2", - "CFG_CENTER_EE2A0_3", - "CFG_CENTER_EE2A0_4", - "CFG_CENTER_EE2A0_5", - "CFG_CENTER_EE2A0_6", - "CFG_CENTER_EE2A0_7", - "CFG_CENTER_EE2A0_8", - "CFG_CENTER_EE2A0_9", - "CFG_CENTER_EE2A1_0", - "CFG_CENTER_EE2A1_1", - "CFG_CENTER_EE2A1_10", - "CFG_CENTER_EE2A1_11", - "CFG_CENTER_EE2A1_12", - "CFG_CENTER_EE2A1_13", - "CFG_CENTER_EE2A1_14", - "CFG_CENTER_EE2A1_15", - "CFG_CENTER_EE2A1_16", - "CFG_CENTER_EE2A1_17", - "CFG_CENTER_EE2A1_18", - "CFG_CENTER_EE2A1_19", - "CFG_CENTER_EE2A1_2", - "CFG_CENTER_EE2A1_3", - "CFG_CENTER_EE2A1_4", - "CFG_CENTER_EE2A1_5", - "CFG_CENTER_EE2A1_6", - "CFG_CENTER_EE2A1_7", - "CFG_CENTER_EE2A1_8", - "CFG_CENTER_EE2A1_9", - "CFG_CENTER_EE2A2_0", - "CFG_CENTER_EE2A2_1", - "CFG_CENTER_EE2A2_10", - "CFG_CENTER_EE2A2_11", - "CFG_CENTER_EE2A2_12", - "CFG_CENTER_EE2A2_13", - "CFG_CENTER_EE2A2_14", - "CFG_CENTER_EE2A2_15", - "CFG_CENTER_EE2A2_16", - "CFG_CENTER_EE2A2_17", - "CFG_CENTER_EE2A2_18", - "CFG_CENTER_EE2A2_19", - "CFG_CENTER_EE2A2_2", - "CFG_CENTER_EE2A2_3", - "CFG_CENTER_EE2A2_4", - "CFG_CENTER_EE2A2_5", - "CFG_CENTER_EE2A2_6", - "CFG_CENTER_EE2A2_7", - "CFG_CENTER_EE2A2_8", - "CFG_CENTER_EE2A2_9", - "CFG_CENTER_EE2A3_0", - "CFG_CENTER_EE2A3_1", - "CFG_CENTER_EE2A3_10", - "CFG_CENTER_EE2A3_11", - "CFG_CENTER_EE2A3_12", - "CFG_CENTER_EE2A3_13", - "CFG_CENTER_EE2A3_14", - "CFG_CENTER_EE2A3_15", - "CFG_CENTER_EE2A3_16", - "CFG_CENTER_EE2A3_17", - "CFG_CENTER_EE2A3_18", - "CFG_CENTER_EE2A3_19", - "CFG_CENTER_EE2A3_2", - "CFG_CENTER_EE2A3_3", - "CFG_CENTER_EE2A3_4", - "CFG_CENTER_EE2A3_5", - "CFG_CENTER_EE2A3_6", - "CFG_CENTER_EE2A3_7", - "CFG_CENTER_EE2A3_8", - "CFG_CENTER_EE2A3_9", - "CFG_CENTER_EE2BEG0_0", - "CFG_CENTER_EE2BEG0_1", - "CFG_CENTER_EE2BEG0_10", - "CFG_CENTER_EE2BEG0_11", - "CFG_CENTER_EE2BEG0_12", - "CFG_CENTER_EE2BEG0_13", - "CFG_CENTER_EE2BEG0_14", - "CFG_CENTER_EE2BEG0_15", - "CFG_CENTER_EE2BEG0_16", - "CFG_CENTER_EE2BEG0_17", - "CFG_CENTER_EE2BEG0_18", - "CFG_CENTER_EE2BEG0_19", - "CFG_CENTER_EE2BEG0_2", - "CFG_CENTER_EE2BEG0_3", - "CFG_CENTER_EE2BEG0_4", - "CFG_CENTER_EE2BEG0_5", - "CFG_CENTER_EE2BEG0_6", - "CFG_CENTER_EE2BEG0_7", - "CFG_CENTER_EE2BEG0_8", - "CFG_CENTER_EE2BEG0_9", - "CFG_CENTER_EE2BEG1_0", - "CFG_CENTER_EE2BEG1_1", - "CFG_CENTER_EE2BEG1_10", - "CFG_CENTER_EE2BEG1_11", - "CFG_CENTER_EE2BEG1_12", - "CFG_CENTER_EE2BEG1_13", - "CFG_CENTER_EE2BEG1_14", - "CFG_CENTER_EE2BEG1_15", - "CFG_CENTER_EE2BEG1_16", - "CFG_CENTER_EE2BEG1_17", - "CFG_CENTER_EE2BEG1_18", - "CFG_CENTER_EE2BEG1_19", - "CFG_CENTER_EE2BEG1_2", - "CFG_CENTER_EE2BEG1_3", - "CFG_CENTER_EE2BEG1_4", - "CFG_CENTER_EE2BEG1_5", - "CFG_CENTER_EE2BEG1_6", - "CFG_CENTER_EE2BEG1_7", - "CFG_CENTER_EE2BEG1_8", - "CFG_CENTER_EE2BEG1_9", - "CFG_CENTER_EE2BEG2_0", - "CFG_CENTER_EE2BEG2_1", - "CFG_CENTER_EE2BEG2_10", - "CFG_CENTER_EE2BEG2_11", - "CFG_CENTER_EE2BEG2_12", - "CFG_CENTER_EE2BEG2_13", - "CFG_CENTER_EE2BEG2_14", - "CFG_CENTER_EE2BEG2_15", - "CFG_CENTER_EE2BEG2_16", - "CFG_CENTER_EE2BEG2_17", - "CFG_CENTER_EE2BEG2_18", - "CFG_CENTER_EE2BEG2_19", - "CFG_CENTER_EE2BEG2_2", - "CFG_CENTER_EE2BEG2_3", - "CFG_CENTER_EE2BEG2_4", - "CFG_CENTER_EE2BEG2_5", - "CFG_CENTER_EE2BEG2_6", - "CFG_CENTER_EE2BEG2_7", - "CFG_CENTER_EE2BEG2_8", - "CFG_CENTER_EE2BEG2_9", - "CFG_CENTER_EE2BEG3_0", - "CFG_CENTER_EE2BEG3_1", - "CFG_CENTER_EE2BEG3_10", - "CFG_CENTER_EE2BEG3_11", - "CFG_CENTER_EE2BEG3_12", - "CFG_CENTER_EE2BEG3_13", - "CFG_CENTER_EE2BEG3_14", - "CFG_CENTER_EE2BEG3_15", - "CFG_CENTER_EE2BEG3_16", - "CFG_CENTER_EE2BEG3_17", - "CFG_CENTER_EE2BEG3_18", - "CFG_CENTER_EE2BEG3_19", - "CFG_CENTER_EE2BEG3_2", - "CFG_CENTER_EE2BEG3_3", - "CFG_CENTER_EE2BEG3_4", - "CFG_CENTER_EE2BEG3_5", - "CFG_CENTER_EE2BEG3_6", - "CFG_CENTER_EE2BEG3_7", - "CFG_CENTER_EE2BEG3_8", - "CFG_CENTER_EE2BEG3_9", - "CFG_CENTER_EE4A0_0", - "CFG_CENTER_EE4A0_1", - "CFG_CENTER_EE4A0_10", - "CFG_CENTER_EE4A0_11", - "CFG_CENTER_EE4A0_12", - "CFG_CENTER_EE4A0_13", - "CFG_CENTER_EE4A0_14", - "CFG_CENTER_EE4A0_15", - "CFG_CENTER_EE4A0_16", - "CFG_CENTER_EE4A0_17", - "CFG_CENTER_EE4A0_18", - "CFG_CENTER_EE4A0_19", - "CFG_CENTER_EE4A0_2", - "CFG_CENTER_EE4A0_3", - "CFG_CENTER_EE4A0_4", - "CFG_CENTER_EE4A0_5", - "CFG_CENTER_EE4A0_6", - "CFG_CENTER_EE4A0_7", - "CFG_CENTER_EE4A0_8", - "CFG_CENTER_EE4A0_9", - "CFG_CENTER_EE4A1_0", - "CFG_CENTER_EE4A1_1", - "CFG_CENTER_EE4A1_10", - "CFG_CENTER_EE4A1_11", - "CFG_CENTER_EE4A1_12", - "CFG_CENTER_EE4A1_13", - "CFG_CENTER_EE4A1_14", - "CFG_CENTER_EE4A1_15", - "CFG_CENTER_EE4A1_16", - "CFG_CENTER_EE4A1_17", - "CFG_CENTER_EE4A1_18", - "CFG_CENTER_EE4A1_19", - "CFG_CENTER_EE4A1_2", - "CFG_CENTER_EE4A1_3", - "CFG_CENTER_EE4A1_4", - "CFG_CENTER_EE4A1_5", - "CFG_CENTER_EE4A1_6", - "CFG_CENTER_EE4A1_7", - "CFG_CENTER_EE4A1_8", - "CFG_CENTER_EE4A1_9", - "CFG_CENTER_EE4A2_0", - "CFG_CENTER_EE4A2_1", - "CFG_CENTER_EE4A2_10", - "CFG_CENTER_EE4A2_11", - "CFG_CENTER_EE4A2_12", - "CFG_CENTER_EE4A2_13", - "CFG_CENTER_EE4A2_14", - "CFG_CENTER_EE4A2_15", - "CFG_CENTER_EE4A2_16", - "CFG_CENTER_EE4A2_17", - "CFG_CENTER_EE4A2_18", - "CFG_CENTER_EE4A2_19", - "CFG_CENTER_EE4A2_2", - "CFG_CENTER_EE4A2_3", - "CFG_CENTER_EE4A2_4", - "CFG_CENTER_EE4A2_5", - "CFG_CENTER_EE4A2_6", - "CFG_CENTER_EE4A2_7", - "CFG_CENTER_EE4A2_8", - "CFG_CENTER_EE4A2_9", - "CFG_CENTER_EE4A3_0", - "CFG_CENTER_EE4A3_1", - "CFG_CENTER_EE4A3_10", - "CFG_CENTER_EE4A3_11", - "CFG_CENTER_EE4A3_12", - "CFG_CENTER_EE4A3_13", - "CFG_CENTER_EE4A3_14", - "CFG_CENTER_EE4A3_15", - "CFG_CENTER_EE4A3_16", - "CFG_CENTER_EE4A3_17", - "CFG_CENTER_EE4A3_18", - "CFG_CENTER_EE4A3_19", - "CFG_CENTER_EE4A3_2", - "CFG_CENTER_EE4A3_3", - "CFG_CENTER_EE4A3_4", - "CFG_CENTER_EE4A3_5", - "CFG_CENTER_EE4A3_6", - "CFG_CENTER_EE4A3_7", - "CFG_CENTER_EE4A3_8", - "CFG_CENTER_EE4A3_9", - "CFG_CENTER_EE4B0_0", - "CFG_CENTER_EE4B0_1", - "CFG_CENTER_EE4B0_10", - "CFG_CENTER_EE4B0_11", - "CFG_CENTER_EE4B0_12", - "CFG_CENTER_EE4B0_13", - "CFG_CENTER_EE4B0_14", - "CFG_CENTER_EE4B0_15", - "CFG_CENTER_EE4B0_16", - "CFG_CENTER_EE4B0_17", - "CFG_CENTER_EE4B0_18", - "CFG_CENTER_EE4B0_19", - "CFG_CENTER_EE4B0_2", - "CFG_CENTER_EE4B0_3", - "CFG_CENTER_EE4B0_4", - "CFG_CENTER_EE4B0_5", - "CFG_CENTER_EE4B0_6", - "CFG_CENTER_EE4B0_7", - "CFG_CENTER_EE4B0_8", - "CFG_CENTER_EE4B0_9", - "CFG_CENTER_EE4B1_0", - "CFG_CENTER_EE4B1_1", - "CFG_CENTER_EE4B1_10", - "CFG_CENTER_EE4B1_11", - "CFG_CENTER_EE4B1_12", - "CFG_CENTER_EE4B1_13", - "CFG_CENTER_EE4B1_14", - "CFG_CENTER_EE4B1_15", - "CFG_CENTER_EE4B1_16", - "CFG_CENTER_EE4B1_17", - "CFG_CENTER_EE4B1_18", - "CFG_CENTER_EE4B1_19", - "CFG_CENTER_EE4B1_2", - "CFG_CENTER_EE4B1_3", - "CFG_CENTER_EE4B1_4", - "CFG_CENTER_EE4B1_5", - "CFG_CENTER_EE4B1_6", - "CFG_CENTER_EE4B1_7", - "CFG_CENTER_EE4B1_8", - "CFG_CENTER_EE4B1_9", - "CFG_CENTER_EE4B2_0", - "CFG_CENTER_EE4B2_1", - "CFG_CENTER_EE4B2_10", - "CFG_CENTER_EE4B2_11", - "CFG_CENTER_EE4B2_12", - "CFG_CENTER_EE4B2_13", - "CFG_CENTER_EE4B2_14", - "CFG_CENTER_EE4B2_15", - "CFG_CENTER_EE4B2_16", - "CFG_CENTER_EE4B2_17", - "CFG_CENTER_EE4B2_18", - "CFG_CENTER_EE4B2_19", - "CFG_CENTER_EE4B2_2", - "CFG_CENTER_EE4B2_3", - "CFG_CENTER_EE4B2_4", - "CFG_CENTER_EE4B2_5", - "CFG_CENTER_EE4B2_6", - "CFG_CENTER_EE4B2_7", - "CFG_CENTER_EE4B2_8", - "CFG_CENTER_EE4B2_9", - "CFG_CENTER_EE4B3_0", - "CFG_CENTER_EE4B3_1", - "CFG_CENTER_EE4B3_10", - "CFG_CENTER_EE4B3_11", - "CFG_CENTER_EE4B3_12", - "CFG_CENTER_EE4B3_13", - "CFG_CENTER_EE4B3_14", - "CFG_CENTER_EE4B3_15", - "CFG_CENTER_EE4B3_16", - "CFG_CENTER_EE4B3_17", - "CFG_CENTER_EE4B3_18", - "CFG_CENTER_EE4B3_19", - "CFG_CENTER_EE4B3_2", - "CFG_CENTER_EE4B3_3", - "CFG_CENTER_EE4B3_4", - "CFG_CENTER_EE4B3_5", - "CFG_CENTER_EE4B3_6", - "CFG_CENTER_EE4B3_7", - "CFG_CENTER_EE4B3_8", - "CFG_CENTER_EE4B3_9", - "CFG_CENTER_EE4BEG0_0", - "CFG_CENTER_EE4BEG0_1", - "CFG_CENTER_EE4BEG0_10", - "CFG_CENTER_EE4BEG0_11", - "CFG_CENTER_EE4BEG0_12", - "CFG_CENTER_EE4BEG0_13", - "CFG_CENTER_EE4BEG0_14", - "CFG_CENTER_EE4BEG0_15", - "CFG_CENTER_EE4BEG0_16", - "CFG_CENTER_EE4BEG0_17", - "CFG_CENTER_EE4BEG0_18", - "CFG_CENTER_EE4BEG0_19", - "CFG_CENTER_EE4BEG0_2", - "CFG_CENTER_EE4BEG0_3", - "CFG_CENTER_EE4BEG0_4", - "CFG_CENTER_EE4BEG0_5", - "CFG_CENTER_EE4BEG0_6", - "CFG_CENTER_EE4BEG0_7", - "CFG_CENTER_EE4BEG0_8", - "CFG_CENTER_EE4BEG0_9", - "CFG_CENTER_EE4BEG1_0", - "CFG_CENTER_EE4BEG1_1", - "CFG_CENTER_EE4BEG1_10", - "CFG_CENTER_EE4BEG1_11", - "CFG_CENTER_EE4BEG1_12", - "CFG_CENTER_EE4BEG1_13", - "CFG_CENTER_EE4BEG1_14", - "CFG_CENTER_EE4BEG1_15", - "CFG_CENTER_EE4BEG1_16", - "CFG_CENTER_EE4BEG1_17", - "CFG_CENTER_EE4BEG1_18", - "CFG_CENTER_EE4BEG1_19", - "CFG_CENTER_EE4BEG1_2", - "CFG_CENTER_EE4BEG1_3", - "CFG_CENTER_EE4BEG1_4", - "CFG_CENTER_EE4BEG1_5", - "CFG_CENTER_EE4BEG1_6", - "CFG_CENTER_EE4BEG1_7", - "CFG_CENTER_EE4BEG1_8", - "CFG_CENTER_EE4BEG1_9", - "CFG_CENTER_EE4BEG2_0", - "CFG_CENTER_EE4BEG2_1", - "CFG_CENTER_EE4BEG2_10", - "CFG_CENTER_EE4BEG2_11", - "CFG_CENTER_EE4BEG2_12", - "CFG_CENTER_EE4BEG2_13", - "CFG_CENTER_EE4BEG2_14", - "CFG_CENTER_EE4BEG2_15", - "CFG_CENTER_EE4BEG2_16", - "CFG_CENTER_EE4BEG2_17", - "CFG_CENTER_EE4BEG2_18", - "CFG_CENTER_EE4BEG2_19", - "CFG_CENTER_EE4BEG2_2", - "CFG_CENTER_EE4BEG2_3", - "CFG_CENTER_EE4BEG2_4", - "CFG_CENTER_EE4BEG2_5", - "CFG_CENTER_EE4BEG2_6", - "CFG_CENTER_EE4BEG2_7", - "CFG_CENTER_EE4BEG2_8", - "CFG_CENTER_EE4BEG2_9", - "CFG_CENTER_EE4BEG3_0", - "CFG_CENTER_EE4BEG3_1", - "CFG_CENTER_EE4BEG3_10", - "CFG_CENTER_EE4BEG3_11", - "CFG_CENTER_EE4BEG3_12", - "CFG_CENTER_EE4BEG3_13", - "CFG_CENTER_EE4BEG3_14", - "CFG_CENTER_EE4BEG3_15", - "CFG_CENTER_EE4BEG3_16", - "CFG_CENTER_EE4BEG3_17", - "CFG_CENTER_EE4BEG3_18", - "CFG_CENTER_EE4BEG3_19", - "CFG_CENTER_EE4BEG3_2", - "CFG_CENTER_EE4BEG3_3", - "CFG_CENTER_EE4BEG3_4", - "CFG_CENTER_EE4BEG3_5", - "CFG_CENTER_EE4BEG3_6", - "CFG_CENTER_EE4BEG3_7", - "CFG_CENTER_EE4BEG3_8", - "CFG_CENTER_EE4BEG3_9", - "CFG_CENTER_EE4C0_0", - "CFG_CENTER_EE4C0_1", - "CFG_CENTER_EE4C0_10", - "CFG_CENTER_EE4C0_11", - "CFG_CENTER_EE4C0_12", - "CFG_CENTER_EE4C0_13", - "CFG_CENTER_EE4C0_14", - "CFG_CENTER_EE4C0_15", - "CFG_CENTER_EE4C0_16", - "CFG_CENTER_EE4C0_17", - "CFG_CENTER_EE4C0_18", - "CFG_CENTER_EE4C0_19", - "CFG_CENTER_EE4C0_2", - "CFG_CENTER_EE4C0_3", - "CFG_CENTER_EE4C0_4", - "CFG_CENTER_EE4C0_5", - "CFG_CENTER_EE4C0_6", - "CFG_CENTER_EE4C0_7", - "CFG_CENTER_EE4C0_8", - "CFG_CENTER_EE4C0_9", - "CFG_CENTER_EE4C1_0", - "CFG_CENTER_EE4C1_1", - "CFG_CENTER_EE4C1_10", - "CFG_CENTER_EE4C1_11", - "CFG_CENTER_EE4C1_12", - "CFG_CENTER_EE4C1_13", - "CFG_CENTER_EE4C1_14", - "CFG_CENTER_EE4C1_15", - "CFG_CENTER_EE4C1_16", - "CFG_CENTER_EE4C1_17", - "CFG_CENTER_EE4C1_18", - "CFG_CENTER_EE4C1_19", - "CFG_CENTER_EE4C1_2", - "CFG_CENTER_EE4C1_3", - "CFG_CENTER_EE4C1_4", - "CFG_CENTER_EE4C1_5", - "CFG_CENTER_EE4C1_6", - "CFG_CENTER_EE4C1_7", - "CFG_CENTER_EE4C1_8", - "CFG_CENTER_EE4C1_9", - "CFG_CENTER_EE4C2_0", - "CFG_CENTER_EE4C2_1", - "CFG_CENTER_EE4C2_10", - "CFG_CENTER_EE4C2_11", - "CFG_CENTER_EE4C2_12", - "CFG_CENTER_EE4C2_13", - "CFG_CENTER_EE4C2_14", - "CFG_CENTER_EE4C2_15", - "CFG_CENTER_EE4C2_16", - "CFG_CENTER_EE4C2_17", - "CFG_CENTER_EE4C2_18", - "CFG_CENTER_EE4C2_19", - "CFG_CENTER_EE4C2_2", - "CFG_CENTER_EE4C2_3", - "CFG_CENTER_EE4C2_4", - "CFG_CENTER_EE4C2_5", - "CFG_CENTER_EE4C2_6", - "CFG_CENTER_EE4C2_7", - "CFG_CENTER_EE4C2_8", - "CFG_CENTER_EE4C2_9", - "CFG_CENTER_EE4C3_0", - "CFG_CENTER_EE4C3_1", - "CFG_CENTER_EE4C3_10", - "CFG_CENTER_EE4C3_11", - "CFG_CENTER_EE4C3_12", - "CFG_CENTER_EE4C3_13", - "CFG_CENTER_EE4C3_14", - "CFG_CENTER_EE4C3_15", - "CFG_CENTER_EE4C3_16", - "CFG_CENTER_EE4C3_17", - "CFG_CENTER_EE4C3_18", - "CFG_CENTER_EE4C3_19", - "CFG_CENTER_EE4C3_2", - "CFG_CENTER_EE4C3_3", - "CFG_CENTER_EE4C3_4", - "CFG_CENTER_EE4C3_5", - "CFG_CENTER_EE4C3_6", - "CFG_CENTER_EE4C3_7", - "CFG_CENTER_EE4C3_8", - "CFG_CENTER_EE4C3_9", - "CFG_CENTER_EL1BEG0_0", - "CFG_CENTER_EL1BEG0_1", - "CFG_CENTER_EL1BEG0_10", - "CFG_CENTER_EL1BEG0_11", - "CFG_CENTER_EL1BEG0_12", - "CFG_CENTER_EL1BEG0_13", - "CFG_CENTER_EL1BEG0_14", - "CFG_CENTER_EL1BEG0_15", - "CFG_CENTER_EL1BEG0_16", - "CFG_CENTER_EL1BEG0_17", - "CFG_CENTER_EL1BEG0_18", - "CFG_CENTER_EL1BEG0_19", - "CFG_CENTER_EL1BEG0_2", - "CFG_CENTER_EL1BEG0_3", - "CFG_CENTER_EL1BEG0_4", - "CFG_CENTER_EL1BEG0_5", - "CFG_CENTER_EL1BEG0_6", - "CFG_CENTER_EL1BEG0_7", - "CFG_CENTER_EL1BEG0_8", - "CFG_CENTER_EL1BEG0_9", - "CFG_CENTER_EL1BEG1_0", - "CFG_CENTER_EL1BEG1_1", - "CFG_CENTER_EL1BEG1_10", - "CFG_CENTER_EL1BEG1_11", - "CFG_CENTER_EL1BEG1_12", - "CFG_CENTER_EL1BEG1_13", - "CFG_CENTER_EL1BEG1_14", - "CFG_CENTER_EL1BEG1_15", - "CFG_CENTER_EL1BEG1_16", - "CFG_CENTER_EL1BEG1_17", - "CFG_CENTER_EL1BEG1_18", - "CFG_CENTER_EL1BEG1_19", - "CFG_CENTER_EL1BEG1_2", - "CFG_CENTER_EL1BEG1_3", - "CFG_CENTER_EL1BEG1_4", - "CFG_CENTER_EL1BEG1_5", - "CFG_CENTER_EL1BEG1_6", - "CFG_CENTER_EL1BEG1_7", - "CFG_CENTER_EL1BEG1_8", - "CFG_CENTER_EL1BEG1_9", - "CFG_CENTER_EL1BEG2_0", - "CFG_CENTER_EL1BEG2_1", - "CFG_CENTER_EL1BEG2_10", - "CFG_CENTER_EL1BEG2_11", - "CFG_CENTER_EL1BEG2_12", - "CFG_CENTER_EL1BEG2_13", - "CFG_CENTER_EL1BEG2_14", - "CFG_CENTER_EL1BEG2_15", - "CFG_CENTER_EL1BEG2_16", - "CFG_CENTER_EL1BEG2_17", - "CFG_CENTER_EL1BEG2_18", - "CFG_CENTER_EL1BEG2_19", - "CFG_CENTER_EL1BEG2_2", - "CFG_CENTER_EL1BEG2_3", - "CFG_CENTER_EL1BEG2_4", - "CFG_CENTER_EL1BEG2_5", - "CFG_CENTER_EL1BEG2_6", - "CFG_CENTER_EL1BEG2_7", - "CFG_CENTER_EL1BEG2_8", - "CFG_CENTER_EL1BEG2_9", - "CFG_CENTER_EL1BEG3_0", - "CFG_CENTER_EL1BEG3_1", - "CFG_CENTER_EL1BEG3_10", - "CFG_CENTER_EL1BEG3_11", - "CFG_CENTER_EL1BEG3_12", - "CFG_CENTER_EL1BEG3_13", - "CFG_CENTER_EL1BEG3_14", - "CFG_CENTER_EL1BEG3_15", - "CFG_CENTER_EL1BEG3_16", - "CFG_CENTER_EL1BEG3_17", - "CFG_CENTER_EL1BEG3_18", - "CFG_CENTER_EL1BEG3_19", - "CFG_CENTER_EL1BEG3_2", - "CFG_CENTER_EL1BEG3_3", - "CFG_CENTER_EL1BEG3_4", - "CFG_CENTER_EL1BEG3_5", - "CFG_CENTER_EL1BEG3_6", - "CFG_CENTER_EL1BEG3_7", - "CFG_CENTER_EL1BEG3_8", - "CFG_CENTER_EL1BEG3_9", - "CFG_CENTER_ER1BEG0_0", - "CFG_CENTER_ER1BEG0_1", - "CFG_CENTER_ER1BEG0_10", - "CFG_CENTER_ER1BEG0_11", - "CFG_CENTER_ER1BEG0_12", - "CFG_CENTER_ER1BEG0_13", - "CFG_CENTER_ER1BEG0_14", - "CFG_CENTER_ER1BEG0_15", - "CFG_CENTER_ER1BEG0_16", - "CFG_CENTER_ER1BEG0_17", - "CFG_CENTER_ER1BEG0_18", - "CFG_CENTER_ER1BEG0_19", - "CFG_CENTER_ER1BEG0_2", - "CFG_CENTER_ER1BEG0_3", - "CFG_CENTER_ER1BEG0_4", - "CFG_CENTER_ER1BEG0_5", - "CFG_CENTER_ER1BEG0_6", - "CFG_CENTER_ER1BEG0_7", - "CFG_CENTER_ER1BEG0_8", - "CFG_CENTER_ER1BEG0_9", - "CFG_CENTER_ER1BEG1_0", - "CFG_CENTER_ER1BEG1_1", - "CFG_CENTER_ER1BEG1_10", - "CFG_CENTER_ER1BEG1_11", - "CFG_CENTER_ER1BEG1_12", - "CFG_CENTER_ER1BEG1_13", - "CFG_CENTER_ER1BEG1_14", - "CFG_CENTER_ER1BEG1_15", - "CFG_CENTER_ER1BEG1_16", - "CFG_CENTER_ER1BEG1_17", - "CFG_CENTER_ER1BEG1_18", - "CFG_CENTER_ER1BEG1_19", - "CFG_CENTER_ER1BEG1_2", - "CFG_CENTER_ER1BEG1_3", - "CFG_CENTER_ER1BEG1_4", - "CFG_CENTER_ER1BEG1_5", - "CFG_CENTER_ER1BEG1_6", - "CFG_CENTER_ER1BEG1_7", - "CFG_CENTER_ER1BEG1_8", - "CFG_CENTER_ER1BEG1_9", - "CFG_CENTER_ER1BEG2_0", - "CFG_CENTER_ER1BEG2_1", - "CFG_CENTER_ER1BEG2_10", - "CFG_CENTER_ER1BEG2_11", - "CFG_CENTER_ER1BEG2_12", - "CFG_CENTER_ER1BEG2_13", - "CFG_CENTER_ER1BEG2_14", - "CFG_CENTER_ER1BEG2_15", - "CFG_CENTER_ER1BEG2_16", - "CFG_CENTER_ER1BEG2_17", - "CFG_CENTER_ER1BEG2_18", - "CFG_CENTER_ER1BEG2_19", - "CFG_CENTER_ER1BEG2_2", - "CFG_CENTER_ER1BEG2_3", - "CFG_CENTER_ER1BEG2_4", - "CFG_CENTER_ER1BEG2_5", - "CFG_CENTER_ER1BEG2_6", - "CFG_CENTER_ER1BEG2_7", - "CFG_CENTER_ER1BEG2_8", - "CFG_CENTER_ER1BEG2_9", - "CFG_CENTER_ER1BEG3_0", - "CFG_CENTER_ER1BEG3_1", - "CFG_CENTER_ER1BEG3_10", - "CFG_CENTER_ER1BEG3_11", - "CFG_CENTER_ER1BEG3_12", - "CFG_CENTER_ER1BEG3_13", - "CFG_CENTER_ER1BEG3_14", - "CFG_CENTER_ER1BEG3_15", - "CFG_CENTER_ER1BEG3_16", - "CFG_CENTER_ER1BEG3_17", - "CFG_CENTER_ER1BEG3_18", - "CFG_CENTER_ER1BEG3_19", - "CFG_CENTER_ER1BEG3_2", - "CFG_CENTER_ER1BEG3_3", - "CFG_CENTER_ER1BEG3_4", - "CFG_CENTER_ER1BEG3_5", - "CFG_CENTER_ER1BEG3_6", - "CFG_CENTER_ER1BEG3_7", - "CFG_CENTER_ER1BEG3_8", - "CFG_CENTER_ER1BEG3_9", - "CFG_CENTER_FAN0_0", - "CFG_CENTER_FAN0_1", - "CFG_CENTER_FAN0_10", - "CFG_CENTER_FAN0_11", - "CFG_CENTER_FAN0_12", - "CFG_CENTER_FAN0_13", - "CFG_CENTER_FAN0_14", - "CFG_CENTER_FAN0_15", - "CFG_CENTER_FAN0_16", - "CFG_CENTER_FAN0_17", - "CFG_CENTER_FAN0_18", - "CFG_CENTER_FAN0_19", - "CFG_CENTER_FAN0_2", - "CFG_CENTER_FAN0_3", - "CFG_CENTER_FAN0_4", - "CFG_CENTER_FAN0_5", - "CFG_CENTER_FAN0_6", - "CFG_CENTER_FAN0_7", - "CFG_CENTER_FAN0_8", - "CFG_CENTER_FAN0_9", - "CFG_CENTER_FAN1_0", - "CFG_CENTER_FAN1_1", - "CFG_CENTER_FAN1_10", - "CFG_CENTER_FAN1_11", - "CFG_CENTER_FAN1_12", - "CFG_CENTER_FAN1_13", - "CFG_CENTER_FAN1_14", - "CFG_CENTER_FAN1_15", - "CFG_CENTER_FAN1_16", - "CFG_CENTER_FAN1_17", - "CFG_CENTER_FAN1_18", - "CFG_CENTER_FAN1_19", - "CFG_CENTER_FAN1_2", - "CFG_CENTER_FAN1_3", - "CFG_CENTER_FAN1_4", - "CFG_CENTER_FAN1_5", - "CFG_CENTER_FAN1_6", - "CFG_CENTER_FAN1_7", - "CFG_CENTER_FAN1_8", - "CFG_CENTER_FAN1_9", - "CFG_CENTER_FAN2_0", - "CFG_CENTER_FAN2_1", - "CFG_CENTER_FAN2_10", - "CFG_CENTER_FAN2_11", - "CFG_CENTER_FAN2_12", - "CFG_CENTER_FAN2_13", - "CFG_CENTER_FAN2_14", - "CFG_CENTER_FAN2_15", - "CFG_CENTER_FAN2_16", - "CFG_CENTER_FAN2_17", - "CFG_CENTER_FAN2_18", - "CFG_CENTER_FAN2_19", - "CFG_CENTER_FAN2_2", - "CFG_CENTER_FAN2_3", - "CFG_CENTER_FAN2_4", - "CFG_CENTER_FAN2_5", - "CFG_CENTER_FAN2_6", - "CFG_CENTER_FAN2_7", - "CFG_CENTER_FAN2_8", - "CFG_CENTER_FAN2_9", - "CFG_CENTER_FAN3_0", - "CFG_CENTER_FAN3_1", - "CFG_CENTER_FAN3_10", - "CFG_CENTER_FAN3_11", - "CFG_CENTER_FAN3_12", - "CFG_CENTER_FAN3_13", - "CFG_CENTER_FAN3_14", - "CFG_CENTER_FAN3_15", - "CFG_CENTER_FAN3_16", - "CFG_CENTER_FAN3_17", - "CFG_CENTER_FAN3_18", - "CFG_CENTER_FAN3_19", - "CFG_CENTER_FAN3_2", - "CFG_CENTER_FAN3_3", - "CFG_CENTER_FAN3_4", - "CFG_CENTER_FAN3_5", - "CFG_CENTER_FAN3_6", - "CFG_CENTER_FAN3_7", - "CFG_CENTER_FAN3_8", - "CFG_CENTER_FAN3_9", - "CFG_CENTER_FAN4_0", - "CFG_CENTER_FAN4_1", - "CFG_CENTER_FAN4_10", - "CFG_CENTER_FAN4_11", - "CFG_CENTER_FAN4_12", - "CFG_CENTER_FAN4_13", - "CFG_CENTER_FAN4_14", - "CFG_CENTER_FAN4_15", - "CFG_CENTER_FAN4_16", - "CFG_CENTER_FAN4_17", - "CFG_CENTER_FAN4_18", - "CFG_CENTER_FAN4_19", - "CFG_CENTER_FAN4_2", - "CFG_CENTER_FAN4_3", - "CFG_CENTER_FAN4_4", - "CFG_CENTER_FAN4_5", - "CFG_CENTER_FAN4_6", - "CFG_CENTER_FAN4_7", - "CFG_CENTER_FAN4_8", - "CFG_CENTER_FAN4_9", - "CFG_CENTER_FAN5_0", - "CFG_CENTER_FAN5_1", - "CFG_CENTER_FAN5_10", - "CFG_CENTER_FAN5_11", - "CFG_CENTER_FAN5_12", - "CFG_CENTER_FAN5_13", - "CFG_CENTER_FAN5_14", - "CFG_CENTER_FAN5_15", - "CFG_CENTER_FAN5_16", - "CFG_CENTER_FAN5_17", - "CFG_CENTER_FAN5_18", - "CFG_CENTER_FAN5_19", - "CFG_CENTER_FAN5_2", - "CFG_CENTER_FAN5_3", - "CFG_CENTER_FAN5_4", - "CFG_CENTER_FAN5_5", - "CFG_CENTER_FAN5_6", - "CFG_CENTER_FAN5_7", - "CFG_CENTER_FAN5_8", - "CFG_CENTER_FAN5_9", - "CFG_CENTER_FAN6_0", - "CFG_CENTER_FAN6_1", - "CFG_CENTER_FAN6_10", - "CFG_CENTER_FAN6_11", - "CFG_CENTER_FAN6_12", - "CFG_CENTER_FAN6_13", - "CFG_CENTER_FAN6_14", - "CFG_CENTER_FAN6_15", - "CFG_CENTER_FAN6_16", - "CFG_CENTER_FAN6_17", - "CFG_CENTER_FAN6_18", - "CFG_CENTER_FAN6_19", - "CFG_CENTER_FAN6_2", - "CFG_CENTER_FAN6_3", - "CFG_CENTER_FAN6_4", - "CFG_CENTER_FAN6_5", - "CFG_CENTER_FAN6_6", - "CFG_CENTER_FAN6_7", - "CFG_CENTER_FAN6_8", - "CFG_CENTER_FAN6_9", - "CFG_CENTER_FAN7_0", - "CFG_CENTER_FAN7_1", - "CFG_CENTER_FAN7_10", - "CFG_CENTER_FAN7_11", - "CFG_CENTER_FAN7_12", - "CFG_CENTER_FAN7_13", - "CFG_CENTER_FAN7_14", - "CFG_CENTER_FAN7_15", - "CFG_CENTER_FAN7_16", - "CFG_CENTER_FAN7_17", - "CFG_CENTER_FAN7_18", - "CFG_CENTER_FAN7_19", - "CFG_CENTER_FAN7_2", - "CFG_CENTER_FAN7_3", - "CFG_CENTER_FAN7_4", - "CFG_CENTER_FAN7_5", - "CFG_CENTER_FAN7_6", - "CFG_CENTER_FAN7_7", - "CFG_CENTER_FAN7_8", - "CFG_CENTER_FAN7_9", - "CFG_CENTER_IMUX0_0", - "CFG_CENTER_IMUX0_1", - "CFG_CENTER_IMUX0_10", - "CFG_CENTER_IMUX0_11", - "CFG_CENTER_IMUX0_12", - "CFG_CENTER_IMUX0_13", - "CFG_CENTER_IMUX0_14", - "CFG_CENTER_IMUX0_15", - "CFG_CENTER_IMUX0_16", - "CFG_CENTER_IMUX0_17", - "CFG_CENTER_IMUX0_18", - "CFG_CENTER_IMUX0_19", - "CFG_CENTER_IMUX0_2", - "CFG_CENTER_IMUX0_3", - "CFG_CENTER_IMUX0_4", - "CFG_CENTER_IMUX0_5", - "CFG_CENTER_IMUX0_6", - "CFG_CENTER_IMUX0_7", - "CFG_CENTER_IMUX0_8", - "CFG_CENTER_IMUX0_9", - "CFG_CENTER_IMUX10_0", - "CFG_CENTER_IMUX10_1", - "CFG_CENTER_IMUX10_10", - "CFG_CENTER_IMUX10_11", - "CFG_CENTER_IMUX10_12", - "CFG_CENTER_IMUX10_13", - "CFG_CENTER_IMUX10_14", - "CFG_CENTER_IMUX10_15", - "CFG_CENTER_IMUX10_16", - "CFG_CENTER_IMUX10_17", - "CFG_CENTER_IMUX10_18", - "CFG_CENTER_IMUX10_19", - "CFG_CENTER_IMUX10_2", - "CFG_CENTER_IMUX10_3", - "CFG_CENTER_IMUX10_4", - "CFG_CENTER_IMUX10_5", - "CFG_CENTER_IMUX10_6", - "CFG_CENTER_IMUX10_7", - "CFG_CENTER_IMUX10_8", - "CFG_CENTER_IMUX10_9", - "CFG_CENTER_IMUX11_0", - "CFG_CENTER_IMUX11_1", - "CFG_CENTER_IMUX11_10", - "CFG_CENTER_IMUX11_11", - "CFG_CENTER_IMUX11_12", - "CFG_CENTER_IMUX11_13", - "CFG_CENTER_IMUX11_14", - "CFG_CENTER_IMUX11_15", - "CFG_CENTER_IMUX11_16", - "CFG_CENTER_IMUX11_17", - "CFG_CENTER_IMUX11_18", - "CFG_CENTER_IMUX11_19", - "CFG_CENTER_IMUX11_2", - "CFG_CENTER_IMUX11_3", - "CFG_CENTER_IMUX11_4", - "CFG_CENTER_IMUX11_5", - "CFG_CENTER_IMUX11_6", - "CFG_CENTER_IMUX11_7", - "CFG_CENTER_IMUX11_8", - "CFG_CENTER_IMUX11_9", - "CFG_CENTER_IMUX12_0", - "CFG_CENTER_IMUX12_1", - "CFG_CENTER_IMUX12_10", - "CFG_CENTER_IMUX12_11", - "CFG_CENTER_IMUX12_12", - "CFG_CENTER_IMUX12_13", - "CFG_CENTER_IMUX12_14", - "CFG_CENTER_IMUX12_15", - "CFG_CENTER_IMUX12_16", - "CFG_CENTER_IMUX12_17", - "CFG_CENTER_IMUX12_18", - "CFG_CENTER_IMUX12_19", - "CFG_CENTER_IMUX12_2", - "CFG_CENTER_IMUX12_3", - "CFG_CENTER_IMUX12_4", - "CFG_CENTER_IMUX12_5", - "CFG_CENTER_IMUX12_6", - "CFG_CENTER_IMUX12_7", - "CFG_CENTER_IMUX12_8", - "CFG_CENTER_IMUX12_9", - "CFG_CENTER_IMUX13_0", - "CFG_CENTER_IMUX13_1", - "CFG_CENTER_IMUX13_10", - "CFG_CENTER_IMUX13_11", - "CFG_CENTER_IMUX13_12", - "CFG_CENTER_IMUX13_13", - "CFG_CENTER_IMUX13_14", - "CFG_CENTER_IMUX13_15", - "CFG_CENTER_IMUX13_16", - "CFG_CENTER_IMUX13_17", - "CFG_CENTER_IMUX13_18", - "CFG_CENTER_IMUX13_19", - "CFG_CENTER_IMUX13_2", - "CFG_CENTER_IMUX13_3", - "CFG_CENTER_IMUX13_4", - "CFG_CENTER_IMUX13_5", - "CFG_CENTER_IMUX13_6", - "CFG_CENTER_IMUX13_7", - "CFG_CENTER_IMUX13_8", - "CFG_CENTER_IMUX13_9", - "CFG_CENTER_IMUX14_0", - "CFG_CENTER_IMUX14_1", - "CFG_CENTER_IMUX14_10", - "CFG_CENTER_IMUX14_11", - "CFG_CENTER_IMUX14_12", - "CFG_CENTER_IMUX14_13", - "CFG_CENTER_IMUX14_14", - "CFG_CENTER_IMUX14_15", - "CFG_CENTER_IMUX14_16", - "CFG_CENTER_IMUX14_17", - "CFG_CENTER_IMUX14_18", - "CFG_CENTER_IMUX14_19", - "CFG_CENTER_IMUX14_2", - "CFG_CENTER_IMUX14_3", - "CFG_CENTER_IMUX14_4", - "CFG_CENTER_IMUX14_5", - "CFG_CENTER_IMUX14_6", - "CFG_CENTER_IMUX14_7", - "CFG_CENTER_IMUX14_8", - "CFG_CENTER_IMUX14_9", - "CFG_CENTER_IMUX15_0", - "CFG_CENTER_IMUX15_1", - "CFG_CENTER_IMUX15_10", - "CFG_CENTER_IMUX15_11", - "CFG_CENTER_IMUX15_12", - "CFG_CENTER_IMUX15_13", - "CFG_CENTER_IMUX15_14", - "CFG_CENTER_IMUX15_15", - "CFG_CENTER_IMUX15_16", - "CFG_CENTER_IMUX15_17", - "CFG_CENTER_IMUX15_18", - "CFG_CENTER_IMUX15_19", - "CFG_CENTER_IMUX15_2", - "CFG_CENTER_IMUX15_3", - "CFG_CENTER_IMUX15_4", - "CFG_CENTER_IMUX15_5", - "CFG_CENTER_IMUX15_6", - "CFG_CENTER_IMUX15_7", - "CFG_CENTER_IMUX15_8", - "CFG_CENTER_IMUX15_9", - "CFG_CENTER_IMUX16_0", - "CFG_CENTER_IMUX16_1", - "CFG_CENTER_IMUX16_10", - "CFG_CENTER_IMUX16_11", - "CFG_CENTER_IMUX16_12", - "CFG_CENTER_IMUX16_13", - "CFG_CENTER_IMUX16_14", - "CFG_CENTER_IMUX16_15", - "CFG_CENTER_IMUX16_16", - "CFG_CENTER_IMUX16_17", - "CFG_CENTER_IMUX16_18", - "CFG_CENTER_IMUX16_19", - "CFG_CENTER_IMUX16_2", - "CFG_CENTER_IMUX16_3", - "CFG_CENTER_IMUX16_4", - "CFG_CENTER_IMUX16_5", - "CFG_CENTER_IMUX16_6", - "CFG_CENTER_IMUX16_7", - "CFG_CENTER_IMUX16_8", - "CFG_CENTER_IMUX16_9", - "CFG_CENTER_IMUX17_0", - "CFG_CENTER_IMUX17_1", - "CFG_CENTER_IMUX17_10", - "CFG_CENTER_IMUX17_11", - "CFG_CENTER_IMUX17_12", - "CFG_CENTER_IMUX17_13", - "CFG_CENTER_IMUX17_14", - "CFG_CENTER_IMUX17_15", - "CFG_CENTER_IMUX17_16", - "CFG_CENTER_IMUX17_17", - "CFG_CENTER_IMUX17_18", - "CFG_CENTER_IMUX17_19", - "CFG_CENTER_IMUX17_2", - "CFG_CENTER_IMUX17_3", - "CFG_CENTER_IMUX17_4", - "CFG_CENTER_IMUX17_5", - "CFG_CENTER_IMUX17_6", - "CFG_CENTER_IMUX17_7", - "CFG_CENTER_IMUX17_8", - "CFG_CENTER_IMUX17_9", - "CFG_CENTER_IMUX18_0", - "CFG_CENTER_IMUX18_1", - "CFG_CENTER_IMUX18_10", - "CFG_CENTER_IMUX18_11", - "CFG_CENTER_IMUX18_12", - "CFG_CENTER_IMUX18_13", - "CFG_CENTER_IMUX18_14", - "CFG_CENTER_IMUX18_15", - "CFG_CENTER_IMUX18_16", - "CFG_CENTER_IMUX18_17", - "CFG_CENTER_IMUX18_18", - "CFG_CENTER_IMUX18_19", - "CFG_CENTER_IMUX18_2", - "CFG_CENTER_IMUX18_3", - "CFG_CENTER_IMUX18_4", - "CFG_CENTER_IMUX18_5", - "CFG_CENTER_IMUX18_6", - "CFG_CENTER_IMUX18_7", - "CFG_CENTER_IMUX18_8", - "CFG_CENTER_IMUX18_9", - "CFG_CENTER_IMUX19_0", - "CFG_CENTER_IMUX19_1", - "CFG_CENTER_IMUX19_10", - "CFG_CENTER_IMUX19_11", - "CFG_CENTER_IMUX19_12", - "CFG_CENTER_IMUX19_13", - "CFG_CENTER_IMUX19_14", - "CFG_CENTER_IMUX19_15", - "CFG_CENTER_IMUX19_16", - "CFG_CENTER_IMUX19_17", - "CFG_CENTER_IMUX19_18", - "CFG_CENTER_IMUX19_19", - "CFG_CENTER_IMUX19_2", - "CFG_CENTER_IMUX19_3", - "CFG_CENTER_IMUX19_4", - "CFG_CENTER_IMUX19_5", - "CFG_CENTER_IMUX19_6", - "CFG_CENTER_IMUX19_7", - "CFG_CENTER_IMUX19_8", - "CFG_CENTER_IMUX19_9", - "CFG_CENTER_IMUX1_0", - "CFG_CENTER_IMUX1_1", - "CFG_CENTER_IMUX1_10", - "CFG_CENTER_IMUX1_11", - "CFG_CENTER_IMUX1_12", - "CFG_CENTER_IMUX1_13", - "CFG_CENTER_IMUX1_14", - "CFG_CENTER_IMUX1_15", - "CFG_CENTER_IMUX1_16", - "CFG_CENTER_IMUX1_17", - "CFG_CENTER_IMUX1_18", - "CFG_CENTER_IMUX1_19", - "CFG_CENTER_IMUX1_2", - "CFG_CENTER_IMUX1_3", - "CFG_CENTER_IMUX1_4", - "CFG_CENTER_IMUX1_5", - "CFG_CENTER_IMUX1_6", - "CFG_CENTER_IMUX1_7", - "CFG_CENTER_IMUX1_8", - "CFG_CENTER_IMUX1_9", - "CFG_CENTER_IMUX20_0", - "CFG_CENTER_IMUX20_1", - "CFG_CENTER_IMUX20_10", - "CFG_CENTER_IMUX20_11", - "CFG_CENTER_IMUX20_12", - "CFG_CENTER_IMUX20_13", - "CFG_CENTER_IMUX20_14", - "CFG_CENTER_IMUX20_15", - "CFG_CENTER_IMUX20_16", - "CFG_CENTER_IMUX20_17", - "CFG_CENTER_IMUX20_18", - "CFG_CENTER_IMUX20_19", - "CFG_CENTER_IMUX20_2", - "CFG_CENTER_IMUX20_3", - "CFG_CENTER_IMUX20_4", - "CFG_CENTER_IMUX20_5", - "CFG_CENTER_IMUX20_6", - "CFG_CENTER_IMUX20_7", - "CFG_CENTER_IMUX20_8", - "CFG_CENTER_IMUX20_9", - "CFG_CENTER_IMUX21_0", - "CFG_CENTER_IMUX21_1", - "CFG_CENTER_IMUX21_10", - "CFG_CENTER_IMUX21_11", - "CFG_CENTER_IMUX21_12", - "CFG_CENTER_IMUX21_13", - "CFG_CENTER_IMUX21_14", - "CFG_CENTER_IMUX21_15", - "CFG_CENTER_IMUX21_16", - "CFG_CENTER_IMUX21_17", - "CFG_CENTER_IMUX21_18", - "CFG_CENTER_IMUX21_19", - "CFG_CENTER_IMUX21_2", - "CFG_CENTER_IMUX21_3", - "CFG_CENTER_IMUX21_4", - "CFG_CENTER_IMUX21_5", - "CFG_CENTER_IMUX21_6", - "CFG_CENTER_IMUX21_7", - "CFG_CENTER_IMUX21_8", - "CFG_CENTER_IMUX21_9", - "CFG_CENTER_IMUX22_0", - "CFG_CENTER_IMUX22_1", - "CFG_CENTER_IMUX22_10", - "CFG_CENTER_IMUX22_11", - "CFG_CENTER_IMUX22_12", - "CFG_CENTER_IMUX22_13", - "CFG_CENTER_IMUX22_14", - "CFG_CENTER_IMUX22_15", - "CFG_CENTER_IMUX22_16", - "CFG_CENTER_IMUX22_17", - "CFG_CENTER_IMUX22_18", - "CFG_CENTER_IMUX22_19", - "CFG_CENTER_IMUX22_2", - "CFG_CENTER_IMUX22_3", - "CFG_CENTER_IMUX22_4", - "CFG_CENTER_IMUX22_5", - "CFG_CENTER_IMUX22_6", - "CFG_CENTER_IMUX22_7", - "CFG_CENTER_IMUX22_8", - "CFG_CENTER_IMUX22_9", - "CFG_CENTER_IMUX23_0", - "CFG_CENTER_IMUX23_1", - "CFG_CENTER_IMUX23_10", - "CFG_CENTER_IMUX23_11", - "CFG_CENTER_IMUX23_12", - "CFG_CENTER_IMUX23_13", - "CFG_CENTER_IMUX23_14", - "CFG_CENTER_IMUX23_15", - "CFG_CENTER_IMUX23_16", - "CFG_CENTER_IMUX23_17", - "CFG_CENTER_IMUX23_18", - "CFG_CENTER_IMUX23_19", - "CFG_CENTER_IMUX23_2", - "CFG_CENTER_IMUX23_3", - "CFG_CENTER_IMUX23_4", - "CFG_CENTER_IMUX23_5", - "CFG_CENTER_IMUX23_6", - "CFG_CENTER_IMUX23_7", - "CFG_CENTER_IMUX23_8", - "CFG_CENTER_IMUX23_9", - "CFG_CENTER_IMUX24_0", - "CFG_CENTER_IMUX24_1", - "CFG_CENTER_IMUX24_10", - "CFG_CENTER_IMUX24_11", - "CFG_CENTER_IMUX24_12", - "CFG_CENTER_IMUX24_13", - "CFG_CENTER_IMUX24_14", - "CFG_CENTER_IMUX24_15", - "CFG_CENTER_IMUX24_16", - "CFG_CENTER_IMUX24_17", - "CFG_CENTER_IMUX24_18", - "CFG_CENTER_IMUX24_19", - "CFG_CENTER_IMUX24_2", - "CFG_CENTER_IMUX24_3", - "CFG_CENTER_IMUX24_4", - "CFG_CENTER_IMUX24_5", - "CFG_CENTER_IMUX24_6", - "CFG_CENTER_IMUX24_7", - "CFG_CENTER_IMUX24_8", - "CFG_CENTER_IMUX24_9", - "CFG_CENTER_IMUX25_0", - "CFG_CENTER_IMUX25_1", - "CFG_CENTER_IMUX25_10", - "CFG_CENTER_IMUX25_11", - "CFG_CENTER_IMUX25_12", - "CFG_CENTER_IMUX25_13", - "CFG_CENTER_IMUX25_14", - "CFG_CENTER_IMUX25_15", - "CFG_CENTER_IMUX25_16", - "CFG_CENTER_IMUX25_17", - "CFG_CENTER_IMUX25_18", - "CFG_CENTER_IMUX25_19", - "CFG_CENTER_IMUX25_2", - "CFG_CENTER_IMUX25_3", - "CFG_CENTER_IMUX25_4", - "CFG_CENTER_IMUX25_5", - "CFG_CENTER_IMUX25_6", - "CFG_CENTER_IMUX25_7", - "CFG_CENTER_IMUX25_8", - "CFG_CENTER_IMUX25_9", - "CFG_CENTER_IMUX26_0", - "CFG_CENTER_IMUX26_1", - "CFG_CENTER_IMUX26_10", - "CFG_CENTER_IMUX26_11", - "CFG_CENTER_IMUX26_12", - "CFG_CENTER_IMUX26_13", - "CFG_CENTER_IMUX26_14", - "CFG_CENTER_IMUX26_15", - "CFG_CENTER_IMUX26_16", - "CFG_CENTER_IMUX26_17", - "CFG_CENTER_IMUX26_18", - "CFG_CENTER_IMUX26_19", - "CFG_CENTER_IMUX26_2", - "CFG_CENTER_IMUX26_3", - "CFG_CENTER_IMUX26_4", - "CFG_CENTER_IMUX26_5", - "CFG_CENTER_IMUX26_6", - "CFG_CENTER_IMUX26_7", - "CFG_CENTER_IMUX26_8", - "CFG_CENTER_IMUX26_9", - "CFG_CENTER_IMUX27_0", - "CFG_CENTER_IMUX27_1", - "CFG_CENTER_IMUX27_10", - "CFG_CENTER_IMUX27_11", - "CFG_CENTER_IMUX27_12", - "CFG_CENTER_IMUX27_13", - "CFG_CENTER_IMUX27_14", - "CFG_CENTER_IMUX27_15", - "CFG_CENTER_IMUX27_16", - "CFG_CENTER_IMUX27_17", - "CFG_CENTER_IMUX27_18", - "CFG_CENTER_IMUX27_19", - "CFG_CENTER_IMUX27_2", - "CFG_CENTER_IMUX27_3", - "CFG_CENTER_IMUX27_4", - "CFG_CENTER_IMUX27_5", - "CFG_CENTER_IMUX27_6", - "CFG_CENTER_IMUX27_7", - "CFG_CENTER_IMUX27_8", - "CFG_CENTER_IMUX27_9", - "CFG_CENTER_IMUX28_0", - "CFG_CENTER_IMUX28_1", - "CFG_CENTER_IMUX28_10", - "CFG_CENTER_IMUX28_11", - "CFG_CENTER_IMUX28_12", - "CFG_CENTER_IMUX28_13", - "CFG_CENTER_IMUX28_14", - "CFG_CENTER_IMUX28_15", - "CFG_CENTER_IMUX28_16", - "CFG_CENTER_IMUX28_17", - "CFG_CENTER_IMUX28_18", - "CFG_CENTER_IMUX28_19", - "CFG_CENTER_IMUX28_2", - "CFG_CENTER_IMUX28_3", - "CFG_CENTER_IMUX28_4", - "CFG_CENTER_IMUX28_5", - "CFG_CENTER_IMUX28_6", - "CFG_CENTER_IMUX28_7", - "CFG_CENTER_IMUX28_8", - "CFG_CENTER_IMUX28_9", - "CFG_CENTER_IMUX29_0", - "CFG_CENTER_IMUX29_1", - "CFG_CENTER_IMUX29_10", - "CFG_CENTER_IMUX29_11", - "CFG_CENTER_IMUX29_12", - "CFG_CENTER_IMUX29_13", - "CFG_CENTER_IMUX29_14", - "CFG_CENTER_IMUX29_15", - "CFG_CENTER_IMUX29_16", - "CFG_CENTER_IMUX29_17", - "CFG_CENTER_IMUX29_18", - "CFG_CENTER_IMUX29_19", - "CFG_CENTER_IMUX29_2", - "CFG_CENTER_IMUX29_3", - "CFG_CENTER_IMUX29_4", - "CFG_CENTER_IMUX29_5", - "CFG_CENTER_IMUX29_6", - "CFG_CENTER_IMUX29_7", - "CFG_CENTER_IMUX29_8", - "CFG_CENTER_IMUX29_9", - "CFG_CENTER_IMUX2_0", - "CFG_CENTER_IMUX2_1", - "CFG_CENTER_IMUX2_10", - "CFG_CENTER_IMUX2_11", - "CFG_CENTER_IMUX2_12", - "CFG_CENTER_IMUX2_13", - "CFG_CENTER_IMUX2_14", - "CFG_CENTER_IMUX2_15", - "CFG_CENTER_IMUX2_16", - "CFG_CENTER_IMUX2_17", - "CFG_CENTER_IMUX2_18", - "CFG_CENTER_IMUX2_19", - "CFG_CENTER_IMUX2_2", - "CFG_CENTER_IMUX2_3", - "CFG_CENTER_IMUX2_4", - "CFG_CENTER_IMUX2_5", - "CFG_CENTER_IMUX2_6", - "CFG_CENTER_IMUX2_7", - "CFG_CENTER_IMUX2_8", - "CFG_CENTER_IMUX2_9", - "CFG_CENTER_IMUX30_0", - "CFG_CENTER_IMUX30_1", - "CFG_CENTER_IMUX30_10", - "CFG_CENTER_IMUX30_11", - "CFG_CENTER_IMUX30_12", - "CFG_CENTER_IMUX30_13", - "CFG_CENTER_IMUX30_14", - "CFG_CENTER_IMUX30_15", - "CFG_CENTER_IMUX30_16", - "CFG_CENTER_IMUX30_17", - "CFG_CENTER_IMUX30_18", - "CFG_CENTER_IMUX30_19", - "CFG_CENTER_IMUX30_2", - "CFG_CENTER_IMUX30_3", - "CFG_CENTER_IMUX30_4", - "CFG_CENTER_IMUX30_5", - "CFG_CENTER_IMUX30_6", - "CFG_CENTER_IMUX30_7", - "CFG_CENTER_IMUX30_8", - "CFG_CENTER_IMUX30_9", - "CFG_CENTER_IMUX31_0", - "CFG_CENTER_IMUX31_1", - "CFG_CENTER_IMUX31_10", - "CFG_CENTER_IMUX31_11", - "CFG_CENTER_IMUX31_12", - "CFG_CENTER_IMUX31_13", - "CFG_CENTER_IMUX31_14", - "CFG_CENTER_IMUX31_15", - "CFG_CENTER_IMUX31_16", - "CFG_CENTER_IMUX31_17", - "CFG_CENTER_IMUX31_18", - "CFG_CENTER_IMUX31_19", - "CFG_CENTER_IMUX31_2", - "CFG_CENTER_IMUX31_3", - "CFG_CENTER_IMUX31_4", - "CFG_CENTER_IMUX31_5", - "CFG_CENTER_IMUX31_6", - "CFG_CENTER_IMUX31_7", - "CFG_CENTER_IMUX31_8", - "CFG_CENTER_IMUX31_9", - "CFG_CENTER_IMUX32_0", - "CFG_CENTER_IMUX32_1", - "CFG_CENTER_IMUX32_10", - "CFG_CENTER_IMUX32_11", - "CFG_CENTER_IMUX32_12", - "CFG_CENTER_IMUX32_13", - "CFG_CENTER_IMUX32_14", - "CFG_CENTER_IMUX32_15", - "CFG_CENTER_IMUX32_16", - "CFG_CENTER_IMUX32_17", - "CFG_CENTER_IMUX32_18", - "CFG_CENTER_IMUX32_19", - "CFG_CENTER_IMUX32_2", - "CFG_CENTER_IMUX32_3", - "CFG_CENTER_IMUX32_4", - "CFG_CENTER_IMUX32_5", - "CFG_CENTER_IMUX32_6", - "CFG_CENTER_IMUX32_7", - "CFG_CENTER_IMUX32_8", - "CFG_CENTER_IMUX32_9", - "CFG_CENTER_IMUX33_0", - "CFG_CENTER_IMUX33_1", - "CFG_CENTER_IMUX33_10", - "CFG_CENTER_IMUX33_11", - "CFG_CENTER_IMUX33_12", - "CFG_CENTER_IMUX33_13", - "CFG_CENTER_IMUX33_14", - "CFG_CENTER_IMUX33_15", - "CFG_CENTER_IMUX33_16", - "CFG_CENTER_IMUX33_17", - "CFG_CENTER_IMUX33_18", - "CFG_CENTER_IMUX33_19", - "CFG_CENTER_IMUX33_2", - "CFG_CENTER_IMUX33_3", - "CFG_CENTER_IMUX33_4", - "CFG_CENTER_IMUX33_5", - "CFG_CENTER_IMUX33_6", - "CFG_CENTER_IMUX33_7", - "CFG_CENTER_IMUX33_8", - "CFG_CENTER_IMUX33_9", - "CFG_CENTER_IMUX34_0", - "CFG_CENTER_IMUX34_1", - "CFG_CENTER_IMUX34_10", - "CFG_CENTER_IMUX34_11", - "CFG_CENTER_IMUX34_12", - "CFG_CENTER_IMUX34_13", - "CFG_CENTER_IMUX34_14", - "CFG_CENTER_IMUX34_15", - "CFG_CENTER_IMUX34_16", - "CFG_CENTER_IMUX34_17", - "CFG_CENTER_IMUX34_18", - "CFG_CENTER_IMUX34_19", - "CFG_CENTER_IMUX34_2", - "CFG_CENTER_IMUX34_3", - "CFG_CENTER_IMUX34_4", - "CFG_CENTER_IMUX34_5", - "CFG_CENTER_IMUX34_6", - "CFG_CENTER_IMUX34_7", - "CFG_CENTER_IMUX34_8", - "CFG_CENTER_IMUX34_9", - "CFG_CENTER_IMUX35_0", - "CFG_CENTER_IMUX35_1", - "CFG_CENTER_IMUX35_10", - "CFG_CENTER_IMUX35_11", - "CFG_CENTER_IMUX35_12", - "CFG_CENTER_IMUX35_13", - "CFG_CENTER_IMUX35_14", - "CFG_CENTER_IMUX35_15", - "CFG_CENTER_IMUX35_16", - "CFG_CENTER_IMUX35_17", - "CFG_CENTER_IMUX35_18", - "CFG_CENTER_IMUX35_19", - "CFG_CENTER_IMUX35_2", - "CFG_CENTER_IMUX35_3", - "CFG_CENTER_IMUX35_4", - "CFG_CENTER_IMUX35_5", - "CFG_CENTER_IMUX35_6", - "CFG_CENTER_IMUX35_7", - "CFG_CENTER_IMUX35_8", - "CFG_CENTER_IMUX35_9", - "CFG_CENTER_IMUX36_0", - "CFG_CENTER_IMUX36_1", - "CFG_CENTER_IMUX36_10", - "CFG_CENTER_IMUX36_11", - "CFG_CENTER_IMUX36_12", - "CFG_CENTER_IMUX36_13", - "CFG_CENTER_IMUX36_14", - "CFG_CENTER_IMUX36_15", - "CFG_CENTER_IMUX36_16", - "CFG_CENTER_IMUX36_17", - "CFG_CENTER_IMUX36_18", - "CFG_CENTER_IMUX36_19", - "CFG_CENTER_IMUX36_2", - "CFG_CENTER_IMUX36_3", - "CFG_CENTER_IMUX36_4", - "CFG_CENTER_IMUX36_5", - "CFG_CENTER_IMUX36_6", - "CFG_CENTER_IMUX36_7", - "CFG_CENTER_IMUX36_8", - "CFG_CENTER_IMUX36_9", - "CFG_CENTER_IMUX37_0", - "CFG_CENTER_IMUX37_1", - "CFG_CENTER_IMUX37_10", - "CFG_CENTER_IMUX37_11", - "CFG_CENTER_IMUX37_12", - "CFG_CENTER_IMUX37_13", - "CFG_CENTER_IMUX37_14", - "CFG_CENTER_IMUX37_15", - "CFG_CENTER_IMUX37_16", - "CFG_CENTER_IMUX37_17", - "CFG_CENTER_IMUX37_18", - "CFG_CENTER_IMUX37_19", - "CFG_CENTER_IMUX37_2", - "CFG_CENTER_IMUX37_3", - "CFG_CENTER_IMUX37_4", - "CFG_CENTER_IMUX37_5", - "CFG_CENTER_IMUX37_6", - "CFG_CENTER_IMUX37_7", - "CFG_CENTER_IMUX37_8", - "CFG_CENTER_IMUX37_9", - "CFG_CENTER_IMUX38_0", - "CFG_CENTER_IMUX38_1", - "CFG_CENTER_IMUX38_10", - "CFG_CENTER_IMUX38_11", - "CFG_CENTER_IMUX38_12", - "CFG_CENTER_IMUX38_13", - "CFG_CENTER_IMUX38_14", - "CFG_CENTER_IMUX38_15", - "CFG_CENTER_IMUX38_16", - "CFG_CENTER_IMUX38_17", - "CFG_CENTER_IMUX38_18", - "CFG_CENTER_IMUX38_19", - "CFG_CENTER_IMUX38_2", - "CFG_CENTER_IMUX38_3", - "CFG_CENTER_IMUX38_4", - "CFG_CENTER_IMUX38_5", - "CFG_CENTER_IMUX38_6", - "CFG_CENTER_IMUX38_7", - "CFG_CENTER_IMUX38_8", - "CFG_CENTER_IMUX38_9", - "CFG_CENTER_IMUX39_0", - "CFG_CENTER_IMUX39_1", - "CFG_CENTER_IMUX39_10", - "CFG_CENTER_IMUX39_11", - "CFG_CENTER_IMUX39_12", - "CFG_CENTER_IMUX39_13", - "CFG_CENTER_IMUX39_14", - "CFG_CENTER_IMUX39_15", - "CFG_CENTER_IMUX39_16", - "CFG_CENTER_IMUX39_17", - "CFG_CENTER_IMUX39_18", - "CFG_CENTER_IMUX39_19", - "CFG_CENTER_IMUX39_2", - "CFG_CENTER_IMUX39_3", - "CFG_CENTER_IMUX39_4", - "CFG_CENTER_IMUX39_5", - "CFG_CENTER_IMUX39_6", - "CFG_CENTER_IMUX39_7", - "CFG_CENTER_IMUX39_8", - "CFG_CENTER_IMUX39_9", - "CFG_CENTER_IMUX3_0", - "CFG_CENTER_IMUX3_1", - "CFG_CENTER_IMUX3_10", - "CFG_CENTER_IMUX3_11", - "CFG_CENTER_IMUX3_12", - "CFG_CENTER_IMUX3_13", - "CFG_CENTER_IMUX3_14", - "CFG_CENTER_IMUX3_15", - "CFG_CENTER_IMUX3_16", - "CFG_CENTER_IMUX3_17", - "CFG_CENTER_IMUX3_18", - "CFG_CENTER_IMUX3_19", - "CFG_CENTER_IMUX3_2", - "CFG_CENTER_IMUX3_3", - "CFG_CENTER_IMUX3_4", - "CFG_CENTER_IMUX3_5", - "CFG_CENTER_IMUX3_6", - "CFG_CENTER_IMUX3_7", - "CFG_CENTER_IMUX3_8", - "CFG_CENTER_IMUX3_9", - "CFG_CENTER_IMUX40_0", - "CFG_CENTER_IMUX40_1", - "CFG_CENTER_IMUX40_10", - "CFG_CENTER_IMUX40_11", - "CFG_CENTER_IMUX40_12", - "CFG_CENTER_IMUX40_13", - "CFG_CENTER_IMUX40_14", - "CFG_CENTER_IMUX40_15", - "CFG_CENTER_IMUX40_16", - "CFG_CENTER_IMUX40_17", - "CFG_CENTER_IMUX40_18", - "CFG_CENTER_IMUX40_19", - "CFG_CENTER_IMUX40_2", - "CFG_CENTER_IMUX40_3", - "CFG_CENTER_IMUX40_4", - "CFG_CENTER_IMUX40_5", - "CFG_CENTER_IMUX40_6", - "CFG_CENTER_IMUX40_7", - "CFG_CENTER_IMUX40_8", - "CFG_CENTER_IMUX40_9", - "CFG_CENTER_IMUX41_0", - "CFG_CENTER_IMUX41_1", - "CFG_CENTER_IMUX41_10", - "CFG_CENTER_IMUX41_11", - "CFG_CENTER_IMUX41_12", - "CFG_CENTER_IMUX41_13", - "CFG_CENTER_IMUX41_14", - "CFG_CENTER_IMUX41_15", - "CFG_CENTER_IMUX41_16", - "CFG_CENTER_IMUX41_17", - "CFG_CENTER_IMUX41_18", - "CFG_CENTER_IMUX41_19", - "CFG_CENTER_IMUX41_2", - "CFG_CENTER_IMUX41_3", - "CFG_CENTER_IMUX41_4", - "CFG_CENTER_IMUX41_5", - "CFG_CENTER_IMUX41_6", - "CFG_CENTER_IMUX41_7", - "CFG_CENTER_IMUX41_8", - "CFG_CENTER_IMUX41_9", - "CFG_CENTER_IMUX42_0", - "CFG_CENTER_IMUX42_1", - "CFG_CENTER_IMUX42_10", - "CFG_CENTER_IMUX42_11", - "CFG_CENTER_IMUX42_12", - "CFG_CENTER_IMUX42_13", - "CFG_CENTER_IMUX42_14", - "CFG_CENTER_IMUX42_15", - "CFG_CENTER_IMUX42_16", - "CFG_CENTER_IMUX42_17", - "CFG_CENTER_IMUX42_18", - "CFG_CENTER_IMUX42_19", - "CFG_CENTER_IMUX42_2", - "CFG_CENTER_IMUX42_3", - "CFG_CENTER_IMUX42_4", - "CFG_CENTER_IMUX42_5", - "CFG_CENTER_IMUX42_6", - "CFG_CENTER_IMUX42_7", - "CFG_CENTER_IMUX42_8", - "CFG_CENTER_IMUX42_9", - "CFG_CENTER_IMUX43_0", - "CFG_CENTER_IMUX43_1", - "CFG_CENTER_IMUX43_10", - "CFG_CENTER_IMUX43_11", - "CFG_CENTER_IMUX43_12", - "CFG_CENTER_IMUX43_13", - "CFG_CENTER_IMUX43_14", - "CFG_CENTER_IMUX43_15", - "CFG_CENTER_IMUX43_16", - "CFG_CENTER_IMUX43_17", - "CFG_CENTER_IMUX43_18", - "CFG_CENTER_IMUX43_19", - "CFG_CENTER_IMUX43_2", - "CFG_CENTER_IMUX43_3", - "CFG_CENTER_IMUX43_4", - "CFG_CENTER_IMUX43_5", - "CFG_CENTER_IMUX43_6", - "CFG_CENTER_IMUX43_7", - "CFG_CENTER_IMUX43_8", - "CFG_CENTER_IMUX43_9", - "CFG_CENTER_IMUX44_0", - "CFG_CENTER_IMUX44_1", - "CFG_CENTER_IMUX44_10", - "CFG_CENTER_IMUX44_11", - "CFG_CENTER_IMUX44_12", - "CFG_CENTER_IMUX44_13", - "CFG_CENTER_IMUX44_14", - "CFG_CENTER_IMUX44_15", - "CFG_CENTER_IMUX44_16", - "CFG_CENTER_IMUX44_17", - "CFG_CENTER_IMUX44_18", - "CFG_CENTER_IMUX44_19", - "CFG_CENTER_IMUX44_2", - "CFG_CENTER_IMUX44_3", - "CFG_CENTER_IMUX44_4", - "CFG_CENTER_IMUX44_5", - "CFG_CENTER_IMUX44_6", - "CFG_CENTER_IMUX44_7", - "CFG_CENTER_IMUX44_8", - "CFG_CENTER_IMUX44_9", - "CFG_CENTER_IMUX45_0", - "CFG_CENTER_IMUX45_1", - "CFG_CENTER_IMUX45_10", - "CFG_CENTER_IMUX45_11", - "CFG_CENTER_IMUX45_12", - "CFG_CENTER_IMUX45_13", - "CFG_CENTER_IMUX45_14", - "CFG_CENTER_IMUX45_15", - "CFG_CENTER_IMUX45_16", - "CFG_CENTER_IMUX45_17", - "CFG_CENTER_IMUX45_18", - "CFG_CENTER_IMUX45_19", - "CFG_CENTER_IMUX45_2", - "CFG_CENTER_IMUX45_3", - "CFG_CENTER_IMUX45_4", - "CFG_CENTER_IMUX45_5", - "CFG_CENTER_IMUX45_6", - "CFG_CENTER_IMUX45_7", - "CFG_CENTER_IMUX45_8", - "CFG_CENTER_IMUX45_9", - "CFG_CENTER_IMUX46_0", - "CFG_CENTER_IMUX46_1", - "CFG_CENTER_IMUX46_10", - "CFG_CENTER_IMUX46_11", - "CFG_CENTER_IMUX46_12", - "CFG_CENTER_IMUX46_13", - "CFG_CENTER_IMUX46_14", - "CFG_CENTER_IMUX46_15", - "CFG_CENTER_IMUX46_16", - "CFG_CENTER_IMUX46_17", - "CFG_CENTER_IMUX46_18", - "CFG_CENTER_IMUX46_19", - "CFG_CENTER_IMUX46_2", - "CFG_CENTER_IMUX46_3", - "CFG_CENTER_IMUX46_4", - "CFG_CENTER_IMUX46_5", - "CFG_CENTER_IMUX46_6", - "CFG_CENTER_IMUX46_7", - "CFG_CENTER_IMUX46_8", - "CFG_CENTER_IMUX46_9", - "CFG_CENTER_IMUX47_0", - "CFG_CENTER_IMUX47_1", - "CFG_CENTER_IMUX47_10", - "CFG_CENTER_IMUX47_11", - "CFG_CENTER_IMUX47_12", - "CFG_CENTER_IMUX47_13", - "CFG_CENTER_IMUX47_14", - "CFG_CENTER_IMUX47_15", - "CFG_CENTER_IMUX47_16", - "CFG_CENTER_IMUX47_17", - "CFG_CENTER_IMUX47_18", - "CFG_CENTER_IMUX47_19", - "CFG_CENTER_IMUX47_2", - "CFG_CENTER_IMUX47_3", - "CFG_CENTER_IMUX47_4", - "CFG_CENTER_IMUX47_5", - "CFG_CENTER_IMUX47_6", - "CFG_CENTER_IMUX47_7", - "CFG_CENTER_IMUX47_8", - "CFG_CENTER_IMUX47_9", - "CFG_CENTER_IMUX4_0", - "CFG_CENTER_IMUX4_1", - "CFG_CENTER_IMUX4_10", - "CFG_CENTER_IMUX4_11", - "CFG_CENTER_IMUX4_12", - "CFG_CENTER_IMUX4_13", - "CFG_CENTER_IMUX4_14", - "CFG_CENTER_IMUX4_15", - "CFG_CENTER_IMUX4_16", - "CFG_CENTER_IMUX4_17", - "CFG_CENTER_IMUX4_18", - "CFG_CENTER_IMUX4_19", - "CFG_CENTER_IMUX4_2", - "CFG_CENTER_IMUX4_3", - "CFG_CENTER_IMUX4_4", - "CFG_CENTER_IMUX4_5", - "CFG_CENTER_IMUX4_6", - "CFG_CENTER_IMUX4_7", - "CFG_CENTER_IMUX4_8", - "CFG_CENTER_IMUX4_9", - "CFG_CENTER_IMUX5_0", - "CFG_CENTER_IMUX5_1", - "CFG_CENTER_IMUX5_10", - "CFG_CENTER_IMUX5_11", - "CFG_CENTER_IMUX5_12", - "CFG_CENTER_IMUX5_13", - "CFG_CENTER_IMUX5_14", - "CFG_CENTER_IMUX5_15", - "CFG_CENTER_IMUX5_16", - "CFG_CENTER_IMUX5_17", - "CFG_CENTER_IMUX5_18", - "CFG_CENTER_IMUX5_19", - "CFG_CENTER_IMUX5_2", - "CFG_CENTER_IMUX5_3", - "CFG_CENTER_IMUX5_4", - "CFG_CENTER_IMUX5_5", - "CFG_CENTER_IMUX5_6", - "CFG_CENTER_IMUX5_7", - "CFG_CENTER_IMUX5_8", - "CFG_CENTER_IMUX5_9", - "CFG_CENTER_IMUX6_0", - "CFG_CENTER_IMUX6_1", - "CFG_CENTER_IMUX6_10", - "CFG_CENTER_IMUX6_11", - "CFG_CENTER_IMUX6_12", - "CFG_CENTER_IMUX6_13", - "CFG_CENTER_IMUX6_14", - "CFG_CENTER_IMUX6_15", - "CFG_CENTER_IMUX6_16", - "CFG_CENTER_IMUX6_17", - "CFG_CENTER_IMUX6_18", - "CFG_CENTER_IMUX6_19", - "CFG_CENTER_IMUX6_2", - "CFG_CENTER_IMUX6_3", - "CFG_CENTER_IMUX6_4", - "CFG_CENTER_IMUX6_5", - "CFG_CENTER_IMUX6_6", - "CFG_CENTER_IMUX6_7", - "CFG_CENTER_IMUX6_8", - "CFG_CENTER_IMUX6_9", - "CFG_CENTER_IMUX7_0", - "CFG_CENTER_IMUX7_1", - "CFG_CENTER_IMUX7_10", - "CFG_CENTER_IMUX7_11", - "CFG_CENTER_IMUX7_12", - "CFG_CENTER_IMUX7_13", - "CFG_CENTER_IMUX7_14", - "CFG_CENTER_IMUX7_15", - "CFG_CENTER_IMUX7_16", - "CFG_CENTER_IMUX7_17", - "CFG_CENTER_IMUX7_18", - "CFG_CENTER_IMUX7_19", - "CFG_CENTER_IMUX7_2", - "CFG_CENTER_IMUX7_3", - "CFG_CENTER_IMUX7_4", - "CFG_CENTER_IMUX7_5", - "CFG_CENTER_IMUX7_6", - "CFG_CENTER_IMUX7_7", - "CFG_CENTER_IMUX7_8", - "CFG_CENTER_IMUX7_9", - "CFG_CENTER_IMUX8_0", - "CFG_CENTER_IMUX8_1", - "CFG_CENTER_IMUX8_10", - "CFG_CENTER_IMUX8_11", - "CFG_CENTER_IMUX8_12", - "CFG_CENTER_IMUX8_13", - "CFG_CENTER_IMUX8_14", - "CFG_CENTER_IMUX8_15", - "CFG_CENTER_IMUX8_16", - "CFG_CENTER_IMUX8_17", - "CFG_CENTER_IMUX8_18", - "CFG_CENTER_IMUX8_19", - "CFG_CENTER_IMUX8_2", - "CFG_CENTER_IMUX8_3", - "CFG_CENTER_IMUX8_4", - "CFG_CENTER_IMUX8_5", - "CFG_CENTER_IMUX8_6", - "CFG_CENTER_IMUX8_7", - "CFG_CENTER_IMUX8_8", - "CFG_CENTER_IMUX8_9", - "CFG_CENTER_IMUX9_0", - "CFG_CENTER_IMUX9_1", - "CFG_CENTER_IMUX9_10", - "CFG_CENTER_IMUX9_11", - "CFG_CENTER_IMUX9_12", - "CFG_CENTER_IMUX9_13", - "CFG_CENTER_IMUX9_14", - "CFG_CENTER_IMUX9_15", - "CFG_CENTER_IMUX9_16", - "CFG_CENTER_IMUX9_17", - "CFG_CENTER_IMUX9_18", - "CFG_CENTER_IMUX9_19", - "CFG_CENTER_IMUX9_2", - "CFG_CENTER_IMUX9_3", - "CFG_CENTER_IMUX9_4", - "CFG_CENTER_IMUX9_5", - "CFG_CENTER_IMUX9_6", - "CFG_CENTER_IMUX9_7", - "CFG_CENTER_IMUX9_8", - "CFG_CENTER_IMUX9_9", - "CFG_CENTER_LH10_0", - "CFG_CENTER_LH10_1", - "CFG_CENTER_LH10_10", - "CFG_CENTER_LH10_11", - "CFG_CENTER_LH10_12", - "CFG_CENTER_LH10_13", - "CFG_CENTER_LH10_14", - "CFG_CENTER_LH10_15", - "CFG_CENTER_LH10_16", - "CFG_CENTER_LH10_17", - "CFG_CENTER_LH10_18", - "CFG_CENTER_LH10_19", - "CFG_CENTER_LH10_2", - "CFG_CENTER_LH10_3", - "CFG_CENTER_LH10_4", - "CFG_CENTER_LH10_5", - "CFG_CENTER_LH10_6", - "CFG_CENTER_LH10_7", - "CFG_CENTER_LH10_8", - "CFG_CENTER_LH10_9", - "CFG_CENTER_LH11_0", - "CFG_CENTER_LH11_1", - "CFG_CENTER_LH11_10", - "CFG_CENTER_LH11_11", - "CFG_CENTER_LH11_12", - "CFG_CENTER_LH11_13", - "CFG_CENTER_LH11_14", - "CFG_CENTER_LH11_15", - "CFG_CENTER_LH11_16", - "CFG_CENTER_LH11_17", - "CFG_CENTER_LH11_18", - "CFG_CENTER_LH11_19", - "CFG_CENTER_LH11_2", - "CFG_CENTER_LH11_3", - "CFG_CENTER_LH11_4", - "CFG_CENTER_LH11_5", - "CFG_CENTER_LH11_6", - "CFG_CENTER_LH11_7", - "CFG_CENTER_LH11_8", - "CFG_CENTER_LH11_9", - "CFG_CENTER_LH12_0", - "CFG_CENTER_LH12_1", - "CFG_CENTER_LH12_10", - "CFG_CENTER_LH12_11", - "CFG_CENTER_LH12_12", - "CFG_CENTER_LH12_13", - "CFG_CENTER_LH12_14", - "CFG_CENTER_LH12_15", - "CFG_CENTER_LH12_16", - "CFG_CENTER_LH12_17", - "CFG_CENTER_LH12_18", - "CFG_CENTER_LH12_19", - "CFG_CENTER_LH12_2", - "CFG_CENTER_LH12_3", - "CFG_CENTER_LH12_4", - "CFG_CENTER_LH12_5", - "CFG_CENTER_LH12_6", - "CFG_CENTER_LH12_7", - "CFG_CENTER_LH12_8", - "CFG_CENTER_LH12_9", - "CFG_CENTER_LH1_0", - "CFG_CENTER_LH1_1", - "CFG_CENTER_LH1_10", - "CFG_CENTER_LH1_11", - "CFG_CENTER_LH1_12", - "CFG_CENTER_LH1_13", - "CFG_CENTER_LH1_14", - "CFG_CENTER_LH1_15", - "CFG_CENTER_LH1_16", - "CFG_CENTER_LH1_17", - "CFG_CENTER_LH1_18", - "CFG_CENTER_LH1_19", - "CFG_CENTER_LH1_2", - "CFG_CENTER_LH1_3", - "CFG_CENTER_LH1_4", - "CFG_CENTER_LH1_5", - "CFG_CENTER_LH1_6", - "CFG_CENTER_LH1_7", - "CFG_CENTER_LH1_8", - "CFG_CENTER_LH1_9", - "CFG_CENTER_LH2_0", - "CFG_CENTER_LH2_1", - "CFG_CENTER_LH2_10", - "CFG_CENTER_LH2_11", - "CFG_CENTER_LH2_12", - "CFG_CENTER_LH2_13", - "CFG_CENTER_LH2_14", - "CFG_CENTER_LH2_15", - "CFG_CENTER_LH2_16", - "CFG_CENTER_LH2_17", - "CFG_CENTER_LH2_18", - "CFG_CENTER_LH2_19", - "CFG_CENTER_LH2_2", - "CFG_CENTER_LH2_3", - "CFG_CENTER_LH2_4", - "CFG_CENTER_LH2_5", - "CFG_CENTER_LH2_6", - "CFG_CENTER_LH2_7", - "CFG_CENTER_LH2_8", - "CFG_CENTER_LH2_9", - "CFG_CENTER_LH3_0", - "CFG_CENTER_LH3_1", - "CFG_CENTER_LH3_10", - "CFG_CENTER_LH3_11", - "CFG_CENTER_LH3_12", - "CFG_CENTER_LH3_13", - "CFG_CENTER_LH3_14", - "CFG_CENTER_LH3_15", - "CFG_CENTER_LH3_16", - "CFG_CENTER_LH3_17", - "CFG_CENTER_LH3_18", - "CFG_CENTER_LH3_19", - "CFG_CENTER_LH3_2", - "CFG_CENTER_LH3_3", - "CFG_CENTER_LH3_4", - "CFG_CENTER_LH3_5", - "CFG_CENTER_LH3_6", - "CFG_CENTER_LH3_7", - "CFG_CENTER_LH3_8", - "CFG_CENTER_LH3_9", - "CFG_CENTER_LH4_0", - "CFG_CENTER_LH4_1", - "CFG_CENTER_LH4_10", - "CFG_CENTER_LH4_11", - "CFG_CENTER_LH4_12", - "CFG_CENTER_LH4_13", - "CFG_CENTER_LH4_14", - "CFG_CENTER_LH4_15", - "CFG_CENTER_LH4_16", - "CFG_CENTER_LH4_17", - "CFG_CENTER_LH4_18", - "CFG_CENTER_LH4_19", - "CFG_CENTER_LH4_2", - "CFG_CENTER_LH4_3", - "CFG_CENTER_LH4_4", - "CFG_CENTER_LH4_5", - "CFG_CENTER_LH4_6", - "CFG_CENTER_LH4_7", - "CFG_CENTER_LH4_8", - "CFG_CENTER_LH4_9", - "CFG_CENTER_LH5_0", - "CFG_CENTER_LH5_1", - "CFG_CENTER_LH5_10", - "CFG_CENTER_LH5_11", - "CFG_CENTER_LH5_12", - "CFG_CENTER_LH5_13", - "CFG_CENTER_LH5_14", - "CFG_CENTER_LH5_15", - "CFG_CENTER_LH5_16", - "CFG_CENTER_LH5_17", - "CFG_CENTER_LH5_18", - "CFG_CENTER_LH5_19", - "CFG_CENTER_LH5_2", - "CFG_CENTER_LH5_3", - "CFG_CENTER_LH5_4", - "CFG_CENTER_LH5_5", - "CFG_CENTER_LH5_6", - "CFG_CENTER_LH5_7", - "CFG_CENTER_LH5_8", - "CFG_CENTER_LH5_9", - "CFG_CENTER_LH6_0", - "CFG_CENTER_LH6_1", - "CFG_CENTER_LH6_10", - "CFG_CENTER_LH6_11", - "CFG_CENTER_LH6_12", - "CFG_CENTER_LH6_13", - "CFG_CENTER_LH6_14", - "CFG_CENTER_LH6_15", - "CFG_CENTER_LH6_16", - "CFG_CENTER_LH6_17", - "CFG_CENTER_LH6_18", - "CFG_CENTER_LH6_19", - "CFG_CENTER_LH6_2", - "CFG_CENTER_LH6_3", - "CFG_CENTER_LH6_4", - "CFG_CENTER_LH6_5", - "CFG_CENTER_LH6_6", - "CFG_CENTER_LH6_7", - "CFG_CENTER_LH6_8", - "CFG_CENTER_LH6_9", - "CFG_CENTER_LH7_0", - "CFG_CENTER_LH7_1", - "CFG_CENTER_LH7_10", - "CFG_CENTER_LH7_11", - "CFG_CENTER_LH7_12", - "CFG_CENTER_LH7_13", - "CFG_CENTER_LH7_14", - "CFG_CENTER_LH7_15", - "CFG_CENTER_LH7_16", - "CFG_CENTER_LH7_17", - "CFG_CENTER_LH7_18", - "CFG_CENTER_LH7_19", - "CFG_CENTER_LH7_2", - "CFG_CENTER_LH7_3", - "CFG_CENTER_LH7_4", - "CFG_CENTER_LH7_5", - "CFG_CENTER_LH7_6", - "CFG_CENTER_LH7_7", - "CFG_CENTER_LH7_8", - "CFG_CENTER_LH7_9", - "CFG_CENTER_LH8_0", - "CFG_CENTER_LH8_1", - "CFG_CENTER_LH8_10", - "CFG_CENTER_LH8_11", - "CFG_CENTER_LH8_12", - "CFG_CENTER_LH8_13", - "CFG_CENTER_LH8_14", - "CFG_CENTER_LH8_15", - "CFG_CENTER_LH8_16", - "CFG_CENTER_LH8_17", - "CFG_CENTER_LH8_18", - "CFG_CENTER_LH8_19", - "CFG_CENTER_LH8_2", - "CFG_CENTER_LH8_3", - "CFG_CENTER_LH8_4", - "CFG_CENTER_LH8_5", - "CFG_CENTER_LH8_6", - "CFG_CENTER_LH8_7", - "CFG_CENTER_LH8_8", - "CFG_CENTER_LH8_9", - "CFG_CENTER_LH9_0", - "CFG_CENTER_LH9_1", - "CFG_CENTER_LH9_10", - "CFG_CENTER_LH9_11", - "CFG_CENTER_LH9_12", - "CFG_CENTER_LH9_13", - "CFG_CENTER_LH9_14", - "CFG_CENTER_LH9_15", - "CFG_CENTER_LH9_16", - "CFG_CENTER_LH9_17", - "CFG_CENTER_LH9_18", - "CFG_CENTER_LH9_19", - "CFG_CENTER_LH9_2", - "CFG_CENTER_LH9_3", - "CFG_CENTER_LH9_4", - "CFG_CENTER_LH9_5", - "CFG_CENTER_LH9_6", - "CFG_CENTER_LH9_7", - "CFG_CENTER_LH9_8", - "CFG_CENTER_LH9_9", - "CFG_CENTER_LOGIC_OUTS_B0_0", - "CFG_CENTER_LOGIC_OUTS_B0_1", - "CFG_CENTER_LOGIC_OUTS_B0_10", - "CFG_CENTER_LOGIC_OUTS_B0_11", - "CFG_CENTER_LOGIC_OUTS_B0_12", - "CFG_CENTER_LOGIC_OUTS_B0_13", - "CFG_CENTER_LOGIC_OUTS_B0_14", - "CFG_CENTER_LOGIC_OUTS_B0_15", - "CFG_CENTER_LOGIC_OUTS_B0_16", - "CFG_CENTER_LOGIC_OUTS_B0_17", - "CFG_CENTER_LOGIC_OUTS_B0_18", - "CFG_CENTER_LOGIC_OUTS_B0_19", - "CFG_CENTER_LOGIC_OUTS_B0_2", - "CFG_CENTER_LOGIC_OUTS_B0_3", - "CFG_CENTER_LOGIC_OUTS_B0_4", - "CFG_CENTER_LOGIC_OUTS_B0_5", - "CFG_CENTER_LOGIC_OUTS_B0_6", - "CFG_CENTER_LOGIC_OUTS_B0_7", - "CFG_CENTER_LOGIC_OUTS_B0_8", - "CFG_CENTER_LOGIC_OUTS_B0_9", - "CFG_CENTER_LOGIC_OUTS_B10_0", - "CFG_CENTER_LOGIC_OUTS_B10_1", - "CFG_CENTER_LOGIC_OUTS_B10_10", - "CFG_CENTER_LOGIC_OUTS_B10_11", - "CFG_CENTER_LOGIC_OUTS_B10_12", - "CFG_CENTER_LOGIC_OUTS_B10_13", - "CFG_CENTER_LOGIC_OUTS_B10_14", - "CFG_CENTER_LOGIC_OUTS_B10_15", - "CFG_CENTER_LOGIC_OUTS_B10_16", - "CFG_CENTER_LOGIC_OUTS_B10_17", - "CFG_CENTER_LOGIC_OUTS_B10_18", - "CFG_CENTER_LOGIC_OUTS_B10_19", - "CFG_CENTER_LOGIC_OUTS_B10_2", - "CFG_CENTER_LOGIC_OUTS_B10_3", - "CFG_CENTER_LOGIC_OUTS_B10_4", - "CFG_CENTER_LOGIC_OUTS_B10_5", - "CFG_CENTER_LOGIC_OUTS_B10_6", - "CFG_CENTER_LOGIC_OUTS_B10_7", - "CFG_CENTER_LOGIC_OUTS_B10_8", - "CFG_CENTER_LOGIC_OUTS_B10_9", - "CFG_CENTER_LOGIC_OUTS_B11_0", - "CFG_CENTER_LOGIC_OUTS_B11_1", - "CFG_CENTER_LOGIC_OUTS_B11_10", - "CFG_CENTER_LOGIC_OUTS_B11_11", - "CFG_CENTER_LOGIC_OUTS_B11_12", - "CFG_CENTER_LOGIC_OUTS_B11_13", - "CFG_CENTER_LOGIC_OUTS_B11_14", - "CFG_CENTER_LOGIC_OUTS_B11_15", - "CFG_CENTER_LOGIC_OUTS_B11_16", - "CFG_CENTER_LOGIC_OUTS_B11_17", - "CFG_CENTER_LOGIC_OUTS_B11_18", - "CFG_CENTER_LOGIC_OUTS_B11_19", - "CFG_CENTER_LOGIC_OUTS_B11_2", - "CFG_CENTER_LOGIC_OUTS_B11_3", - "CFG_CENTER_LOGIC_OUTS_B11_4", - "CFG_CENTER_LOGIC_OUTS_B11_5", - "CFG_CENTER_LOGIC_OUTS_B11_6", - "CFG_CENTER_LOGIC_OUTS_B11_7", - "CFG_CENTER_LOGIC_OUTS_B11_8", - "CFG_CENTER_LOGIC_OUTS_B11_9", - "CFG_CENTER_LOGIC_OUTS_B12_0", - "CFG_CENTER_LOGIC_OUTS_B12_1", - "CFG_CENTER_LOGIC_OUTS_B12_10", - "CFG_CENTER_LOGIC_OUTS_B12_11", - "CFG_CENTER_LOGIC_OUTS_B12_12", - "CFG_CENTER_LOGIC_OUTS_B12_13", - "CFG_CENTER_LOGIC_OUTS_B12_14", - "CFG_CENTER_LOGIC_OUTS_B12_15", - "CFG_CENTER_LOGIC_OUTS_B12_16", - "CFG_CENTER_LOGIC_OUTS_B12_17", - "CFG_CENTER_LOGIC_OUTS_B12_18", - "CFG_CENTER_LOGIC_OUTS_B12_19", - "CFG_CENTER_LOGIC_OUTS_B12_2", - "CFG_CENTER_LOGIC_OUTS_B12_3", - "CFG_CENTER_LOGIC_OUTS_B12_4", - "CFG_CENTER_LOGIC_OUTS_B12_5", - "CFG_CENTER_LOGIC_OUTS_B12_6", - "CFG_CENTER_LOGIC_OUTS_B12_7", - "CFG_CENTER_LOGIC_OUTS_B12_8", - "CFG_CENTER_LOGIC_OUTS_B12_9", - "CFG_CENTER_LOGIC_OUTS_B13_0", - "CFG_CENTER_LOGIC_OUTS_B13_1", - "CFG_CENTER_LOGIC_OUTS_B13_10", - "CFG_CENTER_LOGIC_OUTS_B13_11", - "CFG_CENTER_LOGIC_OUTS_B13_12", - "CFG_CENTER_LOGIC_OUTS_B13_13", - "CFG_CENTER_LOGIC_OUTS_B13_14", - "CFG_CENTER_LOGIC_OUTS_B13_15", - "CFG_CENTER_LOGIC_OUTS_B13_16", - "CFG_CENTER_LOGIC_OUTS_B13_17", - "CFG_CENTER_LOGIC_OUTS_B13_18", - "CFG_CENTER_LOGIC_OUTS_B13_19", - "CFG_CENTER_LOGIC_OUTS_B13_2", - "CFG_CENTER_LOGIC_OUTS_B13_3", - "CFG_CENTER_LOGIC_OUTS_B13_4", - "CFG_CENTER_LOGIC_OUTS_B13_5", - "CFG_CENTER_LOGIC_OUTS_B13_6", - "CFG_CENTER_LOGIC_OUTS_B13_7", - "CFG_CENTER_LOGIC_OUTS_B13_8", - "CFG_CENTER_LOGIC_OUTS_B13_9", - "CFG_CENTER_LOGIC_OUTS_B14_0", - "CFG_CENTER_LOGIC_OUTS_B14_1", - "CFG_CENTER_LOGIC_OUTS_B14_10", - "CFG_CENTER_LOGIC_OUTS_B14_11", - "CFG_CENTER_LOGIC_OUTS_B14_12", - "CFG_CENTER_LOGIC_OUTS_B14_13", - "CFG_CENTER_LOGIC_OUTS_B14_14", - "CFG_CENTER_LOGIC_OUTS_B14_15", - "CFG_CENTER_LOGIC_OUTS_B14_16", - "CFG_CENTER_LOGIC_OUTS_B14_17", - "CFG_CENTER_LOGIC_OUTS_B14_18", - "CFG_CENTER_LOGIC_OUTS_B14_19", - "CFG_CENTER_LOGIC_OUTS_B14_2", - "CFG_CENTER_LOGIC_OUTS_B14_3", - "CFG_CENTER_LOGIC_OUTS_B14_4", - "CFG_CENTER_LOGIC_OUTS_B14_5", - "CFG_CENTER_LOGIC_OUTS_B14_6", - "CFG_CENTER_LOGIC_OUTS_B14_7", - "CFG_CENTER_LOGIC_OUTS_B14_8", - "CFG_CENTER_LOGIC_OUTS_B14_9", - "CFG_CENTER_LOGIC_OUTS_B15_0", - "CFG_CENTER_LOGIC_OUTS_B15_1", - "CFG_CENTER_LOGIC_OUTS_B15_10", - "CFG_CENTER_LOGIC_OUTS_B15_11", - "CFG_CENTER_LOGIC_OUTS_B15_12", - "CFG_CENTER_LOGIC_OUTS_B15_13", - "CFG_CENTER_LOGIC_OUTS_B15_14", - "CFG_CENTER_LOGIC_OUTS_B15_15", - "CFG_CENTER_LOGIC_OUTS_B15_16", - "CFG_CENTER_LOGIC_OUTS_B15_17", - "CFG_CENTER_LOGIC_OUTS_B15_18", - "CFG_CENTER_LOGIC_OUTS_B15_19", - "CFG_CENTER_LOGIC_OUTS_B15_2", - "CFG_CENTER_LOGIC_OUTS_B15_3", - "CFG_CENTER_LOGIC_OUTS_B15_4", - "CFG_CENTER_LOGIC_OUTS_B15_5", - "CFG_CENTER_LOGIC_OUTS_B15_6", - "CFG_CENTER_LOGIC_OUTS_B15_7", - "CFG_CENTER_LOGIC_OUTS_B15_8", - "CFG_CENTER_LOGIC_OUTS_B15_9", - "CFG_CENTER_LOGIC_OUTS_B16_0", - "CFG_CENTER_LOGIC_OUTS_B16_1", - "CFG_CENTER_LOGIC_OUTS_B16_10", - "CFG_CENTER_LOGIC_OUTS_B16_11", - "CFG_CENTER_LOGIC_OUTS_B16_12", - "CFG_CENTER_LOGIC_OUTS_B16_13", - "CFG_CENTER_LOGIC_OUTS_B16_14", - "CFG_CENTER_LOGIC_OUTS_B16_15", - "CFG_CENTER_LOGIC_OUTS_B16_16", - "CFG_CENTER_LOGIC_OUTS_B16_17", - "CFG_CENTER_LOGIC_OUTS_B16_18", - "CFG_CENTER_LOGIC_OUTS_B16_19", - "CFG_CENTER_LOGIC_OUTS_B16_2", - "CFG_CENTER_LOGIC_OUTS_B16_3", - "CFG_CENTER_LOGIC_OUTS_B16_4", - "CFG_CENTER_LOGIC_OUTS_B16_5", - "CFG_CENTER_LOGIC_OUTS_B16_6", - "CFG_CENTER_LOGIC_OUTS_B16_7", - "CFG_CENTER_LOGIC_OUTS_B16_8", - "CFG_CENTER_LOGIC_OUTS_B16_9", - "CFG_CENTER_LOGIC_OUTS_B17_0", - "CFG_CENTER_LOGIC_OUTS_B17_1", - "CFG_CENTER_LOGIC_OUTS_B17_10", - "CFG_CENTER_LOGIC_OUTS_B17_11", - "CFG_CENTER_LOGIC_OUTS_B17_12", - "CFG_CENTER_LOGIC_OUTS_B17_13", - "CFG_CENTER_LOGIC_OUTS_B17_14", - "CFG_CENTER_LOGIC_OUTS_B17_15", - "CFG_CENTER_LOGIC_OUTS_B17_16", - "CFG_CENTER_LOGIC_OUTS_B17_17", - "CFG_CENTER_LOGIC_OUTS_B17_18", - "CFG_CENTER_LOGIC_OUTS_B17_19", - "CFG_CENTER_LOGIC_OUTS_B17_2", - "CFG_CENTER_LOGIC_OUTS_B17_3", - "CFG_CENTER_LOGIC_OUTS_B17_4", - "CFG_CENTER_LOGIC_OUTS_B17_5", - "CFG_CENTER_LOGIC_OUTS_B17_6", - "CFG_CENTER_LOGIC_OUTS_B17_7", - "CFG_CENTER_LOGIC_OUTS_B17_8", - "CFG_CENTER_LOGIC_OUTS_B17_9", - "CFG_CENTER_LOGIC_OUTS_B18_0", - "CFG_CENTER_LOGIC_OUTS_B18_1", - "CFG_CENTER_LOGIC_OUTS_B18_10", - "CFG_CENTER_LOGIC_OUTS_B18_11", - "CFG_CENTER_LOGIC_OUTS_B18_12", - "CFG_CENTER_LOGIC_OUTS_B18_13", - "CFG_CENTER_LOGIC_OUTS_B18_14", - "CFG_CENTER_LOGIC_OUTS_B18_15", - "CFG_CENTER_LOGIC_OUTS_B18_16", - "CFG_CENTER_LOGIC_OUTS_B18_17", - "CFG_CENTER_LOGIC_OUTS_B18_18", - "CFG_CENTER_LOGIC_OUTS_B18_19", - "CFG_CENTER_LOGIC_OUTS_B18_2", - "CFG_CENTER_LOGIC_OUTS_B18_3", - "CFG_CENTER_LOGIC_OUTS_B18_4", - "CFG_CENTER_LOGIC_OUTS_B18_5", - "CFG_CENTER_LOGIC_OUTS_B18_6", - "CFG_CENTER_LOGIC_OUTS_B18_7", - "CFG_CENTER_LOGIC_OUTS_B18_8", - "CFG_CENTER_LOGIC_OUTS_B18_9", - "CFG_CENTER_LOGIC_OUTS_B19_0", - "CFG_CENTER_LOGIC_OUTS_B19_1", - "CFG_CENTER_LOGIC_OUTS_B19_10", - "CFG_CENTER_LOGIC_OUTS_B19_11", - "CFG_CENTER_LOGIC_OUTS_B19_12", - "CFG_CENTER_LOGIC_OUTS_B19_13", - "CFG_CENTER_LOGIC_OUTS_B19_14", - "CFG_CENTER_LOGIC_OUTS_B19_15", - "CFG_CENTER_LOGIC_OUTS_B19_16", - "CFG_CENTER_LOGIC_OUTS_B19_17", - "CFG_CENTER_LOGIC_OUTS_B19_18", - "CFG_CENTER_LOGIC_OUTS_B19_19", - "CFG_CENTER_LOGIC_OUTS_B19_2", - "CFG_CENTER_LOGIC_OUTS_B19_3", - "CFG_CENTER_LOGIC_OUTS_B19_4", - "CFG_CENTER_LOGIC_OUTS_B19_5", - "CFG_CENTER_LOGIC_OUTS_B19_6", - "CFG_CENTER_LOGIC_OUTS_B19_7", - "CFG_CENTER_LOGIC_OUTS_B19_8", - "CFG_CENTER_LOGIC_OUTS_B19_9", - "CFG_CENTER_LOGIC_OUTS_B1_0", - "CFG_CENTER_LOGIC_OUTS_B1_1", - "CFG_CENTER_LOGIC_OUTS_B1_10", - "CFG_CENTER_LOGIC_OUTS_B1_11", - "CFG_CENTER_LOGIC_OUTS_B1_12", - "CFG_CENTER_LOGIC_OUTS_B1_13", - "CFG_CENTER_LOGIC_OUTS_B1_14", - "CFG_CENTER_LOGIC_OUTS_B1_15", - "CFG_CENTER_LOGIC_OUTS_B1_16", - "CFG_CENTER_LOGIC_OUTS_B1_17", - "CFG_CENTER_LOGIC_OUTS_B1_18", - "CFG_CENTER_LOGIC_OUTS_B1_19", - "CFG_CENTER_LOGIC_OUTS_B1_2", - "CFG_CENTER_LOGIC_OUTS_B1_3", - "CFG_CENTER_LOGIC_OUTS_B1_4", - "CFG_CENTER_LOGIC_OUTS_B1_5", - "CFG_CENTER_LOGIC_OUTS_B1_6", - "CFG_CENTER_LOGIC_OUTS_B1_7", - "CFG_CENTER_LOGIC_OUTS_B1_8", - "CFG_CENTER_LOGIC_OUTS_B1_9", - "CFG_CENTER_LOGIC_OUTS_B20_0", - "CFG_CENTER_LOGIC_OUTS_B20_1", - "CFG_CENTER_LOGIC_OUTS_B20_10", - "CFG_CENTER_LOGIC_OUTS_B20_11", - "CFG_CENTER_LOGIC_OUTS_B20_12", - "CFG_CENTER_LOGIC_OUTS_B20_13", - "CFG_CENTER_LOGIC_OUTS_B20_14", - "CFG_CENTER_LOGIC_OUTS_B20_15", - "CFG_CENTER_LOGIC_OUTS_B20_16", - "CFG_CENTER_LOGIC_OUTS_B20_17", - "CFG_CENTER_LOGIC_OUTS_B20_18", - "CFG_CENTER_LOGIC_OUTS_B20_19", - "CFG_CENTER_LOGIC_OUTS_B20_2", - "CFG_CENTER_LOGIC_OUTS_B20_3", - "CFG_CENTER_LOGIC_OUTS_B20_4", - "CFG_CENTER_LOGIC_OUTS_B20_5", - "CFG_CENTER_LOGIC_OUTS_B20_6", - "CFG_CENTER_LOGIC_OUTS_B20_7", - "CFG_CENTER_LOGIC_OUTS_B20_8", - "CFG_CENTER_LOGIC_OUTS_B20_9", - "CFG_CENTER_LOGIC_OUTS_B21_0", - "CFG_CENTER_LOGIC_OUTS_B21_1", - "CFG_CENTER_LOGIC_OUTS_B21_10", - "CFG_CENTER_LOGIC_OUTS_B21_11", - "CFG_CENTER_LOGIC_OUTS_B21_12", - "CFG_CENTER_LOGIC_OUTS_B21_13", - "CFG_CENTER_LOGIC_OUTS_B21_14", - "CFG_CENTER_LOGIC_OUTS_B21_15", - "CFG_CENTER_LOGIC_OUTS_B21_16", - "CFG_CENTER_LOGIC_OUTS_B21_17", - "CFG_CENTER_LOGIC_OUTS_B21_18", - "CFG_CENTER_LOGIC_OUTS_B21_19", - "CFG_CENTER_LOGIC_OUTS_B21_2", - "CFG_CENTER_LOGIC_OUTS_B21_3", - "CFG_CENTER_LOGIC_OUTS_B21_4", - "CFG_CENTER_LOGIC_OUTS_B21_5", - "CFG_CENTER_LOGIC_OUTS_B21_6", - "CFG_CENTER_LOGIC_OUTS_B21_7", - "CFG_CENTER_LOGIC_OUTS_B21_8", - "CFG_CENTER_LOGIC_OUTS_B21_9", - "CFG_CENTER_LOGIC_OUTS_B22_0", - "CFG_CENTER_LOGIC_OUTS_B22_1", - "CFG_CENTER_LOGIC_OUTS_B22_10", - "CFG_CENTER_LOGIC_OUTS_B22_11", - "CFG_CENTER_LOGIC_OUTS_B22_12", - "CFG_CENTER_LOGIC_OUTS_B22_13", - "CFG_CENTER_LOGIC_OUTS_B22_14", - "CFG_CENTER_LOGIC_OUTS_B22_15", - "CFG_CENTER_LOGIC_OUTS_B22_16", - "CFG_CENTER_LOGIC_OUTS_B22_17", - "CFG_CENTER_LOGIC_OUTS_B22_18", - "CFG_CENTER_LOGIC_OUTS_B22_19", - "CFG_CENTER_LOGIC_OUTS_B22_2", - "CFG_CENTER_LOGIC_OUTS_B22_3", - "CFG_CENTER_LOGIC_OUTS_B22_4", - "CFG_CENTER_LOGIC_OUTS_B22_5", - "CFG_CENTER_LOGIC_OUTS_B22_6", - "CFG_CENTER_LOGIC_OUTS_B22_7", - "CFG_CENTER_LOGIC_OUTS_B22_8", - "CFG_CENTER_LOGIC_OUTS_B22_9", - "CFG_CENTER_LOGIC_OUTS_B23_0", - "CFG_CENTER_LOGIC_OUTS_B23_1", - "CFG_CENTER_LOGIC_OUTS_B23_10", - "CFG_CENTER_LOGIC_OUTS_B23_11", - "CFG_CENTER_LOGIC_OUTS_B23_12", - "CFG_CENTER_LOGIC_OUTS_B23_13", - "CFG_CENTER_LOGIC_OUTS_B23_14", - "CFG_CENTER_LOGIC_OUTS_B23_15", - "CFG_CENTER_LOGIC_OUTS_B23_16", - "CFG_CENTER_LOGIC_OUTS_B23_17", - "CFG_CENTER_LOGIC_OUTS_B23_18", - "CFG_CENTER_LOGIC_OUTS_B23_19", - "CFG_CENTER_LOGIC_OUTS_B23_2", - "CFG_CENTER_LOGIC_OUTS_B23_3", - "CFG_CENTER_LOGIC_OUTS_B23_4", - "CFG_CENTER_LOGIC_OUTS_B23_5", - "CFG_CENTER_LOGIC_OUTS_B23_6", - "CFG_CENTER_LOGIC_OUTS_B23_7", - "CFG_CENTER_LOGIC_OUTS_B23_8", - "CFG_CENTER_LOGIC_OUTS_B23_9", - "CFG_CENTER_LOGIC_OUTS_B2_0", - "CFG_CENTER_LOGIC_OUTS_B2_1", - "CFG_CENTER_LOGIC_OUTS_B2_10", - "CFG_CENTER_LOGIC_OUTS_B2_11", - "CFG_CENTER_LOGIC_OUTS_B2_12", - "CFG_CENTER_LOGIC_OUTS_B2_13", - "CFG_CENTER_LOGIC_OUTS_B2_14", - "CFG_CENTER_LOGIC_OUTS_B2_15", - "CFG_CENTER_LOGIC_OUTS_B2_16", - "CFG_CENTER_LOGIC_OUTS_B2_17", - "CFG_CENTER_LOGIC_OUTS_B2_18", - "CFG_CENTER_LOGIC_OUTS_B2_19", - "CFG_CENTER_LOGIC_OUTS_B2_2", - "CFG_CENTER_LOGIC_OUTS_B2_3", - "CFG_CENTER_LOGIC_OUTS_B2_4", - "CFG_CENTER_LOGIC_OUTS_B2_5", - "CFG_CENTER_LOGIC_OUTS_B2_6", - "CFG_CENTER_LOGIC_OUTS_B2_7", - "CFG_CENTER_LOGIC_OUTS_B2_8", - "CFG_CENTER_LOGIC_OUTS_B2_9", - "CFG_CENTER_LOGIC_OUTS_B3_0", - "CFG_CENTER_LOGIC_OUTS_B3_1", - "CFG_CENTER_LOGIC_OUTS_B3_10", - "CFG_CENTER_LOGIC_OUTS_B3_11", - "CFG_CENTER_LOGIC_OUTS_B3_12", - "CFG_CENTER_LOGIC_OUTS_B3_13", - "CFG_CENTER_LOGIC_OUTS_B3_14", - "CFG_CENTER_LOGIC_OUTS_B3_15", - "CFG_CENTER_LOGIC_OUTS_B3_16", - "CFG_CENTER_LOGIC_OUTS_B3_17", - "CFG_CENTER_LOGIC_OUTS_B3_18", - "CFG_CENTER_LOGIC_OUTS_B3_19", - "CFG_CENTER_LOGIC_OUTS_B3_2", - "CFG_CENTER_LOGIC_OUTS_B3_3", - "CFG_CENTER_LOGIC_OUTS_B3_4", - "CFG_CENTER_LOGIC_OUTS_B3_5", - "CFG_CENTER_LOGIC_OUTS_B3_6", - "CFG_CENTER_LOGIC_OUTS_B3_7", - "CFG_CENTER_LOGIC_OUTS_B3_8", - "CFG_CENTER_LOGIC_OUTS_B3_9", - "CFG_CENTER_LOGIC_OUTS_B4_0", - "CFG_CENTER_LOGIC_OUTS_B4_1", - "CFG_CENTER_LOGIC_OUTS_B4_10", - "CFG_CENTER_LOGIC_OUTS_B4_11", - "CFG_CENTER_LOGIC_OUTS_B4_12", - "CFG_CENTER_LOGIC_OUTS_B4_13", - "CFG_CENTER_LOGIC_OUTS_B4_14", - "CFG_CENTER_LOGIC_OUTS_B4_15", - "CFG_CENTER_LOGIC_OUTS_B4_16", - "CFG_CENTER_LOGIC_OUTS_B4_17", - "CFG_CENTER_LOGIC_OUTS_B4_18", - "CFG_CENTER_LOGIC_OUTS_B4_19", - "CFG_CENTER_LOGIC_OUTS_B4_2", - "CFG_CENTER_LOGIC_OUTS_B4_3", - "CFG_CENTER_LOGIC_OUTS_B4_4", - "CFG_CENTER_LOGIC_OUTS_B4_5", - "CFG_CENTER_LOGIC_OUTS_B4_6", - "CFG_CENTER_LOGIC_OUTS_B4_7", - "CFG_CENTER_LOGIC_OUTS_B4_8", - "CFG_CENTER_LOGIC_OUTS_B4_9", - "CFG_CENTER_LOGIC_OUTS_B5_0", - "CFG_CENTER_LOGIC_OUTS_B5_1", - "CFG_CENTER_LOGIC_OUTS_B5_10", - "CFG_CENTER_LOGIC_OUTS_B5_11", - "CFG_CENTER_LOGIC_OUTS_B5_12", - "CFG_CENTER_LOGIC_OUTS_B5_13", - "CFG_CENTER_LOGIC_OUTS_B5_14", - "CFG_CENTER_LOGIC_OUTS_B5_15", - "CFG_CENTER_LOGIC_OUTS_B5_16", - "CFG_CENTER_LOGIC_OUTS_B5_17", - "CFG_CENTER_LOGIC_OUTS_B5_18", - "CFG_CENTER_LOGIC_OUTS_B5_19", - "CFG_CENTER_LOGIC_OUTS_B5_2", - "CFG_CENTER_LOGIC_OUTS_B5_3", - "CFG_CENTER_LOGIC_OUTS_B5_4", - "CFG_CENTER_LOGIC_OUTS_B5_5", - "CFG_CENTER_LOGIC_OUTS_B5_6", - "CFG_CENTER_LOGIC_OUTS_B5_7", - "CFG_CENTER_LOGIC_OUTS_B5_8", - "CFG_CENTER_LOGIC_OUTS_B5_9", - "CFG_CENTER_LOGIC_OUTS_B6_0", - "CFG_CENTER_LOGIC_OUTS_B6_1", - "CFG_CENTER_LOGIC_OUTS_B6_10", - "CFG_CENTER_LOGIC_OUTS_B6_11", - "CFG_CENTER_LOGIC_OUTS_B6_12", - "CFG_CENTER_LOGIC_OUTS_B6_13", - "CFG_CENTER_LOGIC_OUTS_B6_14", - "CFG_CENTER_LOGIC_OUTS_B6_15", - "CFG_CENTER_LOGIC_OUTS_B6_16", - "CFG_CENTER_LOGIC_OUTS_B6_17", - "CFG_CENTER_LOGIC_OUTS_B6_18", - "CFG_CENTER_LOGIC_OUTS_B6_19", - "CFG_CENTER_LOGIC_OUTS_B6_2", - "CFG_CENTER_LOGIC_OUTS_B6_3", - "CFG_CENTER_LOGIC_OUTS_B6_4", - "CFG_CENTER_LOGIC_OUTS_B6_5", - "CFG_CENTER_LOGIC_OUTS_B6_6", - "CFG_CENTER_LOGIC_OUTS_B6_7", - "CFG_CENTER_LOGIC_OUTS_B6_8", - "CFG_CENTER_LOGIC_OUTS_B6_9", - "CFG_CENTER_LOGIC_OUTS_B7_0", - "CFG_CENTER_LOGIC_OUTS_B7_1", - "CFG_CENTER_LOGIC_OUTS_B7_10", - "CFG_CENTER_LOGIC_OUTS_B7_11", - "CFG_CENTER_LOGIC_OUTS_B7_12", - "CFG_CENTER_LOGIC_OUTS_B7_13", - "CFG_CENTER_LOGIC_OUTS_B7_14", - "CFG_CENTER_LOGIC_OUTS_B7_15", - "CFG_CENTER_LOGIC_OUTS_B7_16", - "CFG_CENTER_LOGIC_OUTS_B7_17", - "CFG_CENTER_LOGIC_OUTS_B7_18", - "CFG_CENTER_LOGIC_OUTS_B7_19", - "CFG_CENTER_LOGIC_OUTS_B7_2", - "CFG_CENTER_LOGIC_OUTS_B7_3", - "CFG_CENTER_LOGIC_OUTS_B7_4", - "CFG_CENTER_LOGIC_OUTS_B7_5", - "CFG_CENTER_LOGIC_OUTS_B7_6", - "CFG_CENTER_LOGIC_OUTS_B7_7", - "CFG_CENTER_LOGIC_OUTS_B7_8", - "CFG_CENTER_LOGIC_OUTS_B7_9", - "CFG_CENTER_LOGIC_OUTS_B8_0", - "CFG_CENTER_LOGIC_OUTS_B8_1", - "CFG_CENTER_LOGIC_OUTS_B8_10", - "CFG_CENTER_LOGIC_OUTS_B8_11", - "CFG_CENTER_LOGIC_OUTS_B8_12", - "CFG_CENTER_LOGIC_OUTS_B8_13", - "CFG_CENTER_LOGIC_OUTS_B8_14", - "CFG_CENTER_LOGIC_OUTS_B8_15", - "CFG_CENTER_LOGIC_OUTS_B8_16", - "CFG_CENTER_LOGIC_OUTS_B8_17", - "CFG_CENTER_LOGIC_OUTS_B8_18", - "CFG_CENTER_LOGIC_OUTS_B8_19", - "CFG_CENTER_LOGIC_OUTS_B8_2", - "CFG_CENTER_LOGIC_OUTS_B8_3", - "CFG_CENTER_LOGIC_OUTS_B8_4", - "CFG_CENTER_LOGIC_OUTS_B8_5", - "CFG_CENTER_LOGIC_OUTS_B8_6", - "CFG_CENTER_LOGIC_OUTS_B8_7", - "CFG_CENTER_LOGIC_OUTS_B8_8", - "CFG_CENTER_LOGIC_OUTS_B8_9", - "CFG_CENTER_LOGIC_OUTS_B9_0", - "CFG_CENTER_LOGIC_OUTS_B9_1", - "CFG_CENTER_LOGIC_OUTS_B9_10", - "CFG_CENTER_LOGIC_OUTS_B9_11", - "CFG_CENTER_LOGIC_OUTS_B9_12", - "CFG_CENTER_LOGIC_OUTS_B9_13", - "CFG_CENTER_LOGIC_OUTS_B9_14", - "CFG_CENTER_LOGIC_OUTS_B9_15", - "CFG_CENTER_LOGIC_OUTS_B9_16", - "CFG_CENTER_LOGIC_OUTS_B9_17", - "CFG_CENTER_LOGIC_OUTS_B9_18", - "CFG_CENTER_LOGIC_OUTS_B9_19", - "CFG_CENTER_LOGIC_OUTS_B9_2", - "CFG_CENTER_LOGIC_OUTS_B9_3", - "CFG_CENTER_LOGIC_OUTS_B9_4", - "CFG_CENTER_LOGIC_OUTS_B9_5", - "CFG_CENTER_LOGIC_OUTS_B9_6", - "CFG_CENTER_LOGIC_OUTS_B9_7", - "CFG_CENTER_LOGIC_OUTS_B9_8", - "CFG_CENTER_LOGIC_OUTS_B9_9", - "CFG_CENTER_NE2A0_0", - "CFG_CENTER_NE2A0_1", - "CFG_CENTER_NE2A0_10", - "CFG_CENTER_NE2A0_11", - "CFG_CENTER_NE2A0_12", - "CFG_CENTER_NE2A0_13", - "CFG_CENTER_NE2A0_14", - "CFG_CENTER_NE2A0_15", - "CFG_CENTER_NE2A0_16", - "CFG_CENTER_NE2A0_17", - "CFG_CENTER_NE2A0_18", - "CFG_CENTER_NE2A0_19", - "CFG_CENTER_NE2A0_2", - "CFG_CENTER_NE2A0_3", - "CFG_CENTER_NE2A0_4", - "CFG_CENTER_NE2A0_5", - "CFG_CENTER_NE2A0_6", - "CFG_CENTER_NE2A0_7", - "CFG_CENTER_NE2A0_8", - "CFG_CENTER_NE2A0_9", - "CFG_CENTER_NE2A1_0", - "CFG_CENTER_NE2A1_1", - "CFG_CENTER_NE2A1_10", - "CFG_CENTER_NE2A1_11", - "CFG_CENTER_NE2A1_12", - "CFG_CENTER_NE2A1_13", - "CFG_CENTER_NE2A1_14", - "CFG_CENTER_NE2A1_15", - "CFG_CENTER_NE2A1_16", - "CFG_CENTER_NE2A1_17", - "CFG_CENTER_NE2A1_18", - "CFG_CENTER_NE2A1_19", - "CFG_CENTER_NE2A1_2", - "CFG_CENTER_NE2A1_3", - "CFG_CENTER_NE2A1_4", - "CFG_CENTER_NE2A1_5", - "CFG_CENTER_NE2A1_6", - "CFG_CENTER_NE2A1_7", - "CFG_CENTER_NE2A1_8", - "CFG_CENTER_NE2A1_9", - "CFG_CENTER_NE2A2_0", - "CFG_CENTER_NE2A2_1", - "CFG_CENTER_NE2A2_10", - "CFG_CENTER_NE2A2_11", - "CFG_CENTER_NE2A2_12", - "CFG_CENTER_NE2A2_13", - "CFG_CENTER_NE2A2_14", - "CFG_CENTER_NE2A2_15", - "CFG_CENTER_NE2A2_16", - "CFG_CENTER_NE2A2_17", - "CFG_CENTER_NE2A2_18", - "CFG_CENTER_NE2A2_19", - "CFG_CENTER_NE2A2_2", - "CFG_CENTER_NE2A2_3", - "CFG_CENTER_NE2A2_4", - "CFG_CENTER_NE2A2_5", - "CFG_CENTER_NE2A2_6", - "CFG_CENTER_NE2A2_7", - "CFG_CENTER_NE2A2_8", - "CFG_CENTER_NE2A2_9", - "CFG_CENTER_NE2A3_0", - "CFG_CENTER_NE2A3_1", - "CFG_CENTER_NE2A3_10", - "CFG_CENTER_NE2A3_11", - "CFG_CENTER_NE2A3_12", - "CFG_CENTER_NE2A3_13", - "CFG_CENTER_NE2A3_14", - "CFG_CENTER_NE2A3_15", - "CFG_CENTER_NE2A3_16", - "CFG_CENTER_NE2A3_17", - "CFG_CENTER_NE2A3_18", - "CFG_CENTER_NE2A3_19", - "CFG_CENTER_NE2A3_2", - "CFG_CENTER_NE2A3_3", - "CFG_CENTER_NE2A3_4", - "CFG_CENTER_NE2A3_5", - "CFG_CENTER_NE2A3_6", - "CFG_CENTER_NE2A3_7", - "CFG_CENTER_NE2A3_8", - "CFG_CENTER_NE2A3_9", - "CFG_CENTER_NE4BEG0_0", - "CFG_CENTER_NE4BEG0_1", - "CFG_CENTER_NE4BEG0_10", - "CFG_CENTER_NE4BEG0_11", - "CFG_CENTER_NE4BEG0_12", - "CFG_CENTER_NE4BEG0_13", - "CFG_CENTER_NE4BEG0_14", - "CFG_CENTER_NE4BEG0_15", - "CFG_CENTER_NE4BEG0_16", - "CFG_CENTER_NE4BEG0_17", - "CFG_CENTER_NE4BEG0_18", - "CFG_CENTER_NE4BEG0_19", - "CFG_CENTER_NE4BEG0_2", - "CFG_CENTER_NE4BEG0_3", - "CFG_CENTER_NE4BEG0_4", - "CFG_CENTER_NE4BEG0_5", - "CFG_CENTER_NE4BEG0_6", - "CFG_CENTER_NE4BEG0_7", - "CFG_CENTER_NE4BEG0_8", - "CFG_CENTER_NE4BEG0_9", - "CFG_CENTER_NE4BEG1_0", - "CFG_CENTER_NE4BEG1_1", - "CFG_CENTER_NE4BEG1_10", - "CFG_CENTER_NE4BEG1_11", - "CFG_CENTER_NE4BEG1_12", - "CFG_CENTER_NE4BEG1_13", - "CFG_CENTER_NE4BEG1_14", - "CFG_CENTER_NE4BEG1_15", - "CFG_CENTER_NE4BEG1_16", - "CFG_CENTER_NE4BEG1_17", - "CFG_CENTER_NE4BEG1_18", - "CFG_CENTER_NE4BEG1_19", - "CFG_CENTER_NE4BEG1_2", - "CFG_CENTER_NE4BEG1_3", - "CFG_CENTER_NE4BEG1_4", - "CFG_CENTER_NE4BEG1_5", - "CFG_CENTER_NE4BEG1_6", - "CFG_CENTER_NE4BEG1_7", - "CFG_CENTER_NE4BEG1_8", - "CFG_CENTER_NE4BEG1_9", - "CFG_CENTER_NE4BEG2_0", - "CFG_CENTER_NE4BEG2_1", - "CFG_CENTER_NE4BEG2_10", - "CFG_CENTER_NE4BEG2_11", - "CFG_CENTER_NE4BEG2_12", - "CFG_CENTER_NE4BEG2_13", - "CFG_CENTER_NE4BEG2_14", - "CFG_CENTER_NE4BEG2_15", - "CFG_CENTER_NE4BEG2_16", - "CFG_CENTER_NE4BEG2_17", - "CFG_CENTER_NE4BEG2_18", - "CFG_CENTER_NE4BEG2_19", - "CFG_CENTER_NE4BEG2_2", - "CFG_CENTER_NE4BEG2_3", - "CFG_CENTER_NE4BEG2_4", - "CFG_CENTER_NE4BEG2_5", - "CFG_CENTER_NE4BEG2_6", - "CFG_CENTER_NE4BEG2_7", - "CFG_CENTER_NE4BEG2_8", - "CFG_CENTER_NE4BEG2_9", - "CFG_CENTER_NE4BEG3_0", - "CFG_CENTER_NE4BEG3_1", - "CFG_CENTER_NE4BEG3_10", - "CFG_CENTER_NE4BEG3_11", - "CFG_CENTER_NE4BEG3_12", - "CFG_CENTER_NE4BEG3_13", - "CFG_CENTER_NE4BEG3_14", - "CFG_CENTER_NE4BEG3_15", - "CFG_CENTER_NE4BEG3_16", - "CFG_CENTER_NE4BEG3_17", - "CFG_CENTER_NE4BEG3_18", - "CFG_CENTER_NE4BEG3_19", - "CFG_CENTER_NE4BEG3_2", - "CFG_CENTER_NE4BEG3_3", - "CFG_CENTER_NE4BEG3_4", - "CFG_CENTER_NE4BEG3_5", - "CFG_CENTER_NE4BEG3_6", - "CFG_CENTER_NE4BEG3_7", - "CFG_CENTER_NE4BEG3_8", - "CFG_CENTER_NE4BEG3_9", - "CFG_CENTER_NE4C0_0", - "CFG_CENTER_NE4C0_1", - "CFG_CENTER_NE4C0_10", - "CFG_CENTER_NE4C0_11", - "CFG_CENTER_NE4C0_12", - "CFG_CENTER_NE4C0_13", - "CFG_CENTER_NE4C0_14", - "CFG_CENTER_NE4C0_15", - "CFG_CENTER_NE4C0_16", - "CFG_CENTER_NE4C0_17", - "CFG_CENTER_NE4C0_18", - "CFG_CENTER_NE4C0_19", - "CFG_CENTER_NE4C0_2", - "CFG_CENTER_NE4C0_3", - "CFG_CENTER_NE4C0_4", - "CFG_CENTER_NE4C0_5", - "CFG_CENTER_NE4C0_6", - "CFG_CENTER_NE4C0_7", - "CFG_CENTER_NE4C0_8", - "CFG_CENTER_NE4C0_9", - "CFG_CENTER_NE4C1_0", - "CFG_CENTER_NE4C1_1", - "CFG_CENTER_NE4C1_10", - "CFG_CENTER_NE4C1_11", - "CFG_CENTER_NE4C1_12", - "CFG_CENTER_NE4C1_13", - "CFG_CENTER_NE4C1_14", - "CFG_CENTER_NE4C1_15", - "CFG_CENTER_NE4C1_16", - "CFG_CENTER_NE4C1_17", - "CFG_CENTER_NE4C1_18", - "CFG_CENTER_NE4C1_19", - "CFG_CENTER_NE4C1_2", - "CFG_CENTER_NE4C1_3", - "CFG_CENTER_NE4C1_4", - "CFG_CENTER_NE4C1_5", - "CFG_CENTER_NE4C1_6", - "CFG_CENTER_NE4C1_7", - "CFG_CENTER_NE4C1_8", - "CFG_CENTER_NE4C1_9", - "CFG_CENTER_NE4C2_0", - "CFG_CENTER_NE4C2_1", - "CFG_CENTER_NE4C2_10", - "CFG_CENTER_NE4C2_11", - "CFG_CENTER_NE4C2_12", - "CFG_CENTER_NE4C2_13", - "CFG_CENTER_NE4C2_14", - "CFG_CENTER_NE4C2_15", - "CFG_CENTER_NE4C2_16", - "CFG_CENTER_NE4C2_17", - "CFG_CENTER_NE4C2_18", - "CFG_CENTER_NE4C2_19", - "CFG_CENTER_NE4C2_2", - "CFG_CENTER_NE4C2_3", - "CFG_CENTER_NE4C2_4", - "CFG_CENTER_NE4C2_5", - "CFG_CENTER_NE4C2_6", - "CFG_CENTER_NE4C2_7", - "CFG_CENTER_NE4C2_8", - "CFG_CENTER_NE4C2_9", - "CFG_CENTER_NE4C3_0", - "CFG_CENTER_NE4C3_1", - "CFG_CENTER_NE4C3_10", - "CFG_CENTER_NE4C3_11", - "CFG_CENTER_NE4C3_12", - "CFG_CENTER_NE4C3_13", - "CFG_CENTER_NE4C3_14", - "CFG_CENTER_NE4C3_15", - "CFG_CENTER_NE4C3_16", - "CFG_CENTER_NE4C3_17", - "CFG_CENTER_NE4C3_18", - "CFG_CENTER_NE4C3_19", - "CFG_CENTER_NE4C3_2", - "CFG_CENTER_NE4C3_3", - "CFG_CENTER_NE4C3_4", - "CFG_CENTER_NE4C3_5", - "CFG_CENTER_NE4C3_6", - "CFG_CENTER_NE4C3_7", - "CFG_CENTER_NE4C3_8", - "CFG_CENTER_NE4C3_9", - "CFG_CENTER_NW2A0_0", - "CFG_CENTER_NW2A0_1", - "CFG_CENTER_NW2A0_10", - "CFG_CENTER_NW2A0_11", - "CFG_CENTER_NW2A0_12", - "CFG_CENTER_NW2A0_13", - "CFG_CENTER_NW2A0_14", - "CFG_CENTER_NW2A0_15", - "CFG_CENTER_NW2A0_16", - "CFG_CENTER_NW2A0_17", - "CFG_CENTER_NW2A0_18", - "CFG_CENTER_NW2A0_19", - "CFG_CENTER_NW2A0_2", - "CFG_CENTER_NW2A0_3", - "CFG_CENTER_NW2A0_4", - "CFG_CENTER_NW2A0_5", - "CFG_CENTER_NW2A0_6", - "CFG_CENTER_NW2A0_7", - "CFG_CENTER_NW2A0_8", - "CFG_CENTER_NW2A0_9", - "CFG_CENTER_NW2A1_0", - "CFG_CENTER_NW2A1_1", - "CFG_CENTER_NW2A1_10", - "CFG_CENTER_NW2A1_11", - "CFG_CENTER_NW2A1_12", - "CFG_CENTER_NW2A1_13", - "CFG_CENTER_NW2A1_14", - "CFG_CENTER_NW2A1_15", - "CFG_CENTER_NW2A1_16", - "CFG_CENTER_NW2A1_17", - "CFG_CENTER_NW2A1_18", - "CFG_CENTER_NW2A1_19", - "CFG_CENTER_NW2A1_2", - "CFG_CENTER_NW2A1_3", - "CFG_CENTER_NW2A1_4", - "CFG_CENTER_NW2A1_5", - "CFG_CENTER_NW2A1_6", - "CFG_CENTER_NW2A1_7", - "CFG_CENTER_NW2A1_8", - "CFG_CENTER_NW2A1_9", - "CFG_CENTER_NW2A2_0", - "CFG_CENTER_NW2A2_1", - "CFG_CENTER_NW2A2_10", - "CFG_CENTER_NW2A2_11", - "CFG_CENTER_NW2A2_12", - "CFG_CENTER_NW2A2_13", - "CFG_CENTER_NW2A2_14", - "CFG_CENTER_NW2A2_15", - "CFG_CENTER_NW2A2_16", - "CFG_CENTER_NW2A2_17", - "CFG_CENTER_NW2A2_18", - "CFG_CENTER_NW2A2_19", - "CFG_CENTER_NW2A2_2", - "CFG_CENTER_NW2A2_3", - "CFG_CENTER_NW2A2_4", - "CFG_CENTER_NW2A2_5", - "CFG_CENTER_NW2A2_6", - "CFG_CENTER_NW2A2_7", - "CFG_CENTER_NW2A2_8", - "CFG_CENTER_NW2A2_9", - "CFG_CENTER_NW2A3_0", - "CFG_CENTER_NW2A3_1", - "CFG_CENTER_NW2A3_10", - "CFG_CENTER_NW2A3_11", - "CFG_CENTER_NW2A3_12", - "CFG_CENTER_NW2A3_13", - "CFG_CENTER_NW2A3_14", - "CFG_CENTER_NW2A3_15", - "CFG_CENTER_NW2A3_16", - "CFG_CENTER_NW2A3_17", - "CFG_CENTER_NW2A3_18", - "CFG_CENTER_NW2A3_19", - "CFG_CENTER_NW2A3_2", - "CFG_CENTER_NW2A3_3", - "CFG_CENTER_NW2A3_4", - "CFG_CENTER_NW2A3_5", - "CFG_CENTER_NW2A3_6", - "CFG_CENTER_NW2A3_7", - "CFG_CENTER_NW2A3_8", - "CFG_CENTER_NW2A3_9", - "CFG_CENTER_NW4A0_0", - "CFG_CENTER_NW4A0_1", - "CFG_CENTER_NW4A0_10", - "CFG_CENTER_NW4A0_11", - "CFG_CENTER_NW4A0_12", - "CFG_CENTER_NW4A0_13", - "CFG_CENTER_NW4A0_14", - "CFG_CENTER_NW4A0_15", - "CFG_CENTER_NW4A0_16", - "CFG_CENTER_NW4A0_17", - "CFG_CENTER_NW4A0_18", - "CFG_CENTER_NW4A0_19", - "CFG_CENTER_NW4A0_2", - "CFG_CENTER_NW4A0_3", - "CFG_CENTER_NW4A0_4", - "CFG_CENTER_NW4A0_5", - "CFG_CENTER_NW4A0_6", - "CFG_CENTER_NW4A0_7", - "CFG_CENTER_NW4A0_8", - "CFG_CENTER_NW4A0_9", - "CFG_CENTER_NW4A1_0", - "CFG_CENTER_NW4A1_1", - "CFG_CENTER_NW4A1_10", - "CFG_CENTER_NW4A1_11", - "CFG_CENTER_NW4A1_12", - "CFG_CENTER_NW4A1_13", - "CFG_CENTER_NW4A1_14", - "CFG_CENTER_NW4A1_15", - "CFG_CENTER_NW4A1_16", - "CFG_CENTER_NW4A1_17", - "CFG_CENTER_NW4A1_18", - "CFG_CENTER_NW4A1_19", - "CFG_CENTER_NW4A1_2", - "CFG_CENTER_NW4A1_3", - "CFG_CENTER_NW4A1_4", - "CFG_CENTER_NW4A1_5", - "CFG_CENTER_NW4A1_6", - "CFG_CENTER_NW4A1_7", - "CFG_CENTER_NW4A1_8", - "CFG_CENTER_NW4A1_9", - "CFG_CENTER_NW4A2_0", - "CFG_CENTER_NW4A2_1", - "CFG_CENTER_NW4A2_10", - "CFG_CENTER_NW4A2_11", - "CFG_CENTER_NW4A2_12", - "CFG_CENTER_NW4A2_13", - "CFG_CENTER_NW4A2_14", - "CFG_CENTER_NW4A2_15", - "CFG_CENTER_NW4A2_16", - "CFG_CENTER_NW4A2_17", - "CFG_CENTER_NW4A2_18", - "CFG_CENTER_NW4A2_19", - "CFG_CENTER_NW4A2_2", - "CFG_CENTER_NW4A2_3", - "CFG_CENTER_NW4A2_4", - "CFG_CENTER_NW4A2_5", - "CFG_CENTER_NW4A2_6", - "CFG_CENTER_NW4A2_7", - "CFG_CENTER_NW4A2_8", - "CFG_CENTER_NW4A2_9", - "CFG_CENTER_NW4A3_0", - "CFG_CENTER_NW4A3_1", - "CFG_CENTER_NW4A3_10", - "CFG_CENTER_NW4A3_11", - "CFG_CENTER_NW4A3_12", - "CFG_CENTER_NW4A3_13", - "CFG_CENTER_NW4A3_14", - "CFG_CENTER_NW4A3_15", - "CFG_CENTER_NW4A3_16", - "CFG_CENTER_NW4A3_17", - "CFG_CENTER_NW4A3_18", - "CFG_CENTER_NW4A3_19", - "CFG_CENTER_NW4A3_2", - "CFG_CENTER_NW4A3_3", - "CFG_CENTER_NW4A3_4", - "CFG_CENTER_NW4A3_5", - "CFG_CENTER_NW4A3_6", - "CFG_CENTER_NW4A3_7", - "CFG_CENTER_NW4A3_8", - "CFG_CENTER_NW4A3_9", - "CFG_CENTER_NW4END0_0", - "CFG_CENTER_NW4END0_1", - "CFG_CENTER_NW4END0_10", - "CFG_CENTER_NW4END0_11", - "CFG_CENTER_NW4END0_12", - "CFG_CENTER_NW4END0_13", - "CFG_CENTER_NW4END0_14", - "CFG_CENTER_NW4END0_15", - "CFG_CENTER_NW4END0_16", - "CFG_CENTER_NW4END0_17", - "CFG_CENTER_NW4END0_18", - "CFG_CENTER_NW4END0_19", - "CFG_CENTER_NW4END0_2", - "CFG_CENTER_NW4END0_3", - "CFG_CENTER_NW4END0_4", - "CFG_CENTER_NW4END0_5", - "CFG_CENTER_NW4END0_6", - "CFG_CENTER_NW4END0_7", - "CFG_CENTER_NW4END0_8", - "CFG_CENTER_NW4END0_9", - "CFG_CENTER_NW4END1_0", - "CFG_CENTER_NW4END1_1", - "CFG_CENTER_NW4END1_10", - "CFG_CENTER_NW4END1_11", - "CFG_CENTER_NW4END1_12", - "CFG_CENTER_NW4END1_13", - "CFG_CENTER_NW4END1_14", - "CFG_CENTER_NW4END1_15", - "CFG_CENTER_NW4END1_16", - "CFG_CENTER_NW4END1_17", - "CFG_CENTER_NW4END1_18", - "CFG_CENTER_NW4END1_19", - "CFG_CENTER_NW4END1_2", - "CFG_CENTER_NW4END1_3", - "CFG_CENTER_NW4END1_4", - "CFG_CENTER_NW4END1_5", - "CFG_CENTER_NW4END1_6", - "CFG_CENTER_NW4END1_7", - "CFG_CENTER_NW4END1_8", - "CFG_CENTER_NW4END1_9", - "CFG_CENTER_NW4END2_0", - "CFG_CENTER_NW4END2_1", - "CFG_CENTER_NW4END2_10", - "CFG_CENTER_NW4END2_11", - "CFG_CENTER_NW4END2_12", - "CFG_CENTER_NW4END2_13", - "CFG_CENTER_NW4END2_14", - "CFG_CENTER_NW4END2_15", - "CFG_CENTER_NW4END2_16", - "CFG_CENTER_NW4END2_17", - "CFG_CENTER_NW4END2_18", - "CFG_CENTER_NW4END2_19", - "CFG_CENTER_NW4END2_2", - "CFG_CENTER_NW4END2_3", - "CFG_CENTER_NW4END2_4", - "CFG_CENTER_NW4END2_5", - "CFG_CENTER_NW4END2_6", - "CFG_CENTER_NW4END2_7", - "CFG_CENTER_NW4END2_8", - "CFG_CENTER_NW4END2_9", - "CFG_CENTER_NW4END3_0", - "CFG_CENTER_NW4END3_1", - "CFG_CENTER_NW4END3_10", - "CFG_CENTER_NW4END3_11", - "CFG_CENTER_NW4END3_12", - "CFG_CENTER_NW4END3_13", - "CFG_CENTER_NW4END3_14", - "CFG_CENTER_NW4END3_15", - "CFG_CENTER_NW4END3_16", - "CFG_CENTER_NW4END3_17", - "CFG_CENTER_NW4END3_18", - "CFG_CENTER_NW4END3_19", - "CFG_CENTER_NW4END3_2", - "CFG_CENTER_NW4END3_3", - "CFG_CENTER_NW4END3_4", - "CFG_CENTER_NW4END3_5", - "CFG_CENTER_NW4END3_6", - "CFG_CENTER_NW4END3_7", - "CFG_CENTER_NW4END3_8", - "CFG_CENTER_NW4END3_9", - "CFG_CENTER_SE2A0_0", - "CFG_CENTER_SE2A0_1", - "CFG_CENTER_SE2A0_10", - "CFG_CENTER_SE2A0_11", - "CFG_CENTER_SE2A0_12", - "CFG_CENTER_SE2A0_13", - "CFG_CENTER_SE2A0_14", - "CFG_CENTER_SE2A0_15", - "CFG_CENTER_SE2A0_16", - "CFG_CENTER_SE2A0_17", - "CFG_CENTER_SE2A0_18", - "CFG_CENTER_SE2A0_19", - "CFG_CENTER_SE2A0_2", - "CFG_CENTER_SE2A0_3", - "CFG_CENTER_SE2A0_4", - "CFG_CENTER_SE2A0_5", - "CFG_CENTER_SE2A0_6", - "CFG_CENTER_SE2A0_7", - "CFG_CENTER_SE2A0_8", - "CFG_CENTER_SE2A0_9", - "CFG_CENTER_SE2A1_0", - "CFG_CENTER_SE2A1_1", - "CFG_CENTER_SE2A1_10", - "CFG_CENTER_SE2A1_11", - "CFG_CENTER_SE2A1_12", - "CFG_CENTER_SE2A1_13", - "CFG_CENTER_SE2A1_14", - "CFG_CENTER_SE2A1_15", - "CFG_CENTER_SE2A1_16", - "CFG_CENTER_SE2A1_17", - "CFG_CENTER_SE2A1_18", - "CFG_CENTER_SE2A1_19", - "CFG_CENTER_SE2A1_2", - "CFG_CENTER_SE2A1_3", - "CFG_CENTER_SE2A1_4", - "CFG_CENTER_SE2A1_5", - "CFG_CENTER_SE2A1_6", - "CFG_CENTER_SE2A1_7", - "CFG_CENTER_SE2A1_8", - "CFG_CENTER_SE2A1_9", - "CFG_CENTER_SE2A2_0", - "CFG_CENTER_SE2A2_1", - "CFG_CENTER_SE2A2_10", - "CFG_CENTER_SE2A2_11", - "CFG_CENTER_SE2A2_12", - "CFG_CENTER_SE2A2_13", - "CFG_CENTER_SE2A2_14", - "CFG_CENTER_SE2A2_15", - "CFG_CENTER_SE2A2_16", - "CFG_CENTER_SE2A2_17", - "CFG_CENTER_SE2A2_18", - "CFG_CENTER_SE2A2_19", - "CFG_CENTER_SE2A2_2", - "CFG_CENTER_SE2A2_3", - "CFG_CENTER_SE2A2_4", - "CFG_CENTER_SE2A2_5", - "CFG_CENTER_SE2A2_6", - "CFG_CENTER_SE2A2_7", - "CFG_CENTER_SE2A2_8", - "CFG_CENTER_SE2A2_9", - "CFG_CENTER_SE2A3_0", - "CFG_CENTER_SE2A3_1", - "CFG_CENTER_SE2A3_10", - "CFG_CENTER_SE2A3_11", - "CFG_CENTER_SE2A3_12", - "CFG_CENTER_SE2A3_13", - "CFG_CENTER_SE2A3_14", - "CFG_CENTER_SE2A3_15", - "CFG_CENTER_SE2A3_16", - "CFG_CENTER_SE2A3_17", - "CFG_CENTER_SE2A3_18", - "CFG_CENTER_SE2A3_19", - "CFG_CENTER_SE2A3_2", - "CFG_CENTER_SE2A3_3", - "CFG_CENTER_SE2A3_4", - "CFG_CENTER_SE2A3_5", - "CFG_CENTER_SE2A3_6", - "CFG_CENTER_SE2A3_7", - "CFG_CENTER_SE2A3_8", - "CFG_CENTER_SE2A3_9", - "CFG_CENTER_SE4BEG0_0", - "CFG_CENTER_SE4BEG0_1", - "CFG_CENTER_SE4BEG0_10", - "CFG_CENTER_SE4BEG0_11", - "CFG_CENTER_SE4BEG0_12", - "CFG_CENTER_SE4BEG0_13", - "CFG_CENTER_SE4BEG0_14", - "CFG_CENTER_SE4BEG0_15", - "CFG_CENTER_SE4BEG0_16", - "CFG_CENTER_SE4BEG0_17", - "CFG_CENTER_SE4BEG0_18", - "CFG_CENTER_SE4BEG0_19", - "CFG_CENTER_SE4BEG0_2", - "CFG_CENTER_SE4BEG0_3", - "CFG_CENTER_SE4BEG0_4", - "CFG_CENTER_SE4BEG0_5", - "CFG_CENTER_SE4BEG0_6", - "CFG_CENTER_SE4BEG0_7", - "CFG_CENTER_SE4BEG0_8", - "CFG_CENTER_SE4BEG0_9", - "CFG_CENTER_SE4BEG1_0", - "CFG_CENTER_SE4BEG1_1", - "CFG_CENTER_SE4BEG1_10", - "CFG_CENTER_SE4BEG1_11", - "CFG_CENTER_SE4BEG1_12", - "CFG_CENTER_SE4BEG1_13", - "CFG_CENTER_SE4BEG1_14", - "CFG_CENTER_SE4BEG1_15", - "CFG_CENTER_SE4BEG1_16", - "CFG_CENTER_SE4BEG1_17", - "CFG_CENTER_SE4BEG1_18", - "CFG_CENTER_SE4BEG1_19", - "CFG_CENTER_SE4BEG1_2", - "CFG_CENTER_SE4BEG1_3", - "CFG_CENTER_SE4BEG1_4", - "CFG_CENTER_SE4BEG1_5", - "CFG_CENTER_SE4BEG1_6", - "CFG_CENTER_SE4BEG1_7", - "CFG_CENTER_SE4BEG1_8", - "CFG_CENTER_SE4BEG1_9", - "CFG_CENTER_SE4BEG2_0", - "CFG_CENTER_SE4BEG2_1", - "CFG_CENTER_SE4BEG2_10", - "CFG_CENTER_SE4BEG2_11", - "CFG_CENTER_SE4BEG2_12", - "CFG_CENTER_SE4BEG2_13", - "CFG_CENTER_SE4BEG2_14", - "CFG_CENTER_SE4BEG2_15", - "CFG_CENTER_SE4BEG2_16", - "CFG_CENTER_SE4BEG2_17", - "CFG_CENTER_SE4BEG2_18", - "CFG_CENTER_SE4BEG2_19", - "CFG_CENTER_SE4BEG2_2", - "CFG_CENTER_SE4BEG2_3", - "CFG_CENTER_SE4BEG2_4", - "CFG_CENTER_SE4BEG2_5", - "CFG_CENTER_SE4BEG2_6", - "CFG_CENTER_SE4BEG2_7", - "CFG_CENTER_SE4BEG2_8", - "CFG_CENTER_SE4BEG2_9", - "CFG_CENTER_SE4BEG3_0", - "CFG_CENTER_SE4BEG3_1", - "CFG_CENTER_SE4BEG3_10", - "CFG_CENTER_SE4BEG3_11", - "CFG_CENTER_SE4BEG3_12", - "CFG_CENTER_SE4BEG3_13", - "CFG_CENTER_SE4BEG3_14", - "CFG_CENTER_SE4BEG3_15", - "CFG_CENTER_SE4BEG3_16", - "CFG_CENTER_SE4BEG3_17", - "CFG_CENTER_SE4BEG3_18", - "CFG_CENTER_SE4BEG3_19", - "CFG_CENTER_SE4BEG3_2", - "CFG_CENTER_SE4BEG3_3", - "CFG_CENTER_SE4BEG3_4", - "CFG_CENTER_SE4BEG3_5", - "CFG_CENTER_SE4BEG3_6", - "CFG_CENTER_SE4BEG3_7", - "CFG_CENTER_SE4BEG3_8", - "CFG_CENTER_SE4BEG3_9", - "CFG_CENTER_SE4C0_0", - "CFG_CENTER_SE4C0_1", - "CFG_CENTER_SE4C0_10", - "CFG_CENTER_SE4C0_11", - "CFG_CENTER_SE4C0_12", - "CFG_CENTER_SE4C0_13", - "CFG_CENTER_SE4C0_14", - "CFG_CENTER_SE4C0_15", - "CFG_CENTER_SE4C0_16", - "CFG_CENTER_SE4C0_17", - "CFG_CENTER_SE4C0_18", - "CFG_CENTER_SE4C0_19", - "CFG_CENTER_SE4C0_2", - "CFG_CENTER_SE4C0_3", - "CFG_CENTER_SE4C0_4", - "CFG_CENTER_SE4C0_5", - "CFG_CENTER_SE4C0_6", - "CFG_CENTER_SE4C0_7", - "CFG_CENTER_SE4C0_8", - "CFG_CENTER_SE4C0_9", - "CFG_CENTER_SE4C1_0", - "CFG_CENTER_SE4C1_1", - "CFG_CENTER_SE4C1_10", - "CFG_CENTER_SE4C1_11", - "CFG_CENTER_SE4C1_12", - "CFG_CENTER_SE4C1_13", - "CFG_CENTER_SE4C1_14", - "CFG_CENTER_SE4C1_15", - "CFG_CENTER_SE4C1_16", - "CFG_CENTER_SE4C1_17", - "CFG_CENTER_SE4C1_18", - "CFG_CENTER_SE4C1_19", - "CFG_CENTER_SE4C1_2", - "CFG_CENTER_SE4C1_3", - "CFG_CENTER_SE4C1_4", - "CFG_CENTER_SE4C1_5", - "CFG_CENTER_SE4C1_6", - "CFG_CENTER_SE4C1_7", - "CFG_CENTER_SE4C1_8", - "CFG_CENTER_SE4C1_9", - "CFG_CENTER_SE4C2_0", - "CFG_CENTER_SE4C2_1", - "CFG_CENTER_SE4C2_10", - "CFG_CENTER_SE4C2_11", - "CFG_CENTER_SE4C2_12", - "CFG_CENTER_SE4C2_13", - "CFG_CENTER_SE4C2_14", - "CFG_CENTER_SE4C2_15", - "CFG_CENTER_SE4C2_16", - "CFG_CENTER_SE4C2_17", - "CFG_CENTER_SE4C2_18", - "CFG_CENTER_SE4C2_19", - "CFG_CENTER_SE4C2_2", - "CFG_CENTER_SE4C2_3", - "CFG_CENTER_SE4C2_4", - "CFG_CENTER_SE4C2_5", - "CFG_CENTER_SE4C2_6", - "CFG_CENTER_SE4C2_7", - "CFG_CENTER_SE4C2_8", - "CFG_CENTER_SE4C2_9", - "CFG_CENTER_SE4C3_0", - "CFG_CENTER_SE4C3_1", - "CFG_CENTER_SE4C3_10", - "CFG_CENTER_SE4C3_11", - "CFG_CENTER_SE4C3_12", - "CFG_CENTER_SE4C3_13", - "CFG_CENTER_SE4C3_14", - "CFG_CENTER_SE4C3_15", - "CFG_CENTER_SE4C3_16", - "CFG_CENTER_SE4C3_17", - "CFG_CENTER_SE4C3_18", - "CFG_CENTER_SE4C3_19", - "CFG_CENTER_SE4C3_2", - "CFG_CENTER_SE4C3_3", - "CFG_CENTER_SE4C3_4", - "CFG_CENTER_SE4C3_5", - "CFG_CENTER_SE4C3_6", - "CFG_CENTER_SE4C3_7", - "CFG_CENTER_SE4C3_8", - "CFG_CENTER_SE4C3_9", - "CFG_CENTER_SW2A0_0", - "CFG_CENTER_SW2A0_1", - "CFG_CENTER_SW2A0_10", - "CFG_CENTER_SW2A0_11", - "CFG_CENTER_SW2A0_12", - "CFG_CENTER_SW2A0_13", - "CFG_CENTER_SW2A0_14", - "CFG_CENTER_SW2A0_15", - "CFG_CENTER_SW2A0_16", - "CFG_CENTER_SW2A0_17", - "CFG_CENTER_SW2A0_18", - "CFG_CENTER_SW2A0_19", - "CFG_CENTER_SW2A0_2", - "CFG_CENTER_SW2A0_3", - "CFG_CENTER_SW2A0_4", - "CFG_CENTER_SW2A0_5", - "CFG_CENTER_SW2A0_6", - "CFG_CENTER_SW2A0_7", - "CFG_CENTER_SW2A0_8", - "CFG_CENTER_SW2A0_9", - "CFG_CENTER_SW2A1_0", - "CFG_CENTER_SW2A1_1", - "CFG_CENTER_SW2A1_10", - "CFG_CENTER_SW2A1_11", - "CFG_CENTER_SW2A1_12", - "CFG_CENTER_SW2A1_13", - "CFG_CENTER_SW2A1_14", - "CFG_CENTER_SW2A1_15", - "CFG_CENTER_SW2A1_16", - "CFG_CENTER_SW2A1_17", - "CFG_CENTER_SW2A1_18", - "CFG_CENTER_SW2A1_19", - "CFG_CENTER_SW2A1_2", - "CFG_CENTER_SW2A1_3", - "CFG_CENTER_SW2A1_4", - "CFG_CENTER_SW2A1_5", - "CFG_CENTER_SW2A1_6", - "CFG_CENTER_SW2A1_7", - "CFG_CENTER_SW2A1_8", - "CFG_CENTER_SW2A1_9", - "CFG_CENTER_SW2A2_0", - "CFG_CENTER_SW2A2_1", - "CFG_CENTER_SW2A2_10", - "CFG_CENTER_SW2A2_11", - "CFG_CENTER_SW2A2_12", - "CFG_CENTER_SW2A2_13", - "CFG_CENTER_SW2A2_14", - "CFG_CENTER_SW2A2_15", - "CFG_CENTER_SW2A2_16", - "CFG_CENTER_SW2A2_17", - "CFG_CENTER_SW2A2_18", - "CFG_CENTER_SW2A2_19", - "CFG_CENTER_SW2A2_2", - "CFG_CENTER_SW2A2_3", - "CFG_CENTER_SW2A2_4", - "CFG_CENTER_SW2A2_5", - "CFG_CENTER_SW2A2_6", - "CFG_CENTER_SW2A2_7", - "CFG_CENTER_SW2A2_8", - "CFG_CENTER_SW2A2_9", - "CFG_CENTER_SW2A3_0", - "CFG_CENTER_SW2A3_1", - "CFG_CENTER_SW2A3_10", - "CFG_CENTER_SW2A3_11", - "CFG_CENTER_SW2A3_12", - "CFG_CENTER_SW2A3_13", - "CFG_CENTER_SW2A3_14", - "CFG_CENTER_SW2A3_15", - "CFG_CENTER_SW2A3_16", - "CFG_CENTER_SW2A3_17", - "CFG_CENTER_SW2A3_18", - "CFG_CENTER_SW2A3_19", - "CFG_CENTER_SW2A3_2", - "CFG_CENTER_SW2A3_3", - "CFG_CENTER_SW2A3_4", - "CFG_CENTER_SW2A3_5", - "CFG_CENTER_SW2A3_6", - "CFG_CENTER_SW2A3_7", - "CFG_CENTER_SW2A3_8", - "CFG_CENTER_SW2A3_9", - "CFG_CENTER_SW4A0_0", - "CFG_CENTER_SW4A0_1", - "CFG_CENTER_SW4A0_10", - "CFG_CENTER_SW4A0_11", - "CFG_CENTER_SW4A0_12", - "CFG_CENTER_SW4A0_13", - "CFG_CENTER_SW4A0_14", - "CFG_CENTER_SW4A0_15", - "CFG_CENTER_SW4A0_16", - "CFG_CENTER_SW4A0_17", - "CFG_CENTER_SW4A0_18", - "CFG_CENTER_SW4A0_19", - "CFG_CENTER_SW4A0_2", - "CFG_CENTER_SW4A0_3", - "CFG_CENTER_SW4A0_4", - "CFG_CENTER_SW4A0_5", - "CFG_CENTER_SW4A0_6", - "CFG_CENTER_SW4A0_7", - "CFG_CENTER_SW4A0_8", - "CFG_CENTER_SW4A0_9", - "CFG_CENTER_SW4A1_0", - "CFG_CENTER_SW4A1_1", - "CFG_CENTER_SW4A1_10", - "CFG_CENTER_SW4A1_11", - "CFG_CENTER_SW4A1_12", - "CFG_CENTER_SW4A1_13", - "CFG_CENTER_SW4A1_14", - "CFG_CENTER_SW4A1_15", - "CFG_CENTER_SW4A1_16", - "CFG_CENTER_SW4A1_17", - "CFG_CENTER_SW4A1_18", - "CFG_CENTER_SW4A1_19", - "CFG_CENTER_SW4A1_2", - "CFG_CENTER_SW4A1_3", - "CFG_CENTER_SW4A1_4", - "CFG_CENTER_SW4A1_5", - "CFG_CENTER_SW4A1_6", - "CFG_CENTER_SW4A1_7", - "CFG_CENTER_SW4A1_8", - "CFG_CENTER_SW4A1_9", - "CFG_CENTER_SW4A2_0", - "CFG_CENTER_SW4A2_1", - "CFG_CENTER_SW4A2_10", - "CFG_CENTER_SW4A2_11", - "CFG_CENTER_SW4A2_12", - "CFG_CENTER_SW4A2_13", - "CFG_CENTER_SW4A2_14", - "CFG_CENTER_SW4A2_15", - "CFG_CENTER_SW4A2_16", - "CFG_CENTER_SW4A2_17", - "CFG_CENTER_SW4A2_18", - "CFG_CENTER_SW4A2_19", - "CFG_CENTER_SW4A2_2", - "CFG_CENTER_SW4A2_3", - "CFG_CENTER_SW4A2_4", - "CFG_CENTER_SW4A2_5", - "CFG_CENTER_SW4A2_6", - "CFG_CENTER_SW4A2_7", - "CFG_CENTER_SW4A2_8", - "CFG_CENTER_SW4A2_9", - "CFG_CENTER_SW4A3_0", - "CFG_CENTER_SW4A3_1", - "CFG_CENTER_SW4A3_10", - "CFG_CENTER_SW4A3_11", - "CFG_CENTER_SW4A3_12", - "CFG_CENTER_SW4A3_13", - "CFG_CENTER_SW4A3_14", - "CFG_CENTER_SW4A3_15", - "CFG_CENTER_SW4A3_16", - "CFG_CENTER_SW4A3_17", - "CFG_CENTER_SW4A3_18", - "CFG_CENTER_SW4A3_19", - "CFG_CENTER_SW4A3_2", - "CFG_CENTER_SW4A3_3", - "CFG_CENTER_SW4A3_4", - "CFG_CENTER_SW4A3_5", - "CFG_CENTER_SW4A3_6", - "CFG_CENTER_SW4A3_7", - "CFG_CENTER_SW4A3_8", - "CFG_CENTER_SW4A3_9", - "CFG_CENTER_SW4END0_0", - "CFG_CENTER_SW4END0_1", - "CFG_CENTER_SW4END0_10", - "CFG_CENTER_SW4END0_11", - "CFG_CENTER_SW4END0_12", - "CFG_CENTER_SW4END0_13", - "CFG_CENTER_SW4END0_14", - "CFG_CENTER_SW4END0_15", - "CFG_CENTER_SW4END0_16", - "CFG_CENTER_SW4END0_17", - "CFG_CENTER_SW4END0_18", - "CFG_CENTER_SW4END0_19", - "CFG_CENTER_SW4END0_2", - "CFG_CENTER_SW4END0_3", - "CFG_CENTER_SW4END0_4", - "CFG_CENTER_SW4END0_5", - "CFG_CENTER_SW4END0_6", - "CFG_CENTER_SW4END0_7", - "CFG_CENTER_SW4END0_8", - "CFG_CENTER_SW4END0_9", - "CFG_CENTER_SW4END1_0", - "CFG_CENTER_SW4END1_1", - "CFG_CENTER_SW4END1_10", - "CFG_CENTER_SW4END1_11", - "CFG_CENTER_SW4END1_12", - "CFG_CENTER_SW4END1_13", - "CFG_CENTER_SW4END1_14", - "CFG_CENTER_SW4END1_15", - "CFG_CENTER_SW4END1_16", - "CFG_CENTER_SW4END1_17", - "CFG_CENTER_SW4END1_18", - "CFG_CENTER_SW4END1_19", - "CFG_CENTER_SW4END1_2", - "CFG_CENTER_SW4END1_3", - "CFG_CENTER_SW4END1_4", - "CFG_CENTER_SW4END1_5", - "CFG_CENTER_SW4END1_6", - "CFG_CENTER_SW4END1_7", - "CFG_CENTER_SW4END1_8", - "CFG_CENTER_SW4END1_9", - "CFG_CENTER_SW4END2_0", - "CFG_CENTER_SW4END2_1", - "CFG_CENTER_SW4END2_10", - "CFG_CENTER_SW4END2_11", - "CFG_CENTER_SW4END2_12", - "CFG_CENTER_SW4END2_13", - "CFG_CENTER_SW4END2_14", - "CFG_CENTER_SW4END2_15", - "CFG_CENTER_SW4END2_16", - "CFG_CENTER_SW4END2_17", - "CFG_CENTER_SW4END2_18", - "CFG_CENTER_SW4END2_19", - "CFG_CENTER_SW4END2_2", - "CFG_CENTER_SW4END2_3", - "CFG_CENTER_SW4END2_4", - "CFG_CENTER_SW4END2_5", - "CFG_CENTER_SW4END2_6", - "CFG_CENTER_SW4END2_7", - "CFG_CENTER_SW4END2_8", - "CFG_CENTER_SW4END2_9", - "CFG_CENTER_SW4END3_0", - "CFG_CENTER_SW4END3_1", - "CFG_CENTER_SW4END3_10", - "CFG_CENTER_SW4END3_11", - "CFG_CENTER_SW4END3_12", - "CFG_CENTER_SW4END3_13", - "CFG_CENTER_SW4END3_14", - "CFG_CENTER_SW4END3_15", - "CFG_CENTER_SW4END3_16", - "CFG_CENTER_SW4END3_17", - "CFG_CENTER_SW4END3_18", - "CFG_CENTER_SW4END3_19", - "CFG_CENTER_SW4END3_2", - "CFG_CENTER_SW4END3_3", - "CFG_CENTER_SW4END3_4", - "CFG_CENTER_SW4END3_5", - "CFG_CENTER_SW4END3_6", - "CFG_CENTER_SW4END3_7", - "CFG_CENTER_SW4END3_8", - "CFG_CENTER_SW4END3_9", - "CFG_CENTER_WL1END0_0", - "CFG_CENTER_WL1END0_1", - "CFG_CENTER_WL1END0_10", - "CFG_CENTER_WL1END0_11", - "CFG_CENTER_WL1END0_12", - "CFG_CENTER_WL1END0_13", - "CFG_CENTER_WL1END0_14", - "CFG_CENTER_WL1END0_15", - "CFG_CENTER_WL1END0_16", - "CFG_CENTER_WL1END0_17", - "CFG_CENTER_WL1END0_18", - "CFG_CENTER_WL1END0_19", - "CFG_CENTER_WL1END0_2", - "CFG_CENTER_WL1END0_3", - "CFG_CENTER_WL1END0_4", - "CFG_CENTER_WL1END0_5", - "CFG_CENTER_WL1END0_6", - "CFG_CENTER_WL1END0_7", - "CFG_CENTER_WL1END0_8", - "CFG_CENTER_WL1END0_9", - "CFG_CENTER_WL1END1_0", - "CFG_CENTER_WL1END1_1", - "CFG_CENTER_WL1END1_10", - "CFG_CENTER_WL1END1_11", - "CFG_CENTER_WL1END1_12", - "CFG_CENTER_WL1END1_13", - "CFG_CENTER_WL1END1_14", - "CFG_CENTER_WL1END1_15", - "CFG_CENTER_WL1END1_16", - "CFG_CENTER_WL1END1_17", - "CFG_CENTER_WL1END1_18", - "CFG_CENTER_WL1END1_19", - "CFG_CENTER_WL1END1_2", - "CFG_CENTER_WL1END1_3", - "CFG_CENTER_WL1END1_4", - "CFG_CENTER_WL1END1_5", - "CFG_CENTER_WL1END1_6", - "CFG_CENTER_WL1END1_7", - "CFG_CENTER_WL1END1_8", - "CFG_CENTER_WL1END1_9", - "CFG_CENTER_WL1END2_0", - "CFG_CENTER_WL1END2_1", - "CFG_CENTER_WL1END2_10", - "CFG_CENTER_WL1END2_11", - "CFG_CENTER_WL1END2_12", - "CFG_CENTER_WL1END2_13", - "CFG_CENTER_WL1END2_14", - "CFG_CENTER_WL1END2_15", - "CFG_CENTER_WL1END2_16", - "CFG_CENTER_WL1END2_17", - "CFG_CENTER_WL1END2_18", - "CFG_CENTER_WL1END2_19", - "CFG_CENTER_WL1END2_2", - "CFG_CENTER_WL1END2_3", - "CFG_CENTER_WL1END2_4", - "CFG_CENTER_WL1END2_5", - "CFG_CENTER_WL1END2_6", - "CFG_CENTER_WL1END2_7", - "CFG_CENTER_WL1END2_8", - "CFG_CENTER_WL1END2_9", - "CFG_CENTER_WL1END3_0", - "CFG_CENTER_WL1END3_1", - "CFG_CENTER_WL1END3_10", - "CFG_CENTER_WL1END3_11", - "CFG_CENTER_WL1END3_12", - "CFG_CENTER_WL1END3_13", - "CFG_CENTER_WL1END3_14", - "CFG_CENTER_WL1END3_15", - "CFG_CENTER_WL1END3_16", - "CFG_CENTER_WL1END3_17", - "CFG_CENTER_WL1END3_18", - "CFG_CENTER_WL1END3_19", - "CFG_CENTER_WL1END3_2", - "CFG_CENTER_WL1END3_3", - "CFG_CENTER_WL1END3_4", - "CFG_CENTER_WL1END3_5", - "CFG_CENTER_WL1END3_6", - "CFG_CENTER_WL1END3_7", - "CFG_CENTER_WL1END3_8", - "CFG_CENTER_WL1END3_9", - "CFG_CENTER_WR1END0_0", - "CFG_CENTER_WR1END0_1", - "CFG_CENTER_WR1END0_10", - "CFG_CENTER_WR1END0_11", - "CFG_CENTER_WR1END0_12", - "CFG_CENTER_WR1END0_13", - "CFG_CENTER_WR1END0_14", - "CFG_CENTER_WR1END0_15", - "CFG_CENTER_WR1END0_16", - "CFG_CENTER_WR1END0_17", - "CFG_CENTER_WR1END0_18", - "CFG_CENTER_WR1END0_19", - "CFG_CENTER_WR1END0_2", - "CFG_CENTER_WR1END0_3", - "CFG_CENTER_WR1END0_4", - "CFG_CENTER_WR1END0_5", - "CFG_CENTER_WR1END0_6", - "CFG_CENTER_WR1END0_7", - "CFG_CENTER_WR1END0_8", - "CFG_CENTER_WR1END0_9", - "CFG_CENTER_WR1END1_0", - "CFG_CENTER_WR1END1_1", - "CFG_CENTER_WR1END1_10", - "CFG_CENTER_WR1END1_11", - "CFG_CENTER_WR1END1_12", - "CFG_CENTER_WR1END1_13", - "CFG_CENTER_WR1END1_14", - "CFG_CENTER_WR1END1_15", - "CFG_CENTER_WR1END1_16", - "CFG_CENTER_WR1END1_17", - "CFG_CENTER_WR1END1_18", - "CFG_CENTER_WR1END1_19", - "CFG_CENTER_WR1END1_2", - "CFG_CENTER_WR1END1_3", - "CFG_CENTER_WR1END1_4", - "CFG_CENTER_WR1END1_5", - "CFG_CENTER_WR1END1_6", - "CFG_CENTER_WR1END1_7", - "CFG_CENTER_WR1END1_8", - "CFG_CENTER_WR1END1_9", - "CFG_CENTER_WR1END2_0", - "CFG_CENTER_WR1END2_1", - "CFG_CENTER_WR1END2_10", - "CFG_CENTER_WR1END2_11", - "CFG_CENTER_WR1END2_12", - "CFG_CENTER_WR1END2_13", - "CFG_CENTER_WR1END2_14", - "CFG_CENTER_WR1END2_15", - "CFG_CENTER_WR1END2_16", - "CFG_CENTER_WR1END2_17", - "CFG_CENTER_WR1END2_18", - "CFG_CENTER_WR1END2_19", - "CFG_CENTER_WR1END2_2", - "CFG_CENTER_WR1END2_3", - "CFG_CENTER_WR1END2_4", - "CFG_CENTER_WR1END2_5", - "CFG_CENTER_WR1END2_6", - "CFG_CENTER_WR1END2_7", - "CFG_CENTER_WR1END2_8", - "CFG_CENTER_WR1END2_9", - "CFG_CENTER_WR1END3_0", - "CFG_CENTER_WR1END3_1", - "CFG_CENTER_WR1END3_10", - "CFG_CENTER_WR1END3_11", - "CFG_CENTER_WR1END3_12", - "CFG_CENTER_WR1END3_13", - "CFG_CENTER_WR1END3_14", - "CFG_CENTER_WR1END3_15", - "CFG_CENTER_WR1END3_16", - "CFG_CENTER_WR1END3_17", - "CFG_CENTER_WR1END3_18", - "CFG_CENTER_WR1END3_19", - "CFG_CENTER_WR1END3_2", - "CFG_CENTER_WR1END3_3", - "CFG_CENTER_WR1END3_4", - "CFG_CENTER_WR1END3_5", - "CFG_CENTER_WR1END3_6", - "CFG_CENTER_WR1END3_7", - "CFG_CENTER_WR1END3_8", - "CFG_CENTER_WR1END3_9", - "CFG_CENTER_WW2A0_0", - "CFG_CENTER_WW2A0_1", - "CFG_CENTER_WW2A0_10", - "CFG_CENTER_WW2A0_11", - "CFG_CENTER_WW2A0_12", - "CFG_CENTER_WW2A0_13", - "CFG_CENTER_WW2A0_14", - "CFG_CENTER_WW2A0_15", - "CFG_CENTER_WW2A0_16", - "CFG_CENTER_WW2A0_17", - "CFG_CENTER_WW2A0_18", - "CFG_CENTER_WW2A0_19", - "CFG_CENTER_WW2A0_2", - "CFG_CENTER_WW2A0_3", - "CFG_CENTER_WW2A0_4", - "CFG_CENTER_WW2A0_5", - "CFG_CENTER_WW2A0_6", - "CFG_CENTER_WW2A0_7", - "CFG_CENTER_WW2A0_8", - "CFG_CENTER_WW2A0_9", - "CFG_CENTER_WW2A1_0", - "CFG_CENTER_WW2A1_1", - "CFG_CENTER_WW2A1_10", - "CFG_CENTER_WW2A1_11", - "CFG_CENTER_WW2A1_12", - "CFG_CENTER_WW2A1_13", - "CFG_CENTER_WW2A1_14", - "CFG_CENTER_WW2A1_15", - "CFG_CENTER_WW2A1_16", - "CFG_CENTER_WW2A1_17", - "CFG_CENTER_WW2A1_18", - "CFG_CENTER_WW2A1_19", - "CFG_CENTER_WW2A1_2", - "CFG_CENTER_WW2A1_3", - "CFG_CENTER_WW2A1_4", - "CFG_CENTER_WW2A1_5", - "CFG_CENTER_WW2A1_6", - "CFG_CENTER_WW2A1_7", - "CFG_CENTER_WW2A1_8", - "CFG_CENTER_WW2A1_9", - "CFG_CENTER_WW2A2_0", - "CFG_CENTER_WW2A2_1", - "CFG_CENTER_WW2A2_10", - "CFG_CENTER_WW2A2_11", - "CFG_CENTER_WW2A2_12", - "CFG_CENTER_WW2A2_13", - "CFG_CENTER_WW2A2_14", - "CFG_CENTER_WW2A2_15", - "CFG_CENTER_WW2A2_16", - "CFG_CENTER_WW2A2_17", - "CFG_CENTER_WW2A2_18", - "CFG_CENTER_WW2A2_19", - "CFG_CENTER_WW2A2_2", - "CFG_CENTER_WW2A2_3", - "CFG_CENTER_WW2A2_4", - "CFG_CENTER_WW2A2_5", - "CFG_CENTER_WW2A2_6", - "CFG_CENTER_WW2A2_7", - "CFG_CENTER_WW2A2_8", - "CFG_CENTER_WW2A2_9", - "CFG_CENTER_WW2A3_0", - "CFG_CENTER_WW2A3_1", - "CFG_CENTER_WW2A3_10", - "CFG_CENTER_WW2A3_11", - "CFG_CENTER_WW2A3_12", - "CFG_CENTER_WW2A3_13", - "CFG_CENTER_WW2A3_14", - "CFG_CENTER_WW2A3_15", - "CFG_CENTER_WW2A3_16", - "CFG_CENTER_WW2A3_17", - "CFG_CENTER_WW2A3_18", - "CFG_CENTER_WW2A3_19", - "CFG_CENTER_WW2A3_2", - "CFG_CENTER_WW2A3_3", - "CFG_CENTER_WW2A3_4", - "CFG_CENTER_WW2A3_5", - "CFG_CENTER_WW2A3_6", - "CFG_CENTER_WW2A3_7", - "CFG_CENTER_WW2A3_8", - "CFG_CENTER_WW2A3_9", - "CFG_CENTER_WW2END0_0", - "CFG_CENTER_WW2END0_1", - "CFG_CENTER_WW2END0_10", - "CFG_CENTER_WW2END0_11", - "CFG_CENTER_WW2END0_12", - "CFG_CENTER_WW2END0_13", - "CFG_CENTER_WW2END0_14", - "CFG_CENTER_WW2END0_15", - "CFG_CENTER_WW2END0_16", - "CFG_CENTER_WW2END0_17", - "CFG_CENTER_WW2END0_18", - "CFG_CENTER_WW2END0_19", - "CFG_CENTER_WW2END0_2", - "CFG_CENTER_WW2END0_3", - "CFG_CENTER_WW2END0_4", - "CFG_CENTER_WW2END0_5", - "CFG_CENTER_WW2END0_6", - "CFG_CENTER_WW2END0_7", - "CFG_CENTER_WW2END0_8", - "CFG_CENTER_WW2END0_9", - "CFG_CENTER_WW2END1_0", - "CFG_CENTER_WW2END1_1", - "CFG_CENTER_WW2END1_10", - "CFG_CENTER_WW2END1_11", - "CFG_CENTER_WW2END1_12", - "CFG_CENTER_WW2END1_13", - "CFG_CENTER_WW2END1_14", - "CFG_CENTER_WW2END1_15", - "CFG_CENTER_WW2END1_16", - "CFG_CENTER_WW2END1_17", - "CFG_CENTER_WW2END1_18", - "CFG_CENTER_WW2END1_19", - "CFG_CENTER_WW2END1_2", - "CFG_CENTER_WW2END1_3", - "CFG_CENTER_WW2END1_4", - "CFG_CENTER_WW2END1_5", - "CFG_CENTER_WW2END1_6", - "CFG_CENTER_WW2END1_7", - "CFG_CENTER_WW2END1_8", - "CFG_CENTER_WW2END1_9", - "CFG_CENTER_WW2END2_0", - "CFG_CENTER_WW2END2_1", - "CFG_CENTER_WW2END2_10", - "CFG_CENTER_WW2END2_11", - "CFG_CENTER_WW2END2_12", - "CFG_CENTER_WW2END2_13", - "CFG_CENTER_WW2END2_14", - "CFG_CENTER_WW2END2_15", - "CFG_CENTER_WW2END2_16", - "CFG_CENTER_WW2END2_17", - "CFG_CENTER_WW2END2_18", - "CFG_CENTER_WW2END2_19", - "CFG_CENTER_WW2END2_2", - "CFG_CENTER_WW2END2_3", - "CFG_CENTER_WW2END2_4", - "CFG_CENTER_WW2END2_5", - "CFG_CENTER_WW2END2_6", - "CFG_CENTER_WW2END2_7", - "CFG_CENTER_WW2END2_8", - "CFG_CENTER_WW2END2_9", - "CFG_CENTER_WW2END3_0", - "CFG_CENTER_WW2END3_1", - "CFG_CENTER_WW2END3_10", - "CFG_CENTER_WW2END3_11", - "CFG_CENTER_WW2END3_12", - "CFG_CENTER_WW2END3_13", - "CFG_CENTER_WW2END3_14", - "CFG_CENTER_WW2END3_15", - "CFG_CENTER_WW2END3_16", - "CFG_CENTER_WW2END3_17", - "CFG_CENTER_WW2END3_18", - "CFG_CENTER_WW2END3_19", - "CFG_CENTER_WW2END3_2", - "CFG_CENTER_WW2END3_3", - "CFG_CENTER_WW2END3_4", - "CFG_CENTER_WW2END3_5", - "CFG_CENTER_WW2END3_6", - "CFG_CENTER_WW2END3_7", - "CFG_CENTER_WW2END3_8", - "CFG_CENTER_WW2END3_9", - "CFG_CENTER_WW4A0_0", - "CFG_CENTER_WW4A0_1", - "CFG_CENTER_WW4A0_10", - "CFG_CENTER_WW4A0_11", - "CFG_CENTER_WW4A0_12", - "CFG_CENTER_WW4A0_13", - "CFG_CENTER_WW4A0_14", - "CFG_CENTER_WW4A0_15", - "CFG_CENTER_WW4A0_16", - "CFG_CENTER_WW4A0_17", - "CFG_CENTER_WW4A0_18", - "CFG_CENTER_WW4A0_19", - "CFG_CENTER_WW4A0_2", - "CFG_CENTER_WW4A0_3", - "CFG_CENTER_WW4A0_4", - "CFG_CENTER_WW4A0_5", - "CFG_CENTER_WW4A0_6", - "CFG_CENTER_WW4A0_7", - "CFG_CENTER_WW4A0_8", - "CFG_CENTER_WW4A0_9", - "CFG_CENTER_WW4A1_0", - "CFG_CENTER_WW4A1_1", - "CFG_CENTER_WW4A1_10", - "CFG_CENTER_WW4A1_11", - "CFG_CENTER_WW4A1_12", - "CFG_CENTER_WW4A1_13", - "CFG_CENTER_WW4A1_14", - "CFG_CENTER_WW4A1_15", - "CFG_CENTER_WW4A1_16", - "CFG_CENTER_WW4A1_17", - "CFG_CENTER_WW4A1_18", - "CFG_CENTER_WW4A1_19", - "CFG_CENTER_WW4A1_2", - "CFG_CENTER_WW4A1_3", - "CFG_CENTER_WW4A1_4", - "CFG_CENTER_WW4A1_5", - "CFG_CENTER_WW4A1_6", - "CFG_CENTER_WW4A1_7", - "CFG_CENTER_WW4A1_8", - "CFG_CENTER_WW4A1_9", - "CFG_CENTER_WW4A2_0", - "CFG_CENTER_WW4A2_1", - "CFG_CENTER_WW4A2_10", - "CFG_CENTER_WW4A2_11", - "CFG_CENTER_WW4A2_12", - "CFG_CENTER_WW4A2_13", - "CFG_CENTER_WW4A2_14", - "CFG_CENTER_WW4A2_15", - "CFG_CENTER_WW4A2_16", - "CFG_CENTER_WW4A2_17", - "CFG_CENTER_WW4A2_18", - "CFG_CENTER_WW4A2_19", - "CFG_CENTER_WW4A2_2", - "CFG_CENTER_WW4A2_3", - "CFG_CENTER_WW4A2_4", - "CFG_CENTER_WW4A2_5", - "CFG_CENTER_WW4A2_6", - "CFG_CENTER_WW4A2_7", - "CFG_CENTER_WW4A2_8", - "CFG_CENTER_WW4A2_9", - "CFG_CENTER_WW4A3_0", - "CFG_CENTER_WW4A3_1", - "CFG_CENTER_WW4A3_10", - "CFG_CENTER_WW4A3_11", - "CFG_CENTER_WW4A3_12", - "CFG_CENTER_WW4A3_13", - "CFG_CENTER_WW4A3_14", - "CFG_CENTER_WW4A3_15", - "CFG_CENTER_WW4A3_16", - "CFG_CENTER_WW4A3_17", - "CFG_CENTER_WW4A3_18", - "CFG_CENTER_WW4A3_19", - "CFG_CENTER_WW4A3_2", - "CFG_CENTER_WW4A3_3", - "CFG_CENTER_WW4A3_4", - "CFG_CENTER_WW4A3_5", - "CFG_CENTER_WW4A3_6", - "CFG_CENTER_WW4A3_7", - "CFG_CENTER_WW4A3_8", - "CFG_CENTER_WW4A3_9", - "CFG_CENTER_WW4B0_0", - "CFG_CENTER_WW4B0_1", - "CFG_CENTER_WW4B0_10", - "CFG_CENTER_WW4B0_11", - "CFG_CENTER_WW4B0_12", - "CFG_CENTER_WW4B0_13", - "CFG_CENTER_WW4B0_14", - "CFG_CENTER_WW4B0_15", - "CFG_CENTER_WW4B0_16", - "CFG_CENTER_WW4B0_17", - "CFG_CENTER_WW4B0_18", - "CFG_CENTER_WW4B0_19", - "CFG_CENTER_WW4B0_2", - "CFG_CENTER_WW4B0_3", - "CFG_CENTER_WW4B0_4", - "CFG_CENTER_WW4B0_5", - "CFG_CENTER_WW4B0_6", - "CFG_CENTER_WW4B0_7", - "CFG_CENTER_WW4B0_8", - "CFG_CENTER_WW4B0_9", - "CFG_CENTER_WW4B1_0", - "CFG_CENTER_WW4B1_1", - "CFG_CENTER_WW4B1_10", - "CFG_CENTER_WW4B1_11", - "CFG_CENTER_WW4B1_12", - "CFG_CENTER_WW4B1_13", - "CFG_CENTER_WW4B1_14", - "CFG_CENTER_WW4B1_15", - "CFG_CENTER_WW4B1_16", - "CFG_CENTER_WW4B1_17", - "CFG_CENTER_WW4B1_18", - "CFG_CENTER_WW4B1_19", - "CFG_CENTER_WW4B1_2", - "CFG_CENTER_WW4B1_3", - "CFG_CENTER_WW4B1_4", - "CFG_CENTER_WW4B1_5", - "CFG_CENTER_WW4B1_6", - "CFG_CENTER_WW4B1_7", - "CFG_CENTER_WW4B1_8", - "CFG_CENTER_WW4B1_9", - "CFG_CENTER_WW4B2_0", - "CFG_CENTER_WW4B2_1", - "CFG_CENTER_WW4B2_10", - "CFG_CENTER_WW4B2_11", - "CFG_CENTER_WW4B2_12", - "CFG_CENTER_WW4B2_13", - "CFG_CENTER_WW4B2_14", - "CFG_CENTER_WW4B2_15", - "CFG_CENTER_WW4B2_16", - "CFG_CENTER_WW4B2_17", - "CFG_CENTER_WW4B2_18", - "CFG_CENTER_WW4B2_19", - "CFG_CENTER_WW4B2_2", - "CFG_CENTER_WW4B2_3", - "CFG_CENTER_WW4B2_4", - "CFG_CENTER_WW4B2_5", - "CFG_CENTER_WW4B2_6", - "CFG_CENTER_WW4B2_7", - "CFG_CENTER_WW4B2_8", - "CFG_CENTER_WW4B2_9", - "CFG_CENTER_WW4B3_0", - "CFG_CENTER_WW4B3_1", - "CFG_CENTER_WW4B3_10", - "CFG_CENTER_WW4B3_11", - "CFG_CENTER_WW4B3_12", - "CFG_CENTER_WW4B3_13", - "CFG_CENTER_WW4B3_14", - "CFG_CENTER_WW4B3_15", - "CFG_CENTER_WW4B3_16", - "CFG_CENTER_WW4B3_17", - "CFG_CENTER_WW4B3_18", - "CFG_CENTER_WW4B3_19", - "CFG_CENTER_WW4B3_2", - "CFG_CENTER_WW4B3_3", - "CFG_CENTER_WW4B3_4", - "CFG_CENTER_WW4B3_5", - "CFG_CENTER_WW4B3_6", - "CFG_CENTER_WW4B3_7", - "CFG_CENTER_WW4B3_8", - "CFG_CENTER_WW4B3_9", - "CFG_CENTER_WW4C0_0", - "CFG_CENTER_WW4C0_1", - "CFG_CENTER_WW4C0_10", - "CFG_CENTER_WW4C0_11", - "CFG_CENTER_WW4C0_12", - "CFG_CENTER_WW4C0_13", - "CFG_CENTER_WW4C0_14", - "CFG_CENTER_WW4C0_15", - "CFG_CENTER_WW4C0_16", - "CFG_CENTER_WW4C0_17", - "CFG_CENTER_WW4C0_18", - "CFG_CENTER_WW4C0_19", - "CFG_CENTER_WW4C0_2", - "CFG_CENTER_WW4C0_3", - "CFG_CENTER_WW4C0_4", - "CFG_CENTER_WW4C0_5", - "CFG_CENTER_WW4C0_6", - "CFG_CENTER_WW4C0_7", - "CFG_CENTER_WW4C0_8", - "CFG_CENTER_WW4C0_9", - "CFG_CENTER_WW4C1_0", - "CFG_CENTER_WW4C1_1", - "CFG_CENTER_WW4C1_10", - "CFG_CENTER_WW4C1_11", - "CFG_CENTER_WW4C1_12", - "CFG_CENTER_WW4C1_13", - "CFG_CENTER_WW4C1_14", - "CFG_CENTER_WW4C1_15", - "CFG_CENTER_WW4C1_16", - "CFG_CENTER_WW4C1_17", - "CFG_CENTER_WW4C1_18", - "CFG_CENTER_WW4C1_19", - "CFG_CENTER_WW4C1_2", - "CFG_CENTER_WW4C1_3", - "CFG_CENTER_WW4C1_4", - "CFG_CENTER_WW4C1_5", - "CFG_CENTER_WW4C1_6", - "CFG_CENTER_WW4C1_7", - "CFG_CENTER_WW4C1_8", - "CFG_CENTER_WW4C1_9", - "CFG_CENTER_WW4C2_0", - "CFG_CENTER_WW4C2_1", - "CFG_CENTER_WW4C2_10", - "CFG_CENTER_WW4C2_11", - "CFG_CENTER_WW4C2_12", - "CFG_CENTER_WW4C2_13", - "CFG_CENTER_WW4C2_14", - "CFG_CENTER_WW4C2_15", - "CFG_CENTER_WW4C2_16", - "CFG_CENTER_WW4C2_17", - "CFG_CENTER_WW4C2_18", - "CFG_CENTER_WW4C2_19", - "CFG_CENTER_WW4C2_2", - "CFG_CENTER_WW4C2_3", - "CFG_CENTER_WW4C2_4", - "CFG_CENTER_WW4C2_5", - "CFG_CENTER_WW4C2_6", - "CFG_CENTER_WW4C2_7", - "CFG_CENTER_WW4C2_8", - "CFG_CENTER_WW4C2_9", - "CFG_CENTER_WW4C3_0", - "CFG_CENTER_WW4C3_1", - "CFG_CENTER_WW4C3_10", - "CFG_CENTER_WW4C3_11", - "CFG_CENTER_WW4C3_12", - "CFG_CENTER_WW4C3_13", - "CFG_CENTER_WW4C3_14", - "CFG_CENTER_WW4C3_15", - "CFG_CENTER_WW4C3_16", - "CFG_CENTER_WW4C3_17", - "CFG_CENTER_WW4C3_18", - "CFG_CENTER_WW4C3_19", - "CFG_CENTER_WW4C3_2", - "CFG_CENTER_WW4C3_3", - "CFG_CENTER_WW4C3_4", - "CFG_CENTER_WW4C3_5", - "CFG_CENTER_WW4C3_6", - "CFG_CENTER_WW4C3_7", - "CFG_CENTER_WW4C3_8", - "CFG_CENTER_WW4C3_9", - "CFG_CENTER_WW4END0_0", - "CFG_CENTER_WW4END0_1", - "CFG_CENTER_WW4END0_10", - "CFG_CENTER_WW4END0_11", - "CFG_CENTER_WW4END0_12", - "CFG_CENTER_WW4END0_13", - "CFG_CENTER_WW4END0_14", - "CFG_CENTER_WW4END0_15", - "CFG_CENTER_WW4END0_16", - "CFG_CENTER_WW4END0_17", - "CFG_CENTER_WW4END0_18", - "CFG_CENTER_WW4END0_19", - "CFG_CENTER_WW4END0_2", - "CFG_CENTER_WW4END0_3", - "CFG_CENTER_WW4END0_4", - "CFG_CENTER_WW4END0_5", - "CFG_CENTER_WW4END0_6", - "CFG_CENTER_WW4END0_7", - "CFG_CENTER_WW4END0_8", - "CFG_CENTER_WW4END0_9", - "CFG_CENTER_WW4END1_0", - "CFG_CENTER_WW4END1_1", - "CFG_CENTER_WW4END1_10", - "CFG_CENTER_WW4END1_11", - "CFG_CENTER_WW4END1_12", - "CFG_CENTER_WW4END1_13", - "CFG_CENTER_WW4END1_14", - "CFG_CENTER_WW4END1_15", - "CFG_CENTER_WW4END1_16", - "CFG_CENTER_WW4END1_17", - "CFG_CENTER_WW4END1_18", - "CFG_CENTER_WW4END1_19", - "CFG_CENTER_WW4END1_2", - "CFG_CENTER_WW4END1_3", - "CFG_CENTER_WW4END1_4", - "CFG_CENTER_WW4END1_5", - "CFG_CENTER_WW4END1_6", - "CFG_CENTER_WW4END1_7", - "CFG_CENTER_WW4END1_8", - "CFG_CENTER_WW4END1_9", - "CFG_CENTER_WW4END2_0", - "CFG_CENTER_WW4END2_1", - "CFG_CENTER_WW4END2_10", - "CFG_CENTER_WW4END2_11", - "CFG_CENTER_WW4END2_12", - "CFG_CENTER_WW4END2_13", - "CFG_CENTER_WW4END2_14", - "CFG_CENTER_WW4END2_15", - "CFG_CENTER_WW4END2_16", - "CFG_CENTER_WW4END2_17", - "CFG_CENTER_WW4END2_18", - "CFG_CENTER_WW4END2_19", - "CFG_CENTER_WW4END2_2", - "CFG_CENTER_WW4END2_3", - "CFG_CENTER_WW4END2_4", - "CFG_CENTER_WW4END2_5", - "CFG_CENTER_WW4END2_6", - "CFG_CENTER_WW4END2_7", - "CFG_CENTER_WW4END2_8", - "CFG_CENTER_WW4END2_9", - "CFG_CENTER_WW4END3_0", - "CFG_CENTER_WW4END3_1", - "CFG_CENTER_WW4END3_10", - "CFG_CENTER_WW4END3_11", - "CFG_CENTER_WW4END3_12", - "CFG_CENTER_WW4END3_13", - "CFG_CENTER_WW4END3_14", - "CFG_CENTER_WW4END3_15", - "CFG_CENTER_WW4END3_16", - "CFG_CENTER_WW4END3_17", - "CFG_CENTER_WW4END3_18", - "CFG_CENTER_WW4END3_19", - "CFG_CENTER_WW4END3_2", - "CFG_CENTER_WW4END3_3", - "CFG_CENTER_WW4END3_4", - "CFG_CENTER_WW4END3_5", - "CFG_CENTER_WW4END3_6", - "CFG_CENTER_WW4END3_7", - "CFG_CENTER_WW4END3_8", - "CFG_CENTER_WW4END3_9" - ] + "wires": { + "CFG_CENTER_BLOCK_OUTS_B0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BOT_CFG_IO_ACCESS_VGGCOMPOUT": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA10": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA11": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA12": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA13": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA14": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA2": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA3": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA4": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA5": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA6": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA7": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA8": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA9": null, + "CFG_CENTER_BYP0_0": null, + "CFG_CENTER_BYP0_1": null, + "CFG_CENTER_BYP0_10": null, + "CFG_CENTER_BYP0_11": null, + "CFG_CENTER_BYP0_12": null, + "CFG_CENTER_BYP0_13": null, + "CFG_CENTER_BYP0_14": null, + "CFG_CENTER_BYP0_15": null, + "CFG_CENTER_BYP0_16": null, + "CFG_CENTER_BYP0_17": null, + "CFG_CENTER_BYP0_18": null, + "CFG_CENTER_BYP0_19": null, + "CFG_CENTER_BYP0_2": null, + "CFG_CENTER_BYP0_3": null, + "CFG_CENTER_BYP0_4": null, + "CFG_CENTER_BYP0_5": null, + "CFG_CENTER_BYP0_6": null, + "CFG_CENTER_BYP0_7": null, + "CFG_CENTER_BYP0_8": null, + "CFG_CENTER_BYP0_9": null, + "CFG_CENTER_BYP1_0": null, + "CFG_CENTER_BYP1_1": null, + "CFG_CENTER_BYP1_10": null, + "CFG_CENTER_BYP1_11": null, + "CFG_CENTER_BYP1_12": null, + "CFG_CENTER_BYP1_13": null, + "CFG_CENTER_BYP1_14": null, + "CFG_CENTER_BYP1_15": null, + "CFG_CENTER_BYP1_16": null, + "CFG_CENTER_BYP1_17": null, + "CFG_CENTER_BYP1_18": null, + "CFG_CENTER_BYP1_19": null, + "CFG_CENTER_BYP1_2": null, + "CFG_CENTER_BYP1_3": null, + "CFG_CENTER_BYP1_4": null, + "CFG_CENTER_BYP1_5": null, + "CFG_CENTER_BYP1_6": null, + "CFG_CENTER_BYP1_7": null, + "CFG_CENTER_BYP1_8": null, + "CFG_CENTER_BYP1_9": null, + "CFG_CENTER_BYP2_0": null, + "CFG_CENTER_BYP2_1": null, + "CFG_CENTER_BYP2_10": null, + "CFG_CENTER_BYP2_11": null, + "CFG_CENTER_BYP2_12": null, + "CFG_CENTER_BYP2_13": null, + "CFG_CENTER_BYP2_14": null, + "CFG_CENTER_BYP2_15": null, + "CFG_CENTER_BYP2_16": null, + "CFG_CENTER_BYP2_17": null, + "CFG_CENTER_BYP2_18": null, + "CFG_CENTER_BYP2_19": null, + "CFG_CENTER_BYP2_2": null, + "CFG_CENTER_BYP2_3": null, + "CFG_CENTER_BYP2_4": null, + "CFG_CENTER_BYP2_5": null, + "CFG_CENTER_BYP2_6": null, + "CFG_CENTER_BYP2_7": null, + "CFG_CENTER_BYP2_8": null, + "CFG_CENTER_BYP2_9": null, + "CFG_CENTER_BYP3_0": null, + "CFG_CENTER_BYP3_1": null, + "CFG_CENTER_BYP3_10": null, + "CFG_CENTER_BYP3_11": null, + "CFG_CENTER_BYP3_12": null, + "CFG_CENTER_BYP3_13": null, + "CFG_CENTER_BYP3_14": null, + "CFG_CENTER_BYP3_15": null, + "CFG_CENTER_BYP3_16": null, + "CFG_CENTER_BYP3_17": null, + "CFG_CENTER_BYP3_18": null, + "CFG_CENTER_BYP3_19": null, + "CFG_CENTER_BYP3_2": null, + "CFG_CENTER_BYP3_3": null, + "CFG_CENTER_BYP3_4": null, + "CFG_CENTER_BYP3_5": null, + "CFG_CENTER_BYP3_6": null, + "CFG_CENTER_BYP3_7": null, + "CFG_CENTER_BYP3_8": null, + "CFG_CENTER_BYP3_9": null, + "CFG_CENTER_BYP4_0": null, + "CFG_CENTER_BYP4_1": null, + "CFG_CENTER_BYP4_10": null, + "CFG_CENTER_BYP4_11": null, + "CFG_CENTER_BYP4_12": null, + "CFG_CENTER_BYP4_13": null, + "CFG_CENTER_BYP4_14": null, + "CFG_CENTER_BYP4_15": null, + "CFG_CENTER_BYP4_16": null, + "CFG_CENTER_BYP4_17": null, + "CFG_CENTER_BYP4_18": null, + "CFG_CENTER_BYP4_19": null, + "CFG_CENTER_BYP4_2": null, + "CFG_CENTER_BYP4_3": null, + "CFG_CENTER_BYP4_4": null, + "CFG_CENTER_BYP4_5": null, + "CFG_CENTER_BYP4_6": null, + "CFG_CENTER_BYP4_7": null, + "CFG_CENTER_BYP4_8": null, + "CFG_CENTER_BYP4_9": null, + "CFG_CENTER_BYP5_0": null, + "CFG_CENTER_BYP5_1": null, + "CFG_CENTER_BYP5_10": null, + "CFG_CENTER_BYP5_11": null, + "CFG_CENTER_BYP5_12": null, + "CFG_CENTER_BYP5_13": null, + "CFG_CENTER_BYP5_14": null, + "CFG_CENTER_BYP5_15": null, + "CFG_CENTER_BYP5_16": null, + "CFG_CENTER_BYP5_17": null, + "CFG_CENTER_BYP5_18": null, + "CFG_CENTER_BYP5_19": null, + "CFG_CENTER_BYP5_2": null, + "CFG_CENTER_BYP5_3": null, + "CFG_CENTER_BYP5_4": null, + "CFG_CENTER_BYP5_5": null, + "CFG_CENTER_BYP5_6": null, + "CFG_CENTER_BYP5_7": null, + "CFG_CENTER_BYP5_8": null, + "CFG_CENTER_BYP5_9": null, + "CFG_CENTER_BYP6_0": null, + "CFG_CENTER_BYP6_1": null, + "CFG_CENTER_BYP6_10": null, + "CFG_CENTER_BYP6_11": null, + "CFG_CENTER_BYP6_12": null, + "CFG_CENTER_BYP6_13": null, + "CFG_CENTER_BYP6_14": null, + "CFG_CENTER_BYP6_15": null, + "CFG_CENTER_BYP6_16": null, + "CFG_CENTER_BYP6_17": null, + "CFG_CENTER_BYP6_18": null, + "CFG_CENTER_BYP6_19": null, + "CFG_CENTER_BYP6_2": null, + "CFG_CENTER_BYP6_3": null, + "CFG_CENTER_BYP6_4": null, + "CFG_CENTER_BYP6_5": null, + "CFG_CENTER_BYP6_6": null, + "CFG_CENTER_BYP6_7": null, + "CFG_CENTER_BYP6_8": null, + "CFG_CENTER_BYP6_9": null, + "CFG_CENTER_BYP7_0": null, + "CFG_CENTER_BYP7_1": null, + "CFG_CENTER_BYP7_10": null, + "CFG_CENTER_BYP7_11": null, + "CFG_CENTER_BYP7_12": null, + "CFG_CENTER_BYP7_13": null, + "CFG_CENTER_BYP7_14": null, + "CFG_CENTER_BYP7_15": null, + "CFG_CENTER_BYP7_16": null, + "CFG_CENTER_BYP7_17": null, + "CFG_CENTER_BYP7_18": null, + "CFG_CENTER_BYP7_19": null, + "CFG_CENTER_BYP7_2": null, + "CFG_CENTER_BYP7_3": null, + "CFG_CENTER_BYP7_4": null, + "CFG_CENTER_BYP7_5": null, + "CFG_CENTER_BYP7_6": null, + "CFG_CENTER_BYP7_7": null, + "CFG_CENTER_BYP7_8": null, + "CFG_CENTER_BYP7_9": null, + "CFG_CENTER_CLK0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_EE2A0_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_16": { 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"325.400" + }, + "CFG_CENTER_EE2A3_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A3_1": { + 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+ "CFG_CENTER_FAN0_2": null, + "CFG_CENTER_FAN0_3": null, + "CFG_CENTER_FAN0_4": null, + "CFG_CENTER_FAN0_5": null, + "CFG_CENTER_FAN0_6": null, + "CFG_CENTER_FAN0_7": null, + "CFG_CENTER_FAN0_8": null, + "CFG_CENTER_FAN0_9": null, + "CFG_CENTER_FAN1_0": null, + "CFG_CENTER_FAN1_1": null, + "CFG_CENTER_FAN1_10": null, + "CFG_CENTER_FAN1_11": null, + "CFG_CENTER_FAN1_12": null, + "CFG_CENTER_FAN1_13": null, + "CFG_CENTER_FAN1_14": null, + "CFG_CENTER_FAN1_15": null, + "CFG_CENTER_FAN1_16": null, + "CFG_CENTER_FAN1_17": null, + "CFG_CENTER_FAN1_18": null, + "CFG_CENTER_FAN1_19": null, + "CFG_CENTER_FAN1_2": null, + "CFG_CENTER_FAN1_3": null, + "CFG_CENTER_FAN1_4": null, + "CFG_CENTER_FAN1_5": null, + "CFG_CENTER_FAN1_6": null, + "CFG_CENTER_FAN1_7": null, + "CFG_CENTER_FAN1_8": null, + "CFG_CENTER_FAN1_9": null, + "CFG_CENTER_FAN2_0": null, + "CFG_CENTER_FAN2_1": null, + "CFG_CENTER_FAN2_10": null, + "CFG_CENTER_FAN2_11": null, + "CFG_CENTER_FAN2_12": null, + "CFG_CENTER_FAN2_13": null, + "CFG_CENTER_FAN2_14": null, + "CFG_CENTER_FAN2_15": null, + "CFG_CENTER_FAN2_16": null, + "CFG_CENTER_FAN2_17": null, + "CFG_CENTER_FAN2_18": null, + "CFG_CENTER_FAN2_19": null, + "CFG_CENTER_FAN2_2": null, + "CFG_CENTER_FAN2_3": null, + "CFG_CENTER_FAN2_4": null, + "CFG_CENTER_FAN2_5": null, + "CFG_CENTER_FAN2_6": null, + "CFG_CENTER_FAN2_7": null, + "CFG_CENTER_FAN2_8": null, + "CFG_CENTER_FAN2_9": null, + "CFG_CENTER_FAN3_0": null, + "CFG_CENTER_FAN3_1": null, + "CFG_CENTER_FAN3_10": null, + "CFG_CENTER_FAN3_11": null, + "CFG_CENTER_FAN3_12": null, + "CFG_CENTER_FAN3_13": null, + "CFG_CENTER_FAN3_14": null, + "CFG_CENTER_FAN3_15": null, + "CFG_CENTER_FAN3_16": null, + "CFG_CENTER_FAN3_17": null, + "CFG_CENTER_FAN3_18": null, + "CFG_CENTER_FAN3_19": null, + "CFG_CENTER_FAN3_2": null, + "CFG_CENTER_FAN3_3": null, + "CFG_CENTER_FAN3_4": null, + "CFG_CENTER_FAN3_5": null, + "CFG_CENTER_FAN3_6": null, + "CFG_CENTER_FAN3_7": null, + "CFG_CENTER_FAN3_8": null, + "CFG_CENTER_FAN3_9": null, + "CFG_CENTER_FAN4_0": null, + "CFG_CENTER_FAN4_1": null, + "CFG_CENTER_FAN4_10": null, + "CFG_CENTER_FAN4_11": null, + "CFG_CENTER_FAN4_12": null, + "CFG_CENTER_FAN4_13": null, + "CFG_CENTER_FAN4_14": null, + "CFG_CENTER_FAN4_15": null, + "CFG_CENTER_FAN4_16": null, + "CFG_CENTER_FAN4_17": null, + "CFG_CENTER_FAN4_18": null, + "CFG_CENTER_FAN4_19": null, + "CFG_CENTER_FAN4_2": null, + "CFG_CENTER_FAN4_3": null, + "CFG_CENTER_FAN4_4": null, + "CFG_CENTER_FAN4_5": null, + "CFG_CENTER_FAN4_6": null, + "CFG_CENTER_FAN4_7": null, + "CFG_CENTER_FAN4_8": null, + "CFG_CENTER_FAN4_9": null, + "CFG_CENTER_FAN5_0": null, + "CFG_CENTER_FAN5_1": null, + "CFG_CENTER_FAN5_10": null, + "CFG_CENTER_FAN5_11": null, + "CFG_CENTER_FAN5_12": null, + "CFG_CENTER_FAN5_13": null, + "CFG_CENTER_FAN5_14": null, + "CFG_CENTER_FAN5_15": null, + "CFG_CENTER_FAN5_16": null, + "CFG_CENTER_FAN5_17": null, + "CFG_CENTER_FAN5_18": null, + "CFG_CENTER_FAN5_19": null, + "CFG_CENTER_FAN5_2": null, + "CFG_CENTER_FAN5_3": null, + "CFG_CENTER_FAN5_4": null, + "CFG_CENTER_FAN5_5": null, + "CFG_CENTER_FAN5_6": null, + "CFG_CENTER_FAN5_7": null, + "CFG_CENTER_FAN5_8": null, + "CFG_CENTER_FAN5_9": null, + "CFG_CENTER_FAN6_0": null, + "CFG_CENTER_FAN6_1": null, + "CFG_CENTER_FAN6_10": null, + "CFG_CENTER_FAN6_11": null, + "CFG_CENTER_FAN6_12": null, + "CFG_CENTER_FAN6_13": null, + "CFG_CENTER_FAN6_14": null, + "CFG_CENTER_FAN6_15": null, + "CFG_CENTER_FAN6_16": null, + "CFG_CENTER_FAN6_17": null, + "CFG_CENTER_FAN6_18": null, + "CFG_CENTER_FAN6_19": null, + "CFG_CENTER_FAN6_2": null, + "CFG_CENTER_FAN6_3": null, + "CFG_CENTER_FAN6_4": null, + "CFG_CENTER_FAN6_5": null, + "CFG_CENTER_FAN6_6": null, + "CFG_CENTER_FAN6_7": null, + "CFG_CENTER_FAN6_8": null, + "CFG_CENTER_FAN6_9": null, + "CFG_CENTER_FAN7_0": null, + "CFG_CENTER_FAN7_1": null, + "CFG_CENTER_FAN7_10": null, + "CFG_CENTER_FAN7_11": null, + "CFG_CENTER_FAN7_12": null, + "CFG_CENTER_FAN7_13": null, + "CFG_CENTER_FAN7_14": null, + "CFG_CENTER_FAN7_15": null, + "CFG_CENTER_FAN7_16": null, + "CFG_CENTER_FAN7_17": null, + "CFG_CENTER_FAN7_18": null, + "CFG_CENTER_FAN7_19": null, + "CFG_CENTER_FAN7_2": null, + "CFG_CENTER_FAN7_3": null, + "CFG_CENTER_FAN7_4": null, + "CFG_CENTER_FAN7_5": null, + "CFG_CENTER_FAN7_6": null, + "CFG_CENTER_FAN7_7": null, + "CFG_CENTER_FAN7_8": null, + "CFG_CENTER_FAN7_9": null, + "CFG_CENTER_IMUX0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_2": { + "cap": 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"0.000" + }, + "CFG_CENTER_IMUX25_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_2": { + "cap": "1.111", + "res": "0.000" + }, + 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+ "res": "0.000" + }, + "CFG_CENTER_IMUX29_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_2": { 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"0.000" + }, + "CFG_CENTER_IMUX43_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LH10_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LOGIC_OUTS_B0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_8": { + "cap": "1.111", + "res": "0.000" + }, + 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"CFG_CENTER_LOGIC_OUTS_B16_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_12": { + "cap": "1.111", + "res": "0.000" + }, + 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{ + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_10": { + "cap": "1.111", + "res": "0.000" + }, + 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"CFG_CENTER_LOGIC_OUTS_B23_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_NE2A0_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_1": { + "cap": "83.787", + "res": "325.400" + }, + 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"res": "325.400" + }, + "CFG_CENTER_SE2A1_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_15": { + "cap": "83.787", + "res": "325.400" + }, + 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"CFG_CENTER_SW4A1_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_0": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_1": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_10": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_11": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_12": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_13": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_14": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_15": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_16": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_17": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_18": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_19": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_2": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_3": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_4": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_5": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_6": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_7": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_8": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_9": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_0": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_1": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_10": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_11": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_12": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_13": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_14": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_15": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_16": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_17": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_18": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_19": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_2": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_3": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_4": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_5": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_6": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_7": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_8": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_9": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_0": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_1": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_10": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_11": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_12": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_13": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_14": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_15": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_16": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_17": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_18": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_19": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_2": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_3": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_4": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_5": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_6": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_7": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_8": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_9": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_0": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_1": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_10": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_11": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_12": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_13": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_14": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_15": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_16": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_17": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_18": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_19": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_2": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_3": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_4": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_5": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_6": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_7": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_8": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_9": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_0": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_1": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_10": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_11": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_12": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_13": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_14": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_15": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_16": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_17": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_18": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_19": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_2": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_3": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_4": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_5": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_6": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_7": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_8": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_9": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_0": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_1": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_10": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_11": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_12": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_13": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_14": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_15": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_16": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_17": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_18": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_19": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_2": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_3": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_4": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_5": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_6": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_7": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_8": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_9": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_0": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_1": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_10": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_11": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_12": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_13": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_14": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_15": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_16": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_17": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_18": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_19": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_2": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_3": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_4": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_5": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_6": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_7": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_8": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_9": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_0": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_1": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_10": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_11": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_12": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_13": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_14": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_15": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_16": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_17": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_18": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_19": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_2": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_3": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_4": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_5": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_6": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_7": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_8": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_9": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A2_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_3": { 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"325.400" + }, + "CFG_CENTER_WW4B3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_9": { + "cap": "64.544", + "res": "325.400" + } + } } diff --git a/zynq7/tile_type_CFG_CENTER_MID.json b/zynq7/tile_type_CFG_CENTER_MID.json index 6206124..f764de3 100644 --- a/zynq7/tile_type_CFG_CENTER_MID.json +++ b/zynq7/tile_type_CFG_CENTER_MID.json @@ -2,1997 +2,5132 @@ "pips": { "CFG_CENTER_MID.CFG_CENTER_BSCAN1_CAPTURE->CFG_CENTER_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_CAPTURE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_DRCK->CFG_CENTER_LOGIC_OUTS_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_DRCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_RESET->CFG_CENTER_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_RESET" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_RUNTEST->CFG_CENTER_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_RUNTEST" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_SEL->CFG_CENTER_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_SEL" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_SHIFT->CFG_CENTER_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_SHIFT" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TCK->CFG_CENTER_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_TCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TDI->CFG_CENTER_LOGIC_OUTS_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_TDI" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TMS->CFG_CENTER_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_TMS" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_UPDATE->CFG_CENTER_LOGIC_OUTS_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_UPDATE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_CAPTURE->CFG_CENTER_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_CAPTURE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_DRCK->CFG_CENTER_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_DRCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_RESET->CFG_CENTER_LOGIC_OUTS_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_RESET" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_RUNTEST->CFG_CENTER_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_RUNTEST" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_SEL->CFG_CENTER_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_SEL" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_SHIFT->CFG_CENTER_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_SHIFT" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TCK->CFG_CENTER_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_TCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TDI->CFG_CENTER_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_TDI" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TMS->CFG_CENTER_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_TMS" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_UPDATE->CFG_CENTER_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_UPDATE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_CAPTURE->CFG_CENTER_LOGIC_OUTS_B11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_CAPTURE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_DRCK->CFG_CENTER_LOGIC_OUTS_B22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_DRCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_RESET->CFG_CENTER_LOGIC_OUTS_B20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_RESET" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_RUNTEST->CFG_CENTER_LOGIC_OUTS_B13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_RUNTEST" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_SEL->CFG_CENTER_LOGIC_OUTS_B16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_SEL" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_SHIFT->CFG_CENTER_LOGIC_OUTS_B21_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_SHIFT" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TCK->CFG_CENTER_LOGIC_OUTS_B19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_TCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TDI->CFG_CENTER_LOGIC_OUTS_B17_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_TDI" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TMS->CFG_CENTER_LOGIC_OUTS_B15_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_TMS" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_UPDATE->CFG_CENTER_LOGIC_OUTS_B18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_UPDATE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_CAPTURE->CFG_CENTER_LOGIC_OUTS_B12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_CAPTURE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_DRCK->CFG_CENTER_LOGIC_OUTS_B23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_DRCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_RESET->CFG_CENTER_LOGIC_OUTS_B21_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_RESET" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_RUNTEST->CFG_CENTER_LOGIC_OUTS_B14_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_RUNTEST" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_SEL->CFG_CENTER_LOGIC_OUTS_B17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_SEL" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_SHIFT->CFG_CENTER_LOGIC_OUTS_B22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_SHIFT" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TCK->CFG_CENTER_LOGIC_OUTS_B20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_TCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TDI->CFG_CENTER_LOGIC_OUTS_B18_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_TDI" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TMS->CFG_CENTER_LOGIC_OUTS_B16_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_TMS" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_UPDATE->CFG_CENTER_LOGIC_OUTS_B19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_UPDATE" }, "CFG_CENTER_MID.CFG_CENTER_CLK1_5->CFG_CENTER_STARTUP_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_CLK1_5" }, "CFG_CENTER_MID.CFG_CENTER_CLK1_6->CFG_CENTER_ICAP0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_CLK1_6" }, "CFG_CENTER_MID.CFG_CENTER_CLK1_7->CFG_CENTER_STARTUP_USRCCLKO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_USRCCLKO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_CLK1_7" }, "CFG_CENTER_MID.CFG_CENTER_CLK1_8->CFG_CENTER_MID_DNA_PORT_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_DNA_PORT_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_CLK1_8" }, "CFG_CENTER_MID.CFG_CENTER_CLK1_9->CFG_CENTER_CAPTURE_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_CAPTURE_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_CLK1_9" }, "CFG_CENTER_MID.CFG_CENTER_DCIRESET_LOCKED->CFG_CENTER_LOGIC_OUTS_B21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_DCIRESET_LOCKED" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_CRCERROR->CFG_CENTER_LOGIC_OUTS_B15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_CRCERROR" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_ECCERROR->CFG_CENTER_LOGIC_OUTS_B20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_ECCERROR" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_ECCERRORSINGLE->CFG_CENTER_LOGIC_OUTS_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR0->CFG_CENTER_LOGIC_OUTS_B10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR0" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR1->CFG_CENTER_LOGIC_OUTS_B11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR1" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR10->CFG_CENTER_LOGIC_OUTS_B20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR10" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR11->CFG_CENTER_LOGIC_OUTS_B21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR11" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR12->CFG_CENTER_LOGIC_OUTS_B22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR12" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR13->CFG_CENTER_LOGIC_OUTS_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR13" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR14->CFG_CENTER_LOGIC_OUTS_B8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR14" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR15->CFG_CENTER_LOGIC_OUTS_B9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR15" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR16->CFG_CENTER_LOGIC_OUTS_B10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR16" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR17->CFG_CENTER_LOGIC_OUTS_B11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR17" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR18->CFG_CENTER_LOGIC_OUTS_B12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR18" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR19->CFG_CENTER_LOGIC_OUTS_B13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR19" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR2->CFG_CENTER_LOGIC_OUTS_B12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR2" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR20->CFG_CENTER_LOGIC_OUTS_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR20" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR21->CFG_CENTER_LOGIC_OUTS_B15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR21" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR22->CFG_CENTER_LOGIC_OUTS_B16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR22" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR23->CFG_CENTER_LOGIC_OUTS_B17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR23" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR24->CFG_CENTER_LOGIC_OUTS_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR24" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR25->CFG_CENTER_LOGIC_OUTS_B19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR25" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR3->CFG_CENTER_LOGIC_OUTS_B13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR3" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR4->CFG_CENTER_LOGIC_OUTS_B14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR4" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR5->CFG_CENTER_LOGIC_OUTS_B15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR5" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR6->CFG_CENTER_LOGIC_OUTS_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR6" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR7->CFG_CENTER_LOGIC_OUTS_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR7" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR8->CFG_CENTER_LOGIC_OUTS_B18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR8" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR9->CFG_CENTER_LOGIC_OUTS_B19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR9" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT0->CFG_CENTER_LOGIC_OUTS_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT0" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT1->CFG_CENTER_LOGIC_OUTS_B19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT1" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT2->CFG_CENTER_LOGIC_OUTS_B20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT2" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT3->CFG_CENTER_LOGIC_OUTS_B21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT3" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT4->CFG_CENTER_LOGIC_OUTS_B22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT4" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME0->CFG_CENTER_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME0" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME1->CFG_CENTER_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME1" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME10->CFG_CENTER_LOGIC_OUTS_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME10" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME11->CFG_CENTER_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME11" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME12->CFG_CENTER_LOGIC_OUTS_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME12" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME2->CFG_CENTER_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME2" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME3->CFG_CENTER_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME3" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME4->CFG_CENTER_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME4" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME5->CFG_CENTER_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME5" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME6->CFG_CENTER_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME6" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME7->CFG_CENTER_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME7" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME8->CFG_CENTER_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME8" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME9->CFG_CENTER_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME9" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROMEVALID->CFG_CENTER_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROMEVALID" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD0->CFG_CENTER_LOGIC_OUTS_B20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD0" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD1->CFG_CENTER_LOGIC_OUTS_B21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD1" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD2->CFG_CENTER_LOGIC_OUTS_B22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD2" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD3->CFG_CENTER_LOGIC_OUTS_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD3" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD4->CFG_CENTER_LOGIC_OUTS_B8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD4" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD5->CFG_CENTER_LOGIC_OUTS_B9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD5" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD6->CFG_CENTER_LOGIC_OUTS_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD6" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O0->CFG_CENTER_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O0" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O1->CFG_CENTER_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O1" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O10->CFG_CENTER_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O10" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O11->CFG_CENTER_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O11" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O12->CFG_CENTER_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O12" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O13->CFG_CENTER_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O13" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O14->CFG_CENTER_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O14" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O15->CFG_CENTER_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O15" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O16->CFG_CENTER_LOGIC_OUTS_B16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O16" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O17->CFG_CENTER_LOGIC_OUTS_B17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O17" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O18->CFG_CENTER_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O18" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O19->CFG_CENTER_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O19" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O2->CFG_CENTER_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O2" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O20->CFG_CENTER_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O20" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O21->CFG_CENTER_LOGIC_OUTS_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O21" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O22->CFG_CENTER_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O22" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O23->CFG_CENTER_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O23" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O24->CFG_CENTER_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O24" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O25->CFG_CENTER_LOGIC_OUTS_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O25" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O26->CFG_CENTER_LOGIC_OUTS_B10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O26" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O27->CFG_CENTER_LOGIC_OUTS_B11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O27" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O28->CFG_CENTER_LOGIC_OUTS_B12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O28" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O29->CFG_CENTER_LOGIC_OUTS_B13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O29" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O3->CFG_CENTER_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O3" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O30->CFG_CENTER_LOGIC_OUTS_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O30" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O31->CFG_CENTER_LOGIC_OUTS_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O31" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O4->CFG_CENTER_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O4" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O5->CFG_CENTER_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O5" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O6->CFG_CENTER_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O6" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O7->CFG_CENTER_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O7" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O8->CFG_CENTER_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O8" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O9->CFG_CENTER_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O9" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O0->CFG_CENTER_LOGIC_OUTS_B23_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O0" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O1->CFG_CENTER_LOGIC_OUTS_B12_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O1" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O10->CFG_CENTER_LOGIC_OUTS_B21_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O10" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O11->CFG_CENTER_LOGIC_OUTS_B22_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O11" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O12->CFG_CENTER_LOGIC_OUTS_B23_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O12" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O13->CFG_CENTER_LOGIC_OUTS_B12_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O13" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O14->CFG_CENTER_LOGIC_OUTS_B13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O14" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O15->CFG_CENTER_LOGIC_OUTS_B14_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O15" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O16->CFG_CENTER_LOGIC_OUTS_B15_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O16" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O17->CFG_CENTER_LOGIC_OUTS_B16_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O17" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O18->CFG_CENTER_LOGIC_OUTS_B17_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O18" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O19->CFG_CENTER_LOGIC_OUTS_B18_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O19" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O2->CFG_CENTER_LOGIC_OUTS_B13_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O2" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O20->CFG_CENTER_LOGIC_OUTS_B19_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O20" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O21->CFG_CENTER_LOGIC_OUTS_B20_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O21" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O22->CFG_CENTER_LOGIC_OUTS_B21_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O22" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O23->CFG_CENTER_LOGIC_OUTS_B22_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O23" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O24->CFG_CENTER_LOGIC_OUTS_B23_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O24" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O25->CFG_CENTER_LOGIC_OUTS_B10_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O25" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O26->CFG_CENTER_LOGIC_OUTS_B11_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O26" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O27->CFG_CENTER_LOGIC_OUTS_B12_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O27" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O28->CFG_CENTER_LOGIC_OUTS_B13_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O28" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O29->CFG_CENTER_LOGIC_OUTS_B14_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O29" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O3->CFG_CENTER_LOGIC_OUTS_B14_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O3" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O30->CFG_CENTER_LOGIC_OUTS_B15_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O30" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O31->CFG_CENTER_LOGIC_OUTS_B16_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O31" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O4->CFG_CENTER_LOGIC_OUTS_B15_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O4" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O5->CFG_CENTER_LOGIC_OUTS_B16_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O5" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O6->CFG_CENTER_LOGIC_OUTS_B17_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O6" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O7->CFG_CENTER_LOGIC_OUTS_B18_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O7" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O8->CFG_CENTER_LOGIC_OUTS_B19_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O8" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O9->CFG_CENTER_LOGIC_OUTS_B20_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O9" }, "CFG_CENTER_MID.CFG_CENTER_IMUX27_5->CFG_CENTER_ICAP0_I16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX27_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX28_12->CFG_CENTER_ICAP1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX28_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX28_13->CFG_CENTER_ICAP1_I16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX28_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX28_4->CFG_CENTER_ICAP0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX28_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX28_5->CFG_CENTER_ICAP0_I17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX28_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX29_12->CFG_CENTER_ICAP1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX29_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX29_13->CFG_CENTER_ICAP1_I17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX29_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX29_4->CFG_CENTER_ICAP0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX29_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX29_5->CFG_CENTER_ICAP0_I18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX29_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX30_12->CFG_CENTER_ICAP1_I2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX30_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX30_13->CFG_CENTER_ICAP1_I18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX30_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX30_4->CFG_CENTER_ICAP0_I2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX30_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX30_5->CFG_CENTER_ICAP0_I19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX30_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX31_12->CFG_CENTER_ICAP1_I3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX31_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX31_13->CFG_CENTER_ICAP1_I19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX31_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX31_4->CFG_CENTER_ICAP0_I3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX31_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX31_5->CFG_CENTER_ICAP0_I20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX31_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX32_12->CFG_CENTER_ICAP1_I4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX32_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX32_13->CFG_CENTER_ICAP1_I20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX32_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX32_4->CFG_CENTER_ICAP0_I4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX32_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX32_5->CFG_CENTER_ICAP0_I21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX32_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX33_12->CFG_CENTER_ICAP1_I5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX33_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX33_13->CFG_CENTER_ICAP1_I21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX33_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX33_3->CFG_CENTER_BSCAN1_TDO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_BSCAN1_TDO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX33_3" }, "CFG_CENTER_MID.CFG_CENTER_IMUX33_4->CFG_CENTER_ICAP0_I5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX33_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX33_5->CFG_CENTER_ICAP0_I22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX33_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX34_12->CFG_CENTER_ICAP1_I6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX34_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX34_13->CFG_CENTER_ICAP1_I22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX34_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX34_3->CFG_CENTER_BSCAN2_TDO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_BSCAN2_TDO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX34_3" }, "CFG_CENTER_MID.CFG_CENTER_IMUX34_4->CFG_CENTER_ICAP0_I6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX34_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX34_5->CFG_CENTER_ICAP0_I23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX34_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX35_12->CFG_CENTER_ICAP1_I7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX35_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX35_13->CFG_CENTER_ICAP1_I23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX35_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX35_4->CFG_CENTER_ICAP0_I7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX35_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX35_5->CFG_CENTER_ICAP0_I24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX35_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX35_8->CFG_CENTER_DCIRESET_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_DCIRESET_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX35_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX36_12->CFG_CENTER_ICAP1_I8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX36_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX36_13->CFG_CENTER_ICAP1_I24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX36_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX36_4->CFG_CENTER_ICAP0_I8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX36_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX36_5->CFG_CENTER_ICAP0_I25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX36_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX36_8->CFG_CENTER_STARTUP_KEYCLEARB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_KEYCLEARB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX36_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX37_12->CFG_CENTER_ICAP1_I9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX37_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX37_13->CFG_CENTER_ICAP1_I25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX37_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX37_4->CFG_CENTER_ICAP0_I9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX37_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX37_5->CFG_CENTER_ICAP0_I26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX37_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX37_8->CFG_CENTER_CAPTURE_CAP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_CAPTURE_CAP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX37_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX38_11->CFG_CENTER_BSCAN3_TDO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_BSCAN3_TDO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX38_11" }, "CFG_CENTER_MID.CFG_CENTER_IMUX38_12->CFG_CENTER_ICAP1_I10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX38_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX38_13->CFG_CENTER_ICAP1_I26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX38_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX38_4->CFG_CENTER_ICAP0_I10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX38_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX38_5->CFG_CENTER_ICAP0_I27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX38_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX38_8->CFG_CENTER_STARTUP_USRCCLKTS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_USRCCLKTS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX38_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX39_11->CFG_CENTER_BSCAN4_TDO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_BSCAN4_TDO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX39_11" }, "CFG_CENTER_MID.CFG_CENTER_IMUX39_12->CFG_CENTER_ICAP1_I11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX39_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX39_13->CFG_CENTER_ICAP1_I27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX39_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX39_4->CFG_CENTER_ICAP0_I11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX39_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX39_5->CFG_CENTER_ICAP0_I28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX39_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX39_8->CFG_CENTER_STARTUP_GTS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_GTS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX39_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX40_11->CFG_CENTER_ICAP0_CSIB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_CSIB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX40_11" }, "CFG_CENTER_MID.CFG_CENTER_IMUX40_12->CFG_CENTER_ICAP1_I12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX40_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX40_13->CFG_CENTER_ICAP1_I28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX40_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX40_4->CFG_CENTER_ICAP0_I12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX40_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX40_5->CFG_CENTER_ICAP0_I29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX40_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX40_8->CFG_CENTER_STARTUP_GSR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_GSR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX40_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX41_11->CFG_CENTER_ICAP0_RDWRB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_RDWRB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_11" }, "CFG_CENTER_MID.CFG_CENTER_IMUX41_12->CFG_CENTER_ICAP1_I13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX41_13->CFG_CENTER_ICAP1_I29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX41_4->CFG_CENTER_ICAP0_I13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX41_5->CFG_CENTER_ICAP0_I30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX41_8->CFG_CENTER_STARTUP_USRDONETS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_USRDONETS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX42_11->CFG_CENTER_ICAP1_RDWRB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_RDWRB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_11" }, "CFG_CENTER_MID.CFG_CENTER_IMUX42_12->CFG_CENTER_ICAP1_I14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX42_13->CFG_CENTER_ICAP1_I30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX42_4->CFG_CENTER_ICAP0_I14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX42_5->CFG_CENTER_ICAP0_I31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX42_8->CFG_CENTER_STARTUP_USRDONEO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_USRDONEO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX43_11->CFG_CENTER_ICAP1_CSIB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_CSIB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX43_11" }, "CFG_CENTER_MID.CFG_CENTER_IMUX43_12->CFG_CENTER_ICAP1_I15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX43_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX43_13->CFG_CENTER_ICAP1_I31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX43_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX43_4->CFG_CENTER_ICAP0_I15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX43_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX43_8->CFG_CENTER_STARTUP_PACK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_PACK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX43_8" }, "CFG_CENTER_MID.CFG_CENTER_MID_ICAP1_CLK->CFG_CENTER_ICAP1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_MID_ICAP1_CLK" }, "CFG_CENTER_MID.CFG_CENTER_STARTUP_CFGCLK->CFG_CENTER_LOGIC_OUTS_B14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_STARTUP_CFGCLK" }, "CFG_CENTER_MID.CFG_CENTER_STARTUP_CFGMCLK->CFG_CENTER_LOGIC_OUTS_B18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_STARTUP_CFGMCLK" }, "CFG_CENTER_MID.CFG_CENTER_STARTUP_EOS->CFG_CENTER_LOGIC_OUTS_B23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_STARTUP_EOS" }, "CFG_CENTER_MID.CFG_CENTER_STARTUP_PREQ->CFG_CENTER_LOGIC_OUTS_B22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_STARTUP_PREQ" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_CFGCLK->CFG_CENTER_LOGIC_OUTS_B9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_CFGCLK" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA0->CFG_CENTER_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA0" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA1->CFG_CENTER_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA1" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA10->CFG_CENTER_MID_USR_ACCESS_DATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA10" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA11->CFG_CENTER_MID_USR_ACCESS_DATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA11" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA12->CFG_CENTER_MID_USR_ACCESS_DATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA12" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA13->CFG_CENTER_MID_USR_ACCESS_DATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA13" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA14->CFG_CENTER_MID_USR_ACCESS_DATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA14" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA15->CFG_CENTER_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA15" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA16->CFG_CENTER_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA16" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA17->CFG_CENTER_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA17" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA18->CFG_CENTER_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA18" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA19->CFG_CENTER_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA19" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA2->CFG_CENTER_MID_USR_ACCESS_DATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA2" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA20->CFG_CENTER_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA20" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA21->CFG_CENTER_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA21" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA22->CFG_CENTER_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA22" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA23->CFG_CENTER_LOGIC_OUTS_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA23" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA24->CFG_CENTER_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA24" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA25->CFG_CENTER_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA25" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA26->CFG_CENTER_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA26" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA27->CFG_CENTER_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA27" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA28->CFG_CENTER_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA28" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA29->CFG_CENTER_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA29" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA3->CFG_CENTER_MID_USR_ACCESS_DATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA3" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA30->CFG_CENTER_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA30" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA31->CFG_CENTER_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA31" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA4->CFG_CENTER_MID_USR_ACCESS_DATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA4" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA5->CFG_CENTER_MID_USR_ACCESS_DATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA5" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA6->CFG_CENTER_MID_USR_ACCESS_DATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA6" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA7->CFG_CENTER_MID_USR_ACCESS_DATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA7" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA8->CFG_CENTER_MID_USR_ACCESS_DATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA8" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA9->CFG_CENTER_MID_USR_ACCESS_DATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA9" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATAVALID->CFG_CENTER_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATAVALID" } }, @@ -2001,40 +5136,346 @@ "name": "X0Y0", "prefix": "USR_ACCESS", "site_pins": { - "CFGCLK": "CFG_CENTER_USR_ACCESS_CFGCLK", - "DATA0": "CFG_CENTER_USR_ACCESS_DATA0", - "DATA1": "CFG_CENTER_USR_ACCESS_DATA1", - "DATA10": "CFG_CENTER_USR_ACCESS_DATA10", - "DATA11": "CFG_CENTER_USR_ACCESS_DATA11", - "DATA12": "CFG_CENTER_USR_ACCESS_DATA12", - "DATA13": "CFG_CENTER_USR_ACCESS_DATA13", - "DATA14": "CFG_CENTER_USR_ACCESS_DATA14", - "DATA15": "CFG_CENTER_USR_ACCESS_DATA15", - "DATA16": "CFG_CENTER_USR_ACCESS_DATA16", - "DATA17": "CFG_CENTER_USR_ACCESS_DATA17", - "DATA18": "CFG_CENTER_USR_ACCESS_DATA18", - "DATA19": "CFG_CENTER_USR_ACCESS_DATA19", - "DATA2": "CFG_CENTER_USR_ACCESS_DATA2", - "DATA20": "CFG_CENTER_USR_ACCESS_DATA20", - "DATA21": "CFG_CENTER_USR_ACCESS_DATA21", - "DATA22": "CFG_CENTER_USR_ACCESS_DATA22", - "DATA23": "CFG_CENTER_USR_ACCESS_DATA23", - "DATA24": "CFG_CENTER_USR_ACCESS_DATA24", - "DATA25": "CFG_CENTER_USR_ACCESS_DATA25", - "DATA26": "CFG_CENTER_USR_ACCESS_DATA26", - "DATA27": "CFG_CENTER_USR_ACCESS_DATA27", - "DATA28": "CFG_CENTER_USR_ACCESS_DATA28", - "DATA29": "CFG_CENTER_USR_ACCESS_DATA29", - "DATA3": "CFG_CENTER_USR_ACCESS_DATA3", - "DATA30": "CFG_CENTER_USR_ACCESS_DATA30", - "DATA31": "CFG_CENTER_USR_ACCESS_DATA31", - "DATA4": "CFG_CENTER_USR_ACCESS_DATA4", - "DATA5": "CFG_CENTER_USR_ACCESS_DATA5", - "DATA6": "CFG_CENTER_USR_ACCESS_DATA6", - "DATA7": "CFG_CENTER_USR_ACCESS_DATA7", - "DATA8": "CFG_CENTER_USR_ACCESS_DATA8", - "DATA9": "CFG_CENTER_USR_ACCESS_DATA9", - "DATAVALID": "CFG_CENTER_USR_ACCESS_DATAVALID" + "CFGCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_CFGCLK" + }, + "DATA0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA0" + }, + "DATA1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA1" + }, + "DATA10": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA10" + }, + "DATA11": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA11" + }, + "DATA12": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA12" + }, + "DATA13": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA13" + }, + "DATA14": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA14" + }, + "DATA15": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA15" + }, + "DATA16": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA16" + }, + "DATA17": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA17" + }, + "DATA18": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA18" + }, + "DATA19": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA19" + }, + "DATA2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA2" + }, + "DATA20": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA20" + }, + "DATA21": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA21" + }, + "DATA22": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA22" + }, + "DATA23": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA23" + }, + "DATA24": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA24" + }, + "DATA25": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA25" + }, + "DATA26": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA26" + }, + "DATA27": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA27" + }, + "DATA28": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA28" + }, + "DATA29": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA29" + }, + "DATA3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA3" + }, + "DATA30": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA30" + }, + "DATA31": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA31" + }, + "DATA4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA4" + }, + "DATA5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA5" + }, + "DATA6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA6" + }, + "DATA7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA7" + }, + "DATA8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA8" + }, + "DATA9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATA9" + }, + "DATAVALID": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_USR_ACCESS_DATAVALID" + } }, "type": "USR_ACCESS", "x_coord": 0, @@ -2044,17 +5485,116 @@ "name": "X0Y0", "prefix": "BSCAN", "site_pins": { - "CAPTURE": "CFG_CENTER_BSCAN1_CAPTURE", - "DRCK": "CFG_CENTER_BSCAN1_DRCK", - "RESET": "CFG_CENTER_BSCAN1_RESET", - "RUNTEST": "CFG_CENTER_BSCAN1_RUNTEST", - "SEL": "CFG_CENTER_BSCAN1_SEL", - "SHIFT": "CFG_CENTER_BSCAN1_SHIFT", - "TCK": "CFG_CENTER_BSCAN1_TCK", - "TDI": "CFG_CENTER_BSCAN1_TDI", - "TDO": "CFG_CENTER_BSCAN1_TDO", - "TMS": "CFG_CENTER_BSCAN1_TMS", - "UPDATE": "CFG_CENTER_BSCAN1_UPDATE" + "CAPTURE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN1_CAPTURE" + }, + "DRCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN1_DRCK" + }, + "RESET": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN1_RESET" + }, + "RUNTEST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN1_RUNTEST" + }, + "SEL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN1_SEL" + }, + "SHIFT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN1_SHIFT" + }, + "TCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN1_TCK" + }, + "TDI": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN1_TDI" + }, + "TDO": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_BSCAN1_TDO" + }, + "TMS": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN1_TMS" + }, + "UPDATE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN1_UPDATE" + } }, "type": "BSCAN", "x_coord": 0, @@ -2064,17 +5604,116 @@ "name": "X0Y1", "prefix": "BSCAN", "site_pins": { - "CAPTURE": "CFG_CENTER_BSCAN2_CAPTURE", - "DRCK": "CFG_CENTER_BSCAN2_DRCK", - "RESET": "CFG_CENTER_BSCAN2_RESET", - "RUNTEST": "CFG_CENTER_BSCAN2_RUNTEST", - "SEL": "CFG_CENTER_BSCAN2_SEL", - "SHIFT": "CFG_CENTER_BSCAN2_SHIFT", - "TCK": "CFG_CENTER_BSCAN2_TCK", - "TDI": "CFG_CENTER_BSCAN2_TDI", - "TDO": "CFG_CENTER_BSCAN2_TDO", - "TMS": "CFG_CENTER_BSCAN2_TMS", - "UPDATE": "CFG_CENTER_BSCAN2_UPDATE" + "CAPTURE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN2_CAPTURE" + }, + "DRCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN2_DRCK" + }, + "RESET": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN2_RESET" + }, + "RUNTEST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN2_RUNTEST" + }, + "SEL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN2_SEL" + }, + "SHIFT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN2_SHIFT" + }, + "TCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN2_TCK" + }, + "TDI": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN2_TDI" + }, + "TDO": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_BSCAN2_TDO" + }, + "TMS": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN2_TMS" + }, + "UPDATE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN2_UPDATE" + } }, "type": "BSCAN", "x_coord": 0, @@ -2084,73 +5723,676 @@ "name": "X0Y0", "prefix": "ICAP", "site_pins": { - "CLK": "CFG_CENTER_ICAP0_CLK", - "CSIB": "CFG_CENTER_ICAP0_CSIB", - "I0": "CFG_CENTER_ICAP0_I0", - "I1": "CFG_CENTER_ICAP0_I1", - "I10": "CFG_CENTER_ICAP0_I10", - "I11": "CFG_CENTER_ICAP0_I11", - "I12": "CFG_CENTER_ICAP0_I12", - "I13": "CFG_CENTER_ICAP0_I13", - "I14": "CFG_CENTER_ICAP0_I14", - "I15": "CFG_CENTER_ICAP0_I15", - "I16": "CFG_CENTER_ICAP0_I16", - "I17": "CFG_CENTER_ICAP0_I17", - "I18": "CFG_CENTER_ICAP0_I18", - "I19": "CFG_CENTER_ICAP0_I19", - "I2": "CFG_CENTER_ICAP0_I2", - "I20": "CFG_CENTER_ICAP0_I20", - "I21": "CFG_CENTER_ICAP0_I21", - "I22": "CFG_CENTER_ICAP0_I22", - "I23": "CFG_CENTER_ICAP0_I23", - "I24": "CFG_CENTER_ICAP0_I24", - "I25": "CFG_CENTER_ICAP0_I25", - "I26": "CFG_CENTER_ICAP0_I26", - "I27": "CFG_CENTER_ICAP0_I27", - "I28": "CFG_CENTER_ICAP0_I28", - "I29": "CFG_CENTER_ICAP0_I29", - "I3": "CFG_CENTER_ICAP0_I3", - "I30": "CFG_CENTER_ICAP0_I30", - "I31": "CFG_CENTER_ICAP0_I31", - "I4": "CFG_CENTER_ICAP0_I4", - "I5": "CFG_CENTER_ICAP0_I5", - "I6": "CFG_CENTER_ICAP0_I6", - "I7": "CFG_CENTER_ICAP0_I7", - "I8": "CFG_CENTER_ICAP0_I8", - "I9": "CFG_CENTER_ICAP0_I9", - "O0": "CFG_CENTER_ICAP0_O0", - "O1": "CFG_CENTER_ICAP0_O1", - "O10": "CFG_CENTER_ICAP0_O10", - "O11": "CFG_CENTER_ICAP0_O11", - "O12": "CFG_CENTER_ICAP0_O12", - "O13": "CFG_CENTER_ICAP0_O13", - "O14": "CFG_CENTER_ICAP0_O14", - "O15": "CFG_CENTER_ICAP0_O15", - "O16": "CFG_CENTER_ICAP0_O16", - "O17": "CFG_CENTER_ICAP0_O17", - "O18": "CFG_CENTER_ICAP0_O18", - "O19": "CFG_CENTER_ICAP0_O19", - "O2": "CFG_CENTER_ICAP0_O2", - "O20": "CFG_CENTER_ICAP0_O20", - "O21": "CFG_CENTER_ICAP0_O21", - "O22": "CFG_CENTER_ICAP0_O22", - "O23": "CFG_CENTER_ICAP0_O23", - "O24": "CFG_CENTER_ICAP0_O24", - "O25": "CFG_CENTER_ICAP0_O25", - "O26": "CFG_CENTER_ICAP0_O26", - "O27": "CFG_CENTER_ICAP0_O27", - "O28": "CFG_CENTER_ICAP0_O28", - "O29": "CFG_CENTER_ICAP0_O29", - "O3": "CFG_CENTER_ICAP0_O3", - "O30": "CFG_CENTER_ICAP0_O30", - "O31": "CFG_CENTER_ICAP0_O31", - "O4": "CFG_CENTER_ICAP0_O4", - "O5": "CFG_CENTER_ICAP0_O5", - "O6": "CFG_CENTER_ICAP0_O6", - "O7": "CFG_CENTER_ICAP0_O7", - "O8": "CFG_CENTER_ICAP0_O8", - "O9": "CFG_CENTER_ICAP0_O9", - "RDWRB": "CFG_CENTER_ICAP0_RDWRB" + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_CLK" + }, + "CSIB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_CSIB" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I1" + }, + "I10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I10" + }, + "I11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I11" + }, + "I12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I12" + }, + "I13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I13" + }, + "I14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I14" + }, + "I15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I15" + }, + "I16": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I16" + }, + "I17": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I17" + }, + "I18": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I18" + }, + "I19": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I19" + }, + "I2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I2" + }, + "I20": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I20" + }, + "I21": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I21" + }, + "I22": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I22" + }, + "I23": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I23" + }, + "I24": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I24" + }, + "I25": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I25" + }, + "I26": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I26" + }, + "I27": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I27" + }, + "I28": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I28" + }, + "I29": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I29" + }, + "I3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I3" + }, + "I30": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I30" + }, + "I31": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I31" + }, + "I4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I4" + }, + "I5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I5" + }, + "I6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I6" + }, + "I7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I7" + }, + "I8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I8" + }, + "I9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I9" + }, + "O0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O0" + }, + "O1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O1" + }, + "O10": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O10" + }, + "O11": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O11" + }, + "O12": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O12" + }, + "O13": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O13" + }, + "O14": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O14" + }, + "O15": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O15" + }, + "O16": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O16" + }, + "O17": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O17" + }, + "O18": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O18" + }, + "O19": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O19" + }, + "O2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O2" + }, + "O20": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O20" + }, + "O21": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O21" + }, + "O22": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O22" + }, + "O23": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O23" + }, + "O24": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O24" + }, + "O25": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O25" + }, + "O26": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O26" + }, + "O27": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O27" + }, + "O28": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O28" + }, + "O29": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O29" + }, + "O3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O3" + }, + "O30": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O30" + }, + "O31": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O31" + }, + "O4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O4" + }, + "O5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O5" + }, + "O6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O6" + }, + "O7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O7" + }, + "O8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O8" + }, + "O9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP0_O9" + }, + "RDWRB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_RDWRB" + } }, "type": "ICAP", "x_coord": 0, @@ -2160,61 +6402,556 @@ "name": "X0Y0", "prefix": "FRAME_ECC", "site_pins": { - "CRCERROR": "CFG_CENTER_FRAME_ECC_CRCERROR", - "ECCERROR": "CFG_CENTER_FRAME_ECC_ECCERROR", - "ECCERRORSINGLE": "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE", - "FAR0": "CFG_CENTER_FRAME_ECC_FAR0", - "FAR1": "CFG_CENTER_FRAME_ECC_FAR1", - "FAR10": "CFG_CENTER_FRAME_ECC_FAR10", - "FAR11": "CFG_CENTER_FRAME_ECC_FAR11", - "FAR12": "CFG_CENTER_FRAME_ECC_FAR12", - "FAR13": "CFG_CENTER_FRAME_ECC_FAR13", - "FAR14": "CFG_CENTER_FRAME_ECC_FAR14", - "FAR15": "CFG_CENTER_FRAME_ECC_FAR15", - "FAR16": "CFG_CENTER_FRAME_ECC_FAR16", - "FAR17": "CFG_CENTER_FRAME_ECC_FAR17", - "FAR18": "CFG_CENTER_FRAME_ECC_FAR18", - "FAR19": "CFG_CENTER_FRAME_ECC_FAR19", - "FAR2": "CFG_CENTER_FRAME_ECC_FAR2", - "FAR20": "CFG_CENTER_FRAME_ECC_FAR20", - "FAR21": "CFG_CENTER_FRAME_ECC_FAR21", - "FAR22": "CFG_CENTER_FRAME_ECC_FAR22", - "FAR23": "CFG_CENTER_FRAME_ECC_FAR23", - "FAR24": "CFG_CENTER_FRAME_ECC_FAR24", - "FAR25": "CFG_CENTER_FRAME_ECC_FAR25", - "FAR3": "CFG_CENTER_FRAME_ECC_FAR3", - "FAR4": "CFG_CENTER_FRAME_ECC_FAR4", - "FAR5": "CFG_CENTER_FRAME_ECC_FAR5", - "FAR6": "CFG_CENTER_FRAME_ECC_FAR6", - "FAR7": "CFG_CENTER_FRAME_ECC_FAR7", - "FAR8": "CFG_CENTER_FRAME_ECC_FAR8", - "FAR9": "CFG_CENTER_FRAME_ECC_FAR9", - "SYNBIT0": "CFG_CENTER_FRAME_ECC_SYNBIT0", - "SYNBIT1": "CFG_CENTER_FRAME_ECC_SYNBIT1", - "SYNBIT2": "CFG_CENTER_FRAME_ECC_SYNBIT2", - "SYNBIT3": "CFG_CENTER_FRAME_ECC_SYNBIT3", - "SYNBIT4": "CFG_CENTER_FRAME_ECC_SYNBIT4", - "SYNDROME0": "CFG_CENTER_FRAME_ECC_SYNDROME0", - "SYNDROME1": "CFG_CENTER_FRAME_ECC_SYNDROME1", - "SYNDROME10": "CFG_CENTER_FRAME_ECC_SYNDROME10", - "SYNDROME11": "CFG_CENTER_FRAME_ECC_SYNDROME11", - "SYNDROME12": "CFG_CENTER_FRAME_ECC_SYNDROME12", - "SYNDROME2": "CFG_CENTER_FRAME_ECC_SYNDROME2", - "SYNDROME3": "CFG_CENTER_FRAME_ECC_SYNDROME3", - "SYNDROME4": "CFG_CENTER_FRAME_ECC_SYNDROME4", - "SYNDROME5": "CFG_CENTER_FRAME_ECC_SYNDROME5", - "SYNDROME6": "CFG_CENTER_FRAME_ECC_SYNDROME6", - "SYNDROME7": "CFG_CENTER_FRAME_ECC_SYNDROME7", - "SYNDROME8": "CFG_CENTER_FRAME_ECC_SYNDROME8", - "SYNDROME9": "CFG_CENTER_FRAME_ECC_SYNDROME9", - "SYNDROMEVALID": "CFG_CENTER_FRAME_ECC_SYNDROMEVALID", - "SYNWORD0": "CFG_CENTER_FRAME_ECC_SYNWORD0", - "SYNWORD1": "CFG_CENTER_FRAME_ECC_SYNWORD1", - "SYNWORD2": "CFG_CENTER_FRAME_ECC_SYNWORD2", - "SYNWORD3": "CFG_CENTER_FRAME_ECC_SYNWORD3", - "SYNWORD4": "CFG_CENTER_FRAME_ECC_SYNWORD4", - "SYNWORD5": "CFG_CENTER_FRAME_ECC_SYNWORD5", - "SYNWORD6": "CFG_CENTER_FRAME_ECC_SYNWORD6" + "CRCERROR": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_CRCERROR" + }, + "ECCERROR": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_ECCERROR" + }, + "ECCERRORSINGLE": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE" + }, + "FAR0": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR0" + }, + "FAR1": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR1" + }, + "FAR10": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR10" + }, + "FAR11": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR11" + }, + "FAR12": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR12" + }, + "FAR13": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR13" + }, + "FAR14": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR14" + }, + "FAR15": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR15" + }, + "FAR16": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR16" + }, + "FAR17": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR17" + }, + "FAR18": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR18" + }, + "FAR19": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR19" + }, + "FAR2": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR2" + }, + "FAR20": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR20" + }, + "FAR21": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR21" + }, + "FAR22": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR22" + }, + "FAR23": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR23" + }, + "FAR24": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR24" + }, + "FAR25": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR25" + }, + "FAR3": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR3" + }, + "FAR4": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR4" + }, + "FAR5": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR5" + }, + "FAR6": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR6" + }, + "FAR7": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR7" + }, + "FAR8": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR8" + }, + "FAR9": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_FAR9" + }, + "SYNBIT0": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNBIT0" + }, + "SYNBIT1": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNBIT1" + }, + "SYNBIT2": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNBIT2" + }, + "SYNBIT3": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNBIT3" + }, + "SYNBIT4": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNBIT4" + }, + "SYNDROME0": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME0" + }, + "SYNDROME1": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME1" + }, + "SYNDROME10": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME10" + }, + "SYNDROME11": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME11" + }, + "SYNDROME12": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME12" + }, + "SYNDROME2": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME2" + }, + "SYNDROME3": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME3" + }, + "SYNDROME4": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME4" + }, + "SYNDROME5": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME5" + }, + "SYNDROME6": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME6" + }, + "SYNDROME7": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME7" + }, + "SYNDROME8": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME8" + }, + "SYNDROME9": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME9" + }, + "SYNDROMEVALID": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROMEVALID" + }, + "SYNWORD0": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD0" + }, + "SYNWORD1": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD1" + }, + "SYNWORD2": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD2" + }, + "SYNWORD3": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD3" + }, + "SYNWORD4": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD4" + }, + "SYNWORD5": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD5" + }, + "SYNWORD6": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD6" + } }, "type": "FRAME_ECC", "x_coord": 0, @@ -2224,19 +6961,136 @@ "name": "X0Y0", "prefix": "STARTUP", "site_pins": { - "CFGCLK": "CFG_CENTER_STARTUP_CFGCLK", - "CFGMCLK": "CFG_CENTER_STARTUP_CFGMCLK", - "CLK": "CFG_CENTER_STARTUP_CLK", - "EOS": "CFG_CENTER_STARTUP_EOS", - "GSR": "CFG_CENTER_STARTUP_GSR", - "GTS": "CFG_CENTER_STARTUP_GTS", - "KEYCLEARB": "CFG_CENTER_STARTUP_KEYCLEARB", - "PACK": "CFG_CENTER_STARTUP_PACK", - "PREQ": "CFG_CENTER_STARTUP_PREQ", - "USRCCLKO": "CFG_CENTER_STARTUP_USRCCLKO", - "USRCCLKTS": "CFG_CENTER_STARTUP_USRCCLKTS", - "USRDONEO": "CFG_CENTER_STARTUP_USRDONEO", - "USRDONETS": "CFG_CENTER_STARTUP_USRDONETS" + "CFGCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_STARTUP_CFGCLK" + }, + "CFGMCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_STARTUP_CFGMCLK" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_CLK" + }, + "EOS": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_STARTUP_EOS" + }, + "GSR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_GSR" + }, + "GTS": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_GTS" + }, + "KEYCLEARB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_KEYCLEARB" + }, + "PACK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_PACK" + }, + "PREQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_STARTUP_PREQ" + }, + "USRCCLKO": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_USRCCLKO" + }, + "USRCCLKTS": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_USRCCLKTS" + }, + "USRDONEO": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_USRDONEO" + }, + "USRDONETS": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_USRDONETS" + } }, "type": "STARTUP", "x_coord": 0, @@ -2246,8 +7100,26 @@ "name": "X0Y0", "prefix": "CAPTURE", "site_pins": { - "CAP": "CFG_CENTER_CAPTURE_CAP", - "CLK": "CFG_CENTER_CAPTURE_CLK" + "CAP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_CAPTURE_CAP" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_CAPTURE_CLK" + } }, "type": "CAPTURE", "x_coord": 0, @@ -2257,8 +7129,26 @@ "name": "X0Y0", "prefix": "DCIRESET", "site_pins": { - "LOCKED": "CFG_CENTER_DCIRESET_LOCKED", - "RST": "CFG_CENTER_DCIRESET_RST" + "LOCKED": { + "delay": [ + "0.003", + "0.003", + "0.003", + "0.003" + ], + "res": "206.25", + "wire": "CFG_CENTER_DCIRESET_LOCKED" + }, + "RST": { + "cap": "1.615", + "delay": [ + "0.018", + "0.021", + "0.051", + "0.058" + ], + "wire": "CFG_CENTER_DCIRESET_RST" + } }, "type": "DCIRESET", "x_coord": 0, @@ -2268,17 +7158,116 @@ "name": "X0Y2", "prefix": "BSCAN", "site_pins": { - "CAPTURE": "CFG_CENTER_BSCAN3_CAPTURE", - "DRCK": "CFG_CENTER_BSCAN3_DRCK", - "RESET": "CFG_CENTER_BSCAN3_RESET", - "RUNTEST": "CFG_CENTER_BSCAN3_RUNTEST", - "SEL": "CFG_CENTER_BSCAN3_SEL", - "SHIFT": "CFG_CENTER_BSCAN3_SHIFT", - "TCK": "CFG_CENTER_BSCAN3_TCK", - "TDI": "CFG_CENTER_BSCAN3_TDI", - "TDO": "CFG_CENTER_BSCAN3_TDO", - "TMS": "CFG_CENTER_BSCAN3_TMS", - "UPDATE": "CFG_CENTER_BSCAN3_UPDATE" + "CAPTURE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN3_CAPTURE" + }, + "DRCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN3_DRCK" + }, + "RESET": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN3_RESET" + }, + "RUNTEST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN3_RUNTEST" + }, + "SEL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN3_SEL" + }, + "SHIFT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN3_SHIFT" + }, + "TCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN3_TCK" + }, + "TDI": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN3_TDI" + }, + "TDO": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_BSCAN3_TDO" + }, + "TMS": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN3_TMS" + }, + "UPDATE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN3_UPDATE" + } }, "type": "BSCAN", "x_coord": 0, @@ -2288,17 +7277,116 @@ "name": "X0Y3", "prefix": "BSCAN", "site_pins": { - "CAPTURE": "CFG_CENTER_BSCAN4_CAPTURE", - "DRCK": "CFG_CENTER_BSCAN4_DRCK", - "RESET": "CFG_CENTER_BSCAN4_RESET", - "RUNTEST": "CFG_CENTER_BSCAN4_RUNTEST", - "SEL": "CFG_CENTER_BSCAN4_SEL", - "SHIFT": "CFG_CENTER_BSCAN4_SHIFT", - "TCK": "CFG_CENTER_BSCAN4_TCK", - "TDI": "CFG_CENTER_BSCAN4_TDI", - "TDO": "CFG_CENTER_BSCAN4_TDO", - "TMS": "CFG_CENTER_BSCAN4_TMS", - "UPDATE": "CFG_CENTER_BSCAN4_UPDATE" + "CAPTURE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN4_CAPTURE" + }, + "DRCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN4_DRCK" + }, + "RESET": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN4_RESET" + }, + "RUNTEST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN4_RUNTEST" + }, + "SEL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN4_SEL" + }, + "SHIFT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN4_SHIFT" + }, + "TCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN4_TCK" + }, + "TDI": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN4_TDI" + }, + "TDO": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_BSCAN4_TDO" + }, + "TMS": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN4_TMS" + }, + "UPDATE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_BSCAN4_UPDATE" + } }, "type": "BSCAN", "x_coord": 0, @@ -2308,73 +7396,676 @@ "name": "X0Y1", "prefix": "ICAP", "site_pins": { - "CLK": "CFG_CENTER_ICAP1_CLK", - "CSIB": "CFG_CENTER_ICAP1_CSIB", - "I0": "CFG_CENTER_ICAP1_I0", - "I1": "CFG_CENTER_ICAP1_I1", - "I10": "CFG_CENTER_ICAP1_I10", - "I11": "CFG_CENTER_ICAP1_I11", - "I12": "CFG_CENTER_ICAP1_I12", - "I13": "CFG_CENTER_ICAP1_I13", - "I14": "CFG_CENTER_ICAP1_I14", - "I15": "CFG_CENTER_ICAP1_I15", - "I16": "CFG_CENTER_ICAP1_I16", - "I17": "CFG_CENTER_ICAP1_I17", - "I18": "CFG_CENTER_ICAP1_I18", - "I19": "CFG_CENTER_ICAP1_I19", - "I2": "CFG_CENTER_ICAP1_I2", - "I20": "CFG_CENTER_ICAP1_I20", - "I21": "CFG_CENTER_ICAP1_I21", - "I22": "CFG_CENTER_ICAP1_I22", - "I23": "CFG_CENTER_ICAP1_I23", - "I24": "CFG_CENTER_ICAP1_I24", - "I25": "CFG_CENTER_ICAP1_I25", - "I26": "CFG_CENTER_ICAP1_I26", - "I27": "CFG_CENTER_ICAP1_I27", - "I28": "CFG_CENTER_ICAP1_I28", - "I29": "CFG_CENTER_ICAP1_I29", - "I3": "CFG_CENTER_ICAP1_I3", - "I30": "CFG_CENTER_ICAP1_I30", - "I31": "CFG_CENTER_ICAP1_I31", - "I4": "CFG_CENTER_ICAP1_I4", - "I5": "CFG_CENTER_ICAP1_I5", - "I6": "CFG_CENTER_ICAP1_I6", - "I7": "CFG_CENTER_ICAP1_I7", - "I8": "CFG_CENTER_ICAP1_I8", - "I9": "CFG_CENTER_ICAP1_I9", - "O0": "CFG_CENTER_ICAP1_O0", - "O1": "CFG_CENTER_ICAP1_O1", - "O10": "CFG_CENTER_ICAP1_O10", - "O11": "CFG_CENTER_ICAP1_O11", - "O12": "CFG_CENTER_ICAP1_O12", - "O13": "CFG_CENTER_ICAP1_O13", - "O14": "CFG_CENTER_ICAP1_O14", - "O15": "CFG_CENTER_ICAP1_O15", - "O16": "CFG_CENTER_ICAP1_O16", - "O17": "CFG_CENTER_ICAP1_O17", - "O18": "CFG_CENTER_ICAP1_O18", - "O19": "CFG_CENTER_ICAP1_O19", - "O2": "CFG_CENTER_ICAP1_O2", - "O20": "CFG_CENTER_ICAP1_O20", - "O21": "CFG_CENTER_ICAP1_O21", - "O22": "CFG_CENTER_ICAP1_O22", - "O23": "CFG_CENTER_ICAP1_O23", - "O24": "CFG_CENTER_ICAP1_O24", - "O25": "CFG_CENTER_ICAP1_O25", - "O26": "CFG_CENTER_ICAP1_O26", - "O27": "CFG_CENTER_ICAP1_O27", - "O28": "CFG_CENTER_ICAP1_O28", - "O29": "CFG_CENTER_ICAP1_O29", - "O3": "CFG_CENTER_ICAP1_O3", - "O30": "CFG_CENTER_ICAP1_O30", - "O31": "CFG_CENTER_ICAP1_O31", - "O4": "CFG_CENTER_ICAP1_O4", - "O5": "CFG_CENTER_ICAP1_O5", - "O6": "CFG_CENTER_ICAP1_O6", - "O7": "CFG_CENTER_ICAP1_O7", - "O8": "CFG_CENTER_ICAP1_O8", - "O9": "CFG_CENTER_ICAP1_O9", - "RDWRB": "CFG_CENTER_ICAP1_RDWRB" + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_CLK" + }, + "CSIB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_CSIB" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I1" + }, + "I10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I10" + }, + "I11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I11" + }, + "I12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I12" + }, + "I13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I13" + }, + "I14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I14" + }, + "I15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I15" + }, + "I16": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I16" + }, + "I17": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I17" + }, + "I18": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I18" + }, + "I19": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I19" + }, + "I2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I2" + }, + "I20": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I20" + }, + "I21": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I21" + }, + "I22": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I22" + }, + "I23": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I23" + }, + "I24": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I24" + }, + "I25": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I25" + }, + "I26": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I26" + }, + "I27": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I27" + }, + "I28": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I28" + }, + "I29": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I29" + }, + "I3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I3" + }, + "I30": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I30" + }, + "I31": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I31" + }, + "I4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I4" + }, + "I5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I5" + }, + "I6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I6" + }, + "I7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I7" + }, + "I8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I8" + }, + "I9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I9" + }, + "O0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O0" + }, + "O1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O1" + }, + "O10": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O10" + }, + "O11": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O11" + }, + "O12": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O12" + }, + "O13": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O13" + }, + "O14": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O14" + }, + "O15": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O15" + }, + "O16": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O16" + }, + "O17": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O17" + }, + "O18": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O18" + }, + "O19": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O19" + }, + "O2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O2" + }, + "O20": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O20" + }, + "O21": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O21" + }, + "O22": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O22" + }, + "O23": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O23" + }, + "O24": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O24" + }, + "O25": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O25" + }, + "O26": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O26" + }, + "O27": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O27" + }, + "O28": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O28" + }, + "O29": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O29" + }, + "O3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O3" + }, + "O30": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O30" + }, + "O31": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O31" + }, + "O4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O4" + }, + "O5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O5" + }, + "O6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O6" + }, + "O7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O7" + }, + "O8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O8" + }, + "O9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "240.625", + "wire": "CFG_CENTER_ICAP1_O9" + }, + "RDWRB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_RDWRB" + } }, "type": "ICAP", "x_coord": 0, @@ -2382,4806 +8073,17310 @@ } ], "tile_type": "CFG_CENTER_MID", - "wires": [ - "CFG_CENTER_BLOCK_OUTS_B0_0", - "CFG_CENTER_BLOCK_OUTS_B0_1", - "CFG_CENTER_BLOCK_OUTS_B0_10", - "CFG_CENTER_BLOCK_OUTS_B0_11", - "CFG_CENTER_BLOCK_OUTS_B0_12", - "CFG_CENTER_BLOCK_OUTS_B0_13", - "CFG_CENTER_BLOCK_OUTS_B0_14", - "CFG_CENTER_BLOCK_OUTS_B0_15", - "CFG_CENTER_BLOCK_OUTS_B0_16", - "CFG_CENTER_BLOCK_OUTS_B0_17", - "CFG_CENTER_BLOCK_OUTS_B0_18", - "CFG_CENTER_BLOCK_OUTS_B0_19", - "CFG_CENTER_BLOCK_OUTS_B0_2", - "CFG_CENTER_BLOCK_OUTS_B0_3", - "CFG_CENTER_BLOCK_OUTS_B0_4", - "CFG_CENTER_BLOCK_OUTS_B0_5", - "CFG_CENTER_BLOCK_OUTS_B0_6", - "CFG_CENTER_BLOCK_OUTS_B0_7", - "CFG_CENTER_BLOCK_OUTS_B0_8", - "CFG_CENTER_BLOCK_OUTS_B0_9", - "CFG_CENTER_BLOCK_OUTS_B1_0", - "CFG_CENTER_BLOCK_OUTS_B1_1", - "CFG_CENTER_BLOCK_OUTS_B1_10", - "CFG_CENTER_BLOCK_OUTS_B1_11", - "CFG_CENTER_BLOCK_OUTS_B1_12", - "CFG_CENTER_BLOCK_OUTS_B1_13", - "CFG_CENTER_BLOCK_OUTS_B1_14", - "CFG_CENTER_BLOCK_OUTS_B1_15", - "CFG_CENTER_BLOCK_OUTS_B1_16", - "CFG_CENTER_BLOCK_OUTS_B1_17", - "CFG_CENTER_BLOCK_OUTS_B1_18", - "CFG_CENTER_BLOCK_OUTS_B1_19", - "CFG_CENTER_BLOCK_OUTS_B1_2", - "CFG_CENTER_BLOCK_OUTS_B1_3", - "CFG_CENTER_BLOCK_OUTS_B1_4", - "CFG_CENTER_BLOCK_OUTS_B1_5", - "CFG_CENTER_BLOCK_OUTS_B1_6", - "CFG_CENTER_BLOCK_OUTS_B1_7", - "CFG_CENTER_BLOCK_OUTS_B1_8", - "CFG_CENTER_BLOCK_OUTS_B1_9", - "CFG_CENTER_BLOCK_OUTS_B2_0", - "CFG_CENTER_BLOCK_OUTS_B2_1", - "CFG_CENTER_BLOCK_OUTS_B2_10", - "CFG_CENTER_BLOCK_OUTS_B2_11", - "CFG_CENTER_BLOCK_OUTS_B2_12", - "CFG_CENTER_BLOCK_OUTS_B2_13", - "CFG_CENTER_BLOCK_OUTS_B2_14", - "CFG_CENTER_BLOCK_OUTS_B2_15", - "CFG_CENTER_BLOCK_OUTS_B2_16", - "CFG_CENTER_BLOCK_OUTS_B2_17", - "CFG_CENTER_BLOCK_OUTS_B2_18", - "CFG_CENTER_BLOCK_OUTS_B2_19", - "CFG_CENTER_BLOCK_OUTS_B2_2", - "CFG_CENTER_BLOCK_OUTS_B2_3", - "CFG_CENTER_BLOCK_OUTS_B2_4", - "CFG_CENTER_BLOCK_OUTS_B2_5", - "CFG_CENTER_BLOCK_OUTS_B2_6", - "CFG_CENTER_BLOCK_OUTS_B2_7", - "CFG_CENTER_BLOCK_OUTS_B2_8", - "CFG_CENTER_BLOCK_OUTS_B2_9", - "CFG_CENTER_BLOCK_OUTS_B3_0", - "CFG_CENTER_BLOCK_OUTS_B3_1", - "CFG_CENTER_BLOCK_OUTS_B3_10", - "CFG_CENTER_BLOCK_OUTS_B3_11", - "CFG_CENTER_BLOCK_OUTS_B3_12", - "CFG_CENTER_BLOCK_OUTS_B3_13", - "CFG_CENTER_BLOCK_OUTS_B3_14", - "CFG_CENTER_BLOCK_OUTS_B3_15", - "CFG_CENTER_BLOCK_OUTS_B3_16", - "CFG_CENTER_BLOCK_OUTS_B3_17", - "CFG_CENTER_BLOCK_OUTS_B3_18", - "CFG_CENTER_BLOCK_OUTS_B3_19", - "CFG_CENTER_BLOCK_OUTS_B3_2", - "CFG_CENTER_BLOCK_OUTS_B3_3", - "CFG_CENTER_BLOCK_OUTS_B3_4", - "CFG_CENTER_BLOCK_OUTS_B3_5", - "CFG_CENTER_BLOCK_OUTS_B3_6", - "CFG_CENTER_BLOCK_OUTS_B3_7", - "CFG_CENTER_BLOCK_OUTS_B3_8", - "CFG_CENTER_BLOCK_OUTS_B3_9", - "CFG_CENTER_BSCAN1_CAPTURE", - "CFG_CENTER_BSCAN1_DRCK", - "CFG_CENTER_BSCAN1_RESET", - "CFG_CENTER_BSCAN1_RUNTEST", - "CFG_CENTER_BSCAN1_SEL", - "CFG_CENTER_BSCAN1_SHIFT", - "CFG_CENTER_BSCAN1_TCK", - "CFG_CENTER_BSCAN1_TDI", - "CFG_CENTER_BSCAN1_TDO", - "CFG_CENTER_BSCAN1_TMS", - "CFG_CENTER_BSCAN1_UPDATE", - "CFG_CENTER_BSCAN2_CAPTURE", - "CFG_CENTER_BSCAN2_DRCK", - "CFG_CENTER_BSCAN2_RESET", - "CFG_CENTER_BSCAN2_RUNTEST", - "CFG_CENTER_BSCAN2_SEL", - "CFG_CENTER_BSCAN2_SHIFT", - "CFG_CENTER_BSCAN2_TCK", - "CFG_CENTER_BSCAN2_TDI", - "CFG_CENTER_BSCAN2_TDO", - "CFG_CENTER_BSCAN2_TMS", - "CFG_CENTER_BSCAN2_UPDATE", - "CFG_CENTER_BSCAN3_CAPTURE", - "CFG_CENTER_BSCAN3_DRCK", - "CFG_CENTER_BSCAN3_RESET", - "CFG_CENTER_BSCAN3_RUNTEST", - "CFG_CENTER_BSCAN3_SEL", - "CFG_CENTER_BSCAN3_SHIFT", - "CFG_CENTER_BSCAN3_TCK", - "CFG_CENTER_BSCAN3_TDI", - "CFG_CENTER_BSCAN3_TDO", - "CFG_CENTER_BSCAN3_TMS", - "CFG_CENTER_BSCAN3_UPDATE", - "CFG_CENTER_BSCAN4_CAPTURE", - "CFG_CENTER_BSCAN4_DRCK", - "CFG_CENTER_BSCAN4_RESET", - "CFG_CENTER_BSCAN4_RUNTEST", - "CFG_CENTER_BSCAN4_SEL", - "CFG_CENTER_BSCAN4_SHIFT", - "CFG_CENTER_BSCAN4_TCK", - "CFG_CENTER_BSCAN4_TDI", - "CFG_CENTER_BSCAN4_TDO", - "CFG_CENTER_BSCAN4_TMS", - "CFG_CENTER_BSCAN4_UPDATE", - "CFG_CENTER_BYP0_0", - "CFG_CENTER_BYP0_1", - "CFG_CENTER_BYP0_10", - "CFG_CENTER_BYP0_11", - "CFG_CENTER_BYP0_12", - "CFG_CENTER_BYP0_13", - "CFG_CENTER_BYP0_14", - "CFG_CENTER_BYP0_15", - "CFG_CENTER_BYP0_16", - "CFG_CENTER_BYP0_17", - "CFG_CENTER_BYP0_18", - "CFG_CENTER_BYP0_19", - "CFG_CENTER_BYP0_2", - "CFG_CENTER_BYP0_3", - "CFG_CENTER_BYP0_4", - "CFG_CENTER_BYP0_5", - "CFG_CENTER_BYP0_6", - "CFG_CENTER_BYP0_7", - "CFG_CENTER_BYP0_8", - "CFG_CENTER_BYP0_9", - "CFG_CENTER_BYP1_0", - "CFG_CENTER_BYP1_1", - "CFG_CENTER_BYP1_10", - "CFG_CENTER_BYP1_11", - "CFG_CENTER_BYP1_12", - "CFG_CENTER_BYP1_13", - "CFG_CENTER_BYP1_14", - "CFG_CENTER_BYP1_15", - "CFG_CENTER_BYP1_16", - "CFG_CENTER_BYP1_17", - "CFG_CENTER_BYP1_18", - "CFG_CENTER_BYP1_19", - "CFG_CENTER_BYP1_2", - "CFG_CENTER_BYP1_3", - "CFG_CENTER_BYP1_4", - "CFG_CENTER_BYP1_5", - "CFG_CENTER_BYP1_6", - "CFG_CENTER_BYP1_7", - "CFG_CENTER_BYP1_8", - "CFG_CENTER_BYP1_9", - "CFG_CENTER_BYP2_0", - "CFG_CENTER_BYP2_1", - "CFG_CENTER_BYP2_10", - "CFG_CENTER_BYP2_11", - "CFG_CENTER_BYP2_12", - "CFG_CENTER_BYP2_13", - "CFG_CENTER_BYP2_14", - "CFG_CENTER_BYP2_15", - "CFG_CENTER_BYP2_16", - "CFG_CENTER_BYP2_17", - "CFG_CENTER_BYP2_18", - "CFG_CENTER_BYP2_19", - "CFG_CENTER_BYP2_2", - "CFG_CENTER_BYP2_3", - "CFG_CENTER_BYP2_4", - "CFG_CENTER_BYP2_5", - "CFG_CENTER_BYP2_6", - "CFG_CENTER_BYP2_7", - "CFG_CENTER_BYP2_8", - "CFG_CENTER_BYP2_9", - "CFG_CENTER_BYP3_0", - "CFG_CENTER_BYP3_1", - "CFG_CENTER_BYP3_10", - "CFG_CENTER_BYP3_11", - "CFG_CENTER_BYP3_12", - "CFG_CENTER_BYP3_13", - "CFG_CENTER_BYP3_14", - "CFG_CENTER_BYP3_15", - "CFG_CENTER_BYP3_16", - "CFG_CENTER_BYP3_17", - "CFG_CENTER_BYP3_18", - "CFG_CENTER_BYP3_19", - "CFG_CENTER_BYP3_2", - "CFG_CENTER_BYP3_3", - "CFG_CENTER_BYP3_4", - "CFG_CENTER_BYP3_5", - "CFG_CENTER_BYP3_6", - "CFG_CENTER_BYP3_7", - "CFG_CENTER_BYP3_8", - "CFG_CENTER_BYP3_9", - "CFG_CENTER_BYP4_0", - "CFG_CENTER_BYP4_1", - "CFG_CENTER_BYP4_10", - "CFG_CENTER_BYP4_11", - "CFG_CENTER_BYP4_12", - "CFG_CENTER_BYP4_13", - "CFG_CENTER_BYP4_14", - "CFG_CENTER_BYP4_15", - "CFG_CENTER_BYP4_16", - "CFG_CENTER_BYP4_17", - "CFG_CENTER_BYP4_18", - "CFG_CENTER_BYP4_19", - "CFG_CENTER_BYP4_2", - "CFG_CENTER_BYP4_3", - "CFG_CENTER_BYP4_4", - "CFG_CENTER_BYP4_5", - "CFG_CENTER_BYP4_6", - "CFG_CENTER_BYP4_7", - "CFG_CENTER_BYP4_8", - "CFG_CENTER_BYP4_9", - "CFG_CENTER_BYP5_0", - "CFG_CENTER_BYP5_1", - "CFG_CENTER_BYP5_10", - "CFG_CENTER_BYP5_11", - "CFG_CENTER_BYP5_12", - "CFG_CENTER_BYP5_13", - "CFG_CENTER_BYP5_14", - "CFG_CENTER_BYP5_15", - "CFG_CENTER_BYP5_16", - "CFG_CENTER_BYP5_17", - "CFG_CENTER_BYP5_18", - "CFG_CENTER_BYP5_19", - "CFG_CENTER_BYP5_2", - "CFG_CENTER_BYP5_3", - "CFG_CENTER_BYP5_4", - "CFG_CENTER_BYP5_5", - "CFG_CENTER_BYP5_6", - "CFG_CENTER_BYP5_7", - "CFG_CENTER_BYP5_8", - "CFG_CENTER_BYP5_9", - "CFG_CENTER_BYP6_0", - "CFG_CENTER_BYP6_1", - "CFG_CENTER_BYP6_10", - "CFG_CENTER_BYP6_11", - "CFG_CENTER_BYP6_12", - "CFG_CENTER_BYP6_13", - "CFG_CENTER_BYP6_14", - "CFG_CENTER_BYP6_15", - "CFG_CENTER_BYP6_16", - "CFG_CENTER_BYP6_17", - "CFG_CENTER_BYP6_18", - "CFG_CENTER_BYP6_19", - "CFG_CENTER_BYP6_2", - "CFG_CENTER_BYP6_3", - "CFG_CENTER_BYP6_4", - "CFG_CENTER_BYP6_5", - "CFG_CENTER_BYP6_6", - "CFG_CENTER_BYP6_7", - "CFG_CENTER_BYP6_8", - "CFG_CENTER_BYP6_9", - "CFG_CENTER_BYP7_0", - "CFG_CENTER_BYP7_1", - "CFG_CENTER_BYP7_10", - "CFG_CENTER_BYP7_11", - "CFG_CENTER_BYP7_12", - "CFG_CENTER_BYP7_13", - "CFG_CENTER_BYP7_14", - "CFG_CENTER_BYP7_15", - "CFG_CENTER_BYP7_16", - "CFG_CENTER_BYP7_17", - "CFG_CENTER_BYP7_18", - "CFG_CENTER_BYP7_19", - "CFG_CENTER_BYP7_2", - "CFG_CENTER_BYP7_3", - "CFG_CENTER_BYP7_4", - "CFG_CENTER_BYP7_5", - "CFG_CENTER_BYP7_6", - "CFG_CENTER_BYP7_7", - "CFG_CENTER_BYP7_8", - "CFG_CENTER_BYP7_9", - "CFG_CENTER_CAPTURE_CAP", - "CFG_CENTER_CAPTURE_CLK", - "CFG_CENTER_CFG_IO_ACCESS_CCLK", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA0", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA1", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA10", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA11", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA12", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA13", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA14", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA15", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA16", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA17", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA18", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA19", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA2", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA20", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA21", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA22", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA23", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA24", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA25", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA26", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA27", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA28", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA29", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA3", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA30", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA31", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA4", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA5", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA6", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA7", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA8", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA9", - "CFG_CENTER_CFG_IO_ACCESS_INITBI", - "CFG_CENTER_CFG_IO_ACCESS_INITBO", - "CFG_CENTER_CFG_IO_ACCESS_MASTER", - "CFG_CENTER_CFG_IO_ACCESS_MODE0", - "CFG_CENTER_CFG_IO_ACCESS_MODE1", - "CFG_CENTER_CFG_IO_ACCESS_MODE2", - "CFG_CENTER_CFG_IO_ACCESS_PUDCB", - "CFG_CENTER_CFG_IO_ACCESS_RDWRB", - "CFG_CENTER_CFG_IO_ACCESS_TDO", - "CFG_CENTER_CFG_IO_ACCESS_VGGCOMPOUT", - "CFG_CENTER_CK_BUFHCLK0", - "CFG_CENTER_CK_BUFHCLK1", - "CFG_CENTER_CK_BUFHCLK10", - "CFG_CENTER_CK_BUFHCLK11", - "CFG_CENTER_CK_BUFHCLK2", - "CFG_CENTER_CK_BUFHCLK3", - "CFG_CENTER_CK_BUFHCLK4", - "CFG_CENTER_CK_BUFHCLK5", - "CFG_CENTER_CK_BUFHCLK6", - "CFG_CENTER_CK_BUFHCLK7", - "CFG_CENTER_CK_BUFHCLK8", - "CFG_CENTER_CK_BUFHCLK9", - "CFG_CENTER_CK_BUFRCLK0", - "CFG_CENTER_CK_BUFRCLK1", - "CFG_CENTER_CK_BUFRCLK2", - "CFG_CENTER_CK_BUFRCLK3", - "CFG_CENTER_CK_IN0", - "CFG_CENTER_CK_IN1", - "CFG_CENTER_CK_IN10", - "CFG_CENTER_CK_IN11", - "CFG_CENTER_CK_IN12", - "CFG_CENTER_CK_IN13", - "CFG_CENTER_CK_IN2", - "CFG_CENTER_CK_IN3", - "CFG_CENTER_CK_IN4", - "CFG_CENTER_CK_IN5", - "CFG_CENTER_CK_IN6", - "CFG_CENTER_CK_IN7", - "CFG_CENTER_CK_IN8", - "CFG_CENTER_CK_IN9", - "CFG_CENTER_CLK0_0", - "CFG_CENTER_CLK0_1", - "CFG_CENTER_CLK0_10", - "CFG_CENTER_CLK0_11", - "CFG_CENTER_CLK0_12", - "CFG_CENTER_CLK0_13", - "CFG_CENTER_CLK0_14", - "CFG_CENTER_CLK0_15", - "CFG_CENTER_CLK0_16", - "CFG_CENTER_CLK0_17", - "CFG_CENTER_CLK0_18", - "CFG_CENTER_CLK0_19", - "CFG_CENTER_CLK0_2", - "CFG_CENTER_CLK0_3", - "CFG_CENTER_CLK0_4", - "CFG_CENTER_CLK0_5", - "CFG_CENTER_CLK0_6", - "CFG_CENTER_CLK0_7", - "CFG_CENTER_CLK0_8", - "CFG_CENTER_CLK0_9", - "CFG_CENTER_CLK1_0", - "CFG_CENTER_CLK1_1", - "CFG_CENTER_CLK1_10", - "CFG_CENTER_CLK1_11", - "CFG_CENTER_CLK1_12", - "CFG_CENTER_CLK1_13", - "CFG_CENTER_CLK1_14", - "CFG_CENTER_CLK1_15", - "CFG_CENTER_CLK1_16", - "CFG_CENTER_CLK1_17", - "CFG_CENTER_CLK1_18", - "CFG_CENTER_CLK1_19", - "CFG_CENTER_CLK1_2", - "CFG_CENTER_CLK1_3", - "CFG_CENTER_CLK1_4", - "CFG_CENTER_CLK1_5", - "CFG_CENTER_CLK1_6", - "CFG_CENTER_CLK1_7", - "CFG_CENTER_CLK1_8", - "CFG_CENTER_CLK1_9", - "CFG_CENTER_CTRL0_0", - "CFG_CENTER_CTRL0_1", - "CFG_CENTER_CTRL0_10", - "CFG_CENTER_CTRL0_11", - "CFG_CENTER_CTRL0_12", - "CFG_CENTER_CTRL0_13", - "CFG_CENTER_CTRL0_14", - "CFG_CENTER_CTRL0_15", - "CFG_CENTER_CTRL0_16", - "CFG_CENTER_CTRL0_17", - "CFG_CENTER_CTRL0_18", - "CFG_CENTER_CTRL0_19", - "CFG_CENTER_CTRL0_2", - "CFG_CENTER_CTRL0_3", - "CFG_CENTER_CTRL0_4", - "CFG_CENTER_CTRL0_5", - "CFG_CENTER_CTRL0_6", - "CFG_CENTER_CTRL0_7", - "CFG_CENTER_CTRL0_8", - "CFG_CENTER_CTRL0_9", - "CFG_CENTER_CTRL1_0", - "CFG_CENTER_CTRL1_1", - "CFG_CENTER_CTRL1_10", - "CFG_CENTER_CTRL1_11", - "CFG_CENTER_CTRL1_12", - "CFG_CENTER_CTRL1_13", - "CFG_CENTER_CTRL1_14", - "CFG_CENTER_CTRL1_15", - "CFG_CENTER_CTRL1_16", - "CFG_CENTER_CTRL1_17", - "CFG_CENTER_CTRL1_18", - "CFG_CENTER_CTRL1_19", - "CFG_CENTER_CTRL1_2", - "CFG_CENTER_CTRL1_3", - "CFG_CENTER_CTRL1_4", - "CFG_CENTER_CTRL1_5", - "CFG_CENTER_CTRL1_6", - "CFG_CENTER_CTRL1_7", - "CFG_CENTER_CTRL1_8", - "CFG_CENTER_CTRL1_9", - "CFG_CENTER_DCIRESET_LOCKED", - "CFG_CENTER_DCIRESET_RST", - "CFG_CENTER_EE2A0_0", - "CFG_CENTER_EE2A0_1", - "CFG_CENTER_EE2A0_10", - "CFG_CENTER_EE2A0_11", - "CFG_CENTER_EE2A0_12", - "CFG_CENTER_EE2A0_13", - "CFG_CENTER_EE2A0_14", - "CFG_CENTER_EE2A0_15", - "CFG_CENTER_EE2A0_16", - "CFG_CENTER_EE2A0_17", - "CFG_CENTER_EE2A0_18", - "CFG_CENTER_EE2A0_19", - "CFG_CENTER_EE2A0_2", - "CFG_CENTER_EE2A0_3", - "CFG_CENTER_EE2A0_4", - "CFG_CENTER_EE2A0_5", - "CFG_CENTER_EE2A0_6", - "CFG_CENTER_EE2A0_7", - "CFG_CENTER_EE2A0_8", - "CFG_CENTER_EE2A0_9", - "CFG_CENTER_EE2A1_0", - "CFG_CENTER_EE2A1_1", - "CFG_CENTER_EE2A1_10", - "CFG_CENTER_EE2A1_11", - "CFG_CENTER_EE2A1_12", - "CFG_CENTER_EE2A1_13", - "CFG_CENTER_EE2A1_14", - "CFG_CENTER_EE2A1_15", - "CFG_CENTER_EE2A1_16", - "CFG_CENTER_EE2A1_17", - "CFG_CENTER_EE2A1_18", - "CFG_CENTER_EE2A1_19", - "CFG_CENTER_EE2A1_2", - "CFG_CENTER_EE2A1_3", - "CFG_CENTER_EE2A1_4", - "CFG_CENTER_EE2A1_5", - "CFG_CENTER_EE2A1_6", - "CFG_CENTER_EE2A1_7", - "CFG_CENTER_EE2A1_8", - "CFG_CENTER_EE2A1_9", - "CFG_CENTER_EE2A2_0", - "CFG_CENTER_EE2A2_1", - "CFG_CENTER_EE2A2_10", - "CFG_CENTER_EE2A2_11", - "CFG_CENTER_EE2A2_12", - "CFG_CENTER_EE2A2_13", - "CFG_CENTER_EE2A2_14", - "CFG_CENTER_EE2A2_15", - "CFG_CENTER_EE2A2_16", - "CFG_CENTER_EE2A2_17", - "CFG_CENTER_EE2A2_18", - "CFG_CENTER_EE2A2_19", - "CFG_CENTER_EE2A2_2", - "CFG_CENTER_EE2A2_3", - "CFG_CENTER_EE2A2_4", - "CFG_CENTER_EE2A2_5", - "CFG_CENTER_EE2A2_6", - "CFG_CENTER_EE2A2_7", - "CFG_CENTER_EE2A2_8", - "CFG_CENTER_EE2A2_9", - "CFG_CENTER_EE2A3_0", - "CFG_CENTER_EE2A3_1", - "CFG_CENTER_EE2A3_10", - "CFG_CENTER_EE2A3_11", - "CFG_CENTER_EE2A3_12", - "CFG_CENTER_EE2A3_13", - "CFG_CENTER_EE2A3_14", - "CFG_CENTER_EE2A3_15", - "CFG_CENTER_EE2A3_16", - "CFG_CENTER_EE2A3_17", - "CFG_CENTER_EE2A3_18", - "CFG_CENTER_EE2A3_19", - "CFG_CENTER_EE2A3_2", - "CFG_CENTER_EE2A3_3", - "CFG_CENTER_EE2A3_4", - "CFG_CENTER_EE2A3_5", - "CFG_CENTER_EE2A3_6", - "CFG_CENTER_EE2A3_7", - "CFG_CENTER_EE2A3_8", - "CFG_CENTER_EE2A3_9", - "CFG_CENTER_EE2BEG0_0", - "CFG_CENTER_EE2BEG0_1", - "CFG_CENTER_EE2BEG0_10", - "CFG_CENTER_EE2BEG0_11", - "CFG_CENTER_EE2BEG0_12", - "CFG_CENTER_EE2BEG0_13", - "CFG_CENTER_EE2BEG0_14", - "CFG_CENTER_EE2BEG0_15", - "CFG_CENTER_EE2BEG0_16", - "CFG_CENTER_EE2BEG0_17", - "CFG_CENTER_EE2BEG0_18", - "CFG_CENTER_EE2BEG0_19", - "CFG_CENTER_EE2BEG0_2", - "CFG_CENTER_EE2BEG0_3", - "CFG_CENTER_EE2BEG0_4", - "CFG_CENTER_EE2BEG0_5", - "CFG_CENTER_EE2BEG0_6", - "CFG_CENTER_EE2BEG0_7", - "CFG_CENTER_EE2BEG0_8", - "CFG_CENTER_EE2BEG0_9", - "CFG_CENTER_EE2BEG1_0", - "CFG_CENTER_EE2BEG1_1", - "CFG_CENTER_EE2BEG1_10", - "CFG_CENTER_EE2BEG1_11", - "CFG_CENTER_EE2BEG1_12", - "CFG_CENTER_EE2BEG1_13", - "CFG_CENTER_EE2BEG1_14", - "CFG_CENTER_EE2BEG1_15", - "CFG_CENTER_EE2BEG1_16", - "CFG_CENTER_EE2BEG1_17", - "CFG_CENTER_EE2BEG1_18", - "CFG_CENTER_EE2BEG1_19", - "CFG_CENTER_EE2BEG1_2", - "CFG_CENTER_EE2BEG1_3", - "CFG_CENTER_EE2BEG1_4", - "CFG_CENTER_EE2BEG1_5", - "CFG_CENTER_EE2BEG1_6", - "CFG_CENTER_EE2BEG1_7", - "CFG_CENTER_EE2BEG1_8", - "CFG_CENTER_EE2BEG1_9", - "CFG_CENTER_EE2BEG2_0", - "CFG_CENTER_EE2BEG2_1", - "CFG_CENTER_EE2BEG2_10", - "CFG_CENTER_EE2BEG2_11", - "CFG_CENTER_EE2BEG2_12", - "CFG_CENTER_EE2BEG2_13", - "CFG_CENTER_EE2BEG2_14", - "CFG_CENTER_EE2BEG2_15", - "CFG_CENTER_EE2BEG2_16", - "CFG_CENTER_EE2BEG2_17", - "CFG_CENTER_EE2BEG2_18", - "CFG_CENTER_EE2BEG2_19", - "CFG_CENTER_EE2BEG2_2", - "CFG_CENTER_EE2BEG2_3", - "CFG_CENTER_EE2BEG2_4", - "CFG_CENTER_EE2BEG2_5", - "CFG_CENTER_EE2BEG2_6", - "CFG_CENTER_EE2BEG2_7", - "CFG_CENTER_EE2BEG2_8", - "CFG_CENTER_EE2BEG2_9", - "CFG_CENTER_EE2BEG3_0", - "CFG_CENTER_EE2BEG3_1", - "CFG_CENTER_EE2BEG3_10", - "CFG_CENTER_EE2BEG3_11", - "CFG_CENTER_EE2BEG3_12", - "CFG_CENTER_EE2BEG3_13", - "CFG_CENTER_EE2BEG3_14", - "CFG_CENTER_EE2BEG3_15", - "CFG_CENTER_EE2BEG3_16", - "CFG_CENTER_EE2BEG3_17", - "CFG_CENTER_EE2BEG3_18", - "CFG_CENTER_EE2BEG3_19", - "CFG_CENTER_EE2BEG3_2", - "CFG_CENTER_EE2BEG3_3", - "CFG_CENTER_EE2BEG3_4", - "CFG_CENTER_EE2BEG3_5", - "CFG_CENTER_EE2BEG3_6", - "CFG_CENTER_EE2BEG3_7", - "CFG_CENTER_EE2BEG3_8", - "CFG_CENTER_EE2BEG3_9", - "CFG_CENTER_EE4A0_0", - "CFG_CENTER_EE4A0_1", - "CFG_CENTER_EE4A0_10", - "CFG_CENTER_EE4A0_11", - "CFG_CENTER_EE4A0_12", - "CFG_CENTER_EE4A0_13", - "CFG_CENTER_EE4A0_14", - "CFG_CENTER_EE4A0_15", - "CFG_CENTER_EE4A0_16", - "CFG_CENTER_EE4A0_17", - "CFG_CENTER_EE4A0_18", - "CFG_CENTER_EE4A0_19", - "CFG_CENTER_EE4A0_2", - "CFG_CENTER_EE4A0_3", - "CFG_CENTER_EE4A0_4", - "CFG_CENTER_EE4A0_5", - "CFG_CENTER_EE4A0_6", - "CFG_CENTER_EE4A0_7", - "CFG_CENTER_EE4A0_8", - "CFG_CENTER_EE4A0_9", - "CFG_CENTER_EE4A1_0", - "CFG_CENTER_EE4A1_1", - "CFG_CENTER_EE4A1_10", - "CFG_CENTER_EE4A1_11", - "CFG_CENTER_EE4A1_12", - "CFG_CENTER_EE4A1_13", - "CFG_CENTER_EE4A1_14", - "CFG_CENTER_EE4A1_15", - "CFG_CENTER_EE4A1_16", - "CFG_CENTER_EE4A1_17", - "CFG_CENTER_EE4A1_18", - "CFG_CENTER_EE4A1_19", - "CFG_CENTER_EE4A1_2", - "CFG_CENTER_EE4A1_3", - "CFG_CENTER_EE4A1_4", - "CFG_CENTER_EE4A1_5", - "CFG_CENTER_EE4A1_6", - "CFG_CENTER_EE4A1_7", - "CFG_CENTER_EE4A1_8", - "CFG_CENTER_EE4A1_9", - "CFG_CENTER_EE4A2_0", - "CFG_CENTER_EE4A2_1", - "CFG_CENTER_EE4A2_10", - "CFG_CENTER_EE4A2_11", - "CFG_CENTER_EE4A2_12", - "CFG_CENTER_EE4A2_13", - "CFG_CENTER_EE4A2_14", - "CFG_CENTER_EE4A2_15", - "CFG_CENTER_EE4A2_16", - "CFG_CENTER_EE4A2_17", - "CFG_CENTER_EE4A2_18", - "CFG_CENTER_EE4A2_19", - "CFG_CENTER_EE4A2_2", - "CFG_CENTER_EE4A2_3", - "CFG_CENTER_EE4A2_4", - "CFG_CENTER_EE4A2_5", - "CFG_CENTER_EE4A2_6", - "CFG_CENTER_EE4A2_7", - "CFG_CENTER_EE4A2_8", - "CFG_CENTER_EE4A2_9", - "CFG_CENTER_EE4A3_0", - "CFG_CENTER_EE4A3_1", - "CFG_CENTER_EE4A3_10", - "CFG_CENTER_EE4A3_11", - "CFG_CENTER_EE4A3_12", - "CFG_CENTER_EE4A3_13", - "CFG_CENTER_EE4A3_14", - "CFG_CENTER_EE4A3_15", - "CFG_CENTER_EE4A3_16", - "CFG_CENTER_EE4A3_17", - "CFG_CENTER_EE4A3_18", - "CFG_CENTER_EE4A3_19", - "CFG_CENTER_EE4A3_2", - "CFG_CENTER_EE4A3_3", - "CFG_CENTER_EE4A3_4", - "CFG_CENTER_EE4A3_5", - "CFG_CENTER_EE4A3_6", - "CFG_CENTER_EE4A3_7", - "CFG_CENTER_EE4A3_8", - "CFG_CENTER_EE4A3_9", - "CFG_CENTER_EE4B0_0", - "CFG_CENTER_EE4B0_1", - "CFG_CENTER_EE4B0_10", - "CFG_CENTER_EE4B0_11", - "CFG_CENTER_EE4B0_12", - "CFG_CENTER_EE4B0_13", - "CFG_CENTER_EE4B0_14", - "CFG_CENTER_EE4B0_15", - "CFG_CENTER_EE4B0_16", - "CFG_CENTER_EE4B0_17", - "CFG_CENTER_EE4B0_18", - "CFG_CENTER_EE4B0_19", - "CFG_CENTER_EE4B0_2", - "CFG_CENTER_EE4B0_3", - "CFG_CENTER_EE4B0_4", - "CFG_CENTER_EE4B0_5", - "CFG_CENTER_EE4B0_6", - "CFG_CENTER_EE4B0_7", - "CFG_CENTER_EE4B0_8", - "CFG_CENTER_EE4B0_9", - "CFG_CENTER_EE4B1_0", - "CFG_CENTER_EE4B1_1", - "CFG_CENTER_EE4B1_10", - "CFG_CENTER_EE4B1_11", - "CFG_CENTER_EE4B1_12", - "CFG_CENTER_EE4B1_13", - "CFG_CENTER_EE4B1_14", - "CFG_CENTER_EE4B1_15", - "CFG_CENTER_EE4B1_16", - "CFG_CENTER_EE4B1_17", - "CFG_CENTER_EE4B1_18", - "CFG_CENTER_EE4B1_19", - "CFG_CENTER_EE4B1_2", - "CFG_CENTER_EE4B1_3", - "CFG_CENTER_EE4B1_4", - "CFG_CENTER_EE4B1_5", - "CFG_CENTER_EE4B1_6", - "CFG_CENTER_EE4B1_7", - "CFG_CENTER_EE4B1_8", - "CFG_CENTER_EE4B1_9", - "CFG_CENTER_EE4B2_0", - "CFG_CENTER_EE4B2_1", - "CFG_CENTER_EE4B2_10", - "CFG_CENTER_EE4B2_11", - "CFG_CENTER_EE4B2_12", - "CFG_CENTER_EE4B2_13", - "CFG_CENTER_EE4B2_14", - "CFG_CENTER_EE4B2_15", - "CFG_CENTER_EE4B2_16", - "CFG_CENTER_EE4B2_17", - "CFG_CENTER_EE4B2_18", - "CFG_CENTER_EE4B2_19", - "CFG_CENTER_EE4B2_2", - "CFG_CENTER_EE4B2_3", - "CFG_CENTER_EE4B2_4", - "CFG_CENTER_EE4B2_5", - "CFG_CENTER_EE4B2_6", - "CFG_CENTER_EE4B2_7", - "CFG_CENTER_EE4B2_8", - "CFG_CENTER_EE4B2_9", - "CFG_CENTER_EE4B3_0", - "CFG_CENTER_EE4B3_1", - "CFG_CENTER_EE4B3_10", - "CFG_CENTER_EE4B3_11", - "CFG_CENTER_EE4B3_12", - "CFG_CENTER_EE4B3_13", - "CFG_CENTER_EE4B3_14", - "CFG_CENTER_EE4B3_15", - "CFG_CENTER_EE4B3_16", - "CFG_CENTER_EE4B3_17", - "CFG_CENTER_EE4B3_18", - "CFG_CENTER_EE4B3_19", - "CFG_CENTER_EE4B3_2", - "CFG_CENTER_EE4B3_3", - "CFG_CENTER_EE4B3_4", - "CFG_CENTER_EE4B3_5", - "CFG_CENTER_EE4B3_6", - "CFG_CENTER_EE4B3_7", - "CFG_CENTER_EE4B3_8", - "CFG_CENTER_EE4B3_9", - "CFG_CENTER_EE4BEG0_0", - "CFG_CENTER_EE4BEG0_1", - "CFG_CENTER_EE4BEG0_10", - "CFG_CENTER_EE4BEG0_11", - "CFG_CENTER_EE4BEG0_12", - "CFG_CENTER_EE4BEG0_13", - "CFG_CENTER_EE4BEG0_14", - "CFG_CENTER_EE4BEG0_15", - "CFG_CENTER_EE4BEG0_16", - "CFG_CENTER_EE4BEG0_17", - "CFG_CENTER_EE4BEG0_18", - "CFG_CENTER_EE4BEG0_19", - "CFG_CENTER_EE4BEG0_2", - "CFG_CENTER_EE4BEG0_3", - "CFG_CENTER_EE4BEG0_4", - "CFG_CENTER_EE4BEG0_5", - "CFG_CENTER_EE4BEG0_6", - "CFG_CENTER_EE4BEG0_7", - "CFG_CENTER_EE4BEG0_8", - "CFG_CENTER_EE4BEG0_9", - "CFG_CENTER_EE4BEG1_0", - "CFG_CENTER_EE4BEG1_1", - "CFG_CENTER_EE4BEG1_10", - "CFG_CENTER_EE4BEG1_11", - "CFG_CENTER_EE4BEG1_12", - "CFG_CENTER_EE4BEG1_13", - "CFG_CENTER_EE4BEG1_14", - "CFG_CENTER_EE4BEG1_15", - "CFG_CENTER_EE4BEG1_16", - "CFG_CENTER_EE4BEG1_17", - "CFG_CENTER_EE4BEG1_18", - "CFG_CENTER_EE4BEG1_19", - "CFG_CENTER_EE4BEG1_2", - "CFG_CENTER_EE4BEG1_3", - "CFG_CENTER_EE4BEG1_4", - "CFG_CENTER_EE4BEG1_5", - "CFG_CENTER_EE4BEG1_6", - "CFG_CENTER_EE4BEG1_7", - "CFG_CENTER_EE4BEG1_8", - "CFG_CENTER_EE4BEG1_9", - "CFG_CENTER_EE4BEG2_0", - "CFG_CENTER_EE4BEG2_1", - "CFG_CENTER_EE4BEG2_10", - "CFG_CENTER_EE4BEG2_11", - "CFG_CENTER_EE4BEG2_12", - "CFG_CENTER_EE4BEG2_13", - "CFG_CENTER_EE4BEG2_14", - "CFG_CENTER_EE4BEG2_15", - "CFG_CENTER_EE4BEG2_16", - "CFG_CENTER_EE4BEG2_17", - "CFG_CENTER_EE4BEG2_18", - "CFG_CENTER_EE4BEG2_19", - "CFG_CENTER_EE4BEG2_2", - "CFG_CENTER_EE4BEG2_3", - "CFG_CENTER_EE4BEG2_4", - "CFG_CENTER_EE4BEG2_5", - "CFG_CENTER_EE4BEG2_6", - "CFG_CENTER_EE4BEG2_7", - "CFG_CENTER_EE4BEG2_8", - "CFG_CENTER_EE4BEG2_9", - "CFG_CENTER_EE4BEG3_0", - "CFG_CENTER_EE4BEG3_1", - "CFG_CENTER_EE4BEG3_10", - "CFG_CENTER_EE4BEG3_11", - "CFG_CENTER_EE4BEG3_12", - "CFG_CENTER_EE4BEG3_13", - "CFG_CENTER_EE4BEG3_14", - "CFG_CENTER_EE4BEG3_15", - "CFG_CENTER_EE4BEG3_16", - "CFG_CENTER_EE4BEG3_17", - "CFG_CENTER_EE4BEG3_18", - "CFG_CENTER_EE4BEG3_19", - "CFG_CENTER_EE4BEG3_2", - "CFG_CENTER_EE4BEG3_3", - "CFG_CENTER_EE4BEG3_4", - "CFG_CENTER_EE4BEG3_5", - "CFG_CENTER_EE4BEG3_6", - "CFG_CENTER_EE4BEG3_7", - "CFG_CENTER_EE4BEG3_8", - "CFG_CENTER_EE4BEG3_9", - "CFG_CENTER_EE4C0_0", - "CFG_CENTER_EE4C0_1", - "CFG_CENTER_EE4C0_10", - "CFG_CENTER_EE4C0_11", - "CFG_CENTER_EE4C0_12", - "CFG_CENTER_EE4C0_13", - "CFG_CENTER_EE4C0_14", - "CFG_CENTER_EE4C0_15", - "CFG_CENTER_EE4C0_16", - "CFG_CENTER_EE4C0_17", - "CFG_CENTER_EE4C0_18", - "CFG_CENTER_EE4C0_19", - "CFG_CENTER_EE4C0_2", - "CFG_CENTER_EE4C0_3", - "CFG_CENTER_EE4C0_4", - "CFG_CENTER_EE4C0_5", - "CFG_CENTER_EE4C0_6", - "CFG_CENTER_EE4C0_7", - "CFG_CENTER_EE4C0_8", - "CFG_CENTER_EE4C0_9", - "CFG_CENTER_EE4C1_0", - "CFG_CENTER_EE4C1_1", - "CFG_CENTER_EE4C1_10", - "CFG_CENTER_EE4C1_11", - "CFG_CENTER_EE4C1_12", - "CFG_CENTER_EE4C1_13", - "CFG_CENTER_EE4C1_14", - "CFG_CENTER_EE4C1_15", - "CFG_CENTER_EE4C1_16", - "CFG_CENTER_EE4C1_17", - "CFG_CENTER_EE4C1_18", - "CFG_CENTER_EE4C1_19", - "CFG_CENTER_EE4C1_2", - "CFG_CENTER_EE4C1_3", - "CFG_CENTER_EE4C1_4", - "CFG_CENTER_EE4C1_5", - "CFG_CENTER_EE4C1_6", - "CFG_CENTER_EE4C1_7", - "CFG_CENTER_EE4C1_8", - "CFG_CENTER_EE4C1_9", - "CFG_CENTER_EE4C2_0", - "CFG_CENTER_EE4C2_1", - "CFG_CENTER_EE4C2_10", - "CFG_CENTER_EE4C2_11", - "CFG_CENTER_EE4C2_12", - "CFG_CENTER_EE4C2_13", - "CFG_CENTER_EE4C2_14", - "CFG_CENTER_EE4C2_15", - "CFG_CENTER_EE4C2_16", - "CFG_CENTER_EE4C2_17", - "CFG_CENTER_EE4C2_18", - "CFG_CENTER_EE4C2_19", - "CFG_CENTER_EE4C2_2", - "CFG_CENTER_EE4C2_3", - "CFG_CENTER_EE4C2_4", - "CFG_CENTER_EE4C2_5", - "CFG_CENTER_EE4C2_6", - "CFG_CENTER_EE4C2_7", - "CFG_CENTER_EE4C2_8", - "CFG_CENTER_EE4C2_9", - "CFG_CENTER_EE4C3_0", - "CFG_CENTER_EE4C3_1", - "CFG_CENTER_EE4C3_10", - "CFG_CENTER_EE4C3_11", - "CFG_CENTER_EE4C3_12", - "CFG_CENTER_EE4C3_13", - "CFG_CENTER_EE4C3_14", - "CFG_CENTER_EE4C3_15", - "CFG_CENTER_EE4C3_16", - "CFG_CENTER_EE4C3_17", - "CFG_CENTER_EE4C3_18", - "CFG_CENTER_EE4C3_19", - "CFG_CENTER_EE4C3_2", - "CFG_CENTER_EE4C3_3", - "CFG_CENTER_EE4C3_4", - "CFG_CENTER_EE4C3_5", - "CFG_CENTER_EE4C3_6", - "CFG_CENTER_EE4C3_7", - "CFG_CENTER_EE4C3_8", - "CFG_CENTER_EE4C3_9", - "CFG_CENTER_EL1BEG0_0", - "CFG_CENTER_EL1BEG0_1", - "CFG_CENTER_EL1BEG0_10", - "CFG_CENTER_EL1BEG0_11", - "CFG_CENTER_EL1BEG0_12", - "CFG_CENTER_EL1BEG0_13", - "CFG_CENTER_EL1BEG0_14", - "CFG_CENTER_EL1BEG0_15", - "CFG_CENTER_EL1BEG0_16", - "CFG_CENTER_EL1BEG0_17", - "CFG_CENTER_EL1BEG0_18", - "CFG_CENTER_EL1BEG0_19", - "CFG_CENTER_EL1BEG0_2", - "CFG_CENTER_EL1BEG0_3", - "CFG_CENTER_EL1BEG0_4", - "CFG_CENTER_EL1BEG0_5", - "CFG_CENTER_EL1BEG0_6", - "CFG_CENTER_EL1BEG0_7", - "CFG_CENTER_EL1BEG0_8", - "CFG_CENTER_EL1BEG0_9", - "CFG_CENTER_EL1BEG1_0", - "CFG_CENTER_EL1BEG1_1", - "CFG_CENTER_EL1BEG1_10", - "CFG_CENTER_EL1BEG1_11", - "CFG_CENTER_EL1BEG1_12", - "CFG_CENTER_EL1BEG1_13", - "CFG_CENTER_EL1BEG1_14", - "CFG_CENTER_EL1BEG1_15", - "CFG_CENTER_EL1BEG1_16", - "CFG_CENTER_EL1BEG1_17", - "CFG_CENTER_EL1BEG1_18", - "CFG_CENTER_EL1BEG1_19", - "CFG_CENTER_EL1BEG1_2", - "CFG_CENTER_EL1BEG1_3", - "CFG_CENTER_EL1BEG1_4", - "CFG_CENTER_EL1BEG1_5", - "CFG_CENTER_EL1BEG1_6", - "CFG_CENTER_EL1BEG1_7", - "CFG_CENTER_EL1BEG1_8", - "CFG_CENTER_EL1BEG1_9", - "CFG_CENTER_EL1BEG2_0", - "CFG_CENTER_EL1BEG2_1", - "CFG_CENTER_EL1BEG2_10", - "CFG_CENTER_EL1BEG2_11", - "CFG_CENTER_EL1BEG2_12", - "CFG_CENTER_EL1BEG2_13", - "CFG_CENTER_EL1BEG2_14", - "CFG_CENTER_EL1BEG2_15", - "CFG_CENTER_EL1BEG2_16", - "CFG_CENTER_EL1BEG2_17", - "CFG_CENTER_EL1BEG2_18", - "CFG_CENTER_EL1BEG2_19", - "CFG_CENTER_EL1BEG2_2", - "CFG_CENTER_EL1BEG2_3", - "CFG_CENTER_EL1BEG2_4", - "CFG_CENTER_EL1BEG2_5", - "CFG_CENTER_EL1BEG2_6", - "CFG_CENTER_EL1BEG2_7", - "CFG_CENTER_EL1BEG2_8", - "CFG_CENTER_EL1BEG2_9", - "CFG_CENTER_EL1BEG3_0", - "CFG_CENTER_EL1BEG3_1", - "CFG_CENTER_EL1BEG3_10", - "CFG_CENTER_EL1BEG3_11", - "CFG_CENTER_EL1BEG3_12", - "CFG_CENTER_EL1BEG3_13", - "CFG_CENTER_EL1BEG3_14", - "CFG_CENTER_EL1BEG3_15", - "CFG_CENTER_EL1BEG3_16", - "CFG_CENTER_EL1BEG3_17", - "CFG_CENTER_EL1BEG3_18", - "CFG_CENTER_EL1BEG3_19", - "CFG_CENTER_EL1BEG3_2", - "CFG_CENTER_EL1BEG3_3", - "CFG_CENTER_EL1BEG3_4", - "CFG_CENTER_EL1BEG3_5", - "CFG_CENTER_EL1BEG3_6", - "CFG_CENTER_EL1BEG3_7", - "CFG_CENTER_EL1BEG3_8", - "CFG_CENTER_EL1BEG3_9", - "CFG_CENTER_ER1BEG0_0", - "CFG_CENTER_ER1BEG0_1", - "CFG_CENTER_ER1BEG0_10", - "CFG_CENTER_ER1BEG0_11", - "CFG_CENTER_ER1BEG0_12", - "CFG_CENTER_ER1BEG0_13", - "CFG_CENTER_ER1BEG0_14", - "CFG_CENTER_ER1BEG0_15", - "CFG_CENTER_ER1BEG0_16", - "CFG_CENTER_ER1BEG0_17", - "CFG_CENTER_ER1BEG0_18", - "CFG_CENTER_ER1BEG0_19", - "CFG_CENTER_ER1BEG0_2", - "CFG_CENTER_ER1BEG0_3", - "CFG_CENTER_ER1BEG0_4", - "CFG_CENTER_ER1BEG0_5", - "CFG_CENTER_ER1BEG0_6", - "CFG_CENTER_ER1BEG0_7", - "CFG_CENTER_ER1BEG0_8", - "CFG_CENTER_ER1BEG0_9", - "CFG_CENTER_ER1BEG1_0", - "CFG_CENTER_ER1BEG1_1", - "CFG_CENTER_ER1BEG1_10", - "CFG_CENTER_ER1BEG1_11", - "CFG_CENTER_ER1BEG1_12", - "CFG_CENTER_ER1BEG1_13", - "CFG_CENTER_ER1BEG1_14", - "CFG_CENTER_ER1BEG1_15", - "CFG_CENTER_ER1BEG1_16", - "CFG_CENTER_ER1BEG1_17", - "CFG_CENTER_ER1BEG1_18", - "CFG_CENTER_ER1BEG1_19", - "CFG_CENTER_ER1BEG1_2", - "CFG_CENTER_ER1BEG1_3", - "CFG_CENTER_ER1BEG1_4", - "CFG_CENTER_ER1BEG1_5", - "CFG_CENTER_ER1BEG1_6", - "CFG_CENTER_ER1BEG1_7", - "CFG_CENTER_ER1BEG1_8", - "CFG_CENTER_ER1BEG1_9", - "CFG_CENTER_ER1BEG2_0", - "CFG_CENTER_ER1BEG2_1", - "CFG_CENTER_ER1BEG2_10", - "CFG_CENTER_ER1BEG2_11", - "CFG_CENTER_ER1BEG2_12", - "CFG_CENTER_ER1BEG2_13", - "CFG_CENTER_ER1BEG2_14", - "CFG_CENTER_ER1BEG2_15", - "CFG_CENTER_ER1BEG2_16", - "CFG_CENTER_ER1BEG2_17", - "CFG_CENTER_ER1BEG2_18", - "CFG_CENTER_ER1BEG2_19", - "CFG_CENTER_ER1BEG2_2", - "CFG_CENTER_ER1BEG2_3", - "CFG_CENTER_ER1BEG2_4", - "CFG_CENTER_ER1BEG2_5", - "CFG_CENTER_ER1BEG2_6", - "CFG_CENTER_ER1BEG2_7", - "CFG_CENTER_ER1BEG2_8", - "CFG_CENTER_ER1BEG2_9", - "CFG_CENTER_ER1BEG3_0", - "CFG_CENTER_ER1BEG3_1", - "CFG_CENTER_ER1BEG3_10", - "CFG_CENTER_ER1BEG3_11", - "CFG_CENTER_ER1BEG3_12", - "CFG_CENTER_ER1BEG3_13", - "CFG_CENTER_ER1BEG3_14", - "CFG_CENTER_ER1BEG3_15", - "CFG_CENTER_ER1BEG3_16", - "CFG_CENTER_ER1BEG3_17", - "CFG_CENTER_ER1BEG3_18", - "CFG_CENTER_ER1BEG3_19", - "CFG_CENTER_ER1BEG3_2", - "CFG_CENTER_ER1BEG3_3", - "CFG_CENTER_ER1BEG3_4", - "CFG_CENTER_ER1BEG3_5", - "CFG_CENTER_ER1BEG3_6", - "CFG_CENTER_ER1BEG3_7", - "CFG_CENTER_ER1BEG3_8", - "CFG_CENTER_ER1BEG3_9", - "CFG_CENTER_FAN0_0", - "CFG_CENTER_FAN0_1", - "CFG_CENTER_FAN0_10", - "CFG_CENTER_FAN0_11", - "CFG_CENTER_FAN0_12", - "CFG_CENTER_FAN0_13", - "CFG_CENTER_FAN0_14", - "CFG_CENTER_FAN0_15", - "CFG_CENTER_FAN0_16", - "CFG_CENTER_FAN0_17", - "CFG_CENTER_FAN0_18", - "CFG_CENTER_FAN0_19", - "CFG_CENTER_FAN0_2", - "CFG_CENTER_FAN0_3", - "CFG_CENTER_FAN0_4", - "CFG_CENTER_FAN0_5", - "CFG_CENTER_FAN0_6", - "CFG_CENTER_FAN0_7", - "CFG_CENTER_FAN0_8", - "CFG_CENTER_FAN0_9", - "CFG_CENTER_FAN1_0", - "CFG_CENTER_FAN1_1", - "CFG_CENTER_FAN1_10", - "CFG_CENTER_FAN1_11", - "CFG_CENTER_FAN1_12", - "CFG_CENTER_FAN1_13", - "CFG_CENTER_FAN1_14", - "CFG_CENTER_FAN1_15", - "CFG_CENTER_FAN1_16", - "CFG_CENTER_FAN1_17", - "CFG_CENTER_FAN1_18", - "CFG_CENTER_FAN1_19", - "CFG_CENTER_FAN1_2", - "CFG_CENTER_FAN1_3", - "CFG_CENTER_FAN1_4", - "CFG_CENTER_FAN1_5", - "CFG_CENTER_FAN1_6", - "CFG_CENTER_FAN1_7", - "CFG_CENTER_FAN1_8", - "CFG_CENTER_FAN1_9", - "CFG_CENTER_FAN2_0", - "CFG_CENTER_FAN2_1", - "CFG_CENTER_FAN2_10", - "CFG_CENTER_FAN2_11", - "CFG_CENTER_FAN2_12", - "CFG_CENTER_FAN2_13", - "CFG_CENTER_FAN2_14", - "CFG_CENTER_FAN2_15", - "CFG_CENTER_FAN2_16", - "CFG_CENTER_FAN2_17", - "CFG_CENTER_FAN2_18", - "CFG_CENTER_FAN2_19", - "CFG_CENTER_FAN2_2", - "CFG_CENTER_FAN2_3", - "CFG_CENTER_FAN2_4", - "CFG_CENTER_FAN2_5", - "CFG_CENTER_FAN2_6", - "CFG_CENTER_FAN2_7", - "CFG_CENTER_FAN2_8", - "CFG_CENTER_FAN2_9", - "CFG_CENTER_FAN3_0", - "CFG_CENTER_FAN3_1", - "CFG_CENTER_FAN3_10", - "CFG_CENTER_FAN3_11", - "CFG_CENTER_FAN3_12", - "CFG_CENTER_FAN3_13", - "CFG_CENTER_FAN3_14", - "CFG_CENTER_FAN3_15", - "CFG_CENTER_FAN3_16", - "CFG_CENTER_FAN3_17", - "CFG_CENTER_FAN3_18", - "CFG_CENTER_FAN3_19", - "CFG_CENTER_FAN3_2", - "CFG_CENTER_FAN3_3", - "CFG_CENTER_FAN3_4", - "CFG_CENTER_FAN3_5", - "CFG_CENTER_FAN3_6", - "CFG_CENTER_FAN3_7", - "CFG_CENTER_FAN3_8", - "CFG_CENTER_FAN3_9", - "CFG_CENTER_FAN4_0", - "CFG_CENTER_FAN4_1", - "CFG_CENTER_FAN4_10", - "CFG_CENTER_FAN4_11", - "CFG_CENTER_FAN4_12", - "CFG_CENTER_FAN4_13", - "CFG_CENTER_FAN4_14", - "CFG_CENTER_FAN4_15", - "CFG_CENTER_FAN4_16", - "CFG_CENTER_FAN4_17", - "CFG_CENTER_FAN4_18", - "CFG_CENTER_FAN4_19", - "CFG_CENTER_FAN4_2", - "CFG_CENTER_FAN4_3", - "CFG_CENTER_FAN4_4", - "CFG_CENTER_FAN4_5", - "CFG_CENTER_FAN4_6", - "CFG_CENTER_FAN4_7", - "CFG_CENTER_FAN4_8", - "CFG_CENTER_FAN4_9", - "CFG_CENTER_FAN5_0", - "CFG_CENTER_FAN5_1", - "CFG_CENTER_FAN5_10", - "CFG_CENTER_FAN5_11", - "CFG_CENTER_FAN5_12", - "CFG_CENTER_FAN5_13", - "CFG_CENTER_FAN5_14", - "CFG_CENTER_FAN5_15", - "CFG_CENTER_FAN5_16", - "CFG_CENTER_FAN5_17", - "CFG_CENTER_FAN5_18", - "CFG_CENTER_FAN5_19", - "CFG_CENTER_FAN5_2", - "CFG_CENTER_FAN5_3", - "CFG_CENTER_FAN5_4", - "CFG_CENTER_FAN5_5", - "CFG_CENTER_FAN5_6", - "CFG_CENTER_FAN5_7", - "CFG_CENTER_FAN5_8", - "CFG_CENTER_FAN5_9", - "CFG_CENTER_FAN6_0", - "CFG_CENTER_FAN6_1", - "CFG_CENTER_FAN6_10", - "CFG_CENTER_FAN6_11", - "CFG_CENTER_FAN6_12", - "CFG_CENTER_FAN6_13", - "CFG_CENTER_FAN6_14", - "CFG_CENTER_FAN6_15", - "CFG_CENTER_FAN6_16", - "CFG_CENTER_FAN6_17", - "CFG_CENTER_FAN6_18", - "CFG_CENTER_FAN6_19", - "CFG_CENTER_FAN6_2", - "CFG_CENTER_FAN6_3", - "CFG_CENTER_FAN6_4", - "CFG_CENTER_FAN6_5", - "CFG_CENTER_FAN6_6", - "CFG_CENTER_FAN6_7", - "CFG_CENTER_FAN6_8", - "CFG_CENTER_FAN6_9", - "CFG_CENTER_FAN7_0", - "CFG_CENTER_FAN7_1", - "CFG_CENTER_FAN7_10", - "CFG_CENTER_FAN7_11", - "CFG_CENTER_FAN7_12", - "CFG_CENTER_FAN7_13", - "CFG_CENTER_FAN7_14", - "CFG_CENTER_FAN7_15", - "CFG_CENTER_FAN7_16", - "CFG_CENTER_FAN7_17", - "CFG_CENTER_FAN7_18", - "CFG_CENTER_FAN7_19", - "CFG_CENTER_FAN7_2", - "CFG_CENTER_FAN7_3", - "CFG_CENTER_FAN7_4", - "CFG_CENTER_FAN7_5", - "CFG_CENTER_FAN7_6", - "CFG_CENTER_FAN7_7", - "CFG_CENTER_FAN7_8", - "CFG_CENTER_FAN7_9", - "CFG_CENTER_FRAME_ECC_CRCERROR", - "CFG_CENTER_FRAME_ECC_ECCERROR", - "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE", - "CFG_CENTER_FRAME_ECC_FAR0", - "CFG_CENTER_FRAME_ECC_FAR1", - "CFG_CENTER_FRAME_ECC_FAR10", - "CFG_CENTER_FRAME_ECC_FAR11", - "CFG_CENTER_FRAME_ECC_FAR12", - "CFG_CENTER_FRAME_ECC_FAR13", - "CFG_CENTER_FRAME_ECC_FAR14", - "CFG_CENTER_FRAME_ECC_FAR15", - "CFG_CENTER_FRAME_ECC_FAR16", - "CFG_CENTER_FRAME_ECC_FAR17", - "CFG_CENTER_FRAME_ECC_FAR18", - "CFG_CENTER_FRAME_ECC_FAR19", - "CFG_CENTER_FRAME_ECC_FAR2", - "CFG_CENTER_FRAME_ECC_FAR20", - "CFG_CENTER_FRAME_ECC_FAR21", - "CFG_CENTER_FRAME_ECC_FAR22", - "CFG_CENTER_FRAME_ECC_FAR23", - "CFG_CENTER_FRAME_ECC_FAR24", - "CFG_CENTER_FRAME_ECC_FAR25", - "CFG_CENTER_FRAME_ECC_FAR3", - "CFG_CENTER_FRAME_ECC_FAR4", - "CFG_CENTER_FRAME_ECC_FAR5", - "CFG_CENTER_FRAME_ECC_FAR6", - "CFG_CENTER_FRAME_ECC_FAR7", - "CFG_CENTER_FRAME_ECC_FAR8", - "CFG_CENTER_FRAME_ECC_FAR9", - "CFG_CENTER_FRAME_ECC_SYNBIT0", - "CFG_CENTER_FRAME_ECC_SYNBIT1", - "CFG_CENTER_FRAME_ECC_SYNBIT2", - "CFG_CENTER_FRAME_ECC_SYNBIT3", - "CFG_CENTER_FRAME_ECC_SYNBIT4", - "CFG_CENTER_FRAME_ECC_SYNDROME0", - "CFG_CENTER_FRAME_ECC_SYNDROME1", - "CFG_CENTER_FRAME_ECC_SYNDROME10", - "CFG_CENTER_FRAME_ECC_SYNDROME11", - "CFG_CENTER_FRAME_ECC_SYNDROME12", - "CFG_CENTER_FRAME_ECC_SYNDROME2", - "CFG_CENTER_FRAME_ECC_SYNDROME3", - "CFG_CENTER_FRAME_ECC_SYNDROME4", - "CFG_CENTER_FRAME_ECC_SYNDROME5", - "CFG_CENTER_FRAME_ECC_SYNDROME6", - "CFG_CENTER_FRAME_ECC_SYNDROME7", - "CFG_CENTER_FRAME_ECC_SYNDROME8", - "CFG_CENTER_FRAME_ECC_SYNDROME9", - "CFG_CENTER_FRAME_ECC_SYNDROMEVALID", - "CFG_CENTER_FRAME_ECC_SYNWORD0", - "CFG_CENTER_FRAME_ECC_SYNWORD1", - "CFG_CENTER_FRAME_ECC_SYNWORD2", - "CFG_CENTER_FRAME_ECC_SYNWORD3", - "CFG_CENTER_FRAME_ECC_SYNWORD4", - "CFG_CENTER_FRAME_ECC_SYNWORD5", - "CFG_CENTER_FRAME_ECC_SYNWORD6", - "CFG_CENTER_ICAP0_CLK", - "CFG_CENTER_ICAP0_CSIB", - "CFG_CENTER_ICAP0_I0", - "CFG_CENTER_ICAP0_I1", - "CFG_CENTER_ICAP0_I10", - "CFG_CENTER_ICAP0_I11", - "CFG_CENTER_ICAP0_I12", - "CFG_CENTER_ICAP0_I13", - "CFG_CENTER_ICAP0_I14", - "CFG_CENTER_ICAP0_I15", - "CFG_CENTER_ICAP0_I16", - "CFG_CENTER_ICAP0_I17", - "CFG_CENTER_ICAP0_I18", - "CFG_CENTER_ICAP0_I19", - "CFG_CENTER_ICAP0_I2", - "CFG_CENTER_ICAP0_I20", - "CFG_CENTER_ICAP0_I21", - "CFG_CENTER_ICAP0_I22", - "CFG_CENTER_ICAP0_I23", - "CFG_CENTER_ICAP0_I24", - "CFG_CENTER_ICAP0_I25", - "CFG_CENTER_ICAP0_I26", - "CFG_CENTER_ICAP0_I27", - "CFG_CENTER_ICAP0_I28", - "CFG_CENTER_ICAP0_I29", - "CFG_CENTER_ICAP0_I3", - "CFG_CENTER_ICAP0_I30", - "CFG_CENTER_ICAP0_I31", - "CFG_CENTER_ICAP0_I4", - "CFG_CENTER_ICAP0_I5", - "CFG_CENTER_ICAP0_I6", - "CFG_CENTER_ICAP0_I7", - "CFG_CENTER_ICAP0_I8", - "CFG_CENTER_ICAP0_I9", - "CFG_CENTER_ICAP0_O0", - "CFG_CENTER_ICAP0_O1", - "CFG_CENTER_ICAP0_O10", - "CFG_CENTER_ICAP0_O11", - "CFG_CENTER_ICAP0_O12", - "CFG_CENTER_ICAP0_O13", - "CFG_CENTER_ICAP0_O14", - "CFG_CENTER_ICAP0_O15", - "CFG_CENTER_ICAP0_O16", - "CFG_CENTER_ICAP0_O17", - "CFG_CENTER_ICAP0_O18", - "CFG_CENTER_ICAP0_O19", - "CFG_CENTER_ICAP0_O2", - "CFG_CENTER_ICAP0_O20", - "CFG_CENTER_ICAP0_O21", - "CFG_CENTER_ICAP0_O22", - "CFG_CENTER_ICAP0_O23", - "CFG_CENTER_ICAP0_O24", - "CFG_CENTER_ICAP0_O25", - "CFG_CENTER_ICAP0_O26", - "CFG_CENTER_ICAP0_O27", - "CFG_CENTER_ICAP0_O28", - "CFG_CENTER_ICAP0_O29", - "CFG_CENTER_ICAP0_O3", - "CFG_CENTER_ICAP0_O30", - "CFG_CENTER_ICAP0_O31", - "CFG_CENTER_ICAP0_O4", - "CFG_CENTER_ICAP0_O5", - "CFG_CENTER_ICAP0_O6", - "CFG_CENTER_ICAP0_O7", - "CFG_CENTER_ICAP0_O8", - "CFG_CENTER_ICAP0_O9", - "CFG_CENTER_ICAP0_RDWRB", - "CFG_CENTER_ICAP1_CLK", - "CFG_CENTER_ICAP1_CSIB", - "CFG_CENTER_ICAP1_I0", - "CFG_CENTER_ICAP1_I1", - "CFG_CENTER_ICAP1_I10", - "CFG_CENTER_ICAP1_I11", - "CFG_CENTER_ICAP1_I12", - "CFG_CENTER_ICAP1_I13", - "CFG_CENTER_ICAP1_I14", - "CFG_CENTER_ICAP1_I15", - "CFG_CENTER_ICAP1_I16", - "CFG_CENTER_ICAP1_I17", - "CFG_CENTER_ICAP1_I18", - "CFG_CENTER_ICAP1_I19", - "CFG_CENTER_ICAP1_I2", - "CFG_CENTER_ICAP1_I20", - "CFG_CENTER_ICAP1_I21", - "CFG_CENTER_ICAP1_I22", - "CFG_CENTER_ICAP1_I23", - "CFG_CENTER_ICAP1_I24", - "CFG_CENTER_ICAP1_I25", - "CFG_CENTER_ICAP1_I26", - "CFG_CENTER_ICAP1_I27", - "CFG_CENTER_ICAP1_I28", - "CFG_CENTER_ICAP1_I29", - "CFG_CENTER_ICAP1_I3", - "CFG_CENTER_ICAP1_I30", - "CFG_CENTER_ICAP1_I31", - "CFG_CENTER_ICAP1_I4", - "CFG_CENTER_ICAP1_I5", - "CFG_CENTER_ICAP1_I6", - "CFG_CENTER_ICAP1_I7", - "CFG_CENTER_ICAP1_I8", - "CFG_CENTER_ICAP1_I9", - "CFG_CENTER_ICAP1_O0", - "CFG_CENTER_ICAP1_O1", - "CFG_CENTER_ICAP1_O10", - "CFG_CENTER_ICAP1_O11", - "CFG_CENTER_ICAP1_O12", - "CFG_CENTER_ICAP1_O13", - "CFG_CENTER_ICAP1_O14", - "CFG_CENTER_ICAP1_O15", - "CFG_CENTER_ICAP1_O16", - "CFG_CENTER_ICAP1_O17", - "CFG_CENTER_ICAP1_O18", - "CFG_CENTER_ICAP1_O19", - "CFG_CENTER_ICAP1_O2", - "CFG_CENTER_ICAP1_O20", - "CFG_CENTER_ICAP1_O21", - "CFG_CENTER_ICAP1_O22", - "CFG_CENTER_ICAP1_O23", - "CFG_CENTER_ICAP1_O24", - "CFG_CENTER_ICAP1_O25", - "CFG_CENTER_ICAP1_O26", - "CFG_CENTER_ICAP1_O27", - "CFG_CENTER_ICAP1_O28", - "CFG_CENTER_ICAP1_O29", - "CFG_CENTER_ICAP1_O3", - "CFG_CENTER_ICAP1_O30", - "CFG_CENTER_ICAP1_O31", - "CFG_CENTER_ICAP1_O4", - "CFG_CENTER_ICAP1_O5", - "CFG_CENTER_ICAP1_O6", - "CFG_CENTER_ICAP1_O7", - "CFG_CENTER_ICAP1_O8", - "CFG_CENTER_ICAP1_O9", - "CFG_CENTER_ICAP1_RDWRB", - "CFG_CENTER_IMUX0_0", - "CFG_CENTER_IMUX0_1", - "CFG_CENTER_IMUX0_10", - "CFG_CENTER_IMUX0_11", - "CFG_CENTER_IMUX0_12", - "CFG_CENTER_IMUX0_13", - "CFG_CENTER_IMUX0_14", - "CFG_CENTER_IMUX0_15", - "CFG_CENTER_IMUX0_16", - "CFG_CENTER_IMUX0_17", - "CFG_CENTER_IMUX0_18", - "CFG_CENTER_IMUX0_19", - "CFG_CENTER_IMUX0_2", - "CFG_CENTER_IMUX0_3", - "CFG_CENTER_IMUX0_4", - "CFG_CENTER_IMUX0_5", - "CFG_CENTER_IMUX0_6", - "CFG_CENTER_IMUX0_7", - "CFG_CENTER_IMUX0_8", - "CFG_CENTER_IMUX0_9", - "CFG_CENTER_IMUX10_0", - "CFG_CENTER_IMUX10_1", - "CFG_CENTER_IMUX10_10", - "CFG_CENTER_IMUX10_11", - "CFG_CENTER_IMUX10_12", - "CFG_CENTER_IMUX10_13", - "CFG_CENTER_IMUX10_14", - "CFG_CENTER_IMUX10_15", - "CFG_CENTER_IMUX10_16", - "CFG_CENTER_IMUX10_17", - "CFG_CENTER_IMUX10_18", - "CFG_CENTER_IMUX10_19", - "CFG_CENTER_IMUX10_2", - "CFG_CENTER_IMUX10_3", - "CFG_CENTER_IMUX10_4", - "CFG_CENTER_IMUX10_5", - "CFG_CENTER_IMUX10_6", - "CFG_CENTER_IMUX10_7", - "CFG_CENTER_IMUX10_8", - "CFG_CENTER_IMUX10_9", - "CFG_CENTER_IMUX11_0", - "CFG_CENTER_IMUX11_1", - "CFG_CENTER_IMUX11_10", - "CFG_CENTER_IMUX11_11", - "CFG_CENTER_IMUX11_12", - "CFG_CENTER_IMUX11_13", - "CFG_CENTER_IMUX11_14", - "CFG_CENTER_IMUX11_15", - "CFG_CENTER_IMUX11_16", - "CFG_CENTER_IMUX11_17", - "CFG_CENTER_IMUX11_18", - "CFG_CENTER_IMUX11_19", - "CFG_CENTER_IMUX11_2", - "CFG_CENTER_IMUX11_3", - "CFG_CENTER_IMUX11_4", - "CFG_CENTER_IMUX11_5", - "CFG_CENTER_IMUX11_6", - "CFG_CENTER_IMUX11_7", - "CFG_CENTER_IMUX11_8", - "CFG_CENTER_IMUX11_9", - "CFG_CENTER_IMUX12_0", - "CFG_CENTER_IMUX12_1", - "CFG_CENTER_IMUX12_10", - "CFG_CENTER_IMUX12_11", - "CFG_CENTER_IMUX12_12", - "CFG_CENTER_IMUX12_13", - "CFG_CENTER_IMUX12_14", - "CFG_CENTER_IMUX12_15", - "CFG_CENTER_IMUX12_16", - "CFG_CENTER_IMUX12_17", - "CFG_CENTER_IMUX12_18", - "CFG_CENTER_IMUX12_19", - "CFG_CENTER_IMUX12_2", - "CFG_CENTER_IMUX12_3", - "CFG_CENTER_IMUX12_4", - "CFG_CENTER_IMUX12_5", - "CFG_CENTER_IMUX12_6", - "CFG_CENTER_IMUX12_7", - "CFG_CENTER_IMUX12_8", - "CFG_CENTER_IMUX12_9", - "CFG_CENTER_IMUX13_0", - "CFG_CENTER_IMUX13_1", - "CFG_CENTER_IMUX13_10", - "CFG_CENTER_IMUX13_11", - "CFG_CENTER_IMUX13_12", - "CFG_CENTER_IMUX13_13", - "CFG_CENTER_IMUX13_14", - "CFG_CENTER_IMUX13_15", - "CFG_CENTER_IMUX13_16", - "CFG_CENTER_IMUX13_17", - "CFG_CENTER_IMUX13_18", - "CFG_CENTER_IMUX13_19", - "CFG_CENTER_IMUX13_2", - "CFG_CENTER_IMUX13_3", - "CFG_CENTER_IMUX13_4", - "CFG_CENTER_IMUX13_5", - "CFG_CENTER_IMUX13_6", - "CFG_CENTER_IMUX13_7", - "CFG_CENTER_IMUX13_8", - "CFG_CENTER_IMUX13_9", - "CFG_CENTER_IMUX14_0", - "CFG_CENTER_IMUX14_1", - "CFG_CENTER_IMUX14_10", - "CFG_CENTER_IMUX14_11", - "CFG_CENTER_IMUX14_12", - "CFG_CENTER_IMUX14_13", - "CFG_CENTER_IMUX14_14", - "CFG_CENTER_IMUX14_15", - "CFG_CENTER_IMUX14_16", - "CFG_CENTER_IMUX14_17", - "CFG_CENTER_IMUX14_18", - "CFG_CENTER_IMUX14_19", - "CFG_CENTER_IMUX14_2", - "CFG_CENTER_IMUX14_3", - "CFG_CENTER_IMUX14_4", - "CFG_CENTER_IMUX14_5", - "CFG_CENTER_IMUX14_6", - "CFG_CENTER_IMUX14_7", - "CFG_CENTER_IMUX14_8", - "CFG_CENTER_IMUX14_9", - "CFG_CENTER_IMUX15_0", - "CFG_CENTER_IMUX15_1", - "CFG_CENTER_IMUX15_10", - "CFG_CENTER_IMUX15_11", - "CFG_CENTER_IMUX15_12", - "CFG_CENTER_IMUX15_13", - "CFG_CENTER_IMUX15_14", - "CFG_CENTER_IMUX15_15", - "CFG_CENTER_IMUX15_16", - "CFG_CENTER_IMUX15_17", - "CFG_CENTER_IMUX15_18", - "CFG_CENTER_IMUX15_19", - "CFG_CENTER_IMUX15_2", - "CFG_CENTER_IMUX15_3", - "CFG_CENTER_IMUX15_4", - "CFG_CENTER_IMUX15_5", - "CFG_CENTER_IMUX15_6", - "CFG_CENTER_IMUX15_7", - "CFG_CENTER_IMUX15_8", - "CFG_CENTER_IMUX15_9", - "CFG_CENTER_IMUX16_0", - "CFG_CENTER_IMUX16_1", - "CFG_CENTER_IMUX16_10", - "CFG_CENTER_IMUX16_11", - "CFG_CENTER_IMUX16_12", - "CFG_CENTER_IMUX16_13", - "CFG_CENTER_IMUX16_14", - "CFG_CENTER_IMUX16_15", - "CFG_CENTER_IMUX16_16", - "CFG_CENTER_IMUX16_17", - "CFG_CENTER_IMUX16_18", - "CFG_CENTER_IMUX16_19", - "CFG_CENTER_IMUX16_2", - "CFG_CENTER_IMUX16_3", - "CFG_CENTER_IMUX16_4", - "CFG_CENTER_IMUX16_5", - "CFG_CENTER_IMUX16_6", - "CFG_CENTER_IMUX16_7", - "CFG_CENTER_IMUX16_8", - "CFG_CENTER_IMUX16_9", - "CFG_CENTER_IMUX17_0", - "CFG_CENTER_IMUX17_1", - "CFG_CENTER_IMUX17_10", - "CFG_CENTER_IMUX17_11", - "CFG_CENTER_IMUX17_12", - "CFG_CENTER_IMUX17_13", - "CFG_CENTER_IMUX17_14", - "CFG_CENTER_IMUX17_15", - "CFG_CENTER_IMUX17_16", - "CFG_CENTER_IMUX17_17", - "CFG_CENTER_IMUX17_18", - "CFG_CENTER_IMUX17_19", - "CFG_CENTER_IMUX17_2", - "CFG_CENTER_IMUX17_3", - "CFG_CENTER_IMUX17_4", - "CFG_CENTER_IMUX17_5", - "CFG_CENTER_IMUX17_6", - "CFG_CENTER_IMUX17_7", - "CFG_CENTER_IMUX17_8", - "CFG_CENTER_IMUX17_9", - "CFG_CENTER_IMUX18_0", - "CFG_CENTER_IMUX18_1", - "CFG_CENTER_IMUX18_10", - "CFG_CENTER_IMUX18_11", - "CFG_CENTER_IMUX18_12", - "CFG_CENTER_IMUX18_13", - "CFG_CENTER_IMUX18_14", - "CFG_CENTER_IMUX18_15", - "CFG_CENTER_IMUX18_16", - "CFG_CENTER_IMUX18_17", - "CFG_CENTER_IMUX18_18", - "CFG_CENTER_IMUX18_19", - "CFG_CENTER_IMUX18_2", - "CFG_CENTER_IMUX18_3", - "CFG_CENTER_IMUX18_4", - "CFG_CENTER_IMUX18_5", - "CFG_CENTER_IMUX18_6", - "CFG_CENTER_IMUX18_7", - "CFG_CENTER_IMUX18_8", - "CFG_CENTER_IMUX18_9", - "CFG_CENTER_IMUX19_0", - "CFG_CENTER_IMUX19_1", - "CFG_CENTER_IMUX19_10", - "CFG_CENTER_IMUX19_11", - "CFG_CENTER_IMUX19_12", - "CFG_CENTER_IMUX19_13", - "CFG_CENTER_IMUX19_14", - "CFG_CENTER_IMUX19_15", - "CFG_CENTER_IMUX19_16", - "CFG_CENTER_IMUX19_17", - "CFG_CENTER_IMUX19_18", - "CFG_CENTER_IMUX19_19", - "CFG_CENTER_IMUX19_2", - "CFG_CENTER_IMUX19_3", - "CFG_CENTER_IMUX19_4", - "CFG_CENTER_IMUX19_5", - "CFG_CENTER_IMUX19_6", - "CFG_CENTER_IMUX19_7", - "CFG_CENTER_IMUX19_8", - "CFG_CENTER_IMUX19_9", - "CFG_CENTER_IMUX1_0", - "CFG_CENTER_IMUX1_1", - "CFG_CENTER_IMUX1_10", - "CFG_CENTER_IMUX1_11", - "CFG_CENTER_IMUX1_12", - "CFG_CENTER_IMUX1_13", - "CFG_CENTER_IMUX1_14", - "CFG_CENTER_IMUX1_15", - "CFG_CENTER_IMUX1_16", - "CFG_CENTER_IMUX1_17", - "CFG_CENTER_IMUX1_18", - "CFG_CENTER_IMUX1_19", - "CFG_CENTER_IMUX1_2", - "CFG_CENTER_IMUX1_3", - "CFG_CENTER_IMUX1_4", - "CFG_CENTER_IMUX1_5", - "CFG_CENTER_IMUX1_6", - "CFG_CENTER_IMUX1_7", - "CFG_CENTER_IMUX1_8", - "CFG_CENTER_IMUX1_9", - "CFG_CENTER_IMUX20_0", - "CFG_CENTER_IMUX20_1", - "CFG_CENTER_IMUX20_10", - "CFG_CENTER_IMUX20_11", - "CFG_CENTER_IMUX20_12", - "CFG_CENTER_IMUX20_13", - "CFG_CENTER_IMUX20_14", - "CFG_CENTER_IMUX20_15", - "CFG_CENTER_IMUX20_16", - "CFG_CENTER_IMUX20_17", - "CFG_CENTER_IMUX20_18", - "CFG_CENTER_IMUX20_19", - "CFG_CENTER_IMUX20_2", - "CFG_CENTER_IMUX20_3", - "CFG_CENTER_IMUX20_4", - "CFG_CENTER_IMUX20_5", - "CFG_CENTER_IMUX20_6", - "CFG_CENTER_IMUX20_7", - "CFG_CENTER_IMUX20_8", - "CFG_CENTER_IMUX20_9", - "CFG_CENTER_IMUX21_0", - "CFG_CENTER_IMUX21_1", - "CFG_CENTER_IMUX21_10", - "CFG_CENTER_IMUX21_11", - "CFG_CENTER_IMUX21_12", - "CFG_CENTER_IMUX21_13", - "CFG_CENTER_IMUX21_14", - "CFG_CENTER_IMUX21_15", - "CFG_CENTER_IMUX21_16", - "CFG_CENTER_IMUX21_17", - "CFG_CENTER_IMUX21_18", - "CFG_CENTER_IMUX21_19", - "CFG_CENTER_IMUX21_2", - "CFG_CENTER_IMUX21_3", - "CFG_CENTER_IMUX21_4", - "CFG_CENTER_IMUX21_5", - "CFG_CENTER_IMUX21_6", - "CFG_CENTER_IMUX21_7", - "CFG_CENTER_IMUX21_8", - "CFG_CENTER_IMUX21_9", - "CFG_CENTER_IMUX22_0", - "CFG_CENTER_IMUX22_1", - "CFG_CENTER_IMUX22_10", - "CFG_CENTER_IMUX22_11", - "CFG_CENTER_IMUX22_12", - "CFG_CENTER_IMUX22_13", - "CFG_CENTER_IMUX22_14", - "CFG_CENTER_IMUX22_15", - "CFG_CENTER_IMUX22_16", - "CFG_CENTER_IMUX22_17", - "CFG_CENTER_IMUX22_18", - "CFG_CENTER_IMUX22_19", - "CFG_CENTER_IMUX22_2", - "CFG_CENTER_IMUX22_3", - "CFG_CENTER_IMUX22_4", - "CFG_CENTER_IMUX22_5", - "CFG_CENTER_IMUX22_6", - "CFG_CENTER_IMUX22_7", - "CFG_CENTER_IMUX22_8", - "CFG_CENTER_IMUX22_9", - "CFG_CENTER_IMUX23_0", - "CFG_CENTER_IMUX23_1", - "CFG_CENTER_IMUX23_10", - "CFG_CENTER_IMUX23_11", - "CFG_CENTER_IMUX23_12", - "CFG_CENTER_IMUX23_13", - "CFG_CENTER_IMUX23_14", - "CFG_CENTER_IMUX23_15", - "CFG_CENTER_IMUX23_16", - "CFG_CENTER_IMUX23_17", - "CFG_CENTER_IMUX23_18", - "CFG_CENTER_IMUX23_19", - "CFG_CENTER_IMUX23_2", - "CFG_CENTER_IMUX23_3", - "CFG_CENTER_IMUX23_4", - "CFG_CENTER_IMUX23_5", - "CFG_CENTER_IMUX23_6", - "CFG_CENTER_IMUX23_7", - "CFG_CENTER_IMUX23_8", - "CFG_CENTER_IMUX23_9", - "CFG_CENTER_IMUX24_0", - "CFG_CENTER_IMUX24_1", - "CFG_CENTER_IMUX24_10", - "CFG_CENTER_IMUX24_11", - "CFG_CENTER_IMUX24_12", - "CFG_CENTER_IMUX24_13", - "CFG_CENTER_IMUX24_14", - "CFG_CENTER_IMUX24_15", - "CFG_CENTER_IMUX24_16", - "CFG_CENTER_IMUX24_17", - "CFG_CENTER_IMUX24_18", - "CFG_CENTER_IMUX24_19", - "CFG_CENTER_IMUX24_2", - "CFG_CENTER_IMUX24_3", - "CFG_CENTER_IMUX24_4", - "CFG_CENTER_IMUX24_5", - "CFG_CENTER_IMUX24_6", - "CFG_CENTER_IMUX24_7", - "CFG_CENTER_IMUX24_8", - "CFG_CENTER_IMUX24_9", - "CFG_CENTER_IMUX25_0", - "CFG_CENTER_IMUX25_1", - "CFG_CENTER_IMUX25_10", - "CFG_CENTER_IMUX25_11", - "CFG_CENTER_IMUX25_12", - "CFG_CENTER_IMUX25_13", - "CFG_CENTER_IMUX25_14", - "CFG_CENTER_IMUX25_15", - "CFG_CENTER_IMUX25_16", - "CFG_CENTER_IMUX25_17", - "CFG_CENTER_IMUX25_18", - "CFG_CENTER_IMUX25_19", - "CFG_CENTER_IMUX25_2", - "CFG_CENTER_IMUX25_3", - "CFG_CENTER_IMUX25_4", - "CFG_CENTER_IMUX25_5", - "CFG_CENTER_IMUX25_6", - "CFG_CENTER_IMUX25_7", - "CFG_CENTER_IMUX25_8", - "CFG_CENTER_IMUX25_9", - "CFG_CENTER_IMUX26_0", - "CFG_CENTER_IMUX26_1", - "CFG_CENTER_IMUX26_10", - "CFG_CENTER_IMUX26_11", - "CFG_CENTER_IMUX26_12", - "CFG_CENTER_IMUX26_13", - "CFG_CENTER_IMUX26_14", - "CFG_CENTER_IMUX26_15", - "CFG_CENTER_IMUX26_16", - "CFG_CENTER_IMUX26_17", - "CFG_CENTER_IMUX26_18", - "CFG_CENTER_IMUX26_19", - "CFG_CENTER_IMUX26_2", - "CFG_CENTER_IMUX26_3", - "CFG_CENTER_IMUX26_4", - "CFG_CENTER_IMUX26_5", - "CFG_CENTER_IMUX26_6", - "CFG_CENTER_IMUX26_7", - "CFG_CENTER_IMUX26_8", - "CFG_CENTER_IMUX26_9", - "CFG_CENTER_IMUX27_0", - "CFG_CENTER_IMUX27_1", - "CFG_CENTER_IMUX27_10", - "CFG_CENTER_IMUX27_11", - "CFG_CENTER_IMUX27_12", - "CFG_CENTER_IMUX27_13", - "CFG_CENTER_IMUX27_14", - "CFG_CENTER_IMUX27_15", - "CFG_CENTER_IMUX27_16", - "CFG_CENTER_IMUX27_17", - "CFG_CENTER_IMUX27_18", - "CFG_CENTER_IMUX27_19", - "CFG_CENTER_IMUX27_2", - "CFG_CENTER_IMUX27_3", - "CFG_CENTER_IMUX27_4", - "CFG_CENTER_IMUX27_5", - "CFG_CENTER_IMUX27_6", - "CFG_CENTER_IMUX27_7", - "CFG_CENTER_IMUX27_8", - "CFG_CENTER_IMUX27_9", - "CFG_CENTER_IMUX28_0", - "CFG_CENTER_IMUX28_1", - "CFG_CENTER_IMUX28_10", - "CFG_CENTER_IMUX28_11", - "CFG_CENTER_IMUX28_12", - "CFG_CENTER_IMUX28_13", - "CFG_CENTER_IMUX28_14", - "CFG_CENTER_IMUX28_15", - "CFG_CENTER_IMUX28_16", - "CFG_CENTER_IMUX28_17", - "CFG_CENTER_IMUX28_18", - "CFG_CENTER_IMUX28_19", - "CFG_CENTER_IMUX28_2", - "CFG_CENTER_IMUX28_3", - "CFG_CENTER_IMUX28_4", - "CFG_CENTER_IMUX28_5", - "CFG_CENTER_IMUX28_6", - "CFG_CENTER_IMUX28_7", - "CFG_CENTER_IMUX28_8", - "CFG_CENTER_IMUX28_9", - "CFG_CENTER_IMUX29_0", - "CFG_CENTER_IMUX29_1", - "CFG_CENTER_IMUX29_10", - "CFG_CENTER_IMUX29_11", - "CFG_CENTER_IMUX29_12", - "CFG_CENTER_IMUX29_13", - "CFG_CENTER_IMUX29_14", - "CFG_CENTER_IMUX29_15", - "CFG_CENTER_IMUX29_16", - "CFG_CENTER_IMUX29_17", - "CFG_CENTER_IMUX29_18", - "CFG_CENTER_IMUX29_19", - "CFG_CENTER_IMUX29_2", - "CFG_CENTER_IMUX29_3", - "CFG_CENTER_IMUX29_4", - "CFG_CENTER_IMUX29_5", - "CFG_CENTER_IMUX29_6", - "CFG_CENTER_IMUX29_7", - "CFG_CENTER_IMUX29_8", - "CFG_CENTER_IMUX29_9", - "CFG_CENTER_IMUX2_0", - "CFG_CENTER_IMUX2_1", - "CFG_CENTER_IMUX2_10", - "CFG_CENTER_IMUX2_11", - "CFG_CENTER_IMUX2_12", - "CFG_CENTER_IMUX2_13", - "CFG_CENTER_IMUX2_14", - "CFG_CENTER_IMUX2_15", - "CFG_CENTER_IMUX2_16", - "CFG_CENTER_IMUX2_17", - "CFG_CENTER_IMUX2_18", - "CFG_CENTER_IMUX2_19", - "CFG_CENTER_IMUX2_2", - "CFG_CENTER_IMUX2_3", - "CFG_CENTER_IMUX2_4", - "CFG_CENTER_IMUX2_5", - "CFG_CENTER_IMUX2_6", - "CFG_CENTER_IMUX2_7", - "CFG_CENTER_IMUX2_8", - "CFG_CENTER_IMUX2_9", - "CFG_CENTER_IMUX30_0", - "CFG_CENTER_IMUX30_1", - "CFG_CENTER_IMUX30_10", - "CFG_CENTER_IMUX30_11", - "CFG_CENTER_IMUX30_12", - "CFG_CENTER_IMUX30_13", - "CFG_CENTER_IMUX30_14", - "CFG_CENTER_IMUX30_15", - "CFG_CENTER_IMUX30_16", - "CFG_CENTER_IMUX30_17", - "CFG_CENTER_IMUX30_18", - "CFG_CENTER_IMUX30_19", - "CFG_CENTER_IMUX30_2", - "CFG_CENTER_IMUX30_3", - "CFG_CENTER_IMUX30_4", - "CFG_CENTER_IMUX30_5", - "CFG_CENTER_IMUX30_6", - "CFG_CENTER_IMUX30_7", - "CFG_CENTER_IMUX30_8", - "CFG_CENTER_IMUX30_9", - "CFG_CENTER_IMUX31_0", - "CFG_CENTER_IMUX31_1", - "CFG_CENTER_IMUX31_10", - "CFG_CENTER_IMUX31_11", - "CFG_CENTER_IMUX31_12", - "CFG_CENTER_IMUX31_13", - "CFG_CENTER_IMUX31_14", - "CFG_CENTER_IMUX31_15", - "CFG_CENTER_IMUX31_16", - "CFG_CENTER_IMUX31_17", - "CFG_CENTER_IMUX31_18", - "CFG_CENTER_IMUX31_19", - "CFG_CENTER_IMUX31_2", - "CFG_CENTER_IMUX31_3", - "CFG_CENTER_IMUX31_4", - "CFG_CENTER_IMUX31_5", - "CFG_CENTER_IMUX31_6", - "CFG_CENTER_IMUX31_7", - "CFG_CENTER_IMUX31_8", - "CFG_CENTER_IMUX31_9", - "CFG_CENTER_IMUX32_0", - "CFG_CENTER_IMUX32_1", - "CFG_CENTER_IMUX32_10", - "CFG_CENTER_IMUX32_11", - "CFG_CENTER_IMUX32_12", - "CFG_CENTER_IMUX32_13", - "CFG_CENTER_IMUX32_14", - "CFG_CENTER_IMUX32_15", - "CFG_CENTER_IMUX32_16", - "CFG_CENTER_IMUX32_17", - "CFG_CENTER_IMUX32_18", - "CFG_CENTER_IMUX32_19", - "CFG_CENTER_IMUX32_2", - "CFG_CENTER_IMUX32_3", - "CFG_CENTER_IMUX32_4", - "CFG_CENTER_IMUX32_5", - "CFG_CENTER_IMUX32_6", - "CFG_CENTER_IMUX32_7", - "CFG_CENTER_IMUX32_8", - "CFG_CENTER_IMUX32_9", - "CFG_CENTER_IMUX33_0", - "CFG_CENTER_IMUX33_1", - "CFG_CENTER_IMUX33_10", - "CFG_CENTER_IMUX33_11", - "CFG_CENTER_IMUX33_12", - "CFG_CENTER_IMUX33_13", - "CFG_CENTER_IMUX33_14", - "CFG_CENTER_IMUX33_15", - "CFG_CENTER_IMUX33_16", - "CFG_CENTER_IMUX33_17", - "CFG_CENTER_IMUX33_18", - "CFG_CENTER_IMUX33_19", - "CFG_CENTER_IMUX33_2", - "CFG_CENTER_IMUX33_3", - "CFG_CENTER_IMUX33_4", - "CFG_CENTER_IMUX33_5", - "CFG_CENTER_IMUX33_6", - "CFG_CENTER_IMUX33_7", - "CFG_CENTER_IMUX33_8", - "CFG_CENTER_IMUX33_9", - "CFG_CENTER_IMUX34_0", - "CFG_CENTER_IMUX34_1", - "CFG_CENTER_IMUX34_10", - "CFG_CENTER_IMUX34_11", - "CFG_CENTER_IMUX34_12", - "CFG_CENTER_IMUX34_13", - "CFG_CENTER_IMUX34_14", - "CFG_CENTER_IMUX34_15", - "CFG_CENTER_IMUX34_16", - "CFG_CENTER_IMUX34_17", - "CFG_CENTER_IMUX34_18", - "CFG_CENTER_IMUX34_19", - "CFG_CENTER_IMUX34_2", - "CFG_CENTER_IMUX34_3", - "CFG_CENTER_IMUX34_4", - "CFG_CENTER_IMUX34_5", - "CFG_CENTER_IMUX34_6", - "CFG_CENTER_IMUX34_7", - "CFG_CENTER_IMUX34_8", - "CFG_CENTER_IMUX34_9", - "CFG_CENTER_IMUX35_0", - "CFG_CENTER_IMUX35_1", - "CFG_CENTER_IMUX35_10", - "CFG_CENTER_IMUX35_11", - "CFG_CENTER_IMUX35_12", - "CFG_CENTER_IMUX35_13", - "CFG_CENTER_IMUX35_14", - "CFG_CENTER_IMUX35_15", - "CFG_CENTER_IMUX35_16", - "CFG_CENTER_IMUX35_17", - "CFG_CENTER_IMUX35_18", - "CFG_CENTER_IMUX35_19", - "CFG_CENTER_IMUX35_2", - "CFG_CENTER_IMUX35_3", - "CFG_CENTER_IMUX35_4", - "CFG_CENTER_IMUX35_5", - "CFG_CENTER_IMUX35_6", - "CFG_CENTER_IMUX35_7", - "CFG_CENTER_IMUX35_8", - "CFG_CENTER_IMUX35_9", - "CFG_CENTER_IMUX36_0", - "CFG_CENTER_IMUX36_1", - "CFG_CENTER_IMUX36_10", - "CFG_CENTER_IMUX36_11", - "CFG_CENTER_IMUX36_12", - "CFG_CENTER_IMUX36_13", - "CFG_CENTER_IMUX36_14", - "CFG_CENTER_IMUX36_15", - "CFG_CENTER_IMUX36_16", - "CFG_CENTER_IMUX36_17", - "CFG_CENTER_IMUX36_18", - "CFG_CENTER_IMUX36_19", - "CFG_CENTER_IMUX36_2", - "CFG_CENTER_IMUX36_3", - "CFG_CENTER_IMUX36_4", - "CFG_CENTER_IMUX36_5", - "CFG_CENTER_IMUX36_6", - "CFG_CENTER_IMUX36_7", - "CFG_CENTER_IMUX36_8", - "CFG_CENTER_IMUX36_9", - "CFG_CENTER_IMUX37_0", - "CFG_CENTER_IMUX37_1", - "CFG_CENTER_IMUX37_10", - "CFG_CENTER_IMUX37_11", - "CFG_CENTER_IMUX37_12", - "CFG_CENTER_IMUX37_13", - "CFG_CENTER_IMUX37_14", - "CFG_CENTER_IMUX37_15", - "CFG_CENTER_IMUX37_16", - "CFG_CENTER_IMUX37_17", - "CFG_CENTER_IMUX37_18", - "CFG_CENTER_IMUX37_19", - "CFG_CENTER_IMUX37_2", - "CFG_CENTER_IMUX37_3", - "CFG_CENTER_IMUX37_4", - "CFG_CENTER_IMUX37_5", - "CFG_CENTER_IMUX37_6", - "CFG_CENTER_IMUX37_7", - "CFG_CENTER_IMUX37_8", - "CFG_CENTER_IMUX37_9", - "CFG_CENTER_IMUX38_0", - "CFG_CENTER_IMUX38_1", - "CFG_CENTER_IMUX38_10", - "CFG_CENTER_IMUX38_11", - "CFG_CENTER_IMUX38_12", - "CFG_CENTER_IMUX38_13", - "CFG_CENTER_IMUX38_14", - "CFG_CENTER_IMUX38_15", - "CFG_CENTER_IMUX38_16", - "CFG_CENTER_IMUX38_17", - "CFG_CENTER_IMUX38_18", - "CFG_CENTER_IMUX38_19", - "CFG_CENTER_IMUX38_2", - "CFG_CENTER_IMUX38_3", - "CFG_CENTER_IMUX38_4", - "CFG_CENTER_IMUX38_5", - "CFG_CENTER_IMUX38_6", - "CFG_CENTER_IMUX38_7", - "CFG_CENTER_IMUX38_8", - "CFG_CENTER_IMUX38_9", - "CFG_CENTER_IMUX39_0", - "CFG_CENTER_IMUX39_1", - "CFG_CENTER_IMUX39_10", - "CFG_CENTER_IMUX39_11", - "CFG_CENTER_IMUX39_12", - "CFG_CENTER_IMUX39_13", - "CFG_CENTER_IMUX39_14", - "CFG_CENTER_IMUX39_15", - "CFG_CENTER_IMUX39_16", - "CFG_CENTER_IMUX39_17", - "CFG_CENTER_IMUX39_18", - "CFG_CENTER_IMUX39_19", - "CFG_CENTER_IMUX39_2", - "CFG_CENTER_IMUX39_3", - "CFG_CENTER_IMUX39_4", - "CFG_CENTER_IMUX39_5", - "CFG_CENTER_IMUX39_6", - "CFG_CENTER_IMUX39_7", - "CFG_CENTER_IMUX39_8", - "CFG_CENTER_IMUX39_9", - "CFG_CENTER_IMUX3_0", - "CFG_CENTER_IMUX3_1", - "CFG_CENTER_IMUX3_10", - "CFG_CENTER_IMUX3_11", - "CFG_CENTER_IMUX3_12", - "CFG_CENTER_IMUX3_13", - "CFG_CENTER_IMUX3_14", - "CFG_CENTER_IMUX3_15", - "CFG_CENTER_IMUX3_16", - "CFG_CENTER_IMUX3_17", - "CFG_CENTER_IMUX3_18", - "CFG_CENTER_IMUX3_19", - "CFG_CENTER_IMUX3_2", - "CFG_CENTER_IMUX3_3", - "CFG_CENTER_IMUX3_4", - "CFG_CENTER_IMUX3_5", - "CFG_CENTER_IMUX3_6", - "CFG_CENTER_IMUX3_7", - "CFG_CENTER_IMUX3_8", - "CFG_CENTER_IMUX3_9", - "CFG_CENTER_IMUX40_0", - "CFG_CENTER_IMUX40_1", - "CFG_CENTER_IMUX40_10", - "CFG_CENTER_IMUX40_11", - "CFG_CENTER_IMUX40_12", - "CFG_CENTER_IMUX40_13", - "CFG_CENTER_IMUX40_14", - "CFG_CENTER_IMUX40_15", - "CFG_CENTER_IMUX40_16", - "CFG_CENTER_IMUX40_17", - "CFG_CENTER_IMUX40_18", - "CFG_CENTER_IMUX40_19", - "CFG_CENTER_IMUX40_2", - "CFG_CENTER_IMUX40_3", - "CFG_CENTER_IMUX40_4", - "CFG_CENTER_IMUX40_5", - "CFG_CENTER_IMUX40_6", - "CFG_CENTER_IMUX40_7", - "CFG_CENTER_IMUX40_8", - "CFG_CENTER_IMUX40_9", - "CFG_CENTER_IMUX41_0", - "CFG_CENTER_IMUX41_1", - "CFG_CENTER_IMUX41_10", - "CFG_CENTER_IMUX41_11", - "CFG_CENTER_IMUX41_12", - "CFG_CENTER_IMUX41_13", - "CFG_CENTER_IMUX41_14", - "CFG_CENTER_IMUX41_15", - "CFG_CENTER_IMUX41_16", - "CFG_CENTER_IMUX41_17", - "CFG_CENTER_IMUX41_18", - "CFG_CENTER_IMUX41_19", - "CFG_CENTER_IMUX41_2", - "CFG_CENTER_IMUX41_3", - "CFG_CENTER_IMUX41_4", - "CFG_CENTER_IMUX41_5", - "CFG_CENTER_IMUX41_6", - "CFG_CENTER_IMUX41_7", - "CFG_CENTER_IMUX41_8", - "CFG_CENTER_IMUX41_9", - "CFG_CENTER_IMUX42_0", - "CFG_CENTER_IMUX42_1", - "CFG_CENTER_IMUX42_10", - "CFG_CENTER_IMUX42_11", - "CFG_CENTER_IMUX42_12", - "CFG_CENTER_IMUX42_13", - "CFG_CENTER_IMUX42_14", - "CFG_CENTER_IMUX42_15", - "CFG_CENTER_IMUX42_16", - "CFG_CENTER_IMUX42_17", - "CFG_CENTER_IMUX42_18", - "CFG_CENTER_IMUX42_19", - "CFG_CENTER_IMUX42_2", - "CFG_CENTER_IMUX42_3", - "CFG_CENTER_IMUX42_4", - "CFG_CENTER_IMUX42_5", - "CFG_CENTER_IMUX42_6", - "CFG_CENTER_IMUX42_7", - "CFG_CENTER_IMUX42_8", - "CFG_CENTER_IMUX42_9", - "CFG_CENTER_IMUX43_0", - "CFG_CENTER_IMUX43_1", - "CFG_CENTER_IMUX43_10", - "CFG_CENTER_IMUX43_11", - "CFG_CENTER_IMUX43_12", - "CFG_CENTER_IMUX43_13", - "CFG_CENTER_IMUX43_14", - "CFG_CENTER_IMUX43_15", - "CFG_CENTER_IMUX43_16", - "CFG_CENTER_IMUX43_17", - "CFG_CENTER_IMUX43_18", - "CFG_CENTER_IMUX43_19", - "CFG_CENTER_IMUX43_2", - "CFG_CENTER_IMUX43_3", - "CFG_CENTER_IMUX43_4", - "CFG_CENTER_IMUX43_5", - "CFG_CENTER_IMUX43_6", - "CFG_CENTER_IMUX43_7", - "CFG_CENTER_IMUX43_8", - "CFG_CENTER_IMUX43_9", - "CFG_CENTER_IMUX44_0", - "CFG_CENTER_IMUX44_1", - "CFG_CENTER_IMUX44_10", - "CFG_CENTER_IMUX44_11", - "CFG_CENTER_IMUX44_12", - "CFG_CENTER_IMUX44_13", - "CFG_CENTER_IMUX44_14", - "CFG_CENTER_IMUX44_15", - "CFG_CENTER_IMUX44_16", - "CFG_CENTER_IMUX44_17", - "CFG_CENTER_IMUX44_18", - "CFG_CENTER_IMUX44_19", - "CFG_CENTER_IMUX44_2", - "CFG_CENTER_IMUX44_3", - "CFG_CENTER_IMUX44_4", - "CFG_CENTER_IMUX44_5", - "CFG_CENTER_IMUX44_6", - "CFG_CENTER_IMUX44_7", - "CFG_CENTER_IMUX44_8", - "CFG_CENTER_IMUX44_9", - "CFG_CENTER_IMUX45_0", - "CFG_CENTER_IMUX45_1", - "CFG_CENTER_IMUX45_10", - "CFG_CENTER_IMUX45_11", - "CFG_CENTER_IMUX45_12", - "CFG_CENTER_IMUX45_13", - "CFG_CENTER_IMUX45_14", - "CFG_CENTER_IMUX45_15", - "CFG_CENTER_IMUX45_16", - "CFG_CENTER_IMUX45_17", - "CFG_CENTER_IMUX45_18", - "CFG_CENTER_IMUX45_19", - "CFG_CENTER_IMUX45_2", - "CFG_CENTER_IMUX45_3", - "CFG_CENTER_IMUX45_4", - "CFG_CENTER_IMUX45_5", - "CFG_CENTER_IMUX45_6", - "CFG_CENTER_IMUX45_7", - "CFG_CENTER_IMUX45_8", - "CFG_CENTER_IMUX45_9", - "CFG_CENTER_IMUX46_0", - "CFG_CENTER_IMUX46_1", - "CFG_CENTER_IMUX46_10", - "CFG_CENTER_IMUX46_11", - "CFG_CENTER_IMUX46_12", - "CFG_CENTER_IMUX46_13", - "CFG_CENTER_IMUX46_14", - "CFG_CENTER_IMUX46_15", - "CFG_CENTER_IMUX46_16", - "CFG_CENTER_IMUX46_17", - "CFG_CENTER_IMUX46_18", - "CFG_CENTER_IMUX46_19", - "CFG_CENTER_IMUX46_2", - "CFG_CENTER_IMUX46_3", - "CFG_CENTER_IMUX46_4", - "CFG_CENTER_IMUX46_5", - "CFG_CENTER_IMUX46_6", - "CFG_CENTER_IMUX46_7", - "CFG_CENTER_IMUX46_8", - "CFG_CENTER_IMUX46_9", - "CFG_CENTER_IMUX47_0", - "CFG_CENTER_IMUX47_1", - "CFG_CENTER_IMUX47_10", - "CFG_CENTER_IMUX47_11", - "CFG_CENTER_IMUX47_12", - "CFG_CENTER_IMUX47_13", - "CFG_CENTER_IMUX47_14", - "CFG_CENTER_IMUX47_15", - "CFG_CENTER_IMUX47_16", - "CFG_CENTER_IMUX47_17", - "CFG_CENTER_IMUX47_18", - "CFG_CENTER_IMUX47_19", - "CFG_CENTER_IMUX47_2", - "CFG_CENTER_IMUX47_3", - "CFG_CENTER_IMUX47_4", - "CFG_CENTER_IMUX47_5", - "CFG_CENTER_IMUX47_6", - "CFG_CENTER_IMUX47_7", - "CFG_CENTER_IMUX47_8", - "CFG_CENTER_IMUX47_9", - "CFG_CENTER_IMUX4_0", - "CFG_CENTER_IMUX4_1", - "CFG_CENTER_IMUX4_10", - "CFG_CENTER_IMUX4_11", - "CFG_CENTER_IMUX4_12", - "CFG_CENTER_IMUX4_13", - "CFG_CENTER_IMUX4_14", - "CFG_CENTER_IMUX4_15", - "CFG_CENTER_IMUX4_16", - "CFG_CENTER_IMUX4_17", - "CFG_CENTER_IMUX4_18", - "CFG_CENTER_IMUX4_19", - "CFG_CENTER_IMUX4_2", - "CFG_CENTER_IMUX4_3", - "CFG_CENTER_IMUX4_4", - "CFG_CENTER_IMUX4_5", - "CFG_CENTER_IMUX4_6", - "CFG_CENTER_IMUX4_7", - "CFG_CENTER_IMUX4_8", - "CFG_CENTER_IMUX4_9", - "CFG_CENTER_IMUX5_0", - "CFG_CENTER_IMUX5_1", - "CFG_CENTER_IMUX5_10", - "CFG_CENTER_IMUX5_11", - "CFG_CENTER_IMUX5_12", - "CFG_CENTER_IMUX5_13", - "CFG_CENTER_IMUX5_14", - "CFG_CENTER_IMUX5_15", - "CFG_CENTER_IMUX5_16", - "CFG_CENTER_IMUX5_17", - "CFG_CENTER_IMUX5_18", - "CFG_CENTER_IMUX5_19", - "CFG_CENTER_IMUX5_2", - "CFG_CENTER_IMUX5_3", - "CFG_CENTER_IMUX5_4", - "CFG_CENTER_IMUX5_5", - "CFG_CENTER_IMUX5_6", - "CFG_CENTER_IMUX5_7", - "CFG_CENTER_IMUX5_8", - "CFG_CENTER_IMUX5_9", - "CFG_CENTER_IMUX6_0", - "CFG_CENTER_IMUX6_1", - "CFG_CENTER_IMUX6_10", - "CFG_CENTER_IMUX6_11", - "CFG_CENTER_IMUX6_12", - "CFG_CENTER_IMUX6_13", - "CFG_CENTER_IMUX6_14", - "CFG_CENTER_IMUX6_15", - "CFG_CENTER_IMUX6_16", - "CFG_CENTER_IMUX6_17", - "CFG_CENTER_IMUX6_18", - "CFG_CENTER_IMUX6_19", - "CFG_CENTER_IMUX6_2", - "CFG_CENTER_IMUX6_3", - "CFG_CENTER_IMUX6_4", - "CFG_CENTER_IMUX6_5", - "CFG_CENTER_IMUX6_6", - "CFG_CENTER_IMUX6_7", - "CFG_CENTER_IMUX6_8", - "CFG_CENTER_IMUX6_9", - "CFG_CENTER_IMUX7_0", - "CFG_CENTER_IMUX7_1", - "CFG_CENTER_IMUX7_10", - "CFG_CENTER_IMUX7_11", - "CFG_CENTER_IMUX7_12", - "CFG_CENTER_IMUX7_13", - "CFG_CENTER_IMUX7_14", - "CFG_CENTER_IMUX7_15", - "CFG_CENTER_IMUX7_16", - "CFG_CENTER_IMUX7_17", - "CFG_CENTER_IMUX7_18", - "CFG_CENTER_IMUX7_19", - "CFG_CENTER_IMUX7_2", - "CFG_CENTER_IMUX7_3", - "CFG_CENTER_IMUX7_4", - "CFG_CENTER_IMUX7_5", - "CFG_CENTER_IMUX7_6", - "CFG_CENTER_IMUX7_7", - "CFG_CENTER_IMUX7_8", - "CFG_CENTER_IMUX7_9", - "CFG_CENTER_IMUX8_0", - "CFG_CENTER_IMUX8_1", - "CFG_CENTER_IMUX8_10", - "CFG_CENTER_IMUX8_11", - "CFG_CENTER_IMUX8_12", - "CFG_CENTER_IMUX8_13", - "CFG_CENTER_IMUX8_14", - "CFG_CENTER_IMUX8_15", - "CFG_CENTER_IMUX8_16", - "CFG_CENTER_IMUX8_17", - "CFG_CENTER_IMUX8_18", - "CFG_CENTER_IMUX8_19", - "CFG_CENTER_IMUX8_2", - "CFG_CENTER_IMUX8_3", - "CFG_CENTER_IMUX8_4", - "CFG_CENTER_IMUX8_5", - "CFG_CENTER_IMUX8_6", - "CFG_CENTER_IMUX8_7", - "CFG_CENTER_IMUX8_8", - "CFG_CENTER_IMUX8_9", - "CFG_CENTER_IMUX9_0", - "CFG_CENTER_IMUX9_1", - "CFG_CENTER_IMUX9_10", - "CFG_CENTER_IMUX9_11", - "CFG_CENTER_IMUX9_12", - "CFG_CENTER_IMUX9_13", - "CFG_CENTER_IMUX9_14", - "CFG_CENTER_IMUX9_15", - "CFG_CENTER_IMUX9_16", - "CFG_CENTER_IMUX9_17", - "CFG_CENTER_IMUX9_18", - "CFG_CENTER_IMUX9_19", - "CFG_CENTER_IMUX9_2", - "CFG_CENTER_IMUX9_3", - "CFG_CENTER_IMUX9_4", - "CFG_CENTER_IMUX9_5", - "CFG_CENTER_IMUX9_6", - "CFG_CENTER_IMUX9_7", - "CFG_CENTER_IMUX9_8", - "CFG_CENTER_IMUX9_9", - "CFG_CENTER_LH10_0", - "CFG_CENTER_LH10_1", - "CFG_CENTER_LH10_10", - "CFG_CENTER_LH10_11", - "CFG_CENTER_LH10_12", - "CFG_CENTER_LH10_13", - "CFG_CENTER_LH10_14", - "CFG_CENTER_LH10_15", - "CFG_CENTER_LH10_16", - "CFG_CENTER_LH10_17", - "CFG_CENTER_LH10_18", - "CFG_CENTER_LH10_19", - "CFG_CENTER_LH10_2", - "CFG_CENTER_LH10_3", - "CFG_CENTER_LH10_4", - "CFG_CENTER_LH10_5", - "CFG_CENTER_LH10_6", - "CFG_CENTER_LH10_7", - "CFG_CENTER_LH10_8", - "CFG_CENTER_LH10_9", - "CFG_CENTER_LH11_0", - "CFG_CENTER_LH11_1", - "CFG_CENTER_LH11_10", - "CFG_CENTER_LH11_11", - "CFG_CENTER_LH11_12", - "CFG_CENTER_LH11_13", - "CFG_CENTER_LH11_14", - "CFG_CENTER_LH11_15", - "CFG_CENTER_LH11_16", - "CFG_CENTER_LH11_17", - "CFG_CENTER_LH11_18", - "CFG_CENTER_LH11_19", - "CFG_CENTER_LH11_2", - "CFG_CENTER_LH11_3", - "CFG_CENTER_LH11_4", - "CFG_CENTER_LH11_5", - "CFG_CENTER_LH11_6", - "CFG_CENTER_LH11_7", - "CFG_CENTER_LH11_8", - "CFG_CENTER_LH11_9", - "CFG_CENTER_LH12_0", - "CFG_CENTER_LH12_1", - "CFG_CENTER_LH12_10", - "CFG_CENTER_LH12_11", - "CFG_CENTER_LH12_12", - "CFG_CENTER_LH12_13", - "CFG_CENTER_LH12_14", - "CFG_CENTER_LH12_15", - "CFG_CENTER_LH12_16", - "CFG_CENTER_LH12_17", - "CFG_CENTER_LH12_18", - "CFG_CENTER_LH12_19", - "CFG_CENTER_LH12_2", - "CFG_CENTER_LH12_3", - "CFG_CENTER_LH12_4", - "CFG_CENTER_LH12_5", - "CFG_CENTER_LH12_6", - "CFG_CENTER_LH12_7", - "CFG_CENTER_LH12_8", - "CFG_CENTER_LH12_9", - "CFG_CENTER_LH1_0", - "CFG_CENTER_LH1_1", - "CFG_CENTER_LH1_10", - "CFG_CENTER_LH1_11", - "CFG_CENTER_LH1_12", - "CFG_CENTER_LH1_13", - "CFG_CENTER_LH1_14", - "CFG_CENTER_LH1_15", - "CFG_CENTER_LH1_16", - "CFG_CENTER_LH1_17", - "CFG_CENTER_LH1_18", - "CFG_CENTER_LH1_19", - "CFG_CENTER_LH1_2", - "CFG_CENTER_LH1_3", - "CFG_CENTER_LH1_4", - "CFG_CENTER_LH1_5", - "CFG_CENTER_LH1_6", - "CFG_CENTER_LH1_7", - "CFG_CENTER_LH1_8", - "CFG_CENTER_LH1_9", - "CFG_CENTER_LH2_0", - "CFG_CENTER_LH2_1", - "CFG_CENTER_LH2_10", - "CFG_CENTER_LH2_11", - "CFG_CENTER_LH2_12", - "CFG_CENTER_LH2_13", - "CFG_CENTER_LH2_14", - "CFG_CENTER_LH2_15", - "CFG_CENTER_LH2_16", - "CFG_CENTER_LH2_17", - "CFG_CENTER_LH2_18", - "CFG_CENTER_LH2_19", - "CFG_CENTER_LH2_2", - "CFG_CENTER_LH2_3", - "CFG_CENTER_LH2_4", - "CFG_CENTER_LH2_5", - "CFG_CENTER_LH2_6", - "CFG_CENTER_LH2_7", - "CFG_CENTER_LH2_8", - "CFG_CENTER_LH2_9", - "CFG_CENTER_LH3_0", - "CFG_CENTER_LH3_1", - "CFG_CENTER_LH3_10", - "CFG_CENTER_LH3_11", - "CFG_CENTER_LH3_12", - "CFG_CENTER_LH3_13", - "CFG_CENTER_LH3_14", - "CFG_CENTER_LH3_15", - "CFG_CENTER_LH3_16", - "CFG_CENTER_LH3_17", - "CFG_CENTER_LH3_18", - "CFG_CENTER_LH3_19", - "CFG_CENTER_LH3_2", - "CFG_CENTER_LH3_3", - "CFG_CENTER_LH3_4", - "CFG_CENTER_LH3_5", - "CFG_CENTER_LH3_6", - "CFG_CENTER_LH3_7", - "CFG_CENTER_LH3_8", - "CFG_CENTER_LH3_9", - "CFG_CENTER_LH4_0", - "CFG_CENTER_LH4_1", - "CFG_CENTER_LH4_10", - "CFG_CENTER_LH4_11", - "CFG_CENTER_LH4_12", - "CFG_CENTER_LH4_13", - "CFG_CENTER_LH4_14", - "CFG_CENTER_LH4_15", - "CFG_CENTER_LH4_16", - "CFG_CENTER_LH4_17", - "CFG_CENTER_LH4_18", - "CFG_CENTER_LH4_19", - "CFG_CENTER_LH4_2", - "CFG_CENTER_LH4_3", - "CFG_CENTER_LH4_4", - "CFG_CENTER_LH4_5", - "CFG_CENTER_LH4_6", - "CFG_CENTER_LH4_7", - "CFG_CENTER_LH4_8", - "CFG_CENTER_LH4_9", - "CFG_CENTER_LH5_0", - "CFG_CENTER_LH5_1", - "CFG_CENTER_LH5_10", - "CFG_CENTER_LH5_11", - "CFG_CENTER_LH5_12", - "CFG_CENTER_LH5_13", - "CFG_CENTER_LH5_14", - "CFG_CENTER_LH5_15", - "CFG_CENTER_LH5_16", - "CFG_CENTER_LH5_17", - "CFG_CENTER_LH5_18", - "CFG_CENTER_LH5_19", - "CFG_CENTER_LH5_2", - "CFG_CENTER_LH5_3", - "CFG_CENTER_LH5_4", - "CFG_CENTER_LH5_5", - "CFG_CENTER_LH5_6", - "CFG_CENTER_LH5_7", - "CFG_CENTER_LH5_8", - "CFG_CENTER_LH5_9", - "CFG_CENTER_LH6_0", - "CFG_CENTER_LH6_1", - "CFG_CENTER_LH6_10", - "CFG_CENTER_LH6_11", - "CFG_CENTER_LH6_12", - "CFG_CENTER_LH6_13", - "CFG_CENTER_LH6_14", - "CFG_CENTER_LH6_15", - "CFG_CENTER_LH6_16", - "CFG_CENTER_LH6_17", - "CFG_CENTER_LH6_18", - "CFG_CENTER_LH6_19", - "CFG_CENTER_LH6_2", - "CFG_CENTER_LH6_3", - "CFG_CENTER_LH6_4", - "CFG_CENTER_LH6_5", - "CFG_CENTER_LH6_6", - "CFG_CENTER_LH6_7", - "CFG_CENTER_LH6_8", - "CFG_CENTER_LH6_9", - "CFG_CENTER_LH7_0", - "CFG_CENTER_LH7_1", - "CFG_CENTER_LH7_10", - "CFG_CENTER_LH7_11", - "CFG_CENTER_LH7_12", - "CFG_CENTER_LH7_13", - "CFG_CENTER_LH7_14", - "CFG_CENTER_LH7_15", - "CFG_CENTER_LH7_16", - "CFG_CENTER_LH7_17", - "CFG_CENTER_LH7_18", - "CFG_CENTER_LH7_19", - "CFG_CENTER_LH7_2", - "CFG_CENTER_LH7_3", - "CFG_CENTER_LH7_4", - "CFG_CENTER_LH7_5", - "CFG_CENTER_LH7_6", - "CFG_CENTER_LH7_7", - "CFG_CENTER_LH7_8", - "CFG_CENTER_LH7_9", - "CFG_CENTER_LH8_0", - "CFG_CENTER_LH8_1", - "CFG_CENTER_LH8_10", - "CFG_CENTER_LH8_11", - "CFG_CENTER_LH8_12", - "CFG_CENTER_LH8_13", - "CFG_CENTER_LH8_14", - "CFG_CENTER_LH8_15", - "CFG_CENTER_LH8_16", - "CFG_CENTER_LH8_17", - "CFG_CENTER_LH8_18", - "CFG_CENTER_LH8_19", - "CFG_CENTER_LH8_2", - "CFG_CENTER_LH8_3", - "CFG_CENTER_LH8_4", - "CFG_CENTER_LH8_5", - "CFG_CENTER_LH8_6", - "CFG_CENTER_LH8_7", - "CFG_CENTER_LH8_8", - "CFG_CENTER_LH8_9", - "CFG_CENTER_LH9_0", - "CFG_CENTER_LH9_1", - "CFG_CENTER_LH9_10", - "CFG_CENTER_LH9_11", - "CFG_CENTER_LH9_12", - "CFG_CENTER_LH9_13", - "CFG_CENTER_LH9_14", - "CFG_CENTER_LH9_15", - "CFG_CENTER_LH9_16", - "CFG_CENTER_LH9_17", - "CFG_CENTER_LH9_18", - "CFG_CENTER_LH9_19", - "CFG_CENTER_LH9_2", - "CFG_CENTER_LH9_3", - "CFG_CENTER_LH9_4", - "CFG_CENTER_LH9_5", - "CFG_CENTER_LH9_6", - "CFG_CENTER_LH9_7", - "CFG_CENTER_LH9_8", - "CFG_CENTER_LH9_9", - "CFG_CENTER_LOGIC_OUTS_B0_0", - "CFG_CENTER_LOGIC_OUTS_B0_1", - "CFG_CENTER_LOGIC_OUTS_B0_10", - "CFG_CENTER_LOGIC_OUTS_B0_11", - "CFG_CENTER_LOGIC_OUTS_B0_12", - "CFG_CENTER_LOGIC_OUTS_B0_13", - "CFG_CENTER_LOGIC_OUTS_B0_14", - "CFG_CENTER_LOGIC_OUTS_B0_15", - "CFG_CENTER_LOGIC_OUTS_B0_16", - "CFG_CENTER_LOGIC_OUTS_B0_17", - "CFG_CENTER_LOGIC_OUTS_B0_18", - "CFG_CENTER_LOGIC_OUTS_B0_19", - "CFG_CENTER_LOGIC_OUTS_B0_2", - "CFG_CENTER_LOGIC_OUTS_B0_3", - "CFG_CENTER_LOGIC_OUTS_B0_4", - "CFG_CENTER_LOGIC_OUTS_B0_5", - "CFG_CENTER_LOGIC_OUTS_B0_6", - "CFG_CENTER_LOGIC_OUTS_B0_7", - "CFG_CENTER_LOGIC_OUTS_B0_8", - "CFG_CENTER_LOGIC_OUTS_B0_9", - "CFG_CENTER_LOGIC_OUTS_B10_0", - "CFG_CENTER_LOGIC_OUTS_B10_1", - "CFG_CENTER_LOGIC_OUTS_B10_10", - "CFG_CENTER_LOGIC_OUTS_B10_11", - "CFG_CENTER_LOGIC_OUTS_B10_12", - "CFG_CENTER_LOGIC_OUTS_B10_13", - "CFG_CENTER_LOGIC_OUTS_B10_14", - "CFG_CENTER_LOGIC_OUTS_B10_15", - "CFG_CENTER_LOGIC_OUTS_B10_16", - "CFG_CENTER_LOGIC_OUTS_B10_17", - "CFG_CENTER_LOGIC_OUTS_B10_18", - "CFG_CENTER_LOGIC_OUTS_B10_19", - "CFG_CENTER_LOGIC_OUTS_B10_2", - "CFG_CENTER_LOGIC_OUTS_B10_3", - "CFG_CENTER_LOGIC_OUTS_B10_4", - "CFG_CENTER_LOGIC_OUTS_B10_5", - "CFG_CENTER_LOGIC_OUTS_B10_6", - "CFG_CENTER_LOGIC_OUTS_B10_7", - "CFG_CENTER_LOGIC_OUTS_B10_8", - "CFG_CENTER_LOGIC_OUTS_B10_9", - "CFG_CENTER_LOGIC_OUTS_B11_0", - "CFG_CENTER_LOGIC_OUTS_B11_1", - "CFG_CENTER_LOGIC_OUTS_B11_10", - "CFG_CENTER_LOGIC_OUTS_B11_11", - "CFG_CENTER_LOGIC_OUTS_B11_12", - "CFG_CENTER_LOGIC_OUTS_B11_13", - "CFG_CENTER_LOGIC_OUTS_B11_14", - "CFG_CENTER_LOGIC_OUTS_B11_15", - "CFG_CENTER_LOGIC_OUTS_B11_16", - "CFG_CENTER_LOGIC_OUTS_B11_17", - "CFG_CENTER_LOGIC_OUTS_B11_18", - "CFG_CENTER_LOGIC_OUTS_B11_19", - "CFG_CENTER_LOGIC_OUTS_B11_2", - "CFG_CENTER_LOGIC_OUTS_B11_3", - "CFG_CENTER_LOGIC_OUTS_B11_4", - "CFG_CENTER_LOGIC_OUTS_B11_5", - "CFG_CENTER_LOGIC_OUTS_B11_6", - "CFG_CENTER_LOGIC_OUTS_B11_7", - "CFG_CENTER_LOGIC_OUTS_B11_8", - "CFG_CENTER_LOGIC_OUTS_B11_9", - "CFG_CENTER_LOGIC_OUTS_B12_0", - "CFG_CENTER_LOGIC_OUTS_B12_1", - "CFG_CENTER_LOGIC_OUTS_B12_10", - "CFG_CENTER_LOGIC_OUTS_B12_11", - "CFG_CENTER_LOGIC_OUTS_B12_12", - "CFG_CENTER_LOGIC_OUTS_B12_13", - "CFG_CENTER_LOGIC_OUTS_B12_14", - "CFG_CENTER_LOGIC_OUTS_B12_15", - "CFG_CENTER_LOGIC_OUTS_B12_16", - "CFG_CENTER_LOGIC_OUTS_B12_17", - "CFG_CENTER_LOGIC_OUTS_B12_18", - "CFG_CENTER_LOGIC_OUTS_B12_19", - "CFG_CENTER_LOGIC_OUTS_B12_2", - "CFG_CENTER_LOGIC_OUTS_B12_3", - "CFG_CENTER_LOGIC_OUTS_B12_4", - "CFG_CENTER_LOGIC_OUTS_B12_5", - "CFG_CENTER_LOGIC_OUTS_B12_6", - "CFG_CENTER_LOGIC_OUTS_B12_7", - "CFG_CENTER_LOGIC_OUTS_B12_8", - "CFG_CENTER_LOGIC_OUTS_B12_9", - "CFG_CENTER_LOGIC_OUTS_B13_0", - "CFG_CENTER_LOGIC_OUTS_B13_1", - "CFG_CENTER_LOGIC_OUTS_B13_10", - "CFG_CENTER_LOGIC_OUTS_B13_11", - "CFG_CENTER_LOGIC_OUTS_B13_12", - "CFG_CENTER_LOGIC_OUTS_B13_13", - "CFG_CENTER_LOGIC_OUTS_B13_14", - "CFG_CENTER_LOGIC_OUTS_B13_15", - "CFG_CENTER_LOGIC_OUTS_B13_16", - "CFG_CENTER_LOGIC_OUTS_B13_17", - "CFG_CENTER_LOGIC_OUTS_B13_18", - "CFG_CENTER_LOGIC_OUTS_B13_19", - "CFG_CENTER_LOGIC_OUTS_B13_2", - "CFG_CENTER_LOGIC_OUTS_B13_3", - "CFG_CENTER_LOGIC_OUTS_B13_4", - "CFG_CENTER_LOGIC_OUTS_B13_5", - "CFG_CENTER_LOGIC_OUTS_B13_6", - "CFG_CENTER_LOGIC_OUTS_B13_7", - "CFG_CENTER_LOGIC_OUTS_B13_8", - "CFG_CENTER_LOGIC_OUTS_B13_9", - "CFG_CENTER_LOGIC_OUTS_B14_0", - "CFG_CENTER_LOGIC_OUTS_B14_1", - "CFG_CENTER_LOGIC_OUTS_B14_10", - "CFG_CENTER_LOGIC_OUTS_B14_11", - "CFG_CENTER_LOGIC_OUTS_B14_12", - "CFG_CENTER_LOGIC_OUTS_B14_13", - "CFG_CENTER_LOGIC_OUTS_B14_14", - "CFG_CENTER_LOGIC_OUTS_B14_15", - "CFG_CENTER_LOGIC_OUTS_B14_16", - "CFG_CENTER_LOGIC_OUTS_B14_17", - "CFG_CENTER_LOGIC_OUTS_B14_18", - "CFG_CENTER_LOGIC_OUTS_B14_19", - "CFG_CENTER_LOGIC_OUTS_B14_2", - "CFG_CENTER_LOGIC_OUTS_B14_3", - "CFG_CENTER_LOGIC_OUTS_B14_4", - "CFG_CENTER_LOGIC_OUTS_B14_5", - "CFG_CENTER_LOGIC_OUTS_B14_6", - "CFG_CENTER_LOGIC_OUTS_B14_7", - "CFG_CENTER_LOGIC_OUTS_B14_8", - "CFG_CENTER_LOGIC_OUTS_B14_9", - "CFG_CENTER_LOGIC_OUTS_B15_0", - "CFG_CENTER_LOGIC_OUTS_B15_1", - "CFG_CENTER_LOGIC_OUTS_B15_10", - "CFG_CENTER_LOGIC_OUTS_B15_11", - "CFG_CENTER_LOGIC_OUTS_B15_12", - "CFG_CENTER_LOGIC_OUTS_B15_13", - "CFG_CENTER_LOGIC_OUTS_B15_14", - "CFG_CENTER_LOGIC_OUTS_B15_15", - "CFG_CENTER_LOGIC_OUTS_B15_16", - "CFG_CENTER_LOGIC_OUTS_B15_17", - "CFG_CENTER_LOGIC_OUTS_B15_18", - "CFG_CENTER_LOGIC_OUTS_B15_19", - "CFG_CENTER_LOGIC_OUTS_B15_2", - "CFG_CENTER_LOGIC_OUTS_B15_3", - "CFG_CENTER_LOGIC_OUTS_B15_4", - "CFG_CENTER_LOGIC_OUTS_B15_5", - "CFG_CENTER_LOGIC_OUTS_B15_6", - "CFG_CENTER_LOGIC_OUTS_B15_7", - "CFG_CENTER_LOGIC_OUTS_B15_8", - "CFG_CENTER_LOGIC_OUTS_B15_9", - "CFG_CENTER_LOGIC_OUTS_B16_0", - "CFG_CENTER_LOGIC_OUTS_B16_1", - "CFG_CENTER_LOGIC_OUTS_B16_10", - "CFG_CENTER_LOGIC_OUTS_B16_11", - "CFG_CENTER_LOGIC_OUTS_B16_12", - "CFG_CENTER_LOGIC_OUTS_B16_13", - "CFG_CENTER_LOGIC_OUTS_B16_14", - "CFG_CENTER_LOGIC_OUTS_B16_15", - "CFG_CENTER_LOGIC_OUTS_B16_16", - "CFG_CENTER_LOGIC_OUTS_B16_17", - "CFG_CENTER_LOGIC_OUTS_B16_18", - "CFG_CENTER_LOGIC_OUTS_B16_19", - "CFG_CENTER_LOGIC_OUTS_B16_2", - "CFG_CENTER_LOGIC_OUTS_B16_3", - "CFG_CENTER_LOGIC_OUTS_B16_4", - "CFG_CENTER_LOGIC_OUTS_B16_5", - "CFG_CENTER_LOGIC_OUTS_B16_6", - "CFG_CENTER_LOGIC_OUTS_B16_7", - "CFG_CENTER_LOGIC_OUTS_B16_8", - "CFG_CENTER_LOGIC_OUTS_B16_9", - "CFG_CENTER_LOGIC_OUTS_B17_0", - "CFG_CENTER_LOGIC_OUTS_B17_1", - "CFG_CENTER_LOGIC_OUTS_B17_10", - "CFG_CENTER_LOGIC_OUTS_B17_11", - "CFG_CENTER_LOGIC_OUTS_B17_12", - "CFG_CENTER_LOGIC_OUTS_B17_13", - "CFG_CENTER_LOGIC_OUTS_B17_14", - "CFG_CENTER_LOGIC_OUTS_B17_15", - "CFG_CENTER_LOGIC_OUTS_B17_16", - "CFG_CENTER_LOGIC_OUTS_B17_17", - "CFG_CENTER_LOGIC_OUTS_B17_18", - "CFG_CENTER_LOGIC_OUTS_B17_19", - "CFG_CENTER_LOGIC_OUTS_B17_2", - "CFG_CENTER_LOGIC_OUTS_B17_3", - "CFG_CENTER_LOGIC_OUTS_B17_4", - "CFG_CENTER_LOGIC_OUTS_B17_5", - "CFG_CENTER_LOGIC_OUTS_B17_6", - "CFG_CENTER_LOGIC_OUTS_B17_7", - "CFG_CENTER_LOGIC_OUTS_B17_8", - "CFG_CENTER_LOGIC_OUTS_B17_9", - "CFG_CENTER_LOGIC_OUTS_B18_0", - "CFG_CENTER_LOGIC_OUTS_B18_1", - "CFG_CENTER_LOGIC_OUTS_B18_10", - "CFG_CENTER_LOGIC_OUTS_B18_11", - "CFG_CENTER_LOGIC_OUTS_B18_12", - "CFG_CENTER_LOGIC_OUTS_B18_13", - "CFG_CENTER_LOGIC_OUTS_B18_14", - "CFG_CENTER_LOGIC_OUTS_B18_15", - "CFG_CENTER_LOGIC_OUTS_B18_16", - "CFG_CENTER_LOGIC_OUTS_B18_17", - "CFG_CENTER_LOGIC_OUTS_B18_18", - "CFG_CENTER_LOGIC_OUTS_B18_19", - "CFG_CENTER_LOGIC_OUTS_B18_2", - "CFG_CENTER_LOGIC_OUTS_B18_3", - "CFG_CENTER_LOGIC_OUTS_B18_4", - "CFG_CENTER_LOGIC_OUTS_B18_5", - "CFG_CENTER_LOGIC_OUTS_B18_6", - "CFG_CENTER_LOGIC_OUTS_B18_7", - "CFG_CENTER_LOGIC_OUTS_B18_8", - "CFG_CENTER_LOGIC_OUTS_B18_9", - "CFG_CENTER_LOGIC_OUTS_B19_0", - "CFG_CENTER_LOGIC_OUTS_B19_1", - "CFG_CENTER_LOGIC_OUTS_B19_10", - "CFG_CENTER_LOGIC_OUTS_B19_11", - "CFG_CENTER_LOGIC_OUTS_B19_12", - "CFG_CENTER_LOGIC_OUTS_B19_13", - "CFG_CENTER_LOGIC_OUTS_B19_14", - "CFG_CENTER_LOGIC_OUTS_B19_15", - "CFG_CENTER_LOGIC_OUTS_B19_16", - "CFG_CENTER_LOGIC_OUTS_B19_17", - "CFG_CENTER_LOGIC_OUTS_B19_18", - "CFG_CENTER_LOGIC_OUTS_B19_19", - "CFG_CENTER_LOGIC_OUTS_B19_2", - "CFG_CENTER_LOGIC_OUTS_B19_3", - "CFG_CENTER_LOGIC_OUTS_B19_4", - "CFG_CENTER_LOGIC_OUTS_B19_5", - "CFG_CENTER_LOGIC_OUTS_B19_6", - "CFG_CENTER_LOGIC_OUTS_B19_7", - "CFG_CENTER_LOGIC_OUTS_B19_8", - "CFG_CENTER_LOGIC_OUTS_B19_9", - "CFG_CENTER_LOGIC_OUTS_B1_0", - "CFG_CENTER_LOGIC_OUTS_B1_1", - "CFG_CENTER_LOGIC_OUTS_B1_10", - "CFG_CENTER_LOGIC_OUTS_B1_11", - "CFG_CENTER_LOGIC_OUTS_B1_12", - "CFG_CENTER_LOGIC_OUTS_B1_13", - "CFG_CENTER_LOGIC_OUTS_B1_14", - "CFG_CENTER_LOGIC_OUTS_B1_15", - "CFG_CENTER_LOGIC_OUTS_B1_16", - "CFG_CENTER_LOGIC_OUTS_B1_17", - "CFG_CENTER_LOGIC_OUTS_B1_18", - "CFG_CENTER_LOGIC_OUTS_B1_19", - "CFG_CENTER_LOGIC_OUTS_B1_2", - "CFG_CENTER_LOGIC_OUTS_B1_3", - "CFG_CENTER_LOGIC_OUTS_B1_4", - "CFG_CENTER_LOGIC_OUTS_B1_5", - "CFG_CENTER_LOGIC_OUTS_B1_6", - "CFG_CENTER_LOGIC_OUTS_B1_7", - "CFG_CENTER_LOGIC_OUTS_B1_8", - "CFG_CENTER_LOGIC_OUTS_B1_9", - "CFG_CENTER_LOGIC_OUTS_B20_0", - "CFG_CENTER_LOGIC_OUTS_B20_1", - "CFG_CENTER_LOGIC_OUTS_B20_10", - "CFG_CENTER_LOGIC_OUTS_B20_11", - "CFG_CENTER_LOGIC_OUTS_B20_12", - "CFG_CENTER_LOGIC_OUTS_B20_13", - "CFG_CENTER_LOGIC_OUTS_B20_14", - "CFG_CENTER_LOGIC_OUTS_B20_15", - "CFG_CENTER_LOGIC_OUTS_B20_16", - "CFG_CENTER_LOGIC_OUTS_B20_17", - "CFG_CENTER_LOGIC_OUTS_B20_18", - "CFG_CENTER_LOGIC_OUTS_B20_19", - "CFG_CENTER_LOGIC_OUTS_B20_2", - "CFG_CENTER_LOGIC_OUTS_B20_3", - "CFG_CENTER_LOGIC_OUTS_B20_4", - "CFG_CENTER_LOGIC_OUTS_B20_5", - "CFG_CENTER_LOGIC_OUTS_B20_6", - "CFG_CENTER_LOGIC_OUTS_B20_7", - "CFG_CENTER_LOGIC_OUTS_B20_8", - "CFG_CENTER_LOGIC_OUTS_B20_9", - "CFG_CENTER_LOGIC_OUTS_B21_0", - "CFG_CENTER_LOGIC_OUTS_B21_1", - "CFG_CENTER_LOGIC_OUTS_B21_10", - "CFG_CENTER_LOGIC_OUTS_B21_11", - "CFG_CENTER_LOGIC_OUTS_B21_12", - "CFG_CENTER_LOGIC_OUTS_B21_13", - "CFG_CENTER_LOGIC_OUTS_B21_14", - "CFG_CENTER_LOGIC_OUTS_B21_15", - "CFG_CENTER_LOGIC_OUTS_B21_16", - "CFG_CENTER_LOGIC_OUTS_B21_17", - "CFG_CENTER_LOGIC_OUTS_B21_18", - "CFG_CENTER_LOGIC_OUTS_B21_19", - "CFG_CENTER_LOGIC_OUTS_B21_2", - "CFG_CENTER_LOGIC_OUTS_B21_3", - "CFG_CENTER_LOGIC_OUTS_B21_4", - "CFG_CENTER_LOGIC_OUTS_B21_5", - "CFG_CENTER_LOGIC_OUTS_B21_6", - "CFG_CENTER_LOGIC_OUTS_B21_7", - "CFG_CENTER_LOGIC_OUTS_B21_8", - "CFG_CENTER_LOGIC_OUTS_B21_9", - "CFG_CENTER_LOGIC_OUTS_B22_0", - "CFG_CENTER_LOGIC_OUTS_B22_1", - "CFG_CENTER_LOGIC_OUTS_B22_10", - "CFG_CENTER_LOGIC_OUTS_B22_11", - "CFG_CENTER_LOGIC_OUTS_B22_12", - "CFG_CENTER_LOGIC_OUTS_B22_13", - "CFG_CENTER_LOGIC_OUTS_B22_14", - "CFG_CENTER_LOGIC_OUTS_B22_15", - "CFG_CENTER_LOGIC_OUTS_B22_16", - "CFG_CENTER_LOGIC_OUTS_B22_17", - "CFG_CENTER_LOGIC_OUTS_B22_18", - "CFG_CENTER_LOGIC_OUTS_B22_19", - "CFG_CENTER_LOGIC_OUTS_B22_2", - "CFG_CENTER_LOGIC_OUTS_B22_3", - "CFG_CENTER_LOGIC_OUTS_B22_4", - "CFG_CENTER_LOGIC_OUTS_B22_5", - "CFG_CENTER_LOGIC_OUTS_B22_6", - "CFG_CENTER_LOGIC_OUTS_B22_7", - "CFG_CENTER_LOGIC_OUTS_B22_8", - "CFG_CENTER_LOGIC_OUTS_B22_9", - "CFG_CENTER_LOGIC_OUTS_B23_0", - "CFG_CENTER_LOGIC_OUTS_B23_1", - "CFG_CENTER_LOGIC_OUTS_B23_10", - "CFG_CENTER_LOGIC_OUTS_B23_11", - "CFG_CENTER_LOGIC_OUTS_B23_12", - "CFG_CENTER_LOGIC_OUTS_B23_13", - "CFG_CENTER_LOGIC_OUTS_B23_14", - "CFG_CENTER_LOGIC_OUTS_B23_15", - "CFG_CENTER_LOGIC_OUTS_B23_16", - "CFG_CENTER_LOGIC_OUTS_B23_17", - "CFG_CENTER_LOGIC_OUTS_B23_18", - "CFG_CENTER_LOGIC_OUTS_B23_19", - "CFG_CENTER_LOGIC_OUTS_B23_2", - "CFG_CENTER_LOGIC_OUTS_B23_3", - "CFG_CENTER_LOGIC_OUTS_B23_4", - "CFG_CENTER_LOGIC_OUTS_B23_5", - "CFG_CENTER_LOGIC_OUTS_B23_6", - "CFG_CENTER_LOGIC_OUTS_B23_7", - "CFG_CENTER_LOGIC_OUTS_B23_8", - "CFG_CENTER_LOGIC_OUTS_B23_9", - "CFG_CENTER_LOGIC_OUTS_B2_0", - "CFG_CENTER_LOGIC_OUTS_B2_1", - "CFG_CENTER_LOGIC_OUTS_B2_10", - "CFG_CENTER_LOGIC_OUTS_B2_11", - "CFG_CENTER_LOGIC_OUTS_B2_12", - "CFG_CENTER_LOGIC_OUTS_B2_13", - "CFG_CENTER_LOGIC_OUTS_B2_14", - "CFG_CENTER_LOGIC_OUTS_B2_15", - "CFG_CENTER_LOGIC_OUTS_B2_16", - "CFG_CENTER_LOGIC_OUTS_B2_17", - "CFG_CENTER_LOGIC_OUTS_B2_18", - "CFG_CENTER_LOGIC_OUTS_B2_19", - "CFG_CENTER_LOGIC_OUTS_B2_2", - "CFG_CENTER_LOGIC_OUTS_B2_3", - "CFG_CENTER_LOGIC_OUTS_B2_4", - "CFG_CENTER_LOGIC_OUTS_B2_5", - "CFG_CENTER_LOGIC_OUTS_B2_6", - "CFG_CENTER_LOGIC_OUTS_B2_7", - "CFG_CENTER_LOGIC_OUTS_B2_8", - "CFG_CENTER_LOGIC_OUTS_B2_9", - "CFG_CENTER_LOGIC_OUTS_B3_0", - "CFG_CENTER_LOGIC_OUTS_B3_1", - "CFG_CENTER_LOGIC_OUTS_B3_10", - "CFG_CENTER_LOGIC_OUTS_B3_11", - "CFG_CENTER_LOGIC_OUTS_B3_12", - "CFG_CENTER_LOGIC_OUTS_B3_13", - "CFG_CENTER_LOGIC_OUTS_B3_14", - "CFG_CENTER_LOGIC_OUTS_B3_15", - "CFG_CENTER_LOGIC_OUTS_B3_16", - "CFG_CENTER_LOGIC_OUTS_B3_17", - "CFG_CENTER_LOGIC_OUTS_B3_18", - "CFG_CENTER_LOGIC_OUTS_B3_19", - "CFG_CENTER_LOGIC_OUTS_B3_2", - "CFG_CENTER_LOGIC_OUTS_B3_3", - "CFG_CENTER_LOGIC_OUTS_B3_4", - "CFG_CENTER_LOGIC_OUTS_B3_5", - "CFG_CENTER_LOGIC_OUTS_B3_6", - "CFG_CENTER_LOGIC_OUTS_B3_7", - "CFG_CENTER_LOGIC_OUTS_B3_8", - "CFG_CENTER_LOGIC_OUTS_B3_9", - "CFG_CENTER_LOGIC_OUTS_B4_0", - "CFG_CENTER_LOGIC_OUTS_B4_1", - "CFG_CENTER_LOGIC_OUTS_B4_10", - "CFG_CENTER_LOGIC_OUTS_B4_11", - "CFG_CENTER_LOGIC_OUTS_B4_12", - "CFG_CENTER_LOGIC_OUTS_B4_13", - "CFG_CENTER_LOGIC_OUTS_B4_14", - "CFG_CENTER_LOGIC_OUTS_B4_15", - "CFG_CENTER_LOGIC_OUTS_B4_16", - "CFG_CENTER_LOGIC_OUTS_B4_17", - "CFG_CENTER_LOGIC_OUTS_B4_18", - "CFG_CENTER_LOGIC_OUTS_B4_19", - "CFG_CENTER_LOGIC_OUTS_B4_2", - "CFG_CENTER_LOGIC_OUTS_B4_3", - "CFG_CENTER_LOGIC_OUTS_B4_4", - "CFG_CENTER_LOGIC_OUTS_B4_5", - "CFG_CENTER_LOGIC_OUTS_B4_6", - "CFG_CENTER_LOGIC_OUTS_B4_7", - "CFG_CENTER_LOGIC_OUTS_B4_8", - "CFG_CENTER_LOGIC_OUTS_B4_9", - "CFG_CENTER_LOGIC_OUTS_B5_0", - "CFG_CENTER_LOGIC_OUTS_B5_1", - "CFG_CENTER_LOGIC_OUTS_B5_10", - "CFG_CENTER_LOGIC_OUTS_B5_11", - "CFG_CENTER_LOGIC_OUTS_B5_12", - "CFG_CENTER_LOGIC_OUTS_B5_13", - "CFG_CENTER_LOGIC_OUTS_B5_14", - "CFG_CENTER_LOGIC_OUTS_B5_15", - "CFG_CENTER_LOGIC_OUTS_B5_16", - "CFG_CENTER_LOGIC_OUTS_B5_17", - "CFG_CENTER_LOGIC_OUTS_B5_18", - "CFG_CENTER_LOGIC_OUTS_B5_19", - "CFG_CENTER_LOGIC_OUTS_B5_2", - "CFG_CENTER_LOGIC_OUTS_B5_3", - "CFG_CENTER_LOGIC_OUTS_B5_4", - "CFG_CENTER_LOGIC_OUTS_B5_5", - "CFG_CENTER_LOGIC_OUTS_B5_6", - "CFG_CENTER_LOGIC_OUTS_B5_7", - "CFG_CENTER_LOGIC_OUTS_B5_8", - "CFG_CENTER_LOGIC_OUTS_B5_9", - "CFG_CENTER_LOGIC_OUTS_B6_0", - "CFG_CENTER_LOGIC_OUTS_B6_1", - "CFG_CENTER_LOGIC_OUTS_B6_10", - "CFG_CENTER_LOGIC_OUTS_B6_11", - "CFG_CENTER_LOGIC_OUTS_B6_12", - "CFG_CENTER_LOGIC_OUTS_B6_13", - "CFG_CENTER_LOGIC_OUTS_B6_14", - "CFG_CENTER_LOGIC_OUTS_B6_15", - "CFG_CENTER_LOGIC_OUTS_B6_16", - "CFG_CENTER_LOGIC_OUTS_B6_17", - "CFG_CENTER_LOGIC_OUTS_B6_18", - "CFG_CENTER_LOGIC_OUTS_B6_19", - "CFG_CENTER_LOGIC_OUTS_B6_2", - "CFG_CENTER_LOGIC_OUTS_B6_3", - "CFG_CENTER_LOGIC_OUTS_B6_4", - "CFG_CENTER_LOGIC_OUTS_B6_5", - "CFG_CENTER_LOGIC_OUTS_B6_6", - "CFG_CENTER_LOGIC_OUTS_B6_7", - "CFG_CENTER_LOGIC_OUTS_B6_8", - "CFG_CENTER_LOGIC_OUTS_B6_9", - "CFG_CENTER_LOGIC_OUTS_B7_0", - "CFG_CENTER_LOGIC_OUTS_B7_1", - "CFG_CENTER_LOGIC_OUTS_B7_10", - "CFG_CENTER_LOGIC_OUTS_B7_11", - "CFG_CENTER_LOGIC_OUTS_B7_12", - "CFG_CENTER_LOGIC_OUTS_B7_13", - "CFG_CENTER_LOGIC_OUTS_B7_14", - "CFG_CENTER_LOGIC_OUTS_B7_15", - "CFG_CENTER_LOGIC_OUTS_B7_16", - "CFG_CENTER_LOGIC_OUTS_B7_17", - "CFG_CENTER_LOGIC_OUTS_B7_18", - "CFG_CENTER_LOGIC_OUTS_B7_19", - "CFG_CENTER_LOGIC_OUTS_B7_2", - "CFG_CENTER_LOGIC_OUTS_B7_3", - "CFG_CENTER_LOGIC_OUTS_B7_4", - "CFG_CENTER_LOGIC_OUTS_B7_5", - "CFG_CENTER_LOGIC_OUTS_B7_6", - "CFG_CENTER_LOGIC_OUTS_B7_7", - "CFG_CENTER_LOGIC_OUTS_B7_8", - "CFG_CENTER_LOGIC_OUTS_B7_9", - "CFG_CENTER_LOGIC_OUTS_B8_0", - "CFG_CENTER_LOGIC_OUTS_B8_1", - "CFG_CENTER_LOGIC_OUTS_B8_10", - "CFG_CENTER_LOGIC_OUTS_B8_11", - "CFG_CENTER_LOGIC_OUTS_B8_12", - "CFG_CENTER_LOGIC_OUTS_B8_13", - "CFG_CENTER_LOGIC_OUTS_B8_14", - "CFG_CENTER_LOGIC_OUTS_B8_15", - "CFG_CENTER_LOGIC_OUTS_B8_16", - "CFG_CENTER_LOGIC_OUTS_B8_17", - "CFG_CENTER_LOGIC_OUTS_B8_18", - "CFG_CENTER_LOGIC_OUTS_B8_19", - "CFG_CENTER_LOGIC_OUTS_B8_2", - "CFG_CENTER_LOGIC_OUTS_B8_3", - "CFG_CENTER_LOGIC_OUTS_B8_4", - "CFG_CENTER_LOGIC_OUTS_B8_5", - "CFG_CENTER_LOGIC_OUTS_B8_6", - "CFG_CENTER_LOGIC_OUTS_B8_7", - "CFG_CENTER_LOGIC_OUTS_B8_8", - "CFG_CENTER_LOGIC_OUTS_B8_9", - "CFG_CENTER_LOGIC_OUTS_B9_0", - "CFG_CENTER_LOGIC_OUTS_B9_1", - "CFG_CENTER_LOGIC_OUTS_B9_10", - "CFG_CENTER_LOGIC_OUTS_B9_11", - "CFG_CENTER_LOGIC_OUTS_B9_12", - "CFG_CENTER_LOGIC_OUTS_B9_13", - "CFG_CENTER_LOGIC_OUTS_B9_14", - "CFG_CENTER_LOGIC_OUTS_B9_15", - "CFG_CENTER_LOGIC_OUTS_B9_16", - "CFG_CENTER_LOGIC_OUTS_B9_17", - "CFG_CENTER_LOGIC_OUTS_B9_18", - "CFG_CENTER_LOGIC_OUTS_B9_19", - "CFG_CENTER_LOGIC_OUTS_B9_2", - "CFG_CENTER_LOGIC_OUTS_B9_3", - "CFG_CENTER_LOGIC_OUTS_B9_4", - "CFG_CENTER_LOGIC_OUTS_B9_5", - "CFG_CENTER_LOGIC_OUTS_B9_6", - "CFG_CENTER_LOGIC_OUTS_B9_7", - "CFG_CENTER_LOGIC_OUTS_B9_8", - "CFG_CENTER_LOGIC_OUTS_B9_9", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA11", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA12", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA13", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA14", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA15", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA16", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA17", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA18", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA19", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA20", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA21", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA22", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA23", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA24", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA25", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA26", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA27", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA28", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA29", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA30", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA31", - "CFG_CENTER_MID_CFG_IO_ACCESS_VGGCOMPOUT", - "CFG_CENTER_MID_DNA_PORT_CLK", - "CFG_CENTER_MID_ICAP1_CLK", - "CFG_CENTER_MID_USR_ACCESS_DATA10", - "CFG_CENTER_MID_USR_ACCESS_DATA11", - "CFG_CENTER_MID_USR_ACCESS_DATA12", - "CFG_CENTER_MID_USR_ACCESS_DATA13", - "CFG_CENTER_MID_USR_ACCESS_DATA14", - "CFG_CENTER_MID_USR_ACCESS_DATA2", - "CFG_CENTER_MID_USR_ACCESS_DATA3", - "CFG_CENTER_MID_USR_ACCESS_DATA4", - "CFG_CENTER_MID_USR_ACCESS_DATA5", - "CFG_CENTER_MID_USR_ACCESS_DATA6", - "CFG_CENTER_MID_USR_ACCESS_DATA7", - "CFG_CENTER_MID_USR_ACCESS_DATA8", - "CFG_CENTER_MID_USR_ACCESS_DATA9", - "CFG_CENTER_NE2A0_0", - "CFG_CENTER_NE2A0_1", - "CFG_CENTER_NE2A0_10", - "CFG_CENTER_NE2A0_11", - "CFG_CENTER_NE2A0_12", - "CFG_CENTER_NE2A0_13", - "CFG_CENTER_NE2A0_14", - "CFG_CENTER_NE2A0_15", - "CFG_CENTER_NE2A0_16", - "CFG_CENTER_NE2A0_17", - "CFG_CENTER_NE2A0_18", - "CFG_CENTER_NE2A0_19", - "CFG_CENTER_NE2A0_2", - "CFG_CENTER_NE2A0_3", - "CFG_CENTER_NE2A0_4", - "CFG_CENTER_NE2A0_5", - "CFG_CENTER_NE2A0_6", - "CFG_CENTER_NE2A0_7", - "CFG_CENTER_NE2A0_8", - "CFG_CENTER_NE2A0_9", - "CFG_CENTER_NE2A1_0", - "CFG_CENTER_NE2A1_1", - "CFG_CENTER_NE2A1_10", - "CFG_CENTER_NE2A1_11", - "CFG_CENTER_NE2A1_12", - "CFG_CENTER_NE2A1_13", - "CFG_CENTER_NE2A1_14", - "CFG_CENTER_NE2A1_15", - "CFG_CENTER_NE2A1_16", - "CFG_CENTER_NE2A1_17", - "CFG_CENTER_NE2A1_18", - "CFG_CENTER_NE2A1_19", - "CFG_CENTER_NE2A1_2", - "CFG_CENTER_NE2A1_3", - "CFG_CENTER_NE2A1_4", - "CFG_CENTER_NE2A1_5", - "CFG_CENTER_NE2A1_6", - "CFG_CENTER_NE2A1_7", - "CFG_CENTER_NE2A1_8", - "CFG_CENTER_NE2A1_9", - "CFG_CENTER_NE2A2_0", - "CFG_CENTER_NE2A2_1", - "CFG_CENTER_NE2A2_10", - "CFG_CENTER_NE2A2_11", - "CFG_CENTER_NE2A2_12", - "CFG_CENTER_NE2A2_13", - "CFG_CENTER_NE2A2_14", - "CFG_CENTER_NE2A2_15", - "CFG_CENTER_NE2A2_16", - "CFG_CENTER_NE2A2_17", - "CFG_CENTER_NE2A2_18", - "CFG_CENTER_NE2A2_19", - "CFG_CENTER_NE2A2_2", - "CFG_CENTER_NE2A2_3", - "CFG_CENTER_NE2A2_4", - "CFG_CENTER_NE2A2_5", - "CFG_CENTER_NE2A2_6", - "CFG_CENTER_NE2A2_7", - "CFG_CENTER_NE2A2_8", - "CFG_CENTER_NE2A2_9", - "CFG_CENTER_NE2A3_0", - "CFG_CENTER_NE2A3_1", - "CFG_CENTER_NE2A3_10", - "CFG_CENTER_NE2A3_11", - "CFG_CENTER_NE2A3_12", - "CFG_CENTER_NE2A3_13", - "CFG_CENTER_NE2A3_14", - "CFG_CENTER_NE2A3_15", - "CFG_CENTER_NE2A3_16", - "CFG_CENTER_NE2A3_17", - "CFG_CENTER_NE2A3_18", - "CFG_CENTER_NE2A3_19", - "CFG_CENTER_NE2A3_2", - "CFG_CENTER_NE2A3_3", - "CFG_CENTER_NE2A3_4", - "CFG_CENTER_NE2A3_5", - "CFG_CENTER_NE2A3_6", - "CFG_CENTER_NE2A3_7", - "CFG_CENTER_NE2A3_8", - "CFG_CENTER_NE2A3_9", - "CFG_CENTER_NE4BEG0_0", - "CFG_CENTER_NE4BEG0_1", - "CFG_CENTER_NE4BEG0_10", - "CFG_CENTER_NE4BEG0_11", - "CFG_CENTER_NE4BEG0_12", - "CFG_CENTER_NE4BEG0_13", - "CFG_CENTER_NE4BEG0_14", - "CFG_CENTER_NE4BEG0_15", - "CFG_CENTER_NE4BEG0_16", - "CFG_CENTER_NE4BEG0_17", - "CFG_CENTER_NE4BEG0_18", - "CFG_CENTER_NE4BEG0_19", - "CFG_CENTER_NE4BEG0_2", - "CFG_CENTER_NE4BEG0_3", - "CFG_CENTER_NE4BEG0_4", - "CFG_CENTER_NE4BEG0_5", - "CFG_CENTER_NE4BEG0_6", - "CFG_CENTER_NE4BEG0_7", - "CFG_CENTER_NE4BEG0_8", - "CFG_CENTER_NE4BEG0_9", - "CFG_CENTER_NE4BEG1_0", - "CFG_CENTER_NE4BEG1_1", - "CFG_CENTER_NE4BEG1_10", - "CFG_CENTER_NE4BEG1_11", - "CFG_CENTER_NE4BEG1_12", - "CFG_CENTER_NE4BEG1_13", - "CFG_CENTER_NE4BEG1_14", - "CFG_CENTER_NE4BEG1_15", - "CFG_CENTER_NE4BEG1_16", - "CFG_CENTER_NE4BEG1_17", - "CFG_CENTER_NE4BEG1_18", - "CFG_CENTER_NE4BEG1_19", - "CFG_CENTER_NE4BEG1_2", - "CFG_CENTER_NE4BEG1_3", - "CFG_CENTER_NE4BEG1_4", - "CFG_CENTER_NE4BEG1_5", - "CFG_CENTER_NE4BEG1_6", - "CFG_CENTER_NE4BEG1_7", - "CFG_CENTER_NE4BEG1_8", - "CFG_CENTER_NE4BEG1_9", - "CFG_CENTER_NE4BEG2_0", - "CFG_CENTER_NE4BEG2_1", - "CFG_CENTER_NE4BEG2_10", - "CFG_CENTER_NE4BEG2_11", - "CFG_CENTER_NE4BEG2_12", - "CFG_CENTER_NE4BEG2_13", - "CFG_CENTER_NE4BEG2_14", - "CFG_CENTER_NE4BEG2_15", - "CFG_CENTER_NE4BEG2_16", - "CFG_CENTER_NE4BEG2_17", - "CFG_CENTER_NE4BEG2_18", - "CFG_CENTER_NE4BEG2_19", - "CFG_CENTER_NE4BEG2_2", - "CFG_CENTER_NE4BEG2_3", - "CFG_CENTER_NE4BEG2_4", - "CFG_CENTER_NE4BEG2_5", - "CFG_CENTER_NE4BEG2_6", - "CFG_CENTER_NE4BEG2_7", - "CFG_CENTER_NE4BEG2_8", - "CFG_CENTER_NE4BEG2_9", - "CFG_CENTER_NE4BEG3_0", - "CFG_CENTER_NE4BEG3_1", - "CFG_CENTER_NE4BEG3_10", - "CFG_CENTER_NE4BEG3_11", - "CFG_CENTER_NE4BEG3_12", - "CFG_CENTER_NE4BEG3_13", - "CFG_CENTER_NE4BEG3_14", - "CFG_CENTER_NE4BEG3_15", - "CFG_CENTER_NE4BEG3_16", - "CFG_CENTER_NE4BEG3_17", - "CFG_CENTER_NE4BEG3_18", - "CFG_CENTER_NE4BEG3_19", - "CFG_CENTER_NE4BEG3_2", - "CFG_CENTER_NE4BEG3_3", - "CFG_CENTER_NE4BEG3_4", - "CFG_CENTER_NE4BEG3_5", - "CFG_CENTER_NE4BEG3_6", - "CFG_CENTER_NE4BEG3_7", - "CFG_CENTER_NE4BEG3_8", - "CFG_CENTER_NE4BEG3_9", - "CFG_CENTER_NE4C0_0", - "CFG_CENTER_NE4C0_1", - "CFG_CENTER_NE4C0_10", - "CFG_CENTER_NE4C0_11", - "CFG_CENTER_NE4C0_12", - "CFG_CENTER_NE4C0_13", - "CFG_CENTER_NE4C0_14", - "CFG_CENTER_NE4C0_15", - "CFG_CENTER_NE4C0_16", - "CFG_CENTER_NE4C0_17", - "CFG_CENTER_NE4C0_18", - "CFG_CENTER_NE4C0_19", - "CFG_CENTER_NE4C0_2", - "CFG_CENTER_NE4C0_3", - "CFG_CENTER_NE4C0_4", - "CFG_CENTER_NE4C0_5", - "CFG_CENTER_NE4C0_6", - "CFG_CENTER_NE4C0_7", - "CFG_CENTER_NE4C0_8", - "CFG_CENTER_NE4C0_9", - "CFG_CENTER_NE4C1_0", - "CFG_CENTER_NE4C1_1", - "CFG_CENTER_NE4C1_10", - "CFG_CENTER_NE4C1_11", - "CFG_CENTER_NE4C1_12", - "CFG_CENTER_NE4C1_13", - "CFG_CENTER_NE4C1_14", - "CFG_CENTER_NE4C1_15", - "CFG_CENTER_NE4C1_16", - "CFG_CENTER_NE4C1_17", - "CFG_CENTER_NE4C1_18", - "CFG_CENTER_NE4C1_19", - "CFG_CENTER_NE4C1_2", - "CFG_CENTER_NE4C1_3", - "CFG_CENTER_NE4C1_4", - "CFG_CENTER_NE4C1_5", - "CFG_CENTER_NE4C1_6", - "CFG_CENTER_NE4C1_7", - "CFG_CENTER_NE4C1_8", - "CFG_CENTER_NE4C1_9", - "CFG_CENTER_NE4C2_0", - "CFG_CENTER_NE4C2_1", - "CFG_CENTER_NE4C2_10", - "CFG_CENTER_NE4C2_11", - "CFG_CENTER_NE4C2_12", - "CFG_CENTER_NE4C2_13", - "CFG_CENTER_NE4C2_14", - "CFG_CENTER_NE4C2_15", - "CFG_CENTER_NE4C2_16", - "CFG_CENTER_NE4C2_17", - "CFG_CENTER_NE4C2_18", - "CFG_CENTER_NE4C2_19", - "CFG_CENTER_NE4C2_2", - "CFG_CENTER_NE4C2_3", - "CFG_CENTER_NE4C2_4", - "CFG_CENTER_NE4C2_5", - "CFG_CENTER_NE4C2_6", - "CFG_CENTER_NE4C2_7", - "CFG_CENTER_NE4C2_8", - "CFG_CENTER_NE4C2_9", - "CFG_CENTER_NE4C3_0", - "CFG_CENTER_NE4C3_1", - "CFG_CENTER_NE4C3_10", - "CFG_CENTER_NE4C3_11", - "CFG_CENTER_NE4C3_12", - "CFG_CENTER_NE4C3_13", - "CFG_CENTER_NE4C3_14", - "CFG_CENTER_NE4C3_15", - "CFG_CENTER_NE4C3_16", - "CFG_CENTER_NE4C3_17", - "CFG_CENTER_NE4C3_18", - "CFG_CENTER_NE4C3_19", - "CFG_CENTER_NE4C3_2", - "CFG_CENTER_NE4C3_3", - "CFG_CENTER_NE4C3_4", - "CFG_CENTER_NE4C3_5", - "CFG_CENTER_NE4C3_6", - "CFG_CENTER_NE4C3_7", - "CFG_CENTER_NE4C3_8", - "CFG_CENTER_NE4C3_9", - "CFG_CENTER_NW2A0_0", - "CFG_CENTER_NW2A0_1", - "CFG_CENTER_NW2A0_10", - "CFG_CENTER_NW2A0_11", - "CFG_CENTER_NW2A0_12", - "CFG_CENTER_NW2A0_13", - "CFG_CENTER_NW2A0_14", - "CFG_CENTER_NW2A0_15", - "CFG_CENTER_NW2A0_16", - "CFG_CENTER_NW2A0_17", - "CFG_CENTER_NW2A0_18", - "CFG_CENTER_NW2A0_19", - "CFG_CENTER_NW2A0_2", - "CFG_CENTER_NW2A0_3", - "CFG_CENTER_NW2A0_4", - "CFG_CENTER_NW2A0_5", - "CFG_CENTER_NW2A0_6", - "CFG_CENTER_NW2A0_7", - "CFG_CENTER_NW2A0_8", - "CFG_CENTER_NW2A0_9", - "CFG_CENTER_NW2A1_0", - "CFG_CENTER_NW2A1_1", - "CFG_CENTER_NW2A1_10", - "CFG_CENTER_NW2A1_11", - "CFG_CENTER_NW2A1_12", - "CFG_CENTER_NW2A1_13", - "CFG_CENTER_NW2A1_14", - "CFG_CENTER_NW2A1_15", - "CFG_CENTER_NW2A1_16", - "CFG_CENTER_NW2A1_17", - "CFG_CENTER_NW2A1_18", - "CFG_CENTER_NW2A1_19", - "CFG_CENTER_NW2A1_2", - "CFG_CENTER_NW2A1_3", - "CFG_CENTER_NW2A1_4", - "CFG_CENTER_NW2A1_5", - "CFG_CENTER_NW2A1_6", - "CFG_CENTER_NW2A1_7", - "CFG_CENTER_NW2A1_8", - "CFG_CENTER_NW2A1_9", - "CFG_CENTER_NW2A2_0", - "CFG_CENTER_NW2A2_1", - "CFG_CENTER_NW2A2_10", - "CFG_CENTER_NW2A2_11", - "CFG_CENTER_NW2A2_12", - "CFG_CENTER_NW2A2_13", - "CFG_CENTER_NW2A2_14", - "CFG_CENTER_NW2A2_15", - "CFG_CENTER_NW2A2_16", - "CFG_CENTER_NW2A2_17", - "CFG_CENTER_NW2A2_18", - "CFG_CENTER_NW2A2_19", - "CFG_CENTER_NW2A2_2", - "CFG_CENTER_NW2A2_3", - "CFG_CENTER_NW2A2_4", - "CFG_CENTER_NW2A2_5", - "CFG_CENTER_NW2A2_6", - "CFG_CENTER_NW2A2_7", - "CFG_CENTER_NW2A2_8", - "CFG_CENTER_NW2A2_9", - "CFG_CENTER_NW2A3_0", - "CFG_CENTER_NW2A3_1", - "CFG_CENTER_NW2A3_10", - "CFG_CENTER_NW2A3_11", - "CFG_CENTER_NW2A3_12", - "CFG_CENTER_NW2A3_13", - "CFG_CENTER_NW2A3_14", - "CFG_CENTER_NW2A3_15", - "CFG_CENTER_NW2A3_16", - "CFG_CENTER_NW2A3_17", - "CFG_CENTER_NW2A3_18", - "CFG_CENTER_NW2A3_19", - "CFG_CENTER_NW2A3_2", - "CFG_CENTER_NW2A3_3", - "CFG_CENTER_NW2A3_4", - "CFG_CENTER_NW2A3_5", - "CFG_CENTER_NW2A3_6", - "CFG_CENTER_NW2A3_7", - "CFG_CENTER_NW2A3_8", - "CFG_CENTER_NW2A3_9", - "CFG_CENTER_NW4A0_0", - "CFG_CENTER_NW4A0_1", - "CFG_CENTER_NW4A0_10", - "CFG_CENTER_NW4A0_11", - "CFG_CENTER_NW4A0_12", - "CFG_CENTER_NW4A0_13", - "CFG_CENTER_NW4A0_14", - "CFG_CENTER_NW4A0_15", - "CFG_CENTER_NW4A0_16", - "CFG_CENTER_NW4A0_17", - "CFG_CENTER_NW4A0_18", - "CFG_CENTER_NW4A0_19", - "CFG_CENTER_NW4A0_2", - "CFG_CENTER_NW4A0_3", - "CFG_CENTER_NW4A0_4", - "CFG_CENTER_NW4A0_5", - "CFG_CENTER_NW4A0_6", - "CFG_CENTER_NW4A0_7", - "CFG_CENTER_NW4A0_8", - "CFG_CENTER_NW4A0_9", - "CFG_CENTER_NW4A1_0", - "CFG_CENTER_NW4A1_1", - "CFG_CENTER_NW4A1_10", - "CFG_CENTER_NW4A1_11", - "CFG_CENTER_NW4A1_12", - "CFG_CENTER_NW4A1_13", - "CFG_CENTER_NW4A1_14", - "CFG_CENTER_NW4A1_15", - "CFG_CENTER_NW4A1_16", - "CFG_CENTER_NW4A1_17", - "CFG_CENTER_NW4A1_18", - "CFG_CENTER_NW4A1_19", - "CFG_CENTER_NW4A1_2", - "CFG_CENTER_NW4A1_3", - "CFG_CENTER_NW4A1_4", - "CFG_CENTER_NW4A1_5", - "CFG_CENTER_NW4A1_6", - "CFG_CENTER_NW4A1_7", - "CFG_CENTER_NW4A1_8", - "CFG_CENTER_NW4A1_9", - "CFG_CENTER_NW4A2_0", - "CFG_CENTER_NW4A2_1", - "CFG_CENTER_NW4A2_10", - "CFG_CENTER_NW4A2_11", - "CFG_CENTER_NW4A2_12", - "CFG_CENTER_NW4A2_13", - "CFG_CENTER_NW4A2_14", - "CFG_CENTER_NW4A2_15", - "CFG_CENTER_NW4A2_16", - "CFG_CENTER_NW4A2_17", - "CFG_CENTER_NW4A2_18", - "CFG_CENTER_NW4A2_19", - "CFG_CENTER_NW4A2_2", - "CFG_CENTER_NW4A2_3", - "CFG_CENTER_NW4A2_4", - "CFG_CENTER_NW4A2_5", - "CFG_CENTER_NW4A2_6", - "CFG_CENTER_NW4A2_7", - "CFG_CENTER_NW4A2_8", - "CFG_CENTER_NW4A2_9", - "CFG_CENTER_NW4A3_0", - "CFG_CENTER_NW4A3_1", - "CFG_CENTER_NW4A3_10", - "CFG_CENTER_NW4A3_11", - "CFG_CENTER_NW4A3_12", - "CFG_CENTER_NW4A3_13", - "CFG_CENTER_NW4A3_14", - "CFG_CENTER_NW4A3_15", - "CFG_CENTER_NW4A3_16", - "CFG_CENTER_NW4A3_17", - "CFG_CENTER_NW4A3_18", - "CFG_CENTER_NW4A3_19", - "CFG_CENTER_NW4A3_2", - "CFG_CENTER_NW4A3_3", - "CFG_CENTER_NW4A3_4", - "CFG_CENTER_NW4A3_5", - "CFG_CENTER_NW4A3_6", - "CFG_CENTER_NW4A3_7", - "CFG_CENTER_NW4A3_8", - "CFG_CENTER_NW4A3_9", - "CFG_CENTER_NW4END0_0", - "CFG_CENTER_NW4END0_1", - "CFG_CENTER_NW4END0_10", - "CFG_CENTER_NW4END0_11", - "CFG_CENTER_NW4END0_12", - "CFG_CENTER_NW4END0_13", - "CFG_CENTER_NW4END0_14", - "CFG_CENTER_NW4END0_15", - "CFG_CENTER_NW4END0_16", - "CFG_CENTER_NW4END0_17", - "CFG_CENTER_NW4END0_18", - "CFG_CENTER_NW4END0_19", - "CFG_CENTER_NW4END0_2", - "CFG_CENTER_NW4END0_3", - "CFG_CENTER_NW4END0_4", - "CFG_CENTER_NW4END0_5", - "CFG_CENTER_NW4END0_6", - "CFG_CENTER_NW4END0_7", - "CFG_CENTER_NW4END0_8", - "CFG_CENTER_NW4END0_9", - "CFG_CENTER_NW4END1_0", - "CFG_CENTER_NW4END1_1", - "CFG_CENTER_NW4END1_10", - "CFG_CENTER_NW4END1_11", - "CFG_CENTER_NW4END1_12", - "CFG_CENTER_NW4END1_13", - "CFG_CENTER_NW4END1_14", - "CFG_CENTER_NW4END1_15", - "CFG_CENTER_NW4END1_16", - "CFG_CENTER_NW4END1_17", - "CFG_CENTER_NW4END1_18", - "CFG_CENTER_NW4END1_19", - "CFG_CENTER_NW4END1_2", - "CFG_CENTER_NW4END1_3", - "CFG_CENTER_NW4END1_4", - "CFG_CENTER_NW4END1_5", - "CFG_CENTER_NW4END1_6", - "CFG_CENTER_NW4END1_7", - "CFG_CENTER_NW4END1_8", - "CFG_CENTER_NW4END1_9", - "CFG_CENTER_NW4END2_0", - "CFG_CENTER_NW4END2_1", - "CFG_CENTER_NW4END2_10", - "CFG_CENTER_NW4END2_11", - "CFG_CENTER_NW4END2_12", - "CFG_CENTER_NW4END2_13", - "CFG_CENTER_NW4END2_14", - "CFG_CENTER_NW4END2_15", - "CFG_CENTER_NW4END2_16", - "CFG_CENTER_NW4END2_17", - "CFG_CENTER_NW4END2_18", - "CFG_CENTER_NW4END2_19", - "CFG_CENTER_NW4END2_2", - "CFG_CENTER_NW4END2_3", - "CFG_CENTER_NW4END2_4", - "CFG_CENTER_NW4END2_5", - "CFG_CENTER_NW4END2_6", - "CFG_CENTER_NW4END2_7", - "CFG_CENTER_NW4END2_8", - "CFG_CENTER_NW4END2_9", - "CFG_CENTER_NW4END3_0", - "CFG_CENTER_NW4END3_1", - "CFG_CENTER_NW4END3_10", - "CFG_CENTER_NW4END3_11", - "CFG_CENTER_NW4END3_12", - "CFG_CENTER_NW4END3_13", - "CFG_CENTER_NW4END3_14", - "CFG_CENTER_NW4END3_15", - "CFG_CENTER_NW4END3_16", - "CFG_CENTER_NW4END3_17", - "CFG_CENTER_NW4END3_18", - "CFG_CENTER_NW4END3_19", - "CFG_CENTER_NW4END3_2", - "CFG_CENTER_NW4END3_3", - "CFG_CENTER_NW4END3_4", - "CFG_CENTER_NW4END3_5", - "CFG_CENTER_NW4END3_6", - "CFG_CENTER_NW4END3_7", - "CFG_CENTER_NW4END3_8", - "CFG_CENTER_NW4END3_9", - "CFG_CENTER_PMVIOB_A0", - "CFG_CENTER_PMVIOB_A1", - "CFG_CENTER_PMVIOB_EN", - "CFG_CENTER_PMVIOB_O", - "CFG_CENTER_PMVIOB_ODIV2", - "CFG_CENTER_PMVIOB_ODIV4", - "CFG_CENTER_SE2A0_0", - "CFG_CENTER_SE2A0_1", - "CFG_CENTER_SE2A0_10", - "CFG_CENTER_SE2A0_11", - "CFG_CENTER_SE2A0_12", - "CFG_CENTER_SE2A0_13", - "CFG_CENTER_SE2A0_14", - "CFG_CENTER_SE2A0_15", - "CFG_CENTER_SE2A0_16", - "CFG_CENTER_SE2A0_17", - "CFG_CENTER_SE2A0_18", - "CFG_CENTER_SE2A0_19", - "CFG_CENTER_SE2A0_2", - "CFG_CENTER_SE2A0_3", - "CFG_CENTER_SE2A0_4", - "CFG_CENTER_SE2A0_5", - "CFG_CENTER_SE2A0_6", - "CFG_CENTER_SE2A0_7", - "CFG_CENTER_SE2A0_8", - "CFG_CENTER_SE2A0_9", - "CFG_CENTER_SE2A1_0", - "CFG_CENTER_SE2A1_1", - "CFG_CENTER_SE2A1_10", - "CFG_CENTER_SE2A1_11", - "CFG_CENTER_SE2A1_12", - "CFG_CENTER_SE2A1_13", - "CFG_CENTER_SE2A1_14", - "CFG_CENTER_SE2A1_15", - "CFG_CENTER_SE2A1_16", - "CFG_CENTER_SE2A1_17", - "CFG_CENTER_SE2A1_18", - "CFG_CENTER_SE2A1_19", - "CFG_CENTER_SE2A1_2", - "CFG_CENTER_SE2A1_3", - "CFG_CENTER_SE2A1_4", - "CFG_CENTER_SE2A1_5", - "CFG_CENTER_SE2A1_6", - "CFG_CENTER_SE2A1_7", - "CFG_CENTER_SE2A1_8", - "CFG_CENTER_SE2A1_9", - "CFG_CENTER_SE2A2_0", - "CFG_CENTER_SE2A2_1", - "CFG_CENTER_SE2A2_10", - "CFG_CENTER_SE2A2_11", - "CFG_CENTER_SE2A2_12", - "CFG_CENTER_SE2A2_13", - "CFG_CENTER_SE2A2_14", - "CFG_CENTER_SE2A2_15", - "CFG_CENTER_SE2A2_16", - "CFG_CENTER_SE2A2_17", - "CFG_CENTER_SE2A2_18", - "CFG_CENTER_SE2A2_19", - "CFG_CENTER_SE2A2_2", - "CFG_CENTER_SE2A2_3", - "CFG_CENTER_SE2A2_4", - "CFG_CENTER_SE2A2_5", - "CFG_CENTER_SE2A2_6", - "CFG_CENTER_SE2A2_7", - "CFG_CENTER_SE2A2_8", - "CFG_CENTER_SE2A2_9", - "CFG_CENTER_SE2A3_0", - "CFG_CENTER_SE2A3_1", - "CFG_CENTER_SE2A3_10", - "CFG_CENTER_SE2A3_11", - "CFG_CENTER_SE2A3_12", - "CFG_CENTER_SE2A3_13", - "CFG_CENTER_SE2A3_14", - "CFG_CENTER_SE2A3_15", - "CFG_CENTER_SE2A3_16", - "CFG_CENTER_SE2A3_17", - "CFG_CENTER_SE2A3_18", - "CFG_CENTER_SE2A3_19", - "CFG_CENTER_SE2A3_2", - "CFG_CENTER_SE2A3_3", - "CFG_CENTER_SE2A3_4", - "CFG_CENTER_SE2A3_5", - "CFG_CENTER_SE2A3_6", - "CFG_CENTER_SE2A3_7", - "CFG_CENTER_SE2A3_8", - "CFG_CENTER_SE2A3_9", - "CFG_CENTER_SE4BEG0_0", - "CFG_CENTER_SE4BEG0_1", - "CFG_CENTER_SE4BEG0_10", - "CFG_CENTER_SE4BEG0_11", - "CFG_CENTER_SE4BEG0_12", - "CFG_CENTER_SE4BEG0_13", - "CFG_CENTER_SE4BEG0_14", - "CFG_CENTER_SE4BEG0_15", - "CFG_CENTER_SE4BEG0_16", - "CFG_CENTER_SE4BEG0_17", - "CFG_CENTER_SE4BEG0_18", - "CFG_CENTER_SE4BEG0_19", - "CFG_CENTER_SE4BEG0_2", - "CFG_CENTER_SE4BEG0_3", - "CFG_CENTER_SE4BEG0_4", - "CFG_CENTER_SE4BEG0_5", - "CFG_CENTER_SE4BEG0_6", - "CFG_CENTER_SE4BEG0_7", - "CFG_CENTER_SE4BEG0_8", - "CFG_CENTER_SE4BEG0_9", - "CFG_CENTER_SE4BEG1_0", - "CFG_CENTER_SE4BEG1_1", - "CFG_CENTER_SE4BEG1_10", - "CFG_CENTER_SE4BEG1_11", - "CFG_CENTER_SE4BEG1_12", - "CFG_CENTER_SE4BEG1_13", - "CFG_CENTER_SE4BEG1_14", - "CFG_CENTER_SE4BEG1_15", - "CFG_CENTER_SE4BEG1_16", - "CFG_CENTER_SE4BEG1_17", - "CFG_CENTER_SE4BEG1_18", - "CFG_CENTER_SE4BEG1_19", - "CFG_CENTER_SE4BEG1_2", - "CFG_CENTER_SE4BEG1_3", - "CFG_CENTER_SE4BEG1_4", - "CFG_CENTER_SE4BEG1_5", - "CFG_CENTER_SE4BEG1_6", - "CFG_CENTER_SE4BEG1_7", - "CFG_CENTER_SE4BEG1_8", - "CFG_CENTER_SE4BEG1_9", - "CFG_CENTER_SE4BEG2_0", - "CFG_CENTER_SE4BEG2_1", - "CFG_CENTER_SE4BEG2_10", - "CFG_CENTER_SE4BEG2_11", - "CFG_CENTER_SE4BEG2_12", - "CFG_CENTER_SE4BEG2_13", - "CFG_CENTER_SE4BEG2_14", - "CFG_CENTER_SE4BEG2_15", - "CFG_CENTER_SE4BEG2_16", - "CFG_CENTER_SE4BEG2_17", - "CFG_CENTER_SE4BEG2_18", - "CFG_CENTER_SE4BEG2_19", - "CFG_CENTER_SE4BEG2_2", - "CFG_CENTER_SE4BEG2_3", - "CFG_CENTER_SE4BEG2_4", - "CFG_CENTER_SE4BEG2_5", - "CFG_CENTER_SE4BEG2_6", - "CFG_CENTER_SE4BEG2_7", - "CFG_CENTER_SE4BEG2_8", - "CFG_CENTER_SE4BEG2_9", - "CFG_CENTER_SE4BEG3_0", - "CFG_CENTER_SE4BEG3_1", - "CFG_CENTER_SE4BEG3_10", - "CFG_CENTER_SE4BEG3_11", - "CFG_CENTER_SE4BEG3_12", - "CFG_CENTER_SE4BEG3_13", - "CFG_CENTER_SE4BEG3_14", - "CFG_CENTER_SE4BEG3_15", - "CFG_CENTER_SE4BEG3_16", - "CFG_CENTER_SE4BEG3_17", - "CFG_CENTER_SE4BEG3_18", - "CFG_CENTER_SE4BEG3_19", - "CFG_CENTER_SE4BEG3_2", - "CFG_CENTER_SE4BEG3_3", - "CFG_CENTER_SE4BEG3_4", - "CFG_CENTER_SE4BEG3_5", - "CFG_CENTER_SE4BEG3_6", - "CFG_CENTER_SE4BEG3_7", - "CFG_CENTER_SE4BEG3_8", - "CFG_CENTER_SE4BEG3_9", - "CFG_CENTER_SE4C0_0", - "CFG_CENTER_SE4C0_1", - "CFG_CENTER_SE4C0_10", - "CFG_CENTER_SE4C0_11", - "CFG_CENTER_SE4C0_12", - "CFG_CENTER_SE4C0_13", - "CFG_CENTER_SE4C0_14", - "CFG_CENTER_SE4C0_15", - "CFG_CENTER_SE4C0_16", - "CFG_CENTER_SE4C0_17", - "CFG_CENTER_SE4C0_18", - "CFG_CENTER_SE4C0_19", - "CFG_CENTER_SE4C0_2", - "CFG_CENTER_SE4C0_3", - "CFG_CENTER_SE4C0_4", - "CFG_CENTER_SE4C0_5", - "CFG_CENTER_SE4C0_6", - "CFG_CENTER_SE4C0_7", - "CFG_CENTER_SE4C0_8", - "CFG_CENTER_SE4C0_9", - "CFG_CENTER_SE4C1_0", - "CFG_CENTER_SE4C1_1", - "CFG_CENTER_SE4C1_10", - "CFG_CENTER_SE4C1_11", - "CFG_CENTER_SE4C1_12", - "CFG_CENTER_SE4C1_13", - "CFG_CENTER_SE4C1_14", - "CFG_CENTER_SE4C1_15", - "CFG_CENTER_SE4C1_16", - "CFG_CENTER_SE4C1_17", - "CFG_CENTER_SE4C1_18", - "CFG_CENTER_SE4C1_19", - "CFG_CENTER_SE4C1_2", - "CFG_CENTER_SE4C1_3", - "CFG_CENTER_SE4C1_4", - "CFG_CENTER_SE4C1_5", - "CFG_CENTER_SE4C1_6", - "CFG_CENTER_SE4C1_7", - "CFG_CENTER_SE4C1_8", - "CFG_CENTER_SE4C1_9", - "CFG_CENTER_SE4C2_0", - "CFG_CENTER_SE4C2_1", - "CFG_CENTER_SE4C2_10", - "CFG_CENTER_SE4C2_11", - "CFG_CENTER_SE4C2_12", - "CFG_CENTER_SE4C2_13", - "CFG_CENTER_SE4C2_14", - "CFG_CENTER_SE4C2_15", - "CFG_CENTER_SE4C2_16", - "CFG_CENTER_SE4C2_17", - "CFG_CENTER_SE4C2_18", - "CFG_CENTER_SE4C2_19", - "CFG_CENTER_SE4C2_2", - "CFG_CENTER_SE4C2_3", - "CFG_CENTER_SE4C2_4", - "CFG_CENTER_SE4C2_5", - "CFG_CENTER_SE4C2_6", - "CFG_CENTER_SE4C2_7", - "CFG_CENTER_SE4C2_8", - "CFG_CENTER_SE4C2_9", - "CFG_CENTER_SE4C3_0", - "CFG_CENTER_SE4C3_1", - "CFG_CENTER_SE4C3_10", - "CFG_CENTER_SE4C3_11", - "CFG_CENTER_SE4C3_12", - "CFG_CENTER_SE4C3_13", - "CFG_CENTER_SE4C3_14", - "CFG_CENTER_SE4C3_15", - "CFG_CENTER_SE4C3_16", - "CFG_CENTER_SE4C3_17", - "CFG_CENTER_SE4C3_18", - "CFG_CENTER_SE4C3_19", - "CFG_CENTER_SE4C3_2", - "CFG_CENTER_SE4C3_3", - "CFG_CENTER_SE4C3_4", - "CFG_CENTER_SE4C3_5", - "CFG_CENTER_SE4C3_6", - "CFG_CENTER_SE4C3_7", - "CFG_CENTER_SE4C3_8", - "CFG_CENTER_SE4C3_9", - "CFG_CENTER_STARTUP_CFGCLK", - "CFG_CENTER_STARTUP_CFGMCLK", - "CFG_CENTER_STARTUP_CLK", - "CFG_CENTER_STARTUP_EOS", - "CFG_CENTER_STARTUP_GSR", - "CFG_CENTER_STARTUP_GTS", - "CFG_CENTER_STARTUP_KEYCLEARB", - "CFG_CENTER_STARTUP_PACK", - "CFG_CENTER_STARTUP_PREQ", - "CFG_CENTER_STARTUP_USRCCLKO", - "CFG_CENTER_STARTUP_USRCCLKTS", - "CFG_CENTER_STARTUP_USRDONEO", - "CFG_CENTER_STARTUP_USRDONETS", - "CFG_CENTER_SW2A0_0", - "CFG_CENTER_SW2A0_1", - "CFG_CENTER_SW2A0_10", - "CFG_CENTER_SW2A0_11", - "CFG_CENTER_SW2A0_12", - "CFG_CENTER_SW2A0_13", - "CFG_CENTER_SW2A0_14", - "CFG_CENTER_SW2A0_15", - "CFG_CENTER_SW2A0_16", - "CFG_CENTER_SW2A0_17", - "CFG_CENTER_SW2A0_18", - "CFG_CENTER_SW2A0_19", - "CFG_CENTER_SW2A0_2", - "CFG_CENTER_SW2A0_3", - "CFG_CENTER_SW2A0_4", - "CFG_CENTER_SW2A0_5", - "CFG_CENTER_SW2A0_6", - "CFG_CENTER_SW2A0_7", - "CFG_CENTER_SW2A0_8", - "CFG_CENTER_SW2A0_9", - "CFG_CENTER_SW2A1_0", - "CFG_CENTER_SW2A1_1", - "CFG_CENTER_SW2A1_10", - "CFG_CENTER_SW2A1_11", - "CFG_CENTER_SW2A1_12", - "CFG_CENTER_SW2A1_13", - "CFG_CENTER_SW2A1_14", - "CFG_CENTER_SW2A1_15", - "CFG_CENTER_SW2A1_16", - "CFG_CENTER_SW2A1_17", - "CFG_CENTER_SW2A1_18", - "CFG_CENTER_SW2A1_19", - "CFG_CENTER_SW2A1_2", - "CFG_CENTER_SW2A1_3", - "CFG_CENTER_SW2A1_4", - "CFG_CENTER_SW2A1_5", - "CFG_CENTER_SW2A1_6", - "CFG_CENTER_SW2A1_7", - "CFG_CENTER_SW2A1_8", - "CFG_CENTER_SW2A1_9", - "CFG_CENTER_SW2A2_0", - "CFG_CENTER_SW2A2_1", - "CFG_CENTER_SW2A2_10", - "CFG_CENTER_SW2A2_11", - "CFG_CENTER_SW2A2_12", - "CFG_CENTER_SW2A2_13", - "CFG_CENTER_SW2A2_14", - "CFG_CENTER_SW2A2_15", - "CFG_CENTER_SW2A2_16", - "CFG_CENTER_SW2A2_17", - "CFG_CENTER_SW2A2_18", - "CFG_CENTER_SW2A2_19", - "CFG_CENTER_SW2A2_2", - "CFG_CENTER_SW2A2_3", - "CFG_CENTER_SW2A2_4", - "CFG_CENTER_SW2A2_5", - "CFG_CENTER_SW2A2_6", - "CFG_CENTER_SW2A2_7", - "CFG_CENTER_SW2A2_8", - "CFG_CENTER_SW2A2_9", - "CFG_CENTER_SW2A3_0", - "CFG_CENTER_SW2A3_1", - "CFG_CENTER_SW2A3_10", - "CFG_CENTER_SW2A3_11", - "CFG_CENTER_SW2A3_12", - "CFG_CENTER_SW2A3_13", - "CFG_CENTER_SW2A3_14", - "CFG_CENTER_SW2A3_15", - "CFG_CENTER_SW2A3_16", - "CFG_CENTER_SW2A3_17", - "CFG_CENTER_SW2A3_18", - "CFG_CENTER_SW2A3_19", - "CFG_CENTER_SW2A3_2", - "CFG_CENTER_SW2A3_3", - "CFG_CENTER_SW2A3_4", - "CFG_CENTER_SW2A3_5", - "CFG_CENTER_SW2A3_6", - "CFG_CENTER_SW2A3_7", - "CFG_CENTER_SW2A3_8", - "CFG_CENTER_SW2A3_9", - "CFG_CENTER_SW4A0_0", - "CFG_CENTER_SW4A0_1", - "CFG_CENTER_SW4A0_10", - "CFG_CENTER_SW4A0_11", - "CFG_CENTER_SW4A0_12", - "CFG_CENTER_SW4A0_13", - "CFG_CENTER_SW4A0_14", - "CFG_CENTER_SW4A0_15", - "CFG_CENTER_SW4A0_16", - "CFG_CENTER_SW4A0_17", - "CFG_CENTER_SW4A0_18", - "CFG_CENTER_SW4A0_19", - "CFG_CENTER_SW4A0_2", - "CFG_CENTER_SW4A0_3", - "CFG_CENTER_SW4A0_4", - "CFG_CENTER_SW4A0_5", - "CFG_CENTER_SW4A0_6", - "CFG_CENTER_SW4A0_7", - "CFG_CENTER_SW4A0_8", - "CFG_CENTER_SW4A0_9", - "CFG_CENTER_SW4A1_0", - "CFG_CENTER_SW4A1_1", - "CFG_CENTER_SW4A1_10", - "CFG_CENTER_SW4A1_11", - "CFG_CENTER_SW4A1_12", - "CFG_CENTER_SW4A1_13", - "CFG_CENTER_SW4A1_14", - "CFG_CENTER_SW4A1_15", - "CFG_CENTER_SW4A1_16", - "CFG_CENTER_SW4A1_17", - "CFG_CENTER_SW4A1_18", - "CFG_CENTER_SW4A1_19", - "CFG_CENTER_SW4A1_2", - "CFG_CENTER_SW4A1_3", - "CFG_CENTER_SW4A1_4", - "CFG_CENTER_SW4A1_5", - "CFG_CENTER_SW4A1_6", - "CFG_CENTER_SW4A1_7", - "CFG_CENTER_SW4A1_8", - "CFG_CENTER_SW4A1_9", - "CFG_CENTER_SW4A2_0", - "CFG_CENTER_SW4A2_1", - "CFG_CENTER_SW4A2_10", - "CFG_CENTER_SW4A2_11", - "CFG_CENTER_SW4A2_12", - "CFG_CENTER_SW4A2_13", - "CFG_CENTER_SW4A2_14", - "CFG_CENTER_SW4A2_15", - "CFG_CENTER_SW4A2_16", - "CFG_CENTER_SW4A2_17", - "CFG_CENTER_SW4A2_18", - "CFG_CENTER_SW4A2_19", - "CFG_CENTER_SW4A2_2", - "CFG_CENTER_SW4A2_3", - "CFG_CENTER_SW4A2_4", - "CFG_CENTER_SW4A2_5", - "CFG_CENTER_SW4A2_6", - "CFG_CENTER_SW4A2_7", - "CFG_CENTER_SW4A2_8", - "CFG_CENTER_SW4A2_9", - "CFG_CENTER_SW4A3_0", - "CFG_CENTER_SW4A3_1", - "CFG_CENTER_SW4A3_10", - "CFG_CENTER_SW4A3_11", - "CFG_CENTER_SW4A3_12", - "CFG_CENTER_SW4A3_13", - "CFG_CENTER_SW4A3_14", - "CFG_CENTER_SW4A3_15", - "CFG_CENTER_SW4A3_16", - "CFG_CENTER_SW4A3_17", - "CFG_CENTER_SW4A3_18", - "CFG_CENTER_SW4A3_19", - "CFG_CENTER_SW4A3_2", - "CFG_CENTER_SW4A3_3", - "CFG_CENTER_SW4A3_4", - "CFG_CENTER_SW4A3_5", - "CFG_CENTER_SW4A3_6", - "CFG_CENTER_SW4A3_7", - "CFG_CENTER_SW4A3_8", - "CFG_CENTER_SW4A3_9", - "CFG_CENTER_SW4END0_0", - "CFG_CENTER_SW4END0_1", - "CFG_CENTER_SW4END0_10", - "CFG_CENTER_SW4END0_11", - "CFG_CENTER_SW4END0_12", - "CFG_CENTER_SW4END0_13", - "CFG_CENTER_SW4END0_14", - "CFG_CENTER_SW4END0_15", - "CFG_CENTER_SW4END0_16", - "CFG_CENTER_SW4END0_17", - "CFG_CENTER_SW4END0_18", - "CFG_CENTER_SW4END0_19", - "CFG_CENTER_SW4END0_2", - "CFG_CENTER_SW4END0_3", - "CFG_CENTER_SW4END0_4", - "CFG_CENTER_SW4END0_5", - "CFG_CENTER_SW4END0_6", - "CFG_CENTER_SW4END0_7", - "CFG_CENTER_SW4END0_8", - "CFG_CENTER_SW4END0_9", - "CFG_CENTER_SW4END1_0", - "CFG_CENTER_SW4END1_1", - "CFG_CENTER_SW4END1_10", - "CFG_CENTER_SW4END1_11", - "CFG_CENTER_SW4END1_12", - "CFG_CENTER_SW4END1_13", - "CFG_CENTER_SW4END1_14", - "CFG_CENTER_SW4END1_15", - "CFG_CENTER_SW4END1_16", - "CFG_CENTER_SW4END1_17", - "CFG_CENTER_SW4END1_18", - "CFG_CENTER_SW4END1_19", - "CFG_CENTER_SW4END1_2", - "CFG_CENTER_SW4END1_3", - "CFG_CENTER_SW4END1_4", - "CFG_CENTER_SW4END1_5", - "CFG_CENTER_SW4END1_6", - "CFG_CENTER_SW4END1_7", - "CFG_CENTER_SW4END1_8", - "CFG_CENTER_SW4END1_9", - "CFG_CENTER_SW4END2_0", - "CFG_CENTER_SW4END2_1", - "CFG_CENTER_SW4END2_10", - "CFG_CENTER_SW4END2_11", - "CFG_CENTER_SW4END2_12", - "CFG_CENTER_SW4END2_13", - "CFG_CENTER_SW4END2_14", - "CFG_CENTER_SW4END2_15", - "CFG_CENTER_SW4END2_16", - "CFG_CENTER_SW4END2_17", - "CFG_CENTER_SW4END2_18", - "CFG_CENTER_SW4END2_19", - "CFG_CENTER_SW4END2_2", - "CFG_CENTER_SW4END2_3", - "CFG_CENTER_SW4END2_4", - "CFG_CENTER_SW4END2_5", - "CFG_CENTER_SW4END2_6", - "CFG_CENTER_SW4END2_7", - "CFG_CENTER_SW4END2_8", - "CFG_CENTER_SW4END2_9", - "CFG_CENTER_SW4END3_0", - "CFG_CENTER_SW4END3_1", - "CFG_CENTER_SW4END3_10", - "CFG_CENTER_SW4END3_11", - "CFG_CENTER_SW4END3_12", - "CFG_CENTER_SW4END3_13", - "CFG_CENTER_SW4END3_14", - "CFG_CENTER_SW4END3_15", - "CFG_CENTER_SW4END3_16", - "CFG_CENTER_SW4END3_17", - "CFG_CENTER_SW4END3_18", - "CFG_CENTER_SW4END3_19", - "CFG_CENTER_SW4END3_2", - "CFG_CENTER_SW4END3_3", - "CFG_CENTER_SW4END3_4", - "CFG_CENTER_SW4END3_5", - "CFG_CENTER_SW4END3_6", - "CFG_CENTER_SW4END3_7", - "CFG_CENTER_SW4END3_8", - "CFG_CENTER_SW4END3_9", - "CFG_CENTER_USR_ACCESS_CFGCLK", - "CFG_CENTER_USR_ACCESS_DATA0", - "CFG_CENTER_USR_ACCESS_DATA1", - "CFG_CENTER_USR_ACCESS_DATA10", - "CFG_CENTER_USR_ACCESS_DATA11", - "CFG_CENTER_USR_ACCESS_DATA12", - "CFG_CENTER_USR_ACCESS_DATA13", - "CFG_CENTER_USR_ACCESS_DATA14", - "CFG_CENTER_USR_ACCESS_DATA15", - "CFG_CENTER_USR_ACCESS_DATA16", - "CFG_CENTER_USR_ACCESS_DATA17", - "CFG_CENTER_USR_ACCESS_DATA18", - "CFG_CENTER_USR_ACCESS_DATA19", - "CFG_CENTER_USR_ACCESS_DATA2", - "CFG_CENTER_USR_ACCESS_DATA20", - "CFG_CENTER_USR_ACCESS_DATA21", - "CFG_CENTER_USR_ACCESS_DATA22", - "CFG_CENTER_USR_ACCESS_DATA23", - "CFG_CENTER_USR_ACCESS_DATA24", - "CFG_CENTER_USR_ACCESS_DATA25", - "CFG_CENTER_USR_ACCESS_DATA26", - "CFG_CENTER_USR_ACCESS_DATA27", - "CFG_CENTER_USR_ACCESS_DATA28", - "CFG_CENTER_USR_ACCESS_DATA29", - "CFG_CENTER_USR_ACCESS_DATA3", - "CFG_CENTER_USR_ACCESS_DATA30", - "CFG_CENTER_USR_ACCESS_DATA31", - "CFG_CENTER_USR_ACCESS_DATA4", - "CFG_CENTER_USR_ACCESS_DATA5", - "CFG_CENTER_USR_ACCESS_DATA6", - "CFG_CENTER_USR_ACCESS_DATA7", - "CFG_CENTER_USR_ACCESS_DATA8", - "CFG_CENTER_USR_ACCESS_DATA9", - "CFG_CENTER_USR_ACCESS_DATAVALID", - "CFG_CENTER_WL1END0_0", - "CFG_CENTER_WL1END0_1", - "CFG_CENTER_WL1END0_10", - "CFG_CENTER_WL1END0_11", - "CFG_CENTER_WL1END0_12", - "CFG_CENTER_WL1END0_13", - "CFG_CENTER_WL1END0_14", - "CFG_CENTER_WL1END0_15", - "CFG_CENTER_WL1END0_16", - "CFG_CENTER_WL1END0_17", - "CFG_CENTER_WL1END0_18", - "CFG_CENTER_WL1END0_19", - "CFG_CENTER_WL1END0_2", - "CFG_CENTER_WL1END0_3", - "CFG_CENTER_WL1END0_4", - "CFG_CENTER_WL1END0_5", - "CFG_CENTER_WL1END0_6", - "CFG_CENTER_WL1END0_7", - "CFG_CENTER_WL1END0_8", - "CFG_CENTER_WL1END0_9", - "CFG_CENTER_WL1END1_0", - "CFG_CENTER_WL1END1_1", - "CFG_CENTER_WL1END1_10", - "CFG_CENTER_WL1END1_11", - "CFG_CENTER_WL1END1_12", - "CFG_CENTER_WL1END1_13", - "CFG_CENTER_WL1END1_14", - "CFG_CENTER_WL1END1_15", - "CFG_CENTER_WL1END1_16", - "CFG_CENTER_WL1END1_17", - "CFG_CENTER_WL1END1_18", - "CFG_CENTER_WL1END1_19", - "CFG_CENTER_WL1END1_2", - "CFG_CENTER_WL1END1_3", - "CFG_CENTER_WL1END1_4", - "CFG_CENTER_WL1END1_5", - "CFG_CENTER_WL1END1_6", - "CFG_CENTER_WL1END1_7", - "CFG_CENTER_WL1END1_8", - "CFG_CENTER_WL1END1_9", - "CFG_CENTER_WL1END2_0", - "CFG_CENTER_WL1END2_1", - "CFG_CENTER_WL1END2_10", - "CFG_CENTER_WL1END2_11", - "CFG_CENTER_WL1END2_12", - "CFG_CENTER_WL1END2_13", - "CFG_CENTER_WL1END2_14", - "CFG_CENTER_WL1END2_15", - "CFG_CENTER_WL1END2_16", - "CFG_CENTER_WL1END2_17", - "CFG_CENTER_WL1END2_18", - "CFG_CENTER_WL1END2_19", - "CFG_CENTER_WL1END2_2", - "CFG_CENTER_WL1END2_3", - "CFG_CENTER_WL1END2_4", - "CFG_CENTER_WL1END2_5", - "CFG_CENTER_WL1END2_6", - "CFG_CENTER_WL1END2_7", - "CFG_CENTER_WL1END2_8", - "CFG_CENTER_WL1END2_9", - "CFG_CENTER_WL1END3_0", - "CFG_CENTER_WL1END3_1", - "CFG_CENTER_WL1END3_10", - "CFG_CENTER_WL1END3_11", - "CFG_CENTER_WL1END3_12", - "CFG_CENTER_WL1END3_13", - "CFG_CENTER_WL1END3_14", - "CFG_CENTER_WL1END3_15", - "CFG_CENTER_WL1END3_16", - "CFG_CENTER_WL1END3_17", - "CFG_CENTER_WL1END3_18", - "CFG_CENTER_WL1END3_19", - "CFG_CENTER_WL1END3_2", - "CFG_CENTER_WL1END3_3", - "CFG_CENTER_WL1END3_4", - "CFG_CENTER_WL1END3_5", - "CFG_CENTER_WL1END3_6", - "CFG_CENTER_WL1END3_7", - "CFG_CENTER_WL1END3_8", - "CFG_CENTER_WL1END3_9", - "CFG_CENTER_WR1END0_0", - "CFG_CENTER_WR1END0_1", - "CFG_CENTER_WR1END0_10", - "CFG_CENTER_WR1END0_11", - "CFG_CENTER_WR1END0_12", - "CFG_CENTER_WR1END0_13", - "CFG_CENTER_WR1END0_14", - "CFG_CENTER_WR1END0_15", - "CFG_CENTER_WR1END0_16", - "CFG_CENTER_WR1END0_17", - "CFG_CENTER_WR1END0_18", - "CFG_CENTER_WR1END0_19", - "CFG_CENTER_WR1END0_2", - "CFG_CENTER_WR1END0_3", - "CFG_CENTER_WR1END0_4", - "CFG_CENTER_WR1END0_5", - "CFG_CENTER_WR1END0_6", - "CFG_CENTER_WR1END0_7", - "CFG_CENTER_WR1END0_8", - "CFG_CENTER_WR1END0_9", - "CFG_CENTER_WR1END1_0", - "CFG_CENTER_WR1END1_1", - "CFG_CENTER_WR1END1_10", - "CFG_CENTER_WR1END1_11", - "CFG_CENTER_WR1END1_12", - "CFG_CENTER_WR1END1_13", - "CFG_CENTER_WR1END1_14", - "CFG_CENTER_WR1END1_15", - "CFG_CENTER_WR1END1_16", - "CFG_CENTER_WR1END1_17", - "CFG_CENTER_WR1END1_18", - "CFG_CENTER_WR1END1_19", - "CFG_CENTER_WR1END1_2", - "CFG_CENTER_WR1END1_3", - "CFG_CENTER_WR1END1_4", - "CFG_CENTER_WR1END1_5", - "CFG_CENTER_WR1END1_6", - "CFG_CENTER_WR1END1_7", - "CFG_CENTER_WR1END1_8", - "CFG_CENTER_WR1END1_9", - "CFG_CENTER_WR1END2_0", - "CFG_CENTER_WR1END2_1", - "CFG_CENTER_WR1END2_10", - "CFG_CENTER_WR1END2_11", - "CFG_CENTER_WR1END2_12", - "CFG_CENTER_WR1END2_13", - "CFG_CENTER_WR1END2_14", - "CFG_CENTER_WR1END2_15", - "CFG_CENTER_WR1END2_16", - "CFG_CENTER_WR1END2_17", - "CFG_CENTER_WR1END2_18", - "CFG_CENTER_WR1END2_19", - "CFG_CENTER_WR1END2_2", - "CFG_CENTER_WR1END2_3", - "CFG_CENTER_WR1END2_4", - "CFG_CENTER_WR1END2_5", - "CFG_CENTER_WR1END2_6", - "CFG_CENTER_WR1END2_7", - "CFG_CENTER_WR1END2_8", - "CFG_CENTER_WR1END2_9", - "CFG_CENTER_WR1END3_0", - "CFG_CENTER_WR1END3_1", - "CFG_CENTER_WR1END3_10", - "CFG_CENTER_WR1END3_11", - "CFG_CENTER_WR1END3_12", - "CFG_CENTER_WR1END3_13", - "CFG_CENTER_WR1END3_14", - "CFG_CENTER_WR1END3_15", - "CFG_CENTER_WR1END3_16", - "CFG_CENTER_WR1END3_17", - "CFG_CENTER_WR1END3_18", - "CFG_CENTER_WR1END3_19", - "CFG_CENTER_WR1END3_2", - "CFG_CENTER_WR1END3_3", - "CFG_CENTER_WR1END3_4", - "CFG_CENTER_WR1END3_5", - "CFG_CENTER_WR1END3_6", - "CFG_CENTER_WR1END3_7", - "CFG_CENTER_WR1END3_8", - "CFG_CENTER_WR1END3_9", - "CFG_CENTER_WW2A0_0", - "CFG_CENTER_WW2A0_1", - "CFG_CENTER_WW2A0_10", - "CFG_CENTER_WW2A0_11", - "CFG_CENTER_WW2A0_12", - "CFG_CENTER_WW2A0_13", - "CFG_CENTER_WW2A0_14", - "CFG_CENTER_WW2A0_15", - "CFG_CENTER_WW2A0_16", - "CFG_CENTER_WW2A0_17", - "CFG_CENTER_WW2A0_18", - "CFG_CENTER_WW2A0_19", - "CFG_CENTER_WW2A0_2", - "CFG_CENTER_WW2A0_3", - "CFG_CENTER_WW2A0_4", - "CFG_CENTER_WW2A0_5", - "CFG_CENTER_WW2A0_6", - "CFG_CENTER_WW2A0_7", - "CFG_CENTER_WW2A0_8", - "CFG_CENTER_WW2A0_9", - "CFG_CENTER_WW2A1_0", - "CFG_CENTER_WW2A1_1", - "CFG_CENTER_WW2A1_10", - "CFG_CENTER_WW2A1_11", - "CFG_CENTER_WW2A1_12", - "CFG_CENTER_WW2A1_13", - "CFG_CENTER_WW2A1_14", - "CFG_CENTER_WW2A1_15", - "CFG_CENTER_WW2A1_16", - "CFG_CENTER_WW2A1_17", - "CFG_CENTER_WW2A1_18", - "CFG_CENTER_WW2A1_19", - "CFG_CENTER_WW2A1_2", - "CFG_CENTER_WW2A1_3", - "CFG_CENTER_WW2A1_4", - "CFG_CENTER_WW2A1_5", - "CFG_CENTER_WW2A1_6", - "CFG_CENTER_WW2A1_7", - "CFG_CENTER_WW2A1_8", - "CFG_CENTER_WW2A1_9", - "CFG_CENTER_WW2A2_0", - "CFG_CENTER_WW2A2_1", - "CFG_CENTER_WW2A2_10", - "CFG_CENTER_WW2A2_11", - "CFG_CENTER_WW2A2_12", - "CFG_CENTER_WW2A2_13", - "CFG_CENTER_WW2A2_14", - "CFG_CENTER_WW2A2_15", - "CFG_CENTER_WW2A2_16", - "CFG_CENTER_WW2A2_17", - "CFG_CENTER_WW2A2_18", - "CFG_CENTER_WW2A2_19", - "CFG_CENTER_WW2A2_2", - "CFG_CENTER_WW2A2_3", - "CFG_CENTER_WW2A2_4", - "CFG_CENTER_WW2A2_5", - "CFG_CENTER_WW2A2_6", - "CFG_CENTER_WW2A2_7", - "CFG_CENTER_WW2A2_8", - "CFG_CENTER_WW2A2_9", - "CFG_CENTER_WW2A3_0", - "CFG_CENTER_WW2A3_1", - "CFG_CENTER_WW2A3_10", - "CFG_CENTER_WW2A3_11", - "CFG_CENTER_WW2A3_12", - "CFG_CENTER_WW2A3_13", - "CFG_CENTER_WW2A3_14", - "CFG_CENTER_WW2A3_15", - "CFG_CENTER_WW2A3_16", - "CFG_CENTER_WW2A3_17", - "CFG_CENTER_WW2A3_18", - "CFG_CENTER_WW2A3_19", - "CFG_CENTER_WW2A3_2", - "CFG_CENTER_WW2A3_3", - "CFG_CENTER_WW2A3_4", - "CFG_CENTER_WW2A3_5", - "CFG_CENTER_WW2A3_6", - "CFG_CENTER_WW2A3_7", - "CFG_CENTER_WW2A3_8", - "CFG_CENTER_WW2A3_9", - "CFG_CENTER_WW2END0_0", - "CFG_CENTER_WW2END0_1", - "CFG_CENTER_WW2END0_10", - "CFG_CENTER_WW2END0_11", - "CFG_CENTER_WW2END0_12", - "CFG_CENTER_WW2END0_13", - "CFG_CENTER_WW2END0_14", - "CFG_CENTER_WW2END0_15", - "CFG_CENTER_WW2END0_16", - "CFG_CENTER_WW2END0_17", - "CFG_CENTER_WW2END0_18", - "CFG_CENTER_WW2END0_19", - "CFG_CENTER_WW2END0_2", - "CFG_CENTER_WW2END0_3", - "CFG_CENTER_WW2END0_4", - "CFG_CENTER_WW2END0_5", - "CFG_CENTER_WW2END0_6", - "CFG_CENTER_WW2END0_7", - "CFG_CENTER_WW2END0_8", - "CFG_CENTER_WW2END0_9", - "CFG_CENTER_WW2END1_0", - "CFG_CENTER_WW2END1_1", - "CFG_CENTER_WW2END1_10", - "CFG_CENTER_WW2END1_11", - "CFG_CENTER_WW2END1_12", - "CFG_CENTER_WW2END1_13", - "CFG_CENTER_WW2END1_14", - "CFG_CENTER_WW2END1_15", - "CFG_CENTER_WW2END1_16", - "CFG_CENTER_WW2END1_17", - "CFG_CENTER_WW2END1_18", - "CFG_CENTER_WW2END1_19", - "CFG_CENTER_WW2END1_2", - "CFG_CENTER_WW2END1_3", - "CFG_CENTER_WW2END1_4", - "CFG_CENTER_WW2END1_5", - "CFG_CENTER_WW2END1_6", - "CFG_CENTER_WW2END1_7", - "CFG_CENTER_WW2END1_8", - "CFG_CENTER_WW2END1_9", - "CFG_CENTER_WW2END2_0", - "CFG_CENTER_WW2END2_1", - "CFG_CENTER_WW2END2_10", - "CFG_CENTER_WW2END2_11", - "CFG_CENTER_WW2END2_12", - "CFG_CENTER_WW2END2_13", - "CFG_CENTER_WW2END2_14", - "CFG_CENTER_WW2END2_15", - "CFG_CENTER_WW2END2_16", - "CFG_CENTER_WW2END2_17", - "CFG_CENTER_WW2END2_18", - "CFG_CENTER_WW2END2_19", - "CFG_CENTER_WW2END2_2", - "CFG_CENTER_WW2END2_3", - "CFG_CENTER_WW2END2_4", - "CFG_CENTER_WW2END2_5", - "CFG_CENTER_WW2END2_6", - "CFG_CENTER_WW2END2_7", - "CFG_CENTER_WW2END2_8", - "CFG_CENTER_WW2END2_9", - "CFG_CENTER_WW2END3_0", - "CFG_CENTER_WW2END3_1", - "CFG_CENTER_WW2END3_10", - "CFG_CENTER_WW2END3_11", - "CFG_CENTER_WW2END3_12", - "CFG_CENTER_WW2END3_13", - "CFG_CENTER_WW2END3_14", - "CFG_CENTER_WW2END3_15", - "CFG_CENTER_WW2END3_16", - "CFG_CENTER_WW2END3_17", - "CFG_CENTER_WW2END3_18", - "CFG_CENTER_WW2END3_19", - "CFG_CENTER_WW2END3_2", - "CFG_CENTER_WW2END3_3", - "CFG_CENTER_WW2END3_4", - "CFG_CENTER_WW2END3_5", - "CFG_CENTER_WW2END3_6", - "CFG_CENTER_WW2END3_7", - "CFG_CENTER_WW2END3_8", - "CFG_CENTER_WW2END3_9", - "CFG_CENTER_WW4A0_0", - "CFG_CENTER_WW4A0_1", - "CFG_CENTER_WW4A0_10", - "CFG_CENTER_WW4A0_11", - "CFG_CENTER_WW4A0_12", - "CFG_CENTER_WW4A0_13", - "CFG_CENTER_WW4A0_14", - "CFG_CENTER_WW4A0_15", - "CFG_CENTER_WW4A0_16", - "CFG_CENTER_WW4A0_17", - "CFG_CENTER_WW4A0_18", - "CFG_CENTER_WW4A0_19", - "CFG_CENTER_WW4A0_2", - "CFG_CENTER_WW4A0_3", - "CFG_CENTER_WW4A0_4", - "CFG_CENTER_WW4A0_5", - "CFG_CENTER_WW4A0_6", - "CFG_CENTER_WW4A0_7", - "CFG_CENTER_WW4A0_8", - "CFG_CENTER_WW4A0_9", - "CFG_CENTER_WW4A1_0", - "CFG_CENTER_WW4A1_1", - "CFG_CENTER_WW4A1_10", - "CFG_CENTER_WW4A1_11", - "CFG_CENTER_WW4A1_12", - "CFG_CENTER_WW4A1_13", - "CFG_CENTER_WW4A1_14", - "CFG_CENTER_WW4A1_15", - "CFG_CENTER_WW4A1_16", - "CFG_CENTER_WW4A1_17", - "CFG_CENTER_WW4A1_18", - "CFG_CENTER_WW4A1_19", - "CFG_CENTER_WW4A1_2", - "CFG_CENTER_WW4A1_3", - "CFG_CENTER_WW4A1_4", - "CFG_CENTER_WW4A1_5", - "CFG_CENTER_WW4A1_6", - "CFG_CENTER_WW4A1_7", - "CFG_CENTER_WW4A1_8", - "CFG_CENTER_WW4A1_9", - "CFG_CENTER_WW4A2_0", - "CFG_CENTER_WW4A2_1", - "CFG_CENTER_WW4A2_10", - "CFG_CENTER_WW4A2_11", - "CFG_CENTER_WW4A2_12", - "CFG_CENTER_WW4A2_13", - "CFG_CENTER_WW4A2_14", - "CFG_CENTER_WW4A2_15", - "CFG_CENTER_WW4A2_16", - "CFG_CENTER_WW4A2_17", - "CFG_CENTER_WW4A2_18", - "CFG_CENTER_WW4A2_19", - "CFG_CENTER_WW4A2_2", - "CFG_CENTER_WW4A2_3", - "CFG_CENTER_WW4A2_4", - "CFG_CENTER_WW4A2_5", - "CFG_CENTER_WW4A2_6", - "CFG_CENTER_WW4A2_7", - "CFG_CENTER_WW4A2_8", - "CFG_CENTER_WW4A2_9", - "CFG_CENTER_WW4A3_0", - "CFG_CENTER_WW4A3_1", - "CFG_CENTER_WW4A3_10", - "CFG_CENTER_WW4A3_11", - "CFG_CENTER_WW4A3_12", - "CFG_CENTER_WW4A3_13", - "CFG_CENTER_WW4A3_14", - "CFG_CENTER_WW4A3_15", - "CFG_CENTER_WW4A3_16", - "CFG_CENTER_WW4A3_17", - "CFG_CENTER_WW4A3_18", - "CFG_CENTER_WW4A3_19", - "CFG_CENTER_WW4A3_2", - "CFG_CENTER_WW4A3_3", - "CFG_CENTER_WW4A3_4", - "CFG_CENTER_WW4A3_5", - "CFG_CENTER_WW4A3_6", - "CFG_CENTER_WW4A3_7", - "CFG_CENTER_WW4A3_8", - "CFG_CENTER_WW4A3_9", - "CFG_CENTER_WW4B0_0", - "CFG_CENTER_WW4B0_1", - "CFG_CENTER_WW4B0_10", - "CFG_CENTER_WW4B0_11", - "CFG_CENTER_WW4B0_12", - "CFG_CENTER_WW4B0_13", - "CFG_CENTER_WW4B0_14", - "CFG_CENTER_WW4B0_15", - "CFG_CENTER_WW4B0_16", - "CFG_CENTER_WW4B0_17", - "CFG_CENTER_WW4B0_18", - "CFG_CENTER_WW4B0_19", - "CFG_CENTER_WW4B0_2", - "CFG_CENTER_WW4B0_3", - "CFG_CENTER_WW4B0_4", - "CFG_CENTER_WW4B0_5", - "CFG_CENTER_WW4B0_6", - "CFG_CENTER_WW4B0_7", - "CFG_CENTER_WW4B0_8", - "CFG_CENTER_WW4B0_9", - "CFG_CENTER_WW4B1_0", - "CFG_CENTER_WW4B1_1", - "CFG_CENTER_WW4B1_10", - "CFG_CENTER_WW4B1_11", - "CFG_CENTER_WW4B1_12", - "CFG_CENTER_WW4B1_13", - "CFG_CENTER_WW4B1_14", - "CFG_CENTER_WW4B1_15", - "CFG_CENTER_WW4B1_16", - "CFG_CENTER_WW4B1_17", - "CFG_CENTER_WW4B1_18", - "CFG_CENTER_WW4B1_19", - "CFG_CENTER_WW4B1_2", - "CFG_CENTER_WW4B1_3", - "CFG_CENTER_WW4B1_4", - "CFG_CENTER_WW4B1_5", - "CFG_CENTER_WW4B1_6", - "CFG_CENTER_WW4B1_7", - "CFG_CENTER_WW4B1_8", - "CFG_CENTER_WW4B1_9", - "CFG_CENTER_WW4B2_0", - "CFG_CENTER_WW4B2_1", - "CFG_CENTER_WW4B2_10", - "CFG_CENTER_WW4B2_11", - "CFG_CENTER_WW4B2_12", - "CFG_CENTER_WW4B2_13", - "CFG_CENTER_WW4B2_14", - "CFG_CENTER_WW4B2_15", - "CFG_CENTER_WW4B2_16", - "CFG_CENTER_WW4B2_17", - "CFG_CENTER_WW4B2_18", - "CFG_CENTER_WW4B2_19", - "CFG_CENTER_WW4B2_2", - "CFG_CENTER_WW4B2_3", - "CFG_CENTER_WW4B2_4", - "CFG_CENTER_WW4B2_5", - "CFG_CENTER_WW4B2_6", - "CFG_CENTER_WW4B2_7", - "CFG_CENTER_WW4B2_8", - "CFG_CENTER_WW4B2_9", - "CFG_CENTER_WW4B3_0", - "CFG_CENTER_WW4B3_1", - "CFG_CENTER_WW4B3_10", - "CFG_CENTER_WW4B3_11", - "CFG_CENTER_WW4B3_12", - "CFG_CENTER_WW4B3_13", - "CFG_CENTER_WW4B3_14", - "CFG_CENTER_WW4B3_15", - "CFG_CENTER_WW4B3_16", - "CFG_CENTER_WW4B3_17", - "CFG_CENTER_WW4B3_18", - "CFG_CENTER_WW4B3_19", - "CFG_CENTER_WW4B3_2", - "CFG_CENTER_WW4B3_3", - "CFG_CENTER_WW4B3_4", - "CFG_CENTER_WW4B3_5", - "CFG_CENTER_WW4B3_6", - "CFG_CENTER_WW4B3_7", - "CFG_CENTER_WW4B3_8", - "CFG_CENTER_WW4B3_9", - "CFG_CENTER_WW4C0_0", - "CFG_CENTER_WW4C0_1", - "CFG_CENTER_WW4C0_10", - "CFG_CENTER_WW4C0_11", - "CFG_CENTER_WW4C0_12", - "CFG_CENTER_WW4C0_13", - "CFG_CENTER_WW4C0_14", - "CFG_CENTER_WW4C0_15", - "CFG_CENTER_WW4C0_16", - "CFG_CENTER_WW4C0_17", - "CFG_CENTER_WW4C0_18", - "CFG_CENTER_WW4C0_19", - "CFG_CENTER_WW4C0_2", - "CFG_CENTER_WW4C0_3", - "CFG_CENTER_WW4C0_4", - "CFG_CENTER_WW4C0_5", - "CFG_CENTER_WW4C0_6", - "CFG_CENTER_WW4C0_7", - "CFG_CENTER_WW4C0_8", - "CFG_CENTER_WW4C0_9", - "CFG_CENTER_WW4C1_0", - "CFG_CENTER_WW4C1_1", - "CFG_CENTER_WW4C1_10", - "CFG_CENTER_WW4C1_11", - "CFG_CENTER_WW4C1_12", - "CFG_CENTER_WW4C1_13", - "CFG_CENTER_WW4C1_14", - "CFG_CENTER_WW4C1_15", - "CFG_CENTER_WW4C1_16", - "CFG_CENTER_WW4C1_17", - "CFG_CENTER_WW4C1_18", - "CFG_CENTER_WW4C1_19", - "CFG_CENTER_WW4C1_2", - "CFG_CENTER_WW4C1_3", - "CFG_CENTER_WW4C1_4", - "CFG_CENTER_WW4C1_5", - "CFG_CENTER_WW4C1_6", - "CFG_CENTER_WW4C1_7", - "CFG_CENTER_WW4C1_8", - "CFG_CENTER_WW4C1_9", - "CFG_CENTER_WW4C2_0", - "CFG_CENTER_WW4C2_1", - "CFG_CENTER_WW4C2_10", - "CFG_CENTER_WW4C2_11", - "CFG_CENTER_WW4C2_12", - "CFG_CENTER_WW4C2_13", - "CFG_CENTER_WW4C2_14", - "CFG_CENTER_WW4C2_15", - "CFG_CENTER_WW4C2_16", - "CFG_CENTER_WW4C2_17", - "CFG_CENTER_WW4C2_18", - "CFG_CENTER_WW4C2_19", - "CFG_CENTER_WW4C2_2", - "CFG_CENTER_WW4C2_3", - "CFG_CENTER_WW4C2_4", - "CFG_CENTER_WW4C2_5", - "CFG_CENTER_WW4C2_6", - "CFG_CENTER_WW4C2_7", - "CFG_CENTER_WW4C2_8", - "CFG_CENTER_WW4C2_9", - "CFG_CENTER_WW4C3_0", - "CFG_CENTER_WW4C3_1", - "CFG_CENTER_WW4C3_10", - "CFG_CENTER_WW4C3_11", - "CFG_CENTER_WW4C3_12", - "CFG_CENTER_WW4C3_13", - "CFG_CENTER_WW4C3_14", - "CFG_CENTER_WW4C3_15", - "CFG_CENTER_WW4C3_16", - "CFG_CENTER_WW4C3_17", - "CFG_CENTER_WW4C3_18", - "CFG_CENTER_WW4C3_19", - "CFG_CENTER_WW4C3_2", - "CFG_CENTER_WW4C3_3", - "CFG_CENTER_WW4C3_4", - "CFG_CENTER_WW4C3_5", - "CFG_CENTER_WW4C3_6", - "CFG_CENTER_WW4C3_7", - "CFG_CENTER_WW4C3_8", - "CFG_CENTER_WW4C3_9", - "CFG_CENTER_WW4END0_0", - "CFG_CENTER_WW4END0_1", - "CFG_CENTER_WW4END0_10", - "CFG_CENTER_WW4END0_11", - "CFG_CENTER_WW4END0_12", - "CFG_CENTER_WW4END0_13", - "CFG_CENTER_WW4END0_14", - "CFG_CENTER_WW4END0_15", - "CFG_CENTER_WW4END0_16", - "CFG_CENTER_WW4END0_17", - "CFG_CENTER_WW4END0_18", - "CFG_CENTER_WW4END0_19", - "CFG_CENTER_WW4END0_2", - "CFG_CENTER_WW4END0_3", - "CFG_CENTER_WW4END0_4", - "CFG_CENTER_WW4END0_5", - "CFG_CENTER_WW4END0_6", - "CFG_CENTER_WW4END0_7", - "CFG_CENTER_WW4END0_8", - "CFG_CENTER_WW4END0_9", - "CFG_CENTER_WW4END1_0", - "CFG_CENTER_WW4END1_1", - "CFG_CENTER_WW4END1_10", - "CFG_CENTER_WW4END1_11", - "CFG_CENTER_WW4END1_12", - "CFG_CENTER_WW4END1_13", - "CFG_CENTER_WW4END1_14", - "CFG_CENTER_WW4END1_15", - "CFG_CENTER_WW4END1_16", - "CFG_CENTER_WW4END1_17", - "CFG_CENTER_WW4END1_18", - "CFG_CENTER_WW4END1_19", - "CFG_CENTER_WW4END1_2", - "CFG_CENTER_WW4END1_3", - "CFG_CENTER_WW4END1_4", - "CFG_CENTER_WW4END1_5", - "CFG_CENTER_WW4END1_6", - "CFG_CENTER_WW4END1_7", - "CFG_CENTER_WW4END1_8", - "CFG_CENTER_WW4END1_9", - "CFG_CENTER_WW4END2_0", - "CFG_CENTER_WW4END2_1", - "CFG_CENTER_WW4END2_10", - "CFG_CENTER_WW4END2_11", - "CFG_CENTER_WW4END2_12", - "CFG_CENTER_WW4END2_13", - "CFG_CENTER_WW4END2_14", - "CFG_CENTER_WW4END2_15", - "CFG_CENTER_WW4END2_16", - "CFG_CENTER_WW4END2_17", - "CFG_CENTER_WW4END2_18", - "CFG_CENTER_WW4END2_19", - "CFG_CENTER_WW4END2_2", - "CFG_CENTER_WW4END2_3", - "CFG_CENTER_WW4END2_4", - "CFG_CENTER_WW4END2_5", - "CFG_CENTER_WW4END2_6", - "CFG_CENTER_WW4END2_7", - "CFG_CENTER_WW4END2_8", - "CFG_CENTER_WW4END2_9", - "CFG_CENTER_WW4END3_0", - "CFG_CENTER_WW4END3_1", - "CFG_CENTER_WW4END3_10", - "CFG_CENTER_WW4END3_11", - "CFG_CENTER_WW4END3_12", - "CFG_CENTER_WW4END3_13", - "CFG_CENTER_WW4END3_14", - "CFG_CENTER_WW4END3_15", - "CFG_CENTER_WW4END3_16", - "CFG_CENTER_WW4END3_17", - "CFG_CENTER_WW4END3_18", - "CFG_CENTER_WW4END3_19", - "CFG_CENTER_WW4END3_2", - "CFG_CENTER_WW4END3_3", - "CFG_CENTER_WW4END3_4", - "CFG_CENTER_WW4END3_5", - "CFG_CENTER_WW4END3_6", - "CFG_CENTER_WW4END3_7", - "CFG_CENTER_WW4END3_8", - "CFG_CENTER_WW4END3_9" - ] + "wires": { + "CFG_CENTER_BLOCK_OUTS_B0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BSCAN1_CAPTURE": null, + "CFG_CENTER_BSCAN1_DRCK": null, + "CFG_CENTER_BSCAN1_RESET": null, + "CFG_CENTER_BSCAN1_RUNTEST": null, + "CFG_CENTER_BSCAN1_SEL": null, + "CFG_CENTER_BSCAN1_SHIFT": null, + "CFG_CENTER_BSCAN1_TCK": null, + "CFG_CENTER_BSCAN1_TDI": null, + "CFG_CENTER_BSCAN1_TDO": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_BSCAN1_TMS": null, + "CFG_CENTER_BSCAN1_UPDATE": null, + "CFG_CENTER_BSCAN2_CAPTURE": null, + "CFG_CENTER_BSCAN2_DRCK": null, + "CFG_CENTER_BSCAN2_RESET": null, + "CFG_CENTER_BSCAN2_RUNTEST": null, + "CFG_CENTER_BSCAN2_SEL": null, + "CFG_CENTER_BSCAN2_SHIFT": null, + "CFG_CENTER_BSCAN2_TCK": null, + "CFG_CENTER_BSCAN2_TDI": null, + "CFG_CENTER_BSCAN2_TDO": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_BSCAN2_TMS": null, + "CFG_CENTER_BSCAN2_UPDATE": null, + "CFG_CENTER_BSCAN3_CAPTURE": null, + "CFG_CENTER_BSCAN3_DRCK": null, + "CFG_CENTER_BSCAN3_RESET": null, + "CFG_CENTER_BSCAN3_RUNTEST": null, + "CFG_CENTER_BSCAN3_SEL": null, + "CFG_CENTER_BSCAN3_SHIFT": null, + "CFG_CENTER_BSCAN3_TCK": null, + "CFG_CENTER_BSCAN3_TDI": null, + "CFG_CENTER_BSCAN3_TDO": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_BSCAN3_TMS": null, + "CFG_CENTER_BSCAN3_UPDATE": null, + "CFG_CENTER_BSCAN4_CAPTURE": null, + "CFG_CENTER_BSCAN4_DRCK": null, + "CFG_CENTER_BSCAN4_RESET": null, + "CFG_CENTER_BSCAN4_RUNTEST": null, + "CFG_CENTER_BSCAN4_SEL": null, + "CFG_CENTER_BSCAN4_SHIFT": null, + "CFG_CENTER_BSCAN4_TCK": null, + "CFG_CENTER_BSCAN4_TDI": null, + "CFG_CENTER_BSCAN4_TDO": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_BSCAN4_TMS": null, + "CFG_CENTER_BSCAN4_UPDATE": null, + "CFG_CENTER_BYP0_0": null, + "CFG_CENTER_BYP0_1": null, + "CFG_CENTER_BYP0_10": null, + "CFG_CENTER_BYP0_11": null, + "CFG_CENTER_BYP0_12": null, + "CFG_CENTER_BYP0_13": null, + "CFG_CENTER_BYP0_14": null, + "CFG_CENTER_BYP0_15": null, + "CFG_CENTER_BYP0_16": null, + "CFG_CENTER_BYP0_17": null, + "CFG_CENTER_BYP0_18": null, + "CFG_CENTER_BYP0_19": null, + "CFG_CENTER_BYP0_2": null, + "CFG_CENTER_BYP0_3": null, + "CFG_CENTER_BYP0_4": null, + "CFG_CENTER_BYP0_5": null, + "CFG_CENTER_BYP0_6": null, + "CFG_CENTER_BYP0_7": null, + "CFG_CENTER_BYP0_8": null, + "CFG_CENTER_BYP0_9": null, + "CFG_CENTER_BYP1_0": null, + "CFG_CENTER_BYP1_1": null, + "CFG_CENTER_BYP1_10": null, + "CFG_CENTER_BYP1_11": null, + "CFG_CENTER_BYP1_12": null, + "CFG_CENTER_BYP1_13": null, + "CFG_CENTER_BYP1_14": null, + "CFG_CENTER_BYP1_15": null, + "CFG_CENTER_BYP1_16": null, + "CFG_CENTER_BYP1_17": null, + "CFG_CENTER_BYP1_18": null, + "CFG_CENTER_BYP1_19": null, + "CFG_CENTER_BYP1_2": null, + "CFG_CENTER_BYP1_3": null, + "CFG_CENTER_BYP1_4": null, + "CFG_CENTER_BYP1_5": null, + "CFG_CENTER_BYP1_6": null, + "CFG_CENTER_BYP1_7": null, + "CFG_CENTER_BYP1_8": null, + "CFG_CENTER_BYP1_9": null, + "CFG_CENTER_BYP2_0": null, + "CFG_CENTER_BYP2_1": null, + "CFG_CENTER_BYP2_10": null, + "CFG_CENTER_BYP2_11": null, + "CFG_CENTER_BYP2_12": null, + "CFG_CENTER_BYP2_13": null, + "CFG_CENTER_BYP2_14": null, + "CFG_CENTER_BYP2_15": null, + "CFG_CENTER_BYP2_16": null, + "CFG_CENTER_BYP2_17": null, + "CFG_CENTER_BYP2_18": null, + "CFG_CENTER_BYP2_19": null, + "CFG_CENTER_BYP2_2": null, + "CFG_CENTER_BYP2_3": null, + "CFG_CENTER_BYP2_4": null, + "CFG_CENTER_BYP2_5": null, + "CFG_CENTER_BYP2_6": null, + "CFG_CENTER_BYP2_7": null, + "CFG_CENTER_BYP2_8": null, + "CFG_CENTER_BYP2_9": null, + "CFG_CENTER_BYP3_0": null, + "CFG_CENTER_BYP3_1": null, + "CFG_CENTER_BYP3_10": null, + "CFG_CENTER_BYP3_11": null, + "CFG_CENTER_BYP3_12": null, + "CFG_CENTER_BYP3_13": null, + "CFG_CENTER_BYP3_14": null, + "CFG_CENTER_BYP3_15": null, + "CFG_CENTER_BYP3_16": null, + "CFG_CENTER_BYP3_17": null, + "CFG_CENTER_BYP3_18": null, + "CFG_CENTER_BYP3_19": null, + "CFG_CENTER_BYP3_2": null, + "CFG_CENTER_BYP3_3": null, + "CFG_CENTER_BYP3_4": null, + "CFG_CENTER_BYP3_5": null, + "CFG_CENTER_BYP3_6": null, + "CFG_CENTER_BYP3_7": null, + "CFG_CENTER_BYP3_8": null, + "CFG_CENTER_BYP3_9": null, + "CFG_CENTER_BYP4_0": null, + "CFG_CENTER_BYP4_1": null, + "CFG_CENTER_BYP4_10": null, + "CFG_CENTER_BYP4_11": null, + "CFG_CENTER_BYP4_12": null, + "CFG_CENTER_BYP4_13": null, + "CFG_CENTER_BYP4_14": null, + "CFG_CENTER_BYP4_15": null, + "CFG_CENTER_BYP4_16": null, + "CFG_CENTER_BYP4_17": null, + "CFG_CENTER_BYP4_18": null, + "CFG_CENTER_BYP4_19": null, + "CFG_CENTER_BYP4_2": null, + "CFG_CENTER_BYP4_3": null, + "CFG_CENTER_BYP4_4": null, + "CFG_CENTER_BYP4_5": null, + "CFG_CENTER_BYP4_6": null, + "CFG_CENTER_BYP4_7": null, + "CFG_CENTER_BYP4_8": null, + "CFG_CENTER_BYP4_9": null, + "CFG_CENTER_BYP5_0": null, + "CFG_CENTER_BYP5_1": null, + "CFG_CENTER_BYP5_10": null, + "CFG_CENTER_BYP5_11": null, + "CFG_CENTER_BYP5_12": null, + "CFG_CENTER_BYP5_13": null, + "CFG_CENTER_BYP5_14": null, + "CFG_CENTER_BYP5_15": null, + "CFG_CENTER_BYP5_16": null, + "CFG_CENTER_BYP5_17": null, + "CFG_CENTER_BYP5_18": null, + "CFG_CENTER_BYP5_19": null, + "CFG_CENTER_BYP5_2": null, + "CFG_CENTER_BYP5_3": null, + "CFG_CENTER_BYP5_4": null, + "CFG_CENTER_BYP5_5": null, + "CFG_CENTER_BYP5_6": null, + "CFG_CENTER_BYP5_7": null, + "CFG_CENTER_BYP5_8": null, + "CFG_CENTER_BYP5_9": null, + "CFG_CENTER_BYP6_0": null, + "CFG_CENTER_BYP6_1": null, + "CFG_CENTER_BYP6_10": null, + "CFG_CENTER_BYP6_11": null, + "CFG_CENTER_BYP6_12": null, + "CFG_CENTER_BYP6_13": null, + "CFG_CENTER_BYP6_14": null, + "CFG_CENTER_BYP6_15": null, + "CFG_CENTER_BYP6_16": null, + "CFG_CENTER_BYP6_17": null, + "CFG_CENTER_BYP6_18": null, + "CFG_CENTER_BYP6_19": null, + "CFG_CENTER_BYP6_2": null, + "CFG_CENTER_BYP6_3": null, + "CFG_CENTER_BYP6_4": null, + "CFG_CENTER_BYP6_5": null, + "CFG_CENTER_BYP6_6": null, + "CFG_CENTER_BYP6_7": null, + "CFG_CENTER_BYP6_8": null, + "CFG_CENTER_BYP6_9": null, + "CFG_CENTER_BYP7_0": null, + "CFG_CENTER_BYP7_1": null, + "CFG_CENTER_BYP7_10": null, + "CFG_CENTER_BYP7_11": null, + "CFG_CENTER_BYP7_12": null, + "CFG_CENTER_BYP7_13": null, + "CFG_CENTER_BYP7_14": null, + "CFG_CENTER_BYP7_15": null, + "CFG_CENTER_BYP7_16": null, + "CFG_CENTER_BYP7_17": null, + "CFG_CENTER_BYP7_18": null, + "CFG_CENTER_BYP7_19": null, + "CFG_CENTER_BYP7_2": null, + "CFG_CENTER_BYP7_3": null, + "CFG_CENTER_BYP7_4": null, + "CFG_CENTER_BYP7_5": null, + "CFG_CENTER_BYP7_6": null, + "CFG_CENTER_BYP7_7": null, + "CFG_CENTER_BYP7_8": null, + "CFG_CENTER_BYP7_9": null, + "CFG_CENTER_CAPTURE_CAP": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_CAPTURE_CLK": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_CFG_IO_ACCESS_CCLK": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA0": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA1": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA10": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA11": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA12": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA13": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA14": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA15": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA16": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA17": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA18": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA19": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA2": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA20": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA21": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA22": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA23": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA24": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA25": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA26": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA27": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA28": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA29": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA3": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA30": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA31": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA4": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA5": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA6": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA7": 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"CFG_CENTER_EE2BEG1_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG2_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_1": { + "cap": "83.787", + "res": "325.400" + }, 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}, + "CFG_CENTER_EE2BEG3_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG3_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A1_8": { + "cap": "64.544", + "res": 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"CFG_CENTER_EE4A2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A3_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A3_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A3_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A3_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A3_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_EE4A3_15": { + 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"0.000" + }, + "CFG_CENTER_IMUX13_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_18": { + "cap": "1.111", + "res": "0.000" + }, + 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"0.000" + }, + "CFG_CENTER_IMUX16_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_4": { + "cap": "1.111", + "res": "0.000" + }, + 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+ "res": "0.000" + }, + "CFG_CENTER_IMUX19_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_9": { + 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"0.000" + }, + "CFG_CENTER_IMUX21_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_15": { + "cap": "1.111", + "res": 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+ "res": "0.000" + }, + "CFG_CENTER_IMUX24_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_19": { + "cap": "1.111", + "res": "0.000" + }, + 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+ "res": "0.000" + }, + "CFG_CENTER_IMUX27_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_6": { + 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"1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_13": { 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"0.000" + }, + "CFG_CENTER_IMUX32_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_17": { + "cap": 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"0.000" + }, + "CFG_CENTER_IMUX35_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_16": { + "cap": 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"cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LH10_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LOGIC_OUTS_B0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_11": { + "cap": "1.111", + "res": "0.000" + }, + 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"CFG_CENTER_LOGIC_OUTS_B21_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_7": 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"325.400" + }, + "CFG_CENTER_WW2A0_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A1_17": { + "cap": "83.787", + "res": "325.400" + }, + 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"325.400" + }, + "CFG_CENTER_WW2A2_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2A3_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END0_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END1_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_10": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_11": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_12": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_13": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_14": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_15": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_16": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_17": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_18": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_19": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END2_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END3_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END3_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END3_10": { + "cap": "83.787", + "res": "325.400" + }, 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}, + "CFG_CENTER_WW2END3_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END3_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW2END3_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_WW4A0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A0_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A0_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A0_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A0_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A0_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A0_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A0_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A0_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A0_18": { + "cap": "64.544", + "res": "325.400" + }, + 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"CFG_CENTER_WW4C1_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_10": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_11": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_12": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_13": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_14": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_15": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_16": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_17": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_18": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_19": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_9": { + "cap": "64.544", + "res": "325.400" + } + } } diff --git a/zynq7/tile_type_CFG_CENTER_TOP.json b/zynq7/tile_type_CFG_CENTER_TOP.json index e0a60f6..9e84b67 100644 --- a/zynq7/tile_type_CFG_CENTER_TOP.json +++ b/zynq7/tile_type_CFG_CENTER_TOP.json @@ -2,268 +2,686 @@ "pips": { "CFG_CENTER_TOP.CFG_CENTER_CLK1_0->CFG_CENTER_TOP_ICAP1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_TOP_ICAP1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_CLK1_0" }, "CFG_CENTER_TOP.CFG_CENTER_DNA_PORT_DOUT->CFG_CENTER_LOGIC_OUTS_B23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_DNA_PORT_DOUT" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR0->CFG_CENTER_LOGIC_OUTS_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR0" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR1->CFG_CENTER_LOGIC_OUTS_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR1" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR10->CFG_CENTER_LOGIC_OUTS_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR10" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR11->CFG_CENTER_LOGIC_OUTS_B19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR11" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR12->CFG_CENTER_LOGIC_OUTS_B20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR12" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR13->CFG_CENTER_LOGIC_OUTS_B21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR13" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR14->CFG_CENTER_LOGIC_OUTS_B22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR14" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR15->CFG_CENTER_LOGIC_OUTS_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR15" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR16->CFG_CENTER_LOGIC_OUTS_B16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR16" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR17->CFG_CENTER_LOGIC_OUTS_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR17" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR18->CFG_CENTER_LOGIC_OUTS_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR18" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR19->CFG_CENTER_LOGIC_OUTS_B19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR19" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR2->CFG_CENTER_LOGIC_OUTS_B18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR2" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR20->CFG_CENTER_LOGIC_OUTS_B20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR20" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR21->CFG_CENTER_LOGIC_OUTS_B21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR21" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR22->CFG_CENTER_LOGIC_OUTS_B22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR22" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR23->CFG_CENTER_LOGIC_OUTS_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR23" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR24->CFG_CENTER_LOGIC_OUTS_B16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR24" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR25->CFG_CENTER_LOGIC_OUTS_B17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR25" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR26->CFG_CENTER_LOGIC_OUTS_B18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR26" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR27->CFG_CENTER_LOGIC_OUTS_B19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR27" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR28->CFG_CENTER_LOGIC_OUTS_B20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR28" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR29->CFG_CENTER_LOGIC_OUTS_B21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR29" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR3->CFG_CENTER_LOGIC_OUTS_B19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR3" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR30->CFG_CENTER_LOGIC_OUTS_B22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR30" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR31->CFG_CENTER_LOGIC_OUTS_B23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR31" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR4->CFG_CENTER_LOGIC_OUTS_B20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR4" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR5->CFG_CENTER_LOGIC_OUTS_B21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR5" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR6->CFG_CENTER_LOGIC_OUTS_B22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR6" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR7->CFG_CENTER_LOGIC_OUTS_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR7" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR8->CFG_CENTER_LOGIC_OUTS_B16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR8" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR9->CFG_CENTER_LOGIC_OUTS_B17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR9" }, "CFG_CENTER_TOP.CFG_CENTER_IMUX41_5->CFG_CENTER_DNA_PORT_READ": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_DNA_PORT_READ", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_5" }, "CFG_CENTER_TOP.CFG_CENTER_IMUX42_5->CFG_CENTER_DNA_PORT_SHIFT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_DNA_PORT_SHIFT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_5" }, "CFG_CENTER_TOP.CFG_CENTER_IMUX43_5->CFG_CENTER_DNA_PORT_DIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_DNA_PORT_DIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX43_5" }, "CFG_CENTER_TOP.CFG_CENTER_TOP_DNA_PORT_CLK->CFG_CENTER_DNA_PORT_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_DNA_PORT_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_TOP_DNA_PORT_CLK" } }, @@ -272,11 +690,56 @@ "name": "X0Y0", "prefix": "DNA_PORT", "site_pins": { - "CLK": "CFG_CENTER_DNA_PORT_CLK", - "DIN": "CFG_CENTER_DNA_PORT_DIN", - "DOUT": "CFG_CENTER_DNA_PORT_DOUT", - "READ": "CFG_CENTER_DNA_PORT_READ", - "SHIFT": "CFG_CENTER_DNA_PORT_SHIFT" + "CLK": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.010", + "0.011" + ], + "wire": "CFG_CENTER_DNA_PORT_CLK" + }, + "DIN": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.010", + "0.011" + ], + "wire": "CFG_CENTER_DNA_PORT_DIN" + }, + "DOUT": { + "delay": [ + "0.001", + "0.001", + "0.010", + "0.011" + ], + "res": "0.0", + "wire": "CFG_CENTER_DNA_PORT_DOUT" + }, + "READ": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.010", + "0.011" + ], + "wire": "CFG_CENTER_DNA_PORT_READ" + }, + "SHIFT": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.010", + "0.011" + ], + "wire": "CFG_CENTER_DNA_PORT_SHIFT" + } }, "type": "DNA_PORT", "x_coord": 0, @@ -286,38 +749,326 @@ "name": "X0Y0", "prefix": "EFUSE_USR", "site_pins": { - "EFUSEUSR0": "CFG_CENTER_EFUSE_USR_EFUSEUSR0", - "EFUSEUSR1": "CFG_CENTER_EFUSE_USR_EFUSEUSR1", - "EFUSEUSR10": "CFG_CENTER_EFUSE_USR_EFUSEUSR10", - "EFUSEUSR11": "CFG_CENTER_EFUSE_USR_EFUSEUSR11", - "EFUSEUSR12": "CFG_CENTER_EFUSE_USR_EFUSEUSR12", - "EFUSEUSR13": "CFG_CENTER_EFUSE_USR_EFUSEUSR13", - "EFUSEUSR14": "CFG_CENTER_EFUSE_USR_EFUSEUSR14", - "EFUSEUSR15": "CFG_CENTER_EFUSE_USR_EFUSEUSR15", - "EFUSEUSR16": "CFG_CENTER_EFUSE_USR_EFUSEUSR16", - "EFUSEUSR17": "CFG_CENTER_EFUSE_USR_EFUSEUSR17", - "EFUSEUSR18": "CFG_CENTER_EFUSE_USR_EFUSEUSR18", - "EFUSEUSR19": "CFG_CENTER_EFUSE_USR_EFUSEUSR19", - "EFUSEUSR2": "CFG_CENTER_EFUSE_USR_EFUSEUSR2", - "EFUSEUSR20": "CFG_CENTER_EFUSE_USR_EFUSEUSR20", - "EFUSEUSR21": "CFG_CENTER_EFUSE_USR_EFUSEUSR21", - "EFUSEUSR22": "CFG_CENTER_EFUSE_USR_EFUSEUSR22", - "EFUSEUSR23": "CFG_CENTER_EFUSE_USR_EFUSEUSR23", - "EFUSEUSR24": "CFG_CENTER_EFUSE_USR_EFUSEUSR24", - "EFUSEUSR25": "CFG_CENTER_EFUSE_USR_EFUSEUSR25", - "EFUSEUSR26": "CFG_CENTER_EFUSE_USR_EFUSEUSR26", - "EFUSEUSR27": "CFG_CENTER_EFUSE_USR_EFUSEUSR27", - "EFUSEUSR28": "CFG_CENTER_EFUSE_USR_EFUSEUSR28", - "EFUSEUSR29": "CFG_CENTER_EFUSE_USR_EFUSEUSR29", - "EFUSEUSR3": "CFG_CENTER_EFUSE_USR_EFUSEUSR3", - "EFUSEUSR30": "CFG_CENTER_EFUSE_USR_EFUSEUSR30", - "EFUSEUSR31": "CFG_CENTER_EFUSE_USR_EFUSEUSR31", - "EFUSEUSR4": "CFG_CENTER_EFUSE_USR_EFUSEUSR4", - "EFUSEUSR5": "CFG_CENTER_EFUSE_USR_EFUSEUSR5", - "EFUSEUSR6": "CFG_CENTER_EFUSE_USR_EFUSEUSR6", - "EFUSEUSR7": "CFG_CENTER_EFUSE_USR_EFUSEUSR7", - "EFUSEUSR8": "CFG_CENTER_EFUSE_USR_EFUSEUSR8", - "EFUSEUSR9": "CFG_CENTER_EFUSE_USR_EFUSEUSR9" + "EFUSEUSR0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR0" + }, + "EFUSEUSR1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR1" + }, + "EFUSEUSR10": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR10" + }, + "EFUSEUSR11": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR11" + }, + "EFUSEUSR12": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR12" + }, + "EFUSEUSR13": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR13" + }, + "EFUSEUSR14": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR14" + }, + "EFUSEUSR15": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR15" + }, + "EFUSEUSR16": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR16" + }, + "EFUSEUSR17": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR17" + }, + "EFUSEUSR18": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR18" + }, + "EFUSEUSR19": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR19" + }, + "EFUSEUSR2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR2" + }, + "EFUSEUSR20": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR20" + }, + "EFUSEUSR21": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR21" + }, + "EFUSEUSR22": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR22" + }, + "EFUSEUSR23": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR23" + }, + "EFUSEUSR24": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR24" + }, + "EFUSEUSR25": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR25" + }, + "EFUSEUSR26": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR26" + }, + "EFUSEUSR27": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR27" + }, + "EFUSEUSR28": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR28" + }, + "EFUSEUSR29": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR29" + }, + "EFUSEUSR3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR3" + }, + "EFUSEUSR30": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR30" + }, + "EFUSEUSR31": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR31" + }, + "EFUSEUSR4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR4" + }, + "EFUSEUSR5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR5" + }, + "EFUSEUSR6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR6" + }, + "EFUSEUSR7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR7" + }, + "EFUSEUSR8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR8" + }, + "EFUSEUSR9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "175.3125", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR9" + } }, "type": "EFUSE_USR", "x_coord": 0, @@ -325,2266 +1076,8398 @@ } ], "tile_type": "CFG_CENTER_TOP", - "wires": [ - "CFG_CENTER_BLOCK_OUTS_B0_0", - "CFG_CENTER_BLOCK_OUTS_B0_1", - "CFG_CENTER_BLOCK_OUTS_B0_2", - "CFG_CENTER_BLOCK_OUTS_B0_3", - "CFG_CENTER_BLOCK_OUTS_B0_4", - "CFG_CENTER_BLOCK_OUTS_B0_5", - "CFG_CENTER_BLOCK_OUTS_B0_6", - "CFG_CENTER_BLOCK_OUTS_B0_7", - "CFG_CENTER_BLOCK_OUTS_B0_8", - "CFG_CENTER_BLOCK_OUTS_B0_9", - "CFG_CENTER_BLOCK_OUTS_B1_0", - "CFG_CENTER_BLOCK_OUTS_B1_1", - "CFG_CENTER_BLOCK_OUTS_B1_2", - "CFG_CENTER_BLOCK_OUTS_B1_3", - "CFG_CENTER_BLOCK_OUTS_B1_4", - "CFG_CENTER_BLOCK_OUTS_B1_5", - "CFG_CENTER_BLOCK_OUTS_B1_6", - "CFG_CENTER_BLOCK_OUTS_B1_7", - "CFG_CENTER_BLOCK_OUTS_B1_8", - "CFG_CENTER_BLOCK_OUTS_B1_9", - "CFG_CENTER_BLOCK_OUTS_B2_0", - "CFG_CENTER_BLOCK_OUTS_B2_1", - "CFG_CENTER_BLOCK_OUTS_B2_2", - "CFG_CENTER_BLOCK_OUTS_B2_3", - "CFG_CENTER_BLOCK_OUTS_B2_4", - "CFG_CENTER_BLOCK_OUTS_B2_5", - "CFG_CENTER_BLOCK_OUTS_B2_6", - "CFG_CENTER_BLOCK_OUTS_B2_7", - "CFG_CENTER_BLOCK_OUTS_B2_8", - "CFG_CENTER_BLOCK_OUTS_B2_9", - "CFG_CENTER_BLOCK_OUTS_B3_0", - "CFG_CENTER_BLOCK_OUTS_B3_1", - "CFG_CENTER_BLOCK_OUTS_B3_2", - "CFG_CENTER_BLOCK_OUTS_B3_3", - "CFG_CENTER_BLOCK_OUTS_B3_4", - "CFG_CENTER_BLOCK_OUTS_B3_5", - "CFG_CENTER_BLOCK_OUTS_B3_6", - "CFG_CENTER_BLOCK_OUTS_B3_7", - "CFG_CENTER_BLOCK_OUTS_B3_8", - "CFG_CENTER_BLOCK_OUTS_B3_9", - "CFG_CENTER_BYP0_0", - "CFG_CENTER_BYP0_1", - "CFG_CENTER_BYP0_2", - "CFG_CENTER_BYP0_3", - "CFG_CENTER_BYP0_4", - "CFG_CENTER_BYP0_5", - "CFG_CENTER_BYP0_6", - "CFG_CENTER_BYP0_7", - "CFG_CENTER_BYP0_8", - "CFG_CENTER_BYP0_9", - "CFG_CENTER_BYP1_0", - "CFG_CENTER_BYP1_1", - "CFG_CENTER_BYP1_2", - "CFG_CENTER_BYP1_3", - "CFG_CENTER_BYP1_4", - "CFG_CENTER_BYP1_5", - "CFG_CENTER_BYP1_6", - "CFG_CENTER_BYP1_7", - "CFG_CENTER_BYP1_8", - "CFG_CENTER_BYP1_9", - "CFG_CENTER_BYP2_0", - "CFG_CENTER_BYP2_1", - "CFG_CENTER_BYP2_2", - "CFG_CENTER_BYP2_3", - "CFG_CENTER_BYP2_4", - "CFG_CENTER_BYP2_5", - "CFG_CENTER_BYP2_6", - "CFG_CENTER_BYP2_7", - "CFG_CENTER_BYP2_8", - "CFG_CENTER_BYP2_9", - "CFG_CENTER_BYP3_0", - "CFG_CENTER_BYP3_1", - "CFG_CENTER_BYP3_2", - "CFG_CENTER_BYP3_3", - "CFG_CENTER_BYP3_4", - "CFG_CENTER_BYP3_5", - "CFG_CENTER_BYP3_6", - "CFG_CENTER_BYP3_7", - "CFG_CENTER_BYP3_8", - "CFG_CENTER_BYP3_9", - "CFG_CENTER_BYP4_0", - "CFG_CENTER_BYP4_1", - "CFG_CENTER_BYP4_2", - "CFG_CENTER_BYP4_3", - "CFG_CENTER_BYP4_4", - "CFG_CENTER_BYP4_5", - "CFG_CENTER_BYP4_6", - "CFG_CENTER_BYP4_7", - "CFG_CENTER_BYP4_8", - "CFG_CENTER_BYP4_9", - "CFG_CENTER_BYP5_0", - "CFG_CENTER_BYP5_1", - "CFG_CENTER_BYP5_2", - "CFG_CENTER_BYP5_3", - "CFG_CENTER_BYP5_4", - "CFG_CENTER_BYP5_5", - "CFG_CENTER_BYP5_6", - "CFG_CENTER_BYP5_7", - "CFG_CENTER_BYP5_8", - "CFG_CENTER_BYP5_9", - "CFG_CENTER_BYP6_0", - "CFG_CENTER_BYP6_1", - "CFG_CENTER_BYP6_2", - "CFG_CENTER_BYP6_3", - "CFG_CENTER_BYP6_4", - "CFG_CENTER_BYP6_5", - "CFG_CENTER_BYP6_6", - "CFG_CENTER_BYP6_7", - "CFG_CENTER_BYP6_8", - "CFG_CENTER_BYP6_9", - "CFG_CENTER_BYP7_0", - "CFG_CENTER_BYP7_1", - "CFG_CENTER_BYP7_2", - "CFG_CENTER_BYP7_3", - "CFG_CENTER_BYP7_4", - "CFG_CENTER_BYP7_5", - "CFG_CENTER_BYP7_6", - "CFG_CENTER_BYP7_7", - "CFG_CENTER_BYP7_8", - "CFG_CENTER_BYP7_9", - "CFG_CENTER_CLK0_0", - "CFG_CENTER_CLK0_1", - "CFG_CENTER_CLK0_2", - "CFG_CENTER_CLK0_3", - "CFG_CENTER_CLK0_4", - "CFG_CENTER_CLK0_5", - "CFG_CENTER_CLK0_6", - "CFG_CENTER_CLK0_7", - "CFG_CENTER_CLK0_8", - "CFG_CENTER_CLK0_9", - "CFG_CENTER_CLK1_0", - "CFG_CENTER_CLK1_1", - "CFG_CENTER_CLK1_2", - "CFG_CENTER_CLK1_3", - "CFG_CENTER_CLK1_4", - "CFG_CENTER_CLK1_5", - "CFG_CENTER_CLK1_6", - "CFG_CENTER_CLK1_7", - "CFG_CENTER_CLK1_8", - "CFG_CENTER_CLK1_9", - "CFG_CENTER_CTRL0_0", - "CFG_CENTER_CTRL0_1", - "CFG_CENTER_CTRL0_2", - "CFG_CENTER_CTRL0_3", - "CFG_CENTER_CTRL0_4", - "CFG_CENTER_CTRL0_5", - "CFG_CENTER_CTRL0_6", - "CFG_CENTER_CTRL0_7", - "CFG_CENTER_CTRL0_8", - "CFG_CENTER_CTRL0_9", - "CFG_CENTER_CTRL1_0", - "CFG_CENTER_CTRL1_1", - "CFG_CENTER_CTRL1_2", - "CFG_CENTER_CTRL1_3", - "CFG_CENTER_CTRL1_4", - "CFG_CENTER_CTRL1_5", - "CFG_CENTER_CTRL1_6", - "CFG_CENTER_CTRL1_7", - "CFG_CENTER_CTRL1_8", - "CFG_CENTER_CTRL1_9", - "CFG_CENTER_DNA_PORT_CLK", - "CFG_CENTER_DNA_PORT_DIN", - "CFG_CENTER_DNA_PORT_DOUT", - "CFG_CENTER_DNA_PORT_READ", - "CFG_CENTER_DNA_PORT_SHIFT", - "CFG_CENTER_EE2A0_0", - "CFG_CENTER_EE2A0_1", - "CFG_CENTER_EE2A0_2", - "CFG_CENTER_EE2A0_3", - "CFG_CENTER_EE2A0_4", - "CFG_CENTER_EE2A0_5", - "CFG_CENTER_EE2A0_6", - "CFG_CENTER_EE2A0_7", - "CFG_CENTER_EE2A0_8", - "CFG_CENTER_EE2A0_9", - "CFG_CENTER_EE2A1_0", - "CFG_CENTER_EE2A1_1", - "CFG_CENTER_EE2A1_2", - "CFG_CENTER_EE2A1_3", - "CFG_CENTER_EE2A1_4", - "CFG_CENTER_EE2A1_5", - "CFG_CENTER_EE2A1_6", - "CFG_CENTER_EE2A1_7", - "CFG_CENTER_EE2A1_8", - "CFG_CENTER_EE2A1_9", - "CFG_CENTER_EE2A2_0", - "CFG_CENTER_EE2A2_1", - "CFG_CENTER_EE2A2_2", - "CFG_CENTER_EE2A2_3", - "CFG_CENTER_EE2A2_4", - "CFG_CENTER_EE2A2_5", - "CFG_CENTER_EE2A2_6", - "CFG_CENTER_EE2A2_7", - "CFG_CENTER_EE2A2_8", - "CFG_CENTER_EE2A2_9", - "CFG_CENTER_EE2A3_0", - "CFG_CENTER_EE2A3_1", - "CFG_CENTER_EE2A3_2", - "CFG_CENTER_EE2A3_3", - "CFG_CENTER_EE2A3_4", - "CFG_CENTER_EE2A3_5", - "CFG_CENTER_EE2A3_6", - "CFG_CENTER_EE2A3_7", - "CFG_CENTER_EE2A3_8", - "CFG_CENTER_EE2A3_9", - "CFG_CENTER_EE2BEG0_0", - "CFG_CENTER_EE2BEG0_1", - "CFG_CENTER_EE2BEG0_2", - "CFG_CENTER_EE2BEG0_3", - "CFG_CENTER_EE2BEG0_4", - "CFG_CENTER_EE2BEG0_5", - "CFG_CENTER_EE2BEG0_6", - "CFG_CENTER_EE2BEG0_7", - "CFG_CENTER_EE2BEG0_8", - "CFG_CENTER_EE2BEG0_9", - "CFG_CENTER_EE2BEG1_0", - "CFG_CENTER_EE2BEG1_1", - "CFG_CENTER_EE2BEG1_2", - "CFG_CENTER_EE2BEG1_3", - "CFG_CENTER_EE2BEG1_4", - "CFG_CENTER_EE2BEG1_5", - "CFG_CENTER_EE2BEG1_6", - "CFG_CENTER_EE2BEG1_7", - "CFG_CENTER_EE2BEG1_8", - "CFG_CENTER_EE2BEG1_9", - "CFG_CENTER_EE2BEG2_0", - "CFG_CENTER_EE2BEG2_1", - "CFG_CENTER_EE2BEG2_2", - "CFG_CENTER_EE2BEG2_3", - "CFG_CENTER_EE2BEG2_4", - "CFG_CENTER_EE2BEG2_5", - "CFG_CENTER_EE2BEG2_6", - "CFG_CENTER_EE2BEG2_7", - "CFG_CENTER_EE2BEG2_8", - "CFG_CENTER_EE2BEG2_9", - "CFG_CENTER_EE2BEG3_0", - "CFG_CENTER_EE2BEG3_1", - "CFG_CENTER_EE2BEG3_2", - "CFG_CENTER_EE2BEG3_3", - "CFG_CENTER_EE2BEG3_4", - "CFG_CENTER_EE2BEG3_5", - "CFG_CENTER_EE2BEG3_6", - "CFG_CENTER_EE2BEG3_7", - "CFG_CENTER_EE2BEG3_8", - "CFG_CENTER_EE2BEG3_9", - "CFG_CENTER_EE4A0_0", - "CFG_CENTER_EE4A0_1", - "CFG_CENTER_EE4A0_2", - "CFG_CENTER_EE4A0_3", - "CFG_CENTER_EE4A0_4", - "CFG_CENTER_EE4A0_5", - "CFG_CENTER_EE4A0_6", - "CFG_CENTER_EE4A0_7", - "CFG_CENTER_EE4A0_8", - "CFG_CENTER_EE4A0_9", - "CFG_CENTER_EE4A1_0", - "CFG_CENTER_EE4A1_1", - "CFG_CENTER_EE4A1_2", - "CFG_CENTER_EE4A1_3", - "CFG_CENTER_EE4A1_4", - "CFG_CENTER_EE4A1_5", - "CFG_CENTER_EE4A1_6", - "CFG_CENTER_EE4A1_7", - "CFG_CENTER_EE4A1_8", - "CFG_CENTER_EE4A1_9", - "CFG_CENTER_EE4A2_0", - "CFG_CENTER_EE4A2_1", - "CFG_CENTER_EE4A2_2", - "CFG_CENTER_EE4A2_3", - "CFG_CENTER_EE4A2_4", - "CFG_CENTER_EE4A2_5", - "CFG_CENTER_EE4A2_6", - "CFG_CENTER_EE4A2_7", - "CFG_CENTER_EE4A2_8", - "CFG_CENTER_EE4A2_9", - "CFG_CENTER_EE4A3_0", - "CFG_CENTER_EE4A3_1", - "CFG_CENTER_EE4A3_2", - "CFG_CENTER_EE4A3_3", - "CFG_CENTER_EE4A3_4", - "CFG_CENTER_EE4A3_5", - "CFG_CENTER_EE4A3_6", - "CFG_CENTER_EE4A3_7", - "CFG_CENTER_EE4A3_8", - "CFG_CENTER_EE4A3_9", - "CFG_CENTER_EE4B0_0", - "CFG_CENTER_EE4B0_1", - "CFG_CENTER_EE4B0_2", - "CFG_CENTER_EE4B0_3", - "CFG_CENTER_EE4B0_4", - "CFG_CENTER_EE4B0_5", - "CFG_CENTER_EE4B0_6", - "CFG_CENTER_EE4B0_7", - "CFG_CENTER_EE4B0_8", - "CFG_CENTER_EE4B0_9", - "CFG_CENTER_EE4B1_0", - "CFG_CENTER_EE4B1_1", - "CFG_CENTER_EE4B1_2", - "CFG_CENTER_EE4B1_3", - "CFG_CENTER_EE4B1_4", - "CFG_CENTER_EE4B1_5", - "CFG_CENTER_EE4B1_6", - "CFG_CENTER_EE4B1_7", - "CFG_CENTER_EE4B1_8", - "CFG_CENTER_EE4B1_9", - "CFG_CENTER_EE4B2_0", - "CFG_CENTER_EE4B2_1", - "CFG_CENTER_EE4B2_2", - "CFG_CENTER_EE4B2_3", - "CFG_CENTER_EE4B2_4", - "CFG_CENTER_EE4B2_5", - "CFG_CENTER_EE4B2_6", - "CFG_CENTER_EE4B2_7", - "CFG_CENTER_EE4B2_8", - "CFG_CENTER_EE4B2_9", - "CFG_CENTER_EE4B3_0", - "CFG_CENTER_EE4B3_1", - "CFG_CENTER_EE4B3_2", - "CFG_CENTER_EE4B3_3", - "CFG_CENTER_EE4B3_4", - "CFG_CENTER_EE4B3_5", - "CFG_CENTER_EE4B3_6", - "CFG_CENTER_EE4B3_7", - "CFG_CENTER_EE4B3_8", - "CFG_CENTER_EE4B3_9", - "CFG_CENTER_EE4BEG0_0", - "CFG_CENTER_EE4BEG0_1", - "CFG_CENTER_EE4BEG0_2", - "CFG_CENTER_EE4BEG0_3", - "CFG_CENTER_EE4BEG0_4", - "CFG_CENTER_EE4BEG0_5", - "CFG_CENTER_EE4BEG0_6", - "CFG_CENTER_EE4BEG0_7", - "CFG_CENTER_EE4BEG0_8", - "CFG_CENTER_EE4BEG0_9", - "CFG_CENTER_EE4BEG1_0", - "CFG_CENTER_EE4BEG1_1", - "CFG_CENTER_EE4BEG1_2", - "CFG_CENTER_EE4BEG1_3", - "CFG_CENTER_EE4BEG1_4", - "CFG_CENTER_EE4BEG1_5", - "CFG_CENTER_EE4BEG1_6", - "CFG_CENTER_EE4BEG1_7", - "CFG_CENTER_EE4BEG1_8", - "CFG_CENTER_EE4BEG1_9", - "CFG_CENTER_EE4BEG2_0", - "CFG_CENTER_EE4BEG2_1", - "CFG_CENTER_EE4BEG2_2", - "CFG_CENTER_EE4BEG2_3", - "CFG_CENTER_EE4BEG2_4", - "CFG_CENTER_EE4BEG2_5", - "CFG_CENTER_EE4BEG2_6", - "CFG_CENTER_EE4BEG2_7", - "CFG_CENTER_EE4BEG2_8", - "CFG_CENTER_EE4BEG2_9", - "CFG_CENTER_EE4BEG3_0", - "CFG_CENTER_EE4BEG3_1", - "CFG_CENTER_EE4BEG3_2", - "CFG_CENTER_EE4BEG3_3", - "CFG_CENTER_EE4BEG3_4", - "CFG_CENTER_EE4BEG3_5", - "CFG_CENTER_EE4BEG3_6", - "CFG_CENTER_EE4BEG3_7", - "CFG_CENTER_EE4BEG3_8", - "CFG_CENTER_EE4BEG3_9", - "CFG_CENTER_EE4C0_0", - "CFG_CENTER_EE4C0_1", - "CFG_CENTER_EE4C0_2", - "CFG_CENTER_EE4C0_3", - "CFG_CENTER_EE4C0_4", - "CFG_CENTER_EE4C0_5", - "CFG_CENTER_EE4C0_6", - "CFG_CENTER_EE4C0_7", - "CFG_CENTER_EE4C0_8", - "CFG_CENTER_EE4C0_9", - "CFG_CENTER_EE4C1_0", - "CFG_CENTER_EE4C1_1", - "CFG_CENTER_EE4C1_2", - "CFG_CENTER_EE4C1_3", - "CFG_CENTER_EE4C1_4", - "CFG_CENTER_EE4C1_5", - "CFG_CENTER_EE4C1_6", - "CFG_CENTER_EE4C1_7", - "CFG_CENTER_EE4C1_8", - "CFG_CENTER_EE4C1_9", - "CFG_CENTER_EE4C2_0", - "CFG_CENTER_EE4C2_1", - "CFG_CENTER_EE4C2_2", - "CFG_CENTER_EE4C2_3", - "CFG_CENTER_EE4C2_4", - "CFG_CENTER_EE4C2_5", - "CFG_CENTER_EE4C2_6", - "CFG_CENTER_EE4C2_7", - "CFG_CENTER_EE4C2_8", - "CFG_CENTER_EE4C2_9", - "CFG_CENTER_EE4C3_0", - "CFG_CENTER_EE4C3_1", - "CFG_CENTER_EE4C3_2", - "CFG_CENTER_EE4C3_3", - "CFG_CENTER_EE4C3_4", - "CFG_CENTER_EE4C3_5", - "CFG_CENTER_EE4C3_6", - "CFG_CENTER_EE4C3_7", - "CFG_CENTER_EE4C3_8", - "CFG_CENTER_EE4C3_9", - "CFG_CENTER_EFUSE_USR_EFUSEUSR0", - "CFG_CENTER_EFUSE_USR_EFUSEUSR1", - "CFG_CENTER_EFUSE_USR_EFUSEUSR10", - "CFG_CENTER_EFUSE_USR_EFUSEUSR11", - "CFG_CENTER_EFUSE_USR_EFUSEUSR12", - "CFG_CENTER_EFUSE_USR_EFUSEUSR13", - "CFG_CENTER_EFUSE_USR_EFUSEUSR14", - "CFG_CENTER_EFUSE_USR_EFUSEUSR15", - "CFG_CENTER_EFUSE_USR_EFUSEUSR16", - "CFG_CENTER_EFUSE_USR_EFUSEUSR17", - "CFG_CENTER_EFUSE_USR_EFUSEUSR18", - "CFG_CENTER_EFUSE_USR_EFUSEUSR19", - "CFG_CENTER_EFUSE_USR_EFUSEUSR2", - "CFG_CENTER_EFUSE_USR_EFUSEUSR20", - "CFG_CENTER_EFUSE_USR_EFUSEUSR21", - "CFG_CENTER_EFUSE_USR_EFUSEUSR22", - "CFG_CENTER_EFUSE_USR_EFUSEUSR23", - "CFG_CENTER_EFUSE_USR_EFUSEUSR24", - "CFG_CENTER_EFUSE_USR_EFUSEUSR25", - "CFG_CENTER_EFUSE_USR_EFUSEUSR26", - "CFG_CENTER_EFUSE_USR_EFUSEUSR27", - "CFG_CENTER_EFUSE_USR_EFUSEUSR28", - "CFG_CENTER_EFUSE_USR_EFUSEUSR29", - "CFG_CENTER_EFUSE_USR_EFUSEUSR3", - "CFG_CENTER_EFUSE_USR_EFUSEUSR30", - "CFG_CENTER_EFUSE_USR_EFUSEUSR31", - "CFG_CENTER_EFUSE_USR_EFUSEUSR4", - "CFG_CENTER_EFUSE_USR_EFUSEUSR5", - "CFG_CENTER_EFUSE_USR_EFUSEUSR6", - "CFG_CENTER_EFUSE_USR_EFUSEUSR7", - "CFG_CENTER_EFUSE_USR_EFUSEUSR8", - "CFG_CENTER_EFUSE_USR_EFUSEUSR9", - "CFG_CENTER_EL1BEG0_0", - "CFG_CENTER_EL1BEG0_1", - "CFG_CENTER_EL1BEG0_2", - "CFG_CENTER_EL1BEG0_3", - "CFG_CENTER_EL1BEG0_4", - "CFG_CENTER_EL1BEG0_5", - "CFG_CENTER_EL1BEG0_6", - "CFG_CENTER_EL1BEG0_7", - "CFG_CENTER_EL1BEG0_8", - "CFG_CENTER_EL1BEG0_9", - "CFG_CENTER_EL1BEG1_0", - "CFG_CENTER_EL1BEG1_1", - "CFG_CENTER_EL1BEG1_2", - "CFG_CENTER_EL1BEG1_3", - "CFG_CENTER_EL1BEG1_4", - "CFG_CENTER_EL1BEG1_5", - "CFG_CENTER_EL1BEG1_6", - "CFG_CENTER_EL1BEG1_7", - "CFG_CENTER_EL1BEG1_8", - "CFG_CENTER_EL1BEG1_9", - "CFG_CENTER_EL1BEG2_0", - "CFG_CENTER_EL1BEG2_1", - "CFG_CENTER_EL1BEG2_2", - "CFG_CENTER_EL1BEG2_3", - "CFG_CENTER_EL1BEG2_4", - "CFG_CENTER_EL1BEG2_5", - "CFG_CENTER_EL1BEG2_6", - "CFG_CENTER_EL1BEG2_7", - "CFG_CENTER_EL1BEG2_8", - "CFG_CENTER_EL1BEG2_9", - "CFG_CENTER_EL1BEG3_0", - "CFG_CENTER_EL1BEG3_1", - "CFG_CENTER_EL1BEG3_2", - "CFG_CENTER_EL1BEG3_3", - "CFG_CENTER_EL1BEG3_4", - "CFG_CENTER_EL1BEG3_5", - "CFG_CENTER_EL1BEG3_6", - "CFG_CENTER_EL1BEG3_7", - "CFG_CENTER_EL1BEG3_8", - "CFG_CENTER_EL1BEG3_9", - "CFG_CENTER_ER1BEG0_0", - "CFG_CENTER_ER1BEG0_1", - "CFG_CENTER_ER1BEG0_2", - "CFG_CENTER_ER1BEG0_3", - "CFG_CENTER_ER1BEG0_4", - "CFG_CENTER_ER1BEG0_5", - "CFG_CENTER_ER1BEG0_6", - "CFG_CENTER_ER1BEG0_7", - "CFG_CENTER_ER1BEG0_8", - "CFG_CENTER_ER1BEG0_9", - "CFG_CENTER_ER1BEG1_0", - "CFG_CENTER_ER1BEG1_1", - "CFG_CENTER_ER1BEG1_2", - "CFG_CENTER_ER1BEG1_3", - "CFG_CENTER_ER1BEG1_4", - "CFG_CENTER_ER1BEG1_5", - "CFG_CENTER_ER1BEG1_6", - "CFG_CENTER_ER1BEG1_7", - "CFG_CENTER_ER1BEG1_8", - "CFG_CENTER_ER1BEG1_9", - "CFG_CENTER_ER1BEG2_0", - "CFG_CENTER_ER1BEG2_1", - "CFG_CENTER_ER1BEG2_2", - "CFG_CENTER_ER1BEG2_3", - "CFG_CENTER_ER1BEG2_4", - "CFG_CENTER_ER1BEG2_5", - "CFG_CENTER_ER1BEG2_6", - "CFG_CENTER_ER1BEG2_7", - "CFG_CENTER_ER1BEG2_8", - "CFG_CENTER_ER1BEG2_9", - "CFG_CENTER_ER1BEG3_0", - "CFG_CENTER_ER1BEG3_1", - "CFG_CENTER_ER1BEG3_2", - "CFG_CENTER_ER1BEG3_3", - "CFG_CENTER_ER1BEG3_4", - "CFG_CENTER_ER1BEG3_5", - "CFG_CENTER_ER1BEG3_6", - "CFG_CENTER_ER1BEG3_7", - "CFG_CENTER_ER1BEG3_8", - "CFG_CENTER_ER1BEG3_9", - "CFG_CENTER_FAN0_0", - "CFG_CENTER_FAN0_1", - "CFG_CENTER_FAN0_2", - "CFG_CENTER_FAN0_3", - "CFG_CENTER_FAN0_4", - "CFG_CENTER_FAN0_5", - "CFG_CENTER_FAN0_6", - "CFG_CENTER_FAN0_7", - "CFG_CENTER_FAN0_8", - "CFG_CENTER_FAN0_9", - "CFG_CENTER_FAN1_0", - "CFG_CENTER_FAN1_1", - "CFG_CENTER_FAN1_2", - "CFG_CENTER_FAN1_3", - "CFG_CENTER_FAN1_4", - "CFG_CENTER_FAN1_5", - "CFG_CENTER_FAN1_6", - "CFG_CENTER_FAN1_7", - "CFG_CENTER_FAN1_8", - "CFG_CENTER_FAN1_9", - "CFG_CENTER_FAN2_0", - "CFG_CENTER_FAN2_1", - "CFG_CENTER_FAN2_2", - "CFG_CENTER_FAN2_3", - "CFG_CENTER_FAN2_4", - "CFG_CENTER_FAN2_5", - "CFG_CENTER_FAN2_6", - "CFG_CENTER_FAN2_7", - "CFG_CENTER_FAN2_8", - "CFG_CENTER_FAN2_9", - "CFG_CENTER_FAN3_0", - "CFG_CENTER_FAN3_1", - "CFG_CENTER_FAN3_2", - "CFG_CENTER_FAN3_3", - "CFG_CENTER_FAN3_4", - "CFG_CENTER_FAN3_5", - "CFG_CENTER_FAN3_6", - "CFG_CENTER_FAN3_7", - "CFG_CENTER_FAN3_8", - "CFG_CENTER_FAN3_9", - "CFG_CENTER_FAN4_0", - "CFG_CENTER_FAN4_1", - "CFG_CENTER_FAN4_2", - "CFG_CENTER_FAN4_3", - "CFG_CENTER_FAN4_4", - "CFG_CENTER_FAN4_5", - "CFG_CENTER_FAN4_6", - "CFG_CENTER_FAN4_7", - "CFG_CENTER_FAN4_8", - "CFG_CENTER_FAN4_9", - "CFG_CENTER_FAN5_0", - "CFG_CENTER_FAN5_1", - "CFG_CENTER_FAN5_2", - "CFG_CENTER_FAN5_3", - "CFG_CENTER_FAN5_4", - "CFG_CENTER_FAN5_5", - "CFG_CENTER_FAN5_6", - "CFG_CENTER_FAN5_7", - "CFG_CENTER_FAN5_8", - "CFG_CENTER_FAN5_9", - "CFG_CENTER_FAN6_0", - "CFG_CENTER_FAN6_1", - "CFG_CENTER_FAN6_2", - "CFG_CENTER_FAN6_3", - "CFG_CENTER_FAN6_4", - "CFG_CENTER_FAN6_5", - "CFG_CENTER_FAN6_6", - "CFG_CENTER_FAN6_7", - "CFG_CENTER_FAN6_8", - "CFG_CENTER_FAN6_9", - "CFG_CENTER_FAN7_0", - "CFG_CENTER_FAN7_1", - "CFG_CENTER_FAN7_2", - "CFG_CENTER_FAN7_3", - "CFG_CENTER_FAN7_4", - "CFG_CENTER_FAN7_5", - "CFG_CENTER_FAN7_6", - "CFG_CENTER_FAN7_7", - "CFG_CENTER_FAN7_8", - "CFG_CENTER_FAN7_9", - "CFG_CENTER_IMUX0_0", - "CFG_CENTER_IMUX0_1", - "CFG_CENTER_IMUX0_2", - "CFG_CENTER_IMUX0_3", - "CFG_CENTER_IMUX0_4", - "CFG_CENTER_IMUX0_5", - "CFG_CENTER_IMUX0_6", - "CFG_CENTER_IMUX0_7", - "CFG_CENTER_IMUX0_8", - "CFG_CENTER_IMUX0_9", - "CFG_CENTER_IMUX10_0", - "CFG_CENTER_IMUX10_1", - "CFG_CENTER_IMUX10_2", - "CFG_CENTER_IMUX10_3", - "CFG_CENTER_IMUX10_4", - "CFG_CENTER_IMUX10_5", - "CFG_CENTER_IMUX10_6", - "CFG_CENTER_IMUX10_7", - "CFG_CENTER_IMUX10_8", - "CFG_CENTER_IMUX10_9", - "CFG_CENTER_IMUX11_0", - "CFG_CENTER_IMUX11_1", - "CFG_CENTER_IMUX11_2", - "CFG_CENTER_IMUX11_3", - "CFG_CENTER_IMUX11_4", - "CFG_CENTER_IMUX11_5", - "CFG_CENTER_IMUX11_6", - "CFG_CENTER_IMUX11_7", - "CFG_CENTER_IMUX11_8", - "CFG_CENTER_IMUX11_9", - "CFG_CENTER_IMUX12_0", - "CFG_CENTER_IMUX12_1", - "CFG_CENTER_IMUX12_2", - "CFG_CENTER_IMUX12_3", - "CFG_CENTER_IMUX12_4", - "CFG_CENTER_IMUX12_5", - "CFG_CENTER_IMUX12_6", - "CFG_CENTER_IMUX12_7", - "CFG_CENTER_IMUX12_8", - "CFG_CENTER_IMUX12_9", - "CFG_CENTER_IMUX13_0", - "CFG_CENTER_IMUX13_1", - "CFG_CENTER_IMUX13_2", - "CFG_CENTER_IMUX13_3", - "CFG_CENTER_IMUX13_4", - "CFG_CENTER_IMUX13_5", - "CFG_CENTER_IMUX13_6", - "CFG_CENTER_IMUX13_7", - "CFG_CENTER_IMUX13_8", - "CFG_CENTER_IMUX13_9", - "CFG_CENTER_IMUX14_0", - "CFG_CENTER_IMUX14_1", - "CFG_CENTER_IMUX14_2", - "CFG_CENTER_IMUX14_3", - "CFG_CENTER_IMUX14_4", - "CFG_CENTER_IMUX14_5", - "CFG_CENTER_IMUX14_6", - "CFG_CENTER_IMUX14_7", - "CFG_CENTER_IMUX14_8", - "CFG_CENTER_IMUX14_9", - "CFG_CENTER_IMUX15_0", - "CFG_CENTER_IMUX15_1", - "CFG_CENTER_IMUX15_2", - "CFG_CENTER_IMUX15_3", - "CFG_CENTER_IMUX15_4", - "CFG_CENTER_IMUX15_5", - "CFG_CENTER_IMUX15_6", - "CFG_CENTER_IMUX15_7", - "CFG_CENTER_IMUX15_8", - "CFG_CENTER_IMUX15_9", - "CFG_CENTER_IMUX16_0", - "CFG_CENTER_IMUX16_1", - "CFG_CENTER_IMUX16_2", - "CFG_CENTER_IMUX16_3", - "CFG_CENTER_IMUX16_4", - "CFG_CENTER_IMUX16_5", - "CFG_CENTER_IMUX16_6", - "CFG_CENTER_IMUX16_7", - "CFG_CENTER_IMUX16_8", - "CFG_CENTER_IMUX16_9", - "CFG_CENTER_IMUX17_0", - "CFG_CENTER_IMUX17_1", - "CFG_CENTER_IMUX17_2", - "CFG_CENTER_IMUX17_3", - "CFG_CENTER_IMUX17_4", - "CFG_CENTER_IMUX17_5", - "CFG_CENTER_IMUX17_6", - "CFG_CENTER_IMUX17_7", - "CFG_CENTER_IMUX17_8", - "CFG_CENTER_IMUX17_9", - "CFG_CENTER_IMUX18_0", - "CFG_CENTER_IMUX18_1", - "CFG_CENTER_IMUX18_2", - "CFG_CENTER_IMUX18_3", - "CFG_CENTER_IMUX18_4", - "CFG_CENTER_IMUX18_5", - "CFG_CENTER_IMUX18_6", - "CFG_CENTER_IMUX18_7", - "CFG_CENTER_IMUX18_8", - "CFG_CENTER_IMUX18_9", - "CFG_CENTER_IMUX19_0", - "CFG_CENTER_IMUX19_1", - "CFG_CENTER_IMUX19_2", - "CFG_CENTER_IMUX19_3", - "CFG_CENTER_IMUX19_4", - "CFG_CENTER_IMUX19_5", - "CFG_CENTER_IMUX19_6", - "CFG_CENTER_IMUX19_7", - "CFG_CENTER_IMUX19_8", - "CFG_CENTER_IMUX19_9", - "CFG_CENTER_IMUX1_0", - "CFG_CENTER_IMUX1_1", - "CFG_CENTER_IMUX1_2", - "CFG_CENTER_IMUX1_3", - "CFG_CENTER_IMUX1_4", - "CFG_CENTER_IMUX1_5", - "CFG_CENTER_IMUX1_6", - "CFG_CENTER_IMUX1_7", - "CFG_CENTER_IMUX1_8", - "CFG_CENTER_IMUX1_9", - "CFG_CENTER_IMUX20_0", - "CFG_CENTER_IMUX20_1", - "CFG_CENTER_IMUX20_2", - "CFG_CENTER_IMUX20_3", - "CFG_CENTER_IMUX20_4", - "CFG_CENTER_IMUX20_5", - "CFG_CENTER_IMUX20_6", - "CFG_CENTER_IMUX20_7", - "CFG_CENTER_IMUX20_8", - "CFG_CENTER_IMUX20_9", - "CFG_CENTER_IMUX21_0", - "CFG_CENTER_IMUX21_1", - "CFG_CENTER_IMUX21_2", - "CFG_CENTER_IMUX21_3", - "CFG_CENTER_IMUX21_4", - "CFG_CENTER_IMUX21_5", - "CFG_CENTER_IMUX21_6", - "CFG_CENTER_IMUX21_7", - "CFG_CENTER_IMUX21_8", - "CFG_CENTER_IMUX21_9", - "CFG_CENTER_IMUX22_0", - "CFG_CENTER_IMUX22_1", - "CFG_CENTER_IMUX22_2", - "CFG_CENTER_IMUX22_3", - "CFG_CENTER_IMUX22_4", - "CFG_CENTER_IMUX22_5", - "CFG_CENTER_IMUX22_6", - "CFG_CENTER_IMUX22_7", - "CFG_CENTER_IMUX22_8", - "CFG_CENTER_IMUX22_9", - "CFG_CENTER_IMUX23_0", - "CFG_CENTER_IMUX23_1", - "CFG_CENTER_IMUX23_2", - "CFG_CENTER_IMUX23_3", - "CFG_CENTER_IMUX23_4", - "CFG_CENTER_IMUX23_5", - "CFG_CENTER_IMUX23_6", - "CFG_CENTER_IMUX23_7", - "CFG_CENTER_IMUX23_8", - "CFG_CENTER_IMUX23_9", - "CFG_CENTER_IMUX24_0", - "CFG_CENTER_IMUX24_1", - "CFG_CENTER_IMUX24_2", - "CFG_CENTER_IMUX24_3", - "CFG_CENTER_IMUX24_4", - "CFG_CENTER_IMUX24_5", - "CFG_CENTER_IMUX24_6", - "CFG_CENTER_IMUX24_7", - "CFG_CENTER_IMUX24_8", - "CFG_CENTER_IMUX24_9", - "CFG_CENTER_IMUX25_0", - "CFG_CENTER_IMUX25_1", - "CFG_CENTER_IMUX25_2", - "CFG_CENTER_IMUX25_3", - "CFG_CENTER_IMUX25_4", - "CFG_CENTER_IMUX25_5", - "CFG_CENTER_IMUX25_6", - "CFG_CENTER_IMUX25_7", - "CFG_CENTER_IMUX25_8", - "CFG_CENTER_IMUX25_9", - "CFG_CENTER_IMUX26_0", - "CFG_CENTER_IMUX26_1", - "CFG_CENTER_IMUX26_2", - "CFG_CENTER_IMUX26_3", - "CFG_CENTER_IMUX26_4", - "CFG_CENTER_IMUX26_5", - "CFG_CENTER_IMUX26_6", - "CFG_CENTER_IMUX26_7", - "CFG_CENTER_IMUX26_8", - "CFG_CENTER_IMUX26_9", - "CFG_CENTER_IMUX27_0", - "CFG_CENTER_IMUX27_1", - "CFG_CENTER_IMUX27_2", - "CFG_CENTER_IMUX27_3", - "CFG_CENTER_IMUX27_4", - "CFG_CENTER_IMUX27_5", - "CFG_CENTER_IMUX27_6", - "CFG_CENTER_IMUX27_7", - "CFG_CENTER_IMUX27_8", - "CFG_CENTER_IMUX27_9", - "CFG_CENTER_IMUX28_0", - "CFG_CENTER_IMUX28_1", - "CFG_CENTER_IMUX28_2", - "CFG_CENTER_IMUX28_3", - "CFG_CENTER_IMUX28_4", - "CFG_CENTER_IMUX28_5", - "CFG_CENTER_IMUX28_6", - "CFG_CENTER_IMUX28_7", - "CFG_CENTER_IMUX28_8", - "CFG_CENTER_IMUX28_9", - "CFG_CENTER_IMUX29_0", - "CFG_CENTER_IMUX29_1", - "CFG_CENTER_IMUX29_2", - "CFG_CENTER_IMUX29_3", - "CFG_CENTER_IMUX29_4", - "CFG_CENTER_IMUX29_5", - "CFG_CENTER_IMUX29_6", - "CFG_CENTER_IMUX29_7", - "CFG_CENTER_IMUX29_8", - "CFG_CENTER_IMUX29_9", - "CFG_CENTER_IMUX2_0", - "CFG_CENTER_IMUX2_1", - "CFG_CENTER_IMUX2_2", - "CFG_CENTER_IMUX2_3", - "CFG_CENTER_IMUX2_4", - "CFG_CENTER_IMUX2_5", - "CFG_CENTER_IMUX2_6", - "CFG_CENTER_IMUX2_7", - "CFG_CENTER_IMUX2_8", - "CFG_CENTER_IMUX2_9", - "CFG_CENTER_IMUX30_0", - "CFG_CENTER_IMUX30_1", - "CFG_CENTER_IMUX30_2", - "CFG_CENTER_IMUX30_3", - "CFG_CENTER_IMUX30_4", - "CFG_CENTER_IMUX30_5", - "CFG_CENTER_IMUX30_6", - "CFG_CENTER_IMUX30_7", - "CFG_CENTER_IMUX30_8", - "CFG_CENTER_IMUX30_9", - "CFG_CENTER_IMUX31_0", - "CFG_CENTER_IMUX31_1", - "CFG_CENTER_IMUX31_2", - "CFG_CENTER_IMUX31_3", - "CFG_CENTER_IMUX31_4", - "CFG_CENTER_IMUX31_5", - "CFG_CENTER_IMUX31_6", - "CFG_CENTER_IMUX31_7", - "CFG_CENTER_IMUX31_8", - "CFG_CENTER_IMUX31_9", - "CFG_CENTER_IMUX32_0", - "CFG_CENTER_IMUX32_1", - "CFG_CENTER_IMUX32_2", - "CFG_CENTER_IMUX32_3", - "CFG_CENTER_IMUX32_4", - "CFG_CENTER_IMUX32_5", - "CFG_CENTER_IMUX32_6", - "CFG_CENTER_IMUX32_7", - "CFG_CENTER_IMUX32_8", - "CFG_CENTER_IMUX32_9", - "CFG_CENTER_IMUX33_0", - "CFG_CENTER_IMUX33_1", - "CFG_CENTER_IMUX33_2", - "CFG_CENTER_IMUX33_3", - "CFG_CENTER_IMUX33_4", - "CFG_CENTER_IMUX33_5", - "CFG_CENTER_IMUX33_6", - "CFG_CENTER_IMUX33_7", - "CFG_CENTER_IMUX33_8", - "CFG_CENTER_IMUX33_9", - "CFG_CENTER_IMUX34_0", - "CFG_CENTER_IMUX34_1", - "CFG_CENTER_IMUX34_2", - "CFG_CENTER_IMUX34_3", - "CFG_CENTER_IMUX34_4", - "CFG_CENTER_IMUX34_5", - "CFG_CENTER_IMUX34_6", - "CFG_CENTER_IMUX34_7", - "CFG_CENTER_IMUX34_8", - "CFG_CENTER_IMUX34_9", - "CFG_CENTER_IMUX35_0", - "CFG_CENTER_IMUX35_1", - "CFG_CENTER_IMUX35_2", - "CFG_CENTER_IMUX35_3", - "CFG_CENTER_IMUX35_4", - "CFG_CENTER_IMUX35_5", - "CFG_CENTER_IMUX35_6", - "CFG_CENTER_IMUX35_7", - "CFG_CENTER_IMUX35_8", - "CFG_CENTER_IMUX35_9", - "CFG_CENTER_IMUX36_0", - "CFG_CENTER_IMUX36_1", - "CFG_CENTER_IMUX36_2", - "CFG_CENTER_IMUX36_3", - "CFG_CENTER_IMUX36_4", - "CFG_CENTER_IMUX36_5", - "CFG_CENTER_IMUX36_6", - "CFG_CENTER_IMUX36_7", - "CFG_CENTER_IMUX36_8", - "CFG_CENTER_IMUX36_9", - "CFG_CENTER_IMUX37_0", - "CFG_CENTER_IMUX37_1", - "CFG_CENTER_IMUX37_2", - "CFG_CENTER_IMUX37_3", - "CFG_CENTER_IMUX37_4", - "CFG_CENTER_IMUX37_5", - "CFG_CENTER_IMUX37_6", - "CFG_CENTER_IMUX37_7", - "CFG_CENTER_IMUX37_8", - "CFG_CENTER_IMUX37_9", - "CFG_CENTER_IMUX38_0", - "CFG_CENTER_IMUX38_1", - "CFG_CENTER_IMUX38_2", - "CFG_CENTER_IMUX38_3", - "CFG_CENTER_IMUX38_4", - "CFG_CENTER_IMUX38_5", - "CFG_CENTER_IMUX38_6", - "CFG_CENTER_IMUX38_7", - "CFG_CENTER_IMUX38_8", - "CFG_CENTER_IMUX38_9", - "CFG_CENTER_IMUX39_0", - "CFG_CENTER_IMUX39_1", - "CFG_CENTER_IMUX39_2", - "CFG_CENTER_IMUX39_3", - "CFG_CENTER_IMUX39_4", - "CFG_CENTER_IMUX39_5", - "CFG_CENTER_IMUX39_6", - "CFG_CENTER_IMUX39_7", - "CFG_CENTER_IMUX39_8", - "CFG_CENTER_IMUX39_9", - "CFG_CENTER_IMUX3_0", - "CFG_CENTER_IMUX3_1", - "CFG_CENTER_IMUX3_2", - "CFG_CENTER_IMUX3_3", - "CFG_CENTER_IMUX3_4", - "CFG_CENTER_IMUX3_5", - "CFG_CENTER_IMUX3_6", - "CFG_CENTER_IMUX3_7", - "CFG_CENTER_IMUX3_8", - "CFG_CENTER_IMUX3_9", - "CFG_CENTER_IMUX40_0", - "CFG_CENTER_IMUX40_1", - "CFG_CENTER_IMUX40_2", - "CFG_CENTER_IMUX40_3", - "CFG_CENTER_IMUX40_4", - "CFG_CENTER_IMUX40_5", - "CFG_CENTER_IMUX40_6", - "CFG_CENTER_IMUX40_7", - "CFG_CENTER_IMUX40_8", - "CFG_CENTER_IMUX40_9", - "CFG_CENTER_IMUX41_0", - "CFG_CENTER_IMUX41_1", - "CFG_CENTER_IMUX41_2", - "CFG_CENTER_IMUX41_3", - "CFG_CENTER_IMUX41_4", - "CFG_CENTER_IMUX41_5", - "CFG_CENTER_IMUX41_6", - "CFG_CENTER_IMUX41_7", - "CFG_CENTER_IMUX41_8", - "CFG_CENTER_IMUX41_9", - "CFG_CENTER_IMUX42_0", - "CFG_CENTER_IMUX42_1", - "CFG_CENTER_IMUX42_2", - "CFG_CENTER_IMUX42_3", - "CFG_CENTER_IMUX42_4", - "CFG_CENTER_IMUX42_5", - "CFG_CENTER_IMUX42_6", - "CFG_CENTER_IMUX42_7", - "CFG_CENTER_IMUX42_8", - "CFG_CENTER_IMUX42_9", - "CFG_CENTER_IMUX43_0", - "CFG_CENTER_IMUX43_1", - "CFG_CENTER_IMUX43_2", - "CFG_CENTER_IMUX43_3", - "CFG_CENTER_IMUX43_4", - "CFG_CENTER_IMUX43_5", - "CFG_CENTER_IMUX43_6", - "CFG_CENTER_IMUX43_7", - "CFG_CENTER_IMUX43_8", - "CFG_CENTER_IMUX43_9", - "CFG_CENTER_IMUX44_0", - "CFG_CENTER_IMUX44_1", - "CFG_CENTER_IMUX44_2", - "CFG_CENTER_IMUX44_3", - "CFG_CENTER_IMUX44_4", - "CFG_CENTER_IMUX44_5", - "CFG_CENTER_IMUX44_6", - "CFG_CENTER_IMUX44_7", - "CFG_CENTER_IMUX44_8", - "CFG_CENTER_IMUX44_9", - "CFG_CENTER_IMUX45_0", - "CFG_CENTER_IMUX45_1", - "CFG_CENTER_IMUX45_2", - "CFG_CENTER_IMUX45_3", - "CFG_CENTER_IMUX45_4", - "CFG_CENTER_IMUX45_5", - "CFG_CENTER_IMUX45_6", - "CFG_CENTER_IMUX45_7", - "CFG_CENTER_IMUX45_8", - "CFG_CENTER_IMUX45_9", - "CFG_CENTER_IMUX46_0", - "CFG_CENTER_IMUX46_1", - "CFG_CENTER_IMUX46_2", - "CFG_CENTER_IMUX46_3", - "CFG_CENTER_IMUX46_4", - "CFG_CENTER_IMUX46_5", - "CFG_CENTER_IMUX46_6", - "CFG_CENTER_IMUX46_7", - "CFG_CENTER_IMUX46_8", - "CFG_CENTER_IMUX46_9", - "CFG_CENTER_IMUX47_0", - "CFG_CENTER_IMUX47_1", - "CFG_CENTER_IMUX47_2", - "CFG_CENTER_IMUX47_3", - "CFG_CENTER_IMUX47_4", - "CFG_CENTER_IMUX47_5", - "CFG_CENTER_IMUX47_6", - "CFG_CENTER_IMUX47_7", - "CFG_CENTER_IMUX47_8", - "CFG_CENTER_IMUX47_9", - "CFG_CENTER_IMUX4_0", - "CFG_CENTER_IMUX4_1", - "CFG_CENTER_IMUX4_2", - "CFG_CENTER_IMUX4_3", - "CFG_CENTER_IMUX4_4", - "CFG_CENTER_IMUX4_5", - "CFG_CENTER_IMUX4_6", - "CFG_CENTER_IMUX4_7", - "CFG_CENTER_IMUX4_8", - "CFG_CENTER_IMUX4_9", - "CFG_CENTER_IMUX5_0", - "CFG_CENTER_IMUX5_1", - "CFG_CENTER_IMUX5_2", - "CFG_CENTER_IMUX5_3", - "CFG_CENTER_IMUX5_4", - "CFG_CENTER_IMUX5_5", - "CFG_CENTER_IMUX5_6", - "CFG_CENTER_IMUX5_7", - "CFG_CENTER_IMUX5_8", - "CFG_CENTER_IMUX5_9", - "CFG_CENTER_IMUX6_0", - "CFG_CENTER_IMUX6_1", - "CFG_CENTER_IMUX6_2", - "CFG_CENTER_IMUX6_3", - "CFG_CENTER_IMUX6_4", - "CFG_CENTER_IMUX6_5", - "CFG_CENTER_IMUX6_6", - "CFG_CENTER_IMUX6_7", - "CFG_CENTER_IMUX6_8", - "CFG_CENTER_IMUX6_9", - "CFG_CENTER_IMUX7_0", - "CFG_CENTER_IMUX7_1", - "CFG_CENTER_IMUX7_2", - "CFG_CENTER_IMUX7_3", - "CFG_CENTER_IMUX7_4", - "CFG_CENTER_IMUX7_5", - "CFG_CENTER_IMUX7_6", - "CFG_CENTER_IMUX7_7", - "CFG_CENTER_IMUX7_8", - "CFG_CENTER_IMUX7_9", - "CFG_CENTER_IMUX8_0", - "CFG_CENTER_IMUX8_1", - "CFG_CENTER_IMUX8_2", - "CFG_CENTER_IMUX8_3", - "CFG_CENTER_IMUX8_4", - "CFG_CENTER_IMUX8_5", - "CFG_CENTER_IMUX8_6", - "CFG_CENTER_IMUX8_7", - "CFG_CENTER_IMUX8_8", - "CFG_CENTER_IMUX8_9", - "CFG_CENTER_IMUX9_0", - "CFG_CENTER_IMUX9_1", - "CFG_CENTER_IMUX9_2", - "CFG_CENTER_IMUX9_3", - "CFG_CENTER_IMUX9_4", - "CFG_CENTER_IMUX9_5", - "CFG_CENTER_IMUX9_6", - "CFG_CENTER_IMUX9_7", - "CFG_CENTER_IMUX9_8", - "CFG_CENTER_IMUX9_9", - "CFG_CENTER_LH10_0", - "CFG_CENTER_LH10_1", - "CFG_CENTER_LH10_2", - "CFG_CENTER_LH10_3", - "CFG_CENTER_LH10_4", - "CFG_CENTER_LH10_5", - "CFG_CENTER_LH10_6", - "CFG_CENTER_LH10_7", - "CFG_CENTER_LH10_8", - "CFG_CENTER_LH10_9", - "CFG_CENTER_LH11_0", - "CFG_CENTER_LH11_1", - "CFG_CENTER_LH11_2", - "CFG_CENTER_LH11_3", - "CFG_CENTER_LH11_4", - "CFG_CENTER_LH11_5", - "CFG_CENTER_LH11_6", - "CFG_CENTER_LH11_7", - "CFG_CENTER_LH11_8", - "CFG_CENTER_LH11_9", - "CFG_CENTER_LH12_0", - "CFG_CENTER_LH12_1", - "CFG_CENTER_LH12_2", - "CFG_CENTER_LH12_3", - "CFG_CENTER_LH12_4", - "CFG_CENTER_LH12_5", - "CFG_CENTER_LH12_6", - "CFG_CENTER_LH12_7", - "CFG_CENTER_LH12_8", - "CFG_CENTER_LH12_9", - "CFG_CENTER_LH1_0", - "CFG_CENTER_LH1_1", - "CFG_CENTER_LH1_2", - "CFG_CENTER_LH1_3", - "CFG_CENTER_LH1_4", - "CFG_CENTER_LH1_5", - "CFG_CENTER_LH1_6", - "CFG_CENTER_LH1_7", - "CFG_CENTER_LH1_8", - "CFG_CENTER_LH1_9", - "CFG_CENTER_LH2_0", - "CFG_CENTER_LH2_1", - "CFG_CENTER_LH2_2", - "CFG_CENTER_LH2_3", - "CFG_CENTER_LH2_4", - "CFG_CENTER_LH2_5", - "CFG_CENTER_LH2_6", - "CFG_CENTER_LH2_7", - "CFG_CENTER_LH2_8", - "CFG_CENTER_LH2_9", - "CFG_CENTER_LH3_0", - "CFG_CENTER_LH3_1", - "CFG_CENTER_LH3_2", - "CFG_CENTER_LH3_3", - "CFG_CENTER_LH3_4", - "CFG_CENTER_LH3_5", - "CFG_CENTER_LH3_6", - "CFG_CENTER_LH3_7", - "CFG_CENTER_LH3_8", - "CFG_CENTER_LH3_9", - "CFG_CENTER_LH4_0", - "CFG_CENTER_LH4_1", - "CFG_CENTER_LH4_2", - "CFG_CENTER_LH4_3", - "CFG_CENTER_LH4_4", - "CFG_CENTER_LH4_5", - "CFG_CENTER_LH4_6", - "CFG_CENTER_LH4_7", - "CFG_CENTER_LH4_8", - "CFG_CENTER_LH4_9", - "CFG_CENTER_LH5_0", - "CFG_CENTER_LH5_1", - "CFG_CENTER_LH5_2", - "CFG_CENTER_LH5_3", - "CFG_CENTER_LH5_4", - "CFG_CENTER_LH5_5", - "CFG_CENTER_LH5_6", - "CFG_CENTER_LH5_7", - "CFG_CENTER_LH5_8", - "CFG_CENTER_LH5_9", - "CFG_CENTER_LH6_0", - "CFG_CENTER_LH6_1", - "CFG_CENTER_LH6_2", - "CFG_CENTER_LH6_3", - "CFG_CENTER_LH6_4", - "CFG_CENTER_LH6_5", - "CFG_CENTER_LH6_6", - "CFG_CENTER_LH6_7", - "CFG_CENTER_LH6_8", - "CFG_CENTER_LH6_9", - "CFG_CENTER_LH7_0", - "CFG_CENTER_LH7_1", - "CFG_CENTER_LH7_2", - "CFG_CENTER_LH7_3", - "CFG_CENTER_LH7_4", - "CFG_CENTER_LH7_5", - "CFG_CENTER_LH7_6", - "CFG_CENTER_LH7_7", - "CFG_CENTER_LH7_8", - "CFG_CENTER_LH7_9", - "CFG_CENTER_LH8_0", - "CFG_CENTER_LH8_1", - "CFG_CENTER_LH8_2", - "CFG_CENTER_LH8_3", - "CFG_CENTER_LH8_4", - "CFG_CENTER_LH8_5", - "CFG_CENTER_LH8_6", - "CFG_CENTER_LH8_7", - "CFG_CENTER_LH8_8", - "CFG_CENTER_LH8_9", - "CFG_CENTER_LH9_0", - "CFG_CENTER_LH9_1", - "CFG_CENTER_LH9_2", - "CFG_CENTER_LH9_3", - "CFG_CENTER_LH9_4", - "CFG_CENTER_LH9_5", - "CFG_CENTER_LH9_6", - "CFG_CENTER_LH9_7", - "CFG_CENTER_LH9_8", - "CFG_CENTER_LH9_9", - "CFG_CENTER_LOGIC_OUTS_B0_0", - "CFG_CENTER_LOGIC_OUTS_B0_1", - "CFG_CENTER_LOGIC_OUTS_B0_2", - "CFG_CENTER_LOGIC_OUTS_B0_3", - "CFG_CENTER_LOGIC_OUTS_B0_4", - "CFG_CENTER_LOGIC_OUTS_B0_5", - "CFG_CENTER_LOGIC_OUTS_B0_6", - "CFG_CENTER_LOGIC_OUTS_B0_7", - "CFG_CENTER_LOGIC_OUTS_B0_8", - "CFG_CENTER_LOGIC_OUTS_B0_9", - "CFG_CENTER_LOGIC_OUTS_B10_0", - "CFG_CENTER_LOGIC_OUTS_B10_1", - "CFG_CENTER_LOGIC_OUTS_B10_2", - "CFG_CENTER_LOGIC_OUTS_B10_3", - "CFG_CENTER_LOGIC_OUTS_B10_4", - "CFG_CENTER_LOGIC_OUTS_B10_5", - "CFG_CENTER_LOGIC_OUTS_B10_6", - "CFG_CENTER_LOGIC_OUTS_B10_7", - "CFG_CENTER_LOGIC_OUTS_B10_8", - "CFG_CENTER_LOGIC_OUTS_B10_9", - "CFG_CENTER_LOGIC_OUTS_B11_0", - "CFG_CENTER_LOGIC_OUTS_B11_1", - "CFG_CENTER_LOGIC_OUTS_B11_2", - "CFG_CENTER_LOGIC_OUTS_B11_3", - "CFG_CENTER_LOGIC_OUTS_B11_4", - "CFG_CENTER_LOGIC_OUTS_B11_5", - "CFG_CENTER_LOGIC_OUTS_B11_6", - "CFG_CENTER_LOGIC_OUTS_B11_7", - "CFG_CENTER_LOGIC_OUTS_B11_8", - "CFG_CENTER_LOGIC_OUTS_B11_9", - "CFG_CENTER_LOGIC_OUTS_B12_0", - "CFG_CENTER_LOGIC_OUTS_B12_1", - "CFG_CENTER_LOGIC_OUTS_B12_2", - "CFG_CENTER_LOGIC_OUTS_B12_3", - "CFG_CENTER_LOGIC_OUTS_B12_4", - "CFG_CENTER_LOGIC_OUTS_B12_5", - "CFG_CENTER_LOGIC_OUTS_B12_6", - "CFG_CENTER_LOGIC_OUTS_B12_7", - "CFG_CENTER_LOGIC_OUTS_B12_8", - "CFG_CENTER_LOGIC_OUTS_B12_9", - "CFG_CENTER_LOGIC_OUTS_B13_0", - "CFG_CENTER_LOGIC_OUTS_B13_1", - "CFG_CENTER_LOGIC_OUTS_B13_2", - "CFG_CENTER_LOGIC_OUTS_B13_3", - "CFG_CENTER_LOGIC_OUTS_B13_4", - "CFG_CENTER_LOGIC_OUTS_B13_5", - "CFG_CENTER_LOGIC_OUTS_B13_6", - "CFG_CENTER_LOGIC_OUTS_B13_7", - "CFG_CENTER_LOGIC_OUTS_B13_8", - "CFG_CENTER_LOGIC_OUTS_B13_9", - "CFG_CENTER_LOGIC_OUTS_B14_0", - "CFG_CENTER_LOGIC_OUTS_B14_1", - "CFG_CENTER_LOGIC_OUTS_B14_2", - "CFG_CENTER_LOGIC_OUTS_B14_3", - "CFG_CENTER_LOGIC_OUTS_B14_4", - "CFG_CENTER_LOGIC_OUTS_B14_5", - "CFG_CENTER_LOGIC_OUTS_B14_6", - "CFG_CENTER_LOGIC_OUTS_B14_7", - "CFG_CENTER_LOGIC_OUTS_B14_8", - "CFG_CENTER_LOGIC_OUTS_B14_9", - "CFG_CENTER_LOGIC_OUTS_B15_0", - "CFG_CENTER_LOGIC_OUTS_B15_1", - "CFG_CENTER_LOGIC_OUTS_B15_2", - "CFG_CENTER_LOGIC_OUTS_B15_3", - "CFG_CENTER_LOGIC_OUTS_B15_4", - "CFG_CENTER_LOGIC_OUTS_B15_5", - "CFG_CENTER_LOGIC_OUTS_B15_6", - "CFG_CENTER_LOGIC_OUTS_B15_7", - "CFG_CENTER_LOGIC_OUTS_B15_8", - "CFG_CENTER_LOGIC_OUTS_B15_9", - "CFG_CENTER_LOGIC_OUTS_B16_0", - "CFG_CENTER_LOGIC_OUTS_B16_1", - "CFG_CENTER_LOGIC_OUTS_B16_2", - "CFG_CENTER_LOGIC_OUTS_B16_3", - "CFG_CENTER_LOGIC_OUTS_B16_4", - "CFG_CENTER_LOGIC_OUTS_B16_5", - "CFG_CENTER_LOGIC_OUTS_B16_6", - "CFG_CENTER_LOGIC_OUTS_B16_7", - "CFG_CENTER_LOGIC_OUTS_B16_8", - "CFG_CENTER_LOGIC_OUTS_B16_9", - "CFG_CENTER_LOGIC_OUTS_B17_0", - "CFG_CENTER_LOGIC_OUTS_B17_1", - "CFG_CENTER_LOGIC_OUTS_B17_2", - "CFG_CENTER_LOGIC_OUTS_B17_3", - "CFG_CENTER_LOGIC_OUTS_B17_4", - "CFG_CENTER_LOGIC_OUTS_B17_5", - "CFG_CENTER_LOGIC_OUTS_B17_6", - "CFG_CENTER_LOGIC_OUTS_B17_7", - "CFG_CENTER_LOGIC_OUTS_B17_8", - "CFG_CENTER_LOGIC_OUTS_B17_9", - "CFG_CENTER_LOGIC_OUTS_B18_0", - "CFG_CENTER_LOGIC_OUTS_B18_1", - "CFG_CENTER_LOGIC_OUTS_B18_2", - "CFG_CENTER_LOGIC_OUTS_B18_3", - "CFG_CENTER_LOGIC_OUTS_B18_4", - "CFG_CENTER_LOGIC_OUTS_B18_5", - "CFG_CENTER_LOGIC_OUTS_B18_6", - "CFG_CENTER_LOGIC_OUTS_B18_7", - "CFG_CENTER_LOGIC_OUTS_B18_8", - "CFG_CENTER_LOGIC_OUTS_B18_9", - "CFG_CENTER_LOGIC_OUTS_B19_0", - "CFG_CENTER_LOGIC_OUTS_B19_1", - "CFG_CENTER_LOGIC_OUTS_B19_2", - "CFG_CENTER_LOGIC_OUTS_B19_3", - "CFG_CENTER_LOGIC_OUTS_B19_4", - "CFG_CENTER_LOGIC_OUTS_B19_5", - "CFG_CENTER_LOGIC_OUTS_B19_6", - "CFG_CENTER_LOGIC_OUTS_B19_7", - "CFG_CENTER_LOGIC_OUTS_B19_8", - "CFG_CENTER_LOGIC_OUTS_B19_9", - "CFG_CENTER_LOGIC_OUTS_B1_0", - "CFG_CENTER_LOGIC_OUTS_B1_1", - "CFG_CENTER_LOGIC_OUTS_B1_2", - "CFG_CENTER_LOGIC_OUTS_B1_3", - "CFG_CENTER_LOGIC_OUTS_B1_4", - "CFG_CENTER_LOGIC_OUTS_B1_5", - "CFG_CENTER_LOGIC_OUTS_B1_6", - "CFG_CENTER_LOGIC_OUTS_B1_7", - "CFG_CENTER_LOGIC_OUTS_B1_8", - "CFG_CENTER_LOGIC_OUTS_B1_9", - "CFG_CENTER_LOGIC_OUTS_B20_0", - "CFG_CENTER_LOGIC_OUTS_B20_1", - "CFG_CENTER_LOGIC_OUTS_B20_2", - "CFG_CENTER_LOGIC_OUTS_B20_3", - "CFG_CENTER_LOGIC_OUTS_B20_4", - "CFG_CENTER_LOGIC_OUTS_B20_5", - "CFG_CENTER_LOGIC_OUTS_B20_6", - "CFG_CENTER_LOGIC_OUTS_B20_7", - "CFG_CENTER_LOGIC_OUTS_B20_8", - "CFG_CENTER_LOGIC_OUTS_B20_9", - "CFG_CENTER_LOGIC_OUTS_B21_0", - "CFG_CENTER_LOGIC_OUTS_B21_1", - "CFG_CENTER_LOGIC_OUTS_B21_2", - "CFG_CENTER_LOGIC_OUTS_B21_3", - "CFG_CENTER_LOGIC_OUTS_B21_4", - "CFG_CENTER_LOGIC_OUTS_B21_5", - "CFG_CENTER_LOGIC_OUTS_B21_6", - "CFG_CENTER_LOGIC_OUTS_B21_7", - "CFG_CENTER_LOGIC_OUTS_B21_8", - "CFG_CENTER_LOGIC_OUTS_B21_9", - "CFG_CENTER_LOGIC_OUTS_B22_0", - "CFG_CENTER_LOGIC_OUTS_B22_1", - "CFG_CENTER_LOGIC_OUTS_B22_2", - "CFG_CENTER_LOGIC_OUTS_B22_3", - "CFG_CENTER_LOGIC_OUTS_B22_4", - "CFG_CENTER_LOGIC_OUTS_B22_5", - "CFG_CENTER_LOGIC_OUTS_B22_6", - "CFG_CENTER_LOGIC_OUTS_B22_7", - "CFG_CENTER_LOGIC_OUTS_B22_8", - "CFG_CENTER_LOGIC_OUTS_B22_9", - "CFG_CENTER_LOGIC_OUTS_B23_0", - "CFG_CENTER_LOGIC_OUTS_B23_1", - "CFG_CENTER_LOGIC_OUTS_B23_2", - "CFG_CENTER_LOGIC_OUTS_B23_3", - "CFG_CENTER_LOGIC_OUTS_B23_4", - "CFG_CENTER_LOGIC_OUTS_B23_5", - "CFG_CENTER_LOGIC_OUTS_B23_6", - "CFG_CENTER_LOGIC_OUTS_B23_7", - "CFG_CENTER_LOGIC_OUTS_B23_8", - "CFG_CENTER_LOGIC_OUTS_B23_9", - "CFG_CENTER_LOGIC_OUTS_B2_0", - "CFG_CENTER_LOGIC_OUTS_B2_1", - "CFG_CENTER_LOGIC_OUTS_B2_2", - "CFG_CENTER_LOGIC_OUTS_B2_3", - "CFG_CENTER_LOGIC_OUTS_B2_4", - "CFG_CENTER_LOGIC_OUTS_B2_5", - "CFG_CENTER_LOGIC_OUTS_B2_6", - "CFG_CENTER_LOGIC_OUTS_B2_7", - "CFG_CENTER_LOGIC_OUTS_B2_8", - "CFG_CENTER_LOGIC_OUTS_B2_9", - "CFG_CENTER_LOGIC_OUTS_B3_0", - "CFG_CENTER_LOGIC_OUTS_B3_1", - "CFG_CENTER_LOGIC_OUTS_B3_2", - "CFG_CENTER_LOGIC_OUTS_B3_3", - "CFG_CENTER_LOGIC_OUTS_B3_4", - "CFG_CENTER_LOGIC_OUTS_B3_5", - "CFG_CENTER_LOGIC_OUTS_B3_6", - "CFG_CENTER_LOGIC_OUTS_B3_7", - "CFG_CENTER_LOGIC_OUTS_B3_8", - "CFG_CENTER_LOGIC_OUTS_B3_9", - "CFG_CENTER_LOGIC_OUTS_B4_0", - "CFG_CENTER_LOGIC_OUTS_B4_1", - "CFG_CENTER_LOGIC_OUTS_B4_2", - "CFG_CENTER_LOGIC_OUTS_B4_3", - "CFG_CENTER_LOGIC_OUTS_B4_4", - "CFG_CENTER_LOGIC_OUTS_B4_5", - "CFG_CENTER_LOGIC_OUTS_B4_6", - "CFG_CENTER_LOGIC_OUTS_B4_7", - "CFG_CENTER_LOGIC_OUTS_B4_8", - "CFG_CENTER_LOGIC_OUTS_B4_9", - "CFG_CENTER_LOGIC_OUTS_B5_0", - "CFG_CENTER_LOGIC_OUTS_B5_1", - "CFG_CENTER_LOGIC_OUTS_B5_2", - "CFG_CENTER_LOGIC_OUTS_B5_3", - "CFG_CENTER_LOGIC_OUTS_B5_4", - "CFG_CENTER_LOGIC_OUTS_B5_5", - "CFG_CENTER_LOGIC_OUTS_B5_6", - "CFG_CENTER_LOGIC_OUTS_B5_7", - "CFG_CENTER_LOGIC_OUTS_B5_8", - "CFG_CENTER_LOGIC_OUTS_B5_9", - "CFG_CENTER_LOGIC_OUTS_B6_0", - "CFG_CENTER_LOGIC_OUTS_B6_1", - "CFG_CENTER_LOGIC_OUTS_B6_2", - "CFG_CENTER_LOGIC_OUTS_B6_3", - "CFG_CENTER_LOGIC_OUTS_B6_4", - "CFG_CENTER_LOGIC_OUTS_B6_5", - "CFG_CENTER_LOGIC_OUTS_B6_6", - "CFG_CENTER_LOGIC_OUTS_B6_7", - "CFG_CENTER_LOGIC_OUTS_B6_8", - "CFG_CENTER_LOGIC_OUTS_B6_9", - "CFG_CENTER_LOGIC_OUTS_B7_0", - "CFG_CENTER_LOGIC_OUTS_B7_1", - "CFG_CENTER_LOGIC_OUTS_B7_2", - "CFG_CENTER_LOGIC_OUTS_B7_3", - "CFG_CENTER_LOGIC_OUTS_B7_4", - "CFG_CENTER_LOGIC_OUTS_B7_5", - "CFG_CENTER_LOGIC_OUTS_B7_6", - "CFG_CENTER_LOGIC_OUTS_B7_7", - "CFG_CENTER_LOGIC_OUTS_B7_8", - "CFG_CENTER_LOGIC_OUTS_B7_9", - "CFG_CENTER_LOGIC_OUTS_B8_0", - "CFG_CENTER_LOGIC_OUTS_B8_1", - "CFG_CENTER_LOGIC_OUTS_B8_2", - "CFG_CENTER_LOGIC_OUTS_B8_3", - "CFG_CENTER_LOGIC_OUTS_B8_4", - "CFG_CENTER_LOGIC_OUTS_B8_5", - "CFG_CENTER_LOGIC_OUTS_B8_6", - "CFG_CENTER_LOGIC_OUTS_B8_7", - "CFG_CENTER_LOGIC_OUTS_B8_8", - "CFG_CENTER_LOGIC_OUTS_B8_9", - "CFG_CENTER_LOGIC_OUTS_B9_0", - "CFG_CENTER_LOGIC_OUTS_B9_1", - "CFG_CENTER_LOGIC_OUTS_B9_2", - "CFG_CENTER_LOGIC_OUTS_B9_3", - "CFG_CENTER_LOGIC_OUTS_B9_4", - "CFG_CENTER_LOGIC_OUTS_B9_5", - "CFG_CENTER_LOGIC_OUTS_B9_6", - "CFG_CENTER_LOGIC_OUTS_B9_7", - "CFG_CENTER_LOGIC_OUTS_B9_8", - "CFG_CENTER_LOGIC_OUTS_B9_9", - "CFG_CENTER_NE2A0_0", - "CFG_CENTER_NE2A0_1", - "CFG_CENTER_NE2A0_2", - "CFG_CENTER_NE2A0_3", - "CFG_CENTER_NE2A0_4", - "CFG_CENTER_NE2A0_5", - "CFG_CENTER_NE2A0_6", - "CFG_CENTER_NE2A0_7", - "CFG_CENTER_NE2A0_8", - "CFG_CENTER_NE2A0_9", - "CFG_CENTER_NE2A1_0", - "CFG_CENTER_NE2A1_1", - "CFG_CENTER_NE2A1_2", - "CFG_CENTER_NE2A1_3", - "CFG_CENTER_NE2A1_4", - "CFG_CENTER_NE2A1_5", - "CFG_CENTER_NE2A1_6", - "CFG_CENTER_NE2A1_7", - "CFG_CENTER_NE2A1_8", - "CFG_CENTER_NE2A1_9", - "CFG_CENTER_NE2A2_0", - "CFG_CENTER_NE2A2_1", - "CFG_CENTER_NE2A2_2", - "CFG_CENTER_NE2A2_3", - "CFG_CENTER_NE2A2_4", - "CFG_CENTER_NE2A2_5", - "CFG_CENTER_NE2A2_6", - "CFG_CENTER_NE2A2_7", - "CFG_CENTER_NE2A2_8", - "CFG_CENTER_NE2A2_9", - "CFG_CENTER_NE2A3_0", - "CFG_CENTER_NE2A3_1", - "CFG_CENTER_NE2A3_2", - "CFG_CENTER_NE2A3_3", - "CFG_CENTER_NE2A3_4", - "CFG_CENTER_NE2A3_5", - "CFG_CENTER_NE2A3_6", - "CFG_CENTER_NE2A3_7", - "CFG_CENTER_NE2A3_8", - "CFG_CENTER_NE2A3_9", - "CFG_CENTER_NE4BEG0_0", - "CFG_CENTER_NE4BEG0_1", - "CFG_CENTER_NE4BEG0_2", - "CFG_CENTER_NE4BEG0_3", - "CFG_CENTER_NE4BEG0_4", - "CFG_CENTER_NE4BEG0_5", - "CFG_CENTER_NE4BEG0_6", - "CFG_CENTER_NE4BEG0_7", - "CFG_CENTER_NE4BEG0_8", - "CFG_CENTER_NE4BEG0_9", - "CFG_CENTER_NE4BEG1_0", - "CFG_CENTER_NE4BEG1_1", - "CFG_CENTER_NE4BEG1_2", - "CFG_CENTER_NE4BEG1_3", - "CFG_CENTER_NE4BEG1_4", - "CFG_CENTER_NE4BEG1_5", - "CFG_CENTER_NE4BEG1_6", - "CFG_CENTER_NE4BEG1_7", - "CFG_CENTER_NE4BEG1_8", - "CFG_CENTER_NE4BEG1_9", - "CFG_CENTER_NE4BEG2_0", - "CFG_CENTER_NE4BEG2_1", - "CFG_CENTER_NE4BEG2_2", - "CFG_CENTER_NE4BEG2_3", - "CFG_CENTER_NE4BEG2_4", - "CFG_CENTER_NE4BEG2_5", - "CFG_CENTER_NE4BEG2_6", - "CFG_CENTER_NE4BEG2_7", - "CFG_CENTER_NE4BEG2_8", - "CFG_CENTER_NE4BEG2_9", - "CFG_CENTER_NE4BEG3_0", - "CFG_CENTER_NE4BEG3_1", - "CFG_CENTER_NE4BEG3_2", - "CFG_CENTER_NE4BEG3_3", - "CFG_CENTER_NE4BEG3_4", - "CFG_CENTER_NE4BEG3_5", - "CFG_CENTER_NE4BEG3_6", - "CFG_CENTER_NE4BEG3_7", - "CFG_CENTER_NE4BEG3_8", - "CFG_CENTER_NE4BEG3_9", - "CFG_CENTER_NE4C0_0", - "CFG_CENTER_NE4C0_1", - "CFG_CENTER_NE4C0_2", - "CFG_CENTER_NE4C0_3", - "CFG_CENTER_NE4C0_4", - "CFG_CENTER_NE4C0_5", - "CFG_CENTER_NE4C0_6", - "CFG_CENTER_NE4C0_7", - "CFG_CENTER_NE4C0_8", - "CFG_CENTER_NE4C0_9", - "CFG_CENTER_NE4C1_0", - "CFG_CENTER_NE4C1_1", - "CFG_CENTER_NE4C1_2", - "CFG_CENTER_NE4C1_3", - "CFG_CENTER_NE4C1_4", - "CFG_CENTER_NE4C1_5", - "CFG_CENTER_NE4C1_6", - "CFG_CENTER_NE4C1_7", - "CFG_CENTER_NE4C1_8", - "CFG_CENTER_NE4C1_9", - "CFG_CENTER_NE4C2_0", - "CFG_CENTER_NE4C2_1", - "CFG_CENTER_NE4C2_2", - "CFG_CENTER_NE4C2_3", - "CFG_CENTER_NE4C2_4", - "CFG_CENTER_NE4C2_5", - "CFG_CENTER_NE4C2_6", - "CFG_CENTER_NE4C2_7", - "CFG_CENTER_NE4C2_8", - "CFG_CENTER_NE4C2_9", - "CFG_CENTER_NE4C3_0", - "CFG_CENTER_NE4C3_1", - "CFG_CENTER_NE4C3_2", - "CFG_CENTER_NE4C3_3", - "CFG_CENTER_NE4C3_4", - "CFG_CENTER_NE4C3_5", - "CFG_CENTER_NE4C3_6", - "CFG_CENTER_NE4C3_7", - "CFG_CENTER_NE4C3_8", - "CFG_CENTER_NE4C3_9", - "CFG_CENTER_NW2A0_0", - "CFG_CENTER_NW2A0_1", - "CFG_CENTER_NW2A0_2", - "CFG_CENTER_NW2A0_3", - "CFG_CENTER_NW2A0_4", - "CFG_CENTER_NW2A0_5", - "CFG_CENTER_NW2A0_6", - "CFG_CENTER_NW2A0_7", - "CFG_CENTER_NW2A0_8", - "CFG_CENTER_NW2A0_9", - "CFG_CENTER_NW2A1_0", - "CFG_CENTER_NW2A1_1", - "CFG_CENTER_NW2A1_2", - "CFG_CENTER_NW2A1_3", - "CFG_CENTER_NW2A1_4", - "CFG_CENTER_NW2A1_5", - "CFG_CENTER_NW2A1_6", - "CFG_CENTER_NW2A1_7", - "CFG_CENTER_NW2A1_8", - "CFG_CENTER_NW2A1_9", - "CFG_CENTER_NW2A2_0", - "CFG_CENTER_NW2A2_1", - "CFG_CENTER_NW2A2_2", - "CFG_CENTER_NW2A2_3", - "CFG_CENTER_NW2A2_4", - "CFG_CENTER_NW2A2_5", - "CFG_CENTER_NW2A2_6", - "CFG_CENTER_NW2A2_7", - "CFG_CENTER_NW2A2_8", - "CFG_CENTER_NW2A2_9", - "CFG_CENTER_NW2A3_0", - "CFG_CENTER_NW2A3_1", - "CFG_CENTER_NW2A3_2", - "CFG_CENTER_NW2A3_3", - "CFG_CENTER_NW2A3_4", - "CFG_CENTER_NW2A3_5", - "CFG_CENTER_NW2A3_6", - "CFG_CENTER_NW2A3_7", - "CFG_CENTER_NW2A3_8", - "CFG_CENTER_NW2A3_9", - "CFG_CENTER_NW4A0_0", - "CFG_CENTER_NW4A0_1", - "CFG_CENTER_NW4A0_2", - "CFG_CENTER_NW4A0_3", - "CFG_CENTER_NW4A0_4", - "CFG_CENTER_NW4A0_5", - "CFG_CENTER_NW4A0_6", - "CFG_CENTER_NW4A0_7", - "CFG_CENTER_NW4A0_8", - "CFG_CENTER_NW4A0_9", - "CFG_CENTER_NW4A1_0", - "CFG_CENTER_NW4A1_1", - "CFG_CENTER_NW4A1_2", - "CFG_CENTER_NW4A1_3", - "CFG_CENTER_NW4A1_4", - "CFG_CENTER_NW4A1_5", - "CFG_CENTER_NW4A1_6", - "CFG_CENTER_NW4A1_7", - "CFG_CENTER_NW4A1_8", - "CFG_CENTER_NW4A1_9", - "CFG_CENTER_NW4A2_0", - "CFG_CENTER_NW4A2_1", - "CFG_CENTER_NW4A2_2", - "CFG_CENTER_NW4A2_3", - "CFG_CENTER_NW4A2_4", - "CFG_CENTER_NW4A2_5", - "CFG_CENTER_NW4A2_6", - "CFG_CENTER_NW4A2_7", - "CFG_CENTER_NW4A2_8", - "CFG_CENTER_NW4A2_9", - "CFG_CENTER_NW4A3_0", - "CFG_CENTER_NW4A3_1", - "CFG_CENTER_NW4A3_2", - "CFG_CENTER_NW4A3_3", - "CFG_CENTER_NW4A3_4", - "CFG_CENTER_NW4A3_5", - "CFG_CENTER_NW4A3_6", - "CFG_CENTER_NW4A3_7", - "CFG_CENTER_NW4A3_8", - "CFG_CENTER_NW4A3_9", - "CFG_CENTER_NW4END0_0", - "CFG_CENTER_NW4END0_1", - "CFG_CENTER_NW4END0_2", - "CFG_CENTER_NW4END0_3", - "CFG_CENTER_NW4END0_4", - "CFG_CENTER_NW4END0_5", - "CFG_CENTER_NW4END0_6", - "CFG_CENTER_NW4END0_7", - "CFG_CENTER_NW4END0_8", - "CFG_CENTER_NW4END0_9", - "CFG_CENTER_NW4END1_0", - "CFG_CENTER_NW4END1_1", - "CFG_CENTER_NW4END1_2", - "CFG_CENTER_NW4END1_3", - "CFG_CENTER_NW4END1_4", - "CFG_CENTER_NW4END1_5", - "CFG_CENTER_NW4END1_6", - "CFG_CENTER_NW4END1_7", - "CFG_CENTER_NW4END1_8", - "CFG_CENTER_NW4END1_9", - "CFG_CENTER_NW4END2_0", - "CFG_CENTER_NW4END2_1", - "CFG_CENTER_NW4END2_2", - "CFG_CENTER_NW4END2_3", - "CFG_CENTER_NW4END2_4", - "CFG_CENTER_NW4END2_5", - "CFG_CENTER_NW4END2_6", - "CFG_CENTER_NW4END2_7", - "CFG_CENTER_NW4END2_8", - "CFG_CENTER_NW4END2_9", - "CFG_CENTER_NW4END3_0", - "CFG_CENTER_NW4END3_1", - "CFG_CENTER_NW4END3_2", - "CFG_CENTER_NW4END3_3", - "CFG_CENTER_NW4END3_4", - "CFG_CENTER_NW4END3_5", - "CFG_CENTER_NW4END3_6", - "CFG_CENTER_NW4END3_7", - "CFG_CENTER_NW4END3_8", - "CFG_CENTER_NW4END3_9", - "CFG_CENTER_SE2A0_0", - "CFG_CENTER_SE2A0_1", - "CFG_CENTER_SE2A0_2", - "CFG_CENTER_SE2A0_3", - "CFG_CENTER_SE2A0_4", - "CFG_CENTER_SE2A0_5", - "CFG_CENTER_SE2A0_6", - "CFG_CENTER_SE2A0_7", - "CFG_CENTER_SE2A0_8", - "CFG_CENTER_SE2A0_9", - "CFG_CENTER_SE2A1_0", - "CFG_CENTER_SE2A1_1", - "CFG_CENTER_SE2A1_2", - "CFG_CENTER_SE2A1_3", - "CFG_CENTER_SE2A1_4", - "CFG_CENTER_SE2A1_5", - "CFG_CENTER_SE2A1_6", - "CFG_CENTER_SE2A1_7", - "CFG_CENTER_SE2A1_8", - "CFG_CENTER_SE2A1_9", - "CFG_CENTER_SE2A2_0", - "CFG_CENTER_SE2A2_1", - "CFG_CENTER_SE2A2_2", - "CFG_CENTER_SE2A2_3", - "CFG_CENTER_SE2A2_4", - "CFG_CENTER_SE2A2_5", - "CFG_CENTER_SE2A2_6", - "CFG_CENTER_SE2A2_7", - "CFG_CENTER_SE2A2_8", - "CFG_CENTER_SE2A2_9", - "CFG_CENTER_SE2A3_0", - "CFG_CENTER_SE2A3_1", - "CFG_CENTER_SE2A3_2", - "CFG_CENTER_SE2A3_3", - "CFG_CENTER_SE2A3_4", - "CFG_CENTER_SE2A3_5", - "CFG_CENTER_SE2A3_6", - "CFG_CENTER_SE2A3_7", - "CFG_CENTER_SE2A3_8", - "CFG_CENTER_SE2A3_9", - "CFG_CENTER_SE4BEG0_0", - "CFG_CENTER_SE4BEG0_1", - "CFG_CENTER_SE4BEG0_2", - "CFG_CENTER_SE4BEG0_3", - "CFG_CENTER_SE4BEG0_4", - "CFG_CENTER_SE4BEG0_5", - "CFG_CENTER_SE4BEG0_6", - "CFG_CENTER_SE4BEG0_7", - "CFG_CENTER_SE4BEG0_8", - "CFG_CENTER_SE4BEG0_9", - "CFG_CENTER_SE4BEG1_0", - "CFG_CENTER_SE4BEG1_1", - "CFG_CENTER_SE4BEG1_2", - "CFG_CENTER_SE4BEG1_3", - "CFG_CENTER_SE4BEG1_4", - "CFG_CENTER_SE4BEG1_5", - "CFG_CENTER_SE4BEG1_6", - "CFG_CENTER_SE4BEG1_7", - "CFG_CENTER_SE4BEG1_8", - "CFG_CENTER_SE4BEG1_9", - "CFG_CENTER_SE4BEG2_0", - "CFG_CENTER_SE4BEG2_1", - "CFG_CENTER_SE4BEG2_2", - "CFG_CENTER_SE4BEG2_3", - "CFG_CENTER_SE4BEG2_4", - "CFG_CENTER_SE4BEG2_5", - "CFG_CENTER_SE4BEG2_6", - "CFG_CENTER_SE4BEG2_7", - "CFG_CENTER_SE4BEG2_8", - "CFG_CENTER_SE4BEG2_9", - "CFG_CENTER_SE4BEG3_0", - "CFG_CENTER_SE4BEG3_1", - "CFG_CENTER_SE4BEG3_2", - "CFG_CENTER_SE4BEG3_3", - "CFG_CENTER_SE4BEG3_4", - "CFG_CENTER_SE4BEG3_5", - "CFG_CENTER_SE4BEG3_6", - "CFG_CENTER_SE4BEG3_7", - "CFG_CENTER_SE4BEG3_8", - "CFG_CENTER_SE4BEG3_9", - "CFG_CENTER_SE4C0_0", - "CFG_CENTER_SE4C0_1", - "CFG_CENTER_SE4C0_2", - "CFG_CENTER_SE4C0_3", - "CFG_CENTER_SE4C0_4", - "CFG_CENTER_SE4C0_5", - "CFG_CENTER_SE4C0_6", - "CFG_CENTER_SE4C0_7", - "CFG_CENTER_SE4C0_8", - "CFG_CENTER_SE4C0_9", - "CFG_CENTER_SE4C1_0", - "CFG_CENTER_SE4C1_1", - "CFG_CENTER_SE4C1_2", - "CFG_CENTER_SE4C1_3", - "CFG_CENTER_SE4C1_4", - "CFG_CENTER_SE4C1_5", - "CFG_CENTER_SE4C1_6", - "CFG_CENTER_SE4C1_7", - "CFG_CENTER_SE4C1_8", - "CFG_CENTER_SE4C1_9", - "CFG_CENTER_SE4C2_0", - "CFG_CENTER_SE4C2_1", - "CFG_CENTER_SE4C2_2", - "CFG_CENTER_SE4C2_3", - "CFG_CENTER_SE4C2_4", - "CFG_CENTER_SE4C2_5", - "CFG_CENTER_SE4C2_6", - "CFG_CENTER_SE4C2_7", - "CFG_CENTER_SE4C2_8", - "CFG_CENTER_SE4C2_9", - "CFG_CENTER_SE4C3_0", - "CFG_CENTER_SE4C3_1", - "CFG_CENTER_SE4C3_2", - "CFG_CENTER_SE4C3_3", - "CFG_CENTER_SE4C3_4", - "CFG_CENTER_SE4C3_5", - "CFG_CENTER_SE4C3_6", - "CFG_CENTER_SE4C3_7", - "CFG_CENTER_SE4C3_8", - "CFG_CENTER_SE4C3_9", - "CFG_CENTER_SW2A0_0", - "CFG_CENTER_SW2A0_1", - "CFG_CENTER_SW2A0_2", - "CFG_CENTER_SW2A0_3", - "CFG_CENTER_SW2A0_4", - "CFG_CENTER_SW2A0_5", - "CFG_CENTER_SW2A0_6", - "CFG_CENTER_SW2A0_7", - "CFG_CENTER_SW2A0_8", - "CFG_CENTER_SW2A0_9", - "CFG_CENTER_SW2A1_0", - "CFG_CENTER_SW2A1_1", - "CFG_CENTER_SW2A1_2", - "CFG_CENTER_SW2A1_3", - "CFG_CENTER_SW2A1_4", - "CFG_CENTER_SW2A1_5", - "CFG_CENTER_SW2A1_6", - "CFG_CENTER_SW2A1_7", - "CFG_CENTER_SW2A1_8", - "CFG_CENTER_SW2A1_9", - "CFG_CENTER_SW2A2_0", - "CFG_CENTER_SW2A2_1", - "CFG_CENTER_SW2A2_2", - "CFG_CENTER_SW2A2_3", - "CFG_CENTER_SW2A2_4", - "CFG_CENTER_SW2A2_5", - "CFG_CENTER_SW2A2_6", - "CFG_CENTER_SW2A2_7", - "CFG_CENTER_SW2A2_8", - "CFG_CENTER_SW2A2_9", - "CFG_CENTER_SW2A3_0", - "CFG_CENTER_SW2A3_1", - "CFG_CENTER_SW2A3_2", - "CFG_CENTER_SW2A3_3", - "CFG_CENTER_SW2A3_4", - "CFG_CENTER_SW2A3_5", - "CFG_CENTER_SW2A3_6", - "CFG_CENTER_SW2A3_7", - "CFG_CENTER_SW2A3_8", - "CFG_CENTER_SW2A3_9", - "CFG_CENTER_SW4A0_0", - "CFG_CENTER_SW4A0_1", - "CFG_CENTER_SW4A0_2", - "CFG_CENTER_SW4A0_3", - "CFG_CENTER_SW4A0_4", - "CFG_CENTER_SW4A0_5", - "CFG_CENTER_SW4A0_6", - "CFG_CENTER_SW4A0_7", - "CFG_CENTER_SW4A0_8", - "CFG_CENTER_SW4A0_9", - "CFG_CENTER_SW4A1_0", - "CFG_CENTER_SW4A1_1", - "CFG_CENTER_SW4A1_2", - "CFG_CENTER_SW4A1_3", - "CFG_CENTER_SW4A1_4", - "CFG_CENTER_SW4A1_5", - "CFG_CENTER_SW4A1_6", - "CFG_CENTER_SW4A1_7", - "CFG_CENTER_SW4A1_8", - "CFG_CENTER_SW4A1_9", - "CFG_CENTER_SW4A2_0", - "CFG_CENTER_SW4A2_1", - "CFG_CENTER_SW4A2_2", - "CFG_CENTER_SW4A2_3", - "CFG_CENTER_SW4A2_4", - "CFG_CENTER_SW4A2_5", - "CFG_CENTER_SW4A2_6", - "CFG_CENTER_SW4A2_7", - "CFG_CENTER_SW4A2_8", - "CFG_CENTER_SW4A2_9", - "CFG_CENTER_SW4A3_0", - "CFG_CENTER_SW4A3_1", - "CFG_CENTER_SW4A3_2", - "CFG_CENTER_SW4A3_3", - "CFG_CENTER_SW4A3_4", - "CFG_CENTER_SW4A3_5", - "CFG_CENTER_SW4A3_6", - "CFG_CENTER_SW4A3_7", - "CFG_CENTER_SW4A3_8", - "CFG_CENTER_SW4A3_9", - "CFG_CENTER_SW4END0_0", - "CFG_CENTER_SW4END0_1", - "CFG_CENTER_SW4END0_2", - "CFG_CENTER_SW4END0_3", - "CFG_CENTER_SW4END0_4", - "CFG_CENTER_SW4END0_5", - "CFG_CENTER_SW4END0_6", - "CFG_CENTER_SW4END0_7", - "CFG_CENTER_SW4END0_8", - "CFG_CENTER_SW4END0_9", - "CFG_CENTER_SW4END1_0", - "CFG_CENTER_SW4END1_1", - "CFG_CENTER_SW4END1_2", - "CFG_CENTER_SW4END1_3", - "CFG_CENTER_SW4END1_4", - "CFG_CENTER_SW4END1_5", - "CFG_CENTER_SW4END1_6", - "CFG_CENTER_SW4END1_7", - "CFG_CENTER_SW4END1_8", - "CFG_CENTER_SW4END1_9", - "CFG_CENTER_SW4END2_0", - "CFG_CENTER_SW4END2_1", - "CFG_CENTER_SW4END2_2", - "CFG_CENTER_SW4END2_3", - "CFG_CENTER_SW4END2_4", - "CFG_CENTER_SW4END2_5", - "CFG_CENTER_SW4END2_6", - "CFG_CENTER_SW4END2_7", - "CFG_CENTER_SW4END2_8", - "CFG_CENTER_SW4END2_9", - "CFG_CENTER_SW4END3_0", - "CFG_CENTER_SW4END3_1", - "CFG_CENTER_SW4END3_2", - "CFG_CENTER_SW4END3_3", - "CFG_CENTER_SW4END3_4", - "CFG_CENTER_SW4END3_5", - "CFG_CENTER_SW4END3_6", - "CFG_CENTER_SW4END3_7", - "CFG_CENTER_SW4END3_8", - "CFG_CENTER_SW4END3_9", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA11", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA12", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA13", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA14", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA15", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA16", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA17", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA18", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA19", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA20", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA21", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA22", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA23", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA24", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA25", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA26", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA27", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA28", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA29", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA30", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA31", - "CFG_CENTER_TOP_DNA_PORT_CLK", - "CFG_CENTER_TOP_ICAP1_CLK", - "CFG_CENTER_WL1END0_0", - "CFG_CENTER_WL1END0_1", - "CFG_CENTER_WL1END0_2", - "CFG_CENTER_WL1END0_3", - "CFG_CENTER_WL1END0_4", - "CFG_CENTER_WL1END0_5", - "CFG_CENTER_WL1END0_6", - "CFG_CENTER_WL1END0_7", - "CFG_CENTER_WL1END0_8", - "CFG_CENTER_WL1END0_9", - "CFG_CENTER_WL1END1_0", - "CFG_CENTER_WL1END1_1", - "CFG_CENTER_WL1END1_2", - "CFG_CENTER_WL1END1_3", - "CFG_CENTER_WL1END1_4", - "CFG_CENTER_WL1END1_5", - "CFG_CENTER_WL1END1_6", - "CFG_CENTER_WL1END1_7", - "CFG_CENTER_WL1END1_8", - "CFG_CENTER_WL1END1_9", - "CFG_CENTER_WL1END2_0", - "CFG_CENTER_WL1END2_1", - "CFG_CENTER_WL1END2_2", - "CFG_CENTER_WL1END2_3", - "CFG_CENTER_WL1END2_4", - "CFG_CENTER_WL1END2_5", - "CFG_CENTER_WL1END2_6", - "CFG_CENTER_WL1END2_7", - "CFG_CENTER_WL1END2_8", - "CFG_CENTER_WL1END2_9", - "CFG_CENTER_WL1END3_0", - "CFG_CENTER_WL1END3_1", - "CFG_CENTER_WL1END3_2", - "CFG_CENTER_WL1END3_3", - "CFG_CENTER_WL1END3_4", - "CFG_CENTER_WL1END3_5", - "CFG_CENTER_WL1END3_6", - "CFG_CENTER_WL1END3_7", - "CFG_CENTER_WL1END3_8", - "CFG_CENTER_WL1END3_9", - "CFG_CENTER_WR1END0_0", - "CFG_CENTER_WR1END0_1", - "CFG_CENTER_WR1END0_2", - "CFG_CENTER_WR1END0_3", - "CFG_CENTER_WR1END0_4", - "CFG_CENTER_WR1END0_5", - "CFG_CENTER_WR1END0_6", - "CFG_CENTER_WR1END0_7", - "CFG_CENTER_WR1END0_8", - "CFG_CENTER_WR1END0_9", - "CFG_CENTER_WR1END1_0", - "CFG_CENTER_WR1END1_1", - "CFG_CENTER_WR1END1_2", - "CFG_CENTER_WR1END1_3", - "CFG_CENTER_WR1END1_4", - "CFG_CENTER_WR1END1_5", - "CFG_CENTER_WR1END1_6", - "CFG_CENTER_WR1END1_7", - "CFG_CENTER_WR1END1_8", - "CFG_CENTER_WR1END1_9", - "CFG_CENTER_WR1END2_0", - "CFG_CENTER_WR1END2_1", - "CFG_CENTER_WR1END2_2", - "CFG_CENTER_WR1END2_3", - "CFG_CENTER_WR1END2_4", - "CFG_CENTER_WR1END2_5", - "CFG_CENTER_WR1END2_6", - "CFG_CENTER_WR1END2_7", - "CFG_CENTER_WR1END2_8", - "CFG_CENTER_WR1END2_9", - "CFG_CENTER_WR1END3_0", - "CFG_CENTER_WR1END3_1", - "CFG_CENTER_WR1END3_2", - "CFG_CENTER_WR1END3_3", - "CFG_CENTER_WR1END3_4", - "CFG_CENTER_WR1END3_5", - "CFG_CENTER_WR1END3_6", - "CFG_CENTER_WR1END3_7", - "CFG_CENTER_WR1END3_8", - "CFG_CENTER_WR1END3_9", - "CFG_CENTER_WW2A0_0", - "CFG_CENTER_WW2A0_1", - "CFG_CENTER_WW2A0_2", - "CFG_CENTER_WW2A0_3", - "CFG_CENTER_WW2A0_4", - "CFG_CENTER_WW2A0_5", - "CFG_CENTER_WW2A0_6", - "CFG_CENTER_WW2A0_7", - "CFG_CENTER_WW2A0_8", - "CFG_CENTER_WW2A0_9", - "CFG_CENTER_WW2A1_0", - "CFG_CENTER_WW2A1_1", - "CFG_CENTER_WW2A1_2", - "CFG_CENTER_WW2A1_3", - "CFG_CENTER_WW2A1_4", - "CFG_CENTER_WW2A1_5", - "CFG_CENTER_WW2A1_6", - "CFG_CENTER_WW2A1_7", - "CFG_CENTER_WW2A1_8", - "CFG_CENTER_WW2A1_9", - "CFG_CENTER_WW2A2_0", - "CFG_CENTER_WW2A2_1", - "CFG_CENTER_WW2A2_2", - "CFG_CENTER_WW2A2_3", - "CFG_CENTER_WW2A2_4", - "CFG_CENTER_WW2A2_5", - "CFG_CENTER_WW2A2_6", - "CFG_CENTER_WW2A2_7", - "CFG_CENTER_WW2A2_8", - "CFG_CENTER_WW2A2_9", - "CFG_CENTER_WW2A3_0", - "CFG_CENTER_WW2A3_1", - "CFG_CENTER_WW2A3_2", - "CFG_CENTER_WW2A3_3", - "CFG_CENTER_WW2A3_4", - "CFG_CENTER_WW2A3_5", - "CFG_CENTER_WW2A3_6", - "CFG_CENTER_WW2A3_7", - "CFG_CENTER_WW2A3_8", - "CFG_CENTER_WW2A3_9", - "CFG_CENTER_WW2END0_0", - "CFG_CENTER_WW2END0_1", - "CFG_CENTER_WW2END0_2", - "CFG_CENTER_WW2END0_3", - "CFG_CENTER_WW2END0_4", - "CFG_CENTER_WW2END0_5", - "CFG_CENTER_WW2END0_6", - "CFG_CENTER_WW2END0_7", - "CFG_CENTER_WW2END0_8", - "CFG_CENTER_WW2END0_9", - "CFG_CENTER_WW2END1_0", - "CFG_CENTER_WW2END1_1", - "CFG_CENTER_WW2END1_2", - "CFG_CENTER_WW2END1_3", - "CFG_CENTER_WW2END1_4", - "CFG_CENTER_WW2END1_5", - "CFG_CENTER_WW2END1_6", - "CFG_CENTER_WW2END1_7", - "CFG_CENTER_WW2END1_8", - "CFG_CENTER_WW2END1_9", - "CFG_CENTER_WW2END2_0", - "CFG_CENTER_WW2END2_1", - "CFG_CENTER_WW2END2_2", - "CFG_CENTER_WW2END2_3", - "CFG_CENTER_WW2END2_4", - "CFG_CENTER_WW2END2_5", - "CFG_CENTER_WW2END2_6", - "CFG_CENTER_WW2END2_7", - "CFG_CENTER_WW2END2_8", - "CFG_CENTER_WW2END2_9", - "CFG_CENTER_WW2END3_0", - "CFG_CENTER_WW2END3_1", - "CFG_CENTER_WW2END3_2", - "CFG_CENTER_WW2END3_3", - "CFG_CENTER_WW2END3_4", - "CFG_CENTER_WW2END3_5", - "CFG_CENTER_WW2END3_6", - "CFG_CENTER_WW2END3_7", - "CFG_CENTER_WW2END3_8", - "CFG_CENTER_WW2END3_9", - "CFG_CENTER_WW4A0_0", - "CFG_CENTER_WW4A0_1", - "CFG_CENTER_WW4A0_2", - "CFG_CENTER_WW4A0_3", - "CFG_CENTER_WW4A0_4", - "CFG_CENTER_WW4A0_5", - "CFG_CENTER_WW4A0_6", - "CFG_CENTER_WW4A0_7", - "CFG_CENTER_WW4A0_8", - "CFG_CENTER_WW4A0_9", - "CFG_CENTER_WW4A1_0", - "CFG_CENTER_WW4A1_1", - "CFG_CENTER_WW4A1_2", - "CFG_CENTER_WW4A1_3", - "CFG_CENTER_WW4A1_4", - "CFG_CENTER_WW4A1_5", - "CFG_CENTER_WW4A1_6", - "CFG_CENTER_WW4A1_7", - "CFG_CENTER_WW4A1_8", - "CFG_CENTER_WW4A1_9", - "CFG_CENTER_WW4A2_0", - "CFG_CENTER_WW4A2_1", - "CFG_CENTER_WW4A2_2", - "CFG_CENTER_WW4A2_3", - "CFG_CENTER_WW4A2_4", - "CFG_CENTER_WW4A2_5", - "CFG_CENTER_WW4A2_6", - "CFG_CENTER_WW4A2_7", - "CFG_CENTER_WW4A2_8", - "CFG_CENTER_WW4A2_9", - "CFG_CENTER_WW4A3_0", - "CFG_CENTER_WW4A3_1", - "CFG_CENTER_WW4A3_2", - "CFG_CENTER_WW4A3_3", - "CFG_CENTER_WW4A3_4", - "CFG_CENTER_WW4A3_5", - "CFG_CENTER_WW4A3_6", - "CFG_CENTER_WW4A3_7", - "CFG_CENTER_WW4A3_8", - "CFG_CENTER_WW4A3_9", - "CFG_CENTER_WW4B0_0", - "CFG_CENTER_WW4B0_1", - "CFG_CENTER_WW4B0_2", - "CFG_CENTER_WW4B0_3", - "CFG_CENTER_WW4B0_4", - "CFG_CENTER_WW4B0_5", - "CFG_CENTER_WW4B0_6", - "CFG_CENTER_WW4B0_7", - "CFG_CENTER_WW4B0_8", - "CFG_CENTER_WW4B0_9", - "CFG_CENTER_WW4B1_0", - "CFG_CENTER_WW4B1_1", - "CFG_CENTER_WW4B1_2", - "CFG_CENTER_WW4B1_3", - "CFG_CENTER_WW4B1_4", - "CFG_CENTER_WW4B1_5", - "CFG_CENTER_WW4B1_6", - "CFG_CENTER_WW4B1_7", - "CFG_CENTER_WW4B1_8", - "CFG_CENTER_WW4B1_9", - "CFG_CENTER_WW4B2_0", - "CFG_CENTER_WW4B2_1", - "CFG_CENTER_WW4B2_2", - "CFG_CENTER_WW4B2_3", - "CFG_CENTER_WW4B2_4", - "CFG_CENTER_WW4B2_5", - "CFG_CENTER_WW4B2_6", - "CFG_CENTER_WW4B2_7", - "CFG_CENTER_WW4B2_8", - "CFG_CENTER_WW4B2_9", - "CFG_CENTER_WW4B3_0", - "CFG_CENTER_WW4B3_1", - "CFG_CENTER_WW4B3_2", - "CFG_CENTER_WW4B3_3", - "CFG_CENTER_WW4B3_4", - "CFG_CENTER_WW4B3_5", - "CFG_CENTER_WW4B3_6", - "CFG_CENTER_WW4B3_7", - "CFG_CENTER_WW4B3_8", - "CFG_CENTER_WW4B3_9", - "CFG_CENTER_WW4C0_0", - "CFG_CENTER_WW4C0_1", - "CFG_CENTER_WW4C0_2", - "CFG_CENTER_WW4C0_3", - "CFG_CENTER_WW4C0_4", - "CFG_CENTER_WW4C0_5", - "CFG_CENTER_WW4C0_6", - "CFG_CENTER_WW4C0_7", - "CFG_CENTER_WW4C0_8", - "CFG_CENTER_WW4C0_9", - "CFG_CENTER_WW4C1_0", - "CFG_CENTER_WW4C1_1", - "CFG_CENTER_WW4C1_2", - "CFG_CENTER_WW4C1_3", - "CFG_CENTER_WW4C1_4", - "CFG_CENTER_WW4C1_5", - "CFG_CENTER_WW4C1_6", - "CFG_CENTER_WW4C1_7", - "CFG_CENTER_WW4C1_8", - "CFG_CENTER_WW4C1_9", - "CFG_CENTER_WW4C2_0", - "CFG_CENTER_WW4C2_1", - "CFG_CENTER_WW4C2_2", - "CFG_CENTER_WW4C2_3", - "CFG_CENTER_WW4C2_4", - "CFG_CENTER_WW4C2_5", - "CFG_CENTER_WW4C2_6", - "CFG_CENTER_WW4C2_7", - "CFG_CENTER_WW4C2_8", - "CFG_CENTER_WW4C2_9", - "CFG_CENTER_WW4C3_0", - "CFG_CENTER_WW4C3_1", - "CFG_CENTER_WW4C3_2", - "CFG_CENTER_WW4C3_3", - "CFG_CENTER_WW4C3_4", - "CFG_CENTER_WW4C3_5", - "CFG_CENTER_WW4C3_6", - "CFG_CENTER_WW4C3_7", - "CFG_CENTER_WW4C3_8", - "CFG_CENTER_WW4C3_9", - "CFG_CENTER_WW4END0_0", - "CFG_CENTER_WW4END0_1", - "CFG_CENTER_WW4END0_2", - "CFG_CENTER_WW4END0_3", - "CFG_CENTER_WW4END0_4", - "CFG_CENTER_WW4END0_5", - "CFG_CENTER_WW4END0_6", - "CFG_CENTER_WW4END0_7", - "CFG_CENTER_WW4END0_8", - "CFG_CENTER_WW4END0_9", - "CFG_CENTER_WW4END1_0", - "CFG_CENTER_WW4END1_1", - "CFG_CENTER_WW4END1_2", - "CFG_CENTER_WW4END1_3", - "CFG_CENTER_WW4END1_4", - "CFG_CENTER_WW4END1_5", - "CFG_CENTER_WW4END1_6", - "CFG_CENTER_WW4END1_7", - "CFG_CENTER_WW4END1_8", - "CFG_CENTER_WW4END1_9", - "CFG_CENTER_WW4END2_0", - "CFG_CENTER_WW4END2_1", - "CFG_CENTER_WW4END2_2", - "CFG_CENTER_WW4END2_3", - "CFG_CENTER_WW4END2_4", - "CFG_CENTER_WW4END2_5", - "CFG_CENTER_WW4END2_6", - "CFG_CENTER_WW4END2_7", - "CFG_CENTER_WW4END2_8", - "CFG_CENTER_WW4END2_9", - "CFG_CENTER_WW4END3_0", - "CFG_CENTER_WW4END3_1", - "CFG_CENTER_WW4END3_2", - "CFG_CENTER_WW4END3_3", - "CFG_CENTER_WW4END3_4", - "CFG_CENTER_WW4END3_5", - "CFG_CENTER_WW4END3_6", - "CFG_CENTER_WW4END3_7", - "CFG_CENTER_WW4END3_8", - "CFG_CENTER_WW4END3_9" - ] + "wires": { + "CFG_CENTER_BLOCK_OUTS_B0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_6": { + 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"CFG_CENTER_CLK0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_1": { 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{ + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_9": { + "cap": "1.111", + "res": "0.000" + }, + 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}, + "CFG_CENTER_IMUX38_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LH10_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LOGIC_OUTS_B0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_NE2A0_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG3_2": { + "cap": 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"325.400" + }, + "CFG_CENTER_SE4C0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SE4C3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW2A0_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A0_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A0_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A0_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A0_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A0_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A0_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A0_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A0_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A0_9": { + "cap": "83.787", + "res": "325.400" + }, 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"83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A2_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A2_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A2_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A2_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A2_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A3_0": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A3_1": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A3_2": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A3_3": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A3_4": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A3_5": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A3_6": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A3_7": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A3_8": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW2A3_9": { + "cap": "83.787", + "res": "325.400" + }, + "CFG_CENTER_SW4A0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4A3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_SW4END0_2": { + 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"CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA17": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA18": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA19": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA20": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA21": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA22": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA23": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA24": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA25": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA26": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA27": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA28": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA29": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA30": null, + "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA31": null, + "CFG_CENTER_TOP_DNA_PORT_CLK": null, + "CFG_CENTER_TOP_ICAP1_CLK": null, + "CFG_CENTER_WL1END0_0": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_1": { + "cap": "89.773", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_2": { + 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"CFG_CENTER_WW4A1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4A3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_9": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_0": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_1": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_2": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_3": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_4": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_5": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_6": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_7": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_8": { + "cap": "64.544", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_9": { + "cap": "64.544", + "res": "325.400" + } + } } diff --git a/zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json b/zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json index 3f2874e..097b27c 100644 --- a/zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json +++ b/zynq7/tile_type_CFG_SECURITY_BOT_PELE1.json @@ -2,1355 +2,1443 @@ "pips": { "CFG_SECURITY_BOT_PELE1.MONITOR_HORIZ_VAUXN14->MONITOR_VERT_VAUXN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN14" }, "CFG_SECURITY_BOT_PELE1.MONITOR_HORIZ_VAUXN15->MONITOR_VERT_VAUXN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN15" }, "CFG_SECURITY_BOT_PELE1.MONITOR_HORIZ_VAUXN6->MONITOR_VERT_VAUXN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN6" }, "CFG_SECURITY_BOT_PELE1.MONITOR_HORIZ_VAUXN7->MONITOR_VERT_VAUXN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN7" }, "CFG_SECURITY_BOT_PELE1.MONITOR_HORIZ_VAUXP14->MONITOR_VERT_VAUXP14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP14" }, "CFG_SECURITY_BOT_PELE1.MONITOR_HORIZ_VAUXP15->MONITOR_VERT_VAUXP15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP15" }, "CFG_SECURITY_BOT_PELE1.MONITOR_HORIZ_VAUXP6->MONITOR_VERT_VAUXP6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP6" }, "CFG_SECURITY_BOT_PELE1.MONITOR_HORIZ_VAUXP7->MONITOR_VERT_VAUXP7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP7" } }, "sites": [], "tile_type": "CFG_SECURITY_BOT_PELE1", - "wires": [ - "INT_FEEDTHRU_1_EE2A0", - "INT_FEEDTHRU_1_EE2A0_1", - "INT_FEEDTHRU_1_EE2A0_2", - "INT_FEEDTHRU_1_EE2A0_3", - "INT_FEEDTHRU_1_EE2A0_4", - "INT_FEEDTHRU_1_EE2A0_5", - "INT_FEEDTHRU_1_EE2A0_6", - "INT_FEEDTHRU_1_EE2A0_7", - "INT_FEEDTHRU_1_EE2A0_8", - "INT_FEEDTHRU_1_EE2A0_9", - "INT_FEEDTHRU_1_EE2A1", - "INT_FEEDTHRU_1_EE2A1_1", - "INT_FEEDTHRU_1_EE2A1_2", - "INT_FEEDTHRU_1_EE2A1_3", - "INT_FEEDTHRU_1_EE2A1_4", - "INT_FEEDTHRU_1_EE2A1_5", - "INT_FEEDTHRU_1_EE2A1_6", - "INT_FEEDTHRU_1_EE2A1_7", - "INT_FEEDTHRU_1_EE2A1_8", - "INT_FEEDTHRU_1_EE2A1_9", - "INT_FEEDTHRU_1_EE2A2", - "INT_FEEDTHRU_1_EE2A2_1", - "INT_FEEDTHRU_1_EE2A2_2", - "INT_FEEDTHRU_1_EE2A2_3", - "INT_FEEDTHRU_1_EE2A2_4", - "INT_FEEDTHRU_1_EE2A2_5", - "INT_FEEDTHRU_1_EE2A2_6", - "INT_FEEDTHRU_1_EE2A2_7", - "INT_FEEDTHRU_1_EE2A2_8", - "INT_FEEDTHRU_1_EE2A2_9", - "INT_FEEDTHRU_1_EE2A3", - "INT_FEEDTHRU_1_EE2A3_1", - "INT_FEEDTHRU_1_EE2A3_2", - "INT_FEEDTHRU_1_EE2A3_3", - "INT_FEEDTHRU_1_EE2A3_4", - "INT_FEEDTHRU_1_EE2A3_5", - "INT_FEEDTHRU_1_EE2A3_6", - "INT_FEEDTHRU_1_EE2A3_7", - "INT_FEEDTHRU_1_EE2A3_8", - "INT_FEEDTHRU_1_EE2A3_9", - "INT_FEEDTHRU_1_EE2BEG0", - "INT_FEEDTHRU_1_EE2BEG0_1", - "INT_FEEDTHRU_1_EE2BEG0_2", - "INT_FEEDTHRU_1_EE2BEG0_3", - "INT_FEEDTHRU_1_EE2BEG0_4", - "INT_FEEDTHRU_1_EE2BEG0_5", - "INT_FEEDTHRU_1_EE2BEG0_6", - "INT_FEEDTHRU_1_EE2BEG0_7", - "INT_FEEDTHRU_1_EE2BEG0_8", - "INT_FEEDTHRU_1_EE2BEG0_9", - "INT_FEEDTHRU_1_EE2BEG1", - "INT_FEEDTHRU_1_EE2BEG1_1", - "INT_FEEDTHRU_1_EE2BEG1_2", - "INT_FEEDTHRU_1_EE2BEG1_3", - "INT_FEEDTHRU_1_EE2BEG1_4", - "INT_FEEDTHRU_1_EE2BEG1_5", - "INT_FEEDTHRU_1_EE2BEG1_6", - "INT_FEEDTHRU_1_EE2BEG1_7", - "INT_FEEDTHRU_1_EE2BEG1_8", - "INT_FEEDTHRU_1_EE2BEG1_9", - "INT_FEEDTHRU_1_EE2BEG2", - "INT_FEEDTHRU_1_EE2BEG2_1", - "INT_FEEDTHRU_1_EE2BEG2_2", - "INT_FEEDTHRU_1_EE2BEG2_3", - "INT_FEEDTHRU_1_EE2BEG2_4", - "INT_FEEDTHRU_1_EE2BEG2_5", - "INT_FEEDTHRU_1_EE2BEG2_6", - "INT_FEEDTHRU_1_EE2BEG2_7", - "INT_FEEDTHRU_1_EE2BEG2_8", - "INT_FEEDTHRU_1_EE2BEG2_9", - "INT_FEEDTHRU_1_EE2BEG3", - "INT_FEEDTHRU_1_EE2BEG3_1", - "INT_FEEDTHRU_1_EE2BEG3_2", - "INT_FEEDTHRU_1_EE2BEG3_3", - "INT_FEEDTHRU_1_EE2BEG3_4", - "INT_FEEDTHRU_1_EE2BEG3_5", - "INT_FEEDTHRU_1_EE2BEG3_6", - "INT_FEEDTHRU_1_EE2BEG3_7", - "INT_FEEDTHRU_1_EE2BEG3_8", - "INT_FEEDTHRU_1_EE2BEG3_9", - "INT_FEEDTHRU_1_EE4A0", - "INT_FEEDTHRU_1_EE4A0_1", - "INT_FEEDTHRU_1_EE4A0_2", - "INT_FEEDTHRU_1_EE4A0_3", - "INT_FEEDTHRU_1_EE4A0_4", - "INT_FEEDTHRU_1_EE4A0_5", - "INT_FEEDTHRU_1_EE4A0_6", - "INT_FEEDTHRU_1_EE4A0_7", - "INT_FEEDTHRU_1_EE4A0_8", - "INT_FEEDTHRU_1_EE4A0_9", - "INT_FEEDTHRU_1_EE4A1", - "INT_FEEDTHRU_1_EE4A1_1", - "INT_FEEDTHRU_1_EE4A1_2", - "INT_FEEDTHRU_1_EE4A1_3", - "INT_FEEDTHRU_1_EE4A1_4", - "INT_FEEDTHRU_1_EE4A1_5", - "INT_FEEDTHRU_1_EE4A1_6", - "INT_FEEDTHRU_1_EE4A1_7", - "INT_FEEDTHRU_1_EE4A1_8", - "INT_FEEDTHRU_1_EE4A1_9", - "INT_FEEDTHRU_1_EE4A2", - "INT_FEEDTHRU_1_EE4A2_1", - "INT_FEEDTHRU_1_EE4A2_2", - "INT_FEEDTHRU_1_EE4A2_3", - "INT_FEEDTHRU_1_EE4A2_4", - "INT_FEEDTHRU_1_EE4A2_5", - "INT_FEEDTHRU_1_EE4A2_6", - "INT_FEEDTHRU_1_EE4A2_7", - "INT_FEEDTHRU_1_EE4A2_8", - "INT_FEEDTHRU_1_EE4A2_9", - "INT_FEEDTHRU_1_EE4A3", - "INT_FEEDTHRU_1_EE4A3_1", - "INT_FEEDTHRU_1_EE4A3_2", - "INT_FEEDTHRU_1_EE4A3_3", - "INT_FEEDTHRU_1_EE4A3_4", - "INT_FEEDTHRU_1_EE4A3_5", - "INT_FEEDTHRU_1_EE4A3_6", - "INT_FEEDTHRU_1_EE4A3_7", - "INT_FEEDTHRU_1_EE4A3_8", - "INT_FEEDTHRU_1_EE4A3_9", - "INT_FEEDTHRU_1_EE4B0", - "INT_FEEDTHRU_1_EE4B0_1", - "INT_FEEDTHRU_1_EE4B0_2", - "INT_FEEDTHRU_1_EE4B0_3", - "INT_FEEDTHRU_1_EE4B0_4", - "INT_FEEDTHRU_1_EE4B0_5", - "INT_FEEDTHRU_1_EE4B0_6", - "INT_FEEDTHRU_1_EE4B0_7", - "INT_FEEDTHRU_1_EE4B0_8", - "INT_FEEDTHRU_1_EE4B0_9", - "INT_FEEDTHRU_1_EE4B1", - "INT_FEEDTHRU_1_EE4B1_1", - "INT_FEEDTHRU_1_EE4B1_2", - "INT_FEEDTHRU_1_EE4B1_3", - "INT_FEEDTHRU_1_EE4B1_4", - "INT_FEEDTHRU_1_EE4B1_5", - "INT_FEEDTHRU_1_EE4B1_6", - "INT_FEEDTHRU_1_EE4B1_7", - "INT_FEEDTHRU_1_EE4B1_8", - "INT_FEEDTHRU_1_EE4B1_9", - "INT_FEEDTHRU_1_EE4B2", - "INT_FEEDTHRU_1_EE4B2_1", - "INT_FEEDTHRU_1_EE4B2_2", - "INT_FEEDTHRU_1_EE4B2_3", - "INT_FEEDTHRU_1_EE4B2_4", - "INT_FEEDTHRU_1_EE4B2_5", - "INT_FEEDTHRU_1_EE4B2_6", - "INT_FEEDTHRU_1_EE4B2_7", - "INT_FEEDTHRU_1_EE4B2_8", - "INT_FEEDTHRU_1_EE4B2_9", - "INT_FEEDTHRU_1_EE4B3", - "INT_FEEDTHRU_1_EE4B3_1", - "INT_FEEDTHRU_1_EE4B3_2", - "INT_FEEDTHRU_1_EE4B3_3", - "INT_FEEDTHRU_1_EE4B3_4", - "INT_FEEDTHRU_1_EE4B3_5", - "INT_FEEDTHRU_1_EE4B3_6", - "INT_FEEDTHRU_1_EE4B3_7", - "INT_FEEDTHRU_1_EE4B3_8", - "INT_FEEDTHRU_1_EE4B3_9", - "INT_FEEDTHRU_1_EE4BEG0", - "INT_FEEDTHRU_1_EE4BEG0_1", - "INT_FEEDTHRU_1_EE4BEG0_2", - "INT_FEEDTHRU_1_EE4BEG0_3", - "INT_FEEDTHRU_1_EE4BEG0_4", - "INT_FEEDTHRU_1_EE4BEG0_5", - "INT_FEEDTHRU_1_EE4BEG0_6", - "INT_FEEDTHRU_1_EE4BEG0_7", - "INT_FEEDTHRU_1_EE4BEG0_8", - "INT_FEEDTHRU_1_EE4BEG0_9", - "INT_FEEDTHRU_1_EE4BEG1", - "INT_FEEDTHRU_1_EE4BEG1_1", - "INT_FEEDTHRU_1_EE4BEG1_2", - "INT_FEEDTHRU_1_EE4BEG1_3", - "INT_FEEDTHRU_1_EE4BEG1_4", - "INT_FEEDTHRU_1_EE4BEG1_5", - "INT_FEEDTHRU_1_EE4BEG1_6", - "INT_FEEDTHRU_1_EE4BEG1_7", - "INT_FEEDTHRU_1_EE4BEG1_8", - "INT_FEEDTHRU_1_EE4BEG1_9", - "INT_FEEDTHRU_1_EE4BEG2", - "INT_FEEDTHRU_1_EE4BEG2_1", - "INT_FEEDTHRU_1_EE4BEG2_2", - "INT_FEEDTHRU_1_EE4BEG2_3", - "INT_FEEDTHRU_1_EE4BEG2_4", - "INT_FEEDTHRU_1_EE4BEG2_5", - "INT_FEEDTHRU_1_EE4BEG2_6", - "INT_FEEDTHRU_1_EE4BEG2_7", - "INT_FEEDTHRU_1_EE4BEG2_8", - "INT_FEEDTHRU_1_EE4BEG2_9", - "INT_FEEDTHRU_1_EE4BEG3", - "INT_FEEDTHRU_1_EE4BEG3_1", - "INT_FEEDTHRU_1_EE4BEG3_2", - "INT_FEEDTHRU_1_EE4BEG3_3", - "INT_FEEDTHRU_1_EE4BEG3_4", - "INT_FEEDTHRU_1_EE4BEG3_5", - "INT_FEEDTHRU_1_EE4BEG3_6", - "INT_FEEDTHRU_1_EE4BEG3_7", - "INT_FEEDTHRU_1_EE4BEG3_8", - "INT_FEEDTHRU_1_EE4BEG3_9", - "INT_FEEDTHRU_1_EE4C0", - "INT_FEEDTHRU_1_EE4C0_1", - "INT_FEEDTHRU_1_EE4C0_2", - "INT_FEEDTHRU_1_EE4C0_3", - "INT_FEEDTHRU_1_EE4C0_4", - "INT_FEEDTHRU_1_EE4C0_5", - "INT_FEEDTHRU_1_EE4C0_6", - "INT_FEEDTHRU_1_EE4C0_7", - "INT_FEEDTHRU_1_EE4C0_8", - "INT_FEEDTHRU_1_EE4C0_9", - "INT_FEEDTHRU_1_EE4C1", - "INT_FEEDTHRU_1_EE4C1_1", - "INT_FEEDTHRU_1_EE4C1_2", - "INT_FEEDTHRU_1_EE4C1_3", - "INT_FEEDTHRU_1_EE4C1_4", - "INT_FEEDTHRU_1_EE4C1_5", - "INT_FEEDTHRU_1_EE4C1_6", - "INT_FEEDTHRU_1_EE4C1_7", - "INT_FEEDTHRU_1_EE4C1_8", - "INT_FEEDTHRU_1_EE4C1_9", - "INT_FEEDTHRU_1_EE4C2", - "INT_FEEDTHRU_1_EE4C2_1", - "INT_FEEDTHRU_1_EE4C2_2", - "INT_FEEDTHRU_1_EE4C2_3", - "INT_FEEDTHRU_1_EE4C2_4", - "INT_FEEDTHRU_1_EE4C2_5", - "INT_FEEDTHRU_1_EE4C2_6", - "INT_FEEDTHRU_1_EE4C2_7", - "INT_FEEDTHRU_1_EE4C2_8", - "INT_FEEDTHRU_1_EE4C2_9", - "INT_FEEDTHRU_1_EE4C3", - "INT_FEEDTHRU_1_EE4C3_1", - "INT_FEEDTHRU_1_EE4C3_2", - "INT_FEEDTHRU_1_EE4C3_3", - "INT_FEEDTHRU_1_EE4C3_4", - "INT_FEEDTHRU_1_EE4C3_5", - "INT_FEEDTHRU_1_EE4C3_6", - "INT_FEEDTHRU_1_EE4C3_7", - "INT_FEEDTHRU_1_EE4C3_8", - "INT_FEEDTHRU_1_EE4C3_9", - "INT_FEEDTHRU_1_EL1BEG0", - "INT_FEEDTHRU_1_EL1BEG0_1", - "INT_FEEDTHRU_1_EL1BEG0_2", - "INT_FEEDTHRU_1_EL1BEG0_3", - "INT_FEEDTHRU_1_EL1BEG0_4", - "INT_FEEDTHRU_1_EL1BEG0_5", - "INT_FEEDTHRU_1_EL1BEG0_6", - "INT_FEEDTHRU_1_EL1BEG0_7", - "INT_FEEDTHRU_1_EL1BEG0_8", - "INT_FEEDTHRU_1_EL1BEG0_9", - "INT_FEEDTHRU_1_EL1BEG1", - "INT_FEEDTHRU_1_EL1BEG1_1", - "INT_FEEDTHRU_1_EL1BEG1_2", - "INT_FEEDTHRU_1_EL1BEG1_3", - "INT_FEEDTHRU_1_EL1BEG1_4", - "INT_FEEDTHRU_1_EL1BEG1_5", - "INT_FEEDTHRU_1_EL1BEG1_6", - "INT_FEEDTHRU_1_EL1BEG1_7", - "INT_FEEDTHRU_1_EL1BEG1_8", - "INT_FEEDTHRU_1_EL1BEG1_9", - "INT_FEEDTHRU_1_EL1BEG2", - "INT_FEEDTHRU_1_EL1BEG2_1", - "INT_FEEDTHRU_1_EL1BEG2_2", - "INT_FEEDTHRU_1_EL1BEG2_3", - "INT_FEEDTHRU_1_EL1BEG2_4", - "INT_FEEDTHRU_1_EL1BEG2_5", - "INT_FEEDTHRU_1_EL1BEG2_6", - "INT_FEEDTHRU_1_EL1BEG2_7", - "INT_FEEDTHRU_1_EL1BEG2_8", - "INT_FEEDTHRU_1_EL1BEG2_9", - "INT_FEEDTHRU_1_EL1BEG3", - "INT_FEEDTHRU_1_EL1BEG3_1", - "INT_FEEDTHRU_1_EL1BEG3_2", - "INT_FEEDTHRU_1_EL1BEG3_3", - "INT_FEEDTHRU_1_EL1BEG3_4", - "INT_FEEDTHRU_1_EL1BEG3_5", - "INT_FEEDTHRU_1_EL1BEG3_6", - "INT_FEEDTHRU_1_EL1BEG3_7", - "INT_FEEDTHRU_1_EL1BEG3_8", - "INT_FEEDTHRU_1_EL1BEG3_9", - "INT_FEEDTHRU_1_ER1BEG0", - "INT_FEEDTHRU_1_ER1BEG0_1", - "INT_FEEDTHRU_1_ER1BEG0_2", - "INT_FEEDTHRU_1_ER1BEG0_3", - "INT_FEEDTHRU_1_ER1BEG0_4", - "INT_FEEDTHRU_1_ER1BEG0_5", - "INT_FEEDTHRU_1_ER1BEG0_6", - "INT_FEEDTHRU_1_ER1BEG0_7", - "INT_FEEDTHRU_1_ER1BEG0_8", - "INT_FEEDTHRU_1_ER1BEG0_9", - "INT_FEEDTHRU_1_ER1BEG1", - "INT_FEEDTHRU_1_ER1BEG1_1", - "INT_FEEDTHRU_1_ER1BEG1_2", - "INT_FEEDTHRU_1_ER1BEG1_3", - "INT_FEEDTHRU_1_ER1BEG1_4", - "INT_FEEDTHRU_1_ER1BEG1_5", - "INT_FEEDTHRU_1_ER1BEG1_6", - "INT_FEEDTHRU_1_ER1BEG1_7", - "INT_FEEDTHRU_1_ER1BEG1_8", - "INT_FEEDTHRU_1_ER1BEG1_9", - "INT_FEEDTHRU_1_ER1BEG2", - "INT_FEEDTHRU_1_ER1BEG2_1", - "INT_FEEDTHRU_1_ER1BEG2_2", - "INT_FEEDTHRU_1_ER1BEG2_3", - "INT_FEEDTHRU_1_ER1BEG2_4", - "INT_FEEDTHRU_1_ER1BEG2_5", - "INT_FEEDTHRU_1_ER1BEG2_6", - "INT_FEEDTHRU_1_ER1BEG2_7", - "INT_FEEDTHRU_1_ER1BEG2_8", - "INT_FEEDTHRU_1_ER1BEG2_9", - "INT_FEEDTHRU_1_ER1BEG3", - "INT_FEEDTHRU_1_ER1BEG3_1", - "INT_FEEDTHRU_1_ER1BEG3_2", - "INT_FEEDTHRU_1_ER1BEG3_3", - "INT_FEEDTHRU_1_ER1BEG3_4", - "INT_FEEDTHRU_1_ER1BEG3_5", - "INT_FEEDTHRU_1_ER1BEG3_6", - "INT_FEEDTHRU_1_ER1BEG3_7", - "INT_FEEDTHRU_1_ER1BEG3_8", - "INT_FEEDTHRU_1_ER1BEG3_9", - "INT_FEEDTHRU_1_LH1", - "INT_FEEDTHRU_1_LH10", - "INT_FEEDTHRU_1_LH10_1", - "INT_FEEDTHRU_1_LH10_2", - "INT_FEEDTHRU_1_LH10_3", - "INT_FEEDTHRU_1_LH10_4", - "INT_FEEDTHRU_1_LH10_5", - "INT_FEEDTHRU_1_LH10_6", - "INT_FEEDTHRU_1_LH10_7", - "INT_FEEDTHRU_1_LH10_8", - "INT_FEEDTHRU_1_LH10_9", - "INT_FEEDTHRU_1_LH11", - "INT_FEEDTHRU_1_LH11_1", - "INT_FEEDTHRU_1_LH11_2", - "INT_FEEDTHRU_1_LH11_3", - "INT_FEEDTHRU_1_LH11_4", - "INT_FEEDTHRU_1_LH11_5", - "INT_FEEDTHRU_1_LH11_6", - "INT_FEEDTHRU_1_LH11_7", - "INT_FEEDTHRU_1_LH11_8", - "INT_FEEDTHRU_1_LH11_9", - "INT_FEEDTHRU_1_LH12", - "INT_FEEDTHRU_1_LH12_1", - "INT_FEEDTHRU_1_LH12_2", - "INT_FEEDTHRU_1_LH12_3", - "INT_FEEDTHRU_1_LH12_4", - "INT_FEEDTHRU_1_LH12_5", - "INT_FEEDTHRU_1_LH12_6", - "INT_FEEDTHRU_1_LH12_7", - "INT_FEEDTHRU_1_LH12_8", - "INT_FEEDTHRU_1_LH12_9", - "INT_FEEDTHRU_1_LH1_1", - "INT_FEEDTHRU_1_LH1_2", - "INT_FEEDTHRU_1_LH1_3", - "INT_FEEDTHRU_1_LH1_4", - "INT_FEEDTHRU_1_LH1_5", - "INT_FEEDTHRU_1_LH1_6", - "INT_FEEDTHRU_1_LH1_7", - "INT_FEEDTHRU_1_LH1_8", - "INT_FEEDTHRU_1_LH1_9", - "INT_FEEDTHRU_1_LH2", - "INT_FEEDTHRU_1_LH2_1", - "INT_FEEDTHRU_1_LH2_2", - "INT_FEEDTHRU_1_LH2_3", - "INT_FEEDTHRU_1_LH2_4", - "INT_FEEDTHRU_1_LH2_5", - "INT_FEEDTHRU_1_LH2_6", - "INT_FEEDTHRU_1_LH2_7", - "INT_FEEDTHRU_1_LH2_8", - "INT_FEEDTHRU_1_LH2_9", - "INT_FEEDTHRU_1_LH3", - "INT_FEEDTHRU_1_LH3_1", - "INT_FEEDTHRU_1_LH3_2", - "INT_FEEDTHRU_1_LH3_3", - "INT_FEEDTHRU_1_LH3_4", - "INT_FEEDTHRU_1_LH3_5", - "INT_FEEDTHRU_1_LH3_6", - "INT_FEEDTHRU_1_LH3_7", - "INT_FEEDTHRU_1_LH3_8", - "INT_FEEDTHRU_1_LH3_9", - "INT_FEEDTHRU_1_LH4", - "INT_FEEDTHRU_1_LH4_1", - "INT_FEEDTHRU_1_LH4_2", - "INT_FEEDTHRU_1_LH4_3", - "INT_FEEDTHRU_1_LH4_4", - "INT_FEEDTHRU_1_LH4_5", - "INT_FEEDTHRU_1_LH4_6", - "INT_FEEDTHRU_1_LH4_7", - "INT_FEEDTHRU_1_LH4_8", - "INT_FEEDTHRU_1_LH4_9", - "INT_FEEDTHRU_1_LH5", - "INT_FEEDTHRU_1_LH5_1", - "INT_FEEDTHRU_1_LH5_2", - "INT_FEEDTHRU_1_LH5_3", - "INT_FEEDTHRU_1_LH5_4", - "INT_FEEDTHRU_1_LH5_5", - "INT_FEEDTHRU_1_LH5_6", - "INT_FEEDTHRU_1_LH5_7", - "INT_FEEDTHRU_1_LH5_8", - "INT_FEEDTHRU_1_LH5_9", - "INT_FEEDTHRU_1_LH6", - "INT_FEEDTHRU_1_LH6_1", - "INT_FEEDTHRU_1_LH6_2", - "INT_FEEDTHRU_1_LH6_3", - "INT_FEEDTHRU_1_LH6_4", - "INT_FEEDTHRU_1_LH6_5", - "INT_FEEDTHRU_1_LH6_6", - "INT_FEEDTHRU_1_LH6_7", - "INT_FEEDTHRU_1_LH6_8", - "INT_FEEDTHRU_1_LH6_9", - "INT_FEEDTHRU_1_LH7", - "INT_FEEDTHRU_1_LH7_1", - "INT_FEEDTHRU_1_LH7_2", - "INT_FEEDTHRU_1_LH7_3", - "INT_FEEDTHRU_1_LH7_4", - "INT_FEEDTHRU_1_LH7_5", - "INT_FEEDTHRU_1_LH7_6", - "INT_FEEDTHRU_1_LH7_7", - "INT_FEEDTHRU_1_LH7_8", - "INT_FEEDTHRU_1_LH7_9", - "INT_FEEDTHRU_1_LH8", - "INT_FEEDTHRU_1_LH8_1", - "INT_FEEDTHRU_1_LH8_2", - "INT_FEEDTHRU_1_LH8_3", - "INT_FEEDTHRU_1_LH8_4", - "INT_FEEDTHRU_1_LH8_5", - "INT_FEEDTHRU_1_LH8_6", - "INT_FEEDTHRU_1_LH8_7", - "INT_FEEDTHRU_1_LH8_8", - "INT_FEEDTHRU_1_LH8_9", - "INT_FEEDTHRU_1_LH9", - "INT_FEEDTHRU_1_LH9_1", - "INT_FEEDTHRU_1_LH9_2", - "INT_FEEDTHRU_1_LH9_3", - "INT_FEEDTHRU_1_LH9_4", - "INT_FEEDTHRU_1_LH9_5", - "INT_FEEDTHRU_1_LH9_6", - "INT_FEEDTHRU_1_LH9_7", - "INT_FEEDTHRU_1_LH9_8", - "INT_FEEDTHRU_1_LH9_9", - "INT_FEEDTHRU_1_MONITOR_N", - "INT_FEEDTHRU_1_MONITOR_N_2", - "INT_FEEDTHRU_1_MONITOR_N_3", - "INT_FEEDTHRU_1_MONITOR_N_4", - "INT_FEEDTHRU_1_MONITOR_N_6", - "INT_FEEDTHRU_1_MONITOR_N_8", - "INT_FEEDTHRU_1_MONITOR_P", - "INT_FEEDTHRU_1_MONITOR_P_2", - "INT_FEEDTHRU_1_MONITOR_P_3", - "INT_FEEDTHRU_1_MONITOR_P_4", - "INT_FEEDTHRU_1_MONITOR_P_6", - "INT_FEEDTHRU_1_MONITOR_P_8", - "INT_FEEDTHRU_1_NE2A0", - "INT_FEEDTHRU_1_NE2A0_1", - "INT_FEEDTHRU_1_NE2A0_2", - "INT_FEEDTHRU_1_NE2A0_3", - "INT_FEEDTHRU_1_NE2A0_4", - "INT_FEEDTHRU_1_NE2A0_5", - "INT_FEEDTHRU_1_NE2A0_6", - "INT_FEEDTHRU_1_NE2A0_7", - "INT_FEEDTHRU_1_NE2A0_8", - "INT_FEEDTHRU_1_NE2A0_9", - "INT_FEEDTHRU_1_NE2A1", - "INT_FEEDTHRU_1_NE2A1_1", - "INT_FEEDTHRU_1_NE2A1_2", - "INT_FEEDTHRU_1_NE2A1_3", - "INT_FEEDTHRU_1_NE2A1_4", - "INT_FEEDTHRU_1_NE2A1_5", - "INT_FEEDTHRU_1_NE2A1_6", - "INT_FEEDTHRU_1_NE2A1_7", - "INT_FEEDTHRU_1_NE2A1_8", - "INT_FEEDTHRU_1_NE2A1_9", - "INT_FEEDTHRU_1_NE2A2", - "INT_FEEDTHRU_1_NE2A2_1", - "INT_FEEDTHRU_1_NE2A2_2", - "INT_FEEDTHRU_1_NE2A2_3", - "INT_FEEDTHRU_1_NE2A2_4", - "INT_FEEDTHRU_1_NE2A2_5", - "INT_FEEDTHRU_1_NE2A2_6", - "INT_FEEDTHRU_1_NE2A2_7", - "INT_FEEDTHRU_1_NE2A2_8", - "INT_FEEDTHRU_1_NE2A2_9", - "INT_FEEDTHRU_1_NE2A3", - "INT_FEEDTHRU_1_NE2A3_1", - "INT_FEEDTHRU_1_NE2A3_2", - "INT_FEEDTHRU_1_NE2A3_3", - "INT_FEEDTHRU_1_NE2A3_4", - "INT_FEEDTHRU_1_NE2A3_5", - "INT_FEEDTHRU_1_NE2A3_6", - "INT_FEEDTHRU_1_NE2A3_7", - "INT_FEEDTHRU_1_NE2A3_8", - "INT_FEEDTHRU_1_NE2A3_9", - "INT_FEEDTHRU_1_NE4BEG0", - "INT_FEEDTHRU_1_NE4BEG0_1", - "INT_FEEDTHRU_1_NE4BEG0_2", - "INT_FEEDTHRU_1_NE4BEG0_3", - "INT_FEEDTHRU_1_NE4BEG0_4", - "INT_FEEDTHRU_1_NE4BEG0_5", - "INT_FEEDTHRU_1_NE4BEG0_6", - "INT_FEEDTHRU_1_NE4BEG0_7", - "INT_FEEDTHRU_1_NE4BEG0_8", - "INT_FEEDTHRU_1_NE4BEG0_9", - "INT_FEEDTHRU_1_NE4BEG1", - "INT_FEEDTHRU_1_NE4BEG1_1", - "INT_FEEDTHRU_1_NE4BEG1_2", - "INT_FEEDTHRU_1_NE4BEG1_3", - "INT_FEEDTHRU_1_NE4BEG1_4", - "INT_FEEDTHRU_1_NE4BEG1_5", - "INT_FEEDTHRU_1_NE4BEG1_6", - "INT_FEEDTHRU_1_NE4BEG1_7", - "INT_FEEDTHRU_1_NE4BEG1_8", - "INT_FEEDTHRU_1_NE4BEG1_9", - "INT_FEEDTHRU_1_NE4BEG2", - "INT_FEEDTHRU_1_NE4BEG2_1", - "INT_FEEDTHRU_1_NE4BEG2_2", - "INT_FEEDTHRU_1_NE4BEG2_3", - "INT_FEEDTHRU_1_NE4BEG2_4", - "INT_FEEDTHRU_1_NE4BEG2_5", - "INT_FEEDTHRU_1_NE4BEG2_6", - "INT_FEEDTHRU_1_NE4BEG2_7", - "INT_FEEDTHRU_1_NE4BEG2_8", - "INT_FEEDTHRU_1_NE4BEG2_9", - "INT_FEEDTHRU_1_NE4BEG3", - "INT_FEEDTHRU_1_NE4BEG3_1", - "INT_FEEDTHRU_1_NE4BEG3_2", - "INT_FEEDTHRU_1_NE4BEG3_3", - "INT_FEEDTHRU_1_NE4BEG3_4", - "INT_FEEDTHRU_1_NE4BEG3_5", - "INT_FEEDTHRU_1_NE4BEG3_6", - "INT_FEEDTHRU_1_NE4BEG3_7", - "INT_FEEDTHRU_1_NE4BEG3_8", - "INT_FEEDTHRU_1_NE4BEG3_9", - "INT_FEEDTHRU_1_NE4C0", - "INT_FEEDTHRU_1_NE4C0_1", - "INT_FEEDTHRU_1_NE4C0_2", - "INT_FEEDTHRU_1_NE4C0_3", - "INT_FEEDTHRU_1_NE4C0_4", - "INT_FEEDTHRU_1_NE4C0_5", - "INT_FEEDTHRU_1_NE4C0_6", - "INT_FEEDTHRU_1_NE4C0_7", - "INT_FEEDTHRU_1_NE4C0_8", - "INT_FEEDTHRU_1_NE4C0_9", - "INT_FEEDTHRU_1_NE4C1", - "INT_FEEDTHRU_1_NE4C1_1", - "INT_FEEDTHRU_1_NE4C1_2", - "INT_FEEDTHRU_1_NE4C1_3", - "INT_FEEDTHRU_1_NE4C1_4", - "INT_FEEDTHRU_1_NE4C1_5", - "INT_FEEDTHRU_1_NE4C1_6", - "INT_FEEDTHRU_1_NE4C1_7", - "INT_FEEDTHRU_1_NE4C1_8", - "INT_FEEDTHRU_1_NE4C1_9", - "INT_FEEDTHRU_1_NE4C2", - "INT_FEEDTHRU_1_NE4C2_1", - "INT_FEEDTHRU_1_NE4C2_2", - "INT_FEEDTHRU_1_NE4C2_3", - "INT_FEEDTHRU_1_NE4C2_4", - "INT_FEEDTHRU_1_NE4C2_5", - "INT_FEEDTHRU_1_NE4C2_6", - "INT_FEEDTHRU_1_NE4C2_7", - "INT_FEEDTHRU_1_NE4C2_8", - "INT_FEEDTHRU_1_NE4C2_9", - "INT_FEEDTHRU_1_NE4C3", - "INT_FEEDTHRU_1_NE4C3_1", - "INT_FEEDTHRU_1_NE4C3_2", - "INT_FEEDTHRU_1_NE4C3_3", - "INT_FEEDTHRU_1_NE4C3_4", - "INT_FEEDTHRU_1_NE4C3_5", - "INT_FEEDTHRU_1_NE4C3_6", - "INT_FEEDTHRU_1_NE4C3_7", - "INT_FEEDTHRU_1_NE4C3_8", - "INT_FEEDTHRU_1_NE4C3_9", - "INT_FEEDTHRU_1_NW2A0", - "INT_FEEDTHRU_1_NW2A0_1", - "INT_FEEDTHRU_1_NW2A0_2", - "INT_FEEDTHRU_1_NW2A0_3", - "INT_FEEDTHRU_1_NW2A0_4", - "INT_FEEDTHRU_1_NW2A0_5", - "INT_FEEDTHRU_1_NW2A0_6", - "INT_FEEDTHRU_1_NW2A0_7", - "INT_FEEDTHRU_1_NW2A0_8", - "INT_FEEDTHRU_1_NW2A0_9", - "INT_FEEDTHRU_1_NW2A1", - "INT_FEEDTHRU_1_NW2A1_1", - "INT_FEEDTHRU_1_NW2A1_2", - "INT_FEEDTHRU_1_NW2A1_3", - "INT_FEEDTHRU_1_NW2A1_4", - "INT_FEEDTHRU_1_NW2A1_5", - "INT_FEEDTHRU_1_NW2A1_6", - "INT_FEEDTHRU_1_NW2A1_7", - "INT_FEEDTHRU_1_NW2A1_8", - "INT_FEEDTHRU_1_NW2A1_9", - "INT_FEEDTHRU_1_NW2A2", - "INT_FEEDTHRU_1_NW2A2_1", - "INT_FEEDTHRU_1_NW2A2_2", - "INT_FEEDTHRU_1_NW2A2_3", - "INT_FEEDTHRU_1_NW2A2_4", - "INT_FEEDTHRU_1_NW2A2_5", - "INT_FEEDTHRU_1_NW2A2_6", - "INT_FEEDTHRU_1_NW2A2_7", - "INT_FEEDTHRU_1_NW2A2_8", - "INT_FEEDTHRU_1_NW2A2_9", - "INT_FEEDTHRU_1_NW2A3", - "INT_FEEDTHRU_1_NW2A3_1", - "INT_FEEDTHRU_1_NW2A3_2", - "INT_FEEDTHRU_1_NW2A3_3", - "INT_FEEDTHRU_1_NW2A3_4", - "INT_FEEDTHRU_1_NW2A3_5", - "INT_FEEDTHRU_1_NW2A3_6", - "INT_FEEDTHRU_1_NW2A3_7", - "INT_FEEDTHRU_1_NW2A3_8", - "INT_FEEDTHRU_1_NW2A3_9", - "INT_FEEDTHRU_1_NW4A0", - "INT_FEEDTHRU_1_NW4A0_1", - "INT_FEEDTHRU_1_NW4A0_2", - "INT_FEEDTHRU_1_NW4A0_3", - "INT_FEEDTHRU_1_NW4A0_4", - "INT_FEEDTHRU_1_NW4A0_5", - "INT_FEEDTHRU_1_NW4A0_6", - "INT_FEEDTHRU_1_NW4A0_7", - "INT_FEEDTHRU_1_NW4A0_8", - "INT_FEEDTHRU_1_NW4A0_9", - "INT_FEEDTHRU_1_NW4A1", - "INT_FEEDTHRU_1_NW4A1_1", - "INT_FEEDTHRU_1_NW4A1_2", - "INT_FEEDTHRU_1_NW4A1_3", - "INT_FEEDTHRU_1_NW4A1_4", - "INT_FEEDTHRU_1_NW4A1_5", - "INT_FEEDTHRU_1_NW4A1_6", - "INT_FEEDTHRU_1_NW4A1_7", - "INT_FEEDTHRU_1_NW4A1_8", - "INT_FEEDTHRU_1_NW4A1_9", - "INT_FEEDTHRU_1_NW4A2", - "INT_FEEDTHRU_1_NW4A2_1", - "INT_FEEDTHRU_1_NW4A2_2", - "INT_FEEDTHRU_1_NW4A2_3", - "INT_FEEDTHRU_1_NW4A2_4", - "INT_FEEDTHRU_1_NW4A2_5", - "INT_FEEDTHRU_1_NW4A2_6", - "INT_FEEDTHRU_1_NW4A2_7", - "INT_FEEDTHRU_1_NW4A2_8", - "INT_FEEDTHRU_1_NW4A2_9", - "INT_FEEDTHRU_1_NW4A3", - "INT_FEEDTHRU_1_NW4A3_1", - "INT_FEEDTHRU_1_NW4A3_2", - "INT_FEEDTHRU_1_NW4A3_3", - "INT_FEEDTHRU_1_NW4A3_4", - "INT_FEEDTHRU_1_NW4A3_5", - "INT_FEEDTHRU_1_NW4A3_6", - "INT_FEEDTHRU_1_NW4A3_7", - "INT_FEEDTHRU_1_NW4A3_8", - "INT_FEEDTHRU_1_NW4A3_9", - "INT_FEEDTHRU_1_NW4END0", - "INT_FEEDTHRU_1_NW4END0_1", - "INT_FEEDTHRU_1_NW4END0_2", - "INT_FEEDTHRU_1_NW4END0_3", - "INT_FEEDTHRU_1_NW4END0_4", - "INT_FEEDTHRU_1_NW4END0_5", - "INT_FEEDTHRU_1_NW4END0_6", - "INT_FEEDTHRU_1_NW4END0_7", - "INT_FEEDTHRU_1_NW4END0_8", - "INT_FEEDTHRU_1_NW4END0_9", - "INT_FEEDTHRU_1_NW4END1", - "INT_FEEDTHRU_1_NW4END1_1", - "INT_FEEDTHRU_1_NW4END1_2", - "INT_FEEDTHRU_1_NW4END1_3", - "INT_FEEDTHRU_1_NW4END1_4", - "INT_FEEDTHRU_1_NW4END1_5", - "INT_FEEDTHRU_1_NW4END1_6", - "INT_FEEDTHRU_1_NW4END1_7", - "INT_FEEDTHRU_1_NW4END1_8", - "INT_FEEDTHRU_1_NW4END1_9", - "INT_FEEDTHRU_1_NW4END2", - "INT_FEEDTHRU_1_NW4END2_1", - "INT_FEEDTHRU_1_NW4END2_2", - "INT_FEEDTHRU_1_NW4END2_3", - "INT_FEEDTHRU_1_NW4END2_4", - "INT_FEEDTHRU_1_NW4END2_5", - "INT_FEEDTHRU_1_NW4END2_6", - "INT_FEEDTHRU_1_NW4END2_7", - "INT_FEEDTHRU_1_NW4END2_8", - "INT_FEEDTHRU_1_NW4END2_9", - "INT_FEEDTHRU_1_NW4END3", - "INT_FEEDTHRU_1_NW4END3_1", - "INT_FEEDTHRU_1_NW4END3_2", - "INT_FEEDTHRU_1_NW4END3_3", - "INT_FEEDTHRU_1_NW4END3_4", - "INT_FEEDTHRU_1_NW4END3_5", - "INT_FEEDTHRU_1_NW4END3_6", - "INT_FEEDTHRU_1_NW4END3_7", - "INT_FEEDTHRU_1_NW4END3_8", - "INT_FEEDTHRU_1_NW4END3_9", - "INT_FEEDTHRU_1_SE2A0", - "INT_FEEDTHRU_1_SE2A0_1", - "INT_FEEDTHRU_1_SE2A0_2", - "INT_FEEDTHRU_1_SE2A0_3", - "INT_FEEDTHRU_1_SE2A0_4", - "INT_FEEDTHRU_1_SE2A0_5", - "INT_FEEDTHRU_1_SE2A0_6", - "INT_FEEDTHRU_1_SE2A0_7", - "INT_FEEDTHRU_1_SE2A0_8", - "INT_FEEDTHRU_1_SE2A0_9", - "INT_FEEDTHRU_1_SE2A1", - "INT_FEEDTHRU_1_SE2A1_1", - "INT_FEEDTHRU_1_SE2A1_2", - "INT_FEEDTHRU_1_SE2A1_3", - "INT_FEEDTHRU_1_SE2A1_4", - "INT_FEEDTHRU_1_SE2A1_5", - "INT_FEEDTHRU_1_SE2A1_6", - "INT_FEEDTHRU_1_SE2A1_7", - "INT_FEEDTHRU_1_SE2A1_8", - "INT_FEEDTHRU_1_SE2A1_9", - "INT_FEEDTHRU_1_SE2A2", - "INT_FEEDTHRU_1_SE2A2_1", - "INT_FEEDTHRU_1_SE2A2_2", - "INT_FEEDTHRU_1_SE2A2_3", - "INT_FEEDTHRU_1_SE2A2_4", - "INT_FEEDTHRU_1_SE2A2_5", - "INT_FEEDTHRU_1_SE2A2_6", - "INT_FEEDTHRU_1_SE2A2_7", - "INT_FEEDTHRU_1_SE2A2_8", - "INT_FEEDTHRU_1_SE2A2_9", - "INT_FEEDTHRU_1_SE2A3", - "INT_FEEDTHRU_1_SE2A3_1", - "INT_FEEDTHRU_1_SE2A3_2", - "INT_FEEDTHRU_1_SE2A3_3", - "INT_FEEDTHRU_1_SE2A3_4", - "INT_FEEDTHRU_1_SE2A3_5", - "INT_FEEDTHRU_1_SE2A3_6", - "INT_FEEDTHRU_1_SE2A3_7", - "INT_FEEDTHRU_1_SE2A3_8", - "INT_FEEDTHRU_1_SE2A3_9", - "INT_FEEDTHRU_1_SE4BEG0", - "INT_FEEDTHRU_1_SE4BEG0_1", - "INT_FEEDTHRU_1_SE4BEG0_2", - "INT_FEEDTHRU_1_SE4BEG0_3", - "INT_FEEDTHRU_1_SE4BEG0_4", - "INT_FEEDTHRU_1_SE4BEG0_5", - "INT_FEEDTHRU_1_SE4BEG0_6", - "INT_FEEDTHRU_1_SE4BEG0_7", - "INT_FEEDTHRU_1_SE4BEG0_8", - "INT_FEEDTHRU_1_SE4BEG0_9", - "INT_FEEDTHRU_1_SE4BEG1", - "INT_FEEDTHRU_1_SE4BEG1_1", - "INT_FEEDTHRU_1_SE4BEG1_2", - "INT_FEEDTHRU_1_SE4BEG1_3", - "INT_FEEDTHRU_1_SE4BEG1_4", - "INT_FEEDTHRU_1_SE4BEG1_5", - "INT_FEEDTHRU_1_SE4BEG1_6", - "INT_FEEDTHRU_1_SE4BEG1_7", - "INT_FEEDTHRU_1_SE4BEG1_8", - "INT_FEEDTHRU_1_SE4BEG1_9", - "INT_FEEDTHRU_1_SE4BEG2", - "INT_FEEDTHRU_1_SE4BEG2_1", - "INT_FEEDTHRU_1_SE4BEG2_2", - "INT_FEEDTHRU_1_SE4BEG2_3", - "INT_FEEDTHRU_1_SE4BEG2_4", - "INT_FEEDTHRU_1_SE4BEG2_5", - "INT_FEEDTHRU_1_SE4BEG2_6", - "INT_FEEDTHRU_1_SE4BEG2_7", - "INT_FEEDTHRU_1_SE4BEG2_8", - "INT_FEEDTHRU_1_SE4BEG2_9", - "INT_FEEDTHRU_1_SE4BEG3", - "INT_FEEDTHRU_1_SE4BEG3_1", - "INT_FEEDTHRU_1_SE4BEG3_2", - "INT_FEEDTHRU_1_SE4BEG3_3", - "INT_FEEDTHRU_1_SE4BEG3_4", - "INT_FEEDTHRU_1_SE4BEG3_5", - "INT_FEEDTHRU_1_SE4BEG3_6", - "INT_FEEDTHRU_1_SE4BEG3_7", - "INT_FEEDTHRU_1_SE4BEG3_8", - "INT_FEEDTHRU_1_SE4BEG3_9", - "INT_FEEDTHRU_1_SE4C0", - "INT_FEEDTHRU_1_SE4C0_1", - "INT_FEEDTHRU_1_SE4C0_2", - "INT_FEEDTHRU_1_SE4C0_3", - "INT_FEEDTHRU_1_SE4C0_4", - "INT_FEEDTHRU_1_SE4C0_5", - "INT_FEEDTHRU_1_SE4C0_6", - "INT_FEEDTHRU_1_SE4C0_7", - "INT_FEEDTHRU_1_SE4C0_8", - "INT_FEEDTHRU_1_SE4C0_9", - "INT_FEEDTHRU_1_SE4C1", - "INT_FEEDTHRU_1_SE4C1_1", - "INT_FEEDTHRU_1_SE4C1_2", - "INT_FEEDTHRU_1_SE4C1_3", - "INT_FEEDTHRU_1_SE4C1_4", - "INT_FEEDTHRU_1_SE4C1_5", - "INT_FEEDTHRU_1_SE4C1_6", - "INT_FEEDTHRU_1_SE4C1_7", - "INT_FEEDTHRU_1_SE4C1_8", - "INT_FEEDTHRU_1_SE4C1_9", - "INT_FEEDTHRU_1_SE4C2", - "INT_FEEDTHRU_1_SE4C2_1", - "INT_FEEDTHRU_1_SE4C2_2", - "INT_FEEDTHRU_1_SE4C2_3", - "INT_FEEDTHRU_1_SE4C2_4", - "INT_FEEDTHRU_1_SE4C2_5", - "INT_FEEDTHRU_1_SE4C2_6", - "INT_FEEDTHRU_1_SE4C2_7", - "INT_FEEDTHRU_1_SE4C2_8", - "INT_FEEDTHRU_1_SE4C2_9", - "INT_FEEDTHRU_1_SE4C3", - "INT_FEEDTHRU_1_SE4C3_1", - "INT_FEEDTHRU_1_SE4C3_2", - "INT_FEEDTHRU_1_SE4C3_3", - "INT_FEEDTHRU_1_SE4C3_4", - "INT_FEEDTHRU_1_SE4C3_5", - "INT_FEEDTHRU_1_SE4C3_6", - "INT_FEEDTHRU_1_SE4C3_7", - "INT_FEEDTHRU_1_SE4C3_8", - "INT_FEEDTHRU_1_SE4C3_9", - "INT_FEEDTHRU_1_SW2A0", - "INT_FEEDTHRU_1_SW2A0_1", - "INT_FEEDTHRU_1_SW2A0_2", - "INT_FEEDTHRU_1_SW2A0_3", - "INT_FEEDTHRU_1_SW2A0_4", - "INT_FEEDTHRU_1_SW2A0_5", - "INT_FEEDTHRU_1_SW2A0_6", - "INT_FEEDTHRU_1_SW2A0_7", - "INT_FEEDTHRU_1_SW2A0_8", - "INT_FEEDTHRU_1_SW2A0_9", - "INT_FEEDTHRU_1_SW2A1", - "INT_FEEDTHRU_1_SW2A1_1", - "INT_FEEDTHRU_1_SW2A1_2", - "INT_FEEDTHRU_1_SW2A1_3", - "INT_FEEDTHRU_1_SW2A1_4", - "INT_FEEDTHRU_1_SW2A1_5", - "INT_FEEDTHRU_1_SW2A1_6", - "INT_FEEDTHRU_1_SW2A1_7", - "INT_FEEDTHRU_1_SW2A1_8", - "INT_FEEDTHRU_1_SW2A1_9", - "INT_FEEDTHRU_1_SW2A2", - "INT_FEEDTHRU_1_SW2A2_1", - "INT_FEEDTHRU_1_SW2A2_2", - "INT_FEEDTHRU_1_SW2A2_3", - "INT_FEEDTHRU_1_SW2A2_4", - "INT_FEEDTHRU_1_SW2A2_5", - "INT_FEEDTHRU_1_SW2A2_6", - "INT_FEEDTHRU_1_SW2A2_7", - "INT_FEEDTHRU_1_SW2A2_8", - "INT_FEEDTHRU_1_SW2A2_9", - "INT_FEEDTHRU_1_SW2A3", - "INT_FEEDTHRU_1_SW2A3_1", - "INT_FEEDTHRU_1_SW2A3_2", - "INT_FEEDTHRU_1_SW2A3_3", - "INT_FEEDTHRU_1_SW2A3_4", - "INT_FEEDTHRU_1_SW2A3_5", - "INT_FEEDTHRU_1_SW2A3_6", - "INT_FEEDTHRU_1_SW2A3_7", - "INT_FEEDTHRU_1_SW2A3_8", - "INT_FEEDTHRU_1_SW2A3_9", - "INT_FEEDTHRU_1_SW4A0", - "INT_FEEDTHRU_1_SW4A0_1", - "INT_FEEDTHRU_1_SW4A0_2", - "INT_FEEDTHRU_1_SW4A0_3", - "INT_FEEDTHRU_1_SW4A0_4", - "INT_FEEDTHRU_1_SW4A0_5", - "INT_FEEDTHRU_1_SW4A0_6", - "INT_FEEDTHRU_1_SW4A0_7", - "INT_FEEDTHRU_1_SW4A0_8", - "INT_FEEDTHRU_1_SW4A0_9", - "INT_FEEDTHRU_1_SW4A1", - "INT_FEEDTHRU_1_SW4A1_1", - "INT_FEEDTHRU_1_SW4A1_2", - "INT_FEEDTHRU_1_SW4A1_3", - "INT_FEEDTHRU_1_SW4A1_4", - "INT_FEEDTHRU_1_SW4A1_5", - "INT_FEEDTHRU_1_SW4A1_6", - "INT_FEEDTHRU_1_SW4A1_7", - "INT_FEEDTHRU_1_SW4A1_8", - "INT_FEEDTHRU_1_SW4A1_9", - "INT_FEEDTHRU_1_SW4A2", - "INT_FEEDTHRU_1_SW4A2_1", - "INT_FEEDTHRU_1_SW4A2_2", - "INT_FEEDTHRU_1_SW4A2_3", - "INT_FEEDTHRU_1_SW4A2_4", - "INT_FEEDTHRU_1_SW4A2_5", - "INT_FEEDTHRU_1_SW4A2_6", - "INT_FEEDTHRU_1_SW4A2_7", - "INT_FEEDTHRU_1_SW4A2_8", - "INT_FEEDTHRU_1_SW4A2_9", - "INT_FEEDTHRU_1_SW4A3", - "INT_FEEDTHRU_1_SW4A3_1", - "INT_FEEDTHRU_1_SW4A3_2", - "INT_FEEDTHRU_1_SW4A3_3", - "INT_FEEDTHRU_1_SW4A3_4", - "INT_FEEDTHRU_1_SW4A3_5", - "INT_FEEDTHRU_1_SW4A3_6", - "INT_FEEDTHRU_1_SW4A3_7", - "INT_FEEDTHRU_1_SW4A3_8", - "INT_FEEDTHRU_1_SW4A3_9", - "INT_FEEDTHRU_1_SW4END0", - "INT_FEEDTHRU_1_SW4END0_1", - "INT_FEEDTHRU_1_SW4END0_2", - "INT_FEEDTHRU_1_SW4END0_3", - "INT_FEEDTHRU_1_SW4END0_4", - "INT_FEEDTHRU_1_SW4END0_5", - "INT_FEEDTHRU_1_SW4END0_6", - "INT_FEEDTHRU_1_SW4END0_7", - "INT_FEEDTHRU_1_SW4END0_8", - "INT_FEEDTHRU_1_SW4END0_9", - "INT_FEEDTHRU_1_SW4END1", - "INT_FEEDTHRU_1_SW4END1_1", - "INT_FEEDTHRU_1_SW4END1_2", - "INT_FEEDTHRU_1_SW4END1_3", - "INT_FEEDTHRU_1_SW4END1_4", - "INT_FEEDTHRU_1_SW4END1_5", - "INT_FEEDTHRU_1_SW4END1_6", - "INT_FEEDTHRU_1_SW4END1_7", - "INT_FEEDTHRU_1_SW4END1_8", - "INT_FEEDTHRU_1_SW4END1_9", - "INT_FEEDTHRU_1_SW4END2", - "INT_FEEDTHRU_1_SW4END2_1", - "INT_FEEDTHRU_1_SW4END2_2", - "INT_FEEDTHRU_1_SW4END2_3", - "INT_FEEDTHRU_1_SW4END2_4", - "INT_FEEDTHRU_1_SW4END2_5", - "INT_FEEDTHRU_1_SW4END2_6", - "INT_FEEDTHRU_1_SW4END2_7", - "INT_FEEDTHRU_1_SW4END2_8", - "INT_FEEDTHRU_1_SW4END2_9", - "INT_FEEDTHRU_1_SW4END3", - "INT_FEEDTHRU_1_SW4END3_1", - "INT_FEEDTHRU_1_SW4END3_2", - "INT_FEEDTHRU_1_SW4END3_3", - "INT_FEEDTHRU_1_SW4END3_4", - "INT_FEEDTHRU_1_SW4END3_5", - "INT_FEEDTHRU_1_SW4END3_6", - "INT_FEEDTHRU_1_SW4END3_7", - "INT_FEEDTHRU_1_SW4END3_8", - "INT_FEEDTHRU_1_SW4END3_9", - "INT_FEEDTHRU_1_WL1END0", - "INT_FEEDTHRU_1_WL1END0_1", - "INT_FEEDTHRU_1_WL1END0_2", - "INT_FEEDTHRU_1_WL1END0_3", - "INT_FEEDTHRU_1_WL1END0_4", - "INT_FEEDTHRU_1_WL1END0_5", - "INT_FEEDTHRU_1_WL1END0_6", - "INT_FEEDTHRU_1_WL1END0_7", - "INT_FEEDTHRU_1_WL1END0_8", - "INT_FEEDTHRU_1_WL1END0_9", - "INT_FEEDTHRU_1_WL1END1", - "INT_FEEDTHRU_1_WL1END1_1", - "INT_FEEDTHRU_1_WL1END1_2", - "INT_FEEDTHRU_1_WL1END1_3", - "INT_FEEDTHRU_1_WL1END1_4", - "INT_FEEDTHRU_1_WL1END1_5", - "INT_FEEDTHRU_1_WL1END1_6", - "INT_FEEDTHRU_1_WL1END1_7", - "INT_FEEDTHRU_1_WL1END1_8", - "INT_FEEDTHRU_1_WL1END1_9", - "INT_FEEDTHRU_1_WL1END2", - "INT_FEEDTHRU_1_WL1END2_1", - "INT_FEEDTHRU_1_WL1END2_2", - "INT_FEEDTHRU_1_WL1END2_3", - "INT_FEEDTHRU_1_WL1END2_4", - "INT_FEEDTHRU_1_WL1END2_5", - "INT_FEEDTHRU_1_WL1END2_6", - "INT_FEEDTHRU_1_WL1END2_7", - "INT_FEEDTHRU_1_WL1END2_8", - "INT_FEEDTHRU_1_WL1END2_9", - "INT_FEEDTHRU_1_WL1END3", - "INT_FEEDTHRU_1_WL1END3_1", - "INT_FEEDTHRU_1_WL1END3_2", - "INT_FEEDTHRU_1_WL1END3_3", - "INT_FEEDTHRU_1_WL1END3_4", - "INT_FEEDTHRU_1_WL1END3_5", - "INT_FEEDTHRU_1_WL1END3_6", - "INT_FEEDTHRU_1_WL1END3_7", - "INT_FEEDTHRU_1_WL1END3_8", - "INT_FEEDTHRU_1_WL1END3_9", - "INT_FEEDTHRU_1_WR1END0", - "INT_FEEDTHRU_1_WR1END0_1", - "INT_FEEDTHRU_1_WR1END0_2", - "INT_FEEDTHRU_1_WR1END0_3", - "INT_FEEDTHRU_1_WR1END0_4", - "INT_FEEDTHRU_1_WR1END0_5", - "INT_FEEDTHRU_1_WR1END0_6", - "INT_FEEDTHRU_1_WR1END0_7", - "INT_FEEDTHRU_1_WR1END0_8", - "INT_FEEDTHRU_1_WR1END0_9", - "INT_FEEDTHRU_1_WR1END1", - "INT_FEEDTHRU_1_WR1END1_1", - "INT_FEEDTHRU_1_WR1END1_2", - "INT_FEEDTHRU_1_WR1END1_3", - "INT_FEEDTHRU_1_WR1END1_4", - "INT_FEEDTHRU_1_WR1END1_5", - "INT_FEEDTHRU_1_WR1END1_6", - "INT_FEEDTHRU_1_WR1END1_7", - "INT_FEEDTHRU_1_WR1END1_8", - "INT_FEEDTHRU_1_WR1END1_9", - "INT_FEEDTHRU_1_WR1END2", - "INT_FEEDTHRU_1_WR1END2_1", - "INT_FEEDTHRU_1_WR1END2_2", - "INT_FEEDTHRU_1_WR1END2_3", - "INT_FEEDTHRU_1_WR1END2_4", - "INT_FEEDTHRU_1_WR1END2_5", - "INT_FEEDTHRU_1_WR1END2_6", - "INT_FEEDTHRU_1_WR1END2_7", - "INT_FEEDTHRU_1_WR1END2_8", - "INT_FEEDTHRU_1_WR1END2_9", - "INT_FEEDTHRU_1_WR1END3", - "INT_FEEDTHRU_1_WR1END3_1", - "INT_FEEDTHRU_1_WR1END3_2", - "INT_FEEDTHRU_1_WR1END3_3", - "INT_FEEDTHRU_1_WR1END3_4", - "INT_FEEDTHRU_1_WR1END3_5", - "INT_FEEDTHRU_1_WR1END3_6", - "INT_FEEDTHRU_1_WR1END3_7", - "INT_FEEDTHRU_1_WR1END3_8", - "INT_FEEDTHRU_1_WR1END3_9", - "INT_FEEDTHRU_1_WW2A0", - "INT_FEEDTHRU_1_WW2A0_1", - "INT_FEEDTHRU_1_WW2A0_2", - "INT_FEEDTHRU_1_WW2A0_3", - "INT_FEEDTHRU_1_WW2A0_4", - "INT_FEEDTHRU_1_WW2A0_5", - "INT_FEEDTHRU_1_WW2A0_6", - "INT_FEEDTHRU_1_WW2A0_7", - "INT_FEEDTHRU_1_WW2A0_8", - "INT_FEEDTHRU_1_WW2A0_9", - "INT_FEEDTHRU_1_WW2A1", - "INT_FEEDTHRU_1_WW2A1_1", - "INT_FEEDTHRU_1_WW2A1_2", - "INT_FEEDTHRU_1_WW2A1_3", - "INT_FEEDTHRU_1_WW2A1_4", - "INT_FEEDTHRU_1_WW2A1_5", - "INT_FEEDTHRU_1_WW2A1_6", - "INT_FEEDTHRU_1_WW2A1_7", - "INT_FEEDTHRU_1_WW2A1_8", - "INT_FEEDTHRU_1_WW2A1_9", - "INT_FEEDTHRU_1_WW2A2", - "INT_FEEDTHRU_1_WW2A2_1", - "INT_FEEDTHRU_1_WW2A2_2", - "INT_FEEDTHRU_1_WW2A2_3", - "INT_FEEDTHRU_1_WW2A2_4", - "INT_FEEDTHRU_1_WW2A2_5", - "INT_FEEDTHRU_1_WW2A2_6", - "INT_FEEDTHRU_1_WW2A2_7", - "INT_FEEDTHRU_1_WW2A2_8", - "INT_FEEDTHRU_1_WW2A2_9", - "INT_FEEDTHRU_1_WW2A3", - "INT_FEEDTHRU_1_WW2A3_1", - "INT_FEEDTHRU_1_WW2A3_2", - "INT_FEEDTHRU_1_WW2A3_3", - "INT_FEEDTHRU_1_WW2A3_4", - "INT_FEEDTHRU_1_WW2A3_5", - "INT_FEEDTHRU_1_WW2A3_6", - "INT_FEEDTHRU_1_WW2A3_7", - "INT_FEEDTHRU_1_WW2A3_8", - "INT_FEEDTHRU_1_WW2A3_9", - "INT_FEEDTHRU_1_WW2END0", - "INT_FEEDTHRU_1_WW2END0_1", - "INT_FEEDTHRU_1_WW2END0_2", - "INT_FEEDTHRU_1_WW2END0_3", - "INT_FEEDTHRU_1_WW2END0_4", - "INT_FEEDTHRU_1_WW2END0_5", - "INT_FEEDTHRU_1_WW2END0_6", - "INT_FEEDTHRU_1_WW2END0_7", - "INT_FEEDTHRU_1_WW2END0_8", - "INT_FEEDTHRU_1_WW2END0_9", - "INT_FEEDTHRU_1_WW2END1", - "INT_FEEDTHRU_1_WW2END1_1", - "INT_FEEDTHRU_1_WW2END1_2", - "INT_FEEDTHRU_1_WW2END1_3", - "INT_FEEDTHRU_1_WW2END1_4", - "INT_FEEDTHRU_1_WW2END1_5", - "INT_FEEDTHRU_1_WW2END1_6", - "INT_FEEDTHRU_1_WW2END1_7", - "INT_FEEDTHRU_1_WW2END1_8", - "INT_FEEDTHRU_1_WW2END1_9", - "INT_FEEDTHRU_1_WW2END2", - "INT_FEEDTHRU_1_WW2END2_1", - "INT_FEEDTHRU_1_WW2END2_2", - "INT_FEEDTHRU_1_WW2END2_3", - "INT_FEEDTHRU_1_WW2END2_4", - "INT_FEEDTHRU_1_WW2END2_5", - "INT_FEEDTHRU_1_WW2END2_6", - "INT_FEEDTHRU_1_WW2END2_7", - "INT_FEEDTHRU_1_WW2END2_8", - "INT_FEEDTHRU_1_WW2END2_9", - "INT_FEEDTHRU_1_WW2END3", - "INT_FEEDTHRU_1_WW2END3_1", - "INT_FEEDTHRU_1_WW2END3_2", - "INT_FEEDTHRU_1_WW2END3_3", - "INT_FEEDTHRU_1_WW2END3_4", - "INT_FEEDTHRU_1_WW2END3_5", - "INT_FEEDTHRU_1_WW2END3_6", - "INT_FEEDTHRU_1_WW2END3_7", - "INT_FEEDTHRU_1_WW2END3_8", - "INT_FEEDTHRU_1_WW2END3_9", - "INT_FEEDTHRU_1_WW4A0", - "INT_FEEDTHRU_1_WW4A0_1", - "INT_FEEDTHRU_1_WW4A0_2", - "INT_FEEDTHRU_1_WW4A0_3", - "INT_FEEDTHRU_1_WW4A0_4", - "INT_FEEDTHRU_1_WW4A0_5", - "INT_FEEDTHRU_1_WW4A0_6", - "INT_FEEDTHRU_1_WW4A0_7", - "INT_FEEDTHRU_1_WW4A0_8", - "INT_FEEDTHRU_1_WW4A0_9", - "INT_FEEDTHRU_1_WW4A1", - "INT_FEEDTHRU_1_WW4A1_1", - "INT_FEEDTHRU_1_WW4A1_2", - "INT_FEEDTHRU_1_WW4A1_3", - "INT_FEEDTHRU_1_WW4A1_4", - "INT_FEEDTHRU_1_WW4A1_5", - "INT_FEEDTHRU_1_WW4A1_6", - "INT_FEEDTHRU_1_WW4A1_7", - "INT_FEEDTHRU_1_WW4A1_8", - "INT_FEEDTHRU_1_WW4A1_9", - "INT_FEEDTHRU_1_WW4A2", - "INT_FEEDTHRU_1_WW4A2_1", - "INT_FEEDTHRU_1_WW4A2_2", - "INT_FEEDTHRU_1_WW4A2_3", - "INT_FEEDTHRU_1_WW4A2_4", - "INT_FEEDTHRU_1_WW4A2_5", - "INT_FEEDTHRU_1_WW4A2_6", - "INT_FEEDTHRU_1_WW4A2_7", - "INT_FEEDTHRU_1_WW4A2_8", - "INT_FEEDTHRU_1_WW4A2_9", - "INT_FEEDTHRU_1_WW4A3", - "INT_FEEDTHRU_1_WW4A3_1", - "INT_FEEDTHRU_1_WW4A3_2", - "INT_FEEDTHRU_1_WW4A3_3", - "INT_FEEDTHRU_1_WW4A3_4", - "INT_FEEDTHRU_1_WW4A3_5", - "INT_FEEDTHRU_1_WW4A3_6", - "INT_FEEDTHRU_1_WW4A3_7", - "INT_FEEDTHRU_1_WW4A3_8", - "INT_FEEDTHRU_1_WW4A3_9", - "INT_FEEDTHRU_1_WW4B0", - "INT_FEEDTHRU_1_WW4B0_1", - "INT_FEEDTHRU_1_WW4B0_2", - "INT_FEEDTHRU_1_WW4B0_3", - "INT_FEEDTHRU_1_WW4B0_4", - "INT_FEEDTHRU_1_WW4B0_5", - "INT_FEEDTHRU_1_WW4B0_6", - "INT_FEEDTHRU_1_WW4B0_7", - "INT_FEEDTHRU_1_WW4B0_8", - "INT_FEEDTHRU_1_WW4B0_9", - "INT_FEEDTHRU_1_WW4B1", - "INT_FEEDTHRU_1_WW4B1_1", - "INT_FEEDTHRU_1_WW4B1_2", - "INT_FEEDTHRU_1_WW4B1_3", - "INT_FEEDTHRU_1_WW4B1_4", - "INT_FEEDTHRU_1_WW4B1_5", - "INT_FEEDTHRU_1_WW4B1_6", - "INT_FEEDTHRU_1_WW4B1_7", - "INT_FEEDTHRU_1_WW4B1_8", - "INT_FEEDTHRU_1_WW4B1_9", - "INT_FEEDTHRU_1_WW4B2", - "INT_FEEDTHRU_1_WW4B2_1", - "INT_FEEDTHRU_1_WW4B2_2", - "INT_FEEDTHRU_1_WW4B2_3", - "INT_FEEDTHRU_1_WW4B2_4", - "INT_FEEDTHRU_1_WW4B2_5", - "INT_FEEDTHRU_1_WW4B2_6", - "INT_FEEDTHRU_1_WW4B2_7", - "INT_FEEDTHRU_1_WW4B2_8", - "INT_FEEDTHRU_1_WW4B2_9", - "INT_FEEDTHRU_1_WW4B3", - "INT_FEEDTHRU_1_WW4B3_1", - "INT_FEEDTHRU_1_WW4B3_2", - "INT_FEEDTHRU_1_WW4B3_3", - "INT_FEEDTHRU_1_WW4B3_4", - "INT_FEEDTHRU_1_WW4B3_5", - "INT_FEEDTHRU_1_WW4B3_6", - "INT_FEEDTHRU_1_WW4B3_7", - "INT_FEEDTHRU_1_WW4B3_8", - "INT_FEEDTHRU_1_WW4B3_9", - "INT_FEEDTHRU_1_WW4C0", - "INT_FEEDTHRU_1_WW4C0_1", - "INT_FEEDTHRU_1_WW4C0_2", - "INT_FEEDTHRU_1_WW4C0_3", - "INT_FEEDTHRU_1_WW4C0_4", - "INT_FEEDTHRU_1_WW4C0_5", - "INT_FEEDTHRU_1_WW4C0_6", - "INT_FEEDTHRU_1_WW4C0_7", - "INT_FEEDTHRU_1_WW4C0_8", - "INT_FEEDTHRU_1_WW4C0_9", - "INT_FEEDTHRU_1_WW4C1", - "INT_FEEDTHRU_1_WW4C1_1", - "INT_FEEDTHRU_1_WW4C1_2", - "INT_FEEDTHRU_1_WW4C1_3", - "INT_FEEDTHRU_1_WW4C1_4", - "INT_FEEDTHRU_1_WW4C1_5", - "INT_FEEDTHRU_1_WW4C1_6", - "INT_FEEDTHRU_1_WW4C1_7", - "INT_FEEDTHRU_1_WW4C1_8", - "INT_FEEDTHRU_1_WW4C1_9", - "INT_FEEDTHRU_1_WW4C2", - "INT_FEEDTHRU_1_WW4C2_1", - "INT_FEEDTHRU_1_WW4C2_2", - "INT_FEEDTHRU_1_WW4C2_3", - "INT_FEEDTHRU_1_WW4C2_4", - "INT_FEEDTHRU_1_WW4C2_5", - "INT_FEEDTHRU_1_WW4C2_6", - "INT_FEEDTHRU_1_WW4C2_7", - "INT_FEEDTHRU_1_WW4C2_8", - "INT_FEEDTHRU_1_WW4C2_9", - "INT_FEEDTHRU_1_WW4C3", - "INT_FEEDTHRU_1_WW4C3_1", - "INT_FEEDTHRU_1_WW4C3_2", - "INT_FEEDTHRU_1_WW4C3_3", - "INT_FEEDTHRU_1_WW4C3_4", - "INT_FEEDTHRU_1_WW4C3_5", - "INT_FEEDTHRU_1_WW4C3_6", - "INT_FEEDTHRU_1_WW4C3_7", - "INT_FEEDTHRU_1_WW4C3_8", - "INT_FEEDTHRU_1_WW4C3_9", - "INT_FEEDTHRU_1_WW4END0", - "INT_FEEDTHRU_1_WW4END0_1", - "INT_FEEDTHRU_1_WW4END0_2", - "INT_FEEDTHRU_1_WW4END0_3", - "INT_FEEDTHRU_1_WW4END0_4", - "INT_FEEDTHRU_1_WW4END0_5", - "INT_FEEDTHRU_1_WW4END0_6", - "INT_FEEDTHRU_1_WW4END0_7", - "INT_FEEDTHRU_1_WW4END0_8", - "INT_FEEDTHRU_1_WW4END0_9", - "INT_FEEDTHRU_1_WW4END1", - "INT_FEEDTHRU_1_WW4END1_1", - "INT_FEEDTHRU_1_WW4END1_2", - "INT_FEEDTHRU_1_WW4END1_3", - "INT_FEEDTHRU_1_WW4END1_4", - "INT_FEEDTHRU_1_WW4END1_5", - "INT_FEEDTHRU_1_WW4END1_6", - "INT_FEEDTHRU_1_WW4END1_7", - "INT_FEEDTHRU_1_WW4END1_8", - "INT_FEEDTHRU_1_WW4END1_9", - "INT_FEEDTHRU_1_WW4END2", - "INT_FEEDTHRU_1_WW4END2_1", - "INT_FEEDTHRU_1_WW4END2_2", - "INT_FEEDTHRU_1_WW4END2_3", - "INT_FEEDTHRU_1_WW4END2_4", - "INT_FEEDTHRU_1_WW4END2_5", - "INT_FEEDTHRU_1_WW4END2_6", - "INT_FEEDTHRU_1_WW4END2_7", - "INT_FEEDTHRU_1_WW4END2_8", - "INT_FEEDTHRU_1_WW4END2_9", - "INT_FEEDTHRU_1_WW4END3", - "INT_FEEDTHRU_1_WW4END3_1", - "INT_FEEDTHRU_1_WW4END3_2", - "INT_FEEDTHRU_1_WW4END3_3", - "INT_FEEDTHRU_1_WW4END3_4", - "INT_FEEDTHRU_1_WW4END3_5", - "INT_FEEDTHRU_1_WW4END3_6", - "INT_FEEDTHRU_1_WW4END3_7", - "INT_FEEDTHRU_1_WW4END3_8", - "INT_FEEDTHRU_1_WW4END3_9", - "MONITOR_HORIZ_VAUXN14", - "MONITOR_HORIZ_VAUXN15", - "MONITOR_HORIZ_VAUXN6", - "MONITOR_HORIZ_VAUXN7", - "MONITOR_HORIZ_VAUXP14", - "MONITOR_HORIZ_VAUXP15", - "MONITOR_HORIZ_VAUXP6", - "MONITOR_HORIZ_VAUXP7", - "MONITOR_VERT_VAUXN0", - "MONITOR_VERT_VAUXN1", - "MONITOR_VERT_VAUXN10", - "MONITOR_VERT_VAUXN11", - "MONITOR_VERT_VAUXN12", - "MONITOR_VERT_VAUXN13", - "MONITOR_VERT_VAUXN14", - "MONITOR_VERT_VAUXN15", - "MONITOR_VERT_VAUXN2", - "MONITOR_VERT_VAUXN3", - "MONITOR_VERT_VAUXN4", - "MONITOR_VERT_VAUXN5", - "MONITOR_VERT_VAUXN6", - "MONITOR_VERT_VAUXN7", - "MONITOR_VERT_VAUXN8", - "MONITOR_VERT_VAUXN9", - "MONITOR_VERT_VAUXP0", - "MONITOR_VERT_VAUXP1", - "MONITOR_VERT_VAUXP10", - "MONITOR_VERT_VAUXP11", - "MONITOR_VERT_VAUXP12", - "MONITOR_VERT_VAUXP13", - "MONITOR_VERT_VAUXP14", - "MONITOR_VERT_VAUXP15", - "MONITOR_VERT_VAUXP2", - "MONITOR_VERT_VAUXP3", - "MONITOR_VERT_VAUXP4", - "MONITOR_VERT_VAUXP5", - "MONITOR_VERT_VAUXP6", - "MONITOR_VERT_VAUXP7", - "MONITOR_VERT_VAUXP8", - "MONITOR_VERT_VAUXP9" - ] + "wires": { + "INT_FEEDTHRU_1_EE2A0": null, + "INT_FEEDTHRU_1_EE2A0_1": null, + "INT_FEEDTHRU_1_EE2A0_2": null, + "INT_FEEDTHRU_1_EE2A0_3": null, + "INT_FEEDTHRU_1_EE2A0_4": null, + "INT_FEEDTHRU_1_EE2A0_5": null, + "INT_FEEDTHRU_1_EE2A0_6": null, + "INT_FEEDTHRU_1_EE2A0_7": null, + "INT_FEEDTHRU_1_EE2A0_8": null, + "INT_FEEDTHRU_1_EE2A0_9": null, + "INT_FEEDTHRU_1_EE2A1": null, + "INT_FEEDTHRU_1_EE2A1_1": null, + "INT_FEEDTHRU_1_EE2A1_2": null, + "INT_FEEDTHRU_1_EE2A1_3": null, + "INT_FEEDTHRU_1_EE2A1_4": null, + "INT_FEEDTHRU_1_EE2A1_5": null, + "INT_FEEDTHRU_1_EE2A1_6": null, + "INT_FEEDTHRU_1_EE2A1_7": null, + "INT_FEEDTHRU_1_EE2A1_8": null, + "INT_FEEDTHRU_1_EE2A1_9": null, + "INT_FEEDTHRU_1_EE2A2": null, + "INT_FEEDTHRU_1_EE2A2_1": null, + "INT_FEEDTHRU_1_EE2A2_2": null, + "INT_FEEDTHRU_1_EE2A2_3": null, + "INT_FEEDTHRU_1_EE2A2_4": null, + "INT_FEEDTHRU_1_EE2A2_5": null, + "INT_FEEDTHRU_1_EE2A2_6": null, + "INT_FEEDTHRU_1_EE2A2_7": null, + "INT_FEEDTHRU_1_EE2A2_8": null, + "INT_FEEDTHRU_1_EE2A2_9": null, + "INT_FEEDTHRU_1_EE2A3": null, + "INT_FEEDTHRU_1_EE2A3_1": null, + "INT_FEEDTHRU_1_EE2A3_2": null, + "INT_FEEDTHRU_1_EE2A3_3": null, + "INT_FEEDTHRU_1_EE2A3_4": null, + "INT_FEEDTHRU_1_EE2A3_5": null, + "INT_FEEDTHRU_1_EE2A3_6": null, + "INT_FEEDTHRU_1_EE2A3_7": null, + "INT_FEEDTHRU_1_EE2A3_8": null, + "INT_FEEDTHRU_1_EE2A3_9": null, + "INT_FEEDTHRU_1_EE2BEG0": null, + "INT_FEEDTHRU_1_EE2BEG0_1": null, + "INT_FEEDTHRU_1_EE2BEG0_2": null, + "INT_FEEDTHRU_1_EE2BEG0_3": null, + "INT_FEEDTHRU_1_EE2BEG0_4": null, + "INT_FEEDTHRU_1_EE2BEG0_5": null, + "INT_FEEDTHRU_1_EE2BEG0_6": null, + "INT_FEEDTHRU_1_EE2BEG0_7": null, + "INT_FEEDTHRU_1_EE2BEG0_8": null, + "INT_FEEDTHRU_1_EE2BEG0_9": null, + "INT_FEEDTHRU_1_EE2BEG1": null, + "INT_FEEDTHRU_1_EE2BEG1_1": null, + "INT_FEEDTHRU_1_EE2BEG1_2": null, + "INT_FEEDTHRU_1_EE2BEG1_3": null, + "INT_FEEDTHRU_1_EE2BEG1_4": null, + "INT_FEEDTHRU_1_EE2BEG1_5": null, + "INT_FEEDTHRU_1_EE2BEG1_6": null, + "INT_FEEDTHRU_1_EE2BEG1_7": null, + "INT_FEEDTHRU_1_EE2BEG1_8": null, + "INT_FEEDTHRU_1_EE2BEG1_9": null, + "INT_FEEDTHRU_1_EE2BEG2": null, + "INT_FEEDTHRU_1_EE2BEG2_1": null, + "INT_FEEDTHRU_1_EE2BEG2_2": null, + "INT_FEEDTHRU_1_EE2BEG2_3": null, + "INT_FEEDTHRU_1_EE2BEG2_4": null, + "INT_FEEDTHRU_1_EE2BEG2_5": null, + "INT_FEEDTHRU_1_EE2BEG2_6": null, + "INT_FEEDTHRU_1_EE2BEG2_7": null, + "INT_FEEDTHRU_1_EE2BEG2_8": null, + "INT_FEEDTHRU_1_EE2BEG2_9": null, + "INT_FEEDTHRU_1_EE2BEG3": null, + "INT_FEEDTHRU_1_EE2BEG3_1": null, + "INT_FEEDTHRU_1_EE2BEG3_2": null, + "INT_FEEDTHRU_1_EE2BEG3_3": null, + "INT_FEEDTHRU_1_EE2BEG3_4": null, + "INT_FEEDTHRU_1_EE2BEG3_5": null, + "INT_FEEDTHRU_1_EE2BEG3_6": null, + "INT_FEEDTHRU_1_EE2BEG3_7": null, + "INT_FEEDTHRU_1_EE2BEG3_8": null, + "INT_FEEDTHRU_1_EE2BEG3_9": null, + "INT_FEEDTHRU_1_EE4A0": null, + "INT_FEEDTHRU_1_EE4A0_1": null, + "INT_FEEDTHRU_1_EE4A0_2": null, + "INT_FEEDTHRU_1_EE4A0_3": null, + "INT_FEEDTHRU_1_EE4A0_4": null, + "INT_FEEDTHRU_1_EE4A0_5": null, + "INT_FEEDTHRU_1_EE4A0_6": null, + "INT_FEEDTHRU_1_EE4A0_7": null, + "INT_FEEDTHRU_1_EE4A0_8": null, + "INT_FEEDTHRU_1_EE4A0_9": null, + "INT_FEEDTHRU_1_EE4A1": null, + "INT_FEEDTHRU_1_EE4A1_1": null, + "INT_FEEDTHRU_1_EE4A1_2": null, + "INT_FEEDTHRU_1_EE4A1_3": null, + "INT_FEEDTHRU_1_EE4A1_4": null, + "INT_FEEDTHRU_1_EE4A1_5": null, + "INT_FEEDTHRU_1_EE4A1_6": null, + "INT_FEEDTHRU_1_EE4A1_7": null, + "INT_FEEDTHRU_1_EE4A1_8": null, + "INT_FEEDTHRU_1_EE4A1_9": null, + "INT_FEEDTHRU_1_EE4A2": null, + "INT_FEEDTHRU_1_EE4A2_1": null, + "INT_FEEDTHRU_1_EE4A2_2": null, + "INT_FEEDTHRU_1_EE4A2_3": null, + "INT_FEEDTHRU_1_EE4A2_4": null, + "INT_FEEDTHRU_1_EE4A2_5": null, + "INT_FEEDTHRU_1_EE4A2_6": null, + "INT_FEEDTHRU_1_EE4A2_7": null, + "INT_FEEDTHRU_1_EE4A2_8": null, + "INT_FEEDTHRU_1_EE4A2_9": null, + "INT_FEEDTHRU_1_EE4A3": null, + "INT_FEEDTHRU_1_EE4A3_1": null, + "INT_FEEDTHRU_1_EE4A3_2": null, + "INT_FEEDTHRU_1_EE4A3_3": null, + "INT_FEEDTHRU_1_EE4A3_4": null, + "INT_FEEDTHRU_1_EE4A3_5": null, + "INT_FEEDTHRU_1_EE4A3_6": null, + "INT_FEEDTHRU_1_EE4A3_7": null, + "INT_FEEDTHRU_1_EE4A3_8": null, + "INT_FEEDTHRU_1_EE4A3_9": null, + "INT_FEEDTHRU_1_EE4B0": null, + "INT_FEEDTHRU_1_EE4B0_1": null, + "INT_FEEDTHRU_1_EE4B0_2": null, + "INT_FEEDTHRU_1_EE4B0_3": null, + "INT_FEEDTHRU_1_EE4B0_4": null, + "INT_FEEDTHRU_1_EE4B0_5": null, + "INT_FEEDTHRU_1_EE4B0_6": null, + "INT_FEEDTHRU_1_EE4B0_7": null, + "INT_FEEDTHRU_1_EE4B0_8": null, + "INT_FEEDTHRU_1_EE4B0_9": null, + "INT_FEEDTHRU_1_EE4B1": null, + "INT_FEEDTHRU_1_EE4B1_1": null, + "INT_FEEDTHRU_1_EE4B1_2": null, + "INT_FEEDTHRU_1_EE4B1_3": null, + "INT_FEEDTHRU_1_EE4B1_4": null, + "INT_FEEDTHRU_1_EE4B1_5": null, + "INT_FEEDTHRU_1_EE4B1_6": null, + "INT_FEEDTHRU_1_EE4B1_7": null, + "INT_FEEDTHRU_1_EE4B1_8": null, + "INT_FEEDTHRU_1_EE4B1_9": null, + "INT_FEEDTHRU_1_EE4B2": null, + "INT_FEEDTHRU_1_EE4B2_1": null, + "INT_FEEDTHRU_1_EE4B2_2": null, + "INT_FEEDTHRU_1_EE4B2_3": null, + "INT_FEEDTHRU_1_EE4B2_4": null, + "INT_FEEDTHRU_1_EE4B2_5": null, + "INT_FEEDTHRU_1_EE4B2_6": null, + "INT_FEEDTHRU_1_EE4B2_7": null, + "INT_FEEDTHRU_1_EE4B2_8": null, + "INT_FEEDTHRU_1_EE4B2_9": null, + "INT_FEEDTHRU_1_EE4B3": null, + "INT_FEEDTHRU_1_EE4B3_1": null, + "INT_FEEDTHRU_1_EE4B3_2": null, + "INT_FEEDTHRU_1_EE4B3_3": null, + "INT_FEEDTHRU_1_EE4B3_4": null, + "INT_FEEDTHRU_1_EE4B3_5": null, + "INT_FEEDTHRU_1_EE4B3_6": null, + "INT_FEEDTHRU_1_EE4B3_7": null, + "INT_FEEDTHRU_1_EE4B3_8": null, + "INT_FEEDTHRU_1_EE4B3_9": null, + "INT_FEEDTHRU_1_EE4BEG0": null, + "INT_FEEDTHRU_1_EE4BEG0_1": null, + "INT_FEEDTHRU_1_EE4BEG0_2": null, + "INT_FEEDTHRU_1_EE4BEG0_3": null, + "INT_FEEDTHRU_1_EE4BEG0_4": null, + "INT_FEEDTHRU_1_EE4BEG0_5": null, + "INT_FEEDTHRU_1_EE4BEG0_6": null, + "INT_FEEDTHRU_1_EE4BEG0_7": null, + "INT_FEEDTHRU_1_EE4BEG0_8": null, + "INT_FEEDTHRU_1_EE4BEG0_9": null, + "INT_FEEDTHRU_1_EE4BEG1": null, + "INT_FEEDTHRU_1_EE4BEG1_1": null, + "INT_FEEDTHRU_1_EE4BEG1_2": null, + "INT_FEEDTHRU_1_EE4BEG1_3": null, + "INT_FEEDTHRU_1_EE4BEG1_4": null, + "INT_FEEDTHRU_1_EE4BEG1_5": null, + "INT_FEEDTHRU_1_EE4BEG1_6": null, + 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"MONITOR_VERT_VAUXN15": null, + "MONITOR_VERT_VAUXN2": null, + "MONITOR_VERT_VAUXN3": null, + "MONITOR_VERT_VAUXN4": null, + "MONITOR_VERT_VAUXN5": null, + "MONITOR_VERT_VAUXN6": null, + "MONITOR_VERT_VAUXN7": null, + "MONITOR_VERT_VAUXN8": null, + "MONITOR_VERT_VAUXN9": null, + "MONITOR_VERT_VAUXP0": null, + "MONITOR_VERT_VAUXP1": null, + "MONITOR_VERT_VAUXP10": null, + "MONITOR_VERT_VAUXP11": null, + "MONITOR_VERT_VAUXP12": null, + "MONITOR_VERT_VAUXP13": null, + "MONITOR_VERT_VAUXP14": null, + "MONITOR_VERT_VAUXP15": null, + "MONITOR_VERT_VAUXP2": null, + "MONITOR_VERT_VAUXP3": null, + "MONITOR_VERT_VAUXP4": null, + "MONITOR_VERT_VAUXP5": null, + "MONITOR_VERT_VAUXP6": null, + "MONITOR_VERT_VAUXP7": null, + "MONITOR_VERT_VAUXP8": null, + "MONITOR_VERT_VAUXP9": null + } } diff --git a/zynq7/tile_type_CFG_SECURITY_MID_PELE1.json b/zynq7/tile_type_CFG_SECURITY_MID_PELE1.json index 6ae5efa..2985807 100644 --- a/zynq7/tile_type_CFG_SECURITY_MID_PELE1.json +++ b/zynq7/tile_type_CFG_SECURITY_MID_PELE1.json @@ -2,1341 +2,1407 @@ "pips": { "CFG_SECURITY_MID_PELE1.MONITOR_HORIZ_VAUXN12->MONITOR_VERT_VAUXN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN12" }, "CFG_SECURITY_MID_PELE1.MONITOR_HORIZ_VAUXN13->MONITOR_VERT_VAUXN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN13" }, "CFG_SECURITY_MID_PELE1.MONITOR_HORIZ_VAUXN5->MONITOR_VERT_VAUXN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN5" }, "CFG_SECURITY_MID_PELE1.MONITOR_HORIZ_VAUXP12->MONITOR_VERT_VAUXP12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP12" }, "CFG_SECURITY_MID_PELE1.MONITOR_HORIZ_VAUXP13->MONITOR_VERT_VAUXP13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP13" }, "CFG_SECURITY_MID_PELE1.MONITOR_HORIZ_VAUXP5->MONITOR_VERT_VAUXP5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP5" } }, "sites": [], "tile_type": "CFG_SECURITY_MID_PELE1", - "wires": [ - "INT_FEEDTHRU_1_EE2A0", - "INT_FEEDTHRU_1_EE2A0_1", - "INT_FEEDTHRU_1_EE2A0_2", - "INT_FEEDTHRU_1_EE2A0_3", - "INT_FEEDTHRU_1_EE2A0_4", - "INT_FEEDTHRU_1_EE2A0_5", - "INT_FEEDTHRU_1_EE2A0_6", - "INT_FEEDTHRU_1_EE2A0_7", - "INT_FEEDTHRU_1_EE2A0_8", - "INT_FEEDTHRU_1_EE2A0_9", - "INT_FEEDTHRU_1_EE2A1", - "INT_FEEDTHRU_1_EE2A1_1", - "INT_FEEDTHRU_1_EE2A1_2", - "INT_FEEDTHRU_1_EE2A1_3", - "INT_FEEDTHRU_1_EE2A1_4", - "INT_FEEDTHRU_1_EE2A1_5", - "INT_FEEDTHRU_1_EE2A1_6", - "INT_FEEDTHRU_1_EE2A1_7", - "INT_FEEDTHRU_1_EE2A1_8", - "INT_FEEDTHRU_1_EE2A1_9", - "INT_FEEDTHRU_1_EE2A2", - "INT_FEEDTHRU_1_EE2A2_1", - "INT_FEEDTHRU_1_EE2A2_2", - "INT_FEEDTHRU_1_EE2A2_3", - "INT_FEEDTHRU_1_EE2A2_4", - "INT_FEEDTHRU_1_EE2A2_5", - "INT_FEEDTHRU_1_EE2A2_6", - "INT_FEEDTHRU_1_EE2A2_7", - "INT_FEEDTHRU_1_EE2A2_8", - "INT_FEEDTHRU_1_EE2A2_9", - "INT_FEEDTHRU_1_EE2A3", - "INT_FEEDTHRU_1_EE2A3_1", - "INT_FEEDTHRU_1_EE2A3_2", - "INT_FEEDTHRU_1_EE2A3_3", - "INT_FEEDTHRU_1_EE2A3_4", - "INT_FEEDTHRU_1_EE2A3_5", - "INT_FEEDTHRU_1_EE2A3_6", - "INT_FEEDTHRU_1_EE2A3_7", - "INT_FEEDTHRU_1_EE2A3_8", - "INT_FEEDTHRU_1_EE2A3_9", - "INT_FEEDTHRU_1_EE2BEG0", - "INT_FEEDTHRU_1_EE2BEG0_1", - "INT_FEEDTHRU_1_EE2BEG0_2", - "INT_FEEDTHRU_1_EE2BEG0_3", - "INT_FEEDTHRU_1_EE2BEG0_4", - "INT_FEEDTHRU_1_EE2BEG0_5", - "INT_FEEDTHRU_1_EE2BEG0_6", - "INT_FEEDTHRU_1_EE2BEG0_7", - "INT_FEEDTHRU_1_EE2BEG0_8", - "INT_FEEDTHRU_1_EE2BEG0_9", - "INT_FEEDTHRU_1_EE2BEG1", - "INT_FEEDTHRU_1_EE2BEG1_1", - "INT_FEEDTHRU_1_EE2BEG1_2", - "INT_FEEDTHRU_1_EE2BEG1_3", - "INT_FEEDTHRU_1_EE2BEG1_4", - "INT_FEEDTHRU_1_EE2BEG1_5", - "INT_FEEDTHRU_1_EE2BEG1_6", - "INT_FEEDTHRU_1_EE2BEG1_7", - "INT_FEEDTHRU_1_EE2BEG1_8", - "INT_FEEDTHRU_1_EE2BEG1_9", - "INT_FEEDTHRU_1_EE2BEG2", - "INT_FEEDTHRU_1_EE2BEG2_1", - "INT_FEEDTHRU_1_EE2BEG2_2", - "INT_FEEDTHRU_1_EE2BEG2_3", - "INT_FEEDTHRU_1_EE2BEG2_4", - "INT_FEEDTHRU_1_EE2BEG2_5", - "INT_FEEDTHRU_1_EE2BEG2_6", - "INT_FEEDTHRU_1_EE2BEG2_7", - "INT_FEEDTHRU_1_EE2BEG2_8", - "INT_FEEDTHRU_1_EE2BEG2_9", - "INT_FEEDTHRU_1_EE2BEG3", - "INT_FEEDTHRU_1_EE2BEG3_1", - "INT_FEEDTHRU_1_EE2BEG3_2", - "INT_FEEDTHRU_1_EE2BEG3_3", - "INT_FEEDTHRU_1_EE2BEG3_4", - "INT_FEEDTHRU_1_EE2BEG3_5", - "INT_FEEDTHRU_1_EE2BEG3_6", - "INT_FEEDTHRU_1_EE2BEG3_7", - "INT_FEEDTHRU_1_EE2BEG3_8", - "INT_FEEDTHRU_1_EE2BEG3_9", - "INT_FEEDTHRU_1_EE4A0", - "INT_FEEDTHRU_1_EE4A0_1", - "INT_FEEDTHRU_1_EE4A0_2", - "INT_FEEDTHRU_1_EE4A0_3", - "INT_FEEDTHRU_1_EE4A0_4", - "INT_FEEDTHRU_1_EE4A0_5", - "INT_FEEDTHRU_1_EE4A0_6", - "INT_FEEDTHRU_1_EE4A0_7", - "INT_FEEDTHRU_1_EE4A0_8", - "INT_FEEDTHRU_1_EE4A0_9", - "INT_FEEDTHRU_1_EE4A1", - "INT_FEEDTHRU_1_EE4A1_1", - "INT_FEEDTHRU_1_EE4A1_2", - "INT_FEEDTHRU_1_EE4A1_3", - "INT_FEEDTHRU_1_EE4A1_4", - "INT_FEEDTHRU_1_EE4A1_5", - "INT_FEEDTHRU_1_EE4A1_6", - "INT_FEEDTHRU_1_EE4A1_7", - "INT_FEEDTHRU_1_EE4A1_8", - "INT_FEEDTHRU_1_EE4A1_9", - "INT_FEEDTHRU_1_EE4A2", - "INT_FEEDTHRU_1_EE4A2_1", - "INT_FEEDTHRU_1_EE4A2_2", - "INT_FEEDTHRU_1_EE4A2_3", - "INT_FEEDTHRU_1_EE4A2_4", - "INT_FEEDTHRU_1_EE4A2_5", - "INT_FEEDTHRU_1_EE4A2_6", - "INT_FEEDTHRU_1_EE4A2_7", - "INT_FEEDTHRU_1_EE4A2_8", - "INT_FEEDTHRU_1_EE4A2_9", - "INT_FEEDTHRU_1_EE4A3", - "INT_FEEDTHRU_1_EE4A3_1", - "INT_FEEDTHRU_1_EE4A3_2", - "INT_FEEDTHRU_1_EE4A3_3", - "INT_FEEDTHRU_1_EE4A3_4", - "INT_FEEDTHRU_1_EE4A3_5", - "INT_FEEDTHRU_1_EE4A3_6", - "INT_FEEDTHRU_1_EE4A3_7", - "INT_FEEDTHRU_1_EE4A3_8", - "INT_FEEDTHRU_1_EE4A3_9", - "INT_FEEDTHRU_1_EE4B0", - "INT_FEEDTHRU_1_EE4B0_1", - "INT_FEEDTHRU_1_EE4B0_2", - "INT_FEEDTHRU_1_EE4B0_3", - "INT_FEEDTHRU_1_EE4B0_4", - "INT_FEEDTHRU_1_EE4B0_5", - "INT_FEEDTHRU_1_EE4B0_6", - "INT_FEEDTHRU_1_EE4B0_7", - "INT_FEEDTHRU_1_EE4B0_8", - "INT_FEEDTHRU_1_EE4B0_9", - "INT_FEEDTHRU_1_EE4B1", - "INT_FEEDTHRU_1_EE4B1_1", - "INT_FEEDTHRU_1_EE4B1_2", - "INT_FEEDTHRU_1_EE4B1_3", - "INT_FEEDTHRU_1_EE4B1_4", - "INT_FEEDTHRU_1_EE4B1_5", - "INT_FEEDTHRU_1_EE4B1_6", - "INT_FEEDTHRU_1_EE4B1_7", - "INT_FEEDTHRU_1_EE4B1_8", - "INT_FEEDTHRU_1_EE4B1_9", - "INT_FEEDTHRU_1_EE4B2", - "INT_FEEDTHRU_1_EE4B2_1", - "INT_FEEDTHRU_1_EE4B2_2", - "INT_FEEDTHRU_1_EE4B2_3", - "INT_FEEDTHRU_1_EE4B2_4", - "INT_FEEDTHRU_1_EE4B2_5", - "INT_FEEDTHRU_1_EE4B2_6", - "INT_FEEDTHRU_1_EE4B2_7", - "INT_FEEDTHRU_1_EE4B2_8", - "INT_FEEDTHRU_1_EE4B2_9", - "INT_FEEDTHRU_1_EE4B3", - "INT_FEEDTHRU_1_EE4B3_1", - "INT_FEEDTHRU_1_EE4B3_2", - "INT_FEEDTHRU_1_EE4B3_3", - "INT_FEEDTHRU_1_EE4B3_4", - "INT_FEEDTHRU_1_EE4B3_5", - "INT_FEEDTHRU_1_EE4B3_6", - "INT_FEEDTHRU_1_EE4B3_7", - "INT_FEEDTHRU_1_EE4B3_8", - "INT_FEEDTHRU_1_EE4B3_9", - "INT_FEEDTHRU_1_EE4BEG0", - "INT_FEEDTHRU_1_EE4BEG0_1", - "INT_FEEDTHRU_1_EE4BEG0_2", - "INT_FEEDTHRU_1_EE4BEG0_3", - "INT_FEEDTHRU_1_EE4BEG0_4", - "INT_FEEDTHRU_1_EE4BEG0_5", - "INT_FEEDTHRU_1_EE4BEG0_6", - "INT_FEEDTHRU_1_EE4BEG0_7", - "INT_FEEDTHRU_1_EE4BEG0_8", - "INT_FEEDTHRU_1_EE4BEG0_9", - "INT_FEEDTHRU_1_EE4BEG1", - "INT_FEEDTHRU_1_EE4BEG1_1", - "INT_FEEDTHRU_1_EE4BEG1_2", - "INT_FEEDTHRU_1_EE4BEG1_3", - "INT_FEEDTHRU_1_EE4BEG1_4", - "INT_FEEDTHRU_1_EE4BEG1_5", - "INT_FEEDTHRU_1_EE4BEG1_6", - "INT_FEEDTHRU_1_EE4BEG1_7", - "INT_FEEDTHRU_1_EE4BEG1_8", - "INT_FEEDTHRU_1_EE4BEG1_9", - "INT_FEEDTHRU_1_EE4BEG2", - "INT_FEEDTHRU_1_EE4BEG2_1", - "INT_FEEDTHRU_1_EE4BEG2_2", - "INT_FEEDTHRU_1_EE4BEG2_3", - "INT_FEEDTHRU_1_EE4BEG2_4", - "INT_FEEDTHRU_1_EE4BEG2_5", - "INT_FEEDTHRU_1_EE4BEG2_6", - "INT_FEEDTHRU_1_EE4BEG2_7", - "INT_FEEDTHRU_1_EE4BEG2_8", - "INT_FEEDTHRU_1_EE4BEG2_9", - "INT_FEEDTHRU_1_EE4BEG3", - "INT_FEEDTHRU_1_EE4BEG3_1", - "INT_FEEDTHRU_1_EE4BEG3_2", - "INT_FEEDTHRU_1_EE4BEG3_3", - "INT_FEEDTHRU_1_EE4BEG3_4", - "INT_FEEDTHRU_1_EE4BEG3_5", - "INT_FEEDTHRU_1_EE4BEG3_6", - "INT_FEEDTHRU_1_EE4BEG3_7", - "INT_FEEDTHRU_1_EE4BEG3_8", - "INT_FEEDTHRU_1_EE4BEG3_9", - "INT_FEEDTHRU_1_EE4C0", - "INT_FEEDTHRU_1_EE4C0_1", - "INT_FEEDTHRU_1_EE4C0_2", - "INT_FEEDTHRU_1_EE4C0_3", - "INT_FEEDTHRU_1_EE4C0_4", - "INT_FEEDTHRU_1_EE4C0_5", - "INT_FEEDTHRU_1_EE4C0_6", - "INT_FEEDTHRU_1_EE4C0_7", - "INT_FEEDTHRU_1_EE4C0_8", - "INT_FEEDTHRU_1_EE4C0_9", - "INT_FEEDTHRU_1_EE4C1", - "INT_FEEDTHRU_1_EE4C1_1", - "INT_FEEDTHRU_1_EE4C1_2", - "INT_FEEDTHRU_1_EE4C1_3", - "INT_FEEDTHRU_1_EE4C1_4", - "INT_FEEDTHRU_1_EE4C1_5", - "INT_FEEDTHRU_1_EE4C1_6", - "INT_FEEDTHRU_1_EE4C1_7", - "INT_FEEDTHRU_1_EE4C1_8", - "INT_FEEDTHRU_1_EE4C1_9", - "INT_FEEDTHRU_1_EE4C2", - "INT_FEEDTHRU_1_EE4C2_1", - "INT_FEEDTHRU_1_EE4C2_2", - "INT_FEEDTHRU_1_EE4C2_3", - "INT_FEEDTHRU_1_EE4C2_4", - "INT_FEEDTHRU_1_EE4C2_5", - "INT_FEEDTHRU_1_EE4C2_6", - "INT_FEEDTHRU_1_EE4C2_7", - "INT_FEEDTHRU_1_EE4C2_8", - "INT_FEEDTHRU_1_EE4C2_9", - "INT_FEEDTHRU_1_EE4C3", - "INT_FEEDTHRU_1_EE4C3_1", - "INT_FEEDTHRU_1_EE4C3_2", - "INT_FEEDTHRU_1_EE4C3_3", - "INT_FEEDTHRU_1_EE4C3_4", - "INT_FEEDTHRU_1_EE4C3_5", - "INT_FEEDTHRU_1_EE4C3_6", - "INT_FEEDTHRU_1_EE4C3_7", - "INT_FEEDTHRU_1_EE4C3_8", - "INT_FEEDTHRU_1_EE4C3_9", - "INT_FEEDTHRU_1_EL1BEG0", - "INT_FEEDTHRU_1_EL1BEG0_1", - "INT_FEEDTHRU_1_EL1BEG0_2", - "INT_FEEDTHRU_1_EL1BEG0_3", - "INT_FEEDTHRU_1_EL1BEG0_4", - "INT_FEEDTHRU_1_EL1BEG0_5", - "INT_FEEDTHRU_1_EL1BEG0_6", - "INT_FEEDTHRU_1_EL1BEG0_7", - "INT_FEEDTHRU_1_EL1BEG0_8", - "INT_FEEDTHRU_1_EL1BEG0_9", - "INT_FEEDTHRU_1_EL1BEG1", - "INT_FEEDTHRU_1_EL1BEG1_1", - "INT_FEEDTHRU_1_EL1BEG1_2", - "INT_FEEDTHRU_1_EL1BEG1_3", - "INT_FEEDTHRU_1_EL1BEG1_4", - "INT_FEEDTHRU_1_EL1BEG1_5", - "INT_FEEDTHRU_1_EL1BEG1_6", - "INT_FEEDTHRU_1_EL1BEG1_7", - "INT_FEEDTHRU_1_EL1BEG1_8", - "INT_FEEDTHRU_1_EL1BEG1_9", - "INT_FEEDTHRU_1_EL1BEG2", - "INT_FEEDTHRU_1_EL1BEG2_1", - "INT_FEEDTHRU_1_EL1BEG2_2", - "INT_FEEDTHRU_1_EL1BEG2_3", - "INT_FEEDTHRU_1_EL1BEG2_4", - "INT_FEEDTHRU_1_EL1BEG2_5", - "INT_FEEDTHRU_1_EL1BEG2_6", - "INT_FEEDTHRU_1_EL1BEG2_7", - "INT_FEEDTHRU_1_EL1BEG2_8", - "INT_FEEDTHRU_1_EL1BEG2_9", - "INT_FEEDTHRU_1_EL1BEG3", - "INT_FEEDTHRU_1_EL1BEG3_1", - "INT_FEEDTHRU_1_EL1BEG3_2", - "INT_FEEDTHRU_1_EL1BEG3_3", - "INT_FEEDTHRU_1_EL1BEG3_4", - "INT_FEEDTHRU_1_EL1BEG3_5", - "INT_FEEDTHRU_1_EL1BEG3_6", - "INT_FEEDTHRU_1_EL1BEG3_7", - "INT_FEEDTHRU_1_EL1BEG3_8", - "INT_FEEDTHRU_1_EL1BEG3_9", - "INT_FEEDTHRU_1_ER1BEG0", - "INT_FEEDTHRU_1_ER1BEG0_1", - "INT_FEEDTHRU_1_ER1BEG0_2", - "INT_FEEDTHRU_1_ER1BEG0_3", - "INT_FEEDTHRU_1_ER1BEG0_4", - "INT_FEEDTHRU_1_ER1BEG0_5", - "INT_FEEDTHRU_1_ER1BEG0_6", - "INT_FEEDTHRU_1_ER1BEG0_7", - "INT_FEEDTHRU_1_ER1BEG0_8", - "INT_FEEDTHRU_1_ER1BEG0_9", - "INT_FEEDTHRU_1_ER1BEG1", - "INT_FEEDTHRU_1_ER1BEG1_1", - "INT_FEEDTHRU_1_ER1BEG1_2", - "INT_FEEDTHRU_1_ER1BEG1_3", - "INT_FEEDTHRU_1_ER1BEG1_4", - "INT_FEEDTHRU_1_ER1BEG1_5", - "INT_FEEDTHRU_1_ER1BEG1_6", - "INT_FEEDTHRU_1_ER1BEG1_7", - "INT_FEEDTHRU_1_ER1BEG1_8", - "INT_FEEDTHRU_1_ER1BEG1_9", - "INT_FEEDTHRU_1_ER1BEG2", - "INT_FEEDTHRU_1_ER1BEG2_1", - "INT_FEEDTHRU_1_ER1BEG2_2", - "INT_FEEDTHRU_1_ER1BEG2_3", - "INT_FEEDTHRU_1_ER1BEG2_4", - "INT_FEEDTHRU_1_ER1BEG2_5", - "INT_FEEDTHRU_1_ER1BEG2_6", - "INT_FEEDTHRU_1_ER1BEG2_7", - "INT_FEEDTHRU_1_ER1BEG2_8", - "INT_FEEDTHRU_1_ER1BEG2_9", - "INT_FEEDTHRU_1_ER1BEG3", - "INT_FEEDTHRU_1_ER1BEG3_1", - "INT_FEEDTHRU_1_ER1BEG3_2", - "INT_FEEDTHRU_1_ER1BEG3_3", - "INT_FEEDTHRU_1_ER1BEG3_4", - "INT_FEEDTHRU_1_ER1BEG3_5", - "INT_FEEDTHRU_1_ER1BEG3_6", - "INT_FEEDTHRU_1_ER1BEG3_7", - "INT_FEEDTHRU_1_ER1BEG3_8", - "INT_FEEDTHRU_1_ER1BEG3_9", - "INT_FEEDTHRU_1_LH1", - "INT_FEEDTHRU_1_LH10", - "INT_FEEDTHRU_1_LH10_1", - "INT_FEEDTHRU_1_LH10_2", - "INT_FEEDTHRU_1_LH10_3", - "INT_FEEDTHRU_1_LH10_4", - "INT_FEEDTHRU_1_LH10_5", - "INT_FEEDTHRU_1_LH10_6", - "INT_FEEDTHRU_1_LH10_7", - "INT_FEEDTHRU_1_LH10_8", - "INT_FEEDTHRU_1_LH10_9", - "INT_FEEDTHRU_1_LH11", - "INT_FEEDTHRU_1_LH11_1", - "INT_FEEDTHRU_1_LH11_2", - "INT_FEEDTHRU_1_LH11_3", - "INT_FEEDTHRU_1_LH11_4", - "INT_FEEDTHRU_1_LH11_5", - "INT_FEEDTHRU_1_LH11_6", - "INT_FEEDTHRU_1_LH11_7", - "INT_FEEDTHRU_1_LH11_8", - "INT_FEEDTHRU_1_LH11_9", - "INT_FEEDTHRU_1_LH12", - "INT_FEEDTHRU_1_LH12_1", - "INT_FEEDTHRU_1_LH12_2", - "INT_FEEDTHRU_1_LH12_3", - "INT_FEEDTHRU_1_LH12_4", - "INT_FEEDTHRU_1_LH12_5", - "INT_FEEDTHRU_1_LH12_6", - "INT_FEEDTHRU_1_LH12_7", - "INT_FEEDTHRU_1_LH12_8", - "INT_FEEDTHRU_1_LH12_9", - "INT_FEEDTHRU_1_LH1_1", - "INT_FEEDTHRU_1_LH1_2", - "INT_FEEDTHRU_1_LH1_3", - "INT_FEEDTHRU_1_LH1_4", - "INT_FEEDTHRU_1_LH1_5", - "INT_FEEDTHRU_1_LH1_6", - "INT_FEEDTHRU_1_LH1_7", - "INT_FEEDTHRU_1_LH1_8", - "INT_FEEDTHRU_1_LH1_9", - "INT_FEEDTHRU_1_LH2", - "INT_FEEDTHRU_1_LH2_1", - "INT_FEEDTHRU_1_LH2_2", - "INT_FEEDTHRU_1_LH2_3", - "INT_FEEDTHRU_1_LH2_4", - "INT_FEEDTHRU_1_LH2_5", - "INT_FEEDTHRU_1_LH2_6", - "INT_FEEDTHRU_1_LH2_7", - "INT_FEEDTHRU_1_LH2_8", - "INT_FEEDTHRU_1_LH2_9", - "INT_FEEDTHRU_1_LH3", - "INT_FEEDTHRU_1_LH3_1", - "INT_FEEDTHRU_1_LH3_2", - "INT_FEEDTHRU_1_LH3_3", - "INT_FEEDTHRU_1_LH3_4", - "INT_FEEDTHRU_1_LH3_5", - "INT_FEEDTHRU_1_LH3_6", - "INT_FEEDTHRU_1_LH3_7", - "INT_FEEDTHRU_1_LH3_8", - "INT_FEEDTHRU_1_LH3_9", - "INT_FEEDTHRU_1_LH4", - "INT_FEEDTHRU_1_LH4_1", - "INT_FEEDTHRU_1_LH4_2", - "INT_FEEDTHRU_1_LH4_3", - "INT_FEEDTHRU_1_LH4_4", - "INT_FEEDTHRU_1_LH4_5", - "INT_FEEDTHRU_1_LH4_6", - "INT_FEEDTHRU_1_LH4_7", - "INT_FEEDTHRU_1_LH4_8", - "INT_FEEDTHRU_1_LH4_9", - "INT_FEEDTHRU_1_LH5", - "INT_FEEDTHRU_1_LH5_1", - "INT_FEEDTHRU_1_LH5_2", - "INT_FEEDTHRU_1_LH5_3", - "INT_FEEDTHRU_1_LH5_4", - "INT_FEEDTHRU_1_LH5_5", - "INT_FEEDTHRU_1_LH5_6", - "INT_FEEDTHRU_1_LH5_7", - "INT_FEEDTHRU_1_LH5_8", - "INT_FEEDTHRU_1_LH5_9", - "INT_FEEDTHRU_1_LH6", - "INT_FEEDTHRU_1_LH6_1", - "INT_FEEDTHRU_1_LH6_2", - "INT_FEEDTHRU_1_LH6_3", - "INT_FEEDTHRU_1_LH6_4", - "INT_FEEDTHRU_1_LH6_5", - "INT_FEEDTHRU_1_LH6_6", - "INT_FEEDTHRU_1_LH6_7", - "INT_FEEDTHRU_1_LH6_8", - "INT_FEEDTHRU_1_LH6_9", - "INT_FEEDTHRU_1_LH7", - "INT_FEEDTHRU_1_LH7_1", - "INT_FEEDTHRU_1_LH7_2", - "INT_FEEDTHRU_1_LH7_3", - "INT_FEEDTHRU_1_LH7_4", - "INT_FEEDTHRU_1_LH7_5", - "INT_FEEDTHRU_1_LH7_6", - "INT_FEEDTHRU_1_LH7_7", - "INT_FEEDTHRU_1_LH7_8", - "INT_FEEDTHRU_1_LH7_9", - "INT_FEEDTHRU_1_LH8", - "INT_FEEDTHRU_1_LH8_1", - "INT_FEEDTHRU_1_LH8_2", - "INT_FEEDTHRU_1_LH8_3", - "INT_FEEDTHRU_1_LH8_4", - "INT_FEEDTHRU_1_LH8_5", - "INT_FEEDTHRU_1_LH8_6", - "INT_FEEDTHRU_1_LH8_7", - "INT_FEEDTHRU_1_LH8_8", - "INT_FEEDTHRU_1_LH8_9", - "INT_FEEDTHRU_1_LH9", - "INT_FEEDTHRU_1_LH9_1", - "INT_FEEDTHRU_1_LH9_2", - "INT_FEEDTHRU_1_LH9_3", - "INT_FEEDTHRU_1_LH9_4", - "INT_FEEDTHRU_1_LH9_5", - "INT_FEEDTHRU_1_LH9_6", - "INT_FEEDTHRU_1_LH9_7", - "INT_FEEDTHRU_1_LH9_8", - "INT_FEEDTHRU_1_LH9_9", - "INT_FEEDTHRU_1_MONITOR_N", - "INT_FEEDTHRU_1_MONITOR_N_1", - "INT_FEEDTHRU_1_MONITOR_N_2", - "INT_FEEDTHRU_1_MONITOR_N_4", - "INT_FEEDTHRU_1_MONITOR_N_6", - "INT_FEEDTHRU_1_MONITOR_N_7", - "INT_FEEDTHRU_1_MONITOR_N_8", - "INT_FEEDTHRU_1_MONITOR_P", - "INT_FEEDTHRU_1_MONITOR_P_1", - "INT_FEEDTHRU_1_MONITOR_P_2", - "INT_FEEDTHRU_1_MONITOR_P_4", - "INT_FEEDTHRU_1_MONITOR_P_6", - "INT_FEEDTHRU_1_MONITOR_P_7", - "INT_FEEDTHRU_1_MONITOR_P_8", - "INT_FEEDTHRU_1_NE2A0", - "INT_FEEDTHRU_1_NE2A0_1", - "INT_FEEDTHRU_1_NE2A0_2", - "INT_FEEDTHRU_1_NE2A0_3", - "INT_FEEDTHRU_1_NE2A0_4", - "INT_FEEDTHRU_1_NE2A0_5", - "INT_FEEDTHRU_1_NE2A0_6", - "INT_FEEDTHRU_1_NE2A0_7", - "INT_FEEDTHRU_1_NE2A0_8", - "INT_FEEDTHRU_1_NE2A0_9", - "INT_FEEDTHRU_1_NE2A1", - "INT_FEEDTHRU_1_NE2A1_1", - "INT_FEEDTHRU_1_NE2A1_2", - "INT_FEEDTHRU_1_NE2A1_3", - "INT_FEEDTHRU_1_NE2A1_4", - "INT_FEEDTHRU_1_NE2A1_5", - "INT_FEEDTHRU_1_NE2A1_6", - "INT_FEEDTHRU_1_NE2A1_7", - "INT_FEEDTHRU_1_NE2A1_8", - "INT_FEEDTHRU_1_NE2A1_9", - "INT_FEEDTHRU_1_NE2A2", - "INT_FEEDTHRU_1_NE2A2_1", - "INT_FEEDTHRU_1_NE2A2_2", - "INT_FEEDTHRU_1_NE2A2_3", - "INT_FEEDTHRU_1_NE2A2_4", - "INT_FEEDTHRU_1_NE2A2_5", - "INT_FEEDTHRU_1_NE2A2_6", - "INT_FEEDTHRU_1_NE2A2_7", - "INT_FEEDTHRU_1_NE2A2_8", - "INT_FEEDTHRU_1_NE2A2_9", - "INT_FEEDTHRU_1_NE2A3", - "INT_FEEDTHRU_1_NE2A3_1", - "INT_FEEDTHRU_1_NE2A3_2", - "INT_FEEDTHRU_1_NE2A3_3", - "INT_FEEDTHRU_1_NE2A3_4", - "INT_FEEDTHRU_1_NE2A3_5", - "INT_FEEDTHRU_1_NE2A3_6", - "INT_FEEDTHRU_1_NE2A3_7", - "INT_FEEDTHRU_1_NE2A3_8", - "INT_FEEDTHRU_1_NE2A3_9", - "INT_FEEDTHRU_1_NE4BEG0", - "INT_FEEDTHRU_1_NE4BEG0_1", - "INT_FEEDTHRU_1_NE4BEG0_2", - "INT_FEEDTHRU_1_NE4BEG0_3", - "INT_FEEDTHRU_1_NE4BEG0_4", - "INT_FEEDTHRU_1_NE4BEG0_5", - "INT_FEEDTHRU_1_NE4BEG0_6", - "INT_FEEDTHRU_1_NE4BEG0_7", - "INT_FEEDTHRU_1_NE4BEG0_8", - "INT_FEEDTHRU_1_NE4BEG0_9", - "INT_FEEDTHRU_1_NE4BEG1", - "INT_FEEDTHRU_1_NE4BEG1_1", - "INT_FEEDTHRU_1_NE4BEG1_2", - "INT_FEEDTHRU_1_NE4BEG1_3", - "INT_FEEDTHRU_1_NE4BEG1_4", - "INT_FEEDTHRU_1_NE4BEG1_5", - "INT_FEEDTHRU_1_NE4BEG1_6", - "INT_FEEDTHRU_1_NE4BEG1_7", - "INT_FEEDTHRU_1_NE4BEG1_8", - "INT_FEEDTHRU_1_NE4BEG1_9", - "INT_FEEDTHRU_1_NE4BEG2", - "INT_FEEDTHRU_1_NE4BEG2_1", - "INT_FEEDTHRU_1_NE4BEG2_2", - "INT_FEEDTHRU_1_NE4BEG2_3", - "INT_FEEDTHRU_1_NE4BEG2_4", - "INT_FEEDTHRU_1_NE4BEG2_5", - "INT_FEEDTHRU_1_NE4BEG2_6", - "INT_FEEDTHRU_1_NE4BEG2_7", - "INT_FEEDTHRU_1_NE4BEG2_8", - "INT_FEEDTHRU_1_NE4BEG2_9", - "INT_FEEDTHRU_1_NE4BEG3", - "INT_FEEDTHRU_1_NE4BEG3_1", - "INT_FEEDTHRU_1_NE4BEG3_2", - "INT_FEEDTHRU_1_NE4BEG3_3", - "INT_FEEDTHRU_1_NE4BEG3_4", - "INT_FEEDTHRU_1_NE4BEG3_5", - "INT_FEEDTHRU_1_NE4BEG3_6", - "INT_FEEDTHRU_1_NE4BEG3_7", - "INT_FEEDTHRU_1_NE4BEG3_8", - "INT_FEEDTHRU_1_NE4BEG3_9", - "INT_FEEDTHRU_1_NE4C0", - "INT_FEEDTHRU_1_NE4C0_1", - "INT_FEEDTHRU_1_NE4C0_2", - "INT_FEEDTHRU_1_NE4C0_3", - "INT_FEEDTHRU_1_NE4C0_4", - "INT_FEEDTHRU_1_NE4C0_5", - "INT_FEEDTHRU_1_NE4C0_6", - "INT_FEEDTHRU_1_NE4C0_7", - "INT_FEEDTHRU_1_NE4C0_8", - "INT_FEEDTHRU_1_NE4C0_9", - "INT_FEEDTHRU_1_NE4C1", - "INT_FEEDTHRU_1_NE4C1_1", - "INT_FEEDTHRU_1_NE4C1_2", - "INT_FEEDTHRU_1_NE4C1_3", - "INT_FEEDTHRU_1_NE4C1_4", - "INT_FEEDTHRU_1_NE4C1_5", - "INT_FEEDTHRU_1_NE4C1_6", - "INT_FEEDTHRU_1_NE4C1_7", - "INT_FEEDTHRU_1_NE4C1_8", - "INT_FEEDTHRU_1_NE4C1_9", - "INT_FEEDTHRU_1_NE4C2", - "INT_FEEDTHRU_1_NE4C2_1", - "INT_FEEDTHRU_1_NE4C2_2", - "INT_FEEDTHRU_1_NE4C2_3", - "INT_FEEDTHRU_1_NE4C2_4", - "INT_FEEDTHRU_1_NE4C2_5", - "INT_FEEDTHRU_1_NE4C2_6", - "INT_FEEDTHRU_1_NE4C2_7", - "INT_FEEDTHRU_1_NE4C2_8", - "INT_FEEDTHRU_1_NE4C2_9", - "INT_FEEDTHRU_1_NE4C3", - "INT_FEEDTHRU_1_NE4C3_1", - "INT_FEEDTHRU_1_NE4C3_2", - "INT_FEEDTHRU_1_NE4C3_3", - "INT_FEEDTHRU_1_NE4C3_4", - "INT_FEEDTHRU_1_NE4C3_5", - "INT_FEEDTHRU_1_NE4C3_6", - "INT_FEEDTHRU_1_NE4C3_7", - "INT_FEEDTHRU_1_NE4C3_8", - "INT_FEEDTHRU_1_NE4C3_9", - "INT_FEEDTHRU_1_NW2A0", - "INT_FEEDTHRU_1_NW2A0_1", - "INT_FEEDTHRU_1_NW2A0_2", - "INT_FEEDTHRU_1_NW2A0_3", - "INT_FEEDTHRU_1_NW2A0_4", - "INT_FEEDTHRU_1_NW2A0_5", - "INT_FEEDTHRU_1_NW2A0_6", - "INT_FEEDTHRU_1_NW2A0_7", - "INT_FEEDTHRU_1_NW2A0_8", - "INT_FEEDTHRU_1_NW2A0_9", - "INT_FEEDTHRU_1_NW2A1", - "INT_FEEDTHRU_1_NW2A1_1", - "INT_FEEDTHRU_1_NW2A1_2", - "INT_FEEDTHRU_1_NW2A1_3", - "INT_FEEDTHRU_1_NW2A1_4", - "INT_FEEDTHRU_1_NW2A1_5", - "INT_FEEDTHRU_1_NW2A1_6", - "INT_FEEDTHRU_1_NW2A1_7", - "INT_FEEDTHRU_1_NW2A1_8", - "INT_FEEDTHRU_1_NW2A1_9", - "INT_FEEDTHRU_1_NW2A2", - "INT_FEEDTHRU_1_NW2A2_1", - "INT_FEEDTHRU_1_NW2A2_2", - "INT_FEEDTHRU_1_NW2A2_3", - "INT_FEEDTHRU_1_NW2A2_4", - "INT_FEEDTHRU_1_NW2A2_5", - "INT_FEEDTHRU_1_NW2A2_6", - "INT_FEEDTHRU_1_NW2A2_7", - "INT_FEEDTHRU_1_NW2A2_8", - "INT_FEEDTHRU_1_NW2A2_9", - "INT_FEEDTHRU_1_NW2A3", - "INT_FEEDTHRU_1_NW2A3_1", - "INT_FEEDTHRU_1_NW2A3_2", - "INT_FEEDTHRU_1_NW2A3_3", - "INT_FEEDTHRU_1_NW2A3_4", - "INT_FEEDTHRU_1_NW2A3_5", - "INT_FEEDTHRU_1_NW2A3_6", - "INT_FEEDTHRU_1_NW2A3_7", - "INT_FEEDTHRU_1_NW2A3_8", - "INT_FEEDTHRU_1_NW2A3_9", - "INT_FEEDTHRU_1_NW4A0", - "INT_FEEDTHRU_1_NW4A0_1", - "INT_FEEDTHRU_1_NW4A0_2", - "INT_FEEDTHRU_1_NW4A0_3", - "INT_FEEDTHRU_1_NW4A0_4", - "INT_FEEDTHRU_1_NW4A0_5", - "INT_FEEDTHRU_1_NW4A0_6", - "INT_FEEDTHRU_1_NW4A0_7", - "INT_FEEDTHRU_1_NW4A0_8", - "INT_FEEDTHRU_1_NW4A0_9", - "INT_FEEDTHRU_1_NW4A1", - "INT_FEEDTHRU_1_NW4A1_1", - "INT_FEEDTHRU_1_NW4A1_2", - "INT_FEEDTHRU_1_NW4A1_3", - "INT_FEEDTHRU_1_NW4A1_4", - "INT_FEEDTHRU_1_NW4A1_5", - "INT_FEEDTHRU_1_NW4A1_6", - "INT_FEEDTHRU_1_NW4A1_7", - "INT_FEEDTHRU_1_NW4A1_8", - "INT_FEEDTHRU_1_NW4A1_9", - "INT_FEEDTHRU_1_NW4A2", - "INT_FEEDTHRU_1_NW4A2_1", - "INT_FEEDTHRU_1_NW4A2_2", - "INT_FEEDTHRU_1_NW4A2_3", - "INT_FEEDTHRU_1_NW4A2_4", - "INT_FEEDTHRU_1_NW4A2_5", - "INT_FEEDTHRU_1_NW4A2_6", - "INT_FEEDTHRU_1_NW4A2_7", - "INT_FEEDTHRU_1_NW4A2_8", - "INT_FEEDTHRU_1_NW4A2_9", - "INT_FEEDTHRU_1_NW4A3", - "INT_FEEDTHRU_1_NW4A3_1", - "INT_FEEDTHRU_1_NW4A3_2", - "INT_FEEDTHRU_1_NW4A3_3", - "INT_FEEDTHRU_1_NW4A3_4", - "INT_FEEDTHRU_1_NW4A3_5", - "INT_FEEDTHRU_1_NW4A3_6", - "INT_FEEDTHRU_1_NW4A3_7", - "INT_FEEDTHRU_1_NW4A3_8", - "INT_FEEDTHRU_1_NW4A3_9", - "INT_FEEDTHRU_1_NW4END0", - "INT_FEEDTHRU_1_NW4END0_1", - "INT_FEEDTHRU_1_NW4END0_2", - "INT_FEEDTHRU_1_NW4END0_3", - "INT_FEEDTHRU_1_NW4END0_4", - "INT_FEEDTHRU_1_NW4END0_5", - "INT_FEEDTHRU_1_NW4END0_6", - "INT_FEEDTHRU_1_NW4END0_7", - "INT_FEEDTHRU_1_NW4END0_8", - "INT_FEEDTHRU_1_NW4END0_9", - "INT_FEEDTHRU_1_NW4END1", - "INT_FEEDTHRU_1_NW4END1_1", - "INT_FEEDTHRU_1_NW4END1_2", - "INT_FEEDTHRU_1_NW4END1_3", - "INT_FEEDTHRU_1_NW4END1_4", - "INT_FEEDTHRU_1_NW4END1_5", - "INT_FEEDTHRU_1_NW4END1_6", - "INT_FEEDTHRU_1_NW4END1_7", - "INT_FEEDTHRU_1_NW4END1_8", - "INT_FEEDTHRU_1_NW4END1_9", - "INT_FEEDTHRU_1_NW4END2", - "INT_FEEDTHRU_1_NW4END2_1", - "INT_FEEDTHRU_1_NW4END2_2", - "INT_FEEDTHRU_1_NW4END2_3", - "INT_FEEDTHRU_1_NW4END2_4", - "INT_FEEDTHRU_1_NW4END2_5", - "INT_FEEDTHRU_1_NW4END2_6", - "INT_FEEDTHRU_1_NW4END2_7", - "INT_FEEDTHRU_1_NW4END2_8", - "INT_FEEDTHRU_1_NW4END2_9", - "INT_FEEDTHRU_1_NW4END3", - "INT_FEEDTHRU_1_NW4END3_1", - "INT_FEEDTHRU_1_NW4END3_2", - "INT_FEEDTHRU_1_NW4END3_3", - "INT_FEEDTHRU_1_NW4END3_4", - "INT_FEEDTHRU_1_NW4END3_5", - "INT_FEEDTHRU_1_NW4END3_6", - "INT_FEEDTHRU_1_NW4END3_7", - "INT_FEEDTHRU_1_NW4END3_8", - "INT_FEEDTHRU_1_NW4END3_9", - "INT_FEEDTHRU_1_SE2A0", - "INT_FEEDTHRU_1_SE2A0_1", - "INT_FEEDTHRU_1_SE2A0_2", - "INT_FEEDTHRU_1_SE2A0_3", - "INT_FEEDTHRU_1_SE2A0_4", - "INT_FEEDTHRU_1_SE2A0_5", - "INT_FEEDTHRU_1_SE2A0_6", - "INT_FEEDTHRU_1_SE2A0_7", - "INT_FEEDTHRU_1_SE2A0_8", - "INT_FEEDTHRU_1_SE2A0_9", - "INT_FEEDTHRU_1_SE2A1", - "INT_FEEDTHRU_1_SE2A1_1", - "INT_FEEDTHRU_1_SE2A1_2", - "INT_FEEDTHRU_1_SE2A1_3", - "INT_FEEDTHRU_1_SE2A1_4", - "INT_FEEDTHRU_1_SE2A1_5", - "INT_FEEDTHRU_1_SE2A1_6", - "INT_FEEDTHRU_1_SE2A1_7", - "INT_FEEDTHRU_1_SE2A1_8", - "INT_FEEDTHRU_1_SE2A1_9", - "INT_FEEDTHRU_1_SE2A2", - "INT_FEEDTHRU_1_SE2A2_1", - "INT_FEEDTHRU_1_SE2A2_2", - "INT_FEEDTHRU_1_SE2A2_3", - "INT_FEEDTHRU_1_SE2A2_4", - "INT_FEEDTHRU_1_SE2A2_5", - "INT_FEEDTHRU_1_SE2A2_6", - "INT_FEEDTHRU_1_SE2A2_7", - "INT_FEEDTHRU_1_SE2A2_8", - "INT_FEEDTHRU_1_SE2A2_9", - "INT_FEEDTHRU_1_SE2A3", - "INT_FEEDTHRU_1_SE2A3_1", - "INT_FEEDTHRU_1_SE2A3_2", - "INT_FEEDTHRU_1_SE2A3_3", - "INT_FEEDTHRU_1_SE2A3_4", - "INT_FEEDTHRU_1_SE2A3_5", - "INT_FEEDTHRU_1_SE2A3_6", - "INT_FEEDTHRU_1_SE2A3_7", - "INT_FEEDTHRU_1_SE2A3_8", - "INT_FEEDTHRU_1_SE2A3_9", - "INT_FEEDTHRU_1_SE4BEG0", - "INT_FEEDTHRU_1_SE4BEG0_1", - "INT_FEEDTHRU_1_SE4BEG0_2", - "INT_FEEDTHRU_1_SE4BEG0_3", - "INT_FEEDTHRU_1_SE4BEG0_4", - "INT_FEEDTHRU_1_SE4BEG0_5", - "INT_FEEDTHRU_1_SE4BEG0_6", - "INT_FEEDTHRU_1_SE4BEG0_7", - "INT_FEEDTHRU_1_SE4BEG0_8", - "INT_FEEDTHRU_1_SE4BEG0_9", - "INT_FEEDTHRU_1_SE4BEG1", - "INT_FEEDTHRU_1_SE4BEG1_1", - "INT_FEEDTHRU_1_SE4BEG1_2", - "INT_FEEDTHRU_1_SE4BEG1_3", - "INT_FEEDTHRU_1_SE4BEG1_4", - "INT_FEEDTHRU_1_SE4BEG1_5", - "INT_FEEDTHRU_1_SE4BEG1_6", - "INT_FEEDTHRU_1_SE4BEG1_7", - "INT_FEEDTHRU_1_SE4BEG1_8", - "INT_FEEDTHRU_1_SE4BEG1_9", - "INT_FEEDTHRU_1_SE4BEG2", - "INT_FEEDTHRU_1_SE4BEG2_1", - "INT_FEEDTHRU_1_SE4BEG2_2", - "INT_FEEDTHRU_1_SE4BEG2_3", - "INT_FEEDTHRU_1_SE4BEG2_4", - "INT_FEEDTHRU_1_SE4BEG2_5", - "INT_FEEDTHRU_1_SE4BEG2_6", - "INT_FEEDTHRU_1_SE4BEG2_7", - "INT_FEEDTHRU_1_SE4BEG2_8", - "INT_FEEDTHRU_1_SE4BEG2_9", - "INT_FEEDTHRU_1_SE4BEG3", - "INT_FEEDTHRU_1_SE4BEG3_1", - "INT_FEEDTHRU_1_SE4BEG3_2", - "INT_FEEDTHRU_1_SE4BEG3_3", - "INT_FEEDTHRU_1_SE4BEG3_4", - "INT_FEEDTHRU_1_SE4BEG3_5", - "INT_FEEDTHRU_1_SE4BEG3_6", - "INT_FEEDTHRU_1_SE4BEG3_7", - "INT_FEEDTHRU_1_SE4BEG3_8", - "INT_FEEDTHRU_1_SE4BEG3_9", - "INT_FEEDTHRU_1_SE4C0", - "INT_FEEDTHRU_1_SE4C0_1", - "INT_FEEDTHRU_1_SE4C0_2", - "INT_FEEDTHRU_1_SE4C0_3", - "INT_FEEDTHRU_1_SE4C0_4", - "INT_FEEDTHRU_1_SE4C0_5", - "INT_FEEDTHRU_1_SE4C0_6", - "INT_FEEDTHRU_1_SE4C0_7", - "INT_FEEDTHRU_1_SE4C0_8", - "INT_FEEDTHRU_1_SE4C0_9", - "INT_FEEDTHRU_1_SE4C1", - "INT_FEEDTHRU_1_SE4C1_1", - "INT_FEEDTHRU_1_SE4C1_2", - "INT_FEEDTHRU_1_SE4C1_3", - "INT_FEEDTHRU_1_SE4C1_4", - "INT_FEEDTHRU_1_SE4C1_5", - "INT_FEEDTHRU_1_SE4C1_6", - "INT_FEEDTHRU_1_SE4C1_7", - "INT_FEEDTHRU_1_SE4C1_8", - "INT_FEEDTHRU_1_SE4C1_9", - "INT_FEEDTHRU_1_SE4C2", - "INT_FEEDTHRU_1_SE4C2_1", - "INT_FEEDTHRU_1_SE4C2_2", - "INT_FEEDTHRU_1_SE4C2_3", - "INT_FEEDTHRU_1_SE4C2_4", - "INT_FEEDTHRU_1_SE4C2_5", - "INT_FEEDTHRU_1_SE4C2_6", - "INT_FEEDTHRU_1_SE4C2_7", - "INT_FEEDTHRU_1_SE4C2_8", - "INT_FEEDTHRU_1_SE4C2_9", - "INT_FEEDTHRU_1_SE4C3", - "INT_FEEDTHRU_1_SE4C3_1", - "INT_FEEDTHRU_1_SE4C3_2", - "INT_FEEDTHRU_1_SE4C3_3", - "INT_FEEDTHRU_1_SE4C3_4", - "INT_FEEDTHRU_1_SE4C3_5", - "INT_FEEDTHRU_1_SE4C3_6", - "INT_FEEDTHRU_1_SE4C3_7", - "INT_FEEDTHRU_1_SE4C3_8", - "INT_FEEDTHRU_1_SE4C3_9", - "INT_FEEDTHRU_1_SW2A0", - "INT_FEEDTHRU_1_SW2A0_1", - "INT_FEEDTHRU_1_SW2A0_2", - "INT_FEEDTHRU_1_SW2A0_3", - "INT_FEEDTHRU_1_SW2A0_4", - "INT_FEEDTHRU_1_SW2A0_5", - "INT_FEEDTHRU_1_SW2A0_6", - "INT_FEEDTHRU_1_SW2A0_7", - "INT_FEEDTHRU_1_SW2A0_8", - "INT_FEEDTHRU_1_SW2A0_9", - "INT_FEEDTHRU_1_SW2A1", - "INT_FEEDTHRU_1_SW2A1_1", - "INT_FEEDTHRU_1_SW2A1_2", - "INT_FEEDTHRU_1_SW2A1_3", - "INT_FEEDTHRU_1_SW2A1_4", - "INT_FEEDTHRU_1_SW2A1_5", - "INT_FEEDTHRU_1_SW2A1_6", - "INT_FEEDTHRU_1_SW2A1_7", - "INT_FEEDTHRU_1_SW2A1_8", - "INT_FEEDTHRU_1_SW2A1_9", - "INT_FEEDTHRU_1_SW2A2", - "INT_FEEDTHRU_1_SW2A2_1", - "INT_FEEDTHRU_1_SW2A2_2", - "INT_FEEDTHRU_1_SW2A2_3", - "INT_FEEDTHRU_1_SW2A2_4", - "INT_FEEDTHRU_1_SW2A2_5", - "INT_FEEDTHRU_1_SW2A2_6", - "INT_FEEDTHRU_1_SW2A2_7", - "INT_FEEDTHRU_1_SW2A2_8", - "INT_FEEDTHRU_1_SW2A2_9", - "INT_FEEDTHRU_1_SW2A3", - "INT_FEEDTHRU_1_SW2A3_1", - "INT_FEEDTHRU_1_SW2A3_2", - "INT_FEEDTHRU_1_SW2A3_3", - "INT_FEEDTHRU_1_SW2A3_4", - "INT_FEEDTHRU_1_SW2A3_5", - "INT_FEEDTHRU_1_SW2A3_6", - "INT_FEEDTHRU_1_SW2A3_7", - "INT_FEEDTHRU_1_SW2A3_8", - "INT_FEEDTHRU_1_SW2A3_9", - "INT_FEEDTHRU_1_SW4A0", - "INT_FEEDTHRU_1_SW4A0_1", - "INT_FEEDTHRU_1_SW4A0_2", - "INT_FEEDTHRU_1_SW4A0_3", - "INT_FEEDTHRU_1_SW4A0_4", - "INT_FEEDTHRU_1_SW4A0_5", - "INT_FEEDTHRU_1_SW4A0_6", - "INT_FEEDTHRU_1_SW4A0_7", - "INT_FEEDTHRU_1_SW4A0_8", - "INT_FEEDTHRU_1_SW4A0_9", - "INT_FEEDTHRU_1_SW4A1", - "INT_FEEDTHRU_1_SW4A1_1", - "INT_FEEDTHRU_1_SW4A1_2", - "INT_FEEDTHRU_1_SW4A1_3", - "INT_FEEDTHRU_1_SW4A1_4", - "INT_FEEDTHRU_1_SW4A1_5", - "INT_FEEDTHRU_1_SW4A1_6", - "INT_FEEDTHRU_1_SW4A1_7", - "INT_FEEDTHRU_1_SW4A1_8", - "INT_FEEDTHRU_1_SW4A1_9", - "INT_FEEDTHRU_1_SW4A2", - "INT_FEEDTHRU_1_SW4A2_1", - "INT_FEEDTHRU_1_SW4A2_2", - "INT_FEEDTHRU_1_SW4A2_3", - "INT_FEEDTHRU_1_SW4A2_4", - "INT_FEEDTHRU_1_SW4A2_5", - "INT_FEEDTHRU_1_SW4A2_6", - "INT_FEEDTHRU_1_SW4A2_7", - "INT_FEEDTHRU_1_SW4A2_8", - "INT_FEEDTHRU_1_SW4A2_9", - "INT_FEEDTHRU_1_SW4A3", - "INT_FEEDTHRU_1_SW4A3_1", - "INT_FEEDTHRU_1_SW4A3_2", - "INT_FEEDTHRU_1_SW4A3_3", - "INT_FEEDTHRU_1_SW4A3_4", - "INT_FEEDTHRU_1_SW4A3_5", - "INT_FEEDTHRU_1_SW4A3_6", - "INT_FEEDTHRU_1_SW4A3_7", - "INT_FEEDTHRU_1_SW4A3_8", - "INT_FEEDTHRU_1_SW4A3_9", - "INT_FEEDTHRU_1_SW4END0", - "INT_FEEDTHRU_1_SW4END0_1", - "INT_FEEDTHRU_1_SW4END0_2", - "INT_FEEDTHRU_1_SW4END0_3", - "INT_FEEDTHRU_1_SW4END0_4", - "INT_FEEDTHRU_1_SW4END0_5", - "INT_FEEDTHRU_1_SW4END0_6", - "INT_FEEDTHRU_1_SW4END0_7", - "INT_FEEDTHRU_1_SW4END0_8", - "INT_FEEDTHRU_1_SW4END0_9", - "INT_FEEDTHRU_1_SW4END1", - "INT_FEEDTHRU_1_SW4END1_1", - "INT_FEEDTHRU_1_SW4END1_2", - "INT_FEEDTHRU_1_SW4END1_3", - "INT_FEEDTHRU_1_SW4END1_4", - "INT_FEEDTHRU_1_SW4END1_5", - "INT_FEEDTHRU_1_SW4END1_6", - "INT_FEEDTHRU_1_SW4END1_7", - "INT_FEEDTHRU_1_SW4END1_8", - "INT_FEEDTHRU_1_SW4END1_9", - "INT_FEEDTHRU_1_SW4END2", - "INT_FEEDTHRU_1_SW4END2_1", - "INT_FEEDTHRU_1_SW4END2_2", - "INT_FEEDTHRU_1_SW4END2_3", - "INT_FEEDTHRU_1_SW4END2_4", - "INT_FEEDTHRU_1_SW4END2_5", - "INT_FEEDTHRU_1_SW4END2_6", - "INT_FEEDTHRU_1_SW4END2_7", - "INT_FEEDTHRU_1_SW4END2_8", - "INT_FEEDTHRU_1_SW4END2_9", - "INT_FEEDTHRU_1_SW4END3", - "INT_FEEDTHRU_1_SW4END3_1", - "INT_FEEDTHRU_1_SW4END3_2", - "INT_FEEDTHRU_1_SW4END3_3", - "INT_FEEDTHRU_1_SW4END3_4", - "INT_FEEDTHRU_1_SW4END3_5", - "INT_FEEDTHRU_1_SW4END3_6", - "INT_FEEDTHRU_1_SW4END3_7", - "INT_FEEDTHRU_1_SW4END3_8", - "INT_FEEDTHRU_1_SW4END3_9", - "INT_FEEDTHRU_1_WL1END0", - "INT_FEEDTHRU_1_WL1END0_1", - "INT_FEEDTHRU_1_WL1END0_2", - "INT_FEEDTHRU_1_WL1END0_3", - "INT_FEEDTHRU_1_WL1END0_4", - "INT_FEEDTHRU_1_WL1END0_5", - "INT_FEEDTHRU_1_WL1END0_6", - "INT_FEEDTHRU_1_WL1END0_7", - "INT_FEEDTHRU_1_WL1END0_8", - "INT_FEEDTHRU_1_WL1END0_9", - "INT_FEEDTHRU_1_WL1END1", - "INT_FEEDTHRU_1_WL1END1_1", - "INT_FEEDTHRU_1_WL1END1_2", - "INT_FEEDTHRU_1_WL1END1_3", - "INT_FEEDTHRU_1_WL1END1_4", - "INT_FEEDTHRU_1_WL1END1_5", - "INT_FEEDTHRU_1_WL1END1_6", - "INT_FEEDTHRU_1_WL1END1_7", - "INT_FEEDTHRU_1_WL1END1_8", - "INT_FEEDTHRU_1_WL1END1_9", - "INT_FEEDTHRU_1_WL1END2", - "INT_FEEDTHRU_1_WL1END2_1", - "INT_FEEDTHRU_1_WL1END2_2", - "INT_FEEDTHRU_1_WL1END2_3", - "INT_FEEDTHRU_1_WL1END2_4", - "INT_FEEDTHRU_1_WL1END2_5", - "INT_FEEDTHRU_1_WL1END2_6", - "INT_FEEDTHRU_1_WL1END2_7", - "INT_FEEDTHRU_1_WL1END2_8", - "INT_FEEDTHRU_1_WL1END2_9", - "INT_FEEDTHRU_1_WL1END3", - "INT_FEEDTHRU_1_WL1END3_1", - "INT_FEEDTHRU_1_WL1END3_2", - "INT_FEEDTHRU_1_WL1END3_3", - "INT_FEEDTHRU_1_WL1END3_4", - "INT_FEEDTHRU_1_WL1END3_5", - "INT_FEEDTHRU_1_WL1END3_6", - "INT_FEEDTHRU_1_WL1END3_7", - "INT_FEEDTHRU_1_WL1END3_8", - "INT_FEEDTHRU_1_WL1END3_9", - "INT_FEEDTHRU_1_WR1END0", - "INT_FEEDTHRU_1_WR1END0_1", - "INT_FEEDTHRU_1_WR1END0_2", - "INT_FEEDTHRU_1_WR1END0_3", - "INT_FEEDTHRU_1_WR1END0_4", - "INT_FEEDTHRU_1_WR1END0_5", - "INT_FEEDTHRU_1_WR1END0_6", - "INT_FEEDTHRU_1_WR1END0_7", - "INT_FEEDTHRU_1_WR1END0_8", - "INT_FEEDTHRU_1_WR1END0_9", - "INT_FEEDTHRU_1_WR1END1", - "INT_FEEDTHRU_1_WR1END1_1", - "INT_FEEDTHRU_1_WR1END1_2", - "INT_FEEDTHRU_1_WR1END1_3", - "INT_FEEDTHRU_1_WR1END1_4", - "INT_FEEDTHRU_1_WR1END1_5", - "INT_FEEDTHRU_1_WR1END1_6", - "INT_FEEDTHRU_1_WR1END1_7", - "INT_FEEDTHRU_1_WR1END1_8", - "INT_FEEDTHRU_1_WR1END1_9", - "INT_FEEDTHRU_1_WR1END2", - "INT_FEEDTHRU_1_WR1END2_1", - "INT_FEEDTHRU_1_WR1END2_2", - "INT_FEEDTHRU_1_WR1END2_3", - "INT_FEEDTHRU_1_WR1END2_4", - "INT_FEEDTHRU_1_WR1END2_5", - "INT_FEEDTHRU_1_WR1END2_6", - "INT_FEEDTHRU_1_WR1END2_7", - "INT_FEEDTHRU_1_WR1END2_8", - "INT_FEEDTHRU_1_WR1END2_9", - "INT_FEEDTHRU_1_WR1END3", - "INT_FEEDTHRU_1_WR1END3_1", - "INT_FEEDTHRU_1_WR1END3_2", - "INT_FEEDTHRU_1_WR1END3_3", - "INT_FEEDTHRU_1_WR1END3_4", - "INT_FEEDTHRU_1_WR1END3_5", - "INT_FEEDTHRU_1_WR1END3_6", - "INT_FEEDTHRU_1_WR1END3_7", - "INT_FEEDTHRU_1_WR1END3_8", - "INT_FEEDTHRU_1_WR1END3_9", - "INT_FEEDTHRU_1_WW2A0", - "INT_FEEDTHRU_1_WW2A0_1", - "INT_FEEDTHRU_1_WW2A0_2", - "INT_FEEDTHRU_1_WW2A0_3", - "INT_FEEDTHRU_1_WW2A0_4", - "INT_FEEDTHRU_1_WW2A0_5", - "INT_FEEDTHRU_1_WW2A0_6", - "INT_FEEDTHRU_1_WW2A0_7", - "INT_FEEDTHRU_1_WW2A0_8", - "INT_FEEDTHRU_1_WW2A0_9", - "INT_FEEDTHRU_1_WW2A1", - "INT_FEEDTHRU_1_WW2A1_1", - "INT_FEEDTHRU_1_WW2A1_2", - "INT_FEEDTHRU_1_WW2A1_3", - "INT_FEEDTHRU_1_WW2A1_4", - "INT_FEEDTHRU_1_WW2A1_5", - "INT_FEEDTHRU_1_WW2A1_6", - "INT_FEEDTHRU_1_WW2A1_7", - "INT_FEEDTHRU_1_WW2A1_8", - "INT_FEEDTHRU_1_WW2A1_9", - "INT_FEEDTHRU_1_WW2A2", - "INT_FEEDTHRU_1_WW2A2_1", - "INT_FEEDTHRU_1_WW2A2_2", - "INT_FEEDTHRU_1_WW2A2_3", - "INT_FEEDTHRU_1_WW2A2_4", - "INT_FEEDTHRU_1_WW2A2_5", - "INT_FEEDTHRU_1_WW2A2_6", - "INT_FEEDTHRU_1_WW2A2_7", - "INT_FEEDTHRU_1_WW2A2_8", - "INT_FEEDTHRU_1_WW2A2_9", - "INT_FEEDTHRU_1_WW2A3", - "INT_FEEDTHRU_1_WW2A3_1", - "INT_FEEDTHRU_1_WW2A3_2", - "INT_FEEDTHRU_1_WW2A3_3", - "INT_FEEDTHRU_1_WW2A3_4", - "INT_FEEDTHRU_1_WW2A3_5", - "INT_FEEDTHRU_1_WW2A3_6", - "INT_FEEDTHRU_1_WW2A3_7", - "INT_FEEDTHRU_1_WW2A3_8", - "INT_FEEDTHRU_1_WW2A3_9", - "INT_FEEDTHRU_1_WW2END0", - "INT_FEEDTHRU_1_WW2END0_1", - "INT_FEEDTHRU_1_WW2END0_2", - "INT_FEEDTHRU_1_WW2END0_3", - "INT_FEEDTHRU_1_WW2END0_4", - "INT_FEEDTHRU_1_WW2END0_5", - "INT_FEEDTHRU_1_WW2END0_6", - "INT_FEEDTHRU_1_WW2END0_7", - "INT_FEEDTHRU_1_WW2END0_8", - "INT_FEEDTHRU_1_WW2END0_9", - "INT_FEEDTHRU_1_WW2END1", - "INT_FEEDTHRU_1_WW2END1_1", - "INT_FEEDTHRU_1_WW2END1_2", - "INT_FEEDTHRU_1_WW2END1_3", - "INT_FEEDTHRU_1_WW2END1_4", - "INT_FEEDTHRU_1_WW2END1_5", - "INT_FEEDTHRU_1_WW2END1_6", - "INT_FEEDTHRU_1_WW2END1_7", - "INT_FEEDTHRU_1_WW2END1_8", - "INT_FEEDTHRU_1_WW2END1_9", - "INT_FEEDTHRU_1_WW2END2", - "INT_FEEDTHRU_1_WW2END2_1", - "INT_FEEDTHRU_1_WW2END2_2", - "INT_FEEDTHRU_1_WW2END2_3", - "INT_FEEDTHRU_1_WW2END2_4", - "INT_FEEDTHRU_1_WW2END2_5", - "INT_FEEDTHRU_1_WW2END2_6", - "INT_FEEDTHRU_1_WW2END2_7", - "INT_FEEDTHRU_1_WW2END2_8", - "INT_FEEDTHRU_1_WW2END2_9", - "INT_FEEDTHRU_1_WW2END3", - "INT_FEEDTHRU_1_WW2END3_1", - "INT_FEEDTHRU_1_WW2END3_2", - "INT_FEEDTHRU_1_WW2END3_3", - "INT_FEEDTHRU_1_WW2END3_4", - "INT_FEEDTHRU_1_WW2END3_5", - "INT_FEEDTHRU_1_WW2END3_6", - "INT_FEEDTHRU_1_WW2END3_7", - "INT_FEEDTHRU_1_WW2END3_8", - "INT_FEEDTHRU_1_WW2END3_9", - "INT_FEEDTHRU_1_WW4A0", - "INT_FEEDTHRU_1_WW4A0_1", - "INT_FEEDTHRU_1_WW4A0_2", - "INT_FEEDTHRU_1_WW4A0_3", - "INT_FEEDTHRU_1_WW4A0_4", - "INT_FEEDTHRU_1_WW4A0_5", - "INT_FEEDTHRU_1_WW4A0_6", - "INT_FEEDTHRU_1_WW4A0_7", - "INT_FEEDTHRU_1_WW4A0_8", - "INT_FEEDTHRU_1_WW4A0_9", - "INT_FEEDTHRU_1_WW4A1", - "INT_FEEDTHRU_1_WW4A1_1", - "INT_FEEDTHRU_1_WW4A1_2", - "INT_FEEDTHRU_1_WW4A1_3", - "INT_FEEDTHRU_1_WW4A1_4", - "INT_FEEDTHRU_1_WW4A1_5", - "INT_FEEDTHRU_1_WW4A1_6", - "INT_FEEDTHRU_1_WW4A1_7", - "INT_FEEDTHRU_1_WW4A1_8", - "INT_FEEDTHRU_1_WW4A1_9", - "INT_FEEDTHRU_1_WW4A2", - "INT_FEEDTHRU_1_WW4A2_1", - "INT_FEEDTHRU_1_WW4A2_2", - "INT_FEEDTHRU_1_WW4A2_3", - "INT_FEEDTHRU_1_WW4A2_4", - "INT_FEEDTHRU_1_WW4A2_5", - "INT_FEEDTHRU_1_WW4A2_6", - "INT_FEEDTHRU_1_WW4A2_7", - "INT_FEEDTHRU_1_WW4A2_8", - "INT_FEEDTHRU_1_WW4A2_9", - "INT_FEEDTHRU_1_WW4A3", - "INT_FEEDTHRU_1_WW4A3_1", - "INT_FEEDTHRU_1_WW4A3_2", - "INT_FEEDTHRU_1_WW4A3_3", - "INT_FEEDTHRU_1_WW4A3_4", - "INT_FEEDTHRU_1_WW4A3_5", - "INT_FEEDTHRU_1_WW4A3_6", - "INT_FEEDTHRU_1_WW4A3_7", - "INT_FEEDTHRU_1_WW4A3_8", - "INT_FEEDTHRU_1_WW4A3_9", - "INT_FEEDTHRU_1_WW4B0", - "INT_FEEDTHRU_1_WW4B0_1", - "INT_FEEDTHRU_1_WW4B0_2", - "INT_FEEDTHRU_1_WW4B0_3", - "INT_FEEDTHRU_1_WW4B0_4", - "INT_FEEDTHRU_1_WW4B0_5", - "INT_FEEDTHRU_1_WW4B0_6", - "INT_FEEDTHRU_1_WW4B0_7", - "INT_FEEDTHRU_1_WW4B0_8", - "INT_FEEDTHRU_1_WW4B0_9", - "INT_FEEDTHRU_1_WW4B1", - "INT_FEEDTHRU_1_WW4B1_1", - "INT_FEEDTHRU_1_WW4B1_2", - "INT_FEEDTHRU_1_WW4B1_3", - "INT_FEEDTHRU_1_WW4B1_4", - "INT_FEEDTHRU_1_WW4B1_5", - "INT_FEEDTHRU_1_WW4B1_6", - "INT_FEEDTHRU_1_WW4B1_7", - "INT_FEEDTHRU_1_WW4B1_8", - "INT_FEEDTHRU_1_WW4B1_9", - "INT_FEEDTHRU_1_WW4B2", - "INT_FEEDTHRU_1_WW4B2_1", - "INT_FEEDTHRU_1_WW4B2_2", - "INT_FEEDTHRU_1_WW4B2_3", - "INT_FEEDTHRU_1_WW4B2_4", - "INT_FEEDTHRU_1_WW4B2_5", - "INT_FEEDTHRU_1_WW4B2_6", - "INT_FEEDTHRU_1_WW4B2_7", - "INT_FEEDTHRU_1_WW4B2_8", - "INT_FEEDTHRU_1_WW4B2_9", - "INT_FEEDTHRU_1_WW4B3", - "INT_FEEDTHRU_1_WW4B3_1", - "INT_FEEDTHRU_1_WW4B3_2", - "INT_FEEDTHRU_1_WW4B3_3", - "INT_FEEDTHRU_1_WW4B3_4", - "INT_FEEDTHRU_1_WW4B3_5", - "INT_FEEDTHRU_1_WW4B3_6", - "INT_FEEDTHRU_1_WW4B3_7", - "INT_FEEDTHRU_1_WW4B3_8", - "INT_FEEDTHRU_1_WW4B3_9", - "INT_FEEDTHRU_1_WW4C0", - "INT_FEEDTHRU_1_WW4C0_1", - "INT_FEEDTHRU_1_WW4C0_2", - "INT_FEEDTHRU_1_WW4C0_3", - "INT_FEEDTHRU_1_WW4C0_4", - "INT_FEEDTHRU_1_WW4C0_5", - "INT_FEEDTHRU_1_WW4C0_6", - "INT_FEEDTHRU_1_WW4C0_7", - "INT_FEEDTHRU_1_WW4C0_8", - "INT_FEEDTHRU_1_WW4C0_9", - "INT_FEEDTHRU_1_WW4C1", - "INT_FEEDTHRU_1_WW4C1_1", - "INT_FEEDTHRU_1_WW4C1_2", - "INT_FEEDTHRU_1_WW4C1_3", - "INT_FEEDTHRU_1_WW4C1_4", - "INT_FEEDTHRU_1_WW4C1_5", - "INT_FEEDTHRU_1_WW4C1_6", - "INT_FEEDTHRU_1_WW4C1_7", - "INT_FEEDTHRU_1_WW4C1_8", - "INT_FEEDTHRU_1_WW4C1_9", - "INT_FEEDTHRU_1_WW4C2", - "INT_FEEDTHRU_1_WW4C2_1", - "INT_FEEDTHRU_1_WW4C2_2", - "INT_FEEDTHRU_1_WW4C2_3", - "INT_FEEDTHRU_1_WW4C2_4", - "INT_FEEDTHRU_1_WW4C2_5", - "INT_FEEDTHRU_1_WW4C2_6", - "INT_FEEDTHRU_1_WW4C2_7", - "INT_FEEDTHRU_1_WW4C2_8", - "INT_FEEDTHRU_1_WW4C2_9", - "INT_FEEDTHRU_1_WW4C3", - "INT_FEEDTHRU_1_WW4C3_1", - "INT_FEEDTHRU_1_WW4C3_2", - "INT_FEEDTHRU_1_WW4C3_3", - "INT_FEEDTHRU_1_WW4C3_4", - "INT_FEEDTHRU_1_WW4C3_5", - "INT_FEEDTHRU_1_WW4C3_6", - "INT_FEEDTHRU_1_WW4C3_7", - "INT_FEEDTHRU_1_WW4C3_8", - "INT_FEEDTHRU_1_WW4C3_9", - "INT_FEEDTHRU_1_WW4END0", - "INT_FEEDTHRU_1_WW4END0_1", - "INT_FEEDTHRU_1_WW4END0_2", - "INT_FEEDTHRU_1_WW4END0_3", - "INT_FEEDTHRU_1_WW4END0_4", - "INT_FEEDTHRU_1_WW4END0_5", - "INT_FEEDTHRU_1_WW4END0_6", - "INT_FEEDTHRU_1_WW4END0_7", - "INT_FEEDTHRU_1_WW4END0_8", - "INT_FEEDTHRU_1_WW4END0_9", - "INT_FEEDTHRU_1_WW4END1", - "INT_FEEDTHRU_1_WW4END1_1", - "INT_FEEDTHRU_1_WW4END1_2", - "INT_FEEDTHRU_1_WW4END1_3", - "INT_FEEDTHRU_1_WW4END1_4", - "INT_FEEDTHRU_1_WW4END1_5", - "INT_FEEDTHRU_1_WW4END1_6", - "INT_FEEDTHRU_1_WW4END1_7", - "INT_FEEDTHRU_1_WW4END1_8", - "INT_FEEDTHRU_1_WW4END1_9", - "INT_FEEDTHRU_1_WW4END2", - "INT_FEEDTHRU_1_WW4END2_1", - "INT_FEEDTHRU_1_WW4END2_2", - "INT_FEEDTHRU_1_WW4END2_3", - "INT_FEEDTHRU_1_WW4END2_4", - "INT_FEEDTHRU_1_WW4END2_5", - "INT_FEEDTHRU_1_WW4END2_6", - "INT_FEEDTHRU_1_WW4END2_7", - "INT_FEEDTHRU_1_WW4END2_8", - "INT_FEEDTHRU_1_WW4END2_9", - "INT_FEEDTHRU_1_WW4END3", - "INT_FEEDTHRU_1_WW4END3_1", - "INT_FEEDTHRU_1_WW4END3_2", - "INT_FEEDTHRU_1_WW4END3_3", - "INT_FEEDTHRU_1_WW4END3_4", - "INT_FEEDTHRU_1_WW4END3_5", - "INT_FEEDTHRU_1_WW4END3_6", - "INT_FEEDTHRU_1_WW4END3_7", - "INT_FEEDTHRU_1_WW4END3_8", - "INT_FEEDTHRU_1_WW4END3_9", - "MONITOR_HORIZ_VAUXN12", - "MONITOR_HORIZ_VAUXN13", - "MONITOR_HORIZ_VAUXN5", - "MONITOR_HORIZ_VAUXP12", - "MONITOR_HORIZ_VAUXP13", - "MONITOR_HORIZ_VAUXP5", - "MONITOR_VERT_VAUXN0", - "MONITOR_VERT_VAUXN1", - "MONITOR_VERT_VAUXN10", - "MONITOR_VERT_VAUXN11", - "MONITOR_VERT_VAUXN12", - "MONITOR_VERT_VAUXN13", - "MONITOR_VERT_VAUXN14", - "MONITOR_VERT_VAUXN15", - "MONITOR_VERT_VAUXN2", - "MONITOR_VERT_VAUXN3", - "MONITOR_VERT_VAUXN4", - "MONITOR_VERT_VAUXN5", - "MONITOR_VERT_VAUXN6", - "MONITOR_VERT_VAUXN7", - "MONITOR_VERT_VAUXN8", - "MONITOR_VERT_VAUXN9", - "MONITOR_VERT_VAUXP0", - "MONITOR_VERT_VAUXP1", - "MONITOR_VERT_VAUXP10", - "MONITOR_VERT_VAUXP11", - "MONITOR_VERT_VAUXP12", - "MONITOR_VERT_VAUXP13", - "MONITOR_VERT_VAUXP14", - "MONITOR_VERT_VAUXP15", - "MONITOR_VERT_VAUXP2", - "MONITOR_VERT_VAUXP3", - "MONITOR_VERT_VAUXP4", - "MONITOR_VERT_VAUXP5", - "MONITOR_VERT_VAUXP6", - "MONITOR_VERT_VAUXP7", - "MONITOR_VERT_VAUXP8", - "MONITOR_VERT_VAUXP9" - ] + "wires": { + "INT_FEEDTHRU_1_EE2A0": null, + "INT_FEEDTHRU_1_EE2A0_1": null, + "INT_FEEDTHRU_1_EE2A0_2": null, + "INT_FEEDTHRU_1_EE2A0_3": null, + "INT_FEEDTHRU_1_EE2A0_4": null, + "INT_FEEDTHRU_1_EE2A0_5": null, + "INT_FEEDTHRU_1_EE2A0_6": null, + "INT_FEEDTHRU_1_EE2A0_7": null, + "INT_FEEDTHRU_1_EE2A0_8": null, + "INT_FEEDTHRU_1_EE2A0_9": null, + "INT_FEEDTHRU_1_EE2A1": null, + "INT_FEEDTHRU_1_EE2A1_1": null, + "INT_FEEDTHRU_1_EE2A1_2": null, + "INT_FEEDTHRU_1_EE2A1_3": null, + "INT_FEEDTHRU_1_EE2A1_4": null, + "INT_FEEDTHRU_1_EE2A1_5": null, + "INT_FEEDTHRU_1_EE2A1_6": null, + "INT_FEEDTHRU_1_EE2A1_7": null, + "INT_FEEDTHRU_1_EE2A1_8": null, + "INT_FEEDTHRU_1_EE2A1_9": null, + "INT_FEEDTHRU_1_EE2A2": null, + "INT_FEEDTHRU_1_EE2A2_1": null, + "INT_FEEDTHRU_1_EE2A2_2": null, + "INT_FEEDTHRU_1_EE2A2_3": null, + "INT_FEEDTHRU_1_EE2A2_4": null, + "INT_FEEDTHRU_1_EE2A2_5": null, + "INT_FEEDTHRU_1_EE2A2_6": null, + "INT_FEEDTHRU_1_EE2A2_7": null, + "INT_FEEDTHRU_1_EE2A2_8": null, + "INT_FEEDTHRU_1_EE2A2_9": null, + "INT_FEEDTHRU_1_EE2A3": null, + "INT_FEEDTHRU_1_EE2A3_1": null, + "INT_FEEDTHRU_1_EE2A3_2": null, + "INT_FEEDTHRU_1_EE2A3_3": null, + "INT_FEEDTHRU_1_EE2A3_4": null, + "INT_FEEDTHRU_1_EE2A3_5": null, + "INT_FEEDTHRU_1_EE2A3_6": null, + "INT_FEEDTHRU_1_EE2A3_7": null, + "INT_FEEDTHRU_1_EE2A3_8": null, + "INT_FEEDTHRU_1_EE2A3_9": null, + "INT_FEEDTHRU_1_EE2BEG0": null, + "INT_FEEDTHRU_1_EE2BEG0_1": null, + "INT_FEEDTHRU_1_EE2BEG0_2": null, + "INT_FEEDTHRU_1_EE2BEG0_3": null, + "INT_FEEDTHRU_1_EE2BEG0_4": null, + "INT_FEEDTHRU_1_EE2BEG0_5": null, + "INT_FEEDTHRU_1_EE2BEG0_6": null, + "INT_FEEDTHRU_1_EE2BEG0_7": null, + "INT_FEEDTHRU_1_EE2BEG0_8": null, + "INT_FEEDTHRU_1_EE2BEG0_9": null, + "INT_FEEDTHRU_1_EE2BEG1": null, + "INT_FEEDTHRU_1_EE2BEG1_1": null, + "INT_FEEDTHRU_1_EE2BEG1_2": null, + "INT_FEEDTHRU_1_EE2BEG1_3": null, + "INT_FEEDTHRU_1_EE2BEG1_4": null, + "INT_FEEDTHRU_1_EE2BEG1_5": null, + "INT_FEEDTHRU_1_EE2BEG1_6": null, + "INT_FEEDTHRU_1_EE2BEG1_7": null, + "INT_FEEDTHRU_1_EE2BEG1_8": null, + "INT_FEEDTHRU_1_EE2BEG1_9": null, + "INT_FEEDTHRU_1_EE2BEG2": null, + "INT_FEEDTHRU_1_EE2BEG2_1": null, + "INT_FEEDTHRU_1_EE2BEG2_2": null, + "INT_FEEDTHRU_1_EE2BEG2_3": null, + "INT_FEEDTHRU_1_EE2BEG2_4": null, + "INT_FEEDTHRU_1_EE2BEG2_5": null, + "INT_FEEDTHRU_1_EE2BEG2_6": null, + "INT_FEEDTHRU_1_EE2BEG2_7": null, + "INT_FEEDTHRU_1_EE2BEG2_8": null, + "INT_FEEDTHRU_1_EE2BEG2_9": null, + "INT_FEEDTHRU_1_EE2BEG3": null, + "INT_FEEDTHRU_1_EE2BEG3_1": null, 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"INT_FEEDTHRU_1_WW4B3": null, + "INT_FEEDTHRU_1_WW4B3_1": null, + "INT_FEEDTHRU_1_WW4B3_2": null, + "INT_FEEDTHRU_1_WW4B3_3": null, + "INT_FEEDTHRU_1_WW4B3_4": null, + "INT_FEEDTHRU_1_WW4B3_5": null, + "INT_FEEDTHRU_1_WW4B3_6": null, + "INT_FEEDTHRU_1_WW4B3_7": null, + "INT_FEEDTHRU_1_WW4B3_8": null, + "INT_FEEDTHRU_1_WW4B3_9": null, + "INT_FEEDTHRU_1_WW4C0": null, + "INT_FEEDTHRU_1_WW4C0_1": null, + "INT_FEEDTHRU_1_WW4C0_2": null, + "INT_FEEDTHRU_1_WW4C0_3": null, + "INT_FEEDTHRU_1_WW4C0_4": null, + "INT_FEEDTHRU_1_WW4C0_5": null, + "INT_FEEDTHRU_1_WW4C0_6": null, + "INT_FEEDTHRU_1_WW4C0_7": null, + "INT_FEEDTHRU_1_WW4C0_8": null, + "INT_FEEDTHRU_1_WW4C0_9": null, + "INT_FEEDTHRU_1_WW4C1": null, + "INT_FEEDTHRU_1_WW4C1_1": null, + "INT_FEEDTHRU_1_WW4C1_2": null, + "INT_FEEDTHRU_1_WW4C1_3": null, + "INT_FEEDTHRU_1_WW4C1_4": null, + "INT_FEEDTHRU_1_WW4C1_5": null, + "INT_FEEDTHRU_1_WW4C1_6": null, + "INT_FEEDTHRU_1_WW4C1_7": null, + "INT_FEEDTHRU_1_WW4C1_8": null, + "INT_FEEDTHRU_1_WW4C1_9": null, + "INT_FEEDTHRU_1_WW4C2": null, + "INT_FEEDTHRU_1_WW4C2_1": null, + "INT_FEEDTHRU_1_WW4C2_2": null, + "INT_FEEDTHRU_1_WW4C2_3": null, + "INT_FEEDTHRU_1_WW4C2_4": null, + "INT_FEEDTHRU_1_WW4C2_5": null, + "INT_FEEDTHRU_1_WW4C2_6": null, + "INT_FEEDTHRU_1_WW4C2_7": null, + "INT_FEEDTHRU_1_WW4C2_8": null, + "INT_FEEDTHRU_1_WW4C2_9": null, + "INT_FEEDTHRU_1_WW4C3": null, + "INT_FEEDTHRU_1_WW4C3_1": null, + "INT_FEEDTHRU_1_WW4C3_2": null, + "INT_FEEDTHRU_1_WW4C3_3": null, + "INT_FEEDTHRU_1_WW4C3_4": null, + "INT_FEEDTHRU_1_WW4C3_5": null, + "INT_FEEDTHRU_1_WW4C3_6": null, + "INT_FEEDTHRU_1_WW4C3_7": null, + "INT_FEEDTHRU_1_WW4C3_8": null, + "INT_FEEDTHRU_1_WW4C3_9": null, + "INT_FEEDTHRU_1_WW4END0": null, + "INT_FEEDTHRU_1_WW4END0_1": null, + "INT_FEEDTHRU_1_WW4END0_2": null, + "INT_FEEDTHRU_1_WW4END0_3": null, + "INT_FEEDTHRU_1_WW4END0_4": null, + "INT_FEEDTHRU_1_WW4END0_5": null, + "INT_FEEDTHRU_1_WW4END0_6": null, + "INT_FEEDTHRU_1_WW4END0_7": null, + "INT_FEEDTHRU_1_WW4END0_8": null, + "INT_FEEDTHRU_1_WW4END0_9": null, + "INT_FEEDTHRU_1_WW4END1": null, + "INT_FEEDTHRU_1_WW4END1_1": null, + "INT_FEEDTHRU_1_WW4END1_2": null, + "INT_FEEDTHRU_1_WW4END1_3": null, + "INT_FEEDTHRU_1_WW4END1_4": null, + "INT_FEEDTHRU_1_WW4END1_5": null, + "INT_FEEDTHRU_1_WW4END1_6": null, + "INT_FEEDTHRU_1_WW4END1_7": null, + "INT_FEEDTHRU_1_WW4END1_8": null, + "INT_FEEDTHRU_1_WW4END1_9": null, + "INT_FEEDTHRU_1_WW4END2": null, + "INT_FEEDTHRU_1_WW4END2_1": null, + "INT_FEEDTHRU_1_WW4END2_2": null, + "INT_FEEDTHRU_1_WW4END2_3": null, + "INT_FEEDTHRU_1_WW4END2_4": null, + "INT_FEEDTHRU_1_WW4END2_5": null, + "INT_FEEDTHRU_1_WW4END2_6": null, + "INT_FEEDTHRU_1_WW4END2_7": null, + "INT_FEEDTHRU_1_WW4END2_8": null, + "INT_FEEDTHRU_1_WW4END2_9": null, + "INT_FEEDTHRU_1_WW4END3": null, + "INT_FEEDTHRU_1_WW4END3_1": null, + "INT_FEEDTHRU_1_WW4END3_2": null, + "INT_FEEDTHRU_1_WW4END3_3": null, + "INT_FEEDTHRU_1_WW4END3_4": null, + "INT_FEEDTHRU_1_WW4END3_5": null, + "INT_FEEDTHRU_1_WW4END3_6": null, + "INT_FEEDTHRU_1_WW4END3_7": null, + "INT_FEEDTHRU_1_WW4END3_8": null, + "INT_FEEDTHRU_1_WW4END3_9": null, + "MONITOR_HORIZ_VAUXN12": null, + "MONITOR_HORIZ_VAUXN13": null, + "MONITOR_HORIZ_VAUXN5": null, + "MONITOR_HORIZ_VAUXP12": null, + "MONITOR_HORIZ_VAUXP13": null, + "MONITOR_HORIZ_VAUXP5": null, + "MONITOR_VERT_VAUXN0": null, + "MONITOR_VERT_VAUXN1": null, + "MONITOR_VERT_VAUXN10": null, + "MONITOR_VERT_VAUXN11": null, + "MONITOR_VERT_VAUXN12": null, + "MONITOR_VERT_VAUXN13": null, + "MONITOR_VERT_VAUXN14": null, + "MONITOR_VERT_VAUXN15": null, + "MONITOR_VERT_VAUXN2": null, + "MONITOR_VERT_VAUXN3": null, + "MONITOR_VERT_VAUXN4": null, + "MONITOR_VERT_VAUXN5": null, + "MONITOR_VERT_VAUXN6": null, + "MONITOR_VERT_VAUXN7": null, + "MONITOR_VERT_VAUXN8": null, + "MONITOR_VERT_VAUXN9": null, + "MONITOR_VERT_VAUXP0": null, + "MONITOR_VERT_VAUXP1": null, + "MONITOR_VERT_VAUXP10": null, + "MONITOR_VERT_VAUXP11": null, + "MONITOR_VERT_VAUXP12": null, + "MONITOR_VERT_VAUXP13": null, + "MONITOR_VERT_VAUXP14": null, + "MONITOR_VERT_VAUXP15": null, + "MONITOR_VERT_VAUXP2": null, + "MONITOR_VERT_VAUXP3": null, + "MONITOR_VERT_VAUXP4": null, + "MONITOR_VERT_VAUXP5": null, + "MONITOR_VERT_VAUXP6": null, + "MONITOR_VERT_VAUXP7": null, + "MONITOR_VERT_VAUXP8": null, + "MONITOR_VERT_VAUXP9": null + } } diff --git a/zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json b/zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json index 8b2e0ba..0926bf4 100644 --- a/zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json +++ b/zynq7/tile_type_CFG_SECURITY_TOP_PELE1.json @@ -2,683 +2,705 @@ "pips": { "CFG_SECURITY_TOP_PELE1.MONITOR_HORIZ_VAUXN4->MONITOR_VERT_SHORT_VAUXN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_SHORT_VAUXN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN4" }, "CFG_SECURITY_TOP_PELE1.MONITOR_HORIZ_VAUXP4->MONITOR_VERT_SHORT_VAUXP4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_SHORT_VAUXP4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP4" } }, "sites": [], "tile_type": "CFG_SECURITY_TOP_PELE1", - "wires": [ - "INT_FEEDTHRU_1_EE2A0", - "INT_FEEDTHRU_1_EE2A0_1", - "INT_FEEDTHRU_1_EE2A0_2", - "INT_FEEDTHRU_1_EE2A0_3", - "INT_FEEDTHRU_1_EE2A0_4", - "INT_FEEDTHRU_1_EE2A1", - "INT_FEEDTHRU_1_EE2A1_1", - "INT_FEEDTHRU_1_EE2A1_2", - "INT_FEEDTHRU_1_EE2A1_3", - "INT_FEEDTHRU_1_EE2A1_4", - "INT_FEEDTHRU_1_EE2A2", - "INT_FEEDTHRU_1_EE2A2_1", - "INT_FEEDTHRU_1_EE2A2_2", - "INT_FEEDTHRU_1_EE2A2_3", - "INT_FEEDTHRU_1_EE2A2_4", - "INT_FEEDTHRU_1_EE2A3", - "INT_FEEDTHRU_1_EE2A3_1", - "INT_FEEDTHRU_1_EE2A3_2", - "INT_FEEDTHRU_1_EE2A3_3", - "INT_FEEDTHRU_1_EE2A3_4", - "INT_FEEDTHRU_1_EE2BEG0", - "INT_FEEDTHRU_1_EE2BEG0_1", - "INT_FEEDTHRU_1_EE2BEG0_2", - "INT_FEEDTHRU_1_EE2BEG0_3", - "INT_FEEDTHRU_1_EE2BEG0_4", - "INT_FEEDTHRU_1_EE2BEG1", - "INT_FEEDTHRU_1_EE2BEG1_1", - "INT_FEEDTHRU_1_EE2BEG1_2", - "INT_FEEDTHRU_1_EE2BEG1_3", - "INT_FEEDTHRU_1_EE2BEG1_4", - "INT_FEEDTHRU_1_EE2BEG2", - "INT_FEEDTHRU_1_EE2BEG2_1", - "INT_FEEDTHRU_1_EE2BEG2_2", - "INT_FEEDTHRU_1_EE2BEG2_3", - "INT_FEEDTHRU_1_EE2BEG2_4", - "INT_FEEDTHRU_1_EE2BEG3", - "INT_FEEDTHRU_1_EE2BEG3_1", - "INT_FEEDTHRU_1_EE2BEG3_2", - "INT_FEEDTHRU_1_EE2BEG3_3", - "INT_FEEDTHRU_1_EE2BEG3_4", - "INT_FEEDTHRU_1_EE4A0", - "INT_FEEDTHRU_1_EE4A0_1", - "INT_FEEDTHRU_1_EE4A0_2", - "INT_FEEDTHRU_1_EE4A0_3", - "INT_FEEDTHRU_1_EE4A0_4", - "INT_FEEDTHRU_1_EE4A1", - "INT_FEEDTHRU_1_EE4A1_1", - "INT_FEEDTHRU_1_EE4A1_2", - "INT_FEEDTHRU_1_EE4A1_3", - "INT_FEEDTHRU_1_EE4A1_4", - "INT_FEEDTHRU_1_EE4A2", - "INT_FEEDTHRU_1_EE4A2_1", - "INT_FEEDTHRU_1_EE4A2_2", - "INT_FEEDTHRU_1_EE4A2_3", - "INT_FEEDTHRU_1_EE4A2_4", - "INT_FEEDTHRU_1_EE4A3", - "INT_FEEDTHRU_1_EE4A3_1", - "INT_FEEDTHRU_1_EE4A3_2", - "INT_FEEDTHRU_1_EE4A3_3", - "INT_FEEDTHRU_1_EE4A3_4", - "INT_FEEDTHRU_1_EE4B0", - "INT_FEEDTHRU_1_EE4B0_1", - "INT_FEEDTHRU_1_EE4B0_2", - "INT_FEEDTHRU_1_EE4B0_3", - "INT_FEEDTHRU_1_EE4B0_4", - "INT_FEEDTHRU_1_EE4B1", - "INT_FEEDTHRU_1_EE4B1_1", - "INT_FEEDTHRU_1_EE4B1_2", - "INT_FEEDTHRU_1_EE4B1_3", - "INT_FEEDTHRU_1_EE4B1_4", - "INT_FEEDTHRU_1_EE4B2", - "INT_FEEDTHRU_1_EE4B2_1", - "INT_FEEDTHRU_1_EE4B2_2", - "INT_FEEDTHRU_1_EE4B2_3", - "INT_FEEDTHRU_1_EE4B2_4", - "INT_FEEDTHRU_1_EE4B3", - "INT_FEEDTHRU_1_EE4B3_1", - "INT_FEEDTHRU_1_EE4B3_2", - "INT_FEEDTHRU_1_EE4B3_3", - "INT_FEEDTHRU_1_EE4B3_4", - "INT_FEEDTHRU_1_EE4BEG0", - "INT_FEEDTHRU_1_EE4BEG0_1", - "INT_FEEDTHRU_1_EE4BEG0_2", - "INT_FEEDTHRU_1_EE4BEG0_3", - "INT_FEEDTHRU_1_EE4BEG0_4", - "INT_FEEDTHRU_1_EE4BEG1", - "INT_FEEDTHRU_1_EE4BEG1_1", - "INT_FEEDTHRU_1_EE4BEG1_2", - "INT_FEEDTHRU_1_EE4BEG1_3", - "INT_FEEDTHRU_1_EE4BEG1_4", - "INT_FEEDTHRU_1_EE4BEG2", - "INT_FEEDTHRU_1_EE4BEG2_1", - "INT_FEEDTHRU_1_EE4BEG2_2", - "INT_FEEDTHRU_1_EE4BEG2_3", - "INT_FEEDTHRU_1_EE4BEG2_4", - "INT_FEEDTHRU_1_EE4BEG3", - "INT_FEEDTHRU_1_EE4BEG3_1", - "INT_FEEDTHRU_1_EE4BEG3_2", - "INT_FEEDTHRU_1_EE4BEG3_3", - "INT_FEEDTHRU_1_EE4BEG3_4", - "INT_FEEDTHRU_1_EE4C0", - "INT_FEEDTHRU_1_EE4C0_1", - "INT_FEEDTHRU_1_EE4C0_2", - "INT_FEEDTHRU_1_EE4C0_3", - "INT_FEEDTHRU_1_EE4C0_4", - "INT_FEEDTHRU_1_EE4C1", - "INT_FEEDTHRU_1_EE4C1_1", - "INT_FEEDTHRU_1_EE4C1_2", - "INT_FEEDTHRU_1_EE4C1_3", - "INT_FEEDTHRU_1_EE4C1_4", - "INT_FEEDTHRU_1_EE4C2", - "INT_FEEDTHRU_1_EE4C2_1", - "INT_FEEDTHRU_1_EE4C2_2", - "INT_FEEDTHRU_1_EE4C2_3", - "INT_FEEDTHRU_1_EE4C2_4", - "INT_FEEDTHRU_1_EE4C3", - "INT_FEEDTHRU_1_EE4C3_1", - "INT_FEEDTHRU_1_EE4C3_2", - "INT_FEEDTHRU_1_EE4C3_3", - "INT_FEEDTHRU_1_EE4C3_4", - "INT_FEEDTHRU_1_EL1BEG0", - "INT_FEEDTHRU_1_EL1BEG0_1", - "INT_FEEDTHRU_1_EL1BEG0_2", - "INT_FEEDTHRU_1_EL1BEG0_3", - "INT_FEEDTHRU_1_EL1BEG0_4", - "INT_FEEDTHRU_1_EL1BEG1", - "INT_FEEDTHRU_1_EL1BEG1_1", - "INT_FEEDTHRU_1_EL1BEG1_2", - "INT_FEEDTHRU_1_EL1BEG1_3", - "INT_FEEDTHRU_1_EL1BEG1_4", - "INT_FEEDTHRU_1_EL1BEG2", - "INT_FEEDTHRU_1_EL1BEG2_1", - "INT_FEEDTHRU_1_EL1BEG2_2", - "INT_FEEDTHRU_1_EL1BEG2_3", - "INT_FEEDTHRU_1_EL1BEG2_4", - "INT_FEEDTHRU_1_EL1BEG3", - "INT_FEEDTHRU_1_EL1BEG3_1", - "INT_FEEDTHRU_1_EL1BEG3_2", - "INT_FEEDTHRU_1_EL1BEG3_3", - "INT_FEEDTHRU_1_EL1BEG3_4", - "INT_FEEDTHRU_1_ER1BEG0", - "INT_FEEDTHRU_1_ER1BEG0_1", - "INT_FEEDTHRU_1_ER1BEG0_2", - "INT_FEEDTHRU_1_ER1BEG0_3", - "INT_FEEDTHRU_1_ER1BEG0_4", - "INT_FEEDTHRU_1_ER1BEG1", - "INT_FEEDTHRU_1_ER1BEG1_1", - "INT_FEEDTHRU_1_ER1BEG1_2", - "INT_FEEDTHRU_1_ER1BEG1_3", - "INT_FEEDTHRU_1_ER1BEG1_4", - "INT_FEEDTHRU_1_ER1BEG2", - "INT_FEEDTHRU_1_ER1BEG2_1", - "INT_FEEDTHRU_1_ER1BEG2_2", - "INT_FEEDTHRU_1_ER1BEG2_3", - "INT_FEEDTHRU_1_ER1BEG2_4", - "INT_FEEDTHRU_1_ER1BEG3", - "INT_FEEDTHRU_1_ER1BEG3_1", - "INT_FEEDTHRU_1_ER1BEG3_2", - "INT_FEEDTHRU_1_ER1BEG3_3", - "INT_FEEDTHRU_1_ER1BEG3_4", - "INT_FEEDTHRU_1_LH1", - "INT_FEEDTHRU_1_LH10", - "INT_FEEDTHRU_1_LH10_1", - "INT_FEEDTHRU_1_LH10_2", - "INT_FEEDTHRU_1_LH10_3", - "INT_FEEDTHRU_1_LH10_4", - "INT_FEEDTHRU_1_LH11", - "INT_FEEDTHRU_1_LH11_1", - "INT_FEEDTHRU_1_LH11_2", - "INT_FEEDTHRU_1_LH11_3", - "INT_FEEDTHRU_1_LH11_4", - "INT_FEEDTHRU_1_LH12", - "INT_FEEDTHRU_1_LH12_1", - "INT_FEEDTHRU_1_LH12_2", - "INT_FEEDTHRU_1_LH12_3", - "INT_FEEDTHRU_1_LH12_4", - "INT_FEEDTHRU_1_LH1_1", - "INT_FEEDTHRU_1_LH1_2", - "INT_FEEDTHRU_1_LH1_3", - "INT_FEEDTHRU_1_LH1_4", - "INT_FEEDTHRU_1_LH2", - "INT_FEEDTHRU_1_LH2_1", - "INT_FEEDTHRU_1_LH2_2", - "INT_FEEDTHRU_1_LH2_3", - "INT_FEEDTHRU_1_LH2_4", - "INT_FEEDTHRU_1_LH3", - "INT_FEEDTHRU_1_LH3_1", - "INT_FEEDTHRU_1_LH3_2", - "INT_FEEDTHRU_1_LH3_3", - "INT_FEEDTHRU_1_LH3_4", - "INT_FEEDTHRU_1_LH4", - "INT_FEEDTHRU_1_LH4_1", - "INT_FEEDTHRU_1_LH4_2", - "INT_FEEDTHRU_1_LH4_3", - "INT_FEEDTHRU_1_LH4_4", - "INT_FEEDTHRU_1_LH5", - "INT_FEEDTHRU_1_LH5_1", - "INT_FEEDTHRU_1_LH5_2", - "INT_FEEDTHRU_1_LH5_3", - "INT_FEEDTHRU_1_LH5_4", - "INT_FEEDTHRU_1_LH6", - "INT_FEEDTHRU_1_LH6_1", - "INT_FEEDTHRU_1_LH6_2", - "INT_FEEDTHRU_1_LH6_3", - "INT_FEEDTHRU_1_LH6_4", - "INT_FEEDTHRU_1_LH7", - "INT_FEEDTHRU_1_LH7_1", - "INT_FEEDTHRU_1_LH7_2", - "INT_FEEDTHRU_1_LH7_3", - "INT_FEEDTHRU_1_LH7_4", - "INT_FEEDTHRU_1_LH8", - "INT_FEEDTHRU_1_LH8_1", - "INT_FEEDTHRU_1_LH8_2", - "INT_FEEDTHRU_1_LH8_3", - "INT_FEEDTHRU_1_LH8_4", - "INT_FEEDTHRU_1_LH9", - "INT_FEEDTHRU_1_LH9_1", - "INT_FEEDTHRU_1_LH9_2", - "INT_FEEDTHRU_1_LH9_3", - "INT_FEEDTHRU_1_LH9_4", - "INT_FEEDTHRU_1_MONITOR_N", - "INT_FEEDTHRU_1_MONITOR_N_2", - "INT_FEEDTHRU_1_MONITOR_N_3", - "INT_FEEDTHRU_1_MONITOR_N_4", - "INT_FEEDTHRU_1_MONITOR_P", - "INT_FEEDTHRU_1_MONITOR_P_2", - "INT_FEEDTHRU_1_MONITOR_P_3", - "INT_FEEDTHRU_1_MONITOR_P_4", - "INT_FEEDTHRU_1_NE2A0", - "INT_FEEDTHRU_1_NE2A0_1", - "INT_FEEDTHRU_1_NE2A0_2", - "INT_FEEDTHRU_1_NE2A0_3", - "INT_FEEDTHRU_1_NE2A0_4", - "INT_FEEDTHRU_1_NE2A1", - "INT_FEEDTHRU_1_NE2A1_1", - "INT_FEEDTHRU_1_NE2A1_2", - "INT_FEEDTHRU_1_NE2A1_3", - "INT_FEEDTHRU_1_NE2A1_4", - "INT_FEEDTHRU_1_NE2A2", - "INT_FEEDTHRU_1_NE2A2_1", - "INT_FEEDTHRU_1_NE2A2_2", - "INT_FEEDTHRU_1_NE2A2_3", - "INT_FEEDTHRU_1_NE2A2_4", - "INT_FEEDTHRU_1_NE2A3", - "INT_FEEDTHRU_1_NE2A3_1", - "INT_FEEDTHRU_1_NE2A3_2", - "INT_FEEDTHRU_1_NE2A3_3", - "INT_FEEDTHRU_1_NE2A3_4", - "INT_FEEDTHRU_1_NE4BEG0", - "INT_FEEDTHRU_1_NE4BEG0_1", - "INT_FEEDTHRU_1_NE4BEG0_2", - "INT_FEEDTHRU_1_NE4BEG0_3", - "INT_FEEDTHRU_1_NE4BEG0_4", - "INT_FEEDTHRU_1_NE4BEG1", - "INT_FEEDTHRU_1_NE4BEG1_1", - "INT_FEEDTHRU_1_NE4BEG1_2", - "INT_FEEDTHRU_1_NE4BEG1_3", - "INT_FEEDTHRU_1_NE4BEG1_4", - "INT_FEEDTHRU_1_NE4BEG2", - "INT_FEEDTHRU_1_NE4BEG2_1", - "INT_FEEDTHRU_1_NE4BEG2_2", - "INT_FEEDTHRU_1_NE4BEG2_3", - "INT_FEEDTHRU_1_NE4BEG2_4", - "INT_FEEDTHRU_1_NE4BEG3", - "INT_FEEDTHRU_1_NE4BEG3_1", - "INT_FEEDTHRU_1_NE4BEG3_2", - "INT_FEEDTHRU_1_NE4BEG3_3", - "INT_FEEDTHRU_1_NE4BEG3_4", - "INT_FEEDTHRU_1_NE4C0", - "INT_FEEDTHRU_1_NE4C0_1", - "INT_FEEDTHRU_1_NE4C0_2", - "INT_FEEDTHRU_1_NE4C0_3", - "INT_FEEDTHRU_1_NE4C0_4", - "INT_FEEDTHRU_1_NE4C1", - "INT_FEEDTHRU_1_NE4C1_1", - "INT_FEEDTHRU_1_NE4C1_2", - "INT_FEEDTHRU_1_NE4C1_3", - "INT_FEEDTHRU_1_NE4C1_4", - "INT_FEEDTHRU_1_NE4C2", - "INT_FEEDTHRU_1_NE4C2_1", - "INT_FEEDTHRU_1_NE4C2_2", - "INT_FEEDTHRU_1_NE4C2_3", - "INT_FEEDTHRU_1_NE4C2_4", - "INT_FEEDTHRU_1_NE4C3", - "INT_FEEDTHRU_1_NE4C3_1", - "INT_FEEDTHRU_1_NE4C3_2", - "INT_FEEDTHRU_1_NE4C3_3", - "INT_FEEDTHRU_1_NE4C3_4", - "INT_FEEDTHRU_1_NW2A0", - "INT_FEEDTHRU_1_NW2A0_1", - "INT_FEEDTHRU_1_NW2A0_2", - "INT_FEEDTHRU_1_NW2A0_3", - "INT_FEEDTHRU_1_NW2A0_4", - "INT_FEEDTHRU_1_NW2A1", - "INT_FEEDTHRU_1_NW2A1_1", - "INT_FEEDTHRU_1_NW2A1_2", - "INT_FEEDTHRU_1_NW2A1_3", - "INT_FEEDTHRU_1_NW2A1_4", - "INT_FEEDTHRU_1_NW2A2", - "INT_FEEDTHRU_1_NW2A2_1", - "INT_FEEDTHRU_1_NW2A2_2", - "INT_FEEDTHRU_1_NW2A2_3", - "INT_FEEDTHRU_1_NW2A2_4", - "INT_FEEDTHRU_1_NW2A3", - "INT_FEEDTHRU_1_NW2A3_1", - "INT_FEEDTHRU_1_NW2A3_2", - "INT_FEEDTHRU_1_NW2A3_3", - "INT_FEEDTHRU_1_NW2A3_4", - "INT_FEEDTHRU_1_NW4A0", - "INT_FEEDTHRU_1_NW4A0_1", - "INT_FEEDTHRU_1_NW4A0_2", - "INT_FEEDTHRU_1_NW4A0_3", - "INT_FEEDTHRU_1_NW4A0_4", - "INT_FEEDTHRU_1_NW4A1", - "INT_FEEDTHRU_1_NW4A1_1", - "INT_FEEDTHRU_1_NW4A1_2", - "INT_FEEDTHRU_1_NW4A1_3", - "INT_FEEDTHRU_1_NW4A1_4", - "INT_FEEDTHRU_1_NW4A2", - "INT_FEEDTHRU_1_NW4A2_1", - "INT_FEEDTHRU_1_NW4A2_2", - "INT_FEEDTHRU_1_NW4A2_3", - "INT_FEEDTHRU_1_NW4A2_4", - "INT_FEEDTHRU_1_NW4A3", - "INT_FEEDTHRU_1_NW4A3_1", - "INT_FEEDTHRU_1_NW4A3_2", - "INT_FEEDTHRU_1_NW4A3_3", - "INT_FEEDTHRU_1_NW4A3_4", - "INT_FEEDTHRU_1_NW4END0", - "INT_FEEDTHRU_1_NW4END0_1", - "INT_FEEDTHRU_1_NW4END0_2", - "INT_FEEDTHRU_1_NW4END0_3", - "INT_FEEDTHRU_1_NW4END0_4", - "INT_FEEDTHRU_1_NW4END1", - "INT_FEEDTHRU_1_NW4END1_1", - "INT_FEEDTHRU_1_NW4END1_2", - "INT_FEEDTHRU_1_NW4END1_3", - "INT_FEEDTHRU_1_NW4END1_4", - "INT_FEEDTHRU_1_NW4END2", - "INT_FEEDTHRU_1_NW4END2_1", - "INT_FEEDTHRU_1_NW4END2_2", - "INT_FEEDTHRU_1_NW4END2_3", - "INT_FEEDTHRU_1_NW4END2_4", - "INT_FEEDTHRU_1_NW4END3", - "INT_FEEDTHRU_1_NW4END3_1", - "INT_FEEDTHRU_1_NW4END3_2", - "INT_FEEDTHRU_1_NW4END3_3", - "INT_FEEDTHRU_1_NW4END3_4", - "INT_FEEDTHRU_1_SE2A0", - "INT_FEEDTHRU_1_SE2A0_1", - "INT_FEEDTHRU_1_SE2A0_2", - "INT_FEEDTHRU_1_SE2A0_3", - "INT_FEEDTHRU_1_SE2A0_4", - "INT_FEEDTHRU_1_SE2A1", - "INT_FEEDTHRU_1_SE2A1_1", - "INT_FEEDTHRU_1_SE2A1_2", - "INT_FEEDTHRU_1_SE2A1_3", - "INT_FEEDTHRU_1_SE2A1_4", - "INT_FEEDTHRU_1_SE2A2", - "INT_FEEDTHRU_1_SE2A2_1", - "INT_FEEDTHRU_1_SE2A2_2", - "INT_FEEDTHRU_1_SE2A2_3", - "INT_FEEDTHRU_1_SE2A2_4", - "INT_FEEDTHRU_1_SE2A3", - "INT_FEEDTHRU_1_SE2A3_1", - "INT_FEEDTHRU_1_SE2A3_2", - "INT_FEEDTHRU_1_SE2A3_3", - "INT_FEEDTHRU_1_SE2A3_4", - "INT_FEEDTHRU_1_SE4BEG0", - "INT_FEEDTHRU_1_SE4BEG0_1", - "INT_FEEDTHRU_1_SE4BEG0_2", - "INT_FEEDTHRU_1_SE4BEG0_3", - "INT_FEEDTHRU_1_SE4BEG0_4", - "INT_FEEDTHRU_1_SE4BEG1", - "INT_FEEDTHRU_1_SE4BEG1_1", - "INT_FEEDTHRU_1_SE4BEG1_2", - "INT_FEEDTHRU_1_SE4BEG1_3", - "INT_FEEDTHRU_1_SE4BEG1_4", - "INT_FEEDTHRU_1_SE4BEG2", - "INT_FEEDTHRU_1_SE4BEG2_1", - "INT_FEEDTHRU_1_SE4BEG2_2", - "INT_FEEDTHRU_1_SE4BEG2_3", - "INT_FEEDTHRU_1_SE4BEG2_4", - "INT_FEEDTHRU_1_SE4BEG3", - "INT_FEEDTHRU_1_SE4BEG3_1", - "INT_FEEDTHRU_1_SE4BEG3_2", - "INT_FEEDTHRU_1_SE4BEG3_3", - "INT_FEEDTHRU_1_SE4BEG3_4", - "INT_FEEDTHRU_1_SE4C0", - "INT_FEEDTHRU_1_SE4C0_1", - "INT_FEEDTHRU_1_SE4C0_2", - "INT_FEEDTHRU_1_SE4C0_3", - "INT_FEEDTHRU_1_SE4C0_4", - "INT_FEEDTHRU_1_SE4C1", - "INT_FEEDTHRU_1_SE4C1_1", - "INT_FEEDTHRU_1_SE4C1_2", - "INT_FEEDTHRU_1_SE4C1_3", - "INT_FEEDTHRU_1_SE4C1_4", - "INT_FEEDTHRU_1_SE4C2", - "INT_FEEDTHRU_1_SE4C2_1", - "INT_FEEDTHRU_1_SE4C2_2", - "INT_FEEDTHRU_1_SE4C2_3", - "INT_FEEDTHRU_1_SE4C2_4", - "INT_FEEDTHRU_1_SE4C3", - "INT_FEEDTHRU_1_SE4C3_1", - "INT_FEEDTHRU_1_SE4C3_2", - "INT_FEEDTHRU_1_SE4C3_3", - "INT_FEEDTHRU_1_SE4C3_4", - "INT_FEEDTHRU_1_SW2A0", - "INT_FEEDTHRU_1_SW2A0_1", - "INT_FEEDTHRU_1_SW2A0_2", - "INT_FEEDTHRU_1_SW2A0_3", - "INT_FEEDTHRU_1_SW2A0_4", - "INT_FEEDTHRU_1_SW2A1", - "INT_FEEDTHRU_1_SW2A1_1", - "INT_FEEDTHRU_1_SW2A1_2", - "INT_FEEDTHRU_1_SW2A1_3", - "INT_FEEDTHRU_1_SW2A1_4", - "INT_FEEDTHRU_1_SW2A2", - "INT_FEEDTHRU_1_SW2A2_1", - "INT_FEEDTHRU_1_SW2A2_2", - "INT_FEEDTHRU_1_SW2A2_3", - "INT_FEEDTHRU_1_SW2A2_4", - "INT_FEEDTHRU_1_SW2A3", - "INT_FEEDTHRU_1_SW2A3_1", - "INT_FEEDTHRU_1_SW2A3_2", - "INT_FEEDTHRU_1_SW2A3_3", - "INT_FEEDTHRU_1_SW2A3_4", - "INT_FEEDTHRU_1_SW4A0", - "INT_FEEDTHRU_1_SW4A0_1", - "INT_FEEDTHRU_1_SW4A0_2", - "INT_FEEDTHRU_1_SW4A0_3", - "INT_FEEDTHRU_1_SW4A0_4", - "INT_FEEDTHRU_1_SW4A1", - "INT_FEEDTHRU_1_SW4A1_1", - "INT_FEEDTHRU_1_SW4A1_2", - "INT_FEEDTHRU_1_SW4A1_3", - "INT_FEEDTHRU_1_SW4A1_4", - "INT_FEEDTHRU_1_SW4A2", - "INT_FEEDTHRU_1_SW4A2_1", - "INT_FEEDTHRU_1_SW4A2_2", - "INT_FEEDTHRU_1_SW4A2_3", - "INT_FEEDTHRU_1_SW4A2_4", - "INT_FEEDTHRU_1_SW4A3", - "INT_FEEDTHRU_1_SW4A3_1", - "INT_FEEDTHRU_1_SW4A3_2", - "INT_FEEDTHRU_1_SW4A3_3", - "INT_FEEDTHRU_1_SW4A3_4", - "INT_FEEDTHRU_1_SW4END0", - "INT_FEEDTHRU_1_SW4END0_1", - "INT_FEEDTHRU_1_SW4END0_2", - "INT_FEEDTHRU_1_SW4END0_3", - "INT_FEEDTHRU_1_SW4END0_4", - "INT_FEEDTHRU_1_SW4END1", - "INT_FEEDTHRU_1_SW4END1_1", - "INT_FEEDTHRU_1_SW4END1_2", - "INT_FEEDTHRU_1_SW4END1_3", - "INT_FEEDTHRU_1_SW4END1_4", - "INT_FEEDTHRU_1_SW4END2", - "INT_FEEDTHRU_1_SW4END2_1", - "INT_FEEDTHRU_1_SW4END2_2", - "INT_FEEDTHRU_1_SW4END2_3", - "INT_FEEDTHRU_1_SW4END2_4", - "INT_FEEDTHRU_1_SW4END3", - "INT_FEEDTHRU_1_SW4END3_1", - "INT_FEEDTHRU_1_SW4END3_2", - "INT_FEEDTHRU_1_SW4END3_3", - "INT_FEEDTHRU_1_SW4END3_4", - "INT_FEEDTHRU_1_WL1END0", - "INT_FEEDTHRU_1_WL1END0_1", - "INT_FEEDTHRU_1_WL1END0_2", - "INT_FEEDTHRU_1_WL1END0_3", - "INT_FEEDTHRU_1_WL1END0_4", - "INT_FEEDTHRU_1_WL1END1", - "INT_FEEDTHRU_1_WL1END1_1", - "INT_FEEDTHRU_1_WL1END1_2", - "INT_FEEDTHRU_1_WL1END1_3", - "INT_FEEDTHRU_1_WL1END1_4", - "INT_FEEDTHRU_1_WL1END2", - "INT_FEEDTHRU_1_WL1END2_1", - "INT_FEEDTHRU_1_WL1END2_2", - "INT_FEEDTHRU_1_WL1END2_3", - "INT_FEEDTHRU_1_WL1END2_4", - "INT_FEEDTHRU_1_WL1END3", - "INT_FEEDTHRU_1_WL1END3_1", - "INT_FEEDTHRU_1_WL1END3_2", - "INT_FEEDTHRU_1_WL1END3_3", - "INT_FEEDTHRU_1_WL1END3_4", - "INT_FEEDTHRU_1_WR1END0", - "INT_FEEDTHRU_1_WR1END0_1", - "INT_FEEDTHRU_1_WR1END0_2", - "INT_FEEDTHRU_1_WR1END0_3", - "INT_FEEDTHRU_1_WR1END0_4", - "INT_FEEDTHRU_1_WR1END1", - "INT_FEEDTHRU_1_WR1END1_1", - "INT_FEEDTHRU_1_WR1END1_2", - "INT_FEEDTHRU_1_WR1END1_3", - "INT_FEEDTHRU_1_WR1END1_4", - "INT_FEEDTHRU_1_WR1END2", - "INT_FEEDTHRU_1_WR1END2_1", - "INT_FEEDTHRU_1_WR1END2_2", - "INT_FEEDTHRU_1_WR1END2_3", - "INT_FEEDTHRU_1_WR1END2_4", - "INT_FEEDTHRU_1_WR1END3", - "INT_FEEDTHRU_1_WR1END3_1", - "INT_FEEDTHRU_1_WR1END3_2", - "INT_FEEDTHRU_1_WR1END3_3", - "INT_FEEDTHRU_1_WR1END3_4", - "INT_FEEDTHRU_1_WW2A0", - "INT_FEEDTHRU_1_WW2A0_1", - "INT_FEEDTHRU_1_WW2A0_2", - "INT_FEEDTHRU_1_WW2A0_3", - "INT_FEEDTHRU_1_WW2A0_4", - "INT_FEEDTHRU_1_WW2A1", - "INT_FEEDTHRU_1_WW2A1_1", - "INT_FEEDTHRU_1_WW2A1_2", - "INT_FEEDTHRU_1_WW2A1_3", - "INT_FEEDTHRU_1_WW2A1_4", - "INT_FEEDTHRU_1_WW2A2", - "INT_FEEDTHRU_1_WW2A2_1", - "INT_FEEDTHRU_1_WW2A2_2", - "INT_FEEDTHRU_1_WW2A2_3", - "INT_FEEDTHRU_1_WW2A2_4", - "INT_FEEDTHRU_1_WW2A3", - "INT_FEEDTHRU_1_WW2A3_1", - "INT_FEEDTHRU_1_WW2A3_2", - "INT_FEEDTHRU_1_WW2A3_3", - "INT_FEEDTHRU_1_WW2A3_4", - "INT_FEEDTHRU_1_WW2END0", - "INT_FEEDTHRU_1_WW2END0_1", - "INT_FEEDTHRU_1_WW2END0_2", - "INT_FEEDTHRU_1_WW2END0_3", - "INT_FEEDTHRU_1_WW2END0_4", - "INT_FEEDTHRU_1_WW2END1", - "INT_FEEDTHRU_1_WW2END1_1", - "INT_FEEDTHRU_1_WW2END1_2", - "INT_FEEDTHRU_1_WW2END1_3", - "INT_FEEDTHRU_1_WW2END1_4", - "INT_FEEDTHRU_1_WW2END2", - "INT_FEEDTHRU_1_WW2END2_1", - "INT_FEEDTHRU_1_WW2END2_2", - "INT_FEEDTHRU_1_WW2END2_3", - "INT_FEEDTHRU_1_WW2END2_4", - "INT_FEEDTHRU_1_WW2END3", - "INT_FEEDTHRU_1_WW2END3_1", - "INT_FEEDTHRU_1_WW2END3_2", - "INT_FEEDTHRU_1_WW2END3_3", - "INT_FEEDTHRU_1_WW2END3_4", - "INT_FEEDTHRU_1_WW4A0", - "INT_FEEDTHRU_1_WW4A0_1", - "INT_FEEDTHRU_1_WW4A0_2", - "INT_FEEDTHRU_1_WW4A0_3", - "INT_FEEDTHRU_1_WW4A0_4", - "INT_FEEDTHRU_1_WW4A1", - "INT_FEEDTHRU_1_WW4A1_1", - "INT_FEEDTHRU_1_WW4A1_2", - "INT_FEEDTHRU_1_WW4A1_3", - "INT_FEEDTHRU_1_WW4A1_4", - "INT_FEEDTHRU_1_WW4A2", - "INT_FEEDTHRU_1_WW4A2_1", - "INT_FEEDTHRU_1_WW4A2_2", - "INT_FEEDTHRU_1_WW4A2_3", - "INT_FEEDTHRU_1_WW4A2_4", - "INT_FEEDTHRU_1_WW4A3", - "INT_FEEDTHRU_1_WW4A3_1", - "INT_FEEDTHRU_1_WW4A3_2", - "INT_FEEDTHRU_1_WW4A3_3", - "INT_FEEDTHRU_1_WW4A3_4", - "INT_FEEDTHRU_1_WW4B0", - "INT_FEEDTHRU_1_WW4B0_1", - "INT_FEEDTHRU_1_WW4B0_2", - "INT_FEEDTHRU_1_WW4B0_3", - "INT_FEEDTHRU_1_WW4B0_4", - "INT_FEEDTHRU_1_WW4B1", - "INT_FEEDTHRU_1_WW4B1_1", - "INT_FEEDTHRU_1_WW4B1_2", - "INT_FEEDTHRU_1_WW4B1_3", - "INT_FEEDTHRU_1_WW4B1_4", - "INT_FEEDTHRU_1_WW4B2", - "INT_FEEDTHRU_1_WW4B2_1", - "INT_FEEDTHRU_1_WW4B2_2", - "INT_FEEDTHRU_1_WW4B2_3", - "INT_FEEDTHRU_1_WW4B2_4", - "INT_FEEDTHRU_1_WW4B3", - "INT_FEEDTHRU_1_WW4B3_1", - "INT_FEEDTHRU_1_WW4B3_2", - "INT_FEEDTHRU_1_WW4B3_3", - "INT_FEEDTHRU_1_WW4B3_4", - "INT_FEEDTHRU_1_WW4C0", - "INT_FEEDTHRU_1_WW4C0_1", - "INT_FEEDTHRU_1_WW4C0_2", - "INT_FEEDTHRU_1_WW4C0_3", - "INT_FEEDTHRU_1_WW4C0_4", - "INT_FEEDTHRU_1_WW4C1", - "INT_FEEDTHRU_1_WW4C1_1", - "INT_FEEDTHRU_1_WW4C1_2", - "INT_FEEDTHRU_1_WW4C1_3", - "INT_FEEDTHRU_1_WW4C1_4", - "INT_FEEDTHRU_1_WW4C2", - "INT_FEEDTHRU_1_WW4C2_1", - "INT_FEEDTHRU_1_WW4C2_2", - "INT_FEEDTHRU_1_WW4C2_3", - "INT_FEEDTHRU_1_WW4C2_4", - "INT_FEEDTHRU_1_WW4C3", - "INT_FEEDTHRU_1_WW4C3_1", - "INT_FEEDTHRU_1_WW4C3_2", - "INT_FEEDTHRU_1_WW4C3_3", - "INT_FEEDTHRU_1_WW4C3_4", - "INT_FEEDTHRU_1_WW4END0", - "INT_FEEDTHRU_1_WW4END0_1", - "INT_FEEDTHRU_1_WW4END0_2", - "INT_FEEDTHRU_1_WW4END0_3", - "INT_FEEDTHRU_1_WW4END0_4", - "INT_FEEDTHRU_1_WW4END1", - "INT_FEEDTHRU_1_WW4END1_1", - "INT_FEEDTHRU_1_WW4END1_2", - "INT_FEEDTHRU_1_WW4END1_3", - "INT_FEEDTHRU_1_WW4END1_4", - "INT_FEEDTHRU_1_WW4END2", - "INT_FEEDTHRU_1_WW4END2_1", - "INT_FEEDTHRU_1_WW4END2_2", - "INT_FEEDTHRU_1_WW4END2_3", - "INT_FEEDTHRU_1_WW4END2_4", - "INT_FEEDTHRU_1_WW4END3", - "INT_FEEDTHRU_1_WW4END3_1", - "INT_FEEDTHRU_1_WW4END3_2", - "INT_FEEDTHRU_1_WW4END3_3", - "INT_FEEDTHRU_1_WW4END3_4", - "MONITOR_HORIZ_VAUXN4", - "MONITOR_HORIZ_VAUXP4", - "MONITOR_VERT_SHORT_VAUXN0", - "MONITOR_VERT_SHORT_VAUXN1", - "MONITOR_VERT_SHORT_VAUXN10", - "MONITOR_VERT_SHORT_VAUXN11", - "MONITOR_VERT_SHORT_VAUXN12", - "MONITOR_VERT_SHORT_VAUXN13", - "MONITOR_VERT_SHORT_VAUXN14", - "MONITOR_VERT_SHORT_VAUXN15", - "MONITOR_VERT_SHORT_VAUXN2", - "MONITOR_VERT_SHORT_VAUXN3", - "MONITOR_VERT_SHORT_VAUXN4", - "MONITOR_VERT_SHORT_VAUXN5", - "MONITOR_VERT_SHORT_VAUXN6", - "MONITOR_VERT_SHORT_VAUXN7", - "MONITOR_VERT_SHORT_VAUXN8", - "MONITOR_VERT_SHORT_VAUXN9", - "MONITOR_VERT_SHORT_VAUXP0", - "MONITOR_VERT_SHORT_VAUXP1", - "MONITOR_VERT_SHORT_VAUXP10", - "MONITOR_VERT_SHORT_VAUXP11", - "MONITOR_VERT_SHORT_VAUXP12", - "MONITOR_VERT_SHORT_VAUXP13", - "MONITOR_VERT_SHORT_VAUXP14", - "MONITOR_VERT_SHORT_VAUXP15", - "MONITOR_VERT_SHORT_VAUXP2", - "MONITOR_VERT_SHORT_VAUXP3", - "MONITOR_VERT_SHORT_VAUXP4", - "MONITOR_VERT_SHORT_VAUXP5", - "MONITOR_VERT_SHORT_VAUXP6", - "MONITOR_VERT_SHORT_VAUXP7", - "MONITOR_VERT_SHORT_VAUXP8", - "MONITOR_VERT_SHORT_VAUXP9" - ] + "wires": { + "INT_FEEDTHRU_1_EE2A0": null, + "INT_FEEDTHRU_1_EE2A0_1": null, + "INT_FEEDTHRU_1_EE2A0_2": null, + "INT_FEEDTHRU_1_EE2A0_3": null, + "INT_FEEDTHRU_1_EE2A0_4": null, + "INT_FEEDTHRU_1_EE2A1": null, + "INT_FEEDTHRU_1_EE2A1_1": null, + "INT_FEEDTHRU_1_EE2A1_2": null, + "INT_FEEDTHRU_1_EE2A1_3": null, + "INT_FEEDTHRU_1_EE2A1_4": null, + "INT_FEEDTHRU_1_EE2A2": null, + "INT_FEEDTHRU_1_EE2A2_1": null, + "INT_FEEDTHRU_1_EE2A2_2": null, + "INT_FEEDTHRU_1_EE2A2_3": null, + "INT_FEEDTHRU_1_EE2A2_4": null, + "INT_FEEDTHRU_1_EE2A3": null, + "INT_FEEDTHRU_1_EE2A3_1": null, + "INT_FEEDTHRU_1_EE2A3_2": null, + "INT_FEEDTHRU_1_EE2A3_3": null, + "INT_FEEDTHRU_1_EE2A3_4": null, + "INT_FEEDTHRU_1_EE2BEG0": null, + "INT_FEEDTHRU_1_EE2BEG0_1": null, + "INT_FEEDTHRU_1_EE2BEG0_2": null, + "INT_FEEDTHRU_1_EE2BEG0_3": null, + "INT_FEEDTHRU_1_EE2BEG0_4": null, + "INT_FEEDTHRU_1_EE2BEG1": null, + "INT_FEEDTHRU_1_EE2BEG1_1": null, + "INT_FEEDTHRU_1_EE2BEG1_2": null, + "INT_FEEDTHRU_1_EE2BEG1_3": null, + "INT_FEEDTHRU_1_EE2BEG1_4": null, + "INT_FEEDTHRU_1_EE2BEG2": null, + "INT_FEEDTHRU_1_EE2BEG2_1": null, + "INT_FEEDTHRU_1_EE2BEG2_2": null, + "INT_FEEDTHRU_1_EE2BEG2_3": null, + "INT_FEEDTHRU_1_EE2BEG2_4": null, + "INT_FEEDTHRU_1_EE2BEG3": null, + "INT_FEEDTHRU_1_EE2BEG3_1": null, + "INT_FEEDTHRU_1_EE2BEG3_2": null, + "INT_FEEDTHRU_1_EE2BEG3_3": null, + "INT_FEEDTHRU_1_EE2BEG3_4": null, + "INT_FEEDTHRU_1_EE4A0": null, + "INT_FEEDTHRU_1_EE4A0_1": null, + "INT_FEEDTHRU_1_EE4A0_2": null, + "INT_FEEDTHRU_1_EE4A0_3": null, + "INT_FEEDTHRU_1_EE4A0_4": null, + "INT_FEEDTHRU_1_EE4A1": null, + "INT_FEEDTHRU_1_EE4A1_1": null, + "INT_FEEDTHRU_1_EE4A1_2": null, + "INT_FEEDTHRU_1_EE4A1_3": null, + "INT_FEEDTHRU_1_EE4A1_4": null, + "INT_FEEDTHRU_1_EE4A2": null, + "INT_FEEDTHRU_1_EE4A2_1": null, + "INT_FEEDTHRU_1_EE4A2_2": null, + "INT_FEEDTHRU_1_EE4A2_3": null, + "INT_FEEDTHRU_1_EE4A2_4": null, + "INT_FEEDTHRU_1_EE4A3": null, + "INT_FEEDTHRU_1_EE4A3_1": null, + "INT_FEEDTHRU_1_EE4A3_2": null, + "INT_FEEDTHRU_1_EE4A3_3": null, + "INT_FEEDTHRU_1_EE4A3_4": null, + "INT_FEEDTHRU_1_EE4B0": null, + "INT_FEEDTHRU_1_EE4B0_1": null, + "INT_FEEDTHRU_1_EE4B0_2": null, + "INT_FEEDTHRU_1_EE4B0_3": null, + "INT_FEEDTHRU_1_EE4B0_4": null, + "INT_FEEDTHRU_1_EE4B1": null, + "INT_FEEDTHRU_1_EE4B1_1": null, + "INT_FEEDTHRU_1_EE4B1_2": null, + "INT_FEEDTHRU_1_EE4B1_3": null, + "INT_FEEDTHRU_1_EE4B1_4": null, + "INT_FEEDTHRU_1_EE4B2": null, + "INT_FEEDTHRU_1_EE4B2_1": null, + "INT_FEEDTHRU_1_EE4B2_2": null, + "INT_FEEDTHRU_1_EE4B2_3": null, + "INT_FEEDTHRU_1_EE4B2_4": null, + "INT_FEEDTHRU_1_EE4B3": null, + "INT_FEEDTHRU_1_EE4B3_1": null, + "INT_FEEDTHRU_1_EE4B3_2": null, + "INT_FEEDTHRU_1_EE4B3_3": null, + "INT_FEEDTHRU_1_EE4B3_4": null, + "INT_FEEDTHRU_1_EE4BEG0": null, + "INT_FEEDTHRU_1_EE4BEG0_1": null, + "INT_FEEDTHRU_1_EE4BEG0_2": null, + "INT_FEEDTHRU_1_EE4BEG0_3": null, + "INT_FEEDTHRU_1_EE4BEG0_4": null, + "INT_FEEDTHRU_1_EE4BEG1": null, + "INT_FEEDTHRU_1_EE4BEG1_1": null, + "INT_FEEDTHRU_1_EE4BEG1_2": null, + "INT_FEEDTHRU_1_EE4BEG1_3": null, + "INT_FEEDTHRU_1_EE4BEG1_4": null, + "INT_FEEDTHRU_1_EE4BEG2": null, + "INT_FEEDTHRU_1_EE4BEG2_1": null, + "INT_FEEDTHRU_1_EE4BEG2_2": null, + "INT_FEEDTHRU_1_EE4BEG2_3": null, + "INT_FEEDTHRU_1_EE4BEG2_4": null, + "INT_FEEDTHRU_1_EE4BEG3": null, + "INT_FEEDTHRU_1_EE4BEG3_1": null, + "INT_FEEDTHRU_1_EE4BEG3_2": null, + "INT_FEEDTHRU_1_EE4BEG3_3": null, + "INT_FEEDTHRU_1_EE4BEG3_4": null, + "INT_FEEDTHRU_1_EE4C0": null, + "INT_FEEDTHRU_1_EE4C0_1": null, + "INT_FEEDTHRU_1_EE4C0_2": null, + "INT_FEEDTHRU_1_EE4C0_3": null, + "INT_FEEDTHRU_1_EE4C0_4": null, + "INT_FEEDTHRU_1_EE4C1": null, + "INT_FEEDTHRU_1_EE4C1_1": null, + "INT_FEEDTHRU_1_EE4C1_2": null, + "INT_FEEDTHRU_1_EE4C1_3": null, + "INT_FEEDTHRU_1_EE4C1_4": null, + "INT_FEEDTHRU_1_EE4C2": null, + "INT_FEEDTHRU_1_EE4C2_1": null, + "INT_FEEDTHRU_1_EE4C2_2": null, + "INT_FEEDTHRU_1_EE4C2_3": null, + "INT_FEEDTHRU_1_EE4C2_4": null, + "INT_FEEDTHRU_1_EE4C3": null, + "INT_FEEDTHRU_1_EE4C3_1": null, + "INT_FEEDTHRU_1_EE4C3_2": null, + "INT_FEEDTHRU_1_EE4C3_3": null, + "INT_FEEDTHRU_1_EE4C3_4": null, + "INT_FEEDTHRU_1_EL1BEG0": null, + "INT_FEEDTHRU_1_EL1BEG0_1": null, + "INT_FEEDTHRU_1_EL1BEG0_2": null, + "INT_FEEDTHRU_1_EL1BEG0_3": null, + "INT_FEEDTHRU_1_EL1BEG0_4": null, + "INT_FEEDTHRU_1_EL1BEG1": null, + "INT_FEEDTHRU_1_EL1BEG1_1": null, + "INT_FEEDTHRU_1_EL1BEG1_2": null, + "INT_FEEDTHRU_1_EL1BEG1_3": null, + "INT_FEEDTHRU_1_EL1BEG1_4": null, + "INT_FEEDTHRU_1_EL1BEG2": null, + "INT_FEEDTHRU_1_EL1BEG2_1": null, + "INT_FEEDTHRU_1_EL1BEG2_2": null, + "INT_FEEDTHRU_1_EL1BEG2_3": null, + "INT_FEEDTHRU_1_EL1BEG2_4": null, + "INT_FEEDTHRU_1_EL1BEG3": null, + "INT_FEEDTHRU_1_EL1BEG3_1": null, + "INT_FEEDTHRU_1_EL1BEG3_2": null, + "INT_FEEDTHRU_1_EL1BEG3_3": null, + "INT_FEEDTHRU_1_EL1BEG3_4": null, + "INT_FEEDTHRU_1_ER1BEG0": null, + "INT_FEEDTHRU_1_ER1BEG0_1": null, + "INT_FEEDTHRU_1_ER1BEG0_2": null, + "INT_FEEDTHRU_1_ER1BEG0_3": null, + "INT_FEEDTHRU_1_ER1BEG0_4": null, + "INT_FEEDTHRU_1_ER1BEG1": null, + "INT_FEEDTHRU_1_ER1BEG1_1": null, + "INT_FEEDTHRU_1_ER1BEG1_2": null, + "INT_FEEDTHRU_1_ER1BEG1_3": null, + "INT_FEEDTHRU_1_ER1BEG1_4": null, + "INT_FEEDTHRU_1_ER1BEG2": null, + "INT_FEEDTHRU_1_ER1BEG2_1": null, + "INT_FEEDTHRU_1_ER1BEG2_2": null, + "INT_FEEDTHRU_1_ER1BEG2_3": null, + "INT_FEEDTHRU_1_ER1BEG2_4": null, + "INT_FEEDTHRU_1_ER1BEG3": null, + "INT_FEEDTHRU_1_ER1BEG3_1": null, + "INT_FEEDTHRU_1_ER1BEG3_2": null, + "INT_FEEDTHRU_1_ER1BEG3_3": null, + "INT_FEEDTHRU_1_ER1BEG3_4": null, + "INT_FEEDTHRU_1_LH1": null, + "INT_FEEDTHRU_1_LH10": null, + "INT_FEEDTHRU_1_LH10_1": null, + "INT_FEEDTHRU_1_LH10_2": null, + "INT_FEEDTHRU_1_LH10_3": null, + "INT_FEEDTHRU_1_LH10_4": null, + "INT_FEEDTHRU_1_LH11": null, + "INT_FEEDTHRU_1_LH11_1": null, + "INT_FEEDTHRU_1_LH11_2": null, + "INT_FEEDTHRU_1_LH11_3": null, + "INT_FEEDTHRU_1_LH11_4": null, + "INT_FEEDTHRU_1_LH12": null, + "INT_FEEDTHRU_1_LH12_1": null, + "INT_FEEDTHRU_1_LH12_2": null, + "INT_FEEDTHRU_1_LH12_3": null, + "INT_FEEDTHRU_1_LH12_4": null, + "INT_FEEDTHRU_1_LH1_1": null, + "INT_FEEDTHRU_1_LH1_2": null, + "INT_FEEDTHRU_1_LH1_3": null, + "INT_FEEDTHRU_1_LH1_4": null, + "INT_FEEDTHRU_1_LH2": null, + "INT_FEEDTHRU_1_LH2_1": null, + "INT_FEEDTHRU_1_LH2_2": null, + "INT_FEEDTHRU_1_LH2_3": null, + "INT_FEEDTHRU_1_LH2_4": null, + "INT_FEEDTHRU_1_LH3": null, + "INT_FEEDTHRU_1_LH3_1": null, + "INT_FEEDTHRU_1_LH3_2": null, + "INT_FEEDTHRU_1_LH3_3": null, + "INT_FEEDTHRU_1_LH3_4": null, + "INT_FEEDTHRU_1_LH4": null, + "INT_FEEDTHRU_1_LH4_1": null, + "INT_FEEDTHRU_1_LH4_2": null, + "INT_FEEDTHRU_1_LH4_3": null, + "INT_FEEDTHRU_1_LH4_4": null, + "INT_FEEDTHRU_1_LH5": null, + "INT_FEEDTHRU_1_LH5_1": null, + "INT_FEEDTHRU_1_LH5_2": null, + "INT_FEEDTHRU_1_LH5_3": null, + "INT_FEEDTHRU_1_LH5_4": null, + "INT_FEEDTHRU_1_LH6": null, + "INT_FEEDTHRU_1_LH6_1": null, + "INT_FEEDTHRU_1_LH6_2": null, + "INT_FEEDTHRU_1_LH6_3": null, + "INT_FEEDTHRU_1_LH6_4": null, + "INT_FEEDTHRU_1_LH7": null, + "INT_FEEDTHRU_1_LH7_1": null, + "INT_FEEDTHRU_1_LH7_2": null, + "INT_FEEDTHRU_1_LH7_3": null, + "INT_FEEDTHRU_1_LH7_4": null, + "INT_FEEDTHRU_1_LH8": null, + "INT_FEEDTHRU_1_LH8_1": null, + "INT_FEEDTHRU_1_LH8_2": null, + "INT_FEEDTHRU_1_LH8_3": null, + "INT_FEEDTHRU_1_LH8_4": null, + "INT_FEEDTHRU_1_LH9": null, + "INT_FEEDTHRU_1_LH9_1": null, + "INT_FEEDTHRU_1_LH9_2": null, + "INT_FEEDTHRU_1_LH9_3": null, + "INT_FEEDTHRU_1_LH9_4": null, + "INT_FEEDTHRU_1_MONITOR_N": null, + "INT_FEEDTHRU_1_MONITOR_N_2": null, + "INT_FEEDTHRU_1_MONITOR_N_3": null, + "INT_FEEDTHRU_1_MONITOR_N_4": null, + "INT_FEEDTHRU_1_MONITOR_P": null, + "INT_FEEDTHRU_1_MONITOR_P_2": null, + "INT_FEEDTHRU_1_MONITOR_P_3": null, + "INT_FEEDTHRU_1_MONITOR_P_4": null, + "INT_FEEDTHRU_1_NE2A0": null, + "INT_FEEDTHRU_1_NE2A0_1": null, + "INT_FEEDTHRU_1_NE2A0_2": null, + "INT_FEEDTHRU_1_NE2A0_3": null, + "INT_FEEDTHRU_1_NE2A0_4": null, + "INT_FEEDTHRU_1_NE2A1": null, + "INT_FEEDTHRU_1_NE2A1_1": null, + "INT_FEEDTHRU_1_NE2A1_2": null, + "INT_FEEDTHRU_1_NE2A1_3": null, + "INT_FEEDTHRU_1_NE2A1_4": null, + "INT_FEEDTHRU_1_NE2A2": null, + "INT_FEEDTHRU_1_NE2A2_1": null, + "INT_FEEDTHRU_1_NE2A2_2": null, + "INT_FEEDTHRU_1_NE2A2_3": null, + "INT_FEEDTHRU_1_NE2A2_4": null, + "INT_FEEDTHRU_1_NE2A3": null, + "INT_FEEDTHRU_1_NE2A3_1": null, + "INT_FEEDTHRU_1_NE2A3_2": null, + "INT_FEEDTHRU_1_NE2A3_3": null, + "INT_FEEDTHRU_1_NE2A3_4": null, + "INT_FEEDTHRU_1_NE4BEG0": null, + "INT_FEEDTHRU_1_NE4BEG0_1": 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"MONITOR_VERT_SHORT_VAUXP14": null, + "MONITOR_VERT_SHORT_VAUXP15": null, + "MONITOR_VERT_SHORT_VAUXP2": null, + "MONITOR_VERT_SHORT_VAUXP3": null, + "MONITOR_VERT_SHORT_VAUXP4": null, + "MONITOR_VERT_SHORT_VAUXP5": null, + "MONITOR_VERT_SHORT_VAUXP6": null, + "MONITOR_VERT_SHORT_VAUXP7": null, + "MONITOR_VERT_SHORT_VAUXP8": null, + "MONITOR_VERT_SHORT_VAUXP9": null + } } diff --git a/zynq7/tile_type_CLBLL_L.json b/zynq7/tile_type_CLBLL_L.json index d0ef2e2..b19a926 100644 --- a/zynq7/tile_type_CLBLL_L.json +++ b/zynq7/tile_type_CLBLL_L.json @@ -2,1024 +2,3210 @@ "pips": { "CLBLL_L.CLBLL_BYP0->CLBLL_L_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP0" }, "CLBLL_L.CLBLL_BYP1->CLBLL_LL_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP1" }, "CLBLL_L.CLBLL_BYP2->CLBLL_L_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP2" }, "CLBLL_L.CLBLL_BYP3->CLBLL_LL_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP3" }, "CLBLL_L.CLBLL_BYP4->CLBLL_LL_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP4" }, "CLBLL_L.CLBLL_BYP5->CLBLL_L_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP5" }, "CLBLL_L.CLBLL_BYP6->CLBLL_LL_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP6" }, "CLBLL_L.CLBLL_BYP7->CLBLL_L_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP7" }, "CLBLL_L.CLBLL_CLK0->CLBLL_L_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CLK0" }, "CLBLL_L.CLBLL_CLK1->CLBLL_LL_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CLK1" }, "CLBLL_L.CLBLL_CTRL0->CLBLL_L_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CTRL0" }, "CLBLL_L.CLBLL_CTRL1->CLBLL_LL_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CTRL1" }, "CLBLL_L.CLBLL_FAN6->CLBLL_L_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_FAN6" }, "CLBLL_L.CLBLL_FAN7->CLBLL_LL_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_FAN7" }, "CLBLL_L.CLBLL_IMUX0->CLBLL_L_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX0" }, "CLBLL_L.CLBLL_IMUX1->CLBLL_LL_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX1" }, "CLBLL_L.CLBLL_IMUX10->CLBLL_L_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX10" }, "CLBLL_L.CLBLL_IMUX11->CLBLL_LL_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX11" }, "CLBLL_L.CLBLL_IMUX12->CLBLL_LL_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX12" }, "CLBLL_L.CLBLL_IMUX13->CLBLL_L_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX13" }, "CLBLL_L.CLBLL_IMUX14->CLBLL_L_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX14" }, "CLBLL_L.CLBLL_IMUX15->CLBLL_LL_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX15" }, "CLBLL_L.CLBLL_IMUX16->CLBLL_L_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX16" }, "CLBLL_L.CLBLL_IMUX17->CLBLL_LL_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX17" }, "CLBLL_L.CLBLL_IMUX18->CLBLL_LL_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX18" }, "CLBLL_L.CLBLL_IMUX19->CLBLL_L_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX19" }, "CLBLL_L.CLBLL_IMUX2->CLBLL_LL_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX2" }, "CLBLL_L.CLBLL_IMUX20->CLBLL_L_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX20" }, "CLBLL_L.CLBLL_IMUX21->CLBLL_L_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX21" }, "CLBLL_L.CLBLL_IMUX22->CLBLL_LL_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX22" }, "CLBLL_L.CLBLL_IMUX23->CLBLL_L_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX23" }, "CLBLL_L.CLBLL_IMUX24->CLBLL_LL_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX24" }, "CLBLL_L.CLBLL_IMUX25->CLBLL_L_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX25" }, "CLBLL_L.CLBLL_IMUX26->CLBLL_L_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX26" }, "CLBLL_L.CLBLL_IMUX27->CLBLL_LL_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX27" }, "CLBLL_L.CLBLL_IMUX28->CLBLL_LL_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX28" }, "CLBLL_L.CLBLL_IMUX29->CLBLL_LL_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX29" }, "CLBLL_L.CLBLL_IMUX3->CLBLL_L_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX3" }, "CLBLL_L.CLBLL_IMUX30->CLBLL_L_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX30" }, "CLBLL_L.CLBLL_IMUX31->CLBLL_LL_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX31" }, "CLBLL_L.CLBLL_IMUX32->CLBLL_LL_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX32" }, "CLBLL_L.CLBLL_IMUX33->CLBLL_L_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX33" }, "CLBLL_L.CLBLL_IMUX34->CLBLL_L_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX34" }, "CLBLL_L.CLBLL_IMUX35->CLBLL_LL_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX35" }, "CLBLL_L.CLBLL_IMUX36->CLBLL_L_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX36" }, "CLBLL_L.CLBLL_IMUX37->CLBLL_L_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX37" }, "CLBLL_L.CLBLL_IMUX38->CLBLL_LL_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX38" }, "CLBLL_L.CLBLL_IMUX39->CLBLL_L_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX39" }, "CLBLL_L.CLBLL_IMUX4->CLBLL_LL_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX4" }, "CLBLL_L.CLBLL_IMUX40->CLBLL_LL_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX40" }, "CLBLL_L.CLBLL_IMUX41->CLBLL_L_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX41" }, "CLBLL_L.CLBLL_IMUX42->CLBLL_L_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX42" }, "CLBLL_L.CLBLL_IMUX43->CLBLL_LL_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX43" }, "CLBLL_L.CLBLL_IMUX44->CLBLL_LL_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX44" }, "CLBLL_L.CLBLL_IMUX45->CLBLL_LL_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX45" }, "CLBLL_L.CLBLL_IMUX46->CLBLL_L_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX46" }, "CLBLL_L.CLBLL_IMUX47->CLBLL_LL_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX47" }, "CLBLL_L.CLBLL_IMUX5->CLBLL_L_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX5" }, "CLBLL_L.CLBLL_IMUX6->CLBLL_L_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX6" }, "CLBLL_L.CLBLL_IMUX7->CLBLL_LL_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX7" }, "CLBLL_L.CLBLL_IMUX8->CLBLL_LL_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX8" }, "CLBLL_L.CLBLL_IMUX9->CLBLL_L_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX9" }, "CLBLL_L.CLBLL_LL_A->>CLBLL_LL_AMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.071", + "0.088", + "0.168", + "0.209" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_AMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.071", + "0.088", + "0.168", + "0.209" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A" }, "CLBLL_L.CLBLL_LL_A->CLBLL_LOGIC_OUTS12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_LL_A" }, "CLBLL_L.CLBLL_LL_A1->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A1" }, "CLBLL_L.CLBLL_LL_A2->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A2" }, "CLBLL_L.CLBLL_LL_A3->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A3" }, "CLBLL_L.CLBLL_LL_A4->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A4" }, "CLBLL_L.CLBLL_LL_A5->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A5" }, "CLBLL_L.CLBLL_LL_A6->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A6" }, "CLBLL_L.CLBLL_LL_AMUX->CLBLL_LOGIC_OUTS20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_LL_AMUX" }, "CLBLL_L.CLBLL_LL_AQ->CLBLL_LOGIC_OUTS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_LL_AQ" }, "CLBLL_L.CLBLL_LL_B->>CLBLL_LL_BMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.073", + "0.091", + "0.168", + "0.208" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_BMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.073", + "0.091", + "0.168", + "0.208" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_B" }, "CLBLL_L.CLBLL_LL_B->CLBLL_LOGIC_OUTS13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_LL_B" }, "CLBLL_L.CLBLL_LL_B1->>CLBLL_LL_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + 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"CLBLL_L_A6" }, "CLBLL_L.CLBLL_L_AMUX->CLBLL_LOGIC_OUTS16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_AMUX" }, "CLBLL_L.CLBLL_L_AQ->CLBLL_LOGIC_OUTS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_AQ" }, "CLBLL_L.CLBLL_L_B->>CLBLL_L_BMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.073", + "0.091", + "0.168", + "0.208" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_BMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.073", + "0.091", + "0.168", + "0.208" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B" }, "CLBLL_L.CLBLL_L_B->CLBLL_LOGIC_OUTS9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_B" }, "CLBLL_L.CLBLL_L_B1->>CLBLL_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B1" }, "CLBLL_L.CLBLL_L_B2->>CLBLL_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B2" }, "CLBLL_L.CLBLL_L_B3->>CLBLL_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B3" }, "CLBLL_L.CLBLL_L_B4->>CLBLL_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B4" }, "CLBLL_L.CLBLL_L_B5->>CLBLL_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B5" }, "CLBLL_L.CLBLL_L_B6->>CLBLL_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B6" }, "CLBLL_L.CLBLL_L_BMUX->CLBLL_LOGIC_OUTS17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_BMUX" }, "CLBLL_L.CLBLL_L_BQ->CLBLL_LOGIC_OUTS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_BQ" }, "CLBLL_L.CLBLL_L_C->>CLBLL_L_CMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.069", + "0.086", + "0.166", + "0.205" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_CMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.069", + "0.086", + "0.166", + "0.205" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C" }, "CLBLL_L.CLBLL_L_C->CLBLL_LOGIC_OUTS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_C" }, "CLBLL_L.CLBLL_L_C1->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C1" }, "CLBLL_L.CLBLL_L_C2->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C2" }, "CLBLL_L.CLBLL_L_C3->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C3" }, "CLBLL_L.CLBLL_L_C4->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C4" }, "CLBLL_L.CLBLL_L_C5->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C5" }, "CLBLL_L.CLBLL_L_C6->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C6" }, "CLBLL_L.CLBLL_L_CMUX->CLBLL_LOGIC_OUTS18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_CMUX" }, "CLBLL_L.CLBLL_L_COUT->>CLBLL_L_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.131", + "0.246", + "0.305" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.105", + "0.131", + "0.246", + "0.305" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_COUT" }, "CLBLL_L.CLBLL_L_COUT->CLBLL_L_COUT_N": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_COUT_N", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_COUT" }, "CLBLL_L.CLBLL_L_CQ->CLBLL_LOGIC_OUTS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_CQ" }, "CLBLL_L.CLBLL_L_D->>CLBLL_L_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.075", + "0.093", + "0.170", + "0.211" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.075", + "0.093", + "0.170", + "0.211" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D" }, "CLBLL_L.CLBLL_L_D->CLBLL_LOGIC_OUTS11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_D" }, "CLBLL_L.CLBLL_L_D1->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D1" }, "CLBLL_L.CLBLL_L_D2->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D2" }, "CLBLL_L.CLBLL_L_D3->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D3" }, "CLBLL_L.CLBLL_L_D4->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D4" }, "CLBLL_L.CLBLL_L_D5->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D5" }, "CLBLL_L.CLBLL_L_D6->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D6" }, "CLBLL_L.CLBLL_L_DMUX->CLBLL_LOGIC_OUTS19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_DMUX" }, "CLBLL_L.CLBLL_L_DQ->CLBLL_LOGIC_OUTS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_DQ" } }, @@ -1028,51 +3214,456 @@ "name": "X1Y0", "prefix": "SLICE", "site_pins": { - "A": "CLBLL_L_A", - "A1": "CLBLL_L_A1", - "A2": "CLBLL_L_A2", - "A3": "CLBLL_L_A3", - "A4": "CLBLL_L_A4", - "A5": "CLBLL_L_A5", - "A6": "CLBLL_L_A6", - "AMUX": "CLBLL_L_AMUX", - "AQ": "CLBLL_L_AQ", - "AX": "CLBLL_L_AX", - "B": "CLBLL_L_B", - "B1": "CLBLL_L_B1", - "B2": "CLBLL_L_B2", - "B3": "CLBLL_L_B3", - "B4": "CLBLL_L_B4", - "B5": "CLBLL_L_B5", - "B6": "CLBLL_L_B6", - "BMUX": "CLBLL_L_BMUX", - "BQ": "CLBLL_L_BQ", - "BX": "CLBLL_L_BX", - "C": "CLBLL_L_C", - "C1": "CLBLL_L_C1", - "C2": "CLBLL_L_C2", - "C3": "CLBLL_L_C3", - "C4": "CLBLL_L_C4", - "C5": "CLBLL_L_C5", - "C6": "CLBLL_L_C6", - "CE": "CLBLL_L_CE", - "CIN": "CLBLL_L_CIN", - "CLK": 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"0.000" + ], + "res": "1408.0", + "wire": "CLBLL_LL_D" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.174", + "0.216", + "0.421", + "0.522" + ], + "wire": "CLBLL_LL_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.171", + "0.213", + "0.410", + "0.509" + ], + "wire": "CLBLL_LL_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.109", + "0.136", + "0.279", + "0.346" + ], + "wire": "CLBLL_LL_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.088", + "0.109", + "0.229", + "0.284" + ], + "wire": "CLBLL_LL_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.033", + "0.042", + "0.091", + "0.113" + ], + "wire": "CLBLL_LL_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.003", + "0.003", + "0.004", + "0.005" + ], + "wire": "CLBLL_LL_D6" + }, + "DMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1826.7858125", + "wire": "CLBLL_LL_DMUX" + }, + "DQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLL_LL_DQ" + }, + "DX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLL_LL_DX" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLL_LL_SR" + } }, "type": "SLICEL", "x_coord": 0, @@ -1134,316 +4130,490 @@ } ], "tile_type": "CLBLL_L", - "wires": [ - "CLBLL_BYP0", - "CLBLL_BYP1", - "CLBLL_BYP2", - "CLBLL_BYP3", - "CLBLL_BYP4", - "CLBLL_BYP5", - "CLBLL_BYP6", - "CLBLL_BYP7", - "CLBLL_CLK0", - "CLBLL_CLK1", - "CLBLL_CTRL0", - "CLBLL_CTRL1", - "CLBLL_EE2A0", - "CLBLL_EE2A1", - "CLBLL_EE2A2", - "CLBLL_EE2A3", - "CLBLL_EE2BEG0", - "CLBLL_EE2BEG1", - "CLBLL_EE2BEG2", - "CLBLL_EE2BEG3", - "CLBLL_EE4A0", - "CLBLL_EE4A1", - "CLBLL_EE4A2", - "CLBLL_EE4A3", - "CLBLL_EE4B0", - "CLBLL_EE4B1", - "CLBLL_EE4B2", - "CLBLL_EE4B3", - "CLBLL_EE4BEG0", - "CLBLL_EE4BEG1", - "CLBLL_EE4BEG2", - "CLBLL_EE4BEG3", - "CLBLL_EE4C0", - "CLBLL_EE4C1", - "CLBLL_EE4C2", - "CLBLL_EE4C3", - "CLBLL_EL1BEG0", - "CLBLL_EL1BEG1", - "CLBLL_EL1BEG2", - "CLBLL_EL1BEG3", - "CLBLL_ER1BEG0", - "CLBLL_ER1BEG1", - "CLBLL_ER1BEG2", - "CLBLL_ER1BEG3", - "CLBLL_FAN0", - "CLBLL_FAN1", - "CLBLL_FAN2", - "CLBLL_FAN3", - "CLBLL_FAN4", - "CLBLL_FAN5", - "CLBLL_FAN6", - "CLBLL_FAN7", - "CLBLL_IMUX0", - "CLBLL_IMUX1", - "CLBLL_IMUX10", - "CLBLL_IMUX11", - "CLBLL_IMUX12", - "CLBLL_IMUX13", - "CLBLL_IMUX14", - "CLBLL_IMUX15", - "CLBLL_IMUX16", - "CLBLL_IMUX17", - "CLBLL_IMUX18", - "CLBLL_IMUX19", - "CLBLL_IMUX2", - "CLBLL_IMUX20", - "CLBLL_IMUX21", - "CLBLL_IMUX22", - "CLBLL_IMUX23", - "CLBLL_IMUX24", - "CLBLL_IMUX25", - "CLBLL_IMUX26", - "CLBLL_IMUX27", - "CLBLL_IMUX28", - "CLBLL_IMUX29", - "CLBLL_IMUX3", - "CLBLL_IMUX30", - "CLBLL_IMUX31", - "CLBLL_IMUX32", - "CLBLL_IMUX33", - "CLBLL_IMUX34", - "CLBLL_IMUX35", - "CLBLL_IMUX36", - "CLBLL_IMUX37", - "CLBLL_IMUX38", - "CLBLL_IMUX39", - "CLBLL_IMUX4", - "CLBLL_IMUX40", - "CLBLL_IMUX41", - "CLBLL_IMUX42", - "CLBLL_IMUX43", - "CLBLL_IMUX44", - "CLBLL_IMUX45", - "CLBLL_IMUX46", - "CLBLL_IMUX47", - "CLBLL_IMUX5", - "CLBLL_IMUX6", - "CLBLL_IMUX7", - "CLBLL_IMUX8", - "CLBLL_IMUX9", - "CLBLL_LH1", - "CLBLL_LH10", - "CLBLL_LH11", - "CLBLL_LH12", - "CLBLL_LH2", - "CLBLL_LH3", - "CLBLL_LH4", - "CLBLL_LH5", - "CLBLL_LH6", - "CLBLL_LH7", - "CLBLL_LH8", - "CLBLL_LH9", - "CLBLL_LL_A", - "CLBLL_LL_A1", - "CLBLL_LL_A2", - "CLBLL_LL_A3", - "CLBLL_LL_A4", - "CLBLL_LL_A5", - "CLBLL_LL_A6", - "CLBLL_LL_AMUX", - "CLBLL_LL_AQ", - "CLBLL_LL_AX", - "CLBLL_LL_B", - "CLBLL_LL_B1", - "CLBLL_LL_B2", - "CLBLL_LL_B3", - "CLBLL_LL_B4", - "CLBLL_LL_B5", - "CLBLL_LL_B6", - "CLBLL_LL_BMUX", - "CLBLL_LL_BQ", - "CLBLL_LL_BX", - "CLBLL_LL_C", - "CLBLL_LL_C1", - "CLBLL_LL_C2", - "CLBLL_LL_C3", - "CLBLL_LL_C4", - "CLBLL_LL_C5", - "CLBLL_LL_C6", - "CLBLL_LL_CE", - "CLBLL_LL_CIN", - "CLBLL_LL_CLK", - "CLBLL_LL_CMUX", - "CLBLL_LL_COUT", - "CLBLL_LL_COUT_N", - "CLBLL_LL_CQ", - "CLBLL_LL_CX", - "CLBLL_LL_D", - "CLBLL_LL_D1", - "CLBLL_LL_D2", - "CLBLL_LL_D3", - "CLBLL_LL_D4", - "CLBLL_LL_D5", - "CLBLL_LL_D6", - "CLBLL_LL_DMUX", - "CLBLL_LL_DQ", - "CLBLL_LL_DX", - "CLBLL_LL_SR", - "CLBLL_LOGIC_OUTS0", - "CLBLL_LOGIC_OUTS1", - "CLBLL_LOGIC_OUTS10", - "CLBLL_LOGIC_OUTS11", - "CLBLL_LOGIC_OUTS12", - "CLBLL_LOGIC_OUTS13", - "CLBLL_LOGIC_OUTS14", - "CLBLL_LOGIC_OUTS15", - "CLBLL_LOGIC_OUTS16", - "CLBLL_LOGIC_OUTS17", - "CLBLL_LOGIC_OUTS18", - "CLBLL_LOGIC_OUTS19", - "CLBLL_LOGIC_OUTS2", - "CLBLL_LOGIC_OUTS20", - "CLBLL_LOGIC_OUTS21", - "CLBLL_LOGIC_OUTS22", - "CLBLL_LOGIC_OUTS23", - "CLBLL_LOGIC_OUTS3", - "CLBLL_LOGIC_OUTS4", - "CLBLL_LOGIC_OUTS5", - "CLBLL_LOGIC_OUTS6", - "CLBLL_LOGIC_OUTS7", - "CLBLL_LOGIC_OUTS8", - "CLBLL_LOGIC_OUTS9", - "CLBLL_L_A", - "CLBLL_L_A1", - "CLBLL_L_A2", - "CLBLL_L_A3", - "CLBLL_L_A4", - "CLBLL_L_A5", - "CLBLL_L_A6", - "CLBLL_L_AMUX", - "CLBLL_L_AQ", - "CLBLL_L_AX", - "CLBLL_L_B", - "CLBLL_L_B1", - "CLBLL_L_B2", - "CLBLL_L_B3", - "CLBLL_L_B4", - "CLBLL_L_B5", - "CLBLL_L_B6", - "CLBLL_L_BMUX", - "CLBLL_L_BQ", - "CLBLL_L_BX", - "CLBLL_L_C", - "CLBLL_L_C1", - "CLBLL_L_C2", - "CLBLL_L_C3", - "CLBLL_L_C4", - "CLBLL_L_C5", - "CLBLL_L_C6", - "CLBLL_L_CE", - "CLBLL_L_CIN", - "CLBLL_L_CLK", - "CLBLL_L_CMUX", - "CLBLL_L_COUT", - "CLBLL_L_COUT_N", - "CLBLL_L_CQ", - "CLBLL_L_CX", - "CLBLL_L_D", - "CLBLL_L_D1", - "CLBLL_L_D2", - "CLBLL_L_D3", - "CLBLL_L_D4", - "CLBLL_L_D5", - "CLBLL_L_D6", - "CLBLL_L_DMUX", - "CLBLL_L_DQ", - "CLBLL_L_DX", - "CLBLL_L_SR", - "CLBLL_MONITOR_N", - "CLBLL_MONITOR_P", - "CLBLL_NE2A0", - "CLBLL_NE2A1", - "CLBLL_NE2A2", - "CLBLL_NE2A3", - "CLBLL_NE4BEG0", - "CLBLL_NE4BEG1", - "CLBLL_NE4BEG2", - "CLBLL_NE4BEG3", - "CLBLL_NE4C0", - "CLBLL_NE4C1", - "CLBLL_NE4C2", - "CLBLL_NE4C3", - "CLBLL_NW2A0", - "CLBLL_NW2A1", - "CLBLL_NW2A2", - "CLBLL_NW2A3", - "CLBLL_NW4A0", - "CLBLL_NW4A1", - "CLBLL_NW4A2", - "CLBLL_NW4A3", - "CLBLL_NW4END0", - "CLBLL_NW4END1", - "CLBLL_NW4END2", - "CLBLL_NW4END3", - "CLBLL_SE2A0", - "CLBLL_SE2A1", - "CLBLL_SE2A2", - "CLBLL_SE2A3", - "CLBLL_SE4BEG0", - "CLBLL_SE4BEG1", - "CLBLL_SE4BEG2", - "CLBLL_SE4BEG3", - "CLBLL_SE4C0", - "CLBLL_SE4C1", - "CLBLL_SE4C2", - "CLBLL_SE4C3", - "CLBLL_SW2A0", - "CLBLL_SW2A1", - "CLBLL_SW2A2", - "CLBLL_SW2A3", - "CLBLL_SW4A0", - "CLBLL_SW4A1", - "CLBLL_SW4A2", - "CLBLL_SW4A3", - "CLBLL_SW4END0", - "CLBLL_SW4END1", - "CLBLL_SW4END2", - "CLBLL_SW4END3", - "CLBLL_WL1END0", - "CLBLL_WL1END1", - "CLBLL_WL1END2", - "CLBLL_WL1END3", - "CLBLL_WR1END0", - "CLBLL_WR1END1", - "CLBLL_WR1END2", - "CLBLL_WR1END3", - "CLBLL_WW2A0", - "CLBLL_WW2A1", - "CLBLL_WW2A2", - "CLBLL_WW2A3", - "CLBLL_WW2END0", - "CLBLL_WW2END1", - "CLBLL_WW2END2", - "CLBLL_WW2END3", - "CLBLL_WW4A0", - "CLBLL_WW4A1", - "CLBLL_WW4A2", - "CLBLL_WW4A3", - "CLBLL_WW4B0", - "CLBLL_WW4B1", - "CLBLL_WW4B2", - "CLBLL_WW4B3", - "CLBLL_WW4C0", - "CLBLL_WW4C1", - "CLBLL_WW4C2", - "CLBLL_WW4C3", - "CLBLL_WW4END0", - "CLBLL_WW4END1", - "CLBLL_WW4END2", - "CLBLL_WW4END3" - ] + "wires": { + "CLBLL_BYP0": null, + "CLBLL_BYP1": null, + "CLBLL_BYP2": null, + "CLBLL_BYP3": null, + "CLBLL_BYP4": null, + "CLBLL_BYP5": null, + "CLBLL_BYP6": null, + "CLBLL_BYP7": null, + "CLBLL_CLK0": null, + "CLBLL_CLK1": null, + "CLBLL_CTRL0": null, + "CLBLL_CTRL1": null, + "CLBLL_EE2A0": null, + "CLBLL_EE2A1": null, + "CLBLL_EE2A2": null, + "CLBLL_EE2A3": null, + "CLBLL_EE2BEG0": null, + "CLBLL_EE2BEG1": null, + "CLBLL_EE2BEG2": null, + "CLBLL_EE2BEG3": null, + "CLBLL_EE4A0": null, + "CLBLL_EE4A1": null, + "CLBLL_EE4A2": null, + "CLBLL_EE4A3": null, + "CLBLL_EE4B0": null, + "CLBLL_EE4B1": null, + "CLBLL_EE4B2": null, + "CLBLL_EE4B3": null, + "CLBLL_EE4BEG0": null, + "CLBLL_EE4BEG1": null, + "CLBLL_EE4BEG2": null, + "CLBLL_EE4BEG3": null, + "CLBLL_EE4C0": null, + "CLBLL_EE4C1": null, + "CLBLL_EE4C2": null, + "CLBLL_EE4C3": null, + "CLBLL_EL1BEG0": { + "cap": "4.690", + "res": "45.632" + }, + "CLBLL_EL1BEG1": { + "cap": "4.690", + "res": "45.632" + }, + "CLBLL_EL1BEG2": { + "cap": "4.690", + "res": "45.632" + }, + "CLBLL_EL1BEG3": { + "cap": "4.690", + "res": "45.632" + }, + "CLBLL_ER1BEG0": { + "cap": "5.564", + "res": "79.184" + }, + "CLBLL_ER1BEG1": { + "cap": "5.564", + "res": "79.184" + }, + "CLBLL_ER1BEG2": { + "cap": "5.564", + "res": "79.184" + }, + "CLBLL_ER1BEG3": { + "cap": "5.564", + "res": "79.184" + }, + "CLBLL_FAN0": null, + "CLBLL_FAN1": null, + "CLBLL_FAN2": null, + "CLBLL_FAN3": null, + "CLBLL_FAN4": null, + "CLBLL_FAN5": null, + "CLBLL_FAN6": null, + "CLBLL_FAN7": null, + "CLBLL_IMUX0": null, + "CLBLL_IMUX1": null, + "CLBLL_IMUX10": null, + "CLBLL_IMUX11": null, + "CLBLL_IMUX12": null, + "CLBLL_IMUX13": null, + "CLBLL_IMUX14": null, + "CLBLL_IMUX15": null, + "CLBLL_IMUX16": null, + "CLBLL_IMUX17": null, + "CLBLL_IMUX18": null, + "CLBLL_IMUX19": null, + "CLBLL_IMUX2": null, + "CLBLL_IMUX20": null, + "CLBLL_IMUX21": null, + "CLBLL_IMUX22": null, + "CLBLL_IMUX23": null, + "CLBLL_IMUX24": null, + "CLBLL_IMUX25": null, + "CLBLL_IMUX26": null, + "CLBLL_IMUX27": null, + "CLBLL_IMUX28": null, + "CLBLL_IMUX29": null, + "CLBLL_IMUX3": null, + "CLBLL_IMUX30": null, + "CLBLL_IMUX31": null, + "CLBLL_IMUX32": null, + "CLBLL_IMUX33": null, + "CLBLL_IMUX34": null, + "CLBLL_IMUX35": null, + "CLBLL_IMUX36": null, + "CLBLL_IMUX37": null, + "CLBLL_IMUX38": null, + "CLBLL_IMUX39": null, + "CLBLL_IMUX4": null, + "CLBLL_IMUX40": null, + "CLBLL_IMUX41": null, + "CLBLL_IMUX42": null, + "CLBLL_IMUX43": null, + "CLBLL_IMUX44": null, + "CLBLL_IMUX45": null, + "CLBLL_IMUX46": null, + "CLBLL_IMUX47": null, + "CLBLL_IMUX5": null, + "CLBLL_IMUX6": null, + "CLBLL_IMUX7": null, + "CLBLL_IMUX8": null, + "CLBLL_IMUX9": null, + "CLBLL_LH1": null, + "CLBLL_LH10": null, + "CLBLL_LH11": null, + "CLBLL_LH12": null, + "CLBLL_LH2": null, + "CLBLL_LH3": null, + "CLBLL_LH4": null, + "CLBLL_LH5": null, + "CLBLL_LH6": null, + "CLBLL_LH7": null, + "CLBLL_LH8": null, + "CLBLL_LH9": null, + "CLBLL_LL_A": null, + "CLBLL_LL_A1": { + "cap": "5.682", + "res": "0.000" + }, + "CLBLL_LL_A2": null, + "CLBLL_LL_A3": { + "cap": "7.955", + "res": "0.000" + }, + "CLBLL_LL_A4": { + "cap": "6.818", + "res": "0.000" + }, + "CLBLL_LL_A5": { + "cap": "9.091", + "res": "0.000" + }, + "CLBLL_LL_A6": { + "cap": "4.545", + "res": "0.000" + }, + "CLBLL_LL_AMUX": null, + "CLBLL_LL_AQ": { + "cap": "2.484", + "res": "0.000" + }, + "CLBLL_LL_AX": { + "cap": "1.665", + "res": "0.000" + }, + "CLBLL_LL_B": null, + "CLBLL_LL_B1": null, + "CLBLL_LL_B2": { + "cap": "2.273", + "res": "0.000" + }, + "CLBLL_LL_B3": null, + "CLBLL_LL_B4": { + "cap": "1.136", + "res": "0.000" + }, + "CLBLL_LL_B5": { + "cap": "9.091", + "res": "0.000" + }, + "CLBLL_LL_B6": { + "cap": "4.545", + "res": "0.000" + }, + "CLBLL_LL_BMUX": { + "cap": "2.417", + "res": "0.000" + }, + "CLBLL_LL_BQ": { + "cap": "1.268", + "res": "0.000" + }, + "CLBLL_LL_BX": null, + "CLBLL_LL_C": null, + "CLBLL_LL_C1": { + "cap": "2.273", + "res": "0.000" + }, + "CLBLL_LL_C2": { + "cap": "4.545", + "res": "0.000" + }, + "CLBLL_LL_C3": { + "cap": "1.136", + "res": "0.000" + }, + "CLBLL_LL_C4": { + "cap": "4.545", + "res": "0.000" + }, + "CLBLL_LL_C5": { + "cap": "10.227", + "res": "0.000" + }, + "CLBLL_LL_C6": { + "cap": "5.682", + "res": "0.000" + }, + "CLBLL_LL_CE": null, + "CLBLL_LL_CIN": null, + "CLBLL_LL_CLK": null, + "CLBLL_LL_CMUX": null, + "CLBLL_LL_COUT": null, + "CLBLL_LL_COUT_N": null, + "CLBLL_LL_CQ": { + "cap": "1.980", + "res": "0.000" + }, + "CLBLL_LL_CX": null, + "CLBLL_LL_D": null, + "CLBLL_LL_D1": null, + "CLBLL_LL_D2": null, + "CLBLL_LL_D3": null, + "CLBLL_LL_D4": null, + "CLBLL_LL_D5": { + "cap": "7.955", + "res": "0.000" + }, + "CLBLL_LL_D6": { + "cap": "4.545", + "res": "0.000" + }, + "CLBLL_LL_DMUX": { + "cap": "1.398", + "res": "0.000" + }, + "CLBLL_LL_DQ": { + "cap": "1.964", + "res": "0.000" + }, + "CLBLL_LL_DX": { + "cap": "0.836", + "res": "0.000" + }, + "CLBLL_LL_SR": { + "cap": "1.273", + "res": "0.000" + }, + "CLBLL_LOGIC_OUTS0": null, + "CLBLL_LOGIC_OUTS1": null, + "CLBLL_LOGIC_OUTS10": null, + "CLBLL_LOGIC_OUTS11": null, + "CLBLL_LOGIC_OUTS12": null, + "CLBLL_LOGIC_OUTS13": null, + "CLBLL_LOGIC_OUTS14": null, + "CLBLL_LOGIC_OUTS15": null, + "CLBLL_LOGIC_OUTS16": null, + "CLBLL_LOGIC_OUTS17": null, + "CLBLL_LOGIC_OUTS18": null, + "CLBLL_LOGIC_OUTS19": null, + "CLBLL_LOGIC_OUTS2": null, + "CLBLL_LOGIC_OUTS20": null, + "CLBLL_LOGIC_OUTS21": null, + "CLBLL_LOGIC_OUTS22": null, + "CLBLL_LOGIC_OUTS23": null, + "CLBLL_LOGIC_OUTS3": null, + "CLBLL_LOGIC_OUTS4": null, + "CLBLL_LOGIC_OUTS5": null, + "CLBLL_LOGIC_OUTS6": null, + "CLBLL_LOGIC_OUTS7": null, + "CLBLL_LOGIC_OUTS8": null, + "CLBLL_LOGIC_OUTS9": null, + "CLBLL_L_A": null, + "CLBLL_L_A1": null, + "CLBLL_L_A2": null, + "CLBLL_L_A3": null, + "CLBLL_L_A4": null, + "CLBLL_L_A5": null, + "CLBLL_L_A6": null, + "CLBLL_L_AMUX": null, + "CLBLL_L_AQ": null, + "CLBLL_L_AX": null, + "CLBLL_L_B": null, + "CLBLL_L_B1": null, + "CLBLL_L_B2": null, + "CLBLL_L_B3": null, + "CLBLL_L_B4": null, + "CLBLL_L_B5": null, + "CLBLL_L_B6": null, + "CLBLL_L_BMUX": null, + "CLBLL_L_BQ": null, + "CLBLL_L_BX": null, + "CLBLL_L_C": null, + "CLBLL_L_C1": null, + "CLBLL_L_C2": null, + "CLBLL_L_C3": null, + "CLBLL_L_C4": null, + "CLBLL_L_C5": null, + "CLBLL_L_C6": null, + "CLBLL_L_CE": null, + "CLBLL_L_CIN": null, + "CLBLL_L_CLK": null, + "CLBLL_L_CMUX": null, + "CLBLL_L_COUT": null, + "CLBLL_L_COUT_N": null, + "CLBLL_L_CQ": null, + "CLBLL_L_CX": null, + "CLBLL_L_D": null, + "CLBLL_L_D1": null, + "CLBLL_L_D2": null, + "CLBLL_L_D3": null, + "CLBLL_L_D4": null, + "CLBLL_L_D5": null, + "CLBLL_L_D6": null, + "CLBLL_L_DMUX": null, + "CLBLL_L_DQ": null, + "CLBLL_L_DX": null, + "CLBLL_L_SR": null, + "CLBLL_MONITOR_N": null, + "CLBLL_MONITOR_P": null, + "CLBLL_NE2A0": { + "cap": "5.469", + "res": "87.581" + }, + "CLBLL_NE2A1": { + "cap": "5.469", + "res": "87.581" + }, + "CLBLL_NE2A2": { + "cap": "5.469", + "res": "87.581" + }, + "CLBLL_NE2A3": { + "cap": "5.469", + "res": "87.581" + }, + "CLBLL_NE4BEG0": null, + "CLBLL_NE4BEG1": null, + "CLBLL_NE4BEG2": null, + "CLBLL_NE4BEG3": null, + "CLBLL_NE4C0": null, + "CLBLL_NE4C1": null, + "CLBLL_NE4C2": null, + "CLBLL_NE4C3": null, + "CLBLL_NW2A0": { + "cap": "5.884", + "res": "80.091" + }, + "CLBLL_NW2A1": { + "cap": "5.884", + "res": "80.091" + }, + "CLBLL_NW2A2": { + "cap": "5.884", + "res": "80.091" + }, + "CLBLL_NW2A3": { + "cap": "5.884", + "res": "80.091" + }, + "CLBLL_NW4A0": null, + "CLBLL_NW4A1": null, + "CLBLL_NW4A2": null, + "CLBLL_NW4A3": null, + "CLBLL_NW4END0": null, + "CLBLL_NW4END1": null, + "CLBLL_NW4END2": null, + "CLBLL_NW4END3": null, + "CLBLL_SE2A0": { + "cap": "5.065", + "res": "79.040" + }, + "CLBLL_SE2A1": { + "cap": "5.065", + "res": "79.040" + }, + "CLBLL_SE2A2": { + "cap": "5.065", + "res": "79.040" + }, + "CLBLL_SE2A3": { + "cap": "5.065", + "res": "79.040" + }, + "CLBLL_SE4BEG0": null, + "CLBLL_SE4BEG1": null, + "CLBLL_SE4BEG2": null, + "CLBLL_SE4BEG3": null, + "CLBLL_SE4C0": null, + "CLBLL_SE4C1": null, + "CLBLL_SE4C2": null, + "CLBLL_SE4C3": null, + "CLBLL_SW2A0": { + "cap": "5.896", + "res": "78.932" + }, + "CLBLL_SW2A1": { + "cap": "5.896", + "res": "78.932" + }, + "CLBLL_SW2A2": { + "cap": "5.896", + "res": "78.932" + }, + "CLBLL_SW2A3": { + "cap": "5.896", + "res": "78.932" + }, + "CLBLL_SW4A0": null, + "CLBLL_SW4A1": null, + "CLBLL_SW4A2": null, + "CLBLL_SW4A3": null, + "CLBLL_SW4END0": null, + "CLBLL_SW4END1": null, + "CLBLL_SW4END2": null, + "CLBLL_SW4END3": null, + "CLBLL_WL1END0": { + "cap": "6.105", + "res": "51.272" + }, + "CLBLL_WL1END1": { + "cap": "6.105", + "res": "51.272" + }, + "CLBLL_WL1END2": { + "cap": "6.105", + "res": "51.272" + }, + "CLBLL_WL1END3": { + "cap": "6.105", + "res": "51.272" + }, + "CLBLL_WR1END0": { + "cap": "5.801", + "res": "82.696" + }, + "CLBLL_WR1END1": { + "cap": "5.801", + "res": "82.696" + }, + "CLBLL_WR1END2": { + "cap": "5.801", + "res": "82.696" + }, + "CLBLL_WR1END3": { + "cap": "5.801", + "res": "82.696" + }, + "CLBLL_WW2A0": null, + "CLBLL_WW2A1": null, + "CLBLL_WW2A2": null, + "CLBLL_WW2A3": null, + "CLBLL_WW2END0": null, + "CLBLL_WW2END1": null, + "CLBLL_WW2END2": null, + "CLBLL_WW2END3": null, + "CLBLL_WW4A0": null, + "CLBLL_WW4A1": null, + "CLBLL_WW4A2": null, + "CLBLL_WW4A3": null, + "CLBLL_WW4B0": null, + "CLBLL_WW4B1": null, + "CLBLL_WW4B2": null, + "CLBLL_WW4B3": null, + "CLBLL_WW4C0": null, + "CLBLL_WW4C1": null, + "CLBLL_WW4C2": null, + "CLBLL_WW4C3": null, + "CLBLL_WW4END0": null, + "CLBLL_WW4END1": null, + "CLBLL_WW4END2": null, + "CLBLL_WW4END3": null + } } diff --git a/zynq7/tile_type_CLBLL_R.json b/zynq7/tile_type_CLBLL_R.json index 288a860..9c86a5d 100644 --- a/zynq7/tile_type_CLBLL_R.json +++ b/zynq7/tile_type_CLBLL_R.json @@ -2,1024 +2,3210 @@ "pips": { "CLBLL_R.CLBLL_BYP0->CLBLL_L_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP0" }, "CLBLL_R.CLBLL_BYP1->CLBLL_LL_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP1" }, "CLBLL_R.CLBLL_BYP2->CLBLL_L_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP2" }, "CLBLL_R.CLBLL_BYP3->CLBLL_LL_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP3" }, "CLBLL_R.CLBLL_BYP4->CLBLL_LL_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP4" }, "CLBLL_R.CLBLL_BYP5->CLBLL_L_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP5" }, "CLBLL_R.CLBLL_BYP6->CLBLL_LL_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP6" }, "CLBLL_R.CLBLL_BYP7->CLBLL_L_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP7" }, "CLBLL_R.CLBLL_CLK0->CLBLL_L_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CLK0" }, "CLBLL_R.CLBLL_CLK1->CLBLL_LL_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CLK1" }, "CLBLL_R.CLBLL_CTRL0->CLBLL_L_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CTRL0" }, "CLBLL_R.CLBLL_CTRL1->CLBLL_LL_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CTRL1" }, "CLBLL_R.CLBLL_FAN6->CLBLL_L_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_FAN6" }, "CLBLL_R.CLBLL_FAN7->CLBLL_LL_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_FAN7" }, "CLBLL_R.CLBLL_IMUX0->CLBLL_L_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX0" }, "CLBLL_R.CLBLL_IMUX1->CLBLL_LL_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX1" }, "CLBLL_R.CLBLL_IMUX10->CLBLL_L_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX10" }, "CLBLL_R.CLBLL_IMUX11->CLBLL_LL_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX11" }, "CLBLL_R.CLBLL_IMUX12->CLBLL_LL_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX12" }, "CLBLL_R.CLBLL_IMUX13->CLBLL_L_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX13" }, "CLBLL_R.CLBLL_IMUX14->CLBLL_L_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX14" }, "CLBLL_R.CLBLL_IMUX15->CLBLL_LL_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX15" }, "CLBLL_R.CLBLL_IMUX16->CLBLL_L_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX16" }, "CLBLL_R.CLBLL_IMUX17->CLBLL_LL_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX17" }, "CLBLL_R.CLBLL_IMUX18->CLBLL_LL_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX18" }, "CLBLL_R.CLBLL_IMUX19->CLBLL_L_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX19" }, "CLBLL_R.CLBLL_IMUX2->CLBLL_LL_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX2" }, "CLBLL_R.CLBLL_IMUX20->CLBLL_L_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX20" }, "CLBLL_R.CLBLL_IMUX21->CLBLL_L_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX21" }, "CLBLL_R.CLBLL_IMUX22->CLBLL_LL_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX22" }, "CLBLL_R.CLBLL_IMUX23->CLBLL_L_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX23" }, "CLBLL_R.CLBLL_IMUX24->CLBLL_LL_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX24" }, "CLBLL_R.CLBLL_IMUX25->CLBLL_L_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX25" }, "CLBLL_R.CLBLL_IMUX26->CLBLL_L_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX26" }, "CLBLL_R.CLBLL_IMUX27->CLBLL_LL_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX27" }, "CLBLL_R.CLBLL_IMUX28->CLBLL_LL_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX28" }, "CLBLL_R.CLBLL_IMUX29->CLBLL_LL_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX29" }, "CLBLL_R.CLBLL_IMUX3->CLBLL_L_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX3" }, "CLBLL_R.CLBLL_IMUX30->CLBLL_L_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX30" }, "CLBLL_R.CLBLL_IMUX31->CLBLL_LL_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX31" }, "CLBLL_R.CLBLL_IMUX32->CLBLL_LL_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX32" }, "CLBLL_R.CLBLL_IMUX33->CLBLL_L_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX33" }, "CLBLL_R.CLBLL_IMUX34->CLBLL_L_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX34" }, "CLBLL_R.CLBLL_IMUX35->CLBLL_LL_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX35" }, "CLBLL_R.CLBLL_IMUX36->CLBLL_L_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX36" }, "CLBLL_R.CLBLL_IMUX37->CLBLL_L_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX37" }, "CLBLL_R.CLBLL_IMUX38->CLBLL_LL_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX38" }, "CLBLL_R.CLBLL_IMUX39->CLBLL_L_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX39" }, "CLBLL_R.CLBLL_IMUX4->CLBLL_LL_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX4" }, "CLBLL_R.CLBLL_IMUX40->CLBLL_LL_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX40" }, "CLBLL_R.CLBLL_IMUX41->CLBLL_L_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX41" }, "CLBLL_R.CLBLL_IMUX42->CLBLL_L_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX42" }, "CLBLL_R.CLBLL_IMUX43->CLBLL_LL_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX43" }, "CLBLL_R.CLBLL_IMUX44->CLBLL_LL_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX44" }, "CLBLL_R.CLBLL_IMUX45->CLBLL_LL_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX45" }, "CLBLL_R.CLBLL_IMUX46->CLBLL_L_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX46" }, "CLBLL_R.CLBLL_IMUX47->CLBLL_LL_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX47" }, "CLBLL_R.CLBLL_IMUX5->CLBLL_L_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX5" }, "CLBLL_R.CLBLL_IMUX6->CLBLL_L_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX6" }, "CLBLL_R.CLBLL_IMUX7->CLBLL_LL_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX7" }, "CLBLL_R.CLBLL_IMUX8->CLBLL_LL_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX8" }, "CLBLL_R.CLBLL_IMUX9->CLBLL_L_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX9" }, "CLBLL_R.CLBLL_LL_A->>CLBLL_LL_AMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.071", + "0.088", + "0.168", + "0.209" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_AMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.071", + "0.088", + "0.168", + "0.209" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A" }, "CLBLL_R.CLBLL_LL_A->CLBLL_LOGIC_OUTS12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_LL_A" }, "CLBLL_R.CLBLL_LL_A1->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A1" }, "CLBLL_R.CLBLL_LL_A2->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A2" }, "CLBLL_R.CLBLL_LL_A3->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A3" }, "CLBLL_R.CLBLL_LL_A4->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A4" }, "CLBLL_R.CLBLL_LL_A5->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A5" }, "CLBLL_R.CLBLL_LL_A6->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A6" }, "CLBLL_R.CLBLL_LL_AMUX->CLBLL_LOGIC_OUTS20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_LL_AMUX" }, "CLBLL_R.CLBLL_LL_AQ->CLBLL_LOGIC_OUTS4": { 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"CLBLL_L_DMUX" + }, + "DQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLL_L_DQ" + }, + "DX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLL_L_DX" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLL_L_SR" + } }, "type": "SLICEL", "x_coord": 1, @@ -1134,316 +4130,490 @@ } ], "tile_type": "CLBLL_R", - "wires": [ - "CLBLL_BYP0", - "CLBLL_BYP1", - "CLBLL_BYP2", - "CLBLL_BYP3", - "CLBLL_BYP4", - "CLBLL_BYP5", - "CLBLL_BYP6", - "CLBLL_BYP7", - "CLBLL_CLK0", - "CLBLL_CLK1", - "CLBLL_CTRL0", - "CLBLL_CTRL1", - "CLBLL_EE2A0", - "CLBLL_EE2A1", - "CLBLL_EE2A2", - "CLBLL_EE2A3", - "CLBLL_EE2BEG0", - "CLBLL_EE2BEG1", - "CLBLL_EE2BEG2", - "CLBLL_EE2BEG3", - "CLBLL_EE4A0", - "CLBLL_EE4A1", - "CLBLL_EE4A2", - "CLBLL_EE4A3", - "CLBLL_EE4B0", - "CLBLL_EE4B1", - "CLBLL_EE4B2", - "CLBLL_EE4B3", - "CLBLL_EE4BEG0", - "CLBLL_EE4BEG1", - "CLBLL_EE4BEG2", - "CLBLL_EE4BEG3", - "CLBLL_EE4C0", - "CLBLL_EE4C1", - "CLBLL_EE4C2", - "CLBLL_EE4C3", - "CLBLL_EL1BEG0", - "CLBLL_EL1BEG1", - "CLBLL_EL1BEG2", - "CLBLL_EL1BEG3", - "CLBLL_ER1BEG0", - "CLBLL_ER1BEG1", - "CLBLL_ER1BEG2", - "CLBLL_ER1BEG3", - "CLBLL_FAN0", - "CLBLL_FAN1", - "CLBLL_FAN2", - "CLBLL_FAN3", - "CLBLL_FAN4", - "CLBLL_FAN5", - "CLBLL_FAN6", - "CLBLL_FAN7", - "CLBLL_IMUX0", - "CLBLL_IMUX1", - "CLBLL_IMUX10", - "CLBLL_IMUX11", - "CLBLL_IMUX12", - "CLBLL_IMUX13", - "CLBLL_IMUX14", - "CLBLL_IMUX15", - "CLBLL_IMUX16", - "CLBLL_IMUX17", - "CLBLL_IMUX18", - "CLBLL_IMUX19", - "CLBLL_IMUX2", - "CLBLL_IMUX20", - "CLBLL_IMUX21", - "CLBLL_IMUX22", - "CLBLL_IMUX23", - "CLBLL_IMUX24", - "CLBLL_IMUX25", - "CLBLL_IMUX26", - "CLBLL_IMUX27", - "CLBLL_IMUX28", - "CLBLL_IMUX29", - "CLBLL_IMUX3", - "CLBLL_IMUX30", - "CLBLL_IMUX31", - "CLBLL_IMUX32", - "CLBLL_IMUX33", - "CLBLL_IMUX34", - "CLBLL_IMUX35", - "CLBLL_IMUX36", - "CLBLL_IMUX37", - "CLBLL_IMUX38", - "CLBLL_IMUX39", - "CLBLL_IMUX4", - "CLBLL_IMUX40", - "CLBLL_IMUX41", - "CLBLL_IMUX42", - "CLBLL_IMUX43", - "CLBLL_IMUX44", - "CLBLL_IMUX45", - "CLBLL_IMUX46", - "CLBLL_IMUX47", - "CLBLL_IMUX5", - "CLBLL_IMUX6", - "CLBLL_IMUX7", - "CLBLL_IMUX8", - "CLBLL_IMUX9", - "CLBLL_LH1", - "CLBLL_LH10", - "CLBLL_LH11", - "CLBLL_LH12", - "CLBLL_LH2", - "CLBLL_LH3", - "CLBLL_LH4", - "CLBLL_LH5", - "CLBLL_LH6", - "CLBLL_LH7", - "CLBLL_LH8", - "CLBLL_LH9", - "CLBLL_LL_A", - "CLBLL_LL_A1", - "CLBLL_LL_A2", - "CLBLL_LL_A3", - "CLBLL_LL_A4", - "CLBLL_LL_A5", - "CLBLL_LL_A6", - "CLBLL_LL_AMUX", - "CLBLL_LL_AQ", - "CLBLL_LL_AX", - "CLBLL_LL_B", - "CLBLL_LL_B1", - "CLBLL_LL_B2", - "CLBLL_LL_B3", - "CLBLL_LL_B4", - "CLBLL_LL_B5", - "CLBLL_LL_B6", - "CLBLL_LL_BMUX", - "CLBLL_LL_BQ", - "CLBLL_LL_BX", - "CLBLL_LL_C", - "CLBLL_LL_C1", - "CLBLL_LL_C2", - "CLBLL_LL_C3", - "CLBLL_LL_C4", - "CLBLL_LL_C5", - "CLBLL_LL_C6", - "CLBLL_LL_CE", - "CLBLL_LL_CIN", - "CLBLL_LL_CLK", - "CLBLL_LL_CMUX", - "CLBLL_LL_COUT", - "CLBLL_LL_COUT_N", - "CLBLL_LL_CQ", - "CLBLL_LL_CX", - "CLBLL_LL_D", - "CLBLL_LL_D1", - "CLBLL_LL_D2", - "CLBLL_LL_D3", - "CLBLL_LL_D4", - "CLBLL_LL_D5", - "CLBLL_LL_D6", - "CLBLL_LL_DMUX", - "CLBLL_LL_DQ", - "CLBLL_LL_DX", - "CLBLL_LL_SR", - "CLBLL_LOGIC_OUTS0", - "CLBLL_LOGIC_OUTS1", - "CLBLL_LOGIC_OUTS10", - "CLBLL_LOGIC_OUTS11", - "CLBLL_LOGIC_OUTS12", - "CLBLL_LOGIC_OUTS13", - "CLBLL_LOGIC_OUTS14", - "CLBLL_LOGIC_OUTS15", - "CLBLL_LOGIC_OUTS16", - "CLBLL_LOGIC_OUTS17", - "CLBLL_LOGIC_OUTS18", - "CLBLL_LOGIC_OUTS19", - "CLBLL_LOGIC_OUTS2", - "CLBLL_LOGIC_OUTS20", - "CLBLL_LOGIC_OUTS21", - "CLBLL_LOGIC_OUTS22", - "CLBLL_LOGIC_OUTS23", - "CLBLL_LOGIC_OUTS3", - "CLBLL_LOGIC_OUTS4", - "CLBLL_LOGIC_OUTS5", - "CLBLL_LOGIC_OUTS6", - "CLBLL_LOGIC_OUTS7", - "CLBLL_LOGIC_OUTS8", - "CLBLL_LOGIC_OUTS9", - "CLBLL_L_A", - "CLBLL_L_A1", - "CLBLL_L_A2", - "CLBLL_L_A3", - "CLBLL_L_A4", - "CLBLL_L_A5", - "CLBLL_L_A6", - "CLBLL_L_AMUX", - "CLBLL_L_AQ", - "CLBLL_L_AX", - "CLBLL_L_B", - "CLBLL_L_B1", - "CLBLL_L_B2", - "CLBLL_L_B3", - "CLBLL_L_B4", - "CLBLL_L_B5", - "CLBLL_L_B6", - "CLBLL_L_BMUX", - "CLBLL_L_BQ", - "CLBLL_L_BX", - "CLBLL_L_C", - "CLBLL_L_C1", - "CLBLL_L_C2", - "CLBLL_L_C3", - "CLBLL_L_C4", - "CLBLL_L_C5", - "CLBLL_L_C6", - "CLBLL_L_CE", - "CLBLL_L_CIN", - "CLBLL_L_CLK", - "CLBLL_L_CMUX", - "CLBLL_L_COUT", - "CLBLL_L_COUT_N", - "CLBLL_L_CQ", - "CLBLL_L_CX", - "CLBLL_L_D", - "CLBLL_L_D1", - "CLBLL_L_D2", - "CLBLL_L_D3", - "CLBLL_L_D4", - "CLBLL_L_D5", - "CLBLL_L_D6", - "CLBLL_L_DMUX", - "CLBLL_L_DQ", - "CLBLL_L_DX", - "CLBLL_L_SR", - "CLBLL_MONITOR_N", - "CLBLL_MONITOR_P", - "CLBLL_NE2A0", - "CLBLL_NE2A1", - "CLBLL_NE2A2", - "CLBLL_NE2A3", - "CLBLL_NE4BEG0", - "CLBLL_NE4BEG1", - "CLBLL_NE4BEG2", - "CLBLL_NE4BEG3", - "CLBLL_NE4C0", - "CLBLL_NE4C1", - "CLBLL_NE4C2", - "CLBLL_NE4C3", - "CLBLL_NW2A0", - "CLBLL_NW2A1", - "CLBLL_NW2A2", - "CLBLL_NW2A3", - "CLBLL_NW4A0", - "CLBLL_NW4A1", - "CLBLL_NW4A2", - "CLBLL_NW4A3", - "CLBLL_NW4END0", - "CLBLL_NW4END1", - "CLBLL_NW4END2", - "CLBLL_NW4END3", - "CLBLL_SE2A0", - "CLBLL_SE2A1", - "CLBLL_SE2A2", - "CLBLL_SE2A3", - "CLBLL_SE4BEG0", - "CLBLL_SE4BEG1", - "CLBLL_SE4BEG2", - "CLBLL_SE4BEG3", - "CLBLL_SE4C0", - "CLBLL_SE4C1", - "CLBLL_SE4C2", - "CLBLL_SE4C3", - "CLBLL_SW2A0", - "CLBLL_SW2A1", - "CLBLL_SW2A2", - "CLBLL_SW2A3", - "CLBLL_SW4A0", - "CLBLL_SW4A1", - "CLBLL_SW4A2", - "CLBLL_SW4A3", - "CLBLL_SW4END0", - "CLBLL_SW4END1", - "CLBLL_SW4END2", - "CLBLL_SW4END3", - "CLBLL_WL1END0", - "CLBLL_WL1END1", - "CLBLL_WL1END2", - "CLBLL_WL1END3", - "CLBLL_WR1END0", - "CLBLL_WR1END1", - "CLBLL_WR1END2", - "CLBLL_WR1END3", - "CLBLL_WW2A0", - "CLBLL_WW2A1", - "CLBLL_WW2A2", - "CLBLL_WW2A3", - "CLBLL_WW2END0", - "CLBLL_WW2END1", - "CLBLL_WW2END2", - "CLBLL_WW2END3", - "CLBLL_WW4A0", - "CLBLL_WW4A1", - "CLBLL_WW4A2", - "CLBLL_WW4A3", - "CLBLL_WW4B0", - "CLBLL_WW4B1", - "CLBLL_WW4B2", - "CLBLL_WW4B3", - "CLBLL_WW4C0", - "CLBLL_WW4C1", - "CLBLL_WW4C2", - "CLBLL_WW4C3", - "CLBLL_WW4END0", - "CLBLL_WW4END1", - "CLBLL_WW4END2", - "CLBLL_WW4END3" - ] + "wires": { + "CLBLL_BYP0": null, + "CLBLL_BYP1": null, + "CLBLL_BYP2": null, + "CLBLL_BYP3": null, + "CLBLL_BYP4": null, + "CLBLL_BYP5": null, + "CLBLL_BYP6": null, + "CLBLL_BYP7": null, + "CLBLL_CLK0": null, + "CLBLL_CLK1": null, + "CLBLL_CTRL0": null, + "CLBLL_CTRL1": null, + "CLBLL_EE2A0": null, + "CLBLL_EE2A1": null, + "CLBLL_EE2A2": null, + "CLBLL_EE2A3": null, + "CLBLL_EE2BEG0": null, + "CLBLL_EE2BEG1": null, + "CLBLL_EE2BEG2": null, + "CLBLL_EE2BEG3": null, + "CLBLL_EE4A0": null, + "CLBLL_EE4A1": null, + "CLBLL_EE4A2": null, + "CLBLL_EE4A3": null, + "CLBLL_EE4B0": null, + "CLBLL_EE4B1": null, + "CLBLL_EE4B2": null, + "CLBLL_EE4B3": null, + "CLBLL_EE4BEG0": null, + "CLBLL_EE4BEG1": null, + "CLBLL_EE4BEG2": null, + "CLBLL_EE4BEG3": null, + "CLBLL_EE4C0": null, + "CLBLL_EE4C1": null, + "CLBLL_EE4C2": null, + "CLBLL_EE4C3": null, + "CLBLL_EL1BEG0": { + "cap": "4.690", + "res": "45.632" + }, + "CLBLL_EL1BEG1": { + "cap": "4.690", + "res": "45.632" + }, + "CLBLL_EL1BEG2": { + "cap": "4.690", + "res": "45.632" + }, + "CLBLL_EL1BEG3": { + "cap": "4.690", + "res": "45.632" + }, + "CLBLL_ER1BEG0": { + "cap": "5.564", + "res": "79.184" + }, + "CLBLL_ER1BEG1": { + "cap": "5.564", + "res": "79.184" + }, + "CLBLL_ER1BEG2": { + "cap": "5.564", + "res": "79.184" + }, + "CLBLL_ER1BEG3": { + "cap": "5.564", + "res": "79.184" + }, + "CLBLL_FAN0": null, + "CLBLL_FAN1": null, + "CLBLL_FAN2": null, + "CLBLL_FAN3": null, + "CLBLL_FAN4": null, + "CLBLL_FAN5": null, + "CLBLL_FAN6": null, + "CLBLL_FAN7": null, + "CLBLL_IMUX0": null, + "CLBLL_IMUX1": null, + "CLBLL_IMUX10": null, + "CLBLL_IMUX11": null, + "CLBLL_IMUX12": null, + "CLBLL_IMUX13": null, + "CLBLL_IMUX14": null, + "CLBLL_IMUX15": null, + "CLBLL_IMUX16": null, + "CLBLL_IMUX17": null, + "CLBLL_IMUX18": null, + "CLBLL_IMUX19": null, + "CLBLL_IMUX2": null, + "CLBLL_IMUX20": null, + "CLBLL_IMUX21": null, + "CLBLL_IMUX22": null, + "CLBLL_IMUX23": null, + "CLBLL_IMUX24": null, + "CLBLL_IMUX25": null, + "CLBLL_IMUX26": null, + "CLBLL_IMUX27": null, + "CLBLL_IMUX28": null, + "CLBLL_IMUX29": null, + "CLBLL_IMUX3": null, + "CLBLL_IMUX30": null, + "CLBLL_IMUX31": null, + "CLBLL_IMUX32": null, + "CLBLL_IMUX33": null, + "CLBLL_IMUX34": null, + "CLBLL_IMUX35": null, + "CLBLL_IMUX36": null, + "CLBLL_IMUX37": null, + "CLBLL_IMUX38": null, + "CLBLL_IMUX39": null, + "CLBLL_IMUX4": null, + "CLBLL_IMUX40": null, + "CLBLL_IMUX41": null, + "CLBLL_IMUX42": null, + "CLBLL_IMUX43": null, + "CLBLL_IMUX44": null, + "CLBLL_IMUX45": null, + "CLBLL_IMUX46": null, + "CLBLL_IMUX47": null, + "CLBLL_IMUX5": null, + "CLBLL_IMUX6": null, + "CLBLL_IMUX7": null, + "CLBLL_IMUX8": null, + "CLBLL_IMUX9": null, + "CLBLL_LH1": null, + "CLBLL_LH10": null, + "CLBLL_LH11": null, + "CLBLL_LH12": null, + "CLBLL_LH2": null, + "CLBLL_LH3": null, + "CLBLL_LH4": null, + "CLBLL_LH5": null, + "CLBLL_LH6": null, + "CLBLL_LH7": null, + "CLBLL_LH8": null, + "CLBLL_LH9": null, + "CLBLL_LL_A": null, + "CLBLL_LL_A1": { + "cap": "5.682", + "res": "0.000" + }, + "CLBLL_LL_A2": null, + "CLBLL_LL_A3": { + "cap": "7.955", + "res": "0.000" + }, + "CLBLL_LL_A4": { + "cap": "6.818", + "res": "0.000" + }, + "CLBLL_LL_A5": { + "cap": "9.091", + "res": "0.000" + }, + "CLBLL_LL_A6": { + "cap": "4.545", + "res": "0.000" + }, + "CLBLL_LL_AMUX": null, + "CLBLL_LL_AQ": { + "cap": "2.484", + "res": "0.000" + }, + "CLBLL_LL_AX": { + "cap": "1.665", + "res": "0.000" + }, + "CLBLL_LL_B": null, + "CLBLL_LL_B1": null, + "CLBLL_LL_B2": { + "cap": "2.273", + "res": "0.000" + }, + "CLBLL_LL_B3": null, + "CLBLL_LL_B4": { + "cap": "1.136", + "res": "0.000" + }, + "CLBLL_LL_B5": { + "cap": "9.091", + "res": "0.000" + }, + "CLBLL_LL_B6": { + "cap": "4.545", + "res": "0.000" + }, + "CLBLL_LL_BMUX": { + "cap": "2.417", + "res": "0.000" + }, + "CLBLL_LL_BQ": { + "cap": "1.268", + "res": "0.000" + }, + "CLBLL_LL_BX": null, + "CLBLL_LL_C": null, + "CLBLL_LL_C1": { + "cap": "2.273", + "res": "0.000" + }, + "CLBLL_LL_C2": { + "cap": "4.545", + "res": "0.000" + }, + "CLBLL_LL_C3": { + "cap": "1.136", + "res": "0.000" + }, + "CLBLL_LL_C4": { + "cap": "4.545", + "res": "0.000" + }, + "CLBLL_LL_C5": { + "cap": "10.227", + "res": "0.000" + }, + "CLBLL_LL_C6": { + "cap": "5.682", + "res": "0.000" + }, + "CLBLL_LL_CE": null, + "CLBLL_LL_CIN": null, + "CLBLL_LL_CLK": null, + "CLBLL_LL_CMUX": null, + "CLBLL_LL_COUT": null, + "CLBLL_LL_COUT_N": null, + "CLBLL_LL_CQ": { + "cap": "1.980", + "res": "0.000" + }, + "CLBLL_LL_CX": null, + "CLBLL_LL_D": null, + "CLBLL_LL_D1": null, + "CLBLL_LL_D2": null, + "CLBLL_LL_D3": null, + "CLBLL_LL_D4": null, + "CLBLL_LL_D5": { + "cap": "7.955", + "res": "0.000" + }, + "CLBLL_LL_D6": { + "cap": "4.545", + "res": "0.000" + }, + "CLBLL_LL_DMUX": { + "cap": "1.398", + "res": "0.000" + }, + "CLBLL_LL_DQ": { + "cap": "1.964", + "res": "0.000" + }, + "CLBLL_LL_DX": { + "cap": "0.836", + "res": "0.000" + }, + "CLBLL_LL_SR": { + "cap": "1.273", + "res": "0.000" + }, + "CLBLL_LOGIC_OUTS0": null, + "CLBLL_LOGIC_OUTS1": null, + "CLBLL_LOGIC_OUTS10": null, + "CLBLL_LOGIC_OUTS11": null, + "CLBLL_LOGIC_OUTS12": null, + "CLBLL_LOGIC_OUTS13": null, + "CLBLL_LOGIC_OUTS14": null, + "CLBLL_LOGIC_OUTS15": null, + "CLBLL_LOGIC_OUTS16": null, + "CLBLL_LOGIC_OUTS17": null, + "CLBLL_LOGIC_OUTS18": null, + "CLBLL_LOGIC_OUTS19": null, + "CLBLL_LOGIC_OUTS2": null, + "CLBLL_LOGIC_OUTS20": null, + "CLBLL_LOGIC_OUTS21": null, + "CLBLL_LOGIC_OUTS22": null, + "CLBLL_LOGIC_OUTS23": null, + "CLBLL_LOGIC_OUTS3": null, + "CLBLL_LOGIC_OUTS4": null, + "CLBLL_LOGIC_OUTS5": null, + "CLBLL_LOGIC_OUTS6": null, + "CLBLL_LOGIC_OUTS7": null, + "CLBLL_LOGIC_OUTS8": null, + "CLBLL_LOGIC_OUTS9": null, + "CLBLL_L_A": null, + "CLBLL_L_A1": null, + "CLBLL_L_A2": null, + "CLBLL_L_A3": null, + "CLBLL_L_A4": null, + "CLBLL_L_A5": null, + "CLBLL_L_A6": null, + "CLBLL_L_AMUX": null, + "CLBLL_L_AQ": null, + "CLBLL_L_AX": null, + "CLBLL_L_B": null, + "CLBLL_L_B1": null, + "CLBLL_L_B2": null, + "CLBLL_L_B3": null, + "CLBLL_L_B4": null, + "CLBLL_L_B5": null, + "CLBLL_L_B6": null, + "CLBLL_L_BMUX": null, + "CLBLL_L_BQ": null, + "CLBLL_L_BX": null, + "CLBLL_L_C": null, + "CLBLL_L_C1": null, + "CLBLL_L_C2": null, + "CLBLL_L_C3": null, + "CLBLL_L_C4": null, + "CLBLL_L_C5": null, + "CLBLL_L_C6": null, + "CLBLL_L_CE": null, + "CLBLL_L_CIN": null, + "CLBLL_L_CLK": null, + "CLBLL_L_CMUX": null, + "CLBLL_L_COUT": null, + "CLBLL_L_COUT_N": null, + "CLBLL_L_CQ": null, + "CLBLL_L_CX": null, + "CLBLL_L_D": null, + "CLBLL_L_D1": null, + "CLBLL_L_D2": null, + "CLBLL_L_D3": null, + "CLBLL_L_D4": null, + "CLBLL_L_D5": null, + "CLBLL_L_D6": null, + "CLBLL_L_DMUX": null, + "CLBLL_L_DQ": null, + "CLBLL_L_DX": null, + "CLBLL_L_SR": null, + "CLBLL_MONITOR_N": null, + "CLBLL_MONITOR_P": null, + "CLBLL_NE2A0": { + "cap": "5.469", + "res": "87.581" + }, + "CLBLL_NE2A1": { + "cap": "5.469", + "res": "87.581" + }, + "CLBLL_NE2A2": { + "cap": "5.469", + "res": "87.581" + }, + "CLBLL_NE2A3": { + "cap": "5.469", + "res": "87.581" + }, + "CLBLL_NE4BEG0": null, + "CLBLL_NE4BEG1": null, + "CLBLL_NE4BEG2": null, + "CLBLL_NE4BEG3": null, + "CLBLL_NE4C0": null, + "CLBLL_NE4C1": null, + "CLBLL_NE4C2": null, + "CLBLL_NE4C3": null, + "CLBLL_NW2A0": { + "cap": "5.884", + "res": "80.091" + }, + "CLBLL_NW2A1": { + "cap": "5.884", + "res": "80.091" + }, + "CLBLL_NW2A2": { + "cap": "5.884", + "res": "80.091" + }, + "CLBLL_NW2A3": { + "cap": "5.884", + "res": "80.091" + }, + "CLBLL_NW4A0": null, + "CLBLL_NW4A1": null, + "CLBLL_NW4A2": null, + "CLBLL_NW4A3": null, + "CLBLL_NW4END0": null, + "CLBLL_NW4END1": null, + "CLBLL_NW4END2": null, + "CLBLL_NW4END3": null, + "CLBLL_SE2A0": { + "cap": "5.065", + "res": "79.040" + }, + "CLBLL_SE2A1": { + "cap": "5.065", + "res": "79.040" + }, + "CLBLL_SE2A2": { + "cap": "5.065", + "res": "79.040" + }, + "CLBLL_SE2A3": { + "cap": "5.065", + "res": "79.040" + }, + "CLBLL_SE4BEG0": null, + "CLBLL_SE4BEG1": null, + "CLBLL_SE4BEG2": null, + "CLBLL_SE4BEG3": null, + "CLBLL_SE4C0": null, + "CLBLL_SE4C1": null, + "CLBLL_SE4C2": null, + "CLBLL_SE4C3": null, + "CLBLL_SW2A0": { + "cap": "5.896", + "res": "78.932" + }, + "CLBLL_SW2A1": { + "cap": "5.896", + "res": "78.932" + }, + "CLBLL_SW2A2": { + "cap": "5.896", + "res": "78.932" + }, + "CLBLL_SW2A3": { + "cap": "5.896", + "res": "78.932" + }, + "CLBLL_SW4A0": null, + "CLBLL_SW4A1": null, + "CLBLL_SW4A2": null, + "CLBLL_SW4A3": null, + "CLBLL_SW4END0": null, + "CLBLL_SW4END1": null, + "CLBLL_SW4END2": null, + "CLBLL_SW4END3": null, + "CLBLL_WL1END0": { + "cap": "6.105", + "res": "51.272" + }, + "CLBLL_WL1END1": { + "cap": "6.105", + "res": "51.272" + }, + "CLBLL_WL1END2": { + "cap": "6.105", + "res": "51.272" + }, + "CLBLL_WL1END3": { + "cap": "6.105", + "res": "51.272" + }, + "CLBLL_WR1END0": { + "cap": "5.801", + "res": "82.696" + }, + "CLBLL_WR1END1": { + "cap": "5.801", + "res": "82.696" + }, + "CLBLL_WR1END2": { + "cap": "5.801", + "res": "82.696" + }, + "CLBLL_WR1END3": { + "cap": "5.801", + "res": "82.696" + }, + "CLBLL_WW2A0": null, + "CLBLL_WW2A1": null, + "CLBLL_WW2A2": null, + "CLBLL_WW2A3": null, + "CLBLL_WW2END0": null, + "CLBLL_WW2END1": null, + "CLBLL_WW2END2": null, + "CLBLL_WW2END3": null, + "CLBLL_WW4A0": null, + "CLBLL_WW4A1": null, + "CLBLL_WW4A2": null, + "CLBLL_WW4A3": null, + "CLBLL_WW4B0": null, + "CLBLL_WW4B1": null, + "CLBLL_WW4B2": null, + "CLBLL_WW4B3": null, + "CLBLL_WW4C0": null, + "CLBLL_WW4C1": null, + "CLBLL_WW4C2": null, + "CLBLL_WW4C3": null, + "CLBLL_WW4END0": null, + "CLBLL_WW4END1": null, + "CLBLL_WW4END2": null, + "CLBLL_WW4END3": null + } } diff --git a/zynq7/tile_type_CLBLM_L.json b/zynq7/tile_type_CLBLM_L.json index c4c1a5a..b852f11 100644 --- a/zynq7/tile_type_CLBLM_L.json +++ b/zynq7/tile_type_CLBLM_L.json @@ -2,1059 +2,3300 @@ "pips": { "CLBLM_L.CLBLM_BYP0->CLBLM_L_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP0" }, "CLBLM_L.CLBLM_BYP1->CLBLM_M_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP1" }, "CLBLM_L.CLBLM_BYP2->CLBLM_L_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP2" }, "CLBLM_L.CLBLM_BYP3->CLBLM_M_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP3" }, "CLBLM_L.CLBLM_BYP4->CLBLM_M_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP4" }, "CLBLM_L.CLBLM_BYP5->CLBLM_L_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP5" }, "CLBLM_L.CLBLM_BYP6->CLBLM_M_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP6" }, "CLBLM_L.CLBLM_BYP7->CLBLM_L_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP7" }, "CLBLM_L.CLBLM_CLK0->CLBLM_L_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CLK0" }, "CLBLM_L.CLBLM_CLK1->CLBLM_M_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CLK1" }, "CLBLM_L.CLBLM_CTRL0->CLBLM_L_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CTRL0" }, "CLBLM_L.CLBLM_CTRL1->CLBLM_M_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CTRL1" }, "CLBLM_L.CLBLM_FAN0->CLBLM_M_AI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_AI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN0" }, "CLBLM_L.CLBLM_FAN2->CLBLM_M_BI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_BI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN2" }, "CLBLM_L.CLBLM_FAN3->CLBLM_M_DI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_DI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN3" }, "CLBLM_L.CLBLM_FAN4->CLBLM_M_WE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_WE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN4" }, "CLBLM_L.CLBLM_FAN5->CLBLM_M_CI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN5" }, "CLBLM_L.CLBLM_FAN6->CLBLM_L_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN6" }, "CLBLM_L.CLBLM_FAN7->CLBLM_M_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN7" }, "CLBLM_L.CLBLM_IMUX0->CLBLM_L_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX0" }, "CLBLM_L.CLBLM_IMUX1->CLBLM_M_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX1" }, "CLBLM_L.CLBLM_IMUX10->CLBLM_L_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX10" }, "CLBLM_L.CLBLM_IMUX11->CLBLM_M_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX11" }, "CLBLM_L.CLBLM_IMUX12->CLBLM_M_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX12" }, "CLBLM_L.CLBLM_IMUX13->CLBLM_L_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX13" }, "CLBLM_L.CLBLM_IMUX14->CLBLM_L_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX14" }, "CLBLM_L.CLBLM_IMUX15->CLBLM_M_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX15" }, "CLBLM_L.CLBLM_IMUX16->CLBLM_L_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX16" }, "CLBLM_L.CLBLM_IMUX17->CLBLM_M_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX17" }, "CLBLM_L.CLBLM_IMUX18->CLBLM_M_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX18" }, "CLBLM_L.CLBLM_IMUX19->CLBLM_L_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX19" }, "CLBLM_L.CLBLM_IMUX2->CLBLM_M_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX2" }, "CLBLM_L.CLBLM_IMUX20->CLBLM_L_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX20" }, "CLBLM_L.CLBLM_IMUX21->CLBLM_L_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX21" }, "CLBLM_L.CLBLM_IMUX22->CLBLM_M_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX22" }, "CLBLM_L.CLBLM_IMUX23->CLBLM_L_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX23" }, "CLBLM_L.CLBLM_IMUX24->CLBLM_M_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX24" }, "CLBLM_L.CLBLM_IMUX25->CLBLM_L_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX25" }, "CLBLM_L.CLBLM_IMUX26->CLBLM_L_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX26" }, "CLBLM_L.CLBLM_IMUX27->CLBLM_M_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX27" }, "CLBLM_L.CLBLM_IMUX28->CLBLM_M_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX28" }, "CLBLM_L.CLBLM_IMUX29->CLBLM_M_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX29" }, "CLBLM_L.CLBLM_IMUX3->CLBLM_L_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX3" }, "CLBLM_L.CLBLM_IMUX30->CLBLM_L_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX30" }, "CLBLM_L.CLBLM_IMUX31->CLBLM_M_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX31" }, "CLBLM_L.CLBLM_IMUX32->CLBLM_M_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX32" }, "CLBLM_L.CLBLM_IMUX33->CLBLM_L_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX33" }, "CLBLM_L.CLBLM_IMUX34->CLBLM_L_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX34" }, "CLBLM_L.CLBLM_IMUX35->CLBLM_M_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX35" }, "CLBLM_L.CLBLM_IMUX36->CLBLM_L_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX36" }, "CLBLM_L.CLBLM_IMUX37->CLBLM_L_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX37" }, "CLBLM_L.CLBLM_IMUX38->CLBLM_M_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX38" }, "CLBLM_L.CLBLM_IMUX39->CLBLM_L_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX39" }, "CLBLM_L.CLBLM_IMUX4->CLBLM_M_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX4" }, "CLBLM_L.CLBLM_IMUX40->CLBLM_M_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX40" }, "CLBLM_L.CLBLM_IMUX41->CLBLM_L_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX41" }, "CLBLM_L.CLBLM_IMUX42->CLBLM_L_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX42" }, "CLBLM_L.CLBLM_IMUX43->CLBLM_M_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX43" }, "CLBLM_L.CLBLM_IMUX44->CLBLM_M_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX44" }, "CLBLM_L.CLBLM_IMUX45->CLBLM_M_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX45" }, "CLBLM_L.CLBLM_IMUX46->CLBLM_L_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX46" }, "CLBLM_L.CLBLM_IMUX47->CLBLM_M_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX47" }, "CLBLM_L.CLBLM_IMUX5->CLBLM_L_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX5" }, "CLBLM_L.CLBLM_IMUX6->CLBLM_L_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX6" }, "CLBLM_L.CLBLM_IMUX7->CLBLM_M_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX7" }, "CLBLM_L.CLBLM_IMUX8->CLBLM_M_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX8" }, "CLBLM_L.CLBLM_IMUX9->CLBLM_L_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX9" }, "CLBLM_L.CLBLM_L_A->>CLBLM_L_AMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.071", + "0.088", + "0.168", + "0.209" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_AMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.071", + "0.088", + "0.168", + "0.209" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A" }, "CLBLM_L.CLBLM_L_A->CLBLM_LOGIC_OUTS8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_A" }, "CLBLM_L.CLBLM_L_A1->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A1" }, "CLBLM_L.CLBLM_L_A2->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A2" }, "CLBLM_L.CLBLM_L_A3->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A3" }, 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"src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B6" }, "CLBLM_L.CLBLM_L_BMUX->CLBLM_LOGIC_OUTS17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_BMUX" }, "CLBLM_L.CLBLM_L_BQ->CLBLM_LOGIC_OUTS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_BQ" }, "CLBLM_L.CLBLM_L_C->>CLBLM_L_CMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.069", + "0.086", + "0.166", + "0.205" + ], + "in_cap": null, + "res": "0.0" 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"dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C4" }, "CLBLM_L.CLBLM_L_C5->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C5" }, "CLBLM_L.CLBLM_L_C6->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C6" }, "CLBLM_L.CLBLM_L_CMUX->CLBLM_LOGIC_OUTS18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_CMUX" }, "CLBLM_L.CLBLM_L_COUT->>CLBLM_L_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.131", + "0.246", + "0.305" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.105", + "0.131", + "0.246", + "0.305" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_COUT" }, "CLBLM_L.CLBLM_L_COUT->CLBLM_L_COUT_N": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_COUT_N", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_COUT" }, "CLBLM_L.CLBLM_L_CQ->CLBLM_LOGIC_OUTS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_CQ" }, "CLBLM_L.CLBLM_L_D->>CLBLM_L_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.075", + "0.093", + "0.170", + "0.211" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.075", + "0.093", + "0.170", + "0.211" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_D" }, "CLBLM_L.CLBLM_L_D->CLBLM_LOGIC_OUTS11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_D" }, "CLBLM_L.CLBLM_L_D1->>CLBLM_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_D1" }, "CLBLM_L.CLBLM_L_D2->>CLBLM_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + 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null, + "res": "0.000" + }, "src_wire": "CLBLM_M_C" }, "CLBLM_L.CLBLM_M_C1->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C1" }, "CLBLM_L.CLBLM_M_C2->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C2" }, "CLBLM_L.CLBLM_M_C3->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + 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"0.300" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.104", + "0.130", + "0.242", + "0.300" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_COUT" }, "CLBLM_L.CLBLM_M_COUT->CLBLM_M_COUT_N": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_COUT_N", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_COUT" }, "CLBLM_L.CLBLM_M_CQ->CLBLM_LOGIC_OUTS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_CQ" }, "CLBLM_L.CLBLM_M_D->>CLBLM_M_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.077", + "0.095", + "0.173", + "0.214" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.077", + "0.095", + "0.173", + "0.214" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D" }, "CLBLM_L.CLBLM_M_D->CLBLM_LOGIC_OUTS15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_D" }, "CLBLM_L.CLBLM_M_D1->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D1" }, "CLBLM_L.CLBLM_M_D2->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D2" }, "CLBLM_L.CLBLM_M_D3->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D3" }, "CLBLM_L.CLBLM_M_D4->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D4" }, "CLBLM_L.CLBLM_M_D5->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D5" }, "CLBLM_L.CLBLM_M_D6->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D6" }, "CLBLM_L.CLBLM_M_DMUX->CLBLM_LOGIC_OUTS23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_DMUX" }, "CLBLM_L.CLBLM_M_DQ->CLBLM_LOGIC_OUTS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_DQ" } }, @@ -1063,51 +3304,456 @@ "name": "X1Y0", "prefix": "SLICE", "site_pins": { - "A": "CLBLM_L_A", - "A1": "CLBLM_L_A1", - "A2": "CLBLM_L_A2", - "A3": "CLBLM_L_A3", - "A4": "CLBLM_L_A4", - "A5": "CLBLM_L_A5", - "A6": "CLBLM_L_A6", - "AMUX": "CLBLM_L_AMUX", - "AQ": "CLBLM_L_AQ", - "AX": "CLBLM_L_AX", - "B": "CLBLM_L_B", - "B1": "CLBLM_L_B1", - "B2": "CLBLM_L_B2", - "B3": "CLBLM_L_B3", - "B4": "CLBLM_L_B4", - "B5": "CLBLM_L_B5", - "B6": "CLBLM_L_B6", - "BMUX": "CLBLM_L_BMUX", - "BQ": "CLBLM_L_BQ", - "BX": "CLBLM_L_BX", - "C": "CLBLM_L_C", - "C1": "CLBLM_L_C1", - "C2": "CLBLM_L_C2", - "C3": "CLBLM_L_C3", - "C4": "CLBLM_L_C4", - "C5": "CLBLM_L_C5", - "C6": "CLBLM_L_C6", - "CE": "CLBLM_L_CE", - "CIN": "CLBLM_L_CIN", - "CLK": "CLBLM_L_CLK", - "CMUX": "CLBLM_L_CMUX", - "COUT": "CLBLM_L_COUT", - "CQ": "CLBLM_L_CQ", - "CX": "CLBLM_L_CX", - "D": "CLBLM_L_D", - "D1": "CLBLM_L_D1", - "D2": "CLBLM_L_D2", - "D3": "CLBLM_L_D3", - "D4": "CLBLM_L_D4", - "D5": "CLBLM_L_D5", - "D6": "CLBLM_L_D6", - "DMUX": "CLBLM_L_DMUX", - "DQ": "CLBLM_L_DQ", - "DX": "CLBLM_L_DX", - "SR": "CLBLM_L_SR" + "A": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1326.1875", + "wire": "CLBLM_L_A" + }, + "A1": { + "cap": "0.000", + "delay": [ + "0.172", + "0.214", + "0.416", + "0.516" + ], + "wire": "CLBLM_L_A1" + }, + "A2": { + "cap": "0.000", + "delay": [ + "0.170", + "0.212", + "0.409", + "0.507" + ], + "wire": "CLBLM_L_A2" + }, + "A3": { + "cap": "0.000", + "delay": [ + "0.107", + "0.133", + "0.278", + "0.344" + ], + "wire": "CLBLM_L_A3" + }, + "A4": { + "cap": "0.000", + "delay": [ + "0.086", + "0.107", + "0.229", + "0.284" + ], + "wire": "CLBLM_L_A4" + }, + "A5": { + "cap": "0.000", + "delay": [ + "0.033", + "0.042", + "0.091", + "0.112" + ], + "wire": "CLBLM_L_A5" + }, + "A6": { + "cap": "0.000", + "delay": [ + "0.002", + "0.002", + "0.004", + "0.005" + ], + "wire": "CLBLM_L_A6" + }, + "AMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1852.976125", + "wire": "CLBLM_L_AMUX" + }, + "AQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_L_AQ" + }, + "AX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_AX" + }, + "B": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1404.5625", + "wire": "CLBLM_L_B" + }, + "B1": { + "cap": "0.000", + "delay": [ + "0.171", + "0.213", + "0.417", + "0.518" + ], + "wire": "CLBLM_L_B1" + }, + "B2": { + "cap": "0.000", + "delay": [ + "0.170", + "0.212", + "0.408", + "0.506" + ], + "wire": "CLBLM_L_B2" + }, + "B3": { + "cap": "0.000", + "delay": [ + "0.109", + "0.136", + "0.281", + "0.349" + ], + "wire": "CLBLM_L_B3" + }, + "B4": { + "cap": "0.000", + "delay": [ + "0.086", + "0.107", + "0.228", + "0.282" + ], + "wire": "CLBLM_L_B4" + }, + "B5": { + "cap": "0.000", + "delay": [ + "0.034", + "0.043", + "0.093", + "0.116" + ], + "wire": "CLBLM_L_B5" + }, + "B6": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.002", + "0.002" + ], + "wire": "CLBLM_L_B6" + }, + "BMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1869.3455", + "wire": "CLBLM_L_BMUX" + }, + "BQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_L_BQ" + }, + "BX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_BX" + }, + "C": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1453.375", + "wire": "CLBLM_L_C" + }, + "C1": { + "cap": "0.000", + "delay": [ + "0.173", + "0.215", + "0.417", + "0.517" + ], + "wire": "CLBLM_L_C1" + }, + "C2": { + "cap": "0.000", + "delay": [ + "0.171", + "0.213", + "0.409", + "0.507" + ], + "wire": "CLBLM_L_C2" + }, + "C3": { + "cap": "0.000", + "delay": [ + "0.110", + "0.137", + "0.283", + "0.351" + ], + "wire": "CLBLM_L_C3" + }, + "C4": { + "cap": "0.000", + "delay": [ + "0.087", + "0.108", + "0.227", + "0.281" + ], + "wire": "CLBLM_L_C4" + }, + "C5": { + "cap": "0.000", + "delay": [ + "0.033", + "0.042", + "0.092", + "0.114" + ], + "wire": "CLBLM_L_C5" + }, + "C6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_C6" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_CE" + }, + "CIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_CIN" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_CLK" + }, + "CMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1826.7858125", + "wire": "CLBLM_L_CMUX" + }, + "COUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "CLBLM_L_COUT" + }, + "CQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_L_CQ" + }, + "CX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_CX" + }, + "D": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1408.0", + "wire": "CLBLM_L_D" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.174", + "0.216", + "0.421", + "0.522" + ], + "wire": "CLBLM_L_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.171", + "0.213", + "0.410", + "0.509" + ], + "wire": "CLBLM_L_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.109", + "0.136", + "0.279", + "0.346" + ], + "wire": "CLBLM_L_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.088", + "0.109", + "0.229", + "0.284" + ], + "wire": "CLBLM_L_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.033", + "0.042", + "0.091", + "0.113" + ], + "wire": "CLBLM_L_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.003", + "0.003", + "0.004", + "0.005" + ], + "wire": "CLBLM_L_D6" + }, + "DMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1826.7858125", + "wire": "CLBLM_L_DMUX" + }, + "DQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_L_DQ" + }, + "DX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_DX" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_SR" + } }, "type": "SLICEL", "x_coord": 1, @@ -1117,56 +3763,506 @@ "name": "X0Y0", "prefix": "SLICE", "site_pins": { - "A": "CLBLM_M_A", - "A1": "CLBLM_M_A1", - "A2": "CLBLM_M_A2", - "A3": "CLBLM_M_A3", - "A4": "CLBLM_M_A4", - "A5": "CLBLM_M_A5", - "A6": "CLBLM_M_A6", - "AI": "CLBLM_M_AI", - "AMUX": "CLBLM_M_AMUX", - "AQ": "CLBLM_M_AQ", - "AX": "CLBLM_M_AX", - "B": "CLBLM_M_B", - "B1": "CLBLM_M_B1", - "B2": "CLBLM_M_B2", - "B3": "CLBLM_M_B3", - "B4": "CLBLM_M_B4", - "B5": "CLBLM_M_B5", - "B6": "CLBLM_M_B6", - "BI": "CLBLM_M_BI", - "BMUX": "CLBLM_M_BMUX", - "BQ": "CLBLM_M_BQ", - "BX": "CLBLM_M_BX", - "C": "CLBLM_M_C", - "C1": "CLBLM_M_C1", - "C2": "CLBLM_M_C2", - "C3": "CLBLM_M_C3", - "C4": "CLBLM_M_C4", - "C5": "CLBLM_M_C5", - "C6": "CLBLM_M_C6", - "CE": "CLBLM_M_CE", - "CI": "CLBLM_M_CI", - "CIN": "CLBLM_M_CIN", - "CLK": "CLBLM_M_CLK", - "CMUX": "CLBLM_M_CMUX", - "COUT": "CLBLM_M_COUT", - "CQ": "CLBLM_M_CQ", - "CX": "CLBLM_M_CX", - "D": "CLBLM_M_D", - "D1": "CLBLM_M_D1", - "D2": "CLBLM_M_D2", - "D3": "CLBLM_M_D3", - "D4": "CLBLM_M_D4", - "D5": "CLBLM_M_D5", - "D6": "CLBLM_M_D6", - "DI": "CLBLM_M_DI", - "DMUX": "CLBLM_M_DMUX", - "DQ": "CLBLM_M_DQ", - "DX": "CLBLM_M_DX", - "SR": "CLBLM_M_SR", - "WE": "CLBLM_M_WE" + "A": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1463.6875", + "wire": "CLBLM_M_A" + }, + "A1": { + "cap": "0.000", + "delay": [ + "0.180", + "0.225", + "0.428", + "0.531" + ], + "wire": "CLBLM_M_A1" + }, + "A2": { + "cap": "0.000", + "delay": [ + "0.174", + "0.216", + "0.413", + "0.512" + ], + "wire": "CLBLM_M_A2" + }, + "A3": { + "cap": "0.000", + "delay": [ + "0.114", + "0.141", + "0.300", + "0.372" + ], + "wire": "CLBLM_M_A3" + }, + "A4": { + "cap": "0.000", + "delay": [ + "0.091", + "0.113", + "0.244", + "0.303" + ], + "wire": "CLBLM_M_A4" + }, + "A5": { + "cap": "0.000", + "delay": [ + "0.038", + "0.048", + "0.102", + "0.126" + ], + "wire": "CLBLM_M_A5" + }, + "A6": { + "cap": "0.000", + "delay": [ + "0.007", + "0.008", + "0.013", + "0.016" + ], + "wire": "CLBLM_M_A6" + }, + "AI": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_AI" + }, + "AMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1833.3335625", + "wire": "CLBLM_M_AMUX" + }, + "AQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_M_AQ" + }, + "AX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_AX" + }, + "B": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1408.0", + "wire": "CLBLM_M_B" + }, + "B1": { + "cap": "0.000", + "delay": [ + "0.175", + "0.218", + "0.420", + "0.521" + ], + "wire": "CLBLM_M_B1" + }, + "B2": { + "cap": "0.000", + "delay": [ + "0.172", + "0.214", + "0.406", + "0.504" + ], + "wire": "CLBLM_M_B2" + }, + "B3": { + "cap": "0.000", + "delay": [ + "0.114", + "0.141", + "0.298", + "0.370" + ], + "wire": "CLBLM_M_B3" + }, + "B4": { + "cap": "0.000", + "delay": [ + "0.090", + "0.112", + "0.242", + "0.300" + ], + "wire": "CLBLM_M_B4" + }, + "B5": { + "cap": "0.000", + "delay": [ + "0.042", + "0.052", + "0.111", + "0.137" + ], + "wire": "CLBLM_M_B5" + }, + "B6": { + "cap": "0.000", + "delay": [ + "0.005", + "0.006", + "0.011", + "0.013" + ], + "wire": "CLBLM_M_B6" + }, + "BI": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_BI" + }, + "BMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1898.8096875", + "wire": "CLBLM_M_BMUX" + }, + "BQ": { + "delay": [ + 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+ ], + "wire": "CLBLM_M_C6" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_CE" + }, + "CI": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_CI" + }, + "CIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_CIN" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_CLK" + }, + "CMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1833.3335625", + "wire": "CLBLM_M_CMUX" + }, + "COUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "CLBLM_M_COUT" + }, + "CQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_M_CQ" + }, + "CX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_CX" + }, + "D": { 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+ "res": "1859.523875", + "wire": "CLBLM_M_DMUX" + }, + "DQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_M_DQ" + }, + "DX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_DX" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_SR" + }, + "WE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_WE" + } }, "type": "SLICEM", "x_coord": 0, @@ -1174,321 +4270,417 @@ } ], "tile_type": "CLBLM_L", - "wires": [ - "CLBLM_BYP0", - "CLBLM_BYP1", - "CLBLM_BYP2", - "CLBLM_BYP3", - "CLBLM_BYP4", - "CLBLM_BYP5", - "CLBLM_BYP6", - "CLBLM_BYP7", - "CLBLM_CLK0", - "CLBLM_CLK1", - "CLBLM_CTRL0", - "CLBLM_CTRL1", - "CLBLM_EE2A0", - "CLBLM_EE2A1", - "CLBLM_EE2A2", - "CLBLM_EE2A3", - "CLBLM_EE2BEG0", - "CLBLM_EE2BEG1", - "CLBLM_EE2BEG2", - "CLBLM_EE2BEG3", - "CLBLM_EE4A0", - "CLBLM_EE4A1", - "CLBLM_EE4A2", - "CLBLM_EE4A3", - "CLBLM_EE4B0", - "CLBLM_EE4B1", - "CLBLM_EE4B2", - "CLBLM_EE4B3", - "CLBLM_EE4BEG0", - "CLBLM_EE4BEG1", - "CLBLM_EE4BEG2", - "CLBLM_EE4BEG3", - "CLBLM_EE4C0", - "CLBLM_EE4C1", - "CLBLM_EE4C2", - "CLBLM_EE4C3", - "CLBLM_EL1BEG0", - "CLBLM_EL1BEG1", - "CLBLM_EL1BEG2", - "CLBLM_EL1BEG3", - "CLBLM_ER1BEG0", - "CLBLM_ER1BEG1", - "CLBLM_ER1BEG2", - "CLBLM_ER1BEG3", - "CLBLM_FAN0", - "CLBLM_FAN1", - "CLBLM_FAN2", - "CLBLM_FAN3", - "CLBLM_FAN4", - "CLBLM_FAN5", - "CLBLM_FAN6", - "CLBLM_FAN7", - "CLBLM_IMUX0", - "CLBLM_IMUX1", - "CLBLM_IMUX10", - "CLBLM_IMUX11", - "CLBLM_IMUX12", - "CLBLM_IMUX13", - "CLBLM_IMUX14", - "CLBLM_IMUX15", - "CLBLM_IMUX16", - "CLBLM_IMUX17", - "CLBLM_IMUX18", - "CLBLM_IMUX19", - "CLBLM_IMUX2", - "CLBLM_IMUX20", - "CLBLM_IMUX21", - "CLBLM_IMUX22", - "CLBLM_IMUX23", - "CLBLM_IMUX24", - "CLBLM_IMUX25", - "CLBLM_IMUX26", - "CLBLM_IMUX27", - "CLBLM_IMUX28", - "CLBLM_IMUX29", - "CLBLM_IMUX3", - "CLBLM_IMUX30", - "CLBLM_IMUX31", - "CLBLM_IMUX32", - "CLBLM_IMUX33", - "CLBLM_IMUX34", - "CLBLM_IMUX35", - "CLBLM_IMUX36", - "CLBLM_IMUX37", - "CLBLM_IMUX38", - "CLBLM_IMUX39", - "CLBLM_IMUX4", - "CLBLM_IMUX40", - "CLBLM_IMUX41", - "CLBLM_IMUX42", - "CLBLM_IMUX43", - "CLBLM_IMUX44", - "CLBLM_IMUX45", - "CLBLM_IMUX46", - "CLBLM_IMUX47", - "CLBLM_IMUX5", - "CLBLM_IMUX6", - "CLBLM_IMUX7", - "CLBLM_IMUX8", - "CLBLM_IMUX9", - "CLBLM_LH1", - "CLBLM_LH10", - "CLBLM_LH11", - "CLBLM_LH12", - "CLBLM_LH2", - "CLBLM_LH3", - "CLBLM_LH4", - "CLBLM_LH5", - "CLBLM_LH6", - "CLBLM_LH7", - "CLBLM_LH8", - "CLBLM_LH9", - "CLBLM_LOGIC_OUTS0", - "CLBLM_LOGIC_OUTS1", - "CLBLM_LOGIC_OUTS10", - "CLBLM_LOGIC_OUTS11", - "CLBLM_LOGIC_OUTS12", - "CLBLM_LOGIC_OUTS13", - "CLBLM_LOGIC_OUTS14", - "CLBLM_LOGIC_OUTS15", - "CLBLM_LOGIC_OUTS16", - "CLBLM_LOGIC_OUTS17", - "CLBLM_LOGIC_OUTS18", - "CLBLM_LOGIC_OUTS19", - "CLBLM_LOGIC_OUTS2", - "CLBLM_LOGIC_OUTS20", - "CLBLM_LOGIC_OUTS21", - "CLBLM_LOGIC_OUTS22", - "CLBLM_LOGIC_OUTS23", - "CLBLM_LOGIC_OUTS3", - "CLBLM_LOGIC_OUTS4", - "CLBLM_LOGIC_OUTS5", - "CLBLM_LOGIC_OUTS6", - "CLBLM_LOGIC_OUTS7", - "CLBLM_LOGIC_OUTS8", - "CLBLM_LOGIC_OUTS9", - "CLBLM_L_A", - "CLBLM_L_A1", - "CLBLM_L_A2", - "CLBLM_L_A3", - "CLBLM_L_A4", - "CLBLM_L_A5", - "CLBLM_L_A6", - "CLBLM_L_AMUX", - "CLBLM_L_AQ", - "CLBLM_L_AX", - "CLBLM_L_B", - "CLBLM_L_B1", - "CLBLM_L_B2", - "CLBLM_L_B3", - "CLBLM_L_B4", - "CLBLM_L_B5", - "CLBLM_L_B6", - "CLBLM_L_BMUX", - "CLBLM_L_BQ", - "CLBLM_L_BX", - "CLBLM_L_C", - "CLBLM_L_C1", - "CLBLM_L_C2", - "CLBLM_L_C3", - "CLBLM_L_C4", - "CLBLM_L_C5", - "CLBLM_L_C6", - "CLBLM_L_CE", - "CLBLM_L_CIN", - "CLBLM_L_CLK", - "CLBLM_L_CMUX", - "CLBLM_L_COUT", - "CLBLM_L_COUT_N", - "CLBLM_L_CQ", - "CLBLM_L_CX", - "CLBLM_L_D", - "CLBLM_L_D1", - "CLBLM_L_D2", - "CLBLM_L_D3", - "CLBLM_L_D4", - "CLBLM_L_D5", - "CLBLM_L_D6", - "CLBLM_L_DMUX", - "CLBLM_L_DQ", - "CLBLM_L_DX", - "CLBLM_L_SR", - "CLBLM_MONITOR_N", - "CLBLM_MONITOR_P", - "CLBLM_M_A", - "CLBLM_M_A1", - "CLBLM_M_A2", - "CLBLM_M_A3", - "CLBLM_M_A4", - "CLBLM_M_A5", - "CLBLM_M_A6", - "CLBLM_M_AI", - "CLBLM_M_AMUX", - "CLBLM_M_AQ", - "CLBLM_M_AX", - "CLBLM_M_B", - "CLBLM_M_B1", - "CLBLM_M_B2", - "CLBLM_M_B3", - "CLBLM_M_B4", - "CLBLM_M_B5", - "CLBLM_M_B6", - "CLBLM_M_BI", - "CLBLM_M_BMUX", - "CLBLM_M_BQ", - "CLBLM_M_BX", - "CLBLM_M_C", - "CLBLM_M_C1", - "CLBLM_M_C2", - "CLBLM_M_C3", - "CLBLM_M_C4", - "CLBLM_M_C5", - "CLBLM_M_C6", - "CLBLM_M_CE", - "CLBLM_M_CI", - "CLBLM_M_CIN", - "CLBLM_M_CLK", - "CLBLM_M_CMUX", - "CLBLM_M_COUT", - "CLBLM_M_COUT_N", - "CLBLM_M_CQ", - "CLBLM_M_CX", - "CLBLM_M_D", - "CLBLM_M_D1", - "CLBLM_M_D2", - "CLBLM_M_D3", - "CLBLM_M_D4", - "CLBLM_M_D5", - "CLBLM_M_D6", - "CLBLM_M_DI", - "CLBLM_M_DMUX", - "CLBLM_M_DQ", - "CLBLM_M_DX", - "CLBLM_M_SR", - "CLBLM_M_WE", - "CLBLM_NE2A0", - "CLBLM_NE2A1", - "CLBLM_NE2A2", - "CLBLM_NE2A3", - "CLBLM_NE4BEG0", - "CLBLM_NE4BEG1", - "CLBLM_NE4BEG2", - "CLBLM_NE4BEG3", - "CLBLM_NE4C0", - "CLBLM_NE4C1", - "CLBLM_NE4C2", - "CLBLM_NE4C3", - "CLBLM_NW2A0", - "CLBLM_NW2A1", - "CLBLM_NW2A2", - "CLBLM_NW2A3", - "CLBLM_NW4A0", - "CLBLM_NW4A1", - "CLBLM_NW4A2", - "CLBLM_NW4A3", - "CLBLM_NW4END0", - "CLBLM_NW4END1", - "CLBLM_NW4END2", - "CLBLM_NW4END3", - "CLBLM_SE2A0", - "CLBLM_SE2A1", - "CLBLM_SE2A2", - "CLBLM_SE2A3", - "CLBLM_SE4BEG0", - "CLBLM_SE4BEG1", - "CLBLM_SE4BEG2", - "CLBLM_SE4BEG3", - "CLBLM_SE4C0", - "CLBLM_SE4C1", - "CLBLM_SE4C2", - "CLBLM_SE4C3", - "CLBLM_SW2A0", - "CLBLM_SW2A1", - "CLBLM_SW2A2", - "CLBLM_SW2A3", - "CLBLM_SW4A0", - "CLBLM_SW4A1", - "CLBLM_SW4A2", - "CLBLM_SW4A3", - "CLBLM_SW4END0", - "CLBLM_SW4END1", - "CLBLM_SW4END2", - "CLBLM_SW4END3", - "CLBLM_WL1END0", - "CLBLM_WL1END1", - "CLBLM_WL1END2", - "CLBLM_WL1END3", - "CLBLM_WR1END0", - "CLBLM_WR1END1", - "CLBLM_WR1END2", - "CLBLM_WR1END3", - "CLBLM_WW2A0", - "CLBLM_WW2A1", - "CLBLM_WW2A2", - "CLBLM_WW2A3", - "CLBLM_WW2END0", - "CLBLM_WW2END1", - "CLBLM_WW2END2", - "CLBLM_WW2END3", - "CLBLM_WW4A0", - "CLBLM_WW4A1", - "CLBLM_WW4A2", - "CLBLM_WW4A3", - "CLBLM_WW4B0", - "CLBLM_WW4B1", - "CLBLM_WW4B2", - "CLBLM_WW4B3", - "CLBLM_WW4C0", - "CLBLM_WW4C1", - "CLBLM_WW4C2", - "CLBLM_WW4C3", - "CLBLM_WW4END0", - "CLBLM_WW4END1", - "CLBLM_WW4END2", - "CLBLM_WW4END3" - ] + "wires": { + "CLBLM_BYP0": null, + "CLBLM_BYP1": null, + "CLBLM_BYP2": null, + "CLBLM_BYP3": null, + "CLBLM_BYP4": null, + "CLBLM_BYP5": null, + "CLBLM_BYP6": null, + "CLBLM_BYP7": null, + "CLBLM_CLK0": null, + "CLBLM_CLK1": null, + "CLBLM_CTRL0": null, + "CLBLM_CTRL1": null, + "CLBLM_EE2A0": null, + "CLBLM_EE2A1": null, + "CLBLM_EE2A2": null, + "CLBLM_EE2A3": null, + "CLBLM_EE2BEG0": null, + "CLBLM_EE2BEG1": null, + "CLBLM_EE2BEG2": null, + "CLBLM_EE2BEG3": null, + "CLBLM_EE4A0": null, + "CLBLM_EE4A1": null, + "CLBLM_EE4A2": null, + "CLBLM_EE4A3": null, + "CLBLM_EE4B0": null, + "CLBLM_EE4B1": null, + "CLBLM_EE4B2": null, + "CLBLM_EE4B3": null, + "CLBLM_EE4BEG0": null, + "CLBLM_EE4BEG1": null, + "CLBLM_EE4BEG2": null, + "CLBLM_EE4BEG3": null, + "CLBLM_EE4C0": null, + "CLBLM_EE4C1": null, + "CLBLM_EE4C2": null, + "CLBLM_EE4C3": null, + "CLBLM_EL1BEG0": { + "cap": "4.690", + "res": "52.151" + }, + "CLBLM_EL1BEG1": { + "cap": "4.690", + "res": "52.151" + }, + "CLBLM_EL1BEG2": { + "cap": "4.690", + "res": "52.151" + }, + "CLBLM_EL1BEG3": { + "cap": "4.690", + "res": "52.151" + }, + "CLBLM_ER1BEG0": { + "cap": "5.564", + "res": "90.496" + }, + "CLBLM_ER1BEG1": { + "cap": "5.564", + "res": "90.496" + }, + "CLBLM_ER1BEG2": { + "cap": "5.564", + "res": "90.496" + }, + "CLBLM_ER1BEG3": { + "cap": "5.564", + "res": "90.496" + }, + "CLBLM_FAN0": null, + "CLBLM_FAN1": null, + "CLBLM_FAN2": null, + "CLBLM_FAN3": null, + "CLBLM_FAN4": null, + "CLBLM_FAN5": null, + "CLBLM_FAN6": null, + "CLBLM_FAN7": null, + "CLBLM_IMUX0": null, + "CLBLM_IMUX1": null, + "CLBLM_IMUX10": null, + "CLBLM_IMUX11": null, + "CLBLM_IMUX12": null, + "CLBLM_IMUX13": null, + "CLBLM_IMUX14": null, + "CLBLM_IMUX15": null, + "CLBLM_IMUX16": null, + "CLBLM_IMUX17": null, + "CLBLM_IMUX18": null, + "CLBLM_IMUX19": null, + "CLBLM_IMUX2": null, + "CLBLM_IMUX20": null, + "CLBLM_IMUX21": null, + "CLBLM_IMUX22": null, + "CLBLM_IMUX23": null, + "CLBLM_IMUX24": null, + "CLBLM_IMUX25": null, + "CLBLM_IMUX26": null, + "CLBLM_IMUX27": null, + "CLBLM_IMUX28": null, + "CLBLM_IMUX29": null, + "CLBLM_IMUX3": null, + "CLBLM_IMUX30": null, + "CLBLM_IMUX31": null, + "CLBLM_IMUX32": null, + "CLBLM_IMUX33": null, + "CLBLM_IMUX34": null, + "CLBLM_IMUX35": null, + "CLBLM_IMUX36": null, + "CLBLM_IMUX37": null, + "CLBLM_IMUX38": null, + "CLBLM_IMUX39": null, + "CLBLM_IMUX4": null, + "CLBLM_IMUX40": null, + "CLBLM_IMUX41": null, + "CLBLM_IMUX42": null, + "CLBLM_IMUX43": null, + "CLBLM_IMUX44": null, + "CLBLM_IMUX45": null, + "CLBLM_IMUX46": null, + "CLBLM_IMUX47": null, + "CLBLM_IMUX5": null, + "CLBLM_IMUX6": null, + "CLBLM_IMUX7": null, + "CLBLM_IMUX8": null, + "CLBLM_IMUX9": null, + "CLBLM_LH1": null, + "CLBLM_LH10": null, + "CLBLM_LH11": null, + "CLBLM_LH12": null, + "CLBLM_LH2": null, + "CLBLM_LH3": null, + "CLBLM_LH4": null, + "CLBLM_LH5": null, + "CLBLM_LH6": null, + "CLBLM_LH7": null, + "CLBLM_LH8": null, + "CLBLM_LH9": null, + "CLBLM_LOGIC_OUTS0": null, + "CLBLM_LOGIC_OUTS1": null, + "CLBLM_LOGIC_OUTS10": null, + "CLBLM_LOGIC_OUTS11": null, + "CLBLM_LOGIC_OUTS12": null, + "CLBLM_LOGIC_OUTS13": null, + "CLBLM_LOGIC_OUTS14": null, + "CLBLM_LOGIC_OUTS15": null, + "CLBLM_LOGIC_OUTS16": null, + "CLBLM_LOGIC_OUTS17": null, + "CLBLM_LOGIC_OUTS18": null, + "CLBLM_LOGIC_OUTS19": null, + "CLBLM_LOGIC_OUTS2": null, + "CLBLM_LOGIC_OUTS20": null, + "CLBLM_LOGIC_OUTS21": null, + "CLBLM_LOGIC_OUTS22": null, + "CLBLM_LOGIC_OUTS23": null, + "CLBLM_LOGIC_OUTS3": null, + "CLBLM_LOGIC_OUTS4": null, + "CLBLM_LOGIC_OUTS5": null, + "CLBLM_LOGIC_OUTS6": null, + "CLBLM_LOGIC_OUTS7": null, + "CLBLM_LOGIC_OUTS8": null, + "CLBLM_LOGIC_OUTS9": null, + "CLBLM_L_A": null, + "CLBLM_L_A1": null, + "CLBLM_L_A2": null, + "CLBLM_L_A3": null, + "CLBLM_L_A4": null, + "CLBLM_L_A5": null, + "CLBLM_L_A6": null, + "CLBLM_L_AMUX": null, + "CLBLM_L_AQ": null, + "CLBLM_L_AX": null, + "CLBLM_L_B": null, + "CLBLM_L_B1": null, + "CLBLM_L_B2": null, + "CLBLM_L_B3": null, + "CLBLM_L_B4": null, + "CLBLM_L_B5": null, + "CLBLM_L_B6": null, + "CLBLM_L_BMUX": null, + "CLBLM_L_BQ": null, + "CLBLM_L_BX": null, + "CLBLM_L_C": null, + "CLBLM_L_C1": null, + "CLBLM_L_C2": null, + "CLBLM_L_C3": null, + "CLBLM_L_C4": null, + "CLBLM_L_C5": null, + "CLBLM_L_C6": null, + "CLBLM_L_CE": null, + "CLBLM_L_CIN": null, + "CLBLM_L_CLK": null, + "CLBLM_L_CMUX": null, + "CLBLM_L_COUT": null, + "CLBLM_L_COUT_N": null, + "CLBLM_L_CQ": null, + "CLBLM_L_CX": null, + "CLBLM_L_D": null, + "CLBLM_L_D1": null, + "CLBLM_L_D2": null, + "CLBLM_L_D3": null, + "CLBLM_L_D4": null, + "CLBLM_L_D5": null, + "CLBLM_L_D6": null, + "CLBLM_L_DMUX": null, + "CLBLM_L_DQ": null, + "CLBLM_L_DX": null, + "CLBLM_L_SR": null, + "CLBLM_MONITOR_N": null, + "CLBLM_MONITOR_P": null, + "CLBLM_M_A": null, + "CLBLM_M_A1": null, + "CLBLM_M_A2": null, + "CLBLM_M_A3": null, + "CLBLM_M_A4": null, + "CLBLM_M_A5": null, + "CLBLM_M_A6": null, + "CLBLM_M_AI": null, + "CLBLM_M_AMUX": null, + "CLBLM_M_AQ": null, + "CLBLM_M_AX": null, + "CLBLM_M_B": null, + "CLBLM_M_B1": null, + "CLBLM_M_B2": null, + "CLBLM_M_B3": null, + "CLBLM_M_B4": null, + "CLBLM_M_B5": null, + "CLBLM_M_B6": null, + "CLBLM_M_BI": null, + "CLBLM_M_BMUX": null, + "CLBLM_M_BQ": null, + "CLBLM_M_BX": null, + "CLBLM_M_C": null, + "CLBLM_M_C1": null, + "CLBLM_M_C2": null, + "CLBLM_M_C3": null, + "CLBLM_M_C4": null, + "CLBLM_M_C5": null, + "CLBLM_M_C6": null, + "CLBLM_M_CE": null, + "CLBLM_M_CI": null, + "CLBLM_M_CIN": null, + "CLBLM_M_CLK": null, + "CLBLM_M_CMUX": null, + "CLBLM_M_COUT": null, + "CLBLM_M_COUT_N": null, + "CLBLM_M_CQ": null, + "CLBLM_M_CX": null, + "CLBLM_M_D": null, + "CLBLM_M_D1": null, + "CLBLM_M_D2": null, + "CLBLM_M_D3": null, + "CLBLM_M_D4": null, + "CLBLM_M_D5": null, + "CLBLM_M_D6": null, + "CLBLM_M_DI": null, + "CLBLM_M_DMUX": null, + "CLBLM_M_DQ": null, + "CLBLM_M_DX": null, + "CLBLM_M_SR": null, + "CLBLM_M_WE": null, + "CLBLM_NE2A0": { + "cap": "5.469", + "res": "100.092" + }, + "CLBLM_NE2A1": { + "cap": "5.469", + "res": "100.092" + }, + "CLBLM_NE2A2": { + "cap": "5.469", + "res": "100.092" + }, + "CLBLM_NE2A3": { + "cap": "5.469", + "res": "100.092" + }, + "CLBLM_NE4BEG0": null, + "CLBLM_NE4BEG1": null, + "CLBLM_NE4BEG2": null, + "CLBLM_NE4BEG3": null, + "CLBLM_NE4C0": null, + "CLBLM_NE4C1": null, + "CLBLM_NE4C2": null, + "CLBLM_NE4C3": null, + "CLBLM_NW2A0": { + "cap": "5.884", + "res": "91.532" + }, + "CLBLM_NW2A1": { + "cap": "5.884", + "res": "91.532" + }, + "CLBLM_NW2A2": { + "cap": "5.884", + "res": "91.532" + }, + "CLBLM_NW2A3": { + "cap": "5.884", + "res": "91.532" + }, + "CLBLM_NW4A0": null, + "CLBLM_NW4A1": null, + "CLBLM_NW4A2": null, + "CLBLM_NW4A3": null, + "CLBLM_NW4END0": null, + "CLBLM_NW4END1": null, + "CLBLM_NW4END2": null, + "CLBLM_NW4END3": null, + "CLBLM_SE2A0": { + "cap": "5.065", + "res": "90.332" + }, + "CLBLM_SE2A1": { + "cap": "5.065", + "res": "90.332" + }, + "CLBLM_SE2A2": { + "cap": "5.065", + "res": "90.332" + }, + "CLBLM_SE2A3": { + "cap": "5.065", + "res": "90.332" + }, + "CLBLM_SE4BEG0": null, + "CLBLM_SE4BEG1": null, + "CLBLM_SE4BEG2": null, + "CLBLM_SE4BEG3": null, + "CLBLM_SE4C0": null, + "CLBLM_SE4C1": null, + "CLBLM_SE4C2": null, + "CLBLM_SE4C3": null, + "CLBLM_SW2A0": { + "cap": "5.896", + "res": "90.208" + }, + "CLBLM_SW2A1": { + "cap": "5.896", + "res": "90.208" + }, + "CLBLM_SW2A2": { + "cap": "5.896", + "res": "90.208" + }, + "CLBLM_SW2A3": { + "cap": "5.896", + "res": "90.208" + }, + "CLBLM_SW4A0": null, + "CLBLM_SW4A1": null, + "CLBLM_SW4A2": null, + "CLBLM_SW4A3": null, + "CLBLM_SW4END0": null, + "CLBLM_SW4END1": null, + "CLBLM_SW4END2": null, + "CLBLM_SW4END3": null, + "CLBLM_WL1END0": { + "cap": "6.105", + "res": "58.596" + }, + "CLBLM_WL1END1": { + "cap": "6.105", + "res": "58.596" + }, + "CLBLM_WL1END2": { + "cap": "6.105", + "res": "58.596" + }, + "CLBLM_WL1END3": { + "cap": "6.105", + "res": "58.596" + }, + "CLBLM_WR1END0": { + "cap": "5.801", + "res": "94.510" + }, + "CLBLM_WR1END1": { + "cap": "5.801", + "res": "94.510" + }, + "CLBLM_WR1END2": { + "cap": "5.801", + "res": "94.510" + }, + "CLBLM_WR1END3": { + "cap": "5.801", + "res": "94.510" + }, + "CLBLM_WW2A0": null, + "CLBLM_WW2A1": null, + "CLBLM_WW2A2": null, + "CLBLM_WW2A3": null, + "CLBLM_WW2END0": null, + "CLBLM_WW2END1": null, + "CLBLM_WW2END2": null, + "CLBLM_WW2END3": null, + "CLBLM_WW4A0": null, + "CLBLM_WW4A1": null, + "CLBLM_WW4A2": null, + "CLBLM_WW4A3": null, + "CLBLM_WW4B0": null, + "CLBLM_WW4B1": null, + "CLBLM_WW4B2": null, + "CLBLM_WW4B3": null, + "CLBLM_WW4C0": null, + "CLBLM_WW4C1": null, + "CLBLM_WW4C2": null, + "CLBLM_WW4C3": null, + "CLBLM_WW4END0": null, + "CLBLM_WW4END1": null, + "CLBLM_WW4END2": null, + "CLBLM_WW4END3": null + } } diff --git a/zynq7/tile_type_CLBLM_R.json b/zynq7/tile_type_CLBLM_R.json index 466403b..1b7e394 100644 --- a/zynq7/tile_type_CLBLM_R.json +++ b/zynq7/tile_type_CLBLM_R.json @@ -2,1059 +2,3300 @@ "pips": { "CLBLM_R.CLBLM_BYP0->CLBLM_L_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP0" }, "CLBLM_R.CLBLM_BYP1->CLBLM_M_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP1" }, "CLBLM_R.CLBLM_BYP2->CLBLM_L_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP2" }, "CLBLM_R.CLBLM_BYP3->CLBLM_M_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP3" }, "CLBLM_R.CLBLM_BYP4->CLBLM_M_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP4" }, "CLBLM_R.CLBLM_BYP5->CLBLM_L_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP5" }, "CLBLM_R.CLBLM_BYP6->CLBLM_M_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP6" }, "CLBLM_R.CLBLM_BYP7->CLBLM_L_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP7" }, "CLBLM_R.CLBLM_CLK0->CLBLM_L_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CLK0" }, "CLBLM_R.CLBLM_CLK1->CLBLM_M_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CLK1" }, "CLBLM_R.CLBLM_CTRL0->CLBLM_L_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CTRL0" }, "CLBLM_R.CLBLM_CTRL1->CLBLM_M_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CTRL1" }, "CLBLM_R.CLBLM_FAN0->CLBLM_M_AI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_AI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN0" }, "CLBLM_R.CLBLM_FAN2->CLBLM_M_BI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_BI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN2" }, "CLBLM_R.CLBLM_FAN3->CLBLM_M_DI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_DI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN3" }, "CLBLM_R.CLBLM_FAN4->CLBLM_M_WE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_WE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN4" }, "CLBLM_R.CLBLM_FAN5->CLBLM_M_CI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN5" }, "CLBLM_R.CLBLM_FAN6->CLBLM_L_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN6" }, "CLBLM_R.CLBLM_FAN7->CLBLM_M_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN7" }, "CLBLM_R.CLBLM_IMUX0->CLBLM_L_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX0" }, "CLBLM_R.CLBLM_IMUX1->CLBLM_M_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX1" }, "CLBLM_R.CLBLM_IMUX10->CLBLM_L_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX10" }, "CLBLM_R.CLBLM_IMUX11->CLBLM_M_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX11" }, "CLBLM_R.CLBLM_IMUX12->CLBLM_M_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX12" }, "CLBLM_R.CLBLM_IMUX13->CLBLM_L_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX13" }, "CLBLM_R.CLBLM_IMUX14->CLBLM_L_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX14" }, "CLBLM_R.CLBLM_IMUX15->CLBLM_M_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX15" }, "CLBLM_R.CLBLM_IMUX16->CLBLM_L_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX16" }, "CLBLM_R.CLBLM_IMUX17->CLBLM_M_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX17" }, "CLBLM_R.CLBLM_IMUX18->CLBLM_M_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX18" }, "CLBLM_R.CLBLM_IMUX19->CLBLM_L_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX19" }, "CLBLM_R.CLBLM_IMUX2->CLBLM_M_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX2" }, "CLBLM_R.CLBLM_IMUX20->CLBLM_L_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX20" }, "CLBLM_R.CLBLM_IMUX21->CLBLM_L_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX21" }, "CLBLM_R.CLBLM_IMUX22->CLBLM_M_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX22" }, "CLBLM_R.CLBLM_IMUX23->CLBLM_L_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX23" }, "CLBLM_R.CLBLM_IMUX24->CLBLM_M_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX24" }, "CLBLM_R.CLBLM_IMUX25->CLBLM_L_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX25" }, "CLBLM_R.CLBLM_IMUX26->CLBLM_L_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX26" }, "CLBLM_R.CLBLM_IMUX27->CLBLM_M_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX27" }, "CLBLM_R.CLBLM_IMUX28->CLBLM_M_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX28" }, "CLBLM_R.CLBLM_IMUX29->CLBLM_M_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX29" }, "CLBLM_R.CLBLM_IMUX3->CLBLM_L_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX3" }, "CLBLM_R.CLBLM_IMUX30->CLBLM_L_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX30" }, "CLBLM_R.CLBLM_IMUX31->CLBLM_M_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX31" }, "CLBLM_R.CLBLM_IMUX32->CLBLM_M_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX32" }, "CLBLM_R.CLBLM_IMUX33->CLBLM_L_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX33" }, "CLBLM_R.CLBLM_IMUX34->CLBLM_L_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX34" }, "CLBLM_R.CLBLM_IMUX35->CLBLM_M_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX35" }, "CLBLM_R.CLBLM_IMUX36->CLBLM_L_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX36" }, "CLBLM_R.CLBLM_IMUX37->CLBLM_L_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX37" }, "CLBLM_R.CLBLM_IMUX38->CLBLM_M_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX38" }, "CLBLM_R.CLBLM_IMUX39->CLBLM_L_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX39" }, "CLBLM_R.CLBLM_IMUX4->CLBLM_M_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX4" }, "CLBLM_R.CLBLM_IMUX40->CLBLM_M_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX40" }, "CLBLM_R.CLBLM_IMUX41->CLBLM_L_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX41" }, "CLBLM_R.CLBLM_IMUX42->CLBLM_L_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX42" }, "CLBLM_R.CLBLM_IMUX43->CLBLM_M_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX43" }, "CLBLM_R.CLBLM_IMUX44->CLBLM_M_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX44" }, "CLBLM_R.CLBLM_IMUX45->CLBLM_M_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX45" }, "CLBLM_R.CLBLM_IMUX46->CLBLM_L_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX46" }, "CLBLM_R.CLBLM_IMUX47->CLBLM_M_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX47" }, "CLBLM_R.CLBLM_IMUX5->CLBLM_L_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX5" }, "CLBLM_R.CLBLM_IMUX6->CLBLM_L_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX6" }, "CLBLM_R.CLBLM_IMUX7->CLBLM_M_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX7" }, "CLBLM_R.CLBLM_IMUX8->CLBLM_M_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX8" }, 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"delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_A" }, "CLBLM_R.CLBLM_L_A1->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A1" }, "CLBLM_R.CLBLM_L_A2->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A2" }, "CLBLM_R.CLBLM_L_A3->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A3" }, "CLBLM_R.CLBLM_L_A4->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A4" }, "CLBLM_R.CLBLM_L_A5->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A5" }, "CLBLM_R.CLBLM_L_A6->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A6" }, "CLBLM_R.CLBLM_L_AMUX->CLBLM_LOGIC_OUTS16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_AMUX" }, "CLBLM_R.CLBLM_L_AQ->CLBLM_LOGIC_OUTS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_AQ" }, "CLBLM_R.CLBLM_L_B->>CLBLM_L_BMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.073", + "0.091", + "0.168", + "0.208" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_BMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.073", + "0.091", + "0.168", + "0.208" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B" }, "CLBLM_R.CLBLM_L_B->CLBLM_LOGIC_OUTS9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_B" }, 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"dst_wire": "CLBLM_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B3" }, "CLBLM_R.CLBLM_L_B4->>CLBLM_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B4" }, "CLBLM_R.CLBLM_L_B5->>CLBLM_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B5" }, "CLBLM_R.CLBLM_L_B6->>CLBLM_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B6" }, "CLBLM_R.CLBLM_L_BMUX->CLBLM_LOGIC_OUTS17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_BMUX" }, "CLBLM_R.CLBLM_L_BQ->CLBLM_LOGIC_OUTS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_BQ" }, "CLBLM_R.CLBLM_L_C->>CLBLM_L_CMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.069", + "0.086", + "0.166", + "0.205" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_CMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.069", + "0.086", + "0.166", + "0.205" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C" }, "CLBLM_R.CLBLM_L_C->CLBLM_LOGIC_OUTS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_C" }, "CLBLM_R.CLBLM_L_C1->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C1" }, "CLBLM_R.CLBLM_L_C2->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C2" }, "CLBLM_R.CLBLM_L_C3->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C3" }, "CLBLM_R.CLBLM_L_C4->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C4" }, "CLBLM_R.CLBLM_L_C5->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C5" }, "CLBLM_R.CLBLM_L_C6->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C6" }, "CLBLM_R.CLBLM_L_CMUX->CLBLM_LOGIC_OUTS18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_CMUX" }, "CLBLM_R.CLBLM_L_COUT->>CLBLM_L_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.131", + "0.246", + "0.305" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_DMUX", "is_directional": "1", + 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"is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C2" }, "CLBLM_R.CLBLM_M_C3->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C3" }, "CLBLM_R.CLBLM_M_C4->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C4" }, "CLBLM_R.CLBLM_M_C5->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C5" }, "CLBLM_R.CLBLM_M_C6->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C6" }, "CLBLM_R.CLBLM_M_CMUX->CLBLM_LOGIC_OUTS22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_CMUX" }, "CLBLM_R.CLBLM_M_COUT->>CLBLM_M_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.130", + "0.242", + "0.300" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.104", + "0.130", + "0.242", + "0.300" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_COUT" }, "CLBLM_R.CLBLM_M_COUT->CLBLM_M_COUT_N": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_COUT_N", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_COUT" }, "CLBLM_R.CLBLM_M_CQ->CLBLM_LOGIC_OUTS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_CQ" }, "CLBLM_R.CLBLM_M_D->>CLBLM_M_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.077", + "0.095", + "0.173", + "0.214" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.077", + "0.095", + "0.173", + "0.214" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D" }, "CLBLM_R.CLBLM_M_D->CLBLM_LOGIC_OUTS15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_D" }, "CLBLM_R.CLBLM_M_D1->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D1" }, "CLBLM_R.CLBLM_M_D2->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D2" }, "CLBLM_R.CLBLM_M_D3->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D3" }, "CLBLM_R.CLBLM_M_D4->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D4" }, "CLBLM_R.CLBLM_M_D5->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D5" }, "CLBLM_R.CLBLM_M_D6->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.100", + "0.124" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D6" }, "CLBLM_R.CLBLM_M_DMUX->CLBLM_LOGIC_OUTS23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_DMUX" }, "CLBLM_R.CLBLM_M_DQ->CLBLM_LOGIC_OUTS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_DQ" } }, @@ -1063,56 +3304,506 @@ "name": "X0Y0", "prefix": "SLICE", "site_pins": { - "A": "CLBLM_M_A", - "A1": "CLBLM_M_A1", - "A2": "CLBLM_M_A2", - "A3": "CLBLM_M_A3", - "A4": "CLBLM_M_A4", - "A5": "CLBLM_M_A5", - "A6": "CLBLM_M_A6", - "AI": "CLBLM_M_AI", - "AMUX": "CLBLM_M_AMUX", - "AQ": "CLBLM_M_AQ", - "AX": "CLBLM_M_AX", - "B": "CLBLM_M_B", - "B1": "CLBLM_M_B1", - "B2": "CLBLM_M_B2", - "B3": "CLBLM_M_B3", - "B4": "CLBLM_M_B4", - "B5": "CLBLM_M_B5", - "B6": "CLBLM_M_B6", - "BI": "CLBLM_M_BI", - "BMUX": "CLBLM_M_BMUX", - "BQ": "CLBLM_M_BQ", - "BX": "CLBLM_M_BX", - "C": "CLBLM_M_C", - "C1": "CLBLM_M_C1", - "C2": "CLBLM_M_C2", - "C3": "CLBLM_M_C3", - "C4": "CLBLM_M_C4", - "C5": "CLBLM_M_C5", - "C6": "CLBLM_M_C6", - "CE": "CLBLM_M_CE", - "CI": "CLBLM_M_CI", - "CIN": "CLBLM_M_CIN", - "CLK": "CLBLM_M_CLK", - "CMUX": "CLBLM_M_CMUX", - "COUT": "CLBLM_M_COUT", - "CQ": "CLBLM_M_CQ", - "CX": "CLBLM_M_CX", - "D": "CLBLM_M_D", - "D1": "CLBLM_M_D1", - "D2": "CLBLM_M_D2", - "D3": "CLBLM_M_D3", - "D4": "CLBLM_M_D4", - "D5": "CLBLM_M_D5", - "D6": "CLBLM_M_D6", - "DI": "CLBLM_M_DI", - "DMUX": "CLBLM_M_DMUX", - "DQ": "CLBLM_M_DQ", - "DX": "CLBLM_M_DX", - "SR": "CLBLM_M_SR", - "WE": "CLBLM_M_WE" + "A": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1463.6875", + "wire": "CLBLM_M_A" + }, + "A1": { + "cap": "0.000", + "delay": [ + "0.180", + "0.225", + "0.428", + "0.531" + ], + "wire": "CLBLM_M_A1" + }, + "A2": { + "cap": "0.000", + "delay": [ + "0.174", + "0.216", + "0.413", + "0.512" + ], + "wire": "CLBLM_M_A2" + }, + "A3": { + "cap": "0.000", + "delay": [ + "0.114", + "0.141", + "0.300", + "0.372" + ], + "wire": "CLBLM_M_A3" + }, + "A4": { + "cap": "0.000", + "delay": [ + "0.091", + "0.113", + "0.244", + "0.303" + ], + "wire": "CLBLM_M_A4" + }, + "A5": { + "cap": "0.000", + "delay": [ + "0.038", + "0.048", + "0.102", + "0.126" + ], + "wire": "CLBLM_M_A5" + }, + "A6": { + "cap": "0.000", + "delay": [ + "0.007", + "0.008", + "0.013", + "0.016" + ], + "wire": "CLBLM_M_A6" + }, + "AI": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_AI" + }, + "AMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1833.3335625", + "wire": "CLBLM_M_AMUX" + }, + "AQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_M_AQ" + }, + "AX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_AX" + }, + "B": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1408.0", + "wire": "CLBLM_M_B" + }, + "B1": { + "cap": "0.000", + "delay": [ + "0.175", + "0.218", + "0.420", + "0.521" + ], + "wire": "CLBLM_M_B1" + }, + "B2": { + "cap": "0.000", + "delay": [ + "0.172", + "0.214", + "0.406", + "0.504" + ], + "wire": "CLBLM_M_B2" + }, + "B3": { + "cap": "0.000", + "delay": [ + "0.114", + "0.141", + "0.298", + "0.370" + ], + "wire": "CLBLM_M_B3" + }, + "B4": { + "cap": "0.000", + "delay": [ + "0.090", + "0.112", + "0.242", + "0.300" + ], + "wire": "CLBLM_M_B4" + }, + "B5": { + "cap": "0.000", + "delay": [ + "0.042", + "0.052", + "0.111", + "0.137" + ], + "wire": "CLBLM_M_B5" + }, + "B6": { + "cap": "0.000", + "delay": [ + "0.005", + "0.006", + "0.011", + "0.013" + ], + "wire": "CLBLM_M_B6" + }, + "BI": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_BI" + }, + "BMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1898.8096875", + "wire": "CLBLM_M_BMUX" + }, + "BQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_M_BQ" + }, + "BX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_BX" + }, + "C": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1401.125", + "wire": "CLBLM_M_C" + }, + "C1": { + "cap": "0.000", + "delay": [ + "0.176", + "0.219", + "0.420", + "0.521" + ], + "wire": "CLBLM_M_C1" + }, + "C2": { + "cap": "0.000", + "delay": [ + "0.172", + "0.214", + "0.408", + "0.506" + ], + "wire": "CLBLM_M_C2" + }, + "C3": { + "cap": "0.000", + "delay": [ + "0.113", + "0.140", + "0.297", + "0.368" + ], + "wire": "CLBLM_M_C3" + }, + "C4": { + "cap": "0.000", + "delay": [ + "0.089", + "0.111", + "0.242", + "0.300" + ], + "wire": "CLBLM_M_C4" + }, + "C5": { + "cap": "0.000", + "delay": [ + "0.040", + "0.050", + "0.107", + "0.133" + ], + "wire": "CLBLM_M_C5" + }, + "C6": { + "cap": "0.000", + "delay": [ + "0.005", + "0.006", + "0.010", + "0.012" + ], + "wire": "CLBLM_M_C6" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_CE" + }, + "CI": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_CI" + }, + "CIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_CIN" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_CLK" + }, + "CMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1833.3335625", + "wire": "CLBLM_M_CMUX" + }, + "COUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "CLBLM_M_COUT" + }, + "CQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_M_CQ" + }, + "CX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_CX" + }, + "D": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1417.625", + "wire": "CLBLM_M_D" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.145", + "0.226", + "0.305", + "0.540" + ], + "wire": "CLBLM_M_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.141", + "0.219", + "0.293", + "0.520" + ], + "wire": "CLBLM_M_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.088", + "0.144", + "0.209", + "0.377" + ], + "wire": "CLBLM_M_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.073", + "0.118", + "0.176", + "0.317" + ], + "wire": "CLBLM_M_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.031", + "0.052", + "0.072", + "0.137" + ], + "wire": "CLBLM_M_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.003", + "0.007", + "0.010", + "0.022" + ], + "wire": "CLBLM_M_D6" + }, + "DI": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_DI" + }, + "DMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1859.523875", + "wire": "CLBLM_M_DMUX" + }, + "DQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_M_DQ" + }, + "DX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_DX" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_SR" + }, + "WE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_WE" + } }, "type": "SLICEM", "x_coord": 0, @@ -1122,51 +3813,456 @@ "name": "X1Y0", "prefix": "SLICE", "site_pins": { - "A": "CLBLM_L_A", - "A1": "CLBLM_L_A1", - "A2": "CLBLM_L_A2", - "A3": "CLBLM_L_A3", - "A4": "CLBLM_L_A4", - "A5": "CLBLM_L_A5", - "A6": "CLBLM_L_A6", - "AMUX": "CLBLM_L_AMUX", - "AQ": "CLBLM_L_AQ", - "AX": "CLBLM_L_AX", - "B": "CLBLM_L_B", - "B1": "CLBLM_L_B1", - "B2": "CLBLM_L_B2", - "B3": "CLBLM_L_B3", - "B4": "CLBLM_L_B4", - "B5": "CLBLM_L_B5", - "B6": "CLBLM_L_B6", - "BMUX": "CLBLM_L_BMUX", - "BQ": "CLBLM_L_BQ", - "BX": "CLBLM_L_BX", - "C": "CLBLM_L_C", - "C1": "CLBLM_L_C1", - "C2": "CLBLM_L_C2", - "C3": "CLBLM_L_C3", - "C4": "CLBLM_L_C4", - "C5": "CLBLM_L_C5", - "C6": "CLBLM_L_C6", - "CE": "CLBLM_L_CE", - "CIN": "CLBLM_L_CIN", - "CLK": "CLBLM_L_CLK", - "CMUX": "CLBLM_L_CMUX", - "COUT": "CLBLM_L_COUT", - "CQ": "CLBLM_L_CQ", - "CX": "CLBLM_L_CX", - "D": "CLBLM_L_D", - "D1": "CLBLM_L_D1", - "D2": "CLBLM_L_D2", - "D3": "CLBLM_L_D3", - "D4": "CLBLM_L_D4", - "D5": "CLBLM_L_D5", - "D6": "CLBLM_L_D6", - "DMUX": "CLBLM_L_DMUX", - "DQ": "CLBLM_L_DQ", - "DX": "CLBLM_L_DX", - "SR": "CLBLM_L_SR" + "A": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1326.1875", + "wire": "CLBLM_L_A" + }, + "A1": { + "cap": "0.000", + "delay": [ + "0.172", + "0.214", + "0.416", + "0.516" + ], + "wire": "CLBLM_L_A1" + }, + "A2": { + "cap": "0.000", + "delay": [ + "0.170", + "0.212", + "0.409", + "0.507" + ], + "wire": "CLBLM_L_A2" + }, + "A3": { + "cap": "0.000", + "delay": [ + "0.107", + "0.133", + "0.278", + "0.344" + ], + "wire": "CLBLM_L_A3" + }, + "A4": { + "cap": "0.000", + "delay": [ + "0.086", + "0.107", + "0.229", + "0.284" + ], + "wire": "CLBLM_L_A4" + }, + "A5": { + "cap": "0.000", + "delay": [ + "0.033", + "0.042", + "0.091", + "0.112" + ], + "wire": "CLBLM_L_A5" + }, + "A6": { + "cap": "0.000", + "delay": [ + "0.002", + "0.002", + "0.004", + "0.005" + ], + "wire": "CLBLM_L_A6" + }, + "AMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1852.976125", + "wire": "CLBLM_L_AMUX" + }, + "AQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_L_AQ" + }, + "AX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_AX" + }, + "B": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1404.5625", + "wire": "CLBLM_L_B" + }, + "B1": { + "cap": "0.000", + "delay": [ + "0.171", + "0.213", + "0.417", + "0.518" + ], + "wire": "CLBLM_L_B1" + }, + "B2": { + "cap": "0.000", + "delay": [ + "0.170", + "0.212", + "0.408", + "0.506" + ], + "wire": "CLBLM_L_B2" + }, + "B3": { + "cap": "0.000", + "delay": [ + "0.109", + "0.136", + "0.281", + "0.349" + ], + "wire": "CLBLM_L_B3" + }, + "B4": { + "cap": "0.000", + "delay": [ + "0.086", + "0.107", + "0.228", + "0.282" + ], + "wire": "CLBLM_L_B4" + }, + "B5": { + "cap": "0.000", + "delay": [ + "0.034", + "0.043", + "0.093", + "0.116" + ], + "wire": "CLBLM_L_B5" + }, + "B6": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.002", + "0.002" + ], + "wire": "CLBLM_L_B6" + }, + "BMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1869.3455", + "wire": "CLBLM_L_BMUX" + }, + "BQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_L_BQ" + }, + "BX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_BX" + }, + "C": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1453.375", + "wire": "CLBLM_L_C" + }, + "C1": { + "cap": "0.000", + "delay": [ + "0.173", + "0.215", + "0.417", + "0.517" + ], + "wire": "CLBLM_L_C1" + }, + "C2": { + "cap": "0.000", + "delay": [ + "0.171", + "0.213", + "0.409", + "0.507" + ], + "wire": "CLBLM_L_C2" + }, + "C3": { + "cap": "0.000", + "delay": [ + "0.110", + "0.137", + "0.283", + "0.351" + ], + "wire": "CLBLM_L_C3" + }, + "C4": { + "cap": "0.000", + "delay": [ + "0.087", + "0.108", + "0.227", + "0.281" + ], + "wire": "CLBLM_L_C4" + }, + "C5": { + "cap": "0.000", + "delay": [ + "0.033", + "0.042", + "0.092", + "0.114" + ], + "wire": "CLBLM_L_C5" + }, + "C6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_C6" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_CE" + }, + "CIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_CIN" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_CLK" + }, + "CMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1826.7858125", + "wire": "CLBLM_L_CMUX" + }, + "COUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "CLBLM_L_COUT" + }, + "CQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_L_CQ" + }, + "CX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_CX" + }, + "D": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1408.0", + "wire": "CLBLM_L_D" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.174", + "0.216", + "0.421", + "0.522" + ], + "wire": "CLBLM_L_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.171", + "0.213", + "0.410", + "0.509" + ], + "wire": "CLBLM_L_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.109", + "0.136", + "0.279", + "0.346" + ], + "wire": "CLBLM_L_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.088", + "0.109", + "0.229", + "0.284" + ], + "wire": "CLBLM_L_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.033", + "0.042", + "0.091", + "0.113" + ], + "wire": "CLBLM_L_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.003", + "0.003", + "0.004", + "0.005" + ], + "wire": "CLBLM_L_D6" + }, + "DMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1826.7858125", + "wire": "CLBLM_L_DMUX" + }, + "DQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1427.9375", + "wire": "CLBLM_L_DQ" + }, + "DX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_DX" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_SR" + } }, "type": "SLICEL", "x_coord": 1, @@ -1174,321 +4270,417 @@ } ], "tile_type": "CLBLM_R", - "wires": [ - "CLBLM_BYP0", - "CLBLM_BYP1", - "CLBLM_BYP2", - "CLBLM_BYP3", - "CLBLM_BYP4", - "CLBLM_BYP5", - "CLBLM_BYP6", - "CLBLM_BYP7", - "CLBLM_CLK0", - "CLBLM_CLK1", - "CLBLM_CTRL0", - "CLBLM_CTRL1", - "CLBLM_EE2A0", - "CLBLM_EE2A1", - "CLBLM_EE2A2", - "CLBLM_EE2A3", - "CLBLM_EE2BEG0", - "CLBLM_EE2BEG1", - "CLBLM_EE2BEG2", - "CLBLM_EE2BEG3", - "CLBLM_EE4A0", - "CLBLM_EE4A1", - "CLBLM_EE4A2", - "CLBLM_EE4A3", - "CLBLM_EE4B0", - "CLBLM_EE4B1", - "CLBLM_EE4B2", - "CLBLM_EE4B3", - "CLBLM_EE4BEG0", - "CLBLM_EE4BEG1", - "CLBLM_EE4BEG2", - "CLBLM_EE4BEG3", - "CLBLM_EE4C0", - "CLBLM_EE4C1", - "CLBLM_EE4C2", - "CLBLM_EE4C3", - "CLBLM_EL1BEG0", - "CLBLM_EL1BEG1", - "CLBLM_EL1BEG2", - "CLBLM_EL1BEG3", - "CLBLM_ER1BEG0", - "CLBLM_ER1BEG1", - "CLBLM_ER1BEG2", - "CLBLM_ER1BEG3", - "CLBLM_FAN0", - "CLBLM_FAN1", - "CLBLM_FAN2", - "CLBLM_FAN3", - "CLBLM_FAN4", - "CLBLM_FAN5", - "CLBLM_FAN6", - "CLBLM_FAN7", - "CLBLM_IMUX0", - "CLBLM_IMUX1", - "CLBLM_IMUX10", - "CLBLM_IMUX11", - "CLBLM_IMUX12", - "CLBLM_IMUX13", - "CLBLM_IMUX14", - "CLBLM_IMUX15", - "CLBLM_IMUX16", - "CLBLM_IMUX17", - "CLBLM_IMUX18", - "CLBLM_IMUX19", - "CLBLM_IMUX2", - "CLBLM_IMUX20", - "CLBLM_IMUX21", - "CLBLM_IMUX22", - "CLBLM_IMUX23", - "CLBLM_IMUX24", - "CLBLM_IMUX25", - "CLBLM_IMUX26", - "CLBLM_IMUX27", - "CLBLM_IMUX28", - "CLBLM_IMUX29", - "CLBLM_IMUX3", - "CLBLM_IMUX30", - "CLBLM_IMUX31", - "CLBLM_IMUX32", - "CLBLM_IMUX33", - "CLBLM_IMUX34", - "CLBLM_IMUX35", - "CLBLM_IMUX36", - "CLBLM_IMUX37", - "CLBLM_IMUX38", - "CLBLM_IMUX39", - "CLBLM_IMUX4", - "CLBLM_IMUX40", - "CLBLM_IMUX41", - "CLBLM_IMUX42", - "CLBLM_IMUX43", - "CLBLM_IMUX44", - "CLBLM_IMUX45", - "CLBLM_IMUX46", - "CLBLM_IMUX47", - "CLBLM_IMUX5", - "CLBLM_IMUX6", - "CLBLM_IMUX7", - "CLBLM_IMUX8", - "CLBLM_IMUX9", - "CLBLM_LH1", - "CLBLM_LH10", - "CLBLM_LH11", - "CLBLM_LH12", - "CLBLM_LH2", - "CLBLM_LH3", - "CLBLM_LH4", - "CLBLM_LH5", - "CLBLM_LH6", - "CLBLM_LH7", - "CLBLM_LH8", - "CLBLM_LH9", - "CLBLM_LOGIC_OUTS0", - "CLBLM_LOGIC_OUTS1", - "CLBLM_LOGIC_OUTS10", - "CLBLM_LOGIC_OUTS11", - "CLBLM_LOGIC_OUTS12", - "CLBLM_LOGIC_OUTS13", - "CLBLM_LOGIC_OUTS14", - "CLBLM_LOGIC_OUTS15", - "CLBLM_LOGIC_OUTS16", - "CLBLM_LOGIC_OUTS17", - "CLBLM_LOGIC_OUTS18", - "CLBLM_LOGIC_OUTS19", - "CLBLM_LOGIC_OUTS2", - "CLBLM_LOGIC_OUTS20", - "CLBLM_LOGIC_OUTS21", - "CLBLM_LOGIC_OUTS22", - "CLBLM_LOGIC_OUTS23", - "CLBLM_LOGIC_OUTS3", - "CLBLM_LOGIC_OUTS4", - "CLBLM_LOGIC_OUTS5", - "CLBLM_LOGIC_OUTS6", - "CLBLM_LOGIC_OUTS7", - "CLBLM_LOGIC_OUTS8", - "CLBLM_LOGIC_OUTS9", - "CLBLM_L_A", - "CLBLM_L_A1", - "CLBLM_L_A2", - "CLBLM_L_A3", - "CLBLM_L_A4", - "CLBLM_L_A5", - "CLBLM_L_A6", - "CLBLM_L_AMUX", - "CLBLM_L_AQ", - "CLBLM_L_AX", - "CLBLM_L_B", - "CLBLM_L_B1", - "CLBLM_L_B2", - "CLBLM_L_B3", - "CLBLM_L_B4", - "CLBLM_L_B5", - "CLBLM_L_B6", - "CLBLM_L_BMUX", - "CLBLM_L_BQ", - "CLBLM_L_BX", - "CLBLM_L_C", - "CLBLM_L_C1", - "CLBLM_L_C2", - "CLBLM_L_C3", - "CLBLM_L_C4", - "CLBLM_L_C5", - "CLBLM_L_C6", - "CLBLM_L_CE", - "CLBLM_L_CIN", - "CLBLM_L_CLK", - "CLBLM_L_CMUX", - "CLBLM_L_COUT", - "CLBLM_L_COUT_N", - "CLBLM_L_CQ", - "CLBLM_L_CX", - "CLBLM_L_D", - "CLBLM_L_D1", - "CLBLM_L_D2", - "CLBLM_L_D3", - "CLBLM_L_D4", - "CLBLM_L_D5", - "CLBLM_L_D6", - "CLBLM_L_DMUX", - "CLBLM_L_DQ", - "CLBLM_L_DX", - "CLBLM_L_SR", - "CLBLM_MONITOR_N", - "CLBLM_MONITOR_P", - "CLBLM_M_A", - "CLBLM_M_A1", - "CLBLM_M_A2", - "CLBLM_M_A3", - "CLBLM_M_A4", - "CLBLM_M_A5", - "CLBLM_M_A6", - "CLBLM_M_AI", - "CLBLM_M_AMUX", - "CLBLM_M_AQ", - "CLBLM_M_AX", - "CLBLM_M_B", - "CLBLM_M_B1", - "CLBLM_M_B2", - "CLBLM_M_B3", - "CLBLM_M_B4", - "CLBLM_M_B5", - "CLBLM_M_B6", - "CLBLM_M_BI", - "CLBLM_M_BMUX", - "CLBLM_M_BQ", - "CLBLM_M_BX", - "CLBLM_M_C", - "CLBLM_M_C1", - "CLBLM_M_C2", - "CLBLM_M_C3", - "CLBLM_M_C4", - "CLBLM_M_C5", - "CLBLM_M_C6", - "CLBLM_M_CE", - "CLBLM_M_CI", - "CLBLM_M_CIN", - "CLBLM_M_CLK", - "CLBLM_M_CMUX", - "CLBLM_M_COUT", - "CLBLM_M_COUT_N", - "CLBLM_M_CQ", - "CLBLM_M_CX", - "CLBLM_M_D", - "CLBLM_M_D1", - "CLBLM_M_D2", - "CLBLM_M_D3", - "CLBLM_M_D4", - "CLBLM_M_D5", - "CLBLM_M_D6", - "CLBLM_M_DI", - "CLBLM_M_DMUX", - "CLBLM_M_DQ", - "CLBLM_M_DX", - "CLBLM_M_SR", - "CLBLM_M_WE", - "CLBLM_NE2A0", - "CLBLM_NE2A1", - "CLBLM_NE2A2", - "CLBLM_NE2A3", - "CLBLM_NE4BEG0", - "CLBLM_NE4BEG1", - "CLBLM_NE4BEG2", - "CLBLM_NE4BEG3", - "CLBLM_NE4C0", - "CLBLM_NE4C1", - "CLBLM_NE4C2", - "CLBLM_NE4C3", - "CLBLM_NW2A0", - "CLBLM_NW2A1", - "CLBLM_NW2A2", - "CLBLM_NW2A3", - "CLBLM_NW4A0", - "CLBLM_NW4A1", - "CLBLM_NW4A2", - "CLBLM_NW4A3", - "CLBLM_NW4END0", - "CLBLM_NW4END1", - "CLBLM_NW4END2", - "CLBLM_NW4END3", - "CLBLM_SE2A0", - "CLBLM_SE2A1", - "CLBLM_SE2A2", - "CLBLM_SE2A3", - "CLBLM_SE4BEG0", - "CLBLM_SE4BEG1", - "CLBLM_SE4BEG2", - "CLBLM_SE4BEG3", - "CLBLM_SE4C0", - "CLBLM_SE4C1", - "CLBLM_SE4C2", - "CLBLM_SE4C3", - "CLBLM_SW2A0", - "CLBLM_SW2A1", - "CLBLM_SW2A2", - "CLBLM_SW2A3", - "CLBLM_SW4A0", - "CLBLM_SW4A1", - "CLBLM_SW4A2", - "CLBLM_SW4A3", - "CLBLM_SW4END0", - "CLBLM_SW4END1", - "CLBLM_SW4END2", - "CLBLM_SW4END3", - "CLBLM_WL1END0", - "CLBLM_WL1END1", - "CLBLM_WL1END2", - "CLBLM_WL1END3", - "CLBLM_WR1END0", - "CLBLM_WR1END1", - "CLBLM_WR1END2", - "CLBLM_WR1END3", - "CLBLM_WW2A0", - "CLBLM_WW2A1", - "CLBLM_WW2A2", - "CLBLM_WW2A3", - "CLBLM_WW2END0", - "CLBLM_WW2END1", - "CLBLM_WW2END2", - "CLBLM_WW2END3", - "CLBLM_WW4A0", - "CLBLM_WW4A1", - "CLBLM_WW4A2", - "CLBLM_WW4A3", - "CLBLM_WW4B0", - "CLBLM_WW4B1", - "CLBLM_WW4B2", - "CLBLM_WW4B3", - "CLBLM_WW4C0", - "CLBLM_WW4C1", - "CLBLM_WW4C2", - "CLBLM_WW4C3", - "CLBLM_WW4END0", - "CLBLM_WW4END1", - "CLBLM_WW4END2", - "CLBLM_WW4END3" - ] + "wires": { + "CLBLM_BYP0": null, + "CLBLM_BYP1": null, + "CLBLM_BYP2": null, + "CLBLM_BYP3": null, + "CLBLM_BYP4": null, + "CLBLM_BYP5": null, + "CLBLM_BYP6": null, + "CLBLM_BYP7": null, + "CLBLM_CLK0": null, + "CLBLM_CLK1": null, + "CLBLM_CTRL0": null, + "CLBLM_CTRL1": null, + "CLBLM_EE2A0": null, + "CLBLM_EE2A1": null, + "CLBLM_EE2A2": null, + "CLBLM_EE2A3": null, + "CLBLM_EE2BEG0": null, + "CLBLM_EE2BEG1": null, + "CLBLM_EE2BEG2": null, + "CLBLM_EE2BEG3": null, + "CLBLM_EE4A0": null, + "CLBLM_EE4A1": null, + "CLBLM_EE4A2": null, + "CLBLM_EE4A3": null, + "CLBLM_EE4B0": null, + "CLBLM_EE4B1": null, + "CLBLM_EE4B2": null, + "CLBLM_EE4B3": null, + "CLBLM_EE4BEG0": null, + "CLBLM_EE4BEG1": null, + "CLBLM_EE4BEG2": null, + "CLBLM_EE4BEG3": null, + "CLBLM_EE4C0": null, + "CLBLM_EE4C1": null, + "CLBLM_EE4C2": null, + "CLBLM_EE4C3": null, + "CLBLM_EL1BEG0": { + "cap": "4.690", + "res": "52.151" + }, + "CLBLM_EL1BEG1": { + "cap": "4.690", + "res": "52.151" + }, + "CLBLM_EL1BEG2": { + "cap": "4.690", + "res": "52.151" + }, + "CLBLM_EL1BEG3": { + "cap": "4.690", + "res": "52.151" + }, + "CLBLM_ER1BEG0": { + "cap": "5.564", + "res": "90.496" + }, + "CLBLM_ER1BEG1": { + "cap": "5.564", + "res": "90.496" + }, + "CLBLM_ER1BEG2": { + "cap": "5.564", + "res": "90.496" + }, + "CLBLM_ER1BEG3": { + "cap": "5.564", + "res": "90.496" + }, + "CLBLM_FAN0": null, + "CLBLM_FAN1": null, + "CLBLM_FAN2": null, + "CLBLM_FAN3": null, + "CLBLM_FAN4": null, + "CLBLM_FAN5": null, + "CLBLM_FAN6": null, + "CLBLM_FAN7": null, + "CLBLM_IMUX0": null, + "CLBLM_IMUX1": null, + "CLBLM_IMUX10": null, + "CLBLM_IMUX11": null, + "CLBLM_IMUX12": null, + "CLBLM_IMUX13": null, + "CLBLM_IMUX14": null, + "CLBLM_IMUX15": null, + "CLBLM_IMUX16": null, + "CLBLM_IMUX17": null, + "CLBLM_IMUX18": null, + "CLBLM_IMUX19": null, + "CLBLM_IMUX2": null, + "CLBLM_IMUX20": null, + "CLBLM_IMUX21": null, + "CLBLM_IMUX22": null, + "CLBLM_IMUX23": null, + "CLBLM_IMUX24": null, + "CLBLM_IMUX25": null, + "CLBLM_IMUX26": null, + "CLBLM_IMUX27": null, + "CLBLM_IMUX28": null, + "CLBLM_IMUX29": null, + "CLBLM_IMUX3": null, + "CLBLM_IMUX30": null, + "CLBLM_IMUX31": null, + "CLBLM_IMUX32": null, + "CLBLM_IMUX33": null, + "CLBLM_IMUX34": null, + "CLBLM_IMUX35": null, + "CLBLM_IMUX36": null, + "CLBLM_IMUX37": null, + "CLBLM_IMUX38": null, + "CLBLM_IMUX39": null, + "CLBLM_IMUX4": null, + "CLBLM_IMUX40": null, + "CLBLM_IMUX41": null, + "CLBLM_IMUX42": null, + "CLBLM_IMUX43": null, + "CLBLM_IMUX44": null, + "CLBLM_IMUX45": null, + "CLBLM_IMUX46": null, + "CLBLM_IMUX47": null, + "CLBLM_IMUX5": null, + "CLBLM_IMUX6": null, + "CLBLM_IMUX7": null, + "CLBLM_IMUX8": null, + "CLBLM_IMUX9": null, + "CLBLM_LH1": null, + "CLBLM_LH10": null, + "CLBLM_LH11": null, + "CLBLM_LH12": null, + "CLBLM_LH2": null, + "CLBLM_LH3": null, + "CLBLM_LH4": null, + "CLBLM_LH5": null, + "CLBLM_LH6": null, + "CLBLM_LH7": null, + "CLBLM_LH8": null, + "CLBLM_LH9": null, + "CLBLM_LOGIC_OUTS0": null, + "CLBLM_LOGIC_OUTS1": null, + "CLBLM_LOGIC_OUTS10": null, + "CLBLM_LOGIC_OUTS11": null, + "CLBLM_LOGIC_OUTS12": null, + "CLBLM_LOGIC_OUTS13": null, + "CLBLM_LOGIC_OUTS14": null, + "CLBLM_LOGIC_OUTS15": null, + "CLBLM_LOGIC_OUTS16": null, + "CLBLM_LOGIC_OUTS17": null, + "CLBLM_LOGIC_OUTS18": null, + "CLBLM_LOGIC_OUTS19": null, + "CLBLM_LOGIC_OUTS2": null, + "CLBLM_LOGIC_OUTS20": null, + "CLBLM_LOGIC_OUTS21": null, + "CLBLM_LOGIC_OUTS22": null, + "CLBLM_LOGIC_OUTS23": null, + "CLBLM_LOGIC_OUTS3": null, + "CLBLM_LOGIC_OUTS4": null, + "CLBLM_LOGIC_OUTS5": null, + "CLBLM_LOGIC_OUTS6": null, + "CLBLM_LOGIC_OUTS7": null, + "CLBLM_LOGIC_OUTS8": null, + "CLBLM_LOGIC_OUTS9": null, + "CLBLM_L_A": null, + "CLBLM_L_A1": null, + "CLBLM_L_A2": null, + "CLBLM_L_A3": null, + "CLBLM_L_A4": null, + "CLBLM_L_A5": null, + "CLBLM_L_A6": null, + "CLBLM_L_AMUX": null, + "CLBLM_L_AQ": null, + "CLBLM_L_AX": null, + "CLBLM_L_B": null, + "CLBLM_L_B1": null, + "CLBLM_L_B2": null, + "CLBLM_L_B3": null, + "CLBLM_L_B4": null, + "CLBLM_L_B5": null, + "CLBLM_L_B6": null, + "CLBLM_L_BMUX": null, + "CLBLM_L_BQ": null, + "CLBLM_L_BX": null, + "CLBLM_L_C": null, + "CLBLM_L_C1": null, + "CLBLM_L_C2": null, + "CLBLM_L_C3": null, + "CLBLM_L_C4": null, + "CLBLM_L_C5": null, + "CLBLM_L_C6": null, + "CLBLM_L_CE": null, + "CLBLM_L_CIN": null, + "CLBLM_L_CLK": null, + "CLBLM_L_CMUX": null, + "CLBLM_L_COUT": null, + "CLBLM_L_COUT_N": null, + "CLBLM_L_CQ": null, + "CLBLM_L_CX": null, + "CLBLM_L_D": null, + "CLBLM_L_D1": null, + "CLBLM_L_D2": null, + "CLBLM_L_D3": null, + "CLBLM_L_D4": null, + "CLBLM_L_D5": null, + "CLBLM_L_D6": null, + "CLBLM_L_DMUX": null, + "CLBLM_L_DQ": null, + "CLBLM_L_DX": null, + "CLBLM_L_SR": null, + "CLBLM_MONITOR_N": null, + "CLBLM_MONITOR_P": null, + "CLBLM_M_A": null, + "CLBLM_M_A1": null, + "CLBLM_M_A2": null, + "CLBLM_M_A3": null, + "CLBLM_M_A4": null, + "CLBLM_M_A5": null, + "CLBLM_M_A6": null, + "CLBLM_M_AI": null, + "CLBLM_M_AMUX": null, + "CLBLM_M_AQ": null, + "CLBLM_M_AX": null, + "CLBLM_M_B": null, + "CLBLM_M_B1": null, + "CLBLM_M_B2": null, + "CLBLM_M_B3": null, + "CLBLM_M_B4": null, + "CLBLM_M_B5": null, + "CLBLM_M_B6": null, + "CLBLM_M_BI": null, + "CLBLM_M_BMUX": null, + "CLBLM_M_BQ": null, + "CLBLM_M_BX": null, + "CLBLM_M_C": null, + "CLBLM_M_C1": null, + "CLBLM_M_C2": null, + "CLBLM_M_C3": null, + "CLBLM_M_C4": null, + "CLBLM_M_C5": null, + "CLBLM_M_C6": null, + "CLBLM_M_CE": null, + "CLBLM_M_CI": null, + "CLBLM_M_CIN": null, + "CLBLM_M_CLK": null, + "CLBLM_M_CMUX": null, + "CLBLM_M_COUT": null, + "CLBLM_M_COUT_N": null, + "CLBLM_M_CQ": null, + "CLBLM_M_CX": null, + "CLBLM_M_D": null, + "CLBLM_M_D1": null, + "CLBLM_M_D2": null, + "CLBLM_M_D3": null, + "CLBLM_M_D4": null, + "CLBLM_M_D5": null, + "CLBLM_M_D6": null, + "CLBLM_M_DI": null, + "CLBLM_M_DMUX": null, + "CLBLM_M_DQ": null, + "CLBLM_M_DX": null, + "CLBLM_M_SR": null, + "CLBLM_M_WE": null, + "CLBLM_NE2A0": { + "cap": "5.469", + "res": "100.092" + }, + "CLBLM_NE2A1": { + "cap": "5.469", + "res": "100.092" + }, + "CLBLM_NE2A2": { + "cap": "5.469", + "res": "100.092" + }, + "CLBLM_NE2A3": { + "cap": "5.469", + "res": "100.092" + }, + "CLBLM_NE4BEG0": null, + "CLBLM_NE4BEG1": null, + "CLBLM_NE4BEG2": null, + "CLBLM_NE4BEG3": null, + "CLBLM_NE4C0": null, + "CLBLM_NE4C1": null, + "CLBLM_NE4C2": null, + "CLBLM_NE4C3": null, + "CLBLM_NW2A0": { + "cap": "5.884", + "res": "91.532" + }, + "CLBLM_NW2A1": { + "cap": "5.884", + "res": "91.532" + }, + "CLBLM_NW2A2": { + "cap": "5.884", + "res": "91.532" + }, + "CLBLM_NW2A3": { + "cap": "5.884", + "res": "91.532" + }, + "CLBLM_NW4A0": null, + "CLBLM_NW4A1": null, + "CLBLM_NW4A2": null, + "CLBLM_NW4A3": null, + "CLBLM_NW4END0": null, + "CLBLM_NW4END1": null, + "CLBLM_NW4END2": null, + "CLBLM_NW4END3": null, + "CLBLM_SE2A0": { + "cap": "5.065", + "res": "90.332" + }, + "CLBLM_SE2A1": { + "cap": "5.065", + "res": "90.332" + }, + "CLBLM_SE2A2": { + "cap": "5.065", + "res": "90.332" + }, + "CLBLM_SE2A3": { + "cap": "5.065", + "res": "90.332" + }, + "CLBLM_SE4BEG0": null, + "CLBLM_SE4BEG1": null, + "CLBLM_SE4BEG2": null, + "CLBLM_SE4BEG3": null, + "CLBLM_SE4C0": null, + "CLBLM_SE4C1": null, + "CLBLM_SE4C2": null, + "CLBLM_SE4C3": null, + "CLBLM_SW2A0": { + "cap": "5.896", + "res": "90.208" + }, + "CLBLM_SW2A1": { + "cap": "5.896", + "res": "90.208" + }, + "CLBLM_SW2A2": { + "cap": "5.896", + "res": "90.208" + }, + "CLBLM_SW2A3": { + "cap": "5.896", + "res": "90.208" + }, + "CLBLM_SW4A0": null, + "CLBLM_SW4A1": null, + "CLBLM_SW4A2": null, + "CLBLM_SW4A3": null, + "CLBLM_SW4END0": null, + "CLBLM_SW4END1": null, + "CLBLM_SW4END2": null, + "CLBLM_SW4END3": null, + "CLBLM_WL1END0": { + "cap": "6.105", + "res": "58.596" + }, + "CLBLM_WL1END1": { + "cap": "6.105", + "res": "58.596" + }, + "CLBLM_WL1END2": { + "cap": "6.105", + "res": "58.596" + }, + "CLBLM_WL1END3": { + "cap": "6.105", + "res": "58.596" + }, + "CLBLM_WR1END0": { + "cap": "5.801", + "res": "94.510" + }, + "CLBLM_WR1END1": { + "cap": "5.801", + "res": "94.510" + }, + "CLBLM_WR1END2": { + "cap": "5.801", + "res": "94.510" + }, + "CLBLM_WR1END3": { + "cap": "5.801", + "res": "94.510" + }, + "CLBLM_WW2A0": null, + "CLBLM_WW2A1": null, + "CLBLM_WW2A2": null, + "CLBLM_WW2A3": null, + "CLBLM_WW2END0": null, + "CLBLM_WW2END1": null, + "CLBLM_WW2END2": null, + "CLBLM_WW2END3": null, + "CLBLM_WW4A0": null, + "CLBLM_WW4A1": null, + "CLBLM_WW4A2": null, + "CLBLM_WW4A3": null, + "CLBLM_WW4B0": null, + "CLBLM_WW4B1": null, + "CLBLM_WW4B2": null, + "CLBLM_WW4B3": null, + "CLBLM_WW4C0": null, + "CLBLM_WW4C1": null, + "CLBLM_WW4C2": null, + "CLBLM_WW4C3": null, + "CLBLM_WW4END0": null, + "CLBLM_WW4END1": null, + "CLBLM_WW4END2": null, + "CLBLM_WW4END3": null + } } diff --git a/zynq7/tile_type_CLK_BUFG_BOT_R.json b/zynq7/tile_type_CLK_BUFG_BOT_R.json index 164a90a..a446395 100644 --- a/zynq7/tile_type_CLK_BUFG_BOT_R.json +++ b/zynq7/tile_type_CLK_BUFG_BOT_R.json @@ -2,2130 +2,8514 @@ "pips": { "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED1->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED1" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED10->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED10" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED11->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED11" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED12->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED12" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED13->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED13" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED14->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED14" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED15->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED15" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED16->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED16" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED17->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED17" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED18->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED18" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED19->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED19" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED2->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED2" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED20->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED20" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED21->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED21" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED22->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED22" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED23->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED23" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED24->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED24" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED25->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED25" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED26->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED26" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED27->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED27" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED28->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED28" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED29->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED29" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED3->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED3" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED30->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED30" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED31->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED31" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED4->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED4" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED5->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED5" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED6->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED6" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED7->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED7" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED8->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED8" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED9->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED9" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0->>CLK_BUFG_BUFGCTRL0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL0_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_CK_GCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL0_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_R_FBG_OUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL0_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0->>CLK_BUFG_BUFGCTRL10_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL10_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_CK_GCLK10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL10_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_R_FBG_OUT10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL10_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0->>CLK_BUFG_BUFGCTRL11_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL11_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_CK_GCLK11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL11_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_R_FBG_OUT11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL11_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0->>CLK_BUFG_BUFGCTRL12_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL12_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_CK_GCLK12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL12_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_R_FBG_OUT12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL12_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0->>CLK_BUFG_BUFGCTRL13_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL13_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_CK_GCLK13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL13_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_R_FBG_OUT13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL13_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0->>CLK_BUFG_BUFGCTRL14_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL14_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_CK_GCLK14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL14_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_R_FBG_OUT14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL14_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0->>CLK_BUFG_BUFGCTRL15_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL15_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_CK_GCLK15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL15_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_R_FBG_OUT15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL15_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0->>CLK_BUFG_BUFGCTRL1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL1_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_CK_GCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL1_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_R_FBG_OUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL1_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0->>CLK_BUFG_BUFGCTRL2_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL2_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_CK_GCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL2_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_R_FBG_OUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL2_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0->>CLK_BUFG_BUFGCTRL3_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL3_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_CK_GCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL3_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_R_FBG_OUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL3_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0->>CLK_BUFG_BUFGCTRL4_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL4_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_CK_GCLK4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL4_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_R_FBG_OUT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL4_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0->>CLK_BUFG_BUFGCTRL5_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL5_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_CK_GCLK5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL5_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_R_FBG_OUT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL5_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0->>CLK_BUFG_BUFGCTRL6_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL6_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_CK_GCLK6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL6_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_R_FBG_OUT6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL6_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0->>CLK_BUFG_BUFGCTRL7_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL7_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_CK_GCLK7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL7_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_R_FBG_OUT7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL7_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0->>CLK_BUFG_BUFGCTRL8_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL8_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_CK_GCLK8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL8_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_R_FBG_OUT8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL8_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0->>CLK_BUFG_BUFGCTRL9_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL9_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_CK_GCLK9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL9_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_R_FBG_OUT9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL9_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_0->>CLK_BUFG_R_BUFGCTRL0_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_1->>CLK_BUFG_R_BUFGCTRL4_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_2->>CLK_BUFG_R_BUFGCTRL8_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_3->>CLK_BUFG_R_BUFGCTRL12_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_0->>CLK_BUFG_R_BUFGCTRL0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_1->>CLK_BUFG_R_BUFGCTRL4_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_2->>CLK_BUFG_R_BUFGCTRL8_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_3->>CLK_BUFG_R_BUFGCTRL12_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_0->>CLK_BUFG_R_BUFGCTRL1_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_1->>CLK_BUFG_R_BUFGCTRL5_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_2->>CLK_BUFG_R_BUFGCTRL9_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_3->>CLK_BUFG_R_BUFGCTRL13_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_0->>CLK_BUFG_R_BUFGCTRL2_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_1->>CLK_BUFG_R_BUFGCTRL6_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_2->>CLK_BUFG_R_BUFGCTRL10_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_3->>CLK_BUFG_R_BUFGCTRL14_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_0->>CLK_BUFG_R_BUFGCTRL3_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_1->>CLK_BUFG_R_BUFGCTRL7_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_2->>CLK_BUFG_R_BUFGCTRL11_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_3->>CLK_BUFG_R_BUFGCTRL15_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_0->>CLK_BUFG_R_BUFGCTRL1_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_1->>CLK_BUFG_R_BUFGCTRL5_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_2->>CLK_BUFG_R_BUFGCTRL9_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_3->>CLK_BUFG_R_BUFGCTRL13_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_0->>CLK_BUFG_R_BUFGCTRL0_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_1->>CLK_BUFG_R_BUFGCTRL4_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_2->>CLK_BUFG_R_BUFGCTRL8_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_3->>CLK_BUFG_R_BUFGCTRL12_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_0->>CLK_BUFG_R_BUFGCTRL1_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_1->>CLK_BUFG_R_BUFGCTRL5_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_2->>CLK_BUFG_R_BUFGCTRL9_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_3->>CLK_BUFG_R_BUFGCTRL13_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_0->>CLK_BUFG_R_BUFGCTRL2_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_1->>CLK_BUFG_R_BUFGCTRL6_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_2->>CLK_BUFG_R_BUFGCTRL10_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_3->>CLK_BUFG_R_BUFGCTRL14_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_0->>CLK_BUFG_R_BUFGCTRL3_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_1->>CLK_BUFG_R_BUFGCTRL7_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_2->>CLK_BUFG_R_BUFGCTRL11_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_3->>CLK_BUFG_R_BUFGCTRL15_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_0->>CLK_BUFG_R_BUFGCTRL2_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_1->>CLK_BUFG_R_BUFGCTRL6_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_2->>CLK_BUFG_R_BUFGCTRL10_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_3->>CLK_BUFG_R_BUFGCTRL14_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 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+ "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_2->>CLK_BUFG_R_BUFGCTRL11_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_3->>CLK_BUFG_R_BUFGCTRL15_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_0->>CLK_BUFG_R_BUFGCTRL0_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_1->>CLK_BUFG_R_BUFGCTRL4_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_1" }, 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"0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_3->>CLK_BUFG_R_BUFGCTRL13_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_0->>CLK_BUFG_R_BUFGCTRL2_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_1->>CLK_BUFG_R_BUFGCTRL6_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_2->>CLK_BUFG_R_BUFGCTRL10_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_3->>CLK_BUFG_R_BUFGCTRL14_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_0->>CLK_BUFG_R_BUFGCTRL3_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_1->>CLK_BUFG_R_BUFGCTRL7_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_2->>CLK_BUFG_R_BUFGCTRL11_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_3->>CLK_BUFG_R_BUFGCTRL15_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" } }, @@ -2134,15 +8518,96 @@ "name": "X0Y0", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL0_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL0_CE1", - "I0": "CLK_BUFG_BUFGCTRL0_I0", - "I1": "CLK_BUFG_BUFGCTRL0_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL0_O", - "S0": "CLK_BUFG_R_BUFGCTRL0_S0", - "S1": "CLK_BUFG_R_BUFGCTRL0_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL0_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2152,15 +8617,96 @@ "name": "X0Y1", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL1_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL1_CE1", - "I0": "CLK_BUFG_BUFGCTRL1_I0", - "I1": "CLK_BUFG_BUFGCTRL1_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL1_O", - "S0": "CLK_BUFG_R_BUFGCTRL1_S0", - "S1": "CLK_BUFG_R_BUFGCTRL1_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL1_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2170,15 +8716,96 @@ "name": "X0Y2", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL2_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL2_CE1", - "I0": "CLK_BUFG_BUFGCTRL2_I0", - "I1": "CLK_BUFG_BUFGCTRL2_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL2_O", - "S0": "CLK_BUFG_R_BUFGCTRL2_S0", - "S1": "CLK_BUFG_R_BUFGCTRL2_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL2_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2188,15 +8815,96 @@ "name": "X0Y3", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL3_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL3_CE1", - "I0": "CLK_BUFG_BUFGCTRL3_I0", - "I1": "CLK_BUFG_BUFGCTRL3_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL3_O", - "S0": "CLK_BUFG_R_BUFGCTRL3_S0", - "S1": "CLK_BUFG_R_BUFGCTRL3_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL3_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2206,15 +8914,96 @@ "name": "X0Y4", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL4_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL4_CE1", - "I0": "CLK_BUFG_BUFGCTRL4_I0", - "I1": "CLK_BUFG_BUFGCTRL4_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL4_O", - "S0": "CLK_BUFG_R_BUFGCTRL4_S0", - "S1": "CLK_BUFG_R_BUFGCTRL4_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL4_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL4_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2224,15 +9013,96 @@ "name": "X0Y5", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL5_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL5_CE1", - "I0": "CLK_BUFG_BUFGCTRL5_I0", - "I1": "CLK_BUFG_BUFGCTRL5_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL5_O", - "S0": "CLK_BUFG_R_BUFGCTRL5_S0", - "S1": "CLK_BUFG_R_BUFGCTRL5_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL5_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2242,15 +9112,96 @@ "name": "X0Y6", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL6_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL6_CE1", - "I0": "CLK_BUFG_BUFGCTRL6_I0", - "I1": "CLK_BUFG_BUFGCTRL6_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL6_O", - "S0": "CLK_BUFG_R_BUFGCTRL6_S0", - "S1": "CLK_BUFG_R_BUFGCTRL6_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL6_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL6_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL6_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2260,15 +9211,96 @@ "name": "X0Y7", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL7_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL7_CE1", - "I0": "CLK_BUFG_BUFGCTRL7_I0", - "I1": "CLK_BUFG_BUFGCTRL7_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL7_O", - "S0": "CLK_BUFG_R_BUFGCTRL7_S0", - "S1": "CLK_BUFG_R_BUFGCTRL7_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL7_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2278,15 +9310,96 @@ "name": "X0Y8", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL8_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL8_CE1", - "I0": "CLK_BUFG_BUFGCTRL8_I0", - "I1": "CLK_BUFG_BUFGCTRL8_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL8_O", - "S0": "CLK_BUFG_R_BUFGCTRL8_S0", - "S1": "CLK_BUFG_R_BUFGCTRL8_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL8_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2296,15 +9409,96 @@ "name": "X0Y9", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL9_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL9_CE1", - "I0": "CLK_BUFG_BUFGCTRL9_I0", - "I1": "CLK_BUFG_BUFGCTRL9_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL9_O", - "S0": "CLK_BUFG_R_BUFGCTRL9_S0", - "S1": "CLK_BUFG_R_BUFGCTRL9_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL9_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2314,15 +9508,96 @@ "name": "X0Y10", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL10_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL10_CE1", - "I0": "CLK_BUFG_BUFGCTRL10_I0", - "I1": "CLK_BUFG_BUFGCTRL10_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL10_O", - "S0": "CLK_BUFG_R_BUFGCTRL10_S0", - "S1": "CLK_BUFG_R_BUFGCTRL10_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL10_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL10_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2332,15 +9607,96 @@ "name": "X0Y11", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL11_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL11_CE1", - "I0": "CLK_BUFG_BUFGCTRL11_I0", - "I1": "CLK_BUFG_BUFGCTRL11_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL11_O", - "S0": "CLK_BUFG_R_BUFGCTRL11_S0", - "S1": "CLK_BUFG_R_BUFGCTRL11_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL11_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL11_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL11_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2350,15 +9706,96 @@ "name": "X0Y12", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL12_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL12_CE1", - "I0": "CLK_BUFG_BUFGCTRL12_I0", - "I1": "CLK_BUFG_BUFGCTRL12_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL12_O", - "S0": "CLK_BUFG_R_BUFGCTRL12_S0", - "S1": "CLK_BUFG_R_BUFGCTRL12_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL12_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL12_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2368,15 +9805,96 @@ "name": "X0Y13", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL13_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL13_CE1", - "I0": "CLK_BUFG_BUFGCTRL13_I0", - "I1": "CLK_BUFG_BUFGCTRL13_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL13_O", - "S0": "CLK_BUFG_R_BUFGCTRL13_S0", - "S1": "CLK_BUFG_R_BUFGCTRL13_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL13_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2386,15 +9904,96 @@ "name": "X0Y14", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL14_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL14_CE1", - "I0": "CLK_BUFG_BUFGCTRL14_I0", - "I1": "CLK_BUFG_BUFGCTRL14_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL14_O", - "S0": "CLK_BUFG_R_BUFGCTRL14_S0", - "S1": "CLK_BUFG_R_BUFGCTRL14_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL14_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2404,15 +10003,96 @@ "name": "X0Y15", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL15_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL15_CE1", - "I0": "CLK_BUFG_BUFGCTRL15_I0", - "I1": "CLK_BUFG_BUFGCTRL15_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL15_O", - "S0": "CLK_BUFG_R_BUFGCTRL15_S0", - "S1": "CLK_BUFG_R_BUFGCTRL15_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL15_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2420,1150 +10100,1750 @@ } ], "tile_type": "CLK_BUFG_BOT_R", - "wires": [ - "CLK_BUFG_BOT_R_CK_MUXED0", - "CLK_BUFG_BOT_R_CK_MUXED1", - "CLK_BUFG_BOT_R_CK_MUXED10", - "CLK_BUFG_BOT_R_CK_MUXED11", - "CLK_BUFG_BOT_R_CK_MUXED12", - "CLK_BUFG_BOT_R_CK_MUXED13", - "CLK_BUFG_BOT_R_CK_MUXED14", - "CLK_BUFG_BOT_R_CK_MUXED15", - "CLK_BUFG_BOT_R_CK_MUXED16", - "CLK_BUFG_BOT_R_CK_MUXED17", - "CLK_BUFG_BOT_R_CK_MUXED18", - "CLK_BUFG_BOT_R_CK_MUXED19", - "CLK_BUFG_BOT_R_CK_MUXED2", - "CLK_BUFG_BOT_R_CK_MUXED20", - "CLK_BUFG_BOT_R_CK_MUXED21", - "CLK_BUFG_BOT_R_CK_MUXED22", - "CLK_BUFG_BOT_R_CK_MUXED23", - "CLK_BUFG_BOT_R_CK_MUXED24", - "CLK_BUFG_BOT_R_CK_MUXED25", - "CLK_BUFG_BOT_R_CK_MUXED26", - "CLK_BUFG_BOT_R_CK_MUXED27", - "CLK_BUFG_BOT_R_CK_MUXED28", - "CLK_BUFG_BOT_R_CK_MUXED29", - "CLK_BUFG_BOT_R_CK_MUXED3", - "CLK_BUFG_BOT_R_CK_MUXED30", - "CLK_BUFG_BOT_R_CK_MUXED31", - "CLK_BUFG_BOT_R_CK_MUXED4", - "CLK_BUFG_BOT_R_CK_MUXED5", - "CLK_BUFG_BOT_R_CK_MUXED6", - "CLK_BUFG_BOT_R_CK_MUXED7", - "CLK_BUFG_BOT_R_CK_MUXED8", - "CLK_BUFG_BOT_R_CK_MUXED9", - "CLK_BUFG_BUFGCTRL0_I0", - "CLK_BUFG_BUFGCTRL0_I1", - "CLK_BUFG_BUFGCTRL0_O", - "CLK_BUFG_BUFGCTRL10_I0", - "CLK_BUFG_BUFGCTRL10_I1", - "CLK_BUFG_BUFGCTRL10_O", - "CLK_BUFG_BUFGCTRL11_I0", - "CLK_BUFG_BUFGCTRL11_I1", - "CLK_BUFG_BUFGCTRL11_O", - "CLK_BUFG_BUFGCTRL12_I0", - "CLK_BUFG_BUFGCTRL12_I1", - "CLK_BUFG_BUFGCTRL12_O", - "CLK_BUFG_BUFGCTRL13_I0", - "CLK_BUFG_BUFGCTRL13_I1", - "CLK_BUFG_BUFGCTRL13_O", - "CLK_BUFG_BUFGCTRL14_I0", - "CLK_BUFG_BUFGCTRL14_I1", - "CLK_BUFG_BUFGCTRL14_O", - "CLK_BUFG_BUFGCTRL15_I0", - "CLK_BUFG_BUFGCTRL15_I1", - "CLK_BUFG_BUFGCTRL15_O", - "CLK_BUFG_BUFGCTRL1_I0", - "CLK_BUFG_BUFGCTRL1_I1", - "CLK_BUFG_BUFGCTRL1_O", - "CLK_BUFG_BUFGCTRL2_I0", - "CLK_BUFG_BUFGCTRL2_I1", - "CLK_BUFG_BUFGCTRL2_O", - "CLK_BUFG_BUFGCTRL3_I0", - "CLK_BUFG_BUFGCTRL3_I1", - "CLK_BUFG_BUFGCTRL3_O", - "CLK_BUFG_BUFGCTRL4_I0", - "CLK_BUFG_BUFGCTRL4_I1", - "CLK_BUFG_BUFGCTRL4_O", - "CLK_BUFG_BUFGCTRL5_I0", - "CLK_BUFG_BUFGCTRL5_I1", - "CLK_BUFG_BUFGCTRL5_O", - "CLK_BUFG_BUFGCTRL6_I0", - "CLK_BUFG_BUFGCTRL6_I1", - "CLK_BUFG_BUFGCTRL6_O", - "CLK_BUFG_BUFGCTRL7_I0", - "CLK_BUFG_BUFGCTRL7_I1", - "CLK_BUFG_BUFGCTRL7_O", - "CLK_BUFG_BUFGCTRL8_I0", - "CLK_BUFG_BUFGCTRL8_I1", - "CLK_BUFG_BUFGCTRL8_O", - "CLK_BUFG_BUFGCTRL9_I0", - "CLK_BUFG_BUFGCTRL9_I1", - "CLK_BUFG_BUFGCTRL9_O", - "CLK_BUFG_CK_GCLK0", - "CLK_BUFG_CK_GCLK1", - "CLK_BUFG_CK_GCLK10", - "CLK_BUFG_CK_GCLK11", - "CLK_BUFG_CK_GCLK12", - "CLK_BUFG_CK_GCLK13", - "CLK_BUFG_CK_GCLK14", - "CLK_BUFG_CK_GCLK15", - "CLK_BUFG_CK_GCLK16", - "CLK_BUFG_CK_GCLK17", - "CLK_BUFG_CK_GCLK18", - "CLK_BUFG_CK_GCLK19", - "CLK_BUFG_CK_GCLK2", - "CLK_BUFG_CK_GCLK20", - "CLK_BUFG_CK_GCLK21", - "CLK_BUFG_CK_GCLK22", - "CLK_BUFG_CK_GCLK23", - "CLK_BUFG_CK_GCLK24", - "CLK_BUFG_CK_GCLK25", - "CLK_BUFG_CK_GCLK26", - "CLK_BUFG_CK_GCLK27", - "CLK_BUFG_CK_GCLK28", - "CLK_BUFG_CK_GCLK29", - "CLK_BUFG_CK_GCLK3", - "CLK_BUFG_CK_GCLK30", - "CLK_BUFG_CK_GCLK31", - "CLK_BUFG_CK_GCLK4", - "CLK_BUFG_CK_GCLK5", - "CLK_BUFG_CK_GCLK6", - "CLK_BUFG_CK_GCLK7", - "CLK_BUFG_CK_GCLK8", - "CLK_BUFG_CK_GCLK9", - "CLK_BUFG_IMUX0_0", - "CLK_BUFG_IMUX0_1", - "CLK_BUFG_IMUX0_2", - "CLK_BUFG_IMUX0_3", - "CLK_BUFG_IMUX10_0", - "CLK_BUFG_IMUX10_1", - "CLK_BUFG_IMUX10_2", - "CLK_BUFG_IMUX10_3", - "CLK_BUFG_IMUX11_0", - "CLK_BUFG_IMUX11_1", - "CLK_BUFG_IMUX11_2", - "CLK_BUFG_IMUX11_3", - "CLK_BUFG_IMUX12_0", - "CLK_BUFG_IMUX12_1", - "CLK_BUFG_IMUX12_2", - "CLK_BUFG_IMUX12_3", - "CLK_BUFG_IMUX13_0", - "CLK_BUFG_IMUX13_1", - "CLK_BUFG_IMUX13_2", - "CLK_BUFG_IMUX13_3", - "CLK_BUFG_IMUX14_0", - "CLK_BUFG_IMUX14_1", - "CLK_BUFG_IMUX14_2", - "CLK_BUFG_IMUX14_3", - "CLK_BUFG_IMUX15_0", - "CLK_BUFG_IMUX15_1", - "CLK_BUFG_IMUX15_2", - "CLK_BUFG_IMUX15_3", - "CLK_BUFG_IMUX16_0", - "CLK_BUFG_IMUX16_1", - "CLK_BUFG_IMUX16_2", - "CLK_BUFG_IMUX16_3", - "CLK_BUFG_IMUX17_0", - "CLK_BUFG_IMUX17_1", - "CLK_BUFG_IMUX17_2", - "CLK_BUFG_IMUX17_3", - "CLK_BUFG_IMUX18_0", - "CLK_BUFG_IMUX18_1", - "CLK_BUFG_IMUX18_2", - "CLK_BUFG_IMUX18_3", - "CLK_BUFG_IMUX19_0", - "CLK_BUFG_IMUX19_1", - "CLK_BUFG_IMUX19_2", - "CLK_BUFG_IMUX19_3", - "CLK_BUFG_IMUX1_0", - "CLK_BUFG_IMUX1_1", - "CLK_BUFG_IMUX1_2", - "CLK_BUFG_IMUX1_3", - "CLK_BUFG_IMUX20_0", - "CLK_BUFG_IMUX20_1", - "CLK_BUFG_IMUX20_2", - "CLK_BUFG_IMUX20_3", - "CLK_BUFG_IMUX21_0", - "CLK_BUFG_IMUX21_1", - "CLK_BUFG_IMUX21_2", - "CLK_BUFG_IMUX21_3", - "CLK_BUFG_IMUX22_0", - "CLK_BUFG_IMUX22_1", - "CLK_BUFG_IMUX22_2", - "CLK_BUFG_IMUX22_3", - "CLK_BUFG_IMUX23_0", - "CLK_BUFG_IMUX23_1", - "CLK_BUFG_IMUX23_2", - "CLK_BUFG_IMUX23_3", - "CLK_BUFG_IMUX24_0", - "CLK_BUFG_IMUX24_1", - "CLK_BUFG_IMUX24_2", - "CLK_BUFG_IMUX24_3", - "CLK_BUFG_IMUX25_0", - "CLK_BUFG_IMUX25_1", - "CLK_BUFG_IMUX25_2", - "CLK_BUFG_IMUX25_3", - "CLK_BUFG_IMUX26_0", - "CLK_BUFG_IMUX26_1", - "CLK_BUFG_IMUX26_2", - "CLK_BUFG_IMUX26_3", - "CLK_BUFG_IMUX27_0", - "CLK_BUFG_IMUX27_1", - "CLK_BUFG_IMUX27_2", - "CLK_BUFG_IMUX27_3", - "CLK_BUFG_IMUX28_0", - "CLK_BUFG_IMUX28_1", - "CLK_BUFG_IMUX28_2", - "CLK_BUFG_IMUX28_3", - "CLK_BUFG_IMUX29_0", - "CLK_BUFG_IMUX29_1", - "CLK_BUFG_IMUX29_2", - "CLK_BUFG_IMUX29_3", - "CLK_BUFG_IMUX2_0", - "CLK_BUFG_IMUX2_1", - "CLK_BUFG_IMUX2_2", - "CLK_BUFG_IMUX2_3", - "CLK_BUFG_IMUX30_0", - "CLK_BUFG_IMUX30_1", - "CLK_BUFG_IMUX30_2", - "CLK_BUFG_IMUX30_3", - "CLK_BUFG_IMUX31_0", - "CLK_BUFG_IMUX31_1", - "CLK_BUFG_IMUX31_2", - "CLK_BUFG_IMUX31_3", - "CLK_BUFG_IMUX32_0", - "CLK_BUFG_IMUX32_1", - "CLK_BUFG_IMUX32_2", - "CLK_BUFG_IMUX32_3", - "CLK_BUFG_IMUX33_0", - "CLK_BUFG_IMUX33_1", - "CLK_BUFG_IMUX33_2", - "CLK_BUFG_IMUX33_3", - "CLK_BUFG_IMUX34_0", - "CLK_BUFG_IMUX34_1", - "CLK_BUFG_IMUX34_2", - "CLK_BUFG_IMUX34_3", - "CLK_BUFG_IMUX35_0", - "CLK_BUFG_IMUX35_1", - "CLK_BUFG_IMUX35_2", - "CLK_BUFG_IMUX35_3", - "CLK_BUFG_IMUX36_0", - "CLK_BUFG_IMUX36_1", - "CLK_BUFG_IMUX36_2", - "CLK_BUFG_IMUX36_3", - "CLK_BUFG_IMUX37_0", - "CLK_BUFG_IMUX37_1", - "CLK_BUFG_IMUX37_2", - "CLK_BUFG_IMUX37_3", - "CLK_BUFG_IMUX38_0", - "CLK_BUFG_IMUX38_1", - "CLK_BUFG_IMUX38_2", - "CLK_BUFG_IMUX38_3", - "CLK_BUFG_IMUX39_0", - "CLK_BUFG_IMUX39_1", - "CLK_BUFG_IMUX39_2", - "CLK_BUFG_IMUX39_3", - "CLK_BUFG_IMUX3_0", - "CLK_BUFG_IMUX3_1", - "CLK_BUFG_IMUX3_2", - "CLK_BUFG_IMUX3_3", - "CLK_BUFG_IMUX40_0", - "CLK_BUFG_IMUX40_1", - "CLK_BUFG_IMUX40_2", - "CLK_BUFG_IMUX40_3", - "CLK_BUFG_IMUX41_0", - "CLK_BUFG_IMUX41_1", - "CLK_BUFG_IMUX41_2", - "CLK_BUFG_IMUX41_3", - "CLK_BUFG_IMUX42_0", - "CLK_BUFG_IMUX42_1", - "CLK_BUFG_IMUX42_2", - "CLK_BUFG_IMUX42_3", - "CLK_BUFG_IMUX43_0", - "CLK_BUFG_IMUX43_1", - "CLK_BUFG_IMUX43_2", - "CLK_BUFG_IMUX43_3", - "CLK_BUFG_IMUX44_0", - "CLK_BUFG_IMUX44_1", - "CLK_BUFG_IMUX44_2", - "CLK_BUFG_IMUX44_3", - "CLK_BUFG_IMUX45_0", - "CLK_BUFG_IMUX45_1", - "CLK_BUFG_IMUX45_2", - "CLK_BUFG_IMUX45_3", - "CLK_BUFG_IMUX46_0", - "CLK_BUFG_IMUX46_1", - "CLK_BUFG_IMUX46_2", - "CLK_BUFG_IMUX46_3", - "CLK_BUFG_IMUX47_0", - "CLK_BUFG_IMUX47_1", - "CLK_BUFG_IMUX47_2", - "CLK_BUFG_IMUX47_3", - "CLK_BUFG_IMUX4_0", - "CLK_BUFG_IMUX4_1", - "CLK_BUFG_IMUX4_2", - "CLK_BUFG_IMUX4_3", - "CLK_BUFG_IMUX5_0", - "CLK_BUFG_IMUX5_1", - "CLK_BUFG_IMUX5_2", - "CLK_BUFG_IMUX5_3", - "CLK_BUFG_IMUX6_0", - "CLK_BUFG_IMUX6_1", - "CLK_BUFG_IMUX6_2", - "CLK_BUFG_IMUX6_3", - "CLK_BUFG_IMUX7_0", - "CLK_BUFG_IMUX7_1", - "CLK_BUFG_IMUX7_2", - "CLK_BUFG_IMUX7_3", - "CLK_BUFG_IMUX8_0", - "CLK_BUFG_IMUX8_1", - "CLK_BUFG_IMUX8_2", - "CLK_BUFG_IMUX8_3", - "CLK_BUFG_IMUX9_0", - "CLK_BUFG_IMUX9_1", - "CLK_BUFG_IMUX9_2", - "CLK_BUFG_IMUX9_3", - "CLK_BUFG_LOGIC_OUTS_B0_0", - "CLK_BUFG_LOGIC_OUTS_B0_1", - "CLK_BUFG_LOGIC_OUTS_B0_2", - "CLK_BUFG_LOGIC_OUTS_B0_3", - "CLK_BUFG_LOGIC_OUTS_B10_0", - "CLK_BUFG_LOGIC_OUTS_B10_1", - "CLK_BUFG_LOGIC_OUTS_B10_2", - "CLK_BUFG_LOGIC_OUTS_B10_3", - "CLK_BUFG_LOGIC_OUTS_B11_0", - "CLK_BUFG_LOGIC_OUTS_B11_1", - "CLK_BUFG_LOGIC_OUTS_B11_2", - "CLK_BUFG_LOGIC_OUTS_B11_3", - "CLK_BUFG_LOGIC_OUTS_B12_0", - "CLK_BUFG_LOGIC_OUTS_B12_1", - "CLK_BUFG_LOGIC_OUTS_B12_2", - "CLK_BUFG_LOGIC_OUTS_B12_3", - "CLK_BUFG_LOGIC_OUTS_B13_0", - "CLK_BUFG_LOGIC_OUTS_B13_1", - "CLK_BUFG_LOGIC_OUTS_B13_2", - "CLK_BUFG_LOGIC_OUTS_B13_3", - "CLK_BUFG_LOGIC_OUTS_B14_0", - "CLK_BUFG_LOGIC_OUTS_B14_1", - "CLK_BUFG_LOGIC_OUTS_B14_2", - "CLK_BUFG_LOGIC_OUTS_B14_3", - "CLK_BUFG_LOGIC_OUTS_B15_0", - "CLK_BUFG_LOGIC_OUTS_B15_1", - "CLK_BUFG_LOGIC_OUTS_B15_2", - "CLK_BUFG_LOGIC_OUTS_B15_3", - "CLK_BUFG_LOGIC_OUTS_B16_0", - "CLK_BUFG_LOGIC_OUTS_B16_1", - "CLK_BUFG_LOGIC_OUTS_B16_2", - "CLK_BUFG_LOGIC_OUTS_B16_3", - "CLK_BUFG_LOGIC_OUTS_B17_0", - "CLK_BUFG_LOGIC_OUTS_B17_1", - "CLK_BUFG_LOGIC_OUTS_B17_2", - "CLK_BUFG_LOGIC_OUTS_B17_3", - "CLK_BUFG_LOGIC_OUTS_B18_0", - "CLK_BUFG_LOGIC_OUTS_B18_1", - "CLK_BUFG_LOGIC_OUTS_B18_2", - "CLK_BUFG_LOGIC_OUTS_B18_3", - "CLK_BUFG_LOGIC_OUTS_B19_0", - "CLK_BUFG_LOGIC_OUTS_B19_1", - "CLK_BUFG_LOGIC_OUTS_B19_2", - "CLK_BUFG_LOGIC_OUTS_B19_3", - "CLK_BUFG_LOGIC_OUTS_B1_0", - "CLK_BUFG_LOGIC_OUTS_B1_1", - "CLK_BUFG_LOGIC_OUTS_B1_2", - "CLK_BUFG_LOGIC_OUTS_B1_3", - "CLK_BUFG_LOGIC_OUTS_B20_0", - "CLK_BUFG_LOGIC_OUTS_B20_1", - "CLK_BUFG_LOGIC_OUTS_B20_2", - "CLK_BUFG_LOGIC_OUTS_B20_3", - "CLK_BUFG_LOGIC_OUTS_B21_0", - "CLK_BUFG_LOGIC_OUTS_B21_1", - "CLK_BUFG_LOGIC_OUTS_B21_2", - "CLK_BUFG_LOGIC_OUTS_B21_3", - "CLK_BUFG_LOGIC_OUTS_B22_0", - "CLK_BUFG_LOGIC_OUTS_B22_1", - "CLK_BUFG_LOGIC_OUTS_B22_2", - "CLK_BUFG_LOGIC_OUTS_B22_3", - "CLK_BUFG_LOGIC_OUTS_B23_0", - "CLK_BUFG_LOGIC_OUTS_B23_1", - "CLK_BUFG_LOGIC_OUTS_B23_2", - "CLK_BUFG_LOGIC_OUTS_B23_3", - "CLK_BUFG_LOGIC_OUTS_B2_0", - "CLK_BUFG_LOGIC_OUTS_B2_1", - "CLK_BUFG_LOGIC_OUTS_B2_2", - "CLK_BUFG_LOGIC_OUTS_B2_3", - "CLK_BUFG_LOGIC_OUTS_B3_0", - "CLK_BUFG_LOGIC_OUTS_B3_1", - "CLK_BUFG_LOGIC_OUTS_B3_2", - "CLK_BUFG_LOGIC_OUTS_B3_3", - "CLK_BUFG_LOGIC_OUTS_B4_0", - "CLK_BUFG_LOGIC_OUTS_B4_1", - "CLK_BUFG_LOGIC_OUTS_B4_2", - "CLK_BUFG_LOGIC_OUTS_B4_3", - "CLK_BUFG_LOGIC_OUTS_B5_0", - "CLK_BUFG_LOGIC_OUTS_B5_1", - "CLK_BUFG_LOGIC_OUTS_B5_2", - "CLK_BUFG_LOGIC_OUTS_B5_3", - "CLK_BUFG_LOGIC_OUTS_B6_0", - "CLK_BUFG_LOGIC_OUTS_B6_1", - "CLK_BUFG_LOGIC_OUTS_B6_2", - "CLK_BUFG_LOGIC_OUTS_B6_3", - "CLK_BUFG_LOGIC_OUTS_B7_0", - "CLK_BUFG_LOGIC_OUTS_B7_1", - "CLK_BUFG_LOGIC_OUTS_B7_2", - "CLK_BUFG_LOGIC_OUTS_B7_3", - "CLK_BUFG_LOGIC_OUTS_B8_0", - "CLK_BUFG_LOGIC_OUTS_B8_1", - "CLK_BUFG_LOGIC_OUTS_B8_2", - "CLK_BUFG_LOGIC_OUTS_B8_3", - "CLK_BUFG_LOGIC_OUTS_B9_0", - "CLK_BUFG_LOGIC_OUTS_B9_1", - "CLK_BUFG_LOGIC_OUTS_B9_2", - "CLK_BUFG_LOGIC_OUTS_B9_3", - "CLK_BUFG_R_BUFGCTRL0_CE0", - "CLK_BUFG_R_BUFGCTRL0_CE1", - "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "CLK_BUFG_R_BUFGCTRL0_S0", - "CLK_BUFG_R_BUFGCTRL0_S1", - "CLK_BUFG_R_BUFGCTRL10_CE0", - "CLK_BUFG_R_BUFGCTRL10_CE1", - "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "CLK_BUFG_R_BUFGCTRL10_S0", - "CLK_BUFG_R_BUFGCTRL10_S1", - "CLK_BUFG_R_BUFGCTRL11_CE0", - "CLK_BUFG_R_BUFGCTRL11_CE1", - "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "CLK_BUFG_R_BUFGCTRL11_S0", - "CLK_BUFG_R_BUFGCTRL11_S1", - "CLK_BUFG_R_BUFGCTRL12_CE0", - "CLK_BUFG_R_BUFGCTRL12_CE1", - "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "CLK_BUFG_R_BUFGCTRL12_S0", - "CLK_BUFG_R_BUFGCTRL12_S1", - "CLK_BUFG_R_BUFGCTRL13_CE0", - "CLK_BUFG_R_BUFGCTRL13_CE1", - "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "CLK_BUFG_R_BUFGCTRL13_S0", - "CLK_BUFG_R_BUFGCTRL13_S1", - "CLK_BUFG_R_BUFGCTRL14_CE0", - "CLK_BUFG_R_BUFGCTRL14_CE1", - "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "CLK_BUFG_R_BUFGCTRL14_S0", - "CLK_BUFG_R_BUFGCTRL14_S1", - "CLK_BUFG_R_BUFGCTRL15_CE0", - "CLK_BUFG_R_BUFGCTRL15_CE1", - "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "CLK_BUFG_R_BUFGCTRL15_S0", - "CLK_BUFG_R_BUFGCTRL15_S1", - "CLK_BUFG_R_BUFGCTRL1_CE0", - "CLK_BUFG_R_BUFGCTRL1_CE1", - "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "CLK_BUFG_R_BUFGCTRL1_S0", - "CLK_BUFG_R_BUFGCTRL1_S1", - "CLK_BUFG_R_BUFGCTRL2_CE0", - "CLK_BUFG_R_BUFGCTRL2_CE1", - "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "CLK_BUFG_R_BUFGCTRL2_S0", - "CLK_BUFG_R_BUFGCTRL2_S1", - "CLK_BUFG_R_BUFGCTRL3_CE0", - "CLK_BUFG_R_BUFGCTRL3_CE1", - "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "CLK_BUFG_R_BUFGCTRL3_S0", - "CLK_BUFG_R_BUFGCTRL3_S1", - "CLK_BUFG_R_BUFGCTRL4_CE0", - "CLK_BUFG_R_BUFGCTRL4_CE1", - "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "CLK_BUFG_R_BUFGCTRL4_S0", - "CLK_BUFG_R_BUFGCTRL4_S1", - "CLK_BUFG_R_BUFGCTRL5_CE0", - "CLK_BUFG_R_BUFGCTRL5_CE1", - "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "CLK_BUFG_R_BUFGCTRL5_S0", - "CLK_BUFG_R_BUFGCTRL5_S1", - "CLK_BUFG_R_BUFGCTRL6_CE0", - "CLK_BUFG_R_BUFGCTRL6_CE1", - "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "CLK_BUFG_R_BUFGCTRL6_S0", - "CLK_BUFG_R_BUFGCTRL6_S1", - "CLK_BUFG_R_BUFGCTRL7_CE0", - "CLK_BUFG_R_BUFGCTRL7_CE1", - "CLK_BUFG_R_BUFGCTRL7_IGNORE0", - "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "CLK_BUFG_R_BUFGCTRL7_S0", - "CLK_BUFG_R_BUFGCTRL7_S1", - "CLK_BUFG_R_BUFGCTRL8_CE0", - "CLK_BUFG_R_BUFGCTRL8_CE1", - "CLK_BUFG_R_BUFGCTRL8_IGNORE0", - "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "CLK_BUFG_R_BUFGCTRL8_S0", - "CLK_BUFG_R_BUFGCTRL8_S1", - "CLK_BUFG_R_BUFGCTRL9_CE0", - "CLK_BUFG_R_BUFGCTRL9_CE1", - "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "CLK_BUFG_R_BUFGCTRL9_S0", - "CLK_BUFG_R_BUFGCTRL9_S1", - "CLK_BUFG_R_CK_FB_TEST0_0", - "CLK_BUFG_R_CK_FB_TEST0_1", - "CLK_BUFG_R_CK_FB_TEST0_10", - "CLK_BUFG_R_CK_FB_TEST0_11", - "CLK_BUFG_R_CK_FB_TEST0_12", - "CLK_BUFG_R_CK_FB_TEST0_13", - "CLK_BUFG_R_CK_FB_TEST0_14", - "CLK_BUFG_R_CK_FB_TEST0_15", - "CLK_BUFG_R_CK_FB_TEST0_2", - "CLK_BUFG_R_CK_FB_TEST0_3", - "CLK_BUFG_R_CK_FB_TEST0_4", - "CLK_BUFG_R_CK_FB_TEST0_5", - "CLK_BUFG_R_CK_FB_TEST0_6", - "CLK_BUFG_R_CK_FB_TEST0_7", - "CLK_BUFG_R_CK_FB_TEST0_8", - "CLK_BUFG_R_CK_FB_TEST0_9", - "CLK_BUFG_R_CK_FB_TEST1_0", - "CLK_BUFG_R_CK_FB_TEST1_1", - "CLK_BUFG_R_CK_FB_TEST1_10", - "CLK_BUFG_R_CK_FB_TEST1_11", - "CLK_BUFG_R_CK_FB_TEST1_12", - "CLK_BUFG_R_CK_FB_TEST1_13", - "CLK_BUFG_R_CK_FB_TEST1_14", - "CLK_BUFG_R_CK_FB_TEST1_15", - "CLK_BUFG_R_CK_FB_TEST1_2", - "CLK_BUFG_R_CK_FB_TEST1_3", - "CLK_BUFG_R_CK_FB_TEST1_4", - "CLK_BUFG_R_CK_FB_TEST1_5", - "CLK_BUFG_R_CK_FB_TEST1_6", - "CLK_BUFG_R_CK_FB_TEST1_7", - "CLK_BUFG_R_CK_FB_TEST1_8", - "CLK_BUFG_R_CK_FB_TEST1_9", - "CLK_BUFG_R_FBG_OUT0", - "CLK_BUFG_R_FBG_OUT1", - "CLK_BUFG_R_FBG_OUT10", - "CLK_BUFG_R_FBG_OUT11", - "CLK_BUFG_R_FBG_OUT12", - "CLK_BUFG_R_FBG_OUT13", - "CLK_BUFG_R_FBG_OUT14", - "CLK_BUFG_R_FBG_OUT15", - "CLK_BUFG_R_FBG_OUT2", - "CLK_BUFG_R_FBG_OUT3", - "CLK_BUFG_R_FBG_OUT4", - "CLK_BUFG_R_FBG_OUT5", - "CLK_BUFG_R_FBG_OUT6", - "CLK_BUFG_R_FBG_OUT7", - "CLK_BUFG_R_FBG_OUT8", - "CLK_BUFG_R_FBG_OUT9", - "CLK_HROW_BLOCK_OUTS_B0_0", - "CLK_HROW_BLOCK_OUTS_B0_1", - "CLK_HROW_BLOCK_OUTS_B0_2", - "CLK_HROW_BLOCK_OUTS_B0_3", - "CLK_HROW_BLOCK_OUTS_B1_0", - "CLK_HROW_BLOCK_OUTS_B1_1", - "CLK_HROW_BLOCK_OUTS_B1_2", - "CLK_HROW_BLOCK_OUTS_B1_3", - "CLK_HROW_BLOCK_OUTS_B2_0", - "CLK_HROW_BLOCK_OUTS_B2_1", - "CLK_HROW_BLOCK_OUTS_B2_2", - "CLK_HROW_BLOCK_OUTS_B2_3", - "CLK_HROW_BLOCK_OUTS_B3_0", - "CLK_HROW_BLOCK_OUTS_B3_1", - "CLK_HROW_BLOCK_OUTS_B3_2", - "CLK_HROW_BLOCK_OUTS_B3_3", - "CLK_HROW_BYP0_0", - "CLK_HROW_BYP0_1", - "CLK_HROW_BYP0_2", - "CLK_HROW_BYP0_3", - "CLK_HROW_BYP1_0", - "CLK_HROW_BYP1_1", - "CLK_HROW_BYP1_2", - "CLK_HROW_BYP1_3", - "CLK_HROW_BYP2_0", - "CLK_HROW_BYP2_1", - "CLK_HROW_BYP2_2", - "CLK_HROW_BYP2_3", - "CLK_HROW_BYP3_0", - "CLK_HROW_BYP3_1", - "CLK_HROW_BYP3_2", - "CLK_HROW_BYP3_3", - "CLK_HROW_BYP4_0", - "CLK_HROW_BYP4_1", - "CLK_HROW_BYP4_2", - "CLK_HROW_BYP4_3", - "CLK_HROW_BYP5_0", - "CLK_HROW_BYP5_1", - "CLK_HROW_BYP5_2", - "CLK_HROW_BYP5_3", - "CLK_HROW_BYP6_0", - "CLK_HROW_BYP6_1", - "CLK_HROW_BYP6_2", - "CLK_HROW_BYP6_3", - "CLK_HROW_BYP7_0", - "CLK_HROW_BYP7_1", - "CLK_HROW_BYP7_2", - "CLK_HROW_BYP7_3", - "CLK_HROW_CLK0_0", - "CLK_HROW_CLK0_1", - "CLK_HROW_CLK0_2", - "CLK_HROW_CLK0_3", - "CLK_HROW_CLK1_0", - "CLK_HROW_CLK1_1", - "CLK_HROW_CLK1_2", - "CLK_HROW_CLK1_3", - "CLK_HROW_CTRL0_0", - "CLK_HROW_CTRL0_1", - "CLK_HROW_CTRL0_2", - "CLK_HROW_CTRL0_3", - "CLK_HROW_CTRL1_0", - "CLK_HROW_CTRL1_1", - "CLK_HROW_CTRL1_2", - "CLK_HROW_CTRL1_3", - "CLK_HROW_EE2A0_0", - "CLK_HROW_EE2A0_1", - "CLK_HROW_EE2A0_2", - "CLK_HROW_EE2A0_3", - "CLK_HROW_EE2A1_0", - "CLK_HROW_EE2A1_1", - "CLK_HROW_EE2A1_2", - "CLK_HROW_EE2A1_3", - "CLK_HROW_EE2A2_0", - "CLK_HROW_EE2A2_1", - "CLK_HROW_EE2A2_2", - "CLK_HROW_EE2A2_3", - "CLK_HROW_EE2A3_0", - "CLK_HROW_EE2A3_1", - "CLK_HROW_EE2A3_2", - "CLK_HROW_EE2A3_3", - "CLK_HROW_EE2BEG0_0", - "CLK_HROW_EE2BEG0_1", - "CLK_HROW_EE2BEG0_2", - "CLK_HROW_EE2BEG0_3", - "CLK_HROW_EE2BEG1_0", - "CLK_HROW_EE2BEG1_1", - "CLK_HROW_EE2BEG1_2", - "CLK_HROW_EE2BEG1_3", - "CLK_HROW_EE2BEG2_0", - "CLK_HROW_EE2BEG2_1", - "CLK_HROW_EE2BEG2_2", - "CLK_HROW_EE2BEG2_3", - "CLK_HROW_EE2BEG3_0", - "CLK_HROW_EE2BEG3_1", - "CLK_HROW_EE2BEG3_2", - "CLK_HROW_EE2BEG3_3", - "CLK_HROW_EE4A0_0", - "CLK_HROW_EE4A0_1", - "CLK_HROW_EE4A0_2", - "CLK_HROW_EE4A0_3", - "CLK_HROW_EE4A1_0", - "CLK_HROW_EE4A1_1", - "CLK_HROW_EE4A1_2", - "CLK_HROW_EE4A1_3", - "CLK_HROW_EE4A2_0", - "CLK_HROW_EE4A2_1", - "CLK_HROW_EE4A2_2", - "CLK_HROW_EE4A2_3", - "CLK_HROW_EE4A3_0", - "CLK_HROW_EE4A3_1", - "CLK_HROW_EE4A3_2", - "CLK_HROW_EE4A3_3", - "CLK_HROW_EE4B0_0", - "CLK_HROW_EE4B0_1", - "CLK_HROW_EE4B0_2", - "CLK_HROW_EE4B0_3", - "CLK_HROW_EE4B1_0", - "CLK_HROW_EE4B1_1", - "CLK_HROW_EE4B1_2", - "CLK_HROW_EE4B1_3", - "CLK_HROW_EE4B2_0", - "CLK_HROW_EE4B2_1", - "CLK_HROW_EE4B2_2", - "CLK_HROW_EE4B2_3", - "CLK_HROW_EE4B3_0", - "CLK_HROW_EE4B3_1", - "CLK_HROW_EE4B3_2", - "CLK_HROW_EE4B3_3", - "CLK_HROW_EE4BEG0_0", - "CLK_HROW_EE4BEG0_1", - "CLK_HROW_EE4BEG0_2", - "CLK_HROW_EE4BEG0_3", - "CLK_HROW_EE4BEG1_0", - "CLK_HROW_EE4BEG1_1", - "CLK_HROW_EE4BEG1_2", - "CLK_HROW_EE4BEG1_3", - "CLK_HROW_EE4BEG2_0", - "CLK_HROW_EE4BEG2_1", - "CLK_HROW_EE4BEG2_2", - "CLK_HROW_EE4BEG2_3", - "CLK_HROW_EE4BEG3_0", - "CLK_HROW_EE4BEG3_1", - "CLK_HROW_EE4BEG3_2", - "CLK_HROW_EE4BEG3_3", - "CLK_HROW_EE4C0_0", - "CLK_HROW_EE4C0_1", - "CLK_HROW_EE4C0_2", - "CLK_HROW_EE4C0_3", - "CLK_HROW_EE4C1_0", - "CLK_HROW_EE4C1_1", - "CLK_HROW_EE4C1_2", - "CLK_HROW_EE4C1_3", - "CLK_HROW_EE4C2_0", - "CLK_HROW_EE4C2_1", - "CLK_HROW_EE4C2_2", - "CLK_HROW_EE4C2_3", - "CLK_HROW_EE4C3_0", - "CLK_HROW_EE4C3_1", - "CLK_HROW_EE4C3_2", - "CLK_HROW_EE4C3_3", - "CLK_HROW_EL1BEG0_0", - "CLK_HROW_EL1BEG0_1", - "CLK_HROW_EL1BEG0_2", - "CLK_HROW_EL1BEG0_3", - "CLK_HROW_EL1BEG1_0", - "CLK_HROW_EL1BEG1_1", - "CLK_HROW_EL1BEG1_2", - "CLK_HROW_EL1BEG1_3", - "CLK_HROW_EL1BEG2_0", - "CLK_HROW_EL1BEG2_1", - "CLK_HROW_EL1BEG2_2", - "CLK_HROW_EL1BEG2_3", - "CLK_HROW_EL1BEG3_0", - "CLK_HROW_EL1BEG3_1", - "CLK_HROW_EL1BEG3_2", - "CLK_HROW_EL1BEG3_3", - "CLK_HROW_ER1BEG0_0", - "CLK_HROW_ER1BEG0_1", - "CLK_HROW_ER1BEG0_2", - "CLK_HROW_ER1BEG0_3", - "CLK_HROW_ER1BEG1_0", - "CLK_HROW_ER1BEG1_1", - "CLK_HROW_ER1BEG1_2", - "CLK_HROW_ER1BEG1_3", - "CLK_HROW_ER1BEG2_0", - "CLK_HROW_ER1BEG2_1", - "CLK_HROW_ER1BEG2_2", - "CLK_HROW_ER1BEG2_3", - "CLK_HROW_ER1BEG3_0", - "CLK_HROW_ER1BEG3_1", - "CLK_HROW_ER1BEG3_2", - "CLK_HROW_ER1BEG3_3", - "CLK_HROW_FAN0_0", - "CLK_HROW_FAN0_1", - "CLK_HROW_FAN0_2", - "CLK_HROW_FAN0_3", - "CLK_HROW_FAN1_0", - "CLK_HROW_FAN1_1", - "CLK_HROW_FAN1_2", - "CLK_HROW_FAN1_3", - "CLK_HROW_FAN2_0", - "CLK_HROW_FAN2_1", - "CLK_HROW_FAN2_2", - "CLK_HROW_FAN2_3", - "CLK_HROW_FAN3_0", - "CLK_HROW_FAN3_1", - "CLK_HROW_FAN3_2", - "CLK_HROW_FAN3_3", - "CLK_HROW_FAN4_0", - "CLK_HROW_FAN4_1", - "CLK_HROW_FAN4_2", - "CLK_HROW_FAN4_3", - "CLK_HROW_FAN5_0", - "CLK_HROW_FAN5_1", - "CLK_HROW_FAN5_2", - "CLK_HROW_FAN5_3", - "CLK_HROW_FAN6_0", - "CLK_HROW_FAN6_1", - "CLK_HROW_FAN6_2", - "CLK_HROW_FAN6_3", - "CLK_HROW_FAN7_0", - "CLK_HROW_FAN7_1", - "CLK_HROW_FAN7_2", - "CLK_HROW_FAN7_3", - "CLK_HROW_LH10_0", - "CLK_HROW_LH10_1", - "CLK_HROW_LH10_2", - "CLK_HROW_LH10_3", - "CLK_HROW_LH11_0", - "CLK_HROW_LH11_1", - "CLK_HROW_LH11_2", - "CLK_HROW_LH11_3", - "CLK_HROW_LH12_0", - "CLK_HROW_LH12_1", - "CLK_HROW_LH12_2", - "CLK_HROW_LH12_3", - "CLK_HROW_LH1_0", - "CLK_HROW_LH1_1", - "CLK_HROW_LH1_2", - "CLK_HROW_LH1_3", - "CLK_HROW_LH2_0", - "CLK_HROW_LH2_1", - "CLK_HROW_LH2_2", - "CLK_HROW_LH2_3", - "CLK_HROW_LH3_0", - "CLK_HROW_LH3_1", - "CLK_HROW_LH3_2", - "CLK_HROW_LH3_3", - "CLK_HROW_LH4_0", - "CLK_HROW_LH4_1", - "CLK_HROW_LH4_2", - "CLK_HROW_LH4_3", - "CLK_HROW_LH5_0", - "CLK_HROW_LH5_1", - "CLK_HROW_LH5_2", - "CLK_HROW_LH5_3", - "CLK_HROW_LH6_0", - "CLK_HROW_LH6_1", - "CLK_HROW_LH6_2", - "CLK_HROW_LH6_3", - "CLK_HROW_LH7_0", - "CLK_HROW_LH7_1", - "CLK_HROW_LH7_2", - "CLK_HROW_LH7_3", - "CLK_HROW_LH8_0", - "CLK_HROW_LH8_1", - "CLK_HROW_LH8_2", - "CLK_HROW_LH8_3", - "CLK_HROW_LH9_0", - "CLK_HROW_LH9_1", - "CLK_HROW_LH9_2", - "CLK_HROW_LH9_3", - "CLK_HROW_MONITOR_N_0", - "CLK_HROW_MONITOR_N_1", - "CLK_HROW_MONITOR_N_2", - "CLK_HROW_MONITOR_N_3", - "CLK_HROW_MONITOR_P_0", - "CLK_HROW_MONITOR_P_1", - "CLK_HROW_MONITOR_P_2", - "CLK_HROW_MONITOR_P_3", - "CLK_HROW_NE2A0_0", - "CLK_HROW_NE2A0_1", - "CLK_HROW_NE2A0_2", - "CLK_HROW_NE2A0_3", - "CLK_HROW_NE2A1_0", - "CLK_HROW_NE2A1_1", - "CLK_HROW_NE2A1_2", - "CLK_HROW_NE2A1_3", - "CLK_HROW_NE2A2_0", - "CLK_HROW_NE2A2_1", - "CLK_HROW_NE2A2_2", - "CLK_HROW_NE2A2_3", - "CLK_HROW_NE2A3_0", - "CLK_HROW_NE2A3_1", - "CLK_HROW_NE2A3_2", - "CLK_HROW_NE2A3_3", - "CLK_HROW_NE4BEG0_0", - "CLK_HROW_NE4BEG0_1", - "CLK_HROW_NE4BEG0_2", - "CLK_HROW_NE4BEG0_3", - "CLK_HROW_NE4BEG1_0", - "CLK_HROW_NE4BEG1_1", - "CLK_HROW_NE4BEG1_2", - "CLK_HROW_NE4BEG1_3", - "CLK_HROW_NE4BEG2_0", - "CLK_HROW_NE4BEG2_1", - "CLK_HROW_NE4BEG2_2", - "CLK_HROW_NE4BEG2_3", - "CLK_HROW_NE4BEG3_0", - "CLK_HROW_NE4BEG3_1", - "CLK_HROW_NE4BEG3_2", - "CLK_HROW_NE4BEG3_3", - "CLK_HROW_NE4C0_0", - "CLK_HROW_NE4C0_1", - "CLK_HROW_NE4C0_2", - "CLK_HROW_NE4C0_3", - "CLK_HROW_NE4C1_0", - "CLK_HROW_NE4C1_1", - "CLK_HROW_NE4C1_2", - "CLK_HROW_NE4C1_3", - "CLK_HROW_NE4C2_0", - "CLK_HROW_NE4C2_1", - "CLK_HROW_NE4C2_2", - "CLK_HROW_NE4C2_3", - "CLK_HROW_NE4C3_0", - "CLK_HROW_NE4C3_1", - "CLK_HROW_NE4C3_2", - "CLK_HROW_NE4C3_3", - "CLK_HROW_NW2A0_0", - "CLK_HROW_NW2A0_1", - "CLK_HROW_NW2A0_2", - "CLK_HROW_NW2A0_3", - "CLK_HROW_NW2A1_0", - "CLK_HROW_NW2A1_1", - "CLK_HROW_NW2A1_2", - "CLK_HROW_NW2A1_3", - "CLK_HROW_NW2A2_0", - "CLK_HROW_NW2A2_1", - "CLK_HROW_NW2A2_2", - "CLK_HROW_NW2A2_3", - "CLK_HROW_NW2A3_0", - "CLK_HROW_NW2A3_1", - "CLK_HROW_NW2A3_2", - "CLK_HROW_NW2A3_3", - "CLK_HROW_NW4A0_0", - "CLK_HROW_NW4A0_1", - "CLK_HROW_NW4A0_2", - "CLK_HROW_NW4A0_3", - "CLK_HROW_NW4A1_0", - "CLK_HROW_NW4A1_1", - "CLK_HROW_NW4A1_2", - "CLK_HROW_NW4A1_3", - "CLK_HROW_NW4A2_0", - "CLK_HROW_NW4A2_1", - "CLK_HROW_NW4A2_2", - "CLK_HROW_NW4A2_3", - "CLK_HROW_NW4A3_0", - "CLK_HROW_NW4A3_1", - "CLK_HROW_NW4A3_2", - "CLK_HROW_NW4A3_3", - "CLK_HROW_NW4END0_0", - "CLK_HROW_NW4END0_1", - "CLK_HROW_NW4END0_2", - "CLK_HROW_NW4END0_3", - "CLK_HROW_NW4END1_0", - "CLK_HROW_NW4END1_1", - "CLK_HROW_NW4END1_2", - "CLK_HROW_NW4END1_3", - "CLK_HROW_NW4END2_0", - "CLK_HROW_NW4END2_1", - "CLK_HROW_NW4END2_2", - "CLK_HROW_NW4END2_3", - "CLK_HROW_NW4END3_0", - "CLK_HROW_NW4END3_1", - "CLK_HROW_NW4END3_2", - "CLK_HROW_NW4END3_3", - "CLK_HROW_SE2A0_0", - "CLK_HROW_SE2A0_1", - "CLK_HROW_SE2A0_2", - "CLK_HROW_SE2A0_3", - "CLK_HROW_SE2A1_0", - "CLK_HROW_SE2A1_1", - "CLK_HROW_SE2A1_2", - "CLK_HROW_SE2A1_3", - "CLK_HROW_SE2A2_0", - "CLK_HROW_SE2A2_1", - "CLK_HROW_SE2A2_2", - "CLK_HROW_SE2A2_3", - "CLK_HROW_SE2A3_0", - "CLK_HROW_SE2A3_1", - "CLK_HROW_SE2A3_2", - "CLK_HROW_SE2A3_3", - "CLK_HROW_SE4BEG0_0", - "CLK_HROW_SE4BEG0_1", - "CLK_HROW_SE4BEG0_2", - "CLK_HROW_SE4BEG0_3", - "CLK_HROW_SE4BEG1_0", - "CLK_HROW_SE4BEG1_1", - "CLK_HROW_SE4BEG1_2", - "CLK_HROW_SE4BEG1_3", - "CLK_HROW_SE4BEG2_0", - "CLK_HROW_SE4BEG2_1", - "CLK_HROW_SE4BEG2_2", - "CLK_HROW_SE4BEG2_3", - "CLK_HROW_SE4BEG3_0", - "CLK_HROW_SE4BEG3_1", - "CLK_HROW_SE4BEG3_2", - "CLK_HROW_SE4BEG3_3", - "CLK_HROW_SE4C0_0", - "CLK_HROW_SE4C0_1", - "CLK_HROW_SE4C0_2", - "CLK_HROW_SE4C0_3", - "CLK_HROW_SE4C1_0", - "CLK_HROW_SE4C1_1", - "CLK_HROW_SE4C1_2", - "CLK_HROW_SE4C1_3", - "CLK_HROW_SE4C2_0", - "CLK_HROW_SE4C2_1", - "CLK_HROW_SE4C2_2", - "CLK_HROW_SE4C2_3", - "CLK_HROW_SE4C3_0", - "CLK_HROW_SE4C3_1", - "CLK_HROW_SE4C3_2", - "CLK_HROW_SE4C3_3", - "CLK_HROW_SW2A0_0", - "CLK_HROW_SW2A0_1", - "CLK_HROW_SW2A0_2", - "CLK_HROW_SW2A0_3", - "CLK_HROW_SW2A1_0", - "CLK_HROW_SW2A1_1", - "CLK_HROW_SW2A1_2", - "CLK_HROW_SW2A1_3", - "CLK_HROW_SW2A2_0", - "CLK_HROW_SW2A2_1", - "CLK_HROW_SW2A2_2", - "CLK_HROW_SW2A2_3", - "CLK_HROW_SW2A3_0", - "CLK_HROW_SW2A3_1", - "CLK_HROW_SW2A3_2", - "CLK_HROW_SW2A3_3", - "CLK_HROW_SW4A0_0", - "CLK_HROW_SW4A0_1", - "CLK_HROW_SW4A0_2", - "CLK_HROW_SW4A0_3", - "CLK_HROW_SW4A1_0", - "CLK_HROW_SW4A1_1", - "CLK_HROW_SW4A1_2", - "CLK_HROW_SW4A1_3", - "CLK_HROW_SW4A2_0", - "CLK_HROW_SW4A2_1", - "CLK_HROW_SW4A2_2", - "CLK_HROW_SW4A2_3", - "CLK_HROW_SW4A3_0", - "CLK_HROW_SW4A3_1", - "CLK_HROW_SW4A3_2", - "CLK_HROW_SW4A3_3", - "CLK_HROW_SW4END0_0", - "CLK_HROW_SW4END0_1", - "CLK_HROW_SW4END0_2", - "CLK_HROW_SW4END0_3", - "CLK_HROW_SW4END1_0", - "CLK_HROW_SW4END1_1", - "CLK_HROW_SW4END1_2", - "CLK_HROW_SW4END1_3", - "CLK_HROW_SW4END2_0", - "CLK_HROW_SW4END2_1", - "CLK_HROW_SW4END2_2", - "CLK_HROW_SW4END2_3", - "CLK_HROW_SW4END3_0", - "CLK_HROW_SW4END3_1", - "CLK_HROW_SW4END3_2", - "CLK_HROW_SW4END3_3", - "CLK_HROW_WL1END0_0", - "CLK_HROW_WL1END0_1", - "CLK_HROW_WL1END0_2", - "CLK_HROW_WL1END0_3", - "CLK_HROW_WL1END1_0", - "CLK_HROW_WL1END1_1", - "CLK_HROW_WL1END1_2", - "CLK_HROW_WL1END1_3", - "CLK_HROW_WL1END2_0", - "CLK_HROW_WL1END2_1", - "CLK_HROW_WL1END2_2", - "CLK_HROW_WL1END2_3", - "CLK_HROW_WL1END3_0", - "CLK_HROW_WL1END3_1", - "CLK_HROW_WL1END3_2", - "CLK_HROW_WL1END3_3", - "CLK_HROW_WR1END0_0", - "CLK_HROW_WR1END0_1", - "CLK_HROW_WR1END0_2", - "CLK_HROW_WR1END0_3", - "CLK_HROW_WR1END1_0", - "CLK_HROW_WR1END1_1", - "CLK_HROW_WR1END1_2", - "CLK_HROW_WR1END1_3", - "CLK_HROW_WR1END2_0", - "CLK_HROW_WR1END2_1", - "CLK_HROW_WR1END2_2", - "CLK_HROW_WR1END2_3", - "CLK_HROW_WR1END3_0", - "CLK_HROW_WR1END3_1", - "CLK_HROW_WR1END3_2", - "CLK_HROW_WR1END3_3", - "CLK_HROW_WW2A0_0", - "CLK_HROW_WW2A0_1", - "CLK_HROW_WW2A0_2", - "CLK_HROW_WW2A0_3", - "CLK_HROW_WW2A1_0", - "CLK_HROW_WW2A1_1", - "CLK_HROW_WW2A1_2", - "CLK_HROW_WW2A1_3", - "CLK_HROW_WW2A2_0", - "CLK_HROW_WW2A2_1", - "CLK_HROW_WW2A2_2", - "CLK_HROW_WW2A2_3", - "CLK_HROW_WW2A3_0", - "CLK_HROW_WW2A3_1", - "CLK_HROW_WW2A3_2", - "CLK_HROW_WW2A3_3", - "CLK_HROW_WW2END0_0", - "CLK_HROW_WW2END0_1", - "CLK_HROW_WW2END0_2", - "CLK_HROW_WW2END0_3", - "CLK_HROW_WW2END1_0", - "CLK_HROW_WW2END1_1", - "CLK_HROW_WW2END1_2", - "CLK_HROW_WW2END1_3", - "CLK_HROW_WW2END2_0", - "CLK_HROW_WW2END2_1", - "CLK_HROW_WW2END2_2", - "CLK_HROW_WW2END2_3", - "CLK_HROW_WW2END3_0", - "CLK_HROW_WW2END3_1", - "CLK_HROW_WW2END3_2", - "CLK_HROW_WW2END3_3", - "CLK_HROW_WW4A0_0", - "CLK_HROW_WW4A0_1", - "CLK_HROW_WW4A0_2", - "CLK_HROW_WW4A0_3", - "CLK_HROW_WW4A1_0", - "CLK_HROW_WW4A1_1", - "CLK_HROW_WW4A1_2", - "CLK_HROW_WW4A1_3", - "CLK_HROW_WW4A2_0", - "CLK_HROW_WW4A2_1", - "CLK_HROW_WW4A2_2", - "CLK_HROW_WW4A2_3", - "CLK_HROW_WW4A3_0", - "CLK_HROW_WW4A3_1", - "CLK_HROW_WW4A3_2", - "CLK_HROW_WW4A3_3", - "CLK_HROW_WW4B0_0", - "CLK_HROW_WW4B0_1", - "CLK_HROW_WW4B0_2", - "CLK_HROW_WW4B0_3", - "CLK_HROW_WW4B1_0", - "CLK_HROW_WW4B1_1", - "CLK_HROW_WW4B1_2", - "CLK_HROW_WW4B1_3", - "CLK_HROW_WW4B2_0", - "CLK_HROW_WW4B2_1", - "CLK_HROW_WW4B2_2", - "CLK_HROW_WW4B2_3", - "CLK_HROW_WW4B3_0", - "CLK_HROW_WW4B3_1", - "CLK_HROW_WW4B3_2", - "CLK_HROW_WW4B3_3", - "CLK_HROW_WW4C0_0", - "CLK_HROW_WW4C0_1", - "CLK_HROW_WW4C0_2", - "CLK_HROW_WW4C0_3", - "CLK_HROW_WW4C1_0", - "CLK_HROW_WW4C1_1", - "CLK_HROW_WW4C1_2", - "CLK_HROW_WW4C1_3", - "CLK_HROW_WW4C2_0", - "CLK_HROW_WW4C2_1", - "CLK_HROW_WW4C2_2", - "CLK_HROW_WW4C2_3", - "CLK_HROW_WW4C3_0", - "CLK_HROW_WW4C3_1", - "CLK_HROW_WW4C3_2", - "CLK_HROW_WW4C3_3", - "CLK_HROW_WW4END0_0", - "CLK_HROW_WW4END0_1", - "CLK_HROW_WW4END0_2", - "CLK_HROW_WW4END0_3", - "CLK_HROW_WW4END1_0", - "CLK_HROW_WW4END1_1", - "CLK_HROW_WW4END1_2", - "CLK_HROW_WW4END1_3", - "CLK_HROW_WW4END2_0", - "CLK_HROW_WW4END2_1", - "CLK_HROW_WW4END2_2", - "CLK_HROW_WW4END2_3", - "CLK_HROW_WW4END3_0", - "CLK_HROW_WW4END3_1", - "CLK_HROW_WW4END3_2", - "CLK_HROW_WW4END3_3" - ] + "wires": { + "CLK_BUFG_BOT_R_CK_MUXED0": null, + "CLK_BUFG_BOT_R_CK_MUXED1": null, + "CLK_BUFG_BOT_R_CK_MUXED10": null, + "CLK_BUFG_BOT_R_CK_MUXED11": null, + "CLK_BUFG_BOT_R_CK_MUXED12": null, + "CLK_BUFG_BOT_R_CK_MUXED13": null, + "CLK_BUFG_BOT_R_CK_MUXED14": null, + "CLK_BUFG_BOT_R_CK_MUXED15": null, + "CLK_BUFG_BOT_R_CK_MUXED16": null, + "CLK_BUFG_BOT_R_CK_MUXED17": null, + "CLK_BUFG_BOT_R_CK_MUXED18": null, + "CLK_BUFG_BOT_R_CK_MUXED19": null, + "CLK_BUFG_BOT_R_CK_MUXED2": null, + "CLK_BUFG_BOT_R_CK_MUXED20": null, + "CLK_BUFG_BOT_R_CK_MUXED21": null, + "CLK_BUFG_BOT_R_CK_MUXED22": null, + "CLK_BUFG_BOT_R_CK_MUXED23": null, + "CLK_BUFG_BOT_R_CK_MUXED24": null, + "CLK_BUFG_BOT_R_CK_MUXED25": null, + "CLK_BUFG_BOT_R_CK_MUXED26": null, + "CLK_BUFG_BOT_R_CK_MUXED27": null, + "CLK_BUFG_BOT_R_CK_MUXED28": null, + "CLK_BUFG_BOT_R_CK_MUXED29": null, + "CLK_BUFG_BOT_R_CK_MUXED3": null, + "CLK_BUFG_BOT_R_CK_MUXED30": null, + "CLK_BUFG_BOT_R_CK_MUXED31": null, + "CLK_BUFG_BOT_R_CK_MUXED4": null, + "CLK_BUFG_BOT_R_CK_MUXED5": null, + "CLK_BUFG_BOT_R_CK_MUXED6": null, + "CLK_BUFG_BOT_R_CK_MUXED7": null, + "CLK_BUFG_BOT_R_CK_MUXED8": null, + "CLK_BUFG_BOT_R_CK_MUXED9": null, + "CLK_BUFG_BUFGCTRL0_I0": null, + "CLK_BUFG_BUFGCTRL0_I1": null, + "CLK_BUFG_BUFGCTRL0_O": null, + "CLK_BUFG_BUFGCTRL10_I0": null, + "CLK_BUFG_BUFGCTRL10_I1": null, + "CLK_BUFG_BUFGCTRL10_O": null, + "CLK_BUFG_BUFGCTRL11_I0": null, + "CLK_BUFG_BUFGCTRL11_I1": null, + "CLK_BUFG_BUFGCTRL11_O": null, + "CLK_BUFG_BUFGCTRL12_I0": null, + "CLK_BUFG_BUFGCTRL12_I1": null, + "CLK_BUFG_BUFGCTRL12_O": null, + "CLK_BUFG_BUFGCTRL13_I0": null, + "CLK_BUFG_BUFGCTRL13_I1": null, + "CLK_BUFG_BUFGCTRL13_O": null, + "CLK_BUFG_BUFGCTRL14_I0": null, + "CLK_BUFG_BUFGCTRL14_I1": null, + "CLK_BUFG_BUFGCTRL14_O": null, + "CLK_BUFG_BUFGCTRL15_I0": null, + "CLK_BUFG_BUFGCTRL15_I1": null, + "CLK_BUFG_BUFGCTRL15_O": null, + "CLK_BUFG_BUFGCTRL1_I0": null, + "CLK_BUFG_BUFGCTRL1_I1": null, + "CLK_BUFG_BUFGCTRL1_O": null, + "CLK_BUFG_BUFGCTRL2_I0": null, + "CLK_BUFG_BUFGCTRL2_I1": null, + "CLK_BUFG_BUFGCTRL2_O": null, + "CLK_BUFG_BUFGCTRL3_I0": null, + "CLK_BUFG_BUFGCTRL3_I1": null, + "CLK_BUFG_BUFGCTRL3_O": null, + "CLK_BUFG_BUFGCTRL4_I0": null, + "CLK_BUFG_BUFGCTRL4_I1": null, + "CLK_BUFG_BUFGCTRL4_O": null, + "CLK_BUFG_BUFGCTRL5_I0": null, + "CLK_BUFG_BUFGCTRL5_I1": null, + "CLK_BUFG_BUFGCTRL5_O": null, + "CLK_BUFG_BUFGCTRL6_I0": null, + "CLK_BUFG_BUFGCTRL6_I1": null, + "CLK_BUFG_BUFGCTRL6_O": null, + "CLK_BUFG_BUFGCTRL7_I0": null, + "CLK_BUFG_BUFGCTRL7_I1": null, + "CLK_BUFG_BUFGCTRL7_O": null, + "CLK_BUFG_BUFGCTRL8_I0": null, + "CLK_BUFG_BUFGCTRL8_I1": null, + "CLK_BUFG_BUFGCTRL8_O": null, + "CLK_BUFG_BUFGCTRL9_I0": null, + "CLK_BUFG_BUFGCTRL9_I1": null, + "CLK_BUFG_BUFGCTRL9_O": null, + "CLK_BUFG_CK_GCLK0": null, + "CLK_BUFG_CK_GCLK1": null, + "CLK_BUFG_CK_GCLK10": null, + "CLK_BUFG_CK_GCLK11": null, + "CLK_BUFG_CK_GCLK12": null, + "CLK_BUFG_CK_GCLK13": null, + "CLK_BUFG_CK_GCLK14": null, + "CLK_BUFG_CK_GCLK15": null, + "CLK_BUFG_CK_GCLK16": null, + "CLK_BUFG_CK_GCLK17": null, + "CLK_BUFG_CK_GCLK18": null, + "CLK_BUFG_CK_GCLK19": null, + "CLK_BUFG_CK_GCLK2": null, + "CLK_BUFG_CK_GCLK20": null, + "CLK_BUFG_CK_GCLK21": null, + "CLK_BUFG_CK_GCLK22": null, + "CLK_BUFG_CK_GCLK23": null, + "CLK_BUFG_CK_GCLK24": null, + "CLK_BUFG_CK_GCLK25": null, + "CLK_BUFG_CK_GCLK26": null, + "CLK_BUFG_CK_GCLK27": null, + "CLK_BUFG_CK_GCLK28": null, + "CLK_BUFG_CK_GCLK29": null, + "CLK_BUFG_CK_GCLK3": null, + "CLK_BUFG_CK_GCLK30": null, + "CLK_BUFG_CK_GCLK31": null, + "CLK_BUFG_CK_GCLK4": null, + "CLK_BUFG_CK_GCLK5": null, + "CLK_BUFG_CK_GCLK6": null, + "CLK_BUFG_CK_GCLK7": null, + "CLK_BUFG_CK_GCLK8": null, + "CLK_BUFG_CK_GCLK9": null, + "CLK_BUFG_IMUX0_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX0_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX0_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX0_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_2": { + "cap": "28.208", + "res": "0.000" + }, + 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"CLK_BUFG_R_BUFGCTRL10_CE0": null, + "CLK_BUFG_R_BUFGCTRL10_CE1": null, + "CLK_BUFG_R_BUFGCTRL10_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL10_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL10_S0": null, + "CLK_BUFG_R_BUFGCTRL10_S1": null, + "CLK_BUFG_R_BUFGCTRL11_CE0": null, + "CLK_BUFG_R_BUFGCTRL11_CE1": null, + "CLK_BUFG_R_BUFGCTRL11_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL11_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL11_S0": null, + "CLK_BUFG_R_BUFGCTRL11_S1": null, + "CLK_BUFG_R_BUFGCTRL12_CE0": null, + "CLK_BUFG_R_BUFGCTRL12_CE1": null, + "CLK_BUFG_R_BUFGCTRL12_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL12_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL12_S0": null, + "CLK_BUFG_R_BUFGCTRL12_S1": null, + "CLK_BUFG_R_BUFGCTRL13_CE0": null, + "CLK_BUFG_R_BUFGCTRL13_CE1": null, + "CLK_BUFG_R_BUFGCTRL13_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL13_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL13_S0": null, + "CLK_BUFG_R_BUFGCTRL13_S1": null, + "CLK_BUFG_R_BUFGCTRL14_CE0": null, + "CLK_BUFG_R_BUFGCTRL14_CE1": null, + "CLK_BUFG_R_BUFGCTRL14_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL14_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL14_S0": null, + "CLK_BUFG_R_BUFGCTRL14_S1": null, + "CLK_BUFG_R_BUFGCTRL15_CE0": null, + "CLK_BUFG_R_BUFGCTRL15_CE1": null, + "CLK_BUFG_R_BUFGCTRL15_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL15_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL15_S0": null, + "CLK_BUFG_R_BUFGCTRL15_S1": null, + "CLK_BUFG_R_BUFGCTRL1_CE0": null, + "CLK_BUFG_R_BUFGCTRL1_CE1": null, + "CLK_BUFG_R_BUFGCTRL1_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL1_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL1_S0": null, + "CLK_BUFG_R_BUFGCTRL1_S1": null, + "CLK_BUFG_R_BUFGCTRL2_CE0": null, + "CLK_BUFG_R_BUFGCTRL2_CE1": null, + "CLK_BUFG_R_BUFGCTRL2_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL2_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL2_S0": null, + "CLK_BUFG_R_BUFGCTRL2_S1": null, + "CLK_BUFG_R_BUFGCTRL3_CE0": null, + "CLK_BUFG_R_BUFGCTRL3_CE1": null, + "CLK_BUFG_R_BUFGCTRL3_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL3_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL3_S0": null, + "CLK_BUFG_R_BUFGCTRL3_S1": null, + "CLK_BUFG_R_BUFGCTRL4_CE0": null, + "CLK_BUFG_R_BUFGCTRL4_CE1": null, + "CLK_BUFG_R_BUFGCTRL4_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL4_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL4_S0": null, + "CLK_BUFG_R_BUFGCTRL4_S1": null, + "CLK_BUFG_R_BUFGCTRL5_CE0": null, + "CLK_BUFG_R_BUFGCTRL5_CE1": null, + "CLK_BUFG_R_BUFGCTRL5_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL5_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL5_S0": null, + "CLK_BUFG_R_BUFGCTRL5_S1": null, + "CLK_BUFG_R_BUFGCTRL6_CE0": null, + "CLK_BUFG_R_BUFGCTRL6_CE1": null, + "CLK_BUFG_R_BUFGCTRL6_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL6_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL6_S0": null, + "CLK_BUFG_R_BUFGCTRL6_S1": null, + "CLK_BUFG_R_BUFGCTRL7_CE0": null, + "CLK_BUFG_R_BUFGCTRL7_CE1": null, + "CLK_BUFG_R_BUFGCTRL7_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL7_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL7_S0": null, + "CLK_BUFG_R_BUFGCTRL7_S1": null, + "CLK_BUFG_R_BUFGCTRL8_CE0": null, + "CLK_BUFG_R_BUFGCTRL8_CE1": null, + "CLK_BUFG_R_BUFGCTRL8_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL8_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL8_S0": null, + "CLK_BUFG_R_BUFGCTRL8_S1": null, + "CLK_BUFG_R_BUFGCTRL9_CE0": null, + "CLK_BUFG_R_BUFGCTRL9_CE1": null, + "CLK_BUFG_R_BUFGCTRL9_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL9_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL9_S0": null, + "CLK_BUFG_R_BUFGCTRL9_S1": null, + "CLK_BUFG_R_CK_FB_TEST0_0": null, + "CLK_BUFG_R_CK_FB_TEST0_1": null, + "CLK_BUFG_R_CK_FB_TEST0_10": null, + "CLK_BUFG_R_CK_FB_TEST0_11": null, + "CLK_BUFG_R_CK_FB_TEST0_12": null, + "CLK_BUFG_R_CK_FB_TEST0_13": null, + "CLK_BUFG_R_CK_FB_TEST0_14": null, + "CLK_BUFG_R_CK_FB_TEST0_15": null, + "CLK_BUFG_R_CK_FB_TEST0_2": null, + "CLK_BUFG_R_CK_FB_TEST0_3": null, + "CLK_BUFG_R_CK_FB_TEST0_4": null, + "CLK_BUFG_R_CK_FB_TEST0_5": null, + "CLK_BUFG_R_CK_FB_TEST0_6": null, + "CLK_BUFG_R_CK_FB_TEST0_7": null, + "CLK_BUFG_R_CK_FB_TEST0_8": null, + "CLK_BUFG_R_CK_FB_TEST0_9": null, + "CLK_BUFG_R_CK_FB_TEST1_0": null, + "CLK_BUFG_R_CK_FB_TEST1_1": null, + "CLK_BUFG_R_CK_FB_TEST1_10": null, + "CLK_BUFG_R_CK_FB_TEST1_11": null, + "CLK_BUFG_R_CK_FB_TEST1_12": null, + "CLK_BUFG_R_CK_FB_TEST1_13": null, + "CLK_BUFG_R_CK_FB_TEST1_14": null, + "CLK_BUFG_R_CK_FB_TEST1_15": null, + "CLK_BUFG_R_CK_FB_TEST1_2": null, + "CLK_BUFG_R_CK_FB_TEST1_3": null, + "CLK_BUFG_R_CK_FB_TEST1_4": null, + "CLK_BUFG_R_CK_FB_TEST1_5": null, + "CLK_BUFG_R_CK_FB_TEST1_6": null, + "CLK_BUFG_R_CK_FB_TEST1_7": null, + "CLK_BUFG_R_CK_FB_TEST1_8": null, + "CLK_BUFG_R_CK_FB_TEST1_9": null, + "CLK_BUFG_R_FBG_OUT0": null, + "CLK_BUFG_R_FBG_OUT1": null, + "CLK_BUFG_R_FBG_OUT10": null, + "CLK_BUFG_R_FBG_OUT11": null, + "CLK_BUFG_R_FBG_OUT12": null, + "CLK_BUFG_R_FBG_OUT13": null, + "CLK_BUFG_R_FBG_OUT14": null, + "CLK_BUFG_R_FBG_OUT15": null, + "CLK_BUFG_R_FBG_OUT2": null, + "CLK_BUFG_R_FBG_OUT3": null, + "CLK_BUFG_R_FBG_OUT4": null, + "CLK_BUFG_R_FBG_OUT5": null, + "CLK_BUFG_R_FBG_OUT6": null, + "CLK_BUFG_R_FBG_OUT7": null, + "CLK_BUFG_R_FBG_OUT8": null, + "CLK_BUFG_R_FBG_OUT9": null, + "CLK_HROW_BLOCK_OUTS_B0_0": null, + "CLK_HROW_BLOCK_OUTS_B0_1": null, + "CLK_HROW_BLOCK_OUTS_B0_2": null, + "CLK_HROW_BLOCK_OUTS_B0_3": null, + "CLK_HROW_BLOCK_OUTS_B1_0": null, + "CLK_HROW_BLOCK_OUTS_B1_1": null, + "CLK_HROW_BLOCK_OUTS_B1_2": null, + "CLK_HROW_BLOCK_OUTS_B1_3": null, + "CLK_HROW_BLOCK_OUTS_B2_0": null, + "CLK_HROW_BLOCK_OUTS_B2_1": null, + "CLK_HROW_BLOCK_OUTS_B2_2": null, + "CLK_HROW_BLOCK_OUTS_B2_3": null, + "CLK_HROW_BLOCK_OUTS_B3_0": null, + "CLK_HROW_BLOCK_OUTS_B3_1": null, + "CLK_HROW_BLOCK_OUTS_B3_2": null, + "CLK_HROW_BLOCK_OUTS_B3_3": null, + "CLK_HROW_BYP0_0": null, + "CLK_HROW_BYP0_1": null, + "CLK_HROW_BYP0_2": null, + "CLK_HROW_BYP0_3": null, + "CLK_HROW_BYP1_0": null, + "CLK_HROW_BYP1_1": null, + "CLK_HROW_BYP1_2": null, + "CLK_HROW_BYP1_3": null, + "CLK_HROW_BYP2_0": null, + "CLK_HROW_BYP2_1": null, + "CLK_HROW_BYP2_2": null, + "CLK_HROW_BYP2_3": null, + "CLK_HROW_BYP3_0": null, + "CLK_HROW_BYP3_1": null, + "CLK_HROW_BYP3_2": null, + "CLK_HROW_BYP3_3": null, + "CLK_HROW_BYP4_0": null, + "CLK_HROW_BYP4_1": null, + "CLK_HROW_BYP4_2": null, + "CLK_HROW_BYP4_3": null, + "CLK_HROW_BYP5_0": null, + "CLK_HROW_BYP5_1": null, + "CLK_HROW_BYP5_2": null, + "CLK_HROW_BYP5_3": null, + "CLK_HROW_BYP6_0": null, + "CLK_HROW_BYP6_1": null, + "CLK_HROW_BYP6_2": null, + "CLK_HROW_BYP6_3": null, + "CLK_HROW_BYP7_0": null, + "CLK_HROW_BYP7_1": null, + "CLK_HROW_BYP7_2": null, + "CLK_HROW_BYP7_3": null, + "CLK_HROW_CLK0_0": { + "cap": "12.362", + "res": "0.000" + }, + "CLK_HROW_CLK0_1": { + "cap": "12.362", + "res": "0.000" + }, + "CLK_HROW_CLK0_2": { + "cap": "12.362", + "res": "0.000" + }, + "CLK_HROW_CLK0_3": { + "cap": "12.362", + "res": "0.000" + }, + "CLK_HROW_CLK1_0": { + "cap": "12.362", + "res": "0.000" + }, + "CLK_HROW_CLK1_1": { + "cap": "12.362", + "res": "0.000" + }, + "CLK_HROW_CLK1_2": { + "cap": "12.362", + "res": "0.000" + }, + "CLK_HROW_CLK1_3": { + "cap": "12.362", + "res": "0.000" + }, + "CLK_HROW_CTRL0_0": null, + "CLK_HROW_CTRL0_1": null, + "CLK_HROW_CTRL0_2": null, + "CLK_HROW_CTRL0_3": null, + "CLK_HROW_CTRL1_0": null, + "CLK_HROW_CTRL1_1": null, + "CLK_HROW_CTRL1_2": null, + "CLK_HROW_CTRL1_3": null, + "CLK_HROW_EE2A0_0": null, + "CLK_HROW_EE2A0_1": null, + "CLK_HROW_EE2A0_2": null, + "CLK_HROW_EE2A0_3": null, + "CLK_HROW_EE2A1_0": null, + "CLK_HROW_EE2A1_1": null, + "CLK_HROW_EE2A1_2": null, + "CLK_HROW_EE2A1_3": null, + "CLK_HROW_EE2A2_0": null, + "CLK_HROW_EE2A2_1": null, + "CLK_HROW_EE2A2_2": null, + "CLK_HROW_EE2A2_3": null, + "CLK_HROW_EE2A3_0": null, + "CLK_HROW_EE2A3_1": null, + "CLK_HROW_EE2A3_2": null, + "CLK_HROW_EE2A3_3": null, + "CLK_HROW_EE2BEG0_0": null, + "CLK_HROW_EE2BEG0_1": null, + "CLK_HROW_EE2BEG0_2": null, + "CLK_HROW_EE2BEG0_3": null, + "CLK_HROW_EE2BEG1_0": null, + "CLK_HROW_EE2BEG1_1": null, + "CLK_HROW_EE2BEG1_2": null, + "CLK_HROW_EE2BEG1_3": null, + "CLK_HROW_EE2BEG2_0": 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+ "CLK_HROW_EE4B3_0": null, + "CLK_HROW_EE4B3_1": null, + "CLK_HROW_EE4B3_2": null, + "CLK_HROW_EE4B3_3": null, + "CLK_HROW_EE4BEG0_0": null, + "CLK_HROW_EE4BEG0_1": null, + "CLK_HROW_EE4BEG0_2": null, + "CLK_HROW_EE4BEG0_3": null, + "CLK_HROW_EE4BEG1_0": null, + "CLK_HROW_EE4BEG1_1": null, + "CLK_HROW_EE4BEG1_2": null, + "CLK_HROW_EE4BEG1_3": null, + "CLK_HROW_EE4BEG2_0": null, + "CLK_HROW_EE4BEG2_1": null, + "CLK_HROW_EE4BEG2_2": null, + "CLK_HROW_EE4BEG2_3": null, + "CLK_HROW_EE4BEG3_0": null, + "CLK_HROW_EE4BEG3_1": null, + "CLK_HROW_EE4BEG3_2": null, + "CLK_HROW_EE4BEG3_3": null, + "CLK_HROW_EE4C0_0": null, + "CLK_HROW_EE4C0_1": null, + "CLK_HROW_EE4C0_2": null, + "CLK_HROW_EE4C0_3": null, + "CLK_HROW_EE4C1_0": null, + "CLK_HROW_EE4C1_1": null, + "CLK_HROW_EE4C1_2": null, + "CLK_HROW_EE4C1_3": null, + "CLK_HROW_EE4C2_0": null, + "CLK_HROW_EE4C2_1": null, + "CLK_HROW_EE4C2_2": null, + "CLK_HROW_EE4C2_3": null, + "CLK_HROW_EE4C3_0": null, + "CLK_HROW_EE4C3_1": null, + "CLK_HROW_EE4C3_2": null, + "CLK_HROW_EE4C3_3": null, + "CLK_HROW_EL1BEG0_0": null, + "CLK_HROW_EL1BEG0_1": null, + "CLK_HROW_EL1BEG0_2": null, + "CLK_HROW_EL1BEG0_3": null, + "CLK_HROW_EL1BEG1_0": null, + "CLK_HROW_EL1BEG1_1": null, + "CLK_HROW_EL1BEG1_2": null, + "CLK_HROW_EL1BEG1_3": null, + "CLK_HROW_EL1BEG2_0": null, + "CLK_HROW_EL1BEG2_1": null, + "CLK_HROW_EL1BEG2_2": null, + "CLK_HROW_EL1BEG2_3": null, + "CLK_HROW_EL1BEG3_0": null, + "CLK_HROW_EL1BEG3_1": null, + "CLK_HROW_EL1BEG3_2": null, + "CLK_HROW_EL1BEG3_3": null, + "CLK_HROW_ER1BEG0_0": null, + "CLK_HROW_ER1BEG0_1": null, + "CLK_HROW_ER1BEG0_2": null, + "CLK_HROW_ER1BEG0_3": null, + "CLK_HROW_ER1BEG1_0": null, + "CLK_HROW_ER1BEG1_1": null, + "CLK_HROW_ER1BEG1_2": null, + "CLK_HROW_ER1BEG1_3": null, + "CLK_HROW_ER1BEG2_0": null, + "CLK_HROW_ER1BEG2_1": null, + "CLK_HROW_ER1BEG2_2": null, + "CLK_HROW_ER1BEG2_3": null, + "CLK_HROW_ER1BEG3_0": null, + "CLK_HROW_ER1BEG3_1": null, + "CLK_HROW_ER1BEG3_2": null, + "CLK_HROW_ER1BEG3_3": null, + "CLK_HROW_FAN0_0": null, + "CLK_HROW_FAN0_1": null, + "CLK_HROW_FAN0_2": null, + "CLK_HROW_FAN0_3": null, + "CLK_HROW_FAN1_0": null, + "CLK_HROW_FAN1_1": null, + "CLK_HROW_FAN1_2": null, + "CLK_HROW_FAN1_3": null, + "CLK_HROW_FAN2_0": null, + "CLK_HROW_FAN2_1": null, + "CLK_HROW_FAN2_2": null, + "CLK_HROW_FAN2_3": null, + "CLK_HROW_FAN3_0": null, + "CLK_HROW_FAN3_1": null, + "CLK_HROW_FAN3_2": null, + "CLK_HROW_FAN3_3": null, + "CLK_HROW_FAN4_0": null, + "CLK_HROW_FAN4_1": null, + "CLK_HROW_FAN4_2": null, + "CLK_HROW_FAN4_3": null, + "CLK_HROW_FAN5_0": null, + "CLK_HROW_FAN5_1": null, + "CLK_HROW_FAN5_2": null, + "CLK_HROW_FAN5_3": null, + "CLK_HROW_FAN6_0": null, + "CLK_HROW_FAN6_1": null, + "CLK_HROW_FAN6_2": null, + "CLK_HROW_FAN6_3": null, + "CLK_HROW_FAN7_0": null, + "CLK_HROW_FAN7_1": null, + "CLK_HROW_FAN7_2": null, + "CLK_HROW_FAN7_3": null, + "CLK_HROW_LH10_0": null, + "CLK_HROW_LH10_1": null, + "CLK_HROW_LH10_2": null, + "CLK_HROW_LH10_3": null, + "CLK_HROW_LH11_0": null, + "CLK_HROW_LH11_1": null, + "CLK_HROW_LH11_2": null, + "CLK_HROW_LH11_3": null, + "CLK_HROW_LH12_0": null, + "CLK_HROW_LH12_1": null, + "CLK_HROW_LH12_2": null, + "CLK_HROW_LH12_3": null, + "CLK_HROW_LH1_0": null, + "CLK_HROW_LH1_1": null, + "CLK_HROW_LH1_2": null, + "CLK_HROW_LH1_3": null, + "CLK_HROW_LH2_0": null, + "CLK_HROW_LH2_1": null, + "CLK_HROW_LH2_2": null, + "CLK_HROW_LH2_3": null, + "CLK_HROW_LH3_0": null, + "CLK_HROW_LH3_1": null, + "CLK_HROW_LH3_2": null, + "CLK_HROW_LH3_3": null, + "CLK_HROW_LH4_0": null, + "CLK_HROW_LH4_1": null, + "CLK_HROW_LH4_2": null, + "CLK_HROW_LH4_3": null, + "CLK_HROW_LH5_0": null, + "CLK_HROW_LH5_1": null, + "CLK_HROW_LH5_2": null, + "CLK_HROW_LH5_3": null, + "CLK_HROW_LH6_0": null, + "CLK_HROW_LH6_1": null, + "CLK_HROW_LH6_2": null, + "CLK_HROW_LH6_3": null, + "CLK_HROW_LH7_0": null, + "CLK_HROW_LH7_1": null, + "CLK_HROW_LH7_2": null, + "CLK_HROW_LH7_3": null, + "CLK_HROW_LH8_0": null, + "CLK_HROW_LH8_1": null, + "CLK_HROW_LH8_2": null, + "CLK_HROW_LH8_3": null, + "CLK_HROW_LH9_0": null, + "CLK_HROW_LH9_1": null, + "CLK_HROW_LH9_2": null, + "CLK_HROW_LH9_3": null, + "CLK_HROW_MONITOR_N_0": null, + "CLK_HROW_MONITOR_N_1": null, + "CLK_HROW_MONITOR_N_2": null, + "CLK_HROW_MONITOR_N_3": null, + "CLK_HROW_MONITOR_P_0": null, + "CLK_HROW_MONITOR_P_1": null, + "CLK_HROW_MONITOR_P_2": null, + "CLK_HROW_MONITOR_P_3": null, + "CLK_HROW_NE2A0_0": null, + "CLK_HROW_NE2A0_1": null, + "CLK_HROW_NE2A0_2": null, + "CLK_HROW_NE2A0_3": null, + "CLK_HROW_NE2A1_0": null, + "CLK_HROW_NE2A1_1": null, + "CLK_HROW_NE2A1_2": null, + "CLK_HROW_NE2A1_3": null, + "CLK_HROW_NE2A2_0": null, + "CLK_HROW_NE2A2_1": null, + "CLK_HROW_NE2A2_2": null, + "CLK_HROW_NE2A2_3": null, + "CLK_HROW_NE2A3_0": null, + "CLK_HROW_NE2A3_1": null, + "CLK_HROW_NE2A3_2": null, + "CLK_HROW_NE2A3_3": null, + "CLK_HROW_NE4BEG0_0": null, + "CLK_HROW_NE4BEG0_1": null, + "CLK_HROW_NE4BEG0_2": null, + "CLK_HROW_NE4BEG0_3": null, + "CLK_HROW_NE4BEG1_0": null, + "CLK_HROW_NE4BEG1_1": null, + "CLK_HROW_NE4BEG1_2": null, + "CLK_HROW_NE4BEG1_3": null, + "CLK_HROW_NE4BEG2_0": null, + "CLK_HROW_NE4BEG2_1": null, + "CLK_HROW_NE4BEG2_2": null, + "CLK_HROW_NE4BEG2_3": null, + "CLK_HROW_NE4BEG3_0": null, + "CLK_HROW_NE4BEG3_1": null, + "CLK_HROW_NE4BEG3_2": null, + "CLK_HROW_NE4BEG3_3": null, + "CLK_HROW_NE4C0_0": null, + "CLK_HROW_NE4C0_1": null, + "CLK_HROW_NE4C0_2": null, + "CLK_HROW_NE4C0_3": null, + "CLK_HROW_NE4C1_0": null, + "CLK_HROW_NE4C1_1": null, + "CLK_HROW_NE4C1_2": null, + "CLK_HROW_NE4C1_3": null, + "CLK_HROW_NE4C2_0": null, + "CLK_HROW_NE4C2_1": null, + "CLK_HROW_NE4C2_2": null, + "CLK_HROW_NE4C2_3": null, + "CLK_HROW_NE4C3_0": null, + "CLK_HROW_NE4C3_1": null, + "CLK_HROW_NE4C3_2": null, + "CLK_HROW_NE4C3_3": null, + "CLK_HROW_NW2A0_0": null, + "CLK_HROW_NW2A0_1": null, + "CLK_HROW_NW2A0_2": null, + "CLK_HROW_NW2A0_3": null, + "CLK_HROW_NW2A1_0": null, + "CLK_HROW_NW2A1_1": null, + "CLK_HROW_NW2A1_2": null, + "CLK_HROW_NW2A1_3": null, + "CLK_HROW_NW2A2_0": null, + "CLK_HROW_NW2A2_1": null, + "CLK_HROW_NW2A2_2": null, + "CLK_HROW_NW2A2_3": null, + "CLK_HROW_NW2A3_0": null, + "CLK_HROW_NW2A3_1": null, + "CLK_HROW_NW2A3_2": null, + "CLK_HROW_NW2A3_3": null, + "CLK_HROW_NW4A0_0": null, + "CLK_HROW_NW4A0_1": null, + "CLK_HROW_NW4A0_2": null, + "CLK_HROW_NW4A0_3": null, + "CLK_HROW_NW4A1_0": null, + "CLK_HROW_NW4A1_1": null, + "CLK_HROW_NW4A1_2": null, + "CLK_HROW_NW4A1_3": null, + "CLK_HROW_NW4A2_0": null, + "CLK_HROW_NW4A2_1": null, + "CLK_HROW_NW4A2_2": null, + "CLK_HROW_NW4A2_3": null, + "CLK_HROW_NW4A3_0": null, + "CLK_HROW_NW4A3_1": null, + "CLK_HROW_NW4A3_2": null, + "CLK_HROW_NW4A3_3": null, + "CLK_HROW_NW4END0_0": null, + "CLK_HROW_NW4END0_1": null, + "CLK_HROW_NW4END0_2": null, + "CLK_HROW_NW4END0_3": null, + "CLK_HROW_NW4END1_0": null, + "CLK_HROW_NW4END1_1": null, + "CLK_HROW_NW4END1_2": null, + "CLK_HROW_NW4END1_3": null, + "CLK_HROW_NW4END2_0": null, + "CLK_HROW_NW4END2_1": null, + "CLK_HROW_NW4END2_2": null, + "CLK_HROW_NW4END2_3": null, + "CLK_HROW_NW4END3_0": null, + "CLK_HROW_NW4END3_1": null, + "CLK_HROW_NW4END3_2": null, + "CLK_HROW_NW4END3_3": null, + "CLK_HROW_SE2A0_0": null, + "CLK_HROW_SE2A0_1": null, + "CLK_HROW_SE2A0_2": null, + "CLK_HROW_SE2A0_3": null, + "CLK_HROW_SE2A1_0": null, + "CLK_HROW_SE2A1_1": null, + "CLK_HROW_SE2A1_2": null, + "CLK_HROW_SE2A1_3": null, + "CLK_HROW_SE2A2_0": null, + "CLK_HROW_SE2A2_1": null, + "CLK_HROW_SE2A2_2": null, + "CLK_HROW_SE2A2_3": null, + "CLK_HROW_SE2A3_0": null, + "CLK_HROW_SE2A3_1": null, + "CLK_HROW_SE2A3_2": null, + "CLK_HROW_SE2A3_3": null, + "CLK_HROW_SE4BEG0_0": null, + "CLK_HROW_SE4BEG0_1": null, + "CLK_HROW_SE4BEG0_2": null, + "CLK_HROW_SE4BEG0_3": null, + "CLK_HROW_SE4BEG1_0": null, + "CLK_HROW_SE4BEG1_1": null, + "CLK_HROW_SE4BEG1_2": null, + "CLK_HROW_SE4BEG1_3": null, + "CLK_HROW_SE4BEG2_0": null, + "CLK_HROW_SE4BEG2_1": null, + "CLK_HROW_SE4BEG2_2": null, + "CLK_HROW_SE4BEG2_3": null, + "CLK_HROW_SE4BEG3_0": null, + "CLK_HROW_SE4BEG3_1": null, + "CLK_HROW_SE4BEG3_2": null, + "CLK_HROW_SE4BEG3_3": null, + "CLK_HROW_SE4C0_0": null, + "CLK_HROW_SE4C0_1": null, + "CLK_HROW_SE4C0_2": null, + "CLK_HROW_SE4C0_3": null, + "CLK_HROW_SE4C1_0": null, + "CLK_HROW_SE4C1_1": null, + "CLK_HROW_SE4C1_2": null, + "CLK_HROW_SE4C1_3": null, + "CLK_HROW_SE4C2_0": null, + "CLK_HROW_SE4C2_1": null, + "CLK_HROW_SE4C2_2": null, + "CLK_HROW_SE4C2_3": null, + "CLK_HROW_SE4C3_0": null, + "CLK_HROW_SE4C3_1": null, + "CLK_HROW_SE4C3_2": null, + "CLK_HROW_SE4C3_3": null, + "CLK_HROW_SW2A0_0": null, + "CLK_HROW_SW2A0_1": null, + "CLK_HROW_SW2A0_2": null, + "CLK_HROW_SW2A0_3": null, + "CLK_HROW_SW2A1_0": null, + "CLK_HROW_SW2A1_1": null, + "CLK_HROW_SW2A1_2": null, + "CLK_HROW_SW2A1_3": null, + "CLK_HROW_SW2A2_0": null, + "CLK_HROW_SW2A2_1": null, + "CLK_HROW_SW2A2_2": null, + "CLK_HROW_SW2A2_3": null, + "CLK_HROW_SW2A3_0": null, + "CLK_HROW_SW2A3_1": null, + "CLK_HROW_SW2A3_2": null, + "CLK_HROW_SW2A3_3": null, + "CLK_HROW_SW4A0_0": null, + "CLK_HROW_SW4A0_1": null, + "CLK_HROW_SW4A0_2": null, + "CLK_HROW_SW4A0_3": null, + "CLK_HROW_SW4A1_0": null, + "CLK_HROW_SW4A1_1": null, + "CLK_HROW_SW4A1_2": null, + "CLK_HROW_SW4A1_3": null, + "CLK_HROW_SW4A2_0": null, + "CLK_HROW_SW4A2_1": null, + "CLK_HROW_SW4A2_2": null, + "CLK_HROW_SW4A2_3": null, + "CLK_HROW_SW4A3_0": null, + "CLK_HROW_SW4A3_1": null, + "CLK_HROW_SW4A3_2": null, + "CLK_HROW_SW4A3_3": null, + "CLK_HROW_SW4END0_0": null, + "CLK_HROW_SW4END0_1": null, + "CLK_HROW_SW4END0_2": null, + "CLK_HROW_SW4END0_3": null, + "CLK_HROW_SW4END1_0": null, + "CLK_HROW_SW4END1_1": null, + "CLK_HROW_SW4END1_2": null, + "CLK_HROW_SW4END1_3": null, + "CLK_HROW_SW4END2_0": null, + "CLK_HROW_SW4END2_1": null, + "CLK_HROW_SW4END2_2": null, + "CLK_HROW_SW4END2_3": null, + "CLK_HROW_SW4END3_0": null, + "CLK_HROW_SW4END3_1": null, + "CLK_HROW_SW4END3_2": null, + "CLK_HROW_SW4END3_3": null, + "CLK_HROW_WL1END0_0": null, + "CLK_HROW_WL1END0_1": null, + "CLK_HROW_WL1END0_2": null, + "CLK_HROW_WL1END0_3": null, + "CLK_HROW_WL1END1_0": null, + "CLK_HROW_WL1END1_1": null, + "CLK_HROW_WL1END1_2": null, + "CLK_HROW_WL1END1_3": null, + "CLK_HROW_WL1END2_0": null, + "CLK_HROW_WL1END2_1": null, + "CLK_HROW_WL1END2_2": null, + "CLK_HROW_WL1END2_3": null, + "CLK_HROW_WL1END3_0": null, + "CLK_HROW_WL1END3_1": null, + "CLK_HROW_WL1END3_2": null, + "CLK_HROW_WL1END3_3": null, + "CLK_HROW_WR1END0_0": null, + "CLK_HROW_WR1END0_1": null, + "CLK_HROW_WR1END0_2": null, + "CLK_HROW_WR1END0_3": null, + "CLK_HROW_WR1END1_0": null, + "CLK_HROW_WR1END1_1": null, + "CLK_HROW_WR1END1_2": null, + "CLK_HROW_WR1END1_3": null, + "CLK_HROW_WR1END2_0": null, + "CLK_HROW_WR1END2_1": null, + "CLK_HROW_WR1END2_2": null, + "CLK_HROW_WR1END2_3": null, + "CLK_HROW_WR1END3_0": null, + "CLK_HROW_WR1END3_1": null, + "CLK_HROW_WR1END3_2": null, + "CLK_HROW_WR1END3_3": null, + "CLK_HROW_WW2A0_0": null, + "CLK_HROW_WW2A0_1": null, + "CLK_HROW_WW2A0_2": null, + "CLK_HROW_WW2A0_3": null, + "CLK_HROW_WW2A1_0": null, + "CLK_HROW_WW2A1_1": null, + "CLK_HROW_WW2A1_2": null, + "CLK_HROW_WW2A1_3": null, + "CLK_HROW_WW2A2_0": null, + "CLK_HROW_WW2A2_1": null, + "CLK_HROW_WW2A2_2": null, + "CLK_HROW_WW2A2_3": null, + "CLK_HROW_WW2A3_0": null, + "CLK_HROW_WW2A3_1": null, + "CLK_HROW_WW2A3_2": null, + "CLK_HROW_WW2A3_3": null, + "CLK_HROW_WW2END0_0": null, + "CLK_HROW_WW2END0_1": null, + "CLK_HROW_WW2END0_2": null, + "CLK_HROW_WW2END0_3": null, + "CLK_HROW_WW2END1_0": null, + "CLK_HROW_WW2END1_1": null, + "CLK_HROW_WW2END1_2": null, + "CLK_HROW_WW2END1_3": null, + "CLK_HROW_WW2END2_0": null, + "CLK_HROW_WW2END2_1": null, + "CLK_HROW_WW2END2_2": null, + "CLK_HROW_WW2END2_3": null, + "CLK_HROW_WW2END3_0": null, + "CLK_HROW_WW2END3_1": null, + "CLK_HROW_WW2END3_2": null, + "CLK_HROW_WW2END3_3": null, + "CLK_HROW_WW4A0_0": null, + "CLK_HROW_WW4A0_1": null, + "CLK_HROW_WW4A0_2": null, + "CLK_HROW_WW4A0_3": null, + "CLK_HROW_WW4A1_0": null, + "CLK_HROW_WW4A1_1": null, + "CLK_HROW_WW4A1_2": null, + "CLK_HROW_WW4A1_3": null, + "CLK_HROW_WW4A2_0": null, + "CLK_HROW_WW4A2_1": null, + "CLK_HROW_WW4A2_2": null, + "CLK_HROW_WW4A2_3": null, + "CLK_HROW_WW4A3_0": null, + "CLK_HROW_WW4A3_1": null, + "CLK_HROW_WW4A3_2": null, + "CLK_HROW_WW4A3_3": null, + "CLK_HROW_WW4B0_0": null, + "CLK_HROW_WW4B0_1": null, + "CLK_HROW_WW4B0_2": null, + "CLK_HROW_WW4B0_3": null, + "CLK_HROW_WW4B1_0": null, + "CLK_HROW_WW4B1_1": null, + "CLK_HROW_WW4B1_2": null, + "CLK_HROW_WW4B1_3": null, + "CLK_HROW_WW4B2_0": null, + "CLK_HROW_WW4B2_1": null, + "CLK_HROW_WW4B2_2": null, + "CLK_HROW_WW4B2_3": null, + "CLK_HROW_WW4B3_0": null, + "CLK_HROW_WW4B3_1": null, + "CLK_HROW_WW4B3_2": null, + "CLK_HROW_WW4B3_3": null, + "CLK_HROW_WW4C0_0": null, + "CLK_HROW_WW4C0_1": null, + "CLK_HROW_WW4C0_2": null, + "CLK_HROW_WW4C0_3": null, + "CLK_HROW_WW4C1_0": null, + "CLK_HROW_WW4C1_1": null, + "CLK_HROW_WW4C1_2": null, + "CLK_HROW_WW4C1_3": null, + "CLK_HROW_WW4C2_0": null, + "CLK_HROW_WW4C2_1": null, + "CLK_HROW_WW4C2_2": null, + "CLK_HROW_WW4C2_3": null, + "CLK_HROW_WW4C3_0": null, + "CLK_HROW_WW4C3_1": null, + "CLK_HROW_WW4C3_2": null, + "CLK_HROW_WW4C3_3": null, + "CLK_HROW_WW4END0_0": null, + "CLK_HROW_WW4END0_1": null, + "CLK_HROW_WW4END0_2": null, + "CLK_HROW_WW4END0_3": null, + "CLK_HROW_WW4END1_0": null, + "CLK_HROW_WW4END1_1": null, + "CLK_HROW_WW4END1_2": null, + "CLK_HROW_WW4END1_3": null, + "CLK_HROW_WW4END2_0": null, + "CLK_HROW_WW4END2_1": null, + "CLK_HROW_WW4END2_2": null, + "CLK_HROW_WW4END2_3": null, + "CLK_HROW_WW4END3_0": null, + "CLK_HROW_WW4END3_1": null, + "CLK_HROW_WW4END3_2": null, + "CLK_HROW_WW4END3_3": null + } } diff --git a/zynq7/tile_type_CLK_BUFG_REBUF.json b/zynq7/tile_type_CLK_BUFG_REBUF.json index 9473289..bd161eb 100644 --- a/zynq7/tile_type_CLK_BUFG_REBUF.json +++ b/zynq7/tile_type_CLK_BUFG_REBUF.json @@ -2,1187 +2,3203 @@ "pips": { "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT->>GCLK0_1_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK0_1_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK0_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT->>GCLK10_11_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK10_11_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK10_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK11_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_TOP->>GCLK11_10_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK11_10_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_BOT->>GCLK12_13_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK12_13_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK12_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK13_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_TOP->>GCLK13_12_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK13_12_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_BOT->>GCLK14_15_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK14_15_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK14_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK15_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_TOP->>GCLK15_14_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK15_14_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_BOT->>GCLK16_17_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK16_17_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK16_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK17_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_TOP->>GCLK17_16_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK17_16_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT->>GCLK18_19_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK18_19_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK18_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK19_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_TOP->>GCLK19_18_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK19_18_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK1_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_TOP->>GCLK1_0_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK1_0_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT->>GCLK20_21_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK20_21_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK20_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK21_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_TOP->>GCLK21_20_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK21_20_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_BOT->>GCLK22_23_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK22_23_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK22_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK23_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_TOP->>GCLK23_22_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK23_22_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_BOT->>GCLK24_25_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK24_25_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK24_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK25_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_TOP->>GCLK25_24_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK25_24_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_BOT->>GCLK26_27_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK26_27_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK26_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK27_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_TOP->>GCLK27_26_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK27_26_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT->>GCLK28_29_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK28_29_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK28_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK29_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_TOP->>GCLK29_28_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK29_28_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT->>GCLK2_3_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK2_3_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK2_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT->>GCLK30_31_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK30_31_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK30_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK31_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_TOP->>GCLK31_30_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK31_30_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK3_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_TOP->>GCLK3_2_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK3_2_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT->>GCLK4_5_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK4_5_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK4_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK5_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_TOP->>GCLK5_4_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK5_4_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT->>GCLK6_7_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK6_7_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK6_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK7_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_TOP->>GCLK7_6_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK7_6_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT->>GCLK8_9_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK8_9_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK8_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK9_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_TOP->>GCLK9_8_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK9_8_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_TOP" }, "CLK_BUFG_REBUF.GCLK0_1_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK1_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK0_1_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK10_11_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK11_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK10_11_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK11_10_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK10_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK11_10_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK12_13_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK13_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK12_13_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK13_12_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK12_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK13_12_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK14_15_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK15_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK14_15_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK15_14_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK14_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK15_14_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK16_17_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK17_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK16_17_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK17_16_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK16_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK17_16_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK18_19_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK19_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK18_19_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK19_18_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK18_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK19_18_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK1_0_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK0_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK1_0_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK20_21_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK21_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK20_21_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK21_20_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK20_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK21_20_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK22_23_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK23_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK22_23_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK23_22_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK22_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK23_22_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK24_25_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK25_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK24_25_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK25_24_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK24_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK25_24_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK26_27_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK27_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK26_27_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK27_26_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK26_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK27_26_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK28_29_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK29_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK28_29_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK29_28_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK28_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK29_28_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK2_3_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK3_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK2_3_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK30_31_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK31_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK30_31_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK31_30_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK30_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK31_30_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK3_2_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK2_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK3_2_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK4_5_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK5_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK4_5_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK5_4_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK4_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK5_4_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK6_7_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK7_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK6_7_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK7_6_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK6_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK7_6_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK8_9_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK9_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK8_9_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK9_8_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK8_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK9_8_UP_TEST_RING_OUT" } }, "sites": [], "tile_type": "CLK_BUFG_REBUF", - "wires": [ - "CLK_BUFG_REBUF_CK_BUFG_CASC0", - "CLK_BUFG_REBUF_CK_BUFG_CASC1", - "CLK_BUFG_REBUF_CK_BUFG_CASC10", - "CLK_BUFG_REBUF_CK_BUFG_CASC11", - "CLK_BUFG_REBUF_CK_BUFG_CASC12", - "CLK_BUFG_REBUF_CK_BUFG_CASC13", - "CLK_BUFG_REBUF_CK_BUFG_CASC14", - "CLK_BUFG_REBUF_CK_BUFG_CASC15", - "CLK_BUFG_REBUF_CK_BUFG_CASC16", - "CLK_BUFG_REBUF_CK_BUFG_CASC17", - "CLK_BUFG_REBUF_CK_BUFG_CASC18", - "CLK_BUFG_REBUF_CK_BUFG_CASC19", - "CLK_BUFG_REBUF_CK_BUFG_CASC2", - "CLK_BUFG_REBUF_CK_BUFG_CASC20", - "CLK_BUFG_REBUF_CK_BUFG_CASC21", - "CLK_BUFG_REBUF_CK_BUFG_CASC22", - "CLK_BUFG_REBUF_CK_BUFG_CASC23", - "CLK_BUFG_REBUF_CK_BUFG_CASC24", - "CLK_BUFG_REBUF_CK_BUFG_CASC25", - "CLK_BUFG_REBUF_CK_BUFG_CASC26", - "CLK_BUFG_REBUF_CK_BUFG_CASC27", - "CLK_BUFG_REBUF_CK_BUFG_CASC28", - "CLK_BUFG_REBUF_CK_BUFG_CASC29", - "CLK_BUFG_REBUF_CK_BUFG_CASC3", - "CLK_BUFG_REBUF_CK_BUFG_CASC30", - "CLK_BUFG_REBUF_CK_BUFG_CASC31", - "CLK_BUFG_REBUF_CK_BUFG_CASC4", - "CLK_BUFG_REBUF_CK_BUFG_CASC5", - "CLK_BUFG_REBUF_CK_BUFG_CASC6", - "CLK_BUFG_REBUF_CK_BUFG_CASC7", - "CLK_BUFG_REBUF_CK_BUFG_CASC8", - "CLK_BUFG_REBUF_CK_BUFG_CASC9", - "CLK_BUFG_REBUF_CK_GCLK0_BOT", - "CLK_BUFG_REBUF_CK_GCLK0_TOP", - "CLK_BUFG_REBUF_CK_GCLK10_BOT", - "CLK_BUFG_REBUF_CK_GCLK10_TOP", - "CLK_BUFG_REBUF_CK_GCLK11_BOT", - "CLK_BUFG_REBUF_CK_GCLK11_TOP", - "CLK_BUFG_REBUF_CK_GCLK12_BOT", - "CLK_BUFG_REBUF_CK_GCLK12_TOP", - "CLK_BUFG_REBUF_CK_GCLK13_BOT", - "CLK_BUFG_REBUF_CK_GCLK13_TOP", - "CLK_BUFG_REBUF_CK_GCLK14_BOT", - "CLK_BUFG_REBUF_CK_GCLK14_TOP", - "CLK_BUFG_REBUF_CK_GCLK15_BOT", - "CLK_BUFG_REBUF_CK_GCLK15_TOP", - "CLK_BUFG_REBUF_CK_GCLK16_BOT", - "CLK_BUFG_REBUF_CK_GCLK16_TOP", - "CLK_BUFG_REBUF_CK_GCLK17_BOT", - "CLK_BUFG_REBUF_CK_GCLK17_TOP", - "CLK_BUFG_REBUF_CK_GCLK18_BOT", - "CLK_BUFG_REBUF_CK_GCLK18_TOP", - "CLK_BUFG_REBUF_CK_GCLK19_BOT", - "CLK_BUFG_REBUF_CK_GCLK19_TOP", - "CLK_BUFG_REBUF_CK_GCLK1_BOT", - "CLK_BUFG_REBUF_CK_GCLK1_TOP", - "CLK_BUFG_REBUF_CK_GCLK20_BOT", - "CLK_BUFG_REBUF_CK_GCLK20_TOP", - "CLK_BUFG_REBUF_CK_GCLK21_BOT", - "CLK_BUFG_REBUF_CK_GCLK21_TOP", - "CLK_BUFG_REBUF_CK_GCLK22_BOT", - "CLK_BUFG_REBUF_CK_GCLK22_TOP", - "CLK_BUFG_REBUF_CK_GCLK23_BOT", - "CLK_BUFG_REBUF_CK_GCLK23_TOP", - "CLK_BUFG_REBUF_CK_GCLK24_BOT", - "CLK_BUFG_REBUF_CK_GCLK24_TOP", - "CLK_BUFG_REBUF_CK_GCLK25_BOT", - "CLK_BUFG_REBUF_CK_GCLK25_TOP", - "CLK_BUFG_REBUF_CK_GCLK26_BOT", - "CLK_BUFG_REBUF_CK_GCLK26_TOP", - "CLK_BUFG_REBUF_CK_GCLK27_BOT", - "CLK_BUFG_REBUF_CK_GCLK27_TOP", - "CLK_BUFG_REBUF_CK_GCLK28_BOT", - "CLK_BUFG_REBUF_CK_GCLK28_TOP", - "CLK_BUFG_REBUF_CK_GCLK29_BOT", - "CLK_BUFG_REBUF_CK_GCLK29_TOP", - "CLK_BUFG_REBUF_CK_GCLK2_BOT", - "CLK_BUFG_REBUF_CK_GCLK2_TOP", - "CLK_BUFG_REBUF_CK_GCLK30_BOT", - "CLK_BUFG_REBUF_CK_GCLK30_TOP", - "CLK_BUFG_REBUF_CK_GCLK31_BOT", - "CLK_BUFG_REBUF_CK_GCLK31_TOP", - "CLK_BUFG_REBUF_CK_GCLK3_BOT", - "CLK_BUFG_REBUF_CK_GCLK3_TOP", - "CLK_BUFG_REBUF_CK_GCLK4_BOT", - "CLK_BUFG_REBUF_CK_GCLK4_TOP", - "CLK_BUFG_REBUF_CK_GCLK5_BOT", - "CLK_BUFG_REBUF_CK_GCLK5_TOP", - "CLK_BUFG_REBUF_CK_GCLK6_BOT", - "CLK_BUFG_REBUF_CK_GCLK6_TOP", - "CLK_BUFG_REBUF_CK_GCLK7_BOT", - "CLK_BUFG_REBUF_CK_GCLK7_TOP", - "CLK_BUFG_REBUF_CK_GCLK8_BOT", - "CLK_BUFG_REBUF_CK_GCLK8_TOP", - "CLK_BUFG_REBUF_CK_GCLK9_BOT", - "CLK_BUFG_REBUF_CK_GCLK9_TOP", - "CLK_BUFG_REBUF_EE2A0_0", - "CLK_BUFG_REBUF_EE2A0_1", - "CLK_BUFG_REBUF_EE2A1_0", - "CLK_BUFG_REBUF_EE2A1_1", - "CLK_BUFG_REBUF_EE2A2_0", - "CLK_BUFG_REBUF_EE2A2_1", - "CLK_BUFG_REBUF_EE2A3_0", - "CLK_BUFG_REBUF_EE2A3_1", - "CLK_BUFG_REBUF_EE2BEG0_0", - "CLK_BUFG_REBUF_EE2BEG0_1", - "CLK_BUFG_REBUF_EE2BEG1_0", - "CLK_BUFG_REBUF_EE2BEG1_1", - "CLK_BUFG_REBUF_EE2BEG2_0", - "CLK_BUFG_REBUF_EE2BEG2_1", - "CLK_BUFG_REBUF_EE2BEG3_0", - "CLK_BUFG_REBUF_EE2BEG3_1", - "CLK_BUFG_REBUF_EE4A0_0", - "CLK_BUFG_REBUF_EE4A0_1", - "CLK_BUFG_REBUF_EE4A1_0", - "CLK_BUFG_REBUF_EE4A1_1", - "CLK_BUFG_REBUF_EE4A2_0", - "CLK_BUFG_REBUF_EE4A2_1", - "CLK_BUFG_REBUF_EE4A3_0", - "CLK_BUFG_REBUF_EE4A3_1", - "CLK_BUFG_REBUF_EE4B0_0", - "CLK_BUFG_REBUF_EE4B0_1", - "CLK_BUFG_REBUF_EE4B1_0", - "CLK_BUFG_REBUF_EE4B1_1", - "CLK_BUFG_REBUF_EE4B2_0", - "CLK_BUFG_REBUF_EE4B2_1", - "CLK_BUFG_REBUF_EE4B3_0", - "CLK_BUFG_REBUF_EE4B3_1", - "CLK_BUFG_REBUF_EE4BEG0_0", - "CLK_BUFG_REBUF_EE4BEG0_1", - "CLK_BUFG_REBUF_EE4BEG1_0", - "CLK_BUFG_REBUF_EE4BEG1_1", - "CLK_BUFG_REBUF_EE4BEG2_0", - "CLK_BUFG_REBUF_EE4BEG2_1", - "CLK_BUFG_REBUF_EE4BEG3_0", - "CLK_BUFG_REBUF_EE4BEG3_1", - "CLK_BUFG_REBUF_EE4C0_0", - "CLK_BUFG_REBUF_EE4C0_1", - "CLK_BUFG_REBUF_EE4C1_0", - "CLK_BUFG_REBUF_EE4C1_1", - "CLK_BUFG_REBUF_EE4C2_0", - "CLK_BUFG_REBUF_EE4C2_1", - "CLK_BUFG_REBUF_EE4C3_0", - "CLK_BUFG_REBUF_EE4C3_1", - "CLK_BUFG_REBUF_EL1BEG0_0", - "CLK_BUFG_REBUF_EL1BEG0_1", - "CLK_BUFG_REBUF_EL1BEG1_0", - "CLK_BUFG_REBUF_EL1BEG1_1", - "CLK_BUFG_REBUF_EL1BEG2_0", - "CLK_BUFG_REBUF_EL1BEG2_1", - "CLK_BUFG_REBUF_EL1BEG3_0", - "CLK_BUFG_REBUF_EL1BEG3_1", - "CLK_BUFG_REBUF_ER1BEG0_0", - "CLK_BUFG_REBUF_ER1BEG0_1", - "CLK_BUFG_REBUF_ER1BEG1_0", - "CLK_BUFG_REBUF_ER1BEG1_1", - "CLK_BUFG_REBUF_ER1BEG2_0", - "CLK_BUFG_REBUF_ER1BEG2_1", - "CLK_BUFG_REBUF_ER1BEG3_0", - "CLK_BUFG_REBUF_ER1BEG3_1", - "CLK_BUFG_REBUF_LH10_0", - "CLK_BUFG_REBUF_LH10_1", - "CLK_BUFG_REBUF_LH11_0", - "CLK_BUFG_REBUF_LH11_1", - "CLK_BUFG_REBUF_LH12_0", - "CLK_BUFG_REBUF_LH12_1", - "CLK_BUFG_REBUF_LH1_0", - "CLK_BUFG_REBUF_LH1_1", - "CLK_BUFG_REBUF_LH2_0", - "CLK_BUFG_REBUF_LH2_1", - "CLK_BUFG_REBUF_LH3_0", - "CLK_BUFG_REBUF_LH3_1", - "CLK_BUFG_REBUF_LH4_0", - "CLK_BUFG_REBUF_LH4_1", - "CLK_BUFG_REBUF_LH5_0", - "CLK_BUFG_REBUF_LH5_1", - "CLK_BUFG_REBUF_LH6_0", - "CLK_BUFG_REBUF_LH6_1", - "CLK_BUFG_REBUF_LH7_0", - "CLK_BUFG_REBUF_LH7_1", - "CLK_BUFG_REBUF_LH8_0", - "CLK_BUFG_REBUF_LH8_1", - "CLK_BUFG_REBUF_LH9_0", - "CLK_BUFG_REBUF_LH9_1", - "CLK_BUFG_REBUF_MONITOR_N_0", - "CLK_BUFG_REBUF_MONITOR_N_1", - "CLK_BUFG_REBUF_MONITOR_P_0", - "CLK_BUFG_REBUF_MONITOR_P_1", - "CLK_BUFG_REBUF_NE2A0_0", - "CLK_BUFG_REBUF_NE2A0_1", - "CLK_BUFG_REBUF_NE2A1_0", - "CLK_BUFG_REBUF_NE2A1_1", - "CLK_BUFG_REBUF_NE2A2_0", - "CLK_BUFG_REBUF_NE2A2_1", - "CLK_BUFG_REBUF_NE2A3_0", - "CLK_BUFG_REBUF_NE2A3_1", - "CLK_BUFG_REBUF_NE4BEG0_0", - "CLK_BUFG_REBUF_NE4BEG0_1", - "CLK_BUFG_REBUF_NE4BEG1_0", - "CLK_BUFG_REBUF_NE4BEG1_1", - "CLK_BUFG_REBUF_NE4BEG2_0", - "CLK_BUFG_REBUF_NE4BEG2_1", - "CLK_BUFG_REBUF_NE4BEG3_0", - "CLK_BUFG_REBUF_NE4BEG3_1", - "CLK_BUFG_REBUF_NE4C0_0", - "CLK_BUFG_REBUF_NE4C0_1", - "CLK_BUFG_REBUF_NE4C1_0", - "CLK_BUFG_REBUF_NE4C1_1", - "CLK_BUFG_REBUF_NE4C2_0", - "CLK_BUFG_REBUF_NE4C2_1", - "CLK_BUFG_REBUF_NE4C3_0", - "CLK_BUFG_REBUF_NE4C3_1", - "CLK_BUFG_REBUF_NW2A0_0", - "CLK_BUFG_REBUF_NW2A0_1", - "CLK_BUFG_REBUF_NW2A1_0", - "CLK_BUFG_REBUF_NW2A1_1", - "CLK_BUFG_REBUF_NW2A2_0", - "CLK_BUFG_REBUF_NW2A2_1", - "CLK_BUFG_REBUF_NW2A3_0", - "CLK_BUFG_REBUF_NW2A3_1", - "CLK_BUFG_REBUF_NW4A0_0", - "CLK_BUFG_REBUF_NW4A0_1", - "CLK_BUFG_REBUF_NW4A1_0", - "CLK_BUFG_REBUF_NW4A1_1", - "CLK_BUFG_REBUF_NW4A2_0", - "CLK_BUFG_REBUF_NW4A2_1", - "CLK_BUFG_REBUF_NW4A3_0", - "CLK_BUFG_REBUF_NW4A3_1", - "CLK_BUFG_REBUF_NW4END0_0", - "CLK_BUFG_REBUF_NW4END0_1", - "CLK_BUFG_REBUF_NW4END1_0", - "CLK_BUFG_REBUF_NW4END1_1", - "CLK_BUFG_REBUF_NW4END2_0", - "CLK_BUFG_REBUF_NW4END2_1", - "CLK_BUFG_REBUF_NW4END3_0", - "CLK_BUFG_REBUF_NW4END3_1", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC1", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC31", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC9", - "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK12_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", - "CLK_BUFG_REBUF_SE2A0_0", - "CLK_BUFG_REBUF_SE2A0_1", - "CLK_BUFG_REBUF_SE2A1_0", - "CLK_BUFG_REBUF_SE2A1_1", - "CLK_BUFG_REBUF_SE2A2_0", - "CLK_BUFG_REBUF_SE2A2_1", - "CLK_BUFG_REBUF_SE2A3_0", - "CLK_BUFG_REBUF_SE2A3_1", - "CLK_BUFG_REBUF_SE4BEG0_0", - "CLK_BUFG_REBUF_SE4BEG0_1", - "CLK_BUFG_REBUF_SE4BEG1_0", - "CLK_BUFG_REBUF_SE4BEG1_1", - "CLK_BUFG_REBUF_SE4BEG2_0", - "CLK_BUFG_REBUF_SE4BEG2_1", - "CLK_BUFG_REBUF_SE4BEG3_0", - "CLK_BUFG_REBUF_SE4BEG3_1", - "CLK_BUFG_REBUF_SE4C0_0", - "CLK_BUFG_REBUF_SE4C0_1", - "CLK_BUFG_REBUF_SE4C1_0", - "CLK_BUFG_REBUF_SE4C1_1", - "CLK_BUFG_REBUF_SE4C2_0", - "CLK_BUFG_REBUF_SE4C2_1", - "CLK_BUFG_REBUF_SE4C3_0", - "CLK_BUFG_REBUF_SE4C3_1", - "CLK_BUFG_REBUF_SW2A0_0", - "CLK_BUFG_REBUF_SW2A0_1", - "CLK_BUFG_REBUF_SW2A1_0", - "CLK_BUFG_REBUF_SW2A1_1", - "CLK_BUFG_REBUF_SW2A2_0", - "CLK_BUFG_REBUF_SW2A2_1", - "CLK_BUFG_REBUF_SW2A3_0", - "CLK_BUFG_REBUF_SW2A3_1", - "CLK_BUFG_REBUF_SW4A0_0", - "CLK_BUFG_REBUF_SW4A0_1", - "CLK_BUFG_REBUF_SW4A1_0", - "CLK_BUFG_REBUF_SW4A1_1", - "CLK_BUFG_REBUF_SW4A2_0", - "CLK_BUFG_REBUF_SW4A2_1", - "CLK_BUFG_REBUF_SW4A3_0", - "CLK_BUFG_REBUF_SW4A3_1", - "CLK_BUFG_REBUF_SW4END0_0", - "CLK_BUFG_REBUF_SW4END0_1", - "CLK_BUFG_REBUF_SW4END1_0", - "CLK_BUFG_REBUF_SW4END1_1", - "CLK_BUFG_REBUF_SW4END2_0", - "CLK_BUFG_REBUF_SW4END2_1", - "CLK_BUFG_REBUF_SW4END3_0", - "CLK_BUFG_REBUF_SW4END3_1", - "CLK_BUFG_REBUF_WL1END0_0", - "CLK_BUFG_REBUF_WL1END0_1", - "CLK_BUFG_REBUF_WL1END1_0", - "CLK_BUFG_REBUF_WL1END1_1", - "CLK_BUFG_REBUF_WL1END2_0", - "CLK_BUFG_REBUF_WL1END2_1", - "CLK_BUFG_REBUF_WL1END3_0", - "CLK_BUFG_REBUF_WL1END3_1", - "CLK_BUFG_REBUF_WR1END0_0", - "CLK_BUFG_REBUF_WR1END0_1", - "CLK_BUFG_REBUF_WR1END1_0", - "CLK_BUFG_REBUF_WR1END1_1", - "CLK_BUFG_REBUF_WR1END2_0", - "CLK_BUFG_REBUF_WR1END2_1", - "CLK_BUFG_REBUF_WR1END3_0", - "CLK_BUFG_REBUF_WR1END3_1", - "CLK_BUFG_REBUF_WW2A0_0", - "CLK_BUFG_REBUF_WW2A0_1", - "CLK_BUFG_REBUF_WW2A1_0", - "CLK_BUFG_REBUF_WW2A1_1", - "CLK_BUFG_REBUF_WW2A2_0", - "CLK_BUFG_REBUF_WW2A2_1", - "CLK_BUFG_REBUF_WW2A3_0", - "CLK_BUFG_REBUF_WW2A3_1", - "CLK_BUFG_REBUF_WW2END0_0", - "CLK_BUFG_REBUF_WW2END0_1", - "CLK_BUFG_REBUF_WW2END1_0", - "CLK_BUFG_REBUF_WW2END1_1", - "CLK_BUFG_REBUF_WW2END2_0", - "CLK_BUFG_REBUF_WW2END2_1", - "CLK_BUFG_REBUF_WW2END3_0", - "CLK_BUFG_REBUF_WW2END3_1", - "CLK_BUFG_REBUF_WW4A0_0", - "CLK_BUFG_REBUF_WW4A0_1", - "CLK_BUFG_REBUF_WW4A1_0", - "CLK_BUFG_REBUF_WW4A1_1", - "CLK_BUFG_REBUF_WW4A2_0", - "CLK_BUFG_REBUF_WW4A2_1", - "CLK_BUFG_REBUF_WW4A3_0", - "CLK_BUFG_REBUF_WW4A3_1", - "CLK_BUFG_REBUF_WW4B0_0", - "CLK_BUFG_REBUF_WW4B0_1", - "CLK_BUFG_REBUF_WW4B1_0", - "CLK_BUFG_REBUF_WW4B1_1", - "CLK_BUFG_REBUF_WW4B2_0", - "CLK_BUFG_REBUF_WW4B2_1", - "CLK_BUFG_REBUF_WW4B3_0", - "CLK_BUFG_REBUF_WW4B3_1", - "CLK_BUFG_REBUF_WW4C0_0", - "CLK_BUFG_REBUF_WW4C0_1", - "CLK_BUFG_REBUF_WW4C1_0", - "CLK_BUFG_REBUF_WW4C1_1", - "CLK_BUFG_REBUF_WW4C2_0", - "CLK_BUFG_REBUF_WW4C2_1", - "CLK_BUFG_REBUF_WW4C3_0", - "CLK_BUFG_REBUF_WW4C3_1", - "CLK_BUFG_REBUF_WW4END0_0", - "CLK_BUFG_REBUF_WW4END0_1", - "CLK_BUFG_REBUF_WW4END1_0", - "CLK_BUFG_REBUF_WW4END1_1", - "CLK_BUFG_REBUF_WW4END2_0", - "CLK_BUFG_REBUF_WW4END2_1", - "CLK_BUFG_REBUF_WW4END3_0", - "CLK_BUFG_REBUF_WW4END3_1", - "GCLK0_1_DN_TEST_RING_IN", - "GCLK0_1_DN_TEST_RING_OUT", - "GCLK10_11_DN_TEST_RING_IN", - "GCLK10_11_DN_TEST_RING_OUT", - "GCLK11_10_UP_TEST_RING_IN", - "GCLK11_10_UP_TEST_RING_OUT", - "GCLK12_13_DN_TEST_RING_IN", - "GCLK12_13_DN_TEST_RING_OUT", - "GCLK13_12_UP_TEST_RING_IN", - "GCLK13_12_UP_TEST_RING_OUT", - "GCLK14_15_DN_TEST_RING_IN", - "GCLK14_15_DN_TEST_RING_OUT", - "GCLK15_14_UP_TEST_RING_IN", - "GCLK15_14_UP_TEST_RING_OUT", - "GCLK16_17_DN_TEST_RING_IN", - "GCLK16_17_DN_TEST_RING_OUT", - "GCLK17_16_UP_TEST_RING_IN", - "GCLK17_16_UP_TEST_RING_OUT", - "GCLK18_19_DN_TEST_RING_IN", - "GCLK18_19_DN_TEST_RING_OUT", - "GCLK19_18_UP_TEST_RING_IN", - "GCLK19_18_UP_TEST_RING_OUT", - "GCLK1_0_UP_TEST_RING_IN", - "GCLK1_0_UP_TEST_RING_OUT", - "GCLK20_21_DN_TEST_RING_IN", - "GCLK20_21_DN_TEST_RING_OUT", - "GCLK21_20_UP_TEST_RING_IN", - "GCLK21_20_UP_TEST_RING_OUT", - "GCLK22_23_DN_TEST_RING_IN", - "GCLK22_23_DN_TEST_RING_OUT", - "GCLK23_22_UP_TEST_RING_IN", - "GCLK23_22_UP_TEST_RING_OUT", - "GCLK24_25_DN_TEST_RING_IN", - "GCLK24_25_DN_TEST_RING_OUT", - "GCLK25_24_UP_TEST_RING_IN", - "GCLK25_24_UP_TEST_RING_OUT", - "GCLK26_27_DN_TEST_RING_IN", - "GCLK26_27_DN_TEST_RING_OUT", - "GCLK27_26_UP_TEST_RING_IN", - "GCLK27_26_UP_TEST_RING_OUT", - "GCLK28_29_DN_TEST_RING_IN", - "GCLK28_29_DN_TEST_RING_OUT", - "GCLK29_28_UP_TEST_RING_IN", - "GCLK29_28_UP_TEST_RING_OUT", - "GCLK2_3_DN_TEST_RING_IN", - "GCLK2_3_DN_TEST_RING_OUT", - "GCLK30_31_DN_TEST_RING_IN", - "GCLK30_31_DN_TEST_RING_OUT", - "GCLK31_30_UP_TEST_RING_IN", - "GCLK31_30_UP_TEST_RING_OUT", - "GCLK3_2_UP_TEST_RING_IN", - "GCLK3_2_UP_TEST_RING_OUT", - "GCLK4_5_DN_TEST_RING_IN", - "GCLK4_5_DN_TEST_RING_OUT", - "GCLK5_4_UP_TEST_RING_IN", - "GCLK5_4_UP_TEST_RING_OUT", - "GCLK6_7_DN_TEST_RING_IN", - "GCLK6_7_DN_TEST_RING_OUT", - "GCLK7_6_UP_TEST_RING_IN", - "GCLK7_6_UP_TEST_RING_OUT", - "GCLK8_9_DN_TEST_RING_IN", - "GCLK8_9_DN_TEST_RING_OUT", - "GCLK9_8_UP_TEST_RING_IN", - "GCLK9_8_UP_TEST_RING_OUT" - ] + "wires": { + "CLK_BUFG_REBUF_CK_BUFG_CASC0": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC1": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC10": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC11": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC12": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC13": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC14": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC15": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC16": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC17": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC18": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC19": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC2": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC20": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC21": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC22": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC23": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC24": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC25": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC26": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC27": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC28": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC29": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC3": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC30": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC31": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC4": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC5": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC6": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC7": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC8": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC9": null, + "CLK_BUFG_REBUF_CK_GCLK0_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK0_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK10_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK10_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK11_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK11_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK12_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK12_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK13_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK13_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK14_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK14_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK15_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK15_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK16_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK16_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK17_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK17_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK18_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK18_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK19_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK19_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK1_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK1_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK20_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK20_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK21_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK21_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK22_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK22_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK23_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK23_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK24_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK24_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK25_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK25_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK26_BOT": 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"CLK_BUFG_REBUF_R_CK_BUFG_CASC0": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC1": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC10": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC11": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC12": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC13": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC14": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC15": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC16": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC17": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC18": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC19": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC2": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC20": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC21": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC22": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC23": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC24": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC25": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC26": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC27": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC28": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC29": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC3": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC30": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC31": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC4": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC5": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC6": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC7": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC8": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC9": null, + "CLK_BUFG_REBUF_R_CK_GCLK0_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK0_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK10_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK10_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK11_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK11_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK12_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK12_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK13_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK13_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK14_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK14_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK15_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK15_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK16_BOT": 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"CLK_BUFG_REBUF_R_CK_GCLK27_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK27_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK28_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK28_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK29_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK29_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK2_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK2_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK30_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK30_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK31_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK31_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK3_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK3_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK4_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK4_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK5_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK5_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK6_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK6_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK7_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK7_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK8_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK8_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK9_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK9_TOP": null, + "CLK_BUFG_REBUF_SE2A0_0": null, + "CLK_BUFG_REBUF_SE2A0_1": null, + "CLK_BUFG_REBUF_SE2A1_0": null, + "CLK_BUFG_REBUF_SE2A1_1": null, + "CLK_BUFG_REBUF_SE2A2_0": null, + "CLK_BUFG_REBUF_SE2A2_1": null, + "CLK_BUFG_REBUF_SE2A3_0": null, + "CLK_BUFG_REBUF_SE2A3_1": null, + "CLK_BUFG_REBUF_SE4BEG0_0": null, + "CLK_BUFG_REBUF_SE4BEG0_1": null, + "CLK_BUFG_REBUF_SE4BEG1_0": null, + "CLK_BUFG_REBUF_SE4BEG1_1": null, + "CLK_BUFG_REBUF_SE4BEG2_0": null, + "CLK_BUFG_REBUF_SE4BEG2_1": null, + "CLK_BUFG_REBUF_SE4BEG3_0": null, + "CLK_BUFG_REBUF_SE4BEG3_1": null, + "CLK_BUFG_REBUF_SE4C0_0": null, + "CLK_BUFG_REBUF_SE4C0_1": null, + "CLK_BUFG_REBUF_SE4C1_0": null, + "CLK_BUFG_REBUF_SE4C1_1": null, + "CLK_BUFG_REBUF_SE4C2_0": null, + "CLK_BUFG_REBUF_SE4C2_1": null, + "CLK_BUFG_REBUF_SE4C3_0": null, + "CLK_BUFG_REBUF_SE4C3_1": null, + "CLK_BUFG_REBUF_SW2A0_0": null, + "CLK_BUFG_REBUF_SW2A0_1": null, + "CLK_BUFG_REBUF_SW2A1_0": null, + "CLK_BUFG_REBUF_SW2A1_1": null, + "CLK_BUFG_REBUF_SW2A2_0": null, + "CLK_BUFG_REBUF_SW2A2_1": null, + "CLK_BUFG_REBUF_SW2A3_0": null, + "CLK_BUFG_REBUF_SW2A3_1": null, + "CLK_BUFG_REBUF_SW4A0_0": null, + "CLK_BUFG_REBUF_SW4A0_1": null, + "CLK_BUFG_REBUF_SW4A1_0": null, + "CLK_BUFG_REBUF_SW4A1_1": null, + "CLK_BUFG_REBUF_SW4A2_0": null, + "CLK_BUFG_REBUF_SW4A2_1": null, + "CLK_BUFG_REBUF_SW4A3_0": null, + "CLK_BUFG_REBUF_SW4A3_1": null, + "CLK_BUFG_REBUF_SW4END0_0": null, + "CLK_BUFG_REBUF_SW4END0_1": null, + "CLK_BUFG_REBUF_SW4END1_0": null, + "CLK_BUFG_REBUF_SW4END1_1": null, + "CLK_BUFG_REBUF_SW4END2_0": null, + "CLK_BUFG_REBUF_SW4END2_1": null, + "CLK_BUFG_REBUF_SW4END3_0": null, + "CLK_BUFG_REBUF_SW4END3_1": null, + "CLK_BUFG_REBUF_WL1END0_0": null, + "CLK_BUFG_REBUF_WL1END0_1": null, + "CLK_BUFG_REBUF_WL1END1_0": null, + "CLK_BUFG_REBUF_WL1END1_1": null, + "CLK_BUFG_REBUF_WL1END2_0": null, + "CLK_BUFG_REBUF_WL1END2_1": null, + "CLK_BUFG_REBUF_WL1END3_0": null, + "CLK_BUFG_REBUF_WL1END3_1": null, + "CLK_BUFG_REBUF_WR1END0_0": null, + "CLK_BUFG_REBUF_WR1END0_1": null, + "CLK_BUFG_REBUF_WR1END1_0": null, + "CLK_BUFG_REBUF_WR1END1_1": null, + "CLK_BUFG_REBUF_WR1END2_0": null, + "CLK_BUFG_REBUF_WR1END2_1": null, + "CLK_BUFG_REBUF_WR1END3_0": null, + "CLK_BUFG_REBUF_WR1END3_1": null, + "CLK_BUFG_REBUF_WW2A0_0": null, + "CLK_BUFG_REBUF_WW2A0_1": null, + "CLK_BUFG_REBUF_WW2A1_0": null, + "CLK_BUFG_REBUF_WW2A1_1": null, + "CLK_BUFG_REBUF_WW2A2_0": null, + "CLK_BUFG_REBUF_WW2A2_1": null, + "CLK_BUFG_REBUF_WW2A3_0": null, + "CLK_BUFG_REBUF_WW2A3_1": null, + "CLK_BUFG_REBUF_WW2END0_0": null, + "CLK_BUFG_REBUF_WW2END0_1": null, + "CLK_BUFG_REBUF_WW2END1_0": null, + "CLK_BUFG_REBUF_WW2END1_1": null, + "CLK_BUFG_REBUF_WW2END2_0": null, + "CLK_BUFG_REBUF_WW2END2_1": null, + "CLK_BUFG_REBUF_WW2END3_0": null, + "CLK_BUFG_REBUF_WW2END3_1": null, + "CLK_BUFG_REBUF_WW4A0_0": null, + "CLK_BUFG_REBUF_WW4A0_1": null, + "CLK_BUFG_REBUF_WW4A1_0": null, + "CLK_BUFG_REBUF_WW4A1_1": null, + "CLK_BUFG_REBUF_WW4A2_0": null, + "CLK_BUFG_REBUF_WW4A2_1": null, + "CLK_BUFG_REBUF_WW4A3_0": null, + "CLK_BUFG_REBUF_WW4A3_1": null, + "CLK_BUFG_REBUF_WW4B0_0": null, + "CLK_BUFG_REBUF_WW4B0_1": null, + "CLK_BUFG_REBUF_WW4B1_0": null, + "CLK_BUFG_REBUF_WW4B1_1": null, + "CLK_BUFG_REBUF_WW4B2_0": null, + "CLK_BUFG_REBUF_WW4B2_1": null, + "CLK_BUFG_REBUF_WW4B3_0": null, + "CLK_BUFG_REBUF_WW4B3_1": null, + "CLK_BUFG_REBUF_WW4C0_0": null, + "CLK_BUFG_REBUF_WW4C0_1": null, + "CLK_BUFG_REBUF_WW4C1_0": null, + "CLK_BUFG_REBUF_WW4C1_1": null, + "CLK_BUFG_REBUF_WW4C2_0": null, + "CLK_BUFG_REBUF_WW4C2_1": null, + "CLK_BUFG_REBUF_WW4C3_0": null, + "CLK_BUFG_REBUF_WW4C3_1": null, + "CLK_BUFG_REBUF_WW4END0_0": null, + "CLK_BUFG_REBUF_WW4END0_1": null, + "CLK_BUFG_REBUF_WW4END1_0": null, + "CLK_BUFG_REBUF_WW4END1_1": null, + "CLK_BUFG_REBUF_WW4END2_0": null, + "CLK_BUFG_REBUF_WW4END2_1": null, + "CLK_BUFG_REBUF_WW4END3_0": null, + "CLK_BUFG_REBUF_WW4END3_1": null, + "GCLK0_1_DN_TEST_RING_IN": null, + "GCLK0_1_DN_TEST_RING_OUT": null, + "GCLK10_11_DN_TEST_RING_IN": null, + "GCLK10_11_DN_TEST_RING_OUT": null, + "GCLK11_10_UP_TEST_RING_IN": null, + "GCLK11_10_UP_TEST_RING_OUT": null, + "GCLK12_13_DN_TEST_RING_IN": null, + "GCLK12_13_DN_TEST_RING_OUT": null, + "GCLK13_12_UP_TEST_RING_IN": null, + "GCLK13_12_UP_TEST_RING_OUT": null, + "GCLK14_15_DN_TEST_RING_IN": null, + "GCLK14_15_DN_TEST_RING_OUT": null, + "GCLK15_14_UP_TEST_RING_IN": null, + "GCLK15_14_UP_TEST_RING_OUT": null, + "GCLK16_17_DN_TEST_RING_IN": null, + "GCLK16_17_DN_TEST_RING_OUT": null, + "GCLK17_16_UP_TEST_RING_IN": null, + "GCLK17_16_UP_TEST_RING_OUT": null, + "GCLK18_19_DN_TEST_RING_IN": null, + "GCLK18_19_DN_TEST_RING_OUT": null, + "GCLK19_18_UP_TEST_RING_IN": null, + "GCLK19_18_UP_TEST_RING_OUT": null, + "GCLK1_0_UP_TEST_RING_IN": null, + "GCLK1_0_UP_TEST_RING_OUT": null, + "GCLK20_21_DN_TEST_RING_IN": null, + "GCLK20_21_DN_TEST_RING_OUT": null, + "GCLK21_20_UP_TEST_RING_IN": null, + "GCLK21_20_UP_TEST_RING_OUT": null, + "GCLK22_23_DN_TEST_RING_IN": null, + "GCLK22_23_DN_TEST_RING_OUT": null, + "GCLK23_22_UP_TEST_RING_IN": null, + "GCLK23_22_UP_TEST_RING_OUT": null, + "GCLK24_25_DN_TEST_RING_IN": null, + "GCLK24_25_DN_TEST_RING_OUT": null, + "GCLK25_24_UP_TEST_RING_IN": null, + "GCLK25_24_UP_TEST_RING_OUT": null, + "GCLK26_27_DN_TEST_RING_IN": null, + "GCLK26_27_DN_TEST_RING_OUT": null, + "GCLK27_26_UP_TEST_RING_IN": null, + "GCLK27_26_UP_TEST_RING_OUT": null, + "GCLK28_29_DN_TEST_RING_IN": null, + "GCLK28_29_DN_TEST_RING_OUT": null, + "GCLK29_28_UP_TEST_RING_IN": null, + "GCLK29_28_UP_TEST_RING_OUT": null, + "GCLK2_3_DN_TEST_RING_IN": null, + "GCLK2_3_DN_TEST_RING_OUT": null, + "GCLK30_31_DN_TEST_RING_IN": null, + "GCLK30_31_DN_TEST_RING_OUT": null, + "GCLK31_30_UP_TEST_RING_IN": null, + "GCLK31_30_UP_TEST_RING_OUT": null, + "GCLK3_2_UP_TEST_RING_IN": null, + "GCLK3_2_UP_TEST_RING_OUT": null, + "GCLK4_5_DN_TEST_RING_IN": null, + "GCLK4_5_DN_TEST_RING_OUT": null, + "GCLK5_4_UP_TEST_RING_IN": null, + "GCLK5_4_UP_TEST_RING_OUT": null, + "GCLK6_7_DN_TEST_RING_IN": null, + "GCLK6_7_DN_TEST_RING_OUT": null, + "GCLK7_6_UP_TEST_RING_IN": null, + "GCLK7_6_UP_TEST_RING_OUT": null, + "GCLK8_9_DN_TEST_RING_IN": null, + "GCLK8_9_DN_TEST_RING_OUT": null, + "GCLK9_8_UP_TEST_RING_IN": null, + "GCLK9_8_UP_TEST_RING_OUT": null + } } diff --git a/zynq7/tile_type_CLK_BUFG_TOP_R.json b/zynq7/tile_type_CLK_BUFG_TOP_R.json index c2f91e8..5b310d6 100644 --- a/zynq7/tile_type_CLK_BUFG_TOP_R.json +++ b/zynq7/tile_type_CLK_BUFG_TOP_R.json @@ -2,2130 +2,8514 @@ "pips": { "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0->>CLK_BUFG_BUFGCTRL0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL0_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_CK_GCLK16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL0_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_R_FBG_OUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL0_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0->>CLK_BUFG_BUFGCTRL10_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL10_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_CK_GCLK26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL10_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_R_FBG_OUT10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL10_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0->>CLK_BUFG_BUFGCTRL11_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL11_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_CK_GCLK27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL11_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_R_FBG_OUT11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL11_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0->>CLK_BUFG_BUFGCTRL12_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL12_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_CK_GCLK28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL12_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_R_FBG_OUT12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL12_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0->>CLK_BUFG_BUFGCTRL13_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL13_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_CK_GCLK29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL13_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_R_FBG_OUT13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL13_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0->>CLK_BUFG_BUFGCTRL14_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL14_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_CK_GCLK30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL14_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_R_FBG_OUT14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL14_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0->>CLK_BUFG_BUFGCTRL15_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL15_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_CK_GCLK31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL15_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_R_FBG_OUT15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL15_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0->>CLK_BUFG_BUFGCTRL1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL1_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_CK_GCLK17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL1_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_R_FBG_OUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL1_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0->>CLK_BUFG_BUFGCTRL2_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL2_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_CK_GCLK18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL2_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_R_FBG_OUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL2_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0->>CLK_BUFG_BUFGCTRL3_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL3_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_CK_GCLK19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL3_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_R_FBG_OUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL3_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0->>CLK_BUFG_BUFGCTRL4_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL4_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_CK_GCLK20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL4_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_R_FBG_OUT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL4_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0->>CLK_BUFG_BUFGCTRL5_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL5_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_CK_GCLK21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL5_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_R_FBG_OUT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL5_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0->>CLK_BUFG_BUFGCTRL6_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL6_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_CK_GCLK22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL6_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_R_FBG_OUT6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL6_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0->>CLK_BUFG_BUFGCTRL7_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL7_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_CK_GCLK23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL7_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_R_FBG_OUT7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL7_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0->>CLK_BUFG_BUFGCTRL8_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL8_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_CK_GCLK24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL8_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_R_FBG_OUT8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL8_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0->>CLK_BUFG_BUFGCTRL9_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.029", + "0.091", + "0.101" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL9_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_CK_GCLK25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL9_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_R_FBG_OUT9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL9_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_0->>CLK_BUFG_R_BUFGCTRL0_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_1->>CLK_BUFG_R_BUFGCTRL4_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_2->>CLK_BUFG_R_BUFGCTRL8_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_3->>CLK_BUFG_R_BUFGCTRL12_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_0->>CLK_BUFG_R_BUFGCTRL0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_1->>CLK_BUFG_R_BUFGCTRL4_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_2->>CLK_BUFG_R_BUFGCTRL8_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_3->>CLK_BUFG_R_BUFGCTRL12_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_0->>CLK_BUFG_R_BUFGCTRL1_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_1->>CLK_BUFG_R_BUFGCTRL5_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_2->>CLK_BUFG_R_BUFGCTRL9_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_3->>CLK_BUFG_R_BUFGCTRL13_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_0->>CLK_BUFG_R_BUFGCTRL2_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_1->>CLK_BUFG_R_BUFGCTRL6_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_2->>CLK_BUFG_R_BUFGCTRL10_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_3->>CLK_BUFG_R_BUFGCTRL14_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_0->>CLK_BUFG_R_BUFGCTRL3_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_1->>CLK_BUFG_R_BUFGCTRL7_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_2->>CLK_BUFG_R_BUFGCTRL11_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_3->>CLK_BUFG_R_BUFGCTRL15_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_0->>CLK_BUFG_R_BUFGCTRL1_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_1->>CLK_BUFG_R_BUFGCTRL5_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_2->>CLK_BUFG_R_BUFGCTRL9_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_3->>CLK_BUFG_R_BUFGCTRL13_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_0->>CLK_BUFG_R_BUFGCTRL0_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_1->>CLK_BUFG_R_BUFGCTRL4_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_2->>CLK_BUFG_R_BUFGCTRL8_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_3->>CLK_BUFG_R_BUFGCTRL12_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_0->>CLK_BUFG_R_BUFGCTRL1_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_1->>CLK_BUFG_R_BUFGCTRL5_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_2->>CLK_BUFG_R_BUFGCTRL9_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_3->>CLK_BUFG_R_BUFGCTRL13_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_0->>CLK_BUFG_R_BUFGCTRL2_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_1->>CLK_BUFG_R_BUFGCTRL6_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_2->>CLK_BUFG_R_BUFGCTRL10_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_3->>CLK_BUFG_R_BUFGCTRL14_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_0->>CLK_BUFG_R_BUFGCTRL3_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_1->>CLK_BUFG_R_BUFGCTRL7_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_2->>CLK_BUFG_R_BUFGCTRL11_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_3->>CLK_BUFG_R_BUFGCTRL15_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_0->>CLK_BUFG_R_BUFGCTRL2_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_1->>CLK_BUFG_R_BUFGCTRL6_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_2->>CLK_BUFG_R_BUFGCTRL10_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_3->>CLK_BUFG_R_BUFGCTRL14_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.064", + "0.071", + "0.217", + "0.238" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_0->>CLK_BUFG_R_BUFGCTRL3_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_1->>CLK_BUFG_R_BUFGCTRL7_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_2->>CLK_BUFG_R_BUFGCTRL11_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_3->>CLK_BUFG_R_BUFGCTRL15_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_0->>CLK_BUFG_R_BUFGCTRL0_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_1->>CLK_BUFG_R_BUFGCTRL4_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_2->>CLK_BUFG_R_BUFGCTRL8_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_3->>CLK_BUFG_R_BUFGCTRL12_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_0->>CLK_BUFG_R_BUFGCTRL1_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_1->>CLK_BUFG_R_BUFGCTRL5_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_2->>CLK_BUFG_R_BUFGCTRL9_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_3->>CLK_BUFG_R_BUFGCTRL13_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_0->>CLK_BUFG_R_BUFGCTRL2_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_1->>CLK_BUFG_R_BUFGCTRL6_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_2->>CLK_BUFG_R_BUFGCTRL10_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_3->>CLK_BUFG_R_BUFGCTRL14_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_0->>CLK_BUFG_R_BUFGCTRL3_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_1->>CLK_BUFG_R_BUFGCTRL7_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_2->>CLK_BUFG_R_BUFGCTRL11_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_3->>CLK_BUFG_R_BUFGCTRL15_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.022", + "0.069", + "0.076" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.040", + "0.044", + "0.145", + "0.159" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.028", + "0.031", + "0.131", + "0.144" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED0" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED1->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED1" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED10->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED10" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED11->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED11" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED12->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED12" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED13->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED13" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED14->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED14" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED15->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED15" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED16->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED16" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED17->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED17" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED18->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED18" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED19->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED19" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED2->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED2" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED20->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED20" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED21->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED21" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED22->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED22" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED23->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED23" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED24->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED24" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED25->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED25" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED26->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED26" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED27->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED27" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED28->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED28" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED29->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED29" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED3->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED3" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED30->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED30" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED31->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED31" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED4->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED4" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED5->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED5" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED6->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED6" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED7->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED7" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED8->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED8" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED9->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.068", + "0.075", + "0.182", + "0.200" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED9" } }, @@ -2134,15 +8518,96 @@ "name": "X0Y0", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL0_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL0_CE1", - "I0": "CLK_BUFG_BUFGCTRL0_I0", - "I1": "CLK_BUFG_BUFGCTRL0_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL0_O", - "S0": "CLK_BUFG_R_BUFGCTRL0_S0", - "S1": "CLK_BUFG_R_BUFGCTRL0_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL0_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2152,15 +8617,96 @@ "name": "X0Y1", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL1_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL1_CE1", - "I0": "CLK_BUFG_BUFGCTRL1_I0", - "I1": "CLK_BUFG_BUFGCTRL1_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL1_O", - "S0": "CLK_BUFG_R_BUFGCTRL1_S0", - "S1": "CLK_BUFG_R_BUFGCTRL1_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL1_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2170,15 +8716,96 @@ "name": "X0Y2", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL2_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL2_CE1", - "I0": "CLK_BUFG_BUFGCTRL2_I0", - "I1": "CLK_BUFG_BUFGCTRL2_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL2_O", - "S0": "CLK_BUFG_R_BUFGCTRL2_S0", - "S1": "CLK_BUFG_R_BUFGCTRL2_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL2_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2188,15 +8815,96 @@ "name": "X0Y3", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL3_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL3_CE1", - "I0": "CLK_BUFG_BUFGCTRL3_I0", - "I1": "CLK_BUFG_BUFGCTRL3_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL3_O", - "S0": "CLK_BUFG_R_BUFGCTRL3_S0", - "S1": "CLK_BUFG_R_BUFGCTRL3_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL3_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2206,15 +8914,96 @@ "name": "X0Y4", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL4_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL4_CE1", - "I0": "CLK_BUFG_BUFGCTRL4_I0", - "I1": "CLK_BUFG_BUFGCTRL4_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL4_O", - "S0": "CLK_BUFG_R_BUFGCTRL4_S0", - "S1": "CLK_BUFG_R_BUFGCTRL4_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL4_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL4_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2224,15 +9013,96 @@ "name": "X0Y5", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL5_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL5_CE1", - "I0": "CLK_BUFG_BUFGCTRL5_I0", - "I1": "CLK_BUFG_BUFGCTRL5_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL5_O", - "S0": "CLK_BUFG_R_BUFGCTRL5_S0", - "S1": "CLK_BUFG_R_BUFGCTRL5_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL5_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2242,15 +9112,96 @@ "name": "X0Y6", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL6_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL6_CE1", - "I0": "CLK_BUFG_BUFGCTRL6_I0", - "I1": "CLK_BUFG_BUFGCTRL6_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL6_O", - "S0": "CLK_BUFG_R_BUFGCTRL6_S0", - "S1": "CLK_BUFG_R_BUFGCTRL6_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL6_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL6_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL6_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2260,15 +9211,96 @@ "name": "X0Y7", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL7_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL7_CE1", - "I0": "CLK_BUFG_BUFGCTRL7_I0", - "I1": "CLK_BUFG_BUFGCTRL7_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL7_O", - "S0": "CLK_BUFG_R_BUFGCTRL7_S0", - "S1": "CLK_BUFG_R_BUFGCTRL7_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL7_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2278,15 +9310,96 @@ "name": "X0Y8", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL8_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL8_CE1", - "I0": "CLK_BUFG_BUFGCTRL8_I0", - "I1": "CLK_BUFG_BUFGCTRL8_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL8_O", - "S0": "CLK_BUFG_R_BUFGCTRL8_S0", - "S1": "CLK_BUFG_R_BUFGCTRL8_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL8_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2296,15 +9409,96 @@ "name": "X0Y9", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL9_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL9_CE1", - "I0": "CLK_BUFG_BUFGCTRL9_I0", - "I1": "CLK_BUFG_BUFGCTRL9_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL9_O", - "S0": "CLK_BUFG_R_BUFGCTRL9_S0", - "S1": "CLK_BUFG_R_BUFGCTRL9_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL9_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2314,15 +9508,96 @@ "name": "X0Y10", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL10_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL10_CE1", - "I0": "CLK_BUFG_BUFGCTRL10_I0", - "I1": "CLK_BUFG_BUFGCTRL10_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL10_O", - "S0": "CLK_BUFG_R_BUFGCTRL10_S0", - "S1": "CLK_BUFG_R_BUFGCTRL10_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL10_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL10_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2332,15 +9607,96 @@ "name": "X0Y11", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL11_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL11_CE1", - "I0": "CLK_BUFG_BUFGCTRL11_I0", - "I1": "CLK_BUFG_BUFGCTRL11_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL11_O", - "S0": "CLK_BUFG_R_BUFGCTRL11_S0", - "S1": "CLK_BUFG_R_BUFGCTRL11_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL11_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL11_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL11_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2350,15 +9706,96 @@ "name": "X0Y12", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL12_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL12_CE1", - "I0": "CLK_BUFG_BUFGCTRL12_I0", - "I1": "CLK_BUFG_BUFGCTRL12_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL12_O", - "S0": "CLK_BUFG_R_BUFGCTRL12_S0", - "S1": "CLK_BUFG_R_BUFGCTRL12_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL12_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL12_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2368,15 +9805,96 @@ "name": "X0Y13", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL13_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL13_CE1", - "I0": "CLK_BUFG_BUFGCTRL13_I0", - "I1": "CLK_BUFG_BUFGCTRL13_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL13_O", - "S0": "CLK_BUFG_R_BUFGCTRL13_S0", - "S1": "CLK_BUFG_R_BUFGCTRL13_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL13_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2386,15 +9904,96 @@ "name": "X0Y14", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL14_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL14_CE1", - "I0": "CLK_BUFG_BUFGCTRL14_I0", - "I1": "CLK_BUFG_BUFGCTRL14_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL14_O", - "S0": "CLK_BUFG_R_BUFGCTRL14_S0", - "S1": "CLK_BUFG_R_BUFGCTRL14_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL14_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2404,15 +10003,96 @@ "name": "X0Y15", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL15_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL15_CE1", - "I0": "CLK_BUFG_BUFGCTRL15_I0", - "I1": "CLK_BUFG_BUFGCTRL15_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL15_O", - "S0": "CLK_BUFG_R_BUFGCTRL15_S0", - "S1": "CLK_BUFG_R_BUFGCTRL15_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL15_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2420,1150 +10100,1750 @@ } ], "tile_type": "CLK_BUFG_TOP_R", - "wires": [ - "CLK_BUFG_BUFGCTRL0_I0", - "CLK_BUFG_BUFGCTRL0_I1", - "CLK_BUFG_BUFGCTRL0_O", - "CLK_BUFG_BUFGCTRL10_I0", - "CLK_BUFG_BUFGCTRL10_I1", - "CLK_BUFG_BUFGCTRL10_O", - "CLK_BUFG_BUFGCTRL11_I0", - "CLK_BUFG_BUFGCTRL11_I1", - "CLK_BUFG_BUFGCTRL11_O", - "CLK_BUFG_BUFGCTRL12_I0", - "CLK_BUFG_BUFGCTRL12_I1", - "CLK_BUFG_BUFGCTRL12_O", - "CLK_BUFG_BUFGCTRL13_I0", - "CLK_BUFG_BUFGCTRL13_I1", - "CLK_BUFG_BUFGCTRL13_O", - "CLK_BUFG_BUFGCTRL14_I0", - "CLK_BUFG_BUFGCTRL14_I1", - "CLK_BUFG_BUFGCTRL14_O", - "CLK_BUFG_BUFGCTRL15_I0", - "CLK_BUFG_BUFGCTRL15_I1", - "CLK_BUFG_BUFGCTRL15_O", - "CLK_BUFG_BUFGCTRL1_I0", - "CLK_BUFG_BUFGCTRL1_I1", - "CLK_BUFG_BUFGCTRL1_O", - "CLK_BUFG_BUFGCTRL2_I0", - "CLK_BUFG_BUFGCTRL2_I1", - "CLK_BUFG_BUFGCTRL2_O", - "CLK_BUFG_BUFGCTRL3_I0", - "CLK_BUFG_BUFGCTRL3_I1", - "CLK_BUFG_BUFGCTRL3_O", - "CLK_BUFG_BUFGCTRL4_I0", - "CLK_BUFG_BUFGCTRL4_I1", - "CLK_BUFG_BUFGCTRL4_O", - "CLK_BUFG_BUFGCTRL5_I0", - "CLK_BUFG_BUFGCTRL5_I1", - "CLK_BUFG_BUFGCTRL5_O", - "CLK_BUFG_BUFGCTRL6_I0", - "CLK_BUFG_BUFGCTRL6_I1", - "CLK_BUFG_BUFGCTRL6_O", - "CLK_BUFG_BUFGCTRL7_I0", - "CLK_BUFG_BUFGCTRL7_I1", - "CLK_BUFG_BUFGCTRL7_O", - "CLK_BUFG_BUFGCTRL8_I0", - "CLK_BUFG_BUFGCTRL8_I1", - "CLK_BUFG_BUFGCTRL8_O", - "CLK_BUFG_BUFGCTRL9_I0", - "CLK_BUFG_BUFGCTRL9_I1", - "CLK_BUFG_BUFGCTRL9_O", - "CLK_BUFG_CK_GCLK0", - "CLK_BUFG_CK_GCLK1", - "CLK_BUFG_CK_GCLK10", - "CLK_BUFG_CK_GCLK11", - "CLK_BUFG_CK_GCLK12", - "CLK_BUFG_CK_GCLK13", - "CLK_BUFG_CK_GCLK14", - "CLK_BUFG_CK_GCLK15", - "CLK_BUFG_CK_GCLK16", - "CLK_BUFG_CK_GCLK17", - "CLK_BUFG_CK_GCLK18", - "CLK_BUFG_CK_GCLK19", - "CLK_BUFG_CK_GCLK2", - "CLK_BUFG_CK_GCLK20", - "CLK_BUFG_CK_GCLK21", - "CLK_BUFG_CK_GCLK22", - "CLK_BUFG_CK_GCLK23", - "CLK_BUFG_CK_GCLK24", - "CLK_BUFG_CK_GCLK25", - "CLK_BUFG_CK_GCLK26", - "CLK_BUFG_CK_GCLK27", - "CLK_BUFG_CK_GCLK28", - "CLK_BUFG_CK_GCLK29", - "CLK_BUFG_CK_GCLK3", - "CLK_BUFG_CK_GCLK30", - "CLK_BUFG_CK_GCLK31", - "CLK_BUFG_CK_GCLK4", - "CLK_BUFG_CK_GCLK5", - "CLK_BUFG_CK_GCLK6", - "CLK_BUFG_CK_GCLK7", - "CLK_BUFG_CK_GCLK8", - "CLK_BUFG_CK_GCLK9", - "CLK_BUFG_IMUX0_0", - "CLK_BUFG_IMUX0_1", - "CLK_BUFG_IMUX0_2", - "CLK_BUFG_IMUX0_3", - "CLK_BUFG_IMUX10_0", - "CLK_BUFG_IMUX10_1", - "CLK_BUFG_IMUX10_2", - "CLK_BUFG_IMUX10_3", - "CLK_BUFG_IMUX11_0", - "CLK_BUFG_IMUX11_1", - "CLK_BUFG_IMUX11_2", - "CLK_BUFG_IMUX11_3", - "CLK_BUFG_IMUX12_0", - "CLK_BUFG_IMUX12_1", - "CLK_BUFG_IMUX12_2", - "CLK_BUFG_IMUX12_3", - "CLK_BUFG_IMUX13_0", - "CLK_BUFG_IMUX13_1", - "CLK_BUFG_IMUX13_2", - "CLK_BUFG_IMUX13_3", - "CLK_BUFG_IMUX14_0", - "CLK_BUFG_IMUX14_1", - "CLK_BUFG_IMUX14_2", - "CLK_BUFG_IMUX14_3", - "CLK_BUFG_IMUX15_0", - "CLK_BUFG_IMUX15_1", - "CLK_BUFG_IMUX15_2", - "CLK_BUFG_IMUX15_3", - "CLK_BUFG_IMUX16_0", - "CLK_BUFG_IMUX16_1", - "CLK_BUFG_IMUX16_2", - "CLK_BUFG_IMUX16_3", - "CLK_BUFG_IMUX17_0", - "CLK_BUFG_IMUX17_1", - "CLK_BUFG_IMUX17_2", - "CLK_BUFG_IMUX17_3", - "CLK_BUFG_IMUX18_0", - "CLK_BUFG_IMUX18_1", - "CLK_BUFG_IMUX18_2", - "CLK_BUFG_IMUX18_3", - "CLK_BUFG_IMUX19_0", - "CLK_BUFG_IMUX19_1", - "CLK_BUFG_IMUX19_2", - "CLK_BUFG_IMUX19_3", - "CLK_BUFG_IMUX1_0", - "CLK_BUFG_IMUX1_1", - "CLK_BUFG_IMUX1_2", - "CLK_BUFG_IMUX1_3", - "CLK_BUFG_IMUX20_0", - "CLK_BUFG_IMUX20_1", - "CLK_BUFG_IMUX20_2", - "CLK_BUFG_IMUX20_3", - "CLK_BUFG_IMUX21_0", - "CLK_BUFG_IMUX21_1", - "CLK_BUFG_IMUX21_2", - "CLK_BUFG_IMUX21_3", - "CLK_BUFG_IMUX22_0", - "CLK_BUFG_IMUX22_1", - "CLK_BUFG_IMUX22_2", - "CLK_BUFG_IMUX22_3", - "CLK_BUFG_IMUX23_0", - "CLK_BUFG_IMUX23_1", - "CLK_BUFG_IMUX23_2", - "CLK_BUFG_IMUX23_3", - "CLK_BUFG_IMUX24_0", - "CLK_BUFG_IMUX24_1", - "CLK_BUFG_IMUX24_2", - "CLK_BUFG_IMUX24_3", - "CLK_BUFG_IMUX25_0", - "CLK_BUFG_IMUX25_1", - "CLK_BUFG_IMUX25_2", - "CLK_BUFG_IMUX25_3", - "CLK_BUFG_IMUX26_0", - "CLK_BUFG_IMUX26_1", - "CLK_BUFG_IMUX26_2", - "CLK_BUFG_IMUX26_3", - "CLK_BUFG_IMUX27_0", - "CLK_BUFG_IMUX27_1", - "CLK_BUFG_IMUX27_2", - "CLK_BUFG_IMUX27_3", - "CLK_BUFG_IMUX28_0", - "CLK_BUFG_IMUX28_1", - "CLK_BUFG_IMUX28_2", - "CLK_BUFG_IMUX28_3", - "CLK_BUFG_IMUX29_0", - "CLK_BUFG_IMUX29_1", - "CLK_BUFG_IMUX29_2", - "CLK_BUFG_IMUX29_3", - "CLK_BUFG_IMUX2_0", - "CLK_BUFG_IMUX2_1", - "CLK_BUFG_IMUX2_2", - "CLK_BUFG_IMUX2_3", - "CLK_BUFG_IMUX30_0", - "CLK_BUFG_IMUX30_1", - "CLK_BUFG_IMUX30_2", - "CLK_BUFG_IMUX30_3", - "CLK_BUFG_IMUX31_0", - "CLK_BUFG_IMUX31_1", - "CLK_BUFG_IMUX31_2", - "CLK_BUFG_IMUX31_3", - "CLK_BUFG_IMUX32_0", - "CLK_BUFG_IMUX32_1", - "CLK_BUFG_IMUX32_2", - "CLK_BUFG_IMUX32_3", - "CLK_BUFG_IMUX33_0", - "CLK_BUFG_IMUX33_1", - "CLK_BUFG_IMUX33_2", - "CLK_BUFG_IMUX33_3", - "CLK_BUFG_IMUX34_0", - "CLK_BUFG_IMUX34_1", - "CLK_BUFG_IMUX34_2", - "CLK_BUFG_IMUX34_3", - "CLK_BUFG_IMUX35_0", - "CLK_BUFG_IMUX35_1", - "CLK_BUFG_IMUX35_2", - "CLK_BUFG_IMUX35_3", - "CLK_BUFG_IMUX36_0", - "CLK_BUFG_IMUX36_1", - "CLK_BUFG_IMUX36_2", - "CLK_BUFG_IMUX36_3", - "CLK_BUFG_IMUX37_0", - "CLK_BUFG_IMUX37_1", - "CLK_BUFG_IMUX37_2", - "CLK_BUFG_IMUX37_3", - "CLK_BUFG_IMUX38_0", - "CLK_BUFG_IMUX38_1", - "CLK_BUFG_IMUX38_2", - "CLK_BUFG_IMUX38_3", - "CLK_BUFG_IMUX39_0", - "CLK_BUFG_IMUX39_1", - "CLK_BUFG_IMUX39_2", - "CLK_BUFG_IMUX39_3", - "CLK_BUFG_IMUX3_0", - "CLK_BUFG_IMUX3_1", - "CLK_BUFG_IMUX3_2", - "CLK_BUFG_IMUX3_3", - "CLK_BUFG_IMUX40_0", - "CLK_BUFG_IMUX40_1", - "CLK_BUFG_IMUX40_2", - "CLK_BUFG_IMUX40_3", - "CLK_BUFG_IMUX41_0", - "CLK_BUFG_IMUX41_1", - "CLK_BUFG_IMUX41_2", - "CLK_BUFG_IMUX41_3", - "CLK_BUFG_IMUX42_0", - "CLK_BUFG_IMUX42_1", - "CLK_BUFG_IMUX42_2", - "CLK_BUFG_IMUX42_3", - "CLK_BUFG_IMUX43_0", - "CLK_BUFG_IMUX43_1", - "CLK_BUFG_IMUX43_2", - "CLK_BUFG_IMUX43_3", - "CLK_BUFG_IMUX44_0", - "CLK_BUFG_IMUX44_1", - "CLK_BUFG_IMUX44_2", - "CLK_BUFG_IMUX44_3", - "CLK_BUFG_IMUX45_0", - "CLK_BUFG_IMUX45_1", - "CLK_BUFG_IMUX45_2", - "CLK_BUFG_IMUX45_3", - "CLK_BUFG_IMUX46_0", - "CLK_BUFG_IMUX46_1", - "CLK_BUFG_IMUX46_2", - "CLK_BUFG_IMUX46_3", - "CLK_BUFG_IMUX47_0", - "CLK_BUFG_IMUX47_1", - "CLK_BUFG_IMUX47_2", - "CLK_BUFG_IMUX47_3", - "CLK_BUFG_IMUX4_0", - "CLK_BUFG_IMUX4_1", - "CLK_BUFG_IMUX4_2", - "CLK_BUFG_IMUX4_3", - "CLK_BUFG_IMUX5_0", - "CLK_BUFG_IMUX5_1", - "CLK_BUFG_IMUX5_2", - "CLK_BUFG_IMUX5_3", - "CLK_BUFG_IMUX6_0", - "CLK_BUFG_IMUX6_1", - "CLK_BUFG_IMUX6_2", - "CLK_BUFG_IMUX6_3", - "CLK_BUFG_IMUX7_0", - "CLK_BUFG_IMUX7_1", - "CLK_BUFG_IMUX7_2", - "CLK_BUFG_IMUX7_3", - "CLK_BUFG_IMUX8_0", - "CLK_BUFG_IMUX8_1", - "CLK_BUFG_IMUX8_2", - "CLK_BUFG_IMUX8_3", - "CLK_BUFG_IMUX9_0", - "CLK_BUFG_IMUX9_1", - "CLK_BUFG_IMUX9_2", - "CLK_BUFG_IMUX9_3", - "CLK_BUFG_LOGIC_OUTS_B0_0", - "CLK_BUFG_LOGIC_OUTS_B0_1", - "CLK_BUFG_LOGIC_OUTS_B0_2", - "CLK_BUFG_LOGIC_OUTS_B0_3", - "CLK_BUFG_LOGIC_OUTS_B10_0", - "CLK_BUFG_LOGIC_OUTS_B10_1", - "CLK_BUFG_LOGIC_OUTS_B10_2", - "CLK_BUFG_LOGIC_OUTS_B10_3", - "CLK_BUFG_LOGIC_OUTS_B11_0", - "CLK_BUFG_LOGIC_OUTS_B11_1", - "CLK_BUFG_LOGIC_OUTS_B11_2", - "CLK_BUFG_LOGIC_OUTS_B11_3", - "CLK_BUFG_LOGIC_OUTS_B12_0", - "CLK_BUFG_LOGIC_OUTS_B12_1", - "CLK_BUFG_LOGIC_OUTS_B12_2", - "CLK_BUFG_LOGIC_OUTS_B12_3", - "CLK_BUFG_LOGIC_OUTS_B13_0", - "CLK_BUFG_LOGIC_OUTS_B13_1", - "CLK_BUFG_LOGIC_OUTS_B13_2", - "CLK_BUFG_LOGIC_OUTS_B13_3", - "CLK_BUFG_LOGIC_OUTS_B14_0", - "CLK_BUFG_LOGIC_OUTS_B14_1", - "CLK_BUFG_LOGIC_OUTS_B14_2", - "CLK_BUFG_LOGIC_OUTS_B14_3", - "CLK_BUFG_LOGIC_OUTS_B15_0", - "CLK_BUFG_LOGIC_OUTS_B15_1", - "CLK_BUFG_LOGIC_OUTS_B15_2", - "CLK_BUFG_LOGIC_OUTS_B15_3", - "CLK_BUFG_LOGIC_OUTS_B16_0", - "CLK_BUFG_LOGIC_OUTS_B16_1", - "CLK_BUFG_LOGIC_OUTS_B16_2", - "CLK_BUFG_LOGIC_OUTS_B16_3", - "CLK_BUFG_LOGIC_OUTS_B17_0", - "CLK_BUFG_LOGIC_OUTS_B17_1", - "CLK_BUFG_LOGIC_OUTS_B17_2", - "CLK_BUFG_LOGIC_OUTS_B17_3", - "CLK_BUFG_LOGIC_OUTS_B18_0", - "CLK_BUFG_LOGIC_OUTS_B18_1", - "CLK_BUFG_LOGIC_OUTS_B18_2", - "CLK_BUFG_LOGIC_OUTS_B18_3", - "CLK_BUFG_LOGIC_OUTS_B19_0", - "CLK_BUFG_LOGIC_OUTS_B19_1", - "CLK_BUFG_LOGIC_OUTS_B19_2", - "CLK_BUFG_LOGIC_OUTS_B19_3", - "CLK_BUFG_LOGIC_OUTS_B1_0", - "CLK_BUFG_LOGIC_OUTS_B1_1", - "CLK_BUFG_LOGIC_OUTS_B1_2", - "CLK_BUFG_LOGIC_OUTS_B1_3", - "CLK_BUFG_LOGIC_OUTS_B20_0", - "CLK_BUFG_LOGIC_OUTS_B20_1", - "CLK_BUFG_LOGIC_OUTS_B20_2", - "CLK_BUFG_LOGIC_OUTS_B20_3", - "CLK_BUFG_LOGIC_OUTS_B21_0", - "CLK_BUFG_LOGIC_OUTS_B21_1", - "CLK_BUFG_LOGIC_OUTS_B21_2", - "CLK_BUFG_LOGIC_OUTS_B21_3", - "CLK_BUFG_LOGIC_OUTS_B22_0", - "CLK_BUFG_LOGIC_OUTS_B22_1", - "CLK_BUFG_LOGIC_OUTS_B22_2", - "CLK_BUFG_LOGIC_OUTS_B22_3", - "CLK_BUFG_LOGIC_OUTS_B23_0", - "CLK_BUFG_LOGIC_OUTS_B23_1", - "CLK_BUFG_LOGIC_OUTS_B23_2", - "CLK_BUFG_LOGIC_OUTS_B23_3", - "CLK_BUFG_LOGIC_OUTS_B2_0", - "CLK_BUFG_LOGIC_OUTS_B2_1", - "CLK_BUFG_LOGIC_OUTS_B2_2", - "CLK_BUFG_LOGIC_OUTS_B2_3", - "CLK_BUFG_LOGIC_OUTS_B3_0", - "CLK_BUFG_LOGIC_OUTS_B3_1", - "CLK_BUFG_LOGIC_OUTS_B3_2", - "CLK_BUFG_LOGIC_OUTS_B3_3", - "CLK_BUFG_LOGIC_OUTS_B4_0", - "CLK_BUFG_LOGIC_OUTS_B4_1", - "CLK_BUFG_LOGIC_OUTS_B4_2", - "CLK_BUFG_LOGIC_OUTS_B4_3", - "CLK_BUFG_LOGIC_OUTS_B5_0", - "CLK_BUFG_LOGIC_OUTS_B5_1", - "CLK_BUFG_LOGIC_OUTS_B5_2", - "CLK_BUFG_LOGIC_OUTS_B5_3", - "CLK_BUFG_LOGIC_OUTS_B6_0", - "CLK_BUFG_LOGIC_OUTS_B6_1", - "CLK_BUFG_LOGIC_OUTS_B6_2", - "CLK_BUFG_LOGIC_OUTS_B6_3", - "CLK_BUFG_LOGIC_OUTS_B7_0", - "CLK_BUFG_LOGIC_OUTS_B7_1", - "CLK_BUFG_LOGIC_OUTS_B7_2", - "CLK_BUFG_LOGIC_OUTS_B7_3", - "CLK_BUFG_LOGIC_OUTS_B8_0", - "CLK_BUFG_LOGIC_OUTS_B8_1", - "CLK_BUFG_LOGIC_OUTS_B8_2", - "CLK_BUFG_LOGIC_OUTS_B8_3", - "CLK_BUFG_LOGIC_OUTS_B9_0", - "CLK_BUFG_LOGIC_OUTS_B9_1", - "CLK_BUFG_LOGIC_OUTS_B9_2", - "CLK_BUFG_LOGIC_OUTS_B9_3", - "CLK_BUFG_R_BUFGCTRL0_CE0", - "CLK_BUFG_R_BUFGCTRL0_CE1", - "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "CLK_BUFG_R_BUFGCTRL0_S0", - "CLK_BUFG_R_BUFGCTRL0_S1", - "CLK_BUFG_R_BUFGCTRL10_CE0", - "CLK_BUFG_R_BUFGCTRL10_CE1", - "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "CLK_BUFG_R_BUFGCTRL10_S0", - "CLK_BUFG_R_BUFGCTRL10_S1", - "CLK_BUFG_R_BUFGCTRL11_CE0", - "CLK_BUFG_R_BUFGCTRL11_CE1", - "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "CLK_BUFG_R_BUFGCTRL11_S0", - "CLK_BUFG_R_BUFGCTRL11_S1", - "CLK_BUFG_R_BUFGCTRL12_CE0", - "CLK_BUFG_R_BUFGCTRL12_CE1", - "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "CLK_BUFG_R_BUFGCTRL12_S0", - "CLK_BUFG_R_BUFGCTRL12_S1", - "CLK_BUFG_R_BUFGCTRL13_CE0", - "CLK_BUFG_R_BUFGCTRL13_CE1", - "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "CLK_BUFG_R_BUFGCTRL13_S0", - "CLK_BUFG_R_BUFGCTRL13_S1", - "CLK_BUFG_R_BUFGCTRL14_CE0", - "CLK_BUFG_R_BUFGCTRL14_CE1", - "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "CLK_BUFG_R_BUFGCTRL14_S0", - "CLK_BUFG_R_BUFGCTRL14_S1", - "CLK_BUFG_R_BUFGCTRL15_CE0", - "CLK_BUFG_R_BUFGCTRL15_CE1", - "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "CLK_BUFG_R_BUFGCTRL15_S0", - "CLK_BUFG_R_BUFGCTRL15_S1", - "CLK_BUFG_R_BUFGCTRL1_CE0", - "CLK_BUFG_R_BUFGCTRL1_CE1", - "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "CLK_BUFG_R_BUFGCTRL1_S0", - "CLK_BUFG_R_BUFGCTRL1_S1", - "CLK_BUFG_R_BUFGCTRL2_CE0", - "CLK_BUFG_R_BUFGCTRL2_CE1", - "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "CLK_BUFG_R_BUFGCTRL2_S0", - "CLK_BUFG_R_BUFGCTRL2_S1", - "CLK_BUFG_R_BUFGCTRL3_CE0", - "CLK_BUFG_R_BUFGCTRL3_CE1", - "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "CLK_BUFG_R_BUFGCTRL3_S0", - "CLK_BUFG_R_BUFGCTRL3_S1", - "CLK_BUFG_R_BUFGCTRL4_CE0", - "CLK_BUFG_R_BUFGCTRL4_CE1", - "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "CLK_BUFG_R_BUFGCTRL4_S0", - "CLK_BUFG_R_BUFGCTRL4_S1", - "CLK_BUFG_R_BUFGCTRL5_CE0", - "CLK_BUFG_R_BUFGCTRL5_CE1", - "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "CLK_BUFG_R_BUFGCTRL5_S0", - "CLK_BUFG_R_BUFGCTRL5_S1", - "CLK_BUFG_R_BUFGCTRL6_CE0", - "CLK_BUFG_R_BUFGCTRL6_CE1", - "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "CLK_BUFG_R_BUFGCTRL6_S0", - "CLK_BUFG_R_BUFGCTRL6_S1", - "CLK_BUFG_R_BUFGCTRL7_CE0", - "CLK_BUFG_R_BUFGCTRL7_CE1", - "CLK_BUFG_R_BUFGCTRL7_IGNORE0", - "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "CLK_BUFG_R_BUFGCTRL7_S0", - "CLK_BUFG_R_BUFGCTRL7_S1", - "CLK_BUFG_R_BUFGCTRL8_CE0", - "CLK_BUFG_R_BUFGCTRL8_CE1", - "CLK_BUFG_R_BUFGCTRL8_IGNORE0", - "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "CLK_BUFG_R_BUFGCTRL8_S0", - "CLK_BUFG_R_BUFGCTRL8_S1", - "CLK_BUFG_R_BUFGCTRL9_CE0", - "CLK_BUFG_R_BUFGCTRL9_CE1", - "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "CLK_BUFG_R_BUFGCTRL9_S0", - "CLK_BUFG_R_BUFGCTRL9_S1", - "CLK_BUFG_R_CK_FB_TEST0_0", - "CLK_BUFG_R_CK_FB_TEST0_1", - "CLK_BUFG_R_CK_FB_TEST0_10", - "CLK_BUFG_R_CK_FB_TEST0_11", - "CLK_BUFG_R_CK_FB_TEST0_12", - "CLK_BUFG_R_CK_FB_TEST0_13", - "CLK_BUFG_R_CK_FB_TEST0_14", - "CLK_BUFG_R_CK_FB_TEST0_15", - "CLK_BUFG_R_CK_FB_TEST0_2", - "CLK_BUFG_R_CK_FB_TEST0_3", - "CLK_BUFG_R_CK_FB_TEST0_4", - "CLK_BUFG_R_CK_FB_TEST0_5", - "CLK_BUFG_R_CK_FB_TEST0_6", - "CLK_BUFG_R_CK_FB_TEST0_7", - "CLK_BUFG_R_CK_FB_TEST0_8", - "CLK_BUFG_R_CK_FB_TEST0_9", - "CLK_BUFG_R_CK_FB_TEST1_0", - "CLK_BUFG_R_CK_FB_TEST1_1", - "CLK_BUFG_R_CK_FB_TEST1_10", - "CLK_BUFG_R_CK_FB_TEST1_11", - "CLK_BUFG_R_CK_FB_TEST1_12", - "CLK_BUFG_R_CK_FB_TEST1_13", - "CLK_BUFG_R_CK_FB_TEST1_14", - "CLK_BUFG_R_CK_FB_TEST1_15", - "CLK_BUFG_R_CK_FB_TEST1_2", - "CLK_BUFG_R_CK_FB_TEST1_3", - "CLK_BUFG_R_CK_FB_TEST1_4", - "CLK_BUFG_R_CK_FB_TEST1_5", - "CLK_BUFG_R_CK_FB_TEST1_6", - "CLK_BUFG_R_CK_FB_TEST1_7", - "CLK_BUFG_R_CK_FB_TEST1_8", - "CLK_BUFG_R_CK_FB_TEST1_9", - "CLK_BUFG_R_FBG_OUT0", - "CLK_BUFG_R_FBG_OUT1", - "CLK_BUFG_R_FBG_OUT10", - "CLK_BUFG_R_FBG_OUT11", - "CLK_BUFG_R_FBG_OUT12", - "CLK_BUFG_R_FBG_OUT13", - "CLK_BUFG_R_FBG_OUT14", - "CLK_BUFG_R_FBG_OUT15", - "CLK_BUFG_R_FBG_OUT2", - "CLK_BUFG_R_FBG_OUT3", - "CLK_BUFG_R_FBG_OUT4", - "CLK_BUFG_R_FBG_OUT5", - "CLK_BUFG_R_FBG_OUT6", - "CLK_BUFG_R_FBG_OUT7", - "CLK_BUFG_R_FBG_OUT8", - "CLK_BUFG_R_FBG_OUT9", - "CLK_BUFG_TOP_R_CK_MUXED0", - "CLK_BUFG_TOP_R_CK_MUXED1", - "CLK_BUFG_TOP_R_CK_MUXED10", - "CLK_BUFG_TOP_R_CK_MUXED11", - "CLK_BUFG_TOP_R_CK_MUXED12", - "CLK_BUFG_TOP_R_CK_MUXED13", - "CLK_BUFG_TOP_R_CK_MUXED14", - "CLK_BUFG_TOP_R_CK_MUXED15", - "CLK_BUFG_TOP_R_CK_MUXED16", - "CLK_BUFG_TOP_R_CK_MUXED17", - "CLK_BUFG_TOP_R_CK_MUXED18", - "CLK_BUFG_TOP_R_CK_MUXED19", - "CLK_BUFG_TOP_R_CK_MUXED2", - "CLK_BUFG_TOP_R_CK_MUXED20", - "CLK_BUFG_TOP_R_CK_MUXED21", - "CLK_BUFG_TOP_R_CK_MUXED22", - "CLK_BUFG_TOP_R_CK_MUXED23", - "CLK_BUFG_TOP_R_CK_MUXED24", - "CLK_BUFG_TOP_R_CK_MUXED25", - "CLK_BUFG_TOP_R_CK_MUXED26", - "CLK_BUFG_TOP_R_CK_MUXED27", - "CLK_BUFG_TOP_R_CK_MUXED28", - "CLK_BUFG_TOP_R_CK_MUXED29", - "CLK_BUFG_TOP_R_CK_MUXED3", - "CLK_BUFG_TOP_R_CK_MUXED30", - "CLK_BUFG_TOP_R_CK_MUXED31", - "CLK_BUFG_TOP_R_CK_MUXED4", - "CLK_BUFG_TOP_R_CK_MUXED5", - "CLK_BUFG_TOP_R_CK_MUXED6", - "CLK_BUFG_TOP_R_CK_MUXED7", - "CLK_BUFG_TOP_R_CK_MUXED8", - "CLK_BUFG_TOP_R_CK_MUXED9", - "CLK_HROW_BLOCK_OUTS_B0_0", - "CLK_HROW_BLOCK_OUTS_B0_1", - "CLK_HROW_BLOCK_OUTS_B0_2", - "CLK_HROW_BLOCK_OUTS_B0_3", - "CLK_HROW_BLOCK_OUTS_B1_0", - "CLK_HROW_BLOCK_OUTS_B1_1", - "CLK_HROW_BLOCK_OUTS_B1_2", - "CLK_HROW_BLOCK_OUTS_B1_3", - "CLK_HROW_BLOCK_OUTS_B2_0", - "CLK_HROW_BLOCK_OUTS_B2_1", - "CLK_HROW_BLOCK_OUTS_B2_2", - "CLK_HROW_BLOCK_OUTS_B2_3", - "CLK_HROW_BLOCK_OUTS_B3_0", - "CLK_HROW_BLOCK_OUTS_B3_1", - "CLK_HROW_BLOCK_OUTS_B3_2", - "CLK_HROW_BLOCK_OUTS_B3_3", - "CLK_HROW_BYP0_0", - "CLK_HROW_BYP0_1", - "CLK_HROW_BYP0_2", - "CLK_HROW_BYP0_3", - "CLK_HROW_BYP1_0", - "CLK_HROW_BYP1_1", - "CLK_HROW_BYP1_2", - "CLK_HROW_BYP1_3", - "CLK_HROW_BYP2_0", - "CLK_HROW_BYP2_1", - "CLK_HROW_BYP2_2", - "CLK_HROW_BYP2_3", - "CLK_HROW_BYP3_0", - "CLK_HROW_BYP3_1", - "CLK_HROW_BYP3_2", - "CLK_HROW_BYP3_3", - "CLK_HROW_BYP4_0", - "CLK_HROW_BYP4_1", - "CLK_HROW_BYP4_2", - "CLK_HROW_BYP4_3", - "CLK_HROW_BYP5_0", - "CLK_HROW_BYP5_1", - "CLK_HROW_BYP5_2", - "CLK_HROW_BYP5_3", - "CLK_HROW_BYP6_0", - "CLK_HROW_BYP6_1", - "CLK_HROW_BYP6_2", - "CLK_HROW_BYP6_3", - "CLK_HROW_BYP7_0", - "CLK_HROW_BYP7_1", - "CLK_HROW_BYP7_2", - "CLK_HROW_BYP7_3", - "CLK_HROW_CLK0_0", - "CLK_HROW_CLK0_1", - "CLK_HROW_CLK0_2", - "CLK_HROW_CLK0_3", - "CLK_HROW_CLK1_0", - "CLK_HROW_CLK1_1", - "CLK_HROW_CLK1_2", - "CLK_HROW_CLK1_3", - "CLK_HROW_CTRL0_0", - "CLK_HROW_CTRL0_1", - "CLK_HROW_CTRL0_2", - "CLK_HROW_CTRL0_3", - "CLK_HROW_CTRL1_0", - "CLK_HROW_CTRL1_1", - "CLK_HROW_CTRL1_2", - "CLK_HROW_CTRL1_3", - "CLK_HROW_EE2A0_0", - "CLK_HROW_EE2A0_1", - "CLK_HROW_EE2A0_2", - "CLK_HROW_EE2A0_3", - "CLK_HROW_EE2A1_0", - "CLK_HROW_EE2A1_1", - "CLK_HROW_EE2A1_2", - "CLK_HROW_EE2A1_3", - "CLK_HROW_EE2A2_0", - "CLK_HROW_EE2A2_1", - "CLK_HROW_EE2A2_2", - "CLK_HROW_EE2A2_3", - "CLK_HROW_EE2A3_0", - "CLK_HROW_EE2A3_1", - "CLK_HROW_EE2A3_2", - "CLK_HROW_EE2A3_3", - "CLK_HROW_EE2BEG0_0", - "CLK_HROW_EE2BEG0_1", - "CLK_HROW_EE2BEG0_2", - "CLK_HROW_EE2BEG0_3", - "CLK_HROW_EE2BEG1_0", - "CLK_HROW_EE2BEG1_1", - "CLK_HROW_EE2BEG1_2", - "CLK_HROW_EE2BEG1_3", - "CLK_HROW_EE2BEG2_0", - "CLK_HROW_EE2BEG2_1", - "CLK_HROW_EE2BEG2_2", - "CLK_HROW_EE2BEG2_3", - "CLK_HROW_EE2BEG3_0", - "CLK_HROW_EE2BEG3_1", - "CLK_HROW_EE2BEG3_2", - "CLK_HROW_EE2BEG3_3", - "CLK_HROW_EE4A0_0", - "CLK_HROW_EE4A0_1", - "CLK_HROW_EE4A0_2", - "CLK_HROW_EE4A0_3", - "CLK_HROW_EE4A1_0", - "CLK_HROW_EE4A1_1", - "CLK_HROW_EE4A1_2", - "CLK_HROW_EE4A1_3", - "CLK_HROW_EE4A2_0", - "CLK_HROW_EE4A2_1", - "CLK_HROW_EE4A2_2", - "CLK_HROW_EE4A2_3", - "CLK_HROW_EE4A3_0", - "CLK_HROW_EE4A3_1", - "CLK_HROW_EE4A3_2", - "CLK_HROW_EE4A3_3", - "CLK_HROW_EE4B0_0", - "CLK_HROW_EE4B0_1", - "CLK_HROW_EE4B0_2", - "CLK_HROW_EE4B0_3", - "CLK_HROW_EE4B1_0", - "CLK_HROW_EE4B1_1", - "CLK_HROW_EE4B1_2", - "CLK_HROW_EE4B1_3", - "CLK_HROW_EE4B2_0", - "CLK_HROW_EE4B2_1", - "CLK_HROW_EE4B2_2", - "CLK_HROW_EE4B2_3", - "CLK_HROW_EE4B3_0", - "CLK_HROW_EE4B3_1", - "CLK_HROW_EE4B3_2", - "CLK_HROW_EE4B3_3", - "CLK_HROW_EE4BEG0_0", - "CLK_HROW_EE4BEG0_1", - "CLK_HROW_EE4BEG0_2", - "CLK_HROW_EE4BEG0_3", - "CLK_HROW_EE4BEG1_0", - "CLK_HROW_EE4BEG1_1", - "CLK_HROW_EE4BEG1_2", - "CLK_HROW_EE4BEG1_3", - "CLK_HROW_EE4BEG2_0", - "CLK_HROW_EE4BEG2_1", - "CLK_HROW_EE4BEG2_2", - "CLK_HROW_EE4BEG2_3", - "CLK_HROW_EE4BEG3_0", - "CLK_HROW_EE4BEG3_1", - "CLK_HROW_EE4BEG3_2", - "CLK_HROW_EE4BEG3_3", - "CLK_HROW_EE4C0_0", - "CLK_HROW_EE4C0_1", - "CLK_HROW_EE4C0_2", - "CLK_HROW_EE4C0_3", - "CLK_HROW_EE4C1_0", - "CLK_HROW_EE4C1_1", - "CLK_HROW_EE4C1_2", - "CLK_HROW_EE4C1_3", - "CLK_HROW_EE4C2_0", - "CLK_HROW_EE4C2_1", - "CLK_HROW_EE4C2_2", - "CLK_HROW_EE4C2_3", - "CLK_HROW_EE4C3_0", - "CLK_HROW_EE4C3_1", - "CLK_HROW_EE4C3_2", - "CLK_HROW_EE4C3_3", - "CLK_HROW_EL1BEG0_0", - "CLK_HROW_EL1BEG0_1", - "CLK_HROW_EL1BEG0_2", - "CLK_HROW_EL1BEG0_3", - "CLK_HROW_EL1BEG1_0", - "CLK_HROW_EL1BEG1_1", - "CLK_HROW_EL1BEG1_2", - "CLK_HROW_EL1BEG1_3", - "CLK_HROW_EL1BEG2_0", - "CLK_HROW_EL1BEG2_1", - "CLK_HROW_EL1BEG2_2", - "CLK_HROW_EL1BEG2_3", - "CLK_HROW_EL1BEG3_0", - "CLK_HROW_EL1BEG3_1", - "CLK_HROW_EL1BEG3_2", - "CLK_HROW_EL1BEG3_3", - "CLK_HROW_ER1BEG0_0", - "CLK_HROW_ER1BEG0_1", - "CLK_HROW_ER1BEG0_2", - "CLK_HROW_ER1BEG0_3", - "CLK_HROW_ER1BEG1_0", - "CLK_HROW_ER1BEG1_1", - "CLK_HROW_ER1BEG1_2", - "CLK_HROW_ER1BEG1_3", - "CLK_HROW_ER1BEG2_0", - "CLK_HROW_ER1BEG2_1", - "CLK_HROW_ER1BEG2_2", - "CLK_HROW_ER1BEG2_3", - "CLK_HROW_ER1BEG3_0", - "CLK_HROW_ER1BEG3_1", - "CLK_HROW_ER1BEG3_2", - "CLK_HROW_ER1BEG3_3", - "CLK_HROW_FAN0_0", - "CLK_HROW_FAN0_1", - "CLK_HROW_FAN0_2", - "CLK_HROW_FAN0_3", - "CLK_HROW_FAN1_0", - "CLK_HROW_FAN1_1", - "CLK_HROW_FAN1_2", - "CLK_HROW_FAN1_3", - "CLK_HROW_FAN2_0", - "CLK_HROW_FAN2_1", - "CLK_HROW_FAN2_2", - "CLK_HROW_FAN2_3", - "CLK_HROW_FAN3_0", - "CLK_HROW_FAN3_1", - "CLK_HROW_FAN3_2", - "CLK_HROW_FAN3_3", - "CLK_HROW_FAN4_0", - "CLK_HROW_FAN4_1", - "CLK_HROW_FAN4_2", - "CLK_HROW_FAN4_3", - "CLK_HROW_FAN5_0", - "CLK_HROW_FAN5_1", - "CLK_HROW_FAN5_2", - "CLK_HROW_FAN5_3", - "CLK_HROW_FAN6_0", - "CLK_HROW_FAN6_1", - "CLK_HROW_FAN6_2", - "CLK_HROW_FAN6_3", - "CLK_HROW_FAN7_0", - "CLK_HROW_FAN7_1", - "CLK_HROW_FAN7_2", - "CLK_HROW_FAN7_3", - "CLK_HROW_LH10_0", - "CLK_HROW_LH10_1", - "CLK_HROW_LH10_2", - "CLK_HROW_LH10_3", - "CLK_HROW_LH11_0", - "CLK_HROW_LH11_1", - "CLK_HROW_LH11_2", - "CLK_HROW_LH11_3", - "CLK_HROW_LH12_0", - "CLK_HROW_LH12_1", - "CLK_HROW_LH12_2", - "CLK_HROW_LH12_3", - "CLK_HROW_LH1_0", - "CLK_HROW_LH1_1", - "CLK_HROW_LH1_2", - "CLK_HROW_LH1_3", - "CLK_HROW_LH2_0", - "CLK_HROW_LH2_1", - "CLK_HROW_LH2_2", - "CLK_HROW_LH2_3", - "CLK_HROW_LH3_0", - "CLK_HROW_LH3_1", - "CLK_HROW_LH3_2", - "CLK_HROW_LH3_3", - "CLK_HROW_LH4_0", - "CLK_HROW_LH4_1", - "CLK_HROW_LH4_2", - "CLK_HROW_LH4_3", - "CLK_HROW_LH5_0", - "CLK_HROW_LH5_1", - "CLK_HROW_LH5_2", - "CLK_HROW_LH5_3", - "CLK_HROW_LH6_0", - "CLK_HROW_LH6_1", - "CLK_HROW_LH6_2", - "CLK_HROW_LH6_3", - "CLK_HROW_LH7_0", - "CLK_HROW_LH7_1", - "CLK_HROW_LH7_2", - "CLK_HROW_LH7_3", - "CLK_HROW_LH8_0", - "CLK_HROW_LH8_1", - "CLK_HROW_LH8_2", - "CLK_HROW_LH8_3", - "CLK_HROW_LH9_0", - "CLK_HROW_LH9_1", - "CLK_HROW_LH9_2", - "CLK_HROW_LH9_3", - "CLK_HROW_MONITOR_N_0", - "CLK_HROW_MONITOR_N_1", - "CLK_HROW_MONITOR_N_2", - "CLK_HROW_MONITOR_N_3", - "CLK_HROW_MONITOR_P_0", - "CLK_HROW_MONITOR_P_1", - "CLK_HROW_MONITOR_P_2", - "CLK_HROW_MONITOR_P_3", - "CLK_HROW_NE2A0_0", - "CLK_HROW_NE2A0_1", - "CLK_HROW_NE2A0_2", - "CLK_HROW_NE2A0_3", - "CLK_HROW_NE2A1_0", - "CLK_HROW_NE2A1_1", - "CLK_HROW_NE2A1_2", - "CLK_HROW_NE2A1_3", - "CLK_HROW_NE2A2_0", - "CLK_HROW_NE2A2_1", - "CLK_HROW_NE2A2_2", - "CLK_HROW_NE2A2_3", - "CLK_HROW_NE2A3_0", - "CLK_HROW_NE2A3_1", - "CLK_HROW_NE2A3_2", - "CLK_HROW_NE2A3_3", - "CLK_HROW_NE4BEG0_0", - "CLK_HROW_NE4BEG0_1", - "CLK_HROW_NE4BEG0_2", - "CLK_HROW_NE4BEG0_3", - "CLK_HROW_NE4BEG1_0", - "CLK_HROW_NE4BEG1_1", - "CLK_HROW_NE4BEG1_2", - "CLK_HROW_NE4BEG1_3", - "CLK_HROW_NE4BEG2_0", - "CLK_HROW_NE4BEG2_1", - "CLK_HROW_NE4BEG2_2", - "CLK_HROW_NE4BEG2_3", - "CLK_HROW_NE4BEG3_0", - "CLK_HROW_NE4BEG3_1", - "CLK_HROW_NE4BEG3_2", - "CLK_HROW_NE4BEG3_3", - "CLK_HROW_NE4C0_0", - "CLK_HROW_NE4C0_1", - "CLK_HROW_NE4C0_2", - "CLK_HROW_NE4C0_3", - "CLK_HROW_NE4C1_0", - "CLK_HROW_NE4C1_1", - "CLK_HROW_NE4C1_2", - "CLK_HROW_NE4C1_3", - "CLK_HROW_NE4C2_0", - "CLK_HROW_NE4C2_1", - "CLK_HROW_NE4C2_2", - "CLK_HROW_NE4C2_3", - "CLK_HROW_NE4C3_0", - "CLK_HROW_NE4C3_1", - "CLK_HROW_NE4C3_2", - "CLK_HROW_NE4C3_3", - "CLK_HROW_NW2A0_0", - "CLK_HROW_NW2A0_1", - "CLK_HROW_NW2A0_2", - "CLK_HROW_NW2A0_3", - "CLK_HROW_NW2A1_0", - "CLK_HROW_NW2A1_1", - "CLK_HROW_NW2A1_2", - "CLK_HROW_NW2A1_3", - "CLK_HROW_NW2A2_0", - "CLK_HROW_NW2A2_1", - "CLK_HROW_NW2A2_2", - "CLK_HROW_NW2A2_3", - "CLK_HROW_NW2A3_0", - "CLK_HROW_NW2A3_1", - "CLK_HROW_NW2A3_2", - "CLK_HROW_NW2A3_3", - "CLK_HROW_NW4A0_0", - "CLK_HROW_NW4A0_1", - "CLK_HROW_NW4A0_2", - "CLK_HROW_NW4A0_3", - "CLK_HROW_NW4A1_0", - "CLK_HROW_NW4A1_1", - "CLK_HROW_NW4A1_2", - "CLK_HROW_NW4A1_3", - "CLK_HROW_NW4A2_0", - "CLK_HROW_NW4A2_1", - "CLK_HROW_NW4A2_2", - "CLK_HROW_NW4A2_3", - "CLK_HROW_NW4A3_0", - "CLK_HROW_NW4A3_1", - "CLK_HROW_NW4A3_2", - "CLK_HROW_NW4A3_3", - "CLK_HROW_NW4END0_0", - "CLK_HROW_NW4END0_1", - "CLK_HROW_NW4END0_2", - "CLK_HROW_NW4END0_3", - "CLK_HROW_NW4END1_0", - "CLK_HROW_NW4END1_1", - "CLK_HROW_NW4END1_2", - "CLK_HROW_NW4END1_3", - "CLK_HROW_NW4END2_0", - "CLK_HROW_NW4END2_1", - "CLK_HROW_NW4END2_2", - "CLK_HROW_NW4END2_3", - "CLK_HROW_NW4END3_0", - "CLK_HROW_NW4END3_1", - "CLK_HROW_NW4END3_2", - "CLK_HROW_NW4END3_3", - "CLK_HROW_SE2A0_0", - "CLK_HROW_SE2A0_1", - "CLK_HROW_SE2A0_2", - "CLK_HROW_SE2A0_3", - "CLK_HROW_SE2A1_0", - "CLK_HROW_SE2A1_1", - "CLK_HROW_SE2A1_2", - "CLK_HROW_SE2A1_3", - "CLK_HROW_SE2A2_0", - "CLK_HROW_SE2A2_1", - "CLK_HROW_SE2A2_2", - "CLK_HROW_SE2A2_3", - "CLK_HROW_SE2A3_0", - "CLK_HROW_SE2A3_1", - "CLK_HROW_SE2A3_2", - "CLK_HROW_SE2A3_3", - "CLK_HROW_SE4BEG0_0", - "CLK_HROW_SE4BEG0_1", - "CLK_HROW_SE4BEG0_2", - "CLK_HROW_SE4BEG0_3", - "CLK_HROW_SE4BEG1_0", - "CLK_HROW_SE4BEG1_1", - "CLK_HROW_SE4BEG1_2", - "CLK_HROW_SE4BEG1_3", - "CLK_HROW_SE4BEG2_0", - "CLK_HROW_SE4BEG2_1", - "CLK_HROW_SE4BEG2_2", - "CLK_HROW_SE4BEG2_3", - "CLK_HROW_SE4BEG3_0", - "CLK_HROW_SE4BEG3_1", - "CLK_HROW_SE4BEG3_2", - "CLK_HROW_SE4BEG3_3", - "CLK_HROW_SE4C0_0", - "CLK_HROW_SE4C0_1", - "CLK_HROW_SE4C0_2", - "CLK_HROW_SE4C0_3", - "CLK_HROW_SE4C1_0", - "CLK_HROW_SE4C1_1", - "CLK_HROW_SE4C1_2", - "CLK_HROW_SE4C1_3", - "CLK_HROW_SE4C2_0", - "CLK_HROW_SE4C2_1", - "CLK_HROW_SE4C2_2", - "CLK_HROW_SE4C2_3", - "CLK_HROW_SE4C3_0", - "CLK_HROW_SE4C3_1", - "CLK_HROW_SE4C3_2", - "CLK_HROW_SE4C3_3", - "CLK_HROW_SW2A0_0", - "CLK_HROW_SW2A0_1", - "CLK_HROW_SW2A0_2", - "CLK_HROW_SW2A0_3", - "CLK_HROW_SW2A1_0", - "CLK_HROW_SW2A1_1", - "CLK_HROW_SW2A1_2", - "CLK_HROW_SW2A1_3", - "CLK_HROW_SW2A2_0", - "CLK_HROW_SW2A2_1", - "CLK_HROW_SW2A2_2", - "CLK_HROW_SW2A2_3", - "CLK_HROW_SW2A3_0", - "CLK_HROW_SW2A3_1", - "CLK_HROW_SW2A3_2", - "CLK_HROW_SW2A3_3", - "CLK_HROW_SW4A0_0", - "CLK_HROW_SW4A0_1", - "CLK_HROW_SW4A0_2", - "CLK_HROW_SW4A0_3", - "CLK_HROW_SW4A1_0", - "CLK_HROW_SW4A1_1", - "CLK_HROW_SW4A1_2", - "CLK_HROW_SW4A1_3", - "CLK_HROW_SW4A2_0", - "CLK_HROW_SW4A2_1", - "CLK_HROW_SW4A2_2", - "CLK_HROW_SW4A2_3", - "CLK_HROW_SW4A3_0", - "CLK_HROW_SW4A3_1", - "CLK_HROW_SW4A3_2", - "CLK_HROW_SW4A3_3", - "CLK_HROW_SW4END0_0", - "CLK_HROW_SW4END0_1", - "CLK_HROW_SW4END0_2", - "CLK_HROW_SW4END0_3", - "CLK_HROW_SW4END1_0", - "CLK_HROW_SW4END1_1", - "CLK_HROW_SW4END1_2", - "CLK_HROW_SW4END1_3", - "CLK_HROW_SW4END2_0", - "CLK_HROW_SW4END2_1", - "CLK_HROW_SW4END2_2", - "CLK_HROW_SW4END2_3", - "CLK_HROW_SW4END3_0", - "CLK_HROW_SW4END3_1", - "CLK_HROW_SW4END3_2", - "CLK_HROW_SW4END3_3", - "CLK_HROW_WL1END0_0", - "CLK_HROW_WL1END0_1", - "CLK_HROW_WL1END0_2", - "CLK_HROW_WL1END0_3", - "CLK_HROW_WL1END1_0", - "CLK_HROW_WL1END1_1", - "CLK_HROW_WL1END1_2", - "CLK_HROW_WL1END1_3", - "CLK_HROW_WL1END2_0", - "CLK_HROW_WL1END2_1", - "CLK_HROW_WL1END2_2", - "CLK_HROW_WL1END2_3", - "CLK_HROW_WL1END3_0", - "CLK_HROW_WL1END3_1", - "CLK_HROW_WL1END3_2", - "CLK_HROW_WL1END3_3", - "CLK_HROW_WR1END0_0", - "CLK_HROW_WR1END0_1", - "CLK_HROW_WR1END0_2", - "CLK_HROW_WR1END0_3", - "CLK_HROW_WR1END1_0", - "CLK_HROW_WR1END1_1", - "CLK_HROW_WR1END1_2", - "CLK_HROW_WR1END1_3", - "CLK_HROW_WR1END2_0", - "CLK_HROW_WR1END2_1", - "CLK_HROW_WR1END2_2", - "CLK_HROW_WR1END2_3", - "CLK_HROW_WR1END3_0", - "CLK_HROW_WR1END3_1", - "CLK_HROW_WR1END3_2", - "CLK_HROW_WR1END3_3", - "CLK_HROW_WW2A0_0", - "CLK_HROW_WW2A0_1", - "CLK_HROW_WW2A0_2", - "CLK_HROW_WW2A0_3", - "CLK_HROW_WW2A1_0", - "CLK_HROW_WW2A1_1", - "CLK_HROW_WW2A1_2", - "CLK_HROW_WW2A1_3", - "CLK_HROW_WW2A2_0", - "CLK_HROW_WW2A2_1", - "CLK_HROW_WW2A2_2", - "CLK_HROW_WW2A2_3", - "CLK_HROW_WW2A3_0", - "CLK_HROW_WW2A3_1", - "CLK_HROW_WW2A3_2", - "CLK_HROW_WW2A3_3", - "CLK_HROW_WW2END0_0", - "CLK_HROW_WW2END0_1", - "CLK_HROW_WW2END0_2", - "CLK_HROW_WW2END0_3", - "CLK_HROW_WW2END1_0", - "CLK_HROW_WW2END1_1", - "CLK_HROW_WW2END1_2", - "CLK_HROW_WW2END1_3", - "CLK_HROW_WW2END2_0", - "CLK_HROW_WW2END2_1", - "CLK_HROW_WW2END2_2", - "CLK_HROW_WW2END2_3", - "CLK_HROW_WW2END3_0", - "CLK_HROW_WW2END3_1", - "CLK_HROW_WW2END3_2", - "CLK_HROW_WW2END3_3", - "CLK_HROW_WW4A0_0", - "CLK_HROW_WW4A0_1", - "CLK_HROW_WW4A0_2", - "CLK_HROW_WW4A0_3", - "CLK_HROW_WW4A1_0", - "CLK_HROW_WW4A1_1", - "CLK_HROW_WW4A1_2", - "CLK_HROW_WW4A1_3", - "CLK_HROW_WW4A2_0", - "CLK_HROW_WW4A2_1", - "CLK_HROW_WW4A2_2", - "CLK_HROW_WW4A2_3", - "CLK_HROW_WW4A3_0", - "CLK_HROW_WW4A3_1", - "CLK_HROW_WW4A3_2", - "CLK_HROW_WW4A3_3", - "CLK_HROW_WW4B0_0", - "CLK_HROW_WW4B0_1", - "CLK_HROW_WW4B0_2", - "CLK_HROW_WW4B0_3", - "CLK_HROW_WW4B1_0", - "CLK_HROW_WW4B1_1", - "CLK_HROW_WW4B1_2", - "CLK_HROW_WW4B1_3", - "CLK_HROW_WW4B2_0", - "CLK_HROW_WW4B2_1", - "CLK_HROW_WW4B2_2", - "CLK_HROW_WW4B2_3", - "CLK_HROW_WW4B3_0", - "CLK_HROW_WW4B3_1", - "CLK_HROW_WW4B3_2", - "CLK_HROW_WW4B3_3", - "CLK_HROW_WW4C0_0", - "CLK_HROW_WW4C0_1", - "CLK_HROW_WW4C0_2", - "CLK_HROW_WW4C0_3", - "CLK_HROW_WW4C1_0", - "CLK_HROW_WW4C1_1", - "CLK_HROW_WW4C1_2", - "CLK_HROW_WW4C1_3", - "CLK_HROW_WW4C2_0", - "CLK_HROW_WW4C2_1", - "CLK_HROW_WW4C2_2", - "CLK_HROW_WW4C2_3", - "CLK_HROW_WW4C3_0", - "CLK_HROW_WW4C3_1", - "CLK_HROW_WW4C3_2", - "CLK_HROW_WW4C3_3", - "CLK_HROW_WW4END0_0", - "CLK_HROW_WW4END0_1", - "CLK_HROW_WW4END0_2", - "CLK_HROW_WW4END0_3", - "CLK_HROW_WW4END1_0", - "CLK_HROW_WW4END1_1", - "CLK_HROW_WW4END1_2", - "CLK_HROW_WW4END1_3", - "CLK_HROW_WW4END2_0", - "CLK_HROW_WW4END2_1", - "CLK_HROW_WW4END2_2", - "CLK_HROW_WW4END2_3", - "CLK_HROW_WW4END3_0", - "CLK_HROW_WW4END3_1", - "CLK_HROW_WW4END3_2", - "CLK_HROW_WW4END3_3" - ] + "wires": { + "CLK_BUFG_BUFGCTRL0_I0": null, + "CLK_BUFG_BUFGCTRL0_I1": null, + "CLK_BUFG_BUFGCTRL0_O": null, + "CLK_BUFG_BUFGCTRL10_I0": null, + "CLK_BUFG_BUFGCTRL10_I1": null, + "CLK_BUFG_BUFGCTRL10_O": null, + "CLK_BUFG_BUFGCTRL11_I0": null, + "CLK_BUFG_BUFGCTRL11_I1": null, + "CLK_BUFG_BUFGCTRL11_O": null, + "CLK_BUFG_BUFGCTRL12_I0": null, + "CLK_BUFG_BUFGCTRL12_I1": null, + "CLK_BUFG_BUFGCTRL12_O": null, + "CLK_BUFG_BUFGCTRL13_I0": null, + "CLK_BUFG_BUFGCTRL13_I1": null, + "CLK_BUFG_BUFGCTRL13_O": null, + "CLK_BUFG_BUFGCTRL14_I0": null, + "CLK_BUFG_BUFGCTRL14_I1": null, + "CLK_BUFG_BUFGCTRL14_O": null, + "CLK_BUFG_BUFGCTRL15_I0": null, + "CLK_BUFG_BUFGCTRL15_I1": null, + "CLK_BUFG_BUFGCTRL15_O": null, + "CLK_BUFG_BUFGCTRL1_I0": null, + "CLK_BUFG_BUFGCTRL1_I1": null, + "CLK_BUFG_BUFGCTRL1_O": null, + "CLK_BUFG_BUFGCTRL2_I0": null, + "CLK_BUFG_BUFGCTRL2_I1": null, + "CLK_BUFG_BUFGCTRL2_O": null, + "CLK_BUFG_BUFGCTRL3_I0": null, + "CLK_BUFG_BUFGCTRL3_I1": null, + "CLK_BUFG_BUFGCTRL3_O": null, + "CLK_BUFG_BUFGCTRL4_I0": null, + "CLK_BUFG_BUFGCTRL4_I1": null, + "CLK_BUFG_BUFGCTRL4_O": null, + "CLK_BUFG_BUFGCTRL5_I0": null, + "CLK_BUFG_BUFGCTRL5_I1": null, + "CLK_BUFG_BUFGCTRL5_O": null, + "CLK_BUFG_BUFGCTRL6_I0": null, + "CLK_BUFG_BUFGCTRL6_I1": null, + "CLK_BUFG_BUFGCTRL6_O": null, + "CLK_BUFG_BUFGCTRL7_I0": null, + "CLK_BUFG_BUFGCTRL7_I1": null, + "CLK_BUFG_BUFGCTRL7_O": null, + "CLK_BUFG_BUFGCTRL8_I0": null, + "CLK_BUFG_BUFGCTRL8_I1": null, + "CLK_BUFG_BUFGCTRL8_O": null, + "CLK_BUFG_BUFGCTRL9_I0": null, + "CLK_BUFG_BUFGCTRL9_I1": null, + "CLK_BUFG_BUFGCTRL9_O": null, + "CLK_BUFG_CK_GCLK0": null, + "CLK_BUFG_CK_GCLK1": null, + "CLK_BUFG_CK_GCLK10": null, + "CLK_BUFG_CK_GCLK11": null, + "CLK_BUFG_CK_GCLK12": null, + "CLK_BUFG_CK_GCLK13": null, + "CLK_BUFG_CK_GCLK14": null, + "CLK_BUFG_CK_GCLK15": null, + "CLK_BUFG_CK_GCLK16": null, + "CLK_BUFG_CK_GCLK17": null, + "CLK_BUFG_CK_GCLK18": null, + "CLK_BUFG_CK_GCLK19": null, + "CLK_BUFG_CK_GCLK2": null, + "CLK_BUFG_CK_GCLK20": null, + "CLK_BUFG_CK_GCLK21": null, + "CLK_BUFG_CK_GCLK22": null, + "CLK_BUFG_CK_GCLK23": null, + "CLK_BUFG_CK_GCLK24": null, + "CLK_BUFG_CK_GCLK25": null, + "CLK_BUFG_CK_GCLK26": null, + "CLK_BUFG_CK_GCLK27": null, + "CLK_BUFG_CK_GCLK28": null, + "CLK_BUFG_CK_GCLK29": null, + "CLK_BUFG_CK_GCLK3": null, + "CLK_BUFG_CK_GCLK30": null, + "CLK_BUFG_CK_GCLK31": null, + "CLK_BUFG_CK_GCLK4": null, + "CLK_BUFG_CK_GCLK5": null, + "CLK_BUFG_CK_GCLK6": null, + "CLK_BUFG_CK_GCLK7": null, + "CLK_BUFG_CK_GCLK8": null, + "CLK_BUFG_CK_GCLK9": null, + "CLK_BUFG_IMUX0_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX0_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX0_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX0_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX15_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX15_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX15_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX15_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX16_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX16_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX16_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX16_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX17_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX17_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX17_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX17_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX18_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX18_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX18_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX18_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX19_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX19_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX19_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX19_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX1_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX1_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX1_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX1_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX20_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX20_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX20_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX20_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX21_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX21_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX21_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX21_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX22_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX22_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX22_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX22_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX23_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX23_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX23_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX23_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX24_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX24_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX24_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX24_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX25_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX25_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX25_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX25_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX26_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX26_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX26_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX26_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX27_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX27_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX27_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX27_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX28_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX28_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX28_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX28_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX29_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX29_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX29_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX29_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX2_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX2_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX2_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX2_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX30_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX30_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX30_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX30_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX31_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX31_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX31_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX31_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX32_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX32_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX32_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX32_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX33_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX33_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX33_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX33_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX34_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX34_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX34_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX34_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX35_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX35_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX35_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX35_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX36_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX36_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX36_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX36_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX37_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX37_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX37_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX37_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX38_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX38_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX38_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX38_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX39_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX39_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX39_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX39_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX3_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX3_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX3_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX3_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX40_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX40_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX40_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX40_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX41_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX41_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX41_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX41_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX42_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX42_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX42_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX42_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX43_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX43_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX43_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX43_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX44_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX44_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX44_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX44_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX45_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX45_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX45_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX45_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX46_0": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX46_1": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX46_2": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX46_3": { + "cap": "28.208", + "res": "0.000" + }, + "CLK_BUFG_IMUX47_0": { + "cap": "28.208", + "res": "0.000" + }, + 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"CLK_BUFG_LOGIC_OUTS_B7_3": null, + "CLK_BUFG_LOGIC_OUTS_B8_0": null, + "CLK_BUFG_LOGIC_OUTS_B8_1": null, + "CLK_BUFG_LOGIC_OUTS_B8_2": null, + "CLK_BUFG_LOGIC_OUTS_B8_3": null, + "CLK_BUFG_LOGIC_OUTS_B9_0": null, + "CLK_BUFG_LOGIC_OUTS_B9_1": null, + "CLK_BUFG_LOGIC_OUTS_B9_2": null, + "CLK_BUFG_LOGIC_OUTS_B9_3": null, + "CLK_BUFG_R_BUFGCTRL0_CE0": null, + "CLK_BUFG_R_BUFGCTRL0_CE1": null, + "CLK_BUFG_R_BUFGCTRL0_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL0_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL0_S0": null, + "CLK_BUFG_R_BUFGCTRL0_S1": null, + "CLK_BUFG_R_BUFGCTRL10_CE0": null, + "CLK_BUFG_R_BUFGCTRL10_CE1": null, + "CLK_BUFG_R_BUFGCTRL10_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL10_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL10_S0": null, + "CLK_BUFG_R_BUFGCTRL10_S1": null, + "CLK_BUFG_R_BUFGCTRL11_CE0": null, + "CLK_BUFG_R_BUFGCTRL11_CE1": null, + "CLK_BUFG_R_BUFGCTRL11_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL11_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL11_S0": null, + "CLK_BUFG_R_BUFGCTRL11_S1": null, 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"CLK_BUFG_R_BUFGCTRL1_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL1_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL1_S0": null, + "CLK_BUFG_R_BUFGCTRL1_S1": null, + "CLK_BUFG_R_BUFGCTRL2_CE0": null, + "CLK_BUFG_R_BUFGCTRL2_CE1": null, + "CLK_BUFG_R_BUFGCTRL2_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL2_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL2_S0": null, + "CLK_BUFG_R_BUFGCTRL2_S1": null, + "CLK_BUFG_R_BUFGCTRL3_CE0": null, + "CLK_BUFG_R_BUFGCTRL3_CE1": null, + "CLK_BUFG_R_BUFGCTRL3_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL3_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL3_S0": null, + "CLK_BUFG_R_BUFGCTRL3_S1": null, + "CLK_BUFG_R_BUFGCTRL4_CE0": null, + "CLK_BUFG_R_BUFGCTRL4_CE1": null, + "CLK_BUFG_R_BUFGCTRL4_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL4_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL4_S0": null, + "CLK_BUFG_R_BUFGCTRL4_S1": null, + "CLK_BUFG_R_BUFGCTRL5_CE0": null, + "CLK_BUFG_R_BUFGCTRL5_CE1": null, + "CLK_BUFG_R_BUFGCTRL5_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL5_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL5_S0": null, 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"CLK_BUFG_R_CK_FB_TEST0_10": null, + "CLK_BUFG_R_CK_FB_TEST0_11": null, + "CLK_BUFG_R_CK_FB_TEST0_12": null, + "CLK_BUFG_R_CK_FB_TEST0_13": null, + "CLK_BUFG_R_CK_FB_TEST0_14": null, + "CLK_BUFG_R_CK_FB_TEST0_15": null, + "CLK_BUFG_R_CK_FB_TEST0_2": null, + "CLK_BUFG_R_CK_FB_TEST0_3": null, + "CLK_BUFG_R_CK_FB_TEST0_4": null, + "CLK_BUFG_R_CK_FB_TEST0_5": null, + "CLK_BUFG_R_CK_FB_TEST0_6": null, + "CLK_BUFG_R_CK_FB_TEST0_7": null, + "CLK_BUFG_R_CK_FB_TEST0_8": null, + "CLK_BUFG_R_CK_FB_TEST0_9": null, + "CLK_BUFG_R_CK_FB_TEST1_0": null, + "CLK_BUFG_R_CK_FB_TEST1_1": null, + "CLK_BUFG_R_CK_FB_TEST1_10": null, + "CLK_BUFG_R_CK_FB_TEST1_11": null, + "CLK_BUFG_R_CK_FB_TEST1_12": null, + "CLK_BUFG_R_CK_FB_TEST1_13": null, + "CLK_BUFG_R_CK_FB_TEST1_14": null, + "CLK_BUFG_R_CK_FB_TEST1_15": null, + "CLK_BUFG_R_CK_FB_TEST1_2": null, + "CLK_BUFG_R_CK_FB_TEST1_3": null, + "CLK_BUFG_R_CK_FB_TEST1_4": null, + "CLK_BUFG_R_CK_FB_TEST1_5": null, + "CLK_BUFG_R_CK_FB_TEST1_6": null, + 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"CLK_HROW_SE2A0_2": null, + "CLK_HROW_SE2A0_3": null, + "CLK_HROW_SE2A1_0": null, + "CLK_HROW_SE2A1_1": null, + "CLK_HROW_SE2A1_2": null, + "CLK_HROW_SE2A1_3": null, + "CLK_HROW_SE2A2_0": null, + "CLK_HROW_SE2A2_1": null, + "CLK_HROW_SE2A2_2": null, + "CLK_HROW_SE2A2_3": null, + "CLK_HROW_SE2A3_0": null, + "CLK_HROW_SE2A3_1": null, + "CLK_HROW_SE2A3_2": null, + "CLK_HROW_SE2A3_3": null, + "CLK_HROW_SE4BEG0_0": null, + "CLK_HROW_SE4BEG0_1": null, + "CLK_HROW_SE4BEG0_2": null, + "CLK_HROW_SE4BEG0_3": null, + "CLK_HROW_SE4BEG1_0": null, + "CLK_HROW_SE4BEG1_1": null, + "CLK_HROW_SE4BEG1_2": null, + "CLK_HROW_SE4BEG1_3": null, + "CLK_HROW_SE4BEG2_0": null, + "CLK_HROW_SE4BEG2_1": null, + "CLK_HROW_SE4BEG2_2": null, + "CLK_HROW_SE4BEG2_3": null, + "CLK_HROW_SE4BEG3_0": null, + "CLK_HROW_SE4BEG3_1": null, + "CLK_HROW_SE4BEG3_2": null, + "CLK_HROW_SE4BEG3_3": null, + "CLK_HROW_SE4C0_0": null, + "CLK_HROW_SE4C0_1": null, + "CLK_HROW_SE4C0_2": null, + "CLK_HROW_SE4C0_3": null, + "CLK_HROW_SE4C1_0": null, + "CLK_HROW_SE4C1_1": null, + "CLK_HROW_SE4C1_2": null, + "CLK_HROW_SE4C1_3": null, + "CLK_HROW_SE4C2_0": null, + "CLK_HROW_SE4C2_1": null, + "CLK_HROW_SE4C2_2": null, + "CLK_HROW_SE4C2_3": null, + "CLK_HROW_SE4C3_0": null, + "CLK_HROW_SE4C3_1": null, + "CLK_HROW_SE4C3_2": null, + "CLK_HROW_SE4C3_3": null, + "CLK_HROW_SW2A0_0": null, + "CLK_HROW_SW2A0_1": null, + "CLK_HROW_SW2A0_2": null, + "CLK_HROW_SW2A0_3": null, + "CLK_HROW_SW2A1_0": null, + "CLK_HROW_SW2A1_1": null, + "CLK_HROW_SW2A1_2": null, + "CLK_HROW_SW2A1_3": null, + "CLK_HROW_SW2A2_0": null, + "CLK_HROW_SW2A2_1": null, + "CLK_HROW_SW2A2_2": null, + "CLK_HROW_SW2A2_3": null, + "CLK_HROW_SW2A3_0": null, + "CLK_HROW_SW2A3_1": null, + "CLK_HROW_SW2A3_2": null, + "CLK_HROW_SW2A3_3": null, + "CLK_HROW_SW4A0_0": null, + "CLK_HROW_SW4A0_1": null, + "CLK_HROW_SW4A0_2": null, + "CLK_HROW_SW4A0_3": null, + "CLK_HROW_SW4A1_0": null, + "CLK_HROW_SW4A1_1": null, + "CLK_HROW_SW4A1_2": null, + "CLK_HROW_SW4A1_3": null, + "CLK_HROW_SW4A2_0": null, + "CLK_HROW_SW4A2_1": null, + "CLK_HROW_SW4A2_2": null, + "CLK_HROW_SW4A2_3": null, + "CLK_HROW_SW4A3_0": null, + "CLK_HROW_SW4A3_1": null, + "CLK_HROW_SW4A3_2": null, + "CLK_HROW_SW4A3_3": null, + "CLK_HROW_SW4END0_0": null, + "CLK_HROW_SW4END0_1": null, + "CLK_HROW_SW4END0_2": null, + "CLK_HROW_SW4END0_3": null, + "CLK_HROW_SW4END1_0": null, + "CLK_HROW_SW4END1_1": null, + "CLK_HROW_SW4END1_2": null, + "CLK_HROW_SW4END1_3": null, + "CLK_HROW_SW4END2_0": null, + "CLK_HROW_SW4END2_1": null, + "CLK_HROW_SW4END2_2": null, + "CLK_HROW_SW4END2_3": null, + "CLK_HROW_SW4END3_0": null, + "CLK_HROW_SW4END3_1": null, + "CLK_HROW_SW4END3_2": null, + "CLK_HROW_SW4END3_3": null, + "CLK_HROW_WL1END0_0": null, + "CLK_HROW_WL1END0_1": null, + "CLK_HROW_WL1END0_2": null, + "CLK_HROW_WL1END0_3": null, + "CLK_HROW_WL1END1_0": null, + "CLK_HROW_WL1END1_1": null, + "CLK_HROW_WL1END1_2": null, + "CLK_HROW_WL1END1_3": null, + "CLK_HROW_WL1END2_0": null, + "CLK_HROW_WL1END2_1": null, + "CLK_HROW_WL1END2_2": null, + "CLK_HROW_WL1END2_3": null, + "CLK_HROW_WL1END3_0": null, + "CLK_HROW_WL1END3_1": null, + "CLK_HROW_WL1END3_2": null, + "CLK_HROW_WL1END3_3": null, + "CLK_HROW_WR1END0_0": null, + "CLK_HROW_WR1END0_1": null, + "CLK_HROW_WR1END0_2": null, + "CLK_HROW_WR1END0_3": null, + "CLK_HROW_WR1END1_0": null, + "CLK_HROW_WR1END1_1": null, + "CLK_HROW_WR1END1_2": null, + "CLK_HROW_WR1END1_3": null, + "CLK_HROW_WR1END2_0": null, + "CLK_HROW_WR1END2_1": null, + "CLK_HROW_WR1END2_2": null, + "CLK_HROW_WR1END2_3": null, + "CLK_HROW_WR1END3_0": null, + "CLK_HROW_WR1END3_1": null, + "CLK_HROW_WR1END3_2": null, + "CLK_HROW_WR1END3_3": null, + "CLK_HROW_WW2A0_0": null, + "CLK_HROW_WW2A0_1": null, + "CLK_HROW_WW2A0_2": null, + "CLK_HROW_WW2A0_3": null, + "CLK_HROW_WW2A1_0": null, + "CLK_HROW_WW2A1_1": null, + "CLK_HROW_WW2A1_2": null, + "CLK_HROW_WW2A1_3": null, + "CLK_HROW_WW2A2_0": null, + "CLK_HROW_WW2A2_1": null, + "CLK_HROW_WW2A2_2": null, + "CLK_HROW_WW2A2_3": null, + "CLK_HROW_WW2A3_0": null, + "CLK_HROW_WW2A3_1": null, + "CLK_HROW_WW2A3_2": null, + "CLK_HROW_WW2A3_3": null, + "CLK_HROW_WW2END0_0": null, + "CLK_HROW_WW2END0_1": null, + "CLK_HROW_WW2END0_2": null, + "CLK_HROW_WW2END0_3": null, + "CLK_HROW_WW2END1_0": null, + "CLK_HROW_WW2END1_1": null, + "CLK_HROW_WW2END1_2": null, + "CLK_HROW_WW2END1_3": null, + "CLK_HROW_WW2END2_0": null, + "CLK_HROW_WW2END2_1": null, + "CLK_HROW_WW2END2_2": null, + "CLK_HROW_WW2END2_3": null, + "CLK_HROW_WW2END3_0": null, + "CLK_HROW_WW2END3_1": null, + "CLK_HROW_WW2END3_2": null, + "CLK_HROW_WW2END3_3": null, + "CLK_HROW_WW4A0_0": null, + "CLK_HROW_WW4A0_1": null, + "CLK_HROW_WW4A0_2": null, + "CLK_HROW_WW4A0_3": null, + "CLK_HROW_WW4A1_0": null, + "CLK_HROW_WW4A1_1": null, + "CLK_HROW_WW4A1_2": null, + "CLK_HROW_WW4A1_3": null, + "CLK_HROW_WW4A2_0": null, + "CLK_HROW_WW4A2_1": null, + "CLK_HROW_WW4A2_2": null, + "CLK_HROW_WW4A2_3": null, + "CLK_HROW_WW4A3_0": null, + "CLK_HROW_WW4A3_1": null, + "CLK_HROW_WW4A3_2": null, + "CLK_HROW_WW4A3_3": null, + "CLK_HROW_WW4B0_0": null, + "CLK_HROW_WW4B0_1": null, + "CLK_HROW_WW4B0_2": null, + "CLK_HROW_WW4B0_3": null, + "CLK_HROW_WW4B1_0": null, + "CLK_HROW_WW4B1_1": null, + "CLK_HROW_WW4B1_2": null, + "CLK_HROW_WW4B1_3": null, + "CLK_HROW_WW4B2_0": null, + "CLK_HROW_WW4B2_1": null, + "CLK_HROW_WW4B2_2": null, + "CLK_HROW_WW4B2_3": null, + "CLK_HROW_WW4B3_0": null, + "CLK_HROW_WW4B3_1": null, + "CLK_HROW_WW4B3_2": null, + "CLK_HROW_WW4B3_3": null, + "CLK_HROW_WW4C0_0": null, + "CLK_HROW_WW4C0_1": null, + "CLK_HROW_WW4C0_2": null, + "CLK_HROW_WW4C0_3": null, + "CLK_HROW_WW4C1_0": null, + "CLK_HROW_WW4C1_1": null, + "CLK_HROW_WW4C1_2": null, + "CLK_HROW_WW4C1_3": null, + "CLK_HROW_WW4C2_0": null, + "CLK_HROW_WW4C2_1": null, + "CLK_HROW_WW4C2_2": null, + "CLK_HROW_WW4C2_3": null, + "CLK_HROW_WW4C3_0": null, + "CLK_HROW_WW4C3_1": null, + "CLK_HROW_WW4C3_2": null, + "CLK_HROW_WW4C3_3": null, + "CLK_HROW_WW4END0_0": null, + "CLK_HROW_WW4END0_1": null, + "CLK_HROW_WW4END0_2": null, + "CLK_HROW_WW4END0_3": null, + "CLK_HROW_WW4END1_0": null, + "CLK_HROW_WW4END1_1": null, + "CLK_HROW_WW4END1_2": null, + "CLK_HROW_WW4END1_3": null, + "CLK_HROW_WW4END2_0": null, + "CLK_HROW_WW4END2_1": null, + "CLK_HROW_WW4END2_2": null, + "CLK_HROW_WW4END2_3": null, + "CLK_HROW_WW4END3_0": null, + "CLK_HROW_WW4END3_1": null, + "CLK_HROW_WW4END3_2": null, + "CLK_HROW_WW4END3_3": null + } } diff --git a/zynq7/tile_type_CLK_FEED.json b/zynq7/tile_type_CLK_FEED.json index f9b8b57..d4e1f1b 100644 --- a/zynq7/tile_type_CLK_FEED.json +++ b/zynq7/tile_type_CLK_FEED.json @@ -2,260 +2,260 @@ "pips": {}, "sites": [], "tile_type": "CLK_FEED", - "wires": [ - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK0", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK10", - "CLK_FEED_CK_GCLK11", - "CLK_FEED_CK_GCLK12", - "CLK_FEED_CK_GCLK13", - "CLK_FEED_CK_GCLK14", - "CLK_FEED_CK_GCLK15", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_CK_GCLK19", - "CLK_FEED_CK_GCLK2", - "CLK_FEED_CK_GCLK20", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK22", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_CK_GCLK30", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_CK_GCLK5", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_CK_GCLK8", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_EE2A0", - "CLK_FEED_EE2A1", - "CLK_FEED_EE2A2", - "CLK_FEED_EE2A3", - "CLK_FEED_EE2BEG0", - "CLK_FEED_EE2BEG1", - "CLK_FEED_EE2BEG2", - "CLK_FEED_EE2BEG3", - "CLK_FEED_EE4A0", - "CLK_FEED_EE4A1", - "CLK_FEED_EE4A2", - "CLK_FEED_EE4A3", - "CLK_FEED_EE4B0", - "CLK_FEED_EE4B1", - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_EE4BEG0", - "CLK_FEED_EE4BEG1", - "CLK_FEED_EE4BEG2", - "CLK_FEED_EE4BEG3", - "CLK_FEED_EE4C0", - "CLK_FEED_EE4C1", - "CLK_FEED_EE4C2", - "CLK_FEED_EE4C3", - "CLK_FEED_EL1BEG0", - "CLK_FEED_EL1BEG1", - "CLK_FEED_EL1BEG2", - "CLK_FEED_EL1BEG3", - "CLK_FEED_ER1BEG0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_ER1BEG2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_LH1", - "CLK_FEED_LH10", - "CLK_FEED_LH11", - "CLK_FEED_LH12", - "CLK_FEED_LH2", - "CLK_FEED_LH3", - "CLK_FEED_LH4", - "CLK_FEED_LH5", - "CLK_FEED_LH6", - "CLK_FEED_LH7", - "CLK_FEED_LH8", - "CLK_FEED_LH9", - "CLK_FEED_MONITOR_N", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A0", - "CLK_FEED_NE2A1", - "CLK_FEED_NE2A2", - "CLK_FEED_NE2A3", - "CLK_FEED_NE4BEG0", - "CLK_FEED_NE4BEG1", - "CLK_FEED_NE4BEG2", - "CLK_FEED_NE4BEG3", - "CLK_FEED_NE4C0", - "CLK_FEED_NE4C1", - "CLK_FEED_NE4C2", - "CLK_FEED_NE4C3", - "CLK_FEED_NW2A0", - "CLK_FEED_NW2A1", - "CLK_FEED_NW2A2", - "CLK_FEED_NW2A3", - "CLK_FEED_NW4A0", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4A2", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4END0", - "CLK_FEED_NW4END1", - "CLK_FEED_NW4END2", - "CLK_FEED_NW4END3", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_SE2A0", - "CLK_FEED_SE2A1", - "CLK_FEED_SE2A2", - "CLK_FEED_SE2A3", - "CLK_FEED_SE4BEG0", - "CLK_FEED_SE4BEG1", - "CLK_FEED_SE4BEG2", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SE4C0", - "CLK_FEED_SE4C1", - "CLK_FEED_SE4C2", - "CLK_FEED_SE4C3", - "CLK_FEED_SW2A0", - "CLK_FEED_SW2A1", - "CLK_FEED_SW2A2", - "CLK_FEED_SW2A3", - "CLK_FEED_SW4A0", - "CLK_FEED_SW4A1", - "CLK_FEED_SW4A2", - "CLK_FEED_SW4A3", - "CLK_FEED_SW4END0", - "CLK_FEED_SW4END1", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_FEED_WL1END0", - "CLK_FEED_WL1END1", - "CLK_FEED_WL1END2", - "CLK_FEED_WL1END3", - "CLK_FEED_WR1END0", - "CLK_FEED_WR1END1", - "CLK_FEED_WR1END2", - "CLK_FEED_WR1END3", - "CLK_FEED_WW2A0", - "CLK_FEED_WW2A1", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2A3", - "CLK_FEED_WW2END0", - "CLK_FEED_WW2END1", - "CLK_FEED_WW2END2", - "CLK_FEED_WW2END3", - "CLK_FEED_WW4A0", - "CLK_FEED_WW4A1", - "CLK_FEED_WW4A2", - "CLK_FEED_WW4A3", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4B1", - "CLK_FEED_WW4B2", - "CLK_FEED_WW4B3", - "CLK_FEED_WW4C0", - "CLK_FEED_WW4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_WW4C3", - "CLK_FEED_WW4END0", - "CLK_FEED_WW4END1", - "CLK_FEED_WW4END2", - "CLK_FEED_WW4END3" - ] + "wires": { + "CLK_FEED_CK_BUFG_CASC0": null, + "CLK_FEED_CK_BUFG_CASC1": null, + "CLK_FEED_CK_BUFG_CASC10": null, + "CLK_FEED_CK_BUFG_CASC11": null, + "CLK_FEED_CK_BUFG_CASC12": null, + "CLK_FEED_CK_BUFG_CASC13": null, + "CLK_FEED_CK_BUFG_CASC14": null, + "CLK_FEED_CK_BUFG_CASC15": null, + "CLK_FEED_CK_BUFG_CASC16": null, + "CLK_FEED_CK_BUFG_CASC17": null, + "CLK_FEED_CK_BUFG_CASC18": null, + "CLK_FEED_CK_BUFG_CASC19": null, + "CLK_FEED_CK_BUFG_CASC2": null, + "CLK_FEED_CK_BUFG_CASC20": null, + "CLK_FEED_CK_BUFG_CASC21": null, + "CLK_FEED_CK_BUFG_CASC22": null, + "CLK_FEED_CK_BUFG_CASC23": null, + "CLK_FEED_CK_BUFG_CASC24": null, + "CLK_FEED_CK_BUFG_CASC25": null, + "CLK_FEED_CK_BUFG_CASC26": null, + "CLK_FEED_CK_BUFG_CASC27": null, + "CLK_FEED_CK_BUFG_CASC28": null, + "CLK_FEED_CK_BUFG_CASC29": null, + "CLK_FEED_CK_BUFG_CASC3": null, + "CLK_FEED_CK_BUFG_CASC30": null, + "CLK_FEED_CK_BUFG_CASC31": null, + "CLK_FEED_CK_BUFG_CASC4": null, + "CLK_FEED_CK_BUFG_CASC5": null, + "CLK_FEED_CK_BUFG_CASC6": null, + "CLK_FEED_CK_BUFG_CASC7": null, + "CLK_FEED_CK_BUFG_CASC8": null, + "CLK_FEED_CK_BUFG_CASC9": null, + "CLK_FEED_CK_GCLK0": null, + "CLK_FEED_CK_GCLK1": null, + "CLK_FEED_CK_GCLK10": null, + "CLK_FEED_CK_GCLK11": null, + "CLK_FEED_CK_GCLK12": null, + "CLK_FEED_CK_GCLK13": null, + "CLK_FEED_CK_GCLK14": null, + "CLK_FEED_CK_GCLK15": null, + "CLK_FEED_CK_GCLK16": null, + "CLK_FEED_CK_GCLK17": null, + "CLK_FEED_CK_GCLK18": null, + "CLK_FEED_CK_GCLK19": null, + "CLK_FEED_CK_GCLK2": null, + "CLK_FEED_CK_GCLK20": null, + "CLK_FEED_CK_GCLK21": null, + "CLK_FEED_CK_GCLK22": null, + "CLK_FEED_CK_GCLK23": null, + "CLK_FEED_CK_GCLK24": null, + "CLK_FEED_CK_GCLK25": null, + "CLK_FEED_CK_GCLK26": null, + "CLK_FEED_CK_GCLK27": null, + "CLK_FEED_CK_GCLK28": null, + "CLK_FEED_CK_GCLK29": null, + "CLK_FEED_CK_GCLK3": null, + "CLK_FEED_CK_GCLK30": null, + "CLK_FEED_CK_GCLK31": null, + "CLK_FEED_CK_GCLK4": null, + "CLK_FEED_CK_GCLK5": null, + "CLK_FEED_CK_GCLK6": null, + "CLK_FEED_CK_GCLK7": null, + "CLK_FEED_CK_GCLK8": null, + "CLK_FEED_CK_GCLK9": null, + "CLK_FEED_EE2A0": null, + "CLK_FEED_EE2A1": null, + "CLK_FEED_EE2A2": null, + "CLK_FEED_EE2A3": null, + "CLK_FEED_EE2BEG0": null, + "CLK_FEED_EE2BEG1": null, + "CLK_FEED_EE2BEG2": null, + "CLK_FEED_EE2BEG3": null, + "CLK_FEED_EE4A0": null, + "CLK_FEED_EE4A1": null, + "CLK_FEED_EE4A2": null, + "CLK_FEED_EE4A3": null, + "CLK_FEED_EE4B0": null, + "CLK_FEED_EE4B1": null, + "CLK_FEED_EE4B2": null, + "CLK_FEED_EE4B3": null, + "CLK_FEED_EE4BEG0": null, + "CLK_FEED_EE4BEG1": null, + "CLK_FEED_EE4BEG2": null, + "CLK_FEED_EE4BEG3": null, + "CLK_FEED_EE4C0": null, + "CLK_FEED_EE4C1": null, + "CLK_FEED_EE4C2": null, + "CLK_FEED_EE4C3": null, + "CLK_FEED_EL1BEG0": null, + "CLK_FEED_EL1BEG1": null, + "CLK_FEED_EL1BEG2": null, + "CLK_FEED_EL1BEG3": null, + "CLK_FEED_ER1BEG0": null, + "CLK_FEED_ER1BEG1": null, + "CLK_FEED_ER1BEG2": null, + "CLK_FEED_ER1BEG3": null, + "CLK_FEED_LH1": null, + "CLK_FEED_LH10": null, + "CLK_FEED_LH11": null, + "CLK_FEED_LH12": null, + "CLK_FEED_LH2": null, + "CLK_FEED_LH3": null, + "CLK_FEED_LH4": null, + "CLK_FEED_LH5": null, + "CLK_FEED_LH6": null, + "CLK_FEED_LH7": null, + "CLK_FEED_LH8": null, + "CLK_FEED_LH9": null, + "CLK_FEED_MONITOR_N": null, + "CLK_FEED_MONITOR_P": null, + "CLK_FEED_NE2A0": null, + "CLK_FEED_NE2A1": null, + "CLK_FEED_NE2A2": null, + "CLK_FEED_NE2A3": null, + "CLK_FEED_NE4BEG0": null, + "CLK_FEED_NE4BEG1": null, + "CLK_FEED_NE4BEG2": null, + "CLK_FEED_NE4BEG3": null, + "CLK_FEED_NE4C0": null, + "CLK_FEED_NE4C1": null, + "CLK_FEED_NE4C2": null, + "CLK_FEED_NE4C3": null, + "CLK_FEED_NW2A0": null, + "CLK_FEED_NW2A1": null, + "CLK_FEED_NW2A2": null, + "CLK_FEED_NW2A3": null, + "CLK_FEED_NW4A0": null, + "CLK_FEED_NW4A1": null, + "CLK_FEED_NW4A2": null, + "CLK_FEED_NW4A3": null, + "CLK_FEED_NW4END0": null, + "CLK_FEED_NW4END1": null, + "CLK_FEED_NW4END2": null, + "CLK_FEED_NW4END3": null, + "CLK_FEED_R_CK_BUFG_CASC0": null, + "CLK_FEED_R_CK_BUFG_CASC1": null, + "CLK_FEED_R_CK_BUFG_CASC10": null, + "CLK_FEED_R_CK_BUFG_CASC11": null, + "CLK_FEED_R_CK_BUFG_CASC12": null, + "CLK_FEED_R_CK_BUFG_CASC13": null, + "CLK_FEED_R_CK_BUFG_CASC14": null, + "CLK_FEED_R_CK_BUFG_CASC15": null, + "CLK_FEED_R_CK_BUFG_CASC16": null, + "CLK_FEED_R_CK_BUFG_CASC17": null, + "CLK_FEED_R_CK_BUFG_CASC18": null, + "CLK_FEED_R_CK_BUFG_CASC19": null, + "CLK_FEED_R_CK_BUFG_CASC2": null, + "CLK_FEED_R_CK_BUFG_CASC20": null, + "CLK_FEED_R_CK_BUFG_CASC21": null, + "CLK_FEED_R_CK_BUFG_CASC22": null, + "CLK_FEED_R_CK_BUFG_CASC23": null, + "CLK_FEED_R_CK_BUFG_CASC24": null, + "CLK_FEED_R_CK_BUFG_CASC25": null, + "CLK_FEED_R_CK_BUFG_CASC26": null, + "CLK_FEED_R_CK_BUFG_CASC27": null, + "CLK_FEED_R_CK_BUFG_CASC28": null, + "CLK_FEED_R_CK_BUFG_CASC29": null, + "CLK_FEED_R_CK_BUFG_CASC3": null, + "CLK_FEED_R_CK_BUFG_CASC30": null, + "CLK_FEED_R_CK_BUFG_CASC31": null, + "CLK_FEED_R_CK_BUFG_CASC4": null, + "CLK_FEED_R_CK_BUFG_CASC5": null, + "CLK_FEED_R_CK_BUFG_CASC6": null, + "CLK_FEED_R_CK_BUFG_CASC7": null, + "CLK_FEED_R_CK_BUFG_CASC8": null, + "CLK_FEED_R_CK_BUFG_CASC9": null, + "CLK_FEED_R_CK_GCLK0": null, + "CLK_FEED_R_CK_GCLK1": null, + "CLK_FEED_R_CK_GCLK10": null, + "CLK_FEED_R_CK_GCLK11": null, + "CLK_FEED_R_CK_GCLK12": null, + "CLK_FEED_R_CK_GCLK13": null, + "CLK_FEED_R_CK_GCLK14": null, + "CLK_FEED_R_CK_GCLK15": null, + "CLK_FEED_R_CK_GCLK16": null, + "CLK_FEED_R_CK_GCLK17": null, + "CLK_FEED_R_CK_GCLK18": null, + "CLK_FEED_R_CK_GCLK19": null, + "CLK_FEED_R_CK_GCLK2": null, + "CLK_FEED_R_CK_GCLK20": null, + "CLK_FEED_R_CK_GCLK21": null, + "CLK_FEED_R_CK_GCLK22": null, + "CLK_FEED_R_CK_GCLK23": null, + "CLK_FEED_R_CK_GCLK24": null, + "CLK_FEED_R_CK_GCLK25": null, + "CLK_FEED_R_CK_GCLK26": null, + "CLK_FEED_R_CK_GCLK27": null, + "CLK_FEED_R_CK_GCLK28": null, + "CLK_FEED_R_CK_GCLK29": null, + "CLK_FEED_R_CK_GCLK3": null, + "CLK_FEED_R_CK_GCLK30": null, + "CLK_FEED_R_CK_GCLK31": null, + "CLK_FEED_R_CK_GCLK4": null, + "CLK_FEED_R_CK_GCLK5": null, + "CLK_FEED_R_CK_GCLK6": null, + "CLK_FEED_R_CK_GCLK7": null, + "CLK_FEED_R_CK_GCLK8": null, + "CLK_FEED_R_CK_GCLK9": null, + "CLK_FEED_SE2A0": null, + "CLK_FEED_SE2A1": null, + "CLK_FEED_SE2A2": null, + "CLK_FEED_SE2A3": null, + "CLK_FEED_SE4BEG0": null, + "CLK_FEED_SE4BEG1": null, + "CLK_FEED_SE4BEG2": null, + "CLK_FEED_SE4BEG3": null, + "CLK_FEED_SE4C0": null, + "CLK_FEED_SE4C1": null, + "CLK_FEED_SE4C2": null, + "CLK_FEED_SE4C3": null, + "CLK_FEED_SW2A0": null, + "CLK_FEED_SW2A1": null, + "CLK_FEED_SW2A2": null, + "CLK_FEED_SW2A3": null, + "CLK_FEED_SW4A0": null, + "CLK_FEED_SW4A1": null, + "CLK_FEED_SW4A2": null, + "CLK_FEED_SW4A3": null, + "CLK_FEED_SW4END0": null, + "CLK_FEED_SW4END1": null, + "CLK_FEED_SW4END2": null, + "CLK_FEED_SW4END3": null, + "CLK_FEED_WL1END0": null, + "CLK_FEED_WL1END1": null, + "CLK_FEED_WL1END2": null, + "CLK_FEED_WL1END3": null, + "CLK_FEED_WR1END0": null, + "CLK_FEED_WR1END1": null, + "CLK_FEED_WR1END2": null, + "CLK_FEED_WR1END3": null, + "CLK_FEED_WW2A0": null, + "CLK_FEED_WW2A1": null, + "CLK_FEED_WW2A2": null, + "CLK_FEED_WW2A3": null, + "CLK_FEED_WW2END0": null, + "CLK_FEED_WW2END1": null, + "CLK_FEED_WW2END2": null, + "CLK_FEED_WW2END3": null, + "CLK_FEED_WW4A0": null, + "CLK_FEED_WW4A1": null, + "CLK_FEED_WW4A2": null, + "CLK_FEED_WW4A3": null, + "CLK_FEED_WW4B0": null, + "CLK_FEED_WW4B1": null, + "CLK_FEED_WW4B2": null, + "CLK_FEED_WW4B3": null, + "CLK_FEED_WW4C0": null, + "CLK_FEED_WW4C1": null, + "CLK_FEED_WW4C2": null, + "CLK_FEED_WW4C3": null, + "CLK_FEED_WW4END0": null, + "CLK_FEED_WW4END1": null, + "CLK_FEED_WW4END2": null, + "CLK_FEED_WW4END3": null + } } diff --git a/zynq7/tile_type_CLK_HROW_BOT_R.json b/zynq7/tile_type_CLK_HROW_BOT_R.json index 2cd154e..85d8dc1 100644 --- a/zynq7/tile_type_CLK_HROW_BOT_R.json +++ b/zynq7/tile_type_CLK_HROW_BOT_R.json @@ -2,19882 +2,78562 @@ "pips": { "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN0" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN1" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN10" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN11" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN12" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN13" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN14->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN14" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN15->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN15" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN16->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN16" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN17->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN17" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN18->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN18" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN19->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN19" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN2" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN20->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN20" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN21->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN21" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN22->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN22" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN23->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN23" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN24->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN24" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN25->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN25" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN26->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN26" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN27->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN27" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN28->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN28" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN29->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN29" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN3" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN30->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN30" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN31->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN31" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN4" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN5" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN6" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN7" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN8" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.153", + "0.160", + "0.293", + "0.323" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN9" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT0->>CLK_HROW_BUFHCE_CE_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT0" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT1->>CLK_HROW_BUFHCE_CE_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT1" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT10->>CLK_HROW_BUFHCE_CE_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT10" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT11->>CLK_HROW_BUFHCE_CE_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT11" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT2->>CLK_HROW_BUFHCE_CE_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT2" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT3->>CLK_HROW_BUFHCE_CE_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT3" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT4->>CLK_HROW_BUFHCE_CE_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT4" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT5->>CLK_HROW_BUFHCE_CE_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT5" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT6->>CLK_HROW_BUFHCE_CE_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT6" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT7->>CLK_HROW_BUFHCE_CE_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT7" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT8->>CLK_HROW_BUFHCE_CE_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT8" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT9->>CLK_HROW_BUFHCE_CE_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT9" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP0->>CLK_HROW_BUFHCE_CE_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP0" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP1->>CLK_HROW_BUFHCE_CE_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP1" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP10->>CLK_HROW_BUFHCE_CE_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP10" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP11->>CLK_HROW_BUFHCE_CE_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP11" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP2->>CLK_HROW_BUFHCE_CE_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP2" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP3->>CLK_HROW_BUFHCE_CE_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP3" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP4->>CLK_HROW_BUFHCE_CE_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP4" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP5->>CLK_HROW_BUFHCE_CE_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP5" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP6->>CLK_HROW_BUFHCE_CE_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP6" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP7->>CLK_HROW_BUFHCE_CE_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP7" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP8->>CLK_HROW_BUFHCE_CE_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP8" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP9->>CLK_HROW_BUFHCE_CE_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, 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"CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L3" }, 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"CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R0" }, 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"CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, 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"CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, 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"CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST0->CLK_HROW_CK_GCLK_TEST_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST1->CLK_HROW_CK_GCLK_TEST_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST10->CLK_HROW_CK_GCLK_TEST_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST11->CLK_HROW_CK_GCLK_TEST_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST12->CLK_HROW_CK_GCLK_TEST_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST13->CLK_HROW_CK_GCLK_TEST_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST14->CLK_HROW_CK_GCLK_TEST_IN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST14" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST15->CLK_HROW_CK_GCLK_TEST_IN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST15" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST16->CLK_HROW_CK_GCLK_TEST_IN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST16" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST17->CLK_HROW_CK_GCLK_TEST_IN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST17" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST18->CLK_HROW_CK_GCLK_TEST_IN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST18" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST19->CLK_HROW_CK_GCLK_TEST_IN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST19" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST2->CLK_HROW_CK_GCLK_TEST_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST20->CLK_HROW_CK_GCLK_TEST_IN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST20" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST21->CLK_HROW_CK_GCLK_TEST_IN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST21" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST22->CLK_HROW_CK_GCLK_TEST_IN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST22" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST23->CLK_HROW_CK_GCLK_TEST_IN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST23" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST24->CLK_HROW_CK_GCLK_TEST_IN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST24" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST25->CLK_HROW_CK_GCLK_TEST_IN25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST25" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST26->CLK_HROW_CK_GCLK_TEST_IN26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST26" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST27->CLK_HROW_CK_GCLK_TEST_IN27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST27" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST28->CLK_HROW_CK_GCLK_TEST_IN28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST28" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST29->CLK_HROW_CK_GCLK_TEST_IN29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST29" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST3->CLK_HROW_CK_GCLK_TEST_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST30->CLK_HROW_CK_GCLK_TEST_IN30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST30" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST31->CLK_HROW_CK_GCLK_TEST_IN31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST31" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST4->CLK_HROW_CK_GCLK_TEST_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST5->CLK_HROW_CK_GCLK_TEST_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST6->CLK_HROW_CK_GCLK_TEST_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST7->CLK_HROW_CK_GCLK_TEST_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST8->CLK_HROW_CK_GCLK_TEST_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST9->CLK_HROW_CK_GCLK_TEST_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT0->CLK_HROW_CK_GCLK_OUT_TEST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT1->CLK_HROW_CK_GCLK_OUT_TEST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT10->CLK_HROW_CK_GCLK_OUT_TEST10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT11->CLK_HROW_CK_GCLK_OUT_TEST11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT12->CLK_HROW_CK_GCLK_OUT_TEST12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT13->CLK_HROW_CK_GCLK_OUT_TEST13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT14->CLK_HROW_CK_GCLK_OUT_TEST14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT14" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT15->CLK_HROW_CK_GCLK_OUT_TEST15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT15" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT16->CLK_HROW_CK_GCLK_OUT_TEST16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT16" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT17->CLK_HROW_CK_GCLK_OUT_TEST17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT17" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT18->CLK_HROW_CK_GCLK_OUT_TEST18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT18" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT19->CLK_HROW_CK_GCLK_OUT_TEST19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT19" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT2->CLK_HROW_CK_GCLK_OUT_TEST2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT20->CLK_HROW_CK_GCLK_OUT_TEST20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT20" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT21->CLK_HROW_CK_GCLK_OUT_TEST21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT21" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT22->CLK_HROW_CK_GCLK_OUT_TEST22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT22" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT23->CLK_HROW_CK_GCLK_OUT_TEST23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT23" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT24->CLK_HROW_CK_GCLK_OUT_TEST24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT24" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT25->CLK_HROW_CK_GCLK_OUT_TEST25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT25" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT26->CLK_HROW_CK_GCLK_OUT_TEST26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT26" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT27->CLK_HROW_CK_GCLK_OUT_TEST27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT27" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT28->CLK_HROW_CK_GCLK_OUT_TEST28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT28" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT29->CLK_HROW_CK_GCLK_OUT_TEST29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT29" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT3->CLK_HROW_CK_GCLK_OUT_TEST3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT30->CLK_HROW_CK_GCLK_OUT_TEST30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT30" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT31->CLK_HROW_CK_GCLK_OUT_TEST31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT31" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT4->CLK_HROW_CK_GCLK_OUT_TEST4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT5->CLK_HROW_CK_GCLK_OUT_TEST5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT6->CLK_HROW_CK_GCLK_OUT_TEST6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT7->CLK_HROW_CK_GCLK_OUT_TEST7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT8->CLK_HROW_CK_GCLK_OUT_TEST8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT9->CLK_HROW_CK_GCLK_OUT_TEST9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L0->>CLK_HROW_CK_BUFHCLK_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L1->>CLK_HROW_CK_BUFHCLK_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L10->>CLK_HROW_CK_BUFHCLK_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L11->>CLK_HROW_CK_BUFHCLK_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L2->>CLK_HROW_CK_BUFHCLK_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L3->>CLK_HROW_CK_BUFHCLK_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L4->>CLK_HROW_CK_BUFHCLK_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L5->>CLK_HROW_CK_BUFHCLK_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L6->>CLK_HROW_CK_BUFHCLK_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L7->>CLK_HROW_CK_BUFHCLK_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L8->>CLK_HROW_CK_BUFHCLK_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L9->>CLK_HROW_CK_BUFHCLK_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R0->>CLK_HROW_CK_BUFHCLK_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R1->>CLK_HROW_CK_BUFHCLK_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R10->>CLK_HROW_CK_BUFHCLK_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R11->>CLK_HROW_CK_BUFHCLK_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R2->>CLK_HROW_CK_BUFHCLK_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R3->>CLK_HROW_CK_BUFHCLK_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R4->>CLK_HROW_CK_BUFHCLK_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R5->>CLK_HROW_CK_BUFHCLK_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R6->>CLK_HROW_CK_BUFHCLK_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R7->>CLK_HROW_CK_BUFHCLK_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R8->>CLK_HROW_CK_BUFHCLK_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R9->>CLK_HROW_CK_BUFHCLK_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_OUT_TEST->CLK_HROW_CK_IN_L_TEST_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_L_TEST_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_L_OUT_TEST" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_TEST_IN->CLK_HROW_CK_IN_L_IN_TEST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_L_IN_TEST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_L_TEST_IN" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_OUT_TEST->CLK_HROW_CK_IN_R_TEST_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_R_TEST_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_R_OUT_TEST" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_TEST_IN->CLK_HROW_CK_IN_R_IN_TEST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_R_IN_TEST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_R_TEST_IN" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L0->>CLK_HROW_CK_HCLK_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L1->>CLK_HROW_CK_HCLK_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L10->>CLK_HROW_CK_HCLK_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L11->>CLK_HROW_CK_HCLK_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L2->>CLK_HROW_CK_HCLK_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L3->>CLK_HROW_CK_HCLK_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L4->>CLK_HROW_CK_HCLK_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L5->>CLK_HROW_CK_HCLK_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L6->>CLK_HROW_CK_HCLK_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L7->>CLK_HROW_CK_HCLK_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L8->>CLK_HROW_CK_HCLK_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L9->>CLK_HROW_CK_HCLK_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R0->>CLK_HROW_CK_HCLK_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R1->>CLK_HROW_CK_HCLK_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R10->>CLK_HROW_CK_HCLK_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R11->>CLK_HROW_CK_HCLK_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R2->>CLK_HROW_CK_HCLK_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R3->>CLK_HROW_CK_HCLK_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R4->>CLK_HROW_CK_HCLK_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R5->>CLK_HROW_CK_HCLK_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R6->>CLK_HROW_CK_HCLK_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R7->>CLK_HROW_CK_HCLK_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R8->>CLK_HROW_CK_HCLK_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R9->>CLK_HROW_CK_HCLK_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CLK0_3->CLK_HROW_CK_INT_0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK0_3" }, "CLK_HROW_BOT_R.CLK_HROW_CLK0_4->CLK_HROW_CK_INT_1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK0_4" }, "CLK_HROW_BOT_R.CLK_HROW_CLK1_3->CLK_HROW_CK_INT_0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK1_3" }, "CLK_HROW_BOT_R.CLK_HROW_CLK1_4->CLK_HROW_CK_INT_1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK1_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX0_3->CLK_HROW_CE_INT_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX0_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX0_4->CLK_HROW_CE_INT_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX0_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX10_3->CLK_HROW_CE_INT_BOT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX10_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX10_4->CLK_HROW_CE_INT_TOP10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX10_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX11_3->CLK_HROW_CE_INT_BOT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX11_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX11_4->CLK_HROW_CE_INT_TOP11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX11_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX1_3->CLK_HROW_CE_INT_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX1_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX1_4->CLK_HROW_CE_INT_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX1_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX2_3->CLK_HROW_CE_INT_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX2_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX2_4->CLK_HROW_CE_INT_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX2_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX3_3->CLK_HROW_CE_INT_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX3_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX3_4->CLK_HROW_CE_INT_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX3_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX4_3->CLK_HROW_CE_INT_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX4_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX4_4->CLK_HROW_CE_INT_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX4_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX5_3->CLK_HROW_CE_INT_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX5_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX5_4->CLK_HROW_CE_INT_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX5_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX6_3->CLK_HROW_CE_INT_BOT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX6_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX6_4->CLK_HROW_CE_INT_TOP6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX6_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX7_3->CLK_HROW_CE_INT_BOT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX7_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX7_4->CLK_HROW_CE_INT_TOP7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX7_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX8_3->CLK_HROW_CE_INT_BOT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX8_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX8_4->CLK_HROW_CE_INT_TOP8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX8_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX9_3->CLK_HROW_CE_INT_BOT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX9_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX9_4->CLK_HROW_CE_INT_TOP9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX9_4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" } }, @@ -19886,9 +78566,36 @@ "name": "X0Y0", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L0", - "I": "CLK_HROW_CK_MUX_OUT_L0", - "O": "CLK_HROW_CK_HCLK_OUT_L0" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L0" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L0" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19898,9 +78605,36 @@ "name": "X0Y1", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L1", - "I": "CLK_HROW_CK_MUX_OUT_L1", - "O": "CLK_HROW_CK_HCLK_OUT_L1" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L1" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L1" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19910,9 +78644,36 @@ "name": "X0Y2", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L2", - "I": "CLK_HROW_CK_MUX_OUT_L2", - "O": "CLK_HROW_CK_HCLK_OUT_L2" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L2" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L2" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19922,9 +78683,36 @@ "name": "X0Y3", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L3", - "I": "CLK_HROW_CK_MUX_OUT_L3", - "O": "CLK_HROW_CK_HCLK_OUT_L3" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L3" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L3" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19934,9 +78722,36 @@ "name": "X0Y4", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L4", - "I": "CLK_HROW_CK_MUX_OUT_L4", - "O": "CLK_HROW_CK_HCLK_OUT_L4" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L4" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L4" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19946,9 +78761,36 @@ "name": "X0Y5", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L5", - "I": "CLK_HROW_CK_MUX_OUT_L5", - "O": "CLK_HROW_CK_HCLK_OUT_L5" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L5" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L5" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19958,9 +78800,36 @@ "name": "X0Y6", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L6", - "I": "CLK_HROW_CK_MUX_OUT_L6", - "O": "CLK_HROW_CK_HCLK_OUT_L6" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L6" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L6" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19970,9 +78839,36 @@ "name": "X0Y7", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L7", - "I": "CLK_HROW_CK_MUX_OUT_L7", - "O": "CLK_HROW_CK_HCLK_OUT_L7" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L7" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L7" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19982,9 +78878,36 @@ "name": "X0Y8", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L8", - "I": "CLK_HROW_CK_MUX_OUT_L8", - "O": "CLK_HROW_CK_HCLK_OUT_L8" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L8" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L8" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19994,9 +78917,36 @@ "name": "X0Y9", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L9", - "I": "CLK_HROW_CK_MUX_OUT_L9", - "O": "CLK_HROW_CK_HCLK_OUT_L9" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L9" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L9" + } }, "type": "BUFHCE", "x_coord": 0, @@ -20006,9 +78956,36 @@ "name": "X0Y10", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L10", - "I": "CLK_HROW_CK_MUX_OUT_L10", - "O": "CLK_HROW_CK_HCLK_OUT_L10" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L10" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L10" + } }, "type": "BUFHCE", "x_coord": 0, @@ -20018,9 +78995,36 @@ "name": "X0Y11", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L11", - "I": "CLK_HROW_CK_MUX_OUT_L11", - "O": "CLK_HROW_CK_HCLK_OUT_L11" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L11" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L11" + } }, "type": "BUFHCE", "x_coord": 0, @@ -20030,9 +79034,36 @@ "name": "X1Y11", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R11", - "I": "CLK_HROW_CK_MUX_OUT_R11", - "O": "CLK_HROW_CK_HCLK_OUT_R11" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R11" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R11" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20042,9 +79073,36 @@ "name": "X1Y10", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R10", - "I": "CLK_HROW_CK_MUX_OUT_R10", - "O": "CLK_HROW_CK_HCLK_OUT_R10" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R10" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R10" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20054,9 +79112,36 @@ "name": "X1Y9", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R9", - "I": "CLK_HROW_CK_MUX_OUT_R9", - "O": "CLK_HROW_CK_HCLK_OUT_R9" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R9" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R9" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20066,9 +79151,36 @@ "name": "X1Y8", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R8", - "I": "CLK_HROW_CK_MUX_OUT_R8", - "O": "CLK_HROW_CK_HCLK_OUT_R8" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R8" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R8" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20078,9 +79190,36 @@ "name": "X1Y7", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R7", - "I": "CLK_HROW_CK_MUX_OUT_R7", - "O": "CLK_HROW_CK_HCLK_OUT_R7" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R7" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R7" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20090,9 +79229,36 @@ "name": "X1Y6", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R6", - "I": "CLK_HROW_CK_MUX_OUT_R6", - "O": "CLK_HROW_CK_HCLK_OUT_R6" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R6" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R6" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20102,9 +79268,36 @@ "name": "X1Y5", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R5", - "I": "CLK_HROW_CK_MUX_OUT_R5", - "O": "CLK_HROW_CK_HCLK_OUT_R5" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R5" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R5" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20114,9 +79307,36 @@ "name": "X1Y4", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R4", - "I": "CLK_HROW_CK_MUX_OUT_R4", - "O": "CLK_HROW_CK_HCLK_OUT_R4" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R4" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R4" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20126,9 +79346,36 @@ "name": "X1Y3", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R3", - "I": "CLK_HROW_CK_MUX_OUT_R3", - "O": "CLK_HROW_CK_HCLK_OUT_R3" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R3" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R3" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20138,9 +79385,36 @@ "name": "X1Y2", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R2", - "I": "CLK_HROW_CK_MUX_OUT_R2", - "O": "CLK_HROW_CK_HCLK_OUT_R2" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R2" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R2" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20150,9 +79424,36 @@ "name": "X1Y1", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R1", - "I": "CLK_HROW_CK_MUX_OUT_R1", - "O": "CLK_HROW_CK_HCLK_OUT_R1" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R1" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R1" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20162,9 +79463,36 @@ "name": "X1Y0", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R0", - "I": "CLK_HROW_CK_MUX_OUT_R0", - "O": "CLK_HROW_CK_HCLK_OUT_R0" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R0" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R0" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20172,2210 +79500,3410 @@ } ], "tile_type": "CLK_HROW_BOT_R", - "wires": [ - "CLK_HROW_BLOCK_OUTS_B0_0", - "CLK_HROW_BLOCK_OUTS_B0_1", - "CLK_HROW_BLOCK_OUTS_B0_2", - "CLK_HROW_BLOCK_OUTS_B0_3", - "CLK_HROW_BLOCK_OUTS_B0_4", - "CLK_HROW_BLOCK_OUTS_B0_5", - "CLK_HROW_BLOCK_OUTS_B0_6", - "CLK_HROW_BLOCK_OUTS_B0_7", - "CLK_HROW_BLOCK_OUTS_B1_0", - "CLK_HROW_BLOCK_OUTS_B1_1", - "CLK_HROW_BLOCK_OUTS_B1_2", - "CLK_HROW_BLOCK_OUTS_B1_3", - "CLK_HROW_BLOCK_OUTS_B1_4", - "CLK_HROW_BLOCK_OUTS_B1_5", - "CLK_HROW_BLOCK_OUTS_B1_6", - "CLK_HROW_BLOCK_OUTS_B1_7", - "CLK_HROW_BLOCK_OUTS_B2_0", - "CLK_HROW_BLOCK_OUTS_B2_1", - "CLK_HROW_BLOCK_OUTS_B2_2", - "CLK_HROW_BLOCK_OUTS_B2_3", - "CLK_HROW_BLOCK_OUTS_B2_4", - "CLK_HROW_BLOCK_OUTS_B2_5", - "CLK_HROW_BLOCK_OUTS_B2_6", - "CLK_HROW_BLOCK_OUTS_B2_7", - "CLK_HROW_BLOCK_OUTS_B3_0", - "CLK_HROW_BLOCK_OUTS_B3_1", - "CLK_HROW_BLOCK_OUTS_B3_2", - "CLK_HROW_BLOCK_OUTS_B3_3", - "CLK_HROW_BLOCK_OUTS_B3_4", - "CLK_HROW_BLOCK_OUTS_B3_5", - "CLK_HROW_BLOCK_OUTS_B3_6", - "CLK_HROW_BLOCK_OUTS_B3_7", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN0", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN1", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN10", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN11", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN12", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN13", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN14", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN15", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN16", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN17", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN18", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN19", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN2", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN20", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN21", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN22", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN23", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN24", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN25", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN26", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN27", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN28", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN29", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN3", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN30", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN31", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN4", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN5", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN6", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN7", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN8", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN9", - "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "CLK_HROW_BUFHCE_CE_L0", - "CLK_HROW_BUFHCE_CE_L1", - "CLK_HROW_BUFHCE_CE_L10", - "CLK_HROW_BUFHCE_CE_L11", - "CLK_HROW_BUFHCE_CE_L2", - "CLK_HROW_BUFHCE_CE_L3", - "CLK_HROW_BUFHCE_CE_L4", - "CLK_HROW_BUFHCE_CE_L5", - "CLK_HROW_BUFHCE_CE_L6", - "CLK_HROW_BUFHCE_CE_L7", - "CLK_HROW_BUFHCE_CE_L8", - "CLK_HROW_BUFHCE_CE_L9", - "CLK_HROW_BUFHCE_CE_R0", - "CLK_HROW_BUFHCE_CE_R1", - "CLK_HROW_BUFHCE_CE_R10", - "CLK_HROW_BUFHCE_CE_R11", - "CLK_HROW_BUFHCE_CE_R2", - "CLK_HROW_BUFHCE_CE_R3", - "CLK_HROW_BUFHCE_CE_R4", - "CLK_HROW_BUFHCE_CE_R5", - "CLK_HROW_BUFHCE_CE_R6", - "CLK_HROW_BUFHCE_CE_R7", - "CLK_HROW_BUFHCE_CE_R8", - "CLK_HROW_BUFHCE_CE_R9", - "CLK_HROW_BYP0_0", - "CLK_HROW_BYP0_1", - "CLK_HROW_BYP0_2", - "CLK_HROW_BYP0_3", - "CLK_HROW_BYP0_4", - "CLK_HROW_BYP0_5", - "CLK_HROW_BYP0_6", - "CLK_HROW_BYP0_7", - "CLK_HROW_BYP1_0", - "CLK_HROW_BYP1_1", - "CLK_HROW_BYP1_2", - "CLK_HROW_BYP1_3", - "CLK_HROW_BYP1_4", - "CLK_HROW_BYP1_5", - "CLK_HROW_BYP1_6", - "CLK_HROW_BYP1_7", - "CLK_HROW_BYP2_0", - "CLK_HROW_BYP2_1", - "CLK_HROW_BYP2_2", - "CLK_HROW_BYP2_3", - "CLK_HROW_BYP2_4", - "CLK_HROW_BYP2_5", - "CLK_HROW_BYP2_6", - "CLK_HROW_BYP2_7", - "CLK_HROW_BYP3_0", - "CLK_HROW_BYP3_1", - "CLK_HROW_BYP3_2", - "CLK_HROW_BYP3_3", - "CLK_HROW_BYP3_4", - "CLK_HROW_BYP3_5", - "CLK_HROW_BYP3_6", - "CLK_HROW_BYP3_7", - "CLK_HROW_BYP4_0", - "CLK_HROW_BYP4_1", - "CLK_HROW_BYP4_2", - "CLK_HROW_BYP4_3", - "CLK_HROW_BYP4_4", - "CLK_HROW_BYP4_5", - "CLK_HROW_BYP4_6", - "CLK_HROW_BYP4_7", - "CLK_HROW_BYP5_0", - "CLK_HROW_BYP5_1", - "CLK_HROW_BYP5_2", - "CLK_HROW_BYP5_3", - "CLK_HROW_BYP5_4", - "CLK_HROW_BYP5_5", - "CLK_HROW_BYP5_6", - "CLK_HROW_BYP5_7", - "CLK_HROW_BYP6_0", - "CLK_HROW_BYP6_1", - "CLK_HROW_BYP6_2", - "CLK_HROW_BYP6_3", - "CLK_HROW_BYP6_4", - "CLK_HROW_BYP6_5", - "CLK_HROW_BYP6_6", - "CLK_HROW_BYP6_7", - "CLK_HROW_BYP7_0", - "CLK_HROW_BYP7_1", - "CLK_HROW_BYP7_2", - "CLK_HROW_BYP7_3", - "CLK_HROW_BYP7_4", - "CLK_HROW_BYP7_5", - "CLK_HROW_BYP7_6", - "CLK_HROW_BYP7_7", - "CLK_HROW_CE_INT_BOT0", - "CLK_HROW_CE_INT_BOT1", - "CLK_HROW_CE_INT_BOT10", - "CLK_HROW_CE_INT_BOT11", - "CLK_HROW_CE_INT_BOT2", - "CLK_HROW_CE_INT_BOT3", - "CLK_HROW_CE_INT_BOT4", - "CLK_HROW_CE_INT_BOT5", - "CLK_HROW_CE_INT_BOT6", - "CLK_HROW_CE_INT_BOT7", - "CLK_HROW_CE_INT_BOT8", - "CLK_HROW_CE_INT_BOT9", - "CLK_HROW_CE_INT_TOP0", - "CLK_HROW_CE_INT_TOP1", - "CLK_HROW_CE_INT_TOP10", - "CLK_HROW_CE_INT_TOP11", - "CLK_HROW_CE_INT_TOP2", - "CLK_HROW_CE_INT_TOP3", - "CLK_HROW_CE_INT_TOP4", - "CLK_HROW_CE_INT_TOP5", - "CLK_HROW_CE_INT_TOP6", - "CLK_HROW_CE_INT_TOP7", - "CLK_HROW_CE_INT_TOP8", - "CLK_HROW_CE_INT_TOP9", - "CLK_HROW_CK_BUFHCLK_L0", - "CLK_HROW_CK_BUFHCLK_L1", - "CLK_HROW_CK_BUFHCLK_L10", - "CLK_HROW_CK_BUFHCLK_L11", - "CLK_HROW_CK_BUFHCLK_L2", - "CLK_HROW_CK_BUFHCLK_L3", - "CLK_HROW_CK_BUFHCLK_L4", - "CLK_HROW_CK_BUFHCLK_L5", - "CLK_HROW_CK_BUFHCLK_L6", - "CLK_HROW_CK_BUFHCLK_L7", - "CLK_HROW_CK_BUFHCLK_L8", - "CLK_HROW_CK_BUFHCLK_L9", - "CLK_HROW_CK_BUFHCLK_R0", - "CLK_HROW_CK_BUFHCLK_R1", - "CLK_HROW_CK_BUFHCLK_R10", - "CLK_HROW_CK_BUFHCLK_R11", - "CLK_HROW_CK_BUFHCLK_R2", - "CLK_HROW_CK_BUFHCLK_R3", - "CLK_HROW_CK_BUFHCLK_R4", - "CLK_HROW_CK_BUFHCLK_R5", - "CLK_HROW_CK_BUFHCLK_R6", - "CLK_HROW_CK_BUFHCLK_R7", - "CLK_HROW_CK_BUFHCLK_R8", - "CLK_HROW_CK_BUFHCLK_R9", - "CLK_HROW_CK_BUFRCLK_L0", - "CLK_HROW_CK_BUFRCLK_L1", - "CLK_HROW_CK_BUFRCLK_L2", - "CLK_HROW_CK_BUFRCLK_L3", - "CLK_HROW_CK_BUFRCLK_R0", - "CLK_HROW_CK_BUFRCLK_R1", - "CLK_HROW_CK_BUFRCLK_R2", - "CLK_HROW_CK_BUFRCLK_R3", - "CLK_HROW_CK_GCLK_IN_TEST0", - "CLK_HROW_CK_GCLK_IN_TEST1", - "CLK_HROW_CK_GCLK_IN_TEST10", - "CLK_HROW_CK_GCLK_IN_TEST11", - "CLK_HROW_CK_GCLK_IN_TEST12", - "CLK_HROW_CK_GCLK_IN_TEST13", - "CLK_HROW_CK_GCLK_IN_TEST14", - "CLK_HROW_CK_GCLK_IN_TEST15", - "CLK_HROW_CK_GCLK_IN_TEST16", - "CLK_HROW_CK_GCLK_IN_TEST17", - "CLK_HROW_CK_GCLK_IN_TEST18", - "CLK_HROW_CK_GCLK_IN_TEST19", - "CLK_HROW_CK_GCLK_IN_TEST2", - "CLK_HROW_CK_GCLK_IN_TEST20", - "CLK_HROW_CK_GCLK_IN_TEST21", - "CLK_HROW_CK_GCLK_IN_TEST22", - "CLK_HROW_CK_GCLK_IN_TEST23", - "CLK_HROW_CK_GCLK_IN_TEST24", - "CLK_HROW_CK_GCLK_IN_TEST25", - "CLK_HROW_CK_GCLK_IN_TEST26", - "CLK_HROW_CK_GCLK_IN_TEST27", - "CLK_HROW_CK_GCLK_IN_TEST28", - "CLK_HROW_CK_GCLK_IN_TEST29", - "CLK_HROW_CK_GCLK_IN_TEST3", - "CLK_HROW_CK_GCLK_IN_TEST30", - "CLK_HROW_CK_GCLK_IN_TEST31", - "CLK_HROW_CK_GCLK_IN_TEST4", - "CLK_HROW_CK_GCLK_IN_TEST5", - "CLK_HROW_CK_GCLK_IN_TEST6", - "CLK_HROW_CK_GCLK_IN_TEST7", - "CLK_HROW_CK_GCLK_IN_TEST8", - "CLK_HROW_CK_GCLK_IN_TEST9", - "CLK_HROW_CK_GCLK_OUT_TEST0", - "CLK_HROW_CK_GCLK_OUT_TEST1", - "CLK_HROW_CK_GCLK_OUT_TEST10", - "CLK_HROW_CK_GCLK_OUT_TEST11", - "CLK_HROW_CK_GCLK_OUT_TEST12", - "CLK_HROW_CK_GCLK_OUT_TEST13", - "CLK_HROW_CK_GCLK_OUT_TEST14", - "CLK_HROW_CK_GCLK_OUT_TEST15", - "CLK_HROW_CK_GCLK_OUT_TEST16", - "CLK_HROW_CK_GCLK_OUT_TEST17", - "CLK_HROW_CK_GCLK_OUT_TEST18", - "CLK_HROW_CK_GCLK_OUT_TEST19", - "CLK_HROW_CK_GCLK_OUT_TEST2", - "CLK_HROW_CK_GCLK_OUT_TEST20", - "CLK_HROW_CK_GCLK_OUT_TEST21", - "CLK_HROW_CK_GCLK_OUT_TEST22", - "CLK_HROW_CK_GCLK_OUT_TEST23", - "CLK_HROW_CK_GCLK_OUT_TEST24", - "CLK_HROW_CK_GCLK_OUT_TEST25", - "CLK_HROW_CK_GCLK_OUT_TEST26", - "CLK_HROW_CK_GCLK_OUT_TEST27", - "CLK_HROW_CK_GCLK_OUT_TEST28", - "CLK_HROW_CK_GCLK_OUT_TEST29", - "CLK_HROW_CK_GCLK_OUT_TEST3", - "CLK_HROW_CK_GCLK_OUT_TEST30", - "CLK_HROW_CK_GCLK_OUT_TEST31", - "CLK_HROW_CK_GCLK_OUT_TEST4", - "CLK_HROW_CK_GCLK_OUT_TEST5", - "CLK_HROW_CK_GCLK_OUT_TEST6", - "CLK_HROW_CK_GCLK_OUT_TEST7", - "CLK_HROW_CK_GCLK_OUT_TEST8", - "CLK_HROW_CK_GCLK_OUT_TEST9", - "CLK_HROW_CK_GCLK_TEST0", - "CLK_HROW_CK_GCLK_TEST1", - "CLK_HROW_CK_GCLK_TEST10", - "CLK_HROW_CK_GCLK_TEST11", - "CLK_HROW_CK_GCLK_TEST12", - "CLK_HROW_CK_GCLK_TEST13", - "CLK_HROW_CK_GCLK_TEST14", - "CLK_HROW_CK_GCLK_TEST15", - "CLK_HROW_CK_GCLK_TEST16", - "CLK_HROW_CK_GCLK_TEST17", - "CLK_HROW_CK_GCLK_TEST18", - "CLK_HROW_CK_GCLK_TEST19", - "CLK_HROW_CK_GCLK_TEST2", - "CLK_HROW_CK_GCLK_TEST20", - "CLK_HROW_CK_GCLK_TEST21", - "CLK_HROW_CK_GCLK_TEST22", - "CLK_HROW_CK_GCLK_TEST23", - "CLK_HROW_CK_GCLK_TEST24", - "CLK_HROW_CK_GCLK_TEST25", - "CLK_HROW_CK_GCLK_TEST26", - "CLK_HROW_CK_GCLK_TEST27", - "CLK_HROW_CK_GCLK_TEST28", - "CLK_HROW_CK_GCLK_TEST29", - "CLK_HROW_CK_GCLK_TEST3", - "CLK_HROW_CK_GCLK_TEST30", - "CLK_HROW_CK_GCLK_TEST31", - "CLK_HROW_CK_GCLK_TEST4", - "CLK_HROW_CK_GCLK_TEST5", - "CLK_HROW_CK_GCLK_TEST6", - "CLK_HROW_CK_GCLK_TEST7", - "CLK_HROW_CK_GCLK_TEST8", - "CLK_HROW_CK_GCLK_TEST9", - "CLK_HROW_CK_GCLK_TEST_IN0", - "CLK_HROW_CK_GCLK_TEST_IN1", - "CLK_HROW_CK_GCLK_TEST_IN10", - "CLK_HROW_CK_GCLK_TEST_IN11", - "CLK_HROW_CK_GCLK_TEST_IN12", - "CLK_HROW_CK_GCLK_TEST_IN13", - "CLK_HROW_CK_GCLK_TEST_IN14", - "CLK_HROW_CK_GCLK_TEST_IN15", - "CLK_HROW_CK_GCLK_TEST_IN16", - "CLK_HROW_CK_GCLK_TEST_IN17", - "CLK_HROW_CK_GCLK_TEST_IN18", - "CLK_HROW_CK_GCLK_TEST_IN19", - "CLK_HROW_CK_GCLK_TEST_IN2", - "CLK_HROW_CK_GCLK_TEST_IN20", - "CLK_HROW_CK_GCLK_TEST_IN21", - "CLK_HROW_CK_GCLK_TEST_IN22", - "CLK_HROW_CK_GCLK_TEST_IN23", - "CLK_HROW_CK_GCLK_TEST_IN24", - "CLK_HROW_CK_GCLK_TEST_IN25", - "CLK_HROW_CK_GCLK_TEST_IN26", - "CLK_HROW_CK_GCLK_TEST_IN27", - "CLK_HROW_CK_GCLK_TEST_IN28", - "CLK_HROW_CK_GCLK_TEST_IN29", - "CLK_HROW_CK_GCLK_TEST_IN3", - "CLK_HROW_CK_GCLK_TEST_IN30", - "CLK_HROW_CK_GCLK_TEST_IN31", - "CLK_HROW_CK_GCLK_TEST_IN4", - "CLK_HROW_CK_GCLK_TEST_IN5", - "CLK_HROW_CK_GCLK_TEST_IN6", - "CLK_HROW_CK_GCLK_TEST_IN7", - "CLK_HROW_CK_GCLK_TEST_IN8", - "CLK_HROW_CK_GCLK_TEST_IN9", - "CLK_HROW_CK_GCLK_TEST_OUT0", - "CLK_HROW_CK_GCLK_TEST_OUT1", - "CLK_HROW_CK_GCLK_TEST_OUT10", - "CLK_HROW_CK_GCLK_TEST_OUT11", - "CLK_HROW_CK_GCLK_TEST_OUT12", - "CLK_HROW_CK_GCLK_TEST_OUT13", - "CLK_HROW_CK_GCLK_TEST_OUT14", - "CLK_HROW_CK_GCLK_TEST_OUT15", - "CLK_HROW_CK_GCLK_TEST_OUT16", - "CLK_HROW_CK_GCLK_TEST_OUT17", - "CLK_HROW_CK_GCLK_TEST_OUT18", - "CLK_HROW_CK_GCLK_TEST_OUT19", - "CLK_HROW_CK_GCLK_TEST_OUT2", - "CLK_HROW_CK_GCLK_TEST_OUT20", - "CLK_HROW_CK_GCLK_TEST_OUT21", - "CLK_HROW_CK_GCLK_TEST_OUT22", - "CLK_HROW_CK_GCLK_TEST_OUT23", - "CLK_HROW_CK_GCLK_TEST_OUT24", - "CLK_HROW_CK_GCLK_TEST_OUT25", - "CLK_HROW_CK_GCLK_TEST_OUT26", - "CLK_HROW_CK_GCLK_TEST_OUT27", - "CLK_HROW_CK_GCLK_TEST_OUT28", - "CLK_HROW_CK_GCLK_TEST_OUT29", - "CLK_HROW_CK_GCLK_TEST_OUT3", - "CLK_HROW_CK_GCLK_TEST_OUT30", - "CLK_HROW_CK_GCLK_TEST_OUT31", - "CLK_HROW_CK_GCLK_TEST_OUT4", - "CLK_HROW_CK_GCLK_TEST_OUT5", - "CLK_HROW_CK_GCLK_TEST_OUT6", - "CLK_HROW_CK_GCLK_TEST_OUT7", - "CLK_HROW_CK_GCLK_TEST_OUT8", - "CLK_HROW_CK_GCLK_TEST_OUT9", - "CLK_HROW_CK_HCLK_OUT_L0", - "CLK_HROW_CK_HCLK_OUT_L1", - "CLK_HROW_CK_HCLK_OUT_L10", - "CLK_HROW_CK_HCLK_OUT_L11", - "CLK_HROW_CK_HCLK_OUT_L2", - "CLK_HROW_CK_HCLK_OUT_L3", - "CLK_HROW_CK_HCLK_OUT_L4", - "CLK_HROW_CK_HCLK_OUT_L5", - "CLK_HROW_CK_HCLK_OUT_L6", - "CLK_HROW_CK_HCLK_OUT_L7", - "CLK_HROW_CK_HCLK_OUT_L8", - "CLK_HROW_CK_HCLK_OUT_L9", - "CLK_HROW_CK_HCLK_OUT_R0", - "CLK_HROW_CK_HCLK_OUT_R1", - "CLK_HROW_CK_HCLK_OUT_R10", - "CLK_HROW_CK_HCLK_OUT_R11", - "CLK_HROW_CK_HCLK_OUT_R2", - "CLK_HROW_CK_HCLK_OUT_R3", - "CLK_HROW_CK_HCLK_OUT_R4", - "CLK_HROW_CK_HCLK_OUT_R5", - "CLK_HROW_CK_HCLK_OUT_R6", - "CLK_HROW_CK_HCLK_OUT_R7", - "CLK_HROW_CK_HCLK_OUT_R8", - "CLK_HROW_CK_HCLK_OUT_R9", - "CLK_HROW_CK_INT_0_0", - "CLK_HROW_CK_INT_0_1", - "CLK_HROW_CK_INT_1_0", - "CLK_HROW_CK_INT_1_1", - "CLK_HROW_CK_IN_L0", - "CLK_HROW_CK_IN_L1", - "CLK_HROW_CK_IN_L10", - "CLK_HROW_CK_IN_L11", - "CLK_HROW_CK_IN_L12", - "CLK_HROW_CK_IN_L13", - "CLK_HROW_CK_IN_L2", - "CLK_HROW_CK_IN_L3", - "CLK_HROW_CK_IN_L4", - "CLK_HROW_CK_IN_L5", - "CLK_HROW_CK_IN_L6", - "CLK_HROW_CK_IN_L7", - "CLK_HROW_CK_IN_L8", - "CLK_HROW_CK_IN_L9", - "CLK_HROW_CK_IN_L_IN_TEST", - "CLK_HROW_CK_IN_L_OUT_TEST", - "CLK_HROW_CK_IN_L_TEST_IN", - "CLK_HROW_CK_IN_L_TEST_OUT", - "CLK_HROW_CK_IN_R0", - "CLK_HROW_CK_IN_R1", - "CLK_HROW_CK_IN_R10", - "CLK_HROW_CK_IN_R11", - "CLK_HROW_CK_IN_R12", - "CLK_HROW_CK_IN_R13", - "CLK_HROW_CK_IN_R2", - "CLK_HROW_CK_IN_R3", - "CLK_HROW_CK_IN_R4", - "CLK_HROW_CK_IN_R5", - "CLK_HROW_CK_IN_R6", - "CLK_HROW_CK_IN_R7", - "CLK_HROW_CK_IN_R8", - "CLK_HROW_CK_IN_R9", - "CLK_HROW_CK_IN_R_IN_TEST", - "CLK_HROW_CK_IN_R_OUT_TEST", - "CLK_HROW_CK_IN_R_TEST_IN", - "CLK_HROW_CK_IN_R_TEST_OUT", - "CLK_HROW_CK_MUX_OUT_L0", - "CLK_HROW_CK_MUX_OUT_L1", - "CLK_HROW_CK_MUX_OUT_L10", - "CLK_HROW_CK_MUX_OUT_L11", - "CLK_HROW_CK_MUX_OUT_L2", - "CLK_HROW_CK_MUX_OUT_L3", - "CLK_HROW_CK_MUX_OUT_L4", - "CLK_HROW_CK_MUX_OUT_L5", - "CLK_HROW_CK_MUX_OUT_L6", - "CLK_HROW_CK_MUX_OUT_L7", - "CLK_HROW_CK_MUX_OUT_L8", - "CLK_HROW_CK_MUX_OUT_L9", - "CLK_HROW_CK_MUX_OUT_R0", - "CLK_HROW_CK_MUX_OUT_R1", - "CLK_HROW_CK_MUX_OUT_R10", - "CLK_HROW_CK_MUX_OUT_R11", - "CLK_HROW_CK_MUX_OUT_R2", - "CLK_HROW_CK_MUX_OUT_R3", - "CLK_HROW_CK_MUX_OUT_R4", - "CLK_HROW_CK_MUX_OUT_R5", - "CLK_HROW_CK_MUX_OUT_R6", - "CLK_HROW_CK_MUX_OUT_R7", - "CLK_HROW_CK_MUX_OUT_R8", - "CLK_HROW_CK_MUX_OUT_R9", - "CLK_HROW_CLK0_0", - "CLK_HROW_CLK0_1", - "CLK_HROW_CLK0_2", - "CLK_HROW_CLK0_3", - "CLK_HROW_CLK0_4", - "CLK_HROW_CLK0_5", - "CLK_HROW_CLK0_6", - "CLK_HROW_CLK0_7", - "CLK_HROW_CLK1_0", - "CLK_HROW_CLK1_1", - "CLK_HROW_CLK1_2", - "CLK_HROW_CLK1_3", - "CLK_HROW_CLK1_4", - "CLK_HROW_CLK1_5", - "CLK_HROW_CLK1_6", - "CLK_HROW_CLK1_7", - "CLK_HROW_CTRL0_0", - "CLK_HROW_CTRL0_1", - "CLK_HROW_CTRL0_2", - "CLK_HROW_CTRL0_3", - "CLK_HROW_CTRL0_4", - "CLK_HROW_CTRL0_5", - "CLK_HROW_CTRL0_6", - "CLK_HROW_CTRL0_7", - "CLK_HROW_CTRL1_0", - "CLK_HROW_CTRL1_1", - "CLK_HROW_CTRL1_2", - "CLK_HROW_CTRL1_3", - "CLK_HROW_CTRL1_4", - "CLK_HROW_CTRL1_5", - "CLK_HROW_CTRL1_6", - "CLK_HROW_CTRL1_7", - "CLK_HROW_EE2A0_0", - "CLK_HROW_EE2A0_1", - "CLK_HROW_EE2A0_2", - "CLK_HROW_EE2A0_3", - "CLK_HROW_EE2A0_4", - "CLK_HROW_EE2A0_5", - "CLK_HROW_EE2A0_6", - "CLK_HROW_EE2A0_7", - "CLK_HROW_EE2A1_0", - "CLK_HROW_EE2A1_1", - "CLK_HROW_EE2A1_2", - "CLK_HROW_EE2A1_3", - "CLK_HROW_EE2A1_4", - "CLK_HROW_EE2A1_5", - "CLK_HROW_EE2A1_6", - "CLK_HROW_EE2A1_7", - "CLK_HROW_EE2A2_0", - "CLK_HROW_EE2A2_1", - "CLK_HROW_EE2A2_2", - "CLK_HROW_EE2A2_3", - "CLK_HROW_EE2A2_4", - "CLK_HROW_EE2A2_5", - "CLK_HROW_EE2A2_6", - "CLK_HROW_EE2A2_7", - "CLK_HROW_EE2A3_0", - "CLK_HROW_EE2A3_1", - "CLK_HROW_EE2A3_2", - "CLK_HROW_EE2A3_3", - "CLK_HROW_EE2A3_4", - "CLK_HROW_EE2A3_5", - "CLK_HROW_EE2A3_6", - "CLK_HROW_EE2A3_7", - "CLK_HROW_EE2BEG0_0", - "CLK_HROW_EE2BEG0_1", - "CLK_HROW_EE2BEG0_2", - "CLK_HROW_EE2BEG0_3", - "CLK_HROW_EE2BEG0_4", - "CLK_HROW_EE2BEG0_5", - "CLK_HROW_EE2BEG0_6", - "CLK_HROW_EE2BEG0_7", - "CLK_HROW_EE2BEG1_0", - "CLK_HROW_EE2BEG1_1", - "CLK_HROW_EE2BEG1_2", - "CLK_HROW_EE2BEG1_3", - "CLK_HROW_EE2BEG1_4", - "CLK_HROW_EE2BEG1_5", - "CLK_HROW_EE2BEG1_6", - "CLK_HROW_EE2BEG1_7", - "CLK_HROW_EE2BEG2_0", - "CLK_HROW_EE2BEG2_1", - "CLK_HROW_EE2BEG2_2", - "CLK_HROW_EE2BEG2_3", - "CLK_HROW_EE2BEG2_4", - "CLK_HROW_EE2BEG2_5", - "CLK_HROW_EE2BEG2_6", - "CLK_HROW_EE2BEG2_7", - "CLK_HROW_EE2BEG3_0", - "CLK_HROW_EE2BEG3_1", - "CLK_HROW_EE2BEG3_2", - "CLK_HROW_EE2BEG3_3", - "CLK_HROW_EE2BEG3_4", - "CLK_HROW_EE2BEG3_5", - "CLK_HROW_EE2BEG3_6", - "CLK_HROW_EE2BEG3_7", - "CLK_HROW_EE4A0_0", - "CLK_HROW_EE4A0_1", - "CLK_HROW_EE4A0_2", - "CLK_HROW_EE4A0_3", - "CLK_HROW_EE4A0_4", - "CLK_HROW_EE4A0_5", - "CLK_HROW_EE4A0_6", - "CLK_HROW_EE4A0_7", - "CLK_HROW_EE4A1_0", - "CLK_HROW_EE4A1_1", - "CLK_HROW_EE4A1_2", - "CLK_HROW_EE4A1_3", - "CLK_HROW_EE4A1_4", - "CLK_HROW_EE4A1_5", - "CLK_HROW_EE4A1_6", - "CLK_HROW_EE4A1_7", - "CLK_HROW_EE4A2_0", - "CLK_HROW_EE4A2_1", - "CLK_HROW_EE4A2_2", - "CLK_HROW_EE4A2_3", - "CLK_HROW_EE4A2_4", - "CLK_HROW_EE4A2_5", - "CLK_HROW_EE4A2_6", - "CLK_HROW_EE4A2_7", - "CLK_HROW_EE4A3_0", - "CLK_HROW_EE4A3_1", - "CLK_HROW_EE4A3_2", - "CLK_HROW_EE4A3_3", - "CLK_HROW_EE4A3_4", - "CLK_HROW_EE4A3_5", - "CLK_HROW_EE4A3_6", - "CLK_HROW_EE4A3_7", - "CLK_HROW_EE4B0_0", - "CLK_HROW_EE4B0_1", - "CLK_HROW_EE4B0_2", - "CLK_HROW_EE4B0_3", - "CLK_HROW_EE4B0_4", - "CLK_HROW_EE4B0_5", - "CLK_HROW_EE4B0_6", - "CLK_HROW_EE4B0_7", - "CLK_HROW_EE4B1_0", - "CLK_HROW_EE4B1_1", - "CLK_HROW_EE4B1_2", - "CLK_HROW_EE4B1_3", - "CLK_HROW_EE4B1_4", - "CLK_HROW_EE4B1_5", - "CLK_HROW_EE4B1_6", - "CLK_HROW_EE4B1_7", - "CLK_HROW_EE4B2_0", - "CLK_HROW_EE4B2_1", - "CLK_HROW_EE4B2_2", - "CLK_HROW_EE4B2_3", - "CLK_HROW_EE4B2_4", - "CLK_HROW_EE4B2_5", - "CLK_HROW_EE4B2_6", - "CLK_HROW_EE4B2_7", - "CLK_HROW_EE4B3_0", - "CLK_HROW_EE4B3_1", - "CLK_HROW_EE4B3_2", - "CLK_HROW_EE4B3_3", - "CLK_HROW_EE4B3_4", - "CLK_HROW_EE4B3_5", - "CLK_HROW_EE4B3_6", - "CLK_HROW_EE4B3_7", - "CLK_HROW_EE4BEG0_0", - "CLK_HROW_EE4BEG0_1", - "CLK_HROW_EE4BEG0_2", - "CLK_HROW_EE4BEG0_3", - "CLK_HROW_EE4BEG0_4", - "CLK_HROW_EE4BEG0_5", - "CLK_HROW_EE4BEG0_6", - "CLK_HROW_EE4BEG0_7", - "CLK_HROW_EE4BEG1_0", - "CLK_HROW_EE4BEG1_1", - "CLK_HROW_EE4BEG1_2", - "CLK_HROW_EE4BEG1_3", - "CLK_HROW_EE4BEG1_4", - "CLK_HROW_EE4BEG1_5", - "CLK_HROW_EE4BEG1_6", - "CLK_HROW_EE4BEG1_7", - "CLK_HROW_EE4BEG2_0", - "CLK_HROW_EE4BEG2_1", - "CLK_HROW_EE4BEG2_2", - "CLK_HROW_EE4BEG2_3", - "CLK_HROW_EE4BEG2_4", - "CLK_HROW_EE4BEG2_5", - "CLK_HROW_EE4BEG2_6", - "CLK_HROW_EE4BEG2_7", - "CLK_HROW_EE4BEG3_0", - "CLK_HROW_EE4BEG3_1", - "CLK_HROW_EE4BEG3_2", - "CLK_HROW_EE4BEG3_3", - "CLK_HROW_EE4BEG3_4", - "CLK_HROW_EE4BEG3_5", - "CLK_HROW_EE4BEG3_6", - "CLK_HROW_EE4BEG3_7", - "CLK_HROW_EE4C0_0", - "CLK_HROW_EE4C0_1", - "CLK_HROW_EE4C0_2", - "CLK_HROW_EE4C0_3", - "CLK_HROW_EE4C0_4", - "CLK_HROW_EE4C0_5", - "CLK_HROW_EE4C0_6", - "CLK_HROW_EE4C0_7", - "CLK_HROW_EE4C1_0", - "CLK_HROW_EE4C1_1", - "CLK_HROW_EE4C1_2", - "CLK_HROW_EE4C1_3", - "CLK_HROW_EE4C1_4", - "CLK_HROW_EE4C1_5", - "CLK_HROW_EE4C1_6", - "CLK_HROW_EE4C1_7", - "CLK_HROW_EE4C2_0", - "CLK_HROW_EE4C2_1", - "CLK_HROW_EE4C2_2", - "CLK_HROW_EE4C2_3", - "CLK_HROW_EE4C2_4", - "CLK_HROW_EE4C2_5", - "CLK_HROW_EE4C2_6", - "CLK_HROW_EE4C2_7", - "CLK_HROW_EE4C3_0", - "CLK_HROW_EE4C3_1", - "CLK_HROW_EE4C3_2", - "CLK_HROW_EE4C3_3", - "CLK_HROW_EE4C3_4", - "CLK_HROW_EE4C3_5", - "CLK_HROW_EE4C3_6", - "CLK_HROW_EE4C3_7", - "CLK_HROW_EL1BEG0_0", - "CLK_HROW_EL1BEG0_1", - "CLK_HROW_EL1BEG0_2", - "CLK_HROW_EL1BEG0_3", - "CLK_HROW_EL1BEG0_4", - "CLK_HROW_EL1BEG0_5", - "CLK_HROW_EL1BEG0_6", - "CLK_HROW_EL1BEG0_7", - "CLK_HROW_EL1BEG1_0", - "CLK_HROW_EL1BEG1_1", - "CLK_HROW_EL1BEG1_2", - "CLK_HROW_EL1BEG1_3", - "CLK_HROW_EL1BEG1_4", - "CLK_HROW_EL1BEG1_5", - "CLK_HROW_EL1BEG1_6", - "CLK_HROW_EL1BEG1_7", - "CLK_HROW_EL1BEG2_0", - "CLK_HROW_EL1BEG2_1", - "CLK_HROW_EL1BEG2_2", - "CLK_HROW_EL1BEG2_3", - "CLK_HROW_EL1BEG2_4", - "CLK_HROW_EL1BEG2_5", - "CLK_HROW_EL1BEG2_6", - "CLK_HROW_EL1BEG2_7", - "CLK_HROW_EL1BEG3_0", - "CLK_HROW_EL1BEG3_1", - "CLK_HROW_EL1BEG3_2", - "CLK_HROW_EL1BEG3_3", - "CLK_HROW_EL1BEG3_4", - "CLK_HROW_EL1BEG3_5", - "CLK_HROW_EL1BEG3_6", - "CLK_HROW_EL1BEG3_7", - "CLK_HROW_ER1BEG0_0", - "CLK_HROW_ER1BEG0_1", - "CLK_HROW_ER1BEG0_2", - "CLK_HROW_ER1BEG0_3", - "CLK_HROW_ER1BEG0_4", - "CLK_HROW_ER1BEG0_5", - "CLK_HROW_ER1BEG0_6", - "CLK_HROW_ER1BEG0_7", - "CLK_HROW_ER1BEG1_0", - "CLK_HROW_ER1BEG1_1", - "CLK_HROW_ER1BEG1_2", - "CLK_HROW_ER1BEG1_3", - "CLK_HROW_ER1BEG1_4", - "CLK_HROW_ER1BEG1_5", - "CLK_HROW_ER1BEG1_6", - "CLK_HROW_ER1BEG1_7", - "CLK_HROW_ER1BEG2_0", - "CLK_HROW_ER1BEG2_1", - "CLK_HROW_ER1BEG2_2", - "CLK_HROW_ER1BEG2_3", - "CLK_HROW_ER1BEG2_4", - "CLK_HROW_ER1BEG2_5", - "CLK_HROW_ER1BEG2_6", - "CLK_HROW_ER1BEG2_7", - "CLK_HROW_ER1BEG3_0", - "CLK_HROW_ER1BEG3_1", - "CLK_HROW_ER1BEG3_2", - "CLK_HROW_ER1BEG3_3", - "CLK_HROW_ER1BEG3_4", - "CLK_HROW_ER1BEG3_5", - "CLK_HROW_ER1BEG3_6", - "CLK_HROW_ER1BEG3_7", - "CLK_HROW_FAN0_0", - "CLK_HROW_FAN0_1", - "CLK_HROW_FAN0_2", - "CLK_HROW_FAN0_3", - "CLK_HROW_FAN0_4", - "CLK_HROW_FAN0_5", - "CLK_HROW_FAN0_6", - "CLK_HROW_FAN0_7", - "CLK_HROW_FAN1_0", - "CLK_HROW_FAN1_1", - "CLK_HROW_FAN1_2", - "CLK_HROW_FAN1_3", - "CLK_HROW_FAN1_4", - "CLK_HROW_FAN1_5", - "CLK_HROW_FAN1_6", - "CLK_HROW_FAN1_7", - "CLK_HROW_FAN2_0", - "CLK_HROW_FAN2_1", - "CLK_HROW_FAN2_2", - "CLK_HROW_FAN2_3", - "CLK_HROW_FAN2_4", - "CLK_HROW_FAN2_5", - "CLK_HROW_FAN2_6", - "CLK_HROW_FAN2_7", - "CLK_HROW_FAN3_0", - "CLK_HROW_FAN3_1", - "CLK_HROW_FAN3_2", - "CLK_HROW_FAN3_3", - "CLK_HROW_FAN3_4", - "CLK_HROW_FAN3_5", - "CLK_HROW_FAN3_6", - "CLK_HROW_FAN3_7", - "CLK_HROW_FAN4_0", - "CLK_HROW_FAN4_1", - "CLK_HROW_FAN4_2", - "CLK_HROW_FAN4_3", - "CLK_HROW_FAN4_4", - "CLK_HROW_FAN4_5", - "CLK_HROW_FAN4_6", - "CLK_HROW_FAN4_7", - "CLK_HROW_FAN5_0", - "CLK_HROW_FAN5_1", - "CLK_HROW_FAN5_2", - "CLK_HROW_FAN5_3", - "CLK_HROW_FAN5_4", - "CLK_HROW_FAN5_5", - "CLK_HROW_FAN5_6", - "CLK_HROW_FAN5_7", - "CLK_HROW_FAN6_0", - "CLK_HROW_FAN6_1", - "CLK_HROW_FAN6_2", - "CLK_HROW_FAN6_3", - "CLK_HROW_FAN6_4", - "CLK_HROW_FAN6_5", - "CLK_HROW_FAN6_6", - "CLK_HROW_FAN6_7", - "CLK_HROW_FAN7_0", - "CLK_HROW_FAN7_1", - "CLK_HROW_FAN7_2", - "CLK_HROW_FAN7_3", - "CLK_HROW_FAN7_4", - "CLK_HROW_FAN7_5", - "CLK_HROW_FAN7_6", - "CLK_HROW_FAN7_7", - "CLK_HROW_IMUX0_0", - "CLK_HROW_IMUX0_1", - "CLK_HROW_IMUX0_2", - "CLK_HROW_IMUX0_3", - "CLK_HROW_IMUX0_4", - "CLK_HROW_IMUX0_5", - "CLK_HROW_IMUX0_6", - "CLK_HROW_IMUX0_7", - "CLK_HROW_IMUX10_0", - "CLK_HROW_IMUX10_1", - "CLK_HROW_IMUX10_2", - "CLK_HROW_IMUX10_3", - "CLK_HROW_IMUX10_4", - "CLK_HROW_IMUX10_5", - "CLK_HROW_IMUX10_6", - "CLK_HROW_IMUX10_7", - "CLK_HROW_IMUX11_0", - "CLK_HROW_IMUX11_1", - "CLK_HROW_IMUX11_2", - "CLK_HROW_IMUX11_3", - "CLK_HROW_IMUX11_4", - "CLK_HROW_IMUX11_5", - "CLK_HROW_IMUX11_6", - "CLK_HROW_IMUX11_7", - "CLK_HROW_IMUX12_0", - "CLK_HROW_IMUX12_1", - "CLK_HROW_IMUX12_2", - "CLK_HROW_IMUX12_3", - "CLK_HROW_IMUX12_4", - "CLK_HROW_IMUX12_5", - "CLK_HROW_IMUX12_6", - "CLK_HROW_IMUX12_7", - "CLK_HROW_IMUX13_0", - "CLK_HROW_IMUX13_1", - "CLK_HROW_IMUX13_2", - "CLK_HROW_IMUX13_3", - "CLK_HROW_IMUX13_4", - "CLK_HROW_IMUX13_5", - "CLK_HROW_IMUX13_6", - "CLK_HROW_IMUX13_7", - "CLK_HROW_IMUX14_0", - "CLK_HROW_IMUX14_1", - "CLK_HROW_IMUX14_2", - "CLK_HROW_IMUX14_3", - "CLK_HROW_IMUX14_4", - "CLK_HROW_IMUX14_5", - "CLK_HROW_IMUX14_6", - "CLK_HROW_IMUX14_7", - "CLK_HROW_IMUX15_0", - "CLK_HROW_IMUX15_1", - "CLK_HROW_IMUX15_2", - "CLK_HROW_IMUX15_3", - "CLK_HROW_IMUX15_4", - "CLK_HROW_IMUX15_5", - "CLK_HROW_IMUX15_6", - "CLK_HROW_IMUX15_7", - "CLK_HROW_IMUX16_0", - "CLK_HROW_IMUX16_1", - "CLK_HROW_IMUX16_2", - "CLK_HROW_IMUX16_3", - "CLK_HROW_IMUX16_4", - "CLK_HROW_IMUX16_5", - "CLK_HROW_IMUX16_6", - "CLK_HROW_IMUX16_7", - "CLK_HROW_IMUX17_0", - "CLK_HROW_IMUX17_1", - "CLK_HROW_IMUX17_2", - "CLK_HROW_IMUX17_3", - "CLK_HROW_IMUX17_4", - "CLK_HROW_IMUX17_5", - "CLK_HROW_IMUX17_6", - "CLK_HROW_IMUX17_7", - "CLK_HROW_IMUX18_0", - "CLK_HROW_IMUX18_1", - "CLK_HROW_IMUX18_2", - "CLK_HROW_IMUX18_3", - "CLK_HROW_IMUX18_4", - "CLK_HROW_IMUX18_5", - "CLK_HROW_IMUX18_6", - "CLK_HROW_IMUX18_7", - "CLK_HROW_IMUX19_0", - "CLK_HROW_IMUX19_1", - "CLK_HROW_IMUX19_2", - "CLK_HROW_IMUX19_3", - "CLK_HROW_IMUX19_4", - "CLK_HROW_IMUX19_5", - "CLK_HROW_IMUX19_6", - "CLK_HROW_IMUX19_7", - "CLK_HROW_IMUX1_0", - "CLK_HROW_IMUX1_1", - "CLK_HROW_IMUX1_2", - "CLK_HROW_IMUX1_3", - "CLK_HROW_IMUX1_4", - "CLK_HROW_IMUX1_5", - "CLK_HROW_IMUX1_6", - "CLK_HROW_IMUX1_7", - "CLK_HROW_IMUX20_0", - "CLK_HROW_IMUX20_1", - "CLK_HROW_IMUX20_2", - "CLK_HROW_IMUX20_3", - "CLK_HROW_IMUX20_4", - "CLK_HROW_IMUX20_5", - "CLK_HROW_IMUX20_6", - "CLK_HROW_IMUX20_7", - "CLK_HROW_IMUX21_0", - "CLK_HROW_IMUX21_1", - "CLK_HROW_IMUX21_2", - "CLK_HROW_IMUX21_3", - "CLK_HROW_IMUX21_4", - "CLK_HROW_IMUX21_5", - "CLK_HROW_IMUX21_6", - "CLK_HROW_IMUX21_7", - "CLK_HROW_IMUX22_0", - "CLK_HROW_IMUX22_1", - "CLK_HROW_IMUX22_2", - "CLK_HROW_IMUX22_3", - "CLK_HROW_IMUX22_4", - "CLK_HROW_IMUX22_5", - "CLK_HROW_IMUX22_6", - "CLK_HROW_IMUX22_7", - "CLK_HROW_IMUX23_0", - "CLK_HROW_IMUX23_1", - "CLK_HROW_IMUX23_2", - "CLK_HROW_IMUX23_3", - "CLK_HROW_IMUX23_4", - "CLK_HROW_IMUX23_5", - "CLK_HROW_IMUX23_6", - "CLK_HROW_IMUX23_7", - "CLK_HROW_IMUX24_0", - "CLK_HROW_IMUX24_1", - "CLK_HROW_IMUX24_2", - "CLK_HROW_IMUX24_3", - "CLK_HROW_IMUX24_4", - "CLK_HROW_IMUX24_5", - "CLK_HROW_IMUX24_6", - "CLK_HROW_IMUX24_7", - "CLK_HROW_IMUX25_0", - "CLK_HROW_IMUX25_1", - "CLK_HROW_IMUX25_2", - "CLK_HROW_IMUX25_3", - "CLK_HROW_IMUX25_4", - "CLK_HROW_IMUX25_5", - "CLK_HROW_IMUX25_6", - "CLK_HROW_IMUX25_7", - "CLK_HROW_IMUX26_0", - "CLK_HROW_IMUX26_1", - "CLK_HROW_IMUX26_2", - "CLK_HROW_IMUX26_3", - "CLK_HROW_IMUX26_4", - "CLK_HROW_IMUX26_5", - "CLK_HROW_IMUX26_6", - "CLK_HROW_IMUX26_7", - "CLK_HROW_IMUX27_0", - "CLK_HROW_IMUX27_1", - "CLK_HROW_IMUX27_2", - "CLK_HROW_IMUX27_3", - "CLK_HROW_IMUX27_4", - "CLK_HROW_IMUX27_5", - "CLK_HROW_IMUX27_6", - "CLK_HROW_IMUX27_7", - "CLK_HROW_IMUX28_0", - "CLK_HROW_IMUX28_1", - "CLK_HROW_IMUX28_2", - "CLK_HROW_IMUX28_3", - "CLK_HROW_IMUX28_4", - "CLK_HROW_IMUX28_5", - "CLK_HROW_IMUX28_6", - "CLK_HROW_IMUX28_7", - "CLK_HROW_IMUX29_0", - "CLK_HROW_IMUX29_1", - "CLK_HROW_IMUX29_2", - "CLK_HROW_IMUX29_3", - "CLK_HROW_IMUX29_4", - "CLK_HROW_IMUX29_5", - "CLK_HROW_IMUX29_6", - "CLK_HROW_IMUX29_7", - "CLK_HROW_IMUX2_0", - "CLK_HROW_IMUX2_1", - "CLK_HROW_IMUX2_2", - "CLK_HROW_IMUX2_3", - "CLK_HROW_IMUX2_4", - "CLK_HROW_IMUX2_5", - "CLK_HROW_IMUX2_6", - "CLK_HROW_IMUX2_7", - "CLK_HROW_IMUX30_0", - "CLK_HROW_IMUX30_1", - "CLK_HROW_IMUX30_2", - "CLK_HROW_IMUX30_3", - "CLK_HROW_IMUX30_4", - "CLK_HROW_IMUX30_5", - "CLK_HROW_IMUX30_6", - "CLK_HROW_IMUX30_7", - "CLK_HROW_IMUX31_0", - "CLK_HROW_IMUX31_1", - "CLK_HROW_IMUX31_2", - "CLK_HROW_IMUX31_3", - "CLK_HROW_IMUX31_4", - "CLK_HROW_IMUX31_5", - "CLK_HROW_IMUX31_6", - "CLK_HROW_IMUX31_7", - "CLK_HROW_IMUX32_0", - "CLK_HROW_IMUX32_1", - "CLK_HROW_IMUX32_2", - "CLK_HROW_IMUX32_3", - "CLK_HROW_IMUX32_4", - "CLK_HROW_IMUX32_5", - "CLK_HROW_IMUX32_6", - "CLK_HROW_IMUX32_7", - "CLK_HROW_IMUX33_0", - "CLK_HROW_IMUX33_1", - "CLK_HROW_IMUX33_2", - "CLK_HROW_IMUX33_3", - "CLK_HROW_IMUX33_4", - "CLK_HROW_IMUX33_5", - "CLK_HROW_IMUX33_6", - "CLK_HROW_IMUX33_7", - "CLK_HROW_IMUX34_0", - "CLK_HROW_IMUX34_1", - "CLK_HROW_IMUX34_2", - "CLK_HROW_IMUX34_3", - "CLK_HROW_IMUX34_4", - "CLK_HROW_IMUX34_5", - "CLK_HROW_IMUX34_6", - "CLK_HROW_IMUX34_7", - "CLK_HROW_IMUX35_0", - "CLK_HROW_IMUX35_1", - "CLK_HROW_IMUX35_2", - "CLK_HROW_IMUX35_3", - "CLK_HROW_IMUX35_4", - "CLK_HROW_IMUX35_5", - "CLK_HROW_IMUX35_6", - "CLK_HROW_IMUX35_7", - "CLK_HROW_IMUX36_0", - "CLK_HROW_IMUX36_1", - "CLK_HROW_IMUX36_2", - "CLK_HROW_IMUX36_3", - "CLK_HROW_IMUX36_4", - "CLK_HROW_IMUX36_5", - "CLK_HROW_IMUX36_6", - "CLK_HROW_IMUX36_7", - "CLK_HROW_IMUX37_0", - "CLK_HROW_IMUX37_1", - "CLK_HROW_IMUX37_2", - "CLK_HROW_IMUX37_3", - "CLK_HROW_IMUX37_4", - "CLK_HROW_IMUX37_5", - "CLK_HROW_IMUX37_6", - "CLK_HROW_IMUX37_7", - "CLK_HROW_IMUX38_0", - "CLK_HROW_IMUX38_1", - "CLK_HROW_IMUX38_2", - "CLK_HROW_IMUX38_3", - "CLK_HROW_IMUX38_4", - "CLK_HROW_IMUX38_5", - "CLK_HROW_IMUX38_6", - "CLK_HROW_IMUX38_7", - "CLK_HROW_IMUX39_0", - "CLK_HROW_IMUX39_1", - "CLK_HROW_IMUX39_2", - "CLK_HROW_IMUX39_3", - "CLK_HROW_IMUX39_4", - "CLK_HROW_IMUX39_5", - "CLK_HROW_IMUX39_6", - "CLK_HROW_IMUX39_7", - "CLK_HROW_IMUX3_0", - "CLK_HROW_IMUX3_1", - "CLK_HROW_IMUX3_2", - "CLK_HROW_IMUX3_3", - "CLK_HROW_IMUX3_4", - "CLK_HROW_IMUX3_5", - "CLK_HROW_IMUX3_6", - "CLK_HROW_IMUX3_7", - "CLK_HROW_IMUX40_0", - "CLK_HROW_IMUX40_1", - "CLK_HROW_IMUX40_2", - "CLK_HROW_IMUX40_3", - "CLK_HROW_IMUX40_4", - "CLK_HROW_IMUX40_5", - "CLK_HROW_IMUX40_6", - "CLK_HROW_IMUX40_7", - "CLK_HROW_IMUX41_0", - "CLK_HROW_IMUX41_1", - "CLK_HROW_IMUX41_2", - "CLK_HROW_IMUX41_3", - "CLK_HROW_IMUX41_4", - "CLK_HROW_IMUX41_5", - "CLK_HROW_IMUX41_6", - "CLK_HROW_IMUX41_7", - "CLK_HROW_IMUX42_0", - "CLK_HROW_IMUX42_1", - "CLK_HROW_IMUX42_2", - "CLK_HROW_IMUX42_3", - "CLK_HROW_IMUX42_4", - "CLK_HROW_IMUX42_5", - "CLK_HROW_IMUX42_6", - "CLK_HROW_IMUX42_7", - "CLK_HROW_IMUX43_0", - "CLK_HROW_IMUX43_1", - "CLK_HROW_IMUX43_2", - "CLK_HROW_IMUX43_3", - "CLK_HROW_IMUX43_4", - "CLK_HROW_IMUX43_5", - "CLK_HROW_IMUX43_6", - "CLK_HROW_IMUX43_7", - "CLK_HROW_IMUX44_0", - "CLK_HROW_IMUX44_1", - "CLK_HROW_IMUX44_2", - "CLK_HROW_IMUX44_3", - "CLK_HROW_IMUX44_4", - "CLK_HROW_IMUX44_5", - "CLK_HROW_IMUX44_6", - "CLK_HROW_IMUX44_7", - "CLK_HROW_IMUX45_0", - "CLK_HROW_IMUX45_1", - "CLK_HROW_IMUX45_2", - "CLK_HROW_IMUX45_3", - "CLK_HROW_IMUX45_4", - "CLK_HROW_IMUX45_5", - "CLK_HROW_IMUX45_6", - "CLK_HROW_IMUX45_7", - "CLK_HROW_IMUX46_0", - "CLK_HROW_IMUX46_1", - "CLK_HROW_IMUX46_2", - "CLK_HROW_IMUX46_3", - "CLK_HROW_IMUX46_4", - "CLK_HROW_IMUX46_5", - "CLK_HROW_IMUX46_6", - "CLK_HROW_IMUX46_7", - "CLK_HROW_IMUX47_0", - "CLK_HROW_IMUX47_1", - "CLK_HROW_IMUX47_2", - "CLK_HROW_IMUX47_3", - "CLK_HROW_IMUX47_4", - "CLK_HROW_IMUX47_5", - "CLK_HROW_IMUX47_6", - "CLK_HROW_IMUX47_7", - "CLK_HROW_IMUX4_0", - "CLK_HROW_IMUX4_1", - "CLK_HROW_IMUX4_2", - "CLK_HROW_IMUX4_3", - "CLK_HROW_IMUX4_4", - "CLK_HROW_IMUX4_5", - "CLK_HROW_IMUX4_6", - "CLK_HROW_IMUX4_7", - "CLK_HROW_IMUX5_0", - "CLK_HROW_IMUX5_1", - "CLK_HROW_IMUX5_2", - "CLK_HROW_IMUX5_3", - "CLK_HROW_IMUX5_4", - "CLK_HROW_IMUX5_5", - "CLK_HROW_IMUX5_6", - "CLK_HROW_IMUX5_7", - "CLK_HROW_IMUX6_0", - "CLK_HROW_IMUX6_1", - "CLK_HROW_IMUX6_2", - "CLK_HROW_IMUX6_3", - "CLK_HROW_IMUX6_4", - "CLK_HROW_IMUX6_5", - "CLK_HROW_IMUX6_6", - "CLK_HROW_IMUX6_7", - "CLK_HROW_IMUX7_0", - "CLK_HROW_IMUX7_1", - "CLK_HROW_IMUX7_2", - "CLK_HROW_IMUX7_3", - "CLK_HROW_IMUX7_4", - "CLK_HROW_IMUX7_5", - "CLK_HROW_IMUX7_6", - "CLK_HROW_IMUX7_7", - "CLK_HROW_IMUX8_0", - "CLK_HROW_IMUX8_1", - "CLK_HROW_IMUX8_2", - "CLK_HROW_IMUX8_3", - "CLK_HROW_IMUX8_4", - "CLK_HROW_IMUX8_5", - "CLK_HROW_IMUX8_6", - "CLK_HROW_IMUX8_7", - "CLK_HROW_IMUX9_0", - "CLK_HROW_IMUX9_1", - "CLK_HROW_IMUX9_2", - "CLK_HROW_IMUX9_3", - "CLK_HROW_IMUX9_4", - "CLK_HROW_IMUX9_5", - "CLK_HROW_IMUX9_6", - "CLK_HROW_IMUX9_7", - "CLK_HROW_LH10_0", - "CLK_HROW_LH10_1", - "CLK_HROW_LH10_2", - "CLK_HROW_LH10_3", - "CLK_HROW_LH10_4", - "CLK_HROW_LH10_5", - "CLK_HROW_LH10_6", - "CLK_HROW_LH10_7", - "CLK_HROW_LH11_0", - "CLK_HROW_LH11_1", - "CLK_HROW_LH11_2", - "CLK_HROW_LH11_3", - "CLK_HROW_LH11_4", - "CLK_HROW_LH11_5", - "CLK_HROW_LH11_6", - "CLK_HROW_LH11_7", - "CLK_HROW_LH12_0", - "CLK_HROW_LH12_1", - "CLK_HROW_LH12_2", - "CLK_HROW_LH12_3", - "CLK_HROW_LH12_4", - "CLK_HROW_LH12_5", - "CLK_HROW_LH12_6", - "CLK_HROW_LH12_7", - "CLK_HROW_LH1_0", - "CLK_HROW_LH1_1", - "CLK_HROW_LH1_2", - "CLK_HROW_LH1_3", - "CLK_HROW_LH1_4", - "CLK_HROW_LH1_5", - "CLK_HROW_LH1_6", - "CLK_HROW_LH1_7", - "CLK_HROW_LH2_0", - "CLK_HROW_LH2_1", - "CLK_HROW_LH2_2", - "CLK_HROW_LH2_3", - "CLK_HROW_LH2_4", - "CLK_HROW_LH2_5", - "CLK_HROW_LH2_6", - "CLK_HROW_LH2_7", - "CLK_HROW_LH3_0", - "CLK_HROW_LH3_1", - "CLK_HROW_LH3_2", - "CLK_HROW_LH3_3", - "CLK_HROW_LH3_4", - "CLK_HROW_LH3_5", - "CLK_HROW_LH3_6", - "CLK_HROW_LH3_7", - "CLK_HROW_LH4_0", - "CLK_HROW_LH4_1", - "CLK_HROW_LH4_2", - "CLK_HROW_LH4_3", - "CLK_HROW_LH4_4", - "CLK_HROW_LH4_5", - "CLK_HROW_LH4_6", - "CLK_HROW_LH4_7", - "CLK_HROW_LH5_0", - "CLK_HROW_LH5_1", - "CLK_HROW_LH5_2", - "CLK_HROW_LH5_3", - "CLK_HROW_LH5_4", - "CLK_HROW_LH5_5", - "CLK_HROW_LH5_6", - "CLK_HROW_LH5_7", - "CLK_HROW_LH6_0", - "CLK_HROW_LH6_1", - "CLK_HROW_LH6_2", - "CLK_HROW_LH6_3", - "CLK_HROW_LH6_4", - "CLK_HROW_LH6_5", - "CLK_HROW_LH6_6", - "CLK_HROW_LH6_7", - "CLK_HROW_LH7_0", - "CLK_HROW_LH7_1", - "CLK_HROW_LH7_2", - "CLK_HROW_LH7_3", - "CLK_HROW_LH7_4", - "CLK_HROW_LH7_5", - "CLK_HROW_LH7_6", - "CLK_HROW_LH7_7", - "CLK_HROW_LH8_0", - "CLK_HROW_LH8_1", - "CLK_HROW_LH8_2", - "CLK_HROW_LH8_3", - "CLK_HROW_LH8_4", - "CLK_HROW_LH8_5", - "CLK_HROW_LH8_6", - "CLK_HROW_LH8_7", - "CLK_HROW_LH9_0", - "CLK_HROW_LH9_1", - "CLK_HROW_LH9_2", - "CLK_HROW_LH9_3", - "CLK_HROW_LH9_4", - "CLK_HROW_LH9_5", - "CLK_HROW_LH9_6", - "CLK_HROW_LH9_7", - "CLK_HROW_LOGIC_OUTS_B0_0", - "CLK_HROW_LOGIC_OUTS_B0_1", - "CLK_HROW_LOGIC_OUTS_B0_2", - "CLK_HROW_LOGIC_OUTS_B0_3", - "CLK_HROW_LOGIC_OUTS_B0_4", - "CLK_HROW_LOGIC_OUTS_B0_5", - "CLK_HROW_LOGIC_OUTS_B0_6", - "CLK_HROW_LOGIC_OUTS_B0_7", - "CLK_HROW_LOGIC_OUTS_B10_0", - "CLK_HROW_LOGIC_OUTS_B10_1", - "CLK_HROW_LOGIC_OUTS_B10_2", - "CLK_HROW_LOGIC_OUTS_B10_3", - "CLK_HROW_LOGIC_OUTS_B10_4", - "CLK_HROW_LOGIC_OUTS_B10_5", - "CLK_HROW_LOGIC_OUTS_B10_6", - "CLK_HROW_LOGIC_OUTS_B10_7", - "CLK_HROW_LOGIC_OUTS_B11_0", - "CLK_HROW_LOGIC_OUTS_B11_1", - "CLK_HROW_LOGIC_OUTS_B11_2", - "CLK_HROW_LOGIC_OUTS_B11_3", - "CLK_HROW_LOGIC_OUTS_B11_4", - "CLK_HROW_LOGIC_OUTS_B11_5", - "CLK_HROW_LOGIC_OUTS_B11_6", - "CLK_HROW_LOGIC_OUTS_B11_7", - "CLK_HROW_LOGIC_OUTS_B12_0", - "CLK_HROW_LOGIC_OUTS_B12_1", - "CLK_HROW_LOGIC_OUTS_B12_2", - "CLK_HROW_LOGIC_OUTS_B12_3", - "CLK_HROW_LOGIC_OUTS_B12_4", - "CLK_HROW_LOGIC_OUTS_B12_5", - "CLK_HROW_LOGIC_OUTS_B12_6", - "CLK_HROW_LOGIC_OUTS_B12_7", - "CLK_HROW_LOGIC_OUTS_B13_0", - "CLK_HROW_LOGIC_OUTS_B13_1", - "CLK_HROW_LOGIC_OUTS_B13_2", - "CLK_HROW_LOGIC_OUTS_B13_3", - "CLK_HROW_LOGIC_OUTS_B13_4", - "CLK_HROW_LOGIC_OUTS_B13_5", - "CLK_HROW_LOGIC_OUTS_B13_6", - "CLK_HROW_LOGIC_OUTS_B13_7", - "CLK_HROW_LOGIC_OUTS_B14_0", - "CLK_HROW_LOGIC_OUTS_B14_1", - "CLK_HROW_LOGIC_OUTS_B14_2", - "CLK_HROW_LOGIC_OUTS_B14_3", - "CLK_HROW_LOGIC_OUTS_B14_4", - "CLK_HROW_LOGIC_OUTS_B14_5", - "CLK_HROW_LOGIC_OUTS_B14_6", - "CLK_HROW_LOGIC_OUTS_B14_7", - "CLK_HROW_LOGIC_OUTS_B15_0", - "CLK_HROW_LOGIC_OUTS_B15_1", - "CLK_HROW_LOGIC_OUTS_B15_2", - "CLK_HROW_LOGIC_OUTS_B15_3", - "CLK_HROW_LOGIC_OUTS_B15_4", - "CLK_HROW_LOGIC_OUTS_B15_5", - "CLK_HROW_LOGIC_OUTS_B15_6", - "CLK_HROW_LOGIC_OUTS_B15_7", - "CLK_HROW_LOGIC_OUTS_B16_0", - "CLK_HROW_LOGIC_OUTS_B16_1", - "CLK_HROW_LOGIC_OUTS_B16_2", - "CLK_HROW_LOGIC_OUTS_B16_3", - "CLK_HROW_LOGIC_OUTS_B16_4", - "CLK_HROW_LOGIC_OUTS_B16_5", - "CLK_HROW_LOGIC_OUTS_B16_6", - "CLK_HROW_LOGIC_OUTS_B16_7", - "CLK_HROW_LOGIC_OUTS_B17_0", - "CLK_HROW_LOGIC_OUTS_B17_1", - "CLK_HROW_LOGIC_OUTS_B17_2", - "CLK_HROW_LOGIC_OUTS_B17_3", - "CLK_HROW_LOGIC_OUTS_B17_4", - "CLK_HROW_LOGIC_OUTS_B17_5", - "CLK_HROW_LOGIC_OUTS_B17_6", - "CLK_HROW_LOGIC_OUTS_B17_7", - "CLK_HROW_LOGIC_OUTS_B18_0", - "CLK_HROW_LOGIC_OUTS_B18_1", - "CLK_HROW_LOGIC_OUTS_B18_2", - "CLK_HROW_LOGIC_OUTS_B18_3", - "CLK_HROW_LOGIC_OUTS_B18_4", - "CLK_HROW_LOGIC_OUTS_B18_5", - "CLK_HROW_LOGIC_OUTS_B18_6", - "CLK_HROW_LOGIC_OUTS_B18_7", - "CLK_HROW_LOGIC_OUTS_B19_0", - "CLK_HROW_LOGIC_OUTS_B19_1", - "CLK_HROW_LOGIC_OUTS_B19_2", - "CLK_HROW_LOGIC_OUTS_B19_3", - "CLK_HROW_LOGIC_OUTS_B19_4", - "CLK_HROW_LOGIC_OUTS_B19_5", - "CLK_HROW_LOGIC_OUTS_B19_6", - "CLK_HROW_LOGIC_OUTS_B19_7", - "CLK_HROW_LOGIC_OUTS_B1_0", - "CLK_HROW_LOGIC_OUTS_B1_1", - "CLK_HROW_LOGIC_OUTS_B1_2", - "CLK_HROW_LOGIC_OUTS_B1_3", - "CLK_HROW_LOGIC_OUTS_B1_4", - "CLK_HROW_LOGIC_OUTS_B1_5", - "CLK_HROW_LOGIC_OUTS_B1_6", - "CLK_HROW_LOGIC_OUTS_B1_7", - "CLK_HROW_LOGIC_OUTS_B20_0", - "CLK_HROW_LOGIC_OUTS_B20_1", - "CLK_HROW_LOGIC_OUTS_B20_2", - "CLK_HROW_LOGIC_OUTS_B20_3", - "CLK_HROW_LOGIC_OUTS_B20_4", - "CLK_HROW_LOGIC_OUTS_B20_5", - "CLK_HROW_LOGIC_OUTS_B20_6", - "CLK_HROW_LOGIC_OUTS_B20_7", - "CLK_HROW_LOGIC_OUTS_B21_0", - "CLK_HROW_LOGIC_OUTS_B21_1", - "CLK_HROW_LOGIC_OUTS_B21_2", - "CLK_HROW_LOGIC_OUTS_B21_3", - "CLK_HROW_LOGIC_OUTS_B21_4", - "CLK_HROW_LOGIC_OUTS_B21_5", - "CLK_HROW_LOGIC_OUTS_B21_6", - "CLK_HROW_LOGIC_OUTS_B21_7", - "CLK_HROW_LOGIC_OUTS_B22_0", - "CLK_HROW_LOGIC_OUTS_B22_1", - "CLK_HROW_LOGIC_OUTS_B22_2", - "CLK_HROW_LOGIC_OUTS_B22_3", - "CLK_HROW_LOGIC_OUTS_B22_4", - "CLK_HROW_LOGIC_OUTS_B22_5", - "CLK_HROW_LOGIC_OUTS_B22_6", - "CLK_HROW_LOGIC_OUTS_B22_7", - "CLK_HROW_LOGIC_OUTS_B23_0", - "CLK_HROW_LOGIC_OUTS_B23_1", - "CLK_HROW_LOGIC_OUTS_B23_2", - "CLK_HROW_LOGIC_OUTS_B23_3", - "CLK_HROW_LOGIC_OUTS_B23_4", - "CLK_HROW_LOGIC_OUTS_B23_5", - "CLK_HROW_LOGIC_OUTS_B23_6", - "CLK_HROW_LOGIC_OUTS_B23_7", - "CLK_HROW_LOGIC_OUTS_B2_0", - "CLK_HROW_LOGIC_OUTS_B2_1", - "CLK_HROW_LOGIC_OUTS_B2_2", - "CLK_HROW_LOGIC_OUTS_B2_3", - "CLK_HROW_LOGIC_OUTS_B2_4", - "CLK_HROW_LOGIC_OUTS_B2_5", - "CLK_HROW_LOGIC_OUTS_B2_6", - "CLK_HROW_LOGIC_OUTS_B2_7", - "CLK_HROW_LOGIC_OUTS_B3_0", - "CLK_HROW_LOGIC_OUTS_B3_1", - "CLK_HROW_LOGIC_OUTS_B3_2", - "CLK_HROW_LOGIC_OUTS_B3_3", - "CLK_HROW_LOGIC_OUTS_B3_4", - "CLK_HROW_LOGIC_OUTS_B3_5", - "CLK_HROW_LOGIC_OUTS_B3_6", - "CLK_HROW_LOGIC_OUTS_B3_7", - "CLK_HROW_LOGIC_OUTS_B4_0", - "CLK_HROW_LOGIC_OUTS_B4_1", - "CLK_HROW_LOGIC_OUTS_B4_2", - "CLK_HROW_LOGIC_OUTS_B4_3", - "CLK_HROW_LOGIC_OUTS_B4_4", - "CLK_HROW_LOGIC_OUTS_B4_5", - "CLK_HROW_LOGIC_OUTS_B4_6", - "CLK_HROW_LOGIC_OUTS_B4_7", - "CLK_HROW_LOGIC_OUTS_B5_0", - "CLK_HROW_LOGIC_OUTS_B5_1", - "CLK_HROW_LOGIC_OUTS_B5_2", - "CLK_HROW_LOGIC_OUTS_B5_3", - "CLK_HROW_LOGIC_OUTS_B5_4", - "CLK_HROW_LOGIC_OUTS_B5_5", - "CLK_HROW_LOGIC_OUTS_B5_6", - "CLK_HROW_LOGIC_OUTS_B5_7", - "CLK_HROW_LOGIC_OUTS_B6_0", - "CLK_HROW_LOGIC_OUTS_B6_1", - "CLK_HROW_LOGIC_OUTS_B6_2", - "CLK_HROW_LOGIC_OUTS_B6_3", - "CLK_HROW_LOGIC_OUTS_B6_4", - "CLK_HROW_LOGIC_OUTS_B6_5", - "CLK_HROW_LOGIC_OUTS_B6_6", - "CLK_HROW_LOGIC_OUTS_B6_7", - "CLK_HROW_LOGIC_OUTS_B7_0", - "CLK_HROW_LOGIC_OUTS_B7_1", - "CLK_HROW_LOGIC_OUTS_B7_2", - "CLK_HROW_LOGIC_OUTS_B7_3", - "CLK_HROW_LOGIC_OUTS_B7_4", - "CLK_HROW_LOGIC_OUTS_B7_5", - "CLK_HROW_LOGIC_OUTS_B7_6", - "CLK_HROW_LOGIC_OUTS_B7_7", - "CLK_HROW_LOGIC_OUTS_B8_0", - "CLK_HROW_LOGIC_OUTS_B8_1", - "CLK_HROW_LOGIC_OUTS_B8_2", - "CLK_HROW_LOGIC_OUTS_B8_3", - "CLK_HROW_LOGIC_OUTS_B8_4", - "CLK_HROW_LOGIC_OUTS_B8_5", - "CLK_HROW_LOGIC_OUTS_B8_6", - "CLK_HROW_LOGIC_OUTS_B8_7", - "CLK_HROW_LOGIC_OUTS_B9_0", - "CLK_HROW_LOGIC_OUTS_B9_1", - "CLK_HROW_LOGIC_OUTS_B9_2", - "CLK_HROW_LOGIC_OUTS_B9_3", - "CLK_HROW_LOGIC_OUTS_B9_4", - "CLK_HROW_LOGIC_OUTS_B9_5", - "CLK_HROW_LOGIC_OUTS_B9_6", - "CLK_HROW_LOGIC_OUTS_B9_7", - "CLK_HROW_MONITOR_N_0", - "CLK_HROW_MONITOR_N_1", - "CLK_HROW_MONITOR_N_2", - "CLK_HROW_MONITOR_N_3", - "CLK_HROW_MONITOR_N_4", - "CLK_HROW_MONITOR_N_5", - "CLK_HROW_MONITOR_N_6", - "CLK_HROW_MONITOR_N_7", - "CLK_HROW_MONITOR_P_0", - "CLK_HROW_MONITOR_P_1", - "CLK_HROW_MONITOR_P_2", - "CLK_HROW_MONITOR_P_3", - "CLK_HROW_MONITOR_P_4", - "CLK_HROW_MONITOR_P_5", - "CLK_HROW_MONITOR_P_6", - "CLK_HROW_MONITOR_P_7", - "CLK_HROW_NE2A0_0", - "CLK_HROW_NE2A0_1", - "CLK_HROW_NE2A0_2", - "CLK_HROW_NE2A0_3", - "CLK_HROW_NE2A0_4", - "CLK_HROW_NE2A0_5", - "CLK_HROW_NE2A0_6", - "CLK_HROW_NE2A0_7", - "CLK_HROW_NE2A1_0", - "CLK_HROW_NE2A1_1", - "CLK_HROW_NE2A1_2", - "CLK_HROW_NE2A1_3", - "CLK_HROW_NE2A1_4", - "CLK_HROW_NE2A1_5", - "CLK_HROW_NE2A1_6", - "CLK_HROW_NE2A1_7", - "CLK_HROW_NE2A2_0", - "CLK_HROW_NE2A2_1", - "CLK_HROW_NE2A2_2", - "CLK_HROW_NE2A2_3", - "CLK_HROW_NE2A2_4", - "CLK_HROW_NE2A2_5", - "CLK_HROW_NE2A2_6", - "CLK_HROW_NE2A2_7", - "CLK_HROW_NE2A3_0", - "CLK_HROW_NE2A3_1", - "CLK_HROW_NE2A3_2", - "CLK_HROW_NE2A3_3", - "CLK_HROW_NE2A3_4", - "CLK_HROW_NE2A3_5", - "CLK_HROW_NE2A3_6", - "CLK_HROW_NE2A3_7", - "CLK_HROW_NE4BEG0_0", - "CLK_HROW_NE4BEG0_1", - "CLK_HROW_NE4BEG0_2", - "CLK_HROW_NE4BEG0_3", - "CLK_HROW_NE4BEG0_4", - "CLK_HROW_NE4BEG0_5", - "CLK_HROW_NE4BEG0_6", - "CLK_HROW_NE4BEG0_7", - "CLK_HROW_NE4BEG1_0", - "CLK_HROW_NE4BEG1_1", - "CLK_HROW_NE4BEG1_2", - "CLK_HROW_NE4BEG1_3", - "CLK_HROW_NE4BEG1_4", - "CLK_HROW_NE4BEG1_5", - "CLK_HROW_NE4BEG1_6", - "CLK_HROW_NE4BEG1_7", - "CLK_HROW_NE4BEG2_0", - "CLK_HROW_NE4BEG2_1", - "CLK_HROW_NE4BEG2_2", - "CLK_HROW_NE4BEG2_3", - "CLK_HROW_NE4BEG2_4", - "CLK_HROW_NE4BEG2_5", - "CLK_HROW_NE4BEG2_6", - "CLK_HROW_NE4BEG2_7", - "CLK_HROW_NE4BEG3_0", - "CLK_HROW_NE4BEG3_1", - "CLK_HROW_NE4BEG3_2", - "CLK_HROW_NE4BEG3_3", - "CLK_HROW_NE4BEG3_4", - "CLK_HROW_NE4BEG3_5", - "CLK_HROW_NE4BEG3_6", - "CLK_HROW_NE4BEG3_7", - "CLK_HROW_NE4C0_0", - "CLK_HROW_NE4C0_1", - "CLK_HROW_NE4C0_2", - "CLK_HROW_NE4C0_3", - "CLK_HROW_NE4C0_4", - "CLK_HROW_NE4C0_5", - "CLK_HROW_NE4C0_6", - "CLK_HROW_NE4C0_7", - "CLK_HROW_NE4C1_0", - "CLK_HROW_NE4C1_1", - "CLK_HROW_NE4C1_2", - "CLK_HROW_NE4C1_3", - "CLK_HROW_NE4C1_4", - "CLK_HROW_NE4C1_5", - "CLK_HROW_NE4C1_6", - "CLK_HROW_NE4C1_7", - "CLK_HROW_NE4C2_0", - "CLK_HROW_NE4C2_1", - "CLK_HROW_NE4C2_2", - "CLK_HROW_NE4C2_3", - "CLK_HROW_NE4C2_4", - "CLK_HROW_NE4C2_5", - "CLK_HROW_NE4C2_6", - "CLK_HROW_NE4C2_7", - "CLK_HROW_NE4C3_0", - "CLK_HROW_NE4C3_1", - "CLK_HROW_NE4C3_2", - "CLK_HROW_NE4C3_3", - "CLK_HROW_NE4C3_4", - "CLK_HROW_NE4C3_5", - "CLK_HROW_NE4C3_6", - "CLK_HROW_NE4C3_7", - "CLK_HROW_NW2A0_0", - "CLK_HROW_NW2A0_1", - "CLK_HROW_NW2A0_2", - "CLK_HROW_NW2A0_3", - "CLK_HROW_NW2A0_4", - "CLK_HROW_NW2A0_5", - "CLK_HROW_NW2A0_6", - "CLK_HROW_NW2A0_7", - "CLK_HROW_NW2A1_0", - "CLK_HROW_NW2A1_1", - "CLK_HROW_NW2A1_2", - "CLK_HROW_NW2A1_3", - "CLK_HROW_NW2A1_4", - "CLK_HROW_NW2A1_5", - "CLK_HROW_NW2A1_6", - "CLK_HROW_NW2A1_7", - "CLK_HROW_NW2A2_0", - "CLK_HROW_NW2A2_1", - "CLK_HROW_NW2A2_2", - "CLK_HROW_NW2A2_3", - "CLK_HROW_NW2A2_4", - "CLK_HROW_NW2A2_5", - "CLK_HROW_NW2A2_6", - "CLK_HROW_NW2A2_7", - "CLK_HROW_NW2A3_0", - "CLK_HROW_NW2A3_1", - "CLK_HROW_NW2A3_2", - "CLK_HROW_NW2A3_3", - "CLK_HROW_NW2A3_4", - "CLK_HROW_NW2A3_5", - "CLK_HROW_NW2A3_6", - "CLK_HROW_NW2A3_7", - "CLK_HROW_NW4A0_0", - "CLK_HROW_NW4A0_1", - "CLK_HROW_NW4A0_2", - "CLK_HROW_NW4A0_3", - "CLK_HROW_NW4A0_4", - "CLK_HROW_NW4A0_5", - "CLK_HROW_NW4A0_6", - "CLK_HROW_NW4A0_7", - "CLK_HROW_NW4A1_0", - "CLK_HROW_NW4A1_1", - "CLK_HROW_NW4A1_2", - "CLK_HROW_NW4A1_3", - "CLK_HROW_NW4A1_4", - "CLK_HROW_NW4A1_5", - "CLK_HROW_NW4A1_6", - "CLK_HROW_NW4A1_7", - "CLK_HROW_NW4A2_0", - "CLK_HROW_NW4A2_1", - "CLK_HROW_NW4A2_2", - "CLK_HROW_NW4A2_3", - "CLK_HROW_NW4A2_4", - "CLK_HROW_NW4A2_5", - "CLK_HROW_NW4A2_6", - "CLK_HROW_NW4A2_7", - "CLK_HROW_NW4A3_0", - "CLK_HROW_NW4A3_1", - "CLK_HROW_NW4A3_2", - "CLK_HROW_NW4A3_3", - "CLK_HROW_NW4A3_4", - "CLK_HROW_NW4A3_5", - "CLK_HROW_NW4A3_6", - "CLK_HROW_NW4A3_7", - "CLK_HROW_NW4END0_0", - "CLK_HROW_NW4END0_1", - "CLK_HROW_NW4END0_2", - "CLK_HROW_NW4END0_3", - "CLK_HROW_NW4END0_4", - "CLK_HROW_NW4END0_5", - "CLK_HROW_NW4END0_6", - "CLK_HROW_NW4END0_7", - "CLK_HROW_NW4END1_0", - "CLK_HROW_NW4END1_1", - "CLK_HROW_NW4END1_2", - "CLK_HROW_NW4END1_3", - "CLK_HROW_NW4END1_4", - "CLK_HROW_NW4END1_5", - "CLK_HROW_NW4END1_6", - "CLK_HROW_NW4END1_7", - "CLK_HROW_NW4END2_0", - "CLK_HROW_NW4END2_1", - "CLK_HROW_NW4END2_2", - "CLK_HROW_NW4END2_3", - "CLK_HROW_NW4END2_4", - "CLK_HROW_NW4END2_5", - "CLK_HROW_NW4END2_6", - "CLK_HROW_NW4END2_7", - "CLK_HROW_NW4END3_0", - "CLK_HROW_NW4END3_1", - "CLK_HROW_NW4END3_2", - "CLK_HROW_NW4END3_3", - "CLK_HROW_NW4END3_4", - "CLK_HROW_NW4END3_5", - "CLK_HROW_NW4END3_6", - "CLK_HROW_NW4END3_7", - "CLK_HROW_REFCK_EASTCLK0", - "CLK_HROW_REFCK_EASTCLK1", - "CLK_HROW_REFCK_WESTCLK0", - "CLK_HROW_REFCK_WESTCLK1", - "CLK_HROW_R_CK_GCLK0", - "CLK_HROW_R_CK_GCLK1", - "CLK_HROW_R_CK_GCLK10", - "CLK_HROW_R_CK_GCLK11", - "CLK_HROW_R_CK_GCLK12", - "CLK_HROW_R_CK_GCLK13", - "CLK_HROW_R_CK_GCLK14", - "CLK_HROW_R_CK_GCLK15", - "CLK_HROW_R_CK_GCLK16", - "CLK_HROW_R_CK_GCLK17", - "CLK_HROW_R_CK_GCLK18", - "CLK_HROW_R_CK_GCLK19", - "CLK_HROW_R_CK_GCLK2", - "CLK_HROW_R_CK_GCLK20", - "CLK_HROW_R_CK_GCLK21", - "CLK_HROW_R_CK_GCLK22", - "CLK_HROW_R_CK_GCLK23", - "CLK_HROW_R_CK_GCLK24", - "CLK_HROW_R_CK_GCLK25", - "CLK_HROW_R_CK_GCLK26", - "CLK_HROW_R_CK_GCLK27", - "CLK_HROW_R_CK_GCLK28", - "CLK_HROW_R_CK_GCLK29", - "CLK_HROW_R_CK_GCLK3", - "CLK_HROW_R_CK_GCLK30", - "CLK_HROW_R_CK_GCLK31", - "CLK_HROW_R_CK_GCLK4", - "CLK_HROW_R_CK_GCLK5", - "CLK_HROW_R_CK_GCLK6", - "CLK_HROW_R_CK_GCLK7", - "CLK_HROW_R_CK_GCLK8", - "CLK_HROW_R_CK_GCLK9", - "CLK_HROW_SE2A0_0", - "CLK_HROW_SE2A0_1", - "CLK_HROW_SE2A0_2", - "CLK_HROW_SE2A0_3", - "CLK_HROW_SE2A0_4", - "CLK_HROW_SE2A0_5", - "CLK_HROW_SE2A0_6", - "CLK_HROW_SE2A0_7", - "CLK_HROW_SE2A1_0", - "CLK_HROW_SE2A1_1", - "CLK_HROW_SE2A1_2", - "CLK_HROW_SE2A1_3", - "CLK_HROW_SE2A1_4", - "CLK_HROW_SE2A1_5", - "CLK_HROW_SE2A1_6", - "CLK_HROW_SE2A1_7", - "CLK_HROW_SE2A2_0", - "CLK_HROW_SE2A2_1", - "CLK_HROW_SE2A2_2", - "CLK_HROW_SE2A2_3", - "CLK_HROW_SE2A2_4", - "CLK_HROW_SE2A2_5", - "CLK_HROW_SE2A2_6", - "CLK_HROW_SE2A2_7", - "CLK_HROW_SE2A3_0", - "CLK_HROW_SE2A3_1", - "CLK_HROW_SE2A3_2", - "CLK_HROW_SE2A3_3", - "CLK_HROW_SE2A3_4", - "CLK_HROW_SE2A3_5", - "CLK_HROW_SE2A3_6", - "CLK_HROW_SE2A3_7", - "CLK_HROW_SE4BEG0_0", - "CLK_HROW_SE4BEG0_1", - "CLK_HROW_SE4BEG0_2", - "CLK_HROW_SE4BEG0_3", - "CLK_HROW_SE4BEG0_4", - "CLK_HROW_SE4BEG0_5", - "CLK_HROW_SE4BEG0_6", - "CLK_HROW_SE4BEG0_7", - "CLK_HROW_SE4BEG1_0", - "CLK_HROW_SE4BEG1_1", - "CLK_HROW_SE4BEG1_2", - "CLK_HROW_SE4BEG1_3", - "CLK_HROW_SE4BEG1_4", - "CLK_HROW_SE4BEG1_5", - "CLK_HROW_SE4BEG1_6", - "CLK_HROW_SE4BEG1_7", - "CLK_HROW_SE4BEG2_0", - "CLK_HROW_SE4BEG2_1", - "CLK_HROW_SE4BEG2_2", - "CLK_HROW_SE4BEG2_3", - "CLK_HROW_SE4BEG2_4", - "CLK_HROW_SE4BEG2_5", - "CLK_HROW_SE4BEG2_6", - "CLK_HROW_SE4BEG2_7", - "CLK_HROW_SE4BEG3_0", - "CLK_HROW_SE4BEG3_1", - "CLK_HROW_SE4BEG3_2", - "CLK_HROW_SE4BEG3_3", - "CLK_HROW_SE4BEG3_4", - "CLK_HROW_SE4BEG3_5", - "CLK_HROW_SE4BEG3_6", - "CLK_HROW_SE4BEG3_7", - "CLK_HROW_SE4C0_0", - "CLK_HROW_SE4C0_1", - "CLK_HROW_SE4C0_2", - "CLK_HROW_SE4C0_3", - "CLK_HROW_SE4C0_4", - "CLK_HROW_SE4C0_5", - "CLK_HROW_SE4C0_6", - "CLK_HROW_SE4C0_7", - "CLK_HROW_SE4C1_0", - "CLK_HROW_SE4C1_1", - "CLK_HROW_SE4C1_2", - "CLK_HROW_SE4C1_3", - "CLK_HROW_SE4C1_4", - "CLK_HROW_SE4C1_5", - "CLK_HROW_SE4C1_6", - "CLK_HROW_SE4C1_7", - "CLK_HROW_SE4C2_0", - "CLK_HROW_SE4C2_1", - "CLK_HROW_SE4C2_2", - "CLK_HROW_SE4C2_3", - "CLK_HROW_SE4C2_4", - "CLK_HROW_SE4C2_5", - "CLK_HROW_SE4C2_6", - "CLK_HROW_SE4C2_7", - "CLK_HROW_SE4C3_0", - "CLK_HROW_SE4C3_1", - "CLK_HROW_SE4C3_2", - "CLK_HROW_SE4C3_3", - "CLK_HROW_SE4C3_4", - "CLK_HROW_SE4C3_5", - "CLK_HROW_SE4C3_6", - "CLK_HROW_SE4C3_7", - "CLK_HROW_SW2A0_0", - "CLK_HROW_SW2A0_1", - "CLK_HROW_SW2A0_2", - "CLK_HROW_SW2A0_3", - "CLK_HROW_SW2A0_4", - "CLK_HROW_SW2A0_5", - "CLK_HROW_SW2A0_6", - "CLK_HROW_SW2A0_7", - "CLK_HROW_SW2A1_0", - "CLK_HROW_SW2A1_1", - "CLK_HROW_SW2A1_2", - "CLK_HROW_SW2A1_3", - "CLK_HROW_SW2A1_4", - "CLK_HROW_SW2A1_5", - "CLK_HROW_SW2A1_6", - "CLK_HROW_SW2A1_7", - "CLK_HROW_SW2A2_0", - "CLK_HROW_SW2A2_1", - "CLK_HROW_SW2A2_2", - "CLK_HROW_SW2A2_3", - "CLK_HROW_SW2A2_4", - "CLK_HROW_SW2A2_5", - "CLK_HROW_SW2A2_6", - "CLK_HROW_SW2A2_7", - "CLK_HROW_SW2A3_0", - "CLK_HROW_SW2A3_1", - "CLK_HROW_SW2A3_2", - "CLK_HROW_SW2A3_3", - "CLK_HROW_SW2A3_4", - "CLK_HROW_SW2A3_5", - "CLK_HROW_SW2A3_6", - "CLK_HROW_SW2A3_7", - "CLK_HROW_SW4A0_0", - "CLK_HROW_SW4A0_1", - "CLK_HROW_SW4A0_2", - "CLK_HROW_SW4A0_3", - "CLK_HROW_SW4A0_4", - "CLK_HROW_SW4A0_5", - "CLK_HROW_SW4A0_6", - "CLK_HROW_SW4A0_7", - "CLK_HROW_SW4A1_0", - "CLK_HROW_SW4A1_1", - "CLK_HROW_SW4A1_2", - "CLK_HROW_SW4A1_3", - "CLK_HROW_SW4A1_4", - "CLK_HROW_SW4A1_5", - "CLK_HROW_SW4A1_6", - "CLK_HROW_SW4A1_7", - "CLK_HROW_SW4A2_0", - "CLK_HROW_SW4A2_1", - "CLK_HROW_SW4A2_2", - "CLK_HROW_SW4A2_3", - "CLK_HROW_SW4A2_4", - "CLK_HROW_SW4A2_5", - "CLK_HROW_SW4A2_6", - "CLK_HROW_SW4A2_7", - "CLK_HROW_SW4A3_0", - "CLK_HROW_SW4A3_1", - "CLK_HROW_SW4A3_2", - "CLK_HROW_SW4A3_3", - "CLK_HROW_SW4A3_4", - "CLK_HROW_SW4A3_5", - "CLK_HROW_SW4A3_6", - "CLK_HROW_SW4A3_7", - "CLK_HROW_SW4END0_0", - "CLK_HROW_SW4END0_1", - "CLK_HROW_SW4END0_2", - "CLK_HROW_SW4END0_3", - "CLK_HROW_SW4END0_4", - "CLK_HROW_SW4END0_5", - "CLK_HROW_SW4END0_6", - "CLK_HROW_SW4END0_7", - "CLK_HROW_SW4END1_0", - "CLK_HROW_SW4END1_1", - "CLK_HROW_SW4END1_2", - "CLK_HROW_SW4END1_3", - "CLK_HROW_SW4END1_4", - "CLK_HROW_SW4END1_5", - "CLK_HROW_SW4END1_6", - "CLK_HROW_SW4END1_7", - "CLK_HROW_SW4END2_0", - "CLK_HROW_SW4END2_1", - "CLK_HROW_SW4END2_2", - "CLK_HROW_SW4END2_3", - "CLK_HROW_SW4END2_4", - "CLK_HROW_SW4END2_5", - "CLK_HROW_SW4END2_6", - "CLK_HROW_SW4END2_7", - "CLK_HROW_SW4END3_0", - "CLK_HROW_SW4END3_1", - "CLK_HROW_SW4END3_2", - "CLK_HROW_SW4END3_3", - "CLK_HROW_SW4END3_4", - "CLK_HROW_SW4END3_5", - "CLK_HROW_SW4END3_6", - "CLK_HROW_SW4END3_7", - "CLK_HROW_WL1END0_0", - "CLK_HROW_WL1END0_1", - "CLK_HROW_WL1END0_2", - "CLK_HROW_WL1END0_3", - "CLK_HROW_WL1END0_4", - "CLK_HROW_WL1END0_5", - "CLK_HROW_WL1END0_6", - "CLK_HROW_WL1END0_7", - "CLK_HROW_WL1END1_0", - "CLK_HROW_WL1END1_1", - "CLK_HROW_WL1END1_2", - "CLK_HROW_WL1END1_3", - "CLK_HROW_WL1END1_4", - "CLK_HROW_WL1END1_5", - "CLK_HROW_WL1END1_6", - "CLK_HROW_WL1END1_7", - "CLK_HROW_WL1END2_0", - "CLK_HROW_WL1END2_1", - "CLK_HROW_WL1END2_2", - "CLK_HROW_WL1END2_3", - "CLK_HROW_WL1END2_4", - "CLK_HROW_WL1END2_5", - "CLK_HROW_WL1END2_6", - "CLK_HROW_WL1END2_7", - "CLK_HROW_WL1END3_0", - "CLK_HROW_WL1END3_1", - "CLK_HROW_WL1END3_2", - "CLK_HROW_WL1END3_3", - "CLK_HROW_WL1END3_4", - "CLK_HROW_WL1END3_5", - "CLK_HROW_WL1END3_6", - "CLK_HROW_WL1END3_7", - "CLK_HROW_WR1END0_0", - "CLK_HROW_WR1END0_1", - "CLK_HROW_WR1END0_2", - "CLK_HROW_WR1END0_3", - "CLK_HROW_WR1END0_4", - "CLK_HROW_WR1END0_5", - "CLK_HROW_WR1END0_6", - "CLK_HROW_WR1END0_7", - "CLK_HROW_WR1END1_0", - "CLK_HROW_WR1END1_1", - "CLK_HROW_WR1END1_2", - "CLK_HROW_WR1END1_3", - "CLK_HROW_WR1END1_4", - "CLK_HROW_WR1END1_5", - "CLK_HROW_WR1END1_6", - "CLK_HROW_WR1END1_7", - "CLK_HROW_WR1END2_0", - "CLK_HROW_WR1END2_1", - "CLK_HROW_WR1END2_2", - "CLK_HROW_WR1END2_3", - "CLK_HROW_WR1END2_4", - "CLK_HROW_WR1END2_5", - "CLK_HROW_WR1END2_6", - "CLK_HROW_WR1END2_7", - "CLK_HROW_WR1END3_0", - "CLK_HROW_WR1END3_1", - "CLK_HROW_WR1END3_2", - "CLK_HROW_WR1END3_3", - "CLK_HROW_WR1END3_4", - "CLK_HROW_WR1END3_5", - "CLK_HROW_WR1END3_6", - "CLK_HROW_WR1END3_7", - "CLK_HROW_WW2A0_0", - "CLK_HROW_WW2A0_1", - "CLK_HROW_WW2A0_2", - "CLK_HROW_WW2A0_3", - "CLK_HROW_WW2A0_4", - "CLK_HROW_WW2A0_5", - "CLK_HROW_WW2A0_6", - "CLK_HROW_WW2A0_7", - "CLK_HROW_WW2A1_0", - "CLK_HROW_WW2A1_1", - "CLK_HROW_WW2A1_2", - "CLK_HROW_WW2A1_3", - "CLK_HROW_WW2A1_4", - "CLK_HROW_WW2A1_5", - "CLK_HROW_WW2A1_6", - "CLK_HROW_WW2A1_7", - "CLK_HROW_WW2A2_0", - "CLK_HROW_WW2A2_1", - "CLK_HROW_WW2A2_2", - "CLK_HROW_WW2A2_3", - "CLK_HROW_WW2A2_4", - "CLK_HROW_WW2A2_5", - "CLK_HROW_WW2A2_6", - "CLK_HROW_WW2A2_7", - "CLK_HROW_WW2A3_0", - "CLK_HROW_WW2A3_1", - "CLK_HROW_WW2A3_2", - "CLK_HROW_WW2A3_3", - "CLK_HROW_WW2A3_4", - "CLK_HROW_WW2A3_5", - "CLK_HROW_WW2A3_6", - "CLK_HROW_WW2A3_7", - "CLK_HROW_WW2END0_0", - "CLK_HROW_WW2END0_1", - "CLK_HROW_WW2END0_2", - "CLK_HROW_WW2END0_3", - "CLK_HROW_WW2END0_4", - "CLK_HROW_WW2END0_5", - "CLK_HROW_WW2END0_6", - "CLK_HROW_WW2END0_7", - "CLK_HROW_WW2END1_0", - "CLK_HROW_WW2END1_1", - "CLK_HROW_WW2END1_2", - "CLK_HROW_WW2END1_3", - "CLK_HROW_WW2END1_4", - "CLK_HROW_WW2END1_5", - "CLK_HROW_WW2END1_6", - "CLK_HROW_WW2END1_7", - "CLK_HROW_WW2END2_0", - "CLK_HROW_WW2END2_1", - "CLK_HROW_WW2END2_2", - "CLK_HROW_WW2END2_3", - "CLK_HROW_WW2END2_4", - "CLK_HROW_WW2END2_5", - "CLK_HROW_WW2END2_6", - "CLK_HROW_WW2END2_7", - "CLK_HROW_WW2END3_0", - "CLK_HROW_WW2END3_1", - "CLK_HROW_WW2END3_2", - "CLK_HROW_WW2END3_3", - "CLK_HROW_WW2END3_4", - "CLK_HROW_WW2END3_5", - "CLK_HROW_WW2END3_6", - "CLK_HROW_WW2END3_7", - "CLK_HROW_WW4A0_0", - "CLK_HROW_WW4A0_1", - "CLK_HROW_WW4A0_2", - "CLK_HROW_WW4A0_3", - "CLK_HROW_WW4A0_4", - "CLK_HROW_WW4A0_5", - "CLK_HROW_WW4A0_6", - "CLK_HROW_WW4A0_7", - "CLK_HROW_WW4A1_0", - "CLK_HROW_WW4A1_1", - "CLK_HROW_WW4A1_2", - "CLK_HROW_WW4A1_3", - "CLK_HROW_WW4A1_4", - "CLK_HROW_WW4A1_5", - "CLK_HROW_WW4A1_6", - "CLK_HROW_WW4A1_7", - "CLK_HROW_WW4A2_0", - "CLK_HROW_WW4A2_1", - "CLK_HROW_WW4A2_2", - "CLK_HROW_WW4A2_3", - "CLK_HROW_WW4A2_4", - "CLK_HROW_WW4A2_5", - "CLK_HROW_WW4A2_6", - "CLK_HROW_WW4A2_7", - "CLK_HROW_WW4A3_0", - "CLK_HROW_WW4A3_1", - "CLK_HROW_WW4A3_2", - "CLK_HROW_WW4A3_3", - "CLK_HROW_WW4A3_4", - "CLK_HROW_WW4A3_5", - "CLK_HROW_WW4A3_6", - "CLK_HROW_WW4A3_7", - "CLK_HROW_WW4B0_0", - "CLK_HROW_WW4B0_1", - "CLK_HROW_WW4B0_2", - "CLK_HROW_WW4B0_3", - "CLK_HROW_WW4B0_4", - "CLK_HROW_WW4B0_5", - "CLK_HROW_WW4B0_6", - "CLK_HROW_WW4B0_7", - "CLK_HROW_WW4B1_0", - "CLK_HROW_WW4B1_1", - "CLK_HROW_WW4B1_2", - "CLK_HROW_WW4B1_3", - "CLK_HROW_WW4B1_4", - "CLK_HROW_WW4B1_5", - "CLK_HROW_WW4B1_6", - "CLK_HROW_WW4B1_7", - "CLK_HROW_WW4B2_0", - "CLK_HROW_WW4B2_1", - "CLK_HROW_WW4B2_2", - "CLK_HROW_WW4B2_3", - "CLK_HROW_WW4B2_4", - "CLK_HROW_WW4B2_5", - "CLK_HROW_WW4B2_6", - "CLK_HROW_WW4B2_7", - "CLK_HROW_WW4B3_0", - "CLK_HROW_WW4B3_1", - "CLK_HROW_WW4B3_2", - "CLK_HROW_WW4B3_3", - "CLK_HROW_WW4B3_4", - "CLK_HROW_WW4B3_5", - "CLK_HROW_WW4B3_6", - "CLK_HROW_WW4B3_7", - "CLK_HROW_WW4C0_0", - "CLK_HROW_WW4C0_1", - "CLK_HROW_WW4C0_2", - "CLK_HROW_WW4C0_3", - "CLK_HROW_WW4C0_4", - "CLK_HROW_WW4C0_5", - "CLK_HROW_WW4C0_6", - "CLK_HROW_WW4C0_7", - "CLK_HROW_WW4C1_0", - "CLK_HROW_WW4C1_1", - "CLK_HROW_WW4C1_2", - "CLK_HROW_WW4C1_3", - "CLK_HROW_WW4C1_4", - "CLK_HROW_WW4C1_5", - "CLK_HROW_WW4C1_6", - "CLK_HROW_WW4C1_7", - "CLK_HROW_WW4C2_0", - "CLK_HROW_WW4C2_1", - "CLK_HROW_WW4C2_2", - "CLK_HROW_WW4C2_3", - "CLK_HROW_WW4C2_4", - "CLK_HROW_WW4C2_5", - "CLK_HROW_WW4C2_6", - "CLK_HROW_WW4C2_7", - "CLK_HROW_WW4C3_0", - "CLK_HROW_WW4C3_1", - "CLK_HROW_WW4C3_2", - "CLK_HROW_WW4C3_3", - "CLK_HROW_WW4C3_4", - "CLK_HROW_WW4C3_5", - "CLK_HROW_WW4C3_6", - "CLK_HROW_WW4C3_7", - "CLK_HROW_WW4END0_0", - "CLK_HROW_WW4END0_1", - "CLK_HROW_WW4END0_2", - "CLK_HROW_WW4END0_3", - "CLK_HROW_WW4END0_4", - "CLK_HROW_WW4END0_5", - "CLK_HROW_WW4END0_6", - "CLK_HROW_WW4END0_7", - "CLK_HROW_WW4END1_0", - "CLK_HROW_WW4END1_1", - "CLK_HROW_WW4END1_2", - "CLK_HROW_WW4END1_3", - "CLK_HROW_WW4END1_4", - "CLK_HROW_WW4END1_5", - "CLK_HROW_WW4END1_6", - "CLK_HROW_WW4END1_7", - "CLK_HROW_WW4END2_0", - "CLK_HROW_WW4END2_1", - "CLK_HROW_WW4END2_2", - "CLK_HROW_WW4END2_3", - "CLK_HROW_WW4END2_4", - "CLK_HROW_WW4END2_5", - "CLK_HROW_WW4END2_6", - "CLK_HROW_WW4END2_7", - "CLK_HROW_WW4END3_0", - "CLK_HROW_WW4END3_1", - "CLK_HROW_WW4END3_2", - "CLK_HROW_WW4END3_3", - "CLK_HROW_WW4END3_4", - "CLK_HROW_WW4END3_5", - "CLK_HROW_WW4END3_6", - "CLK_HROW_WW4END3_7" - ] + "wires": { + "CLK_HROW_BLOCK_OUTS_B0_0": null, + "CLK_HROW_BLOCK_OUTS_B0_1": null, + "CLK_HROW_BLOCK_OUTS_B0_2": null, + "CLK_HROW_BLOCK_OUTS_B0_3": null, + "CLK_HROW_BLOCK_OUTS_B0_4": null, + "CLK_HROW_BLOCK_OUTS_B0_5": null, + "CLK_HROW_BLOCK_OUTS_B0_6": null, + "CLK_HROW_BLOCK_OUTS_B0_7": null, + "CLK_HROW_BLOCK_OUTS_B1_0": null, + "CLK_HROW_BLOCK_OUTS_B1_1": null, + "CLK_HROW_BLOCK_OUTS_B1_2": null, + "CLK_HROW_BLOCK_OUTS_B1_3": null, + "CLK_HROW_BLOCK_OUTS_B1_4": null, + "CLK_HROW_BLOCK_OUTS_B1_5": null, + "CLK_HROW_BLOCK_OUTS_B1_6": null, + "CLK_HROW_BLOCK_OUTS_B1_7": null, + "CLK_HROW_BLOCK_OUTS_B2_0": null, + "CLK_HROW_BLOCK_OUTS_B2_1": null, + "CLK_HROW_BLOCK_OUTS_B2_2": null, + "CLK_HROW_BLOCK_OUTS_B2_3": null, + "CLK_HROW_BLOCK_OUTS_B2_4": null, + "CLK_HROW_BLOCK_OUTS_B2_5": null, + "CLK_HROW_BLOCK_OUTS_B2_6": null, + "CLK_HROW_BLOCK_OUTS_B2_7": null, + "CLK_HROW_BLOCK_OUTS_B3_0": null, + "CLK_HROW_BLOCK_OUTS_B3_1": null, + "CLK_HROW_BLOCK_OUTS_B3_2": null, + "CLK_HROW_BLOCK_OUTS_B3_3": null, + "CLK_HROW_BLOCK_OUTS_B3_4": null, + "CLK_HROW_BLOCK_OUTS_B3_5": null, + "CLK_HROW_BLOCK_OUTS_B3_6": null, + "CLK_HROW_BLOCK_OUTS_B3_7": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN0": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN1": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN10": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN11": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN12": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN13": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN14": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN15": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN16": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN17": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN18": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN19": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN2": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN20": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN21": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN22": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN23": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN24": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN25": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN26": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN27": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN28": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN29": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN3": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN30": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN31": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN4": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN5": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN6": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN7": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN8": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN9": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO0": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO1": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO10": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO11": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO12": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO13": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO14": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO15": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO16": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO17": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO18": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO19": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO2": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO20": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO21": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO22": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO23": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO24": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO25": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO26": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO27": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO28": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO29": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO3": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO30": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO31": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO4": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO5": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO6": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO7": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO8": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO9": null, + "CLK_HROW_BUFHCE_CE_L0": null, + "CLK_HROW_BUFHCE_CE_L1": null, + "CLK_HROW_BUFHCE_CE_L10": null, + "CLK_HROW_BUFHCE_CE_L11": null, + "CLK_HROW_BUFHCE_CE_L2": null, + "CLK_HROW_BUFHCE_CE_L3": null, + "CLK_HROW_BUFHCE_CE_L4": null, + "CLK_HROW_BUFHCE_CE_L5": null, + "CLK_HROW_BUFHCE_CE_L6": null, + "CLK_HROW_BUFHCE_CE_L7": null, + "CLK_HROW_BUFHCE_CE_L8": null, + "CLK_HROW_BUFHCE_CE_L9": null, + "CLK_HROW_BUFHCE_CE_R0": null, + "CLK_HROW_BUFHCE_CE_R1": null, + "CLK_HROW_BUFHCE_CE_R10": null, + "CLK_HROW_BUFHCE_CE_R11": null, + "CLK_HROW_BUFHCE_CE_R2": null, + "CLK_HROW_BUFHCE_CE_R3": null, + "CLK_HROW_BUFHCE_CE_R4": null, + "CLK_HROW_BUFHCE_CE_R5": null, + "CLK_HROW_BUFHCE_CE_R6": null, + "CLK_HROW_BUFHCE_CE_R7": null, + "CLK_HROW_BUFHCE_CE_R8": null, + "CLK_HROW_BUFHCE_CE_R9": null, + "CLK_HROW_BYP0_0": null, + "CLK_HROW_BYP0_1": null, + "CLK_HROW_BYP0_2": null, + "CLK_HROW_BYP0_3": null, + "CLK_HROW_BYP0_4": null, + "CLK_HROW_BYP0_5": null, + "CLK_HROW_BYP0_6": null, + "CLK_HROW_BYP0_7": null, + "CLK_HROW_BYP1_0": null, + "CLK_HROW_BYP1_1": null, + "CLK_HROW_BYP1_2": null, + "CLK_HROW_BYP1_3": null, + "CLK_HROW_BYP1_4": null, + "CLK_HROW_BYP1_5": null, + "CLK_HROW_BYP1_6": null, + "CLK_HROW_BYP1_7": null, + "CLK_HROW_BYP2_0": null, + "CLK_HROW_BYP2_1": null, + "CLK_HROW_BYP2_2": null, + "CLK_HROW_BYP2_3": null, + "CLK_HROW_BYP2_4": null, + "CLK_HROW_BYP2_5": null, + "CLK_HROW_BYP2_6": null, + "CLK_HROW_BYP2_7": null, + "CLK_HROW_BYP3_0": null, + "CLK_HROW_BYP3_1": null, + "CLK_HROW_BYP3_2": null, + "CLK_HROW_BYP3_3": null, + "CLK_HROW_BYP3_4": null, + "CLK_HROW_BYP3_5": null, + "CLK_HROW_BYP3_6": null, + "CLK_HROW_BYP3_7": null, + "CLK_HROW_BYP4_0": null, + "CLK_HROW_BYP4_1": null, + "CLK_HROW_BYP4_2": null, + "CLK_HROW_BYP4_3": null, + "CLK_HROW_BYP4_4": null, + "CLK_HROW_BYP4_5": null, + "CLK_HROW_BYP4_6": null, + "CLK_HROW_BYP4_7": null, + "CLK_HROW_BYP5_0": null, + "CLK_HROW_BYP5_1": null, + "CLK_HROW_BYP5_2": null, + "CLK_HROW_BYP5_3": null, + "CLK_HROW_BYP5_4": null, + "CLK_HROW_BYP5_5": null, + "CLK_HROW_BYP5_6": null, + "CLK_HROW_BYP5_7": null, + "CLK_HROW_BYP6_0": null, + "CLK_HROW_BYP6_1": null, + "CLK_HROW_BYP6_2": null, + "CLK_HROW_BYP6_3": null, + "CLK_HROW_BYP6_4": null, + "CLK_HROW_BYP6_5": null, + "CLK_HROW_BYP6_6": null, + "CLK_HROW_BYP6_7": null, + "CLK_HROW_BYP7_0": null, + "CLK_HROW_BYP7_1": null, + "CLK_HROW_BYP7_2": null, + "CLK_HROW_BYP7_3": null, + "CLK_HROW_BYP7_4": null, + "CLK_HROW_BYP7_5": null, + "CLK_HROW_BYP7_6": null, + "CLK_HROW_BYP7_7": null, + "CLK_HROW_CE_INT_BOT0": null, + "CLK_HROW_CE_INT_BOT1": null, + "CLK_HROW_CE_INT_BOT10": null, + "CLK_HROW_CE_INT_BOT11": null, + "CLK_HROW_CE_INT_BOT2": null, + "CLK_HROW_CE_INT_BOT3": null, + "CLK_HROW_CE_INT_BOT4": null, + "CLK_HROW_CE_INT_BOT5": null, + "CLK_HROW_CE_INT_BOT6": null, + "CLK_HROW_CE_INT_BOT7": null, + "CLK_HROW_CE_INT_BOT8": null, + "CLK_HROW_CE_INT_BOT9": null, + "CLK_HROW_CE_INT_TOP0": null, + "CLK_HROW_CE_INT_TOP1": null, + "CLK_HROW_CE_INT_TOP10": null, + "CLK_HROW_CE_INT_TOP11": null, + "CLK_HROW_CE_INT_TOP2": null, + "CLK_HROW_CE_INT_TOP3": null, + "CLK_HROW_CE_INT_TOP4": null, + "CLK_HROW_CE_INT_TOP5": null, + "CLK_HROW_CE_INT_TOP6": null, + "CLK_HROW_CE_INT_TOP7": null, + "CLK_HROW_CE_INT_TOP8": null, + "CLK_HROW_CE_INT_TOP9": null, + "CLK_HROW_CK_BUFHCLK_L0": null, + "CLK_HROW_CK_BUFHCLK_L1": null, + "CLK_HROW_CK_BUFHCLK_L10": null, + "CLK_HROW_CK_BUFHCLK_L11": null, + "CLK_HROW_CK_BUFHCLK_L2": null, + "CLK_HROW_CK_BUFHCLK_L3": null, + "CLK_HROW_CK_BUFHCLK_L4": null, + "CLK_HROW_CK_BUFHCLK_L5": null, + "CLK_HROW_CK_BUFHCLK_L6": null, + "CLK_HROW_CK_BUFHCLK_L7": null, + "CLK_HROW_CK_BUFHCLK_L8": null, + "CLK_HROW_CK_BUFHCLK_L9": null, + "CLK_HROW_CK_BUFHCLK_R0": null, + "CLK_HROW_CK_BUFHCLK_R1": null, + "CLK_HROW_CK_BUFHCLK_R10": null, + "CLK_HROW_CK_BUFHCLK_R11": null, + "CLK_HROW_CK_BUFHCLK_R2": null, + "CLK_HROW_CK_BUFHCLK_R3": null, + "CLK_HROW_CK_BUFHCLK_R4": null, + "CLK_HROW_CK_BUFHCLK_R5": null, + "CLK_HROW_CK_BUFHCLK_R6": null, + "CLK_HROW_CK_BUFHCLK_R7": null, + "CLK_HROW_CK_BUFHCLK_R8": null, + "CLK_HROW_CK_BUFHCLK_R9": null, + "CLK_HROW_CK_BUFRCLK_L0": null, + "CLK_HROW_CK_BUFRCLK_L1": null, + "CLK_HROW_CK_BUFRCLK_L2": null, + "CLK_HROW_CK_BUFRCLK_L3": null, + "CLK_HROW_CK_BUFRCLK_R0": null, + "CLK_HROW_CK_BUFRCLK_R1": null, + "CLK_HROW_CK_BUFRCLK_R2": null, + "CLK_HROW_CK_BUFRCLK_R3": null, + "CLK_HROW_CK_GCLK_IN_TEST0": null, + "CLK_HROW_CK_GCLK_IN_TEST1": null, + "CLK_HROW_CK_GCLK_IN_TEST10": null, + "CLK_HROW_CK_GCLK_IN_TEST11": null, + "CLK_HROW_CK_GCLK_IN_TEST12": null, + "CLK_HROW_CK_GCLK_IN_TEST13": null, + "CLK_HROW_CK_GCLK_IN_TEST14": null, + "CLK_HROW_CK_GCLK_IN_TEST15": null, + "CLK_HROW_CK_GCLK_IN_TEST16": null, + "CLK_HROW_CK_GCLK_IN_TEST17": null, + "CLK_HROW_CK_GCLK_IN_TEST18": null, + "CLK_HROW_CK_GCLK_IN_TEST19": null, + "CLK_HROW_CK_GCLK_IN_TEST2": null, + "CLK_HROW_CK_GCLK_IN_TEST20": null, + "CLK_HROW_CK_GCLK_IN_TEST21": null, + "CLK_HROW_CK_GCLK_IN_TEST22": null, + "CLK_HROW_CK_GCLK_IN_TEST23": null, + "CLK_HROW_CK_GCLK_IN_TEST24": null, + "CLK_HROW_CK_GCLK_IN_TEST25": null, + "CLK_HROW_CK_GCLK_IN_TEST26": null, + "CLK_HROW_CK_GCLK_IN_TEST27": null, + "CLK_HROW_CK_GCLK_IN_TEST28": null, + "CLK_HROW_CK_GCLK_IN_TEST29": null, + "CLK_HROW_CK_GCLK_IN_TEST3": null, + "CLK_HROW_CK_GCLK_IN_TEST30": null, + "CLK_HROW_CK_GCLK_IN_TEST31": null, + "CLK_HROW_CK_GCLK_IN_TEST4": null, + "CLK_HROW_CK_GCLK_IN_TEST5": null, + "CLK_HROW_CK_GCLK_IN_TEST6": null, + "CLK_HROW_CK_GCLK_IN_TEST7": null, + "CLK_HROW_CK_GCLK_IN_TEST8": null, + "CLK_HROW_CK_GCLK_IN_TEST9": null, + "CLK_HROW_CK_GCLK_OUT_TEST0": null, + "CLK_HROW_CK_GCLK_OUT_TEST1": null, + "CLK_HROW_CK_GCLK_OUT_TEST10": null, + "CLK_HROW_CK_GCLK_OUT_TEST11": null, + "CLK_HROW_CK_GCLK_OUT_TEST12": null, + "CLK_HROW_CK_GCLK_OUT_TEST13": null, + "CLK_HROW_CK_GCLK_OUT_TEST14": null, + "CLK_HROW_CK_GCLK_OUT_TEST15": null, + "CLK_HROW_CK_GCLK_OUT_TEST16": null, + "CLK_HROW_CK_GCLK_OUT_TEST17": null, + "CLK_HROW_CK_GCLK_OUT_TEST18": null, + "CLK_HROW_CK_GCLK_OUT_TEST19": null, + "CLK_HROW_CK_GCLK_OUT_TEST2": null, + "CLK_HROW_CK_GCLK_OUT_TEST20": null, + "CLK_HROW_CK_GCLK_OUT_TEST21": null, + "CLK_HROW_CK_GCLK_OUT_TEST22": null, + "CLK_HROW_CK_GCLK_OUT_TEST23": null, + "CLK_HROW_CK_GCLK_OUT_TEST24": null, + "CLK_HROW_CK_GCLK_OUT_TEST25": null, + "CLK_HROW_CK_GCLK_OUT_TEST26": null, + "CLK_HROW_CK_GCLK_OUT_TEST27": null, + "CLK_HROW_CK_GCLK_OUT_TEST28": null, + "CLK_HROW_CK_GCLK_OUT_TEST29": null, + "CLK_HROW_CK_GCLK_OUT_TEST3": null, + "CLK_HROW_CK_GCLK_OUT_TEST30": null, + "CLK_HROW_CK_GCLK_OUT_TEST31": null, + "CLK_HROW_CK_GCLK_OUT_TEST4": null, + "CLK_HROW_CK_GCLK_OUT_TEST5": null, + "CLK_HROW_CK_GCLK_OUT_TEST6": null, + "CLK_HROW_CK_GCLK_OUT_TEST7": null, + "CLK_HROW_CK_GCLK_OUT_TEST8": null, + "CLK_HROW_CK_GCLK_OUT_TEST9": null, + "CLK_HROW_CK_GCLK_TEST0": null, + "CLK_HROW_CK_GCLK_TEST1": null, + "CLK_HROW_CK_GCLK_TEST10": null, + "CLK_HROW_CK_GCLK_TEST11": null, + "CLK_HROW_CK_GCLK_TEST12": null, + "CLK_HROW_CK_GCLK_TEST13": null, + "CLK_HROW_CK_GCLK_TEST14": null, + "CLK_HROW_CK_GCLK_TEST15": null, + "CLK_HROW_CK_GCLK_TEST16": null, + "CLK_HROW_CK_GCLK_TEST17": null, + "CLK_HROW_CK_GCLK_TEST18": null, + "CLK_HROW_CK_GCLK_TEST19": null, + "CLK_HROW_CK_GCLK_TEST2": null, + "CLK_HROW_CK_GCLK_TEST20": null, + "CLK_HROW_CK_GCLK_TEST21": null, + "CLK_HROW_CK_GCLK_TEST22": null, + "CLK_HROW_CK_GCLK_TEST23": null, + "CLK_HROW_CK_GCLK_TEST24": null, + "CLK_HROW_CK_GCLK_TEST25": null, + "CLK_HROW_CK_GCLK_TEST26": null, + "CLK_HROW_CK_GCLK_TEST27": null, + "CLK_HROW_CK_GCLK_TEST28": null, + "CLK_HROW_CK_GCLK_TEST29": null, + "CLK_HROW_CK_GCLK_TEST3": null, + "CLK_HROW_CK_GCLK_TEST30": null, + "CLK_HROW_CK_GCLK_TEST31": null, + "CLK_HROW_CK_GCLK_TEST4": null, + "CLK_HROW_CK_GCLK_TEST5": null, + "CLK_HROW_CK_GCLK_TEST6": null, + "CLK_HROW_CK_GCLK_TEST7": null, + "CLK_HROW_CK_GCLK_TEST8": null, + "CLK_HROW_CK_GCLK_TEST9": null, + "CLK_HROW_CK_GCLK_TEST_IN0": null, + "CLK_HROW_CK_GCLK_TEST_IN1": null, + "CLK_HROW_CK_GCLK_TEST_IN10": null, + "CLK_HROW_CK_GCLK_TEST_IN11": null, + "CLK_HROW_CK_GCLK_TEST_IN12": null, + "CLK_HROW_CK_GCLK_TEST_IN13": null, + "CLK_HROW_CK_GCLK_TEST_IN14": null, + "CLK_HROW_CK_GCLK_TEST_IN15": null, + "CLK_HROW_CK_GCLK_TEST_IN16": null, + "CLK_HROW_CK_GCLK_TEST_IN17": null, + "CLK_HROW_CK_GCLK_TEST_IN18": null, + "CLK_HROW_CK_GCLK_TEST_IN19": null, + "CLK_HROW_CK_GCLK_TEST_IN2": null, + "CLK_HROW_CK_GCLK_TEST_IN20": null, + "CLK_HROW_CK_GCLK_TEST_IN21": null, + "CLK_HROW_CK_GCLK_TEST_IN22": null, + "CLK_HROW_CK_GCLK_TEST_IN23": null, + "CLK_HROW_CK_GCLK_TEST_IN24": null, + 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"CLK_HROW_SW4A2_4": null, + "CLK_HROW_SW4A2_5": null, + "CLK_HROW_SW4A2_6": null, + "CLK_HROW_SW4A2_7": null, + "CLK_HROW_SW4A3_0": null, + "CLK_HROW_SW4A3_1": null, + "CLK_HROW_SW4A3_2": null, + "CLK_HROW_SW4A3_3": null, + "CLK_HROW_SW4A3_4": null, + "CLK_HROW_SW4A3_5": null, + "CLK_HROW_SW4A3_6": null, + "CLK_HROW_SW4A3_7": null, + "CLK_HROW_SW4END0_0": null, + "CLK_HROW_SW4END0_1": null, + "CLK_HROW_SW4END0_2": null, + "CLK_HROW_SW4END0_3": null, + "CLK_HROW_SW4END0_4": null, + "CLK_HROW_SW4END0_5": null, + "CLK_HROW_SW4END0_6": null, + "CLK_HROW_SW4END0_7": null, + "CLK_HROW_SW4END1_0": null, + "CLK_HROW_SW4END1_1": null, + "CLK_HROW_SW4END1_2": null, + "CLK_HROW_SW4END1_3": null, + "CLK_HROW_SW4END1_4": null, + "CLK_HROW_SW4END1_5": null, + "CLK_HROW_SW4END1_6": null, + "CLK_HROW_SW4END1_7": null, + "CLK_HROW_SW4END2_0": null, + "CLK_HROW_SW4END2_1": null, + "CLK_HROW_SW4END2_2": null, + "CLK_HROW_SW4END2_3": null, + "CLK_HROW_SW4END2_4": null, + "CLK_HROW_SW4END2_5": null, + "CLK_HROW_SW4END2_6": null, + "CLK_HROW_SW4END2_7": null, + "CLK_HROW_SW4END3_0": null, + "CLK_HROW_SW4END3_1": null, + "CLK_HROW_SW4END3_2": null, + "CLK_HROW_SW4END3_3": null, + "CLK_HROW_SW4END3_4": null, + "CLK_HROW_SW4END3_5": null, + "CLK_HROW_SW4END3_6": null, + "CLK_HROW_SW4END3_7": null, + "CLK_HROW_WL1END0_0": null, + "CLK_HROW_WL1END0_1": null, + "CLK_HROW_WL1END0_2": null, + "CLK_HROW_WL1END0_3": null, + "CLK_HROW_WL1END0_4": null, + "CLK_HROW_WL1END0_5": null, + "CLK_HROW_WL1END0_6": null, + "CLK_HROW_WL1END0_7": null, + "CLK_HROW_WL1END1_0": null, + "CLK_HROW_WL1END1_1": null, + "CLK_HROW_WL1END1_2": null, + "CLK_HROW_WL1END1_3": null, + "CLK_HROW_WL1END1_4": null, + "CLK_HROW_WL1END1_5": null, + "CLK_HROW_WL1END1_6": null, + "CLK_HROW_WL1END1_7": null, + "CLK_HROW_WL1END2_0": null, + "CLK_HROW_WL1END2_1": null, + "CLK_HROW_WL1END2_2": null, + "CLK_HROW_WL1END2_3": null, + "CLK_HROW_WL1END2_4": null, + "CLK_HROW_WL1END2_5": null, + "CLK_HROW_WL1END2_6": null, + "CLK_HROW_WL1END2_7": null, + "CLK_HROW_WL1END3_0": null, + "CLK_HROW_WL1END3_1": null, + "CLK_HROW_WL1END3_2": null, + "CLK_HROW_WL1END3_3": null, + "CLK_HROW_WL1END3_4": null, + "CLK_HROW_WL1END3_5": null, + "CLK_HROW_WL1END3_6": null, + "CLK_HROW_WL1END3_7": null, + "CLK_HROW_WR1END0_0": null, + "CLK_HROW_WR1END0_1": null, + "CLK_HROW_WR1END0_2": null, + "CLK_HROW_WR1END0_3": null, + "CLK_HROW_WR1END0_4": null, + "CLK_HROW_WR1END0_5": null, + "CLK_HROW_WR1END0_6": null, + "CLK_HROW_WR1END0_7": null, + "CLK_HROW_WR1END1_0": null, + "CLK_HROW_WR1END1_1": null, + "CLK_HROW_WR1END1_2": null, + "CLK_HROW_WR1END1_3": null, + "CLK_HROW_WR1END1_4": null, + "CLK_HROW_WR1END1_5": null, + "CLK_HROW_WR1END1_6": null, + "CLK_HROW_WR1END1_7": null, + "CLK_HROW_WR1END2_0": null, + "CLK_HROW_WR1END2_1": null, + "CLK_HROW_WR1END2_2": null, + "CLK_HROW_WR1END2_3": null, + "CLK_HROW_WR1END2_4": null, + "CLK_HROW_WR1END2_5": null, + "CLK_HROW_WR1END2_6": null, + "CLK_HROW_WR1END2_7": null, + "CLK_HROW_WR1END3_0": null, + "CLK_HROW_WR1END3_1": null, + "CLK_HROW_WR1END3_2": null, + "CLK_HROW_WR1END3_3": null, + "CLK_HROW_WR1END3_4": null, + "CLK_HROW_WR1END3_5": null, + "CLK_HROW_WR1END3_6": null, + "CLK_HROW_WR1END3_7": null, + "CLK_HROW_WW2A0_0": null, + "CLK_HROW_WW2A0_1": null, + "CLK_HROW_WW2A0_2": null, + "CLK_HROW_WW2A0_3": null, + "CLK_HROW_WW2A0_4": null, + "CLK_HROW_WW2A0_5": null, + "CLK_HROW_WW2A0_6": null, + "CLK_HROW_WW2A0_7": null, + "CLK_HROW_WW2A1_0": null, + "CLK_HROW_WW2A1_1": null, + "CLK_HROW_WW2A1_2": null, + "CLK_HROW_WW2A1_3": null, + "CLK_HROW_WW2A1_4": null, + "CLK_HROW_WW2A1_5": null, + "CLK_HROW_WW2A1_6": null, + "CLK_HROW_WW2A1_7": null, + "CLK_HROW_WW2A2_0": null, + "CLK_HROW_WW2A2_1": null, + "CLK_HROW_WW2A2_2": null, + "CLK_HROW_WW2A2_3": null, + "CLK_HROW_WW2A2_4": null, + "CLK_HROW_WW2A2_5": null, + "CLK_HROW_WW2A2_6": null, + "CLK_HROW_WW2A2_7": null, + "CLK_HROW_WW2A3_0": null, + "CLK_HROW_WW2A3_1": null, + "CLK_HROW_WW2A3_2": null, + "CLK_HROW_WW2A3_3": null, + "CLK_HROW_WW2A3_4": null, + "CLK_HROW_WW2A3_5": null, + "CLK_HROW_WW2A3_6": null, + "CLK_HROW_WW2A3_7": null, + "CLK_HROW_WW2END0_0": null, + "CLK_HROW_WW2END0_1": null, + "CLK_HROW_WW2END0_2": null, + "CLK_HROW_WW2END0_3": null, + "CLK_HROW_WW2END0_4": null, + "CLK_HROW_WW2END0_5": null, + "CLK_HROW_WW2END0_6": null, + "CLK_HROW_WW2END0_7": null, + "CLK_HROW_WW2END1_0": null, + "CLK_HROW_WW2END1_1": null, + "CLK_HROW_WW2END1_2": null, + "CLK_HROW_WW2END1_3": null, + "CLK_HROW_WW2END1_4": null, + "CLK_HROW_WW2END1_5": null, + "CLK_HROW_WW2END1_6": null, + "CLK_HROW_WW2END1_7": null, + "CLK_HROW_WW2END2_0": null, + "CLK_HROW_WW2END2_1": null, + "CLK_HROW_WW2END2_2": null, + "CLK_HROW_WW2END2_3": null, + "CLK_HROW_WW2END2_4": null, + "CLK_HROW_WW2END2_5": null, + "CLK_HROW_WW2END2_6": null, + "CLK_HROW_WW2END2_7": null, + "CLK_HROW_WW2END3_0": null, + "CLK_HROW_WW2END3_1": null, + "CLK_HROW_WW2END3_2": null, + "CLK_HROW_WW2END3_3": null, + "CLK_HROW_WW2END3_4": null, + "CLK_HROW_WW2END3_5": null, + "CLK_HROW_WW2END3_6": null, + "CLK_HROW_WW2END3_7": null, + "CLK_HROW_WW4A0_0": null, + "CLK_HROW_WW4A0_1": null, + "CLK_HROW_WW4A0_2": null, + "CLK_HROW_WW4A0_3": null, + "CLK_HROW_WW4A0_4": null, + "CLK_HROW_WW4A0_5": null, + "CLK_HROW_WW4A0_6": null, + "CLK_HROW_WW4A0_7": null, + "CLK_HROW_WW4A1_0": null, + "CLK_HROW_WW4A1_1": null, + "CLK_HROW_WW4A1_2": null, + "CLK_HROW_WW4A1_3": null, + "CLK_HROW_WW4A1_4": null, + "CLK_HROW_WW4A1_5": null, + "CLK_HROW_WW4A1_6": null, + "CLK_HROW_WW4A1_7": null, + "CLK_HROW_WW4A2_0": null, + "CLK_HROW_WW4A2_1": null, + "CLK_HROW_WW4A2_2": null, + "CLK_HROW_WW4A2_3": null, + "CLK_HROW_WW4A2_4": null, + "CLK_HROW_WW4A2_5": null, + "CLK_HROW_WW4A2_6": null, + "CLK_HROW_WW4A2_7": null, + "CLK_HROW_WW4A3_0": null, + "CLK_HROW_WW4A3_1": null, + "CLK_HROW_WW4A3_2": null, + "CLK_HROW_WW4A3_3": null, + "CLK_HROW_WW4A3_4": null, + "CLK_HROW_WW4A3_5": null, + "CLK_HROW_WW4A3_6": null, + "CLK_HROW_WW4A3_7": null, + "CLK_HROW_WW4B0_0": null, + "CLK_HROW_WW4B0_1": null, + "CLK_HROW_WW4B0_2": null, + "CLK_HROW_WW4B0_3": null, + "CLK_HROW_WW4B0_4": null, + "CLK_HROW_WW4B0_5": null, + "CLK_HROW_WW4B0_6": null, + "CLK_HROW_WW4B0_7": null, + "CLK_HROW_WW4B1_0": null, + "CLK_HROW_WW4B1_1": null, + "CLK_HROW_WW4B1_2": null, + "CLK_HROW_WW4B1_3": null, + "CLK_HROW_WW4B1_4": null, + "CLK_HROW_WW4B1_5": null, + "CLK_HROW_WW4B1_6": null, + "CLK_HROW_WW4B1_7": null, + "CLK_HROW_WW4B2_0": null, + "CLK_HROW_WW4B2_1": null, + "CLK_HROW_WW4B2_2": null, + "CLK_HROW_WW4B2_3": null, + "CLK_HROW_WW4B2_4": null, + "CLK_HROW_WW4B2_5": null, + "CLK_HROW_WW4B2_6": null, + "CLK_HROW_WW4B2_7": null, + "CLK_HROW_WW4B3_0": null, + "CLK_HROW_WW4B3_1": null, + "CLK_HROW_WW4B3_2": null, + "CLK_HROW_WW4B3_3": null, + "CLK_HROW_WW4B3_4": null, + "CLK_HROW_WW4B3_5": null, + "CLK_HROW_WW4B3_6": null, + "CLK_HROW_WW4B3_7": null, + "CLK_HROW_WW4C0_0": null, + "CLK_HROW_WW4C0_1": null, + "CLK_HROW_WW4C0_2": null, + "CLK_HROW_WW4C0_3": null, + "CLK_HROW_WW4C0_4": null, + "CLK_HROW_WW4C0_5": null, + "CLK_HROW_WW4C0_6": null, + "CLK_HROW_WW4C0_7": null, + "CLK_HROW_WW4C1_0": null, + "CLK_HROW_WW4C1_1": null, + "CLK_HROW_WW4C1_2": null, + "CLK_HROW_WW4C1_3": null, + "CLK_HROW_WW4C1_4": null, + "CLK_HROW_WW4C1_5": null, + "CLK_HROW_WW4C1_6": null, + "CLK_HROW_WW4C1_7": null, + "CLK_HROW_WW4C2_0": null, + "CLK_HROW_WW4C2_1": null, + "CLK_HROW_WW4C2_2": null, + "CLK_HROW_WW4C2_3": null, + "CLK_HROW_WW4C2_4": null, + "CLK_HROW_WW4C2_5": null, + "CLK_HROW_WW4C2_6": null, + "CLK_HROW_WW4C2_7": null, + "CLK_HROW_WW4C3_0": null, + "CLK_HROW_WW4C3_1": null, + "CLK_HROW_WW4C3_2": null, + "CLK_HROW_WW4C3_3": null, + "CLK_HROW_WW4C3_4": null, + "CLK_HROW_WW4C3_5": null, + "CLK_HROW_WW4C3_6": null, + "CLK_HROW_WW4C3_7": null, + "CLK_HROW_WW4END0_0": null, + "CLK_HROW_WW4END0_1": null, + "CLK_HROW_WW4END0_2": null, + "CLK_HROW_WW4END0_3": null, + "CLK_HROW_WW4END0_4": null, + "CLK_HROW_WW4END0_5": null, + "CLK_HROW_WW4END0_6": null, + "CLK_HROW_WW4END0_7": null, + "CLK_HROW_WW4END1_0": null, + "CLK_HROW_WW4END1_1": null, + "CLK_HROW_WW4END1_2": null, + "CLK_HROW_WW4END1_3": null, + "CLK_HROW_WW4END1_4": null, + "CLK_HROW_WW4END1_5": null, + "CLK_HROW_WW4END1_6": null, + "CLK_HROW_WW4END1_7": null, + "CLK_HROW_WW4END2_0": null, + "CLK_HROW_WW4END2_1": null, + "CLK_HROW_WW4END2_2": null, + "CLK_HROW_WW4END2_3": null, + "CLK_HROW_WW4END2_4": null, + "CLK_HROW_WW4END2_5": null, + "CLK_HROW_WW4END2_6": null, + "CLK_HROW_WW4END2_7": null, + "CLK_HROW_WW4END3_0": null, + "CLK_HROW_WW4END3_1": null, + "CLK_HROW_WW4END3_2": null, + "CLK_HROW_WW4END3_3": null, + "CLK_HROW_WW4END3_4": null, + "CLK_HROW_WW4END3_5": null, + "CLK_HROW_WW4END3_6": null, + "CLK_HROW_WW4END3_7": null + } } diff --git a/zynq7/tile_type_CLK_HROW_TOP_R.json b/zynq7/tile_type_CLK_HROW_TOP_R.json index c2c6384..d68695d 100644 --- a/zynq7/tile_type_CLK_HROW_TOP_R.json +++ b/zynq7/tile_type_CLK_HROW_TOP_R.json @@ -2,19882 +2,78562 @@ "pips": { "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT0->>CLK_HROW_BUFHCE_CE_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT0" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT1->>CLK_HROW_BUFHCE_CE_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT1" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT10->>CLK_HROW_BUFHCE_CE_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT10" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT11->>CLK_HROW_BUFHCE_CE_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT11" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT2->>CLK_HROW_BUFHCE_CE_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT2" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT3->>CLK_HROW_BUFHCE_CE_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT3" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT4->>CLK_HROW_BUFHCE_CE_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT4" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT5->>CLK_HROW_BUFHCE_CE_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT5" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT6->>CLK_HROW_BUFHCE_CE_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT6" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT7->>CLK_HROW_BUFHCE_CE_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT7" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT8->>CLK_HROW_BUFHCE_CE_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT8" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT9->>CLK_HROW_BUFHCE_CE_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT9" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP0->>CLK_HROW_BUFHCE_CE_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP0" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP1->>CLK_HROW_BUFHCE_CE_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP1" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP10->>CLK_HROW_BUFHCE_CE_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP10" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP11->>CLK_HROW_BUFHCE_CE_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP11" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP2->>CLK_HROW_BUFHCE_CE_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP2" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP3->>CLK_HROW_BUFHCE_CE_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP3" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP4->>CLK_HROW_BUFHCE_CE_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP4" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP5->>CLK_HROW_BUFHCE_CE_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP5" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP6->>CLK_HROW_BUFHCE_CE_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP6" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP7->>CLK_HROW_BUFHCE_CE_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP7" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP8->>CLK_HROW_BUFHCE_CE_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP8" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP9->>CLK_HROW_BUFHCE_CE_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.016", + "0.018", + "0.050", + "0.055" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.119", + "0.132", + "0.378", + "0.416" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST0->CLK_HROW_CK_GCLK_TEST_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST1->CLK_HROW_CK_GCLK_TEST_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST10->CLK_HROW_CK_GCLK_TEST_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST11->CLK_HROW_CK_GCLK_TEST_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST12->CLK_HROW_CK_GCLK_TEST_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST13->CLK_HROW_CK_GCLK_TEST_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST14->CLK_HROW_CK_GCLK_TEST_IN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST14" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST15->CLK_HROW_CK_GCLK_TEST_IN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST15" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST16->CLK_HROW_CK_GCLK_TEST_IN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST16" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST17->CLK_HROW_CK_GCLK_TEST_IN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST17" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST18->CLK_HROW_CK_GCLK_TEST_IN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST18" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST19->CLK_HROW_CK_GCLK_TEST_IN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST19" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST2->CLK_HROW_CK_GCLK_TEST_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST20->CLK_HROW_CK_GCLK_TEST_IN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST20" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST21->CLK_HROW_CK_GCLK_TEST_IN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST21" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST22->CLK_HROW_CK_GCLK_TEST_IN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST22" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST23->CLK_HROW_CK_GCLK_TEST_IN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST23" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST24->CLK_HROW_CK_GCLK_TEST_IN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST24" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST25->CLK_HROW_CK_GCLK_TEST_IN25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST25" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST26->CLK_HROW_CK_GCLK_TEST_IN26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST26" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST27->CLK_HROW_CK_GCLK_TEST_IN27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST27" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST28->CLK_HROW_CK_GCLK_TEST_IN28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST28" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST29->CLK_HROW_CK_GCLK_TEST_IN29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST29" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST3->CLK_HROW_CK_GCLK_TEST_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST30->CLK_HROW_CK_GCLK_TEST_IN30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST30" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST31->CLK_HROW_CK_GCLK_TEST_IN31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST31" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST4->CLK_HROW_CK_GCLK_TEST_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST5->CLK_HROW_CK_GCLK_TEST_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST6->CLK_HROW_CK_GCLK_TEST_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST7->CLK_HROW_CK_GCLK_TEST_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST8->CLK_HROW_CK_GCLK_TEST_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST9->CLK_HROW_CK_GCLK_TEST_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT0->CLK_HROW_CK_GCLK_OUT_TEST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT1->CLK_HROW_CK_GCLK_OUT_TEST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT10->CLK_HROW_CK_GCLK_OUT_TEST10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT11->CLK_HROW_CK_GCLK_OUT_TEST11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT12->CLK_HROW_CK_GCLK_OUT_TEST12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT13->CLK_HROW_CK_GCLK_OUT_TEST13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT14->CLK_HROW_CK_GCLK_OUT_TEST14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT14" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT15->CLK_HROW_CK_GCLK_OUT_TEST15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT15" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT16->CLK_HROW_CK_GCLK_OUT_TEST16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT16" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT17->CLK_HROW_CK_GCLK_OUT_TEST17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT17" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT18->CLK_HROW_CK_GCLK_OUT_TEST18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT18" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT19->CLK_HROW_CK_GCLK_OUT_TEST19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT19" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT2->CLK_HROW_CK_GCLK_OUT_TEST2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT20->CLK_HROW_CK_GCLK_OUT_TEST20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT20" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT21->CLK_HROW_CK_GCLK_OUT_TEST21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT21" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT22->CLK_HROW_CK_GCLK_OUT_TEST22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT22" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT23->CLK_HROW_CK_GCLK_OUT_TEST23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT23" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT24->CLK_HROW_CK_GCLK_OUT_TEST24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT24" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT25->CLK_HROW_CK_GCLK_OUT_TEST25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT25" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT26->CLK_HROW_CK_GCLK_OUT_TEST26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT26" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT27->CLK_HROW_CK_GCLK_OUT_TEST27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT27" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT28->CLK_HROW_CK_GCLK_OUT_TEST28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT28" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT29->CLK_HROW_CK_GCLK_OUT_TEST29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT29" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT3->CLK_HROW_CK_GCLK_OUT_TEST3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT30->CLK_HROW_CK_GCLK_OUT_TEST30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT30" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT31->CLK_HROW_CK_GCLK_OUT_TEST31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT31" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT4->CLK_HROW_CK_GCLK_OUT_TEST4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT5->CLK_HROW_CK_GCLK_OUT_TEST5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT6->CLK_HROW_CK_GCLK_OUT_TEST6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT7->CLK_HROW_CK_GCLK_OUT_TEST7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT8->CLK_HROW_CK_GCLK_OUT_TEST8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT9->CLK_HROW_CK_GCLK_OUT_TEST9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L0->>CLK_HROW_CK_BUFHCLK_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L1->>CLK_HROW_CK_BUFHCLK_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L10->>CLK_HROW_CK_BUFHCLK_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L11->>CLK_HROW_CK_BUFHCLK_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L2->>CLK_HROW_CK_BUFHCLK_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L3->>CLK_HROW_CK_BUFHCLK_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L4->>CLK_HROW_CK_BUFHCLK_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L5->>CLK_HROW_CK_BUFHCLK_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L6->>CLK_HROW_CK_BUFHCLK_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L7->>CLK_HROW_CK_BUFHCLK_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L8->>CLK_HROW_CK_BUFHCLK_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L9->>CLK_HROW_CK_BUFHCLK_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R0->>CLK_HROW_CK_BUFHCLK_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R1->>CLK_HROW_CK_BUFHCLK_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R10->>CLK_HROW_CK_BUFHCLK_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R11->>CLK_HROW_CK_BUFHCLK_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R2->>CLK_HROW_CK_BUFHCLK_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R3->>CLK_HROW_CK_BUFHCLK_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R4->>CLK_HROW_CK_BUFHCLK_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R5->>CLK_HROW_CK_BUFHCLK_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R6->>CLK_HROW_CK_BUFHCLK_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R7->>CLK_HROW_CK_BUFHCLK_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R8->>CLK_HROW_CK_BUFHCLK_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R9->>CLK_HROW_CK_BUFHCLK_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.190" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.127", + "0.140", + "0.418", + "0.460" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_OUT_TEST->CLK_HROW_CK_IN_L_TEST_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_L_TEST_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_L_OUT_TEST" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_TEST_IN->CLK_HROW_CK_IN_L_IN_TEST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_L_IN_TEST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_L_TEST_IN" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.112", + "0.386", + "0.445" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.159", + "0.633", + "0.698" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_OUT_TEST->CLK_HROW_CK_IN_R_TEST_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_R_TEST_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_R_OUT_TEST" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_TEST_IN->CLK_HROW_CK_IN_R_IN_TEST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_R_IN_TEST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_R_TEST_IN" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L0->>CLK_HROW_CK_HCLK_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L1->>CLK_HROW_CK_HCLK_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L10->>CLK_HROW_CK_HCLK_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L11->>CLK_HROW_CK_HCLK_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L2->>CLK_HROW_CK_HCLK_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L3->>CLK_HROW_CK_HCLK_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L4->>CLK_HROW_CK_HCLK_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L5->>CLK_HROW_CK_HCLK_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L6->>CLK_HROW_CK_HCLK_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L7->>CLK_HROW_CK_HCLK_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L8->>CLK_HROW_CK_HCLK_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L9->>CLK_HROW_CK_HCLK_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R0->>CLK_HROW_CK_HCLK_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R1->>CLK_HROW_CK_HCLK_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R10->>CLK_HROW_CK_HCLK_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R11->>CLK_HROW_CK_HCLK_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R2->>CLK_HROW_CK_HCLK_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R3->>CLK_HROW_CK_HCLK_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R4->>CLK_HROW_CK_HCLK_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R5->>CLK_HROW_CK_HCLK_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R6->>CLK_HROW_CK_HCLK_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R7->>CLK_HROW_CK_HCLK_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R8->>CLK_HROW_CK_HCLK_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R9->>CLK_HROW_CK_HCLK_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.020", + "0.043", + "0.081", + "0.132" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CLK0_3->CLK_HROW_CK_INT_0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK0_3" }, "CLK_HROW_TOP_R.CLK_HROW_CLK0_4->CLK_HROW_CK_INT_1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK0_4" }, "CLK_HROW_TOP_R.CLK_HROW_CLK1_3->CLK_HROW_CK_INT_0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK1_3" }, "CLK_HROW_TOP_R.CLK_HROW_CLK1_4->CLK_HROW_CK_INT_1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK1_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX0_3->CLK_HROW_CE_INT_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX0_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX0_4->CLK_HROW_CE_INT_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX0_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX10_3->CLK_HROW_CE_INT_BOT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX10_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX10_4->CLK_HROW_CE_INT_TOP10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX10_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX11_3->CLK_HROW_CE_INT_BOT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX11_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX11_4->CLK_HROW_CE_INT_TOP11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX11_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX1_3->CLK_HROW_CE_INT_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX1_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX1_4->CLK_HROW_CE_INT_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX1_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX2_3->CLK_HROW_CE_INT_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX2_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX2_4->CLK_HROW_CE_INT_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX2_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX3_3->CLK_HROW_CE_INT_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX3_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX3_4->CLK_HROW_CE_INT_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX3_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX4_3->CLK_HROW_CE_INT_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX4_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX4_4->CLK_HROW_CE_INT_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX4_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX5_3->CLK_HROW_CE_INT_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX5_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX5_4->CLK_HROW_CE_INT_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX5_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX6_3->CLK_HROW_CE_INT_BOT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX6_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX6_4->CLK_HROW_CE_INT_TOP6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX6_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX7_3->CLK_HROW_CE_INT_BOT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX7_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX7_4->CLK_HROW_CE_INT_TOP7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX7_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX8_3->CLK_HROW_CE_INT_BOT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX8_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX8_4->CLK_HROW_CE_INT_TOP8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX8_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX9_3->CLK_HROW_CE_INT_BOT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX9_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX9_4->CLK_HROW_CE_INT_TOP9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX9_4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.110", + "0.324", + "0.356" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN0" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN1" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN10" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN11" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN12" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN13" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN14->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN14" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN15->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN15" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN16->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN16" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN17->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN17" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN18->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN18" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN19->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN19" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN2" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN20->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN20" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN21->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN21" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN22->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN22" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN23->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN23" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN24->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN24" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN25->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN25" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN26->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN26" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN27->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN27" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN28->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN28" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN29->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN29" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN3" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN30->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN30" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN31->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN31" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN4" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN5" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN6" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN7" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN8" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.176", + "0.287", + "0.317" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN9" } }, @@ -19886,9 +78566,36 @@ "name": "X0Y0", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L0", - "I": "CLK_HROW_CK_MUX_OUT_L0", - "O": "CLK_HROW_CK_HCLK_OUT_L0" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L0" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L0" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19898,9 +78605,36 @@ "name": "X0Y1", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L1", - "I": "CLK_HROW_CK_MUX_OUT_L1", - "O": "CLK_HROW_CK_HCLK_OUT_L1" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L1" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L1" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19910,9 +78644,36 @@ "name": "X0Y2", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L2", - "I": "CLK_HROW_CK_MUX_OUT_L2", - "O": "CLK_HROW_CK_HCLK_OUT_L2" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L2" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L2" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19922,9 +78683,36 @@ "name": "X0Y3", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L3", - "I": "CLK_HROW_CK_MUX_OUT_L3", - "O": "CLK_HROW_CK_HCLK_OUT_L3" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L3" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L3" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19934,9 +78722,36 @@ "name": "X0Y4", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L4", - "I": "CLK_HROW_CK_MUX_OUT_L4", - "O": "CLK_HROW_CK_HCLK_OUT_L4" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L4" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L4" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19946,9 +78761,36 @@ "name": "X0Y5", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L5", - "I": "CLK_HROW_CK_MUX_OUT_L5", - "O": "CLK_HROW_CK_HCLK_OUT_L5" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L5" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L5" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19958,9 +78800,36 @@ "name": "X0Y6", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L6", - "I": "CLK_HROW_CK_MUX_OUT_L6", - "O": "CLK_HROW_CK_HCLK_OUT_L6" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L6" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L6" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19970,9 +78839,36 @@ "name": "X0Y7", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L7", - "I": "CLK_HROW_CK_MUX_OUT_L7", - "O": "CLK_HROW_CK_HCLK_OUT_L7" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L7" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L7" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19982,9 +78878,36 @@ "name": "X0Y8", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L8", - "I": "CLK_HROW_CK_MUX_OUT_L8", - "O": "CLK_HROW_CK_HCLK_OUT_L8" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L8" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L8" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19994,9 +78917,36 @@ "name": "X0Y9", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L9", - "I": "CLK_HROW_CK_MUX_OUT_L9", - "O": "CLK_HROW_CK_HCLK_OUT_L9" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L9" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L9" + } }, "type": "BUFHCE", "x_coord": 0, @@ -20006,9 +78956,36 @@ "name": "X0Y10", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L10", - "I": "CLK_HROW_CK_MUX_OUT_L10", - "O": "CLK_HROW_CK_HCLK_OUT_L10" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L10" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L10" + } }, "type": "BUFHCE", "x_coord": 0, @@ -20018,9 +78995,36 @@ "name": "X0Y11", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L11", - "I": "CLK_HROW_CK_MUX_OUT_L11", - "O": "CLK_HROW_CK_HCLK_OUT_L11" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_L11" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L11" + } }, "type": "BUFHCE", "x_coord": 0, @@ -20030,9 +79034,36 @@ "name": "X1Y11", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R11", - "I": "CLK_HROW_CK_MUX_OUT_R11", - "O": "CLK_HROW_CK_HCLK_OUT_R11" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R11" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R11" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20042,9 +79073,36 @@ "name": "X1Y10", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R10", - "I": "CLK_HROW_CK_MUX_OUT_R10", - "O": "CLK_HROW_CK_HCLK_OUT_R10" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R10" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R10" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20054,9 +79112,36 @@ "name": "X1Y9", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R9", - "I": "CLK_HROW_CK_MUX_OUT_R9", - "O": "CLK_HROW_CK_HCLK_OUT_R9" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R9" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R9" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20066,9 +79151,36 @@ "name": "X1Y8", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R8", - "I": "CLK_HROW_CK_MUX_OUT_R8", - "O": "CLK_HROW_CK_HCLK_OUT_R8" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R8" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R8" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20078,9 +79190,36 @@ "name": "X1Y7", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R7", - "I": "CLK_HROW_CK_MUX_OUT_R7", - "O": "CLK_HROW_CK_HCLK_OUT_R7" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R7" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R7" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20090,9 +79229,36 @@ "name": "X1Y6", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R6", - "I": "CLK_HROW_CK_MUX_OUT_R6", - "O": "CLK_HROW_CK_HCLK_OUT_R6" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R6" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R6" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20102,9 +79268,36 @@ "name": "X1Y5", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R5", - "I": "CLK_HROW_CK_MUX_OUT_R5", - "O": "CLK_HROW_CK_HCLK_OUT_R5" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R5" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R5" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20114,9 +79307,36 @@ "name": "X1Y4", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R4", - "I": "CLK_HROW_CK_MUX_OUT_R4", - "O": "CLK_HROW_CK_HCLK_OUT_R4" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R4" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R4" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20126,9 +79346,36 @@ "name": "X1Y3", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R3", - "I": "CLK_HROW_CK_MUX_OUT_R3", - "O": "CLK_HROW_CK_HCLK_OUT_R3" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R3" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R3" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20138,9 +79385,36 @@ "name": "X1Y2", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R2", - "I": "CLK_HROW_CK_MUX_OUT_R2", - "O": "CLK_HROW_CK_HCLK_OUT_R2" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R2" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R2" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20150,9 +79424,36 @@ "name": "X1Y1", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R1", - "I": "CLK_HROW_CK_MUX_OUT_R1", - "O": "CLK_HROW_CK_HCLK_OUT_R1" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R1" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R1" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20162,9 +79463,36 @@ "name": "X1Y0", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R0", - "I": "CLK_HROW_CK_MUX_OUT_R0", - "O": "CLK_HROW_CK_HCLK_OUT_R0" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_BUFHCE_CE_R0" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R0" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20172,2210 +79500,3410 @@ } ], "tile_type": "CLK_HROW_TOP_R", - "wires": [ - "CLK_HROW_BLOCK_OUTS_B0_0", - "CLK_HROW_BLOCK_OUTS_B0_1", - "CLK_HROW_BLOCK_OUTS_B0_2", - "CLK_HROW_BLOCK_OUTS_B0_3", - "CLK_HROW_BLOCK_OUTS_B0_4", - "CLK_HROW_BLOCK_OUTS_B0_5", - "CLK_HROW_BLOCK_OUTS_B0_6", - "CLK_HROW_BLOCK_OUTS_B0_7", - "CLK_HROW_BLOCK_OUTS_B1_0", - "CLK_HROW_BLOCK_OUTS_B1_1", - "CLK_HROW_BLOCK_OUTS_B1_2", - "CLK_HROW_BLOCK_OUTS_B1_3", - "CLK_HROW_BLOCK_OUTS_B1_4", - "CLK_HROW_BLOCK_OUTS_B1_5", - "CLK_HROW_BLOCK_OUTS_B1_6", - "CLK_HROW_BLOCK_OUTS_B1_7", - "CLK_HROW_BLOCK_OUTS_B2_0", - "CLK_HROW_BLOCK_OUTS_B2_1", - "CLK_HROW_BLOCK_OUTS_B2_2", - "CLK_HROW_BLOCK_OUTS_B2_3", - "CLK_HROW_BLOCK_OUTS_B2_4", - "CLK_HROW_BLOCK_OUTS_B2_5", - "CLK_HROW_BLOCK_OUTS_B2_6", - "CLK_HROW_BLOCK_OUTS_B2_7", - "CLK_HROW_BLOCK_OUTS_B3_0", - "CLK_HROW_BLOCK_OUTS_B3_1", - "CLK_HROW_BLOCK_OUTS_B3_2", - "CLK_HROW_BLOCK_OUTS_B3_3", - "CLK_HROW_BLOCK_OUTS_B3_4", - "CLK_HROW_BLOCK_OUTS_B3_5", - "CLK_HROW_BLOCK_OUTS_B3_6", - "CLK_HROW_BLOCK_OUTS_B3_7", - "CLK_HROW_BUFHCE_CE_L0", - "CLK_HROW_BUFHCE_CE_L1", - "CLK_HROW_BUFHCE_CE_L10", - "CLK_HROW_BUFHCE_CE_L11", - "CLK_HROW_BUFHCE_CE_L2", - "CLK_HROW_BUFHCE_CE_L3", - "CLK_HROW_BUFHCE_CE_L4", - "CLK_HROW_BUFHCE_CE_L5", - "CLK_HROW_BUFHCE_CE_L6", - "CLK_HROW_BUFHCE_CE_L7", - "CLK_HROW_BUFHCE_CE_L8", - "CLK_HROW_BUFHCE_CE_L9", - "CLK_HROW_BUFHCE_CE_R0", - "CLK_HROW_BUFHCE_CE_R1", - "CLK_HROW_BUFHCE_CE_R10", - "CLK_HROW_BUFHCE_CE_R11", - "CLK_HROW_BUFHCE_CE_R2", - "CLK_HROW_BUFHCE_CE_R3", - "CLK_HROW_BUFHCE_CE_R4", - "CLK_HROW_BUFHCE_CE_R5", - "CLK_HROW_BUFHCE_CE_R6", - "CLK_HROW_BUFHCE_CE_R7", - "CLK_HROW_BUFHCE_CE_R8", - "CLK_HROW_BUFHCE_CE_R9", - "CLK_HROW_BYP0_0", - "CLK_HROW_BYP0_1", - "CLK_HROW_BYP0_2", - "CLK_HROW_BYP0_3", - "CLK_HROW_BYP0_4", - "CLK_HROW_BYP0_5", - "CLK_HROW_BYP0_6", - "CLK_HROW_BYP0_7", - "CLK_HROW_BYP1_0", - "CLK_HROW_BYP1_1", - "CLK_HROW_BYP1_2", - "CLK_HROW_BYP1_3", - "CLK_HROW_BYP1_4", - "CLK_HROW_BYP1_5", - "CLK_HROW_BYP1_6", - "CLK_HROW_BYP1_7", - "CLK_HROW_BYP2_0", - "CLK_HROW_BYP2_1", - "CLK_HROW_BYP2_2", - "CLK_HROW_BYP2_3", - "CLK_HROW_BYP2_4", - "CLK_HROW_BYP2_5", - "CLK_HROW_BYP2_6", - "CLK_HROW_BYP2_7", - "CLK_HROW_BYP3_0", - "CLK_HROW_BYP3_1", - "CLK_HROW_BYP3_2", - "CLK_HROW_BYP3_3", - "CLK_HROW_BYP3_4", - "CLK_HROW_BYP3_5", - "CLK_HROW_BYP3_6", - "CLK_HROW_BYP3_7", - "CLK_HROW_BYP4_0", - "CLK_HROW_BYP4_1", - "CLK_HROW_BYP4_2", - "CLK_HROW_BYP4_3", - "CLK_HROW_BYP4_4", - "CLK_HROW_BYP4_5", - "CLK_HROW_BYP4_6", - "CLK_HROW_BYP4_7", - "CLK_HROW_BYP5_0", - "CLK_HROW_BYP5_1", - "CLK_HROW_BYP5_2", - "CLK_HROW_BYP5_3", - "CLK_HROW_BYP5_4", - "CLK_HROW_BYP5_5", - "CLK_HROW_BYP5_6", - "CLK_HROW_BYP5_7", - "CLK_HROW_BYP6_0", - "CLK_HROW_BYP6_1", - "CLK_HROW_BYP6_2", - "CLK_HROW_BYP6_3", - "CLK_HROW_BYP6_4", - "CLK_HROW_BYP6_5", - "CLK_HROW_BYP6_6", - "CLK_HROW_BYP6_7", - "CLK_HROW_BYP7_0", - "CLK_HROW_BYP7_1", - "CLK_HROW_BYP7_2", - "CLK_HROW_BYP7_3", - "CLK_HROW_BYP7_4", - "CLK_HROW_BYP7_5", - "CLK_HROW_BYP7_6", - "CLK_HROW_BYP7_7", - "CLK_HROW_CE_INT_BOT0", - "CLK_HROW_CE_INT_BOT1", - "CLK_HROW_CE_INT_BOT10", - "CLK_HROW_CE_INT_BOT11", - "CLK_HROW_CE_INT_BOT2", - "CLK_HROW_CE_INT_BOT3", - "CLK_HROW_CE_INT_BOT4", - "CLK_HROW_CE_INT_BOT5", - "CLK_HROW_CE_INT_BOT6", - "CLK_HROW_CE_INT_BOT7", - "CLK_HROW_CE_INT_BOT8", - "CLK_HROW_CE_INT_BOT9", - "CLK_HROW_CE_INT_TOP0", - "CLK_HROW_CE_INT_TOP1", - "CLK_HROW_CE_INT_TOP10", - "CLK_HROW_CE_INT_TOP11", - "CLK_HROW_CE_INT_TOP2", - "CLK_HROW_CE_INT_TOP3", - "CLK_HROW_CE_INT_TOP4", - "CLK_HROW_CE_INT_TOP5", - "CLK_HROW_CE_INT_TOP6", - "CLK_HROW_CE_INT_TOP7", - "CLK_HROW_CE_INT_TOP8", - "CLK_HROW_CE_INT_TOP9", - "CLK_HROW_CK_BUFHCLK_L0", - "CLK_HROW_CK_BUFHCLK_L1", - "CLK_HROW_CK_BUFHCLK_L10", - "CLK_HROW_CK_BUFHCLK_L11", - "CLK_HROW_CK_BUFHCLK_L2", - "CLK_HROW_CK_BUFHCLK_L3", - "CLK_HROW_CK_BUFHCLK_L4", - "CLK_HROW_CK_BUFHCLK_L5", - "CLK_HROW_CK_BUFHCLK_L6", - "CLK_HROW_CK_BUFHCLK_L7", - "CLK_HROW_CK_BUFHCLK_L8", - "CLK_HROW_CK_BUFHCLK_L9", - "CLK_HROW_CK_BUFHCLK_R0", - "CLK_HROW_CK_BUFHCLK_R1", - "CLK_HROW_CK_BUFHCLK_R10", - "CLK_HROW_CK_BUFHCLK_R11", - "CLK_HROW_CK_BUFHCLK_R2", - "CLK_HROW_CK_BUFHCLK_R3", - "CLK_HROW_CK_BUFHCLK_R4", - "CLK_HROW_CK_BUFHCLK_R5", - "CLK_HROW_CK_BUFHCLK_R6", - "CLK_HROW_CK_BUFHCLK_R7", - "CLK_HROW_CK_BUFHCLK_R8", - "CLK_HROW_CK_BUFHCLK_R9", - "CLK_HROW_CK_BUFRCLK_L0", - "CLK_HROW_CK_BUFRCLK_L1", - "CLK_HROW_CK_BUFRCLK_L2", - "CLK_HROW_CK_BUFRCLK_L3", - "CLK_HROW_CK_BUFRCLK_R0", - "CLK_HROW_CK_BUFRCLK_R1", - "CLK_HROW_CK_BUFRCLK_R2", - "CLK_HROW_CK_BUFRCLK_R3", - "CLK_HROW_CK_GCLK_IN_TEST0", - "CLK_HROW_CK_GCLK_IN_TEST1", - "CLK_HROW_CK_GCLK_IN_TEST10", - "CLK_HROW_CK_GCLK_IN_TEST11", - "CLK_HROW_CK_GCLK_IN_TEST12", - "CLK_HROW_CK_GCLK_IN_TEST13", - "CLK_HROW_CK_GCLK_IN_TEST14", - "CLK_HROW_CK_GCLK_IN_TEST15", - "CLK_HROW_CK_GCLK_IN_TEST16", - "CLK_HROW_CK_GCLK_IN_TEST17", - "CLK_HROW_CK_GCLK_IN_TEST18", - "CLK_HROW_CK_GCLK_IN_TEST19", - "CLK_HROW_CK_GCLK_IN_TEST2", - "CLK_HROW_CK_GCLK_IN_TEST20", - "CLK_HROW_CK_GCLK_IN_TEST21", - "CLK_HROW_CK_GCLK_IN_TEST22", - "CLK_HROW_CK_GCLK_IN_TEST23", - "CLK_HROW_CK_GCLK_IN_TEST24", - "CLK_HROW_CK_GCLK_IN_TEST25", - "CLK_HROW_CK_GCLK_IN_TEST26", - "CLK_HROW_CK_GCLK_IN_TEST27", - "CLK_HROW_CK_GCLK_IN_TEST28", - "CLK_HROW_CK_GCLK_IN_TEST29", - "CLK_HROW_CK_GCLK_IN_TEST3", - "CLK_HROW_CK_GCLK_IN_TEST30", - "CLK_HROW_CK_GCLK_IN_TEST31", - "CLK_HROW_CK_GCLK_IN_TEST4", - "CLK_HROW_CK_GCLK_IN_TEST5", - "CLK_HROW_CK_GCLK_IN_TEST6", - "CLK_HROW_CK_GCLK_IN_TEST7", - "CLK_HROW_CK_GCLK_IN_TEST8", - "CLK_HROW_CK_GCLK_IN_TEST9", - "CLK_HROW_CK_GCLK_OUT_TEST0", - "CLK_HROW_CK_GCLK_OUT_TEST1", - "CLK_HROW_CK_GCLK_OUT_TEST10", - "CLK_HROW_CK_GCLK_OUT_TEST11", - "CLK_HROW_CK_GCLK_OUT_TEST12", - "CLK_HROW_CK_GCLK_OUT_TEST13", - "CLK_HROW_CK_GCLK_OUT_TEST14", - "CLK_HROW_CK_GCLK_OUT_TEST15", - "CLK_HROW_CK_GCLK_OUT_TEST16", - "CLK_HROW_CK_GCLK_OUT_TEST17", - "CLK_HROW_CK_GCLK_OUT_TEST18", - "CLK_HROW_CK_GCLK_OUT_TEST19", - "CLK_HROW_CK_GCLK_OUT_TEST2", - "CLK_HROW_CK_GCLK_OUT_TEST20", - "CLK_HROW_CK_GCLK_OUT_TEST21", - "CLK_HROW_CK_GCLK_OUT_TEST22", - "CLK_HROW_CK_GCLK_OUT_TEST23", - "CLK_HROW_CK_GCLK_OUT_TEST24", - "CLK_HROW_CK_GCLK_OUT_TEST25", - "CLK_HROW_CK_GCLK_OUT_TEST26", - "CLK_HROW_CK_GCLK_OUT_TEST27", - "CLK_HROW_CK_GCLK_OUT_TEST28", - "CLK_HROW_CK_GCLK_OUT_TEST29", - "CLK_HROW_CK_GCLK_OUT_TEST3", - "CLK_HROW_CK_GCLK_OUT_TEST30", - "CLK_HROW_CK_GCLK_OUT_TEST31", - "CLK_HROW_CK_GCLK_OUT_TEST4", - "CLK_HROW_CK_GCLK_OUT_TEST5", - "CLK_HROW_CK_GCLK_OUT_TEST6", - "CLK_HROW_CK_GCLK_OUT_TEST7", - "CLK_HROW_CK_GCLK_OUT_TEST8", - "CLK_HROW_CK_GCLK_OUT_TEST9", - "CLK_HROW_CK_GCLK_TEST0", - "CLK_HROW_CK_GCLK_TEST1", - "CLK_HROW_CK_GCLK_TEST10", - "CLK_HROW_CK_GCLK_TEST11", - "CLK_HROW_CK_GCLK_TEST12", - "CLK_HROW_CK_GCLK_TEST13", - "CLK_HROW_CK_GCLK_TEST14", - "CLK_HROW_CK_GCLK_TEST15", - "CLK_HROW_CK_GCLK_TEST16", - "CLK_HROW_CK_GCLK_TEST17", - "CLK_HROW_CK_GCLK_TEST18", - "CLK_HROW_CK_GCLK_TEST19", - "CLK_HROW_CK_GCLK_TEST2", - "CLK_HROW_CK_GCLK_TEST20", - "CLK_HROW_CK_GCLK_TEST21", - "CLK_HROW_CK_GCLK_TEST22", - "CLK_HROW_CK_GCLK_TEST23", - "CLK_HROW_CK_GCLK_TEST24", - "CLK_HROW_CK_GCLK_TEST25", - "CLK_HROW_CK_GCLK_TEST26", - "CLK_HROW_CK_GCLK_TEST27", - "CLK_HROW_CK_GCLK_TEST28", - "CLK_HROW_CK_GCLK_TEST29", - "CLK_HROW_CK_GCLK_TEST3", - "CLK_HROW_CK_GCLK_TEST30", - "CLK_HROW_CK_GCLK_TEST31", - "CLK_HROW_CK_GCLK_TEST4", - "CLK_HROW_CK_GCLK_TEST5", - "CLK_HROW_CK_GCLK_TEST6", - "CLK_HROW_CK_GCLK_TEST7", - "CLK_HROW_CK_GCLK_TEST8", - "CLK_HROW_CK_GCLK_TEST9", - "CLK_HROW_CK_GCLK_TEST_IN0", - "CLK_HROW_CK_GCLK_TEST_IN1", - "CLK_HROW_CK_GCLK_TEST_IN10", - "CLK_HROW_CK_GCLK_TEST_IN11", - "CLK_HROW_CK_GCLK_TEST_IN12", - "CLK_HROW_CK_GCLK_TEST_IN13", - "CLK_HROW_CK_GCLK_TEST_IN14", - "CLK_HROW_CK_GCLK_TEST_IN15", - "CLK_HROW_CK_GCLK_TEST_IN16", - "CLK_HROW_CK_GCLK_TEST_IN17", - "CLK_HROW_CK_GCLK_TEST_IN18", - "CLK_HROW_CK_GCLK_TEST_IN19", - "CLK_HROW_CK_GCLK_TEST_IN2", - "CLK_HROW_CK_GCLK_TEST_IN20", - "CLK_HROW_CK_GCLK_TEST_IN21", - "CLK_HROW_CK_GCLK_TEST_IN22", - "CLK_HROW_CK_GCLK_TEST_IN23", - "CLK_HROW_CK_GCLK_TEST_IN24", - "CLK_HROW_CK_GCLK_TEST_IN25", - "CLK_HROW_CK_GCLK_TEST_IN26", - "CLK_HROW_CK_GCLK_TEST_IN27", - "CLK_HROW_CK_GCLK_TEST_IN28", - "CLK_HROW_CK_GCLK_TEST_IN29", - "CLK_HROW_CK_GCLK_TEST_IN3", - "CLK_HROW_CK_GCLK_TEST_IN30", - "CLK_HROW_CK_GCLK_TEST_IN31", - "CLK_HROW_CK_GCLK_TEST_IN4", - "CLK_HROW_CK_GCLK_TEST_IN5", - "CLK_HROW_CK_GCLK_TEST_IN6", - "CLK_HROW_CK_GCLK_TEST_IN7", - "CLK_HROW_CK_GCLK_TEST_IN8", - "CLK_HROW_CK_GCLK_TEST_IN9", - "CLK_HROW_CK_GCLK_TEST_OUT0", - "CLK_HROW_CK_GCLK_TEST_OUT1", - "CLK_HROW_CK_GCLK_TEST_OUT10", - "CLK_HROW_CK_GCLK_TEST_OUT11", - "CLK_HROW_CK_GCLK_TEST_OUT12", - "CLK_HROW_CK_GCLK_TEST_OUT13", - "CLK_HROW_CK_GCLK_TEST_OUT14", - "CLK_HROW_CK_GCLK_TEST_OUT15", - "CLK_HROW_CK_GCLK_TEST_OUT16", - "CLK_HROW_CK_GCLK_TEST_OUT17", - "CLK_HROW_CK_GCLK_TEST_OUT18", - "CLK_HROW_CK_GCLK_TEST_OUT19", - "CLK_HROW_CK_GCLK_TEST_OUT2", - "CLK_HROW_CK_GCLK_TEST_OUT20", - "CLK_HROW_CK_GCLK_TEST_OUT21", - "CLK_HROW_CK_GCLK_TEST_OUT22", - "CLK_HROW_CK_GCLK_TEST_OUT23", - "CLK_HROW_CK_GCLK_TEST_OUT24", - "CLK_HROW_CK_GCLK_TEST_OUT25", - "CLK_HROW_CK_GCLK_TEST_OUT26", - "CLK_HROW_CK_GCLK_TEST_OUT27", - "CLK_HROW_CK_GCLK_TEST_OUT28", - "CLK_HROW_CK_GCLK_TEST_OUT29", - "CLK_HROW_CK_GCLK_TEST_OUT3", - "CLK_HROW_CK_GCLK_TEST_OUT30", - "CLK_HROW_CK_GCLK_TEST_OUT31", - "CLK_HROW_CK_GCLK_TEST_OUT4", - "CLK_HROW_CK_GCLK_TEST_OUT5", - "CLK_HROW_CK_GCLK_TEST_OUT6", - "CLK_HROW_CK_GCLK_TEST_OUT7", - "CLK_HROW_CK_GCLK_TEST_OUT8", - "CLK_HROW_CK_GCLK_TEST_OUT9", - "CLK_HROW_CK_HCLK_OUT_L0", - "CLK_HROW_CK_HCLK_OUT_L1", - "CLK_HROW_CK_HCLK_OUT_L10", - "CLK_HROW_CK_HCLK_OUT_L11", - "CLK_HROW_CK_HCLK_OUT_L2", - "CLK_HROW_CK_HCLK_OUT_L3", - "CLK_HROW_CK_HCLK_OUT_L4", - "CLK_HROW_CK_HCLK_OUT_L5", - "CLK_HROW_CK_HCLK_OUT_L6", - "CLK_HROW_CK_HCLK_OUT_L7", - "CLK_HROW_CK_HCLK_OUT_L8", - "CLK_HROW_CK_HCLK_OUT_L9", - "CLK_HROW_CK_HCLK_OUT_R0", - "CLK_HROW_CK_HCLK_OUT_R1", - "CLK_HROW_CK_HCLK_OUT_R10", - "CLK_HROW_CK_HCLK_OUT_R11", - "CLK_HROW_CK_HCLK_OUT_R2", - "CLK_HROW_CK_HCLK_OUT_R3", - "CLK_HROW_CK_HCLK_OUT_R4", - "CLK_HROW_CK_HCLK_OUT_R5", - "CLK_HROW_CK_HCLK_OUT_R6", - "CLK_HROW_CK_HCLK_OUT_R7", - "CLK_HROW_CK_HCLK_OUT_R8", - "CLK_HROW_CK_HCLK_OUT_R9", - "CLK_HROW_CK_INT_0_0", - "CLK_HROW_CK_INT_0_1", - "CLK_HROW_CK_INT_1_0", - "CLK_HROW_CK_INT_1_1", - "CLK_HROW_CK_IN_L0", - "CLK_HROW_CK_IN_L1", - "CLK_HROW_CK_IN_L10", - "CLK_HROW_CK_IN_L11", - "CLK_HROW_CK_IN_L12", - "CLK_HROW_CK_IN_L13", - "CLK_HROW_CK_IN_L2", - "CLK_HROW_CK_IN_L3", - "CLK_HROW_CK_IN_L4", - "CLK_HROW_CK_IN_L5", - "CLK_HROW_CK_IN_L6", - "CLK_HROW_CK_IN_L7", - "CLK_HROW_CK_IN_L8", - "CLK_HROW_CK_IN_L9", - "CLK_HROW_CK_IN_L_IN_TEST", - "CLK_HROW_CK_IN_L_OUT_TEST", - "CLK_HROW_CK_IN_L_TEST_IN", - "CLK_HROW_CK_IN_L_TEST_OUT", - "CLK_HROW_CK_IN_R0", - "CLK_HROW_CK_IN_R1", - "CLK_HROW_CK_IN_R10", - "CLK_HROW_CK_IN_R11", - "CLK_HROW_CK_IN_R12", - "CLK_HROW_CK_IN_R13", - "CLK_HROW_CK_IN_R2", - "CLK_HROW_CK_IN_R3", - "CLK_HROW_CK_IN_R4", - "CLK_HROW_CK_IN_R5", - "CLK_HROW_CK_IN_R6", - "CLK_HROW_CK_IN_R7", - "CLK_HROW_CK_IN_R8", - "CLK_HROW_CK_IN_R9", - "CLK_HROW_CK_IN_R_IN_TEST", - "CLK_HROW_CK_IN_R_OUT_TEST", - "CLK_HROW_CK_IN_R_TEST_IN", - "CLK_HROW_CK_IN_R_TEST_OUT", - "CLK_HROW_CK_MUX_OUT_L0", - "CLK_HROW_CK_MUX_OUT_L1", - "CLK_HROW_CK_MUX_OUT_L10", - "CLK_HROW_CK_MUX_OUT_L11", - "CLK_HROW_CK_MUX_OUT_L2", - "CLK_HROW_CK_MUX_OUT_L3", - "CLK_HROW_CK_MUX_OUT_L4", - "CLK_HROW_CK_MUX_OUT_L5", - "CLK_HROW_CK_MUX_OUT_L6", - "CLK_HROW_CK_MUX_OUT_L7", - "CLK_HROW_CK_MUX_OUT_L8", - "CLK_HROW_CK_MUX_OUT_L9", - "CLK_HROW_CK_MUX_OUT_R0", - "CLK_HROW_CK_MUX_OUT_R1", - "CLK_HROW_CK_MUX_OUT_R10", - "CLK_HROW_CK_MUX_OUT_R11", - "CLK_HROW_CK_MUX_OUT_R2", - "CLK_HROW_CK_MUX_OUT_R3", - "CLK_HROW_CK_MUX_OUT_R4", - "CLK_HROW_CK_MUX_OUT_R5", - "CLK_HROW_CK_MUX_OUT_R6", - "CLK_HROW_CK_MUX_OUT_R7", - "CLK_HROW_CK_MUX_OUT_R8", - "CLK_HROW_CK_MUX_OUT_R9", - "CLK_HROW_CLK0_0", - "CLK_HROW_CLK0_1", - "CLK_HROW_CLK0_2", - "CLK_HROW_CLK0_3", - "CLK_HROW_CLK0_4", - "CLK_HROW_CLK0_5", - "CLK_HROW_CLK0_6", - "CLK_HROW_CLK0_7", - "CLK_HROW_CLK1_0", - "CLK_HROW_CLK1_1", - "CLK_HROW_CLK1_2", - "CLK_HROW_CLK1_3", - "CLK_HROW_CLK1_4", - "CLK_HROW_CLK1_5", - "CLK_HROW_CLK1_6", - "CLK_HROW_CLK1_7", - "CLK_HROW_CTRL0_0", - "CLK_HROW_CTRL0_1", - "CLK_HROW_CTRL0_2", - "CLK_HROW_CTRL0_3", - "CLK_HROW_CTRL0_4", - "CLK_HROW_CTRL0_5", - "CLK_HROW_CTRL0_6", - "CLK_HROW_CTRL0_7", - "CLK_HROW_CTRL1_0", - "CLK_HROW_CTRL1_1", - "CLK_HROW_CTRL1_2", - "CLK_HROW_CTRL1_3", - "CLK_HROW_CTRL1_4", - "CLK_HROW_CTRL1_5", - "CLK_HROW_CTRL1_6", - "CLK_HROW_CTRL1_7", - "CLK_HROW_EE2A0_0", - "CLK_HROW_EE2A0_1", - "CLK_HROW_EE2A0_2", - "CLK_HROW_EE2A0_3", - "CLK_HROW_EE2A0_4", - "CLK_HROW_EE2A0_5", - "CLK_HROW_EE2A0_6", - "CLK_HROW_EE2A0_7", - "CLK_HROW_EE2A1_0", - "CLK_HROW_EE2A1_1", - "CLK_HROW_EE2A1_2", - "CLK_HROW_EE2A1_3", - "CLK_HROW_EE2A1_4", - "CLK_HROW_EE2A1_5", - "CLK_HROW_EE2A1_6", - "CLK_HROW_EE2A1_7", - "CLK_HROW_EE2A2_0", - "CLK_HROW_EE2A2_1", - "CLK_HROW_EE2A2_2", - "CLK_HROW_EE2A2_3", - "CLK_HROW_EE2A2_4", - "CLK_HROW_EE2A2_5", - "CLK_HROW_EE2A2_6", - "CLK_HROW_EE2A2_7", - "CLK_HROW_EE2A3_0", - "CLK_HROW_EE2A3_1", - "CLK_HROW_EE2A3_2", - "CLK_HROW_EE2A3_3", - "CLK_HROW_EE2A3_4", - "CLK_HROW_EE2A3_5", - "CLK_HROW_EE2A3_6", - "CLK_HROW_EE2A3_7", - "CLK_HROW_EE2BEG0_0", - "CLK_HROW_EE2BEG0_1", - "CLK_HROW_EE2BEG0_2", - "CLK_HROW_EE2BEG0_3", - "CLK_HROW_EE2BEG0_4", - "CLK_HROW_EE2BEG0_5", - "CLK_HROW_EE2BEG0_6", - "CLK_HROW_EE2BEG0_7", - "CLK_HROW_EE2BEG1_0", - "CLK_HROW_EE2BEG1_1", - "CLK_HROW_EE2BEG1_2", - "CLK_HROW_EE2BEG1_3", - "CLK_HROW_EE2BEG1_4", - "CLK_HROW_EE2BEG1_5", - "CLK_HROW_EE2BEG1_6", - "CLK_HROW_EE2BEG1_7", - "CLK_HROW_EE2BEG2_0", - "CLK_HROW_EE2BEG2_1", - "CLK_HROW_EE2BEG2_2", - "CLK_HROW_EE2BEG2_3", - "CLK_HROW_EE2BEG2_4", - "CLK_HROW_EE2BEG2_5", - "CLK_HROW_EE2BEG2_6", - "CLK_HROW_EE2BEG2_7", - "CLK_HROW_EE2BEG3_0", - "CLK_HROW_EE2BEG3_1", - "CLK_HROW_EE2BEG3_2", - "CLK_HROW_EE2BEG3_3", - "CLK_HROW_EE2BEG3_4", - "CLK_HROW_EE2BEG3_5", - "CLK_HROW_EE2BEG3_6", - "CLK_HROW_EE2BEG3_7", - "CLK_HROW_EE4A0_0", - "CLK_HROW_EE4A0_1", - "CLK_HROW_EE4A0_2", - "CLK_HROW_EE4A0_3", - "CLK_HROW_EE4A0_4", - "CLK_HROW_EE4A0_5", - "CLK_HROW_EE4A0_6", - "CLK_HROW_EE4A0_7", - "CLK_HROW_EE4A1_0", - "CLK_HROW_EE4A1_1", - "CLK_HROW_EE4A1_2", - "CLK_HROW_EE4A1_3", - "CLK_HROW_EE4A1_4", - "CLK_HROW_EE4A1_5", - "CLK_HROW_EE4A1_6", - "CLK_HROW_EE4A1_7", - "CLK_HROW_EE4A2_0", - "CLK_HROW_EE4A2_1", - "CLK_HROW_EE4A2_2", - "CLK_HROW_EE4A2_3", - "CLK_HROW_EE4A2_4", - "CLK_HROW_EE4A2_5", - "CLK_HROW_EE4A2_6", - "CLK_HROW_EE4A2_7", - "CLK_HROW_EE4A3_0", - "CLK_HROW_EE4A3_1", - "CLK_HROW_EE4A3_2", - "CLK_HROW_EE4A3_3", - "CLK_HROW_EE4A3_4", - "CLK_HROW_EE4A3_5", - "CLK_HROW_EE4A3_6", - "CLK_HROW_EE4A3_7", - "CLK_HROW_EE4B0_0", - "CLK_HROW_EE4B0_1", - "CLK_HROW_EE4B0_2", - "CLK_HROW_EE4B0_3", - "CLK_HROW_EE4B0_4", - "CLK_HROW_EE4B0_5", - "CLK_HROW_EE4B0_6", - "CLK_HROW_EE4B0_7", - "CLK_HROW_EE4B1_0", - "CLK_HROW_EE4B1_1", - "CLK_HROW_EE4B1_2", - "CLK_HROW_EE4B1_3", - "CLK_HROW_EE4B1_4", - "CLK_HROW_EE4B1_5", - "CLK_HROW_EE4B1_6", - "CLK_HROW_EE4B1_7", - "CLK_HROW_EE4B2_0", - "CLK_HROW_EE4B2_1", - "CLK_HROW_EE4B2_2", - "CLK_HROW_EE4B2_3", - "CLK_HROW_EE4B2_4", - "CLK_HROW_EE4B2_5", - "CLK_HROW_EE4B2_6", - "CLK_HROW_EE4B2_7", - "CLK_HROW_EE4B3_0", - "CLK_HROW_EE4B3_1", - "CLK_HROW_EE4B3_2", - "CLK_HROW_EE4B3_3", - "CLK_HROW_EE4B3_4", - "CLK_HROW_EE4B3_5", - "CLK_HROW_EE4B3_6", - "CLK_HROW_EE4B3_7", - "CLK_HROW_EE4BEG0_0", - "CLK_HROW_EE4BEG0_1", - "CLK_HROW_EE4BEG0_2", - "CLK_HROW_EE4BEG0_3", - "CLK_HROW_EE4BEG0_4", - "CLK_HROW_EE4BEG0_5", - "CLK_HROW_EE4BEG0_6", - "CLK_HROW_EE4BEG0_7", - "CLK_HROW_EE4BEG1_0", - "CLK_HROW_EE4BEG1_1", - "CLK_HROW_EE4BEG1_2", - "CLK_HROW_EE4BEG1_3", - "CLK_HROW_EE4BEG1_4", - "CLK_HROW_EE4BEG1_5", - "CLK_HROW_EE4BEG1_6", - "CLK_HROW_EE4BEG1_7", - "CLK_HROW_EE4BEG2_0", - "CLK_HROW_EE4BEG2_1", - "CLK_HROW_EE4BEG2_2", - "CLK_HROW_EE4BEG2_3", - "CLK_HROW_EE4BEG2_4", - "CLK_HROW_EE4BEG2_5", - "CLK_HROW_EE4BEG2_6", - "CLK_HROW_EE4BEG2_7", - "CLK_HROW_EE4BEG3_0", - "CLK_HROW_EE4BEG3_1", - "CLK_HROW_EE4BEG3_2", - "CLK_HROW_EE4BEG3_3", - "CLK_HROW_EE4BEG3_4", - "CLK_HROW_EE4BEG3_5", - "CLK_HROW_EE4BEG3_6", - "CLK_HROW_EE4BEG3_7", - "CLK_HROW_EE4C0_0", - "CLK_HROW_EE4C0_1", - "CLK_HROW_EE4C0_2", - "CLK_HROW_EE4C0_3", - "CLK_HROW_EE4C0_4", - "CLK_HROW_EE4C0_5", - "CLK_HROW_EE4C0_6", - "CLK_HROW_EE4C0_7", - "CLK_HROW_EE4C1_0", - "CLK_HROW_EE4C1_1", - "CLK_HROW_EE4C1_2", - "CLK_HROW_EE4C1_3", - "CLK_HROW_EE4C1_4", - "CLK_HROW_EE4C1_5", - "CLK_HROW_EE4C1_6", - "CLK_HROW_EE4C1_7", - "CLK_HROW_EE4C2_0", - "CLK_HROW_EE4C2_1", - "CLK_HROW_EE4C2_2", - "CLK_HROW_EE4C2_3", - "CLK_HROW_EE4C2_4", - "CLK_HROW_EE4C2_5", - "CLK_HROW_EE4C2_6", - "CLK_HROW_EE4C2_7", - "CLK_HROW_EE4C3_0", - "CLK_HROW_EE4C3_1", - "CLK_HROW_EE4C3_2", - "CLK_HROW_EE4C3_3", - "CLK_HROW_EE4C3_4", - "CLK_HROW_EE4C3_5", - "CLK_HROW_EE4C3_6", - "CLK_HROW_EE4C3_7", - "CLK_HROW_EL1BEG0_0", - "CLK_HROW_EL1BEG0_1", - "CLK_HROW_EL1BEG0_2", - "CLK_HROW_EL1BEG0_3", - "CLK_HROW_EL1BEG0_4", - "CLK_HROW_EL1BEG0_5", - "CLK_HROW_EL1BEG0_6", - "CLK_HROW_EL1BEG0_7", - "CLK_HROW_EL1BEG1_0", - "CLK_HROW_EL1BEG1_1", - "CLK_HROW_EL1BEG1_2", - "CLK_HROW_EL1BEG1_3", - "CLK_HROW_EL1BEG1_4", - "CLK_HROW_EL1BEG1_5", - "CLK_HROW_EL1BEG1_6", - "CLK_HROW_EL1BEG1_7", - "CLK_HROW_EL1BEG2_0", - "CLK_HROW_EL1BEG2_1", - "CLK_HROW_EL1BEG2_2", - "CLK_HROW_EL1BEG2_3", - "CLK_HROW_EL1BEG2_4", - "CLK_HROW_EL1BEG2_5", - "CLK_HROW_EL1BEG2_6", - "CLK_HROW_EL1BEG2_7", - "CLK_HROW_EL1BEG3_0", - "CLK_HROW_EL1BEG3_1", - "CLK_HROW_EL1BEG3_2", - "CLK_HROW_EL1BEG3_3", - "CLK_HROW_EL1BEG3_4", - "CLK_HROW_EL1BEG3_5", - "CLK_HROW_EL1BEG3_6", - "CLK_HROW_EL1BEG3_7", - "CLK_HROW_ER1BEG0_0", - "CLK_HROW_ER1BEG0_1", - "CLK_HROW_ER1BEG0_2", - "CLK_HROW_ER1BEG0_3", - "CLK_HROW_ER1BEG0_4", - "CLK_HROW_ER1BEG0_5", - "CLK_HROW_ER1BEG0_6", - "CLK_HROW_ER1BEG0_7", - "CLK_HROW_ER1BEG1_0", - "CLK_HROW_ER1BEG1_1", - "CLK_HROW_ER1BEG1_2", - "CLK_HROW_ER1BEG1_3", - "CLK_HROW_ER1BEG1_4", - "CLK_HROW_ER1BEG1_5", - "CLK_HROW_ER1BEG1_6", - "CLK_HROW_ER1BEG1_7", - "CLK_HROW_ER1BEG2_0", - "CLK_HROW_ER1BEG2_1", - "CLK_HROW_ER1BEG2_2", - "CLK_HROW_ER1BEG2_3", - "CLK_HROW_ER1BEG2_4", - "CLK_HROW_ER1BEG2_5", - "CLK_HROW_ER1BEG2_6", - "CLK_HROW_ER1BEG2_7", - "CLK_HROW_ER1BEG3_0", - "CLK_HROW_ER1BEG3_1", - "CLK_HROW_ER1BEG3_2", - "CLK_HROW_ER1BEG3_3", - "CLK_HROW_ER1BEG3_4", - "CLK_HROW_ER1BEG3_5", - "CLK_HROW_ER1BEG3_6", - "CLK_HROW_ER1BEG3_7", - "CLK_HROW_FAN0_0", - "CLK_HROW_FAN0_1", - "CLK_HROW_FAN0_2", - "CLK_HROW_FAN0_3", - "CLK_HROW_FAN0_4", - "CLK_HROW_FAN0_5", - "CLK_HROW_FAN0_6", - "CLK_HROW_FAN0_7", - "CLK_HROW_FAN1_0", - "CLK_HROW_FAN1_1", - "CLK_HROW_FAN1_2", - "CLK_HROW_FAN1_3", - "CLK_HROW_FAN1_4", - "CLK_HROW_FAN1_5", - "CLK_HROW_FAN1_6", - "CLK_HROW_FAN1_7", - "CLK_HROW_FAN2_0", - "CLK_HROW_FAN2_1", - "CLK_HROW_FAN2_2", - "CLK_HROW_FAN2_3", - "CLK_HROW_FAN2_4", - "CLK_HROW_FAN2_5", - "CLK_HROW_FAN2_6", - "CLK_HROW_FAN2_7", - "CLK_HROW_FAN3_0", - "CLK_HROW_FAN3_1", - "CLK_HROW_FAN3_2", - "CLK_HROW_FAN3_3", - "CLK_HROW_FAN3_4", - "CLK_HROW_FAN3_5", - "CLK_HROW_FAN3_6", - "CLK_HROW_FAN3_7", - "CLK_HROW_FAN4_0", - "CLK_HROW_FAN4_1", - "CLK_HROW_FAN4_2", - "CLK_HROW_FAN4_3", - "CLK_HROW_FAN4_4", - "CLK_HROW_FAN4_5", - "CLK_HROW_FAN4_6", - "CLK_HROW_FAN4_7", - "CLK_HROW_FAN5_0", - "CLK_HROW_FAN5_1", - "CLK_HROW_FAN5_2", - "CLK_HROW_FAN5_3", - "CLK_HROW_FAN5_4", - "CLK_HROW_FAN5_5", - "CLK_HROW_FAN5_6", - "CLK_HROW_FAN5_7", - "CLK_HROW_FAN6_0", - "CLK_HROW_FAN6_1", - "CLK_HROW_FAN6_2", - "CLK_HROW_FAN6_3", - "CLK_HROW_FAN6_4", - "CLK_HROW_FAN6_5", - "CLK_HROW_FAN6_6", - "CLK_HROW_FAN6_7", - "CLK_HROW_FAN7_0", - "CLK_HROW_FAN7_1", - "CLK_HROW_FAN7_2", - "CLK_HROW_FAN7_3", - "CLK_HROW_FAN7_4", - "CLK_HROW_FAN7_5", - "CLK_HROW_FAN7_6", - "CLK_HROW_FAN7_7", - "CLK_HROW_IMUX0_0", - "CLK_HROW_IMUX0_1", - "CLK_HROW_IMUX0_2", - "CLK_HROW_IMUX0_3", - "CLK_HROW_IMUX0_4", - "CLK_HROW_IMUX0_5", - "CLK_HROW_IMUX0_6", - "CLK_HROW_IMUX0_7", - "CLK_HROW_IMUX10_0", - "CLK_HROW_IMUX10_1", - "CLK_HROW_IMUX10_2", - "CLK_HROW_IMUX10_3", - "CLK_HROW_IMUX10_4", - "CLK_HROW_IMUX10_5", - "CLK_HROW_IMUX10_6", - "CLK_HROW_IMUX10_7", - "CLK_HROW_IMUX11_0", - "CLK_HROW_IMUX11_1", - "CLK_HROW_IMUX11_2", - "CLK_HROW_IMUX11_3", - "CLK_HROW_IMUX11_4", - "CLK_HROW_IMUX11_5", - "CLK_HROW_IMUX11_6", - "CLK_HROW_IMUX11_7", - "CLK_HROW_IMUX12_0", - "CLK_HROW_IMUX12_1", - "CLK_HROW_IMUX12_2", - "CLK_HROW_IMUX12_3", - "CLK_HROW_IMUX12_4", - "CLK_HROW_IMUX12_5", - "CLK_HROW_IMUX12_6", - "CLK_HROW_IMUX12_7", - "CLK_HROW_IMUX13_0", - "CLK_HROW_IMUX13_1", - "CLK_HROW_IMUX13_2", - "CLK_HROW_IMUX13_3", - "CLK_HROW_IMUX13_4", - "CLK_HROW_IMUX13_5", - "CLK_HROW_IMUX13_6", - "CLK_HROW_IMUX13_7", - "CLK_HROW_IMUX14_0", - "CLK_HROW_IMUX14_1", - "CLK_HROW_IMUX14_2", - "CLK_HROW_IMUX14_3", - "CLK_HROW_IMUX14_4", - "CLK_HROW_IMUX14_5", - "CLK_HROW_IMUX14_6", - "CLK_HROW_IMUX14_7", - "CLK_HROW_IMUX15_0", - "CLK_HROW_IMUX15_1", - "CLK_HROW_IMUX15_2", - "CLK_HROW_IMUX15_3", - "CLK_HROW_IMUX15_4", - "CLK_HROW_IMUX15_5", - "CLK_HROW_IMUX15_6", - "CLK_HROW_IMUX15_7", - "CLK_HROW_IMUX16_0", - "CLK_HROW_IMUX16_1", - "CLK_HROW_IMUX16_2", - "CLK_HROW_IMUX16_3", - "CLK_HROW_IMUX16_4", - "CLK_HROW_IMUX16_5", - "CLK_HROW_IMUX16_6", - "CLK_HROW_IMUX16_7", - "CLK_HROW_IMUX17_0", - "CLK_HROW_IMUX17_1", - "CLK_HROW_IMUX17_2", - "CLK_HROW_IMUX17_3", - "CLK_HROW_IMUX17_4", - "CLK_HROW_IMUX17_5", - "CLK_HROW_IMUX17_6", - "CLK_HROW_IMUX17_7", - "CLK_HROW_IMUX18_0", - "CLK_HROW_IMUX18_1", - "CLK_HROW_IMUX18_2", - "CLK_HROW_IMUX18_3", - "CLK_HROW_IMUX18_4", - "CLK_HROW_IMUX18_5", - "CLK_HROW_IMUX18_6", - "CLK_HROW_IMUX18_7", - "CLK_HROW_IMUX19_0", - "CLK_HROW_IMUX19_1", - "CLK_HROW_IMUX19_2", - "CLK_HROW_IMUX19_3", - "CLK_HROW_IMUX19_4", - "CLK_HROW_IMUX19_5", - "CLK_HROW_IMUX19_6", - "CLK_HROW_IMUX19_7", - "CLK_HROW_IMUX1_0", - "CLK_HROW_IMUX1_1", - "CLK_HROW_IMUX1_2", - "CLK_HROW_IMUX1_3", - "CLK_HROW_IMUX1_4", - "CLK_HROW_IMUX1_5", - "CLK_HROW_IMUX1_6", - "CLK_HROW_IMUX1_7", - "CLK_HROW_IMUX20_0", - "CLK_HROW_IMUX20_1", - "CLK_HROW_IMUX20_2", - "CLK_HROW_IMUX20_3", - "CLK_HROW_IMUX20_4", - "CLK_HROW_IMUX20_5", - "CLK_HROW_IMUX20_6", - "CLK_HROW_IMUX20_7", - "CLK_HROW_IMUX21_0", - "CLK_HROW_IMUX21_1", - "CLK_HROW_IMUX21_2", - "CLK_HROW_IMUX21_3", - "CLK_HROW_IMUX21_4", - "CLK_HROW_IMUX21_5", - "CLK_HROW_IMUX21_6", - "CLK_HROW_IMUX21_7", - "CLK_HROW_IMUX22_0", - "CLK_HROW_IMUX22_1", - "CLK_HROW_IMUX22_2", - "CLK_HROW_IMUX22_3", - "CLK_HROW_IMUX22_4", - "CLK_HROW_IMUX22_5", - "CLK_HROW_IMUX22_6", - "CLK_HROW_IMUX22_7", - "CLK_HROW_IMUX23_0", - "CLK_HROW_IMUX23_1", - "CLK_HROW_IMUX23_2", - "CLK_HROW_IMUX23_3", - "CLK_HROW_IMUX23_4", - "CLK_HROW_IMUX23_5", - "CLK_HROW_IMUX23_6", - "CLK_HROW_IMUX23_7", - "CLK_HROW_IMUX24_0", - "CLK_HROW_IMUX24_1", - "CLK_HROW_IMUX24_2", - "CLK_HROW_IMUX24_3", - "CLK_HROW_IMUX24_4", - "CLK_HROW_IMUX24_5", - "CLK_HROW_IMUX24_6", - "CLK_HROW_IMUX24_7", - "CLK_HROW_IMUX25_0", - "CLK_HROW_IMUX25_1", - "CLK_HROW_IMUX25_2", - "CLK_HROW_IMUX25_3", - "CLK_HROW_IMUX25_4", - "CLK_HROW_IMUX25_5", - "CLK_HROW_IMUX25_6", - "CLK_HROW_IMUX25_7", - "CLK_HROW_IMUX26_0", - "CLK_HROW_IMUX26_1", - "CLK_HROW_IMUX26_2", - "CLK_HROW_IMUX26_3", - "CLK_HROW_IMUX26_4", - "CLK_HROW_IMUX26_5", - "CLK_HROW_IMUX26_6", - "CLK_HROW_IMUX26_7", - "CLK_HROW_IMUX27_0", - "CLK_HROW_IMUX27_1", - "CLK_HROW_IMUX27_2", - "CLK_HROW_IMUX27_3", - "CLK_HROW_IMUX27_4", - "CLK_HROW_IMUX27_5", - "CLK_HROW_IMUX27_6", - "CLK_HROW_IMUX27_7", - "CLK_HROW_IMUX28_0", - "CLK_HROW_IMUX28_1", - "CLK_HROW_IMUX28_2", - "CLK_HROW_IMUX28_3", - "CLK_HROW_IMUX28_4", - "CLK_HROW_IMUX28_5", - "CLK_HROW_IMUX28_6", - "CLK_HROW_IMUX28_7", - "CLK_HROW_IMUX29_0", - "CLK_HROW_IMUX29_1", - "CLK_HROW_IMUX29_2", - "CLK_HROW_IMUX29_3", - "CLK_HROW_IMUX29_4", - "CLK_HROW_IMUX29_5", - "CLK_HROW_IMUX29_6", - "CLK_HROW_IMUX29_7", - "CLK_HROW_IMUX2_0", - "CLK_HROW_IMUX2_1", - "CLK_HROW_IMUX2_2", - "CLK_HROW_IMUX2_3", - "CLK_HROW_IMUX2_4", - "CLK_HROW_IMUX2_5", - "CLK_HROW_IMUX2_6", - "CLK_HROW_IMUX2_7", - "CLK_HROW_IMUX30_0", - "CLK_HROW_IMUX30_1", - "CLK_HROW_IMUX30_2", - "CLK_HROW_IMUX30_3", - "CLK_HROW_IMUX30_4", - "CLK_HROW_IMUX30_5", - "CLK_HROW_IMUX30_6", - "CLK_HROW_IMUX30_7", - "CLK_HROW_IMUX31_0", - "CLK_HROW_IMUX31_1", - "CLK_HROW_IMUX31_2", - "CLK_HROW_IMUX31_3", - "CLK_HROW_IMUX31_4", - "CLK_HROW_IMUX31_5", - "CLK_HROW_IMUX31_6", - "CLK_HROW_IMUX31_7", - "CLK_HROW_IMUX32_0", - "CLK_HROW_IMUX32_1", - "CLK_HROW_IMUX32_2", - "CLK_HROW_IMUX32_3", - "CLK_HROW_IMUX32_4", - "CLK_HROW_IMUX32_5", - "CLK_HROW_IMUX32_6", - "CLK_HROW_IMUX32_7", - "CLK_HROW_IMUX33_0", - "CLK_HROW_IMUX33_1", - "CLK_HROW_IMUX33_2", - "CLK_HROW_IMUX33_3", - "CLK_HROW_IMUX33_4", - "CLK_HROW_IMUX33_5", - "CLK_HROW_IMUX33_6", - "CLK_HROW_IMUX33_7", - "CLK_HROW_IMUX34_0", - "CLK_HROW_IMUX34_1", - "CLK_HROW_IMUX34_2", - "CLK_HROW_IMUX34_3", - "CLK_HROW_IMUX34_4", - "CLK_HROW_IMUX34_5", - "CLK_HROW_IMUX34_6", - "CLK_HROW_IMUX34_7", - "CLK_HROW_IMUX35_0", - "CLK_HROW_IMUX35_1", - "CLK_HROW_IMUX35_2", - "CLK_HROW_IMUX35_3", - "CLK_HROW_IMUX35_4", - "CLK_HROW_IMUX35_5", - "CLK_HROW_IMUX35_6", - "CLK_HROW_IMUX35_7", - "CLK_HROW_IMUX36_0", - "CLK_HROW_IMUX36_1", - "CLK_HROW_IMUX36_2", - "CLK_HROW_IMUX36_3", - "CLK_HROW_IMUX36_4", - "CLK_HROW_IMUX36_5", - "CLK_HROW_IMUX36_6", - "CLK_HROW_IMUX36_7", - "CLK_HROW_IMUX37_0", - "CLK_HROW_IMUX37_1", - "CLK_HROW_IMUX37_2", - "CLK_HROW_IMUX37_3", - "CLK_HROW_IMUX37_4", - "CLK_HROW_IMUX37_5", - "CLK_HROW_IMUX37_6", - "CLK_HROW_IMUX37_7", - "CLK_HROW_IMUX38_0", - "CLK_HROW_IMUX38_1", - "CLK_HROW_IMUX38_2", - "CLK_HROW_IMUX38_3", - "CLK_HROW_IMUX38_4", - "CLK_HROW_IMUX38_5", - "CLK_HROW_IMUX38_6", - "CLK_HROW_IMUX38_7", - "CLK_HROW_IMUX39_0", - "CLK_HROW_IMUX39_1", - "CLK_HROW_IMUX39_2", - "CLK_HROW_IMUX39_3", - "CLK_HROW_IMUX39_4", - "CLK_HROW_IMUX39_5", - "CLK_HROW_IMUX39_6", - "CLK_HROW_IMUX39_7", - "CLK_HROW_IMUX3_0", - "CLK_HROW_IMUX3_1", - "CLK_HROW_IMUX3_2", - "CLK_HROW_IMUX3_3", - "CLK_HROW_IMUX3_4", - "CLK_HROW_IMUX3_5", - "CLK_HROW_IMUX3_6", - "CLK_HROW_IMUX3_7", - "CLK_HROW_IMUX40_0", - "CLK_HROW_IMUX40_1", - "CLK_HROW_IMUX40_2", - "CLK_HROW_IMUX40_3", - "CLK_HROW_IMUX40_4", - "CLK_HROW_IMUX40_5", - "CLK_HROW_IMUX40_6", - "CLK_HROW_IMUX40_7", - "CLK_HROW_IMUX41_0", - "CLK_HROW_IMUX41_1", - "CLK_HROW_IMUX41_2", - "CLK_HROW_IMUX41_3", - "CLK_HROW_IMUX41_4", - "CLK_HROW_IMUX41_5", - "CLK_HROW_IMUX41_6", - "CLK_HROW_IMUX41_7", - "CLK_HROW_IMUX42_0", - "CLK_HROW_IMUX42_1", - "CLK_HROW_IMUX42_2", - "CLK_HROW_IMUX42_3", - "CLK_HROW_IMUX42_4", - "CLK_HROW_IMUX42_5", - "CLK_HROW_IMUX42_6", - "CLK_HROW_IMUX42_7", - "CLK_HROW_IMUX43_0", - "CLK_HROW_IMUX43_1", - "CLK_HROW_IMUX43_2", - "CLK_HROW_IMUX43_3", - "CLK_HROW_IMUX43_4", - "CLK_HROW_IMUX43_5", - "CLK_HROW_IMUX43_6", - "CLK_HROW_IMUX43_7", - "CLK_HROW_IMUX44_0", - "CLK_HROW_IMUX44_1", - "CLK_HROW_IMUX44_2", - "CLK_HROW_IMUX44_3", - "CLK_HROW_IMUX44_4", - "CLK_HROW_IMUX44_5", - "CLK_HROW_IMUX44_6", - "CLK_HROW_IMUX44_7", - "CLK_HROW_IMUX45_0", - "CLK_HROW_IMUX45_1", - "CLK_HROW_IMUX45_2", - "CLK_HROW_IMUX45_3", - "CLK_HROW_IMUX45_4", - "CLK_HROW_IMUX45_5", - "CLK_HROW_IMUX45_6", - "CLK_HROW_IMUX45_7", - "CLK_HROW_IMUX46_0", - "CLK_HROW_IMUX46_1", - "CLK_HROW_IMUX46_2", - "CLK_HROW_IMUX46_3", - "CLK_HROW_IMUX46_4", - "CLK_HROW_IMUX46_5", - "CLK_HROW_IMUX46_6", - "CLK_HROW_IMUX46_7", - "CLK_HROW_IMUX47_0", - "CLK_HROW_IMUX47_1", - "CLK_HROW_IMUX47_2", - "CLK_HROW_IMUX47_3", - "CLK_HROW_IMUX47_4", - "CLK_HROW_IMUX47_5", - "CLK_HROW_IMUX47_6", - "CLK_HROW_IMUX47_7", - "CLK_HROW_IMUX4_0", - "CLK_HROW_IMUX4_1", - "CLK_HROW_IMUX4_2", - "CLK_HROW_IMUX4_3", - "CLK_HROW_IMUX4_4", - "CLK_HROW_IMUX4_5", - "CLK_HROW_IMUX4_6", - "CLK_HROW_IMUX4_7", - "CLK_HROW_IMUX5_0", - "CLK_HROW_IMUX5_1", - "CLK_HROW_IMUX5_2", - "CLK_HROW_IMUX5_3", - "CLK_HROW_IMUX5_4", - "CLK_HROW_IMUX5_5", - "CLK_HROW_IMUX5_6", - "CLK_HROW_IMUX5_7", - "CLK_HROW_IMUX6_0", - "CLK_HROW_IMUX6_1", - "CLK_HROW_IMUX6_2", - "CLK_HROW_IMUX6_3", - "CLK_HROW_IMUX6_4", - "CLK_HROW_IMUX6_5", - "CLK_HROW_IMUX6_6", - "CLK_HROW_IMUX6_7", - "CLK_HROW_IMUX7_0", - "CLK_HROW_IMUX7_1", - "CLK_HROW_IMUX7_2", - "CLK_HROW_IMUX7_3", - "CLK_HROW_IMUX7_4", - "CLK_HROW_IMUX7_5", - "CLK_HROW_IMUX7_6", - "CLK_HROW_IMUX7_7", - "CLK_HROW_IMUX8_0", - "CLK_HROW_IMUX8_1", - "CLK_HROW_IMUX8_2", - "CLK_HROW_IMUX8_3", - "CLK_HROW_IMUX8_4", - "CLK_HROW_IMUX8_5", - "CLK_HROW_IMUX8_6", - "CLK_HROW_IMUX8_7", - "CLK_HROW_IMUX9_0", - "CLK_HROW_IMUX9_1", - "CLK_HROW_IMUX9_2", - "CLK_HROW_IMUX9_3", - "CLK_HROW_IMUX9_4", - "CLK_HROW_IMUX9_5", - "CLK_HROW_IMUX9_6", - "CLK_HROW_IMUX9_7", - "CLK_HROW_LH10_0", - "CLK_HROW_LH10_1", - "CLK_HROW_LH10_2", - "CLK_HROW_LH10_3", - "CLK_HROW_LH10_4", - "CLK_HROW_LH10_5", - "CLK_HROW_LH10_6", - "CLK_HROW_LH10_7", - "CLK_HROW_LH11_0", - "CLK_HROW_LH11_1", - "CLK_HROW_LH11_2", - "CLK_HROW_LH11_3", - "CLK_HROW_LH11_4", - "CLK_HROW_LH11_5", - "CLK_HROW_LH11_6", - "CLK_HROW_LH11_7", - "CLK_HROW_LH12_0", - "CLK_HROW_LH12_1", - "CLK_HROW_LH12_2", - "CLK_HROW_LH12_3", - "CLK_HROW_LH12_4", - "CLK_HROW_LH12_5", - "CLK_HROW_LH12_6", - "CLK_HROW_LH12_7", - "CLK_HROW_LH1_0", - "CLK_HROW_LH1_1", - "CLK_HROW_LH1_2", - "CLK_HROW_LH1_3", - "CLK_HROW_LH1_4", - "CLK_HROW_LH1_5", - "CLK_HROW_LH1_6", - "CLK_HROW_LH1_7", - "CLK_HROW_LH2_0", - "CLK_HROW_LH2_1", - "CLK_HROW_LH2_2", - "CLK_HROW_LH2_3", - "CLK_HROW_LH2_4", - "CLK_HROW_LH2_5", - "CLK_HROW_LH2_6", - "CLK_HROW_LH2_7", - "CLK_HROW_LH3_0", - "CLK_HROW_LH3_1", - "CLK_HROW_LH3_2", - "CLK_HROW_LH3_3", - "CLK_HROW_LH3_4", - "CLK_HROW_LH3_5", - "CLK_HROW_LH3_6", - "CLK_HROW_LH3_7", - "CLK_HROW_LH4_0", - "CLK_HROW_LH4_1", - "CLK_HROW_LH4_2", - "CLK_HROW_LH4_3", - "CLK_HROW_LH4_4", - "CLK_HROW_LH4_5", - "CLK_HROW_LH4_6", - "CLK_HROW_LH4_7", - "CLK_HROW_LH5_0", - "CLK_HROW_LH5_1", - "CLK_HROW_LH5_2", - "CLK_HROW_LH5_3", - "CLK_HROW_LH5_4", - "CLK_HROW_LH5_5", - "CLK_HROW_LH5_6", - "CLK_HROW_LH5_7", - "CLK_HROW_LH6_0", - "CLK_HROW_LH6_1", - "CLK_HROW_LH6_2", - "CLK_HROW_LH6_3", - "CLK_HROW_LH6_4", - "CLK_HROW_LH6_5", - "CLK_HROW_LH6_6", - "CLK_HROW_LH6_7", - "CLK_HROW_LH7_0", - "CLK_HROW_LH7_1", - "CLK_HROW_LH7_2", - "CLK_HROW_LH7_3", - "CLK_HROW_LH7_4", - "CLK_HROW_LH7_5", - "CLK_HROW_LH7_6", - "CLK_HROW_LH7_7", - "CLK_HROW_LH8_0", - "CLK_HROW_LH8_1", - "CLK_HROW_LH8_2", - "CLK_HROW_LH8_3", - "CLK_HROW_LH8_4", - "CLK_HROW_LH8_5", - "CLK_HROW_LH8_6", - "CLK_HROW_LH8_7", - "CLK_HROW_LH9_0", - "CLK_HROW_LH9_1", - "CLK_HROW_LH9_2", - "CLK_HROW_LH9_3", - "CLK_HROW_LH9_4", - "CLK_HROW_LH9_5", - "CLK_HROW_LH9_6", - "CLK_HROW_LH9_7", - "CLK_HROW_LOGIC_OUTS_B0_0", - "CLK_HROW_LOGIC_OUTS_B0_1", - "CLK_HROW_LOGIC_OUTS_B0_2", - "CLK_HROW_LOGIC_OUTS_B0_3", - "CLK_HROW_LOGIC_OUTS_B0_4", - "CLK_HROW_LOGIC_OUTS_B0_5", - "CLK_HROW_LOGIC_OUTS_B0_6", - "CLK_HROW_LOGIC_OUTS_B0_7", - "CLK_HROW_LOGIC_OUTS_B10_0", - "CLK_HROW_LOGIC_OUTS_B10_1", - "CLK_HROW_LOGIC_OUTS_B10_2", - "CLK_HROW_LOGIC_OUTS_B10_3", - "CLK_HROW_LOGIC_OUTS_B10_4", - "CLK_HROW_LOGIC_OUTS_B10_5", - "CLK_HROW_LOGIC_OUTS_B10_6", - "CLK_HROW_LOGIC_OUTS_B10_7", - "CLK_HROW_LOGIC_OUTS_B11_0", - "CLK_HROW_LOGIC_OUTS_B11_1", - "CLK_HROW_LOGIC_OUTS_B11_2", - "CLK_HROW_LOGIC_OUTS_B11_3", - "CLK_HROW_LOGIC_OUTS_B11_4", - "CLK_HROW_LOGIC_OUTS_B11_5", - "CLK_HROW_LOGIC_OUTS_B11_6", - "CLK_HROW_LOGIC_OUTS_B11_7", - "CLK_HROW_LOGIC_OUTS_B12_0", - "CLK_HROW_LOGIC_OUTS_B12_1", - "CLK_HROW_LOGIC_OUTS_B12_2", - "CLK_HROW_LOGIC_OUTS_B12_3", - "CLK_HROW_LOGIC_OUTS_B12_4", - "CLK_HROW_LOGIC_OUTS_B12_5", - "CLK_HROW_LOGIC_OUTS_B12_6", - "CLK_HROW_LOGIC_OUTS_B12_7", - "CLK_HROW_LOGIC_OUTS_B13_0", - "CLK_HROW_LOGIC_OUTS_B13_1", - "CLK_HROW_LOGIC_OUTS_B13_2", - "CLK_HROW_LOGIC_OUTS_B13_3", - "CLK_HROW_LOGIC_OUTS_B13_4", - "CLK_HROW_LOGIC_OUTS_B13_5", - "CLK_HROW_LOGIC_OUTS_B13_6", - "CLK_HROW_LOGIC_OUTS_B13_7", - "CLK_HROW_LOGIC_OUTS_B14_0", - "CLK_HROW_LOGIC_OUTS_B14_1", - "CLK_HROW_LOGIC_OUTS_B14_2", - "CLK_HROW_LOGIC_OUTS_B14_3", - "CLK_HROW_LOGIC_OUTS_B14_4", - "CLK_HROW_LOGIC_OUTS_B14_5", - "CLK_HROW_LOGIC_OUTS_B14_6", - "CLK_HROW_LOGIC_OUTS_B14_7", - "CLK_HROW_LOGIC_OUTS_B15_0", - "CLK_HROW_LOGIC_OUTS_B15_1", - "CLK_HROW_LOGIC_OUTS_B15_2", - "CLK_HROW_LOGIC_OUTS_B15_3", - "CLK_HROW_LOGIC_OUTS_B15_4", - "CLK_HROW_LOGIC_OUTS_B15_5", - "CLK_HROW_LOGIC_OUTS_B15_6", - "CLK_HROW_LOGIC_OUTS_B15_7", - "CLK_HROW_LOGIC_OUTS_B16_0", - "CLK_HROW_LOGIC_OUTS_B16_1", - "CLK_HROW_LOGIC_OUTS_B16_2", - "CLK_HROW_LOGIC_OUTS_B16_3", - "CLK_HROW_LOGIC_OUTS_B16_4", - "CLK_HROW_LOGIC_OUTS_B16_5", - "CLK_HROW_LOGIC_OUTS_B16_6", - "CLK_HROW_LOGIC_OUTS_B16_7", - "CLK_HROW_LOGIC_OUTS_B17_0", - "CLK_HROW_LOGIC_OUTS_B17_1", - "CLK_HROW_LOGIC_OUTS_B17_2", - "CLK_HROW_LOGIC_OUTS_B17_3", - "CLK_HROW_LOGIC_OUTS_B17_4", - "CLK_HROW_LOGIC_OUTS_B17_5", - "CLK_HROW_LOGIC_OUTS_B17_6", - "CLK_HROW_LOGIC_OUTS_B17_7", - "CLK_HROW_LOGIC_OUTS_B18_0", - "CLK_HROW_LOGIC_OUTS_B18_1", - "CLK_HROW_LOGIC_OUTS_B18_2", - "CLK_HROW_LOGIC_OUTS_B18_3", - "CLK_HROW_LOGIC_OUTS_B18_4", - "CLK_HROW_LOGIC_OUTS_B18_5", - "CLK_HROW_LOGIC_OUTS_B18_6", - "CLK_HROW_LOGIC_OUTS_B18_7", - "CLK_HROW_LOGIC_OUTS_B19_0", - "CLK_HROW_LOGIC_OUTS_B19_1", - "CLK_HROW_LOGIC_OUTS_B19_2", - "CLK_HROW_LOGIC_OUTS_B19_3", - "CLK_HROW_LOGIC_OUTS_B19_4", - "CLK_HROW_LOGIC_OUTS_B19_5", - "CLK_HROW_LOGIC_OUTS_B19_6", - "CLK_HROW_LOGIC_OUTS_B19_7", - "CLK_HROW_LOGIC_OUTS_B1_0", - "CLK_HROW_LOGIC_OUTS_B1_1", - "CLK_HROW_LOGIC_OUTS_B1_2", - "CLK_HROW_LOGIC_OUTS_B1_3", - "CLK_HROW_LOGIC_OUTS_B1_4", - "CLK_HROW_LOGIC_OUTS_B1_5", - "CLK_HROW_LOGIC_OUTS_B1_6", - "CLK_HROW_LOGIC_OUTS_B1_7", - "CLK_HROW_LOGIC_OUTS_B20_0", - "CLK_HROW_LOGIC_OUTS_B20_1", - "CLK_HROW_LOGIC_OUTS_B20_2", - "CLK_HROW_LOGIC_OUTS_B20_3", - "CLK_HROW_LOGIC_OUTS_B20_4", - "CLK_HROW_LOGIC_OUTS_B20_5", - "CLK_HROW_LOGIC_OUTS_B20_6", - "CLK_HROW_LOGIC_OUTS_B20_7", - "CLK_HROW_LOGIC_OUTS_B21_0", - "CLK_HROW_LOGIC_OUTS_B21_1", - "CLK_HROW_LOGIC_OUTS_B21_2", - "CLK_HROW_LOGIC_OUTS_B21_3", - "CLK_HROW_LOGIC_OUTS_B21_4", - "CLK_HROW_LOGIC_OUTS_B21_5", - "CLK_HROW_LOGIC_OUTS_B21_6", - "CLK_HROW_LOGIC_OUTS_B21_7", - "CLK_HROW_LOGIC_OUTS_B22_0", - "CLK_HROW_LOGIC_OUTS_B22_1", - "CLK_HROW_LOGIC_OUTS_B22_2", - "CLK_HROW_LOGIC_OUTS_B22_3", - "CLK_HROW_LOGIC_OUTS_B22_4", - "CLK_HROW_LOGIC_OUTS_B22_5", - "CLK_HROW_LOGIC_OUTS_B22_6", - "CLK_HROW_LOGIC_OUTS_B22_7", - "CLK_HROW_LOGIC_OUTS_B23_0", - "CLK_HROW_LOGIC_OUTS_B23_1", - "CLK_HROW_LOGIC_OUTS_B23_2", - "CLK_HROW_LOGIC_OUTS_B23_3", - "CLK_HROW_LOGIC_OUTS_B23_4", - "CLK_HROW_LOGIC_OUTS_B23_5", - "CLK_HROW_LOGIC_OUTS_B23_6", - "CLK_HROW_LOGIC_OUTS_B23_7", - "CLK_HROW_LOGIC_OUTS_B2_0", - "CLK_HROW_LOGIC_OUTS_B2_1", - "CLK_HROW_LOGIC_OUTS_B2_2", - "CLK_HROW_LOGIC_OUTS_B2_3", - "CLK_HROW_LOGIC_OUTS_B2_4", - "CLK_HROW_LOGIC_OUTS_B2_5", - "CLK_HROW_LOGIC_OUTS_B2_6", - "CLK_HROW_LOGIC_OUTS_B2_7", - "CLK_HROW_LOGIC_OUTS_B3_0", - "CLK_HROW_LOGIC_OUTS_B3_1", - "CLK_HROW_LOGIC_OUTS_B3_2", - "CLK_HROW_LOGIC_OUTS_B3_3", - "CLK_HROW_LOGIC_OUTS_B3_4", - "CLK_HROW_LOGIC_OUTS_B3_5", - "CLK_HROW_LOGIC_OUTS_B3_6", - "CLK_HROW_LOGIC_OUTS_B3_7", - "CLK_HROW_LOGIC_OUTS_B4_0", - "CLK_HROW_LOGIC_OUTS_B4_1", - "CLK_HROW_LOGIC_OUTS_B4_2", - "CLK_HROW_LOGIC_OUTS_B4_3", - "CLK_HROW_LOGIC_OUTS_B4_4", - "CLK_HROW_LOGIC_OUTS_B4_5", - "CLK_HROW_LOGIC_OUTS_B4_6", - "CLK_HROW_LOGIC_OUTS_B4_7", - "CLK_HROW_LOGIC_OUTS_B5_0", - "CLK_HROW_LOGIC_OUTS_B5_1", - "CLK_HROW_LOGIC_OUTS_B5_2", - "CLK_HROW_LOGIC_OUTS_B5_3", - "CLK_HROW_LOGIC_OUTS_B5_4", - "CLK_HROW_LOGIC_OUTS_B5_5", - "CLK_HROW_LOGIC_OUTS_B5_6", - "CLK_HROW_LOGIC_OUTS_B5_7", - "CLK_HROW_LOGIC_OUTS_B6_0", - "CLK_HROW_LOGIC_OUTS_B6_1", - "CLK_HROW_LOGIC_OUTS_B6_2", - "CLK_HROW_LOGIC_OUTS_B6_3", - "CLK_HROW_LOGIC_OUTS_B6_4", - "CLK_HROW_LOGIC_OUTS_B6_5", - "CLK_HROW_LOGIC_OUTS_B6_6", - "CLK_HROW_LOGIC_OUTS_B6_7", - "CLK_HROW_LOGIC_OUTS_B7_0", - "CLK_HROW_LOGIC_OUTS_B7_1", - "CLK_HROW_LOGIC_OUTS_B7_2", - "CLK_HROW_LOGIC_OUTS_B7_3", - "CLK_HROW_LOGIC_OUTS_B7_4", - "CLK_HROW_LOGIC_OUTS_B7_5", - "CLK_HROW_LOGIC_OUTS_B7_6", - "CLK_HROW_LOGIC_OUTS_B7_7", - "CLK_HROW_LOGIC_OUTS_B8_0", - "CLK_HROW_LOGIC_OUTS_B8_1", - "CLK_HROW_LOGIC_OUTS_B8_2", - "CLK_HROW_LOGIC_OUTS_B8_3", - "CLK_HROW_LOGIC_OUTS_B8_4", - "CLK_HROW_LOGIC_OUTS_B8_5", - "CLK_HROW_LOGIC_OUTS_B8_6", - "CLK_HROW_LOGIC_OUTS_B8_7", - "CLK_HROW_LOGIC_OUTS_B9_0", - "CLK_HROW_LOGIC_OUTS_B9_1", - "CLK_HROW_LOGIC_OUTS_B9_2", - "CLK_HROW_LOGIC_OUTS_B9_3", - "CLK_HROW_LOGIC_OUTS_B9_4", - "CLK_HROW_LOGIC_OUTS_B9_5", - "CLK_HROW_LOGIC_OUTS_B9_6", - "CLK_HROW_LOGIC_OUTS_B9_7", - "CLK_HROW_MONITOR_N_0", - "CLK_HROW_MONITOR_N_1", - "CLK_HROW_MONITOR_N_2", - "CLK_HROW_MONITOR_N_3", - "CLK_HROW_MONITOR_N_4", - "CLK_HROW_MONITOR_N_5", - "CLK_HROW_MONITOR_N_6", - "CLK_HROW_MONITOR_N_7", - "CLK_HROW_MONITOR_P_0", - "CLK_HROW_MONITOR_P_1", - "CLK_HROW_MONITOR_P_2", - "CLK_HROW_MONITOR_P_3", - "CLK_HROW_MONITOR_P_4", - "CLK_HROW_MONITOR_P_5", - "CLK_HROW_MONITOR_P_6", - "CLK_HROW_MONITOR_P_7", - "CLK_HROW_NE2A0_0", - "CLK_HROW_NE2A0_1", - "CLK_HROW_NE2A0_2", - "CLK_HROW_NE2A0_3", - "CLK_HROW_NE2A0_4", - "CLK_HROW_NE2A0_5", - "CLK_HROW_NE2A0_6", - "CLK_HROW_NE2A0_7", - "CLK_HROW_NE2A1_0", - "CLK_HROW_NE2A1_1", - "CLK_HROW_NE2A1_2", - "CLK_HROW_NE2A1_3", - "CLK_HROW_NE2A1_4", - "CLK_HROW_NE2A1_5", - "CLK_HROW_NE2A1_6", - "CLK_HROW_NE2A1_7", - "CLK_HROW_NE2A2_0", - "CLK_HROW_NE2A2_1", - "CLK_HROW_NE2A2_2", - "CLK_HROW_NE2A2_3", - "CLK_HROW_NE2A2_4", - "CLK_HROW_NE2A2_5", - "CLK_HROW_NE2A2_6", - "CLK_HROW_NE2A2_7", - "CLK_HROW_NE2A3_0", - "CLK_HROW_NE2A3_1", - "CLK_HROW_NE2A3_2", - "CLK_HROW_NE2A3_3", - "CLK_HROW_NE2A3_4", - "CLK_HROW_NE2A3_5", - "CLK_HROW_NE2A3_6", - "CLK_HROW_NE2A3_7", - "CLK_HROW_NE4BEG0_0", - "CLK_HROW_NE4BEG0_1", - "CLK_HROW_NE4BEG0_2", - "CLK_HROW_NE4BEG0_3", - "CLK_HROW_NE4BEG0_4", - "CLK_HROW_NE4BEG0_5", - "CLK_HROW_NE4BEG0_6", - "CLK_HROW_NE4BEG0_7", - "CLK_HROW_NE4BEG1_0", - "CLK_HROW_NE4BEG1_1", - "CLK_HROW_NE4BEG1_2", - "CLK_HROW_NE4BEG1_3", - "CLK_HROW_NE4BEG1_4", - "CLK_HROW_NE4BEG1_5", - "CLK_HROW_NE4BEG1_6", - "CLK_HROW_NE4BEG1_7", - "CLK_HROW_NE4BEG2_0", - "CLK_HROW_NE4BEG2_1", - "CLK_HROW_NE4BEG2_2", - "CLK_HROW_NE4BEG2_3", - "CLK_HROW_NE4BEG2_4", - "CLK_HROW_NE4BEG2_5", - "CLK_HROW_NE4BEG2_6", - "CLK_HROW_NE4BEG2_7", - "CLK_HROW_NE4BEG3_0", - "CLK_HROW_NE4BEG3_1", - "CLK_HROW_NE4BEG3_2", - "CLK_HROW_NE4BEG3_3", - "CLK_HROW_NE4BEG3_4", - "CLK_HROW_NE4BEG3_5", - "CLK_HROW_NE4BEG3_6", - "CLK_HROW_NE4BEG3_7", - "CLK_HROW_NE4C0_0", - "CLK_HROW_NE4C0_1", - "CLK_HROW_NE4C0_2", - "CLK_HROW_NE4C0_3", - "CLK_HROW_NE4C0_4", - "CLK_HROW_NE4C0_5", - "CLK_HROW_NE4C0_6", - "CLK_HROW_NE4C0_7", - "CLK_HROW_NE4C1_0", - "CLK_HROW_NE4C1_1", - "CLK_HROW_NE4C1_2", - "CLK_HROW_NE4C1_3", - "CLK_HROW_NE4C1_4", - "CLK_HROW_NE4C1_5", - "CLK_HROW_NE4C1_6", - "CLK_HROW_NE4C1_7", - "CLK_HROW_NE4C2_0", - "CLK_HROW_NE4C2_1", - "CLK_HROW_NE4C2_2", - "CLK_HROW_NE4C2_3", - "CLK_HROW_NE4C2_4", - "CLK_HROW_NE4C2_5", - "CLK_HROW_NE4C2_6", - "CLK_HROW_NE4C2_7", - "CLK_HROW_NE4C3_0", - "CLK_HROW_NE4C3_1", - "CLK_HROW_NE4C3_2", - "CLK_HROW_NE4C3_3", - "CLK_HROW_NE4C3_4", - "CLK_HROW_NE4C3_5", - "CLK_HROW_NE4C3_6", - "CLK_HROW_NE4C3_7", - "CLK_HROW_NW2A0_0", - "CLK_HROW_NW2A0_1", - "CLK_HROW_NW2A0_2", - "CLK_HROW_NW2A0_3", - "CLK_HROW_NW2A0_4", - "CLK_HROW_NW2A0_5", - "CLK_HROW_NW2A0_6", - "CLK_HROW_NW2A0_7", - "CLK_HROW_NW2A1_0", - "CLK_HROW_NW2A1_1", - "CLK_HROW_NW2A1_2", - "CLK_HROW_NW2A1_3", - "CLK_HROW_NW2A1_4", - "CLK_HROW_NW2A1_5", - "CLK_HROW_NW2A1_6", - "CLK_HROW_NW2A1_7", - "CLK_HROW_NW2A2_0", - "CLK_HROW_NW2A2_1", - "CLK_HROW_NW2A2_2", - "CLK_HROW_NW2A2_3", - "CLK_HROW_NW2A2_4", - "CLK_HROW_NW2A2_5", - "CLK_HROW_NW2A2_6", - "CLK_HROW_NW2A2_7", - "CLK_HROW_NW2A3_0", - "CLK_HROW_NW2A3_1", - "CLK_HROW_NW2A3_2", - "CLK_HROW_NW2A3_3", - "CLK_HROW_NW2A3_4", - "CLK_HROW_NW2A3_5", - "CLK_HROW_NW2A3_6", - "CLK_HROW_NW2A3_7", - "CLK_HROW_NW4A0_0", - "CLK_HROW_NW4A0_1", - "CLK_HROW_NW4A0_2", - "CLK_HROW_NW4A0_3", - "CLK_HROW_NW4A0_4", - "CLK_HROW_NW4A0_5", - "CLK_HROW_NW4A0_6", - "CLK_HROW_NW4A0_7", - "CLK_HROW_NW4A1_0", - "CLK_HROW_NW4A1_1", - "CLK_HROW_NW4A1_2", - "CLK_HROW_NW4A1_3", - "CLK_HROW_NW4A1_4", - "CLK_HROW_NW4A1_5", - "CLK_HROW_NW4A1_6", - "CLK_HROW_NW4A1_7", - "CLK_HROW_NW4A2_0", - "CLK_HROW_NW4A2_1", - "CLK_HROW_NW4A2_2", - "CLK_HROW_NW4A2_3", - "CLK_HROW_NW4A2_4", - "CLK_HROW_NW4A2_5", - "CLK_HROW_NW4A2_6", - "CLK_HROW_NW4A2_7", - "CLK_HROW_NW4A3_0", - "CLK_HROW_NW4A3_1", - "CLK_HROW_NW4A3_2", - "CLK_HROW_NW4A3_3", - "CLK_HROW_NW4A3_4", - "CLK_HROW_NW4A3_5", - "CLK_HROW_NW4A3_6", - "CLK_HROW_NW4A3_7", - "CLK_HROW_NW4END0_0", - "CLK_HROW_NW4END0_1", - "CLK_HROW_NW4END0_2", - "CLK_HROW_NW4END0_3", - "CLK_HROW_NW4END0_4", - "CLK_HROW_NW4END0_5", - "CLK_HROW_NW4END0_6", - "CLK_HROW_NW4END0_7", - "CLK_HROW_NW4END1_0", - "CLK_HROW_NW4END1_1", - "CLK_HROW_NW4END1_2", - "CLK_HROW_NW4END1_3", - "CLK_HROW_NW4END1_4", - "CLK_HROW_NW4END1_5", - "CLK_HROW_NW4END1_6", - "CLK_HROW_NW4END1_7", - "CLK_HROW_NW4END2_0", - "CLK_HROW_NW4END2_1", - "CLK_HROW_NW4END2_2", - "CLK_HROW_NW4END2_3", - "CLK_HROW_NW4END2_4", - "CLK_HROW_NW4END2_5", - "CLK_HROW_NW4END2_6", - "CLK_HROW_NW4END2_7", - "CLK_HROW_NW4END3_0", - "CLK_HROW_NW4END3_1", - "CLK_HROW_NW4END3_2", - "CLK_HROW_NW4END3_3", - "CLK_HROW_NW4END3_4", - "CLK_HROW_NW4END3_5", - "CLK_HROW_NW4END3_6", - "CLK_HROW_NW4END3_7", - "CLK_HROW_REFCK_EASTCLK0", - "CLK_HROW_REFCK_EASTCLK1", - "CLK_HROW_REFCK_WESTCLK0", - "CLK_HROW_REFCK_WESTCLK1", - "CLK_HROW_R_CK_GCLK0", - "CLK_HROW_R_CK_GCLK1", - "CLK_HROW_R_CK_GCLK10", - "CLK_HROW_R_CK_GCLK11", - "CLK_HROW_R_CK_GCLK12", - "CLK_HROW_R_CK_GCLK13", - "CLK_HROW_R_CK_GCLK14", - "CLK_HROW_R_CK_GCLK15", - "CLK_HROW_R_CK_GCLK16", - "CLK_HROW_R_CK_GCLK17", - "CLK_HROW_R_CK_GCLK18", - "CLK_HROW_R_CK_GCLK19", - "CLK_HROW_R_CK_GCLK2", - "CLK_HROW_R_CK_GCLK20", - "CLK_HROW_R_CK_GCLK21", - "CLK_HROW_R_CK_GCLK22", - "CLK_HROW_R_CK_GCLK23", - "CLK_HROW_R_CK_GCLK24", - "CLK_HROW_R_CK_GCLK25", - "CLK_HROW_R_CK_GCLK26", - "CLK_HROW_R_CK_GCLK27", - "CLK_HROW_R_CK_GCLK28", - "CLK_HROW_R_CK_GCLK29", - "CLK_HROW_R_CK_GCLK3", - "CLK_HROW_R_CK_GCLK30", - "CLK_HROW_R_CK_GCLK31", - "CLK_HROW_R_CK_GCLK4", - "CLK_HROW_R_CK_GCLK5", - "CLK_HROW_R_CK_GCLK6", - "CLK_HROW_R_CK_GCLK7", - "CLK_HROW_R_CK_GCLK8", - "CLK_HROW_R_CK_GCLK9", - "CLK_HROW_SE2A0_0", - "CLK_HROW_SE2A0_1", - "CLK_HROW_SE2A0_2", - "CLK_HROW_SE2A0_3", - "CLK_HROW_SE2A0_4", - "CLK_HROW_SE2A0_5", - "CLK_HROW_SE2A0_6", - "CLK_HROW_SE2A0_7", - "CLK_HROW_SE2A1_0", - "CLK_HROW_SE2A1_1", - "CLK_HROW_SE2A1_2", - "CLK_HROW_SE2A1_3", - "CLK_HROW_SE2A1_4", - "CLK_HROW_SE2A1_5", - "CLK_HROW_SE2A1_6", - "CLK_HROW_SE2A1_7", - "CLK_HROW_SE2A2_0", - "CLK_HROW_SE2A2_1", - "CLK_HROW_SE2A2_2", - "CLK_HROW_SE2A2_3", - "CLK_HROW_SE2A2_4", - "CLK_HROW_SE2A2_5", - "CLK_HROW_SE2A2_6", - "CLK_HROW_SE2A2_7", - "CLK_HROW_SE2A3_0", - "CLK_HROW_SE2A3_1", - "CLK_HROW_SE2A3_2", - "CLK_HROW_SE2A3_3", - "CLK_HROW_SE2A3_4", - "CLK_HROW_SE2A3_5", - "CLK_HROW_SE2A3_6", - "CLK_HROW_SE2A3_7", - "CLK_HROW_SE4BEG0_0", - "CLK_HROW_SE4BEG0_1", - "CLK_HROW_SE4BEG0_2", - "CLK_HROW_SE4BEG0_3", - "CLK_HROW_SE4BEG0_4", - "CLK_HROW_SE4BEG0_5", - "CLK_HROW_SE4BEG0_6", - "CLK_HROW_SE4BEG0_7", - "CLK_HROW_SE4BEG1_0", - "CLK_HROW_SE4BEG1_1", - "CLK_HROW_SE4BEG1_2", - "CLK_HROW_SE4BEG1_3", - "CLK_HROW_SE4BEG1_4", - "CLK_HROW_SE4BEG1_5", - "CLK_HROW_SE4BEG1_6", - "CLK_HROW_SE4BEG1_7", - "CLK_HROW_SE4BEG2_0", - "CLK_HROW_SE4BEG2_1", - "CLK_HROW_SE4BEG2_2", - "CLK_HROW_SE4BEG2_3", - "CLK_HROW_SE4BEG2_4", - "CLK_HROW_SE4BEG2_5", - "CLK_HROW_SE4BEG2_6", - "CLK_HROW_SE4BEG2_7", - "CLK_HROW_SE4BEG3_0", - "CLK_HROW_SE4BEG3_1", - "CLK_HROW_SE4BEG3_2", - "CLK_HROW_SE4BEG3_3", - "CLK_HROW_SE4BEG3_4", - "CLK_HROW_SE4BEG3_5", - "CLK_HROW_SE4BEG3_6", - "CLK_HROW_SE4BEG3_7", - "CLK_HROW_SE4C0_0", - "CLK_HROW_SE4C0_1", - "CLK_HROW_SE4C0_2", - "CLK_HROW_SE4C0_3", - "CLK_HROW_SE4C0_4", - "CLK_HROW_SE4C0_5", - "CLK_HROW_SE4C0_6", - "CLK_HROW_SE4C0_7", - "CLK_HROW_SE4C1_0", - "CLK_HROW_SE4C1_1", - "CLK_HROW_SE4C1_2", - "CLK_HROW_SE4C1_3", - "CLK_HROW_SE4C1_4", - "CLK_HROW_SE4C1_5", - "CLK_HROW_SE4C1_6", - "CLK_HROW_SE4C1_7", - "CLK_HROW_SE4C2_0", - "CLK_HROW_SE4C2_1", - "CLK_HROW_SE4C2_2", - "CLK_HROW_SE4C2_3", - "CLK_HROW_SE4C2_4", - "CLK_HROW_SE4C2_5", - "CLK_HROW_SE4C2_6", - "CLK_HROW_SE4C2_7", - "CLK_HROW_SE4C3_0", - "CLK_HROW_SE4C3_1", - "CLK_HROW_SE4C3_2", - "CLK_HROW_SE4C3_3", - "CLK_HROW_SE4C3_4", - "CLK_HROW_SE4C3_5", - "CLK_HROW_SE4C3_6", - "CLK_HROW_SE4C3_7", - "CLK_HROW_SW2A0_0", - "CLK_HROW_SW2A0_1", - "CLK_HROW_SW2A0_2", - "CLK_HROW_SW2A0_3", - "CLK_HROW_SW2A0_4", - "CLK_HROW_SW2A0_5", - "CLK_HROW_SW2A0_6", - "CLK_HROW_SW2A0_7", - "CLK_HROW_SW2A1_0", - "CLK_HROW_SW2A1_1", - "CLK_HROW_SW2A1_2", - "CLK_HROW_SW2A1_3", - "CLK_HROW_SW2A1_4", - "CLK_HROW_SW2A1_5", - "CLK_HROW_SW2A1_6", - "CLK_HROW_SW2A1_7", - "CLK_HROW_SW2A2_0", - "CLK_HROW_SW2A2_1", - "CLK_HROW_SW2A2_2", - "CLK_HROW_SW2A2_3", - "CLK_HROW_SW2A2_4", - "CLK_HROW_SW2A2_5", - "CLK_HROW_SW2A2_6", - "CLK_HROW_SW2A2_7", - "CLK_HROW_SW2A3_0", - "CLK_HROW_SW2A3_1", - "CLK_HROW_SW2A3_2", - "CLK_HROW_SW2A3_3", - "CLK_HROW_SW2A3_4", - "CLK_HROW_SW2A3_5", - "CLK_HROW_SW2A3_6", - "CLK_HROW_SW2A3_7", - "CLK_HROW_SW4A0_0", - "CLK_HROW_SW4A0_1", - "CLK_HROW_SW4A0_2", - "CLK_HROW_SW4A0_3", - "CLK_HROW_SW4A0_4", - "CLK_HROW_SW4A0_5", - "CLK_HROW_SW4A0_6", - "CLK_HROW_SW4A0_7", - "CLK_HROW_SW4A1_0", - "CLK_HROW_SW4A1_1", - "CLK_HROW_SW4A1_2", - "CLK_HROW_SW4A1_3", - "CLK_HROW_SW4A1_4", - "CLK_HROW_SW4A1_5", - "CLK_HROW_SW4A1_6", - "CLK_HROW_SW4A1_7", - "CLK_HROW_SW4A2_0", - "CLK_HROW_SW4A2_1", - "CLK_HROW_SW4A2_2", - "CLK_HROW_SW4A2_3", - "CLK_HROW_SW4A2_4", - "CLK_HROW_SW4A2_5", - "CLK_HROW_SW4A2_6", - "CLK_HROW_SW4A2_7", - "CLK_HROW_SW4A3_0", - "CLK_HROW_SW4A3_1", - "CLK_HROW_SW4A3_2", - "CLK_HROW_SW4A3_3", - "CLK_HROW_SW4A3_4", - "CLK_HROW_SW4A3_5", - "CLK_HROW_SW4A3_6", - "CLK_HROW_SW4A3_7", - "CLK_HROW_SW4END0_0", - "CLK_HROW_SW4END0_1", - "CLK_HROW_SW4END0_2", - "CLK_HROW_SW4END0_3", - "CLK_HROW_SW4END0_4", - "CLK_HROW_SW4END0_5", - "CLK_HROW_SW4END0_6", - "CLK_HROW_SW4END0_7", - "CLK_HROW_SW4END1_0", - "CLK_HROW_SW4END1_1", - "CLK_HROW_SW4END1_2", - "CLK_HROW_SW4END1_3", - "CLK_HROW_SW4END1_4", - "CLK_HROW_SW4END1_5", - "CLK_HROW_SW4END1_6", - "CLK_HROW_SW4END1_7", - "CLK_HROW_SW4END2_0", - "CLK_HROW_SW4END2_1", - "CLK_HROW_SW4END2_2", - "CLK_HROW_SW4END2_3", - "CLK_HROW_SW4END2_4", - "CLK_HROW_SW4END2_5", - "CLK_HROW_SW4END2_6", - "CLK_HROW_SW4END2_7", - "CLK_HROW_SW4END3_0", - "CLK_HROW_SW4END3_1", - "CLK_HROW_SW4END3_2", - "CLK_HROW_SW4END3_3", - "CLK_HROW_SW4END3_4", - "CLK_HROW_SW4END3_5", - "CLK_HROW_SW4END3_6", - "CLK_HROW_SW4END3_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN0", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN1", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN10", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN11", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN12", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN13", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN14", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN15", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN16", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN17", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN18", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN19", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN2", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN20", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN21", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN22", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN23", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN24", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN25", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN26", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN27", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN28", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN29", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN3", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN30", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN31", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN4", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN5", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN6", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN7", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN8", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN9", - "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "CLK_HROW_WL1END0_0", - "CLK_HROW_WL1END0_1", - "CLK_HROW_WL1END0_2", - "CLK_HROW_WL1END0_3", - "CLK_HROW_WL1END0_4", - "CLK_HROW_WL1END0_5", - "CLK_HROW_WL1END0_6", - "CLK_HROW_WL1END0_7", - "CLK_HROW_WL1END1_0", - "CLK_HROW_WL1END1_1", - "CLK_HROW_WL1END1_2", - "CLK_HROW_WL1END1_3", - "CLK_HROW_WL1END1_4", - "CLK_HROW_WL1END1_5", - "CLK_HROW_WL1END1_6", - "CLK_HROW_WL1END1_7", - "CLK_HROW_WL1END2_0", - "CLK_HROW_WL1END2_1", - "CLK_HROW_WL1END2_2", - "CLK_HROW_WL1END2_3", - "CLK_HROW_WL1END2_4", - "CLK_HROW_WL1END2_5", - "CLK_HROW_WL1END2_6", - "CLK_HROW_WL1END2_7", - "CLK_HROW_WL1END3_0", - "CLK_HROW_WL1END3_1", - "CLK_HROW_WL1END3_2", - "CLK_HROW_WL1END3_3", - "CLK_HROW_WL1END3_4", - "CLK_HROW_WL1END3_5", - "CLK_HROW_WL1END3_6", - "CLK_HROW_WL1END3_7", - "CLK_HROW_WR1END0_0", - "CLK_HROW_WR1END0_1", - "CLK_HROW_WR1END0_2", - "CLK_HROW_WR1END0_3", - "CLK_HROW_WR1END0_4", - "CLK_HROW_WR1END0_5", - "CLK_HROW_WR1END0_6", - "CLK_HROW_WR1END0_7", - "CLK_HROW_WR1END1_0", - "CLK_HROW_WR1END1_1", - "CLK_HROW_WR1END1_2", - "CLK_HROW_WR1END1_3", - "CLK_HROW_WR1END1_4", - "CLK_HROW_WR1END1_5", - "CLK_HROW_WR1END1_6", - "CLK_HROW_WR1END1_7", - "CLK_HROW_WR1END2_0", - "CLK_HROW_WR1END2_1", - "CLK_HROW_WR1END2_2", - "CLK_HROW_WR1END2_3", - "CLK_HROW_WR1END2_4", - "CLK_HROW_WR1END2_5", - "CLK_HROW_WR1END2_6", - "CLK_HROW_WR1END2_7", - "CLK_HROW_WR1END3_0", - "CLK_HROW_WR1END3_1", - "CLK_HROW_WR1END3_2", - "CLK_HROW_WR1END3_3", - "CLK_HROW_WR1END3_4", - "CLK_HROW_WR1END3_5", - "CLK_HROW_WR1END3_6", - "CLK_HROW_WR1END3_7", - "CLK_HROW_WW2A0_0", - "CLK_HROW_WW2A0_1", - "CLK_HROW_WW2A0_2", - "CLK_HROW_WW2A0_3", - "CLK_HROW_WW2A0_4", - "CLK_HROW_WW2A0_5", - "CLK_HROW_WW2A0_6", - "CLK_HROW_WW2A0_7", - "CLK_HROW_WW2A1_0", - "CLK_HROW_WW2A1_1", - "CLK_HROW_WW2A1_2", - "CLK_HROW_WW2A1_3", - "CLK_HROW_WW2A1_4", - "CLK_HROW_WW2A1_5", - "CLK_HROW_WW2A1_6", - "CLK_HROW_WW2A1_7", - "CLK_HROW_WW2A2_0", - "CLK_HROW_WW2A2_1", - "CLK_HROW_WW2A2_2", - "CLK_HROW_WW2A2_3", - "CLK_HROW_WW2A2_4", - "CLK_HROW_WW2A2_5", - "CLK_HROW_WW2A2_6", - "CLK_HROW_WW2A2_7", - "CLK_HROW_WW2A3_0", - "CLK_HROW_WW2A3_1", - "CLK_HROW_WW2A3_2", - "CLK_HROW_WW2A3_3", - "CLK_HROW_WW2A3_4", - "CLK_HROW_WW2A3_5", - "CLK_HROW_WW2A3_6", - "CLK_HROW_WW2A3_7", - "CLK_HROW_WW2END0_0", - "CLK_HROW_WW2END0_1", - "CLK_HROW_WW2END0_2", - "CLK_HROW_WW2END0_3", - "CLK_HROW_WW2END0_4", - "CLK_HROW_WW2END0_5", - "CLK_HROW_WW2END0_6", - "CLK_HROW_WW2END0_7", - "CLK_HROW_WW2END1_0", - "CLK_HROW_WW2END1_1", - "CLK_HROW_WW2END1_2", - "CLK_HROW_WW2END1_3", - "CLK_HROW_WW2END1_4", - "CLK_HROW_WW2END1_5", - "CLK_HROW_WW2END1_6", - "CLK_HROW_WW2END1_7", - "CLK_HROW_WW2END2_0", - "CLK_HROW_WW2END2_1", - "CLK_HROW_WW2END2_2", - "CLK_HROW_WW2END2_3", - "CLK_HROW_WW2END2_4", - "CLK_HROW_WW2END2_5", - "CLK_HROW_WW2END2_6", - "CLK_HROW_WW2END2_7", - "CLK_HROW_WW2END3_0", - "CLK_HROW_WW2END3_1", - "CLK_HROW_WW2END3_2", - "CLK_HROW_WW2END3_3", - "CLK_HROW_WW2END3_4", - "CLK_HROW_WW2END3_5", - "CLK_HROW_WW2END3_6", - "CLK_HROW_WW2END3_7", - "CLK_HROW_WW4A0_0", - "CLK_HROW_WW4A0_1", - "CLK_HROW_WW4A0_2", - "CLK_HROW_WW4A0_3", - "CLK_HROW_WW4A0_4", - "CLK_HROW_WW4A0_5", - "CLK_HROW_WW4A0_6", - "CLK_HROW_WW4A0_7", - "CLK_HROW_WW4A1_0", - "CLK_HROW_WW4A1_1", - "CLK_HROW_WW4A1_2", - "CLK_HROW_WW4A1_3", - "CLK_HROW_WW4A1_4", - "CLK_HROW_WW4A1_5", - "CLK_HROW_WW4A1_6", - "CLK_HROW_WW4A1_7", - "CLK_HROW_WW4A2_0", - "CLK_HROW_WW4A2_1", - "CLK_HROW_WW4A2_2", - "CLK_HROW_WW4A2_3", - "CLK_HROW_WW4A2_4", - "CLK_HROW_WW4A2_5", - "CLK_HROW_WW4A2_6", - "CLK_HROW_WW4A2_7", - "CLK_HROW_WW4A3_0", - "CLK_HROW_WW4A3_1", - "CLK_HROW_WW4A3_2", - "CLK_HROW_WW4A3_3", - "CLK_HROW_WW4A3_4", - "CLK_HROW_WW4A3_5", - "CLK_HROW_WW4A3_6", - "CLK_HROW_WW4A3_7", - "CLK_HROW_WW4B0_0", - "CLK_HROW_WW4B0_1", - "CLK_HROW_WW4B0_2", - "CLK_HROW_WW4B0_3", - "CLK_HROW_WW4B0_4", - "CLK_HROW_WW4B0_5", - "CLK_HROW_WW4B0_6", - "CLK_HROW_WW4B0_7", - "CLK_HROW_WW4B1_0", - "CLK_HROW_WW4B1_1", - "CLK_HROW_WW4B1_2", - "CLK_HROW_WW4B1_3", - "CLK_HROW_WW4B1_4", - "CLK_HROW_WW4B1_5", - "CLK_HROW_WW4B1_6", - "CLK_HROW_WW4B1_7", - "CLK_HROW_WW4B2_0", - "CLK_HROW_WW4B2_1", - "CLK_HROW_WW4B2_2", - "CLK_HROW_WW4B2_3", - "CLK_HROW_WW4B2_4", - "CLK_HROW_WW4B2_5", - "CLK_HROW_WW4B2_6", - "CLK_HROW_WW4B2_7", - "CLK_HROW_WW4B3_0", - "CLK_HROW_WW4B3_1", - "CLK_HROW_WW4B3_2", - "CLK_HROW_WW4B3_3", - "CLK_HROW_WW4B3_4", - "CLK_HROW_WW4B3_5", - "CLK_HROW_WW4B3_6", - "CLK_HROW_WW4B3_7", - "CLK_HROW_WW4C0_0", - "CLK_HROW_WW4C0_1", - "CLK_HROW_WW4C0_2", - "CLK_HROW_WW4C0_3", - "CLK_HROW_WW4C0_4", - "CLK_HROW_WW4C0_5", - "CLK_HROW_WW4C0_6", - "CLK_HROW_WW4C0_7", - "CLK_HROW_WW4C1_0", - "CLK_HROW_WW4C1_1", - "CLK_HROW_WW4C1_2", - "CLK_HROW_WW4C1_3", - "CLK_HROW_WW4C1_4", - "CLK_HROW_WW4C1_5", - "CLK_HROW_WW4C1_6", - "CLK_HROW_WW4C1_7", - "CLK_HROW_WW4C2_0", - "CLK_HROW_WW4C2_1", - "CLK_HROW_WW4C2_2", - "CLK_HROW_WW4C2_3", - "CLK_HROW_WW4C2_4", - "CLK_HROW_WW4C2_5", - "CLK_HROW_WW4C2_6", - "CLK_HROW_WW4C2_7", - "CLK_HROW_WW4C3_0", - "CLK_HROW_WW4C3_1", - "CLK_HROW_WW4C3_2", - "CLK_HROW_WW4C3_3", - "CLK_HROW_WW4C3_4", - "CLK_HROW_WW4C3_5", - "CLK_HROW_WW4C3_6", - "CLK_HROW_WW4C3_7", - "CLK_HROW_WW4END0_0", - "CLK_HROW_WW4END0_1", - "CLK_HROW_WW4END0_2", - "CLK_HROW_WW4END0_3", - "CLK_HROW_WW4END0_4", - "CLK_HROW_WW4END0_5", - "CLK_HROW_WW4END0_6", - "CLK_HROW_WW4END0_7", - "CLK_HROW_WW4END1_0", - "CLK_HROW_WW4END1_1", - "CLK_HROW_WW4END1_2", - "CLK_HROW_WW4END1_3", - "CLK_HROW_WW4END1_4", - "CLK_HROW_WW4END1_5", - "CLK_HROW_WW4END1_6", - "CLK_HROW_WW4END1_7", - "CLK_HROW_WW4END2_0", - "CLK_HROW_WW4END2_1", - "CLK_HROW_WW4END2_2", - "CLK_HROW_WW4END2_3", - "CLK_HROW_WW4END2_4", - "CLK_HROW_WW4END2_5", - "CLK_HROW_WW4END2_6", - "CLK_HROW_WW4END2_7", - "CLK_HROW_WW4END3_0", - "CLK_HROW_WW4END3_1", - "CLK_HROW_WW4END3_2", - "CLK_HROW_WW4END3_3", - "CLK_HROW_WW4END3_4", - "CLK_HROW_WW4END3_5", - "CLK_HROW_WW4END3_6", - "CLK_HROW_WW4END3_7" - ] + "wires": { + "CLK_HROW_BLOCK_OUTS_B0_0": null, + "CLK_HROW_BLOCK_OUTS_B0_1": null, + "CLK_HROW_BLOCK_OUTS_B0_2": null, + "CLK_HROW_BLOCK_OUTS_B0_3": null, + "CLK_HROW_BLOCK_OUTS_B0_4": null, + "CLK_HROW_BLOCK_OUTS_B0_5": null, + "CLK_HROW_BLOCK_OUTS_B0_6": null, + "CLK_HROW_BLOCK_OUTS_B0_7": null, + "CLK_HROW_BLOCK_OUTS_B1_0": null, + "CLK_HROW_BLOCK_OUTS_B1_1": null, + "CLK_HROW_BLOCK_OUTS_B1_2": null, + "CLK_HROW_BLOCK_OUTS_B1_3": null, + "CLK_HROW_BLOCK_OUTS_B1_4": null, + "CLK_HROW_BLOCK_OUTS_B1_5": null, + "CLK_HROW_BLOCK_OUTS_B1_6": null, + "CLK_HROW_BLOCK_OUTS_B1_7": null, + "CLK_HROW_BLOCK_OUTS_B2_0": null, + "CLK_HROW_BLOCK_OUTS_B2_1": null, + "CLK_HROW_BLOCK_OUTS_B2_2": null, + "CLK_HROW_BLOCK_OUTS_B2_3": null, + "CLK_HROW_BLOCK_OUTS_B2_4": null, + "CLK_HROW_BLOCK_OUTS_B2_5": null, + "CLK_HROW_BLOCK_OUTS_B2_6": null, + "CLK_HROW_BLOCK_OUTS_B2_7": null, + "CLK_HROW_BLOCK_OUTS_B3_0": null, + "CLK_HROW_BLOCK_OUTS_B3_1": null, + "CLK_HROW_BLOCK_OUTS_B3_2": null, + "CLK_HROW_BLOCK_OUTS_B3_3": null, + "CLK_HROW_BLOCK_OUTS_B3_4": null, + "CLK_HROW_BLOCK_OUTS_B3_5": null, + "CLK_HROW_BLOCK_OUTS_B3_6": null, + "CLK_HROW_BLOCK_OUTS_B3_7": null, + "CLK_HROW_BUFHCE_CE_L0": null, + "CLK_HROW_BUFHCE_CE_L1": null, + "CLK_HROW_BUFHCE_CE_L10": null, + "CLK_HROW_BUFHCE_CE_L11": null, + "CLK_HROW_BUFHCE_CE_L2": null, + "CLK_HROW_BUFHCE_CE_L3": null, + "CLK_HROW_BUFHCE_CE_L4": null, + "CLK_HROW_BUFHCE_CE_L5": null, + "CLK_HROW_BUFHCE_CE_L6": null, + "CLK_HROW_BUFHCE_CE_L7": null, + "CLK_HROW_BUFHCE_CE_L8": null, + "CLK_HROW_BUFHCE_CE_L9": null, + "CLK_HROW_BUFHCE_CE_R0": null, + "CLK_HROW_BUFHCE_CE_R1": null, + "CLK_HROW_BUFHCE_CE_R10": null, + "CLK_HROW_BUFHCE_CE_R11": null, + "CLK_HROW_BUFHCE_CE_R2": null, + "CLK_HROW_BUFHCE_CE_R3": null, + "CLK_HROW_BUFHCE_CE_R4": null, + "CLK_HROW_BUFHCE_CE_R5": null, + "CLK_HROW_BUFHCE_CE_R6": null, + "CLK_HROW_BUFHCE_CE_R7": null, + "CLK_HROW_BUFHCE_CE_R8": null, + "CLK_HROW_BUFHCE_CE_R9": null, + "CLK_HROW_BYP0_0": null, + "CLK_HROW_BYP0_1": null, + "CLK_HROW_BYP0_2": null, + "CLK_HROW_BYP0_3": null, + "CLK_HROW_BYP0_4": null, + "CLK_HROW_BYP0_5": null, + "CLK_HROW_BYP0_6": null, + "CLK_HROW_BYP0_7": null, + "CLK_HROW_BYP1_0": null, + "CLK_HROW_BYP1_1": null, + "CLK_HROW_BYP1_2": null, + "CLK_HROW_BYP1_3": null, + "CLK_HROW_BYP1_4": null, + "CLK_HROW_BYP1_5": null, + "CLK_HROW_BYP1_6": null, + "CLK_HROW_BYP1_7": null, + "CLK_HROW_BYP2_0": null, + "CLK_HROW_BYP2_1": null, + "CLK_HROW_BYP2_2": null, + "CLK_HROW_BYP2_3": null, + "CLK_HROW_BYP2_4": null, + "CLK_HROW_BYP2_5": null, + "CLK_HROW_BYP2_6": null, + "CLK_HROW_BYP2_7": null, + "CLK_HROW_BYP3_0": null, + "CLK_HROW_BYP3_1": null, + "CLK_HROW_BYP3_2": null, + "CLK_HROW_BYP3_3": null, + "CLK_HROW_BYP3_4": null, + "CLK_HROW_BYP3_5": null, + "CLK_HROW_BYP3_6": null, + "CLK_HROW_BYP3_7": null, + "CLK_HROW_BYP4_0": null, + "CLK_HROW_BYP4_1": null, + "CLK_HROW_BYP4_2": null, + "CLK_HROW_BYP4_3": null, + "CLK_HROW_BYP4_4": null, + "CLK_HROW_BYP4_5": null, + "CLK_HROW_BYP4_6": null, + "CLK_HROW_BYP4_7": null, + "CLK_HROW_BYP5_0": null, + "CLK_HROW_BYP5_1": null, + "CLK_HROW_BYP5_2": null, + "CLK_HROW_BYP5_3": null, + "CLK_HROW_BYP5_4": null, + "CLK_HROW_BYP5_5": null, + "CLK_HROW_BYP5_6": null, + "CLK_HROW_BYP5_7": null, + "CLK_HROW_BYP6_0": null, + "CLK_HROW_BYP6_1": null, + "CLK_HROW_BYP6_2": null, + "CLK_HROW_BYP6_3": null, + "CLK_HROW_BYP6_4": null, + "CLK_HROW_BYP6_5": null, + "CLK_HROW_BYP6_6": null, + "CLK_HROW_BYP6_7": null, + "CLK_HROW_BYP7_0": null, + "CLK_HROW_BYP7_1": null, + "CLK_HROW_BYP7_2": null, + "CLK_HROW_BYP7_3": null, + "CLK_HROW_BYP7_4": null, + "CLK_HROW_BYP7_5": null, + "CLK_HROW_BYP7_6": null, + "CLK_HROW_BYP7_7": null, + "CLK_HROW_CE_INT_BOT0": null, + "CLK_HROW_CE_INT_BOT1": null, + "CLK_HROW_CE_INT_BOT10": null, + "CLK_HROW_CE_INT_BOT11": null, + "CLK_HROW_CE_INT_BOT2": null, + "CLK_HROW_CE_INT_BOT3": null, + "CLK_HROW_CE_INT_BOT4": null, + "CLK_HROW_CE_INT_BOT5": null, + "CLK_HROW_CE_INT_BOT6": null, + "CLK_HROW_CE_INT_BOT7": null, + "CLK_HROW_CE_INT_BOT8": null, + "CLK_HROW_CE_INT_BOT9": null, + "CLK_HROW_CE_INT_TOP0": null, + "CLK_HROW_CE_INT_TOP1": null, + "CLK_HROW_CE_INT_TOP10": null, + "CLK_HROW_CE_INT_TOP11": null, + "CLK_HROW_CE_INT_TOP2": null, + "CLK_HROW_CE_INT_TOP3": null, + "CLK_HROW_CE_INT_TOP4": null, + "CLK_HROW_CE_INT_TOP5": null, + "CLK_HROW_CE_INT_TOP6": null, + "CLK_HROW_CE_INT_TOP7": null, + "CLK_HROW_CE_INT_TOP8": null, + "CLK_HROW_CE_INT_TOP9": null, + "CLK_HROW_CK_BUFHCLK_L0": null, + "CLK_HROW_CK_BUFHCLK_L1": null, + "CLK_HROW_CK_BUFHCLK_L10": null, + "CLK_HROW_CK_BUFHCLK_L11": null, + "CLK_HROW_CK_BUFHCLK_L2": null, + "CLK_HROW_CK_BUFHCLK_L3": null, + "CLK_HROW_CK_BUFHCLK_L4": null, + "CLK_HROW_CK_BUFHCLK_L5": null, + "CLK_HROW_CK_BUFHCLK_L6": null, + "CLK_HROW_CK_BUFHCLK_L7": null, + "CLK_HROW_CK_BUFHCLK_L8": null, + "CLK_HROW_CK_BUFHCLK_L9": null, + "CLK_HROW_CK_BUFHCLK_R0": null, + "CLK_HROW_CK_BUFHCLK_R1": null, + "CLK_HROW_CK_BUFHCLK_R10": null, + "CLK_HROW_CK_BUFHCLK_R11": null, + "CLK_HROW_CK_BUFHCLK_R2": null, + "CLK_HROW_CK_BUFHCLK_R3": null, + "CLK_HROW_CK_BUFHCLK_R4": null, + "CLK_HROW_CK_BUFHCLK_R5": null, + "CLK_HROW_CK_BUFHCLK_R6": null, + "CLK_HROW_CK_BUFHCLK_R7": null, + "CLK_HROW_CK_BUFHCLK_R8": null, + "CLK_HROW_CK_BUFHCLK_R9": null, + "CLK_HROW_CK_BUFRCLK_L0": null, + "CLK_HROW_CK_BUFRCLK_L1": null, + "CLK_HROW_CK_BUFRCLK_L2": null, + "CLK_HROW_CK_BUFRCLK_L3": null, + "CLK_HROW_CK_BUFRCLK_R0": null, + "CLK_HROW_CK_BUFRCLK_R1": null, + "CLK_HROW_CK_BUFRCLK_R2": null, + "CLK_HROW_CK_BUFRCLK_R3": null, + "CLK_HROW_CK_GCLK_IN_TEST0": null, + "CLK_HROW_CK_GCLK_IN_TEST1": null, + "CLK_HROW_CK_GCLK_IN_TEST10": null, + "CLK_HROW_CK_GCLK_IN_TEST11": null, + "CLK_HROW_CK_GCLK_IN_TEST12": null, + "CLK_HROW_CK_GCLK_IN_TEST13": null, + "CLK_HROW_CK_GCLK_IN_TEST14": null, + "CLK_HROW_CK_GCLK_IN_TEST15": null, + "CLK_HROW_CK_GCLK_IN_TEST16": null, + "CLK_HROW_CK_GCLK_IN_TEST17": null, + "CLK_HROW_CK_GCLK_IN_TEST18": null, + "CLK_HROW_CK_GCLK_IN_TEST19": null, + "CLK_HROW_CK_GCLK_IN_TEST2": null, + "CLK_HROW_CK_GCLK_IN_TEST20": null, + "CLK_HROW_CK_GCLK_IN_TEST21": null, + "CLK_HROW_CK_GCLK_IN_TEST22": null, + "CLK_HROW_CK_GCLK_IN_TEST23": null, + "CLK_HROW_CK_GCLK_IN_TEST24": null, + "CLK_HROW_CK_GCLK_IN_TEST25": null, + "CLK_HROW_CK_GCLK_IN_TEST26": null, + "CLK_HROW_CK_GCLK_IN_TEST27": null, + "CLK_HROW_CK_GCLK_IN_TEST28": null, + "CLK_HROW_CK_GCLK_IN_TEST29": null, + "CLK_HROW_CK_GCLK_IN_TEST3": null, + "CLK_HROW_CK_GCLK_IN_TEST30": null, + "CLK_HROW_CK_GCLK_IN_TEST31": null, + "CLK_HROW_CK_GCLK_IN_TEST4": null, + "CLK_HROW_CK_GCLK_IN_TEST5": null, + "CLK_HROW_CK_GCLK_IN_TEST6": null, + "CLK_HROW_CK_GCLK_IN_TEST7": null, + "CLK_HROW_CK_GCLK_IN_TEST8": null, + "CLK_HROW_CK_GCLK_IN_TEST9": null, + "CLK_HROW_CK_GCLK_OUT_TEST0": null, + "CLK_HROW_CK_GCLK_OUT_TEST1": null, + "CLK_HROW_CK_GCLK_OUT_TEST10": null, + "CLK_HROW_CK_GCLK_OUT_TEST11": null, + "CLK_HROW_CK_GCLK_OUT_TEST12": null, + "CLK_HROW_CK_GCLK_OUT_TEST13": null, + "CLK_HROW_CK_GCLK_OUT_TEST14": null, + "CLK_HROW_CK_GCLK_OUT_TEST15": null, + "CLK_HROW_CK_GCLK_OUT_TEST16": null, + "CLK_HROW_CK_GCLK_OUT_TEST17": null, + "CLK_HROW_CK_GCLK_OUT_TEST18": null, + "CLK_HROW_CK_GCLK_OUT_TEST19": null, + "CLK_HROW_CK_GCLK_OUT_TEST2": null, + "CLK_HROW_CK_GCLK_OUT_TEST20": null, + "CLK_HROW_CK_GCLK_OUT_TEST21": null, + "CLK_HROW_CK_GCLK_OUT_TEST22": null, + "CLK_HROW_CK_GCLK_OUT_TEST23": null, + "CLK_HROW_CK_GCLK_OUT_TEST24": null, + "CLK_HROW_CK_GCLK_OUT_TEST25": null, + "CLK_HROW_CK_GCLK_OUT_TEST26": null, + "CLK_HROW_CK_GCLK_OUT_TEST27": null, + "CLK_HROW_CK_GCLK_OUT_TEST28": null, + "CLK_HROW_CK_GCLK_OUT_TEST29": null, + "CLK_HROW_CK_GCLK_OUT_TEST3": null, + "CLK_HROW_CK_GCLK_OUT_TEST30": null, + "CLK_HROW_CK_GCLK_OUT_TEST31": null, + "CLK_HROW_CK_GCLK_OUT_TEST4": null, + "CLK_HROW_CK_GCLK_OUT_TEST5": null, + "CLK_HROW_CK_GCLK_OUT_TEST6": null, + "CLK_HROW_CK_GCLK_OUT_TEST7": null, + "CLK_HROW_CK_GCLK_OUT_TEST8": null, + "CLK_HROW_CK_GCLK_OUT_TEST9": null, + "CLK_HROW_CK_GCLK_TEST0": null, + "CLK_HROW_CK_GCLK_TEST1": null, + "CLK_HROW_CK_GCLK_TEST10": null, + "CLK_HROW_CK_GCLK_TEST11": null, + "CLK_HROW_CK_GCLK_TEST12": null, + "CLK_HROW_CK_GCLK_TEST13": null, + "CLK_HROW_CK_GCLK_TEST14": null, + "CLK_HROW_CK_GCLK_TEST15": null, + "CLK_HROW_CK_GCLK_TEST16": null, + "CLK_HROW_CK_GCLK_TEST17": null, + "CLK_HROW_CK_GCLK_TEST18": null, + "CLK_HROW_CK_GCLK_TEST19": null, + "CLK_HROW_CK_GCLK_TEST2": null, + "CLK_HROW_CK_GCLK_TEST20": null, + "CLK_HROW_CK_GCLK_TEST21": null, + "CLK_HROW_CK_GCLK_TEST22": null, + "CLK_HROW_CK_GCLK_TEST23": null, + "CLK_HROW_CK_GCLK_TEST24": null, + "CLK_HROW_CK_GCLK_TEST25": null, + "CLK_HROW_CK_GCLK_TEST26": null, + "CLK_HROW_CK_GCLK_TEST27": null, + "CLK_HROW_CK_GCLK_TEST28": null, + "CLK_HROW_CK_GCLK_TEST29": null, + "CLK_HROW_CK_GCLK_TEST3": null, + "CLK_HROW_CK_GCLK_TEST30": null, + "CLK_HROW_CK_GCLK_TEST31": null, + "CLK_HROW_CK_GCLK_TEST4": null, + "CLK_HROW_CK_GCLK_TEST5": null, + "CLK_HROW_CK_GCLK_TEST6": null, + "CLK_HROW_CK_GCLK_TEST7": null, + "CLK_HROW_CK_GCLK_TEST8": null, + "CLK_HROW_CK_GCLK_TEST9": null, + "CLK_HROW_CK_GCLK_TEST_IN0": null, + "CLK_HROW_CK_GCLK_TEST_IN1": null, + "CLK_HROW_CK_GCLK_TEST_IN10": null, + "CLK_HROW_CK_GCLK_TEST_IN11": null, + "CLK_HROW_CK_GCLK_TEST_IN12": null, + "CLK_HROW_CK_GCLK_TEST_IN13": null, + "CLK_HROW_CK_GCLK_TEST_IN14": null, + "CLK_HROW_CK_GCLK_TEST_IN15": null, + "CLK_HROW_CK_GCLK_TEST_IN16": null, + "CLK_HROW_CK_GCLK_TEST_IN17": null, + "CLK_HROW_CK_GCLK_TEST_IN18": null, + "CLK_HROW_CK_GCLK_TEST_IN19": null, + "CLK_HROW_CK_GCLK_TEST_IN2": null, + "CLK_HROW_CK_GCLK_TEST_IN20": null, + "CLK_HROW_CK_GCLK_TEST_IN21": null, + "CLK_HROW_CK_GCLK_TEST_IN22": null, + "CLK_HROW_CK_GCLK_TEST_IN23": null, + "CLK_HROW_CK_GCLK_TEST_IN24": null, + "CLK_HROW_CK_GCLK_TEST_IN25": null, + "CLK_HROW_CK_GCLK_TEST_IN26": null, + "CLK_HROW_CK_GCLK_TEST_IN27": null, + "CLK_HROW_CK_GCLK_TEST_IN28": null, + "CLK_HROW_CK_GCLK_TEST_IN29": null, + "CLK_HROW_CK_GCLK_TEST_IN3": null, + "CLK_HROW_CK_GCLK_TEST_IN30": null, + "CLK_HROW_CK_GCLK_TEST_IN31": null, + "CLK_HROW_CK_GCLK_TEST_IN4": null, + "CLK_HROW_CK_GCLK_TEST_IN5": null, + "CLK_HROW_CK_GCLK_TEST_IN6": null, + "CLK_HROW_CK_GCLK_TEST_IN7": null, + "CLK_HROW_CK_GCLK_TEST_IN8": null, + "CLK_HROW_CK_GCLK_TEST_IN9": null, + "CLK_HROW_CK_GCLK_TEST_OUT0": null, + "CLK_HROW_CK_GCLK_TEST_OUT1": null, + "CLK_HROW_CK_GCLK_TEST_OUT10": null, + "CLK_HROW_CK_GCLK_TEST_OUT11": null, + "CLK_HROW_CK_GCLK_TEST_OUT12": null, + "CLK_HROW_CK_GCLK_TEST_OUT13": null, + "CLK_HROW_CK_GCLK_TEST_OUT14": null, + "CLK_HROW_CK_GCLK_TEST_OUT15": null, + "CLK_HROW_CK_GCLK_TEST_OUT16": null, + "CLK_HROW_CK_GCLK_TEST_OUT17": null, + "CLK_HROW_CK_GCLK_TEST_OUT18": null, + "CLK_HROW_CK_GCLK_TEST_OUT19": null, + "CLK_HROW_CK_GCLK_TEST_OUT2": null, + "CLK_HROW_CK_GCLK_TEST_OUT20": null, + "CLK_HROW_CK_GCLK_TEST_OUT21": null, + "CLK_HROW_CK_GCLK_TEST_OUT22": null, + "CLK_HROW_CK_GCLK_TEST_OUT23": null, + "CLK_HROW_CK_GCLK_TEST_OUT24": null, + "CLK_HROW_CK_GCLK_TEST_OUT25": null, + "CLK_HROW_CK_GCLK_TEST_OUT26": null, + "CLK_HROW_CK_GCLK_TEST_OUT27": null, + "CLK_HROW_CK_GCLK_TEST_OUT28": null, + "CLK_HROW_CK_GCLK_TEST_OUT29": null, + "CLK_HROW_CK_GCLK_TEST_OUT3": null, + "CLK_HROW_CK_GCLK_TEST_OUT30": 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"CLK_HROW_CK_HCLK_OUT_R6": null, + "CLK_HROW_CK_HCLK_OUT_R7": null, + "CLK_HROW_CK_HCLK_OUT_R8": null, + "CLK_HROW_CK_HCLK_OUT_R9": null, + "CLK_HROW_CK_INT_0_0": null, + "CLK_HROW_CK_INT_0_1": null, + "CLK_HROW_CK_INT_1_0": null, + "CLK_HROW_CK_INT_1_1": null, + "CLK_HROW_CK_IN_L0": null, + "CLK_HROW_CK_IN_L1": null, + "CLK_HROW_CK_IN_L10": null, + "CLK_HROW_CK_IN_L11": null, + "CLK_HROW_CK_IN_L12": null, + "CLK_HROW_CK_IN_L13": null, + "CLK_HROW_CK_IN_L2": null, + "CLK_HROW_CK_IN_L3": null, + "CLK_HROW_CK_IN_L4": null, + "CLK_HROW_CK_IN_L5": null, + "CLK_HROW_CK_IN_L6": null, + "CLK_HROW_CK_IN_L7": null, + "CLK_HROW_CK_IN_L8": null, + "CLK_HROW_CK_IN_L9": null, + "CLK_HROW_CK_IN_L_IN_TEST": null, + "CLK_HROW_CK_IN_L_OUT_TEST": null, + "CLK_HROW_CK_IN_L_TEST_IN": null, + "CLK_HROW_CK_IN_L_TEST_OUT": null, + "CLK_HROW_CK_IN_R0": null, + "CLK_HROW_CK_IN_R1": null, + "CLK_HROW_CK_IN_R10": null, + "CLK_HROW_CK_IN_R11": null, + "CLK_HROW_CK_IN_R12": null, + "CLK_HROW_CK_IN_R13": null, + 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"CLK_HROW_R_CK_GCLK31": null, + "CLK_HROW_R_CK_GCLK4": null, + "CLK_HROW_R_CK_GCLK5": null, + "CLK_HROW_R_CK_GCLK6": null, + "CLK_HROW_R_CK_GCLK7": null, + "CLK_HROW_R_CK_GCLK8": null, + "CLK_HROW_R_CK_GCLK9": null, + "CLK_HROW_SE2A0_0": null, + "CLK_HROW_SE2A0_1": null, + "CLK_HROW_SE2A0_2": null, + "CLK_HROW_SE2A0_3": null, + "CLK_HROW_SE2A0_4": null, + "CLK_HROW_SE2A0_5": null, + "CLK_HROW_SE2A0_6": null, + "CLK_HROW_SE2A0_7": null, + "CLK_HROW_SE2A1_0": null, + "CLK_HROW_SE2A1_1": null, + "CLK_HROW_SE2A1_2": null, + "CLK_HROW_SE2A1_3": null, + "CLK_HROW_SE2A1_4": null, + "CLK_HROW_SE2A1_5": null, + "CLK_HROW_SE2A1_6": null, + "CLK_HROW_SE2A1_7": null, + "CLK_HROW_SE2A2_0": null, + "CLK_HROW_SE2A2_1": null, + "CLK_HROW_SE2A2_2": null, + "CLK_HROW_SE2A2_3": null, + "CLK_HROW_SE2A2_4": null, + "CLK_HROW_SE2A2_5": null, + "CLK_HROW_SE2A2_6": null, + "CLK_HROW_SE2A2_7": null, + "CLK_HROW_SE2A3_0": null, + "CLK_HROW_SE2A3_1": null, + "CLK_HROW_SE2A3_2": null, + "CLK_HROW_SE2A3_3": null, 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"CLK_HROW_SW2A0_0": null, + "CLK_HROW_SW2A0_1": null, + "CLK_HROW_SW2A0_2": null, + "CLK_HROW_SW2A0_3": null, + "CLK_HROW_SW2A0_4": null, + "CLK_HROW_SW2A0_5": null, + "CLK_HROW_SW2A0_6": null, + "CLK_HROW_SW2A0_7": null, + "CLK_HROW_SW2A1_0": null, + "CLK_HROW_SW2A1_1": null, + "CLK_HROW_SW2A1_2": null, + "CLK_HROW_SW2A1_3": null, + "CLK_HROW_SW2A1_4": null, + "CLK_HROW_SW2A1_5": null, + "CLK_HROW_SW2A1_6": null, + "CLK_HROW_SW2A1_7": null, + "CLK_HROW_SW2A2_0": null, + "CLK_HROW_SW2A2_1": null, + "CLK_HROW_SW2A2_2": null, + "CLK_HROW_SW2A2_3": null, + "CLK_HROW_SW2A2_4": null, + "CLK_HROW_SW2A2_5": null, + "CLK_HROW_SW2A2_6": null, + "CLK_HROW_SW2A2_7": null, + "CLK_HROW_SW2A3_0": null, + "CLK_HROW_SW2A3_1": null, + "CLK_HROW_SW2A3_2": null, + "CLK_HROW_SW2A3_3": null, + "CLK_HROW_SW2A3_4": null, + "CLK_HROW_SW2A3_5": null, + "CLK_HROW_SW2A3_6": null, + "CLK_HROW_SW2A3_7": null, + "CLK_HROW_SW4A0_0": null, + "CLK_HROW_SW4A0_1": null, + "CLK_HROW_SW4A0_2": null, + "CLK_HROW_SW4A0_3": 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"CLK_HROW_TOP_R_CK_BUFG_CASCIN7": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN8": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN9": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO0": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO1": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO10": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO11": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO12": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO13": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO14": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO15": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO16": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO17": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO18": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO19": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO2": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO20": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO21": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO22": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO23": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO24": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO25": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO26": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO27": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO28": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO29": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO3": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO30": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO31": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO4": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO5": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO6": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO7": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO8": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO9": null, + "CLK_HROW_WL1END0_0": null, + "CLK_HROW_WL1END0_1": null, + "CLK_HROW_WL1END0_2": null, + "CLK_HROW_WL1END0_3": null, + "CLK_HROW_WL1END0_4": null, + "CLK_HROW_WL1END0_5": null, + "CLK_HROW_WL1END0_6": null, + "CLK_HROW_WL1END0_7": null, + "CLK_HROW_WL1END1_0": null, + "CLK_HROW_WL1END1_1": null, + "CLK_HROW_WL1END1_2": null, + "CLK_HROW_WL1END1_3": null, + "CLK_HROW_WL1END1_4": null, + "CLK_HROW_WL1END1_5": null, + "CLK_HROW_WL1END1_6": null, + "CLK_HROW_WL1END1_7": null, + "CLK_HROW_WL1END2_0": null, + "CLK_HROW_WL1END2_1": null, + "CLK_HROW_WL1END2_2": null, + "CLK_HROW_WL1END2_3": null, + "CLK_HROW_WL1END2_4": null, + "CLK_HROW_WL1END2_5": null, + "CLK_HROW_WL1END2_6": null, + "CLK_HROW_WL1END2_7": null, + "CLK_HROW_WL1END3_0": null, + "CLK_HROW_WL1END3_1": null, + "CLK_HROW_WL1END3_2": null, + "CLK_HROW_WL1END3_3": null, + "CLK_HROW_WL1END3_4": null, + "CLK_HROW_WL1END3_5": null, + "CLK_HROW_WL1END3_6": null, + "CLK_HROW_WL1END3_7": null, + "CLK_HROW_WR1END0_0": null, + "CLK_HROW_WR1END0_1": null, + "CLK_HROW_WR1END0_2": null, + "CLK_HROW_WR1END0_3": null, + "CLK_HROW_WR1END0_4": null, + "CLK_HROW_WR1END0_5": null, + "CLK_HROW_WR1END0_6": null, + "CLK_HROW_WR1END0_7": null, + "CLK_HROW_WR1END1_0": null, + "CLK_HROW_WR1END1_1": null, + "CLK_HROW_WR1END1_2": null, + "CLK_HROW_WR1END1_3": null, + "CLK_HROW_WR1END1_4": null, + "CLK_HROW_WR1END1_5": null, + "CLK_HROW_WR1END1_6": null, + "CLK_HROW_WR1END1_7": null, + "CLK_HROW_WR1END2_0": null, + "CLK_HROW_WR1END2_1": null, + "CLK_HROW_WR1END2_2": null, + "CLK_HROW_WR1END2_3": null, + "CLK_HROW_WR1END2_4": null, + "CLK_HROW_WR1END2_5": null, + "CLK_HROW_WR1END2_6": null, + "CLK_HROW_WR1END2_7": null, + "CLK_HROW_WR1END3_0": null, + "CLK_HROW_WR1END3_1": null, + "CLK_HROW_WR1END3_2": null, + "CLK_HROW_WR1END3_3": null, + "CLK_HROW_WR1END3_4": null, + "CLK_HROW_WR1END3_5": null, + "CLK_HROW_WR1END3_6": null, + "CLK_HROW_WR1END3_7": null, + "CLK_HROW_WW2A0_0": null, + "CLK_HROW_WW2A0_1": null, + "CLK_HROW_WW2A0_2": null, + "CLK_HROW_WW2A0_3": null, + "CLK_HROW_WW2A0_4": null, + "CLK_HROW_WW2A0_5": null, + "CLK_HROW_WW2A0_6": null, + "CLK_HROW_WW2A0_7": null, + "CLK_HROW_WW2A1_0": null, + "CLK_HROW_WW2A1_1": null, + "CLK_HROW_WW2A1_2": null, + "CLK_HROW_WW2A1_3": null, + "CLK_HROW_WW2A1_4": null, + "CLK_HROW_WW2A1_5": null, + "CLK_HROW_WW2A1_6": null, + "CLK_HROW_WW2A1_7": null, + "CLK_HROW_WW2A2_0": null, + "CLK_HROW_WW2A2_1": null, + "CLK_HROW_WW2A2_2": null, + "CLK_HROW_WW2A2_3": null, + "CLK_HROW_WW2A2_4": null, + "CLK_HROW_WW2A2_5": null, + "CLK_HROW_WW2A2_6": null, + "CLK_HROW_WW2A2_7": null, + "CLK_HROW_WW2A3_0": null, + "CLK_HROW_WW2A3_1": null, + "CLK_HROW_WW2A3_2": null, + "CLK_HROW_WW2A3_3": null, + "CLK_HROW_WW2A3_4": null, + "CLK_HROW_WW2A3_5": null, + "CLK_HROW_WW2A3_6": null, + "CLK_HROW_WW2A3_7": null, + "CLK_HROW_WW2END0_0": null, + "CLK_HROW_WW2END0_1": null, + "CLK_HROW_WW2END0_2": null, + "CLK_HROW_WW2END0_3": null, + "CLK_HROW_WW2END0_4": null, + "CLK_HROW_WW2END0_5": null, + "CLK_HROW_WW2END0_6": null, + "CLK_HROW_WW2END0_7": null, + "CLK_HROW_WW2END1_0": null, + "CLK_HROW_WW2END1_1": null, + "CLK_HROW_WW2END1_2": null, + "CLK_HROW_WW2END1_3": null, + "CLK_HROW_WW2END1_4": null, + "CLK_HROW_WW2END1_5": null, + "CLK_HROW_WW2END1_6": null, + "CLK_HROW_WW2END1_7": null, + "CLK_HROW_WW2END2_0": null, + "CLK_HROW_WW2END2_1": null, + "CLK_HROW_WW2END2_2": null, + "CLK_HROW_WW2END2_3": null, + "CLK_HROW_WW2END2_4": null, + "CLK_HROW_WW2END2_5": null, + "CLK_HROW_WW2END2_6": null, + "CLK_HROW_WW2END2_7": null, + "CLK_HROW_WW2END3_0": null, + "CLK_HROW_WW2END3_1": null, + "CLK_HROW_WW2END3_2": null, + "CLK_HROW_WW2END3_3": null, + "CLK_HROW_WW2END3_4": null, + "CLK_HROW_WW2END3_5": null, + "CLK_HROW_WW2END3_6": null, + "CLK_HROW_WW2END3_7": null, + "CLK_HROW_WW4A0_0": null, + "CLK_HROW_WW4A0_1": null, + "CLK_HROW_WW4A0_2": null, + "CLK_HROW_WW4A0_3": null, + "CLK_HROW_WW4A0_4": null, + "CLK_HROW_WW4A0_5": null, + "CLK_HROW_WW4A0_6": null, + "CLK_HROW_WW4A0_7": null, + "CLK_HROW_WW4A1_0": null, + "CLK_HROW_WW4A1_1": null, + "CLK_HROW_WW4A1_2": null, + "CLK_HROW_WW4A1_3": null, + "CLK_HROW_WW4A1_4": null, + "CLK_HROW_WW4A1_5": null, + "CLK_HROW_WW4A1_6": null, + "CLK_HROW_WW4A1_7": null, + "CLK_HROW_WW4A2_0": null, + "CLK_HROW_WW4A2_1": null, + "CLK_HROW_WW4A2_2": null, + "CLK_HROW_WW4A2_3": null, + "CLK_HROW_WW4A2_4": null, + "CLK_HROW_WW4A2_5": null, + "CLK_HROW_WW4A2_6": null, + "CLK_HROW_WW4A2_7": null, + "CLK_HROW_WW4A3_0": null, + "CLK_HROW_WW4A3_1": null, + "CLK_HROW_WW4A3_2": null, + "CLK_HROW_WW4A3_3": null, + "CLK_HROW_WW4A3_4": null, + "CLK_HROW_WW4A3_5": null, + "CLK_HROW_WW4A3_6": null, + "CLK_HROW_WW4A3_7": null, + "CLK_HROW_WW4B0_0": null, + "CLK_HROW_WW4B0_1": null, + "CLK_HROW_WW4B0_2": null, + "CLK_HROW_WW4B0_3": null, + "CLK_HROW_WW4B0_4": null, + "CLK_HROW_WW4B0_5": null, + "CLK_HROW_WW4B0_6": null, + "CLK_HROW_WW4B0_7": null, + "CLK_HROW_WW4B1_0": null, + "CLK_HROW_WW4B1_1": null, + "CLK_HROW_WW4B1_2": null, + "CLK_HROW_WW4B1_3": null, + "CLK_HROW_WW4B1_4": null, + "CLK_HROW_WW4B1_5": null, + "CLK_HROW_WW4B1_6": null, + "CLK_HROW_WW4B1_7": null, + "CLK_HROW_WW4B2_0": null, + "CLK_HROW_WW4B2_1": null, + "CLK_HROW_WW4B2_2": null, + "CLK_HROW_WW4B2_3": null, + "CLK_HROW_WW4B2_4": null, + "CLK_HROW_WW4B2_5": null, + "CLK_HROW_WW4B2_6": null, + "CLK_HROW_WW4B2_7": null, + "CLK_HROW_WW4B3_0": null, + "CLK_HROW_WW4B3_1": null, + "CLK_HROW_WW4B3_2": null, + "CLK_HROW_WW4B3_3": null, + "CLK_HROW_WW4B3_4": null, + "CLK_HROW_WW4B3_5": null, + "CLK_HROW_WW4B3_6": null, + "CLK_HROW_WW4B3_7": null, + "CLK_HROW_WW4C0_0": null, + "CLK_HROW_WW4C0_1": null, + "CLK_HROW_WW4C0_2": null, + "CLK_HROW_WW4C0_3": null, + "CLK_HROW_WW4C0_4": null, + "CLK_HROW_WW4C0_5": null, + "CLK_HROW_WW4C0_6": null, + "CLK_HROW_WW4C0_7": null, + "CLK_HROW_WW4C1_0": null, + "CLK_HROW_WW4C1_1": null, + "CLK_HROW_WW4C1_2": null, + "CLK_HROW_WW4C1_3": null, + "CLK_HROW_WW4C1_4": null, + "CLK_HROW_WW4C1_5": null, + "CLK_HROW_WW4C1_6": null, + "CLK_HROW_WW4C1_7": null, + "CLK_HROW_WW4C2_0": null, + "CLK_HROW_WW4C2_1": null, + "CLK_HROW_WW4C2_2": null, + "CLK_HROW_WW4C2_3": null, + "CLK_HROW_WW4C2_4": null, + "CLK_HROW_WW4C2_5": null, + "CLK_HROW_WW4C2_6": null, + "CLK_HROW_WW4C2_7": null, + "CLK_HROW_WW4C3_0": null, + "CLK_HROW_WW4C3_1": null, + "CLK_HROW_WW4C3_2": null, + "CLK_HROW_WW4C3_3": null, + "CLK_HROW_WW4C3_4": null, + "CLK_HROW_WW4C3_5": null, + "CLK_HROW_WW4C3_6": null, + "CLK_HROW_WW4C3_7": null, + "CLK_HROW_WW4END0_0": null, + "CLK_HROW_WW4END0_1": null, + "CLK_HROW_WW4END0_2": null, + "CLK_HROW_WW4END0_3": null, + "CLK_HROW_WW4END0_4": null, + "CLK_HROW_WW4END0_5": null, + "CLK_HROW_WW4END0_6": null, + "CLK_HROW_WW4END0_7": null, + "CLK_HROW_WW4END1_0": null, + "CLK_HROW_WW4END1_1": null, + "CLK_HROW_WW4END1_2": null, + "CLK_HROW_WW4END1_3": null, + "CLK_HROW_WW4END1_4": null, + "CLK_HROW_WW4END1_5": null, + "CLK_HROW_WW4END1_6": null, + "CLK_HROW_WW4END1_7": null, + "CLK_HROW_WW4END2_0": null, + "CLK_HROW_WW4END2_1": null, + "CLK_HROW_WW4END2_2": null, + "CLK_HROW_WW4END2_3": null, + "CLK_HROW_WW4END2_4": null, + "CLK_HROW_WW4END2_5": null, + "CLK_HROW_WW4END2_6": null, + "CLK_HROW_WW4END2_7": null, + "CLK_HROW_WW4END3_0": null, + "CLK_HROW_WW4END3_1": null, + "CLK_HROW_WW4END3_2": null, + "CLK_HROW_WW4END3_3": null, + "CLK_HROW_WW4END3_4": null, + "CLK_HROW_WW4END3_5": null, + "CLK_HROW_WW4END3_6": null, + "CLK_HROW_WW4END3_7": null + } } diff --git a/zynq7/tile_type_CLK_MTBF2.json b/zynq7/tile_type_CLK_MTBF2.json index 20b28cb..cf44fa7 100644 --- a/zynq7/tile_type_CLK_MTBF2.json +++ b/zynq7/tile_type_CLK_MTBF2.json @@ -2,364 +2,364 @@ "pips": {}, "sites": [], "tile_type": "CLK_MTBF2", - "wires": [ - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK0", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK10", - "CLK_FEED_CK_GCLK11", - "CLK_FEED_CK_GCLK12", - "CLK_FEED_CK_GCLK13", - "CLK_FEED_CK_GCLK14", - "CLK_FEED_CK_GCLK15", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_CK_GCLK19", - "CLK_FEED_CK_GCLK2", - "CLK_FEED_CK_GCLK20", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK22", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_CK_GCLK30", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_CK_GCLK5", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_CK_GCLK8", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_EE2A0", - "CLK_FEED_EE2A1", - "CLK_FEED_EE2A2", - "CLK_FEED_EE2A3", - "CLK_FEED_EE2BEG0", - "CLK_FEED_EE2BEG1", - "CLK_FEED_EE2BEG2", - "CLK_FEED_EE2BEG3", - "CLK_FEED_EE4A0", - "CLK_FEED_EE4A1", - "CLK_FEED_EE4A2", - "CLK_FEED_EE4A3", - "CLK_FEED_EE4B0", - "CLK_FEED_EE4B1", - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_EE4BEG0", - "CLK_FEED_EE4BEG1", - "CLK_FEED_EE4BEG2", - "CLK_FEED_EE4BEG3", - "CLK_FEED_EE4C0", - "CLK_FEED_EE4C1", - "CLK_FEED_EE4C2", - "CLK_FEED_EE4C3", - "CLK_FEED_EL1BEG0", - "CLK_FEED_EL1BEG1", - "CLK_FEED_EL1BEG2", - "CLK_FEED_EL1BEG3", - "CLK_FEED_ER1BEG0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_ER1BEG2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_LH1", - "CLK_FEED_LH10", - "CLK_FEED_LH11", - "CLK_FEED_LH12", - "CLK_FEED_LH2", - "CLK_FEED_LH3", - "CLK_FEED_LH4", - "CLK_FEED_LH5", - "CLK_FEED_LH6", - "CLK_FEED_LH7", - "CLK_FEED_LH8", - "CLK_FEED_LH9", - "CLK_FEED_MONITOR_N", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A0", - "CLK_FEED_NE2A1", - "CLK_FEED_NE2A2", - "CLK_FEED_NE2A3", - "CLK_FEED_NE4BEG0", - "CLK_FEED_NE4BEG1", - "CLK_FEED_NE4BEG2", - "CLK_FEED_NE4BEG3", - "CLK_FEED_NE4C0", - "CLK_FEED_NE4C1", - "CLK_FEED_NE4C2", - "CLK_FEED_NE4C3", - "CLK_FEED_NW2A0", - "CLK_FEED_NW2A1", - "CLK_FEED_NW2A2", - "CLK_FEED_NW2A3", - "CLK_FEED_NW4A0", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4A2", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4END0", - "CLK_FEED_NW4END1", - "CLK_FEED_NW4END2", - "CLK_FEED_NW4END3", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_SE2A0", - "CLK_FEED_SE2A1", - "CLK_FEED_SE2A2", - "CLK_FEED_SE2A3", - "CLK_FEED_SE4BEG0", - "CLK_FEED_SE4BEG1", - "CLK_FEED_SE4BEG2", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SE4C0", - "CLK_FEED_SE4C1", - "CLK_FEED_SE4C2", - "CLK_FEED_SE4C3", - "CLK_FEED_SW2A0", - "CLK_FEED_SW2A1", - "CLK_FEED_SW2A2", - "CLK_FEED_SW2A3", - "CLK_FEED_SW4A0", - "CLK_FEED_SW4A1", - "CLK_FEED_SW4A2", - "CLK_FEED_SW4A3", - "CLK_FEED_SW4END0", - "CLK_FEED_SW4END1", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_FEED_WL1END0", - "CLK_FEED_WL1END1", - "CLK_FEED_WL1END2", - "CLK_FEED_WL1END3", - "CLK_FEED_WR1END0", - "CLK_FEED_WR1END1", - "CLK_FEED_WR1END2", - "CLK_FEED_WR1END3", - "CLK_FEED_WW2A0", - "CLK_FEED_WW2A1", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2A3", - "CLK_FEED_WW2END0", - "CLK_FEED_WW2END1", - "CLK_FEED_WW2END2", - "CLK_FEED_WW2END3", - "CLK_FEED_WW4A0", - "CLK_FEED_WW4A1", - "CLK_FEED_WW4A2", - "CLK_FEED_WW4A3", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4B1", - "CLK_FEED_WW4B2", - "CLK_FEED_WW4B3", - "CLK_FEED_WW4C0", - "CLK_FEED_WW4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_WW4C3", - "CLK_FEED_WW4END0", - "CLK_FEED_WW4END1", - "CLK_FEED_WW4END2", - "CLK_FEED_WW4END3", - "CLK_MTBF2_CLK", - "CLK_MTBF2_DIN", - "CLK_MTBF2_EN", - "CLK_MTBF2_Q0B", - "CLK_MTBF2_Q1B", - "CLK_MTBF2_Q2B", - "CLK_MTBF2_Q3B", - "CLK_MTBF2_Q4B", - "CLK_MTBF2_Q5B", - "CLK_MTBF2_Q6B", - "CLK_MTBF2_Q7B", - "CLK_MTBF2_RESET", - "CLK_PMV_BYP0_0", - "CLK_PMV_BYP1_0", - "CLK_PMV_BYP2_0", - "CLK_PMV_BYP3_0", - "CLK_PMV_BYP4_0", - "CLK_PMV_BYP5_0", - "CLK_PMV_BYP6_0", - "CLK_PMV_BYP7_0", - "CLK_PMV_CLK0_0", - "CLK_PMV_CLK1_0", - "CLK_PMV_CTRL0_0", - "CLK_PMV_CTRL1_0", - "CLK_PMV_FAN0_0", - "CLK_PMV_FAN1_0", - "CLK_PMV_FAN2_0", - "CLK_PMV_FAN3_0", - "CLK_PMV_FAN4_0", - "CLK_PMV_FAN5_0", - "CLK_PMV_FAN6_0", - "CLK_PMV_FAN7_0", - "CLK_PMV_IMUX0_0", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX12_0", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX15_0", - "CLK_PMV_IMUX16_0", - "CLK_PMV_IMUX17_0", - "CLK_PMV_IMUX18_0", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX1_0", - "CLK_PMV_IMUX20_0", - "CLK_PMV_IMUX21_0", - "CLK_PMV_IMUX22_0", - "CLK_PMV_IMUX23_0", - "CLK_PMV_IMUX24_0", - "CLK_PMV_IMUX25_0", - "CLK_PMV_IMUX26_0", - "CLK_PMV_IMUX27_0", - "CLK_PMV_IMUX28_0", - "CLK_PMV_IMUX29_0", - "CLK_PMV_IMUX2_0", - "CLK_PMV_IMUX30_0", - "CLK_PMV_IMUX31_0", - "CLK_PMV_IMUX32_0", - "CLK_PMV_IMUX33_0", - "CLK_PMV_IMUX34_0", - "CLK_PMV_IMUX35_0", - "CLK_PMV_IMUX36_0", - "CLK_PMV_IMUX37_0", - "CLK_PMV_IMUX38_0", - "CLK_PMV_IMUX39_0", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX40_0", - "CLK_PMV_IMUX41_0", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX43_0", - "CLK_PMV_IMUX44_0", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX46_0", - "CLK_PMV_IMUX47_0", - "CLK_PMV_IMUX4_0", - "CLK_PMV_IMUX5_0", - "CLK_PMV_IMUX6_0", - "CLK_PMV_IMUX7_0", - "CLK_PMV_IMUX8_0", - "CLK_PMV_IMUX9_0", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_PMV_LOGIC_OUTS9_0" - ] + "wires": { + "CLK_FEED_CK_BUFG_CASC0": null, + "CLK_FEED_CK_BUFG_CASC1": null, + "CLK_FEED_CK_BUFG_CASC10": null, + "CLK_FEED_CK_BUFG_CASC11": null, + "CLK_FEED_CK_BUFG_CASC12": null, + "CLK_FEED_CK_BUFG_CASC13": null, + "CLK_FEED_CK_BUFG_CASC14": null, + "CLK_FEED_CK_BUFG_CASC15": null, + "CLK_FEED_CK_BUFG_CASC16": null, + "CLK_FEED_CK_BUFG_CASC17": null, + "CLK_FEED_CK_BUFG_CASC18": null, + "CLK_FEED_CK_BUFG_CASC19": null, + "CLK_FEED_CK_BUFG_CASC2": null, + "CLK_FEED_CK_BUFG_CASC20": null, + "CLK_FEED_CK_BUFG_CASC21": null, + "CLK_FEED_CK_BUFG_CASC22": null, + "CLK_FEED_CK_BUFG_CASC23": null, + "CLK_FEED_CK_BUFG_CASC24": null, + "CLK_FEED_CK_BUFG_CASC25": null, + "CLK_FEED_CK_BUFG_CASC26": null, + "CLK_FEED_CK_BUFG_CASC27": null, + "CLK_FEED_CK_BUFG_CASC28": null, + "CLK_FEED_CK_BUFG_CASC29": null, + "CLK_FEED_CK_BUFG_CASC3": null, + "CLK_FEED_CK_BUFG_CASC30": null, + "CLK_FEED_CK_BUFG_CASC31": null, + "CLK_FEED_CK_BUFG_CASC4": null, + "CLK_FEED_CK_BUFG_CASC5": null, + "CLK_FEED_CK_BUFG_CASC6": null, + "CLK_FEED_CK_BUFG_CASC7": null, + "CLK_FEED_CK_BUFG_CASC8": null, + "CLK_FEED_CK_BUFG_CASC9": null, + "CLK_FEED_CK_GCLK0": null, + "CLK_FEED_CK_GCLK1": null, + "CLK_FEED_CK_GCLK10": null, + "CLK_FEED_CK_GCLK11": null, + "CLK_FEED_CK_GCLK12": null, + "CLK_FEED_CK_GCLK13": null, + "CLK_FEED_CK_GCLK14": null, + "CLK_FEED_CK_GCLK15": null, + "CLK_FEED_CK_GCLK16": null, + "CLK_FEED_CK_GCLK17": null, + "CLK_FEED_CK_GCLK18": null, + "CLK_FEED_CK_GCLK19": null, + "CLK_FEED_CK_GCLK2": null, + "CLK_FEED_CK_GCLK20": null, + "CLK_FEED_CK_GCLK21": null, + "CLK_FEED_CK_GCLK22": null, + "CLK_FEED_CK_GCLK23": null, + "CLK_FEED_CK_GCLK24": null, + "CLK_FEED_CK_GCLK25": null, + "CLK_FEED_CK_GCLK26": null, + "CLK_FEED_CK_GCLK27": null, + "CLK_FEED_CK_GCLK28": null, + "CLK_FEED_CK_GCLK29": null, + "CLK_FEED_CK_GCLK3": null, + "CLK_FEED_CK_GCLK30": null, + "CLK_FEED_CK_GCLK31": null, + "CLK_FEED_CK_GCLK4": null, + "CLK_FEED_CK_GCLK5": null, + "CLK_FEED_CK_GCLK6": null, + "CLK_FEED_CK_GCLK7": null, + "CLK_FEED_CK_GCLK8": null, + "CLK_FEED_CK_GCLK9": null, + "CLK_FEED_EE2A0": null, + "CLK_FEED_EE2A1": null, + "CLK_FEED_EE2A2": null, + "CLK_FEED_EE2A3": null, + "CLK_FEED_EE2BEG0": null, + "CLK_FEED_EE2BEG1": null, + "CLK_FEED_EE2BEG2": null, + "CLK_FEED_EE2BEG3": null, + "CLK_FEED_EE4A0": null, + "CLK_FEED_EE4A1": null, + "CLK_FEED_EE4A2": null, + "CLK_FEED_EE4A3": null, + "CLK_FEED_EE4B0": null, + "CLK_FEED_EE4B1": null, + "CLK_FEED_EE4B2": null, + "CLK_FEED_EE4B3": null, + "CLK_FEED_EE4BEG0": null, + "CLK_FEED_EE4BEG1": null, + "CLK_FEED_EE4BEG2": null, + "CLK_FEED_EE4BEG3": null, + "CLK_FEED_EE4C0": null, + "CLK_FEED_EE4C1": null, + "CLK_FEED_EE4C2": null, + "CLK_FEED_EE4C3": null, + "CLK_FEED_EL1BEG0": null, + "CLK_FEED_EL1BEG1": null, + "CLK_FEED_EL1BEG2": null, + "CLK_FEED_EL1BEG3": null, + "CLK_FEED_ER1BEG0": null, + "CLK_FEED_ER1BEG1": null, + "CLK_FEED_ER1BEG2": null, + "CLK_FEED_ER1BEG3": null, + "CLK_FEED_LH1": null, + "CLK_FEED_LH10": null, + "CLK_FEED_LH11": null, + "CLK_FEED_LH12": null, + "CLK_FEED_LH2": null, + "CLK_FEED_LH3": null, + "CLK_FEED_LH4": null, + "CLK_FEED_LH5": null, + "CLK_FEED_LH6": null, + "CLK_FEED_LH7": null, + "CLK_FEED_LH8": null, + "CLK_FEED_LH9": null, + "CLK_FEED_MONITOR_N": null, + "CLK_FEED_MONITOR_P": null, + "CLK_FEED_NE2A0": null, + "CLK_FEED_NE2A1": null, + "CLK_FEED_NE2A2": null, + "CLK_FEED_NE2A3": null, + "CLK_FEED_NE4BEG0": null, + "CLK_FEED_NE4BEG1": null, + "CLK_FEED_NE4BEG2": null, + "CLK_FEED_NE4BEG3": null, + "CLK_FEED_NE4C0": null, + "CLK_FEED_NE4C1": null, + "CLK_FEED_NE4C2": null, + "CLK_FEED_NE4C3": null, + "CLK_FEED_NW2A0": null, + "CLK_FEED_NW2A1": null, + "CLK_FEED_NW2A2": null, + "CLK_FEED_NW2A3": null, + "CLK_FEED_NW4A0": null, + "CLK_FEED_NW4A1": null, + "CLK_FEED_NW4A2": null, + "CLK_FEED_NW4A3": null, + "CLK_FEED_NW4END0": null, + "CLK_FEED_NW4END1": null, + "CLK_FEED_NW4END2": null, + "CLK_FEED_NW4END3": null, + "CLK_FEED_R_CK_BUFG_CASC0": null, + "CLK_FEED_R_CK_BUFG_CASC1": null, + "CLK_FEED_R_CK_BUFG_CASC10": null, + "CLK_FEED_R_CK_BUFG_CASC11": null, + "CLK_FEED_R_CK_BUFG_CASC12": null, + "CLK_FEED_R_CK_BUFG_CASC13": null, + "CLK_FEED_R_CK_BUFG_CASC14": null, + "CLK_FEED_R_CK_BUFG_CASC15": null, + "CLK_FEED_R_CK_BUFG_CASC16": null, + "CLK_FEED_R_CK_BUFG_CASC17": null, + "CLK_FEED_R_CK_BUFG_CASC18": null, + "CLK_FEED_R_CK_BUFG_CASC19": null, + "CLK_FEED_R_CK_BUFG_CASC2": null, + "CLK_FEED_R_CK_BUFG_CASC20": null, + "CLK_FEED_R_CK_BUFG_CASC21": null, + "CLK_FEED_R_CK_BUFG_CASC22": null, + "CLK_FEED_R_CK_BUFG_CASC23": null, + "CLK_FEED_R_CK_BUFG_CASC24": null, + "CLK_FEED_R_CK_BUFG_CASC25": null, + "CLK_FEED_R_CK_BUFG_CASC26": null, + "CLK_FEED_R_CK_BUFG_CASC27": null, + "CLK_FEED_R_CK_BUFG_CASC28": null, + "CLK_FEED_R_CK_BUFG_CASC29": null, + "CLK_FEED_R_CK_BUFG_CASC3": null, + "CLK_FEED_R_CK_BUFG_CASC30": null, + "CLK_FEED_R_CK_BUFG_CASC31": null, + "CLK_FEED_R_CK_BUFG_CASC4": null, + "CLK_FEED_R_CK_BUFG_CASC5": null, + "CLK_FEED_R_CK_BUFG_CASC6": null, + "CLK_FEED_R_CK_BUFG_CASC7": null, + "CLK_FEED_R_CK_BUFG_CASC8": null, + "CLK_FEED_R_CK_BUFG_CASC9": null, + "CLK_FEED_R_CK_GCLK0": null, + "CLK_FEED_R_CK_GCLK1": null, + "CLK_FEED_R_CK_GCLK10": null, + "CLK_FEED_R_CK_GCLK11": null, + "CLK_FEED_R_CK_GCLK12": null, + "CLK_FEED_R_CK_GCLK13": null, + "CLK_FEED_R_CK_GCLK14": null, + "CLK_FEED_R_CK_GCLK15": null, + "CLK_FEED_R_CK_GCLK16": null, + "CLK_FEED_R_CK_GCLK17": null, + "CLK_FEED_R_CK_GCLK18": null, + "CLK_FEED_R_CK_GCLK19": null, + "CLK_FEED_R_CK_GCLK2": null, + "CLK_FEED_R_CK_GCLK20": null, + "CLK_FEED_R_CK_GCLK21": null, + "CLK_FEED_R_CK_GCLK22": null, + "CLK_FEED_R_CK_GCLK23": null, + "CLK_FEED_R_CK_GCLK24": null, + "CLK_FEED_R_CK_GCLK25": null, + "CLK_FEED_R_CK_GCLK26": null, + "CLK_FEED_R_CK_GCLK27": null, + "CLK_FEED_R_CK_GCLK28": null, + "CLK_FEED_R_CK_GCLK29": null, + "CLK_FEED_R_CK_GCLK3": null, + "CLK_FEED_R_CK_GCLK30": null, + "CLK_FEED_R_CK_GCLK31": null, + "CLK_FEED_R_CK_GCLK4": null, + "CLK_FEED_R_CK_GCLK5": null, + "CLK_FEED_R_CK_GCLK6": null, + "CLK_FEED_R_CK_GCLK7": null, + "CLK_FEED_R_CK_GCLK8": null, + "CLK_FEED_R_CK_GCLK9": null, + "CLK_FEED_SE2A0": null, + "CLK_FEED_SE2A1": null, + "CLK_FEED_SE2A2": null, + "CLK_FEED_SE2A3": null, + "CLK_FEED_SE4BEG0": null, + "CLK_FEED_SE4BEG1": null, + "CLK_FEED_SE4BEG2": null, + "CLK_FEED_SE4BEG3": null, + "CLK_FEED_SE4C0": null, + "CLK_FEED_SE4C1": null, + "CLK_FEED_SE4C2": null, + "CLK_FEED_SE4C3": null, + "CLK_FEED_SW2A0": null, + "CLK_FEED_SW2A1": null, + "CLK_FEED_SW2A2": null, + "CLK_FEED_SW2A3": null, + "CLK_FEED_SW4A0": null, + "CLK_FEED_SW4A1": null, + "CLK_FEED_SW4A2": null, + "CLK_FEED_SW4A3": null, + "CLK_FEED_SW4END0": null, + "CLK_FEED_SW4END1": null, + "CLK_FEED_SW4END2": null, + "CLK_FEED_SW4END3": null, + "CLK_FEED_WL1END0": null, + "CLK_FEED_WL1END1": null, + "CLK_FEED_WL1END2": null, + "CLK_FEED_WL1END3": null, + "CLK_FEED_WR1END0": null, + "CLK_FEED_WR1END1": null, + "CLK_FEED_WR1END2": null, + "CLK_FEED_WR1END3": null, + "CLK_FEED_WW2A0": null, + "CLK_FEED_WW2A1": null, + "CLK_FEED_WW2A2": null, + "CLK_FEED_WW2A3": null, + "CLK_FEED_WW2END0": null, + "CLK_FEED_WW2END1": null, + "CLK_FEED_WW2END2": null, + "CLK_FEED_WW2END3": null, + "CLK_FEED_WW4A0": null, + "CLK_FEED_WW4A1": null, + "CLK_FEED_WW4A2": null, + "CLK_FEED_WW4A3": null, + "CLK_FEED_WW4B0": null, + "CLK_FEED_WW4B1": null, + "CLK_FEED_WW4B2": null, + "CLK_FEED_WW4B3": null, + "CLK_FEED_WW4C0": null, + "CLK_FEED_WW4C1": null, + "CLK_FEED_WW4C2": null, + "CLK_FEED_WW4C3": null, + "CLK_FEED_WW4END0": null, + "CLK_FEED_WW4END1": null, + "CLK_FEED_WW4END2": null, + "CLK_FEED_WW4END3": null, + "CLK_MTBF2_CLK": null, + "CLK_MTBF2_DIN": null, + "CLK_MTBF2_EN": null, + "CLK_MTBF2_Q0B": null, + "CLK_MTBF2_Q1B": null, + "CLK_MTBF2_Q2B": null, + "CLK_MTBF2_Q3B": null, + "CLK_MTBF2_Q4B": null, + "CLK_MTBF2_Q5B": null, + "CLK_MTBF2_Q6B": null, + "CLK_MTBF2_Q7B": null, + "CLK_MTBF2_RESET": null, + "CLK_PMV_BYP0_0": null, + "CLK_PMV_BYP1_0": null, + "CLK_PMV_BYP2_0": null, + "CLK_PMV_BYP3_0": null, + "CLK_PMV_BYP4_0": null, + "CLK_PMV_BYP5_0": null, + "CLK_PMV_BYP6_0": null, + "CLK_PMV_BYP7_0": null, + "CLK_PMV_CLK0_0": null, + "CLK_PMV_CLK1_0": null, + "CLK_PMV_CTRL0_0": null, + "CLK_PMV_CTRL1_0": null, + "CLK_PMV_FAN0_0": null, + "CLK_PMV_FAN1_0": null, + "CLK_PMV_FAN2_0": null, + "CLK_PMV_FAN3_0": null, + "CLK_PMV_FAN4_0": null, + "CLK_PMV_FAN5_0": null, + "CLK_PMV_FAN6_0": null, + "CLK_PMV_FAN7_0": null, + "CLK_PMV_IMUX0_0": null, + "CLK_PMV_IMUX10_0": null, + "CLK_PMV_IMUX11_0": null, + "CLK_PMV_IMUX12_0": null, + "CLK_PMV_IMUX13_0": null, + "CLK_PMV_IMUX14_0": null, + "CLK_PMV_IMUX15_0": null, + "CLK_PMV_IMUX16_0": null, + "CLK_PMV_IMUX17_0": null, + "CLK_PMV_IMUX18_0": null, + "CLK_PMV_IMUX19_0": null, + "CLK_PMV_IMUX1_0": null, + "CLK_PMV_IMUX20_0": null, + "CLK_PMV_IMUX21_0": null, + "CLK_PMV_IMUX22_0": null, + "CLK_PMV_IMUX23_0": null, + "CLK_PMV_IMUX24_0": null, + "CLK_PMV_IMUX25_0": null, + "CLK_PMV_IMUX26_0": null, + "CLK_PMV_IMUX27_0": null, + "CLK_PMV_IMUX28_0": null, + "CLK_PMV_IMUX29_0": null, + "CLK_PMV_IMUX2_0": null, + "CLK_PMV_IMUX30_0": null, + "CLK_PMV_IMUX31_0": null, + "CLK_PMV_IMUX32_0": null, + "CLK_PMV_IMUX33_0": null, + "CLK_PMV_IMUX34_0": null, + "CLK_PMV_IMUX35_0": null, + "CLK_PMV_IMUX36_0": null, + "CLK_PMV_IMUX37_0": null, + "CLK_PMV_IMUX38_0": null, + "CLK_PMV_IMUX39_0": null, + "CLK_PMV_IMUX3_0": null, + "CLK_PMV_IMUX40_0": null, + "CLK_PMV_IMUX41_0": null, + "CLK_PMV_IMUX42_0": null, + "CLK_PMV_IMUX43_0": null, + "CLK_PMV_IMUX44_0": null, + "CLK_PMV_IMUX45_0": null, + "CLK_PMV_IMUX46_0": null, + "CLK_PMV_IMUX47_0": null, + "CLK_PMV_IMUX4_0": null, + "CLK_PMV_IMUX5_0": null, + "CLK_PMV_IMUX6_0": null, + "CLK_PMV_IMUX7_0": null, + "CLK_PMV_IMUX8_0": null, + "CLK_PMV_IMUX9_0": null, + "CLK_PMV_LOGIC_OUTS0_0": null, + "CLK_PMV_LOGIC_OUTS10_0": null, + "CLK_PMV_LOGIC_OUTS11_0": null, + "CLK_PMV_LOGIC_OUTS12_0": null, + "CLK_PMV_LOGIC_OUTS13_0": null, + "CLK_PMV_LOGIC_OUTS14_0": null, + "CLK_PMV_LOGIC_OUTS15_0": null, + "CLK_PMV_LOGIC_OUTS16_0": null, + "CLK_PMV_LOGIC_OUTS17_0": null, + "CLK_PMV_LOGIC_OUTS18_0": null, + "CLK_PMV_LOGIC_OUTS19_0": null, + "CLK_PMV_LOGIC_OUTS1_0": null, + "CLK_PMV_LOGIC_OUTS20_0": null, + "CLK_PMV_LOGIC_OUTS21_0": null, + "CLK_PMV_LOGIC_OUTS22_0": null, + "CLK_PMV_LOGIC_OUTS23_0": null, + "CLK_PMV_LOGIC_OUTS2_0": null, + "CLK_PMV_LOGIC_OUTS3_0": null, + "CLK_PMV_LOGIC_OUTS4_0": null, + "CLK_PMV_LOGIC_OUTS5_0": null, + "CLK_PMV_LOGIC_OUTS6_0": null, + "CLK_PMV_LOGIC_OUTS7_0": null, + "CLK_PMV_LOGIC_OUTS8_0": null, + "CLK_PMV_LOGIC_OUTS9_0": null + } } diff --git a/zynq7/tile_type_CLK_PMV.json b/zynq7/tile_type_CLK_PMV.json index fdb92ec..35d034c 100644 --- a/zynq7/tile_type_CLK_PMV.json +++ b/zynq7/tile_type_CLK_PMV.json @@ -2,1670 +2,1670 @@ "pips": {}, "sites": [], "tile_type": "CLK_PMV", - "wires": [ - "CLK_PMV_A0", - "CLK_PMV_A1", - "CLK_PMV_A2", - "CLK_PMV_A3", - "CLK_PMV_A4", - "CLK_PMV_A5", - "CLK_PMV_BYP0_0", - "CLK_PMV_BYP0_1", - "CLK_PMV_BYP0_2", - "CLK_PMV_BYP0_3", - "CLK_PMV_BYP0_4", - "CLK_PMV_BYP0_5", - "CLK_PMV_BYP0_6", - "CLK_PMV_BYP1_0", - "CLK_PMV_BYP1_1", - "CLK_PMV_BYP1_2", - "CLK_PMV_BYP1_3", - "CLK_PMV_BYP1_4", - "CLK_PMV_BYP1_5", - "CLK_PMV_BYP1_6", - "CLK_PMV_BYP2_0", - "CLK_PMV_BYP2_1", - "CLK_PMV_BYP2_2", - "CLK_PMV_BYP2_3", - "CLK_PMV_BYP2_4", - "CLK_PMV_BYP2_5", - "CLK_PMV_BYP2_6", - "CLK_PMV_BYP3_0", - "CLK_PMV_BYP3_1", - "CLK_PMV_BYP3_2", - "CLK_PMV_BYP3_3", - "CLK_PMV_BYP3_4", - "CLK_PMV_BYP3_5", - "CLK_PMV_BYP3_6", - "CLK_PMV_BYP4_0", - "CLK_PMV_BYP4_1", - "CLK_PMV_BYP4_2", - "CLK_PMV_BYP4_3", - "CLK_PMV_BYP4_4", - "CLK_PMV_BYP4_5", - "CLK_PMV_BYP4_6", - "CLK_PMV_BYP5_0", - "CLK_PMV_BYP5_1", - "CLK_PMV_BYP5_2", - "CLK_PMV_BYP5_3", - "CLK_PMV_BYP5_4", - "CLK_PMV_BYP5_5", - "CLK_PMV_BYP5_6", - "CLK_PMV_BYP6_0", - "CLK_PMV_BYP6_1", - "CLK_PMV_BYP6_2", - "CLK_PMV_BYP6_3", - "CLK_PMV_BYP6_4", - "CLK_PMV_BYP6_5", - "CLK_PMV_BYP6_6", - "CLK_PMV_BYP7_0", - "CLK_PMV_BYP7_1", - "CLK_PMV_BYP7_2", - "CLK_PMV_BYP7_3", - "CLK_PMV_BYP7_4", - "CLK_PMV_BYP7_5", - "CLK_PMV_BYP7_6", - "CLK_PMV_CK_BUFG_CASC0", - "CLK_PMV_CK_BUFG_CASC1", - "CLK_PMV_CK_BUFG_CASC10", - "CLK_PMV_CK_BUFG_CASC11", - "CLK_PMV_CK_BUFG_CASC12", - "CLK_PMV_CK_BUFG_CASC13", - "CLK_PMV_CK_BUFG_CASC14", - "CLK_PMV_CK_BUFG_CASC15", - "CLK_PMV_CK_BUFG_CASC16", - "CLK_PMV_CK_BUFG_CASC17", - "CLK_PMV_CK_BUFG_CASC18", - "CLK_PMV_CK_BUFG_CASC19", - "CLK_PMV_CK_BUFG_CASC2", - "CLK_PMV_CK_BUFG_CASC20", - "CLK_PMV_CK_BUFG_CASC21", - "CLK_PMV_CK_BUFG_CASC22", - "CLK_PMV_CK_BUFG_CASC23", - "CLK_PMV_CK_BUFG_CASC24", - "CLK_PMV_CK_BUFG_CASC25", - "CLK_PMV_CK_BUFG_CASC26", - "CLK_PMV_CK_BUFG_CASC27", - "CLK_PMV_CK_BUFG_CASC28", - "CLK_PMV_CK_BUFG_CASC29", - "CLK_PMV_CK_BUFG_CASC3", - "CLK_PMV_CK_BUFG_CASC30", - "CLK_PMV_CK_BUFG_CASC31", - "CLK_PMV_CK_BUFG_CASC4", - "CLK_PMV_CK_BUFG_CASC5", - "CLK_PMV_CK_BUFG_CASC6", - "CLK_PMV_CK_BUFG_CASC7", - "CLK_PMV_CK_BUFG_CASC8", - "CLK_PMV_CK_BUFG_CASC9", - "CLK_PMV_CK_GCLK0", - "CLK_PMV_CK_GCLK1", - "CLK_PMV_CK_GCLK10", - "CLK_PMV_CK_GCLK11", - "CLK_PMV_CK_GCLK12", - "CLK_PMV_CK_GCLK13", - "CLK_PMV_CK_GCLK14", - "CLK_PMV_CK_GCLK15", - "CLK_PMV_CK_GCLK16", - "CLK_PMV_CK_GCLK17", - "CLK_PMV_CK_GCLK18", - "CLK_PMV_CK_GCLK19", - "CLK_PMV_CK_GCLK2", - "CLK_PMV_CK_GCLK20", - "CLK_PMV_CK_GCLK21", - "CLK_PMV_CK_GCLK22", - "CLK_PMV_CK_GCLK23", - "CLK_PMV_CK_GCLK24", - "CLK_PMV_CK_GCLK25", - "CLK_PMV_CK_GCLK26", - "CLK_PMV_CK_GCLK27", - "CLK_PMV_CK_GCLK28", - "CLK_PMV_CK_GCLK29", - "CLK_PMV_CK_GCLK3", - "CLK_PMV_CK_GCLK30", - "CLK_PMV_CK_GCLK31", - "CLK_PMV_CK_GCLK4", - "CLK_PMV_CK_GCLK5", - "CLK_PMV_CK_GCLK6", - "CLK_PMV_CK_GCLK7", - "CLK_PMV_CK_GCLK8", - "CLK_PMV_CK_GCLK9", - "CLK_PMV_CLK0_0", - "CLK_PMV_CLK0_1", - "CLK_PMV_CLK0_2", - "CLK_PMV_CLK0_3", - "CLK_PMV_CLK0_4", - "CLK_PMV_CLK0_5", - "CLK_PMV_CLK0_6", - "CLK_PMV_CLK1_0", - "CLK_PMV_CLK1_1", - "CLK_PMV_CLK1_2", - "CLK_PMV_CLK1_3", - "CLK_PMV_CLK1_4", - "CLK_PMV_CLK1_5", - "CLK_PMV_CLK1_6", - "CLK_PMV_CTRL0_0", - "CLK_PMV_CTRL0_1", - "CLK_PMV_CTRL0_2", - "CLK_PMV_CTRL0_3", - "CLK_PMV_CTRL0_4", - "CLK_PMV_CTRL0_5", - "CLK_PMV_CTRL0_6", - "CLK_PMV_CTRL1_0", - "CLK_PMV_CTRL1_1", - "CLK_PMV_CTRL1_2", - "CLK_PMV_CTRL1_3", - "CLK_PMV_CTRL1_4", - "CLK_PMV_CTRL1_5", - "CLK_PMV_CTRL1_6", - "CLK_PMV_EE2A0_0", - "CLK_PMV_EE2A0_1", - "CLK_PMV_EE2A0_2", - "CLK_PMV_EE2A0_3", - "CLK_PMV_EE2A0_4", - "CLK_PMV_EE2A0_5", - "CLK_PMV_EE2A0_6", - "CLK_PMV_EE2A1_0", - "CLK_PMV_EE2A1_1", - "CLK_PMV_EE2A1_2", - "CLK_PMV_EE2A1_3", - "CLK_PMV_EE2A1_4", - "CLK_PMV_EE2A1_5", - "CLK_PMV_EE2A1_6", - "CLK_PMV_EE2A2_0", - "CLK_PMV_EE2A2_1", - "CLK_PMV_EE2A2_2", - "CLK_PMV_EE2A2_3", - "CLK_PMV_EE2A2_4", - "CLK_PMV_EE2A2_5", - "CLK_PMV_EE2A2_6", - "CLK_PMV_EE2A3_0", - "CLK_PMV_EE2A3_1", - "CLK_PMV_EE2A3_2", - "CLK_PMV_EE2A3_3", - "CLK_PMV_EE2A3_4", - "CLK_PMV_EE2A3_5", - "CLK_PMV_EE2A3_6", - "CLK_PMV_EE2BEG0_0", - "CLK_PMV_EE2BEG0_1", - "CLK_PMV_EE2BEG0_2", - "CLK_PMV_EE2BEG0_3", - "CLK_PMV_EE2BEG0_4", - "CLK_PMV_EE2BEG0_5", - "CLK_PMV_EE2BEG0_6", - "CLK_PMV_EE2BEG1_0", - "CLK_PMV_EE2BEG1_1", - "CLK_PMV_EE2BEG1_2", - "CLK_PMV_EE2BEG1_3", - "CLK_PMV_EE2BEG1_4", - "CLK_PMV_EE2BEG1_5", - "CLK_PMV_EE2BEG1_6", - "CLK_PMV_EE2BEG2_0", - "CLK_PMV_EE2BEG2_1", - "CLK_PMV_EE2BEG2_2", - "CLK_PMV_EE2BEG2_3", - "CLK_PMV_EE2BEG2_4", - "CLK_PMV_EE2BEG2_5", - "CLK_PMV_EE2BEG2_6", - "CLK_PMV_EE2BEG3_0", - "CLK_PMV_EE2BEG3_1", - "CLK_PMV_EE2BEG3_2", - "CLK_PMV_EE2BEG3_3", - "CLK_PMV_EE2BEG3_4", - "CLK_PMV_EE2BEG3_5", - "CLK_PMV_EE2BEG3_6", - "CLK_PMV_EE4A0_0", - "CLK_PMV_EE4A0_1", - "CLK_PMV_EE4A0_2", - "CLK_PMV_EE4A0_3", - "CLK_PMV_EE4A0_4", - "CLK_PMV_EE4A0_5", - "CLK_PMV_EE4A0_6", - "CLK_PMV_EE4A1_0", - "CLK_PMV_EE4A1_1", - "CLK_PMV_EE4A1_2", - "CLK_PMV_EE4A1_3", - "CLK_PMV_EE4A1_4", - "CLK_PMV_EE4A1_5", - "CLK_PMV_EE4A1_6", - "CLK_PMV_EE4A2_0", - "CLK_PMV_EE4A2_1", - "CLK_PMV_EE4A2_2", - "CLK_PMV_EE4A2_3", - "CLK_PMV_EE4A2_4", - "CLK_PMV_EE4A2_5", - "CLK_PMV_EE4A2_6", - "CLK_PMV_EE4A3_0", - "CLK_PMV_EE4A3_1", - "CLK_PMV_EE4A3_2", - "CLK_PMV_EE4A3_3", - "CLK_PMV_EE4A3_4", - "CLK_PMV_EE4A3_5", - "CLK_PMV_EE4A3_6", - "CLK_PMV_EE4B0_0", - "CLK_PMV_EE4B0_1", - "CLK_PMV_EE4B0_2", - "CLK_PMV_EE4B0_3", - "CLK_PMV_EE4B0_4", - "CLK_PMV_EE4B0_5", - "CLK_PMV_EE4B0_6", - "CLK_PMV_EE4B1_0", - "CLK_PMV_EE4B1_1", - "CLK_PMV_EE4B1_2", - "CLK_PMV_EE4B1_3", - "CLK_PMV_EE4B1_4", - "CLK_PMV_EE4B1_5", - "CLK_PMV_EE4B1_6", - "CLK_PMV_EE4B2_0", - "CLK_PMV_EE4B2_1", - "CLK_PMV_EE4B2_2", - "CLK_PMV_EE4B2_3", - "CLK_PMV_EE4B2_4", - "CLK_PMV_EE4B2_5", - "CLK_PMV_EE4B2_6", - "CLK_PMV_EE4B3_0", - "CLK_PMV_EE4B3_1", - "CLK_PMV_EE4B3_2", - "CLK_PMV_EE4B3_3", - "CLK_PMV_EE4B3_4", - "CLK_PMV_EE4B3_5", - "CLK_PMV_EE4B3_6", - "CLK_PMV_EE4BEG0_0", - "CLK_PMV_EE4BEG0_1", - "CLK_PMV_EE4BEG0_2", - "CLK_PMV_EE4BEG0_3", - "CLK_PMV_EE4BEG0_4", - "CLK_PMV_EE4BEG0_5", - "CLK_PMV_EE4BEG0_6", - "CLK_PMV_EE4BEG1_0", - "CLK_PMV_EE4BEG1_1", - "CLK_PMV_EE4BEG1_2", - "CLK_PMV_EE4BEG1_3", - "CLK_PMV_EE4BEG1_4", - "CLK_PMV_EE4BEG1_5", - "CLK_PMV_EE4BEG1_6", - "CLK_PMV_EE4BEG2_0", - "CLK_PMV_EE4BEG2_1", - "CLK_PMV_EE4BEG2_2", - "CLK_PMV_EE4BEG2_3", - "CLK_PMV_EE4BEG2_4", - "CLK_PMV_EE4BEG2_5", - "CLK_PMV_EE4BEG2_6", - "CLK_PMV_EE4BEG3_0", - "CLK_PMV_EE4BEG3_1", - "CLK_PMV_EE4BEG3_2", - "CLK_PMV_EE4BEG3_3", - "CLK_PMV_EE4BEG3_4", - "CLK_PMV_EE4BEG3_5", - "CLK_PMV_EE4BEG3_6", - "CLK_PMV_EE4C0_0", - "CLK_PMV_EE4C0_1", - "CLK_PMV_EE4C0_2", - "CLK_PMV_EE4C0_3", - "CLK_PMV_EE4C0_4", - "CLK_PMV_EE4C0_5", - "CLK_PMV_EE4C0_6", - "CLK_PMV_EE4C1_0", - "CLK_PMV_EE4C1_1", - "CLK_PMV_EE4C1_2", - "CLK_PMV_EE4C1_3", - "CLK_PMV_EE4C1_4", - "CLK_PMV_EE4C1_5", - "CLK_PMV_EE4C1_6", - "CLK_PMV_EE4C2_0", - "CLK_PMV_EE4C2_1", - "CLK_PMV_EE4C2_2", - "CLK_PMV_EE4C2_3", - "CLK_PMV_EE4C2_4", - "CLK_PMV_EE4C2_5", - "CLK_PMV_EE4C2_6", - "CLK_PMV_EE4C3_0", - "CLK_PMV_EE4C3_1", - "CLK_PMV_EE4C3_2", - "CLK_PMV_EE4C3_3", - "CLK_PMV_EE4C3_4", - "CLK_PMV_EE4C3_5", - "CLK_PMV_EE4C3_6", - "CLK_PMV_EL1BEG0_0", - "CLK_PMV_EL1BEG0_1", - "CLK_PMV_EL1BEG0_2", - "CLK_PMV_EL1BEG0_3", - "CLK_PMV_EL1BEG0_4", - "CLK_PMV_EL1BEG0_5", - "CLK_PMV_EL1BEG0_6", - "CLK_PMV_EL1BEG1_0", - "CLK_PMV_EL1BEG1_1", - "CLK_PMV_EL1BEG1_2", - "CLK_PMV_EL1BEG1_3", - "CLK_PMV_EL1BEG1_4", - "CLK_PMV_EL1BEG1_5", - "CLK_PMV_EL1BEG1_6", - "CLK_PMV_EL1BEG2_0", - "CLK_PMV_EL1BEG2_1", - "CLK_PMV_EL1BEG2_2", - "CLK_PMV_EL1BEG2_3", - "CLK_PMV_EL1BEG2_4", - "CLK_PMV_EL1BEG2_5", - "CLK_PMV_EL1BEG2_6", - "CLK_PMV_EL1BEG3_0", - "CLK_PMV_EL1BEG3_1", - "CLK_PMV_EL1BEG3_2", - "CLK_PMV_EL1BEG3_3", - "CLK_PMV_EL1BEG3_4", - "CLK_PMV_EL1BEG3_5", - "CLK_PMV_EL1BEG3_6", - "CLK_PMV_EN", - "CLK_PMV_ER1BEG0_0", - "CLK_PMV_ER1BEG0_1", - "CLK_PMV_ER1BEG0_2", - "CLK_PMV_ER1BEG0_3", - "CLK_PMV_ER1BEG0_4", - "CLK_PMV_ER1BEG0_5", - "CLK_PMV_ER1BEG0_6", - "CLK_PMV_ER1BEG1_0", - "CLK_PMV_ER1BEG1_1", - "CLK_PMV_ER1BEG1_2", - "CLK_PMV_ER1BEG1_3", - "CLK_PMV_ER1BEG1_4", - "CLK_PMV_ER1BEG1_5", - "CLK_PMV_ER1BEG1_6", - "CLK_PMV_ER1BEG2_0", - "CLK_PMV_ER1BEG2_1", - "CLK_PMV_ER1BEG2_2", - "CLK_PMV_ER1BEG2_3", - "CLK_PMV_ER1BEG2_4", - "CLK_PMV_ER1BEG2_5", - "CLK_PMV_ER1BEG2_6", - "CLK_PMV_ER1BEG3_0", - "CLK_PMV_ER1BEG3_1", - "CLK_PMV_ER1BEG3_2", - "CLK_PMV_ER1BEG3_3", - "CLK_PMV_ER1BEG3_4", - "CLK_PMV_ER1BEG3_5", - "CLK_PMV_ER1BEG3_6", - "CLK_PMV_FAN0_0", - "CLK_PMV_FAN0_1", - "CLK_PMV_FAN0_2", - "CLK_PMV_FAN0_3", - "CLK_PMV_FAN0_4", - "CLK_PMV_FAN0_5", - "CLK_PMV_FAN0_6", - "CLK_PMV_FAN1_0", - "CLK_PMV_FAN1_1", - "CLK_PMV_FAN1_2", - "CLK_PMV_FAN1_3", - "CLK_PMV_FAN1_4", - "CLK_PMV_FAN1_5", - "CLK_PMV_FAN1_6", - "CLK_PMV_FAN2_0", - "CLK_PMV_FAN2_1", - "CLK_PMV_FAN2_2", - "CLK_PMV_FAN2_3", - "CLK_PMV_FAN2_4", - "CLK_PMV_FAN2_5", - "CLK_PMV_FAN2_6", - "CLK_PMV_FAN3_0", - "CLK_PMV_FAN3_1", - "CLK_PMV_FAN3_2", - "CLK_PMV_FAN3_3", - "CLK_PMV_FAN3_4", - "CLK_PMV_FAN3_5", - "CLK_PMV_FAN3_6", - "CLK_PMV_FAN4_0", - "CLK_PMV_FAN4_1", - "CLK_PMV_FAN4_2", - "CLK_PMV_FAN4_3", - "CLK_PMV_FAN4_4", - "CLK_PMV_FAN4_5", - "CLK_PMV_FAN4_6", - "CLK_PMV_FAN5_0", - "CLK_PMV_FAN5_1", - "CLK_PMV_FAN5_2", - "CLK_PMV_FAN5_3", - "CLK_PMV_FAN5_4", - "CLK_PMV_FAN5_5", - "CLK_PMV_FAN5_6", - "CLK_PMV_FAN6_0", - "CLK_PMV_FAN6_1", - "CLK_PMV_FAN6_2", - "CLK_PMV_FAN6_3", - "CLK_PMV_FAN6_4", - "CLK_PMV_FAN6_5", - "CLK_PMV_FAN6_6", - "CLK_PMV_FAN7_0", - "CLK_PMV_FAN7_1", - "CLK_PMV_FAN7_2", - "CLK_PMV_FAN7_3", - "CLK_PMV_FAN7_4", - "CLK_PMV_FAN7_5", - "CLK_PMV_FAN7_6", - "CLK_PMV_IMUX0_0", - "CLK_PMV_IMUX0_1", - "CLK_PMV_IMUX0_2", - "CLK_PMV_IMUX0_3", - "CLK_PMV_IMUX0_4", - "CLK_PMV_IMUX0_5", - "CLK_PMV_IMUX0_6", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX10_1", - "CLK_PMV_IMUX10_2", - "CLK_PMV_IMUX10_3", - "CLK_PMV_IMUX10_4", - "CLK_PMV_IMUX10_5", - "CLK_PMV_IMUX10_6", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX11_1", - "CLK_PMV_IMUX11_2", - "CLK_PMV_IMUX11_3", - "CLK_PMV_IMUX11_4", - "CLK_PMV_IMUX11_5", - "CLK_PMV_IMUX11_6", - "CLK_PMV_IMUX12_0", - "CLK_PMV_IMUX12_1", - "CLK_PMV_IMUX12_2", - "CLK_PMV_IMUX12_3", - "CLK_PMV_IMUX12_4", - "CLK_PMV_IMUX12_5", - "CLK_PMV_IMUX12_6", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX13_1", - "CLK_PMV_IMUX13_2", - "CLK_PMV_IMUX13_3", - "CLK_PMV_IMUX13_4", - "CLK_PMV_IMUX13_5", - "CLK_PMV_IMUX13_6", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX14_1", - "CLK_PMV_IMUX14_2", - "CLK_PMV_IMUX14_3", - "CLK_PMV_IMUX14_4", - "CLK_PMV_IMUX14_5", - "CLK_PMV_IMUX14_6", - "CLK_PMV_IMUX15_0", - "CLK_PMV_IMUX15_1", - "CLK_PMV_IMUX15_2", - "CLK_PMV_IMUX15_3", - "CLK_PMV_IMUX15_4", - "CLK_PMV_IMUX15_5", - "CLK_PMV_IMUX15_6", - "CLK_PMV_IMUX16_0", - "CLK_PMV_IMUX16_1", - "CLK_PMV_IMUX16_2", - "CLK_PMV_IMUX16_3", - "CLK_PMV_IMUX16_4", - "CLK_PMV_IMUX16_5", - "CLK_PMV_IMUX16_6", - "CLK_PMV_IMUX17_0", - "CLK_PMV_IMUX17_1", - "CLK_PMV_IMUX17_2", - "CLK_PMV_IMUX17_3", - "CLK_PMV_IMUX17_4", - "CLK_PMV_IMUX17_5", - "CLK_PMV_IMUX17_6", - "CLK_PMV_IMUX18_0", - "CLK_PMV_IMUX18_1", - "CLK_PMV_IMUX18_2", - "CLK_PMV_IMUX18_3", - "CLK_PMV_IMUX18_4", - "CLK_PMV_IMUX18_5", - "CLK_PMV_IMUX18_6", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX19_1", - "CLK_PMV_IMUX19_2", - "CLK_PMV_IMUX19_3", - "CLK_PMV_IMUX19_4", - "CLK_PMV_IMUX19_5", - "CLK_PMV_IMUX19_6", - "CLK_PMV_IMUX1_0", - "CLK_PMV_IMUX1_1", - "CLK_PMV_IMUX1_2", - "CLK_PMV_IMUX1_3", - "CLK_PMV_IMUX1_4", - "CLK_PMV_IMUX1_5", - "CLK_PMV_IMUX1_6", - "CLK_PMV_IMUX20_0", - "CLK_PMV_IMUX20_1", - "CLK_PMV_IMUX20_2", - "CLK_PMV_IMUX20_3", - "CLK_PMV_IMUX20_4", - "CLK_PMV_IMUX20_5", - "CLK_PMV_IMUX20_6", - "CLK_PMV_IMUX21_0", - "CLK_PMV_IMUX21_1", - "CLK_PMV_IMUX21_2", - "CLK_PMV_IMUX21_3", - "CLK_PMV_IMUX21_4", - "CLK_PMV_IMUX21_5", - "CLK_PMV_IMUX21_6", - "CLK_PMV_IMUX22_0", - "CLK_PMV_IMUX22_1", - "CLK_PMV_IMUX22_2", - "CLK_PMV_IMUX22_3", - "CLK_PMV_IMUX22_4", - "CLK_PMV_IMUX22_5", - "CLK_PMV_IMUX22_6", - "CLK_PMV_IMUX23_0", - "CLK_PMV_IMUX23_1", - "CLK_PMV_IMUX23_2", - "CLK_PMV_IMUX23_3", - "CLK_PMV_IMUX23_4", - "CLK_PMV_IMUX23_5", - "CLK_PMV_IMUX23_6", - "CLK_PMV_IMUX24_0", - "CLK_PMV_IMUX24_1", - "CLK_PMV_IMUX24_2", - "CLK_PMV_IMUX24_3", - "CLK_PMV_IMUX24_4", - "CLK_PMV_IMUX24_5", - "CLK_PMV_IMUX24_6", - "CLK_PMV_IMUX25_0", - "CLK_PMV_IMUX25_1", - "CLK_PMV_IMUX25_2", - "CLK_PMV_IMUX25_3", - "CLK_PMV_IMUX25_4", - "CLK_PMV_IMUX25_5", - "CLK_PMV_IMUX25_6", - "CLK_PMV_IMUX26_0", - "CLK_PMV_IMUX26_1", - "CLK_PMV_IMUX26_2", - "CLK_PMV_IMUX26_3", - "CLK_PMV_IMUX26_4", - "CLK_PMV_IMUX26_5", - "CLK_PMV_IMUX26_6", - "CLK_PMV_IMUX27_0", - "CLK_PMV_IMUX27_1", - "CLK_PMV_IMUX27_2", - "CLK_PMV_IMUX27_3", - "CLK_PMV_IMUX27_4", - "CLK_PMV_IMUX27_5", - "CLK_PMV_IMUX27_6", - "CLK_PMV_IMUX28_0", - "CLK_PMV_IMUX28_1", - "CLK_PMV_IMUX28_2", - "CLK_PMV_IMUX28_3", - "CLK_PMV_IMUX28_4", - "CLK_PMV_IMUX28_5", - "CLK_PMV_IMUX28_6", - "CLK_PMV_IMUX29_0", - "CLK_PMV_IMUX29_1", - "CLK_PMV_IMUX29_2", - "CLK_PMV_IMUX29_3", - "CLK_PMV_IMUX29_4", - "CLK_PMV_IMUX29_5", - "CLK_PMV_IMUX29_6", - "CLK_PMV_IMUX2_0", - "CLK_PMV_IMUX2_1", - "CLK_PMV_IMUX2_2", - "CLK_PMV_IMUX2_3", - "CLK_PMV_IMUX2_4", - "CLK_PMV_IMUX2_5", - "CLK_PMV_IMUX2_6", - "CLK_PMV_IMUX30_0", - "CLK_PMV_IMUX30_1", - "CLK_PMV_IMUX30_2", - "CLK_PMV_IMUX30_3", - "CLK_PMV_IMUX30_4", - "CLK_PMV_IMUX30_5", - "CLK_PMV_IMUX30_6", - "CLK_PMV_IMUX31_0", - "CLK_PMV_IMUX31_1", - "CLK_PMV_IMUX31_2", - "CLK_PMV_IMUX31_3", - "CLK_PMV_IMUX31_4", - "CLK_PMV_IMUX31_5", - "CLK_PMV_IMUX31_6", - "CLK_PMV_IMUX32_0", - "CLK_PMV_IMUX32_1", - "CLK_PMV_IMUX32_2", - "CLK_PMV_IMUX32_3", - "CLK_PMV_IMUX32_4", - "CLK_PMV_IMUX32_5", - "CLK_PMV_IMUX32_6", - "CLK_PMV_IMUX33_0", - "CLK_PMV_IMUX33_1", - "CLK_PMV_IMUX33_2", - "CLK_PMV_IMUX33_3", - "CLK_PMV_IMUX33_4", - "CLK_PMV_IMUX33_5", - "CLK_PMV_IMUX33_6", - "CLK_PMV_IMUX34_0", - "CLK_PMV_IMUX34_1", - "CLK_PMV_IMUX34_2", - "CLK_PMV_IMUX34_3", - "CLK_PMV_IMUX34_4", - "CLK_PMV_IMUX34_5", - "CLK_PMV_IMUX34_6", - "CLK_PMV_IMUX35_0", - "CLK_PMV_IMUX35_1", - "CLK_PMV_IMUX35_2", - "CLK_PMV_IMUX35_3", - "CLK_PMV_IMUX35_4", - "CLK_PMV_IMUX35_5", - "CLK_PMV_IMUX35_6", - "CLK_PMV_IMUX36_0", - "CLK_PMV_IMUX36_1", - "CLK_PMV_IMUX36_2", - "CLK_PMV_IMUX36_3", - "CLK_PMV_IMUX36_4", - "CLK_PMV_IMUX36_5", - "CLK_PMV_IMUX36_6", - "CLK_PMV_IMUX37_0", - "CLK_PMV_IMUX37_1", - "CLK_PMV_IMUX37_2", - "CLK_PMV_IMUX37_3", - "CLK_PMV_IMUX37_4", - "CLK_PMV_IMUX37_5", - "CLK_PMV_IMUX37_6", - "CLK_PMV_IMUX38_0", - "CLK_PMV_IMUX38_1", - "CLK_PMV_IMUX38_2", - "CLK_PMV_IMUX38_3", - "CLK_PMV_IMUX38_4", - "CLK_PMV_IMUX38_5", - "CLK_PMV_IMUX38_6", - "CLK_PMV_IMUX39_0", - "CLK_PMV_IMUX39_1", - "CLK_PMV_IMUX39_2", - "CLK_PMV_IMUX39_3", - "CLK_PMV_IMUX39_4", - "CLK_PMV_IMUX39_5", - "CLK_PMV_IMUX39_6", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX3_1", - "CLK_PMV_IMUX3_2", - "CLK_PMV_IMUX3_3", - "CLK_PMV_IMUX3_4", - "CLK_PMV_IMUX3_5", - "CLK_PMV_IMUX3_6", - "CLK_PMV_IMUX40_0", - "CLK_PMV_IMUX40_1", - "CLK_PMV_IMUX40_2", - "CLK_PMV_IMUX40_3", - "CLK_PMV_IMUX40_4", - "CLK_PMV_IMUX40_5", - "CLK_PMV_IMUX40_6", - "CLK_PMV_IMUX41_0", - "CLK_PMV_IMUX41_1", - "CLK_PMV_IMUX41_2", - "CLK_PMV_IMUX41_3", - "CLK_PMV_IMUX41_4", - "CLK_PMV_IMUX41_5", - "CLK_PMV_IMUX41_6", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX42_1", - "CLK_PMV_IMUX42_2", - "CLK_PMV_IMUX42_3", - "CLK_PMV_IMUX42_4", - "CLK_PMV_IMUX42_5", - "CLK_PMV_IMUX42_6", - "CLK_PMV_IMUX43_0", - "CLK_PMV_IMUX43_1", - "CLK_PMV_IMUX43_2", - "CLK_PMV_IMUX43_3", - "CLK_PMV_IMUX43_4", - "CLK_PMV_IMUX43_5", - "CLK_PMV_IMUX43_6", - "CLK_PMV_IMUX44_0", - "CLK_PMV_IMUX44_1", - "CLK_PMV_IMUX44_2", - "CLK_PMV_IMUX44_3", - "CLK_PMV_IMUX44_4", - "CLK_PMV_IMUX44_5", - "CLK_PMV_IMUX44_6", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX45_1", - "CLK_PMV_IMUX45_2", - "CLK_PMV_IMUX45_3", - "CLK_PMV_IMUX45_4", - "CLK_PMV_IMUX45_5", - "CLK_PMV_IMUX45_6", - "CLK_PMV_IMUX46_0", - "CLK_PMV_IMUX46_1", - "CLK_PMV_IMUX46_2", - "CLK_PMV_IMUX46_3", - "CLK_PMV_IMUX46_4", - "CLK_PMV_IMUX46_5", - "CLK_PMV_IMUX46_6", - "CLK_PMV_IMUX47_0", - "CLK_PMV_IMUX47_1", - "CLK_PMV_IMUX47_2", - "CLK_PMV_IMUX47_3", - "CLK_PMV_IMUX47_4", - "CLK_PMV_IMUX47_5", - "CLK_PMV_IMUX47_6", - "CLK_PMV_IMUX4_0", - "CLK_PMV_IMUX4_1", - "CLK_PMV_IMUX4_2", - "CLK_PMV_IMUX4_3", - "CLK_PMV_IMUX4_4", - "CLK_PMV_IMUX4_5", - "CLK_PMV_IMUX4_6", - "CLK_PMV_IMUX5_0", - "CLK_PMV_IMUX5_1", - "CLK_PMV_IMUX5_2", - "CLK_PMV_IMUX5_3", - "CLK_PMV_IMUX5_4", - "CLK_PMV_IMUX5_5", - "CLK_PMV_IMUX5_6", - "CLK_PMV_IMUX6_0", - "CLK_PMV_IMUX6_1", - "CLK_PMV_IMUX6_2", - "CLK_PMV_IMUX6_3", - "CLK_PMV_IMUX6_4", - "CLK_PMV_IMUX6_5", - "CLK_PMV_IMUX6_6", - "CLK_PMV_IMUX7_0", - "CLK_PMV_IMUX7_1", - "CLK_PMV_IMUX7_2", - "CLK_PMV_IMUX7_3", - "CLK_PMV_IMUX7_4", - "CLK_PMV_IMUX7_5", - "CLK_PMV_IMUX7_6", - "CLK_PMV_IMUX8_0", - "CLK_PMV_IMUX8_1", - "CLK_PMV_IMUX8_2", - "CLK_PMV_IMUX8_3", - "CLK_PMV_IMUX8_4", - "CLK_PMV_IMUX8_5", - "CLK_PMV_IMUX8_6", - "CLK_PMV_IMUX9_0", - "CLK_PMV_IMUX9_1", - "CLK_PMV_IMUX9_2", - "CLK_PMV_IMUX9_3", - "CLK_PMV_IMUX9_4", - "CLK_PMV_IMUX9_5", - "CLK_PMV_IMUX9_6", - "CLK_PMV_LH10_0", - "CLK_PMV_LH10_1", - "CLK_PMV_LH10_2", - "CLK_PMV_LH10_3", - "CLK_PMV_LH10_4", - "CLK_PMV_LH10_5", - "CLK_PMV_LH10_6", - "CLK_PMV_LH11_0", - "CLK_PMV_LH11_1", - "CLK_PMV_LH11_2", - "CLK_PMV_LH11_3", - "CLK_PMV_LH11_4", - "CLK_PMV_LH11_5", - "CLK_PMV_LH11_6", - "CLK_PMV_LH12_0", - "CLK_PMV_LH12_1", - "CLK_PMV_LH12_2", - "CLK_PMV_LH12_3", - "CLK_PMV_LH12_4", - "CLK_PMV_LH12_5", - "CLK_PMV_LH12_6", - "CLK_PMV_LH1_0", - "CLK_PMV_LH1_1", - "CLK_PMV_LH1_2", - "CLK_PMV_LH1_3", - "CLK_PMV_LH1_4", - "CLK_PMV_LH1_5", - "CLK_PMV_LH1_6", - "CLK_PMV_LH2_0", - "CLK_PMV_LH2_1", - "CLK_PMV_LH2_2", - "CLK_PMV_LH2_3", - "CLK_PMV_LH2_4", - "CLK_PMV_LH2_5", - "CLK_PMV_LH2_6", - "CLK_PMV_LH3_0", - "CLK_PMV_LH3_1", - "CLK_PMV_LH3_2", - "CLK_PMV_LH3_3", - "CLK_PMV_LH3_4", - "CLK_PMV_LH3_5", - "CLK_PMV_LH3_6", - "CLK_PMV_LH4_0", - "CLK_PMV_LH4_1", - "CLK_PMV_LH4_2", - "CLK_PMV_LH4_3", - "CLK_PMV_LH4_4", - "CLK_PMV_LH4_5", - "CLK_PMV_LH4_6", - "CLK_PMV_LH5_0", - "CLK_PMV_LH5_1", - "CLK_PMV_LH5_2", - "CLK_PMV_LH5_3", - "CLK_PMV_LH5_4", - "CLK_PMV_LH5_5", - "CLK_PMV_LH5_6", - "CLK_PMV_LH6_0", - "CLK_PMV_LH6_1", - "CLK_PMV_LH6_2", - "CLK_PMV_LH6_3", - "CLK_PMV_LH6_4", - "CLK_PMV_LH6_5", - "CLK_PMV_LH6_6", - "CLK_PMV_LH7_0", - "CLK_PMV_LH7_1", - "CLK_PMV_LH7_2", - "CLK_PMV_LH7_3", - "CLK_PMV_LH7_4", - "CLK_PMV_LH7_5", - "CLK_PMV_LH7_6", - "CLK_PMV_LH8_0", - "CLK_PMV_LH8_1", - "CLK_PMV_LH8_2", - "CLK_PMV_LH8_3", - "CLK_PMV_LH8_4", - "CLK_PMV_LH8_5", - "CLK_PMV_LH8_6", - "CLK_PMV_LH9_0", - "CLK_PMV_LH9_1", - "CLK_PMV_LH9_2", - "CLK_PMV_LH9_3", - "CLK_PMV_LH9_4", - "CLK_PMV_LH9_5", - "CLK_PMV_LH9_6", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_PMV_LOGIC_OUTS0_1", - "CLK_PMV_LOGIC_OUTS0_2", - "CLK_PMV_LOGIC_OUTS0_3", - "CLK_PMV_LOGIC_OUTS0_4", - "CLK_PMV_LOGIC_OUTS0_5", - "CLK_PMV_LOGIC_OUTS0_6", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS10_1", - "CLK_PMV_LOGIC_OUTS10_2", - "CLK_PMV_LOGIC_OUTS10_3", - "CLK_PMV_LOGIC_OUTS10_4", - "CLK_PMV_LOGIC_OUTS10_5", - "CLK_PMV_LOGIC_OUTS10_6", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_PMV_LOGIC_OUTS11_1", - "CLK_PMV_LOGIC_OUTS11_2", - "CLK_PMV_LOGIC_OUTS11_3", - "CLK_PMV_LOGIC_OUTS11_4", - "CLK_PMV_LOGIC_OUTS11_5", - "CLK_PMV_LOGIC_OUTS11_6", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_PMV_LOGIC_OUTS12_1", - "CLK_PMV_LOGIC_OUTS12_2", - "CLK_PMV_LOGIC_OUTS12_3", - "CLK_PMV_LOGIC_OUTS12_4", - "CLK_PMV_LOGIC_OUTS12_5", - "CLK_PMV_LOGIC_OUTS12_6", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_PMV_LOGIC_OUTS13_1", - "CLK_PMV_LOGIC_OUTS13_2", - "CLK_PMV_LOGIC_OUTS13_3", - "CLK_PMV_LOGIC_OUTS13_4", - "CLK_PMV_LOGIC_OUTS13_5", - "CLK_PMV_LOGIC_OUTS13_6", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS14_1", - "CLK_PMV_LOGIC_OUTS14_2", - "CLK_PMV_LOGIC_OUTS14_3", - "CLK_PMV_LOGIC_OUTS14_4", - "CLK_PMV_LOGIC_OUTS14_5", - "CLK_PMV_LOGIC_OUTS14_6", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_PMV_LOGIC_OUTS15_1", - "CLK_PMV_LOGIC_OUTS15_2", - "CLK_PMV_LOGIC_OUTS15_3", - "CLK_PMV_LOGIC_OUTS15_4", - "CLK_PMV_LOGIC_OUTS15_5", - "CLK_PMV_LOGIC_OUTS15_6", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_PMV_LOGIC_OUTS16_1", - "CLK_PMV_LOGIC_OUTS16_2", - "CLK_PMV_LOGIC_OUTS16_3", - "CLK_PMV_LOGIC_OUTS16_4", - "CLK_PMV_LOGIC_OUTS16_5", - "CLK_PMV_LOGIC_OUTS16_6", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_PMV_LOGIC_OUTS17_1", - "CLK_PMV_LOGIC_OUTS17_2", - "CLK_PMV_LOGIC_OUTS17_3", - "CLK_PMV_LOGIC_OUTS17_4", - "CLK_PMV_LOGIC_OUTS17_5", - "CLK_PMV_LOGIC_OUTS17_6", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_PMV_LOGIC_OUTS18_1", - "CLK_PMV_LOGIC_OUTS18_2", - "CLK_PMV_LOGIC_OUTS18_3", - "CLK_PMV_LOGIC_OUTS18_4", - "CLK_PMV_LOGIC_OUTS18_5", - "CLK_PMV_LOGIC_OUTS18_6", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_PMV_LOGIC_OUTS19_1", - "CLK_PMV_LOGIC_OUTS19_2", - "CLK_PMV_LOGIC_OUTS19_3", - "CLK_PMV_LOGIC_OUTS19_4", - "CLK_PMV_LOGIC_OUTS19_5", - "CLK_PMV_LOGIC_OUTS19_6", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_PMV_LOGIC_OUTS1_1", - "CLK_PMV_LOGIC_OUTS1_2", - "CLK_PMV_LOGIC_OUTS1_3", - "CLK_PMV_LOGIC_OUTS1_4", - "CLK_PMV_LOGIC_OUTS1_5", - "CLK_PMV_LOGIC_OUTS1_6", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_PMV_LOGIC_OUTS20_1", - "CLK_PMV_LOGIC_OUTS20_2", - "CLK_PMV_LOGIC_OUTS20_3", - "CLK_PMV_LOGIC_OUTS20_4", - "CLK_PMV_LOGIC_OUTS20_5", - "CLK_PMV_LOGIC_OUTS20_6", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_PMV_LOGIC_OUTS21_1", - "CLK_PMV_LOGIC_OUTS21_2", - "CLK_PMV_LOGIC_OUTS21_3", - "CLK_PMV_LOGIC_OUTS21_4", - "CLK_PMV_LOGIC_OUTS21_5", - "CLK_PMV_LOGIC_OUTS21_6", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_LOGIC_OUTS22_1", - "CLK_PMV_LOGIC_OUTS22_2", - "CLK_PMV_LOGIC_OUTS22_3", - "CLK_PMV_LOGIC_OUTS22_4", - "CLK_PMV_LOGIC_OUTS22_5", - "CLK_PMV_LOGIC_OUTS22_6", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_PMV_LOGIC_OUTS23_1", - "CLK_PMV_LOGIC_OUTS23_2", - "CLK_PMV_LOGIC_OUTS23_3", - "CLK_PMV_LOGIC_OUTS23_4", - "CLK_PMV_LOGIC_OUTS23_5", - "CLK_PMV_LOGIC_OUTS23_6", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS2_1", - "CLK_PMV_LOGIC_OUTS2_2", - "CLK_PMV_LOGIC_OUTS2_3", - "CLK_PMV_LOGIC_OUTS2_4", - "CLK_PMV_LOGIC_OUTS2_5", - "CLK_PMV_LOGIC_OUTS2_6", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_PMV_LOGIC_OUTS3_1", - "CLK_PMV_LOGIC_OUTS3_2", - "CLK_PMV_LOGIC_OUTS3_3", - "CLK_PMV_LOGIC_OUTS3_4", - "CLK_PMV_LOGIC_OUTS3_5", - "CLK_PMV_LOGIC_OUTS3_6", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_PMV_LOGIC_OUTS4_1", - "CLK_PMV_LOGIC_OUTS4_2", - "CLK_PMV_LOGIC_OUTS4_3", - "CLK_PMV_LOGIC_OUTS4_4", - "CLK_PMV_LOGIC_OUTS4_5", - "CLK_PMV_LOGIC_OUTS4_6", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_LOGIC_OUTS5_1", - "CLK_PMV_LOGIC_OUTS5_2", - "CLK_PMV_LOGIC_OUTS5_3", - "CLK_PMV_LOGIC_OUTS5_4", - "CLK_PMV_LOGIC_OUTS5_5", - "CLK_PMV_LOGIC_OUTS5_6", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_PMV_LOGIC_OUTS6_1", - "CLK_PMV_LOGIC_OUTS6_2", - "CLK_PMV_LOGIC_OUTS6_3", - "CLK_PMV_LOGIC_OUTS6_4", - "CLK_PMV_LOGIC_OUTS6_5", - "CLK_PMV_LOGIC_OUTS6_6", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_LOGIC_OUTS7_1", - "CLK_PMV_LOGIC_OUTS7_2", - "CLK_PMV_LOGIC_OUTS7_3", - "CLK_PMV_LOGIC_OUTS7_4", - "CLK_PMV_LOGIC_OUTS7_5", - "CLK_PMV_LOGIC_OUTS7_6", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_PMV_LOGIC_OUTS8_1", - "CLK_PMV_LOGIC_OUTS8_2", - "CLK_PMV_LOGIC_OUTS8_3", - "CLK_PMV_LOGIC_OUTS8_4", - "CLK_PMV_LOGIC_OUTS8_5", - "CLK_PMV_LOGIC_OUTS8_6", - "CLK_PMV_LOGIC_OUTS9_0", - "CLK_PMV_LOGIC_OUTS9_1", - "CLK_PMV_LOGIC_OUTS9_2", - "CLK_PMV_LOGIC_OUTS9_3", - "CLK_PMV_LOGIC_OUTS9_4", - "CLK_PMV_LOGIC_OUTS9_5", - "CLK_PMV_LOGIC_OUTS9_6", - "CLK_PMV_MONITOR_N_0", - "CLK_PMV_MONITOR_N_1", - "CLK_PMV_MONITOR_N_2", - "CLK_PMV_MONITOR_N_3", - "CLK_PMV_MONITOR_N_4", - "CLK_PMV_MONITOR_N_5", - "CLK_PMV_MONITOR_N_6", - "CLK_PMV_MONITOR_P_0", - "CLK_PMV_MONITOR_P_1", - "CLK_PMV_MONITOR_P_2", - "CLK_PMV_MONITOR_P_3", - "CLK_PMV_MONITOR_P_4", - "CLK_PMV_MONITOR_P_5", - "CLK_PMV_MONITOR_P_6", - "CLK_PMV_NE2A0_0", - "CLK_PMV_NE2A0_1", - "CLK_PMV_NE2A0_2", - "CLK_PMV_NE2A0_3", - "CLK_PMV_NE2A0_4", - "CLK_PMV_NE2A0_5", - "CLK_PMV_NE2A0_6", - "CLK_PMV_NE2A1_0", - "CLK_PMV_NE2A1_1", - "CLK_PMV_NE2A1_2", - "CLK_PMV_NE2A1_3", - "CLK_PMV_NE2A1_4", - "CLK_PMV_NE2A1_5", - "CLK_PMV_NE2A1_6", - "CLK_PMV_NE2A2_0", - "CLK_PMV_NE2A2_1", - "CLK_PMV_NE2A2_2", - "CLK_PMV_NE2A2_3", - "CLK_PMV_NE2A2_4", - "CLK_PMV_NE2A2_5", - "CLK_PMV_NE2A2_6", - "CLK_PMV_NE2A3_0", - "CLK_PMV_NE2A3_1", - "CLK_PMV_NE2A3_2", - "CLK_PMV_NE2A3_3", - "CLK_PMV_NE2A3_4", - "CLK_PMV_NE2A3_5", - "CLK_PMV_NE2A3_6", - "CLK_PMV_NE4BEG0_0", - "CLK_PMV_NE4BEG0_1", - "CLK_PMV_NE4BEG0_2", - "CLK_PMV_NE4BEG0_3", - "CLK_PMV_NE4BEG0_4", - "CLK_PMV_NE4BEG0_5", - "CLK_PMV_NE4BEG0_6", - "CLK_PMV_NE4BEG1_0", - "CLK_PMV_NE4BEG1_1", - "CLK_PMV_NE4BEG1_2", - "CLK_PMV_NE4BEG1_3", - "CLK_PMV_NE4BEG1_4", - "CLK_PMV_NE4BEG1_5", - "CLK_PMV_NE4BEG1_6", - "CLK_PMV_NE4BEG2_0", - "CLK_PMV_NE4BEG2_1", - "CLK_PMV_NE4BEG2_2", - "CLK_PMV_NE4BEG2_3", - "CLK_PMV_NE4BEG2_4", - "CLK_PMV_NE4BEG2_5", - "CLK_PMV_NE4BEG2_6", - "CLK_PMV_NE4BEG3_0", - "CLK_PMV_NE4BEG3_1", - "CLK_PMV_NE4BEG3_2", - "CLK_PMV_NE4BEG3_3", - "CLK_PMV_NE4BEG3_4", - "CLK_PMV_NE4BEG3_5", - "CLK_PMV_NE4BEG3_6", - "CLK_PMV_NE4C0_0", - "CLK_PMV_NE4C0_1", - "CLK_PMV_NE4C0_2", - "CLK_PMV_NE4C0_3", - "CLK_PMV_NE4C0_4", - "CLK_PMV_NE4C0_5", - "CLK_PMV_NE4C0_6", - "CLK_PMV_NE4C1_0", - "CLK_PMV_NE4C1_1", - "CLK_PMV_NE4C1_2", - "CLK_PMV_NE4C1_3", - "CLK_PMV_NE4C1_4", - "CLK_PMV_NE4C1_5", - "CLK_PMV_NE4C1_6", - "CLK_PMV_NE4C2_0", - "CLK_PMV_NE4C2_1", - "CLK_PMV_NE4C2_2", - "CLK_PMV_NE4C2_3", - "CLK_PMV_NE4C2_4", - "CLK_PMV_NE4C2_5", - "CLK_PMV_NE4C2_6", - "CLK_PMV_NE4C3_0", - "CLK_PMV_NE4C3_1", - "CLK_PMV_NE4C3_2", - "CLK_PMV_NE4C3_3", - "CLK_PMV_NE4C3_4", - "CLK_PMV_NE4C3_5", - "CLK_PMV_NE4C3_6", - "CLK_PMV_NW2A0_0", - "CLK_PMV_NW2A0_1", - "CLK_PMV_NW2A0_2", - "CLK_PMV_NW2A0_3", - "CLK_PMV_NW2A0_4", - "CLK_PMV_NW2A0_5", - "CLK_PMV_NW2A0_6", - "CLK_PMV_NW2A1_0", - "CLK_PMV_NW2A1_1", - "CLK_PMV_NW2A1_2", - "CLK_PMV_NW2A1_3", - "CLK_PMV_NW2A1_4", - "CLK_PMV_NW2A1_5", - "CLK_PMV_NW2A1_6", - "CLK_PMV_NW2A2_0", - "CLK_PMV_NW2A2_1", - "CLK_PMV_NW2A2_2", - "CLK_PMV_NW2A2_3", - "CLK_PMV_NW2A2_4", - "CLK_PMV_NW2A2_5", - "CLK_PMV_NW2A2_6", - "CLK_PMV_NW2A3_0", - "CLK_PMV_NW2A3_1", - "CLK_PMV_NW2A3_2", - "CLK_PMV_NW2A3_3", - "CLK_PMV_NW2A3_4", - "CLK_PMV_NW2A3_5", - "CLK_PMV_NW2A3_6", - "CLK_PMV_NW4A0_0", - "CLK_PMV_NW4A0_1", - "CLK_PMV_NW4A0_2", - "CLK_PMV_NW4A0_3", - "CLK_PMV_NW4A0_4", - "CLK_PMV_NW4A0_5", - "CLK_PMV_NW4A0_6", - "CLK_PMV_NW4A1_0", - "CLK_PMV_NW4A1_1", - "CLK_PMV_NW4A1_2", - "CLK_PMV_NW4A1_3", - "CLK_PMV_NW4A1_4", - "CLK_PMV_NW4A1_5", - "CLK_PMV_NW4A1_6", - "CLK_PMV_NW4A2_0", - "CLK_PMV_NW4A2_1", - "CLK_PMV_NW4A2_2", - "CLK_PMV_NW4A2_3", - "CLK_PMV_NW4A2_4", - "CLK_PMV_NW4A2_5", - "CLK_PMV_NW4A2_6", - "CLK_PMV_NW4A3_0", - "CLK_PMV_NW4A3_1", - "CLK_PMV_NW4A3_2", - "CLK_PMV_NW4A3_3", - "CLK_PMV_NW4A3_4", - "CLK_PMV_NW4A3_5", - "CLK_PMV_NW4A3_6", - "CLK_PMV_NW4END0_0", - "CLK_PMV_NW4END0_1", - "CLK_PMV_NW4END0_2", - "CLK_PMV_NW4END0_3", - "CLK_PMV_NW4END0_4", - "CLK_PMV_NW4END0_5", - "CLK_PMV_NW4END0_6", - "CLK_PMV_NW4END1_0", - "CLK_PMV_NW4END1_1", - "CLK_PMV_NW4END1_2", - "CLK_PMV_NW4END1_3", - "CLK_PMV_NW4END1_4", - "CLK_PMV_NW4END1_5", - "CLK_PMV_NW4END1_6", - "CLK_PMV_NW4END2_0", - "CLK_PMV_NW4END2_1", - "CLK_PMV_NW4END2_2", - "CLK_PMV_NW4END2_3", - "CLK_PMV_NW4END2_4", - "CLK_PMV_NW4END2_5", - "CLK_PMV_NW4END2_6", - "CLK_PMV_NW4END3_0", - "CLK_PMV_NW4END3_1", - "CLK_PMV_NW4END3_2", - "CLK_PMV_NW4END3_3", - "CLK_PMV_NW4END3_4", - "CLK_PMV_NW4END3_5", - "CLK_PMV_NW4END3_6", - "CLK_PMV_O", - "CLK_PMV_ODIV2", - "CLK_PMV_ODIV4", - "CLK_PMV_R_CK_BUFG_CASC0", - "CLK_PMV_R_CK_BUFG_CASC1", - "CLK_PMV_R_CK_BUFG_CASC10", - "CLK_PMV_R_CK_BUFG_CASC11", - "CLK_PMV_R_CK_BUFG_CASC12", - "CLK_PMV_R_CK_BUFG_CASC13", - "CLK_PMV_R_CK_BUFG_CASC14", - "CLK_PMV_R_CK_BUFG_CASC15", - "CLK_PMV_R_CK_BUFG_CASC16", - "CLK_PMV_R_CK_BUFG_CASC17", - "CLK_PMV_R_CK_BUFG_CASC18", - "CLK_PMV_R_CK_BUFG_CASC19", - "CLK_PMV_R_CK_BUFG_CASC2", - "CLK_PMV_R_CK_BUFG_CASC20", - "CLK_PMV_R_CK_BUFG_CASC21", - "CLK_PMV_R_CK_BUFG_CASC22", - "CLK_PMV_R_CK_BUFG_CASC23", - "CLK_PMV_R_CK_BUFG_CASC24", - "CLK_PMV_R_CK_BUFG_CASC25", - "CLK_PMV_R_CK_BUFG_CASC26", - "CLK_PMV_R_CK_BUFG_CASC27", - "CLK_PMV_R_CK_BUFG_CASC28", - "CLK_PMV_R_CK_BUFG_CASC29", - "CLK_PMV_R_CK_BUFG_CASC3", - "CLK_PMV_R_CK_BUFG_CASC30", - "CLK_PMV_R_CK_BUFG_CASC31", - "CLK_PMV_R_CK_BUFG_CASC4", - "CLK_PMV_R_CK_BUFG_CASC5", - "CLK_PMV_R_CK_BUFG_CASC6", - "CLK_PMV_R_CK_BUFG_CASC7", - "CLK_PMV_R_CK_BUFG_CASC8", - "CLK_PMV_R_CK_BUFG_CASC9", - "CLK_PMV_R_CK_GCLK0", - "CLK_PMV_R_CK_GCLK1", - "CLK_PMV_R_CK_GCLK10", - "CLK_PMV_R_CK_GCLK11", - "CLK_PMV_R_CK_GCLK12", - "CLK_PMV_R_CK_GCLK13", - "CLK_PMV_R_CK_GCLK14", - "CLK_PMV_R_CK_GCLK15", - "CLK_PMV_R_CK_GCLK16", - "CLK_PMV_R_CK_GCLK17", - "CLK_PMV_R_CK_GCLK18", - "CLK_PMV_R_CK_GCLK19", - "CLK_PMV_R_CK_GCLK2", - "CLK_PMV_R_CK_GCLK20", - "CLK_PMV_R_CK_GCLK21", - "CLK_PMV_R_CK_GCLK22", - "CLK_PMV_R_CK_GCLK23", - "CLK_PMV_R_CK_GCLK24", - "CLK_PMV_R_CK_GCLK25", - "CLK_PMV_R_CK_GCLK26", - "CLK_PMV_R_CK_GCLK27", - "CLK_PMV_R_CK_GCLK28", - "CLK_PMV_R_CK_GCLK29", - "CLK_PMV_R_CK_GCLK3", - "CLK_PMV_R_CK_GCLK30", - "CLK_PMV_R_CK_GCLK31", - "CLK_PMV_R_CK_GCLK4", - "CLK_PMV_R_CK_GCLK5", - "CLK_PMV_R_CK_GCLK6", - "CLK_PMV_R_CK_GCLK7", - "CLK_PMV_R_CK_GCLK8", - "CLK_PMV_R_CK_GCLK9", - "CLK_PMV_SE2A0_0", - "CLK_PMV_SE2A0_1", - "CLK_PMV_SE2A0_2", - "CLK_PMV_SE2A0_3", - "CLK_PMV_SE2A0_4", - "CLK_PMV_SE2A0_5", - "CLK_PMV_SE2A0_6", - "CLK_PMV_SE2A1_0", - "CLK_PMV_SE2A1_1", - "CLK_PMV_SE2A1_2", - "CLK_PMV_SE2A1_3", - "CLK_PMV_SE2A1_4", - "CLK_PMV_SE2A1_5", - "CLK_PMV_SE2A1_6", - "CLK_PMV_SE2A2_0", - "CLK_PMV_SE2A2_1", - "CLK_PMV_SE2A2_2", - "CLK_PMV_SE2A2_3", - "CLK_PMV_SE2A2_4", - "CLK_PMV_SE2A2_5", - "CLK_PMV_SE2A2_6", - "CLK_PMV_SE2A3_0", - "CLK_PMV_SE2A3_1", - "CLK_PMV_SE2A3_2", - "CLK_PMV_SE2A3_3", - "CLK_PMV_SE2A3_4", - "CLK_PMV_SE2A3_5", - "CLK_PMV_SE2A3_6", - "CLK_PMV_SE4BEG0_0", - "CLK_PMV_SE4BEG0_1", - "CLK_PMV_SE4BEG0_2", - "CLK_PMV_SE4BEG0_3", - "CLK_PMV_SE4BEG0_4", - "CLK_PMV_SE4BEG0_5", - "CLK_PMV_SE4BEG0_6", - "CLK_PMV_SE4BEG1_0", - "CLK_PMV_SE4BEG1_1", - "CLK_PMV_SE4BEG1_2", - "CLK_PMV_SE4BEG1_3", - "CLK_PMV_SE4BEG1_4", - "CLK_PMV_SE4BEG1_5", - "CLK_PMV_SE4BEG1_6", - "CLK_PMV_SE4BEG2_0", - "CLK_PMV_SE4BEG2_1", - "CLK_PMV_SE4BEG2_2", - "CLK_PMV_SE4BEG2_3", - "CLK_PMV_SE4BEG2_4", - "CLK_PMV_SE4BEG2_5", - "CLK_PMV_SE4BEG2_6", - "CLK_PMV_SE4BEG3_0", - "CLK_PMV_SE4BEG3_1", - "CLK_PMV_SE4BEG3_2", - "CLK_PMV_SE4BEG3_3", - "CLK_PMV_SE4BEG3_4", - "CLK_PMV_SE4BEG3_5", - "CLK_PMV_SE4BEG3_6", - "CLK_PMV_SE4C0_0", - "CLK_PMV_SE4C0_1", - "CLK_PMV_SE4C0_2", - "CLK_PMV_SE4C0_3", - "CLK_PMV_SE4C0_4", - "CLK_PMV_SE4C0_5", - "CLK_PMV_SE4C0_6", - "CLK_PMV_SE4C1_0", - "CLK_PMV_SE4C1_1", - "CLK_PMV_SE4C1_2", - "CLK_PMV_SE4C1_3", - "CLK_PMV_SE4C1_4", - "CLK_PMV_SE4C1_5", - "CLK_PMV_SE4C1_6", - "CLK_PMV_SE4C2_0", - "CLK_PMV_SE4C2_1", - "CLK_PMV_SE4C2_2", - "CLK_PMV_SE4C2_3", - "CLK_PMV_SE4C2_4", - "CLK_PMV_SE4C2_5", - "CLK_PMV_SE4C2_6", - "CLK_PMV_SE4C3_0", - "CLK_PMV_SE4C3_1", - "CLK_PMV_SE4C3_2", - "CLK_PMV_SE4C3_3", - "CLK_PMV_SE4C3_4", - "CLK_PMV_SE4C3_5", - "CLK_PMV_SE4C3_6", - "CLK_PMV_SW2A0_0", - "CLK_PMV_SW2A0_1", - "CLK_PMV_SW2A0_2", - "CLK_PMV_SW2A0_3", - "CLK_PMV_SW2A0_4", - "CLK_PMV_SW2A0_5", - "CLK_PMV_SW2A0_6", - "CLK_PMV_SW2A1_0", - "CLK_PMV_SW2A1_1", - "CLK_PMV_SW2A1_2", - "CLK_PMV_SW2A1_3", - "CLK_PMV_SW2A1_4", - "CLK_PMV_SW2A1_5", - "CLK_PMV_SW2A1_6", - "CLK_PMV_SW2A2_0", - "CLK_PMV_SW2A2_1", - "CLK_PMV_SW2A2_2", - "CLK_PMV_SW2A2_3", - "CLK_PMV_SW2A2_4", - "CLK_PMV_SW2A2_5", - "CLK_PMV_SW2A2_6", - "CLK_PMV_SW2A3_0", - "CLK_PMV_SW2A3_1", - "CLK_PMV_SW2A3_2", - "CLK_PMV_SW2A3_3", - "CLK_PMV_SW2A3_4", - "CLK_PMV_SW2A3_5", - "CLK_PMV_SW2A3_6", - "CLK_PMV_SW4A0_0", - "CLK_PMV_SW4A0_1", - "CLK_PMV_SW4A0_2", - "CLK_PMV_SW4A0_3", - "CLK_PMV_SW4A0_4", - "CLK_PMV_SW4A0_5", - "CLK_PMV_SW4A0_6", - "CLK_PMV_SW4A1_0", - "CLK_PMV_SW4A1_1", - "CLK_PMV_SW4A1_2", - "CLK_PMV_SW4A1_3", - "CLK_PMV_SW4A1_4", - "CLK_PMV_SW4A1_5", - "CLK_PMV_SW4A1_6", - "CLK_PMV_SW4A2_0", - "CLK_PMV_SW4A2_1", - "CLK_PMV_SW4A2_2", - "CLK_PMV_SW4A2_3", - "CLK_PMV_SW4A2_4", - "CLK_PMV_SW4A2_5", - "CLK_PMV_SW4A2_6", - "CLK_PMV_SW4A3_0", - "CLK_PMV_SW4A3_1", - "CLK_PMV_SW4A3_2", - "CLK_PMV_SW4A3_3", - "CLK_PMV_SW4A3_4", - "CLK_PMV_SW4A3_5", - "CLK_PMV_SW4A3_6", - "CLK_PMV_SW4END0_0", - "CLK_PMV_SW4END0_1", - "CLK_PMV_SW4END0_2", - "CLK_PMV_SW4END0_3", - "CLK_PMV_SW4END0_4", - "CLK_PMV_SW4END0_5", - "CLK_PMV_SW4END0_6", - "CLK_PMV_SW4END1_0", - "CLK_PMV_SW4END1_1", - "CLK_PMV_SW4END1_2", - "CLK_PMV_SW4END1_3", - "CLK_PMV_SW4END1_4", - "CLK_PMV_SW4END1_5", - "CLK_PMV_SW4END1_6", - "CLK_PMV_SW4END2_0", - "CLK_PMV_SW4END2_1", - "CLK_PMV_SW4END2_2", - "CLK_PMV_SW4END2_3", - "CLK_PMV_SW4END2_4", - "CLK_PMV_SW4END2_5", - "CLK_PMV_SW4END2_6", - "CLK_PMV_SW4END3_0", - "CLK_PMV_SW4END3_1", - "CLK_PMV_SW4END3_2", - "CLK_PMV_SW4END3_3", - "CLK_PMV_SW4END3_4", - "CLK_PMV_SW4END3_5", - "CLK_PMV_SW4END3_6", - "CLK_PMV_WL1END0_0", - "CLK_PMV_WL1END0_1", - "CLK_PMV_WL1END0_2", - "CLK_PMV_WL1END0_3", - "CLK_PMV_WL1END0_4", - "CLK_PMV_WL1END0_5", - "CLK_PMV_WL1END0_6", - "CLK_PMV_WL1END1_0", - "CLK_PMV_WL1END1_1", - "CLK_PMV_WL1END1_2", - "CLK_PMV_WL1END1_3", - "CLK_PMV_WL1END1_4", - "CLK_PMV_WL1END1_5", - "CLK_PMV_WL1END1_6", - "CLK_PMV_WL1END2_0", - "CLK_PMV_WL1END2_1", - "CLK_PMV_WL1END2_2", - "CLK_PMV_WL1END2_3", - "CLK_PMV_WL1END2_4", - "CLK_PMV_WL1END2_5", - "CLK_PMV_WL1END2_6", - "CLK_PMV_WL1END3_0", - "CLK_PMV_WL1END3_1", - "CLK_PMV_WL1END3_2", - "CLK_PMV_WL1END3_3", - "CLK_PMV_WL1END3_4", - "CLK_PMV_WL1END3_5", - "CLK_PMV_WL1END3_6", - "CLK_PMV_WR1END0_0", - "CLK_PMV_WR1END0_1", - "CLK_PMV_WR1END0_2", - "CLK_PMV_WR1END0_3", - "CLK_PMV_WR1END0_4", - "CLK_PMV_WR1END0_5", - "CLK_PMV_WR1END0_6", - "CLK_PMV_WR1END1_0", - "CLK_PMV_WR1END1_1", - "CLK_PMV_WR1END1_2", - "CLK_PMV_WR1END1_3", - "CLK_PMV_WR1END1_4", - "CLK_PMV_WR1END1_5", - "CLK_PMV_WR1END1_6", - "CLK_PMV_WR1END2_0", - "CLK_PMV_WR1END2_1", - "CLK_PMV_WR1END2_2", - "CLK_PMV_WR1END2_3", - "CLK_PMV_WR1END2_4", - "CLK_PMV_WR1END2_5", - "CLK_PMV_WR1END2_6", - "CLK_PMV_WR1END3_0", - "CLK_PMV_WR1END3_1", - "CLK_PMV_WR1END3_2", - "CLK_PMV_WR1END3_3", - "CLK_PMV_WR1END3_4", - "CLK_PMV_WR1END3_5", - "CLK_PMV_WR1END3_6", - "CLK_PMV_WW2A0_0", - "CLK_PMV_WW2A0_1", - "CLK_PMV_WW2A0_2", - "CLK_PMV_WW2A0_3", - "CLK_PMV_WW2A0_4", - "CLK_PMV_WW2A0_5", - "CLK_PMV_WW2A0_6", - "CLK_PMV_WW2A1_0", - "CLK_PMV_WW2A1_1", - "CLK_PMV_WW2A1_2", - "CLK_PMV_WW2A1_3", - "CLK_PMV_WW2A1_4", - "CLK_PMV_WW2A1_5", - "CLK_PMV_WW2A1_6", - "CLK_PMV_WW2A2_0", - "CLK_PMV_WW2A2_1", - "CLK_PMV_WW2A2_2", - "CLK_PMV_WW2A2_3", - "CLK_PMV_WW2A2_4", - "CLK_PMV_WW2A2_5", - "CLK_PMV_WW2A2_6", - "CLK_PMV_WW2A3_0", - "CLK_PMV_WW2A3_1", - "CLK_PMV_WW2A3_2", - "CLK_PMV_WW2A3_3", - "CLK_PMV_WW2A3_4", - "CLK_PMV_WW2A3_5", - "CLK_PMV_WW2A3_6", - "CLK_PMV_WW2END0_0", - "CLK_PMV_WW2END0_1", - "CLK_PMV_WW2END0_2", - "CLK_PMV_WW2END0_3", - "CLK_PMV_WW2END0_4", - "CLK_PMV_WW2END0_5", - "CLK_PMV_WW2END0_6", - "CLK_PMV_WW2END1_0", - "CLK_PMV_WW2END1_1", - "CLK_PMV_WW2END1_2", - "CLK_PMV_WW2END1_3", - "CLK_PMV_WW2END1_4", - "CLK_PMV_WW2END1_5", - "CLK_PMV_WW2END1_6", - "CLK_PMV_WW2END2_0", - "CLK_PMV_WW2END2_1", - "CLK_PMV_WW2END2_2", - "CLK_PMV_WW2END2_3", - "CLK_PMV_WW2END2_4", - "CLK_PMV_WW2END2_5", - "CLK_PMV_WW2END2_6", - "CLK_PMV_WW2END3_0", - "CLK_PMV_WW2END3_1", - "CLK_PMV_WW2END3_2", - "CLK_PMV_WW2END3_3", - "CLK_PMV_WW2END3_4", - "CLK_PMV_WW2END3_5", - "CLK_PMV_WW2END3_6", - "CLK_PMV_WW4A0_0", - "CLK_PMV_WW4A0_1", - "CLK_PMV_WW4A0_2", - "CLK_PMV_WW4A0_3", - "CLK_PMV_WW4A0_4", - "CLK_PMV_WW4A0_5", - "CLK_PMV_WW4A0_6", - "CLK_PMV_WW4A1_0", - "CLK_PMV_WW4A1_1", - "CLK_PMV_WW4A1_2", - "CLK_PMV_WW4A1_3", - "CLK_PMV_WW4A1_4", - "CLK_PMV_WW4A1_5", - "CLK_PMV_WW4A1_6", - "CLK_PMV_WW4A2_0", - "CLK_PMV_WW4A2_1", - "CLK_PMV_WW4A2_2", - "CLK_PMV_WW4A2_3", - "CLK_PMV_WW4A2_4", - "CLK_PMV_WW4A2_5", - "CLK_PMV_WW4A2_6", - "CLK_PMV_WW4A3_0", - "CLK_PMV_WW4A3_1", - "CLK_PMV_WW4A3_2", - "CLK_PMV_WW4A3_3", - "CLK_PMV_WW4A3_4", - "CLK_PMV_WW4A3_5", - "CLK_PMV_WW4A3_6", - "CLK_PMV_WW4B0_0", - "CLK_PMV_WW4B0_1", - "CLK_PMV_WW4B0_2", - "CLK_PMV_WW4B0_3", - "CLK_PMV_WW4B0_4", - "CLK_PMV_WW4B0_5", - "CLK_PMV_WW4B0_6", - "CLK_PMV_WW4B1_0", - "CLK_PMV_WW4B1_1", - "CLK_PMV_WW4B1_2", - "CLK_PMV_WW4B1_3", - "CLK_PMV_WW4B1_4", - "CLK_PMV_WW4B1_5", - "CLK_PMV_WW4B1_6", - "CLK_PMV_WW4B2_0", - "CLK_PMV_WW4B2_1", - "CLK_PMV_WW4B2_2", - "CLK_PMV_WW4B2_3", - "CLK_PMV_WW4B2_4", - "CLK_PMV_WW4B2_5", - "CLK_PMV_WW4B2_6", - "CLK_PMV_WW4B3_0", - "CLK_PMV_WW4B3_1", - "CLK_PMV_WW4B3_2", - "CLK_PMV_WW4B3_3", - "CLK_PMV_WW4B3_4", - "CLK_PMV_WW4B3_5", - "CLK_PMV_WW4B3_6", - "CLK_PMV_WW4C0_0", - "CLK_PMV_WW4C0_1", - "CLK_PMV_WW4C0_2", - "CLK_PMV_WW4C0_3", - "CLK_PMV_WW4C0_4", - "CLK_PMV_WW4C0_5", - "CLK_PMV_WW4C0_6", - "CLK_PMV_WW4C1_0", - "CLK_PMV_WW4C1_1", - "CLK_PMV_WW4C1_2", - "CLK_PMV_WW4C1_3", - "CLK_PMV_WW4C1_4", - "CLK_PMV_WW4C1_5", - "CLK_PMV_WW4C1_6", - "CLK_PMV_WW4C2_0", - "CLK_PMV_WW4C2_1", - "CLK_PMV_WW4C2_2", - "CLK_PMV_WW4C2_3", - "CLK_PMV_WW4C2_4", - "CLK_PMV_WW4C2_5", - "CLK_PMV_WW4C2_6", - "CLK_PMV_WW4C3_0", - "CLK_PMV_WW4C3_1", - "CLK_PMV_WW4C3_2", - "CLK_PMV_WW4C3_3", - "CLK_PMV_WW4C3_4", - "CLK_PMV_WW4C3_5", - "CLK_PMV_WW4C3_6", - "CLK_PMV_WW4END0_0", - "CLK_PMV_WW4END0_1", - "CLK_PMV_WW4END0_2", - "CLK_PMV_WW4END0_3", - "CLK_PMV_WW4END0_4", - "CLK_PMV_WW4END0_5", - "CLK_PMV_WW4END0_6", - "CLK_PMV_WW4END1_0", - "CLK_PMV_WW4END1_1", - "CLK_PMV_WW4END1_2", - "CLK_PMV_WW4END1_3", - "CLK_PMV_WW4END1_4", - "CLK_PMV_WW4END1_5", - "CLK_PMV_WW4END1_6", - "CLK_PMV_WW4END2_0", - "CLK_PMV_WW4END2_1", - "CLK_PMV_WW4END2_2", - "CLK_PMV_WW4END2_3", - "CLK_PMV_WW4END2_4", - "CLK_PMV_WW4END2_5", - "CLK_PMV_WW4END2_6", - "CLK_PMV_WW4END3_0", - "CLK_PMV_WW4END3_1", - "CLK_PMV_WW4END3_2", - "CLK_PMV_WW4END3_3", - "CLK_PMV_WW4END3_4", - "CLK_PMV_WW4END3_5", - "CLK_PMV_WW4END3_6" - ] + "wires": { + "CLK_PMV_A0": null, + "CLK_PMV_A1": null, + "CLK_PMV_A2": null, + "CLK_PMV_A3": null, + "CLK_PMV_A4": null, + "CLK_PMV_A5": null, + "CLK_PMV_BYP0_0": null, + "CLK_PMV_BYP0_1": null, + "CLK_PMV_BYP0_2": null, + "CLK_PMV_BYP0_3": null, + "CLK_PMV_BYP0_4": null, + "CLK_PMV_BYP0_5": null, + "CLK_PMV_BYP0_6": null, + "CLK_PMV_BYP1_0": null, + "CLK_PMV_BYP1_1": null, + "CLK_PMV_BYP1_2": null, + "CLK_PMV_BYP1_3": null, + "CLK_PMV_BYP1_4": null, + "CLK_PMV_BYP1_5": null, + "CLK_PMV_BYP1_6": null, + "CLK_PMV_BYP2_0": null, + "CLK_PMV_BYP2_1": null, + "CLK_PMV_BYP2_2": null, + "CLK_PMV_BYP2_3": null, + "CLK_PMV_BYP2_4": null, + "CLK_PMV_BYP2_5": null, + "CLK_PMV_BYP2_6": null, + "CLK_PMV_BYP3_0": null, + "CLK_PMV_BYP3_1": null, + "CLK_PMV_BYP3_2": null, + "CLK_PMV_BYP3_3": null, + "CLK_PMV_BYP3_4": null, + "CLK_PMV_BYP3_5": null, + "CLK_PMV_BYP3_6": null, + "CLK_PMV_BYP4_0": null, + "CLK_PMV_BYP4_1": null, + "CLK_PMV_BYP4_2": null, + "CLK_PMV_BYP4_3": null, + "CLK_PMV_BYP4_4": null, + "CLK_PMV_BYP4_5": null, + "CLK_PMV_BYP4_6": null, + "CLK_PMV_BYP5_0": null, + "CLK_PMV_BYP5_1": null, + "CLK_PMV_BYP5_2": null, + "CLK_PMV_BYP5_3": null, + "CLK_PMV_BYP5_4": null, + "CLK_PMV_BYP5_5": null, + "CLK_PMV_BYP5_6": null, + "CLK_PMV_BYP6_0": null, + "CLK_PMV_BYP6_1": null, + "CLK_PMV_BYP6_2": null, + "CLK_PMV_BYP6_3": null, + "CLK_PMV_BYP6_4": null, + "CLK_PMV_BYP6_5": null, + "CLK_PMV_BYP6_6": null, + "CLK_PMV_BYP7_0": null, + "CLK_PMV_BYP7_1": null, + "CLK_PMV_BYP7_2": null, + "CLK_PMV_BYP7_3": null, + "CLK_PMV_BYP7_4": null, + "CLK_PMV_BYP7_5": null, + "CLK_PMV_BYP7_6": null, + "CLK_PMV_CK_BUFG_CASC0": null, + "CLK_PMV_CK_BUFG_CASC1": null, + "CLK_PMV_CK_BUFG_CASC10": null, + "CLK_PMV_CK_BUFG_CASC11": null, + "CLK_PMV_CK_BUFG_CASC12": null, + "CLK_PMV_CK_BUFG_CASC13": null, + "CLK_PMV_CK_BUFG_CASC14": null, + "CLK_PMV_CK_BUFG_CASC15": null, + "CLK_PMV_CK_BUFG_CASC16": null, + "CLK_PMV_CK_BUFG_CASC17": null, + "CLK_PMV_CK_BUFG_CASC18": null, + "CLK_PMV_CK_BUFG_CASC19": null, + "CLK_PMV_CK_BUFG_CASC2": null, + "CLK_PMV_CK_BUFG_CASC20": null, + "CLK_PMV_CK_BUFG_CASC21": null, + "CLK_PMV_CK_BUFG_CASC22": null, + "CLK_PMV_CK_BUFG_CASC23": null, + "CLK_PMV_CK_BUFG_CASC24": null, + "CLK_PMV_CK_BUFG_CASC25": null, + "CLK_PMV_CK_BUFG_CASC26": null, + "CLK_PMV_CK_BUFG_CASC27": null, + "CLK_PMV_CK_BUFG_CASC28": null, + "CLK_PMV_CK_BUFG_CASC29": null, + "CLK_PMV_CK_BUFG_CASC3": null, + "CLK_PMV_CK_BUFG_CASC30": null, + "CLK_PMV_CK_BUFG_CASC31": null, + "CLK_PMV_CK_BUFG_CASC4": null, + "CLK_PMV_CK_BUFG_CASC5": null, + "CLK_PMV_CK_BUFG_CASC6": null, + "CLK_PMV_CK_BUFG_CASC7": null, + "CLK_PMV_CK_BUFG_CASC8": null, + "CLK_PMV_CK_BUFG_CASC9": null, + "CLK_PMV_CK_GCLK0": null, + "CLK_PMV_CK_GCLK1": null, + "CLK_PMV_CK_GCLK10": null, + "CLK_PMV_CK_GCLK11": null, + "CLK_PMV_CK_GCLK12": null, + "CLK_PMV_CK_GCLK13": null, + "CLK_PMV_CK_GCLK14": null, + "CLK_PMV_CK_GCLK15": null, + "CLK_PMV_CK_GCLK16": null, + "CLK_PMV_CK_GCLK17": null, + "CLK_PMV_CK_GCLK18": null, + "CLK_PMV_CK_GCLK19": null, + "CLK_PMV_CK_GCLK2": null, + "CLK_PMV_CK_GCLK20": null, + "CLK_PMV_CK_GCLK21": null, + "CLK_PMV_CK_GCLK22": null, + "CLK_PMV_CK_GCLK23": null, + "CLK_PMV_CK_GCLK24": null, + "CLK_PMV_CK_GCLK25": null, + "CLK_PMV_CK_GCLK26": null, + "CLK_PMV_CK_GCLK27": null, + "CLK_PMV_CK_GCLK28": null, + "CLK_PMV_CK_GCLK29": null, + "CLK_PMV_CK_GCLK3": null, + "CLK_PMV_CK_GCLK30": null, + "CLK_PMV_CK_GCLK31": null, + "CLK_PMV_CK_GCLK4": null, + "CLK_PMV_CK_GCLK5": null, + "CLK_PMV_CK_GCLK6": null, + "CLK_PMV_CK_GCLK7": null, + "CLK_PMV_CK_GCLK8": null, + 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"CLK_PMV_EE4BEG0_4": null, + "CLK_PMV_EE4BEG0_5": null, + "CLK_PMV_EE4BEG0_6": null, + "CLK_PMV_EE4BEG1_0": null, + "CLK_PMV_EE4BEG1_1": null, + "CLK_PMV_EE4BEG1_2": null, + "CLK_PMV_EE4BEG1_3": null, + "CLK_PMV_EE4BEG1_4": null, + "CLK_PMV_EE4BEG1_5": null, + "CLK_PMV_EE4BEG1_6": null, + "CLK_PMV_EE4BEG2_0": null, + "CLK_PMV_EE4BEG2_1": null, + "CLK_PMV_EE4BEG2_2": null, + "CLK_PMV_EE4BEG2_3": null, + "CLK_PMV_EE4BEG2_4": null, + "CLK_PMV_EE4BEG2_5": null, + "CLK_PMV_EE4BEG2_6": null, + "CLK_PMV_EE4BEG3_0": null, + "CLK_PMV_EE4BEG3_1": null, + "CLK_PMV_EE4BEG3_2": null, + "CLK_PMV_EE4BEG3_3": null, + "CLK_PMV_EE4BEG3_4": null, + "CLK_PMV_EE4BEG3_5": null, + "CLK_PMV_EE4BEG3_6": null, + "CLK_PMV_EE4C0_0": null, + "CLK_PMV_EE4C0_1": null, + "CLK_PMV_EE4C0_2": null, + "CLK_PMV_EE4C0_3": null, + "CLK_PMV_EE4C0_4": null, + "CLK_PMV_EE4C0_5": null, + "CLK_PMV_EE4C0_6": null, + "CLK_PMV_EE4C1_0": null, + "CLK_PMV_EE4C1_1": null, + "CLK_PMV_EE4C1_2": null, + "CLK_PMV_EE4C1_3": null, + "CLK_PMV_EE4C1_4": null, + "CLK_PMV_EE4C1_5": null, + "CLK_PMV_EE4C1_6": null, + "CLK_PMV_EE4C2_0": null, + "CLK_PMV_EE4C2_1": null, + "CLK_PMV_EE4C2_2": null, + "CLK_PMV_EE4C2_3": null, + "CLK_PMV_EE4C2_4": null, + "CLK_PMV_EE4C2_5": null, + "CLK_PMV_EE4C2_6": null, + "CLK_PMV_EE4C3_0": null, + "CLK_PMV_EE4C3_1": null, + "CLK_PMV_EE4C3_2": null, + "CLK_PMV_EE4C3_3": null, + "CLK_PMV_EE4C3_4": null, + "CLK_PMV_EE4C3_5": null, + "CLK_PMV_EE4C3_6": null, + "CLK_PMV_EL1BEG0_0": null, + "CLK_PMV_EL1BEG0_1": null, + "CLK_PMV_EL1BEG0_2": null, + "CLK_PMV_EL1BEG0_3": null, + "CLK_PMV_EL1BEG0_4": null, + "CLK_PMV_EL1BEG0_5": null, + "CLK_PMV_EL1BEG0_6": null, + "CLK_PMV_EL1BEG1_0": null, + "CLK_PMV_EL1BEG1_1": null, + "CLK_PMV_EL1BEG1_2": null, + "CLK_PMV_EL1BEG1_3": null, + "CLK_PMV_EL1BEG1_4": null, + "CLK_PMV_EL1BEG1_5": null, + "CLK_PMV_EL1BEG1_6": null, + "CLK_PMV_EL1BEG2_0": null, + "CLK_PMV_EL1BEG2_1": null, + "CLK_PMV_EL1BEG2_2": null, + "CLK_PMV_EL1BEG2_3": null, + "CLK_PMV_EL1BEG2_4": null, + "CLK_PMV_EL1BEG2_5": null, + "CLK_PMV_EL1BEG2_6": null, + "CLK_PMV_EL1BEG3_0": null, + "CLK_PMV_EL1BEG3_1": null, + "CLK_PMV_EL1BEG3_2": null, + "CLK_PMV_EL1BEG3_3": null, + "CLK_PMV_EL1BEG3_4": null, + "CLK_PMV_EL1BEG3_5": null, + "CLK_PMV_EL1BEG3_6": null, + "CLK_PMV_EN": null, + "CLK_PMV_ER1BEG0_0": null, + "CLK_PMV_ER1BEG0_1": null, + "CLK_PMV_ER1BEG0_2": null, + "CLK_PMV_ER1BEG0_3": null, + "CLK_PMV_ER1BEG0_4": null, + "CLK_PMV_ER1BEG0_5": null, + "CLK_PMV_ER1BEG0_6": null, + "CLK_PMV_ER1BEG1_0": null, + "CLK_PMV_ER1BEG1_1": null, + "CLK_PMV_ER1BEG1_2": null, + "CLK_PMV_ER1BEG1_3": null, + "CLK_PMV_ER1BEG1_4": null, + "CLK_PMV_ER1BEG1_5": null, + "CLK_PMV_ER1BEG1_6": null, + "CLK_PMV_ER1BEG2_0": null, + "CLK_PMV_ER1BEG2_1": null, + "CLK_PMV_ER1BEG2_2": null, + "CLK_PMV_ER1BEG2_3": null, + "CLK_PMV_ER1BEG2_4": null, + "CLK_PMV_ER1BEG2_5": null, + "CLK_PMV_ER1BEG2_6": null, + "CLK_PMV_ER1BEG3_0": null, + "CLK_PMV_ER1BEG3_1": null, + "CLK_PMV_ER1BEG3_2": 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null, + "CLK_PMV_FAN4_6": null, + "CLK_PMV_FAN5_0": null, + "CLK_PMV_FAN5_1": null, + "CLK_PMV_FAN5_2": null, + "CLK_PMV_FAN5_3": null, + "CLK_PMV_FAN5_4": null, + "CLK_PMV_FAN5_5": null, + "CLK_PMV_FAN5_6": null, + "CLK_PMV_FAN6_0": null, + "CLK_PMV_FAN6_1": null, + "CLK_PMV_FAN6_2": null, + "CLK_PMV_FAN6_3": null, + "CLK_PMV_FAN6_4": null, + "CLK_PMV_FAN6_5": null, + "CLK_PMV_FAN6_6": null, + "CLK_PMV_FAN7_0": null, + "CLK_PMV_FAN7_1": null, + "CLK_PMV_FAN7_2": null, + "CLK_PMV_FAN7_3": null, + "CLK_PMV_FAN7_4": null, + "CLK_PMV_FAN7_5": null, + "CLK_PMV_FAN7_6": null, + "CLK_PMV_IMUX0_0": null, + "CLK_PMV_IMUX0_1": null, + "CLK_PMV_IMUX0_2": null, + "CLK_PMV_IMUX0_3": null, + "CLK_PMV_IMUX0_4": null, + "CLK_PMV_IMUX0_5": null, + "CLK_PMV_IMUX0_6": null, + "CLK_PMV_IMUX10_0": null, + "CLK_PMV_IMUX10_1": null, + "CLK_PMV_IMUX10_2": null, + "CLK_PMV_IMUX10_3": null, + "CLK_PMV_IMUX10_4": null, + "CLK_PMV_IMUX10_5": null, + "CLK_PMV_IMUX10_6": null, + "CLK_PMV_IMUX11_0": null, + "CLK_PMV_IMUX11_1": null, + "CLK_PMV_IMUX11_2": null, + "CLK_PMV_IMUX11_3": null, + "CLK_PMV_IMUX11_4": null, + "CLK_PMV_IMUX11_5": null, + "CLK_PMV_IMUX11_6": null, + "CLK_PMV_IMUX12_0": null, + "CLK_PMV_IMUX12_1": null, + "CLK_PMV_IMUX12_2": null, + "CLK_PMV_IMUX12_3": null, + "CLK_PMV_IMUX12_4": null, + "CLK_PMV_IMUX12_5": null, + "CLK_PMV_IMUX12_6": null, + "CLK_PMV_IMUX13_0": null, + "CLK_PMV_IMUX13_1": null, + "CLK_PMV_IMUX13_2": null, + "CLK_PMV_IMUX13_3": null, + "CLK_PMV_IMUX13_4": null, + "CLK_PMV_IMUX13_5": null, + "CLK_PMV_IMUX13_6": null, + "CLK_PMV_IMUX14_0": null, + "CLK_PMV_IMUX14_1": null, + "CLK_PMV_IMUX14_2": null, + "CLK_PMV_IMUX14_3": null, + "CLK_PMV_IMUX14_4": null, + "CLK_PMV_IMUX14_5": null, + "CLK_PMV_IMUX14_6": null, + "CLK_PMV_IMUX15_0": null, + "CLK_PMV_IMUX15_1": null, + "CLK_PMV_IMUX15_2": null, + "CLK_PMV_IMUX15_3": null, + "CLK_PMV_IMUX15_4": null, + "CLK_PMV_IMUX15_5": null, + "CLK_PMV_IMUX15_6": null, + "CLK_PMV_IMUX16_0": null, + "CLK_PMV_IMUX16_1": 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null, + "CLK_PMV_IMUX20_3": null, + "CLK_PMV_IMUX20_4": null, + "CLK_PMV_IMUX20_5": null, + "CLK_PMV_IMUX20_6": null, + "CLK_PMV_IMUX21_0": null, + "CLK_PMV_IMUX21_1": null, + "CLK_PMV_IMUX21_2": null, + "CLK_PMV_IMUX21_3": null, + "CLK_PMV_IMUX21_4": null, + "CLK_PMV_IMUX21_5": null, + "CLK_PMV_IMUX21_6": null, + "CLK_PMV_IMUX22_0": null, + "CLK_PMV_IMUX22_1": null, + "CLK_PMV_IMUX22_2": null, + "CLK_PMV_IMUX22_3": null, + "CLK_PMV_IMUX22_4": null, + "CLK_PMV_IMUX22_5": null, + "CLK_PMV_IMUX22_6": null, + "CLK_PMV_IMUX23_0": null, + "CLK_PMV_IMUX23_1": null, + "CLK_PMV_IMUX23_2": null, + "CLK_PMV_IMUX23_3": null, + "CLK_PMV_IMUX23_4": null, + "CLK_PMV_IMUX23_5": null, + "CLK_PMV_IMUX23_6": null, + "CLK_PMV_IMUX24_0": null, + "CLK_PMV_IMUX24_1": null, + "CLK_PMV_IMUX24_2": null, + "CLK_PMV_IMUX24_3": null, + "CLK_PMV_IMUX24_4": null, + "CLK_PMV_IMUX24_5": null, + "CLK_PMV_IMUX24_6": null, + "CLK_PMV_IMUX25_0": null, + "CLK_PMV_IMUX25_1": null, + "CLK_PMV_IMUX25_2": null, + "CLK_PMV_IMUX25_3": null, + "CLK_PMV_IMUX25_4": null, + "CLK_PMV_IMUX25_5": null, + "CLK_PMV_IMUX25_6": null, + "CLK_PMV_IMUX26_0": null, + "CLK_PMV_IMUX26_1": null, + "CLK_PMV_IMUX26_2": null, + "CLK_PMV_IMUX26_3": null, + "CLK_PMV_IMUX26_4": null, + "CLK_PMV_IMUX26_5": null, + "CLK_PMV_IMUX26_6": null, + "CLK_PMV_IMUX27_0": null, + "CLK_PMV_IMUX27_1": null, + "CLK_PMV_IMUX27_2": null, + "CLK_PMV_IMUX27_3": null, + "CLK_PMV_IMUX27_4": null, + "CLK_PMV_IMUX27_5": null, + "CLK_PMV_IMUX27_6": null, + "CLK_PMV_IMUX28_0": null, + "CLK_PMV_IMUX28_1": null, + "CLK_PMV_IMUX28_2": null, + "CLK_PMV_IMUX28_3": null, + "CLK_PMV_IMUX28_4": null, + "CLK_PMV_IMUX28_5": null, + "CLK_PMV_IMUX28_6": null, + "CLK_PMV_IMUX29_0": null, + "CLK_PMV_IMUX29_1": null, + "CLK_PMV_IMUX29_2": null, + "CLK_PMV_IMUX29_3": null, + "CLK_PMV_IMUX29_4": null, + "CLK_PMV_IMUX29_5": null, + "CLK_PMV_IMUX29_6": null, + "CLK_PMV_IMUX2_0": null, + "CLK_PMV_IMUX2_1": null, + "CLK_PMV_IMUX2_2": null, + "CLK_PMV_IMUX2_3": null, + "CLK_PMV_IMUX2_4": null, + "CLK_PMV_IMUX2_5": null, + "CLK_PMV_IMUX2_6": null, + "CLK_PMV_IMUX30_0": null, + "CLK_PMV_IMUX30_1": null, + "CLK_PMV_IMUX30_2": null, + "CLK_PMV_IMUX30_3": null, + "CLK_PMV_IMUX30_4": null, + "CLK_PMV_IMUX30_5": null, + "CLK_PMV_IMUX30_6": null, + "CLK_PMV_IMUX31_0": null, + "CLK_PMV_IMUX31_1": null, + "CLK_PMV_IMUX31_2": null, + "CLK_PMV_IMUX31_3": null, + "CLK_PMV_IMUX31_4": null, + "CLK_PMV_IMUX31_5": null, + "CLK_PMV_IMUX31_6": null, + "CLK_PMV_IMUX32_0": null, + "CLK_PMV_IMUX32_1": null, + "CLK_PMV_IMUX32_2": null, + "CLK_PMV_IMUX32_3": null, + "CLK_PMV_IMUX32_4": null, + "CLK_PMV_IMUX32_5": null, + "CLK_PMV_IMUX32_6": null, + "CLK_PMV_IMUX33_0": null, + "CLK_PMV_IMUX33_1": null, + "CLK_PMV_IMUX33_2": null, + "CLK_PMV_IMUX33_3": null, + "CLK_PMV_IMUX33_4": null, + "CLK_PMV_IMUX33_5": null, + "CLK_PMV_IMUX33_6": null, + "CLK_PMV_IMUX34_0": null, + "CLK_PMV_IMUX34_1": null, + "CLK_PMV_IMUX34_2": null, + "CLK_PMV_IMUX34_3": null, + "CLK_PMV_IMUX34_4": null, + "CLK_PMV_IMUX34_5": null, + "CLK_PMV_IMUX34_6": null, + "CLK_PMV_IMUX35_0": null, + "CLK_PMV_IMUX35_1": null, + "CLK_PMV_IMUX35_2": null, + "CLK_PMV_IMUX35_3": null, + "CLK_PMV_IMUX35_4": null, + "CLK_PMV_IMUX35_5": null, + "CLK_PMV_IMUX35_6": null, + "CLK_PMV_IMUX36_0": null, + "CLK_PMV_IMUX36_1": null, + "CLK_PMV_IMUX36_2": null, + "CLK_PMV_IMUX36_3": null, + "CLK_PMV_IMUX36_4": null, + "CLK_PMV_IMUX36_5": null, + "CLK_PMV_IMUX36_6": null, + "CLK_PMV_IMUX37_0": null, + "CLK_PMV_IMUX37_1": null, + "CLK_PMV_IMUX37_2": null, + "CLK_PMV_IMUX37_3": null, + "CLK_PMV_IMUX37_4": null, + "CLK_PMV_IMUX37_5": null, + "CLK_PMV_IMUX37_6": null, + "CLK_PMV_IMUX38_0": null, + "CLK_PMV_IMUX38_1": null, + "CLK_PMV_IMUX38_2": null, + "CLK_PMV_IMUX38_3": null, + "CLK_PMV_IMUX38_4": null, + "CLK_PMV_IMUX38_5": null, + "CLK_PMV_IMUX38_6": null, + "CLK_PMV_IMUX39_0": null, + "CLK_PMV_IMUX39_1": null, + "CLK_PMV_IMUX39_2": null, + "CLK_PMV_IMUX39_3": null, + "CLK_PMV_IMUX39_4": null, + "CLK_PMV_IMUX39_5": null, + "CLK_PMV_IMUX39_6": null, + "CLK_PMV_IMUX3_0": null, + "CLK_PMV_IMUX3_1": null, + "CLK_PMV_IMUX3_2": null, + "CLK_PMV_IMUX3_3": null, + "CLK_PMV_IMUX3_4": null, + "CLK_PMV_IMUX3_5": null, + "CLK_PMV_IMUX3_6": null, + "CLK_PMV_IMUX40_0": null, + "CLK_PMV_IMUX40_1": null, + "CLK_PMV_IMUX40_2": null, + "CLK_PMV_IMUX40_3": null, + "CLK_PMV_IMUX40_4": null, + "CLK_PMV_IMUX40_5": null, + "CLK_PMV_IMUX40_6": null, + "CLK_PMV_IMUX41_0": null, + "CLK_PMV_IMUX41_1": null, + "CLK_PMV_IMUX41_2": null, + "CLK_PMV_IMUX41_3": null, + "CLK_PMV_IMUX41_4": null, + "CLK_PMV_IMUX41_5": null, + "CLK_PMV_IMUX41_6": null, + "CLK_PMV_IMUX42_0": null, + "CLK_PMV_IMUX42_1": null, + "CLK_PMV_IMUX42_2": null, + "CLK_PMV_IMUX42_3": null, + "CLK_PMV_IMUX42_4": null, + "CLK_PMV_IMUX42_5": null, + "CLK_PMV_IMUX42_6": null, + "CLK_PMV_IMUX43_0": null, + "CLK_PMV_IMUX43_1": null, + "CLK_PMV_IMUX43_2": null, + "CLK_PMV_IMUX43_3": null, + "CLK_PMV_IMUX43_4": null, + "CLK_PMV_IMUX43_5": null, + "CLK_PMV_IMUX43_6": null, + "CLK_PMV_IMUX44_0": null, + "CLK_PMV_IMUX44_1": null, + "CLK_PMV_IMUX44_2": null, + "CLK_PMV_IMUX44_3": null, + "CLK_PMV_IMUX44_4": null, + "CLK_PMV_IMUX44_5": null, + "CLK_PMV_IMUX44_6": null, + "CLK_PMV_IMUX45_0": null, + "CLK_PMV_IMUX45_1": null, + "CLK_PMV_IMUX45_2": null, + "CLK_PMV_IMUX45_3": null, + "CLK_PMV_IMUX45_4": null, + "CLK_PMV_IMUX45_5": null, + "CLK_PMV_IMUX45_6": null, + "CLK_PMV_IMUX46_0": null, + "CLK_PMV_IMUX46_1": null, + "CLK_PMV_IMUX46_2": null, + "CLK_PMV_IMUX46_3": null, + "CLK_PMV_IMUX46_4": null, + "CLK_PMV_IMUX46_5": null, + "CLK_PMV_IMUX46_6": null, + "CLK_PMV_IMUX47_0": null, + "CLK_PMV_IMUX47_1": null, + "CLK_PMV_IMUX47_2": null, + "CLK_PMV_IMUX47_3": null, + "CLK_PMV_IMUX47_4": null, + "CLK_PMV_IMUX47_5": null, + "CLK_PMV_IMUX47_6": null, + "CLK_PMV_IMUX4_0": null, + "CLK_PMV_IMUX4_1": null, + "CLK_PMV_IMUX4_2": null, + "CLK_PMV_IMUX4_3": null, + "CLK_PMV_IMUX4_4": null, + "CLK_PMV_IMUX4_5": null, + "CLK_PMV_IMUX4_6": null, + "CLK_PMV_IMUX5_0": null, + "CLK_PMV_IMUX5_1": null, + "CLK_PMV_IMUX5_2": null, + "CLK_PMV_IMUX5_3": null, + "CLK_PMV_IMUX5_4": null, + "CLK_PMV_IMUX5_5": null, + "CLK_PMV_IMUX5_6": null, + "CLK_PMV_IMUX6_0": null, + "CLK_PMV_IMUX6_1": null, + "CLK_PMV_IMUX6_2": null, + "CLK_PMV_IMUX6_3": null, + "CLK_PMV_IMUX6_4": null, + "CLK_PMV_IMUX6_5": null, + "CLK_PMV_IMUX6_6": null, + "CLK_PMV_IMUX7_0": null, + "CLK_PMV_IMUX7_1": null, + "CLK_PMV_IMUX7_2": null, + "CLK_PMV_IMUX7_3": null, + "CLK_PMV_IMUX7_4": null, + "CLK_PMV_IMUX7_5": null, + "CLK_PMV_IMUX7_6": null, + "CLK_PMV_IMUX8_0": null, + "CLK_PMV_IMUX8_1": null, + "CLK_PMV_IMUX8_2": null, + "CLK_PMV_IMUX8_3": null, + "CLK_PMV_IMUX8_4": null, + "CLK_PMV_IMUX8_5": null, + "CLK_PMV_IMUX8_6": null, + "CLK_PMV_IMUX9_0": null, + "CLK_PMV_IMUX9_1": null, + "CLK_PMV_IMUX9_2": null, + "CLK_PMV_IMUX9_3": null, + "CLK_PMV_IMUX9_4": null, + "CLK_PMV_IMUX9_5": null, + "CLK_PMV_IMUX9_6": null, + "CLK_PMV_LH10_0": null, + "CLK_PMV_LH10_1": null, + "CLK_PMV_LH10_2": null, + "CLK_PMV_LH10_3": null, + "CLK_PMV_LH10_4": null, + "CLK_PMV_LH10_5": null, + "CLK_PMV_LH10_6": null, + "CLK_PMV_LH11_0": null, + "CLK_PMV_LH11_1": null, + "CLK_PMV_LH11_2": null, + "CLK_PMV_LH11_3": null, + "CLK_PMV_LH11_4": null, + "CLK_PMV_LH11_5": null, + "CLK_PMV_LH11_6": null, + "CLK_PMV_LH12_0": null, + "CLK_PMV_LH12_1": null, + "CLK_PMV_LH12_2": null, + "CLK_PMV_LH12_3": null, + "CLK_PMV_LH12_4": null, + "CLK_PMV_LH12_5": null, + "CLK_PMV_LH12_6": null, + "CLK_PMV_LH1_0": null, + "CLK_PMV_LH1_1": null, + "CLK_PMV_LH1_2": null, + "CLK_PMV_LH1_3": null, + "CLK_PMV_LH1_4": null, + "CLK_PMV_LH1_5": null, + "CLK_PMV_LH1_6": null, + "CLK_PMV_LH2_0": null, + "CLK_PMV_LH2_1": null, + "CLK_PMV_LH2_2": null, + "CLK_PMV_LH2_3": null, + "CLK_PMV_LH2_4": null, + "CLK_PMV_LH2_5": null, + "CLK_PMV_LH2_6": null, + "CLK_PMV_LH3_0": null, + "CLK_PMV_LH3_1": null, + "CLK_PMV_LH3_2": null, + "CLK_PMV_LH3_3": null, + "CLK_PMV_LH3_4": null, + "CLK_PMV_LH3_5": null, + "CLK_PMV_LH3_6": null, + "CLK_PMV_LH4_0": null, + "CLK_PMV_LH4_1": null, + "CLK_PMV_LH4_2": null, + "CLK_PMV_LH4_3": null, + "CLK_PMV_LH4_4": null, + "CLK_PMV_LH4_5": null, + "CLK_PMV_LH4_6": null, + "CLK_PMV_LH5_0": null, + "CLK_PMV_LH5_1": null, + "CLK_PMV_LH5_2": null, + "CLK_PMV_LH5_3": null, + "CLK_PMV_LH5_4": null, + "CLK_PMV_LH5_5": null, + "CLK_PMV_LH5_6": null, + "CLK_PMV_LH6_0": null, + "CLK_PMV_LH6_1": null, + "CLK_PMV_LH6_2": null, + "CLK_PMV_LH6_3": null, + "CLK_PMV_LH6_4": null, + "CLK_PMV_LH6_5": null, + "CLK_PMV_LH6_6": null, + "CLK_PMV_LH7_0": null, + "CLK_PMV_LH7_1": null, + "CLK_PMV_LH7_2": null, + "CLK_PMV_LH7_3": null, + "CLK_PMV_LH7_4": null, + "CLK_PMV_LH7_5": null, + "CLK_PMV_LH7_6": null, + "CLK_PMV_LH8_0": null, + "CLK_PMV_LH8_1": null, + "CLK_PMV_LH8_2": null, + "CLK_PMV_LH8_3": null, + "CLK_PMV_LH8_4": null, + "CLK_PMV_LH8_5": null, + "CLK_PMV_LH8_6": null, + "CLK_PMV_LH9_0": null, + "CLK_PMV_LH9_1": null, + "CLK_PMV_LH9_2": null, + "CLK_PMV_LH9_3": null, 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"CLK_PMV_NW2A2_2": null, + "CLK_PMV_NW2A2_3": null, + "CLK_PMV_NW2A2_4": null, + "CLK_PMV_NW2A2_5": null, + "CLK_PMV_NW2A2_6": null, + "CLK_PMV_NW2A3_0": null, + "CLK_PMV_NW2A3_1": null, + "CLK_PMV_NW2A3_2": null, + "CLK_PMV_NW2A3_3": null, + "CLK_PMV_NW2A3_4": null, + "CLK_PMV_NW2A3_5": null, + "CLK_PMV_NW2A3_6": null, + "CLK_PMV_NW4A0_0": null, + "CLK_PMV_NW4A0_1": null, + "CLK_PMV_NW4A0_2": null, + "CLK_PMV_NW4A0_3": null, + "CLK_PMV_NW4A0_4": null, + "CLK_PMV_NW4A0_5": null, + "CLK_PMV_NW4A0_6": null, + "CLK_PMV_NW4A1_0": null, + "CLK_PMV_NW4A1_1": null, + "CLK_PMV_NW4A1_2": null, + "CLK_PMV_NW4A1_3": null, + "CLK_PMV_NW4A1_4": null, + "CLK_PMV_NW4A1_5": null, + "CLK_PMV_NW4A1_6": null, + "CLK_PMV_NW4A2_0": null, + "CLK_PMV_NW4A2_1": null, + "CLK_PMV_NW4A2_2": null, + "CLK_PMV_NW4A2_3": null, + "CLK_PMV_NW4A2_4": null, + "CLK_PMV_NW4A2_5": null, + "CLK_PMV_NW4A2_6": null, + "CLK_PMV_NW4A3_0": null, + "CLK_PMV_NW4A3_1": null, + "CLK_PMV_NW4A3_2": null, + "CLK_PMV_NW4A3_3": null, + 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"CLK_PMV_R_CK_BUFG_CASC1": null, + "CLK_PMV_R_CK_BUFG_CASC10": null, + "CLK_PMV_R_CK_BUFG_CASC11": null, + "CLK_PMV_R_CK_BUFG_CASC12": null, + "CLK_PMV_R_CK_BUFG_CASC13": null, + "CLK_PMV_R_CK_BUFG_CASC14": null, + "CLK_PMV_R_CK_BUFG_CASC15": null, + "CLK_PMV_R_CK_BUFG_CASC16": null, + "CLK_PMV_R_CK_BUFG_CASC17": null, + "CLK_PMV_R_CK_BUFG_CASC18": null, + "CLK_PMV_R_CK_BUFG_CASC19": null, + "CLK_PMV_R_CK_BUFG_CASC2": null, + "CLK_PMV_R_CK_BUFG_CASC20": null, + "CLK_PMV_R_CK_BUFG_CASC21": null, + "CLK_PMV_R_CK_BUFG_CASC22": null, + "CLK_PMV_R_CK_BUFG_CASC23": null, + "CLK_PMV_R_CK_BUFG_CASC24": null, + "CLK_PMV_R_CK_BUFG_CASC25": null, + "CLK_PMV_R_CK_BUFG_CASC26": null, + "CLK_PMV_R_CK_BUFG_CASC27": null, + "CLK_PMV_R_CK_BUFG_CASC28": null, + "CLK_PMV_R_CK_BUFG_CASC29": null, + "CLK_PMV_R_CK_BUFG_CASC3": null, + "CLK_PMV_R_CK_BUFG_CASC30": null, + "CLK_PMV_R_CK_BUFG_CASC31": null, + "CLK_PMV_R_CK_BUFG_CASC4": null, + "CLK_PMV_R_CK_BUFG_CASC5": null, + "CLK_PMV_R_CK_BUFG_CASC6": null, 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"CLK_PMV_R_CK_GCLK7": null, + "CLK_PMV_R_CK_GCLK8": null, + "CLK_PMV_R_CK_GCLK9": null, + "CLK_PMV_SE2A0_0": null, + "CLK_PMV_SE2A0_1": null, + "CLK_PMV_SE2A0_2": null, + "CLK_PMV_SE2A0_3": null, + "CLK_PMV_SE2A0_4": null, + "CLK_PMV_SE2A0_5": null, + "CLK_PMV_SE2A0_6": null, + "CLK_PMV_SE2A1_0": null, + "CLK_PMV_SE2A1_1": null, + "CLK_PMV_SE2A1_2": null, + "CLK_PMV_SE2A1_3": null, + "CLK_PMV_SE2A1_4": null, + "CLK_PMV_SE2A1_5": null, + "CLK_PMV_SE2A1_6": null, + "CLK_PMV_SE2A2_0": null, + "CLK_PMV_SE2A2_1": null, + "CLK_PMV_SE2A2_2": null, + "CLK_PMV_SE2A2_3": null, + "CLK_PMV_SE2A2_4": null, + "CLK_PMV_SE2A2_5": null, + "CLK_PMV_SE2A2_6": null, + "CLK_PMV_SE2A3_0": null, + "CLK_PMV_SE2A3_1": null, + "CLK_PMV_SE2A3_2": null, + "CLK_PMV_SE2A3_3": null, + "CLK_PMV_SE2A3_4": null, + "CLK_PMV_SE2A3_5": null, + "CLK_PMV_SE2A3_6": null, + "CLK_PMV_SE4BEG0_0": null, + "CLK_PMV_SE4BEG0_1": null, + "CLK_PMV_SE4BEG0_2": null, + "CLK_PMV_SE4BEG0_3": null, + "CLK_PMV_SE4BEG0_4": null, + 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"CLK_PMV_SE4C1_5": null, + "CLK_PMV_SE4C1_6": null, + "CLK_PMV_SE4C2_0": null, + "CLK_PMV_SE4C2_1": null, + "CLK_PMV_SE4C2_2": null, + "CLK_PMV_SE4C2_3": null, + "CLK_PMV_SE4C2_4": null, + "CLK_PMV_SE4C2_5": null, + "CLK_PMV_SE4C2_6": null, + "CLK_PMV_SE4C3_0": null, + "CLK_PMV_SE4C3_1": null, + "CLK_PMV_SE4C3_2": null, + "CLK_PMV_SE4C3_3": null, + "CLK_PMV_SE4C3_4": null, + "CLK_PMV_SE4C3_5": null, + "CLK_PMV_SE4C3_6": null, + "CLK_PMV_SW2A0_0": null, + "CLK_PMV_SW2A0_1": null, + "CLK_PMV_SW2A0_2": null, + "CLK_PMV_SW2A0_3": null, + "CLK_PMV_SW2A0_4": null, + "CLK_PMV_SW2A0_5": null, + "CLK_PMV_SW2A0_6": null, + "CLK_PMV_SW2A1_0": null, + "CLK_PMV_SW2A1_1": null, + "CLK_PMV_SW2A1_2": null, + "CLK_PMV_SW2A1_3": null, + "CLK_PMV_SW2A1_4": null, + "CLK_PMV_SW2A1_5": null, + "CLK_PMV_SW2A1_6": null, + "CLK_PMV_SW2A2_0": null, + "CLK_PMV_SW2A2_1": null, + "CLK_PMV_SW2A2_2": null, + "CLK_PMV_SW2A2_3": null, + "CLK_PMV_SW2A2_4": null, + "CLK_PMV_SW2A2_5": null, + "CLK_PMV_SW2A2_6": null, + "CLK_PMV_SW2A3_0": null, + "CLK_PMV_SW2A3_1": null, + "CLK_PMV_SW2A3_2": null, + "CLK_PMV_SW2A3_3": null, + "CLK_PMV_SW2A3_4": null, + "CLK_PMV_SW2A3_5": null, + "CLK_PMV_SW2A3_6": null, + "CLK_PMV_SW4A0_0": null, + "CLK_PMV_SW4A0_1": null, + "CLK_PMV_SW4A0_2": null, + "CLK_PMV_SW4A0_3": null, + "CLK_PMV_SW4A0_4": null, + "CLK_PMV_SW4A0_5": null, + "CLK_PMV_SW4A0_6": null, + "CLK_PMV_SW4A1_0": null, + "CLK_PMV_SW4A1_1": null, + "CLK_PMV_SW4A1_2": null, + "CLK_PMV_SW4A1_3": null, + "CLK_PMV_SW4A1_4": null, + "CLK_PMV_SW4A1_5": null, + "CLK_PMV_SW4A1_6": null, + "CLK_PMV_SW4A2_0": null, + "CLK_PMV_SW4A2_1": null, + "CLK_PMV_SW4A2_2": null, + "CLK_PMV_SW4A2_3": null, + "CLK_PMV_SW4A2_4": null, + "CLK_PMV_SW4A2_5": null, + "CLK_PMV_SW4A2_6": null, + "CLK_PMV_SW4A3_0": null, + "CLK_PMV_SW4A3_1": null, + "CLK_PMV_SW4A3_2": null, + "CLK_PMV_SW4A3_3": null, + "CLK_PMV_SW4A3_4": null, + "CLK_PMV_SW4A3_5": null, + "CLK_PMV_SW4A3_6": null, + "CLK_PMV_SW4END0_0": null, + "CLK_PMV_SW4END0_1": null, + "CLK_PMV_SW4END0_2": null, + "CLK_PMV_SW4END0_3": null, + "CLK_PMV_SW4END0_4": null, + "CLK_PMV_SW4END0_5": null, + "CLK_PMV_SW4END0_6": null, + "CLK_PMV_SW4END1_0": null, + "CLK_PMV_SW4END1_1": null, + "CLK_PMV_SW4END1_2": null, + "CLK_PMV_SW4END1_3": null, + "CLK_PMV_SW4END1_4": null, + "CLK_PMV_SW4END1_5": null, + "CLK_PMV_SW4END1_6": null, + "CLK_PMV_SW4END2_0": null, + "CLK_PMV_SW4END2_1": null, + "CLK_PMV_SW4END2_2": null, + "CLK_PMV_SW4END2_3": null, + "CLK_PMV_SW4END2_4": null, + "CLK_PMV_SW4END2_5": null, + "CLK_PMV_SW4END2_6": null, + "CLK_PMV_SW4END3_0": null, + "CLK_PMV_SW4END3_1": null, + "CLK_PMV_SW4END3_2": null, + "CLK_PMV_SW4END3_3": null, + "CLK_PMV_SW4END3_4": null, + "CLK_PMV_SW4END3_5": null, + "CLK_PMV_SW4END3_6": null, + "CLK_PMV_WL1END0_0": null, + "CLK_PMV_WL1END0_1": null, + "CLK_PMV_WL1END0_2": null, + "CLK_PMV_WL1END0_3": null, + "CLK_PMV_WL1END0_4": null, + "CLK_PMV_WL1END0_5": null, + "CLK_PMV_WL1END0_6": null, + "CLK_PMV_WL1END1_0": null, + "CLK_PMV_WL1END1_1": null, + "CLK_PMV_WL1END1_2": null, + "CLK_PMV_WL1END1_3": null, + "CLK_PMV_WL1END1_4": null, + "CLK_PMV_WL1END1_5": null, + "CLK_PMV_WL1END1_6": null, + "CLK_PMV_WL1END2_0": null, + "CLK_PMV_WL1END2_1": null, + "CLK_PMV_WL1END2_2": null, + "CLK_PMV_WL1END2_3": null, + "CLK_PMV_WL1END2_4": null, + "CLK_PMV_WL1END2_5": null, + "CLK_PMV_WL1END2_6": null, + "CLK_PMV_WL1END3_0": null, + "CLK_PMV_WL1END3_1": null, + "CLK_PMV_WL1END3_2": null, + "CLK_PMV_WL1END3_3": null, + "CLK_PMV_WL1END3_4": null, + "CLK_PMV_WL1END3_5": null, + "CLK_PMV_WL1END3_6": null, + "CLK_PMV_WR1END0_0": null, + "CLK_PMV_WR1END0_1": null, + "CLK_PMV_WR1END0_2": null, + "CLK_PMV_WR1END0_3": null, + "CLK_PMV_WR1END0_4": null, + "CLK_PMV_WR1END0_5": null, + "CLK_PMV_WR1END0_6": null, + "CLK_PMV_WR1END1_0": null, + "CLK_PMV_WR1END1_1": null, + "CLK_PMV_WR1END1_2": null, + "CLK_PMV_WR1END1_3": null, + "CLK_PMV_WR1END1_4": null, + "CLK_PMV_WR1END1_5": null, + "CLK_PMV_WR1END1_6": null, + "CLK_PMV_WR1END2_0": null, + "CLK_PMV_WR1END2_1": null, + "CLK_PMV_WR1END2_2": null, + "CLK_PMV_WR1END2_3": null, + "CLK_PMV_WR1END2_4": null, + "CLK_PMV_WR1END2_5": null, + "CLK_PMV_WR1END2_6": null, + "CLK_PMV_WR1END3_0": null, + "CLK_PMV_WR1END3_1": null, + "CLK_PMV_WR1END3_2": null, + "CLK_PMV_WR1END3_3": null, + "CLK_PMV_WR1END3_4": null, + "CLK_PMV_WR1END3_5": null, + "CLK_PMV_WR1END3_6": null, + "CLK_PMV_WW2A0_0": null, + "CLK_PMV_WW2A0_1": null, + "CLK_PMV_WW2A0_2": null, + "CLK_PMV_WW2A0_3": null, + "CLK_PMV_WW2A0_4": null, + "CLK_PMV_WW2A0_5": null, + "CLK_PMV_WW2A0_6": null, + "CLK_PMV_WW2A1_0": null, + "CLK_PMV_WW2A1_1": null, + "CLK_PMV_WW2A1_2": null, + "CLK_PMV_WW2A1_3": null, + "CLK_PMV_WW2A1_4": null, + "CLK_PMV_WW2A1_5": null, + "CLK_PMV_WW2A1_6": null, + "CLK_PMV_WW2A2_0": null, + "CLK_PMV_WW2A2_1": null, + "CLK_PMV_WW2A2_2": null, + "CLK_PMV_WW2A2_3": null, + "CLK_PMV_WW2A2_4": null, + "CLK_PMV_WW2A2_5": null, + "CLK_PMV_WW2A2_6": null, + "CLK_PMV_WW2A3_0": null, + "CLK_PMV_WW2A3_1": null, + "CLK_PMV_WW2A3_2": null, + "CLK_PMV_WW2A3_3": null, + "CLK_PMV_WW2A3_4": null, + "CLK_PMV_WW2A3_5": null, + "CLK_PMV_WW2A3_6": null, + "CLK_PMV_WW2END0_0": null, + "CLK_PMV_WW2END0_1": null, + "CLK_PMV_WW2END0_2": null, + "CLK_PMV_WW2END0_3": null, + "CLK_PMV_WW2END0_4": null, + "CLK_PMV_WW2END0_5": null, + "CLK_PMV_WW2END0_6": null, + "CLK_PMV_WW2END1_0": null, + "CLK_PMV_WW2END1_1": null, + "CLK_PMV_WW2END1_2": null, + "CLK_PMV_WW2END1_3": null, + "CLK_PMV_WW2END1_4": null, + "CLK_PMV_WW2END1_5": null, + "CLK_PMV_WW2END1_6": null, + "CLK_PMV_WW2END2_0": null, + "CLK_PMV_WW2END2_1": null, + "CLK_PMV_WW2END2_2": null, + "CLK_PMV_WW2END2_3": null, + "CLK_PMV_WW2END2_4": null, + "CLK_PMV_WW2END2_5": null, + "CLK_PMV_WW2END2_6": null, + "CLK_PMV_WW2END3_0": null, + "CLK_PMV_WW2END3_1": null, + "CLK_PMV_WW2END3_2": null, + "CLK_PMV_WW2END3_3": null, + "CLK_PMV_WW2END3_4": null, + "CLK_PMV_WW2END3_5": null, + "CLK_PMV_WW2END3_6": null, + "CLK_PMV_WW4A0_0": null, + "CLK_PMV_WW4A0_1": null, + "CLK_PMV_WW4A0_2": null, + "CLK_PMV_WW4A0_3": null, + "CLK_PMV_WW4A0_4": null, + "CLK_PMV_WW4A0_5": null, + "CLK_PMV_WW4A0_6": null, + "CLK_PMV_WW4A1_0": null, + "CLK_PMV_WW4A1_1": null, + "CLK_PMV_WW4A1_2": null, + "CLK_PMV_WW4A1_3": null, + "CLK_PMV_WW4A1_4": null, + "CLK_PMV_WW4A1_5": null, + "CLK_PMV_WW4A1_6": null, + "CLK_PMV_WW4A2_0": null, + "CLK_PMV_WW4A2_1": null, + "CLK_PMV_WW4A2_2": null, + "CLK_PMV_WW4A2_3": null, + "CLK_PMV_WW4A2_4": null, + "CLK_PMV_WW4A2_5": null, + "CLK_PMV_WW4A2_6": null, + "CLK_PMV_WW4A3_0": null, + "CLK_PMV_WW4A3_1": null, + "CLK_PMV_WW4A3_2": null, + "CLK_PMV_WW4A3_3": null, + "CLK_PMV_WW4A3_4": null, + "CLK_PMV_WW4A3_5": null, + "CLK_PMV_WW4A3_6": null, + "CLK_PMV_WW4B0_0": null, + "CLK_PMV_WW4B0_1": null, + "CLK_PMV_WW4B0_2": null, + "CLK_PMV_WW4B0_3": null, + "CLK_PMV_WW4B0_4": null, + "CLK_PMV_WW4B0_5": null, + "CLK_PMV_WW4B0_6": null, + "CLK_PMV_WW4B1_0": null, + "CLK_PMV_WW4B1_1": null, + "CLK_PMV_WW4B1_2": null, + "CLK_PMV_WW4B1_3": null, + "CLK_PMV_WW4B1_4": null, + "CLK_PMV_WW4B1_5": null, + "CLK_PMV_WW4B1_6": null, + "CLK_PMV_WW4B2_0": null, + "CLK_PMV_WW4B2_1": null, + "CLK_PMV_WW4B2_2": null, + "CLK_PMV_WW4B2_3": null, + "CLK_PMV_WW4B2_4": null, + "CLK_PMV_WW4B2_5": null, + "CLK_PMV_WW4B2_6": null, + "CLK_PMV_WW4B3_0": null, + "CLK_PMV_WW4B3_1": null, + "CLK_PMV_WW4B3_2": null, + "CLK_PMV_WW4B3_3": null, + "CLK_PMV_WW4B3_4": null, + "CLK_PMV_WW4B3_5": null, + "CLK_PMV_WW4B3_6": null, + "CLK_PMV_WW4C0_0": null, + "CLK_PMV_WW4C0_1": null, + "CLK_PMV_WW4C0_2": null, + "CLK_PMV_WW4C0_3": null, + "CLK_PMV_WW4C0_4": null, + "CLK_PMV_WW4C0_5": null, + "CLK_PMV_WW4C0_6": null, + "CLK_PMV_WW4C1_0": null, + "CLK_PMV_WW4C1_1": null, + "CLK_PMV_WW4C1_2": null, + "CLK_PMV_WW4C1_3": null, + "CLK_PMV_WW4C1_4": null, + "CLK_PMV_WW4C1_5": null, + "CLK_PMV_WW4C1_6": null, + "CLK_PMV_WW4C2_0": null, + "CLK_PMV_WW4C2_1": null, + "CLK_PMV_WW4C2_2": null, + "CLK_PMV_WW4C2_3": null, + "CLK_PMV_WW4C2_4": null, + "CLK_PMV_WW4C2_5": null, + "CLK_PMV_WW4C2_6": null, + "CLK_PMV_WW4C3_0": null, + "CLK_PMV_WW4C3_1": null, + "CLK_PMV_WW4C3_2": null, + "CLK_PMV_WW4C3_3": null, + "CLK_PMV_WW4C3_4": null, + "CLK_PMV_WW4C3_5": null, + "CLK_PMV_WW4C3_6": null, + "CLK_PMV_WW4END0_0": null, + "CLK_PMV_WW4END0_1": null, + "CLK_PMV_WW4END0_2": null, + "CLK_PMV_WW4END0_3": null, + "CLK_PMV_WW4END0_4": null, + "CLK_PMV_WW4END0_5": null, + "CLK_PMV_WW4END0_6": null, + "CLK_PMV_WW4END1_0": null, + "CLK_PMV_WW4END1_1": null, + "CLK_PMV_WW4END1_2": null, + "CLK_PMV_WW4END1_3": null, + "CLK_PMV_WW4END1_4": null, + "CLK_PMV_WW4END1_5": null, + "CLK_PMV_WW4END1_6": null, + "CLK_PMV_WW4END2_0": null, + "CLK_PMV_WW4END2_1": null, + "CLK_PMV_WW4END2_2": null, + "CLK_PMV_WW4END2_3": null, + "CLK_PMV_WW4END2_4": null, + "CLK_PMV_WW4END2_5": null, + "CLK_PMV_WW4END2_6": null, + "CLK_PMV_WW4END3_0": null, + "CLK_PMV_WW4END3_1": null, + "CLK_PMV_WW4END3_2": null, + "CLK_PMV_WW4END3_3": null, + "CLK_PMV_WW4END3_4": null, + "CLK_PMV_WW4END3_5": null, + "CLK_PMV_WW4END3_6": null + } } diff --git a/zynq7/tile_type_CLK_PMV2.json b/zynq7/tile_type_CLK_PMV2.json index 71957cc..db16457 100644 --- a/zynq7/tile_type_CLK_PMV2.json +++ b/zynq7/tile_type_CLK_PMV2.json @@ -5,13 +5,76 @@ "name": "X0Y0", "prefix": "PMV", "site_pins": { - "A0": "CLK_PMV2_A0", - "A1": "CLK_PMV2_A1", - "A2": "CLK_PMV2_A2", - "EN": "CLK_PMV2_EN", - "O": "CLK_PMV2_O", - "ODIV2": "CLK_PMV2_ODIV2", - "ODIV4": "CLK_PMV2_ODIV4" + "A0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_PMV2_A0" + }, + "A1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_PMV2_A1" + }, + "A2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_PMV2_A2" + }, + "EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_PMV2_EN" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_PMV2_O" + }, + "ODIV2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_PMV2_ODIV2" + }, + "ODIV4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_PMV2_ODIV4" + } }, "type": "PMV2", "x_coord": 0, @@ -19,359 +82,359 @@ } ], "tile_type": "CLK_PMV2", - "wires": [ - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK0", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK10", - "CLK_FEED_CK_GCLK11", - "CLK_FEED_CK_GCLK12", - "CLK_FEED_CK_GCLK13", - "CLK_FEED_CK_GCLK14", - "CLK_FEED_CK_GCLK15", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_CK_GCLK19", - "CLK_FEED_CK_GCLK2", - "CLK_FEED_CK_GCLK20", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK22", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_CK_GCLK30", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_CK_GCLK5", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_CK_GCLK8", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_EE2A0", - "CLK_FEED_EE2A1", - "CLK_FEED_EE2A2", - "CLK_FEED_EE2A3", - "CLK_FEED_EE2BEG0", - "CLK_FEED_EE2BEG1", - "CLK_FEED_EE2BEG2", - "CLK_FEED_EE2BEG3", - "CLK_FEED_EE4A0", - "CLK_FEED_EE4A1", - "CLK_FEED_EE4A2", - "CLK_FEED_EE4A3", - "CLK_FEED_EE4B0", - "CLK_FEED_EE4B1", - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_EE4BEG0", - "CLK_FEED_EE4BEG1", - "CLK_FEED_EE4BEG2", - "CLK_FEED_EE4BEG3", - "CLK_FEED_EE4C0", - "CLK_FEED_EE4C1", - "CLK_FEED_EE4C2", - "CLK_FEED_EE4C3", - "CLK_FEED_EL1BEG0", - "CLK_FEED_EL1BEG1", - "CLK_FEED_EL1BEG2", - "CLK_FEED_EL1BEG3", - "CLK_FEED_ER1BEG0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_ER1BEG2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_LH1", - "CLK_FEED_LH10", - "CLK_FEED_LH11", - "CLK_FEED_LH12", - "CLK_FEED_LH2", - "CLK_FEED_LH3", - "CLK_FEED_LH4", - "CLK_FEED_LH5", - "CLK_FEED_LH6", - "CLK_FEED_LH7", - "CLK_FEED_LH8", - "CLK_FEED_LH9", - "CLK_FEED_MONITOR_N", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A0", - "CLK_FEED_NE2A1", - "CLK_FEED_NE2A2", - "CLK_FEED_NE2A3", - "CLK_FEED_NE4BEG0", - "CLK_FEED_NE4BEG1", - "CLK_FEED_NE4BEG2", - "CLK_FEED_NE4BEG3", - "CLK_FEED_NE4C0", - "CLK_FEED_NE4C1", - "CLK_FEED_NE4C2", - "CLK_FEED_NE4C3", - "CLK_FEED_NW2A0", - "CLK_FEED_NW2A1", - "CLK_FEED_NW2A2", - "CLK_FEED_NW2A3", - "CLK_FEED_NW4A0", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4A2", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4END0", - "CLK_FEED_NW4END1", - "CLK_FEED_NW4END2", - "CLK_FEED_NW4END3", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_SE2A0", - "CLK_FEED_SE2A1", - "CLK_FEED_SE2A2", - "CLK_FEED_SE2A3", - "CLK_FEED_SE4BEG0", - "CLK_FEED_SE4BEG1", - "CLK_FEED_SE4BEG2", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SE4C0", - "CLK_FEED_SE4C1", - "CLK_FEED_SE4C2", - "CLK_FEED_SE4C3", - "CLK_FEED_SW2A0", - "CLK_FEED_SW2A1", - "CLK_FEED_SW2A2", - "CLK_FEED_SW2A3", - "CLK_FEED_SW4A0", - "CLK_FEED_SW4A1", - "CLK_FEED_SW4A2", - "CLK_FEED_SW4A3", - "CLK_FEED_SW4END0", - "CLK_FEED_SW4END1", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_FEED_WL1END0", - "CLK_FEED_WL1END1", - "CLK_FEED_WL1END2", - "CLK_FEED_WL1END3", - "CLK_FEED_WR1END0", - "CLK_FEED_WR1END1", - "CLK_FEED_WR1END2", - "CLK_FEED_WR1END3", - "CLK_FEED_WW2A0", - "CLK_FEED_WW2A1", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2A3", - "CLK_FEED_WW2END0", - "CLK_FEED_WW2END1", - "CLK_FEED_WW2END2", - "CLK_FEED_WW2END3", - "CLK_FEED_WW4A0", - "CLK_FEED_WW4A1", - "CLK_FEED_WW4A2", - "CLK_FEED_WW4A3", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4B1", - "CLK_FEED_WW4B2", - "CLK_FEED_WW4B3", - "CLK_FEED_WW4C0", - "CLK_FEED_WW4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_WW4C3", - "CLK_FEED_WW4END0", - "CLK_FEED_WW4END1", - "CLK_FEED_WW4END2", - "CLK_FEED_WW4END3", - "CLK_PMV2_A0", - "CLK_PMV2_A1", - "CLK_PMV2_A2", - "CLK_PMV2_EN", - "CLK_PMV2_O", - "CLK_PMV2_ODIV2", - "CLK_PMV2_ODIV4", - "CLK_PMV_BYP0_0", - "CLK_PMV_BYP1_0", - "CLK_PMV_BYP2_0", - "CLK_PMV_BYP3_0", - "CLK_PMV_BYP4_0", - "CLK_PMV_BYP5_0", - "CLK_PMV_BYP6_0", - "CLK_PMV_BYP7_0", - "CLK_PMV_CLK0_0", - "CLK_PMV_CLK1_0", - "CLK_PMV_CTRL0_0", - "CLK_PMV_CTRL1_0", - "CLK_PMV_FAN0_0", - "CLK_PMV_FAN1_0", - "CLK_PMV_FAN2_0", - "CLK_PMV_FAN3_0", - "CLK_PMV_FAN4_0", - "CLK_PMV_FAN5_0", - "CLK_PMV_FAN6_0", - "CLK_PMV_FAN7_0", - "CLK_PMV_IMUX0_0", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX12_0", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX15_0", - "CLK_PMV_IMUX16_0", - "CLK_PMV_IMUX17_0", - "CLK_PMV_IMUX18_0", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX1_0", - "CLK_PMV_IMUX20_0", - "CLK_PMV_IMUX21_0", - "CLK_PMV_IMUX22_0", - "CLK_PMV_IMUX23_0", - "CLK_PMV_IMUX24_0", - "CLK_PMV_IMUX25_0", - "CLK_PMV_IMUX26_0", - "CLK_PMV_IMUX27_0", - "CLK_PMV_IMUX28_0", - "CLK_PMV_IMUX29_0", - "CLK_PMV_IMUX2_0", - "CLK_PMV_IMUX30_0", - "CLK_PMV_IMUX31_0", - "CLK_PMV_IMUX32_0", - "CLK_PMV_IMUX33_0", - "CLK_PMV_IMUX34_0", - "CLK_PMV_IMUX35_0", - "CLK_PMV_IMUX36_0", - "CLK_PMV_IMUX37_0", - "CLK_PMV_IMUX38_0", - "CLK_PMV_IMUX39_0", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX40_0", - "CLK_PMV_IMUX41_0", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX43_0", - "CLK_PMV_IMUX44_0", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX46_0", - "CLK_PMV_IMUX47_0", - "CLK_PMV_IMUX4_0", - "CLK_PMV_IMUX5_0", - "CLK_PMV_IMUX6_0", - "CLK_PMV_IMUX7_0", - "CLK_PMV_IMUX8_0", - "CLK_PMV_IMUX9_0", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_PMV_LOGIC_OUTS9_0" - ] + "wires": { + "CLK_FEED_CK_BUFG_CASC0": null, + "CLK_FEED_CK_BUFG_CASC1": null, + "CLK_FEED_CK_BUFG_CASC10": null, + "CLK_FEED_CK_BUFG_CASC11": null, + "CLK_FEED_CK_BUFG_CASC12": null, + "CLK_FEED_CK_BUFG_CASC13": null, + "CLK_FEED_CK_BUFG_CASC14": null, + "CLK_FEED_CK_BUFG_CASC15": null, + "CLK_FEED_CK_BUFG_CASC16": null, + "CLK_FEED_CK_BUFG_CASC17": null, + "CLK_FEED_CK_BUFG_CASC18": null, + "CLK_FEED_CK_BUFG_CASC19": null, + "CLK_FEED_CK_BUFG_CASC2": null, + "CLK_FEED_CK_BUFG_CASC20": null, + "CLK_FEED_CK_BUFG_CASC21": null, + "CLK_FEED_CK_BUFG_CASC22": null, + "CLK_FEED_CK_BUFG_CASC23": null, + "CLK_FEED_CK_BUFG_CASC24": null, + "CLK_FEED_CK_BUFG_CASC25": null, + "CLK_FEED_CK_BUFG_CASC26": null, + "CLK_FEED_CK_BUFG_CASC27": null, + "CLK_FEED_CK_BUFG_CASC28": null, + "CLK_FEED_CK_BUFG_CASC29": null, + "CLK_FEED_CK_BUFG_CASC3": null, + "CLK_FEED_CK_BUFG_CASC30": null, + "CLK_FEED_CK_BUFG_CASC31": null, + "CLK_FEED_CK_BUFG_CASC4": null, + "CLK_FEED_CK_BUFG_CASC5": null, + "CLK_FEED_CK_BUFG_CASC6": null, + "CLK_FEED_CK_BUFG_CASC7": null, + "CLK_FEED_CK_BUFG_CASC8": null, + "CLK_FEED_CK_BUFG_CASC9": null, + "CLK_FEED_CK_GCLK0": null, + "CLK_FEED_CK_GCLK1": null, + "CLK_FEED_CK_GCLK10": null, + "CLK_FEED_CK_GCLK11": null, + "CLK_FEED_CK_GCLK12": null, + "CLK_FEED_CK_GCLK13": null, + "CLK_FEED_CK_GCLK14": null, + "CLK_FEED_CK_GCLK15": null, + "CLK_FEED_CK_GCLK16": null, + "CLK_FEED_CK_GCLK17": null, + "CLK_FEED_CK_GCLK18": null, + "CLK_FEED_CK_GCLK19": null, + "CLK_FEED_CK_GCLK2": null, + "CLK_FEED_CK_GCLK20": null, + "CLK_FEED_CK_GCLK21": null, + "CLK_FEED_CK_GCLK22": null, + "CLK_FEED_CK_GCLK23": null, + "CLK_FEED_CK_GCLK24": null, + "CLK_FEED_CK_GCLK25": null, + "CLK_FEED_CK_GCLK26": null, + "CLK_FEED_CK_GCLK27": null, + "CLK_FEED_CK_GCLK28": null, + "CLK_FEED_CK_GCLK29": null, + "CLK_FEED_CK_GCLK3": null, + "CLK_FEED_CK_GCLK30": null, + "CLK_FEED_CK_GCLK31": null, + "CLK_FEED_CK_GCLK4": null, + "CLK_FEED_CK_GCLK5": null, + "CLK_FEED_CK_GCLK6": null, + "CLK_FEED_CK_GCLK7": null, + "CLK_FEED_CK_GCLK8": null, + "CLK_FEED_CK_GCLK9": null, + "CLK_FEED_EE2A0": null, + "CLK_FEED_EE2A1": null, + "CLK_FEED_EE2A2": null, + "CLK_FEED_EE2A3": null, + "CLK_FEED_EE2BEG0": null, + "CLK_FEED_EE2BEG1": null, + "CLK_FEED_EE2BEG2": null, + "CLK_FEED_EE2BEG3": null, + "CLK_FEED_EE4A0": null, + "CLK_FEED_EE4A1": null, + "CLK_FEED_EE4A2": null, + "CLK_FEED_EE4A3": null, + "CLK_FEED_EE4B0": null, + "CLK_FEED_EE4B1": null, + "CLK_FEED_EE4B2": null, + "CLK_FEED_EE4B3": null, + "CLK_FEED_EE4BEG0": null, + "CLK_FEED_EE4BEG1": null, + "CLK_FEED_EE4BEG2": null, + "CLK_FEED_EE4BEG3": null, + "CLK_FEED_EE4C0": null, + "CLK_FEED_EE4C1": null, + "CLK_FEED_EE4C2": null, + "CLK_FEED_EE4C3": null, + "CLK_FEED_EL1BEG0": null, + "CLK_FEED_EL1BEG1": null, + "CLK_FEED_EL1BEG2": null, + "CLK_FEED_EL1BEG3": null, + "CLK_FEED_ER1BEG0": null, + "CLK_FEED_ER1BEG1": null, + "CLK_FEED_ER1BEG2": null, + "CLK_FEED_ER1BEG3": null, + "CLK_FEED_LH1": null, + "CLK_FEED_LH10": null, + "CLK_FEED_LH11": null, + "CLK_FEED_LH12": null, + "CLK_FEED_LH2": null, + "CLK_FEED_LH3": null, + "CLK_FEED_LH4": null, + "CLK_FEED_LH5": null, + "CLK_FEED_LH6": null, + "CLK_FEED_LH7": null, + "CLK_FEED_LH8": null, + "CLK_FEED_LH9": null, + "CLK_FEED_MONITOR_N": null, + "CLK_FEED_MONITOR_P": null, + "CLK_FEED_NE2A0": null, + "CLK_FEED_NE2A1": null, + "CLK_FEED_NE2A2": null, + "CLK_FEED_NE2A3": null, + "CLK_FEED_NE4BEG0": null, + "CLK_FEED_NE4BEG1": null, + "CLK_FEED_NE4BEG2": null, + "CLK_FEED_NE4BEG3": null, + "CLK_FEED_NE4C0": null, + "CLK_FEED_NE4C1": null, + "CLK_FEED_NE4C2": null, + "CLK_FEED_NE4C3": null, + "CLK_FEED_NW2A0": null, + "CLK_FEED_NW2A1": null, + "CLK_FEED_NW2A2": null, + "CLK_FEED_NW2A3": null, + "CLK_FEED_NW4A0": null, + "CLK_FEED_NW4A1": null, + "CLK_FEED_NW4A2": null, + "CLK_FEED_NW4A3": null, + "CLK_FEED_NW4END0": null, + "CLK_FEED_NW4END1": null, + "CLK_FEED_NW4END2": null, + "CLK_FEED_NW4END3": null, + "CLK_FEED_R_CK_BUFG_CASC0": null, + "CLK_FEED_R_CK_BUFG_CASC1": null, + "CLK_FEED_R_CK_BUFG_CASC10": null, + "CLK_FEED_R_CK_BUFG_CASC11": null, + "CLK_FEED_R_CK_BUFG_CASC12": null, + "CLK_FEED_R_CK_BUFG_CASC13": null, + "CLK_FEED_R_CK_BUFG_CASC14": null, + "CLK_FEED_R_CK_BUFG_CASC15": null, + "CLK_FEED_R_CK_BUFG_CASC16": null, + "CLK_FEED_R_CK_BUFG_CASC17": null, + "CLK_FEED_R_CK_BUFG_CASC18": null, + "CLK_FEED_R_CK_BUFG_CASC19": null, + "CLK_FEED_R_CK_BUFG_CASC2": null, + "CLK_FEED_R_CK_BUFG_CASC20": null, + "CLK_FEED_R_CK_BUFG_CASC21": null, + "CLK_FEED_R_CK_BUFG_CASC22": null, + "CLK_FEED_R_CK_BUFG_CASC23": null, + "CLK_FEED_R_CK_BUFG_CASC24": null, + "CLK_FEED_R_CK_BUFG_CASC25": null, + "CLK_FEED_R_CK_BUFG_CASC26": null, + "CLK_FEED_R_CK_BUFG_CASC27": null, + "CLK_FEED_R_CK_BUFG_CASC28": null, + "CLK_FEED_R_CK_BUFG_CASC29": null, + "CLK_FEED_R_CK_BUFG_CASC3": null, + "CLK_FEED_R_CK_BUFG_CASC30": null, + "CLK_FEED_R_CK_BUFG_CASC31": null, + "CLK_FEED_R_CK_BUFG_CASC4": null, + "CLK_FEED_R_CK_BUFG_CASC5": null, + "CLK_FEED_R_CK_BUFG_CASC6": null, + "CLK_FEED_R_CK_BUFG_CASC7": null, + "CLK_FEED_R_CK_BUFG_CASC8": null, + "CLK_FEED_R_CK_BUFG_CASC9": null, + "CLK_FEED_R_CK_GCLK0": null, + "CLK_FEED_R_CK_GCLK1": null, + "CLK_FEED_R_CK_GCLK10": null, + "CLK_FEED_R_CK_GCLK11": null, + "CLK_FEED_R_CK_GCLK12": null, + "CLK_FEED_R_CK_GCLK13": null, + "CLK_FEED_R_CK_GCLK14": null, + "CLK_FEED_R_CK_GCLK15": null, + "CLK_FEED_R_CK_GCLK16": null, + "CLK_FEED_R_CK_GCLK17": null, + "CLK_FEED_R_CK_GCLK18": null, + "CLK_FEED_R_CK_GCLK19": null, + "CLK_FEED_R_CK_GCLK2": null, + "CLK_FEED_R_CK_GCLK20": null, + "CLK_FEED_R_CK_GCLK21": null, + "CLK_FEED_R_CK_GCLK22": null, + "CLK_FEED_R_CK_GCLK23": null, + "CLK_FEED_R_CK_GCLK24": null, + "CLK_FEED_R_CK_GCLK25": null, + "CLK_FEED_R_CK_GCLK26": null, + "CLK_FEED_R_CK_GCLK27": null, + "CLK_FEED_R_CK_GCLK28": null, + "CLK_FEED_R_CK_GCLK29": null, + "CLK_FEED_R_CK_GCLK3": null, + "CLK_FEED_R_CK_GCLK30": null, + "CLK_FEED_R_CK_GCLK31": null, + "CLK_FEED_R_CK_GCLK4": null, + "CLK_FEED_R_CK_GCLK5": null, + "CLK_FEED_R_CK_GCLK6": null, + "CLK_FEED_R_CK_GCLK7": null, + "CLK_FEED_R_CK_GCLK8": null, + "CLK_FEED_R_CK_GCLK9": null, + "CLK_FEED_SE2A0": null, + "CLK_FEED_SE2A1": null, + "CLK_FEED_SE2A2": null, + "CLK_FEED_SE2A3": null, + "CLK_FEED_SE4BEG0": null, + "CLK_FEED_SE4BEG1": null, + "CLK_FEED_SE4BEG2": null, + "CLK_FEED_SE4BEG3": null, + "CLK_FEED_SE4C0": null, + "CLK_FEED_SE4C1": null, + "CLK_FEED_SE4C2": null, + "CLK_FEED_SE4C3": null, + "CLK_FEED_SW2A0": null, + "CLK_FEED_SW2A1": null, + "CLK_FEED_SW2A2": null, + "CLK_FEED_SW2A3": null, + "CLK_FEED_SW4A0": null, + "CLK_FEED_SW4A1": null, + "CLK_FEED_SW4A2": null, + "CLK_FEED_SW4A3": null, + "CLK_FEED_SW4END0": null, + "CLK_FEED_SW4END1": null, + "CLK_FEED_SW4END2": null, + "CLK_FEED_SW4END3": null, + "CLK_FEED_WL1END0": null, + "CLK_FEED_WL1END1": null, + "CLK_FEED_WL1END2": null, + "CLK_FEED_WL1END3": null, + "CLK_FEED_WR1END0": null, + "CLK_FEED_WR1END1": null, + "CLK_FEED_WR1END2": null, + "CLK_FEED_WR1END3": null, + "CLK_FEED_WW2A0": null, + "CLK_FEED_WW2A1": null, + "CLK_FEED_WW2A2": null, + "CLK_FEED_WW2A3": null, + "CLK_FEED_WW2END0": null, + "CLK_FEED_WW2END1": null, + "CLK_FEED_WW2END2": null, + "CLK_FEED_WW2END3": null, + "CLK_FEED_WW4A0": null, + "CLK_FEED_WW4A1": null, + "CLK_FEED_WW4A2": null, + "CLK_FEED_WW4A3": null, + "CLK_FEED_WW4B0": null, + "CLK_FEED_WW4B1": null, + "CLK_FEED_WW4B2": null, + "CLK_FEED_WW4B3": null, + "CLK_FEED_WW4C0": null, + "CLK_FEED_WW4C1": null, + "CLK_FEED_WW4C2": null, + "CLK_FEED_WW4C3": null, + "CLK_FEED_WW4END0": null, + "CLK_FEED_WW4END1": null, + "CLK_FEED_WW4END2": null, + "CLK_FEED_WW4END3": null, + "CLK_PMV2_A0": null, + "CLK_PMV2_A1": null, + "CLK_PMV2_A2": null, + "CLK_PMV2_EN": null, + "CLK_PMV2_O": null, + "CLK_PMV2_ODIV2": null, + "CLK_PMV2_ODIV4": null, + "CLK_PMV_BYP0_0": null, + "CLK_PMV_BYP1_0": null, + "CLK_PMV_BYP2_0": null, + "CLK_PMV_BYP3_0": null, + "CLK_PMV_BYP4_0": null, + "CLK_PMV_BYP5_0": null, + "CLK_PMV_BYP6_0": null, + "CLK_PMV_BYP7_0": null, + "CLK_PMV_CLK0_0": null, + "CLK_PMV_CLK1_0": null, + "CLK_PMV_CTRL0_0": null, + "CLK_PMV_CTRL1_0": null, + "CLK_PMV_FAN0_0": null, + "CLK_PMV_FAN1_0": null, + "CLK_PMV_FAN2_0": null, + "CLK_PMV_FAN3_0": null, + "CLK_PMV_FAN4_0": null, + "CLK_PMV_FAN5_0": null, + "CLK_PMV_FAN6_0": null, + "CLK_PMV_FAN7_0": null, + "CLK_PMV_IMUX0_0": null, + "CLK_PMV_IMUX10_0": null, + "CLK_PMV_IMUX11_0": null, + "CLK_PMV_IMUX12_0": null, + "CLK_PMV_IMUX13_0": null, + "CLK_PMV_IMUX14_0": null, + "CLK_PMV_IMUX15_0": null, + "CLK_PMV_IMUX16_0": null, + "CLK_PMV_IMUX17_0": null, + "CLK_PMV_IMUX18_0": null, + "CLK_PMV_IMUX19_0": null, + "CLK_PMV_IMUX1_0": null, + "CLK_PMV_IMUX20_0": null, + "CLK_PMV_IMUX21_0": null, + "CLK_PMV_IMUX22_0": null, + "CLK_PMV_IMUX23_0": null, + "CLK_PMV_IMUX24_0": null, + "CLK_PMV_IMUX25_0": null, + "CLK_PMV_IMUX26_0": null, + "CLK_PMV_IMUX27_0": null, + "CLK_PMV_IMUX28_0": null, + "CLK_PMV_IMUX29_0": null, + "CLK_PMV_IMUX2_0": null, + "CLK_PMV_IMUX30_0": null, + "CLK_PMV_IMUX31_0": null, + "CLK_PMV_IMUX32_0": null, + "CLK_PMV_IMUX33_0": null, + "CLK_PMV_IMUX34_0": null, + "CLK_PMV_IMUX35_0": null, + "CLK_PMV_IMUX36_0": null, + "CLK_PMV_IMUX37_0": null, + "CLK_PMV_IMUX38_0": null, + "CLK_PMV_IMUX39_0": null, + "CLK_PMV_IMUX3_0": null, + "CLK_PMV_IMUX40_0": null, + "CLK_PMV_IMUX41_0": null, + "CLK_PMV_IMUX42_0": null, + "CLK_PMV_IMUX43_0": null, + "CLK_PMV_IMUX44_0": null, + "CLK_PMV_IMUX45_0": null, + "CLK_PMV_IMUX46_0": null, + "CLK_PMV_IMUX47_0": null, + "CLK_PMV_IMUX4_0": null, + "CLK_PMV_IMUX5_0": null, + "CLK_PMV_IMUX6_0": null, + "CLK_PMV_IMUX7_0": null, + "CLK_PMV_IMUX8_0": null, + "CLK_PMV_IMUX9_0": null, + "CLK_PMV_LOGIC_OUTS0_0": null, + "CLK_PMV_LOGIC_OUTS10_0": null, + "CLK_PMV_LOGIC_OUTS11_0": null, + "CLK_PMV_LOGIC_OUTS12_0": null, + "CLK_PMV_LOGIC_OUTS13_0": null, + "CLK_PMV_LOGIC_OUTS14_0": null, + "CLK_PMV_LOGIC_OUTS15_0": null, + "CLK_PMV_LOGIC_OUTS16_0": null, + "CLK_PMV_LOGIC_OUTS17_0": null, + "CLK_PMV_LOGIC_OUTS18_0": null, + "CLK_PMV_LOGIC_OUTS19_0": null, + "CLK_PMV_LOGIC_OUTS1_0": null, + "CLK_PMV_LOGIC_OUTS20_0": null, + "CLK_PMV_LOGIC_OUTS21_0": null, + "CLK_PMV_LOGIC_OUTS22_0": null, + "CLK_PMV_LOGIC_OUTS23_0": null, + "CLK_PMV_LOGIC_OUTS2_0": null, + "CLK_PMV_LOGIC_OUTS3_0": null, + "CLK_PMV_LOGIC_OUTS4_0": null, + "CLK_PMV_LOGIC_OUTS5_0": null, + "CLK_PMV_LOGIC_OUTS6_0": null, + "CLK_PMV_LOGIC_OUTS7_0": null, + "CLK_PMV_LOGIC_OUTS8_0": null, + "CLK_PMV_LOGIC_OUTS9_0": null + } } diff --git a/zynq7/tile_type_CLK_PMV2_SVT.json b/zynq7/tile_type_CLK_PMV2_SVT.json index cc63563..ab9442d 100644 --- a/zynq7/tile_type_CLK_PMV2_SVT.json +++ b/zynq7/tile_type_CLK_PMV2_SVT.json @@ -2,359 +2,359 @@ "pips": {}, "sites": [], "tile_type": "CLK_PMV2_SVT", - "wires": [ - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK0", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK10", - "CLK_FEED_CK_GCLK11", - "CLK_FEED_CK_GCLK12", - "CLK_FEED_CK_GCLK13", - "CLK_FEED_CK_GCLK14", - "CLK_FEED_CK_GCLK15", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_CK_GCLK19", - "CLK_FEED_CK_GCLK2", - "CLK_FEED_CK_GCLK20", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK22", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_CK_GCLK30", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_CK_GCLK5", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_CK_GCLK8", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_EE2A0", - "CLK_FEED_EE2A1", - "CLK_FEED_EE2A2", - "CLK_FEED_EE2A3", - "CLK_FEED_EE2BEG0", - "CLK_FEED_EE2BEG1", - "CLK_FEED_EE2BEG2", - "CLK_FEED_EE2BEG3", - "CLK_FEED_EE4A0", - "CLK_FEED_EE4A1", - "CLK_FEED_EE4A2", - "CLK_FEED_EE4A3", - "CLK_FEED_EE4B0", - "CLK_FEED_EE4B1", - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_EE4BEG0", - "CLK_FEED_EE4BEG1", - "CLK_FEED_EE4BEG2", - "CLK_FEED_EE4BEG3", - "CLK_FEED_EE4C0", - "CLK_FEED_EE4C1", - "CLK_FEED_EE4C2", - "CLK_FEED_EE4C3", - "CLK_FEED_EL1BEG0", - "CLK_FEED_EL1BEG1", - "CLK_FEED_EL1BEG2", - "CLK_FEED_EL1BEG3", - "CLK_FEED_ER1BEG0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_ER1BEG2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_LH1", - "CLK_FEED_LH10", - "CLK_FEED_LH11", - "CLK_FEED_LH12", - "CLK_FEED_LH2", - "CLK_FEED_LH3", - "CLK_FEED_LH4", - "CLK_FEED_LH5", - "CLK_FEED_LH6", - "CLK_FEED_LH7", - "CLK_FEED_LH8", - "CLK_FEED_LH9", - "CLK_FEED_MONITOR_N", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A0", - "CLK_FEED_NE2A1", - "CLK_FEED_NE2A2", - "CLK_FEED_NE2A3", - "CLK_FEED_NE4BEG0", - "CLK_FEED_NE4BEG1", - "CLK_FEED_NE4BEG2", - "CLK_FEED_NE4BEG3", - "CLK_FEED_NE4C0", - "CLK_FEED_NE4C1", - "CLK_FEED_NE4C2", - "CLK_FEED_NE4C3", - "CLK_FEED_NW2A0", - "CLK_FEED_NW2A1", - "CLK_FEED_NW2A2", - "CLK_FEED_NW2A3", - "CLK_FEED_NW4A0", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4A2", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4END0", - "CLK_FEED_NW4END1", - "CLK_FEED_NW4END2", - "CLK_FEED_NW4END3", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_SE2A0", - "CLK_FEED_SE2A1", - "CLK_FEED_SE2A2", - "CLK_FEED_SE2A3", - "CLK_FEED_SE4BEG0", - "CLK_FEED_SE4BEG1", - "CLK_FEED_SE4BEG2", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SE4C0", - "CLK_FEED_SE4C1", - "CLK_FEED_SE4C2", - "CLK_FEED_SE4C3", - "CLK_FEED_SW2A0", - "CLK_FEED_SW2A1", - "CLK_FEED_SW2A2", - "CLK_FEED_SW2A3", - "CLK_FEED_SW4A0", - "CLK_FEED_SW4A1", - "CLK_FEED_SW4A2", - "CLK_FEED_SW4A3", - "CLK_FEED_SW4END0", - "CLK_FEED_SW4END1", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_FEED_WL1END0", - "CLK_FEED_WL1END1", - "CLK_FEED_WL1END2", - "CLK_FEED_WL1END3", - "CLK_FEED_WR1END0", - "CLK_FEED_WR1END1", - "CLK_FEED_WR1END2", - "CLK_FEED_WR1END3", - "CLK_FEED_WW2A0", - "CLK_FEED_WW2A1", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2A3", - "CLK_FEED_WW2END0", - "CLK_FEED_WW2END1", - "CLK_FEED_WW2END2", - "CLK_FEED_WW2END3", - "CLK_FEED_WW4A0", - "CLK_FEED_WW4A1", - "CLK_FEED_WW4A2", - "CLK_FEED_WW4A3", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4B1", - "CLK_FEED_WW4B2", - "CLK_FEED_WW4B3", - "CLK_FEED_WW4C0", - "CLK_FEED_WW4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_WW4C3", - "CLK_FEED_WW4END0", - "CLK_FEED_WW4END1", - "CLK_FEED_WW4END2", - "CLK_FEED_WW4END3", - "CLK_PMV2_A0", - "CLK_PMV2_A1", - "CLK_PMV2_A2", - "CLK_PMV2_EN", - "CLK_PMV2_O", - "CLK_PMV2_ODIV2", - "CLK_PMV2_ODIV4", - "CLK_PMV_BYP0_0", - "CLK_PMV_BYP1_0", - "CLK_PMV_BYP2_0", - "CLK_PMV_BYP3_0", - "CLK_PMV_BYP4_0", - "CLK_PMV_BYP5_0", - "CLK_PMV_BYP6_0", - "CLK_PMV_BYP7_0", - "CLK_PMV_CLK0_0", - "CLK_PMV_CLK1_0", - "CLK_PMV_CTRL0_0", - "CLK_PMV_CTRL1_0", - "CLK_PMV_FAN0_0", - "CLK_PMV_FAN1_0", - "CLK_PMV_FAN2_0", - "CLK_PMV_FAN3_0", - "CLK_PMV_FAN4_0", - "CLK_PMV_FAN5_0", - "CLK_PMV_FAN6_0", - "CLK_PMV_FAN7_0", - "CLK_PMV_IMUX0_0", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX12_0", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX15_0", - "CLK_PMV_IMUX16_0", - "CLK_PMV_IMUX17_0", - "CLK_PMV_IMUX18_0", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX1_0", - "CLK_PMV_IMUX20_0", - "CLK_PMV_IMUX21_0", - "CLK_PMV_IMUX22_0", - "CLK_PMV_IMUX23_0", - "CLK_PMV_IMUX24_0", - "CLK_PMV_IMUX25_0", - "CLK_PMV_IMUX26_0", - "CLK_PMV_IMUX27_0", - "CLK_PMV_IMUX28_0", - "CLK_PMV_IMUX29_0", - "CLK_PMV_IMUX2_0", - "CLK_PMV_IMUX30_0", - "CLK_PMV_IMUX31_0", - "CLK_PMV_IMUX32_0", - "CLK_PMV_IMUX33_0", - "CLK_PMV_IMUX34_0", - "CLK_PMV_IMUX35_0", - "CLK_PMV_IMUX36_0", - "CLK_PMV_IMUX37_0", - "CLK_PMV_IMUX38_0", - "CLK_PMV_IMUX39_0", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX40_0", - "CLK_PMV_IMUX41_0", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX43_0", - "CLK_PMV_IMUX44_0", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX46_0", - "CLK_PMV_IMUX47_0", - "CLK_PMV_IMUX4_0", - "CLK_PMV_IMUX5_0", - "CLK_PMV_IMUX6_0", - "CLK_PMV_IMUX7_0", - "CLK_PMV_IMUX8_0", - "CLK_PMV_IMUX9_0", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_PMV_LOGIC_OUTS9_0" - ] + "wires": { + "CLK_FEED_CK_BUFG_CASC0": null, + "CLK_FEED_CK_BUFG_CASC1": null, + "CLK_FEED_CK_BUFG_CASC10": null, + "CLK_FEED_CK_BUFG_CASC11": null, + "CLK_FEED_CK_BUFG_CASC12": null, + "CLK_FEED_CK_BUFG_CASC13": null, + "CLK_FEED_CK_BUFG_CASC14": null, + "CLK_FEED_CK_BUFG_CASC15": null, + "CLK_FEED_CK_BUFG_CASC16": null, + "CLK_FEED_CK_BUFG_CASC17": null, + "CLK_FEED_CK_BUFG_CASC18": null, + "CLK_FEED_CK_BUFG_CASC19": null, + "CLK_FEED_CK_BUFG_CASC2": null, + "CLK_FEED_CK_BUFG_CASC20": null, + "CLK_FEED_CK_BUFG_CASC21": null, + "CLK_FEED_CK_BUFG_CASC22": null, + "CLK_FEED_CK_BUFG_CASC23": null, + "CLK_FEED_CK_BUFG_CASC24": null, + "CLK_FEED_CK_BUFG_CASC25": null, + "CLK_FEED_CK_BUFG_CASC26": null, + "CLK_FEED_CK_BUFG_CASC27": null, + "CLK_FEED_CK_BUFG_CASC28": null, + "CLK_FEED_CK_BUFG_CASC29": null, + "CLK_FEED_CK_BUFG_CASC3": null, + "CLK_FEED_CK_BUFG_CASC30": null, + "CLK_FEED_CK_BUFG_CASC31": null, + "CLK_FEED_CK_BUFG_CASC4": null, + "CLK_FEED_CK_BUFG_CASC5": null, + "CLK_FEED_CK_BUFG_CASC6": null, + "CLK_FEED_CK_BUFG_CASC7": null, + "CLK_FEED_CK_BUFG_CASC8": null, + "CLK_FEED_CK_BUFG_CASC9": null, + "CLK_FEED_CK_GCLK0": null, + "CLK_FEED_CK_GCLK1": null, + "CLK_FEED_CK_GCLK10": null, + "CLK_FEED_CK_GCLK11": null, + "CLK_FEED_CK_GCLK12": null, + "CLK_FEED_CK_GCLK13": null, + "CLK_FEED_CK_GCLK14": null, + "CLK_FEED_CK_GCLK15": null, + "CLK_FEED_CK_GCLK16": null, + "CLK_FEED_CK_GCLK17": null, + "CLK_FEED_CK_GCLK18": null, + "CLK_FEED_CK_GCLK19": null, + "CLK_FEED_CK_GCLK2": null, + "CLK_FEED_CK_GCLK20": null, + "CLK_FEED_CK_GCLK21": null, + "CLK_FEED_CK_GCLK22": null, + "CLK_FEED_CK_GCLK23": null, + "CLK_FEED_CK_GCLK24": null, + "CLK_FEED_CK_GCLK25": null, + "CLK_FEED_CK_GCLK26": null, + "CLK_FEED_CK_GCLK27": null, + "CLK_FEED_CK_GCLK28": null, + "CLK_FEED_CK_GCLK29": null, + "CLK_FEED_CK_GCLK3": null, + "CLK_FEED_CK_GCLK30": null, + "CLK_FEED_CK_GCLK31": null, + "CLK_FEED_CK_GCLK4": null, + "CLK_FEED_CK_GCLK5": null, + "CLK_FEED_CK_GCLK6": null, + "CLK_FEED_CK_GCLK7": null, + "CLK_FEED_CK_GCLK8": null, + "CLK_FEED_CK_GCLK9": null, + "CLK_FEED_EE2A0": null, + "CLK_FEED_EE2A1": null, + "CLK_FEED_EE2A2": null, + "CLK_FEED_EE2A3": null, + "CLK_FEED_EE2BEG0": null, + "CLK_FEED_EE2BEG1": null, + "CLK_FEED_EE2BEG2": null, + "CLK_FEED_EE2BEG3": null, + "CLK_FEED_EE4A0": null, + "CLK_FEED_EE4A1": null, + "CLK_FEED_EE4A2": null, + "CLK_FEED_EE4A3": null, + "CLK_FEED_EE4B0": null, + "CLK_FEED_EE4B1": null, + "CLK_FEED_EE4B2": null, + "CLK_FEED_EE4B3": null, + "CLK_FEED_EE4BEG0": null, + "CLK_FEED_EE4BEG1": null, + "CLK_FEED_EE4BEG2": null, + "CLK_FEED_EE4BEG3": null, + "CLK_FEED_EE4C0": null, + "CLK_FEED_EE4C1": null, + "CLK_FEED_EE4C2": null, + "CLK_FEED_EE4C3": null, + "CLK_FEED_EL1BEG0": null, + "CLK_FEED_EL1BEG1": null, + "CLK_FEED_EL1BEG2": null, + "CLK_FEED_EL1BEG3": null, + "CLK_FEED_ER1BEG0": null, + "CLK_FEED_ER1BEG1": null, + "CLK_FEED_ER1BEG2": null, + "CLK_FEED_ER1BEG3": null, + "CLK_FEED_LH1": null, + "CLK_FEED_LH10": null, + "CLK_FEED_LH11": null, + "CLK_FEED_LH12": null, + "CLK_FEED_LH2": null, + "CLK_FEED_LH3": null, + "CLK_FEED_LH4": null, + "CLK_FEED_LH5": null, + "CLK_FEED_LH6": null, + "CLK_FEED_LH7": null, + "CLK_FEED_LH8": null, + "CLK_FEED_LH9": null, + "CLK_FEED_MONITOR_N": null, + "CLK_FEED_MONITOR_P": null, + "CLK_FEED_NE2A0": null, + "CLK_FEED_NE2A1": null, + "CLK_FEED_NE2A2": null, + "CLK_FEED_NE2A3": null, + "CLK_FEED_NE4BEG0": null, + "CLK_FEED_NE4BEG1": null, + "CLK_FEED_NE4BEG2": null, + "CLK_FEED_NE4BEG3": null, + "CLK_FEED_NE4C0": null, + "CLK_FEED_NE4C1": null, + "CLK_FEED_NE4C2": null, + "CLK_FEED_NE4C3": null, + "CLK_FEED_NW2A0": null, + "CLK_FEED_NW2A1": null, + "CLK_FEED_NW2A2": null, + "CLK_FEED_NW2A3": null, + "CLK_FEED_NW4A0": null, + "CLK_FEED_NW4A1": null, + "CLK_FEED_NW4A2": null, + "CLK_FEED_NW4A3": null, + "CLK_FEED_NW4END0": null, + "CLK_FEED_NW4END1": null, + "CLK_FEED_NW4END2": null, + "CLK_FEED_NW4END3": null, + "CLK_FEED_R_CK_BUFG_CASC0": null, + "CLK_FEED_R_CK_BUFG_CASC1": null, + "CLK_FEED_R_CK_BUFG_CASC10": null, + "CLK_FEED_R_CK_BUFG_CASC11": null, + "CLK_FEED_R_CK_BUFG_CASC12": null, + "CLK_FEED_R_CK_BUFG_CASC13": null, + "CLK_FEED_R_CK_BUFG_CASC14": null, + "CLK_FEED_R_CK_BUFG_CASC15": null, + "CLK_FEED_R_CK_BUFG_CASC16": null, + "CLK_FEED_R_CK_BUFG_CASC17": null, + "CLK_FEED_R_CK_BUFG_CASC18": null, + "CLK_FEED_R_CK_BUFG_CASC19": null, + "CLK_FEED_R_CK_BUFG_CASC2": null, + "CLK_FEED_R_CK_BUFG_CASC20": null, + "CLK_FEED_R_CK_BUFG_CASC21": null, + "CLK_FEED_R_CK_BUFG_CASC22": null, + "CLK_FEED_R_CK_BUFG_CASC23": null, + "CLK_FEED_R_CK_BUFG_CASC24": null, + "CLK_FEED_R_CK_BUFG_CASC25": null, + "CLK_FEED_R_CK_BUFG_CASC26": null, + "CLK_FEED_R_CK_BUFG_CASC27": null, + "CLK_FEED_R_CK_BUFG_CASC28": null, + "CLK_FEED_R_CK_BUFG_CASC29": null, + "CLK_FEED_R_CK_BUFG_CASC3": null, + "CLK_FEED_R_CK_BUFG_CASC30": null, + "CLK_FEED_R_CK_BUFG_CASC31": null, + "CLK_FEED_R_CK_BUFG_CASC4": null, + "CLK_FEED_R_CK_BUFG_CASC5": null, + "CLK_FEED_R_CK_BUFG_CASC6": null, + "CLK_FEED_R_CK_BUFG_CASC7": null, + "CLK_FEED_R_CK_BUFG_CASC8": null, + "CLK_FEED_R_CK_BUFG_CASC9": null, + "CLK_FEED_R_CK_GCLK0": null, + "CLK_FEED_R_CK_GCLK1": null, + "CLK_FEED_R_CK_GCLK10": null, + "CLK_FEED_R_CK_GCLK11": null, + "CLK_FEED_R_CK_GCLK12": null, + "CLK_FEED_R_CK_GCLK13": null, + "CLK_FEED_R_CK_GCLK14": null, + "CLK_FEED_R_CK_GCLK15": null, + "CLK_FEED_R_CK_GCLK16": null, + "CLK_FEED_R_CK_GCLK17": null, + "CLK_FEED_R_CK_GCLK18": null, + "CLK_FEED_R_CK_GCLK19": null, + "CLK_FEED_R_CK_GCLK2": null, + "CLK_FEED_R_CK_GCLK20": null, + "CLK_FEED_R_CK_GCLK21": null, + "CLK_FEED_R_CK_GCLK22": null, + "CLK_FEED_R_CK_GCLK23": null, + "CLK_FEED_R_CK_GCLK24": null, + "CLK_FEED_R_CK_GCLK25": null, + "CLK_FEED_R_CK_GCLK26": null, + "CLK_FEED_R_CK_GCLK27": null, + "CLK_FEED_R_CK_GCLK28": null, + "CLK_FEED_R_CK_GCLK29": null, + "CLK_FEED_R_CK_GCLK3": null, + "CLK_FEED_R_CK_GCLK30": null, + "CLK_FEED_R_CK_GCLK31": null, + "CLK_FEED_R_CK_GCLK4": null, + "CLK_FEED_R_CK_GCLK5": null, + "CLK_FEED_R_CK_GCLK6": null, + "CLK_FEED_R_CK_GCLK7": null, + "CLK_FEED_R_CK_GCLK8": null, + "CLK_FEED_R_CK_GCLK9": null, + "CLK_FEED_SE2A0": null, + "CLK_FEED_SE2A1": null, + "CLK_FEED_SE2A2": null, + "CLK_FEED_SE2A3": null, + "CLK_FEED_SE4BEG0": null, + "CLK_FEED_SE4BEG1": null, + "CLK_FEED_SE4BEG2": null, + "CLK_FEED_SE4BEG3": null, + "CLK_FEED_SE4C0": null, + "CLK_FEED_SE4C1": null, + "CLK_FEED_SE4C2": null, + "CLK_FEED_SE4C3": null, + "CLK_FEED_SW2A0": null, + "CLK_FEED_SW2A1": null, + "CLK_FEED_SW2A2": null, + "CLK_FEED_SW2A3": null, + "CLK_FEED_SW4A0": null, + "CLK_FEED_SW4A1": null, + "CLK_FEED_SW4A2": null, + "CLK_FEED_SW4A3": null, + "CLK_FEED_SW4END0": null, + "CLK_FEED_SW4END1": null, + "CLK_FEED_SW4END2": null, + "CLK_FEED_SW4END3": null, + "CLK_FEED_WL1END0": null, + "CLK_FEED_WL1END1": null, + "CLK_FEED_WL1END2": null, + "CLK_FEED_WL1END3": null, + "CLK_FEED_WR1END0": null, + "CLK_FEED_WR1END1": null, + "CLK_FEED_WR1END2": null, + "CLK_FEED_WR1END3": null, + "CLK_FEED_WW2A0": null, + "CLK_FEED_WW2A1": null, + "CLK_FEED_WW2A2": null, + "CLK_FEED_WW2A3": null, + "CLK_FEED_WW2END0": null, + "CLK_FEED_WW2END1": null, + "CLK_FEED_WW2END2": null, + "CLK_FEED_WW2END3": null, + "CLK_FEED_WW4A0": null, + "CLK_FEED_WW4A1": null, + "CLK_FEED_WW4A2": null, + "CLK_FEED_WW4A3": null, + "CLK_FEED_WW4B0": null, + "CLK_FEED_WW4B1": null, + "CLK_FEED_WW4B2": null, + "CLK_FEED_WW4B3": null, + "CLK_FEED_WW4C0": null, + "CLK_FEED_WW4C1": null, + "CLK_FEED_WW4C2": null, + "CLK_FEED_WW4C3": null, + "CLK_FEED_WW4END0": null, + "CLK_FEED_WW4END1": null, + "CLK_FEED_WW4END2": null, + "CLK_FEED_WW4END3": null, + "CLK_PMV2_A0": null, + "CLK_PMV2_A1": null, + "CLK_PMV2_A2": null, + "CLK_PMV2_EN": null, + "CLK_PMV2_O": null, + "CLK_PMV2_ODIV2": null, + "CLK_PMV2_ODIV4": null, + "CLK_PMV_BYP0_0": null, + "CLK_PMV_BYP1_0": null, + "CLK_PMV_BYP2_0": null, + "CLK_PMV_BYP3_0": null, + "CLK_PMV_BYP4_0": null, + "CLK_PMV_BYP5_0": null, + "CLK_PMV_BYP6_0": null, + "CLK_PMV_BYP7_0": null, + "CLK_PMV_CLK0_0": null, + "CLK_PMV_CLK1_0": null, + "CLK_PMV_CTRL0_0": null, + "CLK_PMV_CTRL1_0": null, + "CLK_PMV_FAN0_0": null, + "CLK_PMV_FAN1_0": null, + "CLK_PMV_FAN2_0": null, + "CLK_PMV_FAN3_0": null, + "CLK_PMV_FAN4_0": null, + "CLK_PMV_FAN5_0": null, + "CLK_PMV_FAN6_0": null, + "CLK_PMV_FAN7_0": null, + "CLK_PMV_IMUX0_0": null, + "CLK_PMV_IMUX10_0": null, + "CLK_PMV_IMUX11_0": null, + "CLK_PMV_IMUX12_0": null, + "CLK_PMV_IMUX13_0": null, + "CLK_PMV_IMUX14_0": null, + "CLK_PMV_IMUX15_0": null, + "CLK_PMV_IMUX16_0": null, + "CLK_PMV_IMUX17_0": null, + "CLK_PMV_IMUX18_0": null, + "CLK_PMV_IMUX19_0": null, + "CLK_PMV_IMUX1_0": null, + "CLK_PMV_IMUX20_0": null, + "CLK_PMV_IMUX21_0": null, + "CLK_PMV_IMUX22_0": null, + "CLK_PMV_IMUX23_0": null, + "CLK_PMV_IMUX24_0": null, + "CLK_PMV_IMUX25_0": null, + "CLK_PMV_IMUX26_0": null, + "CLK_PMV_IMUX27_0": null, + "CLK_PMV_IMUX28_0": null, + "CLK_PMV_IMUX29_0": null, + "CLK_PMV_IMUX2_0": null, + "CLK_PMV_IMUX30_0": null, + "CLK_PMV_IMUX31_0": null, + "CLK_PMV_IMUX32_0": null, + "CLK_PMV_IMUX33_0": null, + "CLK_PMV_IMUX34_0": null, + "CLK_PMV_IMUX35_0": null, + "CLK_PMV_IMUX36_0": null, + "CLK_PMV_IMUX37_0": null, + "CLK_PMV_IMUX38_0": null, + "CLK_PMV_IMUX39_0": null, + "CLK_PMV_IMUX3_0": null, + "CLK_PMV_IMUX40_0": null, + "CLK_PMV_IMUX41_0": null, + "CLK_PMV_IMUX42_0": null, + "CLK_PMV_IMUX43_0": null, + "CLK_PMV_IMUX44_0": null, + "CLK_PMV_IMUX45_0": null, + "CLK_PMV_IMUX46_0": null, + "CLK_PMV_IMUX47_0": null, + "CLK_PMV_IMUX4_0": null, + "CLK_PMV_IMUX5_0": null, + "CLK_PMV_IMUX6_0": null, + "CLK_PMV_IMUX7_0": null, + "CLK_PMV_IMUX8_0": null, + "CLK_PMV_IMUX9_0": null, + "CLK_PMV_LOGIC_OUTS0_0": null, + "CLK_PMV_LOGIC_OUTS10_0": null, + "CLK_PMV_LOGIC_OUTS11_0": null, + "CLK_PMV_LOGIC_OUTS12_0": null, + "CLK_PMV_LOGIC_OUTS13_0": null, + "CLK_PMV_LOGIC_OUTS14_0": null, + "CLK_PMV_LOGIC_OUTS15_0": null, + "CLK_PMV_LOGIC_OUTS16_0": null, + "CLK_PMV_LOGIC_OUTS17_0": null, + "CLK_PMV_LOGIC_OUTS18_0": null, + "CLK_PMV_LOGIC_OUTS19_0": null, + "CLK_PMV_LOGIC_OUTS1_0": null, + "CLK_PMV_LOGIC_OUTS20_0": null, + "CLK_PMV_LOGIC_OUTS21_0": null, + "CLK_PMV_LOGIC_OUTS22_0": null, + "CLK_PMV_LOGIC_OUTS23_0": null, + "CLK_PMV_LOGIC_OUTS2_0": null, + "CLK_PMV_LOGIC_OUTS3_0": null, + "CLK_PMV_LOGIC_OUTS4_0": null, + "CLK_PMV_LOGIC_OUTS5_0": null, + "CLK_PMV_LOGIC_OUTS6_0": null, + "CLK_PMV_LOGIC_OUTS7_0": null, + "CLK_PMV_LOGIC_OUTS8_0": null, + "CLK_PMV_LOGIC_OUTS9_0": null + } } diff --git a/zynq7/tile_type_CLK_PMVIOB.json b/zynq7/tile_type_CLK_PMVIOB.json index b51a015..2b494ef 100644 --- a/zynq7/tile_type_CLK_PMVIOB.json +++ b/zynq7/tile_type_CLK_PMVIOB.json @@ -2,358 +2,358 @@ "pips": {}, "sites": [], "tile_type": "CLK_PMVIOB", - "wires": [ - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK0", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK10", - "CLK_FEED_CK_GCLK11", - "CLK_FEED_CK_GCLK12", - "CLK_FEED_CK_GCLK13", - "CLK_FEED_CK_GCLK14", - "CLK_FEED_CK_GCLK15", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_CK_GCLK19", - "CLK_FEED_CK_GCLK2", - "CLK_FEED_CK_GCLK20", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK22", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_CK_GCLK30", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_CK_GCLK5", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_CK_GCLK8", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_EE2A0", - "CLK_FEED_EE2A1", - "CLK_FEED_EE2A2", - "CLK_FEED_EE2A3", - "CLK_FEED_EE2BEG0", - "CLK_FEED_EE2BEG1", - "CLK_FEED_EE2BEG2", - "CLK_FEED_EE2BEG3", - "CLK_FEED_EE4A0", - "CLK_FEED_EE4A1", - "CLK_FEED_EE4A2", - "CLK_FEED_EE4A3", - "CLK_FEED_EE4B0", - "CLK_FEED_EE4B1", - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_EE4BEG0", - "CLK_FEED_EE4BEG1", - "CLK_FEED_EE4BEG2", - "CLK_FEED_EE4BEG3", - "CLK_FEED_EE4C0", - "CLK_FEED_EE4C1", - "CLK_FEED_EE4C2", - "CLK_FEED_EE4C3", - "CLK_FEED_EL1BEG0", - "CLK_FEED_EL1BEG1", - "CLK_FEED_EL1BEG2", - "CLK_FEED_EL1BEG3", - "CLK_FEED_ER1BEG0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_ER1BEG2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_LH1", - "CLK_FEED_LH10", - "CLK_FEED_LH11", - "CLK_FEED_LH12", - "CLK_FEED_LH2", - "CLK_FEED_LH3", - "CLK_FEED_LH4", - "CLK_FEED_LH5", - "CLK_FEED_LH6", - "CLK_FEED_LH7", - "CLK_FEED_LH8", - "CLK_FEED_LH9", - "CLK_FEED_MONITOR_N", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A0", - "CLK_FEED_NE2A1", - "CLK_FEED_NE2A2", - "CLK_FEED_NE2A3", - "CLK_FEED_NE4BEG0", - "CLK_FEED_NE4BEG1", - "CLK_FEED_NE4BEG2", - "CLK_FEED_NE4BEG3", - "CLK_FEED_NE4C0", - "CLK_FEED_NE4C1", - "CLK_FEED_NE4C2", - "CLK_FEED_NE4C3", - "CLK_FEED_NW2A0", - "CLK_FEED_NW2A1", - "CLK_FEED_NW2A2", - "CLK_FEED_NW2A3", - "CLK_FEED_NW4A0", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4A2", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4END0", - "CLK_FEED_NW4END1", - "CLK_FEED_NW4END2", - "CLK_FEED_NW4END3", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_SE2A0", - "CLK_FEED_SE2A1", - "CLK_FEED_SE2A2", - "CLK_FEED_SE2A3", - "CLK_FEED_SE4BEG0", - "CLK_FEED_SE4BEG1", - "CLK_FEED_SE4BEG2", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SE4C0", - "CLK_FEED_SE4C1", - "CLK_FEED_SE4C2", - "CLK_FEED_SE4C3", - "CLK_FEED_SW2A0", - "CLK_FEED_SW2A1", - "CLK_FEED_SW2A2", - "CLK_FEED_SW2A3", - "CLK_FEED_SW4A0", - "CLK_FEED_SW4A1", - "CLK_FEED_SW4A2", - "CLK_FEED_SW4A3", - "CLK_FEED_SW4END0", - "CLK_FEED_SW4END1", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_FEED_WL1END0", - "CLK_FEED_WL1END1", - "CLK_FEED_WL1END2", - "CLK_FEED_WL1END3", - "CLK_FEED_WR1END0", - "CLK_FEED_WR1END1", - "CLK_FEED_WR1END2", - "CLK_FEED_WR1END3", - "CLK_FEED_WW2A0", - "CLK_FEED_WW2A1", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2A3", - "CLK_FEED_WW2END0", - "CLK_FEED_WW2END1", - "CLK_FEED_WW2END2", - "CLK_FEED_WW2END3", - "CLK_FEED_WW4A0", - "CLK_FEED_WW4A1", - "CLK_FEED_WW4A2", - "CLK_FEED_WW4A3", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4B1", - "CLK_FEED_WW4B2", - "CLK_FEED_WW4B3", - "CLK_FEED_WW4C0", - "CLK_FEED_WW4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_WW4C3", - "CLK_FEED_WW4END0", - "CLK_FEED_WW4END1", - "CLK_FEED_WW4END2", - "CLK_FEED_WW4END3", - "CLK_PMVIOB_A0", - "CLK_PMVIOB_A1", - "CLK_PMVIOB_EN", - "CLK_PMVIOB_O", - "CLK_PMVIOB_ODIV2", - "CLK_PMVIOB_ODIV4", - "CLK_PMV_BYP0_0", - "CLK_PMV_BYP1_0", - "CLK_PMV_BYP2_0", - "CLK_PMV_BYP3_0", - "CLK_PMV_BYP4_0", - "CLK_PMV_BYP5_0", - "CLK_PMV_BYP6_0", - "CLK_PMV_BYP7_0", - "CLK_PMV_CLK0_0", - "CLK_PMV_CLK1_0", - "CLK_PMV_CTRL0_0", - "CLK_PMV_CTRL1_0", - "CLK_PMV_FAN0_0", - "CLK_PMV_FAN1_0", - "CLK_PMV_FAN2_0", - "CLK_PMV_FAN3_0", - "CLK_PMV_FAN4_0", - "CLK_PMV_FAN5_0", - "CLK_PMV_FAN6_0", - "CLK_PMV_FAN7_0", - "CLK_PMV_IMUX0_0", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX12_0", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX15_0", - "CLK_PMV_IMUX16_0", - "CLK_PMV_IMUX17_0", - "CLK_PMV_IMUX18_0", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX1_0", - "CLK_PMV_IMUX20_0", - "CLK_PMV_IMUX21_0", - "CLK_PMV_IMUX22_0", - "CLK_PMV_IMUX23_0", - "CLK_PMV_IMUX24_0", - "CLK_PMV_IMUX25_0", - "CLK_PMV_IMUX26_0", - "CLK_PMV_IMUX27_0", - "CLK_PMV_IMUX28_0", - "CLK_PMV_IMUX29_0", - "CLK_PMV_IMUX2_0", - "CLK_PMV_IMUX30_0", - "CLK_PMV_IMUX31_0", - "CLK_PMV_IMUX32_0", - "CLK_PMV_IMUX33_0", - "CLK_PMV_IMUX34_0", - "CLK_PMV_IMUX35_0", - "CLK_PMV_IMUX36_0", - "CLK_PMV_IMUX37_0", - "CLK_PMV_IMUX38_0", - "CLK_PMV_IMUX39_0", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX40_0", - "CLK_PMV_IMUX41_0", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX43_0", - "CLK_PMV_IMUX44_0", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX46_0", - "CLK_PMV_IMUX47_0", - "CLK_PMV_IMUX4_0", - "CLK_PMV_IMUX5_0", - "CLK_PMV_IMUX6_0", - "CLK_PMV_IMUX7_0", - "CLK_PMV_IMUX8_0", - "CLK_PMV_IMUX9_0", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_PMV_LOGIC_OUTS9_0" - ] + "wires": { + "CLK_FEED_CK_BUFG_CASC0": null, + "CLK_FEED_CK_BUFG_CASC1": null, + "CLK_FEED_CK_BUFG_CASC10": null, + "CLK_FEED_CK_BUFG_CASC11": null, + "CLK_FEED_CK_BUFG_CASC12": null, + "CLK_FEED_CK_BUFG_CASC13": null, + "CLK_FEED_CK_BUFG_CASC14": null, + "CLK_FEED_CK_BUFG_CASC15": null, + "CLK_FEED_CK_BUFG_CASC16": null, + "CLK_FEED_CK_BUFG_CASC17": null, + "CLK_FEED_CK_BUFG_CASC18": null, + "CLK_FEED_CK_BUFG_CASC19": null, + "CLK_FEED_CK_BUFG_CASC2": null, + "CLK_FEED_CK_BUFG_CASC20": null, + "CLK_FEED_CK_BUFG_CASC21": null, + "CLK_FEED_CK_BUFG_CASC22": null, + "CLK_FEED_CK_BUFG_CASC23": null, + "CLK_FEED_CK_BUFG_CASC24": null, + "CLK_FEED_CK_BUFG_CASC25": null, + "CLK_FEED_CK_BUFG_CASC26": null, + "CLK_FEED_CK_BUFG_CASC27": null, + "CLK_FEED_CK_BUFG_CASC28": null, + "CLK_FEED_CK_BUFG_CASC29": null, + "CLK_FEED_CK_BUFG_CASC3": null, + "CLK_FEED_CK_BUFG_CASC30": null, + "CLK_FEED_CK_BUFG_CASC31": null, + "CLK_FEED_CK_BUFG_CASC4": null, + "CLK_FEED_CK_BUFG_CASC5": null, + "CLK_FEED_CK_BUFG_CASC6": null, + "CLK_FEED_CK_BUFG_CASC7": null, + "CLK_FEED_CK_BUFG_CASC8": null, + "CLK_FEED_CK_BUFG_CASC9": null, + "CLK_FEED_CK_GCLK0": null, + "CLK_FEED_CK_GCLK1": null, + "CLK_FEED_CK_GCLK10": null, + "CLK_FEED_CK_GCLK11": null, + "CLK_FEED_CK_GCLK12": null, + "CLK_FEED_CK_GCLK13": null, + "CLK_FEED_CK_GCLK14": null, + "CLK_FEED_CK_GCLK15": null, + "CLK_FEED_CK_GCLK16": null, + "CLK_FEED_CK_GCLK17": null, + "CLK_FEED_CK_GCLK18": null, + "CLK_FEED_CK_GCLK19": null, + "CLK_FEED_CK_GCLK2": null, + "CLK_FEED_CK_GCLK20": null, + "CLK_FEED_CK_GCLK21": null, + "CLK_FEED_CK_GCLK22": null, + "CLK_FEED_CK_GCLK23": null, + "CLK_FEED_CK_GCLK24": null, + "CLK_FEED_CK_GCLK25": null, + "CLK_FEED_CK_GCLK26": null, + "CLK_FEED_CK_GCLK27": null, + "CLK_FEED_CK_GCLK28": null, + "CLK_FEED_CK_GCLK29": null, + "CLK_FEED_CK_GCLK3": null, + "CLK_FEED_CK_GCLK30": null, + "CLK_FEED_CK_GCLK31": null, + "CLK_FEED_CK_GCLK4": null, + "CLK_FEED_CK_GCLK5": null, + "CLK_FEED_CK_GCLK6": null, + "CLK_FEED_CK_GCLK7": null, + "CLK_FEED_CK_GCLK8": null, + "CLK_FEED_CK_GCLK9": null, + "CLK_FEED_EE2A0": null, + "CLK_FEED_EE2A1": null, + "CLK_FEED_EE2A2": null, + "CLK_FEED_EE2A3": null, + "CLK_FEED_EE2BEG0": null, + "CLK_FEED_EE2BEG1": null, + "CLK_FEED_EE2BEG2": null, + "CLK_FEED_EE2BEG3": null, + "CLK_FEED_EE4A0": null, + "CLK_FEED_EE4A1": null, + "CLK_FEED_EE4A2": null, + "CLK_FEED_EE4A3": null, + "CLK_FEED_EE4B0": null, + "CLK_FEED_EE4B1": null, + "CLK_FEED_EE4B2": null, + "CLK_FEED_EE4B3": null, + "CLK_FEED_EE4BEG0": null, + "CLK_FEED_EE4BEG1": null, + "CLK_FEED_EE4BEG2": null, + "CLK_FEED_EE4BEG3": null, + "CLK_FEED_EE4C0": null, + "CLK_FEED_EE4C1": null, + "CLK_FEED_EE4C2": null, + "CLK_FEED_EE4C3": null, + "CLK_FEED_EL1BEG0": null, + "CLK_FEED_EL1BEG1": null, + "CLK_FEED_EL1BEG2": null, + "CLK_FEED_EL1BEG3": null, + "CLK_FEED_ER1BEG0": null, + "CLK_FEED_ER1BEG1": null, + "CLK_FEED_ER1BEG2": null, + "CLK_FEED_ER1BEG3": null, + "CLK_FEED_LH1": null, + "CLK_FEED_LH10": null, + "CLK_FEED_LH11": null, + "CLK_FEED_LH12": null, + "CLK_FEED_LH2": null, + "CLK_FEED_LH3": null, + "CLK_FEED_LH4": null, + "CLK_FEED_LH5": null, + "CLK_FEED_LH6": null, + "CLK_FEED_LH7": null, + "CLK_FEED_LH8": null, + "CLK_FEED_LH9": null, + "CLK_FEED_MONITOR_N": null, + "CLK_FEED_MONITOR_P": null, + "CLK_FEED_NE2A0": null, + "CLK_FEED_NE2A1": null, + "CLK_FEED_NE2A2": null, + "CLK_FEED_NE2A3": null, + "CLK_FEED_NE4BEG0": null, + "CLK_FEED_NE4BEG1": null, + "CLK_FEED_NE4BEG2": null, + "CLK_FEED_NE4BEG3": null, + "CLK_FEED_NE4C0": null, + "CLK_FEED_NE4C1": null, + "CLK_FEED_NE4C2": null, + "CLK_FEED_NE4C3": null, + "CLK_FEED_NW2A0": null, + "CLK_FEED_NW2A1": null, + "CLK_FEED_NW2A2": null, + "CLK_FEED_NW2A3": null, + "CLK_FEED_NW4A0": null, + "CLK_FEED_NW4A1": null, + "CLK_FEED_NW4A2": null, + "CLK_FEED_NW4A3": null, + "CLK_FEED_NW4END0": null, + "CLK_FEED_NW4END1": null, + "CLK_FEED_NW4END2": null, + "CLK_FEED_NW4END3": null, + "CLK_FEED_R_CK_BUFG_CASC0": null, + "CLK_FEED_R_CK_BUFG_CASC1": null, + "CLK_FEED_R_CK_BUFG_CASC10": null, + "CLK_FEED_R_CK_BUFG_CASC11": null, + "CLK_FEED_R_CK_BUFG_CASC12": null, + "CLK_FEED_R_CK_BUFG_CASC13": null, + "CLK_FEED_R_CK_BUFG_CASC14": null, + "CLK_FEED_R_CK_BUFG_CASC15": null, + "CLK_FEED_R_CK_BUFG_CASC16": null, + "CLK_FEED_R_CK_BUFG_CASC17": null, + "CLK_FEED_R_CK_BUFG_CASC18": null, + "CLK_FEED_R_CK_BUFG_CASC19": null, + "CLK_FEED_R_CK_BUFG_CASC2": null, + "CLK_FEED_R_CK_BUFG_CASC20": null, + "CLK_FEED_R_CK_BUFG_CASC21": null, + "CLK_FEED_R_CK_BUFG_CASC22": null, + "CLK_FEED_R_CK_BUFG_CASC23": null, + "CLK_FEED_R_CK_BUFG_CASC24": null, + "CLK_FEED_R_CK_BUFG_CASC25": null, + "CLK_FEED_R_CK_BUFG_CASC26": null, + "CLK_FEED_R_CK_BUFG_CASC27": null, + "CLK_FEED_R_CK_BUFG_CASC28": null, + "CLK_FEED_R_CK_BUFG_CASC29": null, + "CLK_FEED_R_CK_BUFG_CASC3": null, + "CLK_FEED_R_CK_BUFG_CASC30": null, + "CLK_FEED_R_CK_BUFG_CASC31": null, + "CLK_FEED_R_CK_BUFG_CASC4": null, + "CLK_FEED_R_CK_BUFG_CASC5": null, + "CLK_FEED_R_CK_BUFG_CASC6": null, + "CLK_FEED_R_CK_BUFG_CASC7": null, + "CLK_FEED_R_CK_BUFG_CASC8": null, + "CLK_FEED_R_CK_BUFG_CASC9": null, + "CLK_FEED_R_CK_GCLK0": null, + "CLK_FEED_R_CK_GCLK1": null, + "CLK_FEED_R_CK_GCLK10": null, + "CLK_FEED_R_CK_GCLK11": null, + "CLK_FEED_R_CK_GCLK12": null, + "CLK_FEED_R_CK_GCLK13": null, + "CLK_FEED_R_CK_GCLK14": null, + "CLK_FEED_R_CK_GCLK15": null, + "CLK_FEED_R_CK_GCLK16": null, + "CLK_FEED_R_CK_GCLK17": null, + "CLK_FEED_R_CK_GCLK18": null, + "CLK_FEED_R_CK_GCLK19": null, + "CLK_FEED_R_CK_GCLK2": null, + "CLK_FEED_R_CK_GCLK20": null, + "CLK_FEED_R_CK_GCLK21": null, + "CLK_FEED_R_CK_GCLK22": null, + "CLK_FEED_R_CK_GCLK23": null, + "CLK_FEED_R_CK_GCLK24": null, + "CLK_FEED_R_CK_GCLK25": null, + "CLK_FEED_R_CK_GCLK26": null, + "CLK_FEED_R_CK_GCLK27": null, + "CLK_FEED_R_CK_GCLK28": null, + "CLK_FEED_R_CK_GCLK29": null, + "CLK_FEED_R_CK_GCLK3": null, + "CLK_FEED_R_CK_GCLK30": null, + "CLK_FEED_R_CK_GCLK31": null, + "CLK_FEED_R_CK_GCLK4": null, + "CLK_FEED_R_CK_GCLK5": null, + "CLK_FEED_R_CK_GCLK6": null, + "CLK_FEED_R_CK_GCLK7": null, + "CLK_FEED_R_CK_GCLK8": null, + "CLK_FEED_R_CK_GCLK9": null, + "CLK_FEED_SE2A0": null, + "CLK_FEED_SE2A1": null, + "CLK_FEED_SE2A2": null, + "CLK_FEED_SE2A3": null, + "CLK_FEED_SE4BEG0": null, + "CLK_FEED_SE4BEG1": null, + "CLK_FEED_SE4BEG2": null, + "CLK_FEED_SE4BEG3": null, + "CLK_FEED_SE4C0": null, + "CLK_FEED_SE4C1": null, + "CLK_FEED_SE4C2": null, + "CLK_FEED_SE4C3": null, + "CLK_FEED_SW2A0": null, + "CLK_FEED_SW2A1": null, + "CLK_FEED_SW2A2": null, + "CLK_FEED_SW2A3": null, + "CLK_FEED_SW4A0": null, + "CLK_FEED_SW4A1": null, + "CLK_FEED_SW4A2": null, + "CLK_FEED_SW4A3": null, + "CLK_FEED_SW4END0": null, + "CLK_FEED_SW4END1": null, + "CLK_FEED_SW4END2": null, + "CLK_FEED_SW4END3": null, + "CLK_FEED_WL1END0": null, + "CLK_FEED_WL1END1": null, + "CLK_FEED_WL1END2": null, + "CLK_FEED_WL1END3": null, + "CLK_FEED_WR1END0": null, + "CLK_FEED_WR1END1": null, + "CLK_FEED_WR1END2": null, + "CLK_FEED_WR1END3": null, + "CLK_FEED_WW2A0": null, + "CLK_FEED_WW2A1": null, + "CLK_FEED_WW2A2": null, + "CLK_FEED_WW2A3": null, + "CLK_FEED_WW2END0": null, + "CLK_FEED_WW2END1": null, + "CLK_FEED_WW2END2": null, + "CLK_FEED_WW2END3": null, + "CLK_FEED_WW4A0": null, + "CLK_FEED_WW4A1": null, + "CLK_FEED_WW4A2": null, + "CLK_FEED_WW4A3": null, + "CLK_FEED_WW4B0": null, + "CLK_FEED_WW4B1": null, + "CLK_FEED_WW4B2": null, + "CLK_FEED_WW4B3": null, + "CLK_FEED_WW4C0": null, + "CLK_FEED_WW4C1": null, + "CLK_FEED_WW4C2": null, + "CLK_FEED_WW4C3": null, + "CLK_FEED_WW4END0": null, + "CLK_FEED_WW4END1": null, + "CLK_FEED_WW4END2": null, + "CLK_FEED_WW4END3": null, + "CLK_PMVIOB_A0": null, + "CLK_PMVIOB_A1": null, + "CLK_PMVIOB_EN": null, + "CLK_PMVIOB_O": null, + "CLK_PMVIOB_ODIV2": null, + "CLK_PMVIOB_ODIV4": null, + "CLK_PMV_BYP0_0": null, + "CLK_PMV_BYP1_0": null, + "CLK_PMV_BYP2_0": null, + "CLK_PMV_BYP3_0": null, + "CLK_PMV_BYP4_0": null, + "CLK_PMV_BYP5_0": null, + "CLK_PMV_BYP6_0": null, + "CLK_PMV_BYP7_0": null, + "CLK_PMV_CLK0_0": null, + "CLK_PMV_CLK1_0": null, + "CLK_PMV_CTRL0_0": null, + "CLK_PMV_CTRL1_0": null, + "CLK_PMV_FAN0_0": null, + "CLK_PMV_FAN1_0": null, + "CLK_PMV_FAN2_0": null, + "CLK_PMV_FAN3_0": null, + "CLK_PMV_FAN4_0": null, + "CLK_PMV_FAN5_0": null, + "CLK_PMV_FAN6_0": null, + "CLK_PMV_FAN7_0": null, + "CLK_PMV_IMUX0_0": null, + "CLK_PMV_IMUX10_0": null, + "CLK_PMV_IMUX11_0": null, + "CLK_PMV_IMUX12_0": null, + "CLK_PMV_IMUX13_0": null, + "CLK_PMV_IMUX14_0": null, + "CLK_PMV_IMUX15_0": null, + "CLK_PMV_IMUX16_0": null, + "CLK_PMV_IMUX17_0": null, + "CLK_PMV_IMUX18_0": null, + "CLK_PMV_IMUX19_0": null, + "CLK_PMV_IMUX1_0": null, + "CLK_PMV_IMUX20_0": null, + "CLK_PMV_IMUX21_0": null, + "CLK_PMV_IMUX22_0": null, + "CLK_PMV_IMUX23_0": null, + "CLK_PMV_IMUX24_0": null, + "CLK_PMV_IMUX25_0": null, + "CLK_PMV_IMUX26_0": null, + "CLK_PMV_IMUX27_0": null, + "CLK_PMV_IMUX28_0": null, + "CLK_PMV_IMUX29_0": null, + "CLK_PMV_IMUX2_0": null, + "CLK_PMV_IMUX30_0": null, + "CLK_PMV_IMUX31_0": null, + "CLK_PMV_IMUX32_0": null, + "CLK_PMV_IMUX33_0": null, + "CLK_PMV_IMUX34_0": null, + "CLK_PMV_IMUX35_0": null, + "CLK_PMV_IMUX36_0": null, + "CLK_PMV_IMUX37_0": null, + "CLK_PMV_IMUX38_0": null, + "CLK_PMV_IMUX39_0": null, + "CLK_PMV_IMUX3_0": null, + "CLK_PMV_IMUX40_0": null, + "CLK_PMV_IMUX41_0": null, + "CLK_PMV_IMUX42_0": null, + "CLK_PMV_IMUX43_0": null, + "CLK_PMV_IMUX44_0": null, + "CLK_PMV_IMUX45_0": null, + "CLK_PMV_IMUX46_0": null, + "CLK_PMV_IMUX47_0": null, + "CLK_PMV_IMUX4_0": null, + "CLK_PMV_IMUX5_0": null, + "CLK_PMV_IMUX6_0": null, + "CLK_PMV_IMUX7_0": null, + "CLK_PMV_IMUX8_0": null, + "CLK_PMV_IMUX9_0": null, + "CLK_PMV_LOGIC_OUTS0_0": null, + "CLK_PMV_LOGIC_OUTS10_0": null, + "CLK_PMV_LOGIC_OUTS11_0": null, + "CLK_PMV_LOGIC_OUTS12_0": null, + "CLK_PMV_LOGIC_OUTS13_0": null, + "CLK_PMV_LOGIC_OUTS14_0": null, + "CLK_PMV_LOGIC_OUTS15_0": null, + "CLK_PMV_LOGIC_OUTS16_0": null, + "CLK_PMV_LOGIC_OUTS17_0": null, + "CLK_PMV_LOGIC_OUTS18_0": null, + "CLK_PMV_LOGIC_OUTS19_0": null, + "CLK_PMV_LOGIC_OUTS1_0": null, + "CLK_PMV_LOGIC_OUTS20_0": null, + "CLK_PMV_LOGIC_OUTS21_0": null, + "CLK_PMV_LOGIC_OUTS22_0": null, + "CLK_PMV_LOGIC_OUTS23_0": null, + "CLK_PMV_LOGIC_OUTS2_0": null, + "CLK_PMV_LOGIC_OUTS3_0": null, + "CLK_PMV_LOGIC_OUTS4_0": null, + "CLK_PMV_LOGIC_OUTS5_0": null, + "CLK_PMV_LOGIC_OUTS6_0": null, + "CLK_PMV_LOGIC_OUTS7_0": null, + "CLK_PMV_LOGIC_OUTS8_0": null, + "CLK_PMV_LOGIC_OUTS9_0": null + } } diff --git a/zynq7/tile_type_CLK_TERM.json b/zynq7/tile_type_CLK_TERM.json index 5bf23c2..40014e1 100644 --- a/zynq7/tile_type_CLK_TERM.json +++ b/zynq7/tile_type_CLK_TERM.json @@ -2,70 +2,70 @@ "pips": {}, "sites": [], "tile_type": "CLK_TERM", - "wires": [ - "CLK_TERM_GCLK0", - "CLK_TERM_GCLK1", - "CLK_TERM_GCLK10", - "CLK_TERM_GCLK11", - "CLK_TERM_GCLK12", - "CLK_TERM_GCLK13", - "CLK_TERM_GCLK14", - "CLK_TERM_GCLK15", - "CLK_TERM_GCLK16", - "CLK_TERM_GCLK17", - "CLK_TERM_GCLK18", - "CLK_TERM_GCLK19", - "CLK_TERM_GCLK2", - "CLK_TERM_GCLK20", - "CLK_TERM_GCLK21", - "CLK_TERM_GCLK22", - "CLK_TERM_GCLK23", - "CLK_TERM_GCLK24", - "CLK_TERM_GCLK25", - "CLK_TERM_GCLK26", - "CLK_TERM_GCLK27", - "CLK_TERM_GCLK28", - "CLK_TERM_GCLK29", - "CLK_TERM_GCLK3", - "CLK_TERM_GCLK30", - "CLK_TERM_GCLK31", - "CLK_TERM_GCLK4", - "CLK_TERM_GCLK5", - "CLK_TERM_GCLK6", - "CLK_TERM_GCLK7", - "CLK_TERM_GCLK8", - "CLK_TERM_GCLK9", - "CLK_TERM_R_GCLK0", - "CLK_TERM_R_GCLK1", - "CLK_TERM_R_GCLK10", - "CLK_TERM_R_GCLK11", - "CLK_TERM_R_GCLK12", - "CLK_TERM_R_GCLK13", - "CLK_TERM_R_GCLK14", - "CLK_TERM_R_GCLK15", - "CLK_TERM_R_GCLK16", - "CLK_TERM_R_GCLK17", - "CLK_TERM_R_GCLK18", - "CLK_TERM_R_GCLK19", - "CLK_TERM_R_GCLK2", - "CLK_TERM_R_GCLK20", - "CLK_TERM_R_GCLK21", - "CLK_TERM_R_GCLK22", - "CLK_TERM_R_GCLK23", - "CLK_TERM_R_GCLK24", - "CLK_TERM_R_GCLK25", - "CLK_TERM_R_GCLK26", - "CLK_TERM_R_GCLK27", - "CLK_TERM_R_GCLK28", - "CLK_TERM_R_GCLK29", - "CLK_TERM_R_GCLK3", - "CLK_TERM_R_GCLK30", - "CLK_TERM_R_GCLK31", - "CLK_TERM_R_GCLK4", - "CLK_TERM_R_GCLK5", - "CLK_TERM_R_GCLK6", - "CLK_TERM_R_GCLK7", - "CLK_TERM_R_GCLK8", - "CLK_TERM_R_GCLK9" - ] + "wires": { + "CLK_TERM_GCLK0": null, + "CLK_TERM_GCLK1": null, + "CLK_TERM_GCLK10": null, + "CLK_TERM_GCLK11": null, + "CLK_TERM_GCLK12": null, + "CLK_TERM_GCLK13": null, + "CLK_TERM_GCLK14": null, + "CLK_TERM_GCLK15": null, + "CLK_TERM_GCLK16": null, + "CLK_TERM_GCLK17": null, + "CLK_TERM_GCLK18": null, + "CLK_TERM_GCLK19": null, + "CLK_TERM_GCLK2": null, + "CLK_TERM_GCLK20": null, + "CLK_TERM_GCLK21": null, + "CLK_TERM_GCLK22": null, + "CLK_TERM_GCLK23": null, + "CLK_TERM_GCLK24": null, + "CLK_TERM_GCLK25": null, + "CLK_TERM_GCLK26": null, + "CLK_TERM_GCLK27": null, + "CLK_TERM_GCLK28": null, + "CLK_TERM_GCLK29": null, + "CLK_TERM_GCLK3": null, + "CLK_TERM_GCLK30": null, + "CLK_TERM_GCLK31": null, + "CLK_TERM_GCLK4": null, + "CLK_TERM_GCLK5": null, + "CLK_TERM_GCLK6": null, + "CLK_TERM_GCLK7": null, + "CLK_TERM_GCLK8": null, + "CLK_TERM_GCLK9": null, + "CLK_TERM_R_GCLK0": null, + "CLK_TERM_R_GCLK1": null, + "CLK_TERM_R_GCLK10": null, + "CLK_TERM_R_GCLK11": null, + "CLK_TERM_R_GCLK12": null, + "CLK_TERM_R_GCLK13": null, + "CLK_TERM_R_GCLK14": null, + "CLK_TERM_R_GCLK15": null, + "CLK_TERM_R_GCLK16": null, + "CLK_TERM_R_GCLK17": null, + "CLK_TERM_R_GCLK18": null, + "CLK_TERM_R_GCLK19": null, + "CLK_TERM_R_GCLK2": null, + "CLK_TERM_R_GCLK20": null, + "CLK_TERM_R_GCLK21": null, + "CLK_TERM_R_GCLK22": null, + "CLK_TERM_R_GCLK23": null, + "CLK_TERM_R_GCLK24": null, + "CLK_TERM_R_GCLK25": null, + "CLK_TERM_R_GCLK26": null, + "CLK_TERM_R_GCLK27": null, + "CLK_TERM_R_GCLK28": null, + "CLK_TERM_R_GCLK29": null, + "CLK_TERM_R_GCLK3": null, + "CLK_TERM_R_GCLK30": null, + "CLK_TERM_R_GCLK31": null, + "CLK_TERM_R_GCLK4": null, + "CLK_TERM_R_GCLK5": null, + "CLK_TERM_R_GCLK6": null, + "CLK_TERM_R_GCLK7": null, + "CLK_TERM_R_GCLK8": null, + "CLK_TERM_R_GCLK9": null + } } diff --git a/zynq7/tile_type_CMT_FIFO_L.json b/zynq7/tile_type_CMT_FIFO_L.json index 6aaea8a..ddc6e59 100644 --- a/zynq7/tile_type_CMT_FIFO_L.json +++ b/zynq7/tile_type_CMT_FIFO_L.json @@ -2,1948 +2,5006 @@ "pips": { "CMT_FIFO_L.CMT_FIFO_L_CLK0_6->CMT_OUT_FIFO_WRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_WRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_CLK0_6" }, "CMT_FIFO_L.CMT_FIFO_L_CLK0_7->CMT_OUT_FIFO_RDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_CLK0_7" }, "CMT_FIFO_L.CMT_FIFO_L_CLK1_6->CMT_IN_FIFO_WRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_WRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_CLK1_6" }, "CMT_FIFO_L.CMT_FIFO_L_CLK1_7->CMT_IN_FIFO_RDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_RDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_CLK1_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_0->CMT_OUT_FIFO_D04": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D04", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_1->CMT_OUT_FIFO_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_10->CMT_OUT_FIFO_D84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_11->CMT_OUT_FIFO_D94": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D94", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_2->CMT_OUT_FIFO_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_3->CMT_OUT_FIFO_D34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_4->CMT_OUT_FIFO_D44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_5->CMT_OUT_FIFO_D54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_8->CMT_OUT_FIFO_D64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_9->CMT_OUT_FIFO_D74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_0->CMT_OUT_FIFO_D01": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D01", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_1->CMT_OUT_FIFO_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_10->CMT_OUT_FIFO_D81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_11->CMT_OUT_FIFO_D91": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D91", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_2->CMT_OUT_FIFO_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_3->CMT_OUT_FIFO_D31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_4->CMT_OUT_FIFO_D41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_5->CMT_OUT_FIFO_D51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_8->CMT_OUT_FIFO_D61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_9->CMT_OUT_FIFO_D71": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D71", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_0->CMT_IN_FIFO_D00": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D00", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_1->CMT_IN_FIFO_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_10->CMT_IN_FIFO_D80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_11->CMT_IN_FIFO_D90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_2->CMT_IN_FIFO_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_3->CMT_IN_FIFO_D30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_4->CMT_IN_FIFO_D40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_5->CMT_IN_FIFO_D50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_6->CMT_IN_FIFO_D54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_7->CMT_IN_FIFO_D64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_8->CMT_IN_FIFO_D60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_9->CMT_IN_FIFO_D70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D70", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_0->CMT_OUT_FIFO_D00": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D00", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_1->CMT_OUT_FIFO_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_10->CMT_OUT_FIFO_D80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_11->CMT_OUT_FIFO_D90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_2->CMT_OUT_FIFO_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_3->CMT_OUT_FIFO_D30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_4->CMT_OUT_FIFO_D40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_5->CMT_OUT_FIFO_D50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_8->CMT_OUT_FIFO_D60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_9->CMT_OUT_FIFO_D70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D70", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_0->CMT_IN_FIFO_D02": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D02", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_1->CMT_IN_FIFO_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_10->CMT_IN_FIFO_D82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_11->CMT_IN_FIFO_D92": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D92", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_2->CMT_IN_FIFO_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_3->CMT_IN_FIFO_D32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_4->CMT_IN_FIFO_D42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_5->CMT_IN_FIFO_D52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_6->CMT_IN_FIFO_D56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_7->CMT_IN_FIFO_D66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_8->CMT_IN_FIFO_D62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_9->CMT_IN_FIFO_D72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_0->CMT_OUT_FIFO_D03": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D03", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_1->CMT_OUT_FIFO_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_10->CMT_OUT_FIFO_D83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_11->CMT_OUT_FIFO_D93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_2->CMT_OUT_FIFO_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_3->CMT_OUT_FIFO_D33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_4->CMT_OUT_FIFO_D43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_5->CMT_OUT_FIFO_D53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_8->CMT_OUT_FIFO_D63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_9->CMT_OUT_FIFO_D73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_0->CMT_OUT_FIFO_D02": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D02", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_1->CMT_OUT_FIFO_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_10->CMT_OUT_FIFO_D82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_11->CMT_OUT_FIFO_D92": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D92", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_2->CMT_OUT_FIFO_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_3->CMT_OUT_FIFO_D32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_4->CMT_OUT_FIFO_D42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_5->CMT_OUT_FIFO_D52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_8->CMT_OUT_FIFO_D62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_9->CMT_OUT_FIFO_D72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_0->CMT_IN_FIFO_D01": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D01", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_1->CMT_IN_FIFO_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_10->CMT_IN_FIFO_D81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_11->CMT_IN_FIFO_D91": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D91", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_2->CMT_IN_FIFO_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_3->CMT_IN_FIFO_D31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_4->CMT_IN_FIFO_D41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_5->CMT_IN_FIFO_D51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_6->CMT_IN_FIFO_D55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_7->CMT_IN_FIFO_D65": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D65", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_8->CMT_IN_FIFO_D61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_9->CMT_IN_FIFO_D71": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D71", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_0->CMT_IN_FIFO_D03": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D03", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_1->CMT_IN_FIFO_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_10->CMT_IN_FIFO_D83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_11->CMT_IN_FIFO_D93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_2->CMT_IN_FIFO_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_3->CMT_IN_FIFO_D33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_4->CMT_IN_FIFO_D43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_5->CMT_IN_FIFO_D53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_6->CMT_IN_FIFO_D57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_7->CMT_IN_FIFO_D67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_8->CMT_IN_FIFO_D63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_9->CMT_IN_FIFO_D73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_0->CMT_OUT_FIFO_D05": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D05", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_1->CMT_OUT_FIFO_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_10->CMT_OUT_FIFO_D85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_11->CMT_OUT_FIFO_D95": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D95", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_2->CMT_OUT_FIFO_D25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_3->CMT_OUT_FIFO_D35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_4->CMT_OUT_FIFO_D45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_5->CMT_OUT_FIFO_D55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_6->CMT_OUT_FIFO_RESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_7->CMT_IN_FIFO_RESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_RESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_8->CMT_OUT_FIFO_D65": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D65", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_9->CMT_OUT_FIFO_D75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_0->CMT_OUT_FIFO_D07": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D07", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_1->CMT_OUT_FIFO_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_10->CMT_OUT_FIFO_D87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_11->CMT_OUT_FIFO_D97": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D97", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_2->CMT_OUT_FIFO_D27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_3->CMT_OUT_FIFO_D37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_4->CMT_OUT_FIFO_D47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_5->CMT_OUT_FIFO_D57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_6->CMT_OUT_FIFO_WREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_WREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_7->CMT_OUT_FIFO_RDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_8->CMT_OUT_FIFO_D67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_9->CMT_OUT_FIFO_D77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_0->CMT_OUT_FIFO_D06": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D06", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_1->CMT_OUT_FIFO_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_10->CMT_OUT_FIFO_D86": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D86", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_11->CMT_OUT_FIFO_D96": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D96", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_2->CMT_OUT_FIFO_D26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_3->CMT_OUT_FIFO_D36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_4->CMT_OUT_FIFO_D46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_5->CMT_OUT_FIFO_D56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_6->CMT_IN_FIFO_WREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_WREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_7->CMT_IN_FIFO_RDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_RDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_8->CMT_OUT_FIFO_D66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_9->CMT_OUT_FIFO_D76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_9" }, "CMT_FIFO_L.CMT_FIFO_L_PHASER_RDCLK->CMT_OUT_FIFO_RDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_PHASER_RDCLK" }, "CMT_FIFO_L.CMT_FIFO_L_PHASER_RDENABLE->CMT_OUT_FIFO_RDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_PHASER_RDENABLE" }, "CMT_FIFO_L.CMT_FIFO_L_PHASER_WRCLK->CMT_IN_FIFO_WRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_WRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_PHASER_WRCLK" }, "CMT_FIFO_L.CMT_FIFO_L_PHASER_WRENABLE->CMT_IN_FIFO_WREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_WREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_PHASER_WRENABLE" }, "CMT_FIFO_L.CMT_IN_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_ALMOSTEMPTY" }, "CMT_FIFO_L.CMT_IN_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_ALMOSTFULL" }, "CMT_FIFO_L.CMT_IN_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_EMPTY" }, "CMT_FIFO_L.CMT_IN_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_FULL" }, "CMT_FIFO_L.CMT_IN_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q00" }, "CMT_FIFO_L.CMT_IN_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q01" }, "CMT_FIFO_L.CMT_IN_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q02" }, "CMT_FIFO_L.CMT_IN_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q03" }, "CMT_FIFO_L.CMT_IN_FIFO_Q04->CMT_FIFO_L_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q04" }, "CMT_FIFO_L.CMT_IN_FIFO_Q05->CMT_FIFO_L_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q05" }, "CMT_FIFO_L.CMT_IN_FIFO_Q06->CMT_FIFO_L_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q06" }, "CMT_FIFO_L.CMT_IN_FIFO_Q07->CMT_FIFO_L_LOGIC_OUTS13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q07" }, "CMT_FIFO_L.CMT_IN_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q10" }, "CMT_FIFO_L.CMT_IN_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q11" }, "CMT_FIFO_L.CMT_IN_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q12" }, "CMT_FIFO_L.CMT_IN_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q13" }, "CMT_FIFO_L.CMT_IN_FIFO_Q14->CMT_FIFO_L_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q14" }, "CMT_FIFO_L.CMT_IN_FIFO_Q15->CMT_FIFO_L_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q15" }, "CMT_FIFO_L.CMT_IN_FIFO_Q16->CMT_FIFO_L_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q16" }, "CMT_FIFO_L.CMT_IN_FIFO_Q17->CMT_FIFO_L_LOGIC_OUTS13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q17" }, "CMT_FIFO_L.CMT_IN_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q20" }, "CMT_FIFO_L.CMT_IN_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q21" }, "CMT_FIFO_L.CMT_IN_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q22" }, "CMT_FIFO_L.CMT_IN_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q23" }, "CMT_FIFO_L.CMT_IN_FIFO_Q24->CMT_FIFO_L_LOGIC_OUTS12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q24" }, "CMT_FIFO_L.CMT_IN_FIFO_Q25->CMT_FIFO_L_LOGIC_OUTS8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q25" }, "CMT_FIFO_L.CMT_IN_FIFO_Q26->CMT_FIFO_L_LOGIC_OUTS9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q26" }, "CMT_FIFO_L.CMT_IN_FIFO_Q27->CMT_FIFO_L_LOGIC_OUTS13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q27" }, "CMT_FIFO_L.CMT_IN_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q30" }, "CMT_FIFO_L.CMT_IN_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q31" }, "CMT_FIFO_L.CMT_IN_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q32" }, "CMT_FIFO_L.CMT_IN_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q33" }, "CMT_FIFO_L.CMT_IN_FIFO_Q34->CMT_FIFO_L_LOGIC_OUTS12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q34" }, "CMT_FIFO_L.CMT_IN_FIFO_Q35->CMT_FIFO_L_LOGIC_OUTS8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q35" }, "CMT_FIFO_L.CMT_IN_FIFO_Q36->CMT_FIFO_L_LOGIC_OUTS9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q36" }, "CMT_FIFO_L.CMT_IN_FIFO_Q37->CMT_FIFO_L_LOGIC_OUTS13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q37" }, "CMT_FIFO_L.CMT_IN_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q40" }, "CMT_FIFO_L.CMT_IN_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q41" }, "CMT_FIFO_L.CMT_IN_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q42" }, "CMT_FIFO_L.CMT_IN_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q43" }, "CMT_FIFO_L.CMT_IN_FIFO_Q44->CMT_FIFO_L_LOGIC_OUTS12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q44" }, "CMT_FIFO_L.CMT_IN_FIFO_Q45->CMT_FIFO_L_LOGIC_OUTS8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q45" }, "CMT_FIFO_L.CMT_IN_FIFO_Q46->CMT_FIFO_L_LOGIC_OUTS9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q46" }, "CMT_FIFO_L.CMT_IN_FIFO_Q47->CMT_FIFO_L_LOGIC_OUTS13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q47" }, "CMT_FIFO_L.CMT_IN_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q50" }, "CMT_FIFO_L.CMT_IN_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q51" }, "CMT_FIFO_L.CMT_IN_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q52" }, "CMT_FIFO_L.CMT_IN_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q53" }, "CMT_FIFO_L.CMT_IN_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q54" }, "CMT_FIFO_L.CMT_IN_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q55" }, "CMT_FIFO_L.CMT_IN_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q56" }, "CMT_FIFO_L.CMT_IN_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q57" }, "CMT_FIFO_L.CMT_IN_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q60" }, "CMT_FIFO_L.CMT_IN_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q61" }, "CMT_FIFO_L.CMT_IN_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q62" }, "CMT_FIFO_L.CMT_IN_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q63" }, "CMT_FIFO_L.CMT_IN_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q64" }, "CMT_FIFO_L.CMT_IN_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q65" }, "CMT_FIFO_L.CMT_IN_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q66" }, "CMT_FIFO_L.CMT_IN_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q67" }, "CMT_FIFO_L.CMT_IN_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q70" }, "CMT_FIFO_L.CMT_IN_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q71" }, "CMT_FIFO_L.CMT_IN_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q72" }, "CMT_FIFO_L.CMT_IN_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q73" }, "CMT_FIFO_L.CMT_IN_FIFO_Q74->CMT_FIFO_L_LOGIC_OUTS12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q74" }, "CMT_FIFO_L.CMT_IN_FIFO_Q75->CMT_FIFO_L_LOGIC_OUTS8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q75" }, "CMT_FIFO_L.CMT_IN_FIFO_Q76->CMT_FIFO_L_LOGIC_OUTS9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q76" }, "CMT_FIFO_L.CMT_IN_FIFO_Q77->CMT_FIFO_L_LOGIC_OUTS13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q77" }, "CMT_FIFO_L.CMT_IN_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q80" }, "CMT_FIFO_L.CMT_IN_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q81" }, "CMT_FIFO_L.CMT_IN_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q82" }, "CMT_FIFO_L.CMT_IN_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q83" }, "CMT_FIFO_L.CMT_IN_FIFO_Q84->CMT_FIFO_L_LOGIC_OUTS12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q84" }, "CMT_FIFO_L.CMT_IN_FIFO_Q85->CMT_FIFO_L_LOGIC_OUTS8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q85" }, "CMT_FIFO_L.CMT_IN_FIFO_Q86->CMT_FIFO_L_LOGIC_OUTS9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q86" }, "CMT_FIFO_L.CMT_IN_FIFO_Q87->CMT_FIFO_L_LOGIC_OUTS13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q87" }, "CMT_FIFO_L.CMT_IN_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q90" }, "CMT_FIFO_L.CMT_IN_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS4_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q91" }, "CMT_FIFO_L.CMT_IN_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q92" }, "CMT_FIFO_L.CMT_IN_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q93" }, "CMT_FIFO_L.CMT_IN_FIFO_Q94->CMT_FIFO_L_LOGIC_OUTS12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q94" }, "CMT_FIFO_L.CMT_IN_FIFO_Q95->CMT_FIFO_L_LOGIC_OUTS8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q95" }, "CMT_FIFO_L.CMT_IN_FIFO_Q96->CMT_FIFO_L_LOGIC_OUTS9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q96" }, "CMT_FIFO_L.CMT_IN_FIFO_Q97->CMT_FIFO_L_LOGIC_OUTS13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q97" }, "CMT_FIFO_L.CMT_OUT_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_ALMOSTEMPTY" }, "CMT_FIFO_L.CMT_OUT_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_ALMOSTFULL" }, "CMT_FIFO_L.CMT_OUT_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_EMPTY" }, "CMT_FIFO_L.CMT_OUT_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_FULL" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q00" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q01" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q02" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q03" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q10" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q11" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q12" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q13" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q20" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q21" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q22" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q23" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q30" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q31" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q32" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q33" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q40" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q41" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q42" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q43" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q50" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q51" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q52" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q53" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q54" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q55" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q56" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q57" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q60" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q61" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q62" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q63" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q64" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q65" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q66" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q67" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q70" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q71" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q72" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q73" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q80" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q81" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q82" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q83" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q90" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q91" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q92" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q93" } }, @@ -1952,155 +5010,1496 @@ "name": "X0Y0", "prefix": "OUT_FIFO", "site_pins": { - "ALMOSTEMPTY": "CMT_OUT_FIFO_ALMOSTEMPTY", - "ALMOSTFULL": "CMT_OUT_FIFO_ALMOSTFULL", - "D00": "CMT_OUT_FIFO_D00", - "D01": "CMT_OUT_FIFO_D01", - "D02": "CMT_OUT_FIFO_D02", - "D03": "CMT_OUT_FIFO_D03", - "D04": "CMT_OUT_FIFO_D04", - "D05": "CMT_OUT_FIFO_D05", - "D06": "CMT_OUT_FIFO_D06", - "D07": "CMT_OUT_FIFO_D07", - "D10": "CMT_OUT_FIFO_D10", - "D11": "CMT_OUT_FIFO_D11", - "D12": "CMT_OUT_FIFO_D12", - "D13": "CMT_OUT_FIFO_D13", - "D14": "CMT_OUT_FIFO_D14", - "D15": "CMT_OUT_FIFO_D15", - "D16": "CMT_OUT_FIFO_D16", - "D17": "CMT_OUT_FIFO_D17", - "D20": "CMT_OUT_FIFO_D20", - "D21": "CMT_OUT_FIFO_D21", - "D22": "CMT_OUT_FIFO_D22", - "D23": "CMT_OUT_FIFO_D23", - "D24": "CMT_OUT_FIFO_D24", - "D25": "CMT_OUT_FIFO_D25", - "D26": "CMT_OUT_FIFO_D26", - "D27": "CMT_OUT_FIFO_D27", - "D30": "CMT_OUT_FIFO_D30", - "D31": "CMT_OUT_FIFO_D31", - "D32": "CMT_OUT_FIFO_D32", - "D33": "CMT_OUT_FIFO_D33", - "D34": "CMT_OUT_FIFO_D34", - "D35": "CMT_OUT_FIFO_D35", - "D36": "CMT_OUT_FIFO_D36", - "D37": "CMT_OUT_FIFO_D37", - "D40": "CMT_OUT_FIFO_D40", - "D41": "CMT_OUT_FIFO_D41", - "D42": "CMT_OUT_FIFO_D42", - "D43": "CMT_OUT_FIFO_D43", - "D44": "CMT_OUT_FIFO_D44", - "D45": "CMT_OUT_FIFO_D45", - "D46": "CMT_OUT_FIFO_D46", - "D47": "CMT_OUT_FIFO_D47", - "D50": "CMT_OUT_FIFO_D50", - "D51": "CMT_OUT_FIFO_D51", - "D52": "CMT_OUT_FIFO_D52", - "D53": "CMT_OUT_FIFO_D53", - "D54": "CMT_OUT_FIFO_D54", - "D55": "CMT_OUT_FIFO_D55", - "D56": "CMT_OUT_FIFO_D56", - "D57": "CMT_OUT_FIFO_D57", - "D60": "CMT_OUT_FIFO_D60", - "D61": "CMT_OUT_FIFO_D61", - "D62": "CMT_OUT_FIFO_D62", - "D63": "CMT_OUT_FIFO_D63", - "D64": "CMT_OUT_FIFO_D64", - "D65": "CMT_OUT_FIFO_D65", - "D66": "CMT_OUT_FIFO_D66", - "D67": "CMT_OUT_FIFO_D67", - "D70": "CMT_OUT_FIFO_D70", - "D71": "CMT_OUT_FIFO_D71", - "D72": "CMT_OUT_FIFO_D72", - "D73": "CMT_OUT_FIFO_D73", - "D74": "CMT_OUT_FIFO_D74", - "D75": "CMT_OUT_FIFO_D75", - "D76": "CMT_OUT_FIFO_D76", - "D77": "CMT_OUT_FIFO_D77", - "D80": "CMT_OUT_FIFO_D80", - "D81": "CMT_OUT_FIFO_D81", - "D82": "CMT_OUT_FIFO_D82", - "D83": "CMT_OUT_FIFO_D83", - "D84": "CMT_OUT_FIFO_D84", - "D85": "CMT_OUT_FIFO_D85", - "D86": "CMT_OUT_FIFO_D86", - "D87": "CMT_OUT_FIFO_D87", - "D90": "CMT_OUT_FIFO_D90", - "D91": "CMT_OUT_FIFO_D91", - "D92": "CMT_OUT_FIFO_D92", - "D93": "CMT_OUT_FIFO_D93", - "D94": "CMT_OUT_FIFO_D94", - "D95": "CMT_OUT_FIFO_D95", - "D96": "CMT_OUT_FIFO_D96", - "D97": "CMT_OUT_FIFO_D97", - "EMPTY": "CMT_OUT_FIFO_EMPTY", - "FULL": "CMT_OUT_FIFO_FULL", - "Q00": "CMT_OUT_FIFO_Q00", - "Q01": "CMT_OUT_FIFO_Q01", - "Q02": "CMT_OUT_FIFO_Q02", - "Q03": "CMT_OUT_FIFO_Q03", - "Q10": "CMT_OUT_FIFO_Q10", - "Q11": "CMT_OUT_FIFO_Q11", - "Q12": "CMT_OUT_FIFO_Q12", - "Q13": "CMT_OUT_FIFO_Q13", - "Q20": "CMT_OUT_FIFO_Q20", - "Q21": "CMT_OUT_FIFO_Q21", - "Q22": "CMT_OUT_FIFO_Q22", - "Q23": "CMT_OUT_FIFO_Q23", - "Q30": "CMT_OUT_FIFO_Q30", - "Q31": "CMT_OUT_FIFO_Q31", - "Q32": "CMT_OUT_FIFO_Q32", - "Q33": "CMT_OUT_FIFO_Q33", - "Q40": "CMT_OUT_FIFO_Q40", - "Q41": "CMT_OUT_FIFO_Q41", - "Q42": "CMT_OUT_FIFO_Q42", - "Q43": "CMT_OUT_FIFO_Q43", - "Q50": "CMT_OUT_FIFO_Q50", - "Q51": "CMT_OUT_FIFO_Q51", - "Q52": "CMT_OUT_FIFO_Q52", - "Q53": "CMT_OUT_FIFO_Q53", - "Q54": "CMT_OUT_FIFO_Q54", - "Q55": "CMT_OUT_FIFO_Q55", - "Q56": "CMT_OUT_FIFO_Q56", - "Q57": "CMT_OUT_FIFO_Q57", - "Q60": "CMT_OUT_FIFO_Q60", - "Q61": "CMT_OUT_FIFO_Q61", - "Q62": "CMT_OUT_FIFO_Q62", - "Q63": "CMT_OUT_FIFO_Q63", - "Q64": "CMT_OUT_FIFO_Q64", - "Q65": "CMT_OUT_FIFO_Q65", - "Q66": "CMT_OUT_FIFO_Q66", - "Q67": "CMT_OUT_FIFO_Q67", - "Q70": "CMT_OUT_FIFO_Q70", - "Q71": "CMT_OUT_FIFO_Q71", - "Q72": "CMT_OUT_FIFO_Q72", - "Q73": "CMT_OUT_FIFO_Q73", - "Q80": "CMT_OUT_FIFO_Q80", - "Q81": "CMT_OUT_FIFO_Q81", - "Q82": "CMT_OUT_FIFO_Q82", - "Q83": "CMT_OUT_FIFO_Q83", - "Q90": "CMT_OUT_FIFO_Q90", - "Q91": "CMT_OUT_FIFO_Q91", - "Q92": "CMT_OUT_FIFO_Q92", - "Q93": "CMT_OUT_FIFO_Q93", - "RDCLK": "CMT_OUT_FIFO_RDCLK", - "RDEN": "CMT_OUT_FIFO_RDEN", - "RESET": "CMT_OUT_FIFO_RESET", - "SCANENB": "CMT_OUT_FIFO_SCANENB", - "SCANIN0": "CMT_OUT_FIFO_SCANIN0", - "SCANIN1": "CMT_OUT_FIFO_SCANIN1", - "SCANIN2": "CMT_OUT_FIFO_SCANIN2", - "SCANIN3": "CMT_OUT_FIFO_SCANIN3", - "SCANOUT0": "CMT_OUT_FIFO_SCANOUT0", - "SCANOUT1": "CMT_OUT_FIFO_SCANOUT1", - "SCANOUT2": "CMT_OUT_FIFO_SCANOUT2", - "SCANOUT3": "CMT_OUT_FIFO_SCANOUT3", - "TESTMODEB": "CMT_OUT_FIFO_TESTMODEB", - "TESTREADDISB": "CMT_OUT_FIFO_TESTREADDISB", - "TESTWRITEDISB": "CMT_OUT_FIFO_TESTWRITEDISB", - "WRCLK": "CMT_OUT_FIFO_WRCLK", - "WREN": "CMT_OUT_FIFO_WREN" + "ALMOSTEMPTY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_OUT_FIFO_ALMOSTEMPTY" + }, + "ALMOSTFULL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_OUT_FIFO_ALMOSTFULL" + }, + "D00": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D00" + }, + "D01": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": 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"CMT_FIFO_EE4A2_10", - "CMT_FIFO_EE4A2_11", - "CMT_FIFO_EE4A2_2", - "CMT_FIFO_EE4A2_3", - "CMT_FIFO_EE4A2_4", - "CMT_FIFO_EE4A2_5", - "CMT_FIFO_EE4A2_6", - "CMT_FIFO_EE4A2_7", - "CMT_FIFO_EE4A2_8", - "CMT_FIFO_EE4A2_9", - "CMT_FIFO_EE4A3_0", - "CMT_FIFO_EE4A3_1", - "CMT_FIFO_EE4A3_10", - "CMT_FIFO_EE4A3_11", - "CMT_FIFO_EE4A3_2", - "CMT_FIFO_EE4A3_3", - "CMT_FIFO_EE4A3_4", - "CMT_FIFO_EE4A3_5", - "CMT_FIFO_EE4A3_6", - "CMT_FIFO_EE4A3_7", - "CMT_FIFO_EE4A3_8", - "CMT_FIFO_EE4A3_9", - "CMT_FIFO_EE4B0_0", - "CMT_FIFO_EE4B0_1", - "CMT_FIFO_EE4B0_10", - "CMT_FIFO_EE4B0_11", - "CMT_FIFO_EE4B0_2", - "CMT_FIFO_EE4B0_3", - "CMT_FIFO_EE4B0_4", - "CMT_FIFO_EE4B0_5", - "CMT_FIFO_EE4B0_6", - "CMT_FIFO_EE4B0_7", - "CMT_FIFO_EE4B0_8", - "CMT_FIFO_EE4B0_9", - "CMT_FIFO_EE4B1_0", - "CMT_FIFO_EE4B1_1", - "CMT_FIFO_EE4B1_10", - "CMT_FIFO_EE4B1_11", - "CMT_FIFO_EE4B1_2", - "CMT_FIFO_EE4B1_3", - "CMT_FIFO_EE4B1_4", - "CMT_FIFO_EE4B1_5", - "CMT_FIFO_EE4B1_6", - "CMT_FIFO_EE4B1_7", - "CMT_FIFO_EE4B1_8", - "CMT_FIFO_EE4B1_9", - "CMT_FIFO_EE4B2_0", - "CMT_FIFO_EE4B2_1", - "CMT_FIFO_EE4B2_10", - "CMT_FIFO_EE4B2_11", - "CMT_FIFO_EE4B2_2", - "CMT_FIFO_EE4B2_3", - "CMT_FIFO_EE4B2_4", - "CMT_FIFO_EE4B2_5", - "CMT_FIFO_EE4B2_6", - "CMT_FIFO_EE4B2_7", - "CMT_FIFO_EE4B2_8", - "CMT_FIFO_EE4B2_9", - "CMT_FIFO_EE4B3_0", - "CMT_FIFO_EE4B3_1", - "CMT_FIFO_EE4B3_10", - "CMT_FIFO_EE4B3_11", - "CMT_FIFO_EE4B3_2", - "CMT_FIFO_EE4B3_3", - "CMT_FIFO_EE4B3_4", - "CMT_FIFO_EE4B3_5", - "CMT_FIFO_EE4B3_6", - "CMT_FIFO_EE4B3_7", - "CMT_FIFO_EE4B3_8", - "CMT_FIFO_EE4B3_9", - "CMT_FIFO_EE4BEG0_0", - "CMT_FIFO_EE4BEG0_1", - "CMT_FIFO_EE4BEG0_10", - "CMT_FIFO_EE4BEG0_11", - "CMT_FIFO_EE4BEG0_2", - "CMT_FIFO_EE4BEG0_3", - "CMT_FIFO_EE4BEG0_4", - "CMT_FIFO_EE4BEG0_5", - "CMT_FIFO_EE4BEG0_6", - "CMT_FIFO_EE4BEG0_7", - "CMT_FIFO_EE4BEG0_8", - "CMT_FIFO_EE4BEG0_9", - "CMT_FIFO_EE4BEG1_0", - "CMT_FIFO_EE4BEG1_1", - "CMT_FIFO_EE4BEG1_10", - "CMT_FIFO_EE4BEG1_11", - "CMT_FIFO_EE4BEG1_2", - "CMT_FIFO_EE4BEG1_3", - "CMT_FIFO_EE4BEG1_4", - "CMT_FIFO_EE4BEG1_5", - "CMT_FIFO_EE4BEG1_6", - "CMT_FIFO_EE4BEG1_7", - "CMT_FIFO_EE4BEG1_8", - "CMT_FIFO_EE4BEG1_9", - "CMT_FIFO_EE4BEG2_0", - "CMT_FIFO_EE4BEG2_1", - "CMT_FIFO_EE4BEG2_10", - "CMT_FIFO_EE4BEG2_11", - "CMT_FIFO_EE4BEG2_2", - "CMT_FIFO_EE4BEG2_3", - "CMT_FIFO_EE4BEG2_4", - "CMT_FIFO_EE4BEG2_5", - "CMT_FIFO_EE4BEG2_6", - "CMT_FIFO_EE4BEG2_7", - "CMT_FIFO_EE4BEG2_8", - "CMT_FIFO_EE4BEG2_9", - "CMT_FIFO_EE4BEG3_0", - "CMT_FIFO_EE4BEG3_1", - "CMT_FIFO_EE4BEG3_10", - "CMT_FIFO_EE4BEG3_11", - "CMT_FIFO_EE4BEG3_2", - "CMT_FIFO_EE4BEG3_3", - "CMT_FIFO_EE4BEG3_4", - "CMT_FIFO_EE4BEG3_5", - "CMT_FIFO_EE4BEG3_6", - "CMT_FIFO_EE4BEG3_7", - "CMT_FIFO_EE4BEG3_8", - "CMT_FIFO_EE4BEG3_9", - "CMT_FIFO_EE4C0_0", - "CMT_FIFO_EE4C0_1", - "CMT_FIFO_EE4C0_10", - "CMT_FIFO_EE4C0_11", - "CMT_FIFO_EE4C0_2", - "CMT_FIFO_EE4C0_3", - "CMT_FIFO_EE4C0_4", - "CMT_FIFO_EE4C0_5", - "CMT_FIFO_EE4C0_6", - "CMT_FIFO_EE4C0_7", - "CMT_FIFO_EE4C0_8", - "CMT_FIFO_EE4C0_9", - "CMT_FIFO_EE4C1_0", - "CMT_FIFO_EE4C1_1", - "CMT_FIFO_EE4C1_10", - "CMT_FIFO_EE4C1_11", - "CMT_FIFO_EE4C1_2", - "CMT_FIFO_EE4C1_3", - "CMT_FIFO_EE4C1_4", - "CMT_FIFO_EE4C1_5", - "CMT_FIFO_EE4C1_6", - "CMT_FIFO_EE4C1_7", - "CMT_FIFO_EE4C1_8", - "CMT_FIFO_EE4C1_9", - "CMT_FIFO_EE4C2_0", - "CMT_FIFO_EE4C2_1", - "CMT_FIFO_EE4C2_10", - "CMT_FIFO_EE4C2_11", - "CMT_FIFO_EE4C2_2", - "CMT_FIFO_EE4C2_3", - "CMT_FIFO_EE4C2_4", - "CMT_FIFO_EE4C2_5", - "CMT_FIFO_EE4C2_6", - "CMT_FIFO_EE4C2_7", - "CMT_FIFO_EE4C2_8", - "CMT_FIFO_EE4C2_9", - "CMT_FIFO_EE4C3_0", - "CMT_FIFO_EE4C3_1", - "CMT_FIFO_EE4C3_10", - "CMT_FIFO_EE4C3_11", - "CMT_FIFO_EE4C3_2", - "CMT_FIFO_EE4C3_3", - "CMT_FIFO_EE4C3_4", - "CMT_FIFO_EE4C3_5", - "CMT_FIFO_EE4C3_6", - "CMT_FIFO_EE4C3_7", - "CMT_FIFO_EE4C3_8", - "CMT_FIFO_EE4C3_9", - "CMT_FIFO_EL1BEG0_0", - "CMT_FIFO_EL1BEG0_1", - "CMT_FIFO_EL1BEG0_10", - "CMT_FIFO_EL1BEG0_11", - "CMT_FIFO_EL1BEG0_2", - "CMT_FIFO_EL1BEG0_3", - "CMT_FIFO_EL1BEG0_4", - "CMT_FIFO_EL1BEG0_5", - "CMT_FIFO_EL1BEG0_6", - "CMT_FIFO_EL1BEG0_7", - "CMT_FIFO_EL1BEG0_8", - "CMT_FIFO_EL1BEG0_9", - "CMT_FIFO_EL1BEG1_0", - "CMT_FIFO_EL1BEG1_1", - "CMT_FIFO_EL1BEG1_10", - "CMT_FIFO_EL1BEG1_11", - "CMT_FIFO_EL1BEG1_2", - "CMT_FIFO_EL1BEG1_3", - "CMT_FIFO_EL1BEG1_4", - "CMT_FIFO_EL1BEG1_5", - "CMT_FIFO_EL1BEG1_6", - "CMT_FIFO_EL1BEG1_7", - "CMT_FIFO_EL1BEG1_8", - "CMT_FIFO_EL1BEG1_9", - "CMT_FIFO_EL1BEG2_0", - "CMT_FIFO_EL1BEG2_1", - "CMT_FIFO_EL1BEG2_10", - "CMT_FIFO_EL1BEG2_11", - "CMT_FIFO_EL1BEG2_2", - "CMT_FIFO_EL1BEG2_3", - "CMT_FIFO_EL1BEG2_4", - "CMT_FIFO_EL1BEG2_5", - "CMT_FIFO_EL1BEG2_6", - "CMT_FIFO_EL1BEG2_7", - "CMT_FIFO_EL1BEG2_8", - "CMT_FIFO_EL1BEG2_9", - "CMT_FIFO_EL1BEG3_0", - "CMT_FIFO_EL1BEG3_1", - "CMT_FIFO_EL1BEG3_10", - "CMT_FIFO_EL1BEG3_11", - "CMT_FIFO_EL1BEG3_2", - "CMT_FIFO_EL1BEG3_3", - "CMT_FIFO_EL1BEG3_4", - "CMT_FIFO_EL1BEG3_5", - "CMT_FIFO_EL1BEG3_6", - "CMT_FIFO_EL1BEG3_7", - "CMT_FIFO_EL1BEG3_8", - "CMT_FIFO_EL1BEG3_9", - "CMT_FIFO_ER1BEG0_0", - "CMT_FIFO_ER1BEG0_1", - "CMT_FIFO_ER1BEG0_10", - "CMT_FIFO_ER1BEG0_11", - "CMT_FIFO_ER1BEG0_2", - "CMT_FIFO_ER1BEG0_3", - "CMT_FIFO_ER1BEG0_4", - "CMT_FIFO_ER1BEG0_5", - "CMT_FIFO_ER1BEG0_6", - "CMT_FIFO_ER1BEG0_7", - "CMT_FIFO_ER1BEG0_8", - "CMT_FIFO_ER1BEG0_9", - "CMT_FIFO_ER1BEG1_0", - "CMT_FIFO_ER1BEG1_1", - "CMT_FIFO_ER1BEG1_10", - "CMT_FIFO_ER1BEG1_11", - "CMT_FIFO_ER1BEG1_2", - "CMT_FIFO_ER1BEG1_3", - "CMT_FIFO_ER1BEG1_4", - "CMT_FIFO_ER1BEG1_5", - "CMT_FIFO_ER1BEG1_6", - "CMT_FIFO_ER1BEG1_7", - "CMT_FIFO_ER1BEG1_8", - "CMT_FIFO_ER1BEG1_9", - "CMT_FIFO_ER1BEG2_0", - "CMT_FIFO_ER1BEG2_1", - "CMT_FIFO_ER1BEG2_10", - "CMT_FIFO_ER1BEG2_11", - "CMT_FIFO_ER1BEG2_2", - "CMT_FIFO_ER1BEG2_3", - "CMT_FIFO_ER1BEG2_4", - "CMT_FIFO_ER1BEG2_5", - "CMT_FIFO_ER1BEG2_6", - "CMT_FIFO_ER1BEG2_7", - "CMT_FIFO_ER1BEG2_8", - "CMT_FIFO_ER1BEG2_9", - "CMT_FIFO_ER1BEG3_0", - "CMT_FIFO_ER1BEG3_1", - "CMT_FIFO_ER1BEG3_10", - "CMT_FIFO_ER1BEG3_11", - "CMT_FIFO_ER1BEG3_2", - "CMT_FIFO_ER1BEG3_3", - "CMT_FIFO_ER1BEG3_4", - "CMT_FIFO_ER1BEG3_5", - "CMT_FIFO_ER1BEG3_6", - "CMT_FIFO_ER1BEG3_7", - "CMT_FIFO_ER1BEG3_8", - "CMT_FIFO_ER1BEG3_9", - "CMT_FIFO_LH10_0", - "CMT_FIFO_LH10_1", - "CMT_FIFO_LH10_10", - "CMT_FIFO_LH10_11", - "CMT_FIFO_LH10_2", - "CMT_FIFO_LH10_3", - "CMT_FIFO_LH10_4", - "CMT_FIFO_LH10_5", - "CMT_FIFO_LH10_6", - "CMT_FIFO_LH10_7", - "CMT_FIFO_LH10_8", - "CMT_FIFO_LH10_9", - "CMT_FIFO_LH11_0", - "CMT_FIFO_LH11_1", - "CMT_FIFO_LH11_10", - "CMT_FIFO_LH11_11", - "CMT_FIFO_LH11_2", - "CMT_FIFO_LH11_3", - "CMT_FIFO_LH11_4", - "CMT_FIFO_LH11_5", - "CMT_FIFO_LH11_6", - "CMT_FIFO_LH11_7", - "CMT_FIFO_LH11_8", - "CMT_FIFO_LH11_9", - "CMT_FIFO_LH12_0", - "CMT_FIFO_LH12_1", - "CMT_FIFO_LH12_10", - "CMT_FIFO_LH12_11", - "CMT_FIFO_LH12_2", - "CMT_FIFO_LH12_3", - "CMT_FIFO_LH12_4", - "CMT_FIFO_LH12_5", - "CMT_FIFO_LH12_6", - "CMT_FIFO_LH12_7", - "CMT_FIFO_LH12_8", - "CMT_FIFO_LH12_9", - "CMT_FIFO_LH1_0", - "CMT_FIFO_LH1_1", - "CMT_FIFO_LH1_10", - "CMT_FIFO_LH1_11", - "CMT_FIFO_LH1_2", - "CMT_FIFO_LH1_3", - "CMT_FIFO_LH1_4", - "CMT_FIFO_LH1_5", - "CMT_FIFO_LH1_6", - "CMT_FIFO_LH1_7", - "CMT_FIFO_LH1_8", - "CMT_FIFO_LH1_9", - "CMT_FIFO_LH2_0", - "CMT_FIFO_LH2_1", - "CMT_FIFO_LH2_10", - "CMT_FIFO_LH2_11", - "CMT_FIFO_LH2_2", - "CMT_FIFO_LH2_3", - "CMT_FIFO_LH2_4", - "CMT_FIFO_LH2_5", - "CMT_FIFO_LH2_6", - "CMT_FIFO_LH2_7", - "CMT_FIFO_LH2_8", - "CMT_FIFO_LH2_9", - "CMT_FIFO_LH3_0", - "CMT_FIFO_LH3_1", - "CMT_FIFO_LH3_10", - "CMT_FIFO_LH3_11", - "CMT_FIFO_LH3_2", - "CMT_FIFO_LH3_3", - "CMT_FIFO_LH3_4", - "CMT_FIFO_LH3_5", - "CMT_FIFO_LH3_6", - "CMT_FIFO_LH3_7", - "CMT_FIFO_LH3_8", - "CMT_FIFO_LH3_9", - "CMT_FIFO_LH4_0", - "CMT_FIFO_LH4_1", - "CMT_FIFO_LH4_10", - "CMT_FIFO_LH4_11", - "CMT_FIFO_LH4_2", - "CMT_FIFO_LH4_3", - "CMT_FIFO_LH4_4", - "CMT_FIFO_LH4_5", - "CMT_FIFO_LH4_6", - "CMT_FIFO_LH4_7", - "CMT_FIFO_LH4_8", - "CMT_FIFO_LH4_9", - "CMT_FIFO_LH5_0", - "CMT_FIFO_LH5_1", - "CMT_FIFO_LH5_10", - "CMT_FIFO_LH5_11", - "CMT_FIFO_LH5_2", - "CMT_FIFO_LH5_3", - "CMT_FIFO_LH5_4", - "CMT_FIFO_LH5_5", - "CMT_FIFO_LH5_6", - "CMT_FIFO_LH5_7", - "CMT_FIFO_LH5_8", - "CMT_FIFO_LH5_9", - "CMT_FIFO_LH6_0", - "CMT_FIFO_LH6_1", - "CMT_FIFO_LH6_10", - "CMT_FIFO_LH6_11", - "CMT_FIFO_LH6_2", - "CMT_FIFO_LH6_3", - "CMT_FIFO_LH6_4", - "CMT_FIFO_LH6_5", - "CMT_FIFO_LH6_6", - "CMT_FIFO_LH6_7", - "CMT_FIFO_LH6_8", - "CMT_FIFO_LH6_9", - "CMT_FIFO_LH7_0", - "CMT_FIFO_LH7_1", - "CMT_FIFO_LH7_10", - "CMT_FIFO_LH7_11", - "CMT_FIFO_LH7_2", - "CMT_FIFO_LH7_3", - "CMT_FIFO_LH7_4", - "CMT_FIFO_LH7_5", - "CMT_FIFO_LH7_6", - "CMT_FIFO_LH7_7", - "CMT_FIFO_LH7_8", - "CMT_FIFO_LH7_9", - "CMT_FIFO_LH8_0", - "CMT_FIFO_LH8_1", - "CMT_FIFO_LH8_10", - "CMT_FIFO_LH8_11", - "CMT_FIFO_LH8_2", - "CMT_FIFO_LH8_3", - "CMT_FIFO_LH8_4", - "CMT_FIFO_LH8_5", - "CMT_FIFO_LH8_6", - "CMT_FIFO_LH8_7", - "CMT_FIFO_LH8_8", - "CMT_FIFO_LH8_9", - "CMT_FIFO_LH9_0", - "CMT_FIFO_LH9_1", - "CMT_FIFO_LH9_10", - "CMT_FIFO_LH9_11", - "CMT_FIFO_LH9_2", - "CMT_FIFO_LH9_3", - "CMT_FIFO_LH9_4", - "CMT_FIFO_LH9_5", - "CMT_FIFO_LH9_6", - "CMT_FIFO_LH9_7", - "CMT_FIFO_LH9_8", - "CMT_FIFO_LH9_9", - "CMT_FIFO_L_BYP0_0", - "CMT_FIFO_L_BYP0_1", - "CMT_FIFO_L_BYP0_10", - "CMT_FIFO_L_BYP0_11", - "CMT_FIFO_L_BYP0_2", - "CMT_FIFO_L_BYP0_3", - "CMT_FIFO_L_BYP0_4", - "CMT_FIFO_L_BYP0_5", - "CMT_FIFO_L_BYP0_6", - "CMT_FIFO_L_BYP0_7", - "CMT_FIFO_L_BYP0_8", - "CMT_FIFO_L_BYP0_9", - "CMT_FIFO_L_BYP1_0", - "CMT_FIFO_L_BYP1_1", - "CMT_FIFO_L_BYP1_10", - "CMT_FIFO_L_BYP1_11", - "CMT_FIFO_L_BYP1_2", - "CMT_FIFO_L_BYP1_3", - "CMT_FIFO_L_BYP1_4", - "CMT_FIFO_L_BYP1_5", - "CMT_FIFO_L_BYP1_6", - "CMT_FIFO_L_BYP1_7", - "CMT_FIFO_L_BYP1_8", - "CMT_FIFO_L_BYP1_9", - "CMT_FIFO_L_BYP2_0", - "CMT_FIFO_L_BYP2_1", - "CMT_FIFO_L_BYP2_10", - "CMT_FIFO_L_BYP2_11", - "CMT_FIFO_L_BYP2_2", - "CMT_FIFO_L_BYP2_3", - "CMT_FIFO_L_BYP2_4", - "CMT_FIFO_L_BYP2_5", - "CMT_FIFO_L_BYP2_6", - "CMT_FIFO_L_BYP2_7", - "CMT_FIFO_L_BYP2_8", - "CMT_FIFO_L_BYP2_9", - "CMT_FIFO_L_BYP3_0", - "CMT_FIFO_L_BYP3_1", - "CMT_FIFO_L_BYP3_10", - "CMT_FIFO_L_BYP3_11", - "CMT_FIFO_L_BYP3_2", - "CMT_FIFO_L_BYP3_3", - "CMT_FIFO_L_BYP3_4", - "CMT_FIFO_L_BYP3_5", - "CMT_FIFO_L_BYP3_6", - "CMT_FIFO_L_BYP3_7", - "CMT_FIFO_L_BYP3_8", - "CMT_FIFO_L_BYP3_9", - "CMT_FIFO_L_BYP4_0", - "CMT_FIFO_L_BYP4_1", - "CMT_FIFO_L_BYP4_10", - "CMT_FIFO_L_BYP4_11", - "CMT_FIFO_L_BYP4_2", - "CMT_FIFO_L_BYP4_3", - "CMT_FIFO_L_BYP4_4", - "CMT_FIFO_L_BYP4_5", - "CMT_FIFO_L_BYP4_6", - "CMT_FIFO_L_BYP4_7", - "CMT_FIFO_L_BYP4_8", - "CMT_FIFO_L_BYP4_9", - "CMT_FIFO_L_BYP5_0", - "CMT_FIFO_L_BYP5_1", - "CMT_FIFO_L_BYP5_10", - "CMT_FIFO_L_BYP5_11", - "CMT_FIFO_L_BYP5_2", - "CMT_FIFO_L_BYP5_3", - "CMT_FIFO_L_BYP5_4", - "CMT_FIFO_L_BYP5_5", - "CMT_FIFO_L_BYP5_6", - "CMT_FIFO_L_BYP5_7", - "CMT_FIFO_L_BYP5_8", - "CMT_FIFO_L_BYP5_9", - "CMT_FIFO_L_BYP6_0", - "CMT_FIFO_L_BYP6_1", - "CMT_FIFO_L_BYP6_10", - "CMT_FIFO_L_BYP6_11", - "CMT_FIFO_L_BYP6_2", - "CMT_FIFO_L_BYP6_3", - "CMT_FIFO_L_BYP6_4", - "CMT_FIFO_L_BYP6_5", - "CMT_FIFO_L_BYP6_6", - "CMT_FIFO_L_BYP6_7", - "CMT_FIFO_L_BYP6_8", - "CMT_FIFO_L_BYP6_9", - "CMT_FIFO_L_BYP7_0", - "CMT_FIFO_L_BYP7_1", - "CMT_FIFO_L_BYP7_10", - "CMT_FIFO_L_BYP7_11", - "CMT_FIFO_L_BYP7_2", - "CMT_FIFO_L_BYP7_3", - "CMT_FIFO_L_BYP7_4", - "CMT_FIFO_L_BYP7_5", - "CMT_FIFO_L_BYP7_6", - "CMT_FIFO_L_BYP7_7", - "CMT_FIFO_L_BYP7_8", - "CMT_FIFO_L_BYP7_9", - "CMT_FIFO_L_CLK0_0", - "CMT_FIFO_L_CLK0_1", - "CMT_FIFO_L_CLK0_10", - "CMT_FIFO_L_CLK0_11", - "CMT_FIFO_L_CLK0_2", - "CMT_FIFO_L_CLK0_3", - "CMT_FIFO_L_CLK0_4", - "CMT_FIFO_L_CLK0_5", - "CMT_FIFO_L_CLK0_6", - "CMT_FIFO_L_CLK0_7", - "CMT_FIFO_L_CLK0_8", - "CMT_FIFO_L_CLK0_9", - "CMT_FIFO_L_CLK1_0", - "CMT_FIFO_L_CLK1_1", - "CMT_FIFO_L_CLK1_10", - "CMT_FIFO_L_CLK1_11", - "CMT_FIFO_L_CLK1_2", - "CMT_FIFO_L_CLK1_3", - "CMT_FIFO_L_CLK1_4", - "CMT_FIFO_L_CLK1_5", - "CMT_FIFO_L_CLK1_6", - "CMT_FIFO_L_CLK1_7", - "CMT_FIFO_L_CLK1_8", - "CMT_FIFO_L_CLK1_9", - "CMT_FIFO_L_CTRL0_0", - "CMT_FIFO_L_CTRL0_1", - "CMT_FIFO_L_CTRL0_10", - "CMT_FIFO_L_CTRL0_11", - "CMT_FIFO_L_CTRL0_2", - "CMT_FIFO_L_CTRL0_3", - "CMT_FIFO_L_CTRL0_4", - "CMT_FIFO_L_CTRL0_5", - "CMT_FIFO_L_CTRL0_6", - "CMT_FIFO_L_CTRL0_7", - "CMT_FIFO_L_CTRL0_8", - "CMT_FIFO_L_CTRL0_9", - "CMT_FIFO_L_CTRL1_0", - "CMT_FIFO_L_CTRL1_1", - "CMT_FIFO_L_CTRL1_10", - "CMT_FIFO_L_CTRL1_11", - "CMT_FIFO_L_CTRL1_2", - "CMT_FIFO_L_CTRL1_3", - "CMT_FIFO_L_CTRL1_4", - "CMT_FIFO_L_CTRL1_5", - "CMT_FIFO_L_CTRL1_6", - "CMT_FIFO_L_CTRL1_7", - "CMT_FIFO_L_CTRL1_8", - "CMT_FIFO_L_CTRL1_9", - "CMT_FIFO_L_FAN0_0", - "CMT_FIFO_L_FAN0_1", - "CMT_FIFO_L_FAN0_10", - "CMT_FIFO_L_FAN0_11", - "CMT_FIFO_L_FAN0_2", - "CMT_FIFO_L_FAN0_3", - "CMT_FIFO_L_FAN0_4", - "CMT_FIFO_L_FAN0_5", - "CMT_FIFO_L_FAN0_6", - "CMT_FIFO_L_FAN0_7", - "CMT_FIFO_L_FAN0_8", - "CMT_FIFO_L_FAN0_9", - "CMT_FIFO_L_FAN1_0", - "CMT_FIFO_L_FAN1_1", - "CMT_FIFO_L_FAN1_10", - "CMT_FIFO_L_FAN1_11", - "CMT_FIFO_L_FAN1_2", - "CMT_FIFO_L_FAN1_3", - "CMT_FIFO_L_FAN1_4", - "CMT_FIFO_L_FAN1_5", - "CMT_FIFO_L_FAN1_6", - "CMT_FIFO_L_FAN1_7", - "CMT_FIFO_L_FAN1_8", - "CMT_FIFO_L_FAN1_9", - "CMT_FIFO_L_FAN2_0", - "CMT_FIFO_L_FAN2_1", - "CMT_FIFO_L_FAN2_10", - "CMT_FIFO_L_FAN2_11", - "CMT_FIFO_L_FAN2_2", - "CMT_FIFO_L_FAN2_3", - "CMT_FIFO_L_FAN2_4", - "CMT_FIFO_L_FAN2_5", - "CMT_FIFO_L_FAN2_6", - "CMT_FIFO_L_FAN2_7", - "CMT_FIFO_L_FAN2_8", - "CMT_FIFO_L_FAN2_9", - "CMT_FIFO_L_FAN3_0", - "CMT_FIFO_L_FAN3_1", - "CMT_FIFO_L_FAN3_10", - "CMT_FIFO_L_FAN3_11", - "CMT_FIFO_L_FAN3_2", - "CMT_FIFO_L_FAN3_3", - "CMT_FIFO_L_FAN3_4", - "CMT_FIFO_L_FAN3_5", - "CMT_FIFO_L_FAN3_6", - "CMT_FIFO_L_FAN3_7", - "CMT_FIFO_L_FAN3_8", - "CMT_FIFO_L_FAN3_9", - "CMT_FIFO_L_FAN4_0", - "CMT_FIFO_L_FAN4_1", - "CMT_FIFO_L_FAN4_10", - "CMT_FIFO_L_FAN4_11", - "CMT_FIFO_L_FAN4_2", - "CMT_FIFO_L_FAN4_3", - "CMT_FIFO_L_FAN4_4", - "CMT_FIFO_L_FAN4_5", - "CMT_FIFO_L_FAN4_6", - "CMT_FIFO_L_FAN4_7", - "CMT_FIFO_L_FAN4_8", - "CMT_FIFO_L_FAN4_9", - "CMT_FIFO_L_FAN5_0", - "CMT_FIFO_L_FAN5_1", - "CMT_FIFO_L_FAN5_10", - "CMT_FIFO_L_FAN5_11", - "CMT_FIFO_L_FAN5_2", - "CMT_FIFO_L_FAN5_3", - "CMT_FIFO_L_FAN5_4", - "CMT_FIFO_L_FAN5_5", - "CMT_FIFO_L_FAN5_6", - "CMT_FIFO_L_FAN5_7", - "CMT_FIFO_L_FAN5_8", - "CMT_FIFO_L_FAN5_9", - "CMT_FIFO_L_FAN6_0", - "CMT_FIFO_L_FAN6_1", - "CMT_FIFO_L_FAN6_10", - "CMT_FIFO_L_FAN6_11", - "CMT_FIFO_L_FAN6_2", - "CMT_FIFO_L_FAN6_3", - "CMT_FIFO_L_FAN6_4", - "CMT_FIFO_L_FAN6_5", - "CMT_FIFO_L_FAN6_6", - "CMT_FIFO_L_FAN6_7", - "CMT_FIFO_L_FAN6_8", - "CMT_FIFO_L_FAN6_9", - "CMT_FIFO_L_FAN7_0", - "CMT_FIFO_L_FAN7_1", - "CMT_FIFO_L_FAN7_10", - "CMT_FIFO_L_FAN7_11", - "CMT_FIFO_L_FAN7_2", - "CMT_FIFO_L_FAN7_3", - "CMT_FIFO_L_FAN7_4", - "CMT_FIFO_L_FAN7_5", - "CMT_FIFO_L_FAN7_6", - "CMT_FIFO_L_FAN7_7", - "CMT_FIFO_L_FAN7_8", - "CMT_FIFO_L_FAN7_9", - "CMT_FIFO_L_IMUX0_0", - "CMT_FIFO_L_IMUX0_1", - "CMT_FIFO_L_IMUX0_10", - "CMT_FIFO_L_IMUX0_11", - "CMT_FIFO_L_IMUX0_2", - "CMT_FIFO_L_IMUX0_3", - "CMT_FIFO_L_IMUX0_4", - "CMT_FIFO_L_IMUX0_5", - "CMT_FIFO_L_IMUX0_6", - "CMT_FIFO_L_IMUX0_7", - "CMT_FIFO_L_IMUX0_8", - "CMT_FIFO_L_IMUX0_9", - "CMT_FIFO_L_IMUX10_0", - "CMT_FIFO_L_IMUX10_1", - "CMT_FIFO_L_IMUX10_10", - "CMT_FIFO_L_IMUX10_11", - "CMT_FIFO_L_IMUX10_2", - "CMT_FIFO_L_IMUX10_3", - "CMT_FIFO_L_IMUX10_4", - "CMT_FIFO_L_IMUX10_5", - "CMT_FIFO_L_IMUX10_6", - "CMT_FIFO_L_IMUX10_7", - "CMT_FIFO_L_IMUX10_8", - "CMT_FIFO_L_IMUX10_9", - "CMT_FIFO_L_IMUX11_0", - "CMT_FIFO_L_IMUX11_1", - "CMT_FIFO_L_IMUX11_10", - "CMT_FIFO_L_IMUX11_11", - "CMT_FIFO_L_IMUX11_2", - "CMT_FIFO_L_IMUX11_3", - "CMT_FIFO_L_IMUX11_4", - "CMT_FIFO_L_IMUX11_5", - "CMT_FIFO_L_IMUX11_6", - "CMT_FIFO_L_IMUX11_7", - "CMT_FIFO_L_IMUX11_8", - "CMT_FIFO_L_IMUX11_9", - "CMT_FIFO_L_IMUX12_0", - "CMT_FIFO_L_IMUX12_1", - "CMT_FIFO_L_IMUX12_10", - "CMT_FIFO_L_IMUX12_11", - "CMT_FIFO_L_IMUX12_2", - "CMT_FIFO_L_IMUX12_3", - "CMT_FIFO_L_IMUX12_4", - "CMT_FIFO_L_IMUX12_5", - "CMT_FIFO_L_IMUX12_6", - "CMT_FIFO_L_IMUX12_7", - "CMT_FIFO_L_IMUX12_8", - "CMT_FIFO_L_IMUX12_9", - "CMT_FIFO_L_IMUX13_0", - "CMT_FIFO_L_IMUX13_1", - "CMT_FIFO_L_IMUX13_10", - "CMT_FIFO_L_IMUX13_11", - "CMT_FIFO_L_IMUX13_2", - "CMT_FIFO_L_IMUX13_3", - "CMT_FIFO_L_IMUX13_4", - "CMT_FIFO_L_IMUX13_5", - "CMT_FIFO_L_IMUX13_6", - "CMT_FIFO_L_IMUX13_7", - "CMT_FIFO_L_IMUX13_8", - "CMT_FIFO_L_IMUX13_9", - "CMT_FIFO_L_IMUX14_0", - "CMT_FIFO_L_IMUX14_1", - "CMT_FIFO_L_IMUX14_10", - "CMT_FIFO_L_IMUX14_11", - "CMT_FIFO_L_IMUX14_2", - "CMT_FIFO_L_IMUX14_3", - "CMT_FIFO_L_IMUX14_4", - "CMT_FIFO_L_IMUX14_5", - "CMT_FIFO_L_IMUX14_6", - "CMT_FIFO_L_IMUX14_7", - "CMT_FIFO_L_IMUX14_8", - "CMT_FIFO_L_IMUX14_9", - "CMT_FIFO_L_IMUX15_0", - "CMT_FIFO_L_IMUX15_1", - "CMT_FIFO_L_IMUX15_10", - "CMT_FIFO_L_IMUX15_11", - "CMT_FIFO_L_IMUX15_2", - "CMT_FIFO_L_IMUX15_3", - "CMT_FIFO_L_IMUX15_4", - "CMT_FIFO_L_IMUX15_5", - "CMT_FIFO_L_IMUX15_6", - "CMT_FIFO_L_IMUX15_7", - "CMT_FIFO_L_IMUX15_8", - "CMT_FIFO_L_IMUX15_9", - "CMT_FIFO_L_IMUX16_0", - "CMT_FIFO_L_IMUX16_1", - "CMT_FIFO_L_IMUX16_10", - "CMT_FIFO_L_IMUX16_11", - "CMT_FIFO_L_IMUX16_2", - "CMT_FIFO_L_IMUX16_3", - "CMT_FIFO_L_IMUX16_4", - "CMT_FIFO_L_IMUX16_5", - "CMT_FIFO_L_IMUX16_6", - "CMT_FIFO_L_IMUX16_7", - "CMT_FIFO_L_IMUX16_8", - "CMT_FIFO_L_IMUX16_9", - "CMT_FIFO_L_IMUX17_0", - "CMT_FIFO_L_IMUX17_1", - "CMT_FIFO_L_IMUX17_10", - "CMT_FIFO_L_IMUX17_11", - "CMT_FIFO_L_IMUX17_2", - "CMT_FIFO_L_IMUX17_3", - "CMT_FIFO_L_IMUX17_4", - "CMT_FIFO_L_IMUX17_5", - "CMT_FIFO_L_IMUX17_6", - "CMT_FIFO_L_IMUX17_7", - "CMT_FIFO_L_IMUX17_8", - "CMT_FIFO_L_IMUX17_9", - "CMT_FIFO_L_IMUX18_0", - "CMT_FIFO_L_IMUX18_1", - "CMT_FIFO_L_IMUX18_10", - "CMT_FIFO_L_IMUX18_11", - "CMT_FIFO_L_IMUX18_2", - "CMT_FIFO_L_IMUX18_3", - "CMT_FIFO_L_IMUX18_4", - "CMT_FIFO_L_IMUX18_5", - "CMT_FIFO_L_IMUX18_6", - "CMT_FIFO_L_IMUX18_7", - "CMT_FIFO_L_IMUX18_8", - "CMT_FIFO_L_IMUX18_9", - "CMT_FIFO_L_IMUX19_0", - "CMT_FIFO_L_IMUX19_1", - "CMT_FIFO_L_IMUX19_10", - "CMT_FIFO_L_IMUX19_11", - "CMT_FIFO_L_IMUX19_2", - "CMT_FIFO_L_IMUX19_3", - "CMT_FIFO_L_IMUX19_4", - "CMT_FIFO_L_IMUX19_5", - "CMT_FIFO_L_IMUX19_6", - "CMT_FIFO_L_IMUX19_7", - "CMT_FIFO_L_IMUX19_8", - "CMT_FIFO_L_IMUX19_9", - "CMT_FIFO_L_IMUX1_0", - "CMT_FIFO_L_IMUX1_1", - "CMT_FIFO_L_IMUX1_10", - "CMT_FIFO_L_IMUX1_11", - "CMT_FIFO_L_IMUX1_2", - "CMT_FIFO_L_IMUX1_3", - "CMT_FIFO_L_IMUX1_4", - "CMT_FIFO_L_IMUX1_5", - "CMT_FIFO_L_IMUX1_6", - "CMT_FIFO_L_IMUX1_7", - "CMT_FIFO_L_IMUX1_8", - "CMT_FIFO_L_IMUX1_9", - "CMT_FIFO_L_IMUX20_0", - "CMT_FIFO_L_IMUX20_1", - "CMT_FIFO_L_IMUX20_10", - "CMT_FIFO_L_IMUX20_11", - "CMT_FIFO_L_IMUX20_2", - "CMT_FIFO_L_IMUX20_3", - "CMT_FIFO_L_IMUX20_4", - "CMT_FIFO_L_IMUX20_5", - "CMT_FIFO_L_IMUX20_6", - "CMT_FIFO_L_IMUX20_7", - "CMT_FIFO_L_IMUX20_8", - "CMT_FIFO_L_IMUX20_9", - "CMT_FIFO_L_IMUX21_0", - "CMT_FIFO_L_IMUX21_1", - "CMT_FIFO_L_IMUX21_10", - "CMT_FIFO_L_IMUX21_11", - "CMT_FIFO_L_IMUX21_2", - "CMT_FIFO_L_IMUX21_3", - "CMT_FIFO_L_IMUX21_4", - "CMT_FIFO_L_IMUX21_5", - "CMT_FIFO_L_IMUX21_6", - "CMT_FIFO_L_IMUX21_7", - "CMT_FIFO_L_IMUX21_8", - "CMT_FIFO_L_IMUX21_9", - "CMT_FIFO_L_IMUX22_0", - "CMT_FIFO_L_IMUX22_1", - "CMT_FIFO_L_IMUX22_10", - "CMT_FIFO_L_IMUX22_11", - "CMT_FIFO_L_IMUX22_2", - "CMT_FIFO_L_IMUX22_3", - "CMT_FIFO_L_IMUX22_4", - "CMT_FIFO_L_IMUX22_5", - "CMT_FIFO_L_IMUX22_6", - "CMT_FIFO_L_IMUX22_7", - "CMT_FIFO_L_IMUX22_8", - "CMT_FIFO_L_IMUX22_9", - "CMT_FIFO_L_IMUX23_0", - "CMT_FIFO_L_IMUX23_1", - "CMT_FIFO_L_IMUX23_10", - "CMT_FIFO_L_IMUX23_11", - "CMT_FIFO_L_IMUX23_2", - "CMT_FIFO_L_IMUX23_3", - "CMT_FIFO_L_IMUX23_4", - "CMT_FIFO_L_IMUX23_5", - "CMT_FIFO_L_IMUX23_6", - "CMT_FIFO_L_IMUX23_7", - "CMT_FIFO_L_IMUX23_8", - "CMT_FIFO_L_IMUX23_9", - "CMT_FIFO_L_IMUX24_0", - "CMT_FIFO_L_IMUX24_1", - "CMT_FIFO_L_IMUX24_10", - "CMT_FIFO_L_IMUX24_11", - "CMT_FIFO_L_IMUX24_2", - "CMT_FIFO_L_IMUX24_3", - "CMT_FIFO_L_IMUX24_4", - "CMT_FIFO_L_IMUX24_5", - "CMT_FIFO_L_IMUX24_6", - "CMT_FIFO_L_IMUX24_7", - "CMT_FIFO_L_IMUX24_8", - "CMT_FIFO_L_IMUX24_9", - "CMT_FIFO_L_IMUX25_0", - "CMT_FIFO_L_IMUX25_1", - "CMT_FIFO_L_IMUX25_10", - "CMT_FIFO_L_IMUX25_11", - "CMT_FIFO_L_IMUX25_2", - "CMT_FIFO_L_IMUX25_3", - "CMT_FIFO_L_IMUX25_4", - "CMT_FIFO_L_IMUX25_5", - "CMT_FIFO_L_IMUX25_6", - "CMT_FIFO_L_IMUX25_7", - "CMT_FIFO_L_IMUX25_8", - "CMT_FIFO_L_IMUX25_9", - "CMT_FIFO_L_IMUX26_0", - "CMT_FIFO_L_IMUX26_1", - "CMT_FIFO_L_IMUX26_10", - "CMT_FIFO_L_IMUX26_11", - "CMT_FIFO_L_IMUX26_2", - "CMT_FIFO_L_IMUX26_3", - "CMT_FIFO_L_IMUX26_4", - "CMT_FIFO_L_IMUX26_5", - "CMT_FIFO_L_IMUX26_6", - "CMT_FIFO_L_IMUX26_7", - "CMT_FIFO_L_IMUX26_8", - "CMT_FIFO_L_IMUX26_9", - "CMT_FIFO_L_IMUX27_0", - "CMT_FIFO_L_IMUX27_1", - "CMT_FIFO_L_IMUX27_10", - "CMT_FIFO_L_IMUX27_11", - "CMT_FIFO_L_IMUX27_2", - "CMT_FIFO_L_IMUX27_3", - "CMT_FIFO_L_IMUX27_4", - "CMT_FIFO_L_IMUX27_5", - "CMT_FIFO_L_IMUX27_6", - "CMT_FIFO_L_IMUX27_7", - "CMT_FIFO_L_IMUX27_8", - "CMT_FIFO_L_IMUX27_9", - "CMT_FIFO_L_IMUX28_0", - "CMT_FIFO_L_IMUX28_1", - "CMT_FIFO_L_IMUX28_10", - "CMT_FIFO_L_IMUX28_11", - "CMT_FIFO_L_IMUX28_2", - "CMT_FIFO_L_IMUX28_3", - "CMT_FIFO_L_IMUX28_4", - "CMT_FIFO_L_IMUX28_5", - "CMT_FIFO_L_IMUX28_6", - "CMT_FIFO_L_IMUX28_7", - "CMT_FIFO_L_IMUX28_8", - "CMT_FIFO_L_IMUX28_9", - "CMT_FIFO_L_IMUX29_0", - "CMT_FIFO_L_IMUX29_1", - "CMT_FIFO_L_IMUX29_10", - "CMT_FIFO_L_IMUX29_11", - "CMT_FIFO_L_IMUX29_2", - "CMT_FIFO_L_IMUX29_3", - "CMT_FIFO_L_IMUX29_4", - "CMT_FIFO_L_IMUX29_5", - "CMT_FIFO_L_IMUX29_6", - "CMT_FIFO_L_IMUX29_7", - "CMT_FIFO_L_IMUX29_8", - "CMT_FIFO_L_IMUX29_9", - "CMT_FIFO_L_IMUX2_0", - "CMT_FIFO_L_IMUX2_1", - "CMT_FIFO_L_IMUX2_10", - "CMT_FIFO_L_IMUX2_11", - "CMT_FIFO_L_IMUX2_2", - "CMT_FIFO_L_IMUX2_3", - "CMT_FIFO_L_IMUX2_4", - "CMT_FIFO_L_IMUX2_5", - "CMT_FIFO_L_IMUX2_6", - "CMT_FIFO_L_IMUX2_7", - "CMT_FIFO_L_IMUX2_8", - "CMT_FIFO_L_IMUX2_9", - "CMT_FIFO_L_IMUX30_0", - "CMT_FIFO_L_IMUX30_1", - "CMT_FIFO_L_IMUX30_10", - "CMT_FIFO_L_IMUX30_11", - "CMT_FIFO_L_IMUX30_2", - "CMT_FIFO_L_IMUX30_3", - "CMT_FIFO_L_IMUX30_4", - "CMT_FIFO_L_IMUX30_5", - "CMT_FIFO_L_IMUX30_6", - "CMT_FIFO_L_IMUX30_7", - "CMT_FIFO_L_IMUX30_8", - "CMT_FIFO_L_IMUX30_9", - "CMT_FIFO_L_IMUX31_0", - "CMT_FIFO_L_IMUX31_1", - "CMT_FIFO_L_IMUX31_10", - "CMT_FIFO_L_IMUX31_11", - "CMT_FIFO_L_IMUX31_2", - "CMT_FIFO_L_IMUX31_3", - "CMT_FIFO_L_IMUX31_4", - "CMT_FIFO_L_IMUX31_5", - "CMT_FIFO_L_IMUX31_6", - "CMT_FIFO_L_IMUX31_7", - "CMT_FIFO_L_IMUX31_8", - "CMT_FIFO_L_IMUX31_9", - "CMT_FIFO_L_IMUX32_0", - "CMT_FIFO_L_IMUX32_1", - "CMT_FIFO_L_IMUX32_10", - "CMT_FIFO_L_IMUX32_11", - "CMT_FIFO_L_IMUX32_2", - "CMT_FIFO_L_IMUX32_3", - "CMT_FIFO_L_IMUX32_4", - "CMT_FIFO_L_IMUX32_5", - "CMT_FIFO_L_IMUX32_6", - "CMT_FIFO_L_IMUX32_7", - "CMT_FIFO_L_IMUX32_8", - "CMT_FIFO_L_IMUX32_9", - "CMT_FIFO_L_IMUX33_0", - "CMT_FIFO_L_IMUX33_1", - "CMT_FIFO_L_IMUX33_10", - "CMT_FIFO_L_IMUX33_11", - "CMT_FIFO_L_IMUX33_2", - "CMT_FIFO_L_IMUX33_3", - "CMT_FIFO_L_IMUX33_4", - "CMT_FIFO_L_IMUX33_5", - "CMT_FIFO_L_IMUX33_6", - "CMT_FIFO_L_IMUX33_7", - "CMT_FIFO_L_IMUX33_8", - "CMT_FIFO_L_IMUX33_9", - "CMT_FIFO_L_IMUX34_0", - "CMT_FIFO_L_IMUX34_1", - "CMT_FIFO_L_IMUX34_10", - "CMT_FIFO_L_IMUX34_11", - "CMT_FIFO_L_IMUX34_2", - "CMT_FIFO_L_IMUX34_3", - "CMT_FIFO_L_IMUX34_4", - "CMT_FIFO_L_IMUX34_5", - "CMT_FIFO_L_IMUX34_6", - "CMT_FIFO_L_IMUX34_7", - "CMT_FIFO_L_IMUX34_8", - "CMT_FIFO_L_IMUX34_9", - "CMT_FIFO_L_IMUX35_0", - "CMT_FIFO_L_IMUX35_1", - "CMT_FIFO_L_IMUX35_10", - "CMT_FIFO_L_IMUX35_11", - "CMT_FIFO_L_IMUX35_2", - "CMT_FIFO_L_IMUX35_3", - "CMT_FIFO_L_IMUX35_4", - "CMT_FIFO_L_IMUX35_5", - "CMT_FIFO_L_IMUX35_6", - "CMT_FIFO_L_IMUX35_7", - "CMT_FIFO_L_IMUX35_8", - "CMT_FIFO_L_IMUX35_9", - "CMT_FIFO_L_IMUX36_0", - "CMT_FIFO_L_IMUX36_1", - "CMT_FIFO_L_IMUX36_10", - "CMT_FIFO_L_IMUX36_11", - "CMT_FIFO_L_IMUX36_2", - "CMT_FIFO_L_IMUX36_3", - "CMT_FIFO_L_IMUX36_4", - "CMT_FIFO_L_IMUX36_5", - "CMT_FIFO_L_IMUX36_6", - "CMT_FIFO_L_IMUX36_7", - "CMT_FIFO_L_IMUX36_8", - "CMT_FIFO_L_IMUX36_9", - "CMT_FIFO_L_IMUX37_0", - "CMT_FIFO_L_IMUX37_1", - "CMT_FIFO_L_IMUX37_10", - "CMT_FIFO_L_IMUX37_11", - "CMT_FIFO_L_IMUX37_2", - "CMT_FIFO_L_IMUX37_3", - "CMT_FIFO_L_IMUX37_4", - "CMT_FIFO_L_IMUX37_5", - "CMT_FIFO_L_IMUX37_6", - "CMT_FIFO_L_IMUX37_7", - "CMT_FIFO_L_IMUX37_8", - "CMT_FIFO_L_IMUX37_9", - "CMT_FIFO_L_IMUX38_0", - "CMT_FIFO_L_IMUX38_1", - "CMT_FIFO_L_IMUX38_10", - "CMT_FIFO_L_IMUX38_11", - "CMT_FIFO_L_IMUX38_2", - "CMT_FIFO_L_IMUX38_3", - "CMT_FIFO_L_IMUX38_4", - "CMT_FIFO_L_IMUX38_5", - "CMT_FIFO_L_IMUX38_6", - "CMT_FIFO_L_IMUX38_7", - "CMT_FIFO_L_IMUX38_8", - "CMT_FIFO_L_IMUX38_9", - "CMT_FIFO_L_IMUX39_0", - "CMT_FIFO_L_IMUX39_1", - "CMT_FIFO_L_IMUX39_10", - "CMT_FIFO_L_IMUX39_11", - "CMT_FIFO_L_IMUX39_2", - "CMT_FIFO_L_IMUX39_3", - "CMT_FIFO_L_IMUX39_4", - "CMT_FIFO_L_IMUX39_5", - "CMT_FIFO_L_IMUX39_6", - "CMT_FIFO_L_IMUX39_7", - "CMT_FIFO_L_IMUX39_8", - "CMT_FIFO_L_IMUX39_9", - "CMT_FIFO_L_IMUX3_0", - "CMT_FIFO_L_IMUX3_1", - "CMT_FIFO_L_IMUX3_10", - "CMT_FIFO_L_IMUX3_11", - "CMT_FIFO_L_IMUX3_2", - "CMT_FIFO_L_IMUX3_3", - "CMT_FIFO_L_IMUX3_4", - "CMT_FIFO_L_IMUX3_5", - "CMT_FIFO_L_IMUX3_6", - "CMT_FIFO_L_IMUX3_7", - "CMT_FIFO_L_IMUX3_8", - "CMT_FIFO_L_IMUX3_9", - "CMT_FIFO_L_IMUX40_0", - "CMT_FIFO_L_IMUX40_1", - "CMT_FIFO_L_IMUX40_10", - "CMT_FIFO_L_IMUX40_11", - "CMT_FIFO_L_IMUX40_2", - "CMT_FIFO_L_IMUX40_3", - "CMT_FIFO_L_IMUX40_4", - "CMT_FIFO_L_IMUX40_5", - "CMT_FIFO_L_IMUX40_6", - "CMT_FIFO_L_IMUX40_7", - "CMT_FIFO_L_IMUX40_8", - "CMT_FIFO_L_IMUX40_9", - "CMT_FIFO_L_IMUX41_0", - "CMT_FIFO_L_IMUX41_1", - "CMT_FIFO_L_IMUX41_10", - "CMT_FIFO_L_IMUX41_11", - "CMT_FIFO_L_IMUX41_2", - "CMT_FIFO_L_IMUX41_3", - "CMT_FIFO_L_IMUX41_4", - "CMT_FIFO_L_IMUX41_5", - "CMT_FIFO_L_IMUX41_6", - "CMT_FIFO_L_IMUX41_7", - "CMT_FIFO_L_IMUX41_8", - "CMT_FIFO_L_IMUX41_9", - "CMT_FIFO_L_IMUX42_0", - "CMT_FIFO_L_IMUX42_1", - "CMT_FIFO_L_IMUX42_10", - "CMT_FIFO_L_IMUX42_11", - "CMT_FIFO_L_IMUX42_2", - "CMT_FIFO_L_IMUX42_3", - "CMT_FIFO_L_IMUX42_4", - "CMT_FIFO_L_IMUX42_5", - "CMT_FIFO_L_IMUX42_6", - "CMT_FIFO_L_IMUX42_7", - "CMT_FIFO_L_IMUX42_8", - "CMT_FIFO_L_IMUX42_9", - "CMT_FIFO_L_IMUX43_0", - "CMT_FIFO_L_IMUX43_1", - "CMT_FIFO_L_IMUX43_10", - "CMT_FIFO_L_IMUX43_11", - "CMT_FIFO_L_IMUX43_2", - "CMT_FIFO_L_IMUX43_3", - "CMT_FIFO_L_IMUX43_4", - "CMT_FIFO_L_IMUX43_5", - "CMT_FIFO_L_IMUX43_6", - "CMT_FIFO_L_IMUX43_7", - "CMT_FIFO_L_IMUX43_8", - "CMT_FIFO_L_IMUX43_9", - "CMT_FIFO_L_IMUX44_0", - "CMT_FIFO_L_IMUX44_1", - "CMT_FIFO_L_IMUX44_10", - "CMT_FIFO_L_IMUX44_11", - "CMT_FIFO_L_IMUX44_2", - "CMT_FIFO_L_IMUX44_3", - "CMT_FIFO_L_IMUX44_4", - "CMT_FIFO_L_IMUX44_5", - "CMT_FIFO_L_IMUX44_6", - "CMT_FIFO_L_IMUX44_7", - "CMT_FIFO_L_IMUX44_8", - "CMT_FIFO_L_IMUX44_9", - "CMT_FIFO_L_IMUX45_0", - "CMT_FIFO_L_IMUX45_1", - "CMT_FIFO_L_IMUX45_10", - "CMT_FIFO_L_IMUX45_11", - "CMT_FIFO_L_IMUX45_2", - "CMT_FIFO_L_IMUX45_3", - "CMT_FIFO_L_IMUX45_4", - "CMT_FIFO_L_IMUX45_5", - "CMT_FIFO_L_IMUX45_6", - "CMT_FIFO_L_IMUX45_7", - "CMT_FIFO_L_IMUX45_8", - "CMT_FIFO_L_IMUX45_9", - "CMT_FIFO_L_IMUX46_0", - "CMT_FIFO_L_IMUX46_1", - "CMT_FIFO_L_IMUX46_10", - "CMT_FIFO_L_IMUX46_11", - "CMT_FIFO_L_IMUX46_2", - "CMT_FIFO_L_IMUX46_3", - "CMT_FIFO_L_IMUX46_4", - "CMT_FIFO_L_IMUX46_5", - "CMT_FIFO_L_IMUX46_6", - "CMT_FIFO_L_IMUX46_7", - "CMT_FIFO_L_IMUX46_8", - "CMT_FIFO_L_IMUX46_9", - "CMT_FIFO_L_IMUX47_0", - "CMT_FIFO_L_IMUX47_1", - "CMT_FIFO_L_IMUX47_10", - "CMT_FIFO_L_IMUX47_11", - "CMT_FIFO_L_IMUX47_2", - "CMT_FIFO_L_IMUX47_3", - "CMT_FIFO_L_IMUX47_4", - "CMT_FIFO_L_IMUX47_5", - "CMT_FIFO_L_IMUX47_6", - "CMT_FIFO_L_IMUX47_7", - "CMT_FIFO_L_IMUX47_8", - "CMT_FIFO_L_IMUX47_9", - "CMT_FIFO_L_IMUX4_0", - "CMT_FIFO_L_IMUX4_1", - "CMT_FIFO_L_IMUX4_10", - "CMT_FIFO_L_IMUX4_11", - "CMT_FIFO_L_IMUX4_2", - "CMT_FIFO_L_IMUX4_3", - "CMT_FIFO_L_IMUX4_4", - "CMT_FIFO_L_IMUX4_5", - "CMT_FIFO_L_IMUX4_6", - "CMT_FIFO_L_IMUX4_7", - "CMT_FIFO_L_IMUX4_8", - "CMT_FIFO_L_IMUX4_9", - "CMT_FIFO_L_IMUX5_0", - "CMT_FIFO_L_IMUX5_1", - "CMT_FIFO_L_IMUX5_10", - "CMT_FIFO_L_IMUX5_11", - "CMT_FIFO_L_IMUX5_2", - "CMT_FIFO_L_IMUX5_3", - "CMT_FIFO_L_IMUX5_4", - "CMT_FIFO_L_IMUX5_5", - "CMT_FIFO_L_IMUX5_6", - "CMT_FIFO_L_IMUX5_7", - "CMT_FIFO_L_IMUX5_8", - "CMT_FIFO_L_IMUX5_9", - "CMT_FIFO_L_IMUX6_0", - "CMT_FIFO_L_IMUX6_1", - "CMT_FIFO_L_IMUX6_10", - "CMT_FIFO_L_IMUX6_11", - "CMT_FIFO_L_IMUX6_2", - "CMT_FIFO_L_IMUX6_3", - "CMT_FIFO_L_IMUX6_4", - "CMT_FIFO_L_IMUX6_5", - "CMT_FIFO_L_IMUX6_6", - "CMT_FIFO_L_IMUX6_7", - "CMT_FIFO_L_IMUX6_8", - "CMT_FIFO_L_IMUX6_9", - "CMT_FIFO_L_IMUX7_0", - "CMT_FIFO_L_IMUX7_1", - "CMT_FIFO_L_IMUX7_10", - "CMT_FIFO_L_IMUX7_11", - "CMT_FIFO_L_IMUX7_2", - "CMT_FIFO_L_IMUX7_3", - "CMT_FIFO_L_IMUX7_4", - "CMT_FIFO_L_IMUX7_5", - "CMT_FIFO_L_IMUX7_6", - "CMT_FIFO_L_IMUX7_7", - "CMT_FIFO_L_IMUX7_8", - "CMT_FIFO_L_IMUX7_9", - "CMT_FIFO_L_IMUX8_0", - "CMT_FIFO_L_IMUX8_1", - "CMT_FIFO_L_IMUX8_10", - "CMT_FIFO_L_IMUX8_11", - "CMT_FIFO_L_IMUX8_2", - "CMT_FIFO_L_IMUX8_3", - "CMT_FIFO_L_IMUX8_4", - "CMT_FIFO_L_IMUX8_5", - "CMT_FIFO_L_IMUX8_6", - "CMT_FIFO_L_IMUX8_7", - "CMT_FIFO_L_IMUX8_8", - "CMT_FIFO_L_IMUX8_9", - "CMT_FIFO_L_IMUX9_0", - "CMT_FIFO_L_IMUX9_1", - "CMT_FIFO_L_IMUX9_10", - "CMT_FIFO_L_IMUX9_11", - "CMT_FIFO_L_IMUX9_2", - "CMT_FIFO_L_IMUX9_3", - "CMT_FIFO_L_IMUX9_4", - "CMT_FIFO_L_IMUX9_5", - "CMT_FIFO_L_IMUX9_6", - "CMT_FIFO_L_IMUX9_7", - "CMT_FIFO_L_IMUX9_8", - "CMT_FIFO_L_IMUX9_9", - "CMT_FIFO_L_LOGIC_OUTS0_0", - "CMT_FIFO_L_LOGIC_OUTS0_1", - "CMT_FIFO_L_LOGIC_OUTS0_10", - "CMT_FIFO_L_LOGIC_OUTS0_11", - "CMT_FIFO_L_LOGIC_OUTS0_2", - "CMT_FIFO_L_LOGIC_OUTS0_3", - "CMT_FIFO_L_LOGIC_OUTS0_4", - "CMT_FIFO_L_LOGIC_OUTS0_5", - "CMT_FIFO_L_LOGIC_OUTS0_6", - "CMT_FIFO_L_LOGIC_OUTS0_7", - "CMT_FIFO_L_LOGIC_OUTS0_8", - "CMT_FIFO_L_LOGIC_OUTS0_9", - "CMT_FIFO_L_LOGIC_OUTS10_0", - "CMT_FIFO_L_LOGIC_OUTS10_1", - "CMT_FIFO_L_LOGIC_OUTS10_10", - "CMT_FIFO_L_LOGIC_OUTS10_11", - "CMT_FIFO_L_LOGIC_OUTS10_2", - "CMT_FIFO_L_LOGIC_OUTS10_3", - "CMT_FIFO_L_LOGIC_OUTS10_4", - "CMT_FIFO_L_LOGIC_OUTS10_5", - "CMT_FIFO_L_LOGIC_OUTS10_6", - "CMT_FIFO_L_LOGIC_OUTS10_7", - "CMT_FIFO_L_LOGIC_OUTS10_8", - "CMT_FIFO_L_LOGIC_OUTS10_9", - "CMT_FIFO_L_LOGIC_OUTS11_0", - "CMT_FIFO_L_LOGIC_OUTS11_1", - "CMT_FIFO_L_LOGIC_OUTS11_10", - "CMT_FIFO_L_LOGIC_OUTS11_11", - "CMT_FIFO_L_LOGIC_OUTS11_2", - "CMT_FIFO_L_LOGIC_OUTS11_3", - "CMT_FIFO_L_LOGIC_OUTS11_4", - "CMT_FIFO_L_LOGIC_OUTS11_5", - "CMT_FIFO_L_LOGIC_OUTS11_6", - "CMT_FIFO_L_LOGIC_OUTS11_7", - "CMT_FIFO_L_LOGIC_OUTS11_8", - "CMT_FIFO_L_LOGIC_OUTS11_9", - "CMT_FIFO_L_LOGIC_OUTS12_0", - "CMT_FIFO_L_LOGIC_OUTS12_1", - "CMT_FIFO_L_LOGIC_OUTS12_10", - "CMT_FIFO_L_LOGIC_OUTS12_11", - "CMT_FIFO_L_LOGIC_OUTS12_2", - "CMT_FIFO_L_LOGIC_OUTS12_3", - "CMT_FIFO_L_LOGIC_OUTS12_4", - "CMT_FIFO_L_LOGIC_OUTS12_5", - "CMT_FIFO_L_LOGIC_OUTS12_6", - "CMT_FIFO_L_LOGIC_OUTS12_7", - "CMT_FIFO_L_LOGIC_OUTS12_8", - "CMT_FIFO_L_LOGIC_OUTS12_9", - "CMT_FIFO_L_LOGIC_OUTS13_0", - "CMT_FIFO_L_LOGIC_OUTS13_1", - "CMT_FIFO_L_LOGIC_OUTS13_10", - "CMT_FIFO_L_LOGIC_OUTS13_11", - "CMT_FIFO_L_LOGIC_OUTS13_2", - "CMT_FIFO_L_LOGIC_OUTS13_3", - "CMT_FIFO_L_LOGIC_OUTS13_4", - "CMT_FIFO_L_LOGIC_OUTS13_5", - "CMT_FIFO_L_LOGIC_OUTS13_6", - "CMT_FIFO_L_LOGIC_OUTS13_7", - "CMT_FIFO_L_LOGIC_OUTS13_8", - "CMT_FIFO_L_LOGIC_OUTS13_9", - "CMT_FIFO_L_LOGIC_OUTS14_0", - "CMT_FIFO_L_LOGIC_OUTS14_1", - "CMT_FIFO_L_LOGIC_OUTS14_10", - "CMT_FIFO_L_LOGIC_OUTS14_11", - "CMT_FIFO_L_LOGIC_OUTS14_2", - "CMT_FIFO_L_LOGIC_OUTS14_3", - "CMT_FIFO_L_LOGIC_OUTS14_4", - "CMT_FIFO_L_LOGIC_OUTS14_5", - "CMT_FIFO_L_LOGIC_OUTS14_6", - "CMT_FIFO_L_LOGIC_OUTS14_7", - "CMT_FIFO_L_LOGIC_OUTS14_8", - "CMT_FIFO_L_LOGIC_OUTS14_9", - "CMT_FIFO_L_LOGIC_OUTS15_0", - "CMT_FIFO_L_LOGIC_OUTS15_1", - "CMT_FIFO_L_LOGIC_OUTS15_10", - "CMT_FIFO_L_LOGIC_OUTS15_11", - "CMT_FIFO_L_LOGIC_OUTS15_2", - "CMT_FIFO_L_LOGIC_OUTS15_3", - "CMT_FIFO_L_LOGIC_OUTS15_4", - "CMT_FIFO_L_LOGIC_OUTS15_5", - "CMT_FIFO_L_LOGIC_OUTS15_6", - "CMT_FIFO_L_LOGIC_OUTS15_7", - "CMT_FIFO_L_LOGIC_OUTS15_8", - "CMT_FIFO_L_LOGIC_OUTS15_9", - "CMT_FIFO_L_LOGIC_OUTS16_0", - "CMT_FIFO_L_LOGIC_OUTS16_1", - "CMT_FIFO_L_LOGIC_OUTS16_10", - "CMT_FIFO_L_LOGIC_OUTS16_11", - "CMT_FIFO_L_LOGIC_OUTS16_2", - "CMT_FIFO_L_LOGIC_OUTS16_3", - "CMT_FIFO_L_LOGIC_OUTS16_4", - "CMT_FIFO_L_LOGIC_OUTS16_5", - "CMT_FIFO_L_LOGIC_OUTS16_6", - "CMT_FIFO_L_LOGIC_OUTS16_7", - "CMT_FIFO_L_LOGIC_OUTS16_8", - "CMT_FIFO_L_LOGIC_OUTS16_9", - "CMT_FIFO_L_LOGIC_OUTS17_0", - "CMT_FIFO_L_LOGIC_OUTS17_1", - "CMT_FIFO_L_LOGIC_OUTS17_10", - "CMT_FIFO_L_LOGIC_OUTS17_11", - "CMT_FIFO_L_LOGIC_OUTS17_2", - "CMT_FIFO_L_LOGIC_OUTS17_3", - "CMT_FIFO_L_LOGIC_OUTS17_4", - "CMT_FIFO_L_LOGIC_OUTS17_5", - "CMT_FIFO_L_LOGIC_OUTS17_6", - "CMT_FIFO_L_LOGIC_OUTS17_7", - "CMT_FIFO_L_LOGIC_OUTS17_8", - "CMT_FIFO_L_LOGIC_OUTS17_9", - "CMT_FIFO_L_LOGIC_OUTS18_0", - "CMT_FIFO_L_LOGIC_OUTS18_1", - "CMT_FIFO_L_LOGIC_OUTS18_10", - "CMT_FIFO_L_LOGIC_OUTS18_11", - "CMT_FIFO_L_LOGIC_OUTS18_2", - "CMT_FIFO_L_LOGIC_OUTS18_3", - "CMT_FIFO_L_LOGIC_OUTS18_4", - "CMT_FIFO_L_LOGIC_OUTS18_5", - "CMT_FIFO_L_LOGIC_OUTS18_6", - "CMT_FIFO_L_LOGIC_OUTS18_7", - "CMT_FIFO_L_LOGIC_OUTS18_8", - "CMT_FIFO_L_LOGIC_OUTS18_9", - "CMT_FIFO_L_LOGIC_OUTS19_0", - "CMT_FIFO_L_LOGIC_OUTS19_1", - "CMT_FIFO_L_LOGIC_OUTS19_10", - "CMT_FIFO_L_LOGIC_OUTS19_11", - "CMT_FIFO_L_LOGIC_OUTS19_2", - "CMT_FIFO_L_LOGIC_OUTS19_3", - "CMT_FIFO_L_LOGIC_OUTS19_4", - "CMT_FIFO_L_LOGIC_OUTS19_5", - "CMT_FIFO_L_LOGIC_OUTS19_6", - "CMT_FIFO_L_LOGIC_OUTS19_7", - "CMT_FIFO_L_LOGIC_OUTS19_8", - "CMT_FIFO_L_LOGIC_OUTS19_9", - "CMT_FIFO_L_LOGIC_OUTS1_0", - "CMT_FIFO_L_LOGIC_OUTS1_1", - "CMT_FIFO_L_LOGIC_OUTS1_10", - "CMT_FIFO_L_LOGIC_OUTS1_11", - "CMT_FIFO_L_LOGIC_OUTS1_2", - "CMT_FIFO_L_LOGIC_OUTS1_3", - "CMT_FIFO_L_LOGIC_OUTS1_4", - "CMT_FIFO_L_LOGIC_OUTS1_5", - "CMT_FIFO_L_LOGIC_OUTS1_6", - "CMT_FIFO_L_LOGIC_OUTS1_7", - "CMT_FIFO_L_LOGIC_OUTS1_8", - "CMT_FIFO_L_LOGIC_OUTS1_9", - "CMT_FIFO_L_LOGIC_OUTS20_0", - "CMT_FIFO_L_LOGIC_OUTS20_1", - "CMT_FIFO_L_LOGIC_OUTS20_10", - "CMT_FIFO_L_LOGIC_OUTS20_11", - "CMT_FIFO_L_LOGIC_OUTS20_2", - "CMT_FIFO_L_LOGIC_OUTS20_3", - "CMT_FIFO_L_LOGIC_OUTS20_4", - "CMT_FIFO_L_LOGIC_OUTS20_5", - "CMT_FIFO_L_LOGIC_OUTS20_6", - "CMT_FIFO_L_LOGIC_OUTS20_7", - "CMT_FIFO_L_LOGIC_OUTS20_8", - "CMT_FIFO_L_LOGIC_OUTS20_9", - "CMT_FIFO_L_LOGIC_OUTS21_0", - "CMT_FIFO_L_LOGIC_OUTS21_1", - "CMT_FIFO_L_LOGIC_OUTS21_10", - "CMT_FIFO_L_LOGIC_OUTS21_11", - "CMT_FIFO_L_LOGIC_OUTS21_2", - "CMT_FIFO_L_LOGIC_OUTS21_3", - "CMT_FIFO_L_LOGIC_OUTS21_4", - "CMT_FIFO_L_LOGIC_OUTS21_5", - "CMT_FIFO_L_LOGIC_OUTS21_6", - "CMT_FIFO_L_LOGIC_OUTS21_7", - "CMT_FIFO_L_LOGIC_OUTS21_8", - "CMT_FIFO_L_LOGIC_OUTS21_9", - "CMT_FIFO_L_LOGIC_OUTS22_0", - "CMT_FIFO_L_LOGIC_OUTS22_1", - "CMT_FIFO_L_LOGIC_OUTS22_10", - "CMT_FIFO_L_LOGIC_OUTS22_11", - "CMT_FIFO_L_LOGIC_OUTS22_2", - "CMT_FIFO_L_LOGIC_OUTS22_3", - "CMT_FIFO_L_LOGIC_OUTS22_4", - "CMT_FIFO_L_LOGIC_OUTS22_5", - "CMT_FIFO_L_LOGIC_OUTS22_6", - "CMT_FIFO_L_LOGIC_OUTS22_7", - "CMT_FIFO_L_LOGIC_OUTS22_8", - "CMT_FIFO_L_LOGIC_OUTS22_9", - "CMT_FIFO_L_LOGIC_OUTS23_0", - "CMT_FIFO_L_LOGIC_OUTS23_1", - "CMT_FIFO_L_LOGIC_OUTS23_10", - "CMT_FIFO_L_LOGIC_OUTS23_11", - "CMT_FIFO_L_LOGIC_OUTS23_2", - "CMT_FIFO_L_LOGIC_OUTS23_3", - "CMT_FIFO_L_LOGIC_OUTS23_4", - "CMT_FIFO_L_LOGIC_OUTS23_5", - "CMT_FIFO_L_LOGIC_OUTS23_6", - "CMT_FIFO_L_LOGIC_OUTS23_7", - "CMT_FIFO_L_LOGIC_OUTS23_8", - "CMT_FIFO_L_LOGIC_OUTS23_9", - "CMT_FIFO_L_LOGIC_OUTS2_0", - "CMT_FIFO_L_LOGIC_OUTS2_1", - "CMT_FIFO_L_LOGIC_OUTS2_10", - "CMT_FIFO_L_LOGIC_OUTS2_11", - "CMT_FIFO_L_LOGIC_OUTS2_2", - "CMT_FIFO_L_LOGIC_OUTS2_3", - "CMT_FIFO_L_LOGIC_OUTS2_4", - "CMT_FIFO_L_LOGIC_OUTS2_5", - "CMT_FIFO_L_LOGIC_OUTS2_6", - "CMT_FIFO_L_LOGIC_OUTS2_7", - "CMT_FIFO_L_LOGIC_OUTS2_8", - "CMT_FIFO_L_LOGIC_OUTS2_9", - "CMT_FIFO_L_LOGIC_OUTS3_0", - "CMT_FIFO_L_LOGIC_OUTS3_1", - "CMT_FIFO_L_LOGIC_OUTS3_10", - "CMT_FIFO_L_LOGIC_OUTS3_11", - "CMT_FIFO_L_LOGIC_OUTS3_2", - "CMT_FIFO_L_LOGIC_OUTS3_3", - "CMT_FIFO_L_LOGIC_OUTS3_4", - "CMT_FIFO_L_LOGIC_OUTS3_5", - "CMT_FIFO_L_LOGIC_OUTS3_6", - "CMT_FIFO_L_LOGIC_OUTS3_7", - "CMT_FIFO_L_LOGIC_OUTS3_8", - "CMT_FIFO_L_LOGIC_OUTS3_9", - "CMT_FIFO_L_LOGIC_OUTS4_0", - "CMT_FIFO_L_LOGIC_OUTS4_1", - "CMT_FIFO_L_LOGIC_OUTS4_10", - "CMT_FIFO_L_LOGIC_OUTS4_11", - "CMT_FIFO_L_LOGIC_OUTS4_2", - "CMT_FIFO_L_LOGIC_OUTS4_3", - "CMT_FIFO_L_LOGIC_OUTS4_4", - "CMT_FIFO_L_LOGIC_OUTS4_5", - "CMT_FIFO_L_LOGIC_OUTS4_6", - "CMT_FIFO_L_LOGIC_OUTS4_7", - "CMT_FIFO_L_LOGIC_OUTS4_8", - "CMT_FIFO_L_LOGIC_OUTS4_9", - "CMT_FIFO_L_LOGIC_OUTS5_0", - "CMT_FIFO_L_LOGIC_OUTS5_1", - "CMT_FIFO_L_LOGIC_OUTS5_10", - "CMT_FIFO_L_LOGIC_OUTS5_11", - "CMT_FIFO_L_LOGIC_OUTS5_2", - "CMT_FIFO_L_LOGIC_OUTS5_3", - "CMT_FIFO_L_LOGIC_OUTS5_4", - "CMT_FIFO_L_LOGIC_OUTS5_5", - "CMT_FIFO_L_LOGIC_OUTS5_6", - "CMT_FIFO_L_LOGIC_OUTS5_7", - "CMT_FIFO_L_LOGIC_OUTS5_8", - "CMT_FIFO_L_LOGIC_OUTS5_9", - "CMT_FIFO_L_LOGIC_OUTS6_0", - "CMT_FIFO_L_LOGIC_OUTS6_1", - "CMT_FIFO_L_LOGIC_OUTS6_10", - "CMT_FIFO_L_LOGIC_OUTS6_11", - "CMT_FIFO_L_LOGIC_OUTS6_2", - "CMT_FIFO_L_LOGIC_OUTS6_3", - "CMT_FIFO_L_LOGIC_OUTS6_4", - "CMT_FIFO_L_LOGIC_OUTS6_5", - "CMT_FIFO_L_LOGIC_OUTS6_6", - "CMT_FIFO_L_LOGIC_OUTS6_7", - "CMT_FIFO_L_LOGIC_OUTS6_8", - "CMT_FIFO_L_LOGIC_OUTS6_9", - "CMT_FIFO_L_LOGIC_OUTS7_0", - "CMT_FIFO_L_LOGIC_OUTS7_1", - "CMT_FIFO_L_LOGIC_OUTS7_10", - "CMT_FIFO_L_LOGIC_OUTS7_11", - "CMT_FIFO_L_LOGIC_OUTS7_2", - "CMT_FIFO_L_LOGIC_OUTS7_3", - "CMT_FIFO_L_LOGIC_OUTS7_4", - "CMT_FIFO_L_LOGIC_OUTS7_5", - "CMT_FIFO_L_LOGIC_OUTS7_6", - "CMT_FIFO_L_LOGIC_OUTS7_7", - "CMT_FIFO_L_LOGIC_OUTS7_8", - "CMT_FIFO_L_LOGIC_OUTS7_9", - "CMT_FIFO_L_LOGIC_OUTS8_0", - "CMT_FIFO_L_LOGIC_OUTS8_1", - "CMT_FIFO_L_LOGIC_OUTS8_10", - "CMT_FIFO_L_LOGIC_OUTS8_11", - "CMT_FIFO_L_LOGIC_OUTS8_2", - "CMT_FIFO_L_LOGIC_OUTS8_3", - "CMT_FIFO_L_LOGIC_OUTS8_4", - "CMT_FIFO_L_LOGIC_OUTS8_5", - "CMT_FIFO_L_LOGIC_OUTS8_6", - "CMT_FIFO_L_LOGIC_OUTS8_7", - "CMT_FIFO_L_LOGIC_OUTS8_8", - "CMT_FIFO_L_LOGIC_OUTS8_9", - "CMT_FIFO_L_LOGIC_OUTS9_0", - "CMT_FIFO_L_LOGIC_OUTS9_1", - "CMT_FIFO_L_LOGIC_OUTS9_10", - "CMT_FIFO_L_LOGIC_OUTS9_11", - "CMT_FIFO_L_LOGIC_OUTS9_2", - "CMT_FIFO_L_LOGIC_OUTS9_3", - "CMT_FIFO_L_LOGIC_OUTS9_4", - "CMT_FIFO_L_LOGIC_OUTS9_5", - "CMT_FIFO_L_LOGIC_OUTS9_6", - "CMT_FIFO_L_LOGIC_OUTS9_7", - "CMT_FIFO_L_LOGIC_OUTS9_8", - "CMT_FIFO_L_LOGIC_OUTS9_9", - "CMT_FIFO_L_PHASER_RDCLK", - "CMT_FIFO_L_PHASER_RDENABLE", - "CMT_FIFO_L_PHASER_WRCLK", - "CMT_FIFO_L_PHASER_WRENABLE", - "CMT_FIFO_MONITOR_N_0", - "CMT_FIFO_MONITOR_N_1", - "CMT_FIFO_MONITOR_N_10", - "CMT_FIFO_MONITOR_N_11", - "CMT_FIFO_MONITOR_N_2", - "CMT_FIFO_MONITOR_N_3", - "CMT_FIFO_MONITOR_N_4", - "CMT_FIFO_MONITOR_N_5", - "CMT_FIFO_MONITOR_N_6", - "CMT_FIFO_MONITOR_N_7", - "CMT_FIFO_MONITOR_N_8", - "CMT_FIFO_MONITOR_N_9", - "CMT_FIFO_MONITOR_P_0", - "CMT_FIFO_MONITOR_P_1", - "CMT_FIFO_MONITOR_P_10", - "CMT_FIFO_MONITOR_P_11", - "CMT_FIFO_MONITOR_P_2", - "CMT_FIFO_MONITOR_P_3", - "CMT_FIFO_MONITOR_P_4", - "CMT_FIFO_MONITOR_P_5", - "CMT_FIFO_MONITOR_P_6", - "CMT_FIFO_MONITOR_P_7", - "CMT_FIFO_MONITOR_P_8", - "CMT_FIFO_MONITOR_P_9", - "CMT_FIFO_NE2A0_0", - "CMT_FIFO_NE2A0_1", - "CMT_FIFO_NE2A0_10", - "CMT_FIFO_NE2A0_11", - "CMT_FIFO_NE2A0_2", - "CMT_FIFO_NE2A0_3", - "CMT_FIFO_NE2A0_4", - "CMT_FIFO_NE2A0_5", - "CMT_FIFO_NE2A0_6", - "CMT_FIFO_NE2A0_7", - "CMT_FIFO_NE2A0_8", - "CMT_FIFO_NE2A0_9", - "CMT_FIFO_NE2A1_0", - "CMT_FIFO_NE2A1_1", - "CMT_FIFO_NE2A1_10", - "CMT_FIFO_NE2A1_11", - "CMT_FIFO_NE2A1_2", - "CMT_FIFO_NE2A1_3", - "CMT_FIFO_NE2A1_4", - "CMT_FIFO_NE2A1_5", - "CMT_FIFO_NE2A1_6", - "CMT_FIFO_NE2A1_7", - "CMT_FIFO_NE2A1_8", - "CMT_FIFO_NE2A1_9", - "CMT_FIFO_NE2A2_0", - "CMT_FIFO_NE2A2_1", - "CMT_FIFO_NE2A2_10", - "CMT_FIFO_NE2A2_11", - "CMT_FIFO_NE2A2_2", - "CMT_FIFO_NE2A2_3", - "CMT_FIFO_NE2A2_4", - "CMT_FIFO_NE2A2_5", - "CMT_FIFO_NE2A2_6", - "CMT_FIFO_NE2A2_7", - "CMT_FIFO_NE2A2_8", - "CMT_FIFO_NE2A2_9", - "CMT_FIFO_NE2A3_0", - "CMT_FIFO_NE2A3_1", - "CMT_FIFO_NE2A3_10", - "CMT_FIFO_NE2A3_11", - "CMT_FIFO_NE2A3_2", - "CMT_FIFO_NE2A3_3", - "CMT_FIFO_NE2A3_4", - "CMT_FIFO_NE2A3_5", - "CMT_FIFO_NE2A3_6", - "CMT_FIFO_NE2A3_7", - "CMT_FIFO_NE2A3_8", - "CMT_FIFO_NE2A3_9", - "CMT_FIFO_NE4BEG0_0", - "CMT_FIFO_NE4BEG0_1", - "CMT_FIFO_NE4BEG0_10", - "CMT_FIFO_NE4BEG0_11", - "CMT_FIFO_NE4BEG0_2", - "CMT_FIFO_NE4BEG0_3", - "CMT_FIFO_NE4BEG0_4", - "CMT_FIFO_NE4BEG0_5", - "CMT_FIFO_NE4BEG0_6", - "CMT_FIFO_NE4BEG0_7", - "CMT_FIFO_NE4BEG0_8", - "CMT_FIFO_NE4BEG0_9", - "CMT_FIFO_NE4BEG1_0", - "CMT_FIFO_NE4BEG1_1", - "CMT_FIFO_NE4BEG1_10", - "CMT_FIFO_NE4BEG1_11", - "CMT_FIFO_NE4BEG1_2", - "CMT_FIFO_NE4BEG1_3", - "CMT_FIFO_NE4BEG1_4", - "CMT_FIFO_NE4BEG1_5", - "CMT_FIFO_NE4BEG1_6", - "CMT_FIFO_NE4BEG1_7", - "CMT_FIFO_NE4BEG1_8", - "CMT_FIFO_NE4BEG1_9", - "CMT_FIFO_NE4BEG2_0", - "CMT_FIFO_NE4BEG2_1", - "CMT_FIFO_NE4BEG2_10", - "CMT_FIFO_NE4BEG2_11", - "CMT_FIFO_NE4BEG2_2", - "CMT_FIFO_NE4BEG2_3", - "CMT_FIFO_NE4BEG2_4", - "CMT_FIFO_NE4BEG2_5", - "CMT_FIFO_NE4BEG2_6", - "CMT_FIFO_NE4BEG2_7", - "CMT_FIFO_NE4BEG2_8", - "CMT_FIFO_NE4BEG2_9", - "CMT_FIFO_NE4BEG3_0", - "CMT_FIFO_NE4BEG3_1", - "CMT_FIFO_NE4BEG3_10", - "CMT_FIFO_NE4BEG3_11", - "CMT_FIFO_NE4BEG3_2", - "CMT_FIFO_NE4BEG3_3", - "CMT_FIFO_NE4BEG3_4", - "CMT_FIFO_NE4BEG3_5", - "CMT_FIFO_NE4BEG3_6", - "CMT_FIFO_NE4BEG3_7", - "CMT_FIFO_NE4BEG3_8", - "CMT_FIFO_NE4BEG3_9", - "CMT_FIFO_NE4C0_0", - "CMT_FIFO_NE4C0_1", - "CMT_FIFO_NE4C0_10", - "CMT_FIFO_NE4C0_11", - "CMT_FIFO_NE4C0_2", - "CMT_FIFO_NE4C0_3", - "CMT_FIFO_NE4C0_4", - "CMT_FIFO_NE4C0_5", - "CMT_FIFO_NE4C0_6", - "CMT_FIFO_NE4C0_7", - "CMT_FIFO_NE4C0_8", - "CMT_FIFO_NE4C0_9", - "CMT_FIFO_NE4C1_0", - "CMT_FIFO_NE4C1_1", - "CMT_FIFO_NE4C1_10", - "CMT_FIFO_NE4C1_11", - "CMT_FIFO_NE4C1_2", - "CMT_FIFO_NE4C1_3", - "CMT_FIFO_NE4C1_4", - "CMT_FIFO_NE4C1_5", - "CMT_FIFO_NE4C1_6", - "CMT_FIFO_NE4C1_7", - "CMT_FIFO_NE4C1_8", - "CMT_FIFO_NE4C1_9", - "CMT_FIFO_NE4C2_0", - "CMT_FIFO_NE4C2_1", - "CMT_FIFO_NE4C2_10", - "CMT_FIFO_NE4C2_11", - "CMT_FIFO_NE4C2_2", - "CMT_FIFO_NE4C2_3", - "CMT_FIFO_NE4C2_4", - "CMT_FIFO_NE4C2_5", - "CMT_FIFO_NE4C2_6", - "CMT_FIFO_NE4C2_7", - "CMT_FIFO_NE4C2_8", - "CMT_FIFO_NE4C2_9", - "CMT_FIFO_NE4C3_0", - "CMT_FIFO_NE4C3_1", - "CMT_FIFO_NE4C3_10", - "CMT_FIFO_NE4C3_11", - "CMT_FIFO_NE4C3_2", - "CMT_FIFO_NE4C3_3", - "CMT_FIFO_NE4C3_4", - "CMT_FIFO_NE4C3_5", - "CMT_FIFO_NE4C3_6", - "CMT_FIFO_NE4C3_7", - "CMT_FIFO_NE4C3_8", - "CMT_FIFO_NE4C3_9", - "CMT_FIFO_NW2A0_0", - "CMT_FIFO_NW2A0_1", - "CMT_FIFO_NW2A0_10", - "CMT_FIFO_NW2A0_11", - "CMT_FIFO_NW2A0_2", - "CMT_FIFO_NW2A0_3", - "CMT_FIFO_NW2A0_4", - "CMT_FIFO_NW2A0_5", - "CMT_FIFO_NW2A0_6", - "CMT_FIFO_NW2A0_7", - "CMT_FIFO_NW2A0_8", - "CMT_FIFO_NW2A0_9", - "CMT_FIFO_NW2A1_0", - "CMT_FIFO_NW2A1_1", - "CMT_FIFO_NW2A1_10", - "CMT_FIFO_NW2A1_11", - "CMT_FIFO_NW2A1_2", - "CMT_FIFO_NW2A1_3", - "CMT_FIFO_NW2A1_4", - "CMT_FIFO_NW2A1_5", - "CMT_FIFO_NW2A1_6", - "CMT_FIFO_NW2A1_7", - "CMT_FIFO_NW2A1_8", - "CMT_FIFO_NW2A1_9", - "CMT_FIFO_NW2A2_0", - "CMT_FIFO_NW2A2_1", - "CMT_FIFO_NW2A2_10", - "CMT_FIFO_NW2A2_11", - "CMT_FIFO_NW2A2_2", - "CMT_FIFO_NW2A2_3", - "CMT_FIFO_NW2A2_4", - "CMT_FIFO_NW2A2_5", - "CMT_FIFO_NW2A2_6", - "CMT_FIFO_NW2A2_7", - "CMT_FIFO_NW2A2_8", - "CMT_FIFO_NW2A2_9", - "CMT_FIFO_NW2A3_0", - "CMT_FIFO_NW2A3_1", - "CMT_FIFO_NW2A3_10", - "CMT_FIFO_NW2A3_11", - "CMT_FIFO_NW2A3_2", - "CMT_FIFO_NW2A3_3", - "CMT_FIFO_NW2A3_4", - "CMT_FIFO_NW2A3_5", - "CMT_FIFO_NW2A3_6", - "CMT_FIFO_NW2A3_7", - "CMT_FIFO_NW2A3_8", - "CMT_FIFO_NW2A3_9", - "CMT_FIFO_NW4A0_0", - "CMT_FIFO_NW4A0_1", - "CMT_FIFO_NW4A0_10", - "CMT_FIFO_NW4A0_11", - "CMT_FIFO_NW4A0_2", - "CMT_FIFO_NW4A0_3", - "CMT_FIFO_NW4A0_4", - "CMT_FIFO_NW4A0_5", - "CMT_FIFO_NW4A0_6", - "CMT_FIFO_NW4A0_7", - "CMT_FIFO_NW4A0_8", - "CMT_FIFO_NW4A0_9", - "CMT_FIFO_NW4A1_0", - "CMT_FIFO_NW4A1_1", - "CMT_FIFO_NW4A1_10", - "CMT_FIFO_NW4A1_11", - "CMT_FIFO_NW4A1_2", - "CMT_FIFO_NW4A1_3", - "CMT_FIFO_NW4A1_4", - "CMT_FIFO_NW4A1_5", - "CMT_FIFO_NW4A1_6", - "CMT_FIFO_NW4A1_7", - "CMT_FIFO_NW4A1_8", - "CMT_FIFO_NW4A1_9", - "CMT_FIFO_NW4A2_0", - "CMT_FIFO_NW4A2_1", - "CMT_FIFO_NW4A2_10", - "CMT_FIFO_NW4A2_11", - "CMT_FIFO_NW4A2_2", - "CMT_FIFO_NW4A2_3", - "CMT_FIFO_NW4A2_4", - "CMT_FIFO_NW4A2_5", - "CMT_FIFO_NW4A2_6", - "CMT_FIFO_NW4A2_7", - "CMT_FIFO_NW4A2_8", - "CMT_FIFO_NW4A2_9", - "CMT_FIFO_NW4A3_0", - "CMT_FIFO_NW4A3_1", - "CMT_FIFO_NW4A3_10", - "CMT_FIFO_NW4A3_11", - "CMT_FIFO_NW4A3_2", - "CMT_FIFO_NW4A3_3", - "CMT_FIFO_NW4A3_4", - "CMT_FIFO_NW4A3_5", - "CMT_FIFO_NW4A3_6", - "CMT_FIFO_NW4A3_7", - "CMT_FIFO_NW4A3_8", - "CMT_FIFO_NW4A3_9", - "CMT_FIFO_NW4END0_0", - "CMT_FIFO_NW4END0_1", - "CMT_FIFO_NW4END0_10", - "CMT_FIFO_NW4END0_11", - "CMT_FIFO_NW4END0_2", - "CMT_FIFO_NW4END0_3", - "CMT_FIFO_NW4END0_4", - "CMT_FIFO_NW4END0_5", - "CMT_FIFO_NW4END0_6", - "CMT_FIFO_NW4END0_7", - "CMT_FIFO_NW4END0_8", - "CMT_FIFO_NW4END0_9", - "CMT_FIFO_NW4END1_0", - "CMT_FIFO_NW4END1_1", - "CMT_FIFO_NW4END1_10", - "CMT_FIFO_NW4END1_11", - "CMT_FIFO_NW4END1_2", - "CMT_FIFO_NW4END1_3", - "CMT_FIFO_NW4END1_4", - "CMT_FIFO_NW4END1_5", - "CMT_FIFO_NW4END1_6", - "CMT_FIFO_NW4END1_7", - "CMT_FIFO_NW4END1_8", - "CMT_FIFO_NW4END1_9", - "CMT_FIFO_NW4END2_0", - "CMT_FIFO_NW4END2_1", - "CMT_FIFO_NW4END2_10", - "CMT_FIFO_NW4END2_11", - "CMT_FIFO_NW4END2_2", - "CMT_FIFO_NW4END2_3", - "CMT_FIFO_NW4END2_4", - "CMT_FIFO_NW4END2_5", - "CMT_FIFO_NW4END2_6", - "CMT_FIFO_NW4END2_7", - "CMT_FIFO_NW4END2_8", - "CMT_FIFO_NW4END2_9", - "CMT_FIFO_NW4END3_0", - "CMT_FIFO_NW4END3_1", - "CMT_FIFO_NW4END3_10", - "CMT_FIFO_NW4END3_11", - "CMT_FIFO_NW4END3_2", - "CMT_FIFO_NW4END3_3", - "CMT_FIFO_NW4END3_4", - "CMT_FIFO_NW4END3_5", - "CMT_FIFO_NW4END3_6", - "CMT_FIFO_NW4END3_7", - "CMT_FIFO_NW4END3_8", - "CMT_FIFO_NW4END3_9", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", - "CMT_FIFO_PHASER_TO_IO_ICLK_0", - "CMT_FIFO_PHASER_TO_IO_ICLK_1", - "CMT_FIFO_PHASER_TO_IO_ICLK_10", - "CMT_FIFO_PHASER_TO_IO_ICLK_11", - "CMT_FIFO_PHASER_TO_IO_ICLK_2", - "CMT_FIFO_PHASER_TO_IO_ICLK_3", - "CMT_FIFO_PHASER_TO_IO_ICLK_4", - "CMT_FIFO_PHASER_TO_IO_ICLK_5", - "CMT_FIFO_PHASER_TO_IO_ICLK_6", - "CMT_FIFO_PHASER_TO_IO_ICLK_7", - "CMT_FIFO_PHASER_TO_IO_ICLK_8", - "CMT_FIFO_PHASER_TO_IO_ICLK_9", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_0", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_1", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_10", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_11", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_2", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_3", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_5", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_6", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_8", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_9", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", - "CMT_FIFO_SE2A0_0", - "CMT_FIFO_SE2A0_1", - "CMT_FIFO_SE2A0_10", - "CMT_FIFO_SE2A0_11", - "CMT_FIFO_SE2A0_2", - "CMT_FIFO_SE2A0_3", - "CMT_FIFO_SE2A0_4", - "CMT_FIFO_SE2A0_5", - "CMT_FIFO_SE2A0_6", - "CMT_FIFO_SE2A0_7", - "CMT_FIFO_SE2A0_8", - "CMT_FIFO_SE2A0_9", - "CMT_FIFO_SE2A1_0", - "CMT_FIFO_SE2A1_1", - "CMT_FIFO_SE2A1_10", - "CMT_FIFO_SE2A1_11", - "CMT_FIFO_SE2A1_2", - "CMT_FIFO_SE2A1_3", - "CMT_FIFO_SE2A1_4", - "CMT_FIFO_SE2A1_5", - "CMT_FIFO_SE2A1_6", - "CMT_FIFO_SE2A1_7", - "CMT_FIFO_SE2A1_8", - "CMT_FIFO_SE2A1_9", - "CMT_FIFO_SE2A2_0", - "CMT_FIFO_SE2A2_1", - "CMT_FIFO_SE2A2_10", - "CMT_FIFO_SE2A2_11", - "CMT_FIFO_SE2A2_2", - "CMT_FIFO_SE2A2_3", - "CMT_FIFO_SE2A2_4", - "CMT_FIFO_SE2A2_5", - "CMT_FIFO_SE2A2_6", - "CMT_FIFO_SE2A2_7", - "CMT_FIFO_SE2A2_8", - "CMT_FIFO_SE2A2_9", - "CMT_FIFO_SE2A3_0", - "CMT_FIFO_SE2A3_1", - "CMT_FIFO_SE2A3_10", - "CMT_FIFO_SE2A3_11", - "CMT_FIFO_SE2A3_2", - "CMT_FIFO_SE2A3_3", - "CMT_FIFO_SE2A3_4", - "CMT_FIFO_SE2A3_5", - "CMT_FIFO_SE2A3_6", - "CMT_FIFO_SE2A3_7", - "CMT_FIFO_SE2A3_8", - "CMT_FIFO_SE2A3_9", - "CMT_FIFO_SE4BEG0_0", - "CMT_FIFO_SE4BEG0_1", - "CMT_FIFO_SE4BEG0_10", - "CMT_FIFO_SE4BEG0_11", - "CMT_FIFO_SE4BEG0_2", - "CMT_FIFO_SE4BEG0_3", - "CMT_FIFO_SE4BEG0_4", - "CMT_FIFO_SE4BEG0_5", - "CMT_FIFO_SE4BEG0_6", - "CMT_FIFO_SE4BEG0_7", - "CMT_FIFO_SE4BEG0_8", - "CMT_FIFO_SE4BEG0_9", - "CMT_FIFO_SE4BEG1_0", - "CMT_FIFO_SE4BEG1_1", - "CMT_FIFO_SE4BEG1_10", - "CMT_FIFO_SE4BEG1_11", - "CMT_FIFO_SE4BEG1_2", - "CMT_FIFO_SE4BEG1_3", - "CMT_FIFO_SE4BEG1_4", - "CMT_FIFO_SE4BEG1_5", - "CMT_FIFO_SE4BEG1_6", - "CMT_FIFO_SE4BEG1_7", - "CMT_FIFO_SE4BEG1_8", - "CMT_FIFO_SE4BEG1_9", - "CMT_FIFO_SE4BEG2_0", - "CMT_FIFO_SE4BEG2_1", - "CMT_FIFO_SE4BEG2_10", - "CMT_FIFO_SE4BEG2_11", - "CMT_FIFO_SE4BEG2_2", - "CMT_FIFO_SE4BEG2_3", - "CMT_FIFO_SE4BEG2_4", - "CMT_FIFO_SE4BEG2_5", - "CMT_FIFO_SE4BEG2_6", - "CMT_FIFO_SE4BEG2_7", - "CMT_FIFO_SE4BEG2_8", - "CMT_FIFO_SE4BEG2_9", - "CMT_FIFO_SE4BEG3_0", - "CMT_FIFO_SE4BEG3_1", - "CMT_FIFO_SE4BEG3_10", - "CMT_FIFO_SE4BEG3_11", - "CMT_FIFO_SE4BEG3_2", - "CMT_FIFO_SE4BEG3_3", - "CMT_FIFO_SE4BEG3_4", - "CMT_FIFO_SE4BEG3_5", - "CMT_FIFO_SE4BEG3_6", - "CMT_FIFO_SE4BEG3_7", - "CMT_FIFO_SE4BEG3_8", - "CMT_FIFO_SE4BEG3_9", - "CMT_FIFO_SE4C0_0", - "CMT_FIFO_SE4C0_1", - "CMT_FIFO_SE4C0_10", - "CMT_FIFO_SE4C0_11", - "CMT_FIFO_SE4C0_2", - "CMT_FIFO_SE4C0_3", - "CMT_FIFO_SE4C0_4", - "CMT_FIFO_SE4C0_5", - "CMT_FIFO_SE4C0_6", - "CMT_FIFO_SE4C0_7", - "CMT_FIFO_SE4C0_8", - "CMT_FIFO_SE4C0_9", - "CMT_FIFO_SE4C1_0", - "CMT_FIFO_SE4C1_1", - "CMT_FIFO_SE4C1_10", - "CMT_FIFO_SE4C1_11", - "CMT_FIFO_SE4C1_2", - "CMT_FIFO_SE4C1_3", - "CMT_FIFO_SE4C1_4", - "CMT_FIFO_SE4C1_5", - "CMT_FIFO_SE4C1_6", - "CMT_FIFO_SE4C1_7", - "CMT_FIFO_SE4C1_8", - "CMT_FIFO_SE4C1_9", - "CMT_FIFO_SE4C2_0", - "CMT_FIFO_SE4C2_1", - "CMT_FIFO_SE4C2_10", - "CMT_FIFO_SE4C2_11", - "CMT_FIFO_SE4C2_2", - "CMT_FIFO_SE4C2_3", - "CMT_FIFO_SE4C2_4", - "CMT_FIFO_SE4C2_5", - "CMT_FIFO_SE4C2_6", - "CMT_FIFO_SE4C2_7", - "CMT_FIFO_SE4C2_8", - "CMT_FIFO_SE4C2_9", - "CMT_FIFO_SE4C3_0", - "CMT_FIFO_SE4C3_1", - "CMT_FIFO_SE4C3_10", - "CMT_FIFO_SE4C3_11", - "CMT_FIFO_SE4C3_2", - "CMT_FIFO_SE4C3_3", - "CMT_FIFO_SE4C3_4", - "CMT_FIFO_SE4C3_5", - "CMT_FIFO_SE4C3_6", - "CMT_FIFO_SE4C3_7", - "CMT_FIFO_SE4C3_8", - "CMT_FIFO_SE4C3_9", - "CMT_FIFO_SW2A0_0", - "CMT_FIFO_SW2A0_1", - "CMT_FIFO_SW2A0_10", - "CMT_FIFO_SW2A0_11", - "CMT_FIFO_SW2A0_2", - "CMT_FIFO_SW2A0_3", - "CMT_FIFO_SW2A0_4", - "CMT_FIFO_SW2A0_5", - "CMT_FIFO_SW2A0_6", - "CMT_FIFO_SW2A0_7", - "CMT_FIFO_SW2A0_8", - "CMT_FIFO_SW2A0_9", - "CMT_FIFO_SW2A1_0", - "CMT_FIFO_SW2A1_1", - "CMT_FIFO_SW2A1_10", - "CMT_FIFO_SW2A1_11", - "CMT_FIFO_SW2A1_2", - "CMT_FIFO_SW2A1_3", - "CMT_FIFO_SW2A1_4", - "CMT_FIFO_SW2A1_5", - "CMT_FIFO_SW2A1_6", - "CMT_FIFO_SW2A1_7", - "CMT_FIFO_SW2A1_8", - "CMT_FIFO_SW2A1_9", - "CMT_FIFO_SW2A2_0", - "CMT_FIFO_SW2A2_1", - "CMT_FIFO_SW2A2_10", - "CMT_FIFO_SW2A2_11", - "CMT_FIFO_SW2A2_2", - "CMT_FIFO_SW2A2_3", - "CMT_FIFO_SW2A2_4", - "CMT_FIFO_SW2A2_5", - "CMT_FIFO_SW2A2_6", - "CMT_FIFO_SW2A2_7", - "CMT_FIFO_SW2A2_8", - "CMT_FIFO_SW2A2_9", - "CMT_FIFO_SW2A3_0", - "CMT_FIFO_SW2A3_1", - "CMT_FIFO_SW2A3_10", - "CMT_FIFO_SW2A3_11", - "CMT_FIFO_SW2A3_2", - "CMT_FIFO_SW2A3_3", - "CMT_FIFO_SW2A3_4", - "CMT_FIFO_SW2A3_5", - "CMT_FIFO_SW2A3_6", - "CMT_FIFO_SW2A3_7", - "CMT_FIFO_SW2A3_8", - "CMT_FIFO_SW2A3_9", - "CMT_FIFO_SW4A0_0", - "CMT_FIFO_SW4A0_1", - "CMT_FIFO_SW4A0_10", - "CMT_FIFO_SW4A0_11", - "CMT_FIFO_SW4A0_2", - "CMT_FIFO_SW4A0_3", - "CMT_FIFO_SW4A0_4", - "CMT_FIFO_SW4A0_5", - "CMT_FIFO_SW4A0_6", - "CMT_FIFO_SW4A0_7", - "CMT_FIFO_SW4A0_8", - "CMT_FIFO_SW4A0_9", - "CMT_FIFO_SW4A1_0", - "CMT_FIFO_SW4A1_1", - "CMT_FIFO_SW4A1_10", - "CMT_FIFO_SW4A1_11", - "CMT_FIFO_SW4A1_2", - "CMT_FIFO_SW4A1_3", - "CMT_FIFO_SW4A1_4", - "CMT_FIFO_SW4A1_5", - "CMT_FIFO_SW4A1_6", - "CMT_FIFO_SW4A1_7", - "CMT_FIFO_SW4A1_8", - "CMT_FIFO_SW4A1_9", - "CMT_FIFO_SW4A2_0", - "CMT_FIFO_SW4A2_1", - "CMT_FIFO_SW4A2_10", - "CMT_FIFO_SW4A2_11", - "CMT_FIFO_SW4A2_2", - "CMT_FIFO_SW4A2_3", - "CMT_FIFO_SW4A2_4", - "CMT_FIFO_SW4A2_5", - "CMT_FIFO_SW4A2_6", - "CMT_FIFO_SW4A2_7", - "CMT_FIFO_SW4A2_8", - "CMT_FIFO_SW4A2_9", - "CMT_FIFO_SW4A3_0", - "CMT_FIFO_SW4A3_1", - "CMT_FIFO_SW4A3_10", - "CMT_FIFO_SW4A3_11", - "CMT_FIFO_SW4A3_2", - "CMT_FIFO_SW4A3_3", - "CMT_FIFO_SW4A3_4", - "CMT_FIFO_SW4A3_5", - "CMT_FIFO_SW4A3_6", - "CMT_FIFO_SW4A3_7", - "CMT_FIFO_SW4A3_8", - "CMT_FIFO_SW4A3_9", - "CMT_FIFO_SW4END0_0", - "CMT_FIFO_SW4END0_1", - "CMT_FIFO_SW4END0_10", - "CMT_FIFO_SW4END0_11", - "CMT_FIFO_SW4END0_2", - "CMT_FIFO_SW4END0_3", - "CMT_FIFO_SW4END0_4", - "CMT_FIFO_SW4END0_5", - "CMT_FIFO_SW4END0_6", - "CMT_FIFO_SW4END0_7", - "CMT_FIFO_SW4END0_8", - "CMT_FIFO_SW4END0_9", - "CMT_FIFO_SW4END1_0", - "CMT_FIFO_SW4END1_1", - "CMT_FIFO_SW4END1_10", - "CMT_FIFO_SW4END1_11", - "CMT_FIFO_SW4END1_2", - "CMT_FIFO_SW4END1_3", - "CMT_FIFO_SW4END1_4", - "CMT_FIFO_SW4END1_5", - "CMT_FIFO_SW4END1_6", - "CMT_FIFO_SW4END1_7", - "CMT_FIFO_SW4END1_8", - "CMT_FIFO_SW4END1_9", - "CMT_FIFO_SW4END2_0", - "CMT_FIFO_SW4END2_1", - "CMT_FIFO_SW4END2_10", - "CMT_FIFO_SW4END2_11", - "CMT_FIFO_SW4END2_2", - "CMT_FIFO_SW4END2_3", - "CMT_FIFO_SW4END2_4", - "CMT_FIFO_SW4END2_5", - "CMT_FIFO_SW4END2_6", - "CMT_FIFO_SW4END2_7", - "CMT_FIFO_SW4END2_8", - "CMT_FIFO_SW4END2_9", - "CMT_FIFO_SW4END3_0", - "CMT_FIFO_SW4END3_1", - "CMT_FIFO_SW4END3_10", - "CMT_FIFO_SW4END3_11", - "CMT_FIFO_SW4END3_2", - "CMT_FIFO_SW4END3_3", - "CMT_FIFO_SW4END3_4", - "CMT_FIFO_SW4END3_5", - "CMT_FIFO_SW4END3_6", - "CMT_FIFO_SW4END3_7", - "CMT_FIFO_SW4END3_8", - "CMT_FIFO_SW4END3_9", - "CMT_FIFO_WL1END0_0", - "CMT_FIFO_WL1END0_1", - "CMT_FIFO_WL1END0_10", - "CMT_FIFO_WL1END0_11", - "CMT_FIFO_WL1END0_2", - "CMT_FIFO_WL1END0_3", - "CMT_FIFO_WL1END0_4", - "CMT_FIFO_WL1END0_5", - "CMT_FIFO_WL1END0_6", - "CMT_FIFO_WL1END0_7", - "CMT_FIFO_WL1END0_8", - "CMT_FIFO_WL1END0_9", - "CMT_FIFO_WL1END1_0", - "CMT_FIFO_WL1END1_1", - "CMT_FIFO_WL1END1_10", - "CMT_FIFO_WL1END1_11", - "CMT_FIFO_WL1END1_2", - "CMT_FIFO_WL1END1_3", - "CMT_FIFO_WL1END1_4", - "CMT_FIFO_WL1END1_5", - "CMT_FIFO_WL1END1_6", - "CMT_FIFO_WL1END1_7", - "CMT_FIFO_WL1END1_8", - "CMT_FIFO_WL1END1_9", - "CMT_FIFO_WL1END2_0", - "CMT_FIFO_WL1END2_1", - "CMT_FIFO_WL1END2_10", - "CMT_FIFO_WL1END2_11", - "CMT_FIFO_WL1END2_2", - "CMT_FIFO_WL1END2_3", - "CMT_FIFO_WL1END2_4", - "CMT_FIFO_WL1END2_5", - "CMT_FIFO_WL1END2_6", - "CMT_FIFO_WL1END2_7", - "CMT_FIFO_WL1END2_8", - "CMT_FIFO_WL1END2_9", - "CMT_FIFO_WL1END3_0", - "CMT_FIFO_WL1END3_1", - "CMT_FIFO_WL1END3_10", - "CMT_FIFO_WL1END3_11", - "CMT_FIFO_WL1END3_2", - "CMT_FIFO_WL1END3_3", - "CMT_FIFO_WL1END3_4", - "CMT_FIFO_WL1END3_5", - "CMT_FIFO_WL1END3_6", - "CMT_FIFO_WL1END3_7", - "CMT_FIFO_WL1END3_8", - "CMT_FIFO_WL1END3_9", - "CMT_FIFO_WR1END0_0", - "CMT_FIFO_WR1END0_1", - "CMT_FIFO_WR1END0_10", - "CMT_FIFO_WR1END0_11", - "CMT_FIFO_WR1END0_2", - "CMT_FIFO_WR1END0_3", - "CMT_FIFO_WR1END0_4", - "CMT_FIFO_WR1END0_5", - "CMT_FIFO_WR1END0_6", - "CMT_FIFO_WR1END0_7", - "CMT_FIFO_WR1END0_8", - "CMT_FIFO_WR1END0_9", - "CMT_FIFO_WR1END1_0", - "CMT_FIFO_WR1END1_1", - "CMT_FIFO_WR1END1_10", - "CMT_FIFO_WR1END1_11", - "CMT_FIFO_WR1END1_2", - "CMT_FIFO_WR1END1_3", - "CMT_FIFO_WR1END1_4", - "CMT_FIFO_WR1END1_5", - "CMT_FIFO_WR1END1_6", - "CMT_FIFO_WR1END1_7", - "CMT_FIFO_WR1END1_8", - "CMT_FIFO_WR1END1_9", - "CMT_FIFO_WR1END2_0", - "CMT_FIFO_WR1END2_1", - "CMT_FIFO_WR1END2_10", - "CMT_FIFO_WR1END2_11", - "CMT_FIFO_WR1END2_2", - "CMT_FIFO_WR1END2_3", - "CMT_FIFO_WR1END2_4", - "CMT_FIFO_WR1END2_5", - "CMT_FIFO_WR1END2_6", - "CMT_FIFO_WR1END2_7", - "CMT_FIFO_WR1END2_8", - "CMT_FIFO_WR1END2_9", - "CMT_FIFO_WR1END3_0", - "CMT_FIFO_WR1END3_1", - "CMT_FIFO_WR1END3_10", - "CMT_FIFO_WR1END3_11", - "CMT_FIFO_WR1END3_2", - "CMT_FIFO_WR1END3_3", - "CMT_FIFO_WR1END3_4", - "CMT_FIFO_WR1END3_5", - "CMT_FIFO_WR1END3_6", - "CMT_FIFO_WR1END3_7", - "CMT_FIFO_WR1END3_8", - "CMT_FIFO_WR1END3_9", - "CMT_FIFO_WW2A0_0", - "CMT_FIFO_WW2A0_1", - "CMT_FIFO_WW2A0_10", - "CMT_FIFO_WW2A0_11", - "CMT_FIFO_WW2A0_2", - "CMT_FIFO_WW2A0_3", - "CMT_FIFO_WW2A0_4", - "CMT_FIFO_WW2A0_5", - "CMT_FIFO_WW2A0_6", - "CMT_FIFO_WW2A0_7", - "CMT_FIFO_WW2A0_8", - "CMT_FIFO_WW2A0_9", - "CMT_FIFO_WW2A1_0", - "CMT_FIFO_WW2A1_1", - "CMT_FIFO_WW2A1_10", - "CMT_FIFO_WW2A1_11", - "CMT_FIFO_WW2A1_2", - "CMT_FIFO_WW2A1_3", - "CMT_FIFO_WW2A1_4", - "CMT_FIFO_WW2A1_5", - "CMT_FIFO_WW2A1_6", - "CMT_FIFO_WW2A1_7", - "CMT_FIFO_WW2A1_8", - "CMT_FIFO_WW2A1_9", - "CMT_FIFO_WW2A2_0", - "CMT_FIFO_WW2A2_1", - "CMT_FIFO_WW2A2_10", - "CMT_FIFO_WW2A2_11", - "CMT_FIFO_WW2A2_2", - "CMT_FIFO_WW2A2_3", - "CMT_FIFO_WW2A2_4", - "CMT_FIFO_WW2A2_5", - "CMT_FIFO_WW2A2_6", - "CMT_FIFO_WW2A2_7", - "CMT_FIFO_WW2A2_8", - "CMT_FIFO_WW2A2_9", - "CMT_FIFO_WW2A3_0", - "CMT_FIFO_WW2A3_1", - "CMT_FIFO_WW2A3_10", - "CMT_FIFO_WW2A3_11", - "CMT_FIFO_WW2A3_2", - "CMT_FIFO_WW2A3_3", - "CMT_FIFO_WW2A3_4", - "CMT_FIFO_WW2A3_5", - "CMT_FIFO_WW2A3_6", - "CMT_FIFO_WW2A3_7", - "CMT_FIFO_WW2A3_8", - "CMT_FIFO_WW2A3_9", - "CMT_FIFO_WW2END0_0", - "CMT_FIFO_WW2END0_1", - "CMT_FIFO_WW2END0_10", - "CMT_FIFO_WW2END0_11", - "CMT_FIFO_WW2END0_2", - "CMT_FIFO_WW2END0_3", - "CMT_FIFO_WW2END0_4", - "CMT_FIFO_WW2END0_5", - "CMT_FIFO_WW2END0_6", - "CMT_FIFO_WW2END0_7", - "CMT_FIFO_WW2END0_8", - "CMT_FIFO_WW2END0_9", - "CMT_FIFO_WW2END1_0", - "CMT_FIFO_WW2END1_1", - "CMT_FIFO_WW2END1_10", - "CMT_FIFO_WW2END1_11", - "CMT_FIFO_WW2END1_2", - "CMT_FIFO_WW2END1_3", - "CMT_FIFO_WW2END1_4", - "CMT_FIFO_WW2END1_5", - "CMT_FIFO_WW2END1_6", - "CMT_FIFO_WW2END1_7", - "CMT_FIFO_WW2END1_8", - "CMT_FIFO_WW2END1_9", - "CMT_FIFO_WW2END2_0", - "CMT_FIFO_WW2END2_1", - "CMT_FIFO_WW2END2_10", - "CMT_FIFO_WW2END2_11", - "CMT_FIFO_WW2END2_2", - "CMT_FIFO_WW2END2_3", - "CMT_FIFO_WW2END2_4", - "CMT_FIFO_WW2END2_5", - "CMT_FIFO_WW2END2_6", - "CMT_FIFO_WW2END2_7", - "CMT_FIFO_WW2END2_8", - "CMT_FIFO_WW2END2_9", - "CMT_FIFO_WW2END3_0", - "CMT_FIFO_WW2END3_1", - "CMT_FIFO_WW2END3_10", - "CMT_FIFO_WW2END3_11", - "CMT_FIFO_WW2END3_2", - "CMT_FIFO_WW2END3_3", - "CMT_FIFO_WW2END3_4", - "CMT_FIFO_WW2END3_5", - "CMT_FIFO_WW2END3_6", - "CMT_FIFO_WW2END3_7", - "CMT_FIFO_WW2END3_8", - "CMT_FIFO_WW2END3_9", - "CMT_FIFO_WW4A0_0", - "CMT_FIFO_WW4A0_1", - "CMT_FIFO_WW4A0_10", - "CMT_FIFO_WW4A0_11", - "CMT_FIFO_WW4A0_2", - "CMT_FIFO_WW4A0_3", - "CMT_FIFO_WW4A0_4", - "CMT_FIFO_WW4A0_5", - "CMT_FIFO_WW4A0_6", - "CMT_FIFO_WW4A0_7", - "CMT_FIFO_WW4A0_8", - "CMT_FIFO_WW4A0_9", - "CMT_FIFO_WW4A1_0", - "CMT_FIFO_WW4A1_1", - "CMT_FIFO_WW4A1_10", - "CMT_FIFO_WW4A1_11", - "CMT_FIFO_WW4A1_2", - "CMT_FIFO_WW4A1_3", - "CMT_FIFO_WW4A1_4", - "CMT_FIFO_WW4A1_5", - "CMT_FIFO_WW4A1_6", - "CMT_FIFO_WW4A1_7", - "CMT_FIFO_WW4A1_8", - "CMT_FIFO_WW4A1_9", - "CMT_FIFO_WW4A2_0", - "CMT_FIFO_WW4A2_1", - "CMT_FIFO_WW4A2_10", - "CMT_FIFO_WW4A2_11", - "CMT_FIFO_WW4A2_2", - "CMT_FIFO_WW4A2_3", - "CMT_FIFO_WW4A2_4", - "CMT_FIFO_WW4A2_5", - "CMT_FIFO_WW4A2_6", - "CMT_FIFO_WW4A2_7", - "CMT_FIFO_WW4A2_8", - "CMT_FIFO_WW4A2_9", - "CMT_FIFO_WW4A3_0", - "CMT_FIFO_WW4A3_1", - "CMT_FIFO_WW4A3_10", - "CMT_FIFO_WW4A3_11", - "CMT_FIFO_WW4A3_2", - "CMT_FIFO_WW4A3_3", - "CMT_FIFO_WW4A3_4", - "CMT_FIFO_WW4A3_5", - "CMT_FIFO_WW4A3_6", - "CMT_FIFO_WW4A3_7", - "CMT_FIFO_WW4A3_8", - "CMT_FIFO_WW4A3_9", - "CMT_FIFO_WW4B0_0", - "CMT_FIFO_WW4B0_1", - "CMT_FIFO_WW4B0_10", - "CMT_FIFO_WW4B0_11", - "CMT_FIFO_WW4B0_2", - "CMT_FIFO_WW4B0_3", - "CMT_FIFO_WW4B0_4", - "CMT_FIFO_WW4B0_5", - "CMT_FIFO_WW4B0_6", - "CMT_FIFO_WW4B0_7", - "CMT_FIFO_WW4B0_8", - "CMT_FIFO_WW4B0_9", - "CMT_FIFO_WW4B1_0", - "CMT_FIFO_WW4B1_1", - "CMT_FIFO_WW4B1_10", - "CMT_FIFO_WW4B1_11", - "CMT_FIFO_WW4B1_2", - "CMT_FIFO_WW4B1_3", - "CMT_FIFO_WW4B1_4", - "CMT_FIFO_WW4B1_5", - "CMT_FIFO_WW4B1_6", - "CMT_FIFO_WW4B1_7", - "CMT_FIFO_WW4B1_8", - "CMT_FIFO_WW4B1_9", - "CMT_FIFO_WW4B2_0", - "CMT_FIFO_WW4B2_1", - "CMT_FIFO_WW4B2_10", - "CMT_FIFO_WW4B2_11", - "CMT_FIFO_WW4B2_2", - "CMT_FIFO_WW4B2_3", - "CMT_FIFO_WW4B2_4", - "CMT_FIFO_WW4B2_5", - "CMT_FIFO_WW4B2_6", - "CMT_FIFO_WW4B2_7", - "CMT_FIFO_WW4B2_8", - "CMT_FIFO_WW4B2_9", - "CMT_FIFO_WW4B3_0", - "CMT_FIFO_WW4B3_1", - "CMT_FIFO_WW4B3_10", - "CMT_FIFO_WW4B3_11", - "CMT_FIFO_WW4B3_2", - "CMT_FIFO_WW4B3_3", - "CMT_FIFO_WW4B3_4", - "CMT_FIFO_WW4B3_5", - "CMT_FIFO_WW4B3_6", - "CMT_FIFO_WW4B3_7", - "CMT_FIFO_WW4B3_8", - "CMT_FIFO_WW4B3_9", - "CMT_FIFO_WW4C0_0", - "CMT_FIFO_WW4C0_1", - "CMT_FIFO_WW4C0_10", - "CMT_FIFO_WW4C0_11", - "CMT_FIFO_WW4C0_2", - "CMT_FIFO_WW4C0_3", - "CMT_FIFO_WW4C0_4", - "CMT_FIFO_WW4C0_5", - "CMT_FIFO_WW4C0_6", - "CMT_FIFO_WW4C0_7", - "CMT_FIFO_WW4C0_8", - "CMT_FIFO_WW4C0_9", - "CMT_FIFO_WW4C1_0", - "CMT_FIFO_WW4C1_1", - "CMT_FIFO_WW4C1_10", - "CMT_FIFO_WW4C1_11", - "CMT_FIFO_WW4C1_2", - "CMT_FIFO_WW4C1_3", - "CMT_FIFO_WW4C1_4", - "CMT_FIFO_WW4C1_5", - "CMT_FIFO_WW4C1_6", - "CMT_FIFO_WW4C1_7", - "CMT_FIFO_WW4C1_8", - "CMT_FIFO_WW4C1_9", - "CMT_FIFO_WW4C2_0", - "CMT_FIFO_WW4C2_1", - "CMT_FIFO_WW4C2_10", - "CMT_FIFO_WW4C2_11", - "CMT_FIFO_WW4C2_2", - "CMT_FIFO_WW4C2_3", - "CMT_FIFO_WW4C2_4", - "CMT_FIFO_WW4C2_5", - "CMT_FIFO_WW4C2_6", - "CMT_FIFO_WW4C2_7", - "CMT_FIFO_WW4C2_8", - "CMT_FIFO_WW4C2_9", - "CMT_FIFO_WW4C3_0", - "CMT_FIFO_WW4C3_1", - "CMT_FIFO_WW4C3_10", - "CMT_FIFO_WW4C3_11", - "CMT_FIFO_WW4C3_2", - "CMT_FIFO_WW4C3_3", - "CMT_FIFO_WW4C3_4", - "CMT_FIFO_WW4C3_5", - "CMT_FIFO_WW4C3_6", - "CMT_FIFO_WW4C3_7", - "CMT_FIFO_WW4C3_8", - "CMT_FIFO_WW4C3_9", - "CMT_FIFO_WW4END0_0", - "CMT_FIFO_WW4END0_1", - "CMT_FIFO_WW4END0_10", - "CMT_FIFO_WW4END0_11", - "CMT_FIFO_WW4END0_2", - "CMT_FIFO_WW4END0_3", - "CMT_FIFO_WW4END0_4", - "CMT_FIFO_WW4END0_5", - "CMT_FIFO_WW4END0_6", - "CMT_FIFO_WW4END0_7", - "CMT_FIFO_WW4END0_8", - "CMT_FIFO_WW4END0_9", - "CMT_FIFO_WW4END1_0", - "CMT_FIFO_WW4END1_1", - "CMT_FIFO_WW4END1_10", - "CMT_FIFO_WW4END1_11", - "CMT_FIFO_WW4END1_2", - "CMT_FIFO_WW4END1_3", - "CMT_FIFO_WW4END1_4", - "CMT_FIFO_WW4END1_5", - "CMT_FIFO_WW4END1_6", - "CMT_FIFO_WW4END1_7", - "CMT_FIFO_WW4END1_8", - "CMT_FIFO_WW4END1_9", - "CMT_FIFO_WW4END2_0", - "CMT_FIFO_WW4END2_1", - "CMT_FIFO_WW4END2_10", - "CMT_FIFO_WW4END2_11", - "CMT_FIFO_WW4END2_2", - "CMT_FIFO_WW4END2_3", - "CMT_FIFO_WW4END2_4", - "CMT_FIFO_WW4END2_5", - "CMT_FIFO_WW4END2_6", - "CMT_FIFO_WW4END2_7", - "CMT_FIFO_WW4END2_8", - "CMT_FIFO_WW4END2_9", - "CMT_FIFO_WW4END3_0", - "CMT_FIFO_WW4END3_1", - "CMT_FIFO_WW4END3_10", - "CMT_FIFO_WW4END3_11", - "CMT_FIFO_WW4END3_2", - "CMT_FIFO_WW4END3_3", - "CMT_FIFO_WW4END3_4", - "CMT_FIFO_WW4END3_5", - "CMT_FIFO_WW4END3_6", - "CMT_FIFO_WW4END3_7", - "CMT_FIFO_WW4END3_8", - "CMT_FIFO_WW4END3_9", - "CMT_IN_FIFO_ALMOSTEMPTY", - "CMT_IN_FIFO_ALMOSTFULL", - "CMT_IN_FIFO_D00", - "CMT_IN_FIFO_D01", - "CMT_IN_FIFO_D02", - "CMT_IN_FIFO_D03", - "CMT_IN_FIFO_D10", - "CMT_IN_FIFO_D11", - "CMT_IN_FIFO_D12", - "CMT_IN_FIFO_D13", - "CMT_IN_FIFO_D20", - "CMT_IN_FIFO_D21", - "CMT_IN_FIFO_D22", - "CMT_IN_FIFO_D23", - "CMT_IN_FIFO_D30", - "CMT_IN_FIFO_D31", - "CMT_IN_FIFO_D32", - "CMT_IN_FIFO_D33", - "CMT_IN_FIFO_D40", - "CMT_IN_FIFO_D41", - "CMT_IN_FIFO_D42", - "CMT_IN_FIFO_D43", - "CMT_IN_FIFO_D50", - "CMT_IN_FIFO_D51", - "CMT_IN_FIFO_D52", - "CMT_IN_FIFO_D53", - "CMT_IN_FIFO_D54", - "CMT_IN_FIFO_D55", - "CMT_IN_FIFO_D56", - "CMT_IN_FIFO_D57", - "CMT_IN_FIFO_D60", - "CMT_IN_FIFO_D61", - "CMT_IN_FIFO_D62", - "CMT_IN_FIFO_D63", - "CMT_IN_FIFO_D64", - "CMT_IN_FIFO_D65", - "CMT_IN_FIFO_D66", - "CMT_IN_FIFO_D67", - "CMT_IN_FIFO_D70", - "CMT_IN_FIFO_D71", - "CMT_IN_FIFO_D72", - "CMT_IN_FIFO_D73", - "CMT_IN_FIFO_D80", - "CMT_IN_FIFO_D81", - "CMT_IN_FIFO_D82", - "CMT_IN_FIFO_D83", - "CMT_IN_FIFO_D90", - "CMT_IN_FIFO_D91", - "CMT_IN_FIFO_D92", - "CMT_IN_FIFO_D93", - "CMT_IN_FIFO_EMPTY", - "CMT_IN_FIFO_FULL", - "CMT_IN_FIFO_Q00", - "CMT_IN_FIFO_Q01", - "CMT_IN_FIFO_Q02", - "CMT_IN_FIFO_Q03", - "CMT_IN_FIFO_Q04", - "CMT_IN_FIFO_Q05", - "CMT_IN_FIFO_Q06", - "CMT_IN_FIFO_Q07", - "CMT_IN_FIFO_Q10", - "CMT_IN_FIFO_Q11", - "CMT_IN_FIFO_Q12", - "CMT_IN_FIFO_Q13", - "CMT_IN_FIFO_Q14", - "CMT_IN_FIFO_Q15", - "CMT_IN_FIFO_Q16", - "CMT_IN_FIFO_Q17", - "CMT_IN_FIFO_Q20", - "CMT_IN_FIFO_Q21", - "CMT_IN_FIFO_Q22", - "CMT_IN_FIFO_Q23", - "CMT_IN_FIFO_Q24", - "CMT_IN_FIFO_Q25", - "CMT_IN_FIFO_Q26", - "CMT_IN_FIFO_Q27", - "CMT_IN_FIFO_Q30", - "CMT_IN_FIFO_Q31", - "CMT_IN_FIFO_Q32", - "CMT_IN_FIFO_Q33", - "CMT_IN_FIFO_Q34", - "CMT_IN_FIFO_Q35", - "CMT_IN_FIFO_Q36", - "CMT_IN_FIFO_Q37", - "CMT_IN_FIFO_Q40", - "CMT_IN_FIFO_Q41", - "CMT_IN_FIFO_Q42", - "CMT_IN_FIFO_Q43", - "CMT_IN_FIFO_Q44", - "CMT_IN_FIFO_Q45", - "CMT_IN_FIFO_Q46", - "CMT_IN_FIFO_Q47", - "CMT_IN_FIFO_Q50", - "CMT_IN_FIFO_Q51", - "CMT_IN_FIFO_Q52", - "CMT_IN_FIFO_Q53", - "CMT_IN_FIFO_Q54", - "CMT_IN_FIFO_Q55", - "CMT_IN_FIFO_Q56", - "CMT_IN_FIFO_Q57", - "CMT_IN_FIFO_Q60", - "CMT_IN_FIFO_Q61", - "CMT_IN_FIFO_Q62", - "CMT_IN_FIFO_Q63", - "CMT_IN_FIFO_Q64", - "CMT_IN_FIFO_Q65", - "CMT_IN_FIFO_Q66", - "CMT_IN_FIFO_Q67", - "CMT_IN_FIFO_Q70", - "CMT_IN_FIFO_Q71", - "CMT_IN_FIFO_Q72", - "CMT_IN_FIFO_Q73", - "CMT_IN_FIFO_Q74", - "CMT_IN_FIFO_Q75", - "CMT_IN_FIFO_Q76", - "CMT_IN_FIFO_Q77", - "CMT_IN_FIFO_Q80", - "CMT_IN_FIFO_Q81", - "CMT_IN_FIFO_Q82", - "CMT_IN_FIFO_Q83", - "CMT_IN_FIFO_Q84", - "CMT_IN_FIFO_Q85", - "CMT_IN_FIFO_Q86", - "CMT_IN_FIFO_Q87", - "CMT_IN_FIFO_Q90", - "CMT_IN_FIFO_Q91", - "CMT_IN_FIFO_Q92", - "CMT_IN_FIFO_Q93", - "CMT_IN_FIFO_Q94", - "CMT_IN_FIFO_Q95", - "CMT_IN_FIFO_Q96", - "CMT_IN_FIFO_Q97", - "CMT_IN_FIFO_RDCLK", - "CMT_IN_FIFO_RDEN", - "CMT_IN_FIFO_RESET", - "CMT_IN_FIFO_SCANENB", - "CMT_IN_FIFO_SCANIN0", - "CMT_IN_FIFO_SCANIN1", - "CMT_IN_FIFO_SCANIN2", - "CMT_IN_FIFO_SCANIN3", - "CMT_IN_FIFO_SCANOUT0", - "CMT_IN_FIFO_SCANOUT1", - "CMT_IN_FIFO_SCANOUT2", - "CMT_IN_FIFO_SCANOUT3", - "CMT_IN_FIFO_TESTMODEB", - "CMT_IN_FIFO_TESTREADDISB", - "CMT_IN_FIFO_TESTWRITEDISB", - "CMT_IN_FIFO_WRCLK", - "CMT_IN_FIFO_WREN", - "CMT_OUT_FIFO_ALMOSTEMPTY", - "CMT_OUT_FIFO_ALMOSTFULL", - "CMT_OUT_FIFO_D00", - "CMT_OUT_FIFO_D01", - "CMT_OUT_FIFO_D02", - "CMT_OUT_FIFO_D03", - "CMT_OUT_FIFO_D04", - "CMT_OUT_FIFO_D05", - "CMT_OUT_FIFO_D06", - "CMT_OUT_FIFO_D07", - "CMT_OUT_FIFO_D10", - "CMT_OUT_FIFO_D11", - "CMT_OUT_FIFO_D12", - "CMT_OUT_FIFO_D13", - "CMT_OUT_FIFO_D14", - "CMT_OUT_FIFO_D15", - "CMT_OUT_FIFO_D16", - "CMT_OUT_FIFO_D17", - "CMT_OUT_FIFO_D20", - "CMT_OUT_FIFO_D21", - "CMT_OUT_FIFO_D22", - "CMT_OUT_FIFO_D23", - "CMT_OUT_FIFO_D24", - "CMT_OUT_FIFO_D25", - "CMT_OUT_FIFO_D26", - "CMT_OUT_FIFO_D27", - "CMT_OUT_FIFO_D30", - "CMT_OUT_FIFO_D31", - "CMT_OUT_FIFO_D32", - "CMT_OUT_FIFO_D33", - "CMT_OUT_FIFO_D34", - "CMT_OUT_FIFO_D35", - "CMT_OUT_FIFO_D36", - "CMT_OUT_FIFO_D37", - "CMT_OUT_FIFO_D40", - "CMT_OUT_FIFO_D41", - "CMT_OUT_FIFO_D42", - "CMT_OUT_FIFO_D43", - "CMT_OUT_FIFO_D44", - "CMT_OUT_FIFO_D45", - "CMT_OUT_FIFO_D46", - "CMT_OUT_FIFO_D47", - "CMT_OUT_FIFO_D50", - "CMT_OUT_FIFO_D51", - "CMT_OUT_FIFO_D52", - "CMT_OUT_FIFO_D53", - "CMT_OUT_FIFO_D54", - "CMT_OUT_FIFO_D55", - "CMT_OUT_FIFO_D56", - "CMT_OUT_FIFO_D57", - "CMT_OUT_FIFO_D60", - "CMT_OUT_FIFO_D61", - "CMT_OUT_FIFO_D62", - "CMT_OUT_FIFO_D63", - "CMT_OUT_FIFO_D64", - "CMT_OUT_FIFO_D65", - "CMT_OUT_FIFO_D66", - "CMT_OUT_FIFO_D67", - "CMT_OUT_FIFO_D70", - "CMT_OUT_FIFO_D71", - "CMT_OUT_FIFO_D72", - "CMT_OUT_FIFO_D73", - "CMT_OUT_FIFO_D74", - "CMT_OUT_FIFO_D75", - "CMT_OUT_FIFO_D76", - "CMT_OUT_FIFO_D77", - "CMT_OUT_FIFO_D80", - "CMT_OUT_FIFO_D81", - "CMT_OUT_FIFO_D82", - "CMT_OUT_FIFO_D83", - "CMT_OUT_FIFO_D84", - "CMT_OUT_FIFO_D85", - "CMT_OUT_FIFO_D86", - "CMT_OUT_FIFO_D87", - "CMT_OUT_FIFO_D90", - "CMT_OUT_FIFO_D91", - "CMT_OUT_FIFO_D92", - "CMT_OUT_FIFO_D93", - "CMT_OUT_FIFO_D94", - "CMT_OUT_FIFO_D95", - "CMT_OUT_FIFO_D96", - "CMT_OUT_FIFO_D97", - "CMT_OUT_FIFO_EMPTY", - "CMT_OUT_FIFO_FULL", - "CMT_OUT_FIFO_Q00", - "CMT_OUT_FIFO_Q01", - "CMT_OUT_FIFO_Q02", - "CMT_OUT_FIFO_Q03", - "CMT_OUT_FIFO_Q10", - "CMT_OUT_FIFO_Q11", - "CMT_OUT_FIFO_Q12", - "CMT_OUT_FIFO_Q13", - "CMT_OUT_FIFO_Q20", - "CMT_OUT_FIFO_Q21", - "CMT_OUT_FIFO_Q22", - "CMT_OUT_FIFO_Q23", - "CMT_OUT_FIFO_Q30", - "CMT_OUT_FIFO_Q31", - "CMT_OUT_FIFO_Q32", - "CMT_OUT_FIFO_Q33", - "CMT_OUT_FIFO_Q40", - "CMT_OUT_FIFO_Q41", - "CMT_OUT_FIFO_Q42", - "CMT_OUT_FIFO_Q43", - "CMT_OUT_FIFO_Q50", - "CMT_OUT_FIFO_Q51", - "CMT_OUT_FIFO_Q52", - "CMT_OUT_FIFO_Q53", - "CMT_OUT_FIFO_Q54", - "CMT_OUT_FIFO_Q55", - "CMT_OUT_FIFO_Q56", - "CMT_OUT_FIFO_Q57", - "CMT_OUT_FIFO_Q60", - "CMT_OUT_FIFO_Q61", - "CMT_OUT_FIFO_Q62", - "CMT_OUT_FIFO_Q63", - "CMT_OUT_FIFO_Q64", - "CMT_OUT_FIFO_Q65", - "CMT_OUT_FIFO_Q66", - "CMT_OUT_FIFO_Q67", - "CMT_OUT_FIFO_Q70", - "CMT_OUT_FIFO_Q71", - "CMT_OUT_FIFO_Q72", - "CMT_OUT_FIFO_Q73", - "CMT_OUT_FIFO_Q80", - "CMT_OUT_FIFO_Q81", - "CMT_OUT_FIFO_Q82", - "CMT_OUT_FIFO_Q83", - "CMT_OUT_FIFO_Q90", - "CMT_OUT_FIFO_Q91", - "CMT_OUT_FIFO_Q92", - "CMT_OUT_FIFO_Q93", - "CMT_OUT_FIFO_RDCLK", - "CMT_OUT_FIFO_RDEN", - "CMT_OUT_FIFO_RESET", - "CMT_OUT_FIFO_SCANENB", - "CMT_OUT_FIFO_SCANIN0", - "CMT_OUT_FIFO_SCANIN1", - "CMT_OUT_FIFO_SCANIN2", - "CMT_OUT_FIFO_SCANIN3", - "CMT_OUT_FIFO_SCANOUT0", - "CMT_OUT_FIFO_SCANOUT1", - "CMT_OUT_FIFO_SCANOUT2", - "CMT_OUT_FIFO_SCANOUT3", - "CMT_OUT_FIFO_TESTMODEB", - "CMT_OUT_FIFO_TESTREADDISB", - "CMT_OUT_FIFO_TESTWRITEDISB", - "CMT_OUT_FIFO_WRCLK", - "CMT_OUT_FIFO_WREN", - "FIFO_DQS_IOTOPHASER_1", - "FIFO_DQS_IOTOPHASER_11", - "FIFO_DQS_IOTOPHASER_2", - "FIFO_DQS_IOTOPHASER_22", - "FIFO_DQS_IOTOPHASER_3", - "FIFO_DQS_IOTOPHASER_33", - "FIFO_DQS_IOTOPHASER_4", - "FIFO_DQS_IOTOPHASER_44", - "FIFO_DQS_IOTOPHASER_5", - "FIFO_DQS_IOTOPHASER_55", - "FIFO_DQS_IOTOPHASER_6", - "FIFO_DQS_IOTOPHASER_66" - ] + "wires": { + "CMT_FIFO_EE2A0_0": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_FIFO_EE2A0_1": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_FIFO_EE2A0_10": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_FIFO_EE2A0_11": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_FIFO_EE2A0_2": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_FIFO_EE2A0_3": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_FIFO_EE2A0_4": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_FIFO_EE2A0_5": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_FIFO_EE2A0_6": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_FIFO_EE2A0_7": { + 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+ "res": "0.000" + }, + "CMT_OUT_FIFO_D90": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_D91": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_D92": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_D93": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_D94": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_D95": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_D96": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_D97": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_EMPTY": { + "cap": "7.117", + "res": "0.000" + }, + "CMT_OUT_FIFO_FULL": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q00": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q01": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q02": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q03": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q10": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q11": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q12": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q13": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q20": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q21": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q22": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q23": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q30": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q31": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q32": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q33": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q40": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q41": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q42": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q43": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q50": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q51": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q52": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q53": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q54": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q55": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q56": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q57": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q60": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q61": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q62": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q63": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q64": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q65": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q66": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q67": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q70": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q71": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q72": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q73": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q80": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q81": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q82": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q83": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q90": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q91": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q92": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q93": { + "cap": "0.712", + "res": "0.000" + }, + "CMT_OUT_FIFO_RDCLK": { + "cap": "9.959", + "res": "0.000" + }, + "CMT_OUT_FIFO_RDEN": { + "cap": "4.460", + "res": "0.000" + }, + "CMT_OUT_FIFO_RESET": { + "cap": "1.039", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANENB": { + "cap": "1.039", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANIN0": { + "cap": "1.039", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANIN1": { + "cap": "1.039", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANIN2": { + "cap": "1.039", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANIN3": { + "cap": "1.039", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANOUT0": { + "cap": "1.039", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANOUT1": { + "cap": "1.039", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANOUT2": { + "cap": "1.039", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANOUT3": { + "cap": "1.039", + "res": "0.000" + }, + "CMT_OUT_FIFO_TESTMODEB": { + "cap": "1.039", + "res": "0.000" + }, + "CMT_OUT_FIFO_TESTREADDISB": { + "cap": "1.039", + "res": "0.000" + }, + "CMT_OUT_FIFO_TESTWRITEDISB": { + "cap": "1.039", + "res": "0.000" + }, + "CMT_OUT_FIFO_WRCLK": { + "cap": "9.959", + "res": "0.000" + }, + "CMT_OUT_FIFO_WREN": { + "cap": "1.713", + "res": "0.000" + }, + "FIFO_DQS_IOTOPHASER_1": null, + "FIFO_DQS_IOTOPHASER_11": null, + "FIFO_DQS_IOTOPHASER_2": null, + "FIFO_DQS_IOTOPHASER_22": null, + "FIFO_DQS_IOTOPHASER_3": null, + "FIFO_DQS_IOTOPHASER_33": null, + "FIFO_DQS_IOTOPHASER_4": null, + "FIFO_DQS_IOTOPHASER_44": null, + "FIFO_DQS_IOTOPHASER_5": null, + "FIFO_DQS_IOTOPHASER_55": null, + "FIFO_DQS_IOTOPHASER_6": null, + "FIFO_DQS_IOTOPHASER_66": null + } } diff --git a/zynq7/tile_type_CMT_PMV_L.json b/zynq7/tile_type_CMT_PMV_L.json index 4fa0775..7e4bd59 100644 --- a/zynq7/tile_type_CMT_PMV_L.json +++ b/zynq7/tile_type_CMT_PMV_L.json @@ -2,229 +2,601 @@ "pips": {}, "sites": [], "tile_type": "CMT_PMV_L", - "wires": [ - "CMT_PMV_BYP0", - "CMT_PMV_BYP1", - "CMT_PMV_BYP2", - "CMT_PMV_BYP3", - "CMT_PMV_BYP4", - "CMT_PMV_BYP5", - "CMT_PMV_BYP6", - "CMT_PMV_BYP7", - "CMT_PMV_CLK0", - "CMT_PMV_CLK1", - "CMT_PMV_CTRL0", - "CMT_PMV_CTRL1", - "CMT_PMV_EE2A0", - "CMT_PMV_EE2A1", - "CMT_PMV_EE2A2", - "CMT_PMV_EE2A3", - "CMT_PMV_EE2BEG0", - "CMT_PMV_EE2BEG1", - "CMT_PMV_EE2BEG2", - "CMT_PMV_EE2BEG3", - "CMT_PMV_EE4A0", - "CMT_PMV_EE4A1", - "CMT_PMV_EE4A2", - "CMT_PMV_EE4A3", - "CMT_PMV_EE4B0", - "CMT_PMV_EE4B1", - "CMT_PMV_EE4B2", - "CMT_PMV_EE4B3", - "CMT_PMV_EE4BEG0", - "CMT_PMV_EE4BEG1", - "CMT_PMV_EE4BEG2", - "CMT_PMV_EE4BEG3", - "CMT_PMV_EE4C0", - "CMT_PMV_EE4C1", - "CMT_PMV_EE4C2", - "CMT_PMV_EE4C3", - "CMT_PMV_EL1BEG0", - "CMT_PMV_EL1BEG1", - "CMT_PMV_EL1BEG2", - "CMT_PMV_EL1BEG3", - "CMT_PMV_ER1BEG0", - "CMT_PMV_ER1BEG1", - "CMT_PMV_ER1BEG2", - "CMT_PMV_ER1BEG3", - "CMT_PMV_FAN0", - "CMT_PMV_FAN1", - "CMT_PMV_FAN2", - "CMT_PMV_FAN3", - "CMT_PMV_FAN4", - "CMT_PMV_FAN5", - "CMT_PMV_FAN6", - "CMT_PMV_FAN7", - "CMT_PMV_IMUX0", - "CMT_PMV_IMUX1", - "CMT_PMV_IMUX10", - "CMT_PMV_IMUX11", - "CMT_PMV_IMUX12", - "CMT_PMV_IMUX13", - "CMT_PMV_IMUX14", - "CMT_PMV_IMUX15", - "CMT_PMV_IMUX16", - "CMT_PMV_IMUX17", - "CMT_PMV_IMUX18", - "CMT_PMV_IMUX19", - "CMT_PMV_IMUX2", - "CMT_PMV_IMUX20", - "CMT_PMV_IMUX21", - "CMT_PMV_IMUX22", - "CMT_PMV_IMUX23", - "CMT_PMV_IMUX24", - "CMT_PMV_IMUX25", - "CMT_PMV_IMUX26", - "CMT_PMV_IMUX27", - "CMT_PMV_IMUX28", - "CMT_PMV_IMUX29", - "CMT_PMV_IMUX3", - "CMT_PMV_IMUX30", - "CMT_PMV_IMUX31", - "CMT_PMV_IMUX32", - "CMT_PMV_IMUX33", - "CMT_PMV_IMUX34", - "CMT_PMV_IMUX35", - "CMT_PMV_IMUX36", - "CMT_PMV_IMUX37", - "CMT_PMV_IMUX38", - "CMT_PMV_IMUX39", - "CMT_PMV_IMUX4", - "CMT_PMV_IMUX40", - "CMT_PMV_IMUX41", - "CMT_PMV_IMUX42", - "CMT_PMV_IMUX43", - "CMT_PMV_IMUX44", - "CMT_PMV_IMUX45", - "CMT_PMV_IMUX46", - "CMT_PMV_IMUX47", - "CMT_PMV_IMUX5", - "CMT_PMV_IMUX6", - "CMT_PMV_IMUX7", - "CMT_PMV_IMUX8", - "CMT_PMV_IMUX9", - "CMT_PMV_LH1", - "CMT_PMV_LH10", - "CMT_PMV_LH11", - "CMT_PMV_LH12", - "CMT_PMV_LH2", - "CMT_PMV_LH3", - "CMT_PMV_LH4", - "CMT_PMV_LH5", - "CMT_PMV_LH6", - "CMT_PMV_LH7", - "CMT_PMV_LH8", - "CMT_PMV_LH9", - "CMT_PMV_LOGIC_OUTS0", - "CMT_PMV_LOGIC_OUTS1", - "CMT_PMV_LOGIC_OUTS10", - "CMT_PMV_LOGIC_OUTS11", - "CMT_PMV_LOGIC_OUTS12", - "CMT_PMV_LOGIC_OUTS13", - "CMT_PMV_LOGIC_OUTS14", - "CMT_PMV_LOGIC_OUTS15", - "CMT_PMV_LOGIC_OUTS16", - "CMT_PMV_LOGIC_OUTS17", - "CMT_PMV_LOGIC_OUTS18", - "CMT_PMV_LOGIC_OUTS19", - "CMT_PMV_LOGIC_OUTS2", - "CMT_PMV_LOGIC_OUTS20", - "CMT_PMV_LOGIC_OUTS21", - "CMT_PMV_LOGIC_OUTS22", - "CMT_PMV_LOGIC_OUTS23", - "CMT_PMV_LOGIC_OUTS3", - "CMT_PMV_LOGIC_OUTS4", - "CMT_PMV_LOGIC_OUTS5", - "CMT_PMV_LOGIC_OUTS6", - "CMT_PMV_LOGIC_OUTS7", - "CMT_PMV_LOGIC_OUTS8", - "CMT_PMV_LOGIC_OUTS9", - "CMT_PMV_MONITOR_N", - "CMT_PMV_MONITOR_P", - "CMT_PMV_NE2A0", - "CMT_PMV_NE2A1", - "CMT_PMV_NE2A2", - "CMT_PMV_NE2A3", - "CMT_PMV_NE4BEG0", - "CMT_PMV_NE4BEG1", - "CMT_PMV_NE4BEG2", - "CMT_PMV_NE4BEG3", - "CMT_PMV_NE4C0", - "CMT_PMV_NE4C1", - "CMT_PMV_NE4C2", - "CMT_PMV_NE4C3", - "CMT_PMV_NW2A0", - "CMT_PMV_NW2A1", - "CMT_PMV_NW2A2", - "CMT_PMV_NW2A3", - "CMT_PMV_NW4A0", - "CMT_PMV_NW4A1", - "CMT_PMV_NW4A2", - "CMT_PMV_NW4A3", - "CMT_PMV_NW4END0", - "CMT_PMV_NW4END1", - "CMT_PMV_NW4END2", - "CMT_PMV_NW4END3", - "CMT_PMV_SE2A0", - "CMT_PMV_SE2A1", - "CMT_PMV_SE2A2", - "CMT_PMV_SE2A3", - "CMT_PMV_SE4BEG0", - "CMT_PMV_SE4BEG1", - "CMT_PMV_SE4BEG2", - "CMT_PMV_SE4BEG3", - "CMT_PMV_SE4C0", - "CMT_PMV_SE4C1", - "CMT_PMV_SE4C2", - "CMT_PMV_SE4C3", - "CMT_PMV_SW2A0", - "CMT_PMV_SW2A1", - "CMT_PMV_SW2A2", - "CMT_PMV_SW2A3", - "CMT_PMV_SW4A0", - "CMT_PMV_SW4A1", - "CMT_PMV_SW4A2", - "CMT_PMV_SW4A3", - "CMT_PMV_SW4END0", - "CMT_PMV_SW4END1", - "CMT_PMV_SW4END2", - "CMT_PMV_SW4END3", - "CMT_PMV_WL1END0", - "CMT_PMV_WL1END1", - "CMT_PMV_WL1END2", - "CMT_PMV_WL1END3", - "CMT_PMV_WR1END0", - "CMT_PMV_WR1END1", - "CMT_PMV_WR1END2", - "CMT_PMV_WR1END3", - "CMT_PMV_WW2A0", - "CMT_PMV_WW2A1", - "CMT_PMV_WW2A2", - "CMT_PMV_WW2A3", - "CMT_PMV_WW2END0", - "CMT_PMV_WW2END1", - "CMT_PMV_WW2END2", - "CMT_PMV_WW2END3", - "CMT_PMV_WW4A0", - "CMT_PMV_WW4A1", - "CMT_PMV_WW4A2", - "CMT_PMV_WW4A3", - "CMT_PMV_WW4B0", - "CMT_PMV_WW4B1", - "CMT_PMV_WW4B2", - "CMT_PMV_WW4B3", - "CMT_PMV_WW4C0", - "CMT_PMV_WW4C1", - "CMT_PMV_WW4C2", - "CMT_PMV_WW4C3", - "CMT_PMV_WW4END0", - "CMT_PMV_WW4END1", - "CMT_PMV_WW4END2", - "CMT_PMV_WW4END3", - "L_TERM_INT_PHASER_TO_IO_ICLK", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV", - "L_TERM_INT_PHASER_TO_IO_OCLK", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" - ] + "wires": { + "CMT_PMV_BYP0": null, + "CMT_PMV_BYP1": null, + "CMT_PMV_BYP2": null, + "CMT_PMV_BYP3": null, + "CMT_PMV_BYP4": null, + "CMT_PMV_BYP5": null, + "CMT_PMV_BYP6": null, + "CMT_PMV_BYP7": null, + "CMT_PMV_CLK0": null, + "CMT_PMV_CLK1": null, + "CMT_PMV_CTRL0": null, + "CMT_PMV_CTRL1": null, + "CMT_PMV_EE2A0": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_EE2A1": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_EE2A2": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_EE2A3": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_EE2BEG0": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_EE2BEG1": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_EE2BEG2": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_EE2BEG3": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_EE4A0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4A1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4A2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4A3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4B0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4B1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4B2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4B3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4BEG0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4BEG1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4BEG2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4BEG3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4C0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4C1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4C2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EE4C3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_EL1BEG0": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_EL1BEG1": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_EL1BEG2": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_EL1BEG3": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_ER1BEG0": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_ER1BEG1": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_ER1BEG2": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_ER1BEG3": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_FAN0": null, + "CMT_PMV_FAN1": null, + "CMT_PMV_FAN2": null, + "CMT_PMV_FAN3": null, + "CMT_PMV_FAN4": null, + "CMT_PMV_FAN5": null, + "CMT_PMV_FAN6": null, + "CMT_PMV_FAN7": null, + "CMT_PMV_IMUX0": null, + "CMT_PMV_IMUX1": null, + "CMT_PMV_IMUX10": null, + "CMT_PMV_IMUX11": null, + "CMT_PMV_IMUX12": null, + "CMT_PMV_IMUX13": null, + "CMT_PMV_IMUX14": null, + "CMT_PMV_IMUX15": null, + "CMT_PMV_IMUX16": null, + "CMT_PMV_IMUX17": null, + "CMT_PMV_IMUX18": null, + "CMT_PMV_IMUX19": null, + "CMT_PMV_IMUX2": null, + "CMT_PMV_IMUX20": null, + "CMT_PMV_IMUX21": null, + "CMT_PMV_IMUX22": null, + "CMT_PMV_IMUX23": null, + "CMT_PMV_IMUX24": null, + "CMT_PMV_IMUX25": null, + "CMT_PMV_IMUX26": null, + "CMT_PMV_IMUX27": null, + "CMT_PMV_IMUX28": null, + "CMT_PMV_IMUX29": null, + "CMT_PMV_IMUX3": null, + "CMT_PMV_IMUX30": null, + "CMT_PMV_IMUX31": null, + "CMT_PMV_IMUX32": null, + "CMT_PMV_IMUX33": null, + "CMT_PMV_IMUX34": null, + "CMT_PMV_IMUX35": null, + "CMT_PMV_IMUX36": null, + "CMT_PMV_IMUX37": null, + "CMT_PMV_IMUX38": null, + "CMT_PMV_IMUX39": null, + "CMT_PMV_IMUX4": null, + "CMT_PMV_IMUX40": null, + "CMT_PMV_IMUX41": null, + "CMT_PMV_IMUX42": null, + "CMT_PMV_IMUX43": null, + "CMT_PMV_IMUX44": null, + "CMT_PMV_IMUX45": null, + "CMT_PMV_IMUX46": null, + "CMT_PMV_IMUX47": null, + "CMT_PMV_IMUX5": null, + "CMT_PMV_IMUX6": null, + "CMT_PMV_IMUX7": null, + "CMT_PMV_IMUX8": null, + "CMT_PMV_IMUX9": null, + "CMT_PMV_LH1": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH10": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH11": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH12": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH2": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH3": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH4": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH5": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH6": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH7": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH8": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH9": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LOGIC_OUTS0": null, + "CMT_PMV_LOGIC_OUTS1": null, + "CMT_PMV_LOGIC_OUTS10": null, + "CMT_PMV_LOGIC_OUTS11": null, + "CMT_PMV_LOGIC_OUTS12": null, + "CMT_PMV_LOGIC_OUTS13": null, + "CMT_PMV_LOGIC_OUTS14": null, + "CMT_PMV_LOGIC_OUTS15": null, + "CMT_PMV_LOGIC_OUTS16": null, + "CMT_PMV_LOGIC_OUTS17": null, + "CMT_PMV_LOGIC_OUTS18": null, + "CMT_PMV_LOGIC_OUTS19": null, + "CMT_PMV_LOGIC_OUTS2": null, + "CMT_PMV_LOGIC_OUTS20": null, + "CMT_PMV_LOGIC_OUTS21": null, + "CMT_PMV_LOGIC_OUTS22": null, + "CMT_PMV_LOGIC_OUTS23": null, + "CMT_PMV_LOGIC_OUTS3": null, + "CMT_PMV_LOGIC_OUTS4": null, + "CMT_PMV_LOGIC_OUTS5": null, + "CMT_PMV_LOGIC_OUTS6": null, + "CMT_PMV_LOGIC_OUTS7": null, + "CMT_PMV_LOGIC_OUTS8": null, + "CMT_PMV_LOGIC_OUTS9": null, + "CMT_PMV_MONITOR_N": null, + "CMT_PMV_MONITOR_P": null, + "CMT_PMV_NE2A0": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_NE2A1": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_NE2A2": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_NE2A3": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_NE4BEG0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NE4BEG1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NE4BEG2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NE4BEG3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NE4C0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NE4C1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NE4C2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NE4C3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NW2A0": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_NW2A1": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_NW2A2": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_NW2A3": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_NW4A0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NW4A1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NW4A2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NW4A3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NW4END0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NW4END1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NW4END2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_NW4END3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SE2A0": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_SE2A1": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_SE2A2": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_SE2A3": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_SE4BEG0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SE4BEG1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SE4BEG2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SE4BEG3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SE4C0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SE4C1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SE4C2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SE4C3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SW2A0": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_SW2A1": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_SW2A2": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_SW2A3": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_SW4A0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SW4A1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SW4A2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SW4A3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SW4END0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SW4END1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SW4END2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_SW4END3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WL1END0": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_WL1END1": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_WL1END2": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_WL1END3": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_WR1END0": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_WR1END1": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_WR1END2": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_WR1END3": { + "cap": "25.000", + "res": "317.510" + }, + "CMT_PMV_WW2A0": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_WW2A1": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_WW2A2": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_WW2A3": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_WW2END0": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_WW2END1": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_WW2END2": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_WW2END3": { + "cap": "22.067", + "res": "317.510" + }, + "CMT_PMV_WW4A0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4A1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4A2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4A3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4B0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4B1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4B2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4B3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4C0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4C1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4C2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4C3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4END0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4END1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4END2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_PMV_WW4END3": { + "cap": "18.000", + "res": "317.510" + }, + "L_TERM_INT_PHASER_TO_IO_ICLK": null, + "L_TERM_INT_PHASER_TO_IO_ICLKDIV": null, + "L_TERM_INT_PHASER_TO_IO_OCLK": null, + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90": null, + "L_TERM_INT_PHASER_TO_IO_OCLKDIV": null + } } diff --git a/zynq7/tile_type_CMT_TOP_L_LOWER_B.json b/zynq7/tile_type_CMT_TOP_L_LOWER_B.json index 55db716..74a385a 100644 --- a/zynq7/tile_type_CMT_TOP_L_LOWER_B.json +++ b/zynq7/tile_type_CMT_TOP_L_LOWER_B.json @@ -2,1395 +2,5514 @@ "pips": { "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_LR_LOWER_B_CLKFBOUT2IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_MMCM11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_MMCM11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUTB->>CMT_L_LOWER_B_CLK_MMCM12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"0.000", + "res": "0.0" + }, "src_wire": "MMCM_CLK_FREQ_BB_NS2" }, "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3->>CMT_L_LOWER_B_CLK_FREQ_BB0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCM_CLK_FREQ_BB_NS3" }, "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF0_NS<<->>MMCM_CLK_FREQ_BB_NS0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQ_BB_NS0", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCM_CLK_FREQ_BB_REBUF0_NS" }, "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF1_NS<<->>MMCM_CLK_FREQ_BB_NS1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQ_BB_NS1", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCM_CLK_FREQ_BB_REBUF1_NS" }, "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF2_NS<<->>MMCM_CLK_FREQ_BB_NS2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQ_BB_NS2", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCM_CLK_FREQ_BB_REBUF2_NS" }, "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF3_NS<<->>MMCM_CLK_FREQ_BB_NS3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQ_BB_NS3", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCM_CLK_FREQ_BB_REBUF3_NS" } }, @@ -1399,172 +5518,1666 @@ "name": "X0Y0", "prefix": "MMCME2_ADV", "site_pins": { - "CLKFBIN": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "CLKFBOUT": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "CLKFBOUTB": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", - "CLKFBSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", - "CLKIN1": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "CLKIN2": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "CLKINSEL": "CMT_LR_LOWER_B_MMCM_CLKINSEL", - "CLKINSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", - "CLKOUT0": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "CLKOUT0B": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", - "CLKOUT1": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "CLKOUT1B": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", - "CLKOUT2": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "CLKOUT2B": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", - "CLKOUT3": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "CLKOUT3B": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", - "CLKOUT4": "CMT_LR_LOWER_B_MMCM_CLKOUT4", - "CLKOUT5": "CMT_LR_LOWER_B_MMCM_CLKOUT5", - "CLKOUT6": "CMT_LR_LOWER_B_MMCM_CLKOUT6", - "DADDR0": "CMT_LR_LOWER_B_MMCM_DADDR0", - "DADDR1": "CMT_LR_LOWER_B_MMCM_DADDR1", - "DADDR2": "CMT_LR_LOWER_B_MMCM_DADDR2", - "DADDR3": "CMT_LR_LOWER_B_MMCM_DADDR3", - "DADDR4": "CMT_LR_LOWER_B_MMCM_DADDR4", - "DADDR5": "CMT_LR_LOWER_B_MMCM_DADDR5", - "DADDR6": "CMT_LR_LOWER_B_MMCM_DADDR6", - "DCLK": "CMT_LR_LOWER_B_MMCM_DCLK", - "DEN": "CMT_LR_LOWER_B_MMCM_DEN", - "DI0": "CMT_LR_LOWER_B_MMCM_DI0", - "DI1": "CMT_LR_LOWER_B_MMCM_DI1", - "DI10": "CMT_LR_LOWER_B_MMCM_DI10", - "DI11": "CMT_LR_LOWER_B_MMCM_DI11", - "DI12": "CMT_LR_LOWER_B_MMCM_DI12", - "DI13": "CMT_LR_LOWER_B_MMCM_DI13", - "DI14": "CMT_LR_LOWER_B_MMCM_DI14", - "DI15": "CMT_LR_LOWER_B_MMCM_DI15", - "DI2": "CMT_LR_LOWER_B_MMCM_DI2", - "DI3": "CMT_LR_LOWER_B_MMCM_DI3", - "DI4": "CMT_LR_LOWER_B_MMCM_DI4", - "DI5": "CMT_LR_LOWER_B_MMCM_DI5", - "DI6": "CMT_LR_LOWER_B_MMCM_DI6", - "DI7": "CMT_LR_LOWER_B_MMCM_DI7", - "DI8": "CMT_LR_LOWER_B_MMCM_DI8", - "DI9": "CMT_LR_LOWER_B_MMCM_DI9", - "DO0": "CMT_LR_LOWER_B_MMCM_DO0", - "DO1": "CMT_LR_LOWER_B_MMCM_DO1", - "DO10": "CMT_LR_LOWER_B_MMCM_DO10", - "DO11": "CMT_LR_LOWER_B_MMCM_DO11", - "DO12": "CMT_LR_LOWER_B_MMCM_DO12", - "DO13": "CMT_LR_LOWER_B_MMCM_DO13", - "DO14": "CMT_LR_LOWER_B_MMCM_DO14", - "DO15": "CMT_LR_LOWER_B_MMCM_DO15", - "DO2": "CMT_LR_LOWER_B_MMCM_DO2", - "DO3": "CMT_LR_LOWER_B_MMCM_DO3", - "DO4": "CMT_LR_LOWER_B_MMCM_DO4", - "DO5": "CMT_LR_LOWER_B_MMCM_DO5", - "DO6": "CMT_LR_LOWER_B_MMCM_DO6", - "DO7": "CMT_LR_LOWER_B_MMCM_DO7", - "DO8": "CMT_LR_LOWER_B_MMCM_DO8", - "DO9": "CMT_LR_LOWER_B_MMCM_DO9", - "DRDY": "CMT_LR_LOWER_B_MMCM_DRDY", - "DWE": "CMT_LR_LOWER_B_MMCM_DWE", - "LOCKED": "CMT_LR_LOWER_B_MMCM_LOCKED", - "PSCLK": "CMT_LR_LOWER_B_MMCM_PSCLK", - "PSDONE": "CMT_LR_LOWER_B_MMCM_PSDONE", - "PSEN": "CMT_LR_LOWER_B_MMCM_PSEN", - "PSINCDEC": "CMT_LR_LOWER_B_MMCM_PSINCDEC", - "PWRDWN": "CMT_LR_LOWER_B_MMCM_PWRDWN", - "RST": "CMT_LR_LOWER_B_MMCM_RST", - "TESTIN0": "CMT_LR_LOWER_B_MMCM_TESTIN0", - "TESTIN1": "CMT_LR_LOWER_B_MMCM_TESTIN1", - "TESTIN10": "CMT_LR_LOWER_B_MMCM_TESTIN10", - "TESTIN11": "CMT_LR_LOWER_B_MMCM_TESTIN11", - "TESTIN12": "CMT_LR_LOWER_B_MMCM_TESTIN12", - "TESTIN13": "CMT_LR_LOWER_B_MMCM_TESTIN13", - "TESTIN14": "CMT_LR_LOWER_B_MMCM_TESTIN14", - "TESTIN15": "CMT_LR_LOWER_B_MMCM_TESTIN15", - "TESTIN16": "CMT_LR_LOWER_B_MMCM_TESTIN16", - "TESTIN17": "CMT_LR_LOWER_B_MMCM_TESTIN17", - "TESTIN18": "CMT_LR_LOWER_B_MMCM_TESTIN18", - "TESTIN19": "CMT_LR_LOWER_B_MMCM_TESTIN19", - "TESTIN2": "CMT_LR_LOWER_B_MMCM_TESTIN2", - "TESTIN20": "CMT_LR_LOWER_B_MMCM_TESTIN20", - "TESTIN21": "CMT_LR_LOWER_B_MMCM_TESTIN21", - "TESTIN22": "CMT_LR_LOWER_B_MMCM_TESTIN22", - "TESTIN23": "CMT_LR_LOWER_B_MMCM_TESTIN23", - "TESTIN24": "CMT_LR_LOWER_B_MMCM_TESTIN24", - "TESTIN25": "CMT_LR_LOWER_B_MMCM_TESTIN25", - "TESTIN26": "CMT_LR_LOWER_B_MMCM_TESTIN26", - "TESTIN27": "CMT_LR_LOWER_B_MMCM_TESTIN27", - "TESTIN28": "CMT_LR_LOWER_B_MMCM_TESTIN28", - "TESTIN29": "CMT_LR_LOWER_B_MMCM_TESTIN29", - "TESTIN3": "CMT_LR_LOWER_B_MMCM_TESTIN3", - "TESTIN30": "CMT_LR_LOWER_B_MMCM_TESTIN30", - "TESTIN31": "CMT_LR_LOWER_B_MMCM_TESTIN31", - "TESTIN4": "CMT_LR_LOWER_B_MMCM_TESTIN4", - "TESTIN5": "CMT_LR_LOWER_B_MMCM_TESTIN5", - "TESTIN6": "CMT_LR_LOWER_B_MMCM_TESTIN6", - "TESTIN7": "CMT_LR_LOWER_B_MMCM_TESTIN7", - "TESTIN8": "CMT_LR_LOWER_B_MMCM_TESTIN8", - "TESTIN9": "CMT_LR_LOWER_B_MMCM_TESTIN9", - "TESTOUT0": "CMT_LR_LOWER_B_MMCM_TESTOUT0", - "TESTOUT1": "CMT_LR_LOWER_B_MMCM_TESTOUT1", - "TESTOUT10": "CMT_LR_LOWER_B_MMCM_TESTOUT10", - "TESTOUT11": "CMT_LR_LOWER_B_MMCM_TESTOUT11", - "TESTOUT12": "CMT_LR_LOWER_B_MMCM_TESTOUT12", - "TESTOUT13": "CMT_LR_LOWER_B_MMCM_TESTOUT13", - "TESTOUT14": "CMT_LR_LOWER_B_MMCM_TESTOUT14", - "TESTOUT15": "CMT_LR_LOWER_B_MMCM_TESTOUT15", - "TESTOUT16": "CMT_LR_LOWER_B_MMCM_TESTOUT16", - "TESTOUT17": "CMT_LR_LOWER_B_MMCM_TESTOUT17", - "TESTOUT18": "CMT_LR_LOWER_B_MMCM_TESTOUT18", - "TESTOUT19": "CMT_LR_LOWER_B_MMCM_TESTOUT19", - "TESTOUT2": "CMT_LR_LOWER_B_MMCM_TESTOUT2", - "TESTOUT20": "CMT_LR_LOWER_B_MMCM_TESTOUT20", - "TESTOUT21": "CMT_LR_LOWER_B_MMCM_TESTOUT21", - "TESTOUT22": "CMT_LR_LOWER_B_MMCM_TESTOUT22", - "TESTOUT23": "CMT_LR_LOWER_B_MMCM_TESTOUT23", - "TESTOUT24": "CMT_LR_LOWER_B_MMCM_TESTOUT24", - "TESTOUT25": "CMT_LR_LOWER_B_MMCM_TESTOUT25", - "TESTOUT26": "CMT_LR_LOWER_B_MMCM_TESTOUT26", - "TESTOUT27": "CMT_LR_LOWER_B_MMCM_TESTOUT27", - "TESTOUT28": "CMT_LR_LOWER_B_MMCM_TESTOUT28", - "TESTOUT29": "CMT_LR_LOWER_B_MMCM_TESTOUT29", - "TESTOUT3": "CMT_LR_LOWER_B_MMCM_TESTOUT3", - "TESTOUT30": "CMT_LR_LOWER_B_MMCM_TESTOUT30", - "TESTOUT31": "CMT_LR_LOWER_B_MMCM_TESTOUT31", - "TESTOUT32": "CMT_LR_LOWER_B_MMCM_TESTOUT32", - "TESTOUT33": "CMT_LR_LOWER_B_MMCM_TESTOUT33", - "TESTOUT34": "CMT_LR_LOWER_B_MMCM_TESTOUT34", - "TESTOUT35": "CMT_LR_LOWER_B_MMCM_TESTOUT35", - "TESTOUT36": "CMT_LR_LOWER_B_MMCM_TESTOUT36", - "TESTOUT37": "CMT_LR_LOWER_B_MMCM_TESTOUT37", - "TESTOUT38": "CMT_LR_LOWER_B_MMCM_TESTOUT38", - "TESTOUT39": "CMT_LR_LOWER_B_MMCM_TESTOUT39", - "TESTOUT4": "CMT_LR_LOWER_B_MMCM_TESTOUT4", - "TESTOUT40": "CMT_LR_LOWER_B_MMCM_TESTOUT40", - "TESTOUT41": "CMT_LR_LOWER_B_MMCM_TESTOUT41", - "TESTOUT42": "CMT_LR_LOWER_B_MMCM_TESTOUT42", - "TESTOUT43": "CMT_LR_LOWER_B_MMCM_TESTOUT43", - "TESTOUT44": "CMT_LR_LOWER_B_MMCM_TESTOUT44", - "TESTOUT45": "CMT_LR_LOWER_B_MMCM_TESTOUT45", - "TESTOUT46": "CMT_LR_LOWER_B_MMCM_TESTOUT46", - "TESTOUT47": "CMT_LR_LOWER_B_MMCM_TESTOUT47", - "TESTOUT48": "CMT_LR_LOWER_B_MMCM_TESTOUT48", - "TESTOUT49": "CMT_LR_LOWER_B_MMCM_TESTOUT49", - "TESTOUT5": "CMT_LR_LOWER_B_MMCM_TESTOUT5", - "TESTOUT50": "CMT_LR_LOWER_B_MMCM_TESTOUT50", - "TESTOUT51": "CMT_LR_LOWER_B_MMCM_TESTOUT51", - "TESTOUT52": "CMT_LR_LOWER_B_MMCM_TESTOUT52", - "TESTOUT53": "CMT_LR_LOWER_B_MMCM_TESTOUT53", - "TESTOUT54": "CMT_LR_LOWER_B_MMCM_TESTOUT54", - "TESTOUT55": "CMT_LR_LOWER_B_MMCM_TESTOUT55", - "TESTOUT56": "CMT_LR_LOWER_B_MMCM_TESTOUT56", - "TESTOUT57": "CMT_LR_LOWER_B_MMCM_TESTOUT57", - "TESTOUT58": "CMT_LR_LOWER_B_MMCM_TESTOUT58", - "TESTOUT59": "CMT_LR_LOWER_B_MMCM_TESTOUT59", - "TESTOUT6": "CMT_LR_LOWER_B_MMCM_TESTOUT6", - "TESTOUT60": "CMT_LR_LOWER_B_MMCM_TESTOUT60", - "TESTOUT61": "CMT_LR_LOWER_B_MMCM_TESTOUT61", - "TESTOUT62": "CMT_LR_LOWER_B_MMCM_TESTOUT62", - "TESTOUT63": "CMT_LR_LOWER_B_MMCM_TESTOUT63", - "TESTOUT7": "CMT_LR_LOWER_B_MMCM_TESTOUT7", - "TESTOUT8": "CMT_LR_LOWER_B_MMCM_TESTOUT8", - "TESTOUT9": "CMT_LR_LOWER_B_MMCM_TESTOUT9", - "TMUXOUT": "CMT_LR_LOWER_B_MMCM_TMUXOUT" + "CLKFBIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CLKFBOUT": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" + }, + "CLKFBOUTB": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB" + }, + "CLKFBSTOPPED": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED" + }, + "CLKIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CLKIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" + }, + "CLKINSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_CLKINSEL" + }, + "CLKINSTOPPED": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED" + }, + "CLKOUT0": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0" + }, + "CLKOUT0B": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0B" + }, + "CLKOUT1": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1" + }, + "CLKOUT1B": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1B" + }, + "CLKOUT2": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2" + }, + "CLKOUT2B": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2B" + }, + "CLKOUT3": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3" + }, + "CLKOUT3B": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3B" + }, + "CLKOUT4": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT4" + }, + "CLKOUT5": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT5" + }, + "CLKOUT6": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT6" + }, + "DADDR0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_DADDR0" + }, + "DADDR1": { + "cap": "0.000", + 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"CMT_LR_LOWER_B_MMCM_CLKOUT1B", - "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "CMT_LR_LOWER_B_MMCM_CLKOUT2B", - "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "CMT_LR_LOWER_B_MMCM_CLKOUT3B", - "CMT_LR_LOWER_B_MMCM_CLKOUT4", - "CMT_LR_LOWER_B_MMCM_CLKOUT5", - "CMT_LR_LOWER_B_MMCM_CLKOUT6", - "CMT_LR_LOWER_B_MMCM_DADDR0", - "CMT_LR_LOWER_B_MMCM_DADDR1", - "CMT_LR_LOWER_B_MMCM_DADDR2", - "CMT_LR_LOWER_B_MMCM_DADDR3", - "CMT_LR_LOWER_B_MMCM_DADDR4", - "CMT_LR_LOWER_B_MMCM_DADDR5", - "CMT_LR_LOWER_B_MMCM_DADDR6", - "CMT_LR_LOWER_B_MMCM_DCLK", - "CMT_LR_LOWER_B_MMCM_DEN", - "CMT_LR_LOWER_B_MMCM_DI0", - "CMT_LR_LOWER_B_MMCM_DI1", - "CMT_LR_LOWER_B_MMCM_DI10", - "CMT_LR_LOWER_B_MMCM_DI11", - "CMT_LR_LOWER_B_MMCM_DI12", - "CMT_LR_LOWER_B_MMCM_DI13", - "CMT_LR_LOWER_B_MMCM_DI14", - "CMT_LR_LOWER_B_MMCM_DI15", - "CMT_LR_LOWER_B_MMCM_DI2", - "CMT_LR_LOWER_B_MMCM_DI3", - "CMT_LR_LOWER_B_MMCM_DI4", - "CMT_LR_LOWER_B_MMCM_DI5", - "CMT_LR_LOWER_B_MMCM_DI6", - "CMT_LR_LOWER_B_MMCM_DI7", - "CMT_LR_LOWER_B_MMCM_DI8", - "CMT_LR_LOWER_B_MMCM_DI9", - "CMT_LR_LOWER_B_MMCM_DO0", - "CMT_LR_LOWER_B_MMCM_DO1", - "CMT_LR_LOWER_B_MMCM_DO10", - "CMT_LR_LOWER_B_MMCM_DO11", - "CMT_LR_LOWER_B_MMCM_DO12", - "CMT_LR_LOWER_B_MMCM_DO13", - "CMT_LR_LOWER_B_MMCM_DO14", - "CMT_LR_LOWER_B_MMCM_DO15", - "CMT_LR_LOWER_B_MMCM_DO2", - "CMT_LR_LOWER_B_MMCM_DO3", - "CMT_LR_LOWER_B_MMCM_DO4", - "CMT_LR_LOWER_B_MMCM_DO5", - "CMT_LR_LOWER_B_MMCM_DO6", - "CMT_LR_LOWER_B_MMCM_DO7", - "CMT_LR_LOWER_B_MMCM_DO8", - "CMT_LR_LOWER_B_MMCM_DO9", - "CMT_LR_LOWER_B_MMCM_DRDY", - "CMT_LR_LOWER_B_MMCM_DWE", - "CMT_LR_LOWER_B_MMCM_LOCKED", - "CMT_LR_LOWER_B_MMCM_PSCLK", - "CMT_LR_LOWER_B_MMCM_PSDONE", - "CMT_LR_LOWER_B_MMCM_PSEN", - "CMT_LR_LOWER_B_MMCM_PSINCDEC", - "CMT_LR_LOWER_B_MMCM_PWRDWN", - "CMT_LR_LOWER_B_MMCM_RST", - "CMT_LR_LOWER_B_MMCM_TESTIN0", - "CMT_LR_LOWER_B_MMCM_TESTIN1", - "CMT_LR_LOWER_B_MMCM_TESTIN10", - "CMT_LR_LOWER_B_MMCM_TESTIN11", - "CMT_LR_LOWER_B_MMCM_TESTIN12", - "CMT_LR_LOWER_B_MMCM_TESTIN13", - "CMT_LR_LOWER_B_MMCM_TESTIN14", - "CMT_LR_LOWER_B_MMCM_TESTIN15", - "CMT_LR_LOWER_B_MMCM_TESTIN16", - "CMT_LR_LOWER_B_MMCM_TESTIN17", - "CMT_LR_LOWER_B_MMCM_TESTIN18", - "CMT_LR_LOWER_B_MMCM_TESTIN19", - "CMT_LR_LOWER_B_MMCM_TESTIN2", - "CMT_LR_LOWER_B_MMCM_TESTIN20", - "CMT_LR_LOWER_B_MMCM_TESTIN21", - "CMT_LR_LOWER_B_MMCM_TESTIN22", - "CMT_LR_LOWER_B_MMCM_TESTIN23", - "CMT_LR_LOWER_B_MMCM_TESTIN24", - "CMT_LR_LOWER_B_MMCM_TESTIN25", - "CMT_LR_LOWER_B_MMCM_TESTIN26", - "CMT_LR_LOWER_B_MMCM_TESTIN27", - "CMT_LR_LOWER_B_MMCM_TESTIN28", - "CMT_LR_LOWER_B_MMCM_TESTIN29", - "CMT_LR_LOWER_B_MMCM_TESTIN3", - "CMT_LR_LOWER_B_MMCM_TESTIN30", - "CMT_LR_LOWER_B_MMCM_TESTIN31", - "CMT_LR_LOWER_B_MMCM_TESTIN4", - "CMT_LR_LOWER_B_MMCM_TESTIN5", - "CMT_LR_LOWER_B_MMCM_TESTIN6", - "CMT_LR_LOWER_B_MMCM_TESTIN7", - "CMT_LR_LOWER_B_MMCM_TESTIN8", - "CMT_LR_LOWER_B_MMCM_TESTIN9", - "CMT_LR_LOWER_B_MMCM_TESTOUT0", - "CMT_LR_LOWER_B_MMCM_TESTOUT1", - "CMT_LR_LOWER_B_MMCM_TESTOUT10", - "CMT_LR_LOWER_B_MMCM_TESTOUT11", - "CMT_LR_LOWER_B_MMCM_TESTOUT12", - "CMT_LR_LOWER_B_MMCM_TESTOUT13", - "CMT_LR_LOWER_B_MMCM_TESTOUT14", - "CMT_LR_LOWER_B_MMCM_TESTOUT15", - "CMT_LR_LOWER_B_MMCM_TESTOUT16", - "CMT_LR_LOWER_B_MMCM_TESTOUT17", - "CMT_LR_LOWER_B_MMCM_TESTOUT18", - "CMT_LR_LOWER_B_MMCM_TESTOUT19", - "CMT_LR_LOWER_B_MMCM_TESTOUT2", - "CMT_LR_LOWER_B_MMCM_TESTOUT20", - "CMT_LR_LOWER_B_MMCM_TESTOUT21", - "CMT_LR_LOWER_B_MMCM_TESTOUT22", - "CMT_LR_LOWER_B_MMCM_TESTOUT23", - "CMT_LR_LOWER_B_MMCM_TESTOUT24", - "CMT_LR_LOWER_B_MMCM_TESTOUT25", - "CMT_LR_LOWER_B_MMCM_TESTOUT26", - "CMT_LR_LOWER_B_MMCM_TESTOUT27", - "CMT_LR_LOWER_B_MMCM_TESTOUT28", - "CMT_LR_LOWER_B_MMCM_TESTOUT29", - "CMT_LR_LOWER_B_MMCM_TESTOUT3", - "CMT_LR_LOWER_B_MMCM_TESTOUT30", - "CMT_LR_LOWER_B_MMCM_TESTOUT31", - "CMT_LR_LOWER_B_MMCM_TESTOUT32", - "CMT_LR_LOWER_B_MMCM_TESTOUT33", - "CMT_LR_LOWER_B_MMCM_TESTOUT34", - "CMT_LR_LOWER_B_MMCM_TESTOUT35", - "CMT_LR_LOWER_B_MMCM_TESTOUT36", - "CMT_LR_LOWER_B_MMCM_TESTOUT37", - "CMT_LR_LOWER_B_MMCM_TESTOUT38", - "CMT_LR_LOWER_B_MMCM_TESTOUT39", - "CMT_LR_LOWER_B_MMCM_TESTOUT4", - "CMT_LR_LOWER_B_MMCM_TESTOUT40", - "CMT_LR_LOWER_B_MMCM_TESTOUT41", - "CMT_LR_LOWER_B_MMCM_TESTOUT42", - "CMT_LR_LOWER_B_MMCM_TESTOUT43", - "CMT_LR_LOWER_B_MMCM_TESTOUT44", - "CMT_LR_LOWER_B_MMCM_TESTOUT45", - "CMT_LR_LOWER_B_MMCM_TESTOUT46", - "CMT_LR_LOWER_B_MMCM_TESTOUT47", - "CMT_LR_LOWER_B_MMCM_TESTOUT48", - "CMT_LR_LOWER_B_MMCM_TESTOUT49", - "CMT_LR_LOWER_B_MMCM_TESTOUT5", - "CMT_LR_LOWER_B_MMCM_TESTOUT50", - "CMT_LR_LOWER_B_MMCM_TESTOUT51", - "CMT_LR_LOWER_B_MMCM_TESTOUT52", - "CMT_LR_LOWER_B_MMCM_TESTOUT53", - "CMT_LR_LOWER_B_MMCM_TESTOUT54", - "CMT_LR_LOWER_B_MMCM_TESTOUT55", - "CMT_LR_LOWER_B_MMCM_TESTOUT56", - "CMT_LR_LOWER_B_MMCM_TESTOUT57", - "CMT_LR_LOWER_B_MMCM_TESTOUT58", - "CMT_LR_LOWER_B_MMCM_TESTOUT59", - "CMT_LR_LOWER_B_MMCM_TESTOUT6", - "CMT_LR_LOWER_B_MMCM_TESTOUT60", - "CMT_LR_LOWER_B_MMCM_TESTOUT61", - "CMT_LR_LOWER_B_MMCM_TESTOUT62", - "CMT_LR_LOWER_B_MMCM_TESTOUT63", - "CMT_LR_LOWER_B_MMCM_TESTOUT7", - "CMT_LR_LOWER_B_MMCM_TESTOUT8", - "CMT_LR_LOWER_B_MMCM_TESTOUT9", - "CMT_LR_LOWER_B_MMCM_TMUXOUT", - "CMT_L_LOWER_B_CLK_FREQ_BB0", - "CMT_L_LOWER_B_CLK_FREQ_BB1", - "CMT_L_LOWER_B_CLK_FREQ_BB2", - "CMT_L_LOWER_B_CLK_FREQ_BB3", - "CMT_L_LOWER_B_CLK_IN1_HCLK", - "CMT_L_LOWER_B_CLK_IN1_INT", - "CMT_L_LOWER_B_CLK_IN2_HCLK", - "CMT_L_LOWER_B_CLK_IN2_INT", - "CMT_L_LOWER_B_CLK_IN3_HCLK", - "CMT_L_LOWER_B_CLK_IN3_INT", - "CMT_L_LOWER_B_CLK_MMCM0", - "CMT_L_LOWER_B_CLK_MMCM1", - "CMT_L_LOWER_B_CLK_MMCM10", - "CMT_L_LOWER_B_CLK_MMCM11", - "CMT_L_LOWER_B_CLK_MMCM12", - "CMT_L_LOWER_B_CLK_MMCM13", - "CMT_L_LOWER_B_CLK_MMCM2", - "CMT_L_LOWER_B_CLK_MMCM3", - "CMT_L_LOWER_B_CLK_MMCM4", - "CMT_L_LOWER_B_CLK_MMCM5", - "CMT_L_LOWER_B_CLK_MMCM6", - "CMT_L_LOWER_B_CLK_MMCM7", - "CMT_L_LOWER_B_CLK_MMCM8", - "CMT_L_LOWER_B_CLK_MMCM9", - "CMT_L_LOWER_B_CLK_PERF0", - "CMT_L_LOWER_B_CLK_PERF1", - "CMT_L_LOWER_B_CLK_PERF2", - "CMT_L_LOWER_B_CLK_PERF3", - "CMT_MMCM_A_RDCLK_TOFIFO", - "CMT_MMCM_A_RDEN_TOFIFO", - "CMT_MMCM_A_WRCLK_TOFIFO", - "CMT_MMCM_A_WREN_TOFIFO", - "CMT_MMCM_DQS_TO_PHASERA", - "CMT_MMCM_PHASERA_CTSBUS0", - "CMT_MMCM_PHASERA_CTSBUS1", - "CMT_MMCM_PHASERA_DQSBUS0", - "CMT_MMCM_PHASERA_DQSBUS1", - "CMT_MMCM_PHASERA_DTSBUS0", - "CMT_MMCM_PHASERA_DTSBUS1", - "CMT_MMCM_PHASERREF0", - "CMT_MMCM_PHASERREF1", - "CMT_MMCM_PHASERREF_ABOVE0", - "CMT_MMCM_PHASERREF_ABOVE1", - "CMT_MMCM_PHASERREF_BELOW0", - "CMT_MMCM_PHASERREF_BELOW1", - "CMT_MMCM_PHASER_IN_A_ICLK", - "CMT_MMCM_PHASER_IN_A_ICLKDIV", - "CMT_MMCM_PHASER_IN_B_ICLK", - "CMT_MMCM_PHASER_IN_B_ICLKDIV", - "CMT_MMCM_PHASER_OUT_A_OCLK", - "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", - "CMT_MMCM_PHASER_OUT_A_OCLKDIV", - "CMT_MMCM_PHASER_OUT_B_OCLK", - "CMT_MMCM_PHASER_OUT_B_OCLK1X_90", - "CMT_MMCM_PHASER_OUT_B_OCLKDIV", - "CMT_MMCM_PHYCTRL_SYNC_BB_DN", - "CMT_MMCM_PHYCTRL_SYNC_BB_UP", - "CMT_PHASER_A_ICLKDIV_TOIOI", - "CMT_PHASER_A_ICLK_TOIOI", - "CMT_PHASER_A_OCLK90_TOIOI", - "CMT_PHASER_A_OCLKDIV_TOIOI", - "CMT_PHASER_A_OCLK_TOIOI", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_BLOCK_OUTS_L_B0_10", - "CMT_TOP_BLOCK_OUTS_L_B0_11", - "CMT_TOP_BLOCK_OUTS_L_B0_12", - "CMT_TOP_BLOCK_OUTS_L_B0_13", - "CMT_TOP_BLOCK_OUTS_L_B0_14", - "CMT_TOP_BLOCK_OUTS_L_B0_15", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_BLOCK_OUTS_L_B0_9", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_BLOCK_OUTS_L_B1_10", - "CMT_TOP_BLOCK_OUTS_L_B1_11", - "CMT_TOP_BLOCK_OUTS_L_B1_12", - "CMT_TOP_BLOCK_OUTS_L_B1_13", - "CMT_TOP_BLOCK_OUTS_L_B1_14", - "CMT_TOP_BLOCK_OUTS_L_B1_15", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_TOP_BLOCK_OUTS_L_B2_12", - "CMT_TOP_BLOCK_OUTS_L_B2_13", - "CMT_TOP_BLOCK_OUTS_L_B2_14", - "CMT_TOP_BLOCK_OUTS_L_B2_15", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_BLOCK_OUTS_L_B3_12", - "CMT_TOP_BLOCK_OUTS_L_B3_13", - "CMT_TOP_BLOCK_OUTS_L_B3_14", - "CMT_TOP_BLOCK_OUTS_L_B3_15", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_BYP0_0", - "CMT_TOP_BYP0_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_BYP0_11", - "CMT_TOP_BYP0_12", - "CMT_TOP_BYP0_13", - "CMT_TOP_BYP0_14", - "CMT_TOP_BYP0_15", - "CMT_TOP_BYP0_2", - "CMT_TOP_BYP0_3", - "CMT_TOP_BYP0_4", - "CMT_TOP_BYP0_5", - "CMT_TOP_BYP0_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_BYP0_8", - "CMT_TOP_BYP0_9", - "CMT_TOP_BYP1_0", - "CMT_TOP_BYP1_1", - "CMT_TOP_BYP1_10", - "CMT_TOP_BYP1_11", - "CMT_TOP_BYP1_12", - "CMT_TOP_BYP1_13", - "CMT_TOP_BYP1_14", - "CMT_TOP_BYP1_15", - "CMT_TOP_BYP1_2", - "CMT_TOP_BYP1_3", - "CMT_TOP_BYP1_4", - "CMT_TOP_BYP1_5", - "CMT_TOP_BYP1_6", - "CMT_TOP_BYP1_7", - "CMT_TOP_BYP1_8", - "CMT_TOP_BYP1_9", - "CMT_TOP_BYP2_0", - "CMT_TOP_BYP2_1", - "CMT_TOP_BYP2_10", - "CMT_TOP_BYP2_11", - "CMT_TOP_BYP2_12", - "CMT_TOP_BYP2_13", - "CMT_TOP_BYP2_14", - "CMT_TOP_BYP2_15", - "CMT_TOP_BYP2_2", - "CMT_TOP_BYP2_3", - "CMT_TOP_BYP2_4", - "CMT_TOP_BYP2_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_BYP3_0", - "CMT_TOP_BYP3_1", - "CMT_TOP_BYP3_10", - "CMT_TOP_BYP3_11", - "CMT_TOP_BYP3_12", - "CMT_TOP_BYP3_13", - "CMT_TOP_BYP3_14", - "CMT_TOP_BYP3_15", - "CMT_TOP_BYP3_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_BYP3_4", - "CMT_TOP_BYP3_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_BYP3_8", - "CMT_TOP_BYP3_9", - "CMT_TOP_BYP4_0", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP4_10", - "CMT_TOP_BYP4_11", - "CMT_TOP_BYP4_12", - "CMT_TOP_BYP4_13", - "CMT_TOP_BYP4_14", - "CMT_TOP_BYP4_15", - "CMT_TOP_BYP4_2", - "CMT_TOP_BYP4_3", - "CMT_TOP_BYP4_4", - "CMT_TOP_BYP4_5", - "CMT_TOP_BYP4_6", - "CMT_TOP_BYP4_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_BYP4_9", - "CMT_TOP_BYP5_0", - "CMT_TOP_BYP5_1", - "CMT_TOP_BYP5_10", - "CMT_TOP_BYP5_11", - "CMT_TOP_BYP5_12", - "CMT_TOP_BYP5_13", - "CMT_TOP_BYP5_14", - "CMT_TOP_BYP5_15", - "CMT_TOP_BYP5_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_BYP5_4", - "CMT_TOP_BYP5_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_BYP5_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_BYP5_9", - "CMT_TOP_BYP6_0", - "CMT_TOP_BYP6_1", - "CMT_TOP_BYP6_10", - "CMT_TOP_BYP6_11", - "CMT_TOP_BYP6_12", - "CMT_TOP_BYP6_13", - "CMT_TOP_BYP6_14", - "CMT_TOP_BYP6_15", - "CMT_TOP_BYP6_2", - "CMT_TOP_BYP6_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_BYP6_5", - "CMT_TOP_BYP6_6", - "CMT_TOP_BYP6_7", - "CMT_TOP_BYP6_8", - "CMT_TOP_BYP6_9", - "CMT_TOP_BYP7_0", - "CMT_TOP_BYP7_1", - "CMT_TOP_BYP7_10", - "CMT_TOP_BYP7_11", - "CMT_TOP_BYP7_12", - "CMT_TOP_BYP7_13", - "CMT_TOP_BYP7_14", - "CMT_TOP_BYP7_15", - "CMT_TOP_BYP7_2", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP7_4", - "CMT_TOP_BYP7_5", - "CMT_TOP_BYP7_6", - "CMT_TOP_BYP7_7", - "CMT_TOP_BYP7_8", - "CMT_TOP_BYP7_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_CLK0_1", - "CMT_TOP_CLK0_10", - "CMT_TOP_CLK0_11", - "CMT_TOP_CLK0_12", - "CMT_TOP_CLK0_13", - "CMT_TOP_CLK0_14", - "CMT_TOP_CLK0_15", - "CMT_TOP_CLK0_2", - "CMT_TOP_CLK0_3", - "CMT_TOP_CLK0_4", - "CMT_TOP_CLK0_5", - "CMT_TOP_CLK0_6", - "CMT_TOP_CLK0_7", - "CMT_TOP_CLK0_8", - "CMT_TOP_CLK0_9", - "CMT_TOP_CLK1_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_CLK1_10", - "CMT_TOP_CLK1_11", - "CMT_TOP_CLK1_12", - "CMT_TOP_CLK1_13", - "CMT_TOP_CLK1_14", - "CMT_TOP_CLK1_15", - "CMT_TOP_CLK1_2", - "CMT_TOP_CLK1_3", - "CMT_TOP_CLK1_4", - "CMT_TOP_CLK1_5", - "CMT_TOP_CLK1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_CLK1_8", - "CMT_TOP_CLK1_9", - "CMT_TOP_CTRL0_0", - "CMT_TOP_CTRL0_1", - "CMT_TOP_CTRL0_10", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CTRL0_12", - "CMT_TOP_CTRL0_13", - "CMT_TOP_CTRL0_14", - "CMT_TOP_CTRL0_15", - "CMT_TOP_CTRL0_2", - "CMT_TOP_CTRL0_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_CTRL0_5", - "CMT_TOP_CTRL0_6", - "CMT_TOP_CTRL0_7", - "CMT_TOP_CTRL0_8", - "CMT_TOP_CTRL0_9", - "CMT_TOP_CTRL1_0", - "CMT_TOP_CTRL1_1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_CTRL1_11", - "CMT_TOP_CTRL1_12", - "CMT_TOP_CTRL1_13", - "CMT_TOP_CTRL1_14", - "CMT_TOP_CTRL1_15", - "CMT_TOP_CTRL1_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_CTRL1_4", - "CMT_TOP_CTRL1_5", - "CMT_TOP_CTRL1_6", - "CMT_TOP_CTRL1_7", - "CMT_TOP_CTRL1_8", - "CMT_TOP_CTRL1_9", - "CMT_TOP_EE2A0_0", - "CMT_TOP_EE2A0_1", - "CMT_TOP_EE2A0_10", - "CMT_TOP_EE2A0_11", - "CMT_TOP_EE2A0_12", - "CMT_TOP_EE2A0_13", - "CMT_TOP_EE2A0_14", - "CMT_TOP_EE2A0_15", - "CMT_TOP_EE2A0_2", - "CMT_TOP_EE2A0_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_EE2A0_6", - "CMT_TOP_EE2A0_7", - "CMT_TOP_EE2A0_8", - "CMT_TOP_EE2A0_9", - "CMT_TOP_EE2A1_0", - "CMT_TOP_EE2A1_1", - "CMT_TOP_EE2A1_10", - "CMT_TOP_EE2A1_11", - "CMT_TOP_EE2A1_12", - "CMT_TOP_EE2A1_13", - "CMT_TOP_EE2A1_14", - "CMT_TOP_EE2A1_15", - "CMT_TOP_EE2A1_2", - "CMT_TOP_EE2A1_3", - "CMT_TOP_EE2A1_4", - "CMT_TOP_EE2A1_5", - "CMT_TOP_EE2A1_6", - "CMT_TOP_EE2A1_7", - "CMT_TOP_EE2A1_8", - "CMT_TOP_EE2A1_9", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_1", - "CMT_TOP_EE2A2_10", - "CMT_TOP_EE2A2_11", - "CMT_TOP_EE2A2_12", - "CMT_TOP_EE2A2_13", - "CMT_TOP_EE2A2_14", - "CMT_TOP_EE2A2_15", - "CMT_TOP_EE2A2_2", - "CMT_TOP_EE2A2_3", - "CMT_TOP_EE2A2_4", - "CMT_TOP_EE2A2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_EE2A2_7", - "CMT_TOP_EE2A2_8", - "CMT_TOP_EE2A2_9", - "CMT_TOP_EE2A3_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_EE2A3_10", - "CMT_TOP_EE2A3_11", - "CMT_TOP_EE2A3_12", - "CMT_TOP_EE2A3_13", - "CMT_TOP_EE2A3_14", - "CMT_TOP_EE2A3_15", - "CMT_TOP_EE2A3_2", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2A3_4", - "CMT_TOP_EE2A3_5", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE2A3_8", - "CMT_TOP_EE2A3_9", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_EE2BEG0_11", - "CMT_TOP_EE2BEG0_12", - "CMT_TOP_EE2BEG0_13", - "CMT_TOP_EE2BEG0_14", - "CMT_TOP_EE2BEG0_15", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_EE2BEG0_9", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_EE2BEG1_12", - "CMT_TOP_EE2BEG1_13", - "CMT_TOP_EE2BEG1_14", - "CMT_TOP_EE2BEG1_15", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE2BEG2_12", - "CMT_TOP_EE2BEG2_13", - "CMT_TOP_EE2BEG2_14", - "CMT_TOP_EE2BEG2_15", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_EE2BEG3_12", - "CMT_TOP_EE2BEG3_13", - "CMT_TOP_EE2BEG3_14", - "CMT_TOP_EE2BEG3_15", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE2BEG3_9", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_EE4A0_10", - "CMT_TOP_EE4A0_11", - "CMT_TOP_EE4A0_12", - "CMT_TOP_EE4A0_13", - "CMT_TOP_EE4A0_14", - "CMT_TOP_EE4A0_15", - "CMT_TOP_EE4A0_2", - "CMT_TOP_EE4A0_3", - "CMT_TOP_EE4A0_4", - "CMT_TOP_EE4A0_5", - "CMT_TOP_EE4A0_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4A0_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_EE4A1_1", - "CMT_TOP_EE4A1_10", - "CMT_TOP_EE4A1_11", - "CMT_TOP_EE4A1_12", - "CMT_TOP_EE4A1_13", - "CMT_TOP_EE4A1_14", - "CMT_TOP_EE4A1_15", - "CMT_TOP_EE4A1_2", - "CMT_TOP_EE4A1_3", - "CMT_TOP_EE4A1_4", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4A1_8", - "CMT_TOP_EE4A1_9", - "CMT_TOP_EE4A2_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_EE4A2_10", - "CMT_TOP_EE4A2_11", - "CMT_TOP_EE4A2_12", - "CMT_TOP_EE4A2_13", - "CMT_TOP_EE4A2_14", - "CMT_TOP_EE4A2_15", - "CMT_TOP_EE4A2_2", - "CMT_TOP_EE4A2_3", - "CMT_TOP_EE4A2_4", - "CMT_TOP_EE4A2_5", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE4A2_7", - "CMT_TOP_EE4A2_8", - "CMT_TOP_EE4A2_9", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4A3_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_EE4A3_11", - "CMT_TOP_EE4A3_12", - "CMT_TOP_EE4A3_13", - "CMT_TOP_EE4A3_14", - "CMT_TOP_EE4A3_15", - "CMT_TOP_EE4A3_2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_EE4A3_5", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE4A3_7", - "CMT_TOP_EE4A3_8", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EE4B0_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_EE4B0_10", - "CMT_TOP_EE4B0_11", - "CMT_TOP_EE4B0_12", - "CMT_TOP_EE4B0_13", - "CMT_TOP_EE4B0_14", - "CMT_TOP_EE4B0_15", - "CMT_TOP_EE4B0_2", - "CMT_TOP_EE4B0_3", - "CMT_TOP_EE4B0_4", - "CMT_TOP_EE4B0_5", - "CMT_TOP_EE4B0_6", - "CMT_TOP_EE4B0_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_EE4B0_9", - "CMT_TOP_EE4B1_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_EE4B1_10", - "CMT_TOP_EE4B1_11", - "CMT_TOP_EE4B1_12", - "CMT_TOP_EE4B1_13", - "CMT_TOP_EE4B1_14", - "CMT_TOP_EE4B1_15", - "CMT_TOP_EE4B1_2", - "CMT_TOP_EE4B1_3", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4B1_8", - "CMT_TOP_EE4B1_9", - "CMT_TOP_EE4B2_0", - "CMT_TOP_EE4B2_1", - "CMT_TOP_EE4B2_10", - "CMT_TOP_EE4B2_11", - "CMT_TOP_EE4B2_12", - "CMT_TOP_EE4B2_13", - "CMT_TOP_EE4B2_14", - "CMT_TOP_EE4B2_15", - "CMT_TOP_EE4B2_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4B2_5", - "CMT_TOP_EE4B2_6", - "CMT_TOP_EE4B2_7", - "CMT_TOP_EE4B2_8", - "CMT_TOP_EE4B2_9", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE4B3_10", - "CMT_TOP_EE4B3_11", - "CMT_TOP_EE4B3_12", - "CMT_TOP_EE4B3_13", - "CMT_TOP_EE4B3_14", - "CMT_TOP_EE4B3_15", - "CMT_TOP_EE4B3_2", - "CMT_TOP_EE4B3_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_EE4B3_5", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EE4B3_7", - "CMT_TOP_EE4B3_8", - "CMT_TOP_EE4B3_9", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_EE4BEG0_11", - "CMT_TOP_EE4BEG0_12", - "CMT_TOP_EE4BEG0_13", - "CMT_TOP_EE4BEG0_14", - "CMT_TOP_EE4BEG0_15", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_EE4BEG1_12", - "CMT_TOP_EE4BEG1_13", - "CMT_TOP_EE4BEG1_14", - "CMT_TOP_EE4BEG1_15", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_EE4BEG1_9", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_EE4BEG2_10", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_EE4BEG2_12", - "CMT_TOP_EE4BEG2_13", - "CMT_TOP_EE4BEG2_14", - "CMT_TOP_EE4BEG2_15", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_EE4BEG3_12", - "CMT_TOP_EE4BEG3_13", - "CMT_TOP_EE4BEG3_14", - "CMT_TOP_EE4BEG3_15", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_EE4C0_0", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4C0_10", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EE4C0_12", - "CMT_TOP_EE4C0_13", - "CMT_TOP_EE4C0_14", - "CMT_TOP_EE4C0_15", - "CMT_TOP_EE4C0_2", - "CMT_TOP_EE4C0_3", - "CMT_TOP_EE4C0_4", - "CMT_TOP_EE4C0_5", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4C0_7", - "CMT_TOP_EE4C0_8", - "CMT_TOP_EE4C0_9", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4C1_1", - "CMT_TOP_EE4C1_10", - "CMT_TOP_EE4C1_11", - "CMT_TOP_EE4C1_12", - "CMT_TOP_EE4C1_13", - "CMT_TOP_EE4C1_14", - "CMT_TOP_EE4C1_15", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE4C1_3", - "CMT_TOP_EE4C1_4", - "CMT_TOP_EE4C1_5", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_7", - "CMT_TOP_EE4C1_8", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4C2_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_EE4C2_10", - "CMT_TOP_EE4C2_11", - "CMT_TOP_EE4C2_12", - "CMT_TOP_EE4C2_13", - "CMT_TOP_EE4C2_14", - "CMT_TOP_EE4C2_15", - "CMT_TOP_EE4C2_2", - "CMT_TOP_EE4C2_3", - "CMT_TOP_EE4C2_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EE4C2_7", - "CMT_TOP_EE4C2_8", - "CMT_TOP_EE4C2_9", - "CMT_TOP_EE4C3_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_EE4C3_10", - "CMT_TOP_EE4C3_11", - "CMT_TOP_EE4C3_12", - "CMT_TOP_EE4C3_13", - "CMT_TOP_EE4C3_14", - "CMT_TOP_EE4C3_15", - "CMT_TOP_EE4C3_2", - "CMT_TOP_EE4C3_3", - "CMT_TOP_EE4C3_4", - "CMT_TOP_EE4C3_5", - "CMT_TOP_EE4C3_6", - "CMT_TOP_EE4C3_7", - "CMT_TOP_EE4C3_8", - "CMT_TOP_EE4C3_9", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_EL1BEG0_12", - "CMT_TOP_EL1BEG0_13", - "CMT_TOP_EL1BEG0_14", - "CMT_TOP_EL1BEG0_15", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EL1BEG1_10", - "CMT_TOP_EL1BEG1_11", - "CMT_TOP_EL1BEG1_12", - "CMT_TOP_EL1BEG1_13", - "CMT_TOP_EL1BEG1_14", - "CMT_TOP_EL1BEG1_15", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_EL1BEG1_9", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_EL1BEG2_12", - "CMT_TOP_EL1BEG2_13", - "CMT_TOP_EL1BEG2_14", - "CMT_TOP_EL1BEG2_15", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_EL1BEG3_12", - "CMT_TOP_EL1BEG3_13", - "CMT_TOP_EL1BEG3_14", - "CMT_TOP_EL1BEG3_15", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_ER1BEG0_12", - "CMT_TOP_ER1BEG0_13", - "CMT_TOP_ER1BEG0_14", - "CMT_TOP_ER1BEG0_15", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_ER1BEG1_10", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_ER1BEG1_12", - "CMT_TOP_ER1BEG1_13", - "CMT_TOP_ER1BEG1_14", - "CMT_TOP_ER1BEG1_15", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_ER1BEG2_10", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_ER1BEG2_12", - "CMT_TOP_ER1BEG2_13", - "CMT_TOP_ER1BEG2_14", - "CMT_TOP_ER1BEG2_15", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_ER1BEG3_12", - "CMT_TOP_ER1BEG3_13", - "CMT_TOP_ER1BEG3_14", - "CMT_TOP_ER1BEG3_15", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_FAN0_0", - "CMT_TOP_FAN0_1", - "CMT_TOP_FAN0_10", - "CMT_TOP_FAN0_11", - "CMT_TOP_FAN0_12", - "CMT_TOP_FAN0_13", - "CMT_TOP_FAN0_14", - "CMT_TOP_FAN0_15", - "CMT_TOP_FAN0_2", - "CMT_TOP_FAN0_3", - "CMT_TOP_FAN0_4", - "CMT_TOP_FAN0_5", - "CMT_TOP_FAN0_6", - "CMT_TOP_FAN0_7", - "CMT_TOP_FAN0_8", - "CMT_TOP_FAN0_9", - "CMT_TOP_FAN1_0", - "CMT_TOP_FAN1_1", - "CMT_TOP_FAN1_10", - "CMT_TOP_FAN1_11", - "CMT_TOP_FAN1_12", - "CMT_TOP_FAN1_13", - "CMT_TOP_FAN1_14", - "CMT_TOP_FAN1_15", - "CMT_TOP_FAN1_2", - "CMT_TOP_FAN1_3", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_5", - "CMT_TOP_FAN1_6", - "CMT_TOP_FAN1_7", - "CMT_TOP_FAN1_8", - "CMT_TOP_FAN1_9", - "CMT_TOP_FAN2_0", - "CMT_TOP_FAN2_1", - "CMT_TOP_FAN2_10", - "CMT_TOP_FAN2_11", - "CMT_TOP_FAN2_12", - "CMT_TOP_FAN2_13", - "CMT_TOP_FAN2_14", - "CMT_TOP_FAN2_15", - "CMT_TOP_FAN2_2", - "CMT_TOP_FAN2_3", - "CMT_TOP_FAN2_4", - "CMT_TOP_FAN2_5", - "CMT_TOP_FAN2_6", - "CMT_TOP_FAN2_7", - "CMT_TOP_FAN2_8", - "CMT_TOP_FAN2_9", - "CMT_TOP_FAN3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_FAN3_10", - "CMT_TOP_FAN3_11", - "CMT_TOP_FAN3_12", - "CMT_TOP_FAN3_13", - "CMT_TOP_FAN3_14", - "CMT_TOP_FAN3_15", - "CMT_TOP_FAN3_2", - "CMT_TOP_FAN3_3", - "CMT_TOP_FAN3_4", - "CMT_TOP_FAN3_5", - "CMT_TOP_FAN3_6", - "CMT_TOP_FAN3_7", - "CMT_TOP_FAN3_8", - "CMT_TOP_FAN3_9", - "CMT_TOP_FAN4_0", - "CMT_TOP_FAN4_1", - "CMT_TOP_FAN4_10", - "CMT_TOP_FAN4_11", - "CMT_TOP_FAN4_12", - "CMT_TOP_FAN4_13", - "CMT_TOP_FAN4_14", - "CMT_TOP_FAN4_15", - "CMT_TOP_FAN4_2", - "CMT_TOP_FAN4_3", - "CMT_TOP_FAN4_4", - "CMT_TOP_FAN4_5", - "CMT_TOP_FAN4_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_FAN4_8", - "CMT_TOP_FAN4_9", - "CMT_TOP_FAN5_0", - "CMT_TOP_FAN5_1", - "CMT_TOP_FAN5_10", - "CMT_TOP_FAN5_11", - "CMT_TOP_FAN5_12", - "CMT_TOP_FAN5_13", - "CMT_TOP_FAN5_14", - "CMT_TOP_FAN5_15", - "CMT_TOP_FAN5_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_FAN5_5", - "CMT_TOP_FAN5_6", - "CMT_TOP_FAN5_7", - "CMT_TOP_FAN5_8", - "CMT_TOP_FAN5_9", - "CMT_TOP_FAN6_0", - "CMT_TOP_FAN6_1", - "CMT_TOP_FAN6_10", - "CMT_TOP_FAN6_11", - "CMT_TOP_FAN6_12", - "CMT_TOP_FAN6_13", - "CMT_TOP_FAN6_14", - "CMT_TOP_FAN6_15", - "CMT_TOP_FAN6_2", - "CMT_TOP_FAN6_3", - "CMT_TOP_FAN6_4", - "CMT_TOP_FAN6_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_FAN6_7", - "CMT_TOP_FAN6_8", - "CMT_TOP_FAN6_9", - "CMT_TOP_FAN7_0", - "CMT_TOP_FAN7_1", - "CMT_TOP_FAN7_10", - "CMT_TOP_FAN7_11", - "CMT_TOP_FAN7_12", - "CMT_TOP_FAN7_13", - "CMT_TOP_FAN7_14", - "CMT_TOP_FAN7_15", - "CMT_TOP_FAN7_2", - "CMT_TOP_FAN7_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_FAN7_5", - "CMT_TOP_FAN7_6", - "CMT_TOP_FAN7_7", - "CMT_TOP_FAN7_8", - "CMT_TOP_FAN7_9", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_ICLKDIV_10", - "CMT_TOP_ICLKDIV_11", - "CMT_TOP_ICLKDIV_12", - "CMT_TOP_ICLKDIV_13", - "CMT_TOP_ICLKDIV_14", - "CMT_TOP_ICLKDIV_15", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ICLKDIV_9", - "CMT_TOP_ICLK_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_ICLK_10", - "CMT_TOP_ICLK_11", - "CMT_TOP_ICLK_12", - "CMT_TOP_ICLK_13", - "CMT_TOP_ICLK_14", - "CMT_TOP_ICLK_15", - "CMT_TOP_ICLK_2", - "CMT_TOP_ICLK_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_ICLK_5", - "CMT_TOP_ICLK_6", - "CMT_TOP_ICLK_7", - "CMT_TOP_ICLK_8", - "CMT_TOP_ICLK_9", - "CMT_TOP_IMUX0_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_IMUX0_10", - "CMT_TOP_IMUX0_11", - "CMT_TOP_IMUX0_12", - "CMT_TOP_IMUX0_13", - "CMT_TOP_IMUX0_14", - "CMT_TOP_IMUX0_15", - "CMT_TOP_IMUX0_2", - "CMT_TOP_IMUX0_3", - "CMT_TOP_IMUX0_4", - "CMT_TOP_IMUX0_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX0_8", - "CMT_TOP_IMUX0_9", - "CMT_TOP_IMUX10_0", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX10_10", - "CMT_TOP_IMUX10_11", - "CMT_TOP_IMUX10_12", - "CMT_TOP_IMUX10_13", - "CMT_TOP_IMUX10_14", - "CMT_TOP_IMUX10_15", - "CMT_TOP_IMUX10_2", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX10_4", - "CMT_TOP_IMUX10_5", - "CMT_TOP_IMUX10_6", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_IMUX10_9", - "CMT_TOP_IMUX11_0", - "CMT_TOP_IMUX11_1", - "CMT_TOP_IMUX11_10", - "CMT_TOP_IMUX11_11", - "CMT_TOP_IMUX11_12", - "CMT_TOP_IMUX11_13", - "CMT_TOP_IMUX11_14", - "CMT_TOP_IMUX11_15", - "CMT_TOP_IMUX11_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_IMUX11_4", - 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"CMT_TOP_IMUX21_6", - "CMT_TOP_IMUX21_7", - "CMT_TOP_IMUX21_8", - "CMT_TOP_IMUX21_9", - "CMT_TOP_IMUX22_0", - "CMT_TOP_IMUX22_1", - "CMT_TOP_IMUX22_10", - "CMT_TOP_IMUX22_11", - "CMT_TOP_IMUX22_12", - "CMT_TOP_IMUX22_13", - "CMT_TOP_IMUX22_14", - "CMT_TOP_IMUX22_15", - "CMT_TOP_IMUX22_2", - "CMT_TOP_IMUX22_3", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX22_5", - "CMT_TOP_IMUX22_6", - "CMT_TOP_IMUX22_7", - "CMT_TOP_IMUX22_8", - "CMT_TOP_IMUX22_9", - "CMT_TOP_IMUX23_0", - "CMT_TOP_IMUX23_1", - "CMT_TOP_IMUX23_10", - "CMT_TOP_IMUX23_11", - "CMT_TOP_IMUX23_12", - "CMT_TOP_IMUX23_13", - "CMT_TOP_IMUX23_14", - "CMT_TOP_IMUX23_15", - "CMT_TOP_IMUX23_2", - "CMT_TOP_IMUX23_3", - "CMT_TOP_IMUX23_4", - "CMT_TOP_IMUX23_5", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX23_7", - "CMT_TOP_IMUX23_8", - "CMT_TOP_IMUX23_9", - "CMT_TOP_IMUX24_0", - "CMT_TOP_IMUX24_1", - "CMT_TOP_IMUX24_10", - "CMT_TOP_IMUX24_11", - "CMT_TOP_IMUX24_12", - "CMT_TOP_IMUX24_13", - "CMT_TOP_IMUX24_14", - "CMT_TOP_IMUX24_15", - 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"CMT_TOP_IMUX31_7", - "CMT_TOP_IMUX31_8", - "CMT_TOP_IMUX31_9", - "CMT_TOP_IMUX32_0", - "CMT_TOP_IMUX32_1", - "CMT_TOP_IMUX32_10", - "CMT_TOP_IMUX32_11", - "CMT_TOP_IMUX32_12", - "CMT_TOP_IMUX32_13", - "CMT_TOP_IMUX32_14", - "CMT_TOP_IMUX32_15", - "CMT_TOP_IMUX32_2", - "CMT_TOP_IMUX32_3", - "CMT_TOP_IMUX32_4", - "CMT_TOP_IMUX32_5", - "CMT_TOP_IMUX32_6", - "CMT_TOP_IMUX32_7", - "CMT_TOP_IMUX32_8", - "CMT_TOP_IMUX32_9", - "CMT_TOP_IMUX33_0", - "CMT_TOP_IMUX33_1", - "CMT_TOP_IMUX33_10", - "CMT_TOP_IMUX33_11", - "CMT_TOP_IMUX33_12", - "CMT_TOP_IMUX33_13", - "CMT_TOP_IMUX33_14", - "CMT_TOP_IMUX33_15", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX33_3", - "CMT_TOP_IMUX33_4", - "CMT_TOP_IMUX33_5", - "CMT_TOP_IMUX33_6", - "CMT_TOP_IMUX33_7", - "CMT_TOP_IMUX33_8", - "CMT_TOP_IMUX33_9", - "CMT_TOP_IMUX34_0", - "CMT_TOP_IMUX34_1", - "CMT_TOP_IMUX34_10", - "CMT_TOP_IMUX34_11", - "CMT_TOP_IMUX34_12", - "CMT_TOP_IMUX34_13", - "CMT_TOP_IMUX34_14", - "CMT_TOP_IMUX34_15", - "CMT_TOP_IMUX34_2", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX34_4", - "CMT_TOP_IMUX34_5", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX34_7", - "CMT_TOP_IMUX34_8", - "CMT_TOP_IMUX34_9", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX35_1", - "CMT_TOP_IMUX35_10", - "CMT_TOP_IMUX35_11", - "CMT_TOP_IMUX35_12", - "CMT_TOP_IMUX35_13", - "CMT_TOP_IMUX35_14", - "CMT_TOP_IMUX35_15", - "CMT_TOP_IMUX35_2", - "CMT_TOP_IMUX35_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_IMUX35_5", - "CMT_TOP_IMUX35_6", - "CMT_TOP_IMUX35_7", - "CMT_TOP_IMUX35_8", - "CMT_TOP_IMUX35_9", - "CMT_TOP_IMUX36_0", - "CMT_TOP_IMUX36_1", - "CMT_TOP_IMUX36_10", - "CMT_TOP_IMUX36_11", - "CMT_TOP_IMUX36_12", - "CMT_TOP_IMUX36_13", - "CMT_TOP_IMUX36_14", - "CMT_TOP_IMUX36_15", - "CMT_TOP_IMUX36_2", - "CMT_TOP_IMUX36_3", - "CMT_TOP_IMUX36_4", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX36_6", - "CMT_TOP_IMUX36_7", - "CMT_TOP_IMUX36_8", - "CMT_TOP_IMUX36_9", - "CMT_TOP_IMUX37_0", - "CMT_TOP_IMUX37_1", - "CMT_TOP_IMUX37_10", - "CMT_TOP_IMUX37_11", - "CMT_TOP_IMUX37_12", - "CMT_TOP_IMUX37_13", - "CMT_TOP_IMUX37_14", - "CMT_TOP_IMUX37_15", - "CMT_TOP_IMUX37_2", - "CMT_TOP_IMUX37_3", - "CMT_TOP_IMUX37_4", - "CMT_TOP_IMUX37_5", - "CMT_TOP_IMUX37_6", - "CMT_TOP_IMUX37_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_IMUX37_9", - "CMT_TOP_IMUX38_0", - "CMT_TOP_IMUX38_1", - "CMT_TOP_IMUX38_10", - "CMT_TOP_IMUX38_11", - "CMT_TOP_IMUX38_12", - "CMT_TOP_IMUX38_13", - "CMT_TOP_IMUX38_14", - "CMT_TOP_IMUX38_15", - "CMT_TOP_IMUX38_2", - "CMT_TOP_IMUX38_3", - "CMT_TOP_IMUX38_4", - "CMT_TOP_IMUX38_5", - "CMT_TOP_IMUX38_6", - "CMT_TOP_IMUX38_7", - "CMT_TOP_IMUX38_8", - "CMT_TOP_IMUX38_9", - "CMT_TOP_IMUX39_0", - "CMT_TOP_IMUX39_1", - "CMT_TOP_IMUX39_10", - "CMT_TOP_IMUX39_11", - "CMT_TOP_IMUX39_12", - "CMT_TOP_IMUX39_13", - "CMT_TOP_IMUX39_14", - "CMT_TOP_IMUX39_15", - "CMT_TOP_IMUX39_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX39_4", - "CMT_TOP_IMUX39_5", - "CMT_TOP_IMUX39_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_IMUX39_8", - "CMT_TOP_IMUX39_9", - "CMT_TOP_IMUX3_0", - "CMT_TOP_IMUX3_1", - "CMT_TOP_IMUX3_10", - "CMT_TOP_IMUX3_11", - "CMT_TOP_IMUX3_12", - "CMT_TOP_IMUX3_13", - "CMT_TOP_IMUX3_14", - "CMT_TOP_IMUX3_15", - "CMT_TOP_IMUX3_2", - "CMT_TOP_IMUX3_3", - "CMT_TOP_IMUX3_4", - "CMT_TOP_IMUX3_5", - "CMT_TOP_IMUX3_6", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX3_8", - "CMT_TOP_IMUX3_9", - "CMT_TOP_IMUX40_0", - "CMT_TOP_IMUX40_1", - "CMT_TOP_IMUX40_10", - "CMT_TOP_IMUX40_11", - "CMT_TOP_IMUX40_12", - "CMT_TOP_IMUX40_13", - "CMT_TOP_IMUX40_14", - "CMT_TOP_IMUX40_15", - "CMT_TOP_IMUX40_2", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX40_4", - "CMT_TOP_IMUX40_5", - "CMT_TOP_IMUX40_6", - "CMT_TOP_IMUX40_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_IMUX40_9", - "CMT_TOP_IMUX41_0", - "CMT_TOP_IMUX41_1", - "CMT_TOP_IMUX41_10", - "CMT_TOP_IMUX41_11", - "CMT_TOP_IMUX41_12", - "CMT_TOP_IMUX41_13", - "CMT_TOP_IMUX41_14", - "CMT_TOP_IMUX41_15", - "CMT_TOP_IMUX41_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX41_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_IMUX41_9", - "CMT_TOP_IMUX42_0", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX42_10", - "CMT_TOP_IMUX42_11", - "CMT_TOP_IMUX42_12", - "CMT_TOP_IMUX42_13", - "CMT_TOP_IMUX42_14", - "CMT_TOP_IMUX42_15", - "CMT_TOP_IMUX42_2", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX42_5", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX42_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_IMUX42_9", - "CMT_TOP_IMUX43_0", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX43_10", - "CMT_TOP_IMUX43_11", - "CMT_TOP_IMUX43_12", - "CMT_TOP_IMUX43_13", - "CMT_TOP_IMUX43_14", - "CMT_TOP_IMUX43_15", - "CMT_TOP_IMUX43_2", - "CMT_TOP_IMUX43_3", - "CMT_TOP_IMUX43_4", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX43_6", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX43_8", - "CMT_TOP_IMUX43_9", - "CMT_TOP_IMUX44_0", - "CMT_TOP_IMUX44_1", - "CMT_TOP_IMUX44_10", - "CMT_TOP_IMUX44_11", - "CMT_TOP_IMUX44_12", - "CMT_TOP_IMUX44_13", - "CMT_TOP_IMUX44_14", - "CMT_TOP_IMUX44_15", - "CMT_TOP_IMUX44_2", - "CMT_TOP_IMUX44_3", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX44_5", - "CMT_TOP_IMUX44_6", - "CMT_TOP_IMUX44_7", - "CMT_TOP_IMUX44_8", - "CMT_TOP_IMUX44_9", - "CMT_TOP_IMUX45_0", - "CMT_TOP_IMUX45_1", - "CMT_TOP_IMUX45_10", - "CMT_TOP_IMUX45_11", - "CMT_TOP_IMUX45_12", - "CMT_TOP_IMUX45_13", - "CMT_TOP_IMUX45_14", - "CMT_TOP_IMUX45_15", - "CMT_TOP_IMUX45_2", - "CMT_TOP_IMUX45_3", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX45_5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX45_8", - "CMT_TOP_IMUX45_9", - "CMT_TOP_IMUX46_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX46_10", - "CMT_TOP_IMUX46_11", - "CMT_TOP_IMUX46_12", - "CMT_TOP_IMUX46_13", - "CMT_TOP_IMUX46_14", - "CMT_TOP_IMUX46_15", - "CMT_TOP_IMUX46_2", - "CMT_TOP_IMUX46_3", - "CMT_TOP_IMUX46_4", - "CMT_TOP_IMUX46_5", - "CMT_TOP_IMUX46_6", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX46_8", - "CMT_TOP_IMUX46_9", - "CMT_TOP_IMUX47_0", - "CMT_TOP_IMUX47_1", - "CMT_TOP_IMUX47_10", - "CMT_TOP_IMUX47_11", - "CMT_TOP_IMUX47_12", - "CMT_TOP_IMUX47_13", - "CMT_TOP_IMUX47_14", - "CMT_TOP_IMUX47_15", - "CMT_TOP_IMUX47_2", - "CMT_TOP_IMUX47_3", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX47_5", - "CMT_TOP_IMUX47_6", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX47_9", - "CMT_TOP_IMUX4_0", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX4_10", - "CMT_TOP_IMUX4_11", - "CMT_TOP_IMUX4_12", - "CMT_TOP_IMUX4_13", - "CMT_TOP_IMUX4_14", - "CMT_TOP_IMUX4_15", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX4_3", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX4_5", - "CMT_TOP_IMUX4_6", - "CMT_TOP_IMUX4_7", - "CMT_TOP_IMUX4_8", - "CMT_TOP_IMUX4_9", - "CMT_TOP_IMUX5_0", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX5_10", - "CMT_TOP_IMUX5_11", - "CMT_TOP_IMUX5_12", - "CMT_TOP_IMUX5_13", - "CMT_TOP_IMUX5_14", - "CMT_TOP_IMUX5_15", - "CMT_TOP_IMUX5_2", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX5_6", - "CMT_TOP_IMUX5_7", - "CMT_TOP_IMUX5_8", - "CMT_TOP_IMUX5_9", - "CMT_TOP_IMUX6_0", - "CMT_TOP_IMUX6_1", - "CMT_TOP_IMUX6_10", - "CMT_TOP_IMUX6_11", - "CMT_TOP_IMUX6_12", - "CMT_TOP_IMUX6_13", - "CMT_TOP_IMUX6_14", - "CMT_TOP_IMUX6_15", - "CMT_TOP_IMUX6_2", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX6_4", - "CMT_TOP_IMUX6_5", - "CMT_TOP_IMUX6_6", - "CMT_TOP_IMUX6_7", - "CMT_TOP_IMUX6_8", - "CMT_TOP_IMUX6_9", - "CMT_TOP_IMUX7_0", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX7_10", - "CMT_TOP_IMUX7_11", - "CMT_TOP_IMUX7_12", - "CMT_TOP_IMUX7_13", - "CMT_TOP_IMUX7_14", - "CMT_TOP_IMUX7_15", - "CMT_TOP_IMUX7_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX7_8", - "CMT_TOP_IMUX7_9", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_IMUX8_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_IMUX8_12", - "CMT_TOP_IMUX8_13", - "CMT_TOP_IMUX8_14", - "CMT_TOP_IMUX8_15", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX8_3", - "CMT_TOP_IMUX8_4", - "CMT_TOP_IMUX8_5", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX8_7", - "CMT_TOP_IMUX8_8", - "CMT_TOP_IMUX8_9", - "CMT_TOP_IMUX9_0", - "CMT_TOP_IMUX9_1", - "CMT_TOP_IMUX9_10", - "CMT_TOP_IMUX9_11", - "CMT_TOP_IMUX9_12", - "CMT_TOP_IMUX9_13", - "CMT_TOP_IMUX9_14", - "CMT_TOP_IMUX9_15", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_IMUX9_4", - "CMT_TOP_IMUX9_5", - "CMT_TOP_IMUX9_6", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX9_9", - "CMT_TOP_LH10_0", - "CMT_TOP_LH10_1", - "CMT_TOP_LH10_10", - "CMT_TOP_LH10_11", - "CMT_TOP_LH10_12", - "CMT_TOP_LH10_13", - "CMT_TOP_LH10_14", - "CMT_TOP_LH10_15", - "CMT_TOP_LH10_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_4", - "CMT_TOP_LH10_5", - "CMT_TOP_LH10_6", - "CMT_TOP_LH10_7", - "CMT_TOP_LH10_8", - "CMT_TOP_LH10_9", - "CMT_TOP_LH11_0", - "CMT_TOP_LH11_1", - "CMT_TOP_LH11_10", - "CMT_TOP_LH11_11", - "CMT_TOP_LH11_12", - "CMT_TOP_LH11_13", - "CMT_TOP_LH11_14", - "CMT_TOP_LH11_15", - "CMT_TOP_LH11_2", - "CMT_TOP_LH11_3", - "CMT_TOP_LH11_4", - "CMT_TOP_LH11_5", - "CMT_TOP_LH11_6", - "CMT_TOP_LH11_7", - "CMT_TOP_LH11_8", - "CMT_TOP_LH11_9", - "CMT_TOP_LH12_0", - "CMT_TOP_LH12_1", - "CMT_TOP_LH12_10", - "CMT_TOP_LH12_11", - "CMT_TOP_LH12_12", - "CMT_TOP_LH12_13", - "CMT_TOP_LH12_14", - "CMT_TOP_LH12_15", - "CMT_TOP_LH12_2", - "CMT_TOP_LH12_3", - "CMT_TOP_LH12_4", - "CMT_TOP_LH12_5", - "CMT_TOP_LH12_6", - "CMT_TOP_LH12_7", - "CMT_TOP_LH12_8", - "CMT_TOP_LH12_9", - "CMT_TOP_LH1_0", - "CMT_TOP_LH1_1", - "CMT_TOP_LH1_10", - "CMT_TOP_LH1_11", - "CMT_TOP_LH1_12", - "CMT_TOP_LH1_13", - "CMT_TOP_LH1_14", - "CMT_TOP_LH1_15", - "CMT_TOP_LH1_2", - "CMT_TOP_LH1_3", - "CMT_TOP_LH1_4", - "CMT_TOP_LH1_5", - "CMT_TOP_LH1_6", - "CMT_TOP_LH1_7", - "CMT_TOP_LH1_8", - "CMT_TOP_LH1_9", - "CMT_TOP_LH2_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH2_10", - "CMT_TOP_LH2_11", - "CMT_TOP_LH2_12", - "CMT_TOP_LH2_13", - "CMT_TOP_LH2_14", - "CMT_TOP_LH2_15", - "CMT_TOP_LH2_2", - "CMT_TOP_LH2_3", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_5", - "CMT_TOP_LH2_6", - "CMT_TOP_LH2_7", - "CMT_TOP_LH2_8", - "CMT_TOP_LH2_9", - "CMT_TOP_LH3_0", - "CMT_TOP_LH3_1", - "CMT_TOP_LH3_10", - "CMT_TOP_LH3_11", - "CMT_TOP_LH3_12", - "CMT_TOP_LH3_13", - "CMT_TOP_LH3_14", - "CMT_TOP_LH3_15", - "CMT_TOP_LH3_2", - "CMT_TOP_LH3_3", - "CMT_TOP_LH3_4", - "CMT_TOP_LH3_5", - "CMT_TOP_LH3_6", - "CMT_TOP_LH3_7", - "CMT_TOP_LH3_8", - "CMT_TOP_LH3_9", - "CMT_TOP_LH4_0", - "CMT_TOP_LH4_1", - "CMT_TOP_LH4_10", - "CMT_TOP_LH4_11", - "CMT_TOP_LH4_12", - "CMT_TOP_LH4_13", - "CMT_TOP_LH4_14", - "CMT_TOP_LH4_15", - "CMT_TOP_LH4_2", - "CMT_TOP_LH4_3", - "CMT_TOP_LH4_4", - "CMT_TOP_LH4_5", - "CMT_TOP_LH4_6", - "CMT_TOP_LH4_7", - "CMT_TOP_LH4_8", - "CMT_TOP_LH4_9", - "CMT_TOP_LH5_0", - "CMT_TOP_LH5_1", - "CMT_TOP_LH5_10", - "CMT_TOP_LH5_11", - "CMT_TOP_LH5_12", - "CMT_TOP_LH5_13", - "CMT_TOP_LH5_14", - "CMT_TOP_LH5_15", - "CMT_TOP_LH5_2", - "CMT_TOP_LH5_3", - "CMT_TOP_LH5_4", - "CMT_TOP_LH5_5", - "CMT_TOP_LH5_6", - "CMT_TOP_LH5_7", - "CMT_TOP_LH5_8", - "CMT_TOP_LH5_9", - "CMT_TOP_LH6_0", - "CMT_TOP_LH6_1", - "CMT_TOP_LH6_10", - "CMT_TOP_LH6_11", - "CMT_TOP_LH6_12", - "CMT_TOP_LH6_13", - "CMT_TOP_LH6_14", - "CMT_TOP_LH6_15", - "CMT_TOP_LH6_2", - "CMT_TOP_LH6_3", - "CMT_TOP_LH6_4", - "CMT_TOP_LH6_5", - "CMT_TOP_LH6_6", - "CMT_TOP_LH6_7", - "CMT_TOP_LH6_8", - "CMT_TOP_LH6_9", - "CMT_TOP_LH7_0", - "CMT_TOP_LH7_1", - "CMT_TOP_LH7_10", - "CMT_TOP_LH7_11", - "CMT_TOP_LH7_12", - "CMT_TOP_LH7_13", - "CMT_TOP_LH7_14", - "CMT_TOP_LH7_15", - "CMT_TOP_LH7_2", - "CMT_TOP_LH7_3", - "CMT_TOP_LH7_4", - "CMT_TOP_LH7_5", - "CMT_TOP_LH7_6", - "CMT_TOP_LH7_7", - "CMT_TOP_LH7_8", - "CMT_TOP_LH7_9", - "CMT_TOP_LH8_0", - "CMT_TOP_LH8_1", - "CMT_TOP_LH8_10", - "CMT_TOP_LH8_11", - "CMT_TOP_LH8_12", - "CMT_TOP_LH8_13", - "CMT_TOP_LH8_14", - "CMT_TOP_LH8_15", - "CMT_TOP_LH8_2", - "CMT_TOP_LH8_3", - "CMT_TOP_LH8_4", - "CMT_TOP_LH8_5", - "CMT_TOP_LH8_6", - "CMT_TOP_LH8_7", - "CMT_TOP_LH8_8", - "CMT_TOP_LH8_9", - "CMT_TOP_LH9_0", - "CMT_TOP_LH9_1", - "CMT_TOP_LH9_10", - "CMT_TOP_LH9_11", - "CMT_TOP_LH9_12", - "CMT_TOP_LH9_13", - "CMT_TOP_LH9_14", - "CMT_TOP_LH9_15", - "CMT_TOP_LH9_2", - "CMT_TOP_LH9_3", - "CMT_TOP_LH9_4", - "CMT_TOP_LH9_5", - "CMT_TOP_LH9_6", - "CMT_TOP_LH9_7", - "CMT_TOP_LH9_8", - "CMT_TOP_LH9_9", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B0_12", - "CMT_TOP_LOGIC_OUTS_L_B0_13", - "CMT_TOP_LOGIC_OUTS_L_B0_14", - "CMT_TOP_LOGIC_OUTS_L_B0_15", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_TOP_LOGIC_OUTS_L_B10_12", - "CMT_TOP_LOGIC_OUTS_L_B10_13", - "CMT_TOP_LOGIC_OUTS_L_B10_14", - "CMT_TOP_LOGIC_OUTS_L_B10_15", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_TOP_LOGIC_OUTS_L_B11_12", - "CMT_TOP_LOGIC_OUTS_L_B11_13", - "CMT_TOP_LOGIC_OUTS_L_B11_14", - "CMT_TOP_LOGIC_OUTS_L_B11_15", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_LOGIC_OUTS_L_B12_12", - "CMT_TOP_LOGIC_OUTS_L_B12_13", - "CMT_TOP_LOGIC_OUTS_L_B12_14", - "CMT_TOP_LOGIC_OUTS_L_B12_15", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LOGIC_OUTS_L_B13_10", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_LOGIC_OUTS_L_B13_12", - "CMT_TOP_LOGIC_OUTS_L_B13_13", - "CMT_TOP_LOGIC_OUTS_L_B13_14", - "CMT_TOP_LOGIC_OUTS_L_B13_15", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_LOGIC_OUTS_L_B14_12", - "CMT_TOP_LOGIC_OUTS_L_B14_13", - "CMT_TOP_LOGIC_OUTS_L_B14_14", - "CMT_TOP_LOGIC_OUTS_L_B14_15", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_LOGIC_OUTS_L_B15_12", - "CMT_TOP_LOGIC_OUTS_L_B15_13", - "CMT_TOP_LOGIC_OUTS_L_B15_14", - "CMT_TOP_LOGIC_OUTS_L_B15_15", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_LOGIC_OUTS_L_B16_12", - "CMT_TOP_LOGIC_OUTS_L_B16_13", - "CMT_TOP_LOGIC_OUTS_L_B16_14", - "CMT_TOP_LOGIC_OUTS_L_B16_15", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B17_12", - "CMT_TOP_LOGIC_OUTS_L_B17_13", - "CMT_TOP_LOGIC_OUTS_L_B17_14", - "CMT_TOP_LOGIC_OUTS_L_B17_15", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_TOP_LOGIC_OUTS_L_B18_12", - "CMT_TOP_LOGIC_OUTS_L_B18_13", - "CMT_TOP_LOGIC_OUTS_L_B18_14", - "CMT_TOP_LOGIC_OUTS_L_B18_15", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LOGIC_OUTS_L_B19_12", - "CMT_TOP_LOGIC_OUTS_L_B19_13", - "CMT_TOP_LOGIC_OUTS_L_B19_14", - "CMT_TOP_LOGIC_OUTS_L_B19_15", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_TOP_LOGIC_OUTS_L_B1_12", - "CMT_TOP_LOGIC_OUTS_L_B1_13", - "CMT_TOP_LOGIC_OUTS_L_B1_14", - "CMT_TOP_LOGIC_OUTS_L_B1_15", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_TOP_LOGIC_OUTS_L_B20_12", - "CMT_TOP_LOGIC_OUTS_L_B20_13", - "CMT_TOP_LOGIC_OUTS_L_B20_14", - "CMT_TOP_LOGIC_OUTS_L_B20_15", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_TOP_LOGIC_OUTS_L_B21_12", - "CMT_TOP_LOGIC_OUTS_L_B21_13", - "CMT_TOP_LOGIC_OUTS_L_B21_14", - "CMT_TOP_LOGIC_OUTS_L_B21_15", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_TOP_LOGIC_OUTS_L_B22_12", - "CMT_TOP_LOGIC_OUTS_L_B22_13", - "CMT_TOP_LOGIC_OUTS_L_B22_14", - "CMT_TOP_LOGIC_OUTS_L_B22_15", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_LOGIC_OUTS_L_B23_12", - "CMT_TOP_LOGIC_OUTS_L_B23_13", - "CMT_TOP_LOGIC_OUTS_L_B23_14", - "CMT_TOP_LOGIC_OUTS_L_B23_15", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LOGIC_OUTS_L_B2_12", - "CMT_TOP_LOGIC_OUTS_L_B2_13", - "CMT_TOP_LOGIC_OUTS_L_B2_14", - "CMT_TOP_LOGIC_OUTS_L_B2_15", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LOGIC_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B3_13", - "CMT_TOP_LOGIC_OUTS_L_B3_14", - "CMT_TOP_LOGIC_OUTS_L_B3_15", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_LOGIC_OUTS_L_B4_12", - "CMT_TOP_LOGIC_OUTS_L_B4_13", - "CMT_TOP_LOGIC_OUTS_L_B4_14", - "CMT_TOP_LOGIC_OUTS_L_B4_15", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_LOGIC_OUTS_L_B5_12", - "CMT_TOP_LOGIC_OUTS_L_B5_13", - "CMT_TOP_LOGIC_OUTS_L_B5_14", - "CMT_TOP_LOGIC_OUTS_L_B5_15", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_TOP_LOGIC_OUTS_L_B6_12", - "CMT_TOP_LOGIC_OUTS_L_B6_13", - "CMT_TOP_LOGIC_OUTS_L_B6_14", - "CMT_TOP_LOGIC_OUTS_L_B6_15", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_LOGIC_OUTS_L_B7_12", - "CMT_TOP_LOGIC_OUTS_L_B7_13", - "CMT_TOP_LOGIC_OUTS_L_B7_14", - "CMT_TOP_LOGIC_OUTS_L_B7_15", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_12", - "CMT_TOP_LOGIC_OUTS_L_B8_13", - "CMT_TOP_LOGIC_OUTS_L_B8_14", - "CMT_TOP_LOGIC_OUTS_L_B8_15", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_LOGIC_OUTS_L_B9_12", - "CMT_TOP_LOGIC_OUTS_L_B9_13", - "CMT_TOP_LOGIC_OUTS_L_B9_14", - "CMT_TOP_LOGIC_OUTS_L_B9_15", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_MONITOR_N_12", - "CMT_TOP_MONITOR_N_13", - "CMT_TOP_MONITOR_N_14", - "CMT_TOP_MONITOR_N_15", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_MONITOR_N_9", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_MONITOR_P_12", - "CMT_TOP_MONITOR_P_13", - "CMT_TOP_MONITOR_P_14", - "CMT_TOP_MONITOR_P_15", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_NE2A0_0", - "CMT_TOP_NE2A0_1", - "CMT_TOP_NE2A0_10", - "CMT_TOP_NE2A0_11", - "CMT_TOP_NE2A0_12", - "CMT_TOP_NE2A0_13", - "CMT_TOP_NE2A0_14", - "CMT_TOP_NE2A0_15", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A0_4", - "CMT_TOP_NE2A0_5", - "CMT_TOP_NE2A0_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_NE2A0_8", - "CMT_TOP_NE2A0_9", - "CMT_TOP_NE2A1_0", - "CMT_TOP_NE2A1_1", - "CMT_TOP_NE2A1_10", - "CMT_TOP_NE2A1_11", - "CMT_TOP_NE2A1_12", - "CMT_TOP_NE2A1_13", - "CMT_TOP_NE2A1_14", - "CMT_TOP_NE2A1_15", - "CMT_TOP_NE2A1_2", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_NE2A1_5", - "CMT_TOP_NE2A1_6", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE2A1_8", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE2A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_NE2A2_10", - "CMT_TOP_NE2A2_11", - "CMT_TOP_NE2A2_12", - "CMT_TOP_NE2A2_13", - "CMT_TOP_NE2A2_14", - "CMT_TOP_NE2A2_15", - "CMT_TOP_NE2A2_2", - "CMT_TOP_NE2A2_3", - "CMT_TOP_NE2A2_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_NE2A2_6", - "CMT_TOP_NE2A2_7", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE2A2_9", - "CMT_TOP_NE2A3_0", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NE2A3_10", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NE2A3_12", - "CMT_TOP_NE2A3_13", - "CMT_TOP_NE2A3_14", - "CMT_TOP_NE2A3_15", - "CMT_TOP_NE2A3_2", - "CMT_TOP_NE2A3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NE2A3_6", - "CMT_TOP_NE2A3_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_NE4BEG0_10", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_NE4BEG0_12", - "CMT_TOP_NE4BEG0_13", - "CMT_TOP_NE4BEG0_14", - "CMT_TOP_NE4BEG0_15", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_NE4BEG1_12", - "CMT_TOP_NE4BEG1_13", - "CMT_TOP_NE4BEG1_14", - "CMT_TOP_NE4BEG1_15", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_NE4BEG2_11", - "CMT_TOP_NE4BEG2_12", - "CMT_TOP_NE4BEG2_13", - "CMT_TOP_NE4BEG2_14", - "CMT_TOP_NE4BEG2_15", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_NE4BEG3_12", - "CMT_TOP_NE4BEG3_13", - "CMT_TOP_NE4BEG3_14", - "CMT_TOP_NE4BEG3_15", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_NE4C0_0", - "CMT_TOP_NE4C0_1", - "CMT_TOP_NE4C0_10", - "CMT_TOP_NE4C0_11", - "CMT_TOP_NE4C0_12", - "CMT_TOP_NE4C0_13", - "CMT_TOP_NE4C0_14", - "CMT_TOP_NE4C0_15", - "CMT_TOP_NE4C0_2", - "CMT_TOP_NE4C0_3", - "CMT_TOP_NE4C0_4", - "CMT_TOP_NE4C0_5", - "CMT_TOP_NE4C0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_9", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_NE4C1_10", - "CMT_TOP_NE4C1_11", - "CMT_TOP_NE4C1_12", - "CMT_TOP_NE4C1_13", - "CMT_TOP_NE4C1_14", - "CMT_TOP_NE4C1_15", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NE4C1_3", - "CMT_TOP_NE4C1_4", - "CMT_TOP_NE4C1_5", - "CMT_TOP_NE4C1_6", - "CMT_TOP_NE4C1_7", - "CMT_TOP_NE4C1_8", - "CMT_TOP_NE4C1_9", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NE4C2_1", - "CMT_TOP_NE4C2_10", - "CMT_TOP_NE4C2_11", - "CMT_TOP_NE4C2_12", - "CMT_TOP_NE4C2_13", - "CMT_TOP_NE4C2_14", - "CMT_TOP_NE4C2_15", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE4C2_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NE4C2_6", - "CMT_TOP_NE4C2_7", - "CMT_TOP_NE4C2_8", - "CMT_TOP_NE4C2_9", - "CMT_TOP_NE4C3_0", - "CMT_TOP_NE4C3_1", - "CMT_TOP_NE4C3_10", - "CMT_TOP_NE4C3_11", - "CMT_TOP_NE4C3_12", - "CMT_TOP_NE4C3_13", - "CMT_TOP_NE4C3_14", - "CMT_TOP_NE4C3_15", - "CMT_TOP_NE4C3_2", - "CMT_TOP_NE4C3_3", - "CMT_TOP_NE4C3_4", - "CMT_TOP_NE4C3_5", - "CMT_TOP_NE4C3_6", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_NE4C3_9", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW2A0_1", - "CMT_TOP_NW2A0_10", - "CMT_TOP_NW2A0_11", - "CMT_TOP_NW2A0_12", - "CMT_TOP_NW2A0_13", - "CMT_TOP_NW2A0_14", - "CMT_TOP_NW2A0_15", - "CMT_TOP_NW2A0_2", - "CMT_TOP_NW2A0_3", - "CMT_TOP_NW2A0_4", - "CMT_TOP_NW2A0_5", - "CMT_TOP_NW2A0_6", - "CMT_TOP_NW2A0_7", - "CMT_TOP_NW2A0_8", - "CMT_TOP_NW2A0_9", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NW2A1_1", - "CMT_TOP_NW2A1_10", - "CMT_TOP_NW2A1_11", - "CMT_TOP_NW2A1_12", - "CMT_TOP_NW2A1_13", - "CMT_TOP_NW2A1_14", - "CMT_TOP_NW2A1_15", - "CMT_TOP_NW2A1_2", - "CMT_TOP_NW2A1_3", - "CMT_TOP_NW2A1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_NW2A1_6", - "CMT_TOP_NW2A1_7", - "CMT_TOP_NW2A1_8", - "CMT_TOP_NW2A1_9", - "CMT_TOP_NW2A2_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_NW2A2_10", - "CMT_TOP_NW2A2_11", - "CMT_TOP_NW2A2_12", - "CMT_TOP_NW2A2_13", - "CMT_TOP_NW2A2_14", - "CMT_TOP_NW2A2_15", - "CMT_TOP_NW2A2_2", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_4", - "CMT_TOP_NW2A2_5", - "CMT_TOP_NW2A2_6", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NW2A2_8", - "CMT_TOP_NW2A2_9", - "CMT_TOP_NW2A3_0", - "CMT_TOP_NW2A3_1", - "CMT_TOP_NW2A3_10", - "CMT_TOP_NW2A3_11", - "CMT_TOP_NW2A3_12", - "CMT_TOP_NW2A3_13", - "CMT_TOP_NW2A3_14", - "CMT_TOP_NW2A3_15", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NW2A3_3", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW2A3_5", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NW2A3_7", - "CMT_TOP_NW2A3_8", - "CMT_TOP_NW2A3_9", - "CMT_TOP_NW4A0_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_NW4A0_10", - "CMT_TOP_NW4A0_11", - "CMT_TOP_NW4A0_12", - "CMT_TOP_NW4A0_13", - "CMT_TOP_NW4A0_14", - "CMT_TOP_NW4A0_15", - "CMT_TOP_NW4A0_2", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A0_4", - "CMT_TOP_NW4A0_5", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NW4A0_7", - "CMT_TOP_NW4A0_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_NW4A1_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_NW4A1_10", - "CMT_TOP_NW4A1_11", - "CMT_TOP_NW4A1_12", - "CMT_TOP_NW4A1_13", - "CMT_TOP_NW4A1_14", - "CMT_TOP_NW4A1_15", - "CMT_TOP_NW4A1_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_NW4A1_4", - "CMT_TOP_NW4A1_5", - "CMT_TOP_NW4A1_6", - "CMT_TOP_NW4A1_7", - "CMT_TOP_NW4A1_8", - "CMT_TOP_NW4A1_9", - "CMT_TOP_NW4A2_0", - "CMT_TOP_NW4A2_1", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NW4A2_11", - "CMT_TOP_NW4A2_12", - "CMT_TOP_NW4A2_13", - "CMT_TOP_NW4A2_14", - "CMT_TOP_NW4A2_15", - "CMT_TOP_NW4A2_2", - "CMT_TOP_NW4A2_3", - "CMT_TOP_NW4A2_4", - "CMT_TOP_NW4A2_5", - "CMT_TOP_NW4A2_6", - "CMT_TOP_NW4A2_7", - "CMT_TOP_NW4A2_8", - "CMT_TOP_NW4A2_9", - "CMT_TOP_NW4A3_0", - "CMT_TOP_NW4A3_1", - "CMT_TOP_NW4A3_10", - "CMT_TOP_NW4A3_11", - "CMT_TOP_NW4A3_12", - "CMT_TOP_NW4A3_13", - "CMT_TOP_NW4A3_14", - "CMT_TOP_NW4A3_15", - "CMT_TOP_NW4A3_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NW4A3_6", - "CMT_TOP_NW4A3_7", - "CMT_TOP_NW4A3_8", - "CMT_TOP_NW4A3_9", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NW4END0_1", - "CMT_TOP_NW4END0_10", - "CMT_TOP_NW4END0_11", - "CMT_TOP_NW4END0_12", - "CMT_TOP_NW4END0_13", - "CMT_TOP_NW4END0_14", - "CMT_TOP_NW4END0_15", - "CMT_TOP_NW4END0_2", - "CMT_TOP_NW4END0_3", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END0_5", - "CMT_TOP_NW4END0_6", - "CMT_TOP_NW4END0_7", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NW4END0_9", - "CMT_TOP_NW4END1_0", - "CMT_TOP_NW4END1_1", - "CMT_TOP_NW4END1_10", - "CMT_TOP_NW4END1_11", - "CMT_TOP_NW4END1_12", - "CMT_TOP_NW4END1_13", - "CMT_TOP_NW4END1_14", - "CMT_TOP_NW4END1_15", - "CMT_TOP_NW4END1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_NW4END1_4", - "CMT_TOP_NW4END1_5", - "CMT_TOP_NW4END1_6", - "CMT_TOP_NW4END1_7", - "CMT_TOP_NW4END1_8", - "CMT_TOP_NW4END1_9", - "CMT_TOP_NW4END2_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END2_10", - "CMT_TOP_NW4END2_11", - "CMT_TOP_NW4END2_12", - "CMT_TOP_NW4END2_13", - "CMT_TOP_NW4END2_14", - "CMT_TOP_NW4END2_15", - "CMT_TOP_NW4END2_2", - "CMT_TOP_NW4END2_3", - "CMT_TOP_NW4END2_4", - "CMT_TOP_NW4END2_5", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NW4END2_8", - "CMT_TOP_NW4END2_9", - "CMT_TOP_NW4END3_0", - "CMT_TOP_NW4END3_1", - "CMT_TOP_NW4END3_10", - "CMT_TOP_NW4END3_11", - "CMT_TOP_NW4END3_12", - "CMT_TOP_NW4END3_13", - "CMT_TOP_NW4END3_14", - "CMT_TOP_NW4END3_15", - "CMT_TOP_NW4END3_2", - "CMT_TOP_NW4END3_3", - "CMT_TOP_NW4END3_4", - "CMT_TOP_NW4END3_5", - "CMT_TOP_NW4END3_6", - "CMT_TOP_NW4END3_7", - "CMT_TOP_NW4END3_8", - "CMT_TOP_NW4END3_9", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_OCLK1X_90_10", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_OCLK1X_90_12", - "CMT_TOP_OCLK1X_90_13", - "CMT_TOP_OCLK1X_90_14", - "CMT_TOP_OCLK1X_90_15", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_OCLK1X_90_9", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_OCLKDIV_12", - "CMT_TOP_OCLKDIV_13", - "CMT_TOP_OCLKDIV_14", - "CMT_TOP_OCLKDIV_15", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_OCLK_0", - "CMT_TOP_OCLK_1", - "CMT_TOP_OCLK_10", - "CMT_TOP_OCLK_11", - "CMT_TOP_OCLK_12", - "CMT_TOP_OCLK_13", - "CMT_TOP_OCLK_14", - "CMT_TOP_OCLK_15", - "CMT_TOP_OCLK_2", - "CMT_TOP_OCLK_3", - "CMT_TOP_OCLK_4", - "CMT_TOP_OCLK_5", - "CMT_TOP_OCLK_6", - "CMT_TOP_OCLK_7", - "CMT_TOP_OCLK_8", - "CMT_TOP_OCLK_9", - "CMT_TOP_SE2A0_0", - "CMT_TOP_SE2A0_1", - "CMT_TOP_SE2A0_10", - "CMT_TOP_SE2A0_11", - "CMT_TOP_SE2A0_12", - "CMT_TOP_SE2A0_13", - "CMT_TOP_SE2A0_14", - "CMT_TOP_SE2A0_15", - "CMT_TOP_SE2A0_2", - "CMT_TOP_SE2A0_3", - "CMT_TOP_SE2A0_4", - "CMT_TOP_SE2A0_5", - "CMT_TOP_SE2A0_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_SE2A0_9", - "CMT_TOP_SE2A1_0", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE2A1_10", - "CMT_TOP_SE2A1_11", - "CMT_TOP_SE2A1_12", - "CMT_TOP_SE2A1_13", - "CMT_TOP_SE2A1_14", - "CMT_TOP_SE2A1_15", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A1_3", - "CMT_TOP_SE2A1_4", - "CMT_TOP_SE2A1_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SE2A1_8", - "CMT_TOP_SE2A1_9", - "CMT_TOP_SE2A2_0", - "CMT_TOP_SE2A2_1", - "CMT_TOP_SE2A2_10", - "CMT_TOP_SE2A2_11", - "CMT_TOP_SE2A2_12", - "CMT_TOP_SE2A2_13", - "CMT_TOP_SE2A2_14", - "CMT_TOP_SE2A2_15", - "CMT_TOP_SE2A2_2", - "CMT_TOP_SE2A2_3", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SE2A2_5", - "CMT_TOP_SE2A2_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_SE2A2_8", - "CMT_TOP_SE2A2_9", - "CMT_TOP_SE2A3_0", - "CMT_TOP_SE2A3_1", - "CMT_TOP_SE2A3_10", - "CMT_TOP_SE2A3_11", - "CMT_TOP_SE2A3_12", - "CMT_TOP_SE2A3_13", - "CMT_TOP_SE2A3_14", - "CMT_TOP_SE2A3_15", - "CMT_TOP_SE2A3_2", - "CMT_TOP_SE2A3_3", - "CMT_TOP_SE2A3_4", - "CMT_TOP_SE2A3_5", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SE2A3_7", - "CMT_TOP_SE2A3_8", - "CMT_TOP_SE2A3_9", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_SE4BEG0_12", - "CMT_TOP_SE4BEG0_13", - "CMT_TOP_SE4BEG0_14", - "CMT_TOP_SE4BEG0_15", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_SE4BEG1_10", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_SE4BEG1_12", - "CMT_TOP_SE4BEG1_13", - "CMT_TOP_SE4BEG1_14", - "CMT_TOP_SE4BEG1_15", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_SE4BEG2_10", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SE4BEG2_12", - "CMT_TOP_SE4BEG2_13", - "CMT_TOP_SE4BEG2_14", - "CMT_TOP_SE4BEG2_15", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_SE4BEG3_12", - "CMT_TOP_SE4BEG3_13", - "CMT_TOP_SE4BEG3_14", - "CMT_TOP_SE4BEG3_15", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_SE4C0_0", - "CMT_TOP_SE4C0_1", - "CMT_TOP_SE4C0_10", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE4C0_12", - "CMT_TOP_SE4C0_13", - "CMT_TOP_SE4C0_14", - "CMT_TOP_SE4C0_15", - "CMT_TOP_SE4C0_2", - "CMT_TOP_SE4C0_3", - "CMT_TOP_SE4C0_4", - "CMT_TOP_SE4C0_5", - "CMT_TOP_SE4C0_6", - "CMT_TOP_SE4C0_7", - "CMT_TOP_SE4C0_8", - "CMT_TOP_SE4C0_9", - "CMT_TOP_SE4C1_0", - "CMT_TOP_SE4C1_1", - "CMT_TOP_SE4C1_10", - "CMT_TOP_SE4C1_11", - "CMT_TOP_SE4C1_12", - "CMT_TOP_SE4C1_13", - "CMT_TOP_SE4C1_14", - "CMT_TOP_SE4C1_15", - "CMT_TOP_SE4C1_2", - "CMT_TOP_SE4C1_3", - "CMT_TOP_SE4C1_4", - "CMT_TOP_SE4C1_5", - "CMT_TOP_SE4C1_6", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE4C1_8", - "CMT_TOP_SE4C1_9", - "CMT_TOP_SE4C2_0", - "CMT_TOP_SE4C2_1", - "CMT_TOP_SE4C2_10", - "CMT_TOP_SE4C2_11", - "CMT_TOP_SE4C2_12", - "CMT_TOP_SE4C2_13", - "CMT_TOP_SE4C2_14", - "CMT_TOP_SE4C2_15", - "CMT_TOP_SE4C2_2", - "CMT_TOP_SE4C2_3", - "CMT_TOP_SE4C2_4", - "CMT_TOP_SE4C2_5", - "CMT_TOP_SE4C2_6", - "CMT_TOP_SE4C2_7", - "CMT_TOP_SE4C2_8", - "CMT_TOP_SE4C2_9", - "CMT_TOP_SE4C3_0", - "CMT_TOP_SE4C3_1", - "CMT_TOP_SE4C3_10", - "CMT_TOP_SE4C3_11", - "CMT_TOP_SE4C3_12", - "CMT_TOP_SE4C3_13", - "CMT_TOP_SE4C3_14", - "CMT_TOP_SE4C3_15", - "CMT_TOP_SE4C3_2", - "CMT_TOP_SE4C3_3", - "CMT_TOP_SE4C3_4", - "CMT_TOP_SE4C3_5", - "CMT_TOP_SE4C3_6", - "CMT_TOP_SE4C3_7", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SE4C3_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_SW2A0_1", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SW2A0_11", - "CMT_TOP_SW2A0_12", - "CMT_TOP_SW2A0_13", - "CMT_TOP_SW2A0_14", - "CMT_TOP_SW2A0_15", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW2A0_3", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW2A0_5", - "CMT_TOP_SW2A0_6", - "CMT_TOP_SW2A0_7", - "CMT_TOP_SW2A0_8", - "CMT_TOP_SW2A0_9", - "CMT_TOP_SW2A1_0", - "CMT_TOP_SW2A1_1", - "CMT_TOP_SW2A1_10", - "CMT_TOP_SW2A1_11", - "CMT_TOP_SW2A1_12", - "CMT_TOP_SW2A1_13", - "CMT_TOP_SW2A1_14", - "CMT_TOP_SW2A1_15", - "CMT_TOP_SW2A1_2", - "CMT_TOP_SW2A1_3", - "CMT_TOP_SW2A1_4", - "CMT_TOP_SW2A1_5", - "CMT_TOP_SW2A1_6", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW2A1_8", - "CMT_TOP_SW2A1_9", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW2A2_1", - "CMT_TOP_SW2A2_10", - "CMT_TOP_SW2A2_11", - "CMT_TOP_SW2A2_12", - "CMT_TOP_SW2A2_13", - "CMT_TOP_SW2A2_14", - "CMT_TOP_SW2A2_15", - "CMT_TOP_SW2A2_2", - "CMT_TOP_SW2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_SW2A2_5", - "CMT_TOP_SW2A2_6", - "CMT_TOP_SW2A2_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_SW2A2_9", - "CMT_TOP_SW2A3_0", - "CMT_TOP_SW2A3_1", - "CMT_TOP_SW2A3_10", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SW2A3_12", - "CMT_TOP_SW2A3_13", - "CMT_TOP_SW2A3_14", - "CMT_TOP_SW2A3_15", - "CMT_TOP_SW2A3_2", - "CMT_TOP_SW2A3_3", - "CMT_TOP_SW2A3_4", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW2A3_6", - "CMT_TOP_SW2A3_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SW2A3_9", - "CMT_TOP_SW4A0_0", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SW4A0_10", - "CMT_TOP_SW4A0_11", - "CMT_TOP_SW4A0_12", - "CMT_TOP_SW4A0_13", - "CMT_TOP_SW4A0_14", - "CMT_TOP_SW4A0_15", - "CMT_TOP_SW4A0_2", - "CMT_TOP_SW4A0_3", - "CMT_TOP_SW4A0_4", - "CMT_TOP_SW4A0_5", - "CMT_TOP_SW4A0_6", - "CMT_TOP_SW4A0_7", - "CMT_TOP_SW4A0_8", - "CMT_TOP_SW4A0_9", - "CMT_TOP_SW4A1_0", - "CMT_TOP_SW4A1_1", - "CMT_TOP_SW4A1_10", - "CMT_TOP_SW4A1_11", - "CMT_TOP_SW4A1_12", - "CMT_TOP_SW4A1_13", - "CMT_TOP_SW4A1_14", - "CMT_TOP_SW4A1_15", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW4A1_3", - "CMT_TOP_SW4A1_4", - "CMT_TOP_SW4A1_5", - "CMT_TOP_SW4A1_6", - "CMT_TOP_SW4A1_7", - "CMT_TOP_SW4A1_8", - "CMT_TOP_SW4A1_9", - "CMT_TOP_SW4A2_0", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SW4A2_10", - "CMT_TOP_SW4A2_11", - "CMT_TOP_SW4A2_12", - "CMT_TOP_SW4A2_13", - "CMT_TOP_SW4A2_14", - "CMT_TOP_SW4A2_15", - "CMT_TOP_SW4A2_2", - "CMT_TOP_SW4A2_3", - "CMT_TOP_SW4A2_4", - "CMT_TOP_SW4A2_5", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SW4A2_7", - "CMT_TOP_SW4A2_8", - "CMT_TOP_SW4A2_9", - "CMT_TOP_SW4A3_0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_SW4A3_10", - "CMT_TOP_SW4A3_11", - "CMT_TOP_SW4A3_12", - "CMT_TOP_SW4A3_13", - "CMT_TOP_SW4A3_14", - "CMT_TOP_SW4A3_15", - "CMT_TOP_SW4A3_2", - "CMT_TOP_SW4A3_3", - "CMT_TOP_SW4A3_4", - "CMT_TOP_SW4A3_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SW4A3_7", - "CMT_TOP_SW4A3_8", - "CMT_TOP_SW4A3_9", - "CMT_TOP_SW4END0_0", - "CMT_TOP_SW4END0_1", - "CMT_TOP_SW4END0_10", - "CMT_TOP_SW4END0_11", - "CMT_TOP_SW4END0_12", - "CMT_TOP_SW4END0_13", - "CMT_TOP_SW4END0_14", - "CMT_TOP_SW4END0_15", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SW4END0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_SW4END0_5", - "CMT_TOP_SW4END0_6", - "CMT_TOP_SW4END0_7", - "CMT_TOP_SW4END0_8", - "CMT_TOP_SW4END0_9", - "CMT_TOP_SW4END1_0", - "CMT_TOP_SW4END1_1", - "CMT_TOP_SW4END1_10", - "CMT_TOP_SW4END1_11", - "CMT_TOP_SW4END1_12", - "CMT_TOP_SW4END1_13", - "CMT_TOP_SW4END1_14", - "CMT_TOP_SW4END1_15", - "CMT_TOP_SW4END1_2", - "CMT_TOP_SW4END1_3", - "CMT_TOP_SW4END1_4", - "CMT_TOP_SW4END1_5", - "CMT_TOP_SW4END1_6", - "CMT_TOP_SW4END1_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_SW4END1_9", - "CMT_TOP_SW4END2_0", - "CMT_TOP_SW4END2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_SW4END2_11", - "CMT_TOP_SW4END2_12", - "CMT_TOP_SW4END2_13", - "CMT_TOP_SW4END2_14", - "CMT_TOP_SW4END2_15", - "CMT_TOP_SW4END2_2", - "CMT_TOP_SW4END2_3", - "CMT_TOP_SW4END2_4", - "CMT_TOP_SW4END2_5", - "CMT_TOP_SW4END2_6", - "CMT_TOP_SW4END2_7", - "CMT_TOP_SW4END2_8", - "CMT_TOP_SW4END2_9", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SW4END3_1", - "CMT_TOP_SW4END3_10", - "CMT_TOP_SW4END3_11", - "CMT_TOP_SW4END3_12", - "CMT_TOP_SW4END3_13", - "CMT_TOP_SW4END3_14", - "CMT_TOP_SW4END3_15", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_3", - "CMT_TOP_SW4END3_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SW4END3_6", - "CMT_TOP_SW4END3_7", - "CMT_TOP_SW4END3_8", - "CMT_TOP_SW4END3_9", - "CMT_TOP_WL1END0_0", - "CMT_TOP_WL1END0_1", - "CMT_TOP_WL1END0_10", - "CMT_TOP_WL1END0_11", - "CMT_TOP_WL1END0_12", - "CMT_TOP_WL1END0_13", - "CMT_TOP_WL1END0_14", - "CMT_TOP_WL1END0_15", - "CMT_TOP_WL1END0_2", - "CMT_TOP_WL1END0_3", - "CMT_TOP_WL1END0_4", - "CMT_TOP_WL1END0_5", - "CMT_TOP_WL1END0_6", - "CMT_TOP_WL1END0_7", - "CMT_TOP_WL1END0_8", - "CMT_TOP_WL1END0_9", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WL1END1_1", - "CMT_TOP_WL1END1_10", - "CMT_TOP_WL1END1_11", - "CMT_TOP_WL1END1_12", - "CMT_TOP_WL1END1_13", - "CMT_TOP_WL1END1_14", - "CMT_TOP_WL1END1_15", - "CMT_TOP_WL1END1_2", - "CMT_TOP_WL1END1_3", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_5", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WL1END1_7", - "CMT_TOP_WL1END1_8", - "CMT_TOP_WL1END1_9", - "CMT_TOP_WL1END2_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_WL1END2_10", - "CMT_TOP_WL1END2_11", - "CMT_TOP_WL1END2_12", - "CMT_TOP_WL1END2_13", - "CMT_TOP_WL1END2_14", - "CMT_TOP_WL1END2_15", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WL1END2_3", - "CMT_TOP_WL1END2_4", - "CMT_TOP_WL1END2_5", - "CMT_TOP_WL1END2_6", - "CMT_TOP_WL1END2_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_WL1END2_9", - "CMT_TOP_WL1END3_0", - "CMT_TOP_WL1END3_1", - "CMT_TOP_WL1END3_10", - "CMT_TOP_WL1END3_11", - "CMT_TOP_WL1END3_12", - "CMT_TOP_WL1END3_13", - "CMT_TOP_WL1END3_14", - "CMT_TOP_WL1END3_15", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WL1END3_3", - "CMT_TOP_WL1END3_4", - "CMT_TOP_WL1END3_5", - "CMT_TOP_WL1END3_6", - "CMT_TOP_WL1END3_7", - "CMT_TOP_WL1END3_8", - "CMT_TOP_WL1END3_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_WR1END0_1", - "CMT_TOP_WR1END0_10", - "CMT_TOP_WR1END0_11", - "CMT_TOP_WR1END0_12", - "CMT_TOP_WR1END0_13", - "CMT_TOP_WR1END0_14", - "CMT_TOP_WR1END0_15", - "CMT_TOP_WR1END0_2", - "CMT_TOP_WR1END0_3", - "CMT_TOP_WR1END0_4", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WR1END0_6", - "CMT_TOP_WR1END0_7", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WR1END1_0", - "CMT_TOP_WR1END1_1", - "CMT_TOP_WR1END1_10", - "CMT_TOP_WR1END1_11", - "CMT_TOP_WR1END1_12", - "CMT_TOP_WR1END1_13", - "CMT_TOP_WR1END1_14", - "CMT_TOP_WR1END1_15", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WR1END1_4", - "CMT_TOP_WR1END1_5", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END1_7", - "CMT_TOP_WR1END1_8", - "CMT_TOP_WR1END1_9", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WR1END2_10", - "CMT_TOP_WR1END2_11", - "CMT_TOP_WR1END2_12", - "CMT_TOP_WR1END2_13", - "CMT_TOP_WR1END2_14", - "CMT_TOP_WR1END2_15", - "CMT_TOP_WR1END2_2", - "CMT_TOP_WR1END2_3", - "CMT_TOP_WR1END2_4", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WR1END2_6", - "CMT_TOP_WR1END2_7", - "CMT_TOP_WR1END2_8", - "CMT_TOP_WR1END2_9", - "CMT_TOP_WR1END3_0", - "CMT_TOP_WR1END3_1", - "CMT_TOP_WR1END3_10", - "CMT_TOP_WR1END3_11", - "CMT_TOP_WR1END3_12", - "CMT_TOP_WR1END3_13", - "CMT_TOP_WR1END3_14", - "CMT_TOP_WR1END3_15", - "CMT_TOP_WR1END3_2", - "CMT_TOP_WR1END3_3", - "CMT_TOP_WR1END3_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_WR1END3_6", - "CMT_TOP_WR1END3_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_WR1END3_9", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW2A0_1", - "CMT_TOP_WW2A0_10", - "CMT_TOP_WW2A0_11", - "CMT_TOP_WW2A0_12", - "CMT_TOP_WW2A0_13", - "CMT_TOP_WW2A0_14", - "CMT_TOP_WW2A0_15", - "CMT_TOP_WW2A0_2", - "CMT_TOP_WW2A0_3", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2A0_5", - "CMT_TOP_WW2A0_6", - "CMT_TOP_WW2A0_7", - "CMT_TOP_WW2A0_8", - "CMT_TOP_WW2A0_9", - "CMT_TOP_WW2A1_0", - "CMT_TOP_WW2A1_1", - "CMT_TOP_WW2A1_10", - "CMT_TOP_WW2A1_11", - "CMT_TOP_WW2A1_12", - "CMT_TOP_WW2A1_13", - "CMT_TOP_WW2A1_14", - "CMT_TOP_WW2A1_15", - "CMT_TOP_WW2A1_2", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WW2A1_4", - "CMT_TOP_WW2A1_5", - "CMT_TOP_WW2A1_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_WW2A1_8", - "CMT_TOP_WW2A1_9", - "CMT_TOP_WW2A2_0", - "CMT_TOP_WW2A2_1", - "CMT_TOP_WW2A2_10", - "CMT_TOP_WW2A2_11", - "CMT_TOP_WW2A2_12", - "CMT_TOP_WW2A2_13", - "CMT_TOP_WW2A2_14", - "CMT_TOP_WW2A2_15", - "CMT_TOP_WW2A2_2", - "CMT_TOP_WW2A2_3", - "CMT_TOP_WW2A2_4", - "CMT_TOP_WW2A2_5", - "CMT_TOP_WW2A2_6", - "CMT_TOP_WW2A2_7", - "CMT_TOP_WW2A2_8", - "CMT_TOP_WW2A2_9", - "CMT_TOP_WW2A3_0", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW2A3_10", - "CMT_TOP_WW2A3_11", - "CMT_TOP_WW2A3_12", - "CMT_TOP_WW2A3_13", - "CMT_TOP_WW2A3_14", - "CMT_TOP_WW2A3_15", - "CMT_TOP_WW2A3_2", - "CMT_TOP_WW2A3_3", - "CMT_TOP_WW2A3_4", - "CMT_TOP_WW2A3_5", - "CMT_TOP_WW2A3_6", - "CMT_TOP_WW2A3_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_WW2A3_9", - "CMT_TOP_WW2END0_0", - "CMT_TOP_WW2END0_1", - "CMT_TOP_WW2END0_10", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW2END0_12", - "CMT_TOP_WW2END0_13", - "CMT_TOP_WW2END0_14", - "CMT_TOP_WW2END0_15", - "CMT_TOP_WW2END0_2", - "CMT_TOP_WW2END0_3", - "CMT_TOP_WW2END0_4", - "CMT_TOP_WW2END0_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_WW2END0_7", - "CMT_TOP_WW2END0_8", - "CMT_TOP_WW2END0_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_WW2END1_1", - "CMT_TOP_WW2END1_10", - "CMT_TOP_WW2END1_11", - "CMT_TOP_WW2END1_12", - "CMT_TOP_WW2END1_13", - "CMT_TOP_WW2END1_14", - "CMT_TOP_WW2END1_15", - "CMT_TOP_WW2END1_2", - "CMT_TOP_WW2END1_3", - "CMT_TOP_WW2END1_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WW2END1_7", - "CMT_TOP_WW2END1_8", - "CMT_TOP_WW2END1_9", - "CMT_TOP_WW2END2_0", - "CMT_TOP_WW2END2_1", - "CMT_TOP_WW2END2_10", - "CMT_TOP_WW2END2_11", - "CMT_TOP_WW2END2_12", - "CMT_TOP_WW2END2_13", - "CMT_TOP_WW2END2_14", - "CMT_TOP_WW2END2_15", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW2END2_3", - "CMT_TOP_WW2END2_4", - "CMT_TOP_WW2END2_5", - "CMT_TOP_WW2END2_6", - "CMT_TOP_WW2END2_7", - "CMT_TOP_WW2END2_8", - "CMT_TOP_WW2END2_9", - "CMT_TOP_WW2END3_0", - "CMT_TOP_WW2END3_1", - "CMT_TOP_WW2END3_10", - "CMT_TOP_WW2END3_11", - "CMT_TOP_WW2END3_12", - "CMT_TOP_WW2END3_13", - "CMT_TOP_WW2END3_14", - "CMT_TOP_WW2END3_15", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END3_3", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WW2END3_5", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END3_7", - "CMT_TOP_WW2END3_8", - "CMT_TOP_WW2END3_9", - "CMT_TOP_WW4A0_0", - "CMT_TOP_WW4A0_1", - "CMT_TOP_WW4A0_10", - "CMT_TOP_WW4A0_11", - "CMT_TOP_WW4A0_12", - "CMT_TOP_WW4A0_13", - "CMT_TOP_WW4A0_14", - "CMT_TOP_WW4A0_15", - "CMT_TOP_WW4A0_2", - "CMT_TOP_WW4A0_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_WW4A0_5", - "CMT_TOP_WW4A0_6", - "CMT_TOP_WW4A0_7", - "CMT_TOP_WW4A0_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4A1_1", - "CMT_TOP_WW4A1_10", - "CMT_TOP_WW4A1_11", - "CMT_TOP_WW4A1_12", - "CMT_TOP_WW4A1_13", - "CMT_TOP_WW4A1_14", - "CMT_TOP_WW4A1_15", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW4A1_3", - "CMT_TOP_WW4A1_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_WW4A1_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4A1_9", - "CMT_TOP_WW4A2_0", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4A2_10", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WW4A2_12", - "CMT_TOP_WW4A2_13", - "CMT_TOP_WW4A2_14", - "CMT_TOP_WW4A2_15", - "CMT_TOP_WW4A2_2", - "CMT_TOP_WW4A2_3", - "CMT_TOP_WW4A2_4", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW4A2_6", - "CMT_TOP_WW4A2_7", - "CMT_TOP_WW4A2_8", - "CMT_TOP_WW4A2_9", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW4A3_10", - "CMT_TOP_WW4A3_11", - "CMT_TOP_WW4A3_12", - "CMT_TOP_WW4A3_13", - "CMT_TOP_WW4A3_14", - "CMT_TOP_WW4A3_15", - "CMT_TOP_WW4A3_2", - "CMT_TOP_WW4A3_3", - "CMT_TOP_WW4A3_4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_WW4A3_6", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WW4A3_8", - "CMT_TOP_WW4A3_9", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4B0_10", - "CMT_TOP_WW4B0_11", - "CMT_TOP_WW4B0_12", - "CMT_TOP_WW4B0_13", - "CMT_TOP_WW4B0_14", - "CMT_TOP_WW4B0_15", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4B0_3", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4B0_5", - "CMT_TOP_WW4B0_6", - "CMT_TOP_WW4B0_7", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B0_9", - "CMT_TOP_WW4B1_0", - "CMT_TOP_WW4B1_1", - "CMT_TOP_WW4B1_10", - "CMT_TOP_WW4B1_11", - "CMT_TOP_WW4B1_12", - "CMT_TOP_WW4B1_13", - "CMT_TOP_WW4B1_14", - "CMT_TOP_WW4B1_15", - "CMT_TOP_WW4B1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_5", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4B1_7", - "CMT_TOP_WW4B1_8", - "CMT_TOP_WW4B1_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_WW4B2_1", - "CMT_TOP_WW4B2_10", - "CMT_TOP_WW4B2_11", - "CMT_TOP_WW4B2_12", - "CMT_TOP_WW4B2_13", - "CMT_TOP_WW4B2_14", - "CMT_TOP_WW4B2_15", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4B2_4", - "CMT_TOP_WW4B2_5", - "CMT_TOP_WW4B2_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_WW4B2_8", - "CMT_TOP_WW4B2_9", - "CMT_TOP_WW4B3_0", - "CMT_TOP_WW4B3_1", - "CMT_TOP_WW4B3_10", - "CMT_TOP_WW4B3_11", - "CMT_TOP_WW4B3_12", - "CMT_TOP_WW4B3_13", - "CMT_TOP_WW4B3_14", - "CMT_TOP_WW4B3_15", - "CMT_TOP_WW4B3_2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_WW4B3_4", - "CMT_TOP_WW4B3_5", - "CMT_TOP_WW4B3_6", - "CMT_TOP_WW4B3_7", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW4B3_9", - "CMT_TOP_WW4C0_0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_WW4C0_10", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4C0_12", - "CMT_TOP_WW4C0_13", - "CMT_TOP_WW4C0_14", - "CMT_TOP_WW4C0_15", - "CMT_TOP_WW4C0_2", - "CMT_TOP_WW4C0_3", - "CMT_TOP_WW4C0_4", - "CMT_TOP_WW4C0_5", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4C0_8", - "CMT_TOP_WW4C0_9", - "CMT_TOP_WW4C1_0", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C1_11", - "CMT_TOP_WW4C1_12", - "CMT_TOP_WW4C1_13", - "CMT_TOP_WW4C1_14", - "CMT_TOP_WW4C1_15", - "CMT_TOP_WW4C1_2", - "CMT_TOP_WW4C1_3", - "CMT_TOP_WW4C1_4", - "CMT_TOP_WW4C1_5", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4C1_7", - "CMT_TOP_WW4C1_8", - "CMT_TOP_WW4C1_9", - "CMT_TOP_WW4C2_0", - "CMT_TOP_WW4C2_1", - "CMT_TOP_WW4C2_10", - "CMT_TOP_WW4C2_11", - "CMT_TOP_WW4C2_12", - "CMT_TOP_WW4C2_13", - "CMT_TOP_WW4C2_14", - "CMT_TOP_WW4C2_15", - "CMT_TOP_WW4C2_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_WW4C2_4", - "CMT_TOP_WW4C2_5", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WW4C2_8", - "CMT_TOP_WW4C2_9", - "CMT_TOP_WW4C3_0", - "CMT_TOP_WW4C3_1", - "CMT_TOP_WW4C3_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_WW4C3_12", - "CMT_TOP_WW4C3_13", - "CMT_TOP_WW4C3_14", - "CMT_TOP_WW4C3_15", - "CMT_TOP_WW4C3_2", - "CMT_TOP_WW4C3_3", - "CMT_TOP_WW4C3_4", - "CMT_TOP_WW4C3_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW4C3_8", - "CMT_TOP_WW4C3_9", - "CMT_TOP_WW4END0_0", - "CMT_TOP_WW4END0_1", - "CMT_TOP_WW4END0_10", - "CMT_TOP_WW4END0_11", - "CMT_TOP_WW4END0_12", - "CMT_TOP_WW4END0_13", - "CMT_TOP_WW4END0_14", - "CMT_TOP_WW4END0_15", - "CMT_TOP_WW4END0_2", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_5", - "CMT_TOP_WW4END0_6", - "CMT_TOP_WW4END0_7", - "CMT_TOP_WW4END0_8", - "CMT_TOP_WW4END0_9", - "CMT_TOP_WW4END1_0", - "CMT_TOP_WW4END1_1", - "CMT_TOP_WW4END1_10", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WW4END1_12", - "CMT_TOP_WW4END1_13", - "CMT_TOP_WW4END1_14", - "CMT_TOP_WW4END1_15", - "CMT_TOP_WW4END1_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END1_6", - "CMT_TOP_WW4END1_7", - "CMT_TOP_WW4END1_8", - "CMT_TOP_WW4END1_9", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW4END2_1", - "CMT_TOP_WW4END2_10", - "CMT_TOP_WW4END2_11", - "CMT_TOP_WW4END2_12", - "CMT_TOP_WW4END2_13", - "CMT_TOP_WW4END2_14", - "CMT_TOP_WW4END2_15", - "CMT_TOP_WW4END2_2", - "CMT_TOP_WW4END2_3", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_WW4END2_7", - "CMT_TOP_WW4END2_8", - "CMT_TOP_WW4END2_9", - "CMT_TOP_WW4END3_0", - "CMT_TOP_WW4END3_1", - "CMT_TOP_WW4END3_10", - "CMT_TOP_WW4END3_11", - "CMT_TOP_WW4END3_12", - "CMT_TOP_WW4END3_13", - "CMT_TOP_WW4END3_14", - "CMT_TOP_WW4END3_15", - "CMT_TOP_WW4END3_2", - "CMT_TOP_WW4END3_3", - "CMT_TOP_WW4END3_4", - "CMT_TOP_WW4END3_5", - "CMT_TOP_WW4END3_6", - "CMT_TOP_WW4END3_7", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4END3_9", - "MMCMOUT_CLK_FREQ_BB_0", - "MMCMOUT_CLK_FREQ_BB_1", - "MMCMOUT_CLK_FREQ_BB_2", - "MMCMOUT_CLK_FREQ_BB_3", - "MMCM_CLK_FREQ_BB_NS0", - "MMCM_CLK_FREQ_BB_NS1", - "MMCM_CLK_FREQ_BB_NS2", - "MMCM_CLK_FREQ_BB_NS3", - "MMCM_CLK_FREQ_BB_REBUF0_NS", - "MMCM_CLK_FREQ_BB_REBUF1_NS", - "MMCM_CLK_FREQ_BB_REBUF2_NS", - "MMCM_CLK_FREQ_BB_REBUF3_NS" - ] + "wires": { + "CMT_LR_LOWER_B_CLKFBOUT2IN": null, + "CMT_LR_LOWER_B_MMCM_CLKFBIN": null, + "CMT_LR_LOWER_B_MMCM_CLKFBOUT": null, + "CMT_LR_LOWER_B_MMCM_CLKFBOUTB": null, + "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED": null, + "CMT_LR_LOWER_B_MMCM_CLKIN1": null, + "CMT_LR_LOWER_B_MMCM_CLKIN2": null, + "CMT_LR_LOWER_B_MMCM_CLKINSEL": null, + "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT0": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT0B": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT1": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT1B": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT2": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT2B": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT3": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT3B": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT4": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT5": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT6": null, + "CMT_LR_LOWER_B_MMCM_DADDR0": null, + "CMT_LR_LOWER_B_MMCM_DADDR1": null, + "CMT_LR_LOWER_B_MMCM_DADDR2": null, + "CMT_LR_LOWER_B_MMCM_DADDR3": null, + "CMT_LR_LOWER_B_MMCM_DADDR4": null, + "CMT_LR_LOWER_B_MMCM_DADDR5": null, + "CMT_LR_LOWER_B_MMCM_DADDR6": null, + "CMT_LR_LOWER_B_MMCM_DCLK": null, + "CMT_LR_LOWER_B_MMCM_DEN": null, + "CMT_LR_LOWER_B_MMCM_DI0": null, + "CMT_LR_LOWER_B_MMCM_DI1": null, + "CMT_LR_LOWER_B_MMCM_DI10": null, + "CMT_LR_LOWER_B_MMCM_DI11": null, + "CMT_LR_LOWER_B_MMCM_DI12": null, + "CMT_LR_LOWER_B_MMCM_DI13": null, + "CMT_LR_LOWER_B_MMCM_DI14": null, + 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"res": "317.510" + }, + "CMT_TOP_WW4END3_10": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_11": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_12": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_13": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_14": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_15": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_4": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_5": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_6": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_7": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_8": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_9": { + "cap": "18.000", + "res": "317.510" + }, + "MMCMOUT_CLK_FREQ_BB_0": null, + "MMCMOUT_CLK_FREQ_BB_1": null, + "MMCMOUT_CLK_FREQ_BB_2": null, + "MMCMOUT_CLK_FREQ_BB_3": null, + "MMCM_CLK_FREQ_BB_NS0": null, + "MMCM_CLK_FREQ_BB_NS1": null, + "MMCM_CLK_FREQ_BB_NS2": null, + "MMCM_CLK_FREQ_BB_NS3": null, + "MMCM_CLK_FREQ_BB_REBUF0_NS": null, + "MMCM_CLK_FREQ_BB_REBUF1_NS": null, + "MMCM_CLK_FREQ_BB_REBUF2_NS": null, + "MMCM_CLK_FREQ_BB_REBUF3_NS": null + } } diff --git a/zynq7/tile_type_CMT_TOP_L_LOWER_T.json b/zynq7/tile_type_CMT_TOP_L_LOWER_T.json index 1484003..96d50b7 100644 --- a/zynq7/tile_type_CMT_TOP_L_LOWER_T.json +++ b/zynq7/tile_type_CMT_TOP_L_LOWER_T.json @@ -2,1962 +2,6082 @@ "pips": { "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_A->CMT_PHASER_IN_CA_PHASEREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" }, "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_B->CMT_PHASER_IN_DB_PHASEREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" }, "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_A->CMT_PHASER_OUT_CA_PHASEREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" }, "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_B->CMT_PHASER_OUT_DB_PHASEREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING0->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_IBURSTPENDING0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING1->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_IBURSTPENDING1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKA0->CMT_PHASER_IN_CA_RANKSELPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_IRANKA0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKA1->CMT_PHASER_IN_CA_RANKSELPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_IRANKA1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKB0->CMT_PHASER_IN_DB_RANKSELPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_IRANKB0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_IRANKB1->CMT_PHASER_IN_DB_RANKSELPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_IRANKB1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING0->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_OBURSTPENDING0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING1->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_OBURSTPENDING1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.086", + "0.095", + "0.241", + "0.265" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.086", + "0.095", + "0.241", + "0.265" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_BOT_REFMUX_0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.241", + "0.265" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.241", + "0.265" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_BOT_REFMUX_0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.089", + "0.098", + "0.252", + "0.277" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.089", + "0.098", + "0.252", + "0.277" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_BOT_REFMUX_0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.089", + "0.098", + "0.252", + "0.277" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.089", + "0.098", + "0.252", + "0.277" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_BOT_REFMUX_0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.086", + "0.095", + "0.241", + "0.265" + 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"delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.114", + "0.228", + "0.276" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_CA_RCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.114", + "0.228", + "0.276" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_A_RCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_A_RCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_RCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_A_WREN_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_A_WREN_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_WRENABLE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_DQSFOUND" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_B_ICLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_B_ICLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ICLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_B_WRCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ICLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ISERDESRST" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.114", + "0.228", + "0.276" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_DB_RCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.114", + "0.228", + "0.276" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_B_RCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_B_RCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_RCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_B_WREN_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_B_WREN_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_WRENABLE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO->CMT_PHASER_OUT_A_OCLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_OCLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK->>CMT_PHASER_B_OCLK_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.092", + "0.102" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_B_OCLK_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.092", + "0.102" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_B_OCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90->>CMT_PHASER_B_OCLK90_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.030", + "0.033", + "0.085", + "0.094" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_B_OCLK90_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.030", + "0.033", + "0.085", + "0.094" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_B_OCLK1X_90" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV->>CMT_PHASER_B_OCLKDIV_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.036", + "0.095", + "0.104" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.036", + "0.095", + "0.104" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_B_OCLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO->CMT_PHASER_OUT_B_OCLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_OCLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS0->CMT_PHASERA_CTSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_CTSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS1->CMT_PHASERA_CTSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_CTSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS0->CMT_PHASERA_DQSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_DQSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS1->CMT_PHASERA_DQSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_DQSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS0->CMT_PHASERA_DTSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_DTSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS1->CMT_PHASERA_DTSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_DTSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_A_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_A_OCLK1X_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_OCLK1X_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_A_RDCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_A_RDEN_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_RDEN_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_RDENABLE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_B_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_B_OCLK1X_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_OCLK1X_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLKDIV->CMT_PHASER_OUT_B_RDCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_RDENABLE->CMT_PHASER_OUT_B_RDEN_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_RDEN_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_RDENABLE" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_1->CMT_PHASER_OUT_CA_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_2->CMT_PHASER_IN_CA_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_6->CMT_PHASER_IN_DB_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_8->>CMT_BOT_HCLKMUX_CLKINT_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_CLK0_8" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK1_8->>CMT_BOT_HCLKMUX_CLKINT_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_CLK1_8" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_7->CMT_PHASER_IN_DB_RSTDQSFIND": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX11_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX11_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX12_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX12_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX12_4->CMT_PHASER_IN_CA_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX12_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_5->CMT_PHASER_OUT_DB_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_6->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_5->CMT_PHASER_OUT_DB_COARSEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX1_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX20_4->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX21_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX21_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_4->CMT_PHASER_OUT_DB_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_6->CMT_PHASER_IN_DB_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX25_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX25_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX25_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX25_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_4->CMT_PHASER_IN_CA_RANKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX28_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX28_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_5->CMT_PHASER_OUT_DB_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_6->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX2_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_5->CMT_PHASER_OUT_DB_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_7->CMT_PHASER_IN_DB_RANKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX32_2->CMT_PHASER_OUT_CA_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX32_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX34_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX39_4->CMT_PHASER_OUT_DB_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX39_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX41_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX43_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX43_4->CMT_PHASER_IN_CA_RANKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_6->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_5->CMT_PHASER_OUT_DB_COARSEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX46_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_5->CMT_PHASER_OUT_DB_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_6->CMT_PHASER_IN_DB_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_7->CMT_PHASER_IN_DB_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX8_3->CMT_PHASER_IN_CA_RSTDQSFIND": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX8_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX9_2" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.131", + "0.144", + "0.380", + "0.419" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT0->>MMCM_CLK_FREQBB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT1->>MMCM_CLK_FREQBB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT2->>MMCM_CLK_FREQBB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT3->>MMCM_CLK_FREQBB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3" } }, @@ -1966,83 +6086,776 @@ "name": "X0Y0", "prefix": "PHASER_OUT_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", - "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", - "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", - "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", - "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", - "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", - "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", - "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", - "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", - "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", - "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", - "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", - "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", - "OCLK": "CMT_PHASER_OUT_CA_OCLK", - "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", - "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", - "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", - "RST": "CMT_PHASER_OUT_CA_RST", - "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", - "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", - "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", - "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", - "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", - "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", - "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", - "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", - "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", - "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", - "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", - "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", - "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", - "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", - "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", - "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", - "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", - "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", - "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", - "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", - "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", - "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", - "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", - "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", - "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_BURSTPENDING" + }, + "BURSTPENDINGPHY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY" + }, + "COARSEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COARSEENABLE" + }, + "COARSEINC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COARSEINC" + }, + "COARSEOVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW" + }, + "COUNTERLOADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN" + }, + "COUNTERLOADVAL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0" + }, + "COUNTERLOADVAL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1" + }, + "COUNTERLOADVAL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2" + }, + "COUNTERLOADVAL3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3" + }, + "COUNTERLOADVAL4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4" + }, + "COUNTERLOADVAL5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5" + }, + "COUNTERLOADVAL6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6" + }, + "COUNTERLOADVAL7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7" + }, + "COUNTERLOADVAL8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8" + }, + "COUNTERREADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERREADEN" + }, + "COUNTERREADVAL0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0" + }, + "COUNTERREADVAL1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1" + }, + "COUNTERREADVAL2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2" + }, + "COUNTERREADVAL3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3" + }, + "COUNTERREADVAL4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4" + }, + "COUNTERREADVAL5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5" + }, + "COUNTERREADVAL6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6" + }, + "COUNTERREADVAL7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7" + }, + "COUNTERREADVAL8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8" + }, + "CTSBUS0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_CTSBUS0" + }, + "CTSBUS1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_CTSBUS1" + }, + "DIVIDERST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_DIVIDERST" + }, + "DQSBUS0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_DQSBUS0" + }, + "DQSBUS1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_DQSBUS1" + }, + "DTSBUS0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_DTSBUS0" + }, + "DTSBUS1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_DTSBUS1" + }, + "EDGEADV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_EDGEADV" + }, + "ENCALIB0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_ENCALIB0" + }, + "ENCALIB1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_ENCALIB1" + }, + "ENCALIBPHY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0" + }, + "ENCALIBPHY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1" + }, + "FINEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_FINEENABLE" + }, + "FINEINC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_FINEINC" + }, + "FINEOVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW" + }, + "FREQREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_FREQREFCLK" + }, + "MEMREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_MEMREFCLK" + }, + "OCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_OCLK" + }, + "OCLKDELAYED": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_OCLKDELAYED" + }, + "OCLKDIV": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_OCLKDIV" + }, + "OSERDESRST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_OSERDESRST" + }, + "PHASEREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_PHASEREFCLK" + }, + "RDENABLE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_RDENABLE" + }, + "RST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_RST" + }, + "SCANCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SCANCLK" + }, + "SCANENB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SCANENB" + }, + "SCANIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SCANIN" + }, + "SCANMODEB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SCANMODEB" + }, + "SCANOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_SCANOUT" + }, + "SELFINEOCLKDELAY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY" + }, + "SYNCIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SYNCIN" + }, + "SYSCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SYSCLK" + }, + "TESTIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN0" + }, + "TESTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN1" + }, + "TESTIN10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN10" + }, + "TESTIN11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN11" + }, + "TESTIN12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN12" + }, + "TESTIN13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN13" + }, + "TESTIN14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN14" + }, + "TESTIN15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN15" + }, + "TESTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN2" + }, + "TESTIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN3" + }, + "TESTIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN4" + }, + "TESTIN5": { + "cap": "0.000", + "delay": [ + "0.000", + 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"wire": "CMT_PHASER_OUT_CA_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_TESTOUT3" + } }, "type": "PHASER_OUT_PHY", "x_coord": 0, @@ -2052,98 +6865,926 @@ "name": "X0Y0", "prefix": "PHASER_IN_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "COUNTERREADVAL2": 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"CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST", - "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", - "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", - "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", - "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", - "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", - "FINEINC": "CMT_PHASER_IN_DB_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", - "ICLK": "CMT_PHASER_IN_DB_ICLK", - "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", - "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", - "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", - "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", - "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", - "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", - "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", - "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", - "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", - "RCLK": "CMT_PHASER_IN_DB_RCLK", - "RST": "CMT_PHASER_IN_DB_RST", - "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", - "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", - "SCANENB": "CMT_PHASER_IN_DB_SCANENB", - "SCANIN": "CMT_PHASER_IN_DB_SCANIN", - "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", - "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", - "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", - "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", - "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", - "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", - "STG1READ": "CMT_PHASER_IN_DB_STG1READ", - "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", - "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", - "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", - "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", - "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", - "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", - "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", - "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", - "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", - "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", - "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", - "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", - "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", - "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", - "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", - "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", - "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", - "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", - "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", - "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", - "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", - "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", - "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", - "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", - "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", - "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", - "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", - "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", - "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", - "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", - "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", - "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", - "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", - "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", - "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1", - "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", - "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", - "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": 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"CMT_BOT_HCLKMUX_CLKINT_0", - "CMT_BOT_HCLKMUX_CLKINT_1", - "CMT_LR_LOWER_T_CLK_IN1_HCLK", - "CMT_LR_LOWER_T_CLK_IN2_HCLK", - "CMT_LR_LOWER_T_CLK_IN3_HCLK", - "CMT_LR_LOWER_T_CLK_MMCM0", - "CMT_LR_LOWER_T_CLK_MMCM1", - "CMT_LR_LOWER_T_CLK_MMCM10", - "CMT_LR_LOWER_T_CLK_MMCM11", - "CMT_LR_LOWER_T_CLK_MMCM12", - "CMT_LR_LOWER_T_CLK_MMCM13", - "CMT_LR_LOWER_T_CLK_MMCM2", - "CMT_LR_LOWER_T_CLK_MMCM3", - "CMT_LR_LOWER_T_CLK_MMCM4", - "CMT_LR_LOWER_T_CLK_MMCM5", - "CMT_LR_LOWER_T_CLK_MMCM6", - "CMT_LR_LOWER_T_CLK_MMCM7", - "CMT_LR_LOWER_T_CLK_MMCM8", - "CMT_LR_LOWER_T_CLK_MMCM9", - "CMT_LR_LOWER_T_CLK_PERF0", - "CMT_LR_LOWER_T_CLK_PERF1", - "CMT_LR_LOWER_T_CLK_PERF2", - "CMT_LR_LOWER_T_CLK_PERF3", - "CMT_PHASERA_CTSBUS0", - "CMT_PHASERA_CTSBUS1", - "CMT_PHASERA_DQSBUS0", - "CMT_PHASERA_DQSBUS1", - "CMT_PHASERA_DTSBUS0", - "CMT_PHASERA_DTSBUS1", - "CMT_PHASERREF_DOWN_PHASERIN_A", - "CMT_PHASERREF_DOWN_PHASERIN_B", - "CMT_PHASERREF_DOWN_PHASEROUT_A", - "CMT_PHASERREF_DOWN_PHASEROUT_B", - "CMT_PHASER_BOT_ENCALIB0", - "CMT_PHASER_BOT_ENCALIB1", - "CMT_PHASER_BOT_IBURSTPENDING0", - "CMT_PHASER_BOT_IBURSTPENDING1", - "CMT_PHASER_BOT_IRANKA0", - "CMT_PHASER_BOT_IRANKA1", - "CMT_PHASER_BOT_IRANKB0", - "CMT_PHASER_BOT_IRANKB1", - "CMT_PHASER_BOT_OBURSTPENDING0", - "CMT_PHASER_BOT_OBURSTPENDING1", - "CMT_PHASER_BOT_REFMUX_0", - "CMT_PHASER_BOT_REFMUX_1", - "CMT_PHASER_BOT_REFMUX_2", - "CMT_PHASER_BOT_SYNC_BB", - "CMT_PHASER_B_ICLKDIV_TOIOI", - "CMT_PHASER_B_ICLK_TOIOI", - "CMT_PHASER_B_OCLK90_TOIOI", - "CMT_PHASER_B_OCLKDIV_TOIOI", - "CMT_PHASER_B_OCLK_TOIOI", - "CMT_PHASER_B_TOMMCM_ICLK", - "CMT_PHASER_B_TOMMCM_ICLKDIV", - "CMT_PHASER_B_TOMMCM_OCLK", - "CMT_PHASER_B_TOMMCM_OCLK1X_90", - "CMT_PHASER_B_TOMMCM_OCLKDIV", - "CMT_PHASER_DOWN_DQS_TO_PHASER_A", - "CMT_PHASER_DOWN_DQS_TO_PHASER_B", - "CMT_PHASER_DOWN_PHASERREF0", - "CMT_PHASER_DOWN_PHASERREF1", - "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "CMT_PHASER_IN_A_ICLK", - "CMT_PHASER_IN_A_ICLKDIV", - "CMT_PHASER_IN_A_RCLK0", - "CMT_PHASER_IN_A_WRCLK_TOFIFO", - "CMT_PHASER_IN_A_WREN_TOFIFO", - "CMT_PHASER_IN_B_ICLK", - "CMT_PHASER_IN_B_ICLKDIV", - "CMT_PHASER_IN_B_RCLK1", - "CMT_PHASER_IN_B_WRCLK_TOFIFO", - "CMT_PHASER_IN_B_WREN_TOFIFO", - "CMT_PHASER_IN_CA_BURSTPENDING", - "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "CMT_PHASER_IN_CA_COUNTERLOADEN", - "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "CMT_PHASER_IN_CA_COUNTERREADEN", - "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "CMT_PHASER_IN_CA_DIVIDERST", - "CMT_PHASER_IN_CA_DQSFOUND", - "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "CMT_PHASER_IN_CA_EDGEADV", - "CMT_PHASER_IN_CA_ENCALIB0", - "CMT_PHASER_IN_CA_ENCALIB1", - "CMT_PHASER_IN_CA_ENCALIBPHY0", - "CMT_PHASER_IN_CA_ENCALIBPHY1", - "CMT_PHASER_IN_CA_ENSTG1", - "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "CMT_PHASER_IN_CA_FINEENABLE", - "CMT_PHASER_IN_CA_FINEINC", - "CMT_PHASER_IN_CA_FINEOVERFLOW", - "CMT_PHASER_IN_CA_FREQREFCLK", - "CMT_PHASER_IN_CA_ICLK", - "CMT_PHASER_IN_CA_ICLKDIV", - "CMT_PHASER_IN_CA_ISERDESRST", - "CMT_PHASER_IN_CA_MEMREFCLK", - "CMT_PHASER_IN_CA_PHASELOCKED", - "CMT_PHASER_IN_CA_PHASEREFCLK", - "CMT_PHASER_IN_CA_RANKSEL0", - "CMT_PHASER_IN_CA_RANKSEL1", - "CMT_PHASER_IN_CA_RANKSELPHY0", - "CMT_PHASER_IN_CA_RANKSELPHY1", - "CMT_PHASER_IN_CA_RCLK", - "CMT_PHASER_IN_CA_RST", - "CMT_PHASER_IN_CA_RSTDQSFIND", - "CMT_PHASER_IN_CA_SCANCLK", - "CMT_PHASER_IN_CA_SCANENB", - "CMT_PHASER_IN_CA_SCANIN", - "CMT_PHASER_IN_CA_SCANMODEB", - "CMT_PHASER_IN_CA_SCANOUT", - "CMT_PHASER_IN_CA_SELCALORSTG1", - "CMT_PHASER_IN_CA_STG1INCDEC", - "CMT_PHASER_IN_CA_STG1LOAD", - "CMT_PHASER_IN_CA_STG1OVERFLOW", - "CMT_PHASER_IN_CA_STG1READ", - "CMT_PHASER_IN_CA_STG1REGL0", - "CMT_PHASER_IN_CA_STG1REGL1", - "CMT_PHASER_IN_CA_STG1REGL2", - "CMT_PHASER_IN_CA_STG1REGL3", - "CMT_PHASER_IN_CA_STG1REGL4", - "CMT_PHASER_IN_CA_STG1REGL5", - "CMT_PHASER_IN_CA_STG1REGL6", - "CMT_PHASER_IN_CA_STG1REGL7", - "CMT_PHASER_IN_CA_STG1REGL8", - "CMT_PHASER_IN_CA_STG1REGR0", - "CMT_PHASER_IN_CA_STG1REGR1", - "CMT_PHASER_IN_CA_STG1REGR2", - "CMT_PHASER_IN_CA_STG1REGR3", - "CMT_PHASER_IN_CA_STG1REGR4", - "CMT_PHASER_IN_CA_STG1REGR5", - "CMT_PHASER_IN_CA_STG1REGR6", - "CMT_PHASER_IN_CA_STG1REGR7", - "CMT_PHASER_IN_CA_STG1REGR8", - "CMT_PHASER_IN_CA_SYNCIN", - "CMT_PHASER_IN_CA_SYSCLK", - "CMT_PHASER_IN_CA_TESTIN0", - "CMT_PHASER_IN_CA_TESTIN1", - "CMT_PHASER_IN_CA_TESTIN10", - "CMT_PHASER_IN_CA_TESTIN11", - "CMT_PHASER_IN_CA_TESTIN12", - "CMT_PHASER_IN_CA_TESTIN13", - "CMT_PHASER_IN_CA_TESTIN2", - "CMT_PHASER_IN_CA_TESTIN3", - "CMT_PHASER_IN_CA_TESTIN4", - "CMT_PHASER_IN_CA_TESTIN5", - "CMT_PHASER_IN_CA_TESTIN6", - "CMT_PHASER_IN_CA_TESTIN7", - "CMT_PHASER_IN_CA_TESTIN8", - "CMT_PHASER_IN_CA_TESTIN9", - "CMT_PHASER_IN_CA_TESTOUT0", - "CMT_PHASER_IN_CA_TESTOUT1", - "CMT_PHASER_IN_CA_TESTOUT2", - "CMT_PHASER_IN_CA_TESTOUT3", - "CMT_PHASER_IN_CA_WRENABLE", - "CMT_PHASER_IN_DB_BURSTPENDING", - "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "CMT_PHASER_IN_DB_COUNTERLOADEN", - "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "CMT_PHASER_IN_DB_COUNTERREADEN", - "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "CMT_PHASER_IN_DB_DIVIDERST", - "CMT_PHASER_IN_DB_DQSFOUND", - "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "CMT_PHASER_IN_DB_EDGEADV", - "CMT_PHASER_IN_DB_ENCALIB0", - "CMT_PHASER_IN_DB_ENCALIB1", - "CMT_PHASER_IN_DB_ENCALIBPHY0", - "CMT_PHASER_IN_DB_ENCALIBPHY1", - "CMT_PHASER_IN_DB_ENSTG1", - "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "CMT_PHASER_IN_DB_FINEENABLE", - "CMT_PHASER_IN_DB_FINEINC", - "CMT_PHASER_IN_DB_FINEOVERFLOW", - "CMT_PHASER_IN_DB_FREQREFCLK", - "CMT_PHASER_IN_DB_ICLK", - "CMT_PHASER_IN_DB_ICLKDIV", - "CMT_PHASER_IN_DB_ISERDESRST", - "CMT_PHASER_IN_DB_MEMREFCLK", - "CMT_PHASER_IN_DB_PHASELOCKED", - "CMT_PHASER_IN_DB_PHASEREFCLK", - "CMT_PHASER_IN_DB_RANKSEL0", - "CMT_PHASER_IN_DB_RANKSEL1", - "CMT_PHASER_IN_DB_RANKSELPHY0", - "CMT_PHASER_IN_DB_RANKSELPHY1", - "CMT_PHASER_IN_DB_RCLK", - "CMT_PHASER_IN_DB_RST", - "CMT_PHASER_IN_DB_RSTDQSFIND", - "CMT_PHASER_IN_DB_SCANCLK", - "CMT_PHASER_IN_DB_SCANENB", - "CMT_PHASER_IN_DB_SCANIN", - "CMT_PHASER_IN_DB_SCANMODEB", - "CMT_PHASER_IN_DB_SCANOUT", - "CMT_PHASER_IN_DB_SELCALORSTG1", - "CMT_PHASER_IN_DB_STG1INCDEC", - "CMT_PHASER_IN_DB_STG1LOAD", - "CMT_PHASER_IN_DB_STG1OVERFLOW", - "CMT_PHASER_IN_DB_STG1READ", - "CMT_PHASER_IN_DB_STG1REGL0", - "CMT_PHASER_IN_DB_STG1REGL1", - "CMT_PHASER_IN_DB_STG1REGL2", - "CMT_PHASER_IN_DB_STG1REGL3", - "CMT_PHASER_IN_DB_STG1REGL4", - "CMT_PHASER_IN_DB_STG1REGL5", - "CMT_PHASER_IN_DB_STG1REGL6", - "CMT_PHASER_IN_DB_STG1REGL7", - "CMT_PHASER_IN_DB_STG1REGL8", - "CMT_PHASER_IN_DB_STG1REGR0", - "CMT_PHASER_IN_DB_STG1REGR1", - "CMT_PHASER_IN_DB_STG1REGR2", - "CMT_PHASER_IN_DB_STG1REGR3", - "CMT_PHASER_IN_DB_STG1REGR4", - "CMT_PHASER_IN_DB_STG1REGR5", - "CMT_PHASER_IN_DB_STG1REGR6", - "CMT_PHASER_IN_DB_STG1REGR7", - "CMT_PHASER_IN_DB_STG1REGR8", - "CMT_PHASER_IN_DB_SYNCIN", - "CMT_PHASER_IN_DB_SYSCLK", - "CMT_PHASER_IN_DB_TESTIN0", - "CMT_PHASER_IN_DB_TESTIN1", - "CMT_PHASER_IN_DB_TESTIN10", - "CMT_PHASER_IN_DB_TESTIN11", - "CMT_PHASER_IN_DB_TESTIN12", - "CMT_PHASER_IN_DB_TESTIN13", - "CMT_PHASER_IN_DB_TESTIN2", - "CMT_PHASER_IN_DB_TESTIN3", - "CMT_PHASER_IN_DB_TESTIN4", - "CMT_PHASER_IN_DB_TESTIN5", - "CMT_PHASER_IN_DB_TESTIN6", - "CMT_PHASER_IN_DB_TESTIN7", - "CMT_PHASER_IN_DB_TESTIN8", - "CMT_PHASER_IN_DB_TESTIN9", - "CMT_PHASER_IN_DB_TESTOUT0", - "CMT_PHASER_IN_DB_TESTOUT1", - "CMT_PHASER_IN_DB_TESTOUT2", - "CMT_PHASER_IN_DB_TESTOUT3", - "CMT_PHASER_IN_DB_WRENABLE", - "CMT_PHASER_OUT_A_OCLK", - "CMT_PHASER_OUT_A_OCLK1X_90", - "CMT_PHASER_OUT_A_OCLKDIV", - "CMT_PHASER_OUT_A_RDCLK_TOFIFO", - "CMT_PHASER_OUT_A_RDEN_TOFIFO", - "CMT_PHASER_OUT_B_OCLK", - "CMT_PHASER_OUT_B_OCLK1X_90", - "CMT_PHASER_OUT_B_OCLKDIV", - "CMT_PHASER_OUT_B_RDCLK_TOFIFO", - "CMT_PHASER_OUT_B_RDEN_TOFIFO", - "CMT_PHASER_OUT_CA_BURSTPENDING", - "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "CMT_PHASER_OUT_CA_COARSEENABLE", - "CMT_PHASER_OUT_CA_COARSEINC", - "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "CMT_PHASER_OUT_CA_COUNTERREADEN", - "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CMT_PHASER_OUT_CA_CTSBUS0", - "CMT_PHASER_OUT_CA_CTSBUS1", - "CMT_PHASER_OUT_CA_DIVIDERST", - "CMT_PHASER_OUT_CA_DQSBUS0", - "CMT_PHASER_OUT_CA_DQSBUS1", - "CMT_PHASER_OUT_CA_DTSBUS0", - "CMT_PHASER_OUT_CA_DTSBUS1", - "CMT_PHASER_OUT_CA_EDGEADV", - "CMT_PHASER_OUT_CA_ENCALIB0", - "CMT_PHASER_OUT_CA_ENCALIB1", - "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "CMT_PHASER_OUT_CA_FINEENABLE", - "CMT_PHASER_OUT_CA_FINEINC", - "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "CMT_PHASER_OUT_CA_FREQREFCLK", - "CMT_PHASER_OUT_CA_MEMREFCLK", - "CMT_PHASER_OUT_CA_OCLK", - "CMT_PHASER_OUT_CA_OCLKDELAYED", - "CMT_PHASER_OUT_CA_OCLKDIV", - "CMT_PHASER_OUT_CA_OSERDESRST", - "CMT_PHASER_OUT_CA_PHASEREFCLK", - "CMT_PHASER_OUT_CA_RDENABLE", - "CMT_PHASER_OUT_CA_RST", - "CMT_PHASER_OUT_CA_SCANCLK", - "CMT_PHASER_OUT_CA_SCANENB", - "CMT_PHASER_OUT_CA_SCANIN", - "CMT_PHASER_OUT_CA_SCANMODEB", - "CMT_PHASER_OUT_CA_SCANOUT", - "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "CMT_PHASER_OUT_CA_SYNCIN", - "CMT_PHASER_OUT_CA_SYSCLK", - "CMT_PHASER_OUT_CA_TESTIN0", - "CMT_PHASER_OUT_CA_TESTIN1", - "CMT_PHASER_OUT_CA_TESTIN10", - "CMT_PHASER_OUT_CA_TESTIN11", - "CMT_PHASER_OUT_CA_TESTIN12", - "CMT_PHASER_OUT_CA_TESTIN13", - "CMT_PHASER_OUT_CA_TESTIN14", - "CMT_PHASER_OUT_CA_TESTIN15", - "CMT_PHASER_OUT_CA_TESTIN2", - "CMT_PHASER_OUT_CA_TESTIN3", - "CMT_PHASER_OUT_CA_TESTIN4", - "CMT_PHASER_OUT_CA_TESTIN5", - "CMT_PHASER_OUT_CA_TESTIN6", - "CMT_PHASER_OUT_CA_TESTIN7", - "CMT_PHASER_OUT_CA_TESTIN8", - "CMT_PHASER_OUT_CA_TESTIN9", - "CMT_PHASER_OUT_CA_TESTOUT0", - "CMT_PHASER_OUT_CA_TESTOUT1", - "CMT_PHASER_OUT_CA_TESTOUT2", - "CMT_PHASER_OUT_CA_TESTOUT3", - "CMT_PHASER_OUT_DB_BURSTPENDING", - "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "CMT_PHASER_OUT_DB_COARSEENABLE", - "CMT_PHASER_OUT_DB_COARSEINC", - "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "CMT_PHASER_OUT_DB_COUNTERREADEN", - "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "CMT_PHASER_OUT_DB_CTSBUS0", - "CMT_PHASER_OUT_DB_CTSBUS1", - "CMT_PHASER_OUT_DB_DIVIDERST", - "CMT_PHASER_OUT_DB_DQSBUS0", - "CMT_PHASER_OUT_DB_DQSBUS1", - "CMT_PHASER_OUT_DB_DTSBUS0", - "CMT_PHASER_OUT_DB_DTSBUS1", - "CMT_PHASER_OUT_DB_EDGEADV", - "CMT_PHASER_OUT_DB_ENCALIB0", - "CMT_PHASER_OUT_DB_ENCALIB1", - "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "CMT_PHASER_OUT_DB_FINEENABLE", - "CMT_PHASER_OUT_DB_FINEINC", - "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "CMT_PHASER_OUT_DB_FREQREFCLK", - "CMT_PHASER_OUT_DB_MEMREFCLK", - "CMT_PHASER_OUT_DB_OCLK", - "CMT_PHASER_OUT_DB_OCLKDELAYED", - "CMT_PHASER_OUT_DB_OCLKDIV", - "CMT_PHASER_OUT_DB_OSERDESRST", - "CMT_PHASER_OUT_DB_PHASEREFCLK", - "CMT_PHASER_OUT_DB_RDENABLE", - "CMT_PHASER_OUT_DB_RST", - "CMT_PHASER_OUT_DB_SCANCLK", - "CMT_PHASER_OUT_DB_SCANENB", - "CMT_PHASER_OUT_DB_SCANIN", - "CMT_PHASER_OUT_DB_SCANMODEB", - "CMT_PHASER_OUT_DB_SCANOUT", - "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "CMT_PHASER_OUT_DB_SYNCIN", - "CMT_PHASER_OUT_DB_SYSCLK", - "CMT_PHASER_OUT_DB_TESTIN0", - "CMT_PHASER_OUT_DB_TESTIN1", - "CMT_PHASER_OUT_DB_TESTIN10", - "CMT_PHASER_OUT_DB_TESTIN11", - "CMT_PHASER_OUT_DB_TESTIN12", - "CMT_PHASER_OUT_DB_TESTIN13", - "CMT_PHASER_OUT_DB_TESTIN14", - "CMT_PHASER_OUT_DB_TESTIN15", - "CMT_PHASER_OUT_DB_TESTIN2", - "CMT_PHASER_OUT_DB_TESTIN3", - "CMT_PHASER_OUT_DB_TESTIN4", - "CMT_PHASER_OUT_DB_TESTIN5", - "CMT_PHASER_OUT_DB_TESTIN6", - "CMT_PHASER_OUT_DB_TESTIN7", - "CMT_PHASER_OUT_DB_TESTIN8", - "CMT_PHASER_OUT_DB_TESTIN9", - "CMT_PHASER_OUT_DB_TESTOUT0", - "CMT_PHASER_OUT_DB_TESTOUT1", - "CMT_PHASER_OUT_DB_TESTOUT2", - "CMT_PHASER_OUT_DB_TESTOUT3", - "CMT_R_TOP_LOWER_B_CLKINT_0", - "CMT_R_TOP_LOWER_B_CLKINT_1", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_BYP0_0", - "CMT_TOP_BYP0_1", - "CMT_TOP_BYP0_2", - "CMT_TOP_BYP0_3", - "CMT_TOP_BYP0_4", - "CMT_TOP_BYP0_5", - "CMT_TOP_BYP0_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_BYP0_8", - "CMT_TOP_BYP1_0", - "CMT_TOP_BYP1_1", - "CMT_TOP_BYP1_2", - "CMT_TOP_BYP1_3", - "CMT_TOP_BYP1_4", - "CMT_TOP_BYP1_5", - "CMT_TOP_BYP1_6", - "CMT_TOP_BYP1_7", - "CMT_TOP_BYP1_8", - "CMT_TOP_BYP2_0", - "CMT_TOP_BYP2_1", - "CMT_TOP_BYP2_2", - "CMT_TOP_BYP2_3", - "CMT_TOP_BYP2_4", - "CMT_TOP_BYP2_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_8", - "CMT_TOP_BYP3_0", - "CMT_TOP_BYP3_1", - "CMT_TOP_BYP3_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_BYP3_4", - "CMT_TOP_BYP3_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_BYP3_8", - "CMT_TOP_BYP4_0", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP4_2", - "CMT_TOP_BYP4_3", - "CMT_TOP_BYP4_4", - "CMT_TOP_BYP4_5", - "CMT_TOP_BYP4_6", - "CMT_TOP_BYP4_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_BYP5_0", - "CMT_TOP_BYP5_1", - "CMT_TOP_BYP5_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_BYP5_4", - "CMT_TOP_BYP5_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_BYP5_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_BYP6_0", - "CMT_TOP_BYP6_1", - "CMT_TOP_BYP6_2", - "CMT_TOP_BYP6_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_BYP6_5", - "CMT_TOP_BYP6_6", - "CMT_TOP_BYP6_7", - "CMT_TOP_BYP6_8", - "CMT_TOP_BYP7_0", - "CMT_TOP_BYP7_1", - "CMT_TOP_BYP7_2", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP7_4", - "CMT_TOP_BYP7_5", - "CMT_TOP_BYP7_6", - "CMT_TOP_BYP7_7", - "CMT_TOP_BYP7_8", - "CMT_TOP_CLK0_0", - "CMT_TOP_CLK0_1", - "CMT_TOP_CLK0_2", - "CMT_TOP_CLK0_3", - "CMT_TOP_CLK0_4", - "CMT_TOP_CLK0_5", - "CMT_TOP_CLK0_6", - "CMT_TOP_CLK0_7", - "CMT_TOP_CLK0_8", - "CMT_TOP_CLK1_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_CLK1_2", - "CMT_TOP_CLK1_3", - "CMT_TOP_CLK1_4", - "CMT_TOP_CLK1_5", - "CMT_TOP_CLK1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_CLK1_8", - "CMT_TOP_CTRL0_0", - "CMT_TOP_CTRL0_1", - "CMT_TOP_CTRL0_2", - "CMT_TOP_CTRL0_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_CTRL0_5", - "CMT_TOP_CTRL0_6", - "CMT_TOP_CTRL0_7", - "CMT_TOP_CTRL0_8", - "CMT_TOP_CTRL1_0", - "CMT_TOP_CTRL1_1", - "CMT_TOP_CTRL1_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_CTRL1_4", - "CMT_TOP_CTRL1_5", - "CMT_TOP_CTRL1_6", - "CMT_TOP_CTRL1_7", - "CMT_TOP_CTRL1_8", - "CMT_TOP_EE2A0_0", - "CMT_TOP_EE2A0_1", - "CMT_TOP_EE2A0_2", - "CMT_TOP_EE2A0_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_EE2A0_6", - "CMT_TOP_EE2A0_7", - "CMT_TOP_EE2A0_8", - "CMT_TOP_EE2A1_0", - "CMT_TOP_EE2A1_1", - "CMT_TOP_EE2A1_2", - "CMT_TOP_EE2A1_3", - "CMT_TOP_EE2A1_4", - "CMT_TOP_EE2A1_5", - "CMT_TOP_EE2A1_6", - "CMT_TOP_EE2A1_7", - "CMT_TOP_EE2A1_8", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_1", - "CMT_TOP_EE2A2_2", - "CMT_TOP_EE2A2_3", - "CMT_TOP_EE2A2_4", - "CMT_TOP_EE2A2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_EE2A2_7", - "CMT_TOP_EE2A2_8", - "CMT_TOP_EE2A3_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_EE2A3_2", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2A3_4", - "CMT_TOP_EE2A3_5", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE2A3_8", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_EE4A0_2", - "CMT_TOP_EE4A0_3", - "CMT_TOP_EE4A0_4", - "CMT_TOP_EE4A0_5", - "CMT_TOP_EE4A0_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4A1_0", - "CMT_TOP_EE4A1_1", - "CMT_TOP_EE4A1_2", - "CMT_TOP_EE4A1_3", - "CMT_TOP_EE4A1_4", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4A1_8", - "CMT_TOP_EE4A2_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_EE4A2_2", - "CMT_TOP_EE4A2_3", - "CMT_TOP_EE4A2_4", - "CMT_TOP_EE4A2_5", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE4A2_7", - "CMT_TOP_EE4A2_8", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4A3_1", - "CMT_TOP_EE4A3_2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_EE4A3_5", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE4A3_7", - "CMT_TOP_EE4A3_8", - "CMT_TOP_EE4B0_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_EE4B0_2", - "CMT_TOP_EE4B0_3", - "CMT_TOP_EE4B0_4", - "CMT_TOP_EE4B0_5", - "CMT_TOP_EE4B0_6", - "CMT_TOP_EE4B0_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_EE4B1_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_EE4B1_2", - "CMT_TOP_EE4B1_3", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4B1_8", - "CMT_TOP_EE4B2_0", - "CMT_TOP_EE4B2_1", - "CMT_TOP_EE4B2_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4B2_5", - "CMT_TOP_EE4B2_6", - "CMT_TOP_EE4B2_7", - "CMT_TOP_EE4B2_8", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE4B3_2", - "CMT_TOP_EE4B3_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_EE4B3_5", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EE4B3_7", - "CMT_TOP_EE4B3_8", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_EE4C0_0", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4C0_2", - "CMT_TOP_EE4C0_3", - "CMT_TOP_EE4C0_4", - "CMT_TOP_EE4C0_5", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4C0_7", - "CMT_TOP_EE4C0_8", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4C1_1", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE4C1_3", - "CMT_TOP_EE4C1_4", - "CMT_TOP_EE4C1_5", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_7", - "CMT_TOP_EE4C1_8", - "CMT_TOP_EE4C2_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_EE4C2_2", - "CMT_TOP_EE4C2_3", - "CMT_TOP_EE4C2_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EE4C2_7", - "CMT_TOP_EE4C2_8", - "CMT_TOP_EE4C3_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_EE4C3_2", - "CMT_TOP_EE4C3_3", - "CMT_TOP_EE4C3_4", - "CMT_TOP_EE4C3_5", - "CMT_TOP_EE4C3_6", - "CMT_TOP_EE4C3_7", - "CMT_TOP_EE4C3_8", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_FAN0_0", - "CMT_TOP_FAN0_1", - "CMT_TOP_FAN0_2", - "CMT_TOP_FAN0_3", - "CMT_TOP_FAN0_4", - "CMT_TOP_FAN0_5", - "CMT_TOP_FAN0_6", - "CMT_TOP_FAN0_7", - "CMT_TOP_FAN0_8", - "CMT_TOP_FAN1_0", - "CMT_TOP_FAN1_1", - "CMT_TOP_FAN1_2", - "CMT_TOP_FAN1_3", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_5", - "CMT_TOP_FAN1_6", - "CMT_TOP_FAN1_7", - "CMT_TOP_FAN1_8", - "CMT_TOP_FAN2_0", - "CMT_TOP_FAN2_1", - "CMT_TOP_FAN2_2", - "CMT_TOP_FAN2_3", - "CMT_TOP_FAN2_4", - "CMT_TOP_FAN2_5", - "CMT_TOP_FAN2_6", - "CMT_TOP_FAN2_7", - "CMT_TOP_FAN2_8", - "CMT_TOP_FAN3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_FAN3_2", - "CMT_TOP_FAN3_3", - "CMT_TOP_FAN3_4", - "CMT_TOP_FAN3_5", - "CMT_TOP_FAN3_6", - "CMT_TOP_FAN3_7", - "CMT_TOP_FAN3_8", - "CMT_TOP_FAN4_0", - "CMT_TOP_FAN4_1", - "CMT_TOP_FAN4_2", - "CMT_TOP_FAN4_3", - "CMT_TOP_FAN4_4", - "CMT_TOP_FAN4_5", - "CMT_TOP_FAN4_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_FAN4_8", - "CMT_TOP_FAN5_0", - "CMT_TOP_FAN5_1", - "CMT_TOP_FAN5_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_FAN5_5", - "CMT_TOP_FAN5_6", - "CMT_TOP_FAN5_7", - "CMT_TOP_FAN5_8", - "CMT_TOP_FAN6_0", - "CMT_TOP_FAN6_1", - "CMT_TOP_FAN6_2", - "CMT_TOP_FAN6_3", - "CMT_TOP_FAN6_4", - "CMT_TOP_FAN6_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_FAN6_7", - "CMT_TOP_FAN6_8", - "CMT_TOP_FAN7_0", - "CMT_TOP_FAN7_1", - "CMT_TOP_FAN7_2", - "CMT_TOP_FAN7_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_FAN7_5", - "CMT_TOP_FAN7_6", - "CMT_TOP_FAN7_7", - "CMT_TOP_FAN7_8", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ICLK_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_ICLK_2", - "CMT_TOP_ICLK_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_ICLK_5", - "CMT_TOP_ICLK_6", - "CMT_TOP_ICLK_7", - "CMT_TOP_ICLK_8", - "CMT_TOP_IMUX0_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_IMUX0_2", - "CMT_TOP_IMUX0_3", - "CMT_TOP_IMUX0_4", - "CMT_TOP_IMUX0_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX0_8", - "CMT_TOP_IMUX10_0", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX10_2", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX10_4", - "CMT_TOP_IMUX10_5", - "CMT_TOP_IMUX10_6", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_IMUX11_0", - "CMT_TOP_IMUX11_1", - "CMT_TOP_IMUX11_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_IMUX11_4", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX11_7", - "CMT_TOP_IMUX11_8", - "CMT_TOP_IMUX12_0", - "CMT_TOP_IMUX12_1", - "CMT_TOP_IMUX12_2", - "CMT_TOP_IMUX12_3", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX12_5", - "CMT_TOP_IMUX12_6", - "CMT_TOP_IMUX12_7", - "CMT_TOP_IMUX12_8", - "CMT_TOP_IMUX13_0", - "CMT_TOP_IMUX13_1", - "CMT_TOP_IMUX13_2", - "CMT_TOP_IMUX13_3", - "CMT_TOP_IMUX13_4", - "CMT_TOP_IMUX13_5", - "CMT_TOP_IMUX13_6", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX13_8", - "CMT_TOP_IMUX14_0", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX14_2", - "CMT_TOP_IMUX14_3", - "CMT_TOP_IMUX14_4", - "CMT_TOP_IMUX14_5", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_IMUX15_0", - "CMT_TOP_IMUX15_1", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX15_4", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_IMUX16_0", - "CMT_TOP_IMUX16_1", - "CMT_TOP_IMUX16_2", - "CMT_TOP_IMUX16_3", - "CMT_TOP_IMUX16_4", - "CMT_TOP_IMUX16_5", - "CMT_TOP_IMUX16_6", - "CMT_TOP_IMUX16_7", - "CMT_TOP_IMUX16_8", - "CMT_TOP_IMUX17_0", - "CMT_TOP_IMUX17_1", - "CMT_TOP_IMUX17_2", - "CMT_TOP_IMUX17_3", - "CMT_TOP_IMUX17_4", - "CMT_TOP_IMUX17_5", - "CMT_TOP_IMUX17_6", - "CMT_TOP_IMUX17_7", - "CMT_TOP_IMUX17_8", - "CMT_TOP_IMUX18_0", - "CMT_TOP_IMUX18_1", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX18_3", - "CMT_TOP_IMUX18_4", - "CMT_TOP_IMUX18_5", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX18_7", - "CMT_TOP_IMUX18_8", - "CMT_TOP_IMUX19_0", - "CMT_TOP_IMUX19_1", - "CMT_TOP_IMUX19_2", - "CMT_TOP_IMUX19_3", - "CMT_TOP_IMUX19_4", - "CMT_TOP_IMUX19_5", - "CMT_TOP_IMUX19_6", - "CMT_TOP_IMUX19_7", - "CMT_TOP_IMUX19_8", - "CMT_TOP_IMUX1_0", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX1_2", - "CMT_TOP_IMUX1_3", - "CMT_TOP_IMUX1_4", - "CMT_TOP_IMUX1_5", - "CMT_TOP_IMUX1_6", - "CMT_TOP_IMUX1_7", - "CMT_TOP_IMUX1_8", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX20_1", - "CMT_TOP_IMUX20_2", - "CMT_TOP_IMUX20_3", - "CMT_TOP_IMUX20_4", - "CMT_TOP_IMUX20_5", - "CMT_TOP_IMUX20_6", - "CMT_TOP_IMUX20_7", - "CMT_TOP_IMUX20_8", - "CMT_TOP_IMUX21_0", - "CMT_TOP_IMUX21_1", - "CMT_TOP_IMUX21_2", - "CMT_TOP_IMUX21_3", - "CMT_TOP_IMUX21_4", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_IMUX21_7", - "CMT_TOP_IMUX21_8", - "CMT_TOP_IMUX22_0", - "CMT_TOP_IMUX22_1", - "CMT_TOP_IMUX22_2", - "CMT_TOP_IMUX22_3", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX22_5", - "CMT_TOP_IMUX22_6", - "CMT_TOP_IMUX22_7", - "CMT_TOP_IMUX22_8", - "CMT_TOP_IMUX23_0", - "CMT_TOP_IMUX23_1", - "CMT_TOP_IMUX23_2", - "CMT_TOP_IMUX23_3", - "CMT_TOP_IMUX23_4", - "CMT_TOP_IMUX23_5", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX23_7", - "CMT_TOP_IMUX23_8", - "CMT_TOP_IMUX24_0", - "CMT_TOP_IMUX24_1", - "CMT_TOP_IMUX24_2", - "CMT_TOP_IMUX24_3", - "CMT_TOP_IMUX24_4", - "CMT_TOP_IMUX24_5", - "CMT_TOP_IMUX24_6", - "CMT_TOP_IMUX24_7", - "CMT_TOP_IMUX24_8", - "CMT_TOP_IMUX25_0", - "CMT_TOP_IMUX25_1", - "CMT_TOP_IMUX25_2", - "CMT_TOP_IMUX25_3", - "CMT_TOP_IMUX25_4", - "CMT_TOP_IMUX25_5", - "CMT_TOP_IMUX25_6", - "CMT_TOP_IMUX25_7", - "CMT_TOP_IMUX25_8", - "CMT_TOP_IMUX26_0", - "CMT_TOP_IMUX26_1", - "CMT_TOP_IMUX26_2", - "CMT_TOP_IMUX26_3", - "CMT_TOP_IMUX26_4", - "CMT_TOP_IMUX26_5", - "CMT_TOP_IMUX26_6", - "CMT_TOP_IMUX26_7", - "CMT_TOP_IMUX26_8", - "CMT_TOP_IMUX27_0", - "CMT_TOP_IMUX27_1", - "CMT_TOP_IMUX27_2", - "CMT_TOP_IMUX27_3", - "CMT_TOP_IMUX27_4", - "CMT_TOP_IMUX27_5", - "CMT_TOP_IMUX27_6", - "CMT_TOP_IMUX27_7", - "CMT_TOP_IMUX27_8", - "CMT_TOP_IMUX28_0", - "CMT_TOP_IMUX28_1", - "CMT_TOP_IMUX28_2", - "CMT_TOP_IMUX28_3", - "CMT_TOP_IMUX28_4", - "CMT_TOP_IMUX28_5", - "CMT_TOP_IMUX28_6", - "CMT_TOP_IMUX28_7", - "CMT_TOP_IMUX28_8", - "CMT_TOP_IMUX29_0", - "CMT_TOP_IMUX29_1", - "CMT_TOP_IMUX29_2", - "CMT_TOP_IMUX29_3", - "CMT_TOP_IMUX29_4", - "CMT_TOP_IMUX29_5", - "CMT_TOP_IMUX29_6", - "CMT_TOP_IMUX29_7", - "CMT_TOP_IMUX29_8", - "CMT_TOP_IMUX2_0", - "CMT_TOP_IMUX2_1", - "CMT_TOP_IMUX2_2", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX2_4", - "CMT_TOP_IMUX2_5", - "CMT_TOP_IMUX2_6", - "CMT_TOP_IMUX2_7", - "CMT_TOP_IMUX2_8", - "CMT_TOP_IMUX30_0", - "CMT_TOP_IMUX30_1", - "CMT_TOP_IMUX30_2", - "CMT_TOP_IMUX30_3", - "CMT_TOP_IMUX30_4", - "CMT_TOP_IMUX30_5", - "CMT_TOP_IMUX30_6", - "CMT_TOP_IMUX30_7", - "CMT_TOP_IMUX30_8", - "CMT_TOP_IMUX31_0", - "CMT_TOP_IMUX31_1", - "CMT_TOP_IMUX31_2", - "CMT_TOP_IMUX31_3", - "CMT_TOP_IMUX31_4", - "CMT_TOP_IMUX31_5", - "CMT_TOP_IMUX31_6", - "CMT_TOP_IMUX31_7", - "CMT_TOP_IMUX31_8", - "CMT_TOP_IMUX32_0", - "CMT_TOP_IMUX32_1", - "CMT_TOP_IMUX32_2", - "CMT_TOP_IMUX32_3", - "CMT_TOP_IMUX32_4", - "CMT_TOP_IMUX32_5", - "CMT_TOP_IMUX32_6", - "CMT_TOP_IMUX32_7", - "CMT_TOP_IMUX32_8", - "CMT_TOP_IMUX33_0", - "CMT_TOP_IMUX33_1", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX33_3", - "CMT_TOP_IMUX33_4", - "CMT_TOP_IMUX33_5", - "CMT_TOP_IMUX33_6", - "CMT_TOP_IMUX33_7", - "CMT_TOP_IMUX33_8", - "CMT_TOP_IMUX34_0", - "CMT_TOP_IMUX34_1", - "CMT_TOP_IMUX34_2", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX34_4", - "CMT_TOP_IMUX34_5", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX34_7", - "CMT_TOP_IMUX34_8", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX35_1", - "CMT_TOP_IMUX35_2", - "CMT_TOP_IMUX35_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_IMUX35_5", - "CMT_TOP_IMUX35_6", - "CMT_TOP_IMUX35_7", - "CMT_TOP_IMUX35_8", - "CMT_TOP_IMUX36_0", - "CMT_TOP_IMUX36_1", - "CMT_TOP_IMUX36_2", - "CMT_TOP_IMUX36_3", - "CMT_TOP_IMUX36_4", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX36_6", - "CMT_TOP_IMUX36_7", - "CMT_TOP_IMUX36_8", - "CMT_TOP_IMUX37_0", - "CMT_TOP_IMUX37_1", - "CMT_TOP_IMUX37_2", - "CMT_TOP_IMUX37_3", - "CMT_TOP_IMUX37_4", - "CMT_TOP_IMUX37_5", - "CMT_TOP_IMUX37_6", - "CMT_TOP_IMUX37_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_IMUX38_0", - "CMT_TOP_IMUX38_1", - "CMT_TOP_IMUX38_2", - "CMT_TOP_IMUX38_3", - "CMT_TOP_IMUX38_4", - "CMT_TOP_IMUX38_5", - "CMT_TOP_IMUX38_6", - "CMT_TOP_IMUX38_7", - "CMT_TOP_IMUX38_8", - "CMT_TOP_IMUX39_0", - "CMT_TOP_IMUX39_1", - "CMT_TOP_IMUX39_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX39_4", - "CMT_TOP_IMUX39_5", - "CMT_TOP_IMUX39_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_IMUX39_8", - "CMT_TOP_IMUX3_0", - "CMT_TOP_IMUX3_1", - "CMT_TOP_IMUX3_2", - "CMT_TOP_IMUX3_3", - "CMT_TOP_IMUX3_4", - "CMT_TOP_IMUX3_5", - "CMT_TOP_IMUX3_6", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX3_8", - "CMT_TOP_IMUX40_0", - "CMT_TOP_IMUX40_1", - "CMT_TOP_IMUX40_2", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX40_4", - "CMT_TOP_IMUX40_5", - "CMT_TOP_IMUX40_6", - "CMT_TOP_IMUX40_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_IMUX41_0", - "CMT_TOP_IMUX41_1", - "CMT_TOP_IMUX41_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX41_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_IMUX42_0", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX42_2", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX42_5", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX42_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_IMUX43_0", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX43_2", - "CMT_TOP_IMUX43_3", - "CMT_TOP_IMUX43_4", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX43_6", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX43_8", - "CMT_TOP_IMUX44_0", - "CMT_TOP_IMUX44_1", - "CMT_TOP_IMUX44_2", - "CMT_TOP_IMUX44_3", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX44_5", - "CMT_TOP_IMUX44_6", - "CMT_TOP_IMUX44_7", - "CMT_TOP_IMUX44_8", - "CMT_TOP_IMUX45_0", - "CMT_TOP_IMUX45_1", - "CMT_TOP_IMUX45_2", - "CMT_TOP_IMUX45_3", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX45_5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX45_8", - "CMT_TOP_IMUX46_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX46_2", - "CMT_TOP_IMUX46_3", - "CMT_TOP_IMUX46_4", - "CMT_TOP_IMUX46_5", - "CMT_TOP_IMUX46_6", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX46_8", - "CMT_TOP_IMUX47_0", - "CMT_TOP_IMUX47_1", - "CMT_TOP_IMUX47_2", - "CMT_TOP_IMUX47_3", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX47_5", - "CMT_TOP_IMUX47_6", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX4_0", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX4_3", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX4_5", - "CMT_TOP_IMUX4_6", - "CMT_TOP_IMUX4_7", - "CMT_TOP_IMUX4_8", - "CMT_TOP_IMUX5_0", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX5_2", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX5_6", - "CMT_TOP_IMUX5_7", - "CMT_TOP_IMUX5_8", - "CMT_TOP_IMUX6_0", - "CMT_TOP_IMUX6_1", - "CMT_TOP_IMUX6_2", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX6_4", - "CMT_TOP_IMUX6_5", - "CMT_TOP_IMUX6_6", - "CMT_TOP_IMUX6_7", - "CMT_TOP_IMUX6_8", - "CMT_TOP_IMUX7_0", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX7_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX7_8", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX8_3", - "CMT_TOP_IMUX8_4", - "CMT_TOP_IMUX8_5", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX8_7", - "CMT_TOP_IMUX8_8", - "CMT_TOP_IMUX9_0", - "CMT_TOP_IMUX9_1", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_IMUX9_4", - "CMT_TOP_IMUX9_5", - "CMT_TOP_IMUX9_6", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX9_8", - "CMT_TOP_LH10_0", - "CMT_TOP_LH10_1", - "CMT_TOP_LH10_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_4", - "CMT_TOP_LH10_5", - "CMT_TOP_LH10_6", - "CMT_TOP_LH10_7", - "CMT_TOP_LH10_8", - "CMT_TOP_LH11_0", - "CMT_TOP_LH11_1", - "CMT_TOP_LH11_2", - "CMT_TOP_LH11_3", - "CMT_TOP_LH11_4", - "CMT_TOP_LH11_5", - "CMT_TOP_LH11_6", - "CMT_TOP_LH11_7", - "CMT_TOP_LH11_8", - "CMT_TOP_LH12_0", - "CMT_TOP_LH12_1", - "CMT_TOP_LH12_2", - "CMT_TOP_LH12_3", - "CMT_TOP_LH12_4", - "CMT_TOP_LH12_5", - "CMT_TOP_LH12_6", - "CMT_TOP_LH12_7", - "CMT_TOP_LH12_8", - "CMT_TOP_LH1_0", - "CMT_TOP_LH1_1", - "CMT_TOP_LH1_2", - "CMT_TOP_LH1_3", - "CMT_TOP_LH1_4", - "CMT_TOP_LH1_5", - "CMT_TOP_LH1_6", - "CMT_TOP_LH1_7", - "CMT_TOP_LH1_8", - "CMT_TOP_LH2_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH2_2", - "CMT_TOP_LH2_3", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_5", - "CMT_TOP_LH2_6", - "CMT_TOP_LH2_7", - "CMT_TOP_LH2_8", - "CMT_TOP_LH3_0", - "CMT_TOP_LH3_1", - "CMT_TOP_LH3_2", - "CMT_TOP_LH3_3", - "CMT_TOP_LH3_4", - "CMT_TOP_LH3_5", - "CMT_TOP_LH3_6", - "CMT_TOP_LH3_7", - "CMT_TOP_LH3_8", - "CMT_TOP_LH4_0", - "CMT_TOP_LH4_1", - "CMT_TOP_LH4_2", - "CMT_TOP_LH4_3", - "CMT_TOP_LH4_4", - "CMT_TOP_LH4_5", - "CMT_TOP_LH4_6", - "CMT_TOP_LH4_7", - "CMT_TOP_LH4_8", - "CMT_TOP_LH5_0", - "CMT_TOP_LH5_1", - "CMT_TOP_LH5_2", - "CMT_TOP_LH5_3", - "CMT_TOP_LH5_4", - "CMT_TOP_LH5_5", - "CMT_TOP_LH5_6", - "CMT_TOP_LH5_7", - "CMT_TOP_LH5_8", - "CMT_TOP_LH6_0", - "CMT_TOP_LH6_1", - "CMT_TOP_LH6_2", - "CMT_TOP_LH6_3", - "CMT_TOP_LH6_4", - "CMT_TOP_LH6_5", - "CMT_TOP_LH6_6", - "CMT_TOP_LH6_7", - "CMT_TOP_LH6_8", - "CMT_TOP_LH7_0", - "CMT_TOP_LH7_1", - "CMT_TOP_LH7_2", - "CMT_TOP_LH7_3", - "CMT_TOP_LH7_4", - "CMT_TOP_LH7_5", - "CMT_TOP_LH7_6", - "CMT_TOP_LH7_7", - "CMT_TOP_LH7_8", - "CMT_TOP_LH8_0", - "CMT_TOP_LH8_1", - "CMT_TOP_LH8_2", - "CMT_TOP_LH8_3", - "CMT_TOP_LH8_4", - "CMT_TOP_LH8_5", - "CMT_TOP_LH8_6", - "CMT_TOP_LH8_7", - "CMT_TOP_LH8_8", - "CMT_TOP_LH9_0", - "CMT_TOP_LH9_1", - "CMT_TOP_LH9_2", - "CMT_TOP_LH9_3", - "CMT_TOP_LH9_4", - "CMT_TOP_LH9_5", - "CMT_TOP_LH9_6", - "CMT_TOP_LH9_7", - "CMT_TOP_LH9_8", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_NE2A0_0", - "CMT_TOP_NE2A0_1", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A0_4", - "CMT_TOP_NE2A0_5", - "CMT_TOP_NE2A0_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_NE2A0_8", - "CMT_TOP_NE2A1_0", - "CMT_TOP_NE2A1_1", - "CMT_TOP_NE2A1_2", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_NE2A1_5", - "CMT_TOP_NE2A1_6", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE2A1_8", - "CMT_TOP_NE2A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_NE2A2_2", - "CMT_TOP_NE2A2_3", - "CMT_TOP_NE2A2_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_NE2A2_6", - "CMT_TOP_NE2A2_7", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE2A3_0", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NE2A3_2", - "CMT_TOP_NE2A3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NE2A3_6", - "CMT_TOP_NE2A3_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_NE4C0_0", - "CMT_TOP_NE4C0_1", - "CMT_TOP_NE4C0_2", - "CMT_TOP_NE4C0_3", - "CMT_TOP_NE4C0_4", - "CMT_TOP_NE4C0_5", - "CMT_TOP_NE4C0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NE4C1_3", - "CMT_TOP_NE4C1_4", - "CMT_TOP_NE4C1_5", - "CMT_TOP_NE4C1_6", - "CMT_TOP_NE4C1_7", - "CMT_TOP_NE4C1_8", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NE4C2_1", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE4C2_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NE4C2_6", - "CMT_TOP_NE4C2_7", - "CMT_TOP_NE4C2_8", - "CMT_TOP_NE4C3_0", - "CMT_TOP_NE4C3_1", - "CMT_TOP_NE4C3_2", - "CMT_TOP_NE4C3_3", - "CMT_TOP_NE4C3_4", - "CMT_TOP_NE4C3_5", - "CMT_TOP_NE4C3_6", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW2A0_1", - "CMT_TOP_NW2A0_2", - "CMT_TOP_NW2A0_3", - "CMT_TOP_NW2A0_4", - "CMT_TOP_NW2A0_5", - "CMT_TOP_NW2A0_6", - "CMT_TOP_NW2A0_7", - "CMT_TOP_NW2A0_8", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NW2A1_1", - "CMT_TOP_NW2A1_2", - "CMT_TOP_NW2A1_3", - "CMT_TOP_NW2A1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_NW2A1_6", - "CMT_TOP_NW2A1_7", - "CMT_TOP_NW2A1_8", - "CMT_TOP_NW2A2_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_NW2A2_2", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_4", - "CMT_TOP_NW2A2_5", - "CMT_TOP_NW2A2_6", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NW2A2_8", - "CMT_TOP_NW2A3_0", - "CMT_TOP_NW2A3_1", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NW2A3_3", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW2A3_5", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NW2A3_7", - "CMT_TOP_NW2A3_8", - "CMT_TOP_NW4A0_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_NW4A0_2", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A0_4", - "CMT_TOP_NW4A0_5", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NW4A0_7", - "CMT_TOP_NW4A0_8", - "CMT_TOP_NW4A1_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_NW4A1_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_NW4A1_4", - "CMT_TOP_NW4A1_5", - "CMT_TOP_NW4A1_6", - "CMT_TOP_NW4A1_7", - "CMT_TOP_NW4A1_8", - "CMT_TOP_NW4A2_0", - "CMT_TOP_NW4A2_1", - "CMT_TOP_NW4A2_2", - "CMT_TOP_NW4A2_3", - "CMT_TOP_NW4A2_4", - "CMT_TOP_NW4A2_5", - "CMT_TOP_NW4A2_6", - "CMT_TOP_NW4A2_7", - "CMT_TOP_NW4A2_8", - "CMT_TOP_NW4A3_0", - "CMT_TOP_NW4A3_1", - "CMT_TOP_NW4A3_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NW4A3_6", - "CMT_TOP_NW4A3_7", - "CMT_TOP_NW4A3_8", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NW4END0_1", - "CMT_TOP_NW4END0_2", - "CMT_TOP_NW4END0_3", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END0_5", - "CMT_TOP_NW4END0_6", - "CMT_TOP_NW4END0_7", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NW4END1_0", - "CMT_TOP_NW4END1_1", - "CMT_TOP_NW4END1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_NW4END1_4", - "CMT_TOP_NW4END1_5", - "CMT_TOP_NW4END1_6", - "CMT_TOP_NW4END1_7", - "CMT_TOP_NW4END1_8", - "CMT_TOP_NW4END2_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END2_2", - "CMT_TOP_NW4END2_3", - "CMT_TOP_NW4END2_4", - "CMT_TOP_NW4END2_5", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NW4END2_8", - "CMT_TOP_NW4END3_0", - "CMT_TOP_NW4END3_1", - "CMT_TOP_NW4END3_2", - "CMT_TOP_NW4END3_3", - "CMT_TOP_NW4END3_4", - "CMT_TOP_NW4END3_5", - "CMT_TOP_NW4END3_6", - "CMT_TOP_NW4END3_7", - "CMT_TOP_NW4END3_8", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_OCLK_0", - "CMT_TOP_OCLK_1", - "CMT_TOP_OCLK_2", - "CMT_TOP_OCLK_3", - "CMT_TOP_OCLK_4", - "CMT_TOP_OCLK_5", - "CMT_TOP_OCLK_6", - "CMT_TOP_OCLK_7", - "CMT_TOP_OCLK_8", - "CMT_TOP_SE2A0_0", - "CMT_TOP_SE2A0_1", - "CMT_TOP_SE2A0_2", - "CMT_TOP_SE2A0_3", - "CMT_TOP_SE2A0_4", - "CMT_TOP_SE2A0_5", - "CMT_TOP_SE2A0_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_SE2A1_0", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A1_3", - "CMT_TOP_SE2A1_4", - "CMT_TOP_SE2A1_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SE2A1_8", - "CMT_TOP_SE2A2_0", - "CMT_TOP_SE2A2_1", - "CMT_TOP_SE2A2_2", - "CMT_TOP_SE2A2_3", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SE2A2_5", - "CMT_TOP_SE2A2_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_SE2A2_8", - "CMT_TOP_SE2A3_0", - "CMT_TOP_SE2A3_1", - "CMT_TOP_SE2A3_2", - "CMT_TOP_SE2A3_3", - "CMT_TOP_SE2A3_4", - "CMT_TOP_SE2A3_5", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SE2A3_7", - "CMT_TOP_SE2A3_8", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_SE4C0_0", - "CMT_TOP_SE4C0_1", - "CMT_TOP_SE4C0_2", - "CMT_TOP_SE4C0_3", - "CMT_TOP_SE4C0_4", - "CMT_TOP_SE4C0_5", - "CMT_TOP_SE4C0_6", - "CMT_TOP_SE4C0_7", - "CMT_TOP_SE4C0_8", - "CMT_TOP_SE4C1_0", - "CMT_TOP_SE4C1_1", - "CMT_TOP_SE4C1_2", - "CMT_TOP_SE4C1_3", - "CMT_TOP_SE4C1_4", - "CMT_TOP_SE4C1_5", - "CMT_TOP_SE4C1_6", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE4C1_8", - "CMT_TOP_SE4C2_0", - "CMT_TOP_SE4C2_1", - "CMT_TOP_SE4C2_2", - "CMT_TOP_SE4C2_3", - "CMT_TOP_SE4C2_4", - "CMT_TOP_SE4C2_5", - "CMT_TOP_SE4C2_6", - "CMT_TOP_SE4C2_7", - "CMT_TOP_SE4C2_8", - "CMT_TOP_SE4C3_0", - "CMT_TOP_SE4C3_1", - "CMT_TOP_SE4C3_2", - "CMT_TOP_SE4C3_3", - "CMT_TOP_SE4C3_4", - "CMT_TOP_SE4C3_5", - "CMT_TOP_SE4C3_6", - "CMT_TOP_SE4C3_7", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SW2A0_0", - "CMT_TOP_SW2A0_1", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW2A0_3", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW2A0_5", - "CMT_TOP_SW2A0_6", - "CMT_TOP_SW2A0_7", - "CMT_TOP_SW2A0_8", - "CMT_TOP_SW2A1_0", - "CMT_TOP_SW2A1_1", - "CMT_TOP_SW2A1_2", - "CMT_TOP_SW2A1_3", - "CMT_TOP_SW2A1_4", - "CMT_TOP_SW2A1_5", - "CMT_TOP_SW2A1_6", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW2A1_8", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW2A2_1", - "CMT_TOP_SW2A2_2", - "CMT_TOP_SW2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_SW2A2_5", - "CMT_TOP_SW2A2_6", - "CMT_TOP_SW2A2_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_SW2A3_0", - "CMT_TOP_SW2A3_1", - "CMT_TOP_SW2A3_2", - "CMT_TOP_SW2A3_3", - "CMT_TOP_SW2A3_4", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW2A3_6", - "CMT_TOP_SW2A3_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SW4A0_0", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SW4A0_2", - "CMT_TOP_SW4A0_3", - "CMT_TOP_SW4A0_4", - "CMT_TOP_SW4A0_5", - "CMT_TOP_SW4A0_6", - "CMT_TOP_SW4A0_7", - "CMT_TOP_SW4A0_8", - "CMT_TOP_SW4A1_0", - "CMT_TOP_SW4A1_1", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW4A1_3", - "CMT_TOP_SW4A1_4", - "CMT_TOP_SW4A1_5", - "CMT_TOP_SW4A1_6", - "CMT_TOP_SW4A1_7", - "CMT_TOP_SW4A1_8", - "CMT_TOP_SW4A2_0", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SW4A2_2", - "CMT_TOP_SW4A2_3", - "CMT_TOP_SW4A2_4", - "CMT_TOP_SW4A2_5", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SW4A2_7", - "CMT_TOP_SW4A2_8", - "CMT_TOP_SW4A3_0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_SW4A3_2", - "CMT_TOP_SW4A3_3", - "CMT_TOP_SW4A3_4", - "CMT_TOP_SW4A3_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SW4A3_7", - "CMT_TOP_SW4A3_8", - "CMT_TOP_SW4END0_0", - "CMT_TOP_SW4END0_1", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SW4END0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_SW4END0_5", - "CMT_TOP_SW4END0_6", - "CMT_TOP_SW4END0_7", - "CMT_TOP_SW4END0_8", - "CMT_TOP_SW4END1_0", - "CMT_TOP_SW4END1_1", - "CMT_TOP_SW4END1_2", - "CMT_TOP_SW4END1_3", - "CMT_TOP_SW4END1_4", - "CMT_TOP_SW4END1_5", - "CMT_TOP_SW4END1_6", - "CMT_TOP_SW4END1_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_SW4END2_0", - "CMT_TOP_SW4END2_1", - "CMT_TOP_SW4END2_2", - "CMT_TOP_SW4END2_3", - "CMT_TOP_SW4END2_4", - "CMT_TOP_SW4END2_5", - "CMT_TOP_SW4END2_6", - "CMT_TOP_SW4END2_7", - "CMT_TOP_SW4END2_8", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SW4END3_1", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_3", - "CMT_TOP_SW4END3_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SW4END3_6", - "CMT_TOP_SW4END3_7", - "CMT_TOP_SW4END3_8", - "CMT_TOP_WL1END0_0", - "CMT_TOP_WL1END0_1", - "CMT_TOP_WL1END0_2", - "CMT_TOP_WL1END0_3", - "CMT_TOP_WL1END0_4", - "CMT_TOP_WL1END0_5", - "CMT_TOP_WL1END0_6", - "CMT_TOP_WL1END0_7", - "CMT_TOP_WL1END0_8", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WL1END1_1", - "CMT_TOP_WL1END1_2", - "CMT_TOP_WL1END1_3", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_5", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WL1END1_7", - "CMT_TOP_WL1END1_8", - "CMT_TOP_WL1END2_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WL1END2_3", - "CMT_TOP_WL1END2_4", - "CMT_TOP_WL1END2_5", - "CMT_TOP_WL1END2_6", - "CMT_TOP_WL1END2_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_WL1END3_0", - "CMT_TOP_WL1END3_1", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WL1END3_3", - "CMT_TOP_WL1END3_4", - "CMT_TOP_WL1END3_5", - "CMT_TOP_WL1END3_6", - "CMT_TOP_WL1END3_7", - "CMT_TOP_WL1END3_8", - "CMT_TOP_WR1END0_0", - "CMT_TOP_WR1END0_1", - "CMT_TOP_WR1END0_2", - "CMT_TOP_WR1END0_3", - "CMT_TOP_WR1END0_4", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WR1END0_6", - "CMT_TOP_WR1END0_7", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WR1END1_0", - "CMT_TOP_WR1END1_1", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WR1END1_4", - "CMT_TOP_WR1END1_5", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END1_7", - "CMT_TOP_WR1END1_8", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WR1END2_2", - "CMT_TOP_WR1END2_3", - "CMT_TOP_WR1END2_4", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WR1END2_6", - "CMT_TOP_WR1END2_7", - "CMT_TOP_WR1END2_8", - "CMT_TOP_WR1END3_0", - "CMT_TOP_WR1END3_1", - "CMT_TOP_WR1END3_2", - "CMT_TOP_WR1END3_3", - "CMT_TOP_WR1END3_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_WR1END3_6", - "CMT_TOP_WR1END3_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW2A0_1", - "CMT_TOP_WW2A0_2", - "CMT_TOP_WW2A0_3", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2A0_5", - "CMT_TOP_WW2A0_6", - "CMT_TOP_WW2A0_7", - "CMT_TOP_WW2A0_8", - "CMT_TOP_WW2A1_0", - "CMT_TOP_WW2A1_1", - "CMT_TOP_WW2A1_2", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WW2A1_4", - "CMT_TOP_WW2A1_5", - "CMT_TOP_WW2A1_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_WW2A1_8", - "CMT_TOP_WW2A2_0", - "CMT_TOP_WW2A2_1", - "CMT_TOP_WW2A2_2", - "CMT_TOP_WW2A2_3", - "CMT_TOP_WW2A2_4", - "CMT_TOP_WW2A2_5", - "CMT_TOP_WW2A2_6", - "CMT_TOP_WW2A2_7", - "CMT_TOP_WW2A2_8", - "CMT_TOP_WW2A3_0", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW2A3_2", - "CMT_TOP_WW2A3_3", - "CMT_TOP_WW2A3_4", - "CMT_TOP_WW2A3_5", - "CMT_TOP_WW2A3_6", - "CMT_TOP_WW2A3_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_WW2END0_0", - "CMT_TOP_WW2END0_1", - "CMT_TOP_WW2END0_2", - "CMT_TOP_WW2END0_3", - "CMT_TOP_WW2END0_4", - "CMT_TOP_WW2END0_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_WW2END0_7", - "CMT_TOP_WW2END0_8", - "CMT_TOP_WW2END1_0", - "CMT_TOP_WW2END1_1", - "CMT_TOP_WW2END1_2", - "CMT_TOP_WW2END1_3", - "CMT_TOP_WW2END1_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WW2END1_7", - "CMT_TOP_WW2END1_8", - "CMT_TOP_WW2END2_0", - "CMT_TOP_WW2END2_1", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW2END2_3", - "CMT_TOP_WW2END2_4", - "CMT_TOP_WW2END2_5", - "CMT_TOP_WW2END2_6", - "CMT_TOP_WW2END2_7", - "CMT_TOP_WW2END2_8", - "CMT_TOP_WW2END3_0", - "CMT_TOP_WW2END3_1", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END3_3", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WW2END3_5", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END3_7", - "CMT_TOP_WW2END3_8", - "CMT_TOP_WW4A0_0", - "CMT_TOP_WW4A0_1", - "CMT_TOP_WW4A0_2", - "CMT_TOP_WW4A0_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_WW4A0_5", - "CMT_TOP_WW4A0_6", - "CMT_TOP_WW4A0_7", - "CMT_TOP_WW4A0_8", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4A1_1", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW4A1_3", - "CMT_TOP_WW4A1_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_WW4A1_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4A2_0", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4A2_2", - "CMT_TOP_WW4A2_3", - "CMT_TOP_WW4A2_4", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW4A2_6", - "CMT_TOP_WW4A2_7", - "CMT_TOP_WW4A2_8", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW4A3_2", - "CMT_TOP_WW4A3_3", - "CMT_TOP_WW4A3_4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_WW4A3_6", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WW4A3_8", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4B0_3", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4B0_5", - "CMT_TOP_WW4B0_6", - "CMT_TOP_WW4B0_7", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B1_0", - "CMT_TOP_WW4B1_1", - "CMT_TOP_WW4B1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_5", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4B1_7", - "CMT_TOP_WW4B1_8", - "CMT_TOP_WW4B2_0", - "CMT_TOP_WW4B2_1", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4B2_4", - "CMT_TOP_WW4B2_5", - "CMT_TOP_WW4B2_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_WW4B2_8", - "CMT_TOP_WW4B3_0", - "CMT_TOP_WW4B3_1", - "CMT_TOP_WW4B3_2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_WW4B3_4", - "CMT_TOP_WW4B3_5", - "CMT_TOP_WW4B3_6", - "CMT_TOP_WW4B3_7", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW4C0_0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_WW4C0_2", - "CMT_TOP_WW4C0_3", - "CMT_TOP_WW4C0_4", - "CMT_TOP_WW4C0_5", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4C0_8", - "CMT_TOP_WW4C1_0", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW4C1_2", - "CMT_TOP_WW4C1_3", - "CMT_TOP_WW4C1_4", - "CMT_TOP_WW4C1_5", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4C1_7", - "CMT_TOP_WW4C1_8", - "CMT_TOP_WW4C2_0", - "CMT_TOP_WW4C2_1", - "CMT_TOP_WW4C2_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_WW4C2_4", - "CMT_TOP_WW4C2_5", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WW4C2_8", - "CMT_TOP_WW4C3_0", - "CMT_TOP_WW4C3_1", - "CMT_TOP_WW4C3_2", - "CMT_TOP_WW4C3_3", - "CMT_TOP_WW4C3_4", - "CMT_TOP_WW4C3_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW4C3_8", - "CMT_TOP_WW4END0_0", - "CMT_TOP_WW4END0_1", - "CMT_TOP_WW4END0_2", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_5", - "CMT_TOP_WW4END0_6", - "CMT_TOP_WW4END0_7", - "CMT_TOP_WW4END0_8", - "CMT_TOP_WW4END1_0", - "CMT_TOP_WW4END1_1", - "CMT_TOP_WW4END1_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END1_6", - "CMT_TOP_WW4END1_7", - "CMT_TOP_WW4END1_8", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW4END2_1", - "CMT_TOP_WW4END2_2", - "CMT_TOP_WW4END2_3", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_WW4END2_7", - "CMT_TOP_WW4END2_8", - "CMT_TOP_WW4END3_0", - "CMT_TOP_WW4END3_1", - "CMT_TOP_WW4END3_2", - "CMT_TOP_WW4END3_3", - "CMT_TOP_WW4END3_4", - "CMT_TOP_WW4END3_5", - "CMT_TOP_WW4END3_6", - "CMT_TOP_WW4END3_7", - "CMT_TOP_WW4END3_8", - "MMCMOUT_CLK_FREQ_BB_REBUFIN0", - "MMCMOUT_CLK_FREQ_BB_REBUFIN1", - "MMCMOUT_CLK_FREQ_BB_REBUFIN2", - "MMCMOUT_CLK_FREQ_BB_REBUFIN3", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "MMCM_CLK_FREQBB_REBUFOUT0", - "MMCM_CLK_FREQBB_REBUFOUT1", - "MMCM_CLK_FREQBB_REBUFOUT2", - "MMCM_CLK_FREQBB_REBUFOUT3" - ] + "wires": { + "CMT_BOT_HCLKMUX_CLKINT_0": null, + "CMT_BOT_HCLKMUX_CLKINT_1": null, + "CMT_LR_LOWER_T_CLK_IN1_HCLK": null, + "CMT_LR_LOWER_T_CLK_IN2_HCLK": null, + "CMT_LR_LOWER_T_CLK_IN3_HCLK": null, + "CMT_LR_LOWER_T_CLK_MMCM0": null, + "CMT_LR_LOWER_T_CLK_MMCM1": null, + "CMT_LR_LOWER_T_CLK_MMCM10": null, + "CMT_LR_LOWER_T_CLK_MMCM11": null, + "CMT_LR_LOWER_T_CLK_MMCM12": null, + "CMT_LR_LOWER_T_CLK_MMCM13": null, + "CMT_LR_LOWER_T_CLK_MMCM2": null, + "CMT_LR_LOWER_T_CLK_MMCM3": null, + "CMT_LR_LOWER_T_CLK_MMCM4": null, + "CMT_LR_LOWER_T_CLK_MMCM5": null, + "CMT_LR_LOWER_T_CLK_MMCM6": null, + "CMT_LR_LOWER_T_CLK_MMCM7": null, + "CMT_LR_LOWER_T_CLK_MMCM8": null, + "CMT_LR_LOWER_T_CLK_MMCM9": null, + "CMT_LR_LOWER_T_CLK_PERF0": null, + "CMT_LR_LOWER_T_CLK_PERF1": null, + "CMT_LR_LOWER_T_CLK_PERF2": null, + "CMT_LR_LOWER_T_CLK_PERF3": null, + "CMT_PHASERA_CTSBUS0": null, + "CMT_PHASERA_CTSBUS1": null, + "CMT_PHASERA_DQSBUS0": null, + "CMT_PHASERA_DQSBUS1": null, + "CMT_PHASERA_DTSBUS0": null, + "CMT_PHASERA_DTSBUS1": null, + "CMT_PHASERREF_DOWN_PHASERIN_A": null, + "CMT_PHASERREF_DOWN_PHASERIN_B": null, + "CMT_PHASERREF_DOWN_PHASEROUT_A": null, + "CMT_PHASERREF_DOWN_PHASEROUT_B": null, + "CMT_PHASER_BOT_ENCALIB0": null, + "CMT_PHASER_BOT_ENCALIB1": null, + "CMT_PHASER_BOT_IBURSTPENDING0": null, + "CMT_PHASER_BOT_IBURSTPENDING1": null, + "CMT_PHASER_BOT_IRANKA0": null, + "CMT_PHASER_BOT_IRANKA1": null, + "CMT_PHASER_BOT_IRANKB0": null, + "CMT_PHASER_BOT_IRANKB1": null, + "CMT_PHASER_BOT_OBURSTPENDING0": null, + "CMT_PHASER_BOT_OBURSTPENDING1": null, + "CMT_PHASER_BOT_REFMUX_0": null, + "CMT_PHASER_BOT_REFMUX_1": null, + "CMT_PHASER_BOT_REFMUX_2": null, + "CMT_PHASER_BOT_SYNC_BB": null, + "CMT_PHASER_B_ICLKDIV_TOIOI": null, + "CMT_PHASER_B_ICLK_TOIOI": null, + "CMT_PHASER_B_OCLK90_TOIOI": null, + "CMT_PHASER_B_OCLKDIV_TOIOI": null, + "CMT_PHASER_B_OCLK_TOIOI": null, + "CMT_PHASER_B_TOMMCM_ICLK": null, + "CMT_PHASER_B_TOMMCM_ICLKDIV": null, + "CMT_PHASER_B_TOMMCM_OCLK": null, + "CMT_PHASER_B_TOMMCM_OCLK1X_90": null, + "CMT_PHASER_B_TOMMCM_OCLKDIV": null, + "CMT_PHASER_DOWN_DQS_TO_PHASER_A": null, + "CMT_PHASER_DOWN_DQS_TO_PHASER_B": null, + "CMT_PHASER_DOWN_PHASERREF0": null, + "CMT_PHASER_DOWN_PHASERREF1": null, + "CMT_PHASER_DOWN_PHASERREF_ABOVE0": null, + "CMT_PHASER_DOWN_PHASERREF_ABOVE1": null, + "CMT_PHASER_DOWN_PHASERREF_BELOW0": null, + "CMT_PHASER_DOWN_PHASERREF_BELOW1": null, + "CMT_PHASER_IN_A_ICLK": null, + "CMT_PHASER_IN_A_ICLKDIV": null, + "CMT_PHASER_IN_A_RCLK0": null, + "CMT_PHASER_IN_A_WRCLK_TOFIFO": null, + "CMT_PHASER_IN_A_WREN_TOFIFO": null, + "CMT_PHASER_IN_B_ICLK": null, + "CMT_PHASER_IN_B_ICLKDIV": null, + "CMT_PHASER_IN_B_RCLK1": null, + "CMT_PHASER_IN_B_WRCLK_TOFIFO": null, + "CMT_PHASER_IN_B_WREN_TOFIFO": null, + "CMT_PHASER_IN_CA_BURSTPENDING": null, + "CMT_PHASER_IN_CA_BURSTPENDINGPHY": null, + "CMT_PHASER_IN_CA_COUNTERLOADEN": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL0": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL1": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL2": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL3": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL4": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL5": null, + "CMT_PHASER_IN_CA_COUNTERREADEN": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL0": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL1": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL2": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL3": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL4": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL5": null, + "CMT_PHASER_IN_CA_DIVIDERST": null, + "CMT_PHASER_IN_CA_DQSFOUND": null, + "CMT_PHASER_IN_CA_DQSOUTOFRANGE": null, + "CMT_PHASER_IN_CA_EDGEADV": null, + "CMT_PHASER_IN_CA_ENCALIB0": null, + "CMT_PHASER_IN_CA_ENCALIB1": null, + "CMT_PHASER_IN_CA_ENCALIBPHY0": null, + "CMT_PHASER_IN_CA_ENCALIBPHY1": null, + "CMT_PHASER_IN_CA_ENSTG1": null, + "CMT_PHASER_IN_CA_ENSTG1ADJUSTB": null, + "CMT_PHASER_IN_CA_FINEENABLE": null, + "CMT_PHASER_IN_CA_FINEINC": null, + "CMT_PHASER_IN_CA_FINEOVERFLOW": null, + "CMT_PHASER_IN_CA_FREQREFCLK": null, + "CMT_PHASER_IN_CA_ICLK": null, + "CMT_PHASER_IN_CA_ICLKDIV": null, + "CMT_PHASER_IN_CA_ISERDESRST": null, + "CMT_PHASER_IN_CA_MEMREFCLK": null, + "CMT_PHASER_IN_CA_PHASELOCKED": null, + "CMT_PHASER_IN_CA_PHASEREFCLK": null, + "CMT_PHASER_IN_CA_RANKSEL0": null, + "CMT_PHASER_IN_CA_RANKSEL1": null, + "CMT_PHASER_IN_CA_RANKSELPHY0": null, + "CMT_PHASER_IN_CA_RANKSELPHY1": null, + "CMT_PHASER_IN_CA_RCLK": null, + "CMT_PHASER_IN_CA_RST": null, + "CMT_PHASER_IN_CA_RSTDQSFIND": null, + "CMT_PHASER_IN_CA_SCANCLK": null, + "CMT_PHASER_IN_CA_SCANENB": null, + "CMT_PHASER_IN_CA_SCANIN": null, + "CMT_PHASER_IN_CA_SCANMODEB": null, + "CMT_PHASER_IN_CA_SCANOUT": null, + "CMT_PHASER_IN_CA_SELCALORSTG1": null, + "CMT_PHASER_IN_CA_STG1INCDEC": null, + "CMT_PHASER_IN_CA_STG1LOAD": null, + "CMT_PHASER_IN_CA_STG1OVERFLOW": null, + "CMT_PHASER_IN_CA_STG1READ": null, + "CMT_PHASER_IN_CA_STG1REGL0": null, + "CMT_PHASER_IN_CA_STG1REGL1": null, + "CMT_PHASER_IN_CA_STG1REGL2": null, + "CMT_PHASER_IN_CA_STG1REGL3": null, + "CMT_PHASER_IN_CA_STG1REGL4": null, + "CMT_PHASER_IN_CA_STG1REGL5": null, + "CMT_PHASER_IN_CA_STG1REGL6": null, + "CMT_PHASER_IN_CA_STG1REGL7": null, + "CMT_PHASER_IN_CA_STG1REGL8": null, + "CMT_PHASER_IN_CA_STG1REGR0": null, + "CMT_PHASER_IN_CA_STG1REGR1": null, + "CMT_PHASER_IN_CA_STG1REGR2": null, + "CMT_PHASER_IN_CA_STG1REGR3": null, + "CMT_PHASER_IN_CA_STG1REGR4": null, + "CMT_PHASER_IN_CA_STG1REGR5": null, + "CMT_PHASER_IN_CA_STG1REGR6": null, + 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"MMCMOUT_CLK_FREQ_BB_REBUFIN0": null, + "MMCMOUT_CLK_FREQ_BB_REBUFIN1": null, + "MMCMOUT_CLK_FREQ_BB_REBUFIN2": null, + "MMCMOUT_CLK_FREQ_BB_REBUFIN3": null, + "MMCMOUT_CLK_FREQ_BB_REBUFOUT0": null, + "MMCMOUT_CLK_FREQ_BB_REBUFOUT1": null, + "MMCMOUT_CLK_FREQ_BB_REBUFOUT2": null, + "MMCMOUT_CLK_FREQ_BB_REBUFOUT3": null, + "MMCM_CLK_FREQBB_REBUFOUT0": null, + "MMCM_CLK_FREQBB_REBUFOUT1": null, + "MMCM_CLK_FREQBB_REBUFOUT2": null, + "MMCM_CLK_FREQBB_REBUFOUT3": null + } } diff --git a/zynq7/tile_type_CMT_TOP_L_UPPER_B.json b/zynq7/tile_type_CMT_TOP_L_UPPER_B.json index 2013056..2fa6fb4 100644 --- a/zynq7/tile_type_CMT_TOP_L_UPPER_B.json +++ b/zynq7/tile_type_CMT_TOP_L_UPPER_B.json @@ -2,2711 +2,8368 @@ "pips": { "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.063", + "0.070", + "0.204", + "0.225" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", "is_directional": "1", + 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"in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_DQSFOUND" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_C_ICLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_C_ICLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_ICLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ICLKDIV->CMT_R_PHASER_IN_C_WRCLK_FIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_R_PHASER_IN_C_WRCLK_FIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_ICLKDIV" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_ISERDESRST" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.114", + "0.228", + "0.276" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_CA_RCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.114", + "0.228", + "0.276" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_C_RCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_C_RCLK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_RCLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_C_WRENABLE_FIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_C_WRENABLE_FIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_WRENABLE" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLK->>CMT_PHASER_C_ICLK_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.096", + "0.105" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_ICLK_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.096", + "0.105" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_C_ICLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLKDIV->>CMT_PHASER_C_ICLKDIV_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.034", + "0.037", + "0.098", + "0.108" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.034", + "0.037", + "0.098", + "0.108" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_C_ICLKDIV" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_DQSFOUND" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_D_ICLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_D_ICLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ICLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ICLKDIV->CMT_R_PHASER_IN_D_WRCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_R_PHASER_IN_D_WRCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ICLKDIV" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ISERDESRST" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.114", + "0.228", + "0.276" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_DB_RCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.114", + "0.228", + "0.276" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_D_RCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_D_RCLK3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_RCLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_D_WRENABLE_FIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_D_WRENABLE_FIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_WRENABLE" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_C_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_C_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_C_OCLK1X_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_C_OCLK1X_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLKDIV->CMT_R_PHASER_OUT_C_RDCLK_FIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_R_PHASER_OUT_C_RDCLK_FIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_RDENABLE->CMT_R_PHASER_OUT_C_RDENABLE_FIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_R_PHASER_OUT_C_RDENABLE_FIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_RDENABLE" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK->>CMT_PHASER_C_OCLK_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.090", + "0.099" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_OCLK_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.090", + "0.099" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_C_OCLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90->>CMT_PHASER_C_OCLK90_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.036", + "0.096", + "0.105" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_OCLK90_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.036", + "0.096", + "0.105" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_C_OCLK1X_90" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV->>CMT_PHASER_C_OCLKDIV_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.034", + "0.038", + "0.102", + "0.112" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.034", + "0.038", + "0.102", + "0.112" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_C_OCLKDIV" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS0->CMT_PHASERD_CTSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_CTSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS1->CMT_PHASERD_CTSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_CTSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS0->CMT_PHASERD_DQSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_DQSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS1->CMT_PHASERD_DQSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_DQSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS0->CMT_PHASERD_DTSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_DTSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS1->CMT_PHASERD_DTSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, 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"res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_RDENABLE->CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_RDENABLE" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKOUT->CMT_PHASER_REF_CLKOUT_TOHCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_REF_CLKOUT_TOHCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": 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+ "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING2" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING3->CMT_PHY_CONTROL_IBURSTPENDING3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING3" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKA0->CMT_PHY_CONTROL_IRANKA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKA0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKA1->CMT_PHY_CONTROL_IRANKA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKA1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKB0->CMT_PHY_CONTROL_IRANKB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKB0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKB1->CMT_PHY_CONTROL_IRANKB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKB1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKC0->CMT_PHY_CONTROL_IRANKC0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKC0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKC0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKC1->CMT_PHY_CONTROL_IRANKC1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKC1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKC1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKD0->CMT_PHY_CONTROL_IRANKD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKD0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKD1->CMT_PHY_CONTROL_IRANKD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKD1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC0->CMT_PHASER_IN_CA_RANKSELPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IRANKC0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC1->CMT_PHASER_IN_CA_RANKSELPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IRANKC1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD0->CMT_PHASER_IN_DB_RANKSELPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IRANKD0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD1->CMT_PHASER_IN_DB_RANKSELPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IRANKD1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING2" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING3" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING0->CMT_PHY_CONTROL_OBURSTPENDING0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING1->CMT_PHY_CONTROL_OBURSTPENDING1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING2->CMT_PHY_CONTROL_OBURSTPENDING2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING2" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING3->CMT_PHY_CONTROL_OBURSTPENDING3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING3" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB0->CMT_PHY_CONTROL_ECALIB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_ECALIB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB1->CMT_PHY_CONTROL_ECALIB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_ECALIB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLALMOSTFULL->CMT_TOP_LOGIC_OUTS_L_B7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLEMPTY->CMT_PHASERTOP_PHYCTLEMPTY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERTOP_PHYCTLEMPTY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PHYCTLEMPTY" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLFULL->CMT_TOP_LOGIC_OUTS_L_B17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PHYCTLFULL" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLREADY->CMT_TOP_LOGIC_OUTS_L_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PHYCTLREADY" }, "CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_C_WRCLK_FIFO->CMT_PHASER_IN_C_ICLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_C_ICLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_R_PHASER_IN_C_WRCLK_FIFO" }, "CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_D_WRCLK_TOFIFO->CMT_PHASER_IN_D_ICLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_D_ICLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_R_PHASER_IN_D_WRCLK_TOFIFO" }, "CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDCLK_FIFO->CMT_PHASER_OUT_C_OCLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_C_OCLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_R_PHASER_OUT_C_RDCLK_FIFO" }, "CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO->CMT_PHASER_OUT_D_OCLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_D_OCLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_0->>CMT_L_TOP_UPPER_B_CLKINT_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_TOP_UPPER_B_CLKINT_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_CLK0_0" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_10->CMT_PHY_CONTROL_PHYCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_2->CMT_PHASER_OUT_CA_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_4->CMT_PHASER_IN_CA_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_8->CMT_PHASER_IN_DB_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_8" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK1_0->>CMT_L_TOP_UPPER_B_CLKINT_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_TOP_UPPER_B_CLKINT_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_CLK1_0" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_0->CMT_PHASER_UP_BUFMRCE_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_0" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_3->CMT_PHASER_IN_CA_RSTDQSFIND": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_11->CMT_PHY_CONTROL_RESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_RESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX11_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_4->CMT_PHASER_IN_CA_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX11_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_5->CMT_PHASER_OUT_DB_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX11_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX12_7->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX12_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_10->CMT_PHY_CONTROL_PHYCTLWD13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_11->CMT_PHY_CONTROL_PHYCTLWD25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_9->CMT_PHY_CONTROL_PHYCTLWD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_10->CMT_PHY_CONTROL_PHYCTLWD15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_11->CMT_PHY_CONTROL_PHYCTLWD27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_9->CMT_PHY_CONTROL_PHYCTLWD5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_0->CMT_PHASER_REF_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_REF_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_0" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_10->CMT_PHY_CONTROL_PHYCTLWD18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_11->CMT_PHY_CONTROL_PHYCTLWD30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_9->CMT_PHY_CONTROL_PHYCTLWD8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX16_0->CMT_PHASER_UP_BUFMRCE_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX16_0" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX16_6->CMT_PHASER_OUT_DB_COARSEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX16_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_2->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX17_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX17_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_6->CMT_PHASER_OUT_DB_ENCALIB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_ENCALIB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX17_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX18_2->CMT_PHASER_OUT_CA_ENCALIB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_ENCALIB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX18_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX18_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX18_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_4->CMT_PHASER_OUT_DB_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_6->CMT_PHASER_IN_DB_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX1_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX1_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX1_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_10->CMT_PHY_CONTROL_PHYCTLWD11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_11->CMT_PHY_CONTROL_PHYCTLWD23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_9->CMT_PHY_CONTROL_PHYCTLWD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX22_10->CMT_PHY_CONTROL_WRITECALIBENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_WRITECALIBENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX22_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX23_3->CMT_PHASER_IN_CA_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX23_7->CMT_PHASER_IN_DB_RANKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_5->CMT_PHASER_OUT_DB_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_7->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX28_7->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX28_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_10->CMT_PHY_CONTROL_READCALIBENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_READCALIBENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX2_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX2_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX2_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_10->CMT_PHY_CONTROL_PHYCTLWD16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_11->CMT_PHY_CONTROL_PHYCTLWD28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_9->CMT_PHY_CONTROL_PHYCTLWD6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_10->CMT_PHY_CONTROL_PHYCTLWD19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_11->CMT_PHY_CONTROL_PHYCTLWD31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_9->CMT_PHY_CONTROL_PHYCTLWD9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX32_4->CMT_PHASER_IN_CA_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX32_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX32_6->CMT_PHASER_OUT_DB_COARSEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX32_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_RANKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX34_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX34_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_6->CMT_PHASER_OUT_DB_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX34_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX37_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX37_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX39_7->CMT_PHASER_IN_DB_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX39_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX3_4->CMT_PHASER_IN_CA_RANKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX3_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX3_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX3_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX41_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_4->CMT_PHASER_IN_CA_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX41_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX41_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_11->CMT_PHY_CONTROL_PHYCTLWD21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_5->CMT_PHASER_OUT_DB_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_7->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_9->CMT_PHY_CONTROL_PLLLOCK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PLLLOCK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_10->CMT_PHY_CONTROL_PHYCTLWD12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_11->CMT_PHY_CONTROL_PHYCTLWD24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_9->CMT_PHY_CONTROL_PHYCTLWD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_0->CMT_PHASER_REF_PWRDWN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_REF_PWRDWN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_0" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_10->CMT_PHY_CONTROL_PHYCTLWD14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_11->CMT_PHY_CONTROL_PHYCTLWD26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_9->CMT_PHY_CONTROL_PHYCTLWD4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_10->CMT_PHY_CONTROL_PHYCTLWD17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_11->CMT_PHY_CONTROL_PHYCTLWD29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_6->CMT_PHASER_IN_DB_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_9->CMT_PHY_CONTROL_PHYCTLWD7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_10->CMT_PHY_CONTROL_PHYCTLWD20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_11->CMT_PHY_CONTROL_PHYCTLWRENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWRENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_3->CMT_PHASER_IN_CA_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_9->CMT_PHY_CONTROL_PHYCTLWD10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_10->CMT_PHY_CONTROL_REFDLLLOCK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_REFDLLLOCK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX4_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_11->CMT_PHY_CONTROL_PHYCTLWD22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX4_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_9->CMT_PHY_CONTROL_PHYCTLWD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX4_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX8_6->CMT_PHASER_OUT_DB_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX8_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX8_7->CMT_PHASER_IN_DB_RSTDQSFIND": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX8_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX9_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX9_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_6->CMT_PHASER_OUT_DB_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX9_6" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>CMT_FREQ_PHASER_REFMUX_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.114", + "0.126", + "0.334", + "0.368" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.114", + "0.126", + "0.334", + "0.368" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": 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+ "res": "0.0" + }, "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.114", + "0.126", + "0.334", + "0.368" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>CMT_FREQ_PHASER_REFMUX_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.114", + "0.126", + "0.334", + "0.368" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.114", + "0.126", + "0.334", + "0.368" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.157", + "0.173", + "0.454", + "0.499" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT0->>PLL_CLK_FREQBB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQBB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT1->>PLL_CLK_FREQBB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQBB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT2->>PLL_CLK_FREQBB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQBB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT3->>PLL_CLK_FREQBB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQBB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3" }, "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT0->>CMT_FREQ_BB_PREF_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_BB_PREF_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQBB_REBUFOUT0" }, "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT1->>CMT_FREQ_BB_PREF_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_BB_PREF_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQBB_REBUFOUT1" }, "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT2->>CMT_FREQ_BB_PREF_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_BB_PREF_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQBB_REBUFOUT2" }, "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT3->>CMT_FREQ_BB_PREF_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_BB_PREF_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQBB_REBUFOUT3" } }, @@ -2715,28 +8372,226 @@ "name": "X0Y0", "prefix": "PHASER_REF", "site_pins": { - "CLKIN": "CMT_PHASER_REF_CLKIN", - "CLKOUT": "CMT_PHASER_REF_CLKOUT", - "LOCKED": "CMT_PHASER_REF_LOCKED", - "PWRDWN": "CMT_PHASER_REF_PWRDWN", - "RST": "CMT_PHASER_REF_RST", - "TESTIN0": "CMT_PHASER_REF_TESTIN0", - "TESTIN1": "CMT_PHASER_REF_TESTIN1", - "TESTIN2": "CMT_PHASER_REF_TESTIN2", - "TESTIN3": "CMT_PHASER_REF_TESTIN3", - "TESTIN4": "CMT_PHASER_REF_TESTIN4", - "TESTIN5": "CMT_PHASER_REF_TESTIN5", - "TESTIN6": "CMT_PHASER_REF_TESTIN6", - "TESTIN7": "CMT_PHASER_REF_TESTIN7", - "TESTOUT0": "CMT_PHASER_REF_TESTOUT0", - "TESTOUT1": "CMT_PHASER_REF_TESTOUT1", - "TESTOUT2": "CMT_PHASER_REF_TESTOUT2", - "TESTOUT3": "CMT_PHASER_REF_TESTOUT3", - "TESTOUT4": "CMT_PHASER_REF_TESTOUT4", - "TESTOUT5": "CMT_PHASER_REF_TESTOUT5", - "TESTOUT6": "CMT_PHASER_REF_TESTOUT6", - "TESTOUT7": "CMT_PHASER_REF_TESTOUT7", - "TMUXOUT": "CMT_PHASER_REF_TMUXOUT" + "CLKIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_CLKIN" + }, + "CLKOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_CLKOUT" + }, + "LOCKED": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_LOCKED" + }, + "PWRDWN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_PWRDWN" + }, + "RST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_RST" + }, + "TESTIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN0" + }, + "TESTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN1" + }, + "TESTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN2" + }, + "TESTIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN3" + }, + "TESTIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN4" + }, + "TESTIN5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN5" + }, + "TESTIN6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN6" + }, + "TESTIN7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN7" + }, + "TESTOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT0" + }, + "TESTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT1" + }, + "TESTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT3" + }, + "TESTOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT4" + }, + "TESTOUT5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT5" + }, + "TESTOUT6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT6" + }, + "TESTOUT7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT7" + }, + "TMUXOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TMUXOUT" + } }, "type": "PHASER_REF", "x_coord": 0, @@ -2746,110 +8601,1046 @@ "name": "X0Y0", "prefix": "PHY_CONTROL", "site_pins": { - "AUXOUTPUT0": "CMT_PHY_CONTROL_AUXOUTPUT0", - "AUXOUTPUT1": "CMT_PHY_CONTROL_AUXOUTPUT1", - "AUXOUTPUT2": "CMT_PHY_CONTROL_AUXOUTPUT2", - "AUXOUTPUT3": "CMT_PHY_CONTROL_AUXOUTPUT3", - "INBURSTPENDING0": "CMT_PHY_CONTROL_INBURSTPENDING0", - "INBURSTPENDING1": "CMT_PHY_CONTROL_INBURSTPENDING1", - "INBURSTPENDING2": "CMT_PHY_CONTROL_INBURSTPENDING2", - "INBURSTPENDING3": "CMT_PHY_CONTROL_INBURSTPENDING3", - "INRANKA0": "CMT_PHY_CONTROL_INRANKA0", - "INRANKA1": "CMT_PHY_CONTROL_INRANKA1", - "INRANKB0": "CMT_PHY_CONTROL_INRANKB0", - "INRANKB1": "CMT_PHY_CONTROL_INRANKB1", - "INRANKC0": "CMT_PHY_CONTROL_INRANKC0", - "INRANKC1": "CMT_PHY_CONTROL_INRANKC1", - "INRANKD0": "CMT_PHY_CONTROL_INRANKD0", - "INRANKD1": "CMT_PHY_CONTROL_INRANKD1", - "MEMREFCLK": "CMT_PHY_CONTROL_MEMREFCLK", - "OUTBURSTPENDING0": "CMT_PHY_CONTROL_OUTBURSTPENDING0", - "OUTBURSTPENDING1": "CMT_PHY_CONTROL_OUTBURSTPENDING1", - "OUTBURSTPENDING2": "CMT_PHY_CONTROL_OUTBURSTPENDING2", - "OUTBURSTPENDING3": "CMT_PHY_CONTROL_OUTBURSTPENDING3", - "PCENABLECALIB0": "CMT_PHY_CONTROL_PCENABLECALIB0", - "PCENABLECALIB1": "CMT_PHY_CONTROL_PCENABLECALIB1", - "PHYCLK": "CMT_PHY_CONTROL_PHYCLK", - "PHYCTLALMOSTFULL": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", - "PHYCTLEMPTY": "CMT_PHY_CONTROL_PHYCTLEMPTY", - "PHYCTLFULL": "CMT_PHY_CONTROL_PHYCTLFULL", - "PHYCTLMSTREMPTY": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", - "PHYCTLREADY": "CMT_PHY_CONTROL_PHYCTLREADY", - "PHYCTLWD0": "CMT_PHY_CONTROL_PHYCTLWD0", - "PHYCTLWD1": "CMT_PHY_CONTROL_PHYCTLWD1", - "PHYCTLWD10": "CMT_PHY_CONTROL_PHYCTLWD10", - "PHYCTLWD11": "CMT_PHY_CONTROL_PHYCTLWD11", - "PHYCTLWD12": "CMT_PHY_CONTROL_PHYCTLWD12", - "PHYCTLWD13": "CMT_PHY_CONTROL_PHYCTLWD13", - "PHYCTLWD14": "CMT_PHY_CONTROL_PHYCTLWD14", - "PHYCTLWD15": "CMT_PHY_CONTROL_PHYCTLWD15", - "PHYCTLWD16": "CMT_PHY_CONTROL_PHYCTLWD16", - "PHYCTLWD17": "CMT_PHY_CONTROL_PHYCTLWD17", - "PHYCTLWD18": "CMT_PHY_CONTROL_PHYCTLWD18", - "PHYCTLWD19": "CMT_PHY_CONTROL_PHYCTLWD19", - "PHYCTLWD2": "CMT_PHY_CONTROL_PHYCTLWD2", - "PHYCTLWD20": "CMT_PHY_CONTROL_PHYCTLWD20", - "PHYCTLWD21": "CMT_PHY_CONTROL_PHYCTLWD21", - "PHYCTLWD22": "CMT_PHY_CONTROL_PHYCTLWD22", - "PHYCTLWD23": "CMT_PHY_CONTROL_PHYCTLWD23", - "PHYCTLWD24": "CMT_PHY_CONTROL_PHYCTLWD24", - "PHYCTLWD25": "CMT_PHY_CONTROL_PHYCTLWD25", - "PHYCTLWD26": "CMT_PHY_CONTROL_PHYCTLWD26", - "PHYCTLWD27": "CMT_PHY_CONTROL_PHYCTLWD27", - "PHYCTLWD28": "CMT_PHY_CONTROL_PHYCTLWD28", - "PHYCTLWD29": "CMT_PHY_CONTROL_PHYCTLWD29", - "PHYCTLWD3": "CMT_PHY_CONTROL_PHYCTLWD3", - "PHYCTLWD30": "CMT_PHY_CONTROL_PHYCTLWD30", - "PHYCTLWD31": "CMT_PHY_CONTROL_PHYCTLWD31", - "PHYCTLWD4": "CMT_PHY_CONTROL_PHYCTLWD4", - "PHYCTLWD5": "CMT_PHY_CONTROL_PHYCTLWD5", - "PHYCTLWD6": "CMT_PHY_CONTROL_PHYCTLWD6", - "PHYCTLWD7": "CMT_PHY_CONTROL_PHYCTLWD7", - "PHYCTLWD8": "CMT_PHY_CONTROL_PHYCTLWD8", - "PHYCTLWD9": "CMT_PHY_CONTROL_PHYCTLWD9", - "PHYCTLWRENABLE": "CMT_PHY_CONTROL_PHYCTLWRENABLE", - "PLLLOCK": "CMT_PHY_CONTROL_PLLLOCK", - "READCALIBENABLE": "CMT_PHY_CONTROL_READCALIBENABLE", - "REFDLLLOCK": "CMT_PHY_CONTROL_REFDLLLOCK", - "RESET": "CMT_PHY_CONTROL_RESET", - "SCANENABLEN": "CMT_PHY_CONTROL_SCANENABLEN", - "SYNCIN": "CMT_PHY_CONTROL_SYNCIN", - "TESTINPUT0": "CMT_PHY_CONTROL_TESTINPUT0", - "TESTINPUT1": "CMT_PHY_CONTROL_TESTINPUT1", - "TESTINPUT10": "CMT_PHY_CONTROL_TESTINPUT10", - "TESTINPUT11": "CMT_PHY_CONTROL_TESTINPUT11", - "TESTINPUT12": "CMT_PHY_CONTROL_TESTINPUT12", - "TESTINPUT13": "CMT_PHY_CONTROL_TESTINPUT13", - "TESTINPUT14": "CMT_PHY_CONTROL_TESTINPUT14", - "TESTINPUT15": "CMT_PHY_CONTROL_TESTINPUT15", - "TESTINPUT2": "CMT_PHY_CONTROL_TESTINPUT2", - "TESTINPUT3": "CMT_PHY_CONTROL_TESTINPUT3", - "TESTINPUT4": "CMT_PHY_CONTROL_TESTINPUT4", - "TESTINPUT5": "CMT_PHY_CONTROL_TESTINPUT5", - "TESTINPUT6": "CMT_PHY_CONTROL_TESTINPUT6", - "TESTINPUT7": "CMT_PHY_CONTROL_TESTINPUT7", - "TESTINPUT8": "CMT_PHY_CONTROL_TESTINPUT8", - "TESTINPUT9": "CMT_PHY_CONTROL_TESTINPUT9", - "TESTOUTPUT0": "CMT_PHY_CONTROL_TESTOUTPUT0", - "TESTOUTPUT1": "CMT_PHY_CONTROL_TESTOUTPUT1", - "TESTOUTPUT10": "CMT_PHY_CONTROL_TESTOUTPUT10", - "TESTOUTPUT11": "CMT_PHY_CONTROL_TESTOUTPUT11", - "TESTOUTPUT12": "CMT_PHY_CONTROL_TESTOUTPUT12", - "TESTOUTPUT13": "CMT_PHY_CONTROL_TESTOUTPUT13", - "TESTOUTPUT14": "CMT_PHY_CONTROL_TESTOUTPUT14", - "TESTOUTPUT15": "CMT_PHY_CONTROL_TESTOUTPUT15", - "TESTOUTPUT2": "CMT_PHY_CONTROL_TESTOUTPUT2", - "TESTOUTPUT3": "CMT_PHY_CONTROL_TESTOUTPUT3", - "TESTOUTPUT4": "CMT_PHY_CONTROL_TESTOUTPUT4", - "TESTOUTPUT5": "CMT_PHY_CONTROL_TESTOUTPUT5", - "TESTOUTPUT6": "CMT_PHY_CONTROL_TESTOUTPUT6", - "TESTOUTPUT7": "CMT_PHY_CONTROL_TESTOUTPUT7", - "TESTOUTPUT8": "CMT_PHY_CONTROL_TESTOUTPUT8", - "TESTOUTPUT9": "CMT_PHY_CONTROL_TESTOUTPUT9", - "TESTSELECT0": "CMT_PHY_CONTROL_TESTSELECT0", - "TESTSELECT1": "CMT_PHY_CONTROL_TESTSELECT1", - "TESTSELECT2": "CMT_PHY_CONTROL_TESTSELECT2", - "WRITECALIBENABLE": "CMT_PHY_CONTROL_WRITECALIBENABLE" + "AUXOUTPUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_AUXOUTPUT0" + }, + "AUXOUTPUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_AUXOUTPUT1" + }, + "AUXOUTPUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_AUXOUTPUT2" + }, + "AUXOUTPUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_AUXOUTPUT3" + }, + "INBURSTPENDING0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INBURSTPENDING0" + }, + "INBURSTPENDING1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INBURSTPENDING1" + }, + "INBURSTPENDING2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INBURSTPENDING2" + }, + "INBURSTPENDING3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INBURSTPENDING3" + }, + "INRANKA0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKA0" + }, + "INRANKA1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKA1" + }, + "INRANKB0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKB0" + }, + "INRANKB1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKB1" + }, + "INRANKC0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKC0" + }, + "INRANKC1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKC1" + }, + "INRANKD0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKD0" + }, + "INRANKD1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKD1" + }, + "MEMREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_MEMREFCLK" + }, + "OUTBURSTPENDING0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_OUTBURSTPENDING0" + }, + "OUTBURSTPENDING1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_OUTBURSTPENDING1" + }, + "OUTBURSTPENDING2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_OUTBURSTPENDING2" + }, + "OUTBURSTPENDING3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_OUTBURSTPENDING3" + }, + "PCENABLECALIB0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_PCENABLECALIB0" + }, + "PCENABLECALIB1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_PCENABLECALIB1" + }, + "PHYCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCLK" + }, + "PHYCTLALMOSTFULL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL" + }, + "PHYCTLEMPTY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_PHYCTLEMPTY" + }, + "PHYCTLFULL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_PHYCTLFULL" + }, + "PHYCTLMSTREMPTY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY" + }, + "PHYCTLREADY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_PHYCTLREADY" + }, + "PHYCTLWD0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD0" + }, + "PHYCTLWD1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD1" + }, + "PHYCTLWD10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD10" + }, + "PHYCTLWD11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD11" + }, + "PHYCTLWD12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD12" + }, + "PHYCTLWD13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD13" + }, + "PHYCTLWD14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD14" + }, + "PHYCTLWD15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD15" + }, + "PHYCTLWD16": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD16" + }, + "PHYCTLWD17": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD17" + }, + "PHYCTLWD18": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD18" + }, + "PHYCTLWD19": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD19" + }, + "PHYCTLWD2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD2" + }, + "PHYCTLWD20": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD20" + }, + "PHYCTLWD21": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD21" + }, + "PHYCTLWD22": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD22" + }, + "PHYCTLWD23": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD23" + }, + "PHYCTLWD24": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD24" + }, + "PHYCTLWD25": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD25" + }, + "PHYCTLWD26": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD26" + }, + "PHYCTLWD27": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD27" + }, + "PHYCTLWD28": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD28" + }, + "PHYCTLWD29": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD29" + }, + "PHYCTLWD3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD3" + }, + "PHYCTLWD30": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD30" + }, + "PHYCTLWD31": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD31" + }, + "PHYCTLWD4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD4" + }, + "PHYCTLWD5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD5" + }, + "PHYCTLWD6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD6" + }, + "PHYCTLWD7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD7" + }, + "PHYCTLWD8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD8" + }, + "PHYCTLWD9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD9" + }, + "PHYCTLWRENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWRENABLE" + }, + "PLLLOCK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PLLLOCK" + }, + "READCALIBENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_READCALIBENABLE" + }, + "REFDLLLOCK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_REFDLLLOCK" + }, + "RESET": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_RESET" + }, + "SCANENABLEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_SCANENABLEN" + }, + "SYNCIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_SYNCIN" + }, + "TESTINPUT0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT0" + }, + "TESTINPUT1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT1" + }, + "TESTINPUT10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT10" + }, + "TESTINPUT11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT11" + }, + "TESTINPUT12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT12" + }, + "TESTINPUT13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT13" + }, + "TESTINPUT14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT14" + }, + "TESTINPUT15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT15" + }, + "TESTINPUT2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT2" + }, + "TESTINPUT3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT3" + }, + "TESTINPUT4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT4" + }, + "TESTINPUT5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": 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"CMT_PHY_CONTROL_TESTOUTPUT3" + }, + "TESTOUTPUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_TESTOUTPUT4" + }, + "TESTOUTPUT5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_TESTOUTPUT5" + }, + "TESTOUTPUT6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_TESTOUTPUT6" + }, + "TESTOUTPUT7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_TESTOUTPUT7" + }, + "TESTOUTPUT8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_TESTOUTPUT8" + }, + "TESTOUTPUT9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_TESTOUTPUT9" + }, + "TESTSELECT0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTSELECT0" + }, + "TESTSELECT1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTSELECT1" + }, + "TESTSELECT2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTSELECT2" + }, + "WRITECALIBENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_WRITECALIBENABLE" + } }, "type": "PHY_CONTROL", "x_coord": 0, @@ -2859,83 +9650,776 @@ "name": "X0Y0", "prefix": "PHASER_OUT_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", - "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", - "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", - "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", - "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", - "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", - "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", - "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", - "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", - "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", - "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", - "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", - "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", - "OCLK": "CMT_PHASER_OUT_CA_OCLK", - "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", - "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", - "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", - "RST": "CMT_PHASER_OUT_CA_RST", - "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", - "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", - "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", - "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", - "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", - "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", - "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", - "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", - "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", - "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", - "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", - "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", - "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", - "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", - "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", - "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", - "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", - "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", - "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", - "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", - "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", - "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", - "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", - "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", - "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_BURSTPENDING" + }, + "BURSTPENDINGPHY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY" + }, + "COARSEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COARSEENABLE" + }, + "COARSEINC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COARSEINC" + }, + "COARSEOVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW" + }, + "COUNTERLOADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN" + }, + "COUNTERLOADVAL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0" + }, + "COUNTERLOADVAL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1" + }, + "COUNTERLOADVAL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2" + }, + "COUNTERLOADVAL3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3" + }, + "COUNTERLOADVAL4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4" + }, + "COUNTERLOADVAL5": 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"wire": "CMT_PHASER_OUT_CA_TESTOUT1" + }, + "TESTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_TESTOUT3" + } }, "type": "PHASER_OUT_PHY", "x_coord": 0, @@ -2945,98 +10429,926 @@ "name": "X0Y0", "prefix": "PHASER_IN_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST", - "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", - "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", - "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", - "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", - "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", - "FINEINC": "CMT_PHASER_IN_CA_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", - "ICLK": "CMT_PHASER_IN_CA_ICLK", - "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", - "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", - "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", - "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", - "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", - "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", - "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", - "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", - "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", - "RCLK": "CMT_PHASER_IN_CA_RCLK", - "RST": "CMT_PHASER_IN_CA_RST", - "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", - "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", - "SCANENB": "CMT_PHASER_IN_CA_SCANENB", - "SCANIN": "CMT_PHASER_IN_CA_SCANIN", - "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", - "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", - "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", - "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", - "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", - "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", - "STG1READ": "CMT_PHASER_IN_CA_STG1READ", - "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", - "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", - "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", - "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", - "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", - "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", - "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", - "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", - "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", - "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", - "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", - "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", - "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", - "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", - "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", - "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", - "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", - "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", - "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", - "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", - "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", - "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", - "TESTIN10": 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"COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", - "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", - "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", - "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", - "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", - "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", - "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", - "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", - "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", - "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", - "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", - "OCLK": "CMT_PHASER_OUT_DB_OCLK", - "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", - "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", - "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", - "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", - "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE", - "RST": "CMT_PHASER_OUT_DB_RST", - "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", - "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", - "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", - "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", - "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", - "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", - "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", - "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", - "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", - "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", - "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", - "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", - "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", - "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", - "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", - "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3", - "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", - "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", - "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", - "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", - "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", - "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", - "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1", - "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", - "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_BURSTPENDING" + }, + "BURSTPENDINGPHY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY" + }, + "COARSEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COARSEENABLE" + }, + "COARSEINC": { + "cap": "0.000", + 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"CMT_PHASER_OUT_DB_COUNTERLOADVAL3" + }, + "COUNTERLOADVAL4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4" + }, + "COUNTERLOADVAL5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5" + }, + "COUNTERLOADVAL6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6" + }, + "COUNTERLOADVAL7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7" + }, + "COUNTERLOADVAL8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8" + }, + "COUNTERREADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COUNTERREADEN" + }, + "COUNTERREADVAL0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0" + }, + "COUNTERREADVAL1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1" + }, + "COUNTERREADVAL2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2" + }, + "COUNTERREADVAL3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3" + }, + "COUNTERREADVAL4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4" + }, + "COUNTERREADVAL5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5" + }, + "COUNTERREADVAL6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6" + }, + "COUNTERREADVAL7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7" + }, + "COUNTERREADVAL8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8" + }, + "CTSBUS0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_CTSBUS0" + }, + "CTSBUS1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_CTSBUS1" + }, + "DIVIDERST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_DIVIDERST" + }, + "DQSBUS0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_DQSBUS0" + }, + "DQSBUS1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_DQSBUS1" + }, + "DTSBUS0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_DTSBUS0" + }, + "DTSBUS1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_DTSBUS1" + }, + "EDGEADV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_EDGEADV" + }, + "ENCALIB0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_ENCALIB0" + }, + "ENCALIB1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_ENCALIB1" + }, + "ENCALIBPHY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0" + }, + "ENCALIBPHY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1" + }, + "FINEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_FINEENABLE" + }, + "FINEINC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_FINEINC" + }, + "FINEOVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW" + }, + "FREQREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_FREQREFCLK" + }, + "MEMREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_MEMREFCLK" + }, + "OCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_OCLK" + }, + "OCLKDELAYED": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_OCLKDELAYED" + }, + "OCLKDIV": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_OCLKDIV" + }, + "OSERDESRST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_OSERDESRST" + }, + "PHASEREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_PHASEREFCLK" + }, + "RDENABLE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_RDENABLE" + }, + "RST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_RST" + }, + "SCANCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SCANCLK" + }, + "SCANENB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SCANENB" + }, + "SCANIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SCANIN" + }, + "SCANMODEB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SCANMODEB" + }, + "SCANOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_SCANOUT" + }, + "SELFINEOCLKDELAY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY" + }, + "SYNCIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SYNCIN" + }, + "SYSCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SYSCLK" + }, + "TESTIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_TESTIN0" + }, + "TESTIN1": { + "cap": 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+ ], + "wire": "CMT_PHASER_OUT_DB_TESTIN9" + }, + "TESTOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_TESTOUT0" + }, + "TESTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_TESTOUT1" + }, + "TESTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_TESTOUT3" + } }, "type": "PHASER_OUT_PHY", "x_coord": 0, @@ -3132,98 +12137,926 @@ "name": "X0Y1", "prefix": "PHASER_IN_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - 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+ "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_STG1REGR1" + }, + "STG1REGR2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_STG1REGR2" + }, + "STG1REGR3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_STG1REGR3" + }, + "STG1REGR4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_STG1REGR4" + }, + "STG1REGR5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_STG1REGR5" + }, + "STG1REGR6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_STG1REGR6" + }, + "STG1REGR7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_STG1REGR7" + }, + "STG1REGR8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_STG1REGR8" + }, + "SYNCIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_SYNCIN" + }, + "SYSCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_SYSCLK" + }, + "TESTIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN0" + }, + "TESTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN1" + }, + "TESTIN10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN10" + }, + "TESTIN11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN11" + }, + "TESTIN12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN12" + }, + "TESTIN13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN13" + }, + "TESTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN2" + }, + "TESTIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN3" + }, + "TESTIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN4" + }, + "TESTIN5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN5" + }, + "TESTIN6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN6" + }, + "TESTIN7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN7" + }, + "TESTIN8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN8" + }, + "TESTIN9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN9" + }, + "TESTOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT0" + }, + "TESTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT1" + }, + "TESTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT3" + }, + "WRENABLE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_WRENABLE" + } }, "type": "PHASER_IN_PHY", "x_coord": 0, @@ -3231,3294 +13064,9792 @@ } ], "tile_type": "CMT_TOP_L_UPPER_B", - "wires": [ - "CMT_FREQ_BB_PREF_IN0", - "CMT_FREQ_BB_PREF_IN1", - "CMT_FREQ_BB_PREF_IN2", - "CMT_FREQ_BB_PREF_IN3", - "CMT_FREQ_PHASER_REFMUX_0", - "CMT_FREQ_PHASER_REFMUX_1", - "CMT_FREQ_PHASER_REFMUX_2", - "CMT_L_TOP_UPPER_B_CLKINT_2", - "CMT_L_TOP_UPPER_B_CLKINT_3", - "CMT_PHASERD_CTSBUS0", - "CMT_PHASERD_CTSBUS1", - "CMT_PHASERD_DQSBUS0", - "CMT_PHASERD_DQSBUS1", - "CMT_PHASERD_DTSBUS0", - "CMT_PHASERD_DTSBUS1", - "CMT_PHASERREF_PHASERIN_C", - "CMT_PHASERREF_PHASERIN_D", - "CMT_PHASERREF_PHASEROUT_C", - "CMT_PHASERREF_PHASEROUT_D", - "CMT_PHASERTOP_PHYCTLEMPTY", - "CMT_PHASERTOP_PHYCTLMSTREMPTY", - "CMT_PHASER_C_ICLKDIV_TOIOI", - "CMT_PHASER_C_ICLK_TOIOI", - "CMT_PHASER_C_OCLK90_TOIOI", - "CMT_PHASER_C_OCLKDIV_TOIOI", - "CMT_PHASER_C_OCLK_TOIOI", - "CMT_PHASER_IN_CA_BURSTPENDING", - "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "CMT_PHASER_IN_CA_COUNTERLOADEN", - "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "CMT_PHASER_IN_CA_COUNTERREADEN", - "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "CMT_PHASER_IN_CA_DIVIDERST", - "CMT_PHASER_IN_CA_DQSFOUND", - "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "CMT_PHASER_IN_CA_EDGEADV", - "CMT_PHASER_IN_CA_ENCALIB0", - "CMT_PHASER_IN_CA_ENCALIB1", - "CMT_PHASER_IN_CA_ENCALIBPHY0", - "CMT_PHASER_IN_CA_ENCALIBPHY1", - "CMT_PHASER_IN_CA_ENSTG1", - "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "CMT_PHASER_IN_CA_FINEENABLE", - "CMT_PHASER_IN_CA_FINEINC", - "CMT_PHASER_IN_CA_FINEOVERFLOW", - "CMT_PHASER_IN_CA_FREQREFCLK", - "CMT_PHASER_IN_CA_ICLK", - "CMT_PHASER_IN_CA_ICLKDIV", - "CMT_PHASER_IN_CA_ISERDESRST", - "CMT_PHASER_IN_CA_MEMREFCLK", - "CMT_PHASER_IN_CA_PHASELOCKED", - "CMT_PHASER_IN_CA_PHASEREFCLK", - "CMT_PHASER_IN_CA_RANKSEL0", - "CMT_PHASER_IN_CA_RANKSEL1", - "CMT_PHASER_IN_CA_RANKSELPHY0", - "CMT_PHASER_IN_CA_RANKSELPHY1", - "CMT_PHASER_IN_CA_RCLK", - "CMT_PHASER_IN_CA_RST", - "CMT_PHASER_IN_CA_RSTDQSFIND", - "CMT_PHASER_IN_CA_SCANCLK", - "CMT_PHASER_IN_CA_SCANENB", - "CMT_PHASER_IN_CA_SCANIN", - "CMT_PHASER_IN_CA_SCANMODEB", - "CMT_PHASER_IN_CA_SCANOUT", - "CMT_PHASER_IN_CA_SELCALORSTG1", - "CMT_PHASER_IN_CA_STG1INCDEC", - "CMT_PHASER_IN_CA_STG1LOAD", - "CMT_PHASER_IN_CA_STG1OVERFLOW", - "CMT_PHASER_IN_CA_STG1READ", - "CMT_PHASER_IN_CA_STG1REGL0", - "CMT_PHASER_IN_CA_STG1REGL1", - "CMT_PHASER_IN_CA_STG1REGL2", - "CMT_PHASER_IN_CA_STG1REGL3", - "CMT_PHASER_IN_CA_STG1REGL4", - "CMT_PHASER_IN_CA_STG1REGL5", - "CMT_PHASER_IN_CA_STG1REGL6", - "CMT_PHASER_IN_CA_STG1REGL7", - "CMT_PHASER_IN_CA_STG1REGL8", - "CMT_PHASER_IN_CA_STG1REGR0", - "CMT_PHASER_IN_CA_STG1REGR1", - "CMT_PHASER_IN_CA_STG1REGR2", - "CMT_PHASER_IN_CA_STG1REGR3", - "CMT_PHASER_IN_CA_STG1REGR4", - "CMT_PHASER_IN_CA_STG1REGR5", - "CMT_PHASER_IN_CA_STG1REGR6", - "CMT_PHASER_IN_CA_STG1REGR7", - "CMT_PHASER_IN_CA_STG1REGR8", - "CMT_PHASER_IN_CA_SYNCIN", - "CMT_PHASER_IN_CA_SYSCLK", - "CMT_PHASER_IN_CA_TESTIN0", - "CMT_PHASER_IN_CA_TESTIN1", - "CMT_PHASER_IN_CA_TESTIN10", - "CMT_PHASER_IN_CA_TESTIN11", - "CMT_PHASER_IN_CA_TESTIN12", - "CMT_PHASER_IN_CA_TESTIN13", - "CMT_PHASER_IN_CA_TESTIN2", - "CMT_PHASER_IN_CA_TESTIN3", - "CMT_PHASER_IN_CA_TESTIN4", - "CMT_PHASER_IN_CA_TESTIN5", - "CMT_PHASER_IN_CA_TESTIN6", - "CMT_PHASER_IN_CA_TESTIN7", - "CMT_PHASER_IN_CA_TESTIN8", - "CMT_PHASER_IN_CA_TESTIN9", - "CMT_PHASER_IN_CA_TESTOUT0", - "CMT_PHASER_IN_CA_TESTOUT1", - "CMT_PHASER_IN_CA_TESTOUT2", - "CMT_PHASER_IN_CA_TESTOUT3", - "CMT_PHASER_IN_CA_WRENABLE", - "CMT_PHASER_IN_C_ICLK", - "CMT_PHASER_IN_C_ICLKDIV", - "CMT_PHASER_IN_C_RCLK2", - "CMT_PHASER_IN_C_WRENABLE_FIFO", - "CMT_PHASER_IN_DB_BURSTPENDING", - "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "CMT_PHASER_IN_DB_COUNTERLOADEN", - "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "CMT_PHASER_IN_DB_COUNTERREADEN", - "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "CMT_PHASER_IN_DB_DIVIDERST", - "CMT_PHASER_IN_DB_DQSFOUND", - "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "CMT_PHASER_IN_DB_EDGEADV", - "CMT_PHASER_IN_DB_ENCALIB0", - "CMT_PHASER_IN_DB_ENCALIB1", - "CMT_PHASER_IN_DB_ENCALIBPHY0", - "CMT_PHASER_IN_DB_ENCALIBPHY1", - "CMT_PHASER_IN_DB_ENSTG1", - "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "CMT_PHASER_IN_DB_FINEENABLE", - "CMT_PHASER_IN_DB_FINEINC", - "CMT_PHASER_IN_DB_FINEOVERFLOW", - "CMT_PHASER_IN_DB_FREQREFCLK", - "CMT_PHASER_IN_DB_ICLK", - "CMT_PHASER_IN_DB_ICLKDIV", - "CMT_PHASER_IN_DB_ISERDESRST", - "CMT_PHASER_IN_DB_MEMREFCLK", - "CMT_PHASER_IN_DB_PHASELOCKED", - "CMT_PHASER_IN_DB_PHASEREFCLK", - "CMT_PHASER_IN_DB_RANKSEL0", - "CMT_PHASER_IN_DB_RANKSEL1", - "CMT_PHASER_IN_DB_RANKSELPHY0", - "CMT_PHASER_IN_DB_RANKSELPHY1", - "CMT_PHASER_IN_DB_RCLK", - "CMT_PHASER_IN_DB_RST", - "CMT_PHASER_IN_DB_RSTDQSFIND", - "CMT_PHASER_IN_DB_SCANCLK", - "CMT_PHASER_IN_DB_SCANENB", - "CMT_PHASER_IN_DB_SCANIN", - "CMT_PHASER_IN_DB_SCANMODEB", - "CMT_PHASER_IN_DB_SCANOUT", - "CMT_PHASER_IN_DB_SELCALORSTG1", - "CMT_PHASER_IN_DB_STG1INCDEC", - "CMT_PHASER_IN_DB_STG1LOAD", - "CMT_PHASER_IN_DB_STG1OVERFLOW", - "CMT_PHASER_IN_DB_STG1READ", - "CMT_PHASER_IN_DB_STG1REGL0", - "CMT_PHASER_IN_DB_STG1REGL1", - "CMT_PHASER_IN_DB_STG1REGL2", - "CMT_PHASER_IN_DB_STG1REGL3", - "CMT_PHASER_IN_DB_STG1REGL4", - "CMT_PHASER_IN_DB_STG1REGL5", - "CMT_PHASER_IN_DB_STG1REGL6", - "CMT_PHASER_IN_DB_STG1REGL7", - "CMT_PHASER_IN_DB_STG1REGL8", - "CMT_PHASER_IN_DB_STG1REGR0", - "CMT_PHASER_IN_DB_STG1REGR1", - "CMT_PHASER_IN_DB_STG1REGR2", - "CMT_PHASER_IN_DB_STG1REGR3", - "CMT_PHASER_IN_DB_STG1REGR4", - "CMT_PHASER_IN_DB_STG1REGR5", - "CMT_PHASER_IN_DB_STG1REGR6", - "CMT_PHASER_IN_DB_STG1REGR7", - "CMT_PHASER_IN_DB_STG1REGR8", - "CMT_PHASER_IN_DB_SYNCIN", - "CMT_PHASER_IN_DB_SYSCLK", - "CMT_PHASER_IN_DB_TESTIN0", - "CMT_PHASER_IN_DB_TESTIN1", - "CMT_PHASER_IN_DB_TESTIN10", - "CMT_PHASER_IN_DB_TESTIN11", - "CMT_PHASER_IN_DB_TESTIN12", - "CMT_PHASER_IN_DB_TESTIN13", - "CMT_PHASER_IN_DB_TESTIN2", - "CMT_PHASER_IN_DB_TESTIN3", - "CMT_PHASER_IN_DB_TESTIN4", - "CMT_PHASER_IN_DB_TESTIN5", - "CMT_PHASER_IN_DB_TESTIN6", - "CMT_PHASER_IN_DB_TESTIN7", - "CMT_PHASER_IN_DB_TESTIN8", - "CMT_PHASER_IN_DB_TESTIN9", - "CMT_PHASER_IN_DB_TESTOUT0", - "CMT_PHASER_IN_DB_TESTOUT1", - "CMT_PHASER_IN_DB_TESTOUT2", - "CMT_PHASER_IN_DB_TESTOUT3", - "CMT_PHASER_IN_DB_WRENABLE", - "CMT_PHASER_IN_D_ICLK", - "CMT_PHASER_IN_D_ICLKDIV", - "CMT_PHASER_IN_D_RCLK3", - "CMT_PHASER_IN_D_WRENABLE_FIFO", - "CMT_PHASER_OUT_CA_BURSTPENDING", - "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "CMT_PHASER_OUT_CA_COARSEENABLE", - "CMT_PHASER_OUT_CA_COARSEINC", - "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "CMT_PHASER_OUT_CA_COUNTERREADEN", - "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CMT_PHASER_OUT_CA_CTSBUS0", - "CMT_PHASER_OUT_CA_CTSBUS1", - "CMT_PHASER_OUT_CA_DIVIDERST", - "CMT_PHASER_OUT_CA_DQSBUS0", - "CMT_PHASER_OUT_CA_DQSBUS1", - "CMT_PHASER_OUT_CA_DTSBUS0", - "CMT_PHASER_OUT_CA_DTSBUS1", - "CMT_PHASER_OUT_CA_EDGEADV", - "CMT_PHASER_OUT_CA_ENCALIB0", - "CMT_PHASER_OUT_CA_ENCALIB1", - "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "CMT_PHASER_OUT_CA_FINEENABLE", - "CMT_PHASER_OUT_CA_FINEINC", - "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "CMT_PHASER_OUT_CA_FREQREFCLK", - "CMT_PHASER_OUT_CA_MEMREFCLK", - "CMT_PHASER_OUT_CA_OCLK", - "CMT_PHASER_OUT_CA_OCLKDELAYED", - "CMT_PHASER_OUT_CA_OCLKDIV", - "CMT_PHASER_OUT_CA_OSERDESRST", - "CMT_PHASER_OUT_CA_PHASEREFCLK", - "CMT_PHASER_OUT_CA_RDENABLE", - "CMT_PHASER_OUT_CA_RST", - "CMT_PHASER_OUT_CA_SCANCLK", - "CMT_PHASER_OUT_CA_SCANENB", - "CMT_PHASER_OUT_CA_SCANIN", - "CMT_PHASER_OUT_CA_SCANMODEB", - "CMT_PHASER_OUT_CA_SCANOUT", - "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "CMT_PHASER_OUT_CA_SYNCIN", - "CMT_PHASER_OUT_CA_SYSCLK", - "CMT_PHASER_OUT_CA_TESTIN0", - "CMT_PHASER_OUT_CA_TESTIN1", - "CMT_PHASER_OUT_CA_TESTIN10", - "CMT_PHASER_OUT_CA_TESTIN11", - "CMT_PHASER_OUT_CA_TESTIN12", - "CMT_PHASER_OUT_CA_TESTIN13", - "CMT_PHASER_OUT_CA_TESTIN14", - "CMT_PHASER_OUT_CA_TESTIN15", - "CMT_PHASER_OUT_CA_TESTIN2", - "CMT_PHASER_OUT_CA_TESTIN3", - "CMT_PHASER_OUT_CA_TESTIN4", - "CMT_PHASER_OUT_CA_TESTIN5", - "CMT_PHASER_OUT_CA_TESTIN6", - "CMT_PHASER_OUT_CA_TESTIN7", - "CMT_PHASER_OUT_CA_TESTIN8", - "CMT_PHASER_OUT_CA_TESTIN9", - "CMT_PHASER_OUT_CA_TESTOUT0", - "CMT_PHASER_OUT_CA_TESTOUT1", - "CMT_PHASER_OUT_CA_TESTOUT2", - "CMT_PHASER_OUT_CA_TESTOUT3", - "CMT_PHASER_OUT_C_OCLK", - "CMT_PHASER_OUT_C_OCLK1X_90", - "CMT_PHASER_OUT_C_OCLKDIV", - "CMT_PHASER_OUT_DB_BURSTPENDING", - "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "CMT_PHASER_OUT_DB_COARSEENABLE", - "CMT_PHASER_OUT_DB_COARSEINC", - "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "CMT_PHASER_OUT_DB_COUNTERREADEN", - "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "CMT_PHASER_OUT_DB_CTSBUS0", - "CMT_PHASER_OUT_DB_CTSBUS1", - "CMT_PHASER_OUT_DB_DIVIDERST", - "CMT_PHASER_OUT_DB_DQSBUS0", - "CMT_PHASER_OUT_DB_DQSBUS1", - "CMT_PHASER_OUT_DB_DTSBUS0", - "CMT_PHASER_OUT_DB_DTSBUS1", - "CMT_PHASER_OUT_DB_EDGEADV", - "CMT_PHASER_OUT_DB_ENCALIB0", - "CMT_PHASER_OUT_DB_ENCALIB1", - "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "CMT_PHASER_OUT_DB_FINEENABLE", - "CMT_PHASER_OUT_DB_FINEINC", - "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "CMT_PHASER_OUT_DB_FREQREFCLK", - "CMT_PHASER_OUT_DB_MEMREFCLK", - "CMT_PHASER_OUT_DB_OCLK", - "CMT_PHASER_OUT_DB_OCLKDELAYED", - "CMT_PHASER_OUT_DB_OCLKDIV", - "CMT_PHASER_OUT_DB_OSERDESRST", - "CMT_PHASER_OUT_DB_PHASEREFCLK", - "CMT_PHASER_OUT_DB_RDENABLE", - "CMT_PHASER_OUT_DB_RST", - "CMT_PHASER_OUT_DB_SCANCLK", - "CMT_PHASER_OUT_DB_SCANENB", - "CMT_PHASER_OUT_DB_SCANIN", - "CMT_PHASER_OUT_DB_SCANMODEB", - "CMT_PHASER_OUT_DB_SCANOUT", - "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "CMT_PHASER_OUT_DB_SYNCIN", - "CMT_PHASER_OUT_DB_SYSCLK", - "CMT_PHASER_OUT_DB_TESTIN0", - "CMT_PHASER_OUT_DB_TESTIN1", - "CMT_PHASER_OUT_DB_TESTIN10", - "CMT_PHASER_OUT_DB_TESTIN11", - "CMT_PHASER_OUT_DB_TESTIN12", - "CMT_PHASER_OUT_DB_TESTIN13", - "CMT_PHASER_OUT_DB_TESTIN14", - "CMT_PHASER_OUT_DB_TESTIN15", - "CMT_PHASER_OUT_DB_TESTIN2", - "CMT_PHASER_OUT_DB_TESTIN3", - "CMT_PHASER_OUT_DB_TESTIN4", - "CMT_PHASER_OUT_DB_TESTIN5", - "CMT_PHASER_OUT_DB_TESTIN6", - "CMT_PHASER_OUT_DB_TESTIN7", - "CMT_PHASER_OUT_DB_TESTIN8", - "CMT_PHASER_OUT_DB_TESTIN9", - "CMT_PHASER_OUT_DB_TESTOUT0", - "CMT_PHASER_OUT_DB_TESTOUT1", - "CMT_PHASER_OUT_DB_TESTOUT2", - "CMT_PHASER_OUT_DB_TESTOUT3", - "CMT_PHASER_OUT_D_OCLK", - "CMT_PHASER_OUT_D_OCLK1X_90", - "CMT_PHASER_OUT_D_OCLKDIV", - "CMT_PHASER_REF_CLKIN", - "CMT_PHASER_REF_CLKOUT", - "CMT_PHASER_REF_CLKOUT_TOHCLK", - "CMT_PHASER_REF_LOCKED", - "CMT_PHASER_REF_PWRDWN", - "CMT_PHASER_REF_RST", - "CMT_PHASER_REF_TESTIN0", - "CMT_PHASER_REF_TESTIN1", - "CMT_PHASER_REF_TESTIN2", - "CMT_PHASER_REF_TESTIN3", - "CMT_PHASER_REF_TESTIN4", - "CMT_PHASER_REF_TESTIN5", - "CMT_PHASER_REF_TESTIN6", - "CMT_PHASER_REF_TESTIN7", - "CMT_PHASER_REF_TESTOUT0", - "CMT_PHASER_REF_TESTOUT1", - "CMT_PHASER_REF_TESTOUT2", - "CMT_PHASER_REF_TESTOUT3", - "CMT_PHASER_REF_TESTOUT4", - "CMT_PHASER_REF_TESTOUT5", - "CMT_PHASER_REF_TESTOUT6", - "CMT_PHASER_REF_TESTOUT7", - "CMT_PHASER_REF_TMUXOUT", - "CMT_PHASER_REF_TMUXOUT_TOHCLK", - "CMT_PHASER_TOP_SYNC_BB", - "CMT_PHASER_UP_BUFMRCE_CE0", - "CMT_PHASER_UP_BUFMRCE_CE1", - "CMT_PHASER_UP_DQS_TO_PHASER_C", - "CMT_PHASER_UP_DQS_TO_PHASER_D", - "CMT_PHASER_UP_PHASERREF0", - "CMT_PHASER_UP_PHASERREF1", - "CMT_PHASER_UP_PHASERREF_ABOVE0", - "CMT_PHASER_UP_PHASERREF_ABOVE1", - "CMT_PHASER_UP_PHASERREF_BELOW0", - "CMT_PHASER_UP_PHASERREF_BELOW1", - "CMT_PHY_CONTROL_AUXOUTPUT0", - "CMT_PHY_CONTROL_AUXOUTPUT1", - "CMT_PHY_CONTROL_AUXOUTPUT2", - "CMT_PHY_CONTROL_AUXOUTPUT3", - "CMT_PHY_CONTROL_ECALIB0", - "CMT_PHY_CONTROL_ECALIB1", - "CMT_PHY_CONTROL_IBURSTPENDING0", - "CMT_PHY_CONTROL_IBURSTPENDING1", - "CMT_PHY_CONTROL_IBURSTPENDING2", - "CMT_PHY_CONTROL_IBURSTPENDING3", - "CMT_PHY_CONTROL_INBURSTPENDING0", - "CMT_PHY_CONTROL_INBURSTPENDING1", - "CMT_PHY_CONTROL_INBURSTPENDING2", - "CMT_PHY_CONTROL_INBURSTPENDING3", - "CMT_PHY_CONTROL_INRANKA0", - "CMT_PHY_CONTROL_INRANKA1", - "CMT_PHY_CONTROL_INRANKB0", - "CMT_PHY_CONTROL_INRANKB1", - "CMT_PHY_CONTROL_INRANKC0", - "CMT_PHY_CONTROL_INRANKC1", - "CMT_PHY_CONTROL_INRANKD0", - "CMT_PHY_CONTROL_INRANKD1", - "CMT_PHY_CONTROL_IRANKA0", - "CMT_PHY_CONTROL_IRANKA1", - "CMT_PHY_CONTROL_IRANKB0", - "CMT_PHY_CONTROL_IRANKB1", - "CMT_PHY_CONTROL_IRANKC0", - "CMT_PHY_CONTROL_IRANKC1", - "CMT_PHY_CONTROL_IRANKD0", - "CMT_PHY_CONTROL_IRANKD1", - "CMT_PHY_CONTROL_MEMREFCLK", - "CMT_PHY_CONTROL_OBURSTPENDING0", - "CMT_PHY_CONTROL_OBURSTPENDING1", - "CMT_PHY_CONTROL_OBURSTPENDING2", - "CMT_PHY_CONTROL_OBURSTPENDING3", - "CMT_PHY_CONTROL_OUTBURSTPENDING0", - "CMT_PHY_CONTROL_OUTBURSTPENDING1", - "CMT_PHY_CONTROL_OUTBURSTPENDING2", - "CMT_PHY_CONTROL_OUTBURSTPENDING3", - "CMT_PHY_CONTROL_PCENABLECALIB0", - "CMT_PHY_CONTROL_PCENABLECALIB1", - "CMT_PHY_CONTROL_PHYCLK", - "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", - "CMT_PHY_CONTROL_PHYCTLEMPTY", - "CMT_PHY_CONTROL_PHYCTLFULL", - "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", - "CMT_PHY_CONTROL_PHYCTLREADY", - "CMT_PHY_CONTROL_PHYCTLWD0", - "CMT_PHY_CONTROL_PHYCTLWD1", - "CMT_PHY_CONTROL_PHYCTLWD10", - "CMT_PHY_CONTROL_PHYCTLWD11", - "CMT_PHY_CONTROL_PHYCTLWD12", - "CMT_PHY_CONTROL_PHYCTLWD13", - "CMT_PHY_CONTROL_PHYCTLWD14", - "CMT_PHY_CONTROL_PHYCTLWD15", - "CMT_PHY_CONTROL_PHYCTLWD16", - "CMT_PHY_CONTROL_PHYCTLWD17", - "CMT_PHY_CONTROL_PHYCTLWD18", - "CMT_PHY_CONTROL_PHYCTLWD19", - "CMT_PHY_CONTROL_PHYCTLWD2", - "CMT_PHY_CONTROL_PHYCTLWD20", - "CMT_PHY_CONTROL_PHYCTLWD21", - "CMT_PHY_CONTROL_PHYCTLWD22", - "CMT_PHY_CONTROL_PHYCTLWD23", - "CMT_PHY_CONTROL_PHYCTLWD24", - "CMT_PHY_CONTROL_PHYCTLWD25", - "CMT_PHY_CONTROL_PHYCTLWD26", - "CMT_PHY_CONTROL_PHYCTLWD27", - "CMT_PHY_CONTROL_PHYCTLWD28", - "CMT_PHY_CONTROL_PHYCTLWD29", - "CMT_PHY_CONTROL_PHYCTLWD3", - "CMT_PHY_CONTROL_PHYCTLWD30", - "CMT_PHY_CONTROL_PHYCTLWD31", - "CMT_PHY_CONTROL_PHYCTLWD4", - "CMT_PHY_CONTROL_PHYCTLWD5", - "CMT_PHY_CONTROL_PHYCTLWD6", - "CMT_PHY_CONTROL_PHYCTLWD7", - "CMT_PHY_CONTROL_PHYCTLWD8", - "CMT_PHY_CONTROL_PHYCTLWD9", - "CMT_PHY_CONTROL_PHYCTLWRENABLE", - "CMT_PHY_CONTROL_PLLLOCK", - "CMT_PHY_CONTROL_READCALIBENABLE", - "CMT_PHY_CONTROL_REFDLLLOCK", - "CMT_PHY_CONTROL_RESET", - "CMT_PHY_CONTROL_SCANENABLEN", - "CMT_PHY_CONTROL_SYNCIN", - "CMT_PHY_CONTROL_TESTINPUT0", - "CMT_PHY_CONTROL_TESTINPUT1", - "CMT_PHY_CONTROL_TESTINPUT10", - "CMT_PHY_CONTROL_TESTINPUT11", - "CMT_PHY_CONTROL_TESTINPUT12", - "CMT_PHY_CONTROL_TESTINPUT13", - "CMT_PHY_CONTROL_TESTINPUT14", - "CMT_PHY_CONTROL_TESTINPUT15", - "CMT_PHY_CONTROL_TESTINPUT2", - "CMT_PHY_CONTROL_TESTINPUT3", - "CMT_PHY_CONTROL_TESTINPUT4", - "CMT_PHY_CONTROL_TESTINPUT5", - "CMT_PHY_CONTROL_TESTINPUT6", - "CMT_PHY_CONTROL_TESTINPUT7", - "CMT_PHY_CONTROL_TESTINPUT8", - "CMT_PHY_CONTROL_TESTINPUT9", - "CMT_PHY_CONTROL_TESTOUTPUT0", - "CMT_PHY_CONTROL_TESTOUTPUT1", - "CMT_PHY_CONTROL_TESTOUTPUT10", - "CMT_PHY_CONTROL_TESTOUTPUT11", - "CMT_PHY_CONTROL_TESTOUTPUT12", - "CMT_PHY_CONTROL_TESTOUTPUT13", - "CMT_PHY_CONTROL_TESTOUTPUT14", - "CMT_PHY_CONTROL_TESTOUTPUT15", - "CMT_PHY_CONTROL_TESTOUTPUT2", - "CMT_PHY_CONTROL_TESTOUTPUT3", - "CMT_PHY_CONTROL_TESTOUTPUT4", - "CMT_PHY_CONTROL_TESTOUTPUT5", - "CMT_PHY_CONTROL_TESTOUTPUT6", - "CMT_PHY_CONTROL_TESTOUTPUT7", - "CMT_PHY_CONTROL_TESTOUTPUT8", - "CMT_PHY_CONTROL_TESTOUTPUT9", - "CMT_PHY_CONTROL_TESTSELECT0", - "CMT_PHY_CONTROL_TESTSELECT1", - "CMT_PHY_CONTROL_TESTSELECT2", - "CMT_PHY_CONTROL_WRITECALIBENABLE", - "CMT_R_PHASER_IN_C_WRCLK_FIFO", - "CMT_R_PHASER_IN_D_WRCLK_TOFIFO", - "CMT_R_PHASER_OUT_C_RDCLK_FIFO", - "CMT_R_PHASER_OUT_C_RDENABLE_FIFO", - "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO", - "CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO", - "CMT_R_TOP_UPPER_B_CLKFBIN", - "CMT_R_TOP_UPPER_B_CLKIN1", - "CMT_R_TOP_UPPER_B_CLKIN2", - "CMT_R_TOP_UPPER_B_CLKPLL0", - "CMT_R_TOP_UPPER_B_CLKPLL1", - "CMT_R_TOP_UPPER_B_CLKPLL2", - "CMT_R_TOP_UPPER_B_CLKPLL3", - "CMT_R_TOP_UPPER_B_CLKPLL4", - "CMT_R_TOP_UPPER_B_CLKPLL5", - "CMT_R_TOP_UPPER_B_CLKPLL6", - "CMT_R_TOP_UPPER_B_CLKPLL7", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_BLOCK_OUTS_L_B0_10", - "CMT_TOP_BLOCK_OUTS_L_B0_11", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_BLOCK_OUTS_L_B0_9", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_BLOCK_OUTS_L_B1_10", - "CMT_TOP_BLOCK_OUTS_L_B1_11", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_BYP0_0", - "CMT_TOP_BYP0_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_BYP0_11", - "CMT_TOP_BYP0_2", - "CMT_TOP_BYP0_3", - "CMT_TOP_BYP0_4", - "CMT_TOP_BYP0_5", - "CMT_TOP_BYP0_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_BYP0_8", - "CMT_TOP_BYP0_9", - "CMT_TOP_BYP1_0", - "CMT_TOP_BYP1_1", - "CMT_TOP_BYP1_10", - "CMT_TOP_BYP1_11", - "CMT_TOP_BYP1_2", - "CMT_TOP_BYP1_3", - "CMT_TOP_BYP1_4", - "CMT_TOP_BYP1_5", - "CMT_TOP_BYP1_6", - "CMT_TOP_BYP1_7", - "CMT_TOP_BYP1_8", - "CMT_TOP_BYP1_9", - "CMT_TOP_BYP2_0", - "CMT_TOP_BYP2_1", - "CMT_TOP_BYP2_10", - "CMT_TOP_BYP2_11", - "CMT_TOP_BYP2_2", - "CMT_TOP_BYP2_3", - "CMT_TOP_BYP2_4", - "CMT_TOP_BYP2_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_BYP3_0", - "CMT_TOP_BYP3_1", - "CMT_TOP_BYP3_10", - "CMT_TOP_BYP3_11", - "CMT_TOP_BYP3_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_BYP3_4", - "CMT_TOP_BYP3_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_BYP3_8", - "CMT_TOP_BYP3_9", - "CMT_TOP_BYP4_0", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP4_10", - "CMT_TOP_BYP4_11", - "CMT_TOP_BYP4_2", - "CMT_TOP_BYP4_3", - "CMT_TOP_BYP4_4", - "CMT_TOP_BYP4_5", - "CMT_TOP_BYP4_6", - "CMT_TOP_BYP4_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_BYP4_9", - "CMT_TOP_BYP5_0", - "CMT_TOP_BYP5_1", - "CMT_TOP_BYP5_10", - "CMT_TOP_BYP5_11", - "CMT_TOP_BYP5_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_BYP5_4", - "CMT_TOP_BYP5_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_BYP5_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_BYP5_9", - "CMT_TOP_BYP6_0", - "CMT_TOP_BYP6_1", - "CMT_TOP_BYP6_10", - "CMT_TOP_BYP6_11", - "CMT_TOP_BYP6_2", - "CMT_TOP_BYP6_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_BYP6_5", - "CMT_TOP_BYP6_6", - "CMT_TOP_BYP6_7", - "CMT_TOP_BYP6_8", - "CMT_TOP_BYP6_9", - "CMT_TOP_BYP7_0", - "CMT_TOP_BYP7_1", - "CMT_TOP_BYP7_10", - "CMT_TOP_BYP7_11", - "CMT_TOP_BYP7_2", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP7_4", - "CMT_TOP_BYP7_5", - "CMT_TOP_BYP7_6", - "CMT_TOP_BYP7_7", - "CMT_TOP_BYP7_8", - "CMT_TOP_BYP7_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_CLK0_1", - "CMT_TOP_CLK0_10", - "CMT_TOP_CLK0_11", - "CMT_TOP_CLK0_2", - "CMT_TOP_CLK0_3", - "CMT_TOP_CLK0_4", - "CMT_TOP_CLK0_5", - "CMT_TOP_CLK0_6", - "CMT_TOP_CLK0_7", - "CMT_TOP_CLK0_8", - "CMT_TOP_CLK0_9", - "CMT_TOP_CLK1_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_CLK1_10", - "CMT_TOP_CLK1_11", - "CMT_TOP_CLK1_2", - "CMT_TOP_CLK1_3", - "CMT_TOP_CLK1_4", - "CMT_TOP_CLK1_5", - "CMT_TOP_CLK1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_CLK1_8", - "CMT_TOP_CLK1_9", - "CMT_TOP_CTRL0_0", - "CMT_TOP_CTRL0_1", - "CMT_TOP_CTRL0_10", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CTRL0_2", - "CMT_TOP_CTRL0_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_CTRL0_5", - "CMT_TOP_CTRL0_6", - "CMT_TOP_CTRL0_7", - "CMT_TOP_CTRL0_8", - "CMT_TOP_CTRL0_9", - "CMT_TOP_CTRL1_0", - "CMT_TOP_CTRL1_1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_CTRL1_11", - "CMT_TOP_CTRL1_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_CTRL1_4", - "CMT_TOP_CTRL1_5", - "CMT_TOP_CTRL1_6", - "CMT_TOP_CTRL1_7", - "CMT_TOP_CTRL1_8", - "CMT_TOP_CTRL1_9", - "CMT_TOP_EE2A0_0", - "CMT_TOP_EE2A0_1", - "CMT_TOP_EE2A0_10", - "CMT_TOP_EE2A0_11", - "CMT_TOP_EE2A0_2", - "CMT_TOP_EE2A0_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_EE2A0_6", - "CMT_TOP_EE2A0_7", - "CMT_TOP_EE2A0_8", - "CMT_TOP_EE2A0_9", - "CMT_TOP_EE2A1_0", - "CMT_TOP_EE2A1_1", - "CMT_TOP_EE2A1_10", - "CMT_TOP_EE2A1_11", - "CMT_TOP_EE2A1_2", - "CMT_TOP_EE2A1_3", - "CMT_TOP_EE2A1_4", - "CMT_TOP_EE2A1_5", - "CMT_TOP_EE2A1_6", - "CMT_TOP_EE2A1_7", - "CMT_TOP_EE2A1_8", - "CMT_TOP_EE2A1_9", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_1", - "CMT_TOP_EE2A2_10", - "CMT_TOP_EE2A2_11", - "CMT_TOP_EE2A2_2", - "CMT_TOP_EE2A2_3", - "CMT_TOP_EE2A2_4", - "CMT_TOP_EE2A2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_EE2A2_7", - "CMT_TOP_EE2A2_8", - "CMT_TOP_EE2A2_9", - "CMT_TOP_EE2A3_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_EE2A3_10", - "CMT_TOP_EE2A3_11", - "CMT_TOP_EE2A3_2", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2A3_4", - "CMT_TOP_EE2A3_5", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE2A3_8", - "CMT_TOP_EE2A3_9", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_EE2BEG0_11", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_EE2BEG0_9", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE2BEG3_9", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_EE4A0_10", - "CMT_TOP_EE4A0_11", - "CMT_TOP_EE4A0_2", - "CMT_TOP_EE4A0_3", - "CMT_TOP_EE4A0_4", - "CMT_TOP_EE4A0_5", - "CMT_TOP_EE4A0_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4A0_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_EE4A1_1", - "CMT_TOP_EE4A1_10", - "CMT_TOP_EE4A1_11", - "CMT_TOP_EE4A1_2", - "CMT_TOP_EE4A1_3", - "CMT_TOP_EE4A1_4", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4A1_8", - "CMT_TOP_EE4A1_9", - "CMT_TOP_EE4A2_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_EE4A2_10", - "CMT_TOP_EE4A2_11", - "CMT_TOP_EE4A2_2", - "CMT_TOP_EE4A2_3", - "CMT_TOP_EE4A2_4", - "CMT_TOP_EE4A2_5", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE4A2_7", - "CMT_TOP_EE4A2_8", - "CMT_TOP_EE4A2_9", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4A3_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_EE4A3_11", - "CMT_TOP_EE4A3_2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_EE4A3_5", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE4A3_7", - "CMT_TOP_EE4A3_8", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EE4B0_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_EE4B0_10", - "CMT_TOP_EE4B0_11", - "CMT_TOP_EE4B0_2", - "CMT_TOP_EE4B0_3", - "CMT_TOP_EE4B0_4", - "CMT_TOP_EE4B0_5", - "CMT_TOP_EE4B0_6", - "CMT_TOP_EE4B0_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_EE4B0_9", - "CMT_TOP_EE4B1_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_EE4B1_10", - "CMT_TOP_EE4B1_11", - "CMT_TOP_EE4B1_2", - "CMT_TOP_EE4B1_3", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4B1_8", - "CMT_TOP_EE4B1_9", - "CMT_TOP_EE4B2_0", - "CMT_TOP_EE4B2_1", - "CMT_TOP_EE4B2_10", - "CMT_TOP_EE4B2_11", - "CMT_TOP_EE4B2_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4B2_5", - "CMT_TOP_EE4B2_6", - "CMT_TOP_EE4B2_7", - "CMT_TOP_EE4B2_8", - "CMT_TOP_EE4B2_9", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE4B3_10", - "CMT_TOP_EE4B3_11", - "CMT_TOP_EE4B3_2", - "CMT_TOP_EE4B3_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_EE4B3_5", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EE4B3_7", - "CMT_TOP_EE4B3_8", - "CMT_TOP_EE4B3_9", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_EE4BEG0_11", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_EE4BEG1_9", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_EE4BEG2_10", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_EE4C0_0", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4C0_10", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EE4C0_2", - "CMT_TOP_EE4C0_3", - "CMT_TOP_EE4C0_4", - "CMT_TOP_EE4C0_5", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4C0_7", - "CMT_TOP_EE4C0_8", - "CMT_TOP_EE4C0_9", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4C1_1", - "CMT_TOP_EE4C1_10", - "CMT_TOP_EE4C1_11", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE4C1_3", - "CMT_TOP_EE4C1_4", - "CMT_TOP_EE4C1_5", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_7", - "CMT_TOP_EE4C1_8", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4C2_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_EE4C2_10", - "CMT_TOP_EE4C2_11", - "CMT_TOP_EE4C2_2", - "CMT_TOP_EE4C2_3", - "CMT_TOP_EE4C2_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EE4C2_7", - "CMT_TOP_EE4C2_8", - "CMT_TOP_EE4C2_9", - "CMT_TOP_EE4C3_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_EE4C3_10", - "CMT_TOP_EE4C3_11", - "CMT_TOP_EE4C3_2", - "CMT_TOP_EE4C3_3", - "CMT_TOP_EE4C3_4", - "CMT_TOP_EE4C3_5", - "CMT_TOP_EE4C3_6", - "CMT_TOP_EE4C3_7", - "CMT_TOP_EE4C3_8", - "CMT_TOP_EE4C3_9", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EL1BEG1_10", - "CMT_TOP_EL1BEG1_11", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_EL1BEG1_9", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_ER1BEG1_10", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_ER1BEG2_10", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_FAN0_0", - "CMT_TOP_FAN0_1", - "CMT_TOP_FAN0_10", - "CMT_TOP_FAN0_11", - "CMT_TOP_FAN0_2", - "CMT_TOP_FAN0_3", - "CMT_TOP_FAN0_4", - "CMT_TOP_FAN0_5", - "CMT_TOP_FAN0_6", - "CMT_TOP_FAN0_7", - "CMT_TOP_FAN0_8", - "CMT_TOP_FAN0_9", - "CMT_TOP_FAN1_0", - "CMT_TOP_FAN1_1", - "CMT_TOP_FAN1_10", - "CMT_TOP_FAN1_11", - "CMT_TOP_FAN1_2", - "CMT_TOP_FAN1_3", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_5", - "CMT_TOP_FAN1_6", - "CMT_TOP_FAN1_7", - "CMT_TOP_FAN1_8", - "CMT_TOP_FAN1_9", - "CMT_TOP_FAN2_0", - "CMT_TOP_FAN2_1", - "CMT_TOP_FAN2_10", - "CMT_TOP_FAN2_11", - "CMT_TOP_FAN2_2", - "CMT_TOP_FAN2_3", - "CMT_TOP_FAN2_4", - "CMT_TOP_FAN2_5", - "CMT_TOP_FAN2_6", - "CMT_TOP_FAN2_7", - "CMT_TOP_FAN2_8", - "CMT_TOP_FAN2_9", - "CMT_TOP_FAN3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_FAN3_10", - "CMT_TOP_FAN3_11", - "CMT_TOP_FAN3_2", - "CMT_TOP_FAN3_3", - "CMT_TOP_FAN3_4", - "CMT_TOP_FAN3_5", - "CMT_TOP_FAN3_6", - "CMT_TOP_FAN3_7", - "CMT_TOP_FAN3_8", - "CMT_TOP_FAN3_9", - "CMT_TOP_FAN4_0", - "CMT_TOP_FAN4_1", - "CMT_TOP_FAN4_10", - "CMT_TOP_FAN4_11", - "CMT_TOP_FAN4_2", - "CMT_TOP_FAN4_3", - "CMT_TOP_FAN4_4", - "CMT_TOP_FAN4_5", - "CMT_TOP_FAN4_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_FAN4_8", - "CMT_TOP_FAN4_9", - "CMT_TOP_FAN5_0", - "CMT_TOP_FAN5_1", - "CMT_TOP_FAN5_10", - "CMT_TOP_FAN5_11", - "CMT_TOP_FAN5_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_FAN5_5", - "CMT_TOP_FAN5_6", - "CMT_TOP_FAN5_7", - "CMT_TOP_FAN5_8", - "CMT_TOP_FAN5_9", - "CMT_TOP_FAN6_0", - "CMT_TOP_FAN6_1", - "CMT_TOP_FAN6_10", - "CMT_TOP_FAN6_11", - "CMT_TOP_FAN6_2", - "CMT_TOP_FAN6_3", - "CMT_TOP_FAN6_4", - "CMT_TOP_FAN6_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_FAN6_7", - "CMT_TOP_FAN6_8", - "CMT_TOP_FAN6_9", - "CMT_TOP_FAN7_0", - "CMT_TOP_FAN7_1", - "CMT_TOP_FAN7_10", - "CMT_TOP_FAN7_11", - "CMT_TOP_FAN7_2", - "CMT_TOP_FAN7_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_FAN7_5", - "CMT_TOP_FAN7_6", - "CMT_TOP_FAN7_7", - "CMT_TOP_FAN7_8", - "CMT_TOP_FAN7_9", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_ICLKDIV_10", - "CMT_TOP_ICLKDIV_11", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ICLKDIV_9", - "CMT_TOP_ICLK_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_ICLK_10", - "CMT_TOP_ICLK_11", - "CMT_TOP_ICLK_2", - "CMT_TOP_ICLK_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_ICLK_5", - "CMT_TOP_ICLK_6", - "CMT_TOP_ICLK_7", - "CMT_TOP_ICLK_8", - "CMT_TOP_ICLK_9", - "CMT_TOP_IMUX0_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_IMUX0_10", - "CMT_TOP_IMUX0_11", - "CMT_TOP_IMUX0_2", - "CMT_TOP_IMUX0_3", - "CMT_TOP_IMUX0_4", - "CMT_TOP_IMUX0_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX0_8", - "CMT_TOP_IMUX0_9", - "CMT_TOP_IMUX10_0", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX10_10", - "CMT_TOP_IMUX10_11", - "CMT_TOP_IMUX10_2", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX10_4", - "CMT_TOP_IMUX10_5", - "CMT_TOP_IMUX10_6", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_IMUX10_9", - "CMT_TOP_IMUX11_0", - "CMT_TOP_IMUX11_1", - "CMT_TOP_IMUX11_10", - "CMT_TOP_IMUX11_11", - "CMT_TOP_IMUX11_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_IMUX11_4", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX11_7", - "CMT_TOP_IMUX11_8", - "CMT_TOP_IMUX11_9", - "CMT_TOP_IMUX12_0", - "CMT_TOP_IMUX12_1", - "CMT_TOP_IMUX12_10", - "CMT_TOP_IMUX12_11", - "CMT_TOP_IMUX12_2", - "CMT_TOP_IMUX12_3", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX12_5", - "CMT_TOP_IMUX12_6", - "CMT_TOP_IMUX12_7", - "CMT_TOP_IMUX12_8", - "CMT_TOP_IMUX12_9", - "CMT_TOP_IMUX13_0", - "CMT_TOP_IMUX13_1", - "CMT_TOP_IMUX13_10", - "CMT_TOP_IMUX13_11", - "CMT_TOP_IMUX13_2", - "CMT_TOP_IMUX13_3", - "CMT_TOP_IMUX13_4", - "CMT_TOP_IMUX13_5", - "CMT_TOP_IMUX13_6", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX13_8", - "CMT_TOP_IMUX13_9", - "CMT_TOP_IMUX14_0", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX14_10", - "CMT_TOP_IMUX14_11", - "CMT_TOP_IMUX14_2", - "CMT_TOP_IMUX14_3", - "CMT_TOP_IMUX14_4", - "CMT_TOP_IMUX14_5", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_IMUX14_9", - "CMT_TOP_IMUX15_0", - "CMT_TOP_IMUX15_1", - "CMT_TOP_IMUX15_10", - "CMT_TOP_IMUX15_11", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX15_4", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_IMUX15_9", - "CMT_TOP_IMUX16_0", - "CMT_TOP_IMUX16_1", - "CMT_TOP_IMUX16_10", - "CMT_TOP_IMUX16_11", - "CMT_TOP_IMUX16_2", - "CMT_TOP_IMUX16_3", - "CMT_TOP_IMUX16_4", - "CMT_TOP_IMUX16_5", - "CMT_TOP_IMUX16_6", - "CMT_TOP_IMUX16_7", - "CMT_TOP_IMUX16_8", - "CMT_TOP_IMUX16_9", - "CMT_TOP_IMUX17_0", - "CMT_TOP_IMUX17_1", - "CMT_TOP_IMUX17_10", - "CMT_TOP_IMUX17_11", - "CMT_TOP_IMUX17_2", - "CMT_TOP_IMUX17_3", - "CMT_TOP_IMUX17_4", - "CMT_TOP_IMUX17_5", - "CMT_TOP_IMUX17_6", - "CMT_TOP_IMUX17_7", - "CMT_TOP_IMUX17_8", - "CMT_TOP_IMUX17_9", - "CMT_TOP_IMUX18_0", - "CMT_TOP_IMUX18_1", - "CMT_TOP_IMUX18_10", - "CMT_TOP_IMUX18_11", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX18_3", - "CMT_TOP_IMUX18_4", - "CMT_TOP_IMUX18_5", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX18_7", - "CMT_TOP_IMUX18_8", - "CMT_TOP_IMUX18_9", - "CMT_TOP_IMUX19_0", - "CMT_TOP_IMUX19_1", - "CMT_TOP_IMUX19_10", - "CMT_TOP_IMUX19_11", - "CMT_TOP_IMUX19_2", - "CMT_TOP_IMUX19_3", - "CMT_TOP_IMUX19_4", - "CMT_TOP_IMUX19_5", - "CMT_TOP_IMUX19_6", - "CMT_TOP_IMUX19_7", - "CMT_TOP_IMUX19_8", - "CMT_TOP_IMUX19_9", - "CMT_TOP_IMUX1_0", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX1_10", - "CMT_TOP_IMUX1_11", - "CMT_TOP_IMUX1_2", - "CMT_TOP_IMUX1_3", - "CMT_TOP_IMUX1_4", - "CMT_TOP_IMUX1_5", - "CMT_TOP_IMUX1_6", - "CMT_TOP_IMUX1_7", - "CMT_TOP_IMUX1_8", - "CMT_TOP_IMUX1_9", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX20_1", - "CMT_TOP_IMUX20_10", - "CMT_TOP_IMUX20_11", - "CMT_TOP_IMUX20_2", - "CMT_TOP_IMUX20_3", - "CMT_TOP_IMUX20_4", - "CMT_TOP_IMUX20_5", - "CMT_TOP_IMUX20_6", - "CMT_TOP_IMUX20_7", - "CMT_TOP_IMUX20_8", - "CMT_TOP_IMUX20_9", - "CMT_TOP_IMUX21_0", - "CMT_TOP_IMUX21_1", - "CMT_TOP_IMUX21_10", - "CMT_TOP_IMUX21_11", - "CMT_TOP_IMUX21_2", - "CMT_TOP_IMUX21_3", - "CMT_TOP_IMUX21_4", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_IMUX21_7", - "CMT_TOP_IMUX21_8", - "CMT_TOP_IMUX21_9", - "CMT_TOP_IMUX22_0", - "CMT_TOP_IMUX22_1", - "CMT_TOP_IMUX22_10", - "CMT_TOP_IMUX22_11", - "CMT_TOP_IMUX22_2", - "CMT_TOP_IMUX22_3", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX22_5", - "CMT_TOP_IMUX22_6", - "CMT_TOP_IMUX22_7", - "CMT_TOP_IMUX22_8", - "CMT_TOP_IMUX22_9", - "CMT_TOP_IMUX23_0", - "CMT_TOP_IMUX23_1", - "CMT_TOP_IMUX23_10", - "CMT_TOP_IMUX23_11", - "CMT_TOP_IMUX23_2", - "CMT_TOP_IMUX23_3", - "CMT_TOP_IMUX23_4", - "CMT_TOP_IMUX23_5", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX23_7", - "CMT_TOP_IMUX23_8", - "CMT_TOP_IMUX23_9", - "CMT_TOP_IMUX24_0", - "CMT_TOP_IMUX24_1", - "CMT_TOP_IMUX24_10", - "CMT_TOP_IMUX24_11", - "CMT_TOP_IMUX24_2", - "CMT_TOP_IMUX24_3", - "CMT_TOP_IMUX24_4", - "CMT_TOP_IMUX24_5", - "CMT_TOP_IMUX24_6", - "CMT_TOP_IMUX24_7", - "CMT_TOP_IMUX24_8", - "CMT_TOP_IMUX24_9", - "CMT_TOP_IMUX25_0", - "CMT_TOP_IMUX25_1", - "CMT_TOP_IMUX25_10", - "CMT_TOP_IMUX25_11", - "CMT_TOP_IMUX25_2", - "CMT_TOP_IMUX25_3", - "CMT_TOP_IMUX25_4", - "CMT_TOP_IMUX25_5", - "CMT_TOP_IMUX25_6", - "CMT_TOP_IMUX25_7", - "CMT_TOP_IMUX25_8", - "CMT_TOP_IMUX25_9", - "CMT_TOP_IMUX26_0", - "CMT_TOP_IMUX26_1", - "CMT_TOP_IMUX26_10", - "CMT_TOP_IMUX26_11", - "CMT_TOP_IMUX26_2", - "CMT_TOP_IMUX26_3", - "CMT_TOP_IMUX26_4", - "CMT_TOP_IMUX26_5", - "CMT_TOP_IMUX26_6", - "CMT_TOP_IMUX26_7", - "CMT_TOP_IMUX26_8", - "CMT_TOP_IMUX26_9", - "CMT_TOP_IMUX27_0", - "CMT_TOP_IMUX27_1", - "CMT_TOP_IMUX27_10", - "CMT_TOP_IMUX27_11", - "CMT_TOP_IMUX27_2", - "CMT_TOP_IMUX27_3", - "CMT_TOP_IMUX27_4", - "CMT_TOP_IMUX27_5", - "CMT_TOP_IMUX27_6", - "CMT_TOP_IMUX27_7", - "CMT_TOP_IMUX27_8", - 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"CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX34_4", - "CMT_TOP_IMUX34_5", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX34_7", - "CMT_TOP_IMUX34_8", - "CMT_TOP_IMUX34_9", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX35_1", - "CMT_TOP_IMUX35_10", - "CMT_TOP_IMUX35_11", - "CMT_TOP_IMUX35_2", - "CMT_TOP_IMUX35_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_IMUX35_5", - "CMT_TOP_IMUX35_6", - "CMT_TOP_IMUX35_7", - "CMT_TOP_IMUX35_8", - "CMT_TOP_IMUX35_9", - "CMT_TOP_IMUX36_0", - "CMT_TOP_IMUX36_1", - "CMT_TOP_IMUX36_10", - "CMT_TOP_IMUX36_11", - "CMT_TOP_IMUX36_2", - "CMT_TOP_IMUX36_3", - "CMT_TOP_IMUX36_4", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX36_6", - "CMT_TOP_IMUX36_7", - "CMT_TOP_IMUX36_8", - "CMT_TOP_IMUX36_9", - "CMT_TOP_IMUX37_0", - "CMT_TOP_IMUX37_1", - "CMT_TOP_IMUX37_10", - "CMT_TOP_IMUX37_11", - "CMT_TOP_IMUX37_2", - "CMT_TOP_IMUX37_3", - "CMT_TOP_IMUX37_4", - "CMT_TOP_IMUX37_5", - "CMT_TOP_IMUX37_6", - "CMT_TOP_IMUX37_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_IMUX37_9", - "CMT_TOP_IMUX38_0", - "CMT_TOP_IMUX38_1", - "CMT_TOP_IMUX38_10", - "CMT_TOP_IMUX38_11", - "CMT_TOP_IMUX38_2", - "CMT_TOP_IMUX38_3", - "CMT_TOP_IMUX38_4", - "CMT_TOP_IMUX38_5", - "CMT_TOP_IMUX38_6", - "CMT_TOP_IMUX38_7", - "CMT_TOP_IMUX38_8", - "CMT_TOP_IMUX38_9", - "CMT_TOP_IMUX39_0", - "CMT_TOP_IMUX39_1", - "CMT_TOP_IMUX39_10", - "CMT_TOP_IMUX39_11", - "CMT_TOP_IMUX39_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX39_4", - "CMT_TOP_IMUX39_5", - "CMT_TOP_IMUX39_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_IMUX39_8", - "CMT_TOP_IMUX39_9", - "CMT_TOP_IMUX3_0", - "CMT_TOP_IMUX3_1", - "CMT_TOP_IMUX3_10", - "CMT_TOP_IMUX3_11", - "CMT_TOP_IMUX3_2", - "CMT_TOP_IMUX3_3", - "CMT_TOP_IMUX3_4", - "CMT_TOP_IMUX3_5", - "CMT_TOP_IMUX3_6", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX3_8", - "CMT_TOP_IMUX3_9", - "CMT_TOP_IMUX40_0", - "CMT_TOP_IMUX40_1", - "CMT_TOP_IMUX40_10", - "CMT_TOP_IMUX40_11", - "CMT_TOP_IMUX40_2", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX40_4", - "CMT_TOP_IMUX40_5", - "CMT_TOP_IMUX40_6", - "CMT_TOP_IMUX40_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_IMUX40_9", - "CMT_TOP_IMUX41_0", - "CMT_TOP_IMUX41_1", - "CMT_TOP_IMUX41_10", - "CMT_TOP_IMUX41_11", - "CMT_TOP_IMUX41_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX41_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_IMUX41_9", - "CMT_TOP_IMUX42_0", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX42_10", - "CMT_TOP_IMUX42_11", - "CMT_TOP_IMUX42_2", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX42_5", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX42_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_IMUX42_9", - "CMT_TOP_IMUX43_0", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX43_10", - "CMT_TOP_IMUX43_11", - "CMT_TOP_IMUX43_2", - "CMT_TOP_IMUX43_3", - "CMT_TOP_IMUX43_4", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX43_6", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX43_8", - "CMT_TOP_IMUX43_9", - "CMT_TOP_IMUX44_0", - "CMT_TOP_IMUX44_1", - "CMT_TOP_IMUX44_10", - "CMT_TOP_IMUX44_11", - "CMT_TOP_IMUX44_2", - "CMT_TOP_IMUX44_3", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX44_5", - "CMT_TOP_IMUX44_6", - "CMT_TOP_IMUX44_7", - "CMT_TOP_IMUX44_8", - "CMT_TOP_IMUX44_9", - "CMT_TOP_IMUX45_0", - "CMT_TOP_IMUX45_1", - "CMT_TOP_IMUX45_10", - "CMT_TOP_IMUX45_11", - "CMT_TOP_IMUX45_2", - "CMT_TOP_IMUX45_3", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX45_5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX45_8", - "CMT_TOP_IMUX45_9", - "CMT_TOP_IMUX46_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX46_10", - "CMT_TOP_IMUX46_11", - "CMT_TOP_IMUX46_2", - "CMT_TOP_IMUX46_3", - "CMT_TOP_IMUX46_4", - "CMT_TOP_IMUX46_5", - "CMT_TOP_IMUX46_6", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX46_8", - "CMT_TOP_IMUX46_9", - "CMT_TOP_IMUX47_0", - "CMT_TOP_IMUX47_1", - "CMT_TOP_IMUX47_10", - "CMT_TOP_IMUX47_11", - "CMT_TOP_IMUX47_2", - "CMT_TOP_IMUX47_3", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX47_5", - "CMT_TOP_IMUX47_6", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX47_9", - "CMT_TOP_IMUX4_0", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX4_10", - "CMT_TOP_IMUX4_11", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX4_3", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX4_5", - "CMT_TOP_IMUX4_6", - "CMT_TOP_IMUX4_7", - "CMT_TOP_IMUX4_8", - "CMT_TOP_IMUX4_9", - "CMT_TOP_IMUX5_0", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX5_10", - "CMT_TOP_IMUX5_11", - "CMT_TOP_IMUX5_2", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX5_6", - "CMT_TOP_IMUX5_7", - "CMT_TOP_IMUX5_8", - "CMT_TOP_IMUX5_9", - "CMT_TOP_IMUX6_0", - "CMT_TOP_IMUX6_1", - "CMT_TOP_IMUX6_10", - "CMT_TOP_IMUX6_11", - "CMT_TOP_IMUX6_2", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX6_4", - "CMT_TOP_IMUX6_5", - "CMT_TOP_IMUX6_6", - "CMT_TOP_IMUX6_7", - "CMT_TOP_IMUX6_8", - "CMT_TOP_IMUX6_9", - "CMT_TOP_IMUX7_0", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX7_10", - "CMT_TOP_IMUX7_11", - "CMT_TOP_IMUX7_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX7_8", - "CMT_TOP_IMUX7_9", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_IMUX8_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX8_3", - "CMT_TOP_IMUX8_4", - "CMT_TOP_IMUX8_5", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX8_7", - "CMT_TOP_IMUX8_8", - "CMT_TOP_IMUX8_9", - "CMT_TOP_IMUX9_0", - "CMT_TOP_IMUX9_1", - "CMT_TOP_IMUX9_10", - "CMT_TOP_IMUX9_11", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_IMUX9_4", - "CMT_TOP_IMUX9_5", - "CMT_TOP_IMUX9_6", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX9_9", - "CMT_TOP_LH10_0", - "CMT_TOP_LH10_1", - "CMT_TOP_LH10_10", - "CMT_TOP_LH10_11", - "CMT_TOP_LH10_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_4", - "CMT_TOP_LH10_5", - "CMT_TOP_LH10_6", - "CMT_TOP_LH10_7", - "CMT_TOP_LH10_8", - "CMT_TOP_LH10_9", - "CMT_TOP_LH11_0", - "CMT_TOP_LH11_1", - "CMT_TOP_LH11_10", - "CMT_TOP_LH11_11", - "CMT_TOP_LH11_2", - "CMT_TOP_LH11_3", - "CMT_TOP_LH11_4", - "CMT_TOP_LH11_5", - "CMT_TOP_LH11_6", - "CMT_TOP_LH11_7", - "CMT_TOP_LH11_8", - "CMT_TOP_LH11_9", - "CMT_TOP_LH12_0", - "CMT_TOP_LH12_1", - "CMT_TOP_LH12_10", - "CMT_TOP_LH12_11", - "CMT_TOP_LH12_2", - "CMT_TOP_LH12_3", - "CMT_TOP_LH12_4", - "CMT_TOP_LH12_5", - "CMT_TOP_LH12_6", - "CMT_TOP_LH12_7", - "CMT_TOP_LH12_8", - "CMT_TOP_LH12_9", - "CMT_TOP_LH1_0", - "CMT_TOP_LH1_1", - "CMT_TOP_LH1_10", - "CMT_TOP_LH1_11", - "CMT_TOP_LH1_2", - "CMT_TOP_LH1_3", - "CMT_TOP_LH1_4", - "CMT_TOP_LH1_5", - "CMT_TOP_LH1_6", - "CMT_TOP_LH1_7", - "CMT_TOP_LH1_8", - "CMT_TOP_LH1_9", - "CMT_TOP_LH2_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH2_10", - "CMT_TOP_LH2_11", - "CMT_TOP_LH2_2", - "CMT_TOP_LH2_3", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_5", - "CMT_TOP_LH2_6", - "CMT_TOP_LH2_7", - "CMT_TOP_LH2_8", - "CMT_TOP_LH2_9", - "CMT_TOP_LH3_0", - "CMT_TOP_LH3_1", - "CMT_TOP_LH3_10", - "CMT_TOP_LH3_11", - "CMT_TOP_LH3_2", - "CMT_TOP_LH3_3", - "CMT_TOP_LH3_4", - "CMT_TOP_LH3_5", - "CMT_TOP_LH3_6", - "CMT_TOP_LH3_7", - "CMT_TOP_LH3_8", - "CMT_TOP_LH3_9", - "CMT_TOP_LH4_0", - "CMT_TOP_LH4_1", - "CMT_TOP_LH4_10", - "CMT_TOP_LH4_11", - "CMT_TOP_LH4_2", - "CMT_TOP_LH4_3", - "CMT_TOP_LH4_4", - "CMT_TOP_LH4_5", - "CMT_TOP_LH4_6", - "CMT_TOP_LH4_7", - "CMT_TOP_LH4_8", - "CMT_TOP_LH4_9", - "CMT_TOP_LH5_0", - "CMT_TOP_LH5_1", - "CMT_TOP_LH5_10", - "CMT_TOP_LH5_11", - "CMT_TOP_LH5_2", - "CMT_TOP_LH5_3", - "CMT_TOP_LH5_4", - "CMT_TOP_LH5_5", - "CMT_TOP_LH5_6", - "CMT_TOP_LH5_7", - "CMT_TOP_LH5_8", - "CMT_TOP_LH5_9", - "CMT_TOP_LH6_0", - "CMT_TOP_LH6_1", - "CMT_TOP_LH6_10", - "CMT_TOP_LH6_11", - "CMT_TOP_LH6_2", - "CMT_TOP_LH6_3", - "CMT_TOP_LH6_4", - "CMT_TOP_LH6_5", - "CMT_TOP_LH6_6", - "CMT_TOP_LH6_7", - "CMT_TOP_LH6_8", - "CMT_TOP_LH6_9", - "CMT_TOP_LH7_0", - "CMT_TOP_LH7_1", - "CMT_TOP_LH7_10", - "CMT_TOP_LH7_11", - "CMT_TOP_LH7_2", - "CMT_TOP_LH7_3", - "CMT_TOP_LH7_4", - "CMT_TOP_LH7_5", - "CMT_TOP_LH7_6", - "CMT_TOP_LH7_7", - "CMT_TOP_LH7_8", - "CMT_TOP_LH7_9", - "CMT_TOP_LH8_0", - "CMT_TOP_LH8_1", - "CMT_TOP_LH8_10", - "CMT_TOP_LH8_11", - "CMT_TOP_LH8_2", - "CMT_TOP_LH8_3", - "CMT_TOP_LH8_4", - "CMT_TOP_LH8_5", - "CMT_TOP_LH8_6", - "CMT_TOP_LH8_7", - "CMT_TOP_LH8_8", - "CMT_TOP_LH8_9", - "CMT_TOP_LH9_0", - "CMT_TOP_LH9_1", - "CMT_TOP_LH9_10", - "CMT_TOP_LH9_11", - "CMT_TOP_LH9_2", - "CMT_TOP_LH9_3", - "CMT_TOP_LH9_4", - "CMT_TOP_LH9_5", - "CMT_TOP_LH9_6", - "CMT_TOP_LH9_7", - "CMT_TOP_LH9_8", - "CMT_TOP_LH9_9", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LOGIC_OUTS_L_B13_10", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_MONITOR_N_9", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_NE2A0_0", - "CMT_TOP_NE2A0_1", - "CMT_TOP_NE2A0_10", - "CMT_TOP_NE2A0_11", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A0_4", - "CMT_TOP_NE2A0_5", - "CMT_TOP_NE2A0_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_NE2A0_8", - "CMT_TOP_NE2A0_9", - "CMT_TOP_NE2A1_0", - "CMT_TOP_NE2A1_1", - "CMT_TOP_NE2A1_10", - "CMT_TOP_NE2A1_11", - "CMT_TOP_NE2A1_2", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_NE2A1_5", - "CMT_TOP_NE2A1_6", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE2A1_8", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE2A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_NE2A2_10", - "CMT_TOP_NE2A2_11", - "CMT_TOP_NE2A2_2", - "CMT_TOP_NE2A2_3", - "CMT_TOP_NE2A2_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_NE2A2_6", - "CMT_TOP_NE2A2_7", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE2A2_9", - "CMT_TOP_NE2A3_0", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NE2A3_10", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NE2A3_2", - "CMT_TOP_NE2A3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NE2A3_6", - "CMT_TOP_NE2A3_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_NE4BEG0_10", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_NE4BEG2_11", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_NE4C0_0", - "CMT_TOP_NE4C0_1", - "CMT_TOP_NE4C0_10", - "CMT_TOP_NE4C0_11", - "CMT_TOP_NE4C0_2", - "CMT_TOP_NE4C0_3", - "CMT_TOP_NE4C0_4", - "CMT_TOP_NE4C0_5", - "CMT_TOP_NE4C0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_9", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_NE4C1_10", - "CMT_TOP_NE4C1_11", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NE4C1_3", - "CMT_TOP_NE4C1_4", - "CMT_TOP_NE4C1_5", - "CMT_TOP_NE4C1_6", - "CMT_TOP_NE4C1_7", - "CMT_TOP_NE4C1_8", - "CMT_TOP_NE4C1_9", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NE4C2_1", - "CMT_TOP_NE4C2_10", - "CMT_TOP_NE4C2_11", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE4C2_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NE4C2_6", - "CMT_TOP_NE4C2_7", - "CMT_TOP_NE4C2_8", - "CMT_TOP_NE4C2_9", - "CMT_TOP_NE4C3_0", - "CMT_TOP_NE4C3_1", - "CMT_TOP_NE4C3_10", - "CMT_TOP_NE4C3_11", - "CMT_TOP_NE4C3_2", - "CMT_TOP_NE4C3_3", - "CMT_TOP_NE4C3_4", - "CMT_TOP_NE4C3_5", - "CMT_TOP_NE4C3_6", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_NE4C3_9", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW2A0_1", - "CMT_TOP_NW2A0_10", - "CMT_TOP_NW2A0_11", - "CMT_TOP_NW2A0_2", - "CMT_TOP_NW2A0_3", - "CMT_TOP_NW2A0_4", - "CMT_TOP_NW2A0_5", - "CMT_TOP_NW2A0_6", - "CMT_TOP_NW2A0_7", - "CMT_TOP_NW2A0_8", - "CMT_TOP_NW2A0_9", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NW2A1_1", - "CMT_TOP_NW2A1_10", - "CMT_TOP_NW2A1_11", - "CMT_TOP_NW2A1_2", - "CMT_TOP_NW2A1_3", - "CMT_TOP_NW2A1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_NW2A1_6", - "CMT_TOP_NW2A1_7", - "CMT_TOP_NW2A1_8", - "CMT_TOP_NW2A1_9", - "CMT_TOP_NW2A2_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_NW2A2_10", - "CMT_TOP_NW2A2_11", - "CMT_TOP_NW2A2_2", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_4", - "CMT_TOP_NW2A2_5", - "CMT_TOP_NW2A2_6", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NW2A2_8", - "CMT_TOP_NW2A2_9", - "CMT_TOP_NW2A3_0", - "CMT_TOP_NW2A3_1", - "CMT_TOP_NW2A3_10", - "CMT_TOP_NW2A3_11", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NW2A3_3", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW2A3_5", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NW2A3_7", - "CMT_TOP_NW2A3_8", - "CMT_TOP_NW2A3_9", - "CMT_TOP_NW4A0_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_NW4A0_10", - "CMT_TOP_NW4A0_11", - "CMT_TOP_NW4A0_2", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A0_4", - "CMT_TOP_NW4A0_5", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NW4A0_7", - "CMT_TOP_NW4A0_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_NW4A1_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_NW4A1_10", - "CMT_TOP_NW4A1_11", - "CMT_TOP_NW4A1_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_NW4A1_4", - "CMT_TOP_NW4A1_5", - "CMT_TOP_NW4A1_6", - "CMT_TOP_NW4A1_7", - "CMT_TOP_NW4A1_8", - "CMT_TOP_NW4A1_9", - "CMT_TOP_NW4A2_0", - "CMT_TOP_NW4A2_1", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NW4A2_11", - "CMT_TOP_NW4A2_2", - "CMT_TOP_NW4A2_3", - "CMT_TOP_NW4A2_4", - "CMT_TOP_NW4A2_5", - "CMT_TOP_NW4A2_6", - "CMT_TOP_NW4A2_7", - "CMT_TOP_NW4A2_8", - "CMT_TOP_NW4A2_9", - "CMT_TOP_NW4A3_0", - "CMT_TOP_NW4A3_1", - "CMT_TOP_NW4A3_10", - "CMT_TOP_NW4A3_11", - "CMT_TOP_NW4A3_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NW4A3_6", - "CMT_TOP_NW4A3_7", - "CMT_TOP_NW4A3_8", - "CMT_TOP_NW4A3_9", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NW4END0_1", - "CMT_TOP_NW4END0_10", - "CMT_TOP_NW4END0_11", - "CMT_TOP_NW4END0_2", - "CMT_TOP_NW4END0_3", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END0_5", - "CMT_TOP_NW4END0_6", - "CMT_TOP_NW4END0_7", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NW4END0_9", - "CMT_TOP_NW4END1_0", - "CMT_TOP_NW4END1_1", - "CMT_TOP_NW4END1_10", - "CMT_TOP_NW4END1_11", - "CMT_TOP_NW4END1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_NW4END1_4", - "CMT_TOP_NW4END1_5", - "CMT_TOP_NW4END1_6", - "CMT_TOP_NW4END1_7", - "CMT_TOP_NW4END1_8", - "CMT_TOP_NW4END1_9", - "CMT_TOP_NW4END2_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END2_10", - "CMT_TOP_NW4END2_11", - "CMT_TOP_NW4END2_2", - "CMT_TOP_NW4END2_3", - "CMT_TOP_NW4END2_4", - "CMT_TOP_NW4END2_5", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NW4END2_8", - "CMT_TOP_NW4END2_9", - "CMT_TOP_NW4END3_0", - "CMT_TOP_NW4END3_1", - "CMT_TOP_NW4END3_10", - "CMT_TOP_NW4END3_11", - "CMT_TOP_NW4END3_2", - "CMT_TOP_NW4END3_3", - "CMT_TOP_NW4END3_4", - "CMT_TOP_NW4END3_5", - "CMT_TOP_NW4END3_6", - "CMT_TOP_NW4END3_7", - "CMT_TOP_NW4END3_8", - "CMT_TOP_NW4END3_9", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_OCLK1X_90_10", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_OCLK1X_90_9", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_OCLK_0", - "CMT_TOP_OCLK_1", - "CMT_TOP_OCLK_10", - "CMT_TOP_OCLK_11", - "CMT_TOP_OCLK_2", - "CMT_TOP_OCLK_3", - "CMT_TOP_OCLK_4", - "CMT_TOP_OCLK_5", - "CMT_TOP_OCLK_6", - "CMT_TOP_OCLK_7", - "CMT_TOP_OCLK_8", - "CMT_TOP_OCLK_9", - "CMT_TOP_SE2A0_0", - "CMT_TOP_SE2A0_1", - "CMT_TOP_SE2A0_10", - "CMT_TOP_SE2A0_11", - "CMT_TOP_SE2A0_2", - "CMT_TOP_SE2A0_3", - "CMT_TOP_SE2A0_4", - "CMT_TOP_SE2A0_5", - "CMT_TOP_SE2A0_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_SE2A0_9", - "CMT_TOP_SE2A1_0", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE2A1_10", - "CMT_TOP_SE2A1_11", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A1_3", - "CMT_TOP_SE2A1_4", - "CMT_TOP_SE2A1_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SE2A1_8", - "CMT_TOP_SE2A1_9", - "CMT_TOP_SE2A2_0", - "CMT_TOP_SE2A2_1", - "CMT_TOP_SE2A2_10", - "CMT_TOP_SE2A2_11", - "CMT_TOP_SE2A2_2", - "CMT_TOP_SE2A2_3", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SE2A2_5", - "CMT_TOP_SE2A2_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_SE2A2_8", - "CMT_TOP_SE2A2_9", - "CMT_TOP_SE2A3_0", - "CMT_TOP_SE2A3_1", - "CMT_TOP_SE2A3_10", - "CMT_TOP_SE2A3_11", - "CMT_TOP_SE2A3_2", - "CMT_TOP_SE2A3_3", - "CMT_TOP_SE2A3_4", - "CMT_TOP_SE2A3_5", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SE2A3_7", - "CMT_TOP_SE2A3_8", - "CMT_TOP_SE2A3_9", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_SE4BEG1_10", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_SE4BEG2_10", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_SE4C0_0", - "CMT_TOP_SE4C0_1", - "CMT_TOP_SE4C0_10", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE4C0_2", - "CMT_TOP_SE4C0_3", - "CMT_TOP_SE4C0_4", - "CMT_TOP_SE4C0_5", - "CMT_TOP_SE4C0_6", - "CMT_TOP_SE4C0_7", - "CMT_TOP_SE4C0_8", - "CMT_TOP_SE4C0_9", - "CMT_TOP_SE4C1_0", - "CMT_TOP_SE4C1_1", - "CMT_TOP_SE4C1_10", - "CMT_TOP_SE4C1_11", - "CMT_TOP_SE4C1_2", - "CMT_TOP_SE4C1_3", - "CMT_TOP_SE4C1_4", - "CMT_TOP_SE4C1_5", - "CMT_TOP_SE4C1_6", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE4C1_8", - "CMT_TOP_SE4C1_9", - "CMT_TOP_SE4C2_0", - "CMT_TOP_SE4C2_1", - "CMT_TOP_SE4C2_10", - "CMT_TOP_SE4C2_11", - "CMT_TOP_SE4C2_2", - "CMT_TOP_SE4C2_3", - "CMT_TOP_SE4C2_4", - "CMT_TOP_SE4C2_5", - "CMT_TOP_SE4C2_6", - "CMT_TOP_SE4C2_7", - "CMT_TOP_SE4C2_8", - "CMT_TOP_SE4C2_9", - "CMT_TOP_SE4C3_0", - "CMT_TOP_SE4C3_1", - "CMT_TOP_SE4C3_10", - "CMT_TOP_SE4C3_11", - "CMT_TOP_SE4C3_2", - "CMT_TOP_SE4C3_3", - "CMT_TOP_SE4C3_4", - "CMT_TOP_SE4C3_5", - "CMT_TOP_SE4C3_6", - "CMT_TOP_SE4C3_7", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SE4C3_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_SW2A0_1", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SW2A0_11", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW2A0_3", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW2A0_5", - "CMT_TOP_SW2A0_6", - "CMT_TOP_SW2A0_7", - "CMT_TOP_SW2A0_8", - "CMT_TOP_SW2A0_9", - "CMT_TOP_SW2A1_0", - "CMT_TOP_SW2A1_1", - "CMT_TOP_SW2A1_10", - "CMT_TOP_SW2A1_11", - "CMT_TOP_SW2A1_2", - "CMT_TOP_SW2A1_3", - "CMT_TOP_SW2A1_4", - "CMT_TOP_SW2A1_5", - "CMT_TOP_SW2A1_6", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW2A1_8", - "CMT_TOP_SW2A1_9", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW2A2_1", - "CMT_TOP_SW2A2_10", - "CMT_TOP_SW2A2_11", - "CMT_TOP_SW2A2_2", - "CMT_TOP_SW2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_SW2A2_5", - "CMT_TOP_SW2A2_6", - "CMT_TOP_SW2A2_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_SW2A2_9", - "CMT_TOP_SW2A3_0", - "CMT_TOP_SW2A3_1", - "CMT_TOP_SW2A3_10", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SW2A3_2", - "CMT_TOP_SW2A3_3", - "CMT_TOP_SW2A3_4", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW2A3_6", - "CMT_TOP_SW2A3_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SW2A3_9", - "CMT_TOP_SW4A0_0", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SW4A0_10", - "CMT_TOP_SW4A0_11", - "CMT_TOP_SW4A0_2", - "CMT_TOP_SW4A0_3", - "CMT_TOP_SW4A0_4", - "CMT_TOP_SW4A0_5", - "CMT_TOP_SW4A0_6", - "CMT_TOP_SW4A0_7", - "CMT_TOP_SW4A0_8", - "CMT_TOP_SW4A0_9", - "CMT_TOP_SW4A1_0", - "CMT_TOP_SW4A1_1", - "CMT_TOP_SW4A1_10", - "CMT_TOP_SW4A1_11", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW4A1_3", - "CMT_TOP_SW4A1_4", - "CMT_TOP_SW4A1_5", - "CMT_TOP_SW4A1_6", - "CMT_TOP_SW4A1_7", - "CMT_TOP_SW4A1_8", - "CMT_TOP_SW4A1_9", - "CMT_TOP_SW4A2_0", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SW4A2_10", - "CMT_TOP_SW4A2_11", - "CMT_TOP_SW4A2_2", - "CMT_TOP_SW4A2_3", - "CMT_TOP_SW4A2_4", - "CMT_TOP_SW4A2_5", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SW4A2_7", - "CMT_TOP_SW4A2_8", - "CMT_TOP_SW4A2_9", - "CMT_TOP_SW4A3_0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_SW4A3_10", - "CMT_TOP_SW4A3_11", - "CMT_TOP_SW4A3_2", - "CMT_TOP_SW4A3_3", - "CMT_TOP_SW4A3_4", - "CMT_TOP_SW4A3_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SW4A3_7", - "CMT_TOP_SW4A3_8", - "CMT_TOP_SW4A3_9", - "CMT_TOP_SW4END0_0", - "CMT_TOP_SW4END0_1", - "CMT_TOP_SW4END0_10", - "CMT_TOP_SW4END0_11", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SW4END0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_SW4END0_5", - "CMT_TOP_SW4END0_6", - "CMT_TOP_SW4END0_7", - "CMT_TOP_SW4END0_8", - "CMT_TOP_SW4END0_9", - "CMT_TOP_SW4END1_0", - "CMT_TOP_SW4END1_1", - "CMT_TOP_SW4END1_10", - "CMT_TOP_SW4END1_11", - "CMT_TOP_SW4END1_2", - "CMT_TOP_SW4END1_3", - "CMT_TOP_SW4END1_4", - "CMT_TOP_SW4END1_5", - "CMT_TOP_SW4END1_6", - "CMT_TOP_SW4END1_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_SW4END1_9", - "CMT_TOP_SW4END2_0", - "CMT_TOP_SW4END2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_SW4END2_11", - "CMT_TOP_SW4END2_2", - "CMT_TOP_SW4END2_3", - "CMT_TOP_SW4END2_4", - "CMT_TOP_SW4END2_5", - "CMT_TOP_SW4END2_6", - "CMT_TOP_SW4END2_7", - "CMT_TOP_SW4END2_8", - "CMT_TOP_SW4END2_9", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SW4END3_1", - "CMT_TOP_SW4END3_10", - "CMT_TOP_SW4END3_11", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_3", - "CMT_TOP_SW4END3_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SW4END3_6", - "CMT_TOP_SW4END3_7", - "CMT_TOP_SW4END3_8", - "CMT_TOP_SW4END3_9", - "CMT_TOP_WL1END0_0", - "CMT_TOP_WL1END0_1", - "CMT_TOP_WL1END0_10", - "CMT_TOP_WL1END0_11", - "CMT_TOP_WL1END0_2", - "CMT_TOP_WL1END0_3", - "CMT_TOP_WL1END0_4", - "CMT_TOP_WL1END0_5", - "CMT_TOP_WL1END0_6", - "CMT_TOP_WL1END0_7", - "CMT_TOP_WL1END0_8", - "CMT_TOP_WL1END0_9", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WL1END1_1", - "CMT_TOP_WL1END1_10", - "CMT_TOP_WL1END1_11", - "CMT_TOP_WL1END1_2", - "CMT_TOP_WL1END1_3", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_5", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WL1END1_7", - "CMT_TOP_WL1END1_8", - "CMT_TOP_WL1END1_9", - "CMT_TOP_WL1END2_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_WL1END2_10", - "CMT_TOP_WL1END2_11", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WL1END2_3", - "CMT_TOP_WL1END2_4", - "CMT_TOP_WL1END2_5", - "CMT_TOP_WL1END2_6", - "CMT_TOP_WL1END2_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_WL1END2_9", - "CMT_TOP_WL1END3_0", - "CMT_TOP_WL1END3_1", - "CMT_TOP_WL1END3_10", - "CMT_TOP_WL1END3_11", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WL1END3_3", - "CMT_TOP_WL1END3_4", - "CMT_TOP_WL1END3_5", - "CMT_TOP_WL1END3_6", - "CMT_TOP_WL1END3_7", - "CMT_TOP_WL1END3_8", - "CMT_TOP_WL1END3_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_WR1END0_1", - "CMT_TOP_WR1END0_10", - "CMT_TOP_WR1END0_11", - "CMT_TOP_WR1END0_2", - "CMT_TOP_WR1END0_3", - "CMT_TOP_WR1END0_4", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WR1END0_6", - "CMT_TOP_WR1END0_7", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WR1END1_0", - "CMT_TOP_WR1END1_1", - "CMT_TOP_WR1END1_10", - "CMT_TOP_WR1END1_11", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WR1END1_4", - "CMT_TOP_WR1END1_5", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END1_7", - "CMT_TOP_WR1END1_8", - "CMT_TOP_WR1END1_9", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WR1END2_10", - "CMT_TOP_WR1END2_11", - "CMT_TOP_WR1END2_2", - "CMT_TOP_WR1END2_3", - "CMT_TOP_WR1END2_4", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WR1END2_6", - "CMT_TOP_WR1END2_7", - "CMT_TOP_WR1END2_8", - "CMT_TOP_WR1END2_9", - "CMT_TOP_WR1END3_0", - "CMT_TOP_WR1END3_1", - "CMT_TOP_WR1END3_10", - "CMT_TOP_WR1END3_11", - "CMT_TOP_WR1END3_2", - "CMT_TOP_WR1END3_3", - "CMT_TOP_WR1END3_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_WR1END3_6", - "CMT_TOP_WR1END3_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_WR1END3_9", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW2A0_1", - "CMT_TOP_WW2A0_10", - "CMT_TOP_WW2A0_11", - "CMT_TOP_WW2A0_2", - "CMT_TOP_WW2A0_3", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2A0_5", - "CMT_TOP_WW2A0_6", - "CMT_TOP_WW2A0_7", - "CMT_TOP_WW2A0_8", - "CMT_TOP_WW2A0_9", - "CMT_TOP_WW2A1_0", - "CMT_TOP_WW2A1_1", - "CMT_TOP_WW2A1_10", - "CMT_TOP_WW2A1_11", - "CMT_TOP_WW2A1_2", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WW2A1_4", - "CMT_TOP_WW2A1_5", - "CMT_TOP_WW2A1_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_WW2A1_8", - "CMT_TOP_WW2A1_9", - "CMT_TOP_WW2A2_0", - "CMT_TOP_WW2A2_1", - "CMT_TOP_WW2A2_10", - "CMT_TOP_WW2A2_11", - "CMT_TOP_WW2A2_2", - "CMT_TOP_WW2A2_3", - "CMT_TOP_WW2A2_4", - "CMT_TOP_WW2A2_5", - "CMT_TOP_WW2A2_6", - "CMT_TOP_WW2A2_7", - "CMT_TOP_WW2A2_8", - "CMT_TOP_WW2A2_9", - "CMT_TOP_WW2A3_0", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW2A3_10", - "CMT_TOP_WW2A3_11", - "CMT_TOP_WW2A3_2", - "CMT_TOP_WW2A3_3", - "CMT_TOP_WW2A3_4", - "CMT_TOP_WW2A3_5", - "CMT_TOP_WW2A3_6", - "CMT_TOP_WW2A3_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_WW2A3_9", - "CMT_TOP_WW2END0_0", - "CMT_TOP_WW2END0_1", - "CMT_TOP_WW2END0_10", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW2END0_2", - "CMT_TOP_WW2END0_3", - "CMT_TOP_WW2END0_4", - "CMT_TOP_WW2END0_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_WW2END0_7", - "CMT_TOP_WW2END0_8", - "CMT_TOP_WW2END0_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_WW2END1_1", - "CMT_TOP_WW2END1_10", - "CMT_TOP_WW2END1_11", - "CMT_TOP_WW2END1_2", - "CMT_TOP_WW2END1_3", - "CMT_TOP_WW2END1_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WW2END1_7", - "CMT_TOP_WW2END1_8", - "CMT_TOP_WW2END1_9", - "CMT_TOP_WW2END2_0", - "CMT_TOP_WW2END2_1", - "CMT_TOP_WW2END2_10", - "CMT_TOP_WW2END2_11", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW2END2_3", - "CMT_TOP_WW2END2_4", - "CMT_TOP_WW2END2_5", - "CMT_TOP_WW2END2_6", - "CMT_TOP_WW2END2_7", - "CMT_TOP_WW2END2_8", - "CMT_TOP_WW2END2_9", - "CMT_TOP_WW2END3_0", - "CMT_TOP_WW2END3_1", - "CMT_TOP_WW2END3_10", - "CMT_TOP_WW2END3_11", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END3_3", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WW2END3_5", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END3_7", - "CMT_TOP_WW2END3_8", - "CMT_TOP_WW2END3_9", - "CMT_TOP_WW4A0_0", - "CMT_TOP_WW4A0_1", - "CMT_TOP_WW4A0_10", - "CMT_TOP_WW4A0_11", - "CMT_TOP_WW4A0_2", - "CMT_TOP_WW4A0_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_WW4A0_5", - "CMT_TOP_WW4A0_6", - "CMT_TOP_WW4A0_7", - "CMT_TOP_WW4A0_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4A1_1", - "CMT_TOP_WW4A1_10", - "CMT_TOP_WW4A1_11", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW4A1_3", - "CMT_TOP_WW4A1_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_WW4A1_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4A1_9", - "CMT_TOP_WW4A2_0", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4A2_10", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WW4A2_2", - "CMT_TOP_WW4A2_3", - "CMT_TOP_WW4A2_4", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW4A2_6", - "CMT_TOP_WW4A2_7", - "CMT_TOP_WW4A2_8", - "CMT_TOP_WW4A2_9", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW4A3_10", - "CMT_TOP_WW4A3_11", - "CMT_TOP_WW4A3_2", - "CMT_TOP_WW4A3_3", - "CMT_TOP_WW4A3_4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_WW4A3_6", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WW4A3_8", - "CMT_TOP_WW4A3_9", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4B0_10", - "CMT_TOP_WW4B0_11", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4B0_3", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4B0_5", - "CMT_TOP_WW4B0_6", - "CMT_TOP_WW4B0_7", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B0_9", - "CMT_TOP_WW4B1_0", - "CMT_TOP_WW4B1_1", - "CMT_TOP_WW4B1_10", - "CMT_TOP_WW4B1_11", - "CMT_TOP_WW4B1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_5", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4B1_7", - "CMT_TOP_WW4B1_8", - "CMT_TOP_WW4B1_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_WW4B2_1", - "CMT_TOP_WW4B2_10", - "CMT_TOP_WW4B2_11", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4B2_4", - "CMT_TOP_WW4B2_5", - "CMT_TOP_WW4B2_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_WW4B2_8", - "CMT_TOP_WW4B2_9", - "CMT_TOP_WW4B3_0", - "CMT_TOP_WW4B3_1", - "CMT_TOP_WW4B3_10", - "CMT_TOP_WW4B3_11", - "CMT_TOP_WW4B3_2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_WW4B3_4", - "CMT_TOP_WW4B3_5", - "CMT_TOP_WW4B3_6", - "CMT_TOP_WW4B3_7", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW4B3_9", - "CMT_TOP_WW4C0_0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_WW4C0_10", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4C0_2", - "CMT_TOP_WW4C0_3", - "CMT_TOP_WW4C0_4", - "CMT_TOP_WW4C0_5", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4C0_8", - "CMT_TOP_WW4C0_9", - "CMT_TOP_WW4C1_0", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C1_11", - "CMT_TOP_WW4C1_2", - "CMT_TOP_WW4C1_3", - "CMT_TOP_WW4C1_4", - "CMT_TOP_WW4C1_5", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4C1_7", - "CMT_TOP_WW4C1_8", - "CMT_TOP_WW4C1_9", - "CMT_TOP_WW4C2_0", - "CMT_TOP_WW4C2_1", - "CMT_TOP_WW4C2_10", - "CMT_TOP_WW4C2_11", - "CMT_TOP_WW4C2_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_WW4C2_4", - "CMT_TOP_WW4C2_5", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WW4C2_8", - "CMT_TOP_WW4C2_9", - "CMT_TOP_WW4C3_0", - "CMT_TOP_WW4C3_1", - "CMT_TOP_WW4C3_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_WW4C3_2", - "CMT_TOP_WW4C3_3", - "CMT_TOP_WW4C3_4", - "CMT_TOP_WW4C3_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW4C3_8", - "CMT_TOP_WW4C3_9", - "CMT_TOP_WW4END0_0", - "CMT_TOP_WW4END0_1", - "CMT_TOP_WW4END0_10", - "CMT_TOP_WW4END0_11", - "CMT_TOP_WW4END0_2", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_5", - "CMT_TOP_WW4END0_6", - "CMT_TOP_WW4END0_7", - "CMT_TOP_WW4END0_8", - "CMT_TOP_WW4END0_9", - "CMT_TOP_WW4END1_0", - "CMT_TOP_WW4END1_1", - "CMT_TOP_WW4END1_10", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WW4END1_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END1_6", - "CMT_TOP_WW4END1_7", - "CMT_TOP_WW4END1_8", - "CMT_TOP_WW4END1_9", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW4END2_1", - "CMT_TOP_WW4END2_10", - "CMT_TOP_WW4END2_11", - "CMT_TOP_WW4END2_2", - "CMT_TOP_WW4END2_3", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_WW4END2_7", - "CMT_TOP_WW4END2_8", - "CMT_TOP_WW4END2_9", - "CMT_TOP_WW4END3_0", - "CMT_TOP_WW4END3_1", - "CMT_TOP_WW4END3_10", - "CMT_TOP_WW4END3_11", - "CMT_TOP_WW4END3_2", - "CMT_TOP_WW4END3_3", - "CMT_TOP_WW4END3_4", - "CMT_TOP_WW4END3_5", - "CMT_TOP_WW4END3_6", - "CMT_TOP_WW4END3_7", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4END3_9", - "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "PLLOUT_CLK_FREQ_BB_REBUFIN3", - "PLLOUT_CLK_FREQ_BB_REBUFOUT0", - "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "PLLOUT_CLK_FREQ_BB_REBUFOUT3", - "PLL_CLK_FREQBB_REBUFOUT0", - "PLL_CLK_FREQBB_REBUFOUT1", - "PLL_CLK_FREQBB_REBUFOUT2", - "PLL_CLK_FREQBB_REBUFOUT3" - ] + "wires": { + "CMT_FREQ_BB_PREF_IN0": null, + "CMT_FREQ_BB_PREF_IN1": null, + "CMT_FREQ_BB_PREF_IN2": null, + "CMT_FREQ_BB_PREF_IN3": null, + "CMT_FREQ_PHASER_REFMUX_0": null, + "CMT_FREQ_PHASER_REFMUX_1": null, + "CMT_FREQ_PHASER_REFMUX_2": null, + "CMT_L_TOP_UPPER_B_CLKINT_2": null, + "CMT_L_TOP_UPPER_B_CLKINT_3": null, + "CMT_PHASERD_CTSBUS0": null, + "CMT_PHASERD_CTSBUS1": null, + "CMT_PHASERD_DQSBUS0": null, + "CMT_PHASERD_DQSBUS1": null, + "CMT_PHASERD_DTSBUS0": null, + "CMT_PHASERD_DTSBUS1": null, + "CMT_PHASERREF_PHASERIN_C": null, + "CMT_PHASERREF_PHASERIN_D": null, + "CMT_PHASERREF_PHASEROUT_C": null, + "CMT_PHASERREF_PHASEROUT_D": null, + "CMT_PHASERTOP_PHYCTLEMPTY": null, + "CMT_PHASERTOP_PHYCTLMSTREMPTY": null, + "CMT_PHASER_C_ICLKDIV_TOIOI": null, + "CMT_PHASER_C_ICLK_TOIOI": null, + "CMT_PHASER_C_OCLK90_TOIOI": null, + "CMT_PHASER_C_OCLKDIV_TOIOI": null, + "CMT_PHASER_C_OCLK_TOIOI": null, + "CMT_PHASER_IN_CA_BURSTPENDING": null, + "CMT_PHASER_IN_CA_BURSTPENDINGPHY": null, + "CMT_PHASER_IN_CA_COUNTERLOADEN": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL0": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL1": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL2": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL3": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL4": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL5": null, + "CMT_PHASER_IN_CA_COUNTERREADEN": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL0": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL1": null, + 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"CMT_PHASER_IN_CA_RANKSEL1": null, + "CMT_PHASER_IN_CA_RANKSELPHY0": null, + "CMT_PHASER_IN_CA_RANKSELPHY1": null, + "CMT_PHASER_IN_CA_RCLK": null, + "CMT_PHASER_IN_CA_RST": null, + "CMT_PHASER_IN_CA_RSTDQSFIND": null, + "CMT_PHASER_IN_CA_SCANCLK": null, + "CMT_PHASER_IN_CA_SCANENB": null, + "CMT_PHASER_IN_CA_SCANIN": null, + "CMT_PHASER_IN_CA_SCANMODEB": null, + "CMT_PHASER_IN_CA_SCANOUT": null, + "CMT_PHASER_IN_CA_SELCALORSTG1": null, + "CMT_PHASER_IN_CA_STG1INCDEC": null, + "CMT_PHASER_IN_CA_STG1LOAD": null, + "CMT_PHASER_IN_CA_STG1OVERFLOW": null, + "CMT_PHASER_IN_CA_STG1READ": null, + "CMT_PHASER_IN_CA_STG1REGL0": null, + "CMT_PHASER_IN_CA_STG1REGL1": null, + "CMT_PHASER_IN_CA_STG1REGL2": null, + "CMT_PHASER_IN_CA_STG1REGL3": null, + "CMT_PHASER_IN_CA_STG1REGL4": null, + "CMT_PHASER_IN_CA_STG1REGL5": null, + "CMT_PHASER_IN_CA_STG1REGL6": null, + "CMT_PHASER_IN_CA_STG1REGL7": null, + "CMT_PHASER_IN_CA_STG1REGL8": null, + "CMT_PHASER_IN_CA_STG1REGR0": null, + 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"CMT_PHASER_OUT_CA_COUNTERREADVAL7": null, + "CMT_PHASER_OUT_CA_COUNTERREADVAL8": null, + "CMT_PHASER_OUT_CA_CTSBUS0": null, + "CMT_PHASER_OUT_CA_CTSBUS1": null, + "CMT_PHASER_OUT_CA_DIVIDERST": null, + "CMT_PHASER_OUT_CA_DQSBUS0": null, + "CMT_PHASER_OUT_CA_DQSBUS1": null, + "CMT_PHASER_OUT_CA_DTSBUS0": null, + "CMT_PHASER_OUT_CA_DTSBUS1": null, + "CMT_PHASER_OUT_CA_EDGEADV": null, + "CMT_PHASER_OUT_CA_ENCALIB0": null, + "CMT_PHASER_OUT_CA_ENCALIB1": null, + "CMT_PHASER_OUT_CA_ENCALIBPHY0": null, + "CMT_PHASER_OUT_CA_ENCALIBPHY1": null, + "CMT_PHASER_OUT_CA_FINEENABLE": null, + "CMT_PHASER_OUT_CA_FINEINC": null, + "CMT_PHASER_OUT_CA_FINEOVERFLOW": null, + "CMT_PHASER_OUT_CA_FREQREFCLK": null, + "CMT_PHASER_OUT_CA_MEMREFCLK": null, + "CMT_PHASER_OUT_CA_OCLK": null, + "CMT_PHASER_OUT_CA_OCLKDELAYED": null, + "CMT_PHASER_OUT_CA_OCLKDIV": null, + "CMT_PHASER_OUT_CA_OSERDESRST": null, + "CMT_PHASER_OUT_CA_PHASEREFCLK": null, + "CMT_PHASER_OUT_CA_RDENABLE": null, + "CMT_PHASER_OUT_CA_RST": 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"CMT_PHASER_OUT_DB_COUNTERREADVAL2": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL3": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL4": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL5": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL6": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL7": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL8": null, + "CMT_PHASER_OUT_DB_CTSBUS0": null, + "CMT_PHASER_OUT_DB_CTSBUS1": null, + "CMT_PHASER_OUT_DB_DIVIDERST": null, + "CMT_PHASER_OUT_DB_DQSBUS0": null, + "CMT_PHASER_OUT_DB_DQSBUS1": null, + "CMT_PHASER_OUT_DB_DTSBUS0": null, + "CMT_PHASER_OUT_DB_DTSBUS1": null, + "CMT_PHASER_OUT_DB_EDGEADV": null, + "CMT_PHASER_OUT_DB_ENCALIB0": null, + "CMT_PHASER_OUT_DB_ENCALIB1": null, + "CMT_PHASER_OUT_DB_ENCALIBPHY0": null, + "CMT_PHASER_OUT_DB_ENCALIBPHY1": null, + "CMT_PHASER_OUT_DB_FINEENABLE": null, + "CMT_PHASER_OUT_DB_FINEINC": null, + "CMT_PHASER_OUT_DB_FINEOVERFLOW": null, + "CMT_PHASER_OUT_DB_FREQREFCLK": null, + "CMT_PHASER_OUT_DB_MEMREFCLK": null, + "CMT_PHASER_OUT_DB_OCLK": null, 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"CMT_PHASER_OUT_DB_TESTIN6": null, + "CMT_PHASER_OUT_DB_TESTIN7": null, + "CMT_PHASER_OUT_DB_TESTIN8": null, + "CMT_PHASER_OUT_DB_TESTIN9": null, + "CMT_PHASER_OUT_DB_TESTOUT0": null, + "CMT_PHASER_OUT_DB_TESTOUT1": null, + "CMT_PHASER_OUT_DB_TESTOUT2": null, + "CMT_PHASER_OUT_DB_TESTOUT3": null, + "CMT_PHASER_OUT_D_OCLK": null, + "CMT_PHASER_OUT_D_OCLK1X_90": null, + "CMT_PHASER_OUT_D_OCLKDIV": null, + "CMT_PHASER_REF_CLKIN": null, + "CMT_PHASER_REF_CLKOUT": null, + "CMT_PHASER_REF_CLKOUT_TOHCLK": null, + "CMT_PHASER_REF_LOCKED": null, + "CMT_PHASER_REF_PWRDWN": null, + "CMT_PHASER_REF_RST": null, + "CMT_PHASER_REF_TESTIN0": null, + "CMT_PHASER_REF_TESTIN1": null, + "CMT_PHASER_REF_TESTIN2": null, + "CMT_PHASER_REF_TESTIN3": null, + "CMT_PHASER_REF_TESTIN4": null, + "CMT_PHASER_REF_TESTIN5": null, + "CMT_PHASER_REF_TESTIN6": null, + "CMT_PHASER_REF_TESTIN7": null, + "CMT_PHASER_REF_TESTOUT0": null, + "CMT_PHASER_REF_TESTOUT1": null, + "CMT_PHASER_REF_TESTOUT2": null, + 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{ + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_4": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_5": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_6": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_7": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_8": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_9": { + "cap": "18.000", + "res": "317.510" + }, + "PLLOUT_CLK_FREQ_BB_REBUFIN0": null, + "PLLOUT_CLK_FREQ_BB_REBUFIN1": null, + "PLLOUT_CLK_FREQ_BB_REBUFIN2": null, + "PLLOUT_CLK_FREQ_BB_REBUFIN3": null, + "PLLOUT_CLK_FREQ_BB_REBUFOUT0": null, + "PLLOUT_CLK_FREQ_BB_REBUFOUT1": null, + "PLLOUT_CLK_FREQ_BB_REBUFOUT2": null, + "PLLOUT_CLK_FREQ_BB_REBUFOUT3": null, + "PLL_CLK_FREQBB_REBUFOUT0": null, + "PLL_CLK_FREQBB_REBUFOUT1": null, + "PLL_CLK_FREQBB_REBUFOUT2": null, + "PLL_CLK_FREQBB_REBUFOUT3": null + } } diff --git a/zynq7/tile_type_CMT_TOP_L_UPPER_T.json b/zynq7/tile_type_CMT_TOP_L_UPPER_T.json index 3a35ee0..df9d870 100644 --- a/zynq7/tile_type_CMT_TOP_L_UPPER_T.json +++ b/zynq7/tile_type_CMT_TOP_L_UPPER_T.json @@ -2,1087 +2,4262 @@ "pips": { "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.093", + "0.107", + "0.221", + "0.255" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_ICLKDIV_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.093", + "0.107", + "0.221", + "0.255" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI" }, "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.093", + "0.107", + "0.221", + "0.255" + ], + "in_cap": "0.000", + "res": "0.0" + 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"CMT_TOP_R_UPPER_T_PLLE2_DO15" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO2->>CMT_TOP_LOGIC_OUTS_L_B21_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO2" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO3->>CMT_TOP_LOGIC_OUTS_L_B15_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO3" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO4->>CMT_TOP_LOGIC_OUTS_L_B20_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO4" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO5->>CMT_TOP_LOGIC_OUTS_L_B2_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO5" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO6->>CMT_TOP_LOGIC_OUTS_L_B16_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO6" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO7->>CMT_TOP_LOGIC_OUTS_L_B10_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO7" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO8->>CMT_TOP_LOGIC_OUTS_L_B19_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO8" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO9->>CMT_TOP_LOGIC_OUTS_L_B5_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO9" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DRDY" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B21_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT->>CMT_TOP_L_UPPER_T_CLKPLL7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS->>CMT_TOP_L_UPPER_T_FREQ_BB0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQ_BB0_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS0", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLL_CLK_FREQ_BB0_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS->>CMT_TOP_L_UPPER_T_FREQ_BB1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQ_BB1_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS1", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLL_CLK_FREQ_BB1_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS->>CMT_TOP_L_UPPER_T_FREQ_BB2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQ_BB2_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS2", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLL_CLK_FREQ_BB2_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS->>CMT_TOP_L_UPPER_T_FREQ_BB3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQ_BB3_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS3", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLL_CLK_FREQ_BB3_NS" } }, @@ -1091,160 +4266,1546 @@ "name": "X0Y0", "prefix": "PLLE2_ADV", "site_pins": { - "CLKFBIN": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "CLKFBOUT": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "CLKIN1": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "CLKIN2": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "CLKINSEL": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", - "CLKOUT0": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "CLKOUT1": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "CLKOUT2": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "CLKOUT3": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "CLKOUT4": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", - "CLKOUT5": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", - "DADDR0": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", - "DADDR1": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", - "DADDR2": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", - "DADDR3": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", - "DADDR4": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", - "DADDR5": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", - "DADDR6": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", - "DCLK": "CMT_TOP_R_UPPER_T_PLLE2_DCLK", - "DEN": "CMT_TOP_R_UPPER_T_PLLE2_DEN", - "DI0": "CMT_TOP_R_UPPER_T_PLLE2_DI0", - "DI1": "CMT_TOP_R_UPPER_T_PLLE2_DI1", - "DI10": "CMT_TOP_R_UPPER_T_PLLE2_DI10", - "DI11": "CMT_TOP_R_UPPER_T_PLLE2_DI11", - "DI12": "CMT_TOP_R_UPPER_T_PLLE2_DI12", - "DI13": "CMT_TOP_R_UPPER_T_PLLE2_DI13", - "DI14": "CMT_TOP_R_UPPER_T_PLLE2_DI14", - "DI15": "CMT_TOP_R_UPPER_T_PLLE2_DI15", - "DI2": "CMT_TOP_R_UPPER_T_PLLE2_DI2", - "DI3": "CMT_TOP_R_UPPER_T_PLLE2_DI3", - "DI4": "CMT_TOP_R_UPPER_T_PLLE2_DI4", - "DI5": "CMT_TOP_R_UPPER_T_PLLE2_DI5", - "DI6": "CMT_TOP_R_UPPER_T_PLLE2_DI6", - "DI7": "CMT_TOP_R_UPPER_T_PLLE2_DI7", - "DI8": "CMT_TOP_R_UPPER_T_PLLE2_DI8", - "DI9": "CMT_TOP_R_UPPER_T_PLLE2_DI9", - "DO0": "CMT_TOP_R_UPPER_T_PLLE2_DO0", - "DO1": "CMT_TOP_R_UPPER_T_PLLE2_DO1", - "DO10": "CMT_TOP_R_UPPER_T_PLLE2_DO10", - "DO11": "CMT_TOP_R_UPPER_T_PLLE2_DO11", - "DO12": "CMT_TOP_R_UPPER_T_PLLE2_DO12", - "DO13": "CMT_TOP_R_UPPER_T_PLLE2_DO13", - "DO14": "CMT_TOP_R_UPPER_T_PLLE2_DO14", - "DO15": "CMT_TOP_R_UPPER_T_PLLE2_DO15", - "DO2": "CMT_TOP_R_UPPER_T_PLLE2_DO2", - "DO3": "CMT_TOP_R_UPPER_T_PLLE2_DO3", - "DO4": "CMT_TOP_R_UPPER_T_PLLE2_DO4", - "DO5": "CMT_TOP_R_UPPER_T_PLLE2_DO5", - "DO6": "CMT_TOP_R_UPPER_T_PLLE2_DO6", - "DO7": "CMT_TOP_R_UPPER_T_PLLE2_DO7", - "DO8": "CMT_TOP_R_UPPER_T_PLLE2_DO8", - "DO9": "CMT_TOP_R_UPPER_T_PLLE2_DO9", - "DRDY": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", - "DWE": "CMT_TOP_R_UPPER_T_PLLE2_DWE", - "LOCKED": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", - "PWRDWN": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", - "RST": "CMT_TOP_R_UPPER_T_PLLE2_RST", - "TESTIN0": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", - "TESTIN1": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", - "TESTIN10": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", - "TESTIN11": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", - "TESTIN12": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", - "TESTIN13": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", - "TESTIN14": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", - "TESTIN15": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", - "TESTIN16": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", - "TESTIN17": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", - "TESTIN18": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", - "TESTIN19": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", - "TESTIN2": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", - "TESTIN20": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", - "TESTIN21": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", - "TESTIN22": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", - "TESTIN23": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", - "TESTIN24": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", - "TESTIN25": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", - "TESTIN26": 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"TESTOUT9": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9" + }, + "TMUXOUT": { + "delay": [ + "0.005", + "0.005", + "0.013", + "0.014" + ], + "res": "0.9831249999999999", + "wire": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT" + } }, "type": "PLLE2_ADV", "x_coord": 0, @@ -1252,3171 +5813,9879 @@ } ], "tile_type": "CMT_TOP_L_UPPER_T", - "wires": [ - "CMT_PHASER_D_ICLKDIV_TOIOI", - "CMT_PHASER_D_ICLK_TOIOI", - "CMT_PHASER_D_OCLK90_TOIOI", - "CMT_PHASER_D_OCLKDIV_TOIOI", - "CMT_PHASER_D_OCLK_TOIOI", - "CMT_PLL_DQS_TO_PHASER_D", - "CMT_PLL_PHASERD_CTSBUS0", - "CMT_PLL_PHASERD_CTSBUS1", - "CMT_PLL_PHASERD_DQSBUS0", - "CMT_PLL_PHASERD_DQSBUS1", - "CMT_PLL_PHASERD_DTSBUS0", - "CMT_PLL_PHASERD_DTSBUS1", - "CMT_PLL_PHASERREF0", - "CMT_PLL_PHASERREF1", - "CMT_PLL_PHASERREF_ABOVE0", - "CMT_PLL_PHASERREF_ABOVE1", - "CMT_PLL_PHASERREF_BELOW0", - "CMT_PLL_PHASERREF_BELOW1", - "CMT_PLL_PHASER_IN_D_ICLK", - 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"CMT_TOP_BYP0_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_BYP0_11", - "CMT_TOP_BYP0_12", - "CMT_TOP_BYP0_2", - "CMT_TOP_BYP0_3", - "CMT_TOP_BYP0_4", - "CMT_TOP_BYP0_5", - "CMT_TOP_BYP0_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_BYP0_8", - "CMT_TOP_BYP0_9", - "CMT_TOP_BYP1_0", - "CMT_TOP_BYP1_1", - "CMT_TOP_BYP1_10", - "CMT_TOP_BYP1_11", - "CMT_TOP_BYP1_12", - "CMT_TOP_BYP1_2", - "CMT_TOP_BYP1_3", - "CMT_TOP_BYP1_4", - "CMT_TOP_BYP1_5", - "CMT_TOP_BYP1_6", - "CMT_TOP_BYP1_7", - "CMT_TOP_BYP1_8", - "CMT_TOP_BYP1_9", - "CMT_TOP_BYP2_0", - "CMT_TOP_BYP2_1", - "CMT_TOP_BYP2_10", - "CMT_TOP_BYP2_11", - "CMT_TOP_BYP2_12", - "CMT_TOP_BYP2_2", - "CMT_TOP_BYP2_3", - "CMT_TOP_BYP2_4", - "CMT_TOP_BYP2_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_BYP3_0", - "CMT_TOP_BYP3_1", - "CMT_TOP_BYP3_10", - "CMT_TOP_BYP3_11", - "CMT_TOP_BYP3_12", - "CMT_TOP_BYP3_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_BYP3_4", - "CMT_TOP_BYP3_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_BYP3_8", - "CMT_TOP_BYP3_9", - "CMT_TOP_BYP4_0", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP4_10", - "CMT_TOP_BYP4_11", - "CMT_TOP_BYP4_12", - "CMT_TOP_BYP4_2", - "CMT_TOP_BYP4_3", - "CMT_TOP_BYP4_4", - "CMT_TOP_BYP4_5", - "CMT_TOP_BYP4_6", - "CMT_TOP_BYP4_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_BYP4_9", - "CMT_TOP_BYP5_0", - "CMT_TOP_BYP5_1", - "CMT_TOP_BYP5_10", - "CMT_TOP_BYP5_11", - "CMT_TOP_BYP5_12", - "CMT_TOP_BYP5_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_BYP5_4", - "CMT_TOP_BYP5_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_BYP5_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_BYP5_9", - "CMT_TOP_BYP6_0", - "CMT_TOP_BYP6_1", - "CMT_TOP_BYP6_10", - "CMT_TOP_BYP6_11", - "CMT_TOP_BYP6_12", - "CMT_TOP_BYP6_2", - "CMT_TOP_BYP6_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_BYP6_5", - "CMT_TOP_BYP6_6", - "CMT_TOP_BYP6_7", - "CMT_TOP_BYP6_8", - "CMT_TOP_BYP6_9", - "CMT_TOP_BYP7_0", - "CMT_TOP_BYP7_1", - "CMT_TOP_BYP7_10", - "CMT_TOP_BYP7_11", - "CMT_TOP_BYP7_12", - "CMT_TOP_BYP7_2", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP7_4", - "CMT_TOP_BYP7_5", - "CMT_TOP_BYP7_6", - "CMT_TOP_BYP7_7", - "CMT_TOP_BYP7_8", - "CMT_TOP_BYP7_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_CLK0_1", - "CMT_TOP_CLK0_10", - "CMT_TOP_CLK0_11", - "CMT_TOP_CLK0_12", - "CMT_TOP_CLK0_2", - "CMT_TOP_CLK0_3", - "CMT_TOP_CLK0_4", - "CMT_TOP_CLK0_5", - "CMT_TOP_CLK0_6", - "CMT_TOP_CLK0_7", - "CMT_TOP_CLK0_8", - "CMT_TOP_CLK0_9", - "CMT_TOP_CLK1_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_CLK1_10", - "CMT_TOP_CLK1_11", - "CMT_TOP_CLK1_12", - "CMT_TOP_CLK1_2", - "CMT_TOP_CLK1_3", - "CMT_TOP_CLK1_4", - "CMT_TOP_CLK1_5", - "CMT_TOP_CLK1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_CLK1_8", - "CMT_TOP_CLK1_9", - "CMT_TOP_CTRL0_0", - "CMT_TOP_CTRL0_1", - "CMT_TOP_CTRL0_10", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CTRL0_12", - "CMT_TOP_CTRL0_2", - "CMT_TOP_CTRL0_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_CTRL0_5", - "CMT_TOP_CTRL0_6", - "CMT_TOP_CTRL0_7", - "CMT_TOP_CTRL0_8", - "CMT_TOP_CTRL0_9", - "CMT_TOP_CTRL1_0", - "CMT_TOP_CTRL1_1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_CTRL1_11", - "CMT_TOP_CTRL1_12", - "CMT_TOP_CTRL1_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_CTRL1_4", - "CMT_TOP_CTRL1_5", - "CMT_TOP_CTRL1_6", - "CMT_TOP_CTRL1_7", - "CMT_TOP_CTRL1_8", - "CMT_TOP_CTRL1_9", - "CMT_TOP_EE2A0_0", - "CMT_TOP_EE2A0_1", - "CMT_TOP_EE2A0_10", - "CMT_TOP_EE2A0_11", - "CMT_TOP_EE2A0_12", - "CMT_TOP_EE2A0_2", - "CMT_TOP_EE2A0_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_EE2A0_6", - "CMT_TOP_EE2A0_7", - "CMT_TOP_EE2A0_8", - "CMT_TOP_EE2A0_9", - "CMT_TOP_EE2A1_0", - "CMT_TOP_EE2A1_1", - "CMT_TOP_EE2A1_10", - "CMT_TOP_EE2A1_11", - "CMT_TOP_EE2A1_12", - "CMT_TOP_EE2A1_2", - "CMT_TOP_EE2A1_3", - "CMT_TOP_EE2A1_4", - "CMT_TOP_EE2A1_5", - "CMT_TOP_EE2A1_6", - "CMT_TOP_EE2A1_7", - "CMT_TOP_EE2A1_8", - "CMT_TOP_EE2A1_9", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_1", - "CMT_TOP_EE2A2_10", - "CMT_TOP_EE2A2_11", - "CMT_TOP_EE2A2_12", - "CMT_TOP_EE2A2_2", - "CMT_TOP_EE2A2_3", - "CMT_TOP_EE2A2_4", - "CMT_TOP_EE2A2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_EE2A2_7", - "CMT_TOP_EE2A2_8", - "CMT_TOP_EE2A2_9", - "CMT_TOP_EE2A3_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_EE2A3_10", - "CMT_TOP_EE2A3_11", - "CMT_TOP_EE2A3_12", - "CMT_TOP_EE2A3_2", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2A3_4", - "CMT_TOP_EE2A3_5", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE2A3_8", - "CMT_TOP_EE2A3_9", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_EE2BEG0_11", - "CMT_TOP_EE2BEG0_12", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_EE2BEG0_9", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_EE2BEG1_12", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE2BEG2_12", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_EE2BEG3_12", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE2BEG3_9", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_EE4A0_10", - "CMT_TOP_EE4A0_11", - "CMT_TOP_EE4A0_12", - "CMT_TOP_EE4A0_2", - "CMT_TOP_EE4A0_3", - "CMT_TOP_EE4A0_4", - "CMT_TOP_EE4A0_5", - "CMT_TOP_EE4A0_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4A0_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_EE4A1_1", - "CMT_TOP_EE4A1_10", - "CMT_TOP_EE4A1_11", - "CMT_TOP_EE4A1_12", - "CMT_TOP_EE4A1_2", - "CMT_TOP_EE4A1_3", - "CMT_TOP_EE4A1_4", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4A1_8", - "CMT_TOP_EE4A1_9", - "CMT_TOP_EE4A2_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_EE4A2_10", - "CMT_TOP_EE4A2_11", - "CMT_TOP_EE4A2_12", - "CMT_TOP_EE4A2_2", - "CMT_TOP_EE4A2_3", - "CMT_TOP_EE4A2_4", - "CMT_TOP_EE4A2_5", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE4A2_7", - "CMT_TOP_EE4A2_8", - "CMT_TOP_EE4A2_9", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4A3_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_EE4A3_11", - "CMT_TOP_EE4A3_12", - "CMT_TOP_EE4A3_2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_EE4A3_5", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE4A3_7", - "CMT_TOP_EE4A3_8", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EE4B0_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_EE4B0_10", - "CMT_TOP_EE4B0_11", - "CMT_TOP_EE4B0_12", - "CMT_TOP_EE4B0_2", - "CMT_TOP_EE4B0_3", - "CMT_TOP_EE4B0_4", - "CMT_TOP_EE4B0_5", - "CMT_TOP_EE4B0_6", - "CMT_TOP_EE4B0_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_EE4B0_9", - "CMT_TOP_EE4B1_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_EE4B1_10", - "CMT_TOP_EE4B1_11", - "CMT_TOP_EE4B1_12", - "CMT_TOP_EE4B1_2", - "CMT_TOP_EE4B1_3", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4B1_8", - "CMT_TOP_EE4B1_9", - "CMT_TOP_EE4B2_0", - "CMT_TOP_EE4B2_1", - "CMT_TOP_EE4B2_10", - "CMT_TOP_EE4B2_11", - "CMT_TOP_EE4B2_12", - "CMT_TOP_EE4B2_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4B2_5", - "CMT_TOP_EE4B2_6", - "CMT_TOP_EE4B2_7", - "CMT_TOP_EE4B2_8", - "CMT_TOP_EE4B2_9", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE4B3_10", - "CMT_TOP_EE4B3_11", - "CMT_TOP_EE4B3_12", - "CMT_TOP_EE4B3_2", - "CMT_TOP_EE4B3_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_EE4B3_5", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EE4B3_7", - "CMT_TOP_EE4B3_8", - "CMT_TOP_EE4B3_9", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_EE4BEG0_11", - "CMT_TOP_EE4BEG0_12", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_EE4BEG1_12", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_EE4BEG1_9", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_EE4BEG2_10", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_EE4BEG2_12", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_EE4BEG3_12", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_EE4C0_0", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4C0_10", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EE4C0_12", - "CMT_TOP_EE4C0_2", - "CMT_TOP_EE4C0_3", - "CMT_TOP_EE4C0_4", - "CMT_TOP_EE4C0_5", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4C0_7", - "CMT_TOP_EE4C0_8", - "CMT_TOP_EE4C0_9", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4C1_1", - "CMT_TOP_EE4C1_10", - "CMT_TOP_EE4C1_11", - "CMT_TOP_EE4C1_12", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE4C1_3", - "CMT_TOP_EE4C1_4", - "CMT_TOP_EE4C1_5", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_7", - "CMT_TOP_EE4C1_8", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4C2_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_EE4C2_10", - "CMT_TOP_EE4C2_11", - "CMT_TOP_EE4C2_12", - "CMT_TOP_EE4C2_2", - "CMT_TOP_EE4C2_3", - "CMT_TOP_EE4C2_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EE4C2_7", - "CMT_TOP_EE4C2_8", - "CMT_TOP_EE4C2_9", - "CMT_TOP_EE4C3_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_EE4C3_10", - "CMT_TOP_EE4C3_11", - "CMT_TOP_EE4C3_12", - "CMT_TOP_EE4C3_2", - "CMT_TOP_EE4C3_3", - "CMT_TOP_EE4C3_4", - "CMT_TOP_EE4C3_5", - "CMT_TOP_EE4C3_6", - "CMT_TOP_EE4C3_7", - "CMT_TOP_EE4C3_8", - "CMT_TOP_EE4C3_9", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_EL1BEG0_12", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EL1BEG1_10", - "CMT_TOP_EL1BEG1_11", - "CMT_TOP_EL1BEG1_12", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_EL1BEG1_9", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_EL1BEG2_12", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_EL1BEG3_12", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_ER1BEG0_12", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_ER1BEG1_10", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_ER1BEG1_12", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_ER1BEG2_10", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_ER1BEG2_12", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_ER1BEG3_12", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_FAN0_0", - "CMT_TOP_FAN0_1", - "CMT_TOP_FAN0_10", - "CMT_TOP_FAN0_11", - "CMT_TOP_FAN0_12", - "CMT_TOP_FAN0_2", - "CMT_TOP_FAN0_3", - "CMT_TOP_FAN0_4", - "CMT_TOP_FAN0_5", - "CMT_TOP_FAN0_6", - "CMT_TOP_FAN0_7", - "CMT_TOP_FAN0_8", - "CMT_TOP_FAN0_9", - "CMT_TOP_FAN1_0", - "CMT_TOP_FAN1_1", - "CMT_TOP_FAN1_10", - "CMT_TOP_FAN1_11", - "CMT_TOP_FAN1_12", - "CMT_TOP_FAN1_2", - "CMT_TOP_FAN1_3", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_5", - "CMT_TOP_FAN1_6", - "CMT_TOP_FAN1_7", - "CMT_TOP_FAN1_8", - "CMT_TOP_FAN1_9", - "CMT_TOP_FAN2_0", - "CMT_TOP_FAN2_1", - "CMT_TOP_FAN2_10", - "CMT_TOP_FAN2_11", - "CMT_TOP_FAN2_12", - "CMT_TOP_FAN2_2", - "CMT_TOP_FAN2_3", - "CMT_TOP_FAN2_4", - "CMT_TOP_FAN2_5", - "CMT_TOP_FAN2_6", - "CMT_TOP_FAN2_7", - "CMT_TOP_FAN2_8", - "CMT_TOP_FAN2_9", - "CMT_TOP_FAN3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_FAN3_10", - "CMT_TOP_FAN3_11", - "CMT_TOP_FAN3_12", - "CMT_TOP_FAN3_2", - "CMT_TOP_FAN3_3", - "CMT_TOP_FAN3_4", - "CMT_TOP_FAN3_5", - "CMT_TOP_FAN3_6", - "CMT_TOP_FAN3_7", - "CMT_TOP_FAN3_8", - "CMT_TOP_FAN3_9", - "CMT_TOP_FAN4_0", - "CMT_TOP_FAN4_1", - "CMT_TOP_FAN4_10", - "CMT_TOP_FAN4_11", - "CMT_TOP_FAN4_12", - "CMT_TOP_FAN4_2", - "CMT_TOP_FAN4_3", - "CMT_TOP_FAN4_4", - "CMT_TOP_FAN4_5", - "CMT_TOP_FAN4_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_FAN4_8", - "CMT_TOP_FAN4_9", - "CMT_TOP_FAN5_0", - "CMT_TOP_FAN5_1", - "CMT_TOP_FAN5_10", - "CMT_TOP_FAN5_11", - "CMT_TOP_FAN5_12", - "CMT_TOP_FAN5_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_FAN5_5", - "CMT_TOP_FAN5_6", - "CMT_TOP_FAN5_7", - "CMT_TOP_FAN5_8", - "CMT_TOP_FAN5_9", - "CMT_TOP_FAN6_0", - "CMT_TOP_FAN6_1", - "CMT_TOP_FAN6_10", - "CMT_TOP_FAN6_11", - "CMT_TOP_FAN6_12", - "CMT_TOP_FAN6_2", - "CMT_TOP_FAN6_3", - "CMT_TOP_FAN6_4", - "CMT_TOP_FAN6_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_FAN6_7", - "CMT_TOP_FAN6_8", - "CMT_TOP_FAN6_9", - "CMT_TOP_FAN7_0", - "CMT_TOP_FAN7_1", - "CMT_TOP_FAN7_10", - "CMT_TOP_FAN7_11", - "CMT_TOP_FAN7_12", - "CMT_TOP_FAN7_2", - "CMT_TOP_FAN7_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_FAN7_5", - "CMT_TOP_FAN7_6", - "CMT_TOP_FAN7_7", - "CMT_TOP_FAN7_8", - "CMT_TOP_FAN7_9", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_ICLKDIV_10", - "CMT_TOP_ICLKDIV_11", - "CMT_TOP_ICLKDIV_12", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ICLKDIV_9", - "CMT_TOP_ICLK_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_ICLK_10", - "CMT_TOP_ICLK_11", - "CMT_TOP_ICLK_12", - "CMT_TOP_ICLK_2", - "CMT_TOP_ICLK_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_ICLK_5", - "CMT_TOP_ICLK_6", - "CMT_TOP_ICLK_7", - "CMT_TOP_ICLK_8", - "CMT_TOP_ICLK_9", - "CMT_TOP_IMUX0_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_IMUX0_10", - "CMT_TOP_IMUX0_11", - "CMT_TOP_IMUX0_12", - "CMT_TOP_IMUX0_2", - "CMT_TOP_IMUX0_3", - "CMT_TOP_IMUX0_4", - "CMT_TOP_IMUX0_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX0_8", - "CMT_TOP_IMUX0_9", - "CMT_TOP_IMUX10_0", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX10_10", - "CMT_TOP_IMUX10_11", - "CMT_TOP_IMUX10_12", - "CMT_TOP_IMUX10_2", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX10_4", - "CMT_TOP_IMUX10_5", - "CMT_TOP_IMUX10_6", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_IMUX10_9", - "CMT_TOP_IMUX11_0", - "CMT_TOP_IMUX11_1", - "CMT_TOP_IMUX11_10", - "CMT_TOP_IMUX11_11", - "CMT_TOP_IMUX11_12", - "CMT_TOP_IMUX11_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_IMUX11_4", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX11_7", - "CMT_TOP_IMUX11_8", - "CMT_TOP_IMUX11_9", - "CMT_TOP_IMUX12_0", - "CMT_TOP_IMUX12_1", - "CMT_TOP_IMUX12_10", - "CMT_TOP_IMUX12_11", - "CMT_TOP_IMUX12_12", - "CMT_TOP_IMUX12_2", - "CMT_TOP_IMUX12_3", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX12_5", - "CMT_TOP_IMUX12_6", - "CMT_TOP_IMUX12_7", - "CMT_TOP_IMUX12_8", - "CMT_TOP_IMUX12_9", - "CMT_TOP_IMUX13_0", - "CMT_TOP_IMUX13_1", - "CMT_TOP_IMUX13_10", - "CMT_TOP_IMUX13_11", - "CMT_TOP_IMUX13_12", - "CMT_TOP_IMUX13_2", - "CMT_TOP_IMUX13_3", - "CMT_TOP_IMUX13_4", - "CMT_TOP_IMUX13_5", - "CMT_TOP_IMUX13_6", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX13_8", - "CMT_TOP_IMUX13_9", - "CMT_TOP_IMUX14_0", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX14_10", - "CMT_TOP_IMUX14_11", - "CMT_TOP_IMUX14_12", - "CMT_TOP_IMUX14_2", - "CMT_TOP_IMUX14_3", - "CMT_TOP_IMUX14_4", - "CMT_TOP_IMUX14_5", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_IMUX14_9", - "CMT_TOP_IMUX15_0", - "CMT_TOP_IMUX15_1", - "CMT_TOP_IMUX15_10", - "CMT_TOP_IMUX15_11", - "CMT_TOP_IMUX15_12", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX15_4", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_IMUX15_9", - "CMT_TOP_IMUX16_0", - "CMT_TOP_IMUX16_1", - "CMT_TOP_IMUX16_10", - "CMT_TOP_IMUX16_11", - "CMT_TOP_IMUX16_12", - "CMT_TOP_IMUX16_2", - "CMT_TOP_IMUX16_3", - "CMT_TOP_IMUX16_4", - "CMT_TOP_IMUX16_5", - "CMT_TOP_IMUX16_6", - "CMT_TOP_IMUX16_7", - "CMT_TOP_IMUX16_8", - "CMT_TOP_IMUX16_9", - "CMT_TOP_IMUX17_0", - "CMT_TOP_IMUX17_1", - "CMT_TOP_IMUX17_10", - "CMT_TOP_IMUX17_11", - "CMT_TOP_IMUX17_12", - "CMT_TOP_IMUX17_2", - "CMT_TOP_IMUX17_3", - "CMT_TOP_IMUX17_4", - "CMT_TOP_IMUX17_5", - "CMT_TOP_IMUX17_6", - "CMT_TOP_IMUX17_7", - "CMT_TOP_IMUX17_8", - "CMT_TOP_IMUX17_9", - "CMT_TOP_IMUX18_0", - "CMT_TOP_IMUX18_1", - "CMT_TOP_IMUX18_10", - "CMT_TOP_IMUX18_11", - "CMT_TOP_IMUX18_12", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX18_3", - "CMT_TOP_IMUX18_4", - "CMT_TOP_IMUX18_5", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX18_7", - "CMT_TOP_IMUX18_8", - "CMT_TOP_IMUX18_9", - "CMT_TOP_IMUX19_0", - "CMT_TOP_IMUX19_1", - "CMT_TOP_IMUX19_10", - "CMT_TOP_IMUX19_11", - "CMT_TOP_IMUX19_12", - "CMT_TOP_IMUX19_2", - "CMT_TOP_IMUX19_3", - "CMT_TOP_IMUX19_4", - "CMT_TOP_IMUX19_5", - "CMT_TOP_IMUX19_6", - "CMT_TOP_IMUX19_7", - "CMT_TOP_IMUX19_8", - "CMT_TOP_IMUX19_9", - "CMT_TOP_IMUX1_0", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX1_10", - "CMT_TOP_IMUX1_11", - "CMT_TOP_IMUX1_12", - "CMT_TOP_IMUX1_2", - "CMT_TOP_IMUX1_3", - "CMT_TOP_IMUX1_4", - "CMT_TOP_IMUX1_5", - "CMT_TOP_IMUX1_6", - "CMT_TOP_IMUX1_7", - "CMT_TOP_IMUX1_8", - "CMT_TOP_IMUX1_9", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX20_1", - "CMT_TOP_IMUX20_10", - "CMT_TOP_IMUX20_11", - "CMT_TOP_IMUX20_12", - "CMT_TOP_IMUX20_2", - "CMT_TOP_IMUX20_3", - "CMT_TOP_IMUX20_4", - "CMT_TOP_IMUX20_5", - "CMT_TOP_IMUX20_6", - "CMT_TOP_IMUX20_7", - "CMT_TOP_IMUX20_8", - "CMT_TOP_IMUX20_9", - "CMT_TOP_IMUX21_0", - "CMT_TOP_IMUX21_1", - "CMT_TOP_IMUX21_10", - "CMT_TOP_IMUX21_11", - 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"CMT_TOP_IMUX6_4", - "CMT_TOP_IMUX6_5", - "CMT_TOP_IMUX6_6", - "CMT_TOP_IMUX6_7", - "CMT_TOP_IMUX6_8", - "CMT_TOP_IMUX6_9", - "CMT_TOP_IMUX7_0", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX7_10", - "CMT_TOP_IMUX7_11", - "CMT_TOP_IMUX7_12", - "CMT_TOP_IMUX7_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX7_8", - "CMT_TOP_IMUX7_9", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_IMUX8_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_IMUX8_12", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX8_3", - "CMT_TOP_IMUX8_4", - "CMT_TOP_IMUX8_5", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX8_7", - "CMT_TOP_IMUX8_8", - "CMT_TOP_IMUX8_9", - "CMT_TOP_IMUX9_0", - "CMT_TOP_IMUX9_1", - "CMT_TOP_IMUX9_10", - "CMT_TOP_IMUX9_11", - "CMT_TOP_IMUX9_12", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_IMUX9_4", - "CMT_TOP_IMUX9_5", - "CMT_TOP_IMUX9_6", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX9_9", - "CMT_TOP_LH10_0", - "CMT_TOP_LH10_1", - "CMT_TOP_LH10_10", - "CMT_TOP_LH10_11", - "CMT_TOP_LH10_12", - "CMT_TOP_LH10_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_4", - "CMT_TOP_LH10_5", - "CMT_TOP_LH10_6", - "CMT_TOP_LH10_7", - "CMT_TOP_LH10_8", - "CMT_TOP_LH10_9", - "CMT_TOP_LH11_0", - "CMT_TOP_LH11_1", - "CMT_TOP_LH11_10", - "CMT_TOP_LH11_11", - "CMT_TOP_LH11_12", - "CMT_TOP_LH11_2", - "CMT_TOP_LH11_3", - "CMT_TOP_LH11_4", - "CMT_TOP_LH11_5", - "CMT_TOP_LH11_6", - "CMT_TOP_LH11_7", - "CMT_TOP_LH11_8", - "CMT_TOP_LH11_9", - "CMT_TOP_LH12_0", - "CMT_TOP_LH12_1", - "CMT_TOP_LH12_10", - "CMT_TOP_LH12_11", - "CMT_TOP_LH12_12", - "CMT_TOP_LH12_2", - "CMT_TOP_LH12_3", - "CMT_TOP_LH12_4", - "CMT_TOP_LH12_5", - "CMT_TOP_LH12_6", - "CMT_TOP_LH12_7", - "CMT_TOP_LH12_8", - "CMT_TOP_LH12_9", - "CMT_TOP_LH1_0", - "CMT_TOP_LH1_1", - "CMT_TOP_LH1_10", - "CMT_TOP_LH1_11", - "CMT_TOP_LH1_12", - "CMT_TOP_LH1_2", - "CMT_TOP_LH1_3", - "CMT_TOP_LH1_4", - "CMT_TOP_LH1_5", - "CMT_TOP_LH1_6", - "CMT_TOP_LH1_7", - "CMT_TOP_LH1_8", - "CMT_TOP_LH1_9", - "CMT_TOP_LH2_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH2_10", - "CMT_TOP_LH2_11", - "CMT_TOP_LH2_12", - "CMT_TOP_LH2_2", - "CMT_TOP_LH2_3", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_5", - "CMT_TOP_LH2_6", - "CMT_TOP_LH2_7", - "CMT_TOP_LH2_8", - "CMT_TOP_LH2_9", - "CMT_TOP_LH3_0", - "CMT_TOP_LH3_1", - "CMT_TOP_LH3_10", - "CMT_TOP_LH3_11", - "CMT_TOP_LH3_12", - "CMT_TOP_LH3_2", - "CMT_TOP_LH3_3", - "CMT_TOP_LH3_4", - "CMT_TOP_LH3_5", - "CMT_TOP_LH3_6", - "CMT_TOP_LH3_7", - "CMT_TOP_LH3_8", - "CMT_TOP_LH3_9", - "CMT_TOP_LH4_0", - "CMT_TOP_LH4_1", - "CMT_TOP_LH4_10", - "CMT_TOP_LH4_11", - "CMT_TOP_LH4_12", - "CMT_TOP_LH4_2", - "CMT_TOP_LH4_3", - "CMT_TOP_LH4_4", - "CMT_TOP_LH4_5", - "CMT_TOP_LH4_6", - "CMT_TOP_LH4_7", - "CMT_TOP_LH4_8", - "CMT_TOP_LH4_9", - "CMT_TOP_LH5_0", - "CMT_TOP_LH5_1", - "CMT_TOP_LH5_10", - "CMT_TOP_LH5_11", - "CMT_TOP_LH5_12", - "CMT_TOP_LH5_2", - "CMT_TOP_LH5_3", - "CMT_TOP_LH5_4", - "CMT_TOP_LH5_5", - "CMT_TOP_LH5_6", - "CMT_TOP_LH5_7", - "CMT_TOP_LH5_8", - "CMT_TOP_LH5_9", - "CMT_TOP_LH6_0", - "CMT_TOP_LH6_1", - "CMT_TOP_LH6_10", - "CMT_TOP_LH6_11", - "CMT_TOP_LH6_12", - "CMT_TOP_LH6_2", - "CMT_TOP_LH6_3", - "CMT_TOP_LH6_4", - "CMT_TOP_LH6_5", - "CMT_TOP_LH6_6", - "CMT_TOP_LH6_7", - "CMT_TOP_LH6_8", - "CMT_TOP_LH6_9", - "CMT_TOP_LH7_0", - "CMT_TOP_LH7_1", - "CMT_TOP_LH7_10", - "CMT_TOP_LH7_11", - "CMT_TOP_LH7_12", - "CMT_TOP_LH7_2", - "CMT_TOP_LH7_3", - "CMT_TOP_LH7_4", - "CMT_TOP_LH7_5", - "CMT_TOP_LH7_6", - "CMT_TOP_LH7_7", - "CMT_TOP_LH7_8", - "CMT_TOP_LH7_9", - "CMT_TOP_LH8_0", - "CMT_TOP_LH8_1", - "CMT_TOP_LH8_10", - "CMT_TOP_LH8_11", - "CMT_TOP_LH8_12", - "CMT_TOP_LH8_2", - "CMT_TOP_LH8_3", - "CMT_TOP_LH8_4", - "CMT_TOP_LH8_5", - "CMT_TOP_LH8_6", - "CMT_TOP_LH8_7", - "CMT_TOP_LH8_8", - "CMT_TOP_LH8_9", - "CMT_TOP_LH9_0", - "CMT_TOP_LH9_1", - "CMT_TOP_LH9_10", - "CMT_TOP_LH9_11", - "CMT_TOP_LH9_12", - "CMT_TOP_LH9_2", - "CMT_TOP_LH9_3", - "CMT_TOP_LH9_4", - "CMT_TOP_LH9_5", - "CMT_TOP_LH9_6", - "CMT_TOP_LH9_7", - "CMT_TOP_LH9_8", - "CMT_TOP_LH9_9", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B0_12", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_TOP_LOGIC_OUTS_L_B10_12", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_TOP_LOGIC_OUTS_L_B11_12", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_LOGIC_OUTS_L_B12_12", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LOGIC_OUTS_L_B13_10", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_LOGIC_OUTS_L_B13_12", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_LOGIC_OUTS_L_B14_12", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_LOGIC_OUTS_L_B15_12", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_LOGIC_OUTS_L_B16_12", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B17_12", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_TOP_LOGIC_OUTS_L_B18_12", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LOGIC_OUTS_L_B19_12", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_TOP_LOGIC_OUTS_L_B1_12", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_TOP_LOGIC_OUTS_L_B20_12", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_TOP_LOGIC_OUTS_L_B21_12", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_TOP_LOGIC_OUTS_L_B22_12", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_LOGIC_OUTS_L_B23_12", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LOGIC_OUTS_L_B2_12", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LOGIC_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_LOGIC_OUTS_L_B4_12", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_LOGIC_OUTS_L_B5_12", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_TOP_LOGIC_OUTS_L_B6_12", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_LOGIC_OUTS_L_B7_12", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_12", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_LOGIC_OUTS_L_B9_12", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_L_CLKFBOUT2IN", - "CMT_TOP_L_UPPER_T_CLKFBIN", - "CMT_TOP_L_UPPER_T_CLKIN1", - "CMT_TOP_L_UPPER_T_CLKIN2", - "CMT_TOP_L_UPPER_T_CLKPLL0", - "CMT_TOP_L_UPPER_T_CLKPLL1", - "CMT_TOP_L_UPPER_T_CLKPLL2", - "CMT_TOP_L_UPPER_T_CLKPLL3", - "CMT_TOP_L_UPPER_T_CLKPLL4", - "CMT_TOP_L_UPPER_T_CLKPLL5", - "CMT_TOP_L_UPPER_T_CLKPLL6", - "CMT_TOP_L_UPPER_T_CLKPLL7", - "CMT_TOP_L_UPPER_T_FREQ_BB0", - "CMT_TOP_L_UPPER_T_FREQ_BB1", - "CMT_TOP_L_UPPER_T_FREQ_BB2", - "CMT_TOP_L_UPPER_T_FREQ_BB3", - "CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT", - "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT", - "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_MONITOR_N_12", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_MONITOR_N_9", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_MONITOR_P_12", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_NE2A0_0", - "CMT_TOP_NE2A0_1", - "CMT_TOP_NE2A0_10", - "CMT_TOP_NE2A0_11", - "CMT_TOP_NE2A0_12", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A0_4", - "CMT_TOP_NE2A0_5", - "CMT_TOP_NE2A0_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_NE2A0_8", - "CMT_TOP_NE2A0_9", - "CMT_TOP_NE2A1_0", - "CMT_TOP_NE2A1_1", - "CMT_TOP_NE2A1_10", - "CMT_TOP_NE2A1_11", - "CMT_TOP_NE2A1_12", - "CMT_TOP_NE2A1_2", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_NE2A1_5", - "CMT_TOP_NE2A1_6", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE2A1_8", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE2A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_NE2A2_10", - "CMT_TOP_NE2A2_11", - "CMT_TOP_NE2A2_12", - "CMT_TOP_NE2A2_2", - "CMT_TOP_NE2A2_3", - "CMT_TOP_NE2A2_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_NE2A2_6", - "CMT_TOP_NE2A2_7", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE2A2_9", - "CMT_TOP_NE2A3_0", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NE2A3_10", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NE2A3_12", - "CMT_TOP_NE2A3_2", - "CMT_TOP_NE2A3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NE2A3_6", - "CMT_TOP_NE2A3_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_NE4BEG0_10", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_NE4BEG0_12", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_NE4BEG1_12", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_NE4BEG2_11", - "CMT_TOP_NE4BEG2_12", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_NE4BEG3_12", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_NE4C0_0", - "CMT_TOP_NE4C0_1", - "CMT_TOP_NE4C0_10", - "CMT_TOP_NE4C0_11", - "CMT_TOP_NE4C0_12", - "CMT_TOP_NE4C0_2", - "CMT_TOP_NE4C0_3", - "CMT_TOP_NE4C0_4", - "CMT_TOP_NE4C0_5", - "CMT_TOP_NE4C0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_9", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_NE4C1_10", - "CMT_TOP_NE4C1_11", - "CMT_TOP_NE4C1_12", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NE4C1_3", - "CMT_TOP_NE4C1_4", - "CMT_TOP_NE4C1_5", - "CMT_TOP_NE4C1_6", - "CMT_TOP_NE4C1_7", - "CMT_TOP_NE4C1_8", - "CMT_TOP_NE4C1_9", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NE4C2_1", - "CMT_TOP_NE4C2_10", - "CMT_TOP_NE4C2_11", - "CMT_TOP_NE4C2_12", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE4C2_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NE4C2_6", - "CMT_TOP_NE4C2_7", - "CMT_TOP_NE4C2_8", - "CMT_TOP_NE4C2_9", - "CMT_TOP_NE4C3_0", - "CMT_TOP_NE4C3_1", - "CMT_TOP_NE4C3_10", - "CMT_TOP_NE4C3_11", - "CMT_TOP_NE4C3_12", - "CMT_TOP_NE4C3_2", - "CMT_TOP_NE4C3_3", - "CMT_TOP_NE4C3_4", - "CMT_TOP_NE4C3_5", - "CMT_TOP_NE4C3_6", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_NE4C3_9", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW2A0_1", - "CMT_TOP_NW2A0_10", - "CMT_TOP_NW2A0_11", - "CMT_TOP_NW2A0_12", - "CMT_TOP_NW2A0_2", - "CMT_TOP_NW2A0_3", - "CMT_TOP_NW2A0_4", - "CMT_TOP_NW2A0_5", - "CMT_TOP_NW2A0_6", - "CMT_TOP_NW2A0_7", - "CMT_TOP_NW2A0_8", - "CMT_TOP_NW2A0_9", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NW2A1_1", - "CMT_TOP_NW2A1_10", - "CMT_TOP_NW2A1_11", - "CMT_TOP_NW2A1_12", - "CMT_TOP_NW2A1_2", - "CMT_TOP_NW2A1_3", - "CMT_TOP_NW2A1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_NW2A1_6", - "CMT_TOP_NW2A1_7", - "CMT_TOP_NW2A1_8", - "CMT_TOP_NW2A1_9", - "CMT_TOP_NW2A2_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_NW2A2_10", - "CMT_TOP_NW2A2_11", - "CMT_TOP_NW2A2_12", - "CMT_TOP_NW2A2_2", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_4", - "CMT_TOP_NW2A2_5", - "CMT_TOP_NW2A2_6", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NW2A2_8", - "CMT_TOP_NW2A2_9", - "CMT_TOP_NW2A3_0", - "CMT_TOP_NW2A3_1", - "CMT_TOP_NW2A3_10", - "CMT_TOP_NW2A3_11", - "CMT_TOP_NW2A3_12", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NW2A3_3", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW2A3_5", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NW2A3_7", - "CMT_TOP_NW2A3_8", - "CMT_TOP_NW2A3_9", - "CMT_TOP_NW4A0_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_NW4A0_10", - "CMT_TOP_NW4A0_11", - "CMT_TOP_NW4A0_12", - "CMT_TOP_NW4A0_2", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A0_4", - "CMT_TOP_NW4A0_5", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NW4A0_7", - "CMT_TOP_NW4A0_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_NW4A1_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_NW4A1_10", - "CMT_TOP_NW4A1_11", - "CMT_TOP_NW4A1_12", - "CMT_TOP_NW4A1_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_NW4A1_4", - "CMT_TOP_NW4A1_5", - "CMT_TOP_NW4A1_6", - "CMT_TOP_NW4A1_7", - "CMT_TOP_NW4A1_8", - "CMT_TOP_NW4A1_9", - "CMT_TOP_NW4A2_0", - "CMT_TOP_NW4A2_1", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NW4A2_11", - "CMT_TOP_NW4A2_12", - "CMT_TOP_NW4A2_2", - "CMT_TOP_NW4A2_3", - "CMT_TOP_NW4A2_4", - "CMT_TOP_NW4A2_5", - "CMT_TOP_NW4A2_6", - "CMT_TOP_NW4A2_7", - "CMT_TOP_NW4A2_8", - "CMT_TOP_NW4A2_9", - "CMT_TOP_NW4A3_0", - "CMT_TOP_NW4A3_1", - "CMT_TOP_NW4A3_10", - "CMT_TOP_NW4A3_11", - "CMT_TOP_NW4A3_12", - "CMT_TOP_NW4A3_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NW4A3_6", - "CMT_TOP_NW4A3_7", - "CMT_TOP_NW4A3_8", - "CMT_TOP_NW4A3_9", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NW4END0_1", - "CMT_TOP_NW4END0_10", - "CMT_TOP_NW4END0_11", - "CMT_TOP_NW4END0_12", - "CMT_TOP_NW4END0_2", - "CMT_TOP_NW4END0_3", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END0_5", - "CMT_TOP_NW4END0_6", - "CMT_TOP_NW4END0_7", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NW4END0_9", - "CMT_TOP_NW4END1_0", - "CMT_TOP_NW4END1_1", - "CMT_TOP_NW4END1_10", - "CMT_TOP_NW4END1_11", - "CMT_TOP_NW4END1_12", - "CMT_TOP_NW4END1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_NW4END1_4", - "CMT_TOP_NW4END1_5", - "CMT_TOP_NW4END1_6", - "CMT_TOP_NW4END1_7", - "CMT_TOP_NW4END1_8", - "CMT_TOP_NW4END1_9", - "CMT_TOP_NW4END2_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END2_10", - "CMT_TOP_NW4END2_11", - "CMT_TOP_NW4END2_12", - "CMT_TOP_NW4END2_2", - "CMT_TOP_NW4END2_3", - "CMT_TOP_NW4END2_4", - "CMT_TOP_NW4END2_5", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NW4END2_8", - "CMT_TOP_NW4END2_9", - "CMT_TOP_NW4END3_0", - "CMT_TOP_NW4END3_1", - "CMT_TOP_NW4END3_10", - "CMT_TOP_NW4END3_11", - "CMT_TOP_NW4END3_12", - "CMT_TOP_NW4END3_2", - "CMT_TOP_NW4END3_3", - "CMT_TOP_NW4END3_4", - "CMT_TOP_NW4END3_5", - "CMT_TOP_NW4END3_6", - "CMT_TOP_NW4END3_7", - "CMT_TOP_NW4END3_8", - "CMT_TOP_NW4END3_9", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_OCLK1X_90_10", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_OCLK1X_90_12", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_OCLK1X_90_9", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_OCLKDIV_12", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_OCLK_0", - "CMT_TOP_OCLK_1", - "CMT_TOP_OCLK_10", - "CMT_TOP_OCLK_11", - "CMT_TOP_OCLK_12", - "CMT_TOP_OCLK_2", - "CMT_TOP_OCLK_3", - "CMT_TOP_OCLK_4", - "CMT_TOP_OCLK_5", - "CMT_TOP_OCLK_6", - "CMT_TOP_OCLK_7", - "CMT_TOP_OCLK_8", - "CMT_TOP_OCLK_9", - "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", - "CMT_TOP_R_UPPER_T_PLLE2_DCLK", - "CMT_TOP_R_UPPER_T_PLLE2_DEN", - "CMT_TOP_R_UPPER_T_PLLE2_DI0", - "CMT_TOP_R_UPPER_T_PLLE2_DI1", - "CMT_TOP_R_UPPER_T_PLLE2_DI10", - "CMT_TOP_R_UPPER_T_PLLE2_DI11", - "CMT_TOP_R_UPPER_T_PLLE2_DI12", - "CMT_TOP_R_UPPER_T_PLLE2_DI13", - "CMT_TOP_R_UPPER_T_PLLE2_DI14", - "CMT_TOP_R_UPPER_T_PLLE2_DI15", - "CMT_TOP_R_UPPER_T_PLLE2_DI2", - "CMT_TOP_R_UPPER_T_PLLE2_DI3", - "CMT_TOP_R_UPPER_T_PLLE2_DI4", - "CMT_TOP_R_UPPER_T_PLLE2_DI5", - "CMT_TOP_R_UPPER_T_PLLE2_DI6", - "CMT_TOP_R_UPPER_T_PLLE2_DI7", - "CMT_TOP_R_UPPER_T_PLLE2_DI8", - "CMT_TOP_R_UPPER_T_PLLE2_DI9", - "CMT_TOP_R_UPPER_T_PLLE2_DO0", - "CMT_TOP_R_UPPER_T_PLLE2_DO1", - "CMT_TOP_R_UPPER_T_PLLE2_DO10", - "CMT_TOP_R_UPPER_T_PLLE2_DO11", - "CMT_TOP_R_UPPER_T_PLLE2_DO12", - "CMT_TOP_R_UPPER_T_PLLE2_DO13", - "CMT_TOP_R_UPPER_T_PLLE2_DO14", - "CMT_TOP_R_UPPER_T_PLLE2_DO15", - "CMT_TOP_R_UPPER_T_PLLE2_DO2", - "CMT_TOP_R_UPPER_T_PLLE2_DO3", - "CMT_TOP_R_UPPER_T_PLLE2_DO4", - "CMT_TOP_R_UPPER_T_PLLE2_DO5", - "CMT_TOP_R_UPPER_T_PLLE2_DO6", - "CMT_TOP_R_UPPER_T_PLLE2_DO7", - "CMT_TOP_R_UPPER_T_PLLE2_DO8", - "CMT_TOP_R_UPPER_T_PLLE2_DO9", - "CMT_TOP_R_UPPER_T_PLLE2_DRDY", - "CMT_TOP_R_UPPER_T_PLLE2_DWE", - "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", - "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", - "CMT_TOP_R_UPPER_T_PLLE2_RST", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", - "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", - "CMT_TOP_SE2A0_0", - "CMT_TOP_SE2A0_1", - "CMT_TOP_SE2A0_10", - "CMT_TOP_SE2A0_11", - "CMT_TOP_SE2A0_12", - "CMT_TOP_SE2A0_2", - "CMT_TOP_SE2A0_3", - "CMT_TOP_SE2A0_4", - "CMT_TOP_SE2A0_5", - "CMT_TOP_SE2A0_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_SE2A0_9", - "CMT_TOP_SE2A1_0", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE2A1_10", - "CMT_TOP_SE2A1_11", - "CMT_TOP_SE2A1_12", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A1_3", - "CMT_TOP_SE2A1_4", - "CMT_TOP_SE2A1_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SE2A1_8", - "CMT_TOP_SE2A1_9", - "CMT_TOP_SE2A2_0", - "CMT_TOP_SE2A2_1", - "CMT_TOP_SE2A2_10", - "CMT_TOP_SE2A2_11", - "CMT_TOP_SE2A2_12", - "CMT_TOP_SE2A2_2", - "CMT_TOP_SE2A2_3", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SE2A2_5", - "CMT_TOP_SE2A2_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_SE2A2_8", - "CMT_TOP_SE2A2_9", - "CMT_TOP_SE2A3_0", - "CMT_TOP_SE2A3_1", - "CMT_TOP_SE2A3_10", - "CMT_TOP_SE2A3_11", - "CMT_TOP_SE2A3_12", - "CMT_TOP_SE2A3_2", - "CMT_TOP_SE2A3_3", - "CMT_TOP_SE2A3_4", - "CMT_TOP_SE2A3_5", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SE2A3_7", - "CMT_TOP_SE2A3_8", - "CMT_TOP_SE2A3_9", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_SE4BEG0_12", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_SE4BEG1_10", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_SE4BEG1_12", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_SE4BEG2_10", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SE4BEG2_12", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_SE4BEG3_12", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_SE4C0_0", - "CMT_TOP_SE4C0_1", - "CMT_TOP_SE4C0_10", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE4C0_12", - "CMT_TOP_SE4C0_2", - "CMT_TOP_SE4C0_3", - "CMT_TOP_SE4C0_4", - "CMT_TOP_SE4C0_5", - "CMT_TOP_SE4C0_6", - "CMT_TOP_SE4C0_7", - "CMT_TOP_SE4C0_8", - "CMT_TOP_SE4C0_9", - "CMT_TOP_SE4C1_0", - "CMT_TOP_SE4C1_1", - "CMT_TOP_SE4C1_10", - "CMT_TOP_SE4C1_11", - "CMT_TOP_SE4C1_12", - "CMT_TOP_SE4C1_2", - "CMT_TOP_SE4C1_3", - "CMT_TOP_SE4C1_4", - "CMT_TOP_SE4C1_5", - "CMT_TOP_SE4C1_6", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE4C1_8", - "CMT_TOP_SE4C1_9", - "CMT_TOP_SE4C2_0", - "CMT_TOP_SE4C2_1", - "CMT_TOP_SE4C2_10", - "CMT_TOP_SE4C2_11", - "CMT_TOP_SE4C2_12", - "CMT_TOP_SE4C2_2", - "CMT_TOP_SE4C2_3", - "CMT_TOP_SE4C2_4", - "CMT_TOP_SE4C2_5", - "CMT_TOP_SE4C2_6", - "CMT_TOP_SE4C2_7", - "CMT_TOP_SE4C2_8", - "CMT_TOP_SE4C2_9", - "CMT_TOP_SE4C3_0", - "CMT_TOP_SE4C3_1", - "CMT_TOP_SE4C3_10", - "CMT_TOP_SE4C3_11", - "CMT_TOP_SE4C3_12", - "CMT_TOP_SE4C3_2", - "CMT_TOP_SE4C3_3", - "CMT_TOP_SE4C3_4", - "CMT_TOP_SE4C3_5", - "CMT_TOP_SE4C3_6", - "CMT_TOP_SE4C3_7", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SE4C3_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_SW2A0_1", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SW2A0_11", - "CMT_TOP_SW2A0_12", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW2A0_3", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW2A0_5", - "CMT_TOP_SW2A0_6", - "CMT_TOP_SW2A0_7", - "CMT_TOP_SW2A0_8", - "CMT_TOP_SW2A0_9", - "CMT_TOP_SW2A1_0", - "CMT_TOP_SW2A1_1", - "CMT_TOP_SW2A1_10", - "CMT_TOP_SW2A1_11", - "CMT_TOP_SW2A1_12", - "CMT_TOP_SW2A1_2", - "CMT_TOP_SW2A1_3", - "CMT_TOP_SW2A1_4", - "CMT_TOP_SW2A1_5", - "CMT_TOP_SW2A1_6", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW2A1_8", - "CMT_TOP_SW2A1_9", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW2A2_1", - "CMT_TOP_SW2A2_10", - "CMT_TOP_SW2A2_11", - "CMT_TOP_SW2A2_12", - "CMT_TOP_SW2A2_2", - "CMT_TOP_SW2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_SW2A2_5", - "CMT_TOP_SW2A2_6", - "CMT_TOP_SW2A2_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_SW2A2_9", - "CMT_TOP_SW2A3_0", - "CMT_TOP_SW2A3_1", - "CMT_TOP_SW2A3_10", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SW2A3_12", - "CMT_TOP_SW2A3_2", - "CMT_TOP_SW2A3_3", - "CMT_TOP_SW2A3_4", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW2A3_6", - "CMT_TOP_SW2A3_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SW2A3_9", - "CMT_TOP_SW4A0_0", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SW4A0_10", - "CMT_TOP_SW4A0_11", - "CMT_TOP_SW4A0_12", - "CMT_TOP_SW4A0_2", - "CMT_TOP_SW4A0_3", - "CMT_TOP_SW4A0_4", - "CMT_TOP_SW4A0_5", - "CMT_TOP_SW4A0_6", - "CMT_TOP_SW4A0_7", - "CMT_TOP_SW4A0_8", - "CMT_TOP_SW4A0_9", - "CMT_TOP_SW4A1_0", - "CMT_TOP_SW4A1_1", - "CMT_TOP_SW4A1_10", - "CMT_TOP_SW4A1_11", - "CMT_TOP_SW4A1_12", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW4A1_3", - "CMT_TOP_SW4A1_4", - "CMT_TOP_SW4A1_5", - "CMT_TOP_SW4A1_6", - "CMT_TOP_SW4A1_7", - "CMT_TOP_SW4A1_8", - "CMT_TOP_SW4A1_9", - "CMT_TOP_SW4A2_0", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SW4A2_10", - "CMT_TOP_SW4A2_11", - "CMT_TOP_SW4A2_12", - "CMT_TOP_SW4A2_2", - "CMT_TOP_SW4A2_3", - "CMT_TOP_SW4A2_4", - "CMT_TOP_SW4A2_5", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SW4A2_7", - "CMT_TOP_SW4A2_8", - "CMT_TOP_SW4A2_9", - "CMT_TOP_SW4A3_0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_SW4A3_10", - "CMT_TOP_SW4A3_11", - "CMT_TOP_SW4A3_12", - "CMT_TOP_SW4A3_2", - "CMT_TOP_SW4A3_3", - "CMT_TOP_SW4A3_4", - "CMT_TOP_SW4A3_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SW4A3_7", - "CMT_TOP_SW4A3_8", - "CMT_TOP_SW4A3_9", - "CMT_TOP_SW4END0_0", - "CMT_TOP_SW4END0_1", - "CMT_TOP_SW4END0_10", - "CMT_TOP_SW4END0_11", - "CMT_TOP_SW4END0_12", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SW4END0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_SW4END0_5", - "CMT_TOP_SW4END0_6", - "CMT_TOP_SW4END0_7", - "CMT_TOP_SW4END0_8", - "CMT_TOP_SW4END0_9", - "CMT_TOP_SW4END1_0", - "CMT_TOP_SW4END1_1", - "CMT_TOP_SW4END1_10", - "CMT_TOP_SW4END1_11", - "CMT_TOP_SW4END1_12", - "CMT_TOP_SW4END1_2", - "CMT_TOP_SW4END1_3", - "CMT_TOP_SW4END1_4", - "CMT_TOP_SW4END1_5", - "CMT_TOP_SW4END1_6", - "CMT_TOP_SW4END1_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_SW4END1_9", - "CMT_TOP_SW4END2_0", - "CMT_TOP_SW4END2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_SW4END2_11", - "CMT_TOP_SW4END2_12", - "CMT_TOP_SW4END2_2", - "CMT_TOP_SW4END2_3", - "CMT_TOP_SW4END2_4", - "CMT_TOP_SW4END2_5", - "CMT_TOP_SW4END2_6", - "CMT_TOP_SW4END2_7", - "CMT_TOP_SW4END2_8", - "CMT_TOP_SW4END2_9", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SW4END3_1", - "CMT_TOP_SW4END3_10", - "CMT_TOP_SW4END3_11", - "CMT_TOP_SW4END3_12", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_3", - "CMT_TOP_SW4END3_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SW4END3_6", - "CMT_TOP_SW4END3_7", - "CMT_TOP_SW4END3_8", - "CMT_TOP_SW4END3_9", - "CMT_TOP_WL1END0_0", - "CMT_TOP_WL1END0_1", - "CMT_TOP_WL1END0_10", - "CMT_TOP_WL1END0_11", - "CMT_TOP_WL1END0_12", - "CMT_TOP_WL1END0_2", - "CMT_TOP_WL1END0_3", - "CMT_TOP_WL1END0_4", - "CMT_TOP_WL1END0_5", - "CMT_TOP_WL1END0_6", - "CMT_TOP_WL1END0_7", - "CMT_TOP_WL1END0_8", - "CMT_TOP_WL1END0_9", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WL1END1_1", - "CMT_TOP_WL1END1_10", - "CMT_TOP_WL1END1_11", - "CMT_TOP_WL1END1_12", - "CMT_TOP_WL1END1_2", - "CMT_TOP_WL1END1_3", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_5", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WL1END1_7", - "CMT_TOP_WL1END1_8", - "CMT_TOP_WL1END1_9", - "CMT_TOP_WL1END2_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_WL1END2_10", - "CMT_TOP_WL1END2_11", - "CMT_TOP_WL1END2_12", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WL1END2_3", - "CMT_TOP_WL1END2_4", - "CMT_TOP_WL1END2_5", - "CMT_TOP_WL1END2_6", - "CMT_TOP_WL1END2_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_WL1END2_9", - "CMT_TOP_WL1END3_0", - "CMT_TOP_WL1END3_1", - "CMT_TOP_WL1END3_10", - "CMT_TOP_WL1END3_11", - "CMT_TOP_WL1END3_12", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WL1END3_3", - "CMT_TOP_WL1END3_4", - "CMT_TOP_WL1END3_5", - "CMT_TOP_WL1END3_6", - "CMT_TOP_WL1END3_7", - "CMT_TOP_WL1END3_8", - "CMT_TOP_WL1END3_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_WR1END0_1", - "CMT_TOP_WR1END0_10", - "CMT_TOP_WR1END0_11", - "CMT_TOP_WR1END0_12", - "CMT_TOP_WR1END0_2", - "CMT_TOP_WR1END0_3", - "CMT_TOP_WR1END0_4", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WR1END0_6", - "CMT_TOP_WR1END0_7", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WR1END1_0", - "CMT_TOP_WR1END1_1", - "CMT_TOP_WR1END1_10", - "CMT_TOP_WR1END1_11", - "CMT_TOP_WR1END1_12", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WR1END1_4", - "CMT_TOP_WR1END1_5", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END1_7", - "CMT_TOP_WR1END1_8", - "CMT_TOP_WR1END1_9", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WR1END2_10", - "CMT_TOP_WR1END2_11", - "CMT_TOP_WR1END2_12", - "CMT_TOP_WR1END2_2", - "CMT_TOP_WR1END2_3", - "CMT_TOP_WR1END2_4", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WR1END2_6", - "CMT_TOP_WR1END2_7", - "CMT_TOP_WR1END2_8", - "CMT_TOP_WR1END2_9", - "CMT_TOP_WR1END3_0", - "CMT_TOP_WR1END3_1", - "CMT_TOP_WR1END3_10", - "CMT_TOP_WR1END3_11", - "CMT_TOP_WR1END3_12", - "CMT_TOP_WR1END3_2", - "CMT_TOP_WR1END3_3", - "CMT_TOP_WR1END3_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_WR1END3_6", - "CMT_TOP_WR1END3_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_WR1END3_9", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW2A0_1", - "CMT_TOP_WW2A0_10", - "CMT_TOP_WW2A0_11", - "CMT_TOP_WW2A0_12", - "CMT_TOP_WW2A0_2", - "CMT_TOP_WW2A0_3", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2A0_5", - "CMT_TOP_WW2A0_6", - "CMT_TOP_WW2A0_7", - "CMT_TOP_WW2A0_8", - "CMT_TOP_WW2A0_9", - "CMT_TOP_WW2A1_0", - "CMT_TOP_WW2A1_1", - "CMT_TOP_WW2A1_10", - "CMT_TOP_WW2A1_11", - "CMT_TOP_WW2A1_12", - "CMT_TOP_WW2A1_2", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WW2A1_4", - "CMT_TOP_WW2A1_5", - "CMT_TOP_WW2A1_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_WW2A1_8", - "CMT_TOP_WW2A1_9", - "CMT_TOP_WW2A2_0", - "CMT_TOP_WW2A2_1", - "CMT_TOP_WW2A2_10", - "CMT_TOP_WW2A2_11", - "CMT_TOP_WW2A2_12", - "CMT_TOP_WW2A2_2", - "CMT_TOP_WW2A2_3", - "CMT_TOP_WW2A2_4", - "CMT_TOP_WW2A2_5", - "CMT_TOP_WW2A2_6", - "CMT_TOP_WW2A2_7", - "CMT_TOP_WW2A2_8", - "CMT_TOP_WW2A2_9", - "CMT_TOP_WW2A3_0", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW2A3_10", - "CMT_TOP_WW2A3_11", - "CMT_TOP_WW2A3_12", - "CMT_TOP_WW2A3_2", - "CMT_TOP_WW2A3_3", - "CMT_TOP_WW2A3_4", - "CMT_TOP_WW2A3_5", - "CMT_TOP_WW2A3_6", - "CMT_TOP_WW2A3_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_WW2A3_9", - "CMT_TOP_WW2END0_0", - "CMT_TOP_WW2END0_1", - "CMT_TOP_WW2END0_10", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW2END0_12", - "CMT_TOP_WW2END0_2", - "CMT_TOP_WW2END0_3", - "CMT_TOP_WW2END0_4", - "CMT_TOP_WW2END0_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_WW2END0_7", - "CMT_TOP_WW2END0_8", - "CMT_TOP_WW2END0_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_WW2END1_1", - "CMT_TOP_WW2END1_10", - "CMT_TOP_WW2END1_11", - "CMT_TOP_WW2END1_12", - "CMT_TOP_WW2END1_2", - "CMT_TOP_WW2END1_3", - "CMT_TOP_WW2END1_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WW2END1_7", - "CMT_TOP_WW2END1_8", - "CMT_TOP_WW2END1_9", - "CMT_TOP_WW2END2_0", - "CMT_TOP_WW2END2_1", - "CMT_TOP_WW2END2_10", - "CMT_TOP_WW2END2_11", - "CMT_TOP_WW2END2_12", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW2END2_3", - "CMT_TOP_WW2END2_4", - "CMT_TOP_WW2END2_5", - "CMT_TOP_WW2END2_6", - "CMT_TOP_WW2END2_7", - "CMT_TOP_WW2END2_8", - "CMT_TOP_WW2END2_9", - "CMT_TOP_WW2END3_0", - "CMT_TOP_WW2END3_1", - "CMT_TOP_WW2END3_10", - "CMT_TOP_WW2END3_11", - "CMT_TOP_WW2END3_12", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END3_3", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WW2END3_5", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END3_7", - "CMT_TOP_WW2END3_8", - "CMT_TOP_WW2END3_9", - "CMT_TOP_WW4A0_0", - "CMT_TOP_WW4A0_1", - "CMT_TOP_WW4A0_10", - "CMT_TOP_WW4A0_11", - "CMT_TOP_WW4A0_12", - "CMT_TOP_WW4A0_2", - "CMT_TOP_WW4A0_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_WW4A0_5", - "CMT_TOP_WW4A0_6", - "CMT_TOP_WW4A0_7", - "CMT_TOP_WW4A0_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4A1_1", - "CMT_TOP_WW4A1_10", - "CMT_TOP_WW4A1_11", - "CMT_TOP_WW4A1_12", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW4A1_3", - "CMT_TOP_WW4A1_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_WW4A1_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4A1_9", - "CMT_TOP_WW4A2_0", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4A2_10", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WW4A2_12", - "CMT_TOP_WW4A2_2", - "CMT_TOP_WW4A2_3", - "CMT_TOP_WW4A2_4", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW4A2_6", - "CMT_TOP_WW4A2_7", - "CMT_TOP_WW4A2_8", - "CMT_TOP_WW4A2_9", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW4A3_10", - "CMT_TOP_WW4A3_11", - "CMT_TOP_WW4A3_12", - "CMT_TOP_WW4A3_2", - "CMT_TOP_WW4A3_3", - "CMT_TOP_WW4A3_4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_WW4A3_6", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WW4A3_8", - "CMT_TOP_WW4A3_9", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4B0_10", - "CMT_TOP_WW4B0_11", - "CMT_TOP_WW4B0_12", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4B0_3", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4B0_5", - "CMT_TOP_WW4B0_6", - "CMT_TOP_WW4B0_7", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B0_9", - "CMT_TOP_WW4B1_0", - "CMT_TOP_WW4B1_1", - "CMT_TOP_WW4B1_10", - "CMT_TOP_WW4B1_11", - "CMT_TOP_WW4B1_12", - "CMT_TOP_WW4B1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_5", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4B1_7", - "CMT_TOP_WW4B1_8", - "CMT_TOP_WW4B1_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_WW4B2_1", - "CMT_TOP_WW4B2_10", - "CMT_TOP_WW4B2_11", - "CMT_TOP_WW4B2_12", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4B2_4", - "CMT_TOP_WW4B2_5", - "CMT_TOP_WW4B2_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_WW4B2_8", - "CMT_TOP_WW4B2_9", - "CMT_TOP_WW4B3_0", - "CMT_TOP_WW4B3_1", - "CMT_TOP_WW4B3_10", - "CMT_TOP_WW4B3_11", - "CMT_TOP_WW4B3_12", - "CMT_TOP_WW4B3_2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_WW4B3_4", - "CMT_TOP_WW4B3_5", - "CMT_TOP_WW4B3_6", - "CMT_TOP_WW4B3_7", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW4B3_9", - "CMT_TOP_WW4C0_0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_WW4C0_10", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4C0_12", - "CMT_TOP_WW4C0_2", - "CMT_TOP_WW4C0_3", - "CMT_TOP_WW4C0_4", - "CMT_TOP_WW4C0_5", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4C0_8", - "CMT_TOP_WW4C0_9", - "CMT_TOP_WW4C1_0", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C1_11", - "CMT_TOP_WW4C1_12", - "CMT_TOP_WW4C1_2", - "CMT_TOP_WW4C1_3", - "CMT_TOP_WW4C1_4", - "CMT_TOP_WW4C1_5", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4C1_7", - "CMT_TOP_WW4C1_8", - "CMT_TOP_WW4C1_9", - "CMT_TOP_WW4C2_0", - "CMT_TOP_WW4C2_1", - "CMT_TOP_WW4C2_10", - "CMT_TOP_WW4C2_11", - "CMT_TOP_WW4C2_12", - "CMT_TOP_WW4C2_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_WW4C2_4", - "CMT_TOP_WW4C2_5", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WW4C2_8", - "CMT_TOP_WW4C2_9", - "CMT_TOP_WW4C3_0", - "CMT_TOP_WW4C3_1", - "CMT_TOP_WW4C3_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_WW4C3_12", - "CMT_TOP_WW4C3_2", - "CMT_TOP_WW4C3_3", - "CMT_TOP_WW4C3_4", - "CMT_TOP_WW4C3_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW4C3_8", - "CMT_TOP_WW4C3_9", - "CMT_TOP_WW4END0_0", - "CMT_TOP_WW4END0_1", - "CMT_TOP_WW4END0_10", - "CMT_TOP_WW4END0_11", - "CMT_TOP_WW4END0_12", - "CMT_TOP_WW4END0_2", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_5", - "CMT_TOP_WW4END0_6", - "CMT_TOP_WW4END0_7", - "CMT_TOP_WW4END0_8", - "CMT_TOP_WW4END0_9", - "CMT_TOP_WW4END1_0", - "CMT_TOP_WW4END1_1", - "CMT_TOP_WW4END1_10", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WW4END1_12", - "CMT_TOP_WW4END1_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END1_6", - "CMT_TOP_WW4END1_7", - "CMT_TOP_WW4END1_8", - "CMT_TOP_WW4END1_9", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW4END2_1", - "CMT_TOP_WW4END2_10", - "CMT_TOP_WW4END2_11", - "CMT_TOP_WW4END2_12", - "CMT_TOP_WW4END2_2", - "CMT_TOP_WW4END2_3", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_WW4END2_7", - "CMT_TOP_WW4END2_8", - "CMT_TOP_WW4END2_9", - "CMT_TOP_WW4END3_0", - "CMT_TOP_WW4END3_1", - "CMT_TOP_WW4END3_10", - "CMT_TOP_WW4END3_11", - "CMT_TOP_WW4END3_12", - "CMT_TOP_WW4END3_2", - "CMT_TOP_WW4END3_3", - "CMT_TOP_WW4END3_4", - "CMT_TOP_WW4END3_5", - "CMT_TOP_WW4END3_6", - "CMT_TOP_WW4END3_7", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4END3_9", - "PLLOUT_CLK_FREQ_BB_0", - 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"res": "317.510" + }, + "CMT_TOP_WW4END3_0": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_1": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_10": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_11": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_12": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_2": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_3": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_4": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_5": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_6": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_7": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_8": { + "cap": "18.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_9": { + "cap": "18.000", + "res": "317.510" + }, + "PLLOUT_CLK_FREQ_BB_0": null, + "PLLOUT_CLK_FREQ_BB_1": null, + "PLLOUT_CLK_FREQ_BB_2": null, + "PLLOUT_CLK_FREQ_BB_3": null, + "PLL_CLK_FREQ_BB0_NS": null, + "PLL_CLK_FREQ_BB1_NS": null, + "PLL_CLK_FREQ_BB2_NS": null, + "PLL_CLK_FREQ_BB3_NS": null, + "PLL_CLK_FREQ_BB_BUFOUT_NS0": null, + "PLL_CLK_FREQ_BB_BUFOUT_NS1": null, + "PLL_CLK_FREQ_BB_BUFOUT_NS2": null, + "PLL_CLK_FREQ_BB_BUFOUT_NS3": null + } } diff --git a/zynq7/tile_type_DSP_L.json b/zynq7/tile_type_DSP_L.json index 20bcc83..44406b5 100644 --- a/zynq7/tile_type_DSP_L.json +++ b/zynq7/tile_type_DSP_L.json @@ -2,5560 +2,14294 @@ "pips": { "DSP_L.DSP_0_ACOUT0->DSP_1_ACIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT0" }, "DSP_L.DSP_0_ACOUT1->DSP_1_ACIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT1" }, "DSP_L.DSP_0_ACOUT10->DSP_1_ACIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT10" }, "DSP_L.DSP_0_ACOUT11->DSP_1_ACIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT11" }, "DSP_L.DSP_0_ACOUT12->DSP_1_ACIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT12" }, "DSP_L.DSP_0_ACOUT13->DSP_1_ACIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT13" }, "DSP_L.DSP_0_ACOUT14->DSP_1_ACIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT14" }, "DSP_L.DSP_0_ACOUT15->DSP_1_ACIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT15" }, "DSP_L.DSP_0_ACOUT16->DSP_1_ACIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT16" }, "DSP_L.DSP_0_ACOUT17->DSP_1_ACIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT17" }, "DSP_L.DSP_0_ACOUT18->DSP_1_ACIN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT18" }, "DSP_L.DSP_0_ACOUT19->DSP_1_ACIN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT19" }, "DSP_L.DSP_0_ACOUT2->DSP_1_ACIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT2" }, "DSP_L.DSP_0_ACOUT20->DSP_1_ACIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT20" }, "DSP_L.DSP_0_ACOUT21->DSP_1_ACIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT21" }, "DSP_L.DSP_0_ACOUT22->DSP_1_ACIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT22" }, "DSP_L.DSP_0_ACOUT23->DSP_1_ACIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT23" }, "DSP_L.DSP_0_ACOUT24->DSP_1_ACIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT24" }, "DSP_L.DSP_0_ACOUT25->DSP_1_ACIN25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT25" }, "DSP_L.DSP_0_ACOUT26->DSP_1_ACIN26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT26" }, "DSP_L.DSP_0_ACOUT27->DSP_1_ACIN27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT27" }, "DSP_L.DSP_0_ACOUT28->DSP_1_ACIN28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT28" }, "DSP_L.DSP_0_ACOUT29->DSP_1_ACIN29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT29" }, "DSP_L.DSP_0_ACOUT3->DSP_1_ACIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT3" }, "DSP_L.DSP_0_ACOUT4->DSP_1_ACIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT4" }, "DSP_L.DSP_0_ACOUT5->DSP_1_ACIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT5" }, "DSP_L.DSP_0_ACOUT6->DSP_1_ACIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT6" }, "DSP_L.DSP_0_ACOUT7->DSP_1_ACIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT7" }, "DSP_L.DSP_0_ACOUT8->DSP_1_ACIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT8" }, "DSP_L.DSP_0_ACOUT9->DSP_1_ACIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT9" }, "DSP_L.DSP_0_BCOUT0->DSP_1_BCIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT0" }, "DSP_L.DSP_0_BCOUT1->DSP_1_BCIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT1" }, "DSP_L.DSP_0_BCOUT10->DSP_1_BCIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT10" }, "DSP_L.DSP_0_BCOUT11->DSP_1_BCIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT11" }, "DSP_L.DSP_0_BCOUT12->DSP_1_BCIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT12" }, "DSP_L.DSP_0_BCOUT13->DSP_1_BCIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT13" }, "DSP_L.DSP_0_BCOUT14->DSP_1_BCIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT14" }, "DSP_L.DSP_0_BCOUT15->DSP_1_BCIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT15" }, "DSP_L.DSP_0_BCOUT16->DSP_1_BCIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT16" }, "DSP_L.DSP_0_BCOUT17->DSP_1_BCIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT17" }, "DSP_L.DSP_0_BCOUT2->DSP_1_BCIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT2" }, "DSP_L.DSP_0_BCOUT3->DSP_1_BCIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT3" }, "DSP_L.DSP_0_BCOUT4->DSP_1_BCIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT4" }, "DSP_L.DSP_0_BCOUT5->DSP_1_BCIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT5" }, "DSP_L.DSP_0_BCOUT6->DSP_1_BCIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT6" }, "DSP_L.DSP_0_BCOUT7->DSP_1_BCIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT7" }, "DSP_L.DSP_0_BCOUT8->DSP_1_BCIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT8" }, "DSP_L.DSP_0_BCOUT9->DSP_1_BCIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT9" }, "DSP_L.DSP_0_CARRYCASCOUT->DSP_1_CARRYCASCIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYCASCIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYCASCOUT" }, "DSP_L.DSP_0_CARRYOUT0->DSP_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT0" }, "DSP_L.DSP_0_CARRYOUT1->DSP_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT1" }, "DSP_L.DSP_0_CARRYOUT2->DSP_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT2" }, "DSP_L.DSP_0_CARRYOUT3->DSP_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT3" }, "DSP_L.DSP_0_MULTSIGNOUT->DSP_1_MULTSIGNIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_MULTSIGNIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_MULTSIGNOUT" }, "DSP_L.DSP_0_OVERFLOW->DSP_LOGIC_OUTS_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_OVERFLOW" }, "DSP_L.DSP_0_P0->DSP_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P0" }, "DSP_L.DSP_0_P1->DSP_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P1" }, "DSP_L.DSP_0_P10->DSP_LOGIC_OUTS_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P10" }, "DSP_L.DSP_0_P11->DSP_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P11" }, "DSP_L.DSP_0_P12->DSP_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P12" }, "DSP_L.DSP_0_P13->DSP_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P13" }, "DSP_L.DSP_0_P14->DSP_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P14" }, "DSP_L.DSP_0_P15->DSP_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P15" }, "DSP_L.DSP_0_P16->DSP_LOGIC_OUTS_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P16" }, "DSP_L.DSP_0_P17->DSP_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P17" }, "DSP_L.DSP_0_P18->DSP_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P18" }, "DSP_L.DSP_0_P19->DSP_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P19" }, "DSP_L.DSP_0_P2->DSP_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P2" }, "DSP_L.DSP_0_P20->DSP_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P20" }, "DSP_L.DSP_0_P21->DSP_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P21" }, "DSP_L.DSP_0_P22->DSP_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P22" }, "DSP_L.DSP_0_P23->DSP_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P23" }, "DSP_L.DSP_0_P24->DSP_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P24" }, "DSP_L.DSP_0_P25->DSP_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P25" }, "DSP_L.DSP_0_P26->DSP_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P26" }, "DSP_L.DSP_0_P27->DSP_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P27" }, "DSP_L.DSP_0_P28->DSP_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P28" }, "DSP_L.DSP_0_P29->DSP_LOGIC_OUTS_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P29" }, "DSP_L.DSP_0_P3->DSP_LOGIC_OUTS_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P3" }, "DSP_L.DSP_0_P30->DSP_LOGIC_OUTS_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P30" }, "DSP_L.DSP_0_P31->DSP_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P31" }, "DSP_L.DSP_0_P32->DSP_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P32" }, "DSP_L.DSP_0_P33->DSP_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P33" }, "DSP_L.DSP_0_P34->DSP_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P34" }, "DSP_L.DSP_0_P35->DSP_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P35" }, "DSP_L.DSP_0_P36->DSP_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P36" }, "DSP_L.DSP_0_P37->DSP_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P37" }, "DSP_L.DSP_0_P38->DSP_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P38" }, "DSP_L.DSP_0_P39->DSP_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P39" }, "DSP_L.DSP_0_P4->DSP_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P4" }, "DSP_L.DSP_0_P40->DSP_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P40" }, "DSP_L.DSP_0_P41->DSP_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P41" }, "DSP_L.DSP_0_P42->DSP_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P42" }, "DSP_L.DSP_0_P43->DSP_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P43" }, "DSP_L.DSP_0_P44->DSP_LOGIC_OUTS_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P44" }, "DSP_L.DSP_0_P45->DSP_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P45" }, "DSP_L.DSP_0_P46->DSP_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P46" }, "DSP_L.DSP_0_P47->DSP_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P47" }, "DSP_L.DSP_0_P5->DSP_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P5" }, "DSP_L.DSP_0_P6->DSP_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P6" }, "DSP_L.DSP_0_P7->DSP_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P7" }, "DSP_L.DSP_0_P8->DSP_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P8" }, "DSP_L.DSP_0_P9->DSP_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P9" }, "DSP_L.DSP_0_PATTERNBDETECT->DSP_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PATTERNBDETECT" }, "DSP_L.DSP_0_PATTERNDETECT->DSP_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PATTERNDETECT" }, "DSP_L.DSP_0_PCOUT0->DSP_1_PCIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT0" }, "DSP_L.DSP_0_PCOUT1->DSP_1_PCIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT1" }, "DSP_L.DSP_0_PCOUT10->DSP_1_PCIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT10" }, "DSP_L.DSP_0_PCOUT11->DSP_1_PCIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT11" }, "DSP_L.DSP_0_PCOUT12->DSP_1_PCIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT12" }, "DSP_L.DSP_0_PCOUT13->DSP_1_PCIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT13" }, "DSP_L.DSP_0_PCOUT14->DSP_1_PCIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT14" }, "DSP_L.DSP_0_PCOUT15->DSP_1_PCIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT15" }, "DSP_L.DSP_0_PCOUT16->DSP_1_PCIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT16" }, "DSP_L.DSP_0_PCOUT17->DSP_1_PCIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT17" }, "DSP_L.DSP_0_PCOUT18->DSP_1_PCIN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT18" }, "DSP_L.DSP_0_PCOUT19->DSP_1_PCIN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT19" }, "DSP_L.DSP_0_PCOUT2->DSP_1_PCIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT2" }, "DSP_L.DSP_0_PCOUT20->DSP_1_PCIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT20" }, "DSP_L.DSP_0_PCOUT21->DSP_1_PCIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT21" }, "DSP_L.DSP_0_PCOUT22->DSP_1_PCIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT22" }, "DSP_L.DSP_0_PCOUT23->DSP_1_PCIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT23" }, "DSP_L.DSP_0_PCOUT24->DSP_1_PCIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT24" }, "DSP_L.DSP_0_PCOUT25->DSP_1_PCIN25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT25" }, "DSP_L.DSP_0_PCOUT26->DSP_1_PCIN26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT26" }, "DSP_L.DSP_0_PCOUT27->DSP_1_PCIN27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT27" }, "DSP_L.DSP_0_PCOUT28->DSP_1_PCIN28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT28" }, "DSP_L.DSP_0_PCOUT29->DSP_1_PCIN29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT29" }, "DSP_L.DSP_0_PCOUT3->DSP_1_PCIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT3" }, "DSP_L.DSP_0_PCOUT30->DSP_1_PCIN30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT30" }, "DSP_L.DSP_0_PCOUT31->DSP_1_PCIN31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT31" }, "DSP_L.DSP_0_PCOUT32->DSP_1_PCIN32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT32" }, "DSP_L.DSP_0_PCOUT33->DSP_1_PCIN33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT33" }, "DSP_L.DSP_0_PCOUT34->DSP_1_PCIN34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT34" }, "DSP_L.DSP_0_PCOUT35->DSP_1_PCIN35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT35" }, "DSP_L.DSP_0_PCOUT36->DSP_1_PCIN36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT36" }, "DSP_L.DSP_0_PCOUT37->DSP_1_PCIN37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT37" }, "DSP_L.DSP_0_PCOUT38->DSP_1_PCIN38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT38" }, "DSP_L.DSP_0_PCOUT39->DSP_1_PCIN39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT39" }, "DSP_L.DSP_0_PCOUT4->DSP_1_PCIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT4" }, "DSP_L.DSP_0_PCOUT40->DSP_1_PCIN40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT40" }, "DSP_L.DSP_0_PCOUT41->DSP_1_PCIN41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT41" }, "DSP_L.DSP_0_PCOUT42->DSP_1_PCIN42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT42" }, "DSP_L.DSP_0_PCOUT43->DSP_1_PCIN43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT43" }, "DSP_L.DSP_0_PCOUT44->DSP_1_PCIN44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT44" }, "DSP_L.DSP_0_PCOUT45->DSP_1_PCIN45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT45" }, "DSP_L.DSP_0_PCOUT46->DSP_1_PCIN46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT46" }, "DSP_L.DSP_0_PCOUT47->DSP_1_PCIN47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT47" }, "DSP_L.DSP_0_PCOUT5->DSP_1_PCIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT5" }, "DSP_L.DSP_0_PCOUT6->DSP_1_PCIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT6" }, "DSP_L.DSP_0_PCOUT7->DSP_1_PCIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT7" }, "DSP_L.DSP_0_PCOUT8->DSP_1_PCIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT8" }, "DSP_L.DSP_0_PCOUT9->DSP_1_PCIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT9" }, "DSP_L.DSP_0_UNDERFLOW->DSP_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_UNDERFLOW" }, "DSP_L.DSP_1_ACOUT0->DSP_ACOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT0" }, "DSP_L.DSP_1_ACOUT1->DSP_ACOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT1" }, "DSP_L.DSP_1_ACOUT10->DSP_ACOUT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT10" }, "DSP_L.DSP_1_ACOUT11->DSP_ACOUT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT11" }, "DSP_L.DSP_1_ACOUT12->DSP_ACOUT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT12" }, "DSP_L.DSP_1_ACOUT13->DSP_ACOUT13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT13" }, "DSP_L.DSP_1_ACOUT14->DSP_ACOUT14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT14" }, "DSP_L.DSP_1_ACOUT15->DSP_ACOUT15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT15" }, "DSP_L.DSP_1_ACOUT16->DSP_ACOUT16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT16" }, "DSP_L.DSP_1_ACOUT17->DSP_ACOUT17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT17" }, "DSP_L.DSP_1_ACOUT18->DSP_ACOUT18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT18" }, "DSP_L.DSP_1_ACOUT19->DSP_ACOUT19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT19" }, "DSP_L.DSP_1_ACOUT2->DSP_ACOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT2" }, "DSP_L.DSP_1_ACOUT20->DSP_ACOUT20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT20" }, "DSP_L.DSP_1_ACOUT21->DSP_ACOUT21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT21" }, "DSP_L.DSP_1_ACOUT22->DSP_ACOUT22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT22" }, "DSP_L.DSP_1_ACOUT23->DSP_ACOUT23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT23" }, "DSP_L.DSP_1_ACOUT24->DSP_ACOUT24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT24" }, "DSP_L.DSP_1_ACOUT25->DSP_ACOUT25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT25" }, "DSP_L.DSP_1_ACOUT26->DSP_ACOUT26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT26" }, "DSP_L.DSP_1_ACOUT27->DSP_ACOUT27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT27" }, "DSP_L.DSP_1_ACOUT28->DSP_ACOUT28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT28" }, "DSP_L.DSP_1_ACOUT29->DSP_ACOUT29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT29" }, "DSP_L.DSP_1_ACOUT3->DSP_ACOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT3" }, "DSP_L.DSP_1_ACOUT4->DSP_ACOUT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT4" }, "DSP_L.DSP_1_ACOUT5->DSP_ACOUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT5" }, "DSP_L.DSP_1_ACOUT6->DSP_ACOUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT6" }, "DSP_L.DSP_1_ACOUT7->DSP_ACOUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT7" }, "DSP_L.DSP_1_ACOUT8->DSP_ACOUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT8" }, "DSP_L.DSP_1_ACOUT9->DSP_ACOUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT9" }, "DSP_L.DSP_1_BCOUT0->DSP_BCOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT0" }, "DSP_L.DSP_1_BCOUT1->DSP_BCOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT1" }, "DSP_L.DSP_1_BCOUT10->DSP_BCOUT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT10" }, "DSP_L.DSP_1_BCOUT11->DSP_BCOUT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT11" }, "DSP_L.DSP_1_BCOUT12->DSP_BCOUT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT12" }, "DSP_L.DSP_1_BCOUT13->DSP_BCOUT13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT13" }, "DSP_L.DSP_1_BCOUT14->DSP_BCOUT14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT14" }, "DSP_L.DSP_1_BCOUT15->DSP_BCOUT15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT15" }, "DSP_L.DSP_1_BCOUT16->DSP_BCOUT16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT16" }, "DSP_L.DSP_1_BCOUT17->DSP_BCOUT17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT17" }, "DSP_L.DSP_1_BCOUT2->DSP_BCOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT2" }, "DSP_L.DSP_1_BCOUT3->DSP_BCOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT3" }, "DSP_L.DSP_1_BCOUT4->DSP_BCOUT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT4" }, "DSP_L.DSP_1_BCOUT5->DSP_BCOUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT5" }, "DSP_L.DSP_1_BCOUT6->DSP_BCOUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT6" }, "DSP_L.DSP_1_BCOUT7->DSP_BCOUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT7" }, "DSP_L.DSP_1_BCOUT8->DSP_BCOUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT8" }, "DSP_L.DSP_1_BCOUT9->DSP_BCOUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT9" }, "DSP_L.DSP_1_CARRYCASCOUT->DSP_CARRYCASCOUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_CARRYCASCOUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYCASCOUT" }, "DSP_L.DSP_1_CARRYOUT0->DSP_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT0" }, "DSP_L.DSP_1_CARRYOUT1->DSP_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT1" }, "DSP_L.DSP_1_CARRYOUT2->DSP_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT2" }, "DSP_L.DSP_1_CARRYOUT3->DSP_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT3" }, "DSP_L.DSP_1_MULTSIGNOUT->DSP_MULTSIGNOUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_MULTSIGNOUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_MULTSIGNOUT" }, "DSP_L.DSP_1_OVERFLOW->DSP_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_OVERFLOW" }, "DSP_L.DSP_1_P0->DSP_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P0" }, "DSP_L.DSP_1_P1->DSP_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P1" }, "DSP_L.DSP_1_P10->DSP_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P10" }, "DSP_L.DSP_1_P11->DSP_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P11" }, "DSP_L.DSP_1_P12->DSP_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P12" }, "DSP_L.DSP_1_P13->DSP_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P13" }, "DSP_L.DSP_1_P14->DSP_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P14" }, "DSP_L.DSP_1_P15->DSP_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P15" }, "DSP_L.DSP_1_P16->DSP_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P16" }, "DSP_L.DSP_1_P17->DSP_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P17" }, "DSP_L.DSP_1_P18->DSP_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P18" }, "DSP_L.DSP_1_P19->DSP_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P19" }, "DSP_L.DSP_1_P2->DSP_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P2" }, "DSP_L.DSP_1_P20->DSP_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P20" }, "DSP_L.DSP_1_P21->DSP_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P21" }, "DSP_L.DSP_1_P22->DSP_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P22" }, "DSP_L.DSP_1_P23->DSP_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P23" }, "DSP_L.DSP_1_P24->DSP_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P24" }, "DSP_L.DSP_1_P25->DSP_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P25" }, "DSP_L.DSP_1_P26->DSP_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P26" }, "DSP_L.DSP_1_P27->DSP_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P27" }, "DSP_L.DSP_1_P28->DSP_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P28" }, "DSP_L.DSP_1_P29->DSP_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P29" }, "DSP_L.DSP_1_P3->DSP_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P3" }, "DSP_L.DSP_1_P30->DSP_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P30" }, "DSP_L.DSP_1_P31->DSP_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P31" }, "DSP_L.DSP_1_P32->DSP_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P32" }, "DSP_L.DSP_1_P33->DSP_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P33" }, "DSP_L.DSP_1_P34->DSP_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P34" }, "DSP_L.DSP_1_P35->DSP_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P35" }, "DSP_L.DSP_1_P36->DSP_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P36" }, "DSP_L.DSP_1_P37->DSP_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P37" }, "DSP_L.DSP_1_P38->DSP_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P38" }, "DSP_L.DSP_1_P39->DSP_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P39" }, "DSP_L.DSP_1_P4->DSP_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P4" }, "DSP_L.DSP_1_P40->DSP_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P40" }, "DSP_L.DSP_1_P41->DSP_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P41" }, "DSP_L.DSP_1_P42->DSP_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P42" }, "DSP_L.DSP_1_P43->DSP_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P43" }, "DSP_L.DSP_1_P44->DSP_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P44" }, "DSP_L.DSP_1_P45->DSP_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P45" }, "DSP_L.DSP_1_P46->DSP_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P46" }, "DSP_L.DSP_1_P47->DSP_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P47" }, "DSP_L.DSP_1_P5->DSP_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P5" }, "DSP_L.DSP_1_P6->DSP_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P6" }, "DSP_L.DSP_1_P7->DSP_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P7" }, "DSP_L.DSP_1_P8->DSP_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P8" }, "DSP_L.DSP_1_P9->DSP_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P9" }, "DSP_L.DSP_1_PATTERNBDETECT->DSP_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PATTERNBDETECT" }, "DSP_L.DSP_1_PATTERNDETECT->DSP_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PATTERNDETECT" }, "DSP_L.DSP_1_PCOUT0->DSP_PCOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT0" }, "DSP_L.DSP_1_PCOUT1->DSP_PCOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT1" }, "DSP_L.DSP_1_PCOUT10->DSP_PCOUT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT10" }, "DSP_L.DSP_1_PCOUT11->DSP_PCOUT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT11" }, "DSP_L.DSP_1_PCOUT12->DSP_PCOUT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT12" }, "DSP_L.DSP_1_PCOUT13->DSP_PCOUT13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT13" }, "DSP_L.DSP_1_PCOUT14->DSP_PCOUT14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT14" }, "DSP_L.DSP_1_PCOUT15->DSP_PCOUT15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT15" }, "DSP_L.DSP_1_PCOUT16->DSP_PCOUT16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT16" }, "DSP_L.DSP_1_PCOUT17->DSP_PCOUT17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT17" }, "DSP_L.DSP_1_PCOUT18->DSP_PCOUT18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT18" }, "DSP_L.DSP_1_PCOUT19->DSP_PCOUT19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT19" }, "DSP_L.DSP_1_PCOUT2->DSP_PCOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT2" }, "DSP_L.DSP_1_PCOUT20->DSP_PCOUT20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT20" }, "DSP_L.DSP_1_PCOUT21->DSP_PCOUT21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT21" }, "DSP_L.DSP_1_PCOUT22->DSP_PCOUT22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT22" }, "DSP_L.DSP_1_PCOUT23->DSP_PCOUT23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT23" }, "DSP_L.DSP_1_PCOUT24->DSP_PCOUT24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT24" }, "DSP_L.DSP_1_PCOUT25->DSP_PCOUT25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT25" }, "DSP_L.DSP_1_PCOUT26->DSP_PCOUT26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT26" }, "DSP_L.DSP_1_PCOUT27->DSP_PCOUT27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT27" }, "DSP_L.DSP_1_PCOUT28->DSP_PCOUT28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT28" }, "DSP_L.DSP_1_PCOUT29->DSP_PCOUT29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT29" }, "DSP_L.DSP_1_PCOUT3->DSP_PCOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT3" }, "DSP_L.DSP_1_PCOUT30->DSP_PCOUT30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT30" }, "DSP_L.DSP_1_PCOUT31->DSP_PCOUT31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT31" }, "DSP_L.DSP_1_PCOUT32->DSP_PCOUT32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT32" }, "DSP_L.DSP_1_PCOUT33->DSP_PCOUT33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT33" }, "DSP_L.DSP_1_PCOUT34->DSP_PCOUT34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT34" }, "DSP_L.DSP_1_PCOUT35->DSP_PCOUT35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT35" }, "DSP_L.DSP_1_PCOUT36->DSP_PCOUT36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT36" }, "DSP_L.DSP_1_PCOUT37->DSP_PCOUT37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT37" }, "DSP_L.DSP_1_PCOUT38->DSP_PCOUT38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT38" }, "DSP_L.DSP_1_PCOUT39->DSP_PCOUT39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT39" }, "DSP_L.DSP_1_PCOUT4->DSP_PCOUT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT4" }, "DSP_L.DSP_1_PCOUT40->DSP_PCOUT40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT40" }, "DSP_L.DSP_1_PCOUT41->DSP_PCOUT41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT41" }, "DSP_L.DSP_1_PCOUT42->DSP_PCOUT42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT42" }, "DSP_L.DSP_1_PCOUT43->DSP_PCOUT43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT43" }, "DSP_L.DSP_1_PCOUT44->DSP_PCOUT44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT44" }, "DSP_L.DSP_1_PCOUT45->DSP_PCOUT45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT45" }, "DSP_L.DSP_1_PCOUT46->DSP_PCOUT46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT46" }, "DSP_L.DSP_1_PCOUT47->DSP_PCOUT47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT47" }, "DSP_L.DSP_1_PCOUT5->DSP_PCOUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT5" }, "DSP_L.DSP_1_PCOUT6->DSP_PCOUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT6" }, "DSP_L.DSP_1_PCOUT7->DSP_PCOUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT7" }, "DSP_L.DSP_1_PCOUT8->DSP_PCOUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT8" }, "DSP_L.DSP_1_PCOUT9->DSP_PCOUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT9" }, "DSP_L.DSP_1_UNDERFLOW->DSP_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_UNDERFLOW" }, "DSP_L.DSP_BYP0_0->DSP_0_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_0" }, "DSP_L.DSP_BYP0_1->DSP_0_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_1" }, "DSP_L.DSP_BYP0_2->DSP_0_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_2" }, "DSP_L.DSP_BYP0_3->DSP_1_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_3" }, "DSP_L.DSP_BYP0_4->DSP_1_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_4" }, "DSP_L.DSP_BYP1_0->DSP_0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_0" }, "DSP_L.DSP_BYP1_1->DSP_0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_1" }, "DSP_L.DSP_BYP1_2->DSP_0_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_2" }, "DSP_L.DSP_BYP1_3->DSP_0_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_3" }, "DSP_L.DSP_BYP1_4->DSP_0_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_4" }, "DSP_L.DSP_BYP2_0->DSP_0_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_0" }, "DSP_L.DSP_BYP2_1->DSP_1_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_1" }, "DSP_L.DSP_BYP2_2->DSP_0_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_2" }, "DSP_L.DSP_BYP2_3->DSP_0_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_3" }, "DSP_L.DSP_BYP2_4->DSP_1_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_4" }, "DSP_L.DSP_BYP3_0->DSP_0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_0" }, "DSP_L.DSP_BYP3_1->DSP_0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_1" }, "DSP_L.DSP_BYP3_2->DSP_0_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_2" }, "DSP_L.DSP_BYP3_3->DSP_0_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_3" }, "DSP_L.DSP_BYP3_4->DSP_0_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_4" }, "DSP_L.DSP_BYP4_0->DSP_0_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_0" }, "DSP_L.DSP_BYP4_1->DSP_0_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_1" }, "DSP_L.DSP_BYP4_2->DSP_1_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_2" }, "DSP_L.DSP_BYP4_3->DSP_1_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_3" }, "DSP_L.DSP_BYP4_4->DSP_1_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_4" }, "DSP_L.DSP_BYP5_0->DSP_0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_0" }, "DSP_L.DSP_BYP5_1->DSP_0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_1" }, "DSP_L.DSP_BYP5_2->DSP_0_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_2" }, "DSP_L.DSP_BYP5_3->DSP_0_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_3" }, "DSP_L.DSP_BYP5_4->DSP_0_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_4" }, "DSP_L.DSP_BYP6_0->DSP_0_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_0" }, "DSP_L.DSP_BYP6_1->DSP_0_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_1" }, "DSP_L.DSP_BYP6_2->DSP_0_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_2" }, "DSP_L.DSP_BYP6_3->DSP_0_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_3" }, "DSP_L.DSP_BYP6_4->DSP_1_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_4" }, "DSP_L.DSP_BYP7_0->DSP_0_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_0" }, "DSP_L.DSP_BYP7_1->DSP_0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_1" }, "DSP_L.DSP_BYP7_2->DSP_0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_2" }, "DSP_L.DSP_BYP7_3->DSP_0_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_3" }, "DSP_L.DSP_BYP7_4->DSP_0_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_4" }, "DSP_L.DSP_CLK0_1->DSP_0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CLK0_1" }, "DSP_L.DSP_CLK0_3->DSP_1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CLK0_3" }, "DSP_L.DSP_CTRL0_0->DSP_0_RSTP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_0" }, "DSP_L.DSP_CTRL0_1->DSP_0_RSTC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_1" }, "DSP_L.DSP_CTRL0_2->DSP_0_RSTB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_2" }, "DSP_L.DSP_CTRL0_3->DSP_1_RSTC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_3" }, "DSP_L.DSP_CTRL0_4->DSP_1_RSTP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_4" }, "DSP_L.DSP_CTRL1_0->DSP_0_RSTA": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTA", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_0" }, "DSP_L.DSP_CTRL1_1->DSP_0_RSTM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_1" }, "DSP_L.DSP_CTRL1_2->DSP_1_RSTA": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTA", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_2" }, "DSP_L.DSP_CTRL1_3->DSP_1_RSTM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_3" }, "DSP_L.DSP_CTRL1_4->DSP_1_RSTB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_4" }, "DSP_L.DSP_FAN0_0->DSP_0_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_0" }, "DSP_L.DSP_FAN0_1->DSP_0_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_1" }, "DSP_L.DSP_FAN0_2->DSP_1_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_2" }, "DSP_L.DSP_FAN0_3->DSP_1_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_3" }, "DSP_L.DSP_FAN0_4->DSP_1_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_4" }, "DSP_L.DSP_FAN1_0->DSP_1_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_0" }, "DSP_L.DSP_FAN1_1->DSP_1_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_1" }, "DSP_L.DSP_FAN1_2->DSP_0_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_2" }, "DSP_L.DSP_FAN1_3->DSP_0_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_3" }, "DSP_L.DSP_FAN2_0->DSP_0_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_0" }, "DSP_L.DSP_FAN2_2->DSP_1_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_2" }, "DSP_L.DSP_FAN2_3->DSP_1_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_3" }, "DSP_L.DSP_FAN2_4->DSP_1_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_4" }, "DSP_L.DSP_FAN3_0->DSP_1_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_0" }, "DSP_L.DSP_FAN3_1->DSP_1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_1" }, "DSP_L.DSP_FAN3_2->DSP_1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_2" }, "DSP_L.DSP_FAN3_3->DSP_1_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_3" }, "DSP_L.DSP_FAN3_4->DSP_1_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_4" }, "DSP_L.DSP_FAN4_0->DSP_1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_0" }, "DSP_L.DSP_FAN4_1->DSP_1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_1" }, "DSP_L.DSP_FAN4_2->DSP_1_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_2" }, "DSP_L.DSP_FAN4_3->DSP_1_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_3" }, "DSP_L.DSP_FAN4_4->DSP_1_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_4" }, "DSP_L.DSP_FAN5_0->DSP_1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_0" }, "DSP_L.DSP_FAN5_1->DSP_1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_1" }, "DSP_L.DSP_FAN5_2->DSP_1_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_2" }, "DSP_L.DSP_FAN5_3->DSP_1_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_3" }, "DSP_L.DSP_FAN5_4->DSP_1_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_4" }, "DSP_L.DSP_FAN6_0->DSP_1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_0" }, "DSP_L.DSP_FAN6_1->DSP_1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_1" }, "DSP_L.DSP_FAN6_2->DSP_1_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_2" }, "DSP_L.DSP_FAN6_3->DSP_1_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_3" }, "DSP_L.DSP_FAN6_4->DSP_1_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_4" }, "DSP_L.DSP_FAN7_0->DSP_1_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_0" }, "DSP_L.DSP_FAN7_1->DSP_0_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_1" }, "DSP_L.DSP_FAN7_2->DSP_0_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_2" }, "DSP_L.DSP_FAN7_3->DSP_1_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_3" }, "DSP_L.DSP_FAN7_4->DSP_1_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_4" }, "DSP_L.DSP_GND_L->DSP_0_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_IMUX0_0->DSP_1_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_0" }, "DSP_L.DSP_IMUX0_1->DSP_0_CEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_1" }, "DSP_L.DSP_IMUX0_2->DSP_0_CECARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CECARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_2" }, "DSP_L.DSP_IMUX0_3->DSP_1_B15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_3" }, "DSP_L.DSP_IMUX0_4->DSP_1_ALUMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_4" }, "DSP_L.DSP_IMUX10_0->DSP_1_C21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_0" }, "DSP_L.DSP_IMUX10_1->DSP_1_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_1" }, "DSP_L.DSP_IMUX10_2->DSP_1_C29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_2" }, "DSP_L.DSP_IMUX10_3->DSP_1_C33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_3" }, "DSP_L.DSP_IMUX10_4->DSP_1_C39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_4" }, "DSP_L.DSP_IMUX11_0->DSP_1_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_0" }, "DSP_L.DSP_IMUX11_1->DSP_1_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_1" }, "DSP_L.DSP_IMUX11_2->DSP_1_A9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_2" }, "DSP_L.DSP_IMUX11_3->DSP_1_CECTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CECTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_3" }, "DSP_L.DSP_IMUX11_4->DSP_1_C46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_4" }, "DSP_L.DSP_IMUX12_0->DSP_1_C22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_0" }, "DSP_L.DSP_IMUX12_1->DSP_1_C26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_1" }, "DSP_L.DSP_IMUX12_2->DSP_0_OPMODE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_2" }, "DSP_L.DSP_IMUX12_3->DSP_1_C34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_3" }, "DSP_L.DSP_IMUX12_4->DSP_1_C38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_4" }, "DSP_L.DSP_IMUX13_0->DSP_1_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_0" }, "DSP_L.DSP_IMUX13_1->DSP_1_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_1" }, "DSP_L.DSP_IMUX13_2->DSP_1_A10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_2" }, "DSP_L.DSP_IMUX13_3->DSP_0_ALUMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_3" }, "DSP_L.DSP_IMUX13_4->DSP_1_C18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_4" }, "DSP_L.DSP_IMUX14_0->DSP_1_B0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_0" }, "DSP_L.DSP_IMUX14_1->DSP_1_C24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_1" }, "DSP_L.DSP_IMUX14_2->DSP_1_B8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_2" }, "DSP_L.DSP_IMUX14_3->DSP_0_CARRYINSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_3" }, "DSP_L.DSP_IMUX14_4->DSP_1_RSTCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_4" }, "DSP_L.DSP_IMUX15_0->DSP_1_A0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_0" }, "DSP_L.DSP_IMUX15_1->DSP_1_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_1" }, "DSP_L.DSP_IMUX15_2->DSP_1_A8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_2" }, "DSP_L.DSP_IMUX15_3->DSP_1_CARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_3" }, "DSP_L.DSP_IMUX15_4->DSP_1_RSTALLCARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTALLCARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_4" }, "DSP_L.DSP_IMUX16_0->DSP_0_C41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_0" }, "DSP_L.DSP_IMUX16_1->DSP_0_B7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_1" }, "DSP_L.DSP_IMUX16_2->DSP_0_B11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_2" }, "DSP_L.DSP_IMUX16_3->DSP_1_CEB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_3" }, "DSP_L.DSP_IMUX16_4->DSP_1_OPMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_4" }, "DSP_L.DSP_IMUX17_0->DSP_0_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_0" }, "DSP_L.DSP_IMUX17_1->DSP_0_A7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_1" }, "DSP_L.DSP_IMUX17_2->DSP_0_A11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_2" }, "DSP_L.DSP_IMUX17_3->DSP_1_CEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_3" }, "DSP_L.DSP_IMUX17_4->DSP_1_OPMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_4" }, "DSP_L.DSP_IMUX18_0->DSP_0_C21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_0" }, "DSP_L.DSP_IMUX18_1->DSP_0_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_1" }, "DSP_L.DSP_IMUX18_2->DSP_0_B9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_2" }, "DSP_L.DSP_IMUX18_3->DSP_0_C33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_3" }, "DSP_L.DSP_IMUX18_4->DSP_0_C39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_4" }, "DSP_L.DSP_IMUX19_0->DSP_0_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_0" }, "DSP_L.DSP_IMUX19_1->DSP_0_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_1" }, "DSP_L.DSP_IMUX19_2->DSP_0_A9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_2" }, "DSP_L.DSP_IMUX19_3->DSP_1_CEM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_3" }, "DSP_L.DSP_IMUX19_4->DSP_0_C46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_4" }, "DSP_L.DSP_IMUX1_0->DSP_0_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_0" }, "DSP_L.DSP_IMUX1_1->DSP_0_CEB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_1" }, "DSP_L.DSP_IMUX1_2->DSP_0_CEM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_2" }, "DSP_L.DSP_IMUX1_3->DSP_1_B13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_3" }, "DSP_L.DSP_IMUX1_4->DSP_0_C19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_4" }, "DSP_L.DSP_IMUX20_0->DSP_0_C22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_0" }, "DSP_L.DSP_IMUX20_1->DSP_0_C26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_1" }, "DSP_L.DSP_IMUX20_2->DSP_0_OPMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_2" }, "DSP_L.DSP_IMUX20_3->DSP_0_C34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_3" }, "DSP_L.DSP_IMUX20_4->DSP_0_C38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_4" }, "DSP_L.DSP_IMUX21_0->DSP_0_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_0" }, "DSP_L.DSP_IMUX21_1->DSP_0_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_1" }, "DSP_L.DSP_IMUX21_2->DSP_0_A10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_2" }, "DSP_L.DSP_IMUX21_3->DSP_0_ALUMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_3" }, "DSP_L.DSP_IMUX21_4->DSP_0_C18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_4" }, "DSP_L.DSP_IMUX22_0->DSP_0_B0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_0" }, "DSP_L.DSP_IMUX22_1->DSP_0_C24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_1" }, "DSP_L.DSP_IMUX22_2->DSP_0_B8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_2" }, "DSP_L.DSP_IMUX22_3->DSP_1_C32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_3" }, "DSP_L.DSP_IMUX22_4->DSP_1_RSTALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_4" }, "DSP_L.DSP_IMUX23_0->DSP_0_A0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_0" }, "DSP_L.DSP_IMUX23_1->DSP_0_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_1" }, "DSP_L.DSP_IMUX23_2->DSP_0_A8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_2" }, "DSP_L.DSP_IMUX23_3->DSP_0_CARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_3" }, "DSP_L.DSP_IMUX23_4->DSP_1_RSTINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_4" }, "DSP_L.DSP_IMUX24_0->DSP_1_C23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_0" }, "DSP_L.DSP_IMUX24_1->DSP_1_C27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_1" }, "DSP_L.DSP_IMUX24_2->DSP_1_C31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_2" }, "DSP_L.DSP_IMUX24_3->DSP_1_C35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_3" }, "DSP_L.DSP_IMUX24_4->DSP_1_C37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_4" }, "DSP_L.DSP_IMUX25_0->DSP_1_C43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_0" }, "DSP_L.DSP_IMUX25_1->DSP_1_C7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_1" }, "DSP_L.DSP_IMUX25_2->DSP_1_C11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_2" }, "DSP_L.DSP_IMUX25_3->DSP_1_C15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_3" }, "DSP_L.DSP_IMUX25_4->DSP_1_C47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_4" }, "DSP_L.DSP_IMUX26_0->DSP_1_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_0" }, "DSP_L.DSP_IMUX26_1->DSP_1_C25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_1" }, "DSP_L.DSP_IMUX26_2->DSP_1_CEP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_2" }, "DSP_L.DSP_IMUX26_3->DSP_1_CECARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CECARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_3" }, "DSP_L.DSP_IMUX26_4->DSP_1_C44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_4" }, "DSP_L.DSP_IMUX27_0->DSP_1_C40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_0" }, "DSP_L.DSP_IMUX27_1->DSP_1_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_1" }, "DSP_L.DSP_IMUX27_2->DSP_0_OPMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_2" }, "DSP_L.DSP_IMUX27_3->DSP_1_C13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_3" }, "DSP_L.DSP_IMUX27_4->DSP_1_C17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_4" }, "DSP_L.DSP_IMUX28_0->DSP_1_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_0" }, "DSP_L.DSP_IMUX28_1->DSP_1_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_1" }, "DSP_L.DSP_IMUX28_2->DSP_1_C30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_2" }, "DSP_L.DSP_IMUX28_3->DSP_1_OPMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_3" }, "DSP_L.DSP_IMUX28_4->DSP_1_CARRYINSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_4" }, "DSP_L.DSP_IMUX29_0->DSP_1_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_0" }, "DSP_L.DSP_IMUX29_1->DSP_1_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_1" }, "DSP_L.DSP_IMUX29_2->DSP_1_C10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_2" }, "DSP_L.DSP_IMUX29_3->DSP_1_C14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_3" }, "DSP_L.DSP_IMUX29_4->DSP_1_C45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_4" }, "DSP_L.DSP_IMUX2_0->DSP_1_C42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_0" }, "DSP_L.DSP_IMUX2_1->DSP_0_RSTALLCARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTALLCARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_1" }, "DSP_L.DSP_IMUX2_2->DSP_0_C29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_2" }, "DSP_L.DSP_IMUX2_3->DSP_0_B15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_3" }, "DSP_L.DSP_IMUX2_4->DSP_1_B17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_4" }, "DSP_L.DSP_IMUX30_0->DSP_1_C20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_0" }, "DSP_L.DSP_IMUX30_1->DSP_1_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_1" }, "DSP_L.DSP_IMUX30_2->DSP_0_OPMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_2" }, "DSP_L.DSP_IMUX30_3->DSP_0_CARRYINSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_3" }, "DSP_L.DSP_IMUX30_4->DSP_1_C36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_4" }, "DSP_L.DSP_IMUX31_0->DSP_1_C0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_0" }, "DSP_L.DSP_IMUX31_1->DSP_1_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_1" }, "DSP_L.DSP_IMUX31_2->DSP_1_C8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_2" }, "DSP_L.DSP_IMUX31_3->DSP_1_C12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_3" }, "DSP_L.DSP_IMUX31_4->DSP_1_C16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_4" }, "DSP_L.DSP_IMUX32_0->DSP_0_C23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_0" }, "DSP_L.DSP_IMUX32_1->DSP_0_C27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_1" }, "DSP_L.DSP_IMUX32_2->DSP_0_C31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_2" }, "DSP_L.DSP_IMUX32_3->DSP_0_C35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_3" }, "DSP_L.DSP_IMUX32_4->DSP_0_C37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_4" }, "DSP_L.DSP_IMUX33_0->DSP_0_C43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_0" }, "DSP_L.DSP_IMUX33_1->DSP_0_C7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_1" }, "DSP_L.DSP_IMUX33_2->DSP_0_C11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_2" }, "DSP_L.DSP_IMUX33_3->DSP_0_C15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_3" }, "DSP_L.DSP_IMUX33_4->DSP_0_C47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_4" }, "DSP_L.DSP_IMUX34_0->DSP_0_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_0" }, "DSP_L.DSP_IMUX34_1->DSP_0_C25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_1" }, "DSP_L.DSP_IMUX34_2->DSP_0_CEP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_2" }, "DSP_L.DSP_IMUX34_3->DSP_1_CEC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_3" }, "DSP_L.DSP_IMUX34_4->DSP_0_C44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_4" }, "DSP_L.DSP_IMUX35_0->DSP_0_C40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_0" }, "DSP_L.DSP_IMUX35_1->DSP_0_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_1" }, "DSP_L.DSP_IMUX35_2->DSP_0_OPMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_2" }, "DSP_L.DSP_IMUX35_3->DSP_0_C13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_3" }, "DSP_L.DSP_IMUX35_4->DSP_0_C17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_4" }, "DSP_L.DSP_IMUX36_0->DSP_0_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_0" }, "DSP_L.DSP_IMUX36_1->DSP_0_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_1" }, "DSP_L.DSP_IMUX36_2->DSP_0_B10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_2" }, "DSP_L.DSP_IMUX36_3->DSP_1_OPMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_3" }, "DSP_L.DSP_IMUX36_4->DSP_1_CARRYINSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_4" }, "DSP_L.DSP_IMUX37_0->DSP_0_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_0" }, "DSP_L.DSP_IMUX37_1->DSP_0_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_1" }, "DSP_L.DSP_IMUX37_2->DSP_0_C10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_2" }, "DSP_L.DSP_IMUX37_3->DSP_0_C14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_3" }, "DSP_L.DSP_IMUX37_4->DSP_0_C45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_4" }, "DSP_L.DSP_IMUX38_0->DSP_0_C20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_0" }, "DSP_L.DSP_IMUX38_1->DSP_0_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_1" }, "DSP_L.DSP_IMUX38_2->DSP_0_OPMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_2" }, "DSP_L.DSP_IMUX38_3->DSP_0_C32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_3" }, "DSP_L.DSP_IMUX38_4->DSP_0_C36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_4" }, "DSP_L.DSP_IMUX39_0->DSP_0_C0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_0" }, "DSP_L.DSP_IMUX39_1->DSP_0_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_1" }, "DSP_L.DSP_IMUX39_2->DSP_0_C8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_2" }, "DSP_L.DSP_IMUX39_3->DSP_0_C12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_3" }, "DSP_L.DSP_IMUX39_4->DSP_0_C16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_4" }, "DSP_L.DSP_IMUX3_0->DSP_0_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_0" }, "DSP_L.DSP_IMUX3_1->DSP_0_RSTALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_1" }, "DSP_L.DSP_IMUX3_2->DSP_0_C9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_2" }, "DSP_L.DSP_IMUX3_3->DSP_0_B13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_3" }, "DSP_L.DSP_IMUX3_4->DSP_0_B17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_4" }, "DSP_L.DSP_IMUX40_0->DSP_0_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_0" }, "DSP_L.DSP_IMUX40_1->DSP_0_CEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_1" }, "DSP_L.DSP_IMUX40_2->DSP_0_CEC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_2" }, "DSP_L.DSP_IMUX40_3->DSP_1_B14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_3" }, "DSP_L.DSP_IMUX40_4->DSP_1_ALUMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_4" }, "DSP_L.DSP_IMUX41_0->DSP_1_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_0" }, "DSP_L.DSP_IMUX41_1->DSP_0_CEB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_1" }, "DSP_L.DSP_IMUX41_2->DSP_0_CECTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CECTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_2" }, "DSP_L.DSP_IMUX41_3->DSP_1_B12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_3" }, "DSP_L.DSP_IMUX41_4->DSP_1_C19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_4" }, "DSP_L.DSP_IMUX42_0->DSP_0_C42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_0" }, "DSP_L.DSP_IMUX42_1->DSP_0_RSTINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_1" }, "DSP_L.DSP_IMUX42_2->DSP_1_B9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_2" }, "DSP_L.DSP_IMUX42_3->DSP_0_B14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_3" }, "DSP_L.DSP_IMUX42_4->DSP_1_B16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_4" }, "DSP_L.DSP_IMUX43_0->DSP_1_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_0" }, "DSP_L.DSP_IMUX43_1->DSP_0_RSTCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_1" }, "DSP_L.DSP_IMUX43_2->DSP_1_C9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_2" }, "DSP_L.DSP_IMUX43_3->DSP_0_B12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_3" }, "DSP_L.DSP_IMUX43_4->DSP_0_B16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_4" }, "DSP_L.DSP_IMUX44_0->DSP_1_A22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_0" }, "DSP_L.DSP_IMUX44_1->DSP_1_A26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_1" }, "DSP_L.DSP_IMUX44_2->DSP_1_B10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_2" }, "DSP_L.DSP_IMUX44_3->DSP_1_A14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_3" }, "DSP_L.DSP_IMUX44_4->DSP_1_A18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_4" }, "DSP_L.DSP_IMUX45_0->DSP_1_A20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_0" }, "DSP_L.DSP_IMUX45_1->DSP_1_A24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_1" }, "DSP_L.DSP_IMUX45_2->DSP_1_A28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_2" }, "DSP_L.DSP_IMUX45_3->DSP_1_A12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_3" }, "DSP_L.DSP_IMUX45_4->DSP_1_A16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_4" }, "DSP_L.DSP_IMUX46_0->DSP_0_A22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_0" }, "DSP_L.DSP_IMUX46_1->DSP_0_A26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_1" }, "DSP_L.DSP_IMUX46_2->DSP_1_C28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_2" }, "DSP_L.DSP_IMUX46_3->DSP_0_A14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_3" }, "DSP_L.DSP_IMUX46_4->DSP_0_A18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_4" }, "DSP_L.DSP_IMUX47_0->DSP_0_A20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_0" }, "DSP_L.DSP_IMUX47_1->DSP_0_A24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_1" }, "DSP_L.DSP_IMUX47_2->DSP_0_A28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_2" }, "DSP_L.DSP_IMUX47_3->DSP_0_A12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_3" }, "DSP_L.DSP_IMUX47_4->DSP_0_A16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_4" }, "DSP_L.DSP_IMUX4_0->DSP_1_A23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_0" }, "DSP_L.DSP_IMUX4_1->DSP_1_A27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_1" }, "DSP_L.DSP_IMUX4_2->DSP_0_C30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_2" }, "DSP_L.DSP_IMUX4_3->DSP_1_A15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_3" }, "DSP_L.DSP_IMUX4_4->DSP_1_A19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_4" }, "DSP_L.DSP_IMUX5_0->DSP_1_A21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_0" }, "DSP_L.DSP_IMUX5_1->DSP_1_A25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_1" }, "DSP_L.DSP_IMUX5_2->DSP_1_A29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_2" }, "DSP_L.DSP_IMUX5_3->DSP_1_A13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_3" }, "DSP_L.DSP_IMUX5_4->DSP_1_A17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_4" }, "DSP_L.DSP_IMUX6_0->DSP_0_A23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_0" }, "DSP_L.DSP_IMUX6_1->DSP_0_A27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_1" }, "DSP_L.DSP_IMUX6_2->DSP_0_C28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_2" }, "DSP_L.DSP_IMUX6_3->DSP_0_A15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_3" }, "DSP_L.DSP_IMUX6_4->DSP_0_A19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_4" }, "DSP_L.DSP_IMUX7_0->DSP_0_A21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_0" }, "DSP_L.DSP_IMUX7_1->DSP_0_A25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_1" }, "DSP_L.DSP_IMUX7_2->DSP_0_A29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_2" }, "DSP_L.DSP_IMUX7_3->DSP_0_A13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_3" }, "DSP_L.DSP_IMUX7_4->DSP_0_A17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_4" }, "DSP_L.DSP_IMUX8_0->DSP_1_C41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_0" }, "DSP_L.DSP_IMUX8_1->DSP_1_B7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_1" }, "DSP_L.DSP_IMUX8_2->DSP_1_B11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_2" }, "DSP_L.DSP_IMUX8_3->DSP_1_CEB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_3" }, "DSP_L.DSP_IMUX8_4->DSP_1_OPMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_4" }, "DSP_L.DSP_IMUX9_0->DSP_1_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_0" }, "DSP_L.DSP_IMUX9_1->DSP_1_A7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_1" }, "DSP_L.DSP_IMUX9_2->DSP_1_A11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_2" }, "DSP_L.DSP_IMUX9_3->DSP_1_CEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_3" }, "DSP_L.DSP_IMUX9_4->DSP_1_OPMODE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_4" }, "DSP_L.DSP_VCC_L->DSP_0_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" } }, @@ -5564,423 +14298,4176 @@ "name": "X0Y0", "prefix": "DSP48", "site_pins": { - "A0": "DSP_0_A0", - "A1": "DSP_0_A1", - "A10": "DSP_0_A10", - "A11": "DSP_0_A11", - "A12": "DSP_0_A12", - "A13": "DSP_0_A13", - "A14": "DSP_0_A14", - "A15": "DSP_0_A15", - "A16": "DSP_0_A16", - "A17": "DSP_0_A17", - "A18": "DSP_0_A18", - "A19": "DSP_0_A19", - "A2": "DSP_0_A2", - "A20": "DSP_0_A20", - "A21": "DSP_0_A21", - "A22": "DSP_0_A22", - "A23": "DSP_0_A23", - "A24": "DSP_0_A24", - "A25": "DSP_0_A25", - "A26": "DSP_0_A26", - "A27": "DSP_0_A27", - "A28": "DSP_0_A28", - "A29": "DSP_0_A29", - "A3": "DSP_0_A3", - "A4": "DSP_0_A4", - "A5": "DSP_0_A5", - "A6": "DSP_0_A6", - "A7": "DSP_0_A7", - "A8": "DSP_0_A8", - "A9": "DSP_0_A9", - "ACIN0": "DSP_0_ACIN0", - "ACIN1": "DSP_0_ACIN1", - "ACIN10": "DSP_0_ACIN10", - "ACIN11": "DSP_0_ACIN11", - "ACIN12": "DSP_0_ACIN12", - "ACIN13": "DSP_0_ACIN13", - "ACIN14": "DSP_0_ACIN14", - "ACIN15": "DSP_0_ACIN15", - "ACIN16": "DSP_0_ACIN16", - "ACIN17": "DSP_0_ACIN17", - "ACIN18": "DSP_0_ACIN18", - "ACIN19": "DSP_0_ACIN19", - "ACIN2": "DSP_0_ACIN2", - "ACIN20": "DSP_0_ACIN20", - "ACIN21": "DSP_0_ACIN21", - "ACIN22": "DSP_0_ACIN22", - "ACIN23": "DSP_0_ACIN23", - "ACIN24": "DSP_0_ACIN24", - "ACIN25": "DSP_0_ACIN25", - "ACIN26": "DSP_0_ACIN26", - "ACIN27": "DSP_0_ACIN27", - "ACIN28": "DSP_0_ACIN28", - "ACIN29": "DSP_0_ACIN29", - "ACIN3": "DSP_0_ACIN3", - "ACIN4": "DSP_0_ACIN4", - "ACIN5": "DSP_0_ACIN5", - "ACIN6": "DSP_0_ACIN6", - "ACIN7": "DSP_0_ACIN7", - "ACIN8": "DSP_0_ACIN8", - "ACIN9": "DSP_0_ACIN9", - "ACOUT0": "DSP_0_ACOUT0", - "ACOUT1": "DSP_0_ACOUT1", - "ACOUT10": "DSP_0_ACOUT10", - "ACOUT11": "DSP_0_ACOUT11", - "ACOUT12": "DSP_0_ACOUT12", - "ACOUT13": "DSP_0_ACOUT13", - "ACOUT14": "DSP_0_ACOUT14", - "ACOUT15": "DSP_0_ACOUT15", - "ACOUT16": "DSP_0_ACOUT16", - "ACOUT17": "DSP_0_ACOUT17", - "ACOUT18": "DSP_0_ACOUT18", - "ACOUT19": "DSP_0_ACOUT19", - "ACOUT2": "DSP_0_ACOUT2", - "ACOUT20": "DSP_0_ACOUT20", - "ACOUT21": "DSP_0_ACOUT21", - "ACOUT22": "DSP_0_ACOUT22", - "ACOUT23": "DSP_0_ACOUT23", - "ACOUT24": "DSP_0_ACOUT24", - "ACOUT25": "DSP_0_ACOUT25", - "ACOUT26": "DSP_0_ACOUT26", - "ACOUT27": "DSP_0_ACOUT27", - "ACOUT28": "DSP_0_ACOUT28", - "ACOUT29": "DSP_0_ACOUT29", - "ACOUT3": "DSP_0_ACOUT3", - "ACOUT4": "DSP_0_ACOUT4", - "ACOUT5": "DSP_0_ACOUT5", - "ACOUT6": "DSP_0_ACOUT6", - "ACOUT7": "DSP_0_ACOUT7", - "ACOUT8": "DSP_0_ACOUT8", - "ACOUT9": "DSP_0_ACOUT9", - "ALUMODE0": "DSP_0_ALUMODE0", - "ALUMODE1": "DSP_0_ALUMODE1", - "ALUMODE2": "DSP_0_ALUMODE2", - "ALUMODE3": "DSP_0_ALUMODE3", - "B0": "DSP_0_B0", - "B1": "DSP_0_B1", - "B10": "DSP_0_B10", - "B11": "DSP_0_B11", - "B12": "DSP_0_B12", - "B13": "DSP_0_B13", - "B14": "DSP_0_B14", - "B15": "DSP_0_B15", - "B16": "DSP_0_B16", - "B17": "DSP_0_B17", - "B2": "DSP_0_B2", - "B3": "DSP_0_B3", - "B4": "DSP_0_B4", - "B5": "DSP_0_B5", - "B6": "DSP_0_B6", - "B7": "DSP_0_B7", - "B8": "DSP_0_B8", - "B9": "DSP_0_B9", - "BCIN0": "DSP_0_BCIN0", - "BCIN1": "DSP_0_BCIN1", - "BCIN10": "DSP_0_BCIN10", - "BCIN11": "DSP_0_BCIN11", - "BCIN12": "DSP_0_BCIN12", - "BCIN13": "DSP_0_BCIN13", - "BCIN14": "DSP_0_BCIN14", - "BCIN15": "DSP_0_BCIN15", - "BCIN16": "DSP_0_BCIN16", - "BCIN17": "DSP_0_BCIN17", - "BCIN2": "DSP_0_BCIN2", - "BCIN3": "DSP_0_BCIN3", - "BCIN4": "DSP_0_BCIN4", - "BCIN5": "DSP_0_BCIN5", - "BCIN6": "DSP_0_BCIN6", - "BCIN7": "DSP_0_BCIN7", - "BCIN8": "DSP_0_BCIN8", - "BCIN9": "DSP_0_BCIN9", - "BCOUT0": "DSP_0_BCOUT0", - "BCOUT1": "DSP_0_BCOUT1", - "BCOUT10": "DSP_0_BCOUT10", - "BCOUT11": "DSP_0_BCOUT11", - "BCOUT12": "DSP_0_BCOUT12", - "BCOUT13": "DSP_0_BCOUT13", - "BCOUT14": "DSP_0_BCOUT14", - "BCOUT15": "DSP_0_BCOUT15", - "BCOUT16": "DSP_0_BCOUT16", - "BCOUT17": "DSP_0_BCOUT17", - "BCOUT2": "DSP_0_BCOUT2", - "BCOUT3": "DSP_0_BCOUT3", - "BCOUT4": "DSP_0_BCOUT4", - "BCOUT5": "DSP_0_BCOUT5", - "BCOUT6": "DSP_0_BCOUT6", - "BCOUT7": "DSP_0_BCOUT7", - "BCOUT8": "DSP_0_BCOUT8", - "BCOUT9": "DSP_0_BCOUT9", - "C0": "DSP_0_C0", - "C1": "DSP_0_C1", - "C10": "DSP_0_C10", - "C11": "DSP_0_C11", - "C12": "DSP_0_C12", - "C13": "DSP_0_C13", - "C14": "DSP_0_C14", - "C15": "DSP_0_C15", - "C16": "DSP_0_C16", - "C17": "DSP_0_C17", - "C18": "DSP_0_C18", - "C19": "DSP_0_C19", - "C2": "DSP_0_C2", - "C20": "DSP_0_C20", - "C21": "DSP_0_C21", - "C22": "DSP_0_C22", - "C23": "DSP_0_C23", - "C24": "DSP_0_C24", - "C25": "DSP_0_C25", - "C26": "DSP_0_C26", - "C27": "DSP_0_C27", - "C28": "DSP_0_C28", - "C29": "DSP_0_C29", - "C3": "DSP_0_C3", - "C30": "DSP_0_C30", - "C31": "DSP_0_C31", - "C32": "DSP_0_C32", - "C33": "DSP_0_C33", - "C34": "DSP_0_C34", - "C35": "DSP_0_C35", - "C36": "DSP_0_C36", - "C37": "DSP_0_C37", - "C38": "DSP_0_C38", - "C39": "DSP_0_C39", - "C4": "DSP_0_C4", - "C40": "DSP_0_C40", - "C41": "DSP_0_C41", - "C42": "DSP_0_C42", - "C43": "DSP_0_C43", - "C44": "DSP_0_C44", - "C45": "DSP_0_C45", - "C46": "DSP_0_C46", - "C47": "DSP_0_C47", - "C5": "DSP_0_C5", - "C6": "DSP_0_C6", - "C7": "DSP_0_C7", - "C8": "DSP_0_C8", - "C9": "DSP_0_C9", - "CARRYCASCIN": "DSP_0_CARRYCASCIN", - "CARRYCASCOUT": "DSP_0_CARRYCASCOUT", - "CARRYIN": "DSP_0_CARRYIN", - "CARRYINSEL0": "DSP_0_CARRYINSEL0", - "CARRYINSEL1": "DSP_0_CARRYINSEL1", - "CARRYINSEL2": "DSP_0_CARRYINSEL2", - "CARRYOUT0": "DSP_0_CARRYOUT0", - "CARRYOUT1": "DSP_0_CARRYOUT1", - "CARRYOUT2": "DSP_0_CARRYOUT2", - "CARRYOUT3": "DSP_0_CARRYOUT3", - "CEA1": "DSP_0_CEA1", - "CEA2": "DSP_0_CEA2", - "CEAD": "DSP_0_CEAD", - "CEALUMODE": "DSP_0_CEALUMODE", - "CEB1": "DSP_0_CEB1", - "CEB2": "DSP_0_CEB2", - "CEC": "DSP_0_CEC", - "CECARRYIN": "DSP_0_CECARRYIN", - "CECTRL": "DSP_0_CECTRL", - "CED": "DSP_0_CED", - "CEINMODE": "DSP_0_CEINMODE", - "CEM": "DSP_0_CEM", - "CEP": "DSP_0_CEP", - "CLK": "DSP_0_CLK", - "D0": "DSP_0_D0", - "D1": "DSP_0_D1", - "D10": "DSP_0_D10", - "D11": "DSP_0_D11", - "D12": "DSP_0_D12", - "D13": "DSP_0_D13", - "D14": "DSP_0_D14", - "D15": "DSP_0_D15", - "D16": "DSP_0_D16", - "D17": "DSP_0_D17", - "D18": "DSP_0_D18", - "D19": "DSP_0_D19", - "D2": "DSP_0_D2", - "D20": "DSP_0_D20", - "D21": "DSP_0_D21", - "D22": "DSP_0_D22", - "D23": "DSP_0_D23", - "D24": "DSP_0_D24", - "D3": "DSP_0_D3", - "D4": "DSP_0_D4", - "D5": "DSP_0_D5", - "D6": "DSP_0_D6", - "D7": "DSP_0_D7", - "D8": "DSP_0_D8", - "D9": "DSP_0_D9", - "INMODE0": "DSP_0_INMODE0", - "INMODE1": "DSP_0_INMODE1", - "INMODE2": "DSP_0_INMODE2", - "INMODE3": "DSP_0_INMODE3", - "INMODE4": "DSP_0_INMODE4", - "MULTSIGNIN": "DSP_0_MULTSIGNIN", - "MULTSIGNOUT": "DSP_0_MULTSIGNOUT", - "OPMODE0": "DSP_0_OPMODE0", - "OPMODE1": "DSP_0_OPMODE1", - "OPMODE2": "DSP_0_OPMODE2", - "OPMODE3": "DSP_0_OPMODE3", - "OPMODE4": "DSP_0_OPMODE4", - "OPMODE5": "DSP_0_OPMODE5", - "OPMODE6": "DSP_0_OPMODE6", - "OVERFLOW": "DSP_0_OVERFLOW", - "P0": "DSP_0_P0", - "P1": "DSP_0_P1", - "P10": "DSP_0_P10", - "P11": "DSP_0_P11", - "P12": "DSP_0_P12", - "P13": "DSP_0_P13", - "P14": "DSP_0_P14", - "P15": "DSP_0_P15", - "P16": "DSP_0_P16", - "P17": "DSP_0_P17", - "P18": "DSP_0_P18", - "P19": "DSP_0_P19", - "P2": "DSP_0_P2", - "P20": "DSP_0_P20", - "P21": "DSP_0_P21", - "P22": "DSP_0_P22", - "P23": "DSP_0_P23", - "P24": "DSP_0_P24", - "P25": "DSP_0_P25", - "P26": "DSP_0_P26", - "P27": "DSP_0_P27", - "P28": "DSP_0_P28", - "P29": "DSP_0_P29", - "P3": "DSP_0_P3", - "P30": "DSP_0_P30", - "P31": "DSP_0_P31", - "P32": "DSP_0_P32", - "P33": "DSP_0_P33", - "P34": "DSP_0_P34", - "P35": "DSP_0_P35", - "P36": "DSP_0_P36", - "P37": "DSP_0_P37", - "P38": "DSP_0_P38", - "P39": "DSP_0_P39", - "P4": "DSP_0_P4", - "P40": "DSP_0_P40", - "P41": "DSP_0_P41", - "P42": "DSP_0_P42", - "P43": "DSP_0_P43", - "P44": "DSP_0_P44", - "P45": "DSP_0_P45", - "P46": "DSP_0_P46", - "P47": "DSP_0_P47", - "P5": "DSP_0_P5", - "P6": "DSP_0_P6", - "P7": "DSP_0_P7", - "P8": "DSP_0_P8", - "P9": "DSP_0_P9", - "PATTERNBDETECT": "DSP_0_PATTERNBDETECT", - "PATTERNDETECT": "DSP_0_PATTERNDETECT", - "PCIN0": "DSP_0_PCIN0", - "PCIN1": "DSP_0_PCIN1", - "PCIN10": "DSP_0_PCIN10", - "PCIN11": "DSP_0_PCIN11", - "PCIN12": "DSP_0_PCIN12", - "PCIN13": "DSP_0_PCIN13", - "PCIN14": "DSP_0_PCIN14", - "PCIN15": "DSP_0_PCIN15", - "PCIN16": "DSP_0_PCIN16", - "PCIN17": "DSP_0_PCIN17", - "PCIN18": "DSP_0_PCIN18", - "PCIN19": "DSP_0_PCIN19", - "PCIN2": "DSP_0_PCIN2", - "PCIN20": "DSP_0_PCIN20", - "PCIN21": "DSP_0_PCIN21", - "PCIN22": "DSP_0_PCIN22", - "PCIN23": "DSP_0_PCIN23", - "PCIN24": "DSP_0_PCIN24", - "PCIN25": "DSP_0_PCIN25", - "PCIN26": "DSP_0_PCIN26", - "PCIN27": "DSP_0_PCIN27", - "PCIN28": "DSP_0_PCIN28", - "PCIN29": "DSP_0_PCIN29", - "PCIN3": "DSP_0_PCIN3", - "PCIN30": "DSP_0_PCIN30", - "PCIN31": "DSP_0_PCIN31", - "PCIN32": "DSP_0_PCIN32", - "PCIN33": "DSP_0_PCIN33", - "PCIN34": "DSP_0_PCIN34", - "PCIN35": "DSP_0_PCIN35", - "PCIN36": "DSP_0_PCIN36", - "PCIN37": "DSP_0_PCIN37", - "PCIN38": "DSP_0_PCIN38", - "PCIN39": "DSP_0_PCIN39", - "PCIN4": "DSP_0_PCIN4", - "PCIN40": "DSP_0_PCIN40", - "PCIN41": "DSP_0_PCIN41", - "PCIN42": "DSP_0_PCIN42", - "PCIN43": "DSP_0_PCIN43", - "PCIN44": "DSP_0_PCIN44", - "PCIN45": "DSP_0_PCIN45", - "PCIN46": "DSP_0_PCIN46", - "PCIN47": "DSP_0_PCIN47", - "PCIN5": "DSP_0_PCIN5", - "PCIN6": "DSP_0_PCIN6", - "PCIN7": "DSP_0_PCIN7", - "PCIN8": "DSP_0_PCIN8", - "PCIN9": "DSP_0_PCIN9", - "PCOUT0": "DSP_0_PCOUT0", - "PCOUT1": "DSP_0_PCOUT1", - "PCOUT10": "DSP_0_PCOUT10", - "PCOUT11": "DSP_0_PCOUT11", - "PCOUT12": "DSP_0_PCOUT12", - "PCOUT13": "DSP_0_PCOUT13", - "PCOUT14": "DSP_0_PCOUT14", - "PCOUT15": "DSP_0_PCOUT15", - "PCOUT16": "DSP_0_PCOUT16", - "PCOUT17": "DSP_0_PCOUT17", - "PCOUT18": "DSP_0_PCOUT18", - "PCOUT19": "DSP_0_PCOUT19", - "PCOUT2": "DSP_0_PCOUT2", - "PCOUT20": "DSP_0_PCOUT20", - "PCOUT21": "DSP_0_PCOUT21", - "PCOUT22": "DSP_0_PCOUT22", - "PCOUT23": "DSP_0_PCOUT23", - "PCOUT24": "DSP_0_PCOUT24", - "PCOUT25": "DSP_0_PCOUT25", - "PCOUT26": "DSP_0_PCOUT26", - "PCOUT27": "DSP_0_PCOUT27", - "PCOUT28": "DSP_0_PCOUT28", - "PCOUT29": "DSP_0_PCOUT29", - "PCOUT3": "DSP_0_PCOUT3", - "PCOUT30": "DSP_0_PCOUT30", - "PCOUT31": "DSP_0_PCOUT31", - "PCOUT32": "DSP_0_PCOUT32", - "PCOUT33": "DSP_0_PCOUT33", - "PCOUT34": "DSP_0_PCOUT34", - "PCOUT35": "DSP_0_PCOUT35", - "PCOUT36": "DSP_0_PCOUT36", - "PCOUT37": "DSP_0_PCOUT37", - "PCOUT38": "DSP_0_PCOUT38", - "PCOUT39": "DSP_0_PCOUT39", - "PCOUT4": "DSP_0_PCOUT4", - "PCOUT40": "DSP_0_PCOUT40", - "PCOUT41": "DSP_0_PCOUT41", - "PCOUT42": "DSP_0_PCOUT42", - "PCOUT43": "DSP_0_PCOUT43", - "PCOUT44": "DSP_0_PCOUT44", - "PCOUT45": "DSP_0_PCOUT45", - "PCOUT46": "DSP_0_PCOUT46", - "PCOUT47": "DSP_0_PCOUT47", - "PCOUT5": "DSP_0_PCOUT5", - "PCOUT6": "DSP_0_PCOUT6", - "PCOUT7": "DSP_0_PCOUT7", - "PCOUT8": "DSP_0_PCOUT8", - "PCOUT9": "DSP_0_PCOUT9", - "RSTA": "DSP_0_RSTA", - "RSTALLCARRYIN": "DSP_0_RSTALLCARRYIN", - "RSTALUMODE": "DSP_0_RSTALUMODE", - "RSTB": "DSP_0_RSTB", - "RSTC": "DSP_0_RSTC", - "RSTCTRL": "DSP_0_RSTCTRL", - "RSTD": "DSP_0_RSTD", - "RSTINMODE": "DSP_0_RSTINMODE", - "RSTM": "DSP_0_RSTM", - "RSTP": "DSP_0_RSTP", - "UNDERFLOW": "DSP_0_UNDERFLOW" + "A0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + 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"DSP_1_A8", - "A9": "DSP_1_A9", - "ACIN0": "DSP_1_ACIN0", - "ACIN1": "DSP_1_ACIN1", - "ACIN10": "DSP_1_ACIN10", - "ACIN11": "DSP_1_ACIN11", - "ACIN12": "DSP_1_ACIN12", - "ACIN13": "DSP_1_ACIN13", - "ACIN14": "DSP_1_ACIN14", - "ACIN15": "DSP_1_ACIN15", - "ACIN16": "DSP_1_ACIN16", - "ACIN17": "DSP_1_ACIN17", - "ACIN18": "DSP_1_ACIN18", - "ACIN19": "DSP_1_ACIN19", - "ACIN2": "DSP_1_ACIN2", - "ACIN20": "DSP_1_ACIN20", - "ACIN21": "DSP_1_ACIN21", - "ACIN22": "DSP_1_ACIN22", - "ACIN23": "DSP_1_ACIN23", - "ACIN24": "DSP_1_ACIN24", - "ACIN25": "DSP_1_ACIN25", - "ACIN26": "DSP_1_ACIN26", - "ACIN27": "DSP_1_ACIN27", - "ACIN28": "DSP_1_ACIN28", - "ACIN29": "DSP_1_ACIN29", - "ACIN3": "DSP_1_ACIN3", - "ACIN4": "DSP_1_ACIN4", - "ACIN5": "DSP_1_ACIN5", - "ACIN6": "DSP_1_ACIN6", - "ACIN7": "DSP_1_ACIN7", - "ACIN8": "DSP_1_ACIN8", - "ACIN9": "DSP_1_ACIN9", - "ACOUT0": "DSP_1_ACOUT0", - "ACOUT1": "DSP_1_ACOUT1", - "ACOUT10": "DSP_1_ACOUT10", - "ACOUT11": "DSP_1_ACOUT11", - "ACOUT12": "DSP_1_ACOUT12", - "ACOUT13": "DSP_1_ACOUT13", - "ACOUT14": "DSP_1_ACOUT14", - "ACOUT15": "DSP_1_ACOUT15", - "ACOUT16": "DSP_1_ACOUT16", - "ACOUT17": "DSP_1_ACOUT17", - "ACOUT18": "DSP_1_ACOUT18", - "ACOUT19": "DSP_1_ACOUT19", - "ACOUT2": "DSP_1_ACOUT2", - "ACOUT20": "DSP_1_ACOUT20", - "ACOUT21": "DSP_1_ACOUT21", - "ACOUT22": "DSP_1_ACOUT22", - "ACOUT23": "DSP_1_ACOUT23", - "ACOUT24": "DSP_1_ACOUT24", - "ACOUT25": "DSP_1_ACOUT25", - "ACOUT26": "DSP_1_ACOUT26", - "ACOUT27": "DSP_1_ACOUT27", - "ACOUT28": "DSP_1_ACOUT28", - "ACOUT29": "DSP_1_ACOUT29", - "ACOUT3": "DSP_1_ACOUT3", - "ACOUT4": "DSP_1_ACOUT4", - "ACOUT5": "DSP_1_ACOUT5", - "ACOUT6": "DSP_1_ACOUT6", - "ACOUT7": "DSP_1_ACOUT7", - "ACOUT8": "DSP_1_ACOUT8", - "ACOUT9": "DSP_1_ACOUT9", - "ALUMODE0": "DSP_1_ALUMODE0", - "ALUMODE1": "DSP_1_ALUMODE1", - "ALUMODE2": "DSP_1_ALUMODE2", - "ALUMODE3": "DSP_1_ALUMODE3", - "B0": "DSP_1_B0", - "B1": "DSP_1_B1", - "B10": "DSP_1_B10", - "B11": "DSP_1_B11", - "B12": "DSP_1_B12", - "B13": "DSP_1_B13", - "B14": "DSP_1_B14", - "B15": "DSP_1_B15", - "B16": "DSP_1_B16", - "B17": "DSP_1_B17", - "B2": "DSP_1_B2", - "B3": "DSP_1_B3", - "B4": "DSP_1_B4", - "B5": "DSP_1_B5", - "B6": "DSP_1_B6", - "B7": "DSP_1_B7", - "B8": "DSP_1_B8", - "B9": "DSP_1_B9", - "BCIN0": "DSP_1_BCIN0", - "BCIN1": "DSP_1_BCIN1", - "BCIN10": "DSP_1_BCIN10", - "BCIN11": "DSP_1_BCIN11", - "BCIN12": "DSP_1_BCIN12", - "BCIN13": "DSP_1_BCIN13", - "BCIN14": "DSP_1_BCIN14", - "BCIN15": "DSP_1_BCIN15", - "BCIN16": "DSP_1_BCIN16", - "BCIN17": "DSP_1_BCIN17", - "BCIN2": "DSP_1_BCIN2", - "BCIN3": "DSP_1_BCIN3", - "BCIN4": "DSP_1_BCIN4", - "BCIN5": "DSP_1_BCIN5", - "BCIN6": "DSP_1_BCIN6", - "BCIN7": "DSP_1_BCIN7", - "BCIN8": "DSP_1_BCIN8", - "BCIN9": "DSP_1_BCIN9", - "BCOUT0": "DSP_1_BCOUT0", - "BCOUT1": "DSP_1_BCOUT1", - "BCOUT10": "DSP_1_BCOUT10", - "BCOUT11": "DSP_1_BCOUT11", - "BCOUT12": "DSP_1_BCOUT12", - "BCOUT13": "DSP_1_BCOUT13", - "BCOUT14": "DSP_1_BCOUT14", - "BCOUT15": "DSP_1_BCOUT15", - "BCOUT16": "DSP_1_BCOUT16", - "BCOUT17": "DSP_1_BCOUT17", - "BCOUT2": "DSP_1_BCOUT2", - "BCOUT3": "DSP_1_BCOUT3", - "BCOUT4": "DSP_1_BCOUT4", - "BCOUT5": "DSP_1_BCOUT5", - "BCOUT6": "DSP_1_BCOUT6", - "BCOUT7": "DSP_1_BCOUT7", - "BCOUT8": "DSP_1_BCOUT8", - "BCOUT9": "DSP_1_BCOUT9", - "C0": "DSP_1_C0", - "C1": "DSP_1_C1", - "C10": "DSP_1_C10", - "C11": "DSP_1_C11", - "C12": "DSP_1_C12", - "C13": "DSP_1_C13", - "C14": "DSP_1_C14", - "C15": "DSP_1_C15", - "C16": "DSP_1_C16", - "C17": "DSP_1_C17", - "C18": "DSP_1_C18", - "C19": "DSP_1_C19", - "C2": "DSP_1_C2", - "C20": "DSP_1_C20", - "C21": "DSP_1_C21", - "C22": "DSP_1_C22", - "C23": "DSP_1_C23", - "C24": "DSP_1_C24", - "C25": "DSP_1_C25", - "C26": "DSP_1_C26", - "C27": "DSP_1_C27", - "C28": "DSP_1_C28", - "C29": "DSP_1_C29", - "C3": "DSP_1_C3", - "C30": "DSP_1_C30", - "C31": "DSP_1_C31", - "C32": "DSP_1_C32", - "C33": "DSP_1_C33", - "C34": "DSP_1_C34", - "C35": "DSP_1_C35", - "C36": "DSP_1_C36", - "C37": "DSP_1_C37", - "C38": "DSP_1_C38", - "C39": "DSP_1_C39", - "C4": "DSP_1_C4", - "C40": "DSP_1_C40", - "C41": "DSP_1_C41", - "C42": "DSP_1_C42", - "C43": "DSP_1_C43", - "C44": "DSP_1_C44", - "C45": "DSP_1_C45", - "C46": "DSP_1_C46", - "C47": "DSP_1_C47", - "C5": "DSP_1_C5", - "C6": "DSP_1_C6", - "C7": "DSP_1_C7", - "C8": "DSP_1_C8", - "C9": "DSP_1_C9", - "CARRYCASCIN": "DSP_1_CARRYCASCIN", - "CARRYCASCOUT": "DSP_1_CARRYCASCOUT", - "CARRYIN": "DSP_1_CARRYIN", - "CARRYINSEL0": "DSP_1_CARRYINSEL0", - "CARRYINSEL1": "DSP_1_CARRYINSEL1", - "CARRYINSEL2": "DSP_1_CARRYINSEL2", - "CARRYOUT0": "DSP_1_CARRYOUT0", - "CARRYOUT1": "DSP_1_CARRYOUT1", - "CARRYOUT2": "DSP_1_CARRYOUT2", - "CARRYOUT3": "DSP_1_CARRYOUT3", - "CEA1": "DSP_1_CEA1", - "CEA2": "DSP_1_CEA2", - "CEAD": "DSP_1_CEAD", - "CEALUMODE": "DSP_1_CEALUMODE", - "CEB1": "DSP_1_CEB1", - "CEB2": "DSP_1_CEB2", - "CEC": "DSP_1_CEC", - "CECARRYIN": "DSP_1_CECARRYIN", - "CECTRL": "DSP_1_CECTRL", - "CED": "DSP_1_CED", - "CEINMODE": "DSP_1_CEINMODE", - "CEM": "DSP_1_CEM", - "CEP": "DSP_1_CEP", - "CLK": "DSP_1_CLK", - "D0": "DSP_1_D0", - "D1": "DSP_1_D1", - "D10": "DSP_1_D10", - "D11": "DSP_1_D11", - "D12": "DSP_1_D12", - "D13": "DSP_1_D13", - "D14": "DSP_1_D14", - "D15": "DSP_1_D15", - "D16": "DSP_1_D16", - "D17": "DSP_1_D17", - "D18": "DSP_1_D18", - "D19": "DSP_1_D19", - "D2": "DSP_1_D2", - "D20": "DSP_1_D20", - "D21": "DSP_1_D21", - "D22": "DSP_1_D22", - "D23": "DSP_1_D23", - "D24": "DSP_1_D24", - "D3": "DSP_1_D3", - "D4": "DSP_1_D4", - "D5": "DSP_1_D5", - "D6": "DSP_1_D6", - "D7": "DSP_1_D7", - "D8": "DSP_1_D8", - "D9": "DSP_1_D9", - "INMODE0": "DSP_1_INMODE0", - "INMODE1": "DSP_1_INMODE1", - "INMODE2": "DSP_1_INMODE2", - "INMODE3": "DSP_1_INMODE3", - "INMODE4": "DSP_1_INMODE4", - "MULTSIGNIN": "DSP_1_MULTSIGNIN", - "MULTSIGNOUT": "DSP_1_MULTSIGNOUT", - "OPMODE0": "DSP_1_OPMODE0", - "OPMODE1": "DSP_1_OPMODE1", - "OPMODE2": "DSP_1_OPMODE2", - "OPMODE3": "DSP_1_OPMODE3", - "OPMODE4": "DSP_1_OPMODE4", - "OPMODE5": "DSP_1_OPMODE5", - "OPMODE6": "DSP_1_OPMODE6", - "OVERFLOW": "DSP_1_OVERFLOW", - "P0": "DSP_1_P0", - "P1": "DSP_1_P1", - "P10": "DSP_1_P10", - "P11": "DSP_1_P11", - "P12": "DSP_1_P12", - "P13": "DSP_1_P13", - "P14": "DSP_1_P14", - "P15": "DSP_1_P15", - "P16": "DSP_1_P16", - "P17": "DSP_1_P17", - "P18": "DSP_1_P18", - "P19": "DSP_1_P19", - "P2": "DSP_1_P2", - "P20": "DSP_1_P20", - "P21": "DSP_1_P21", - "P22": "DSP_1_P22", - "P23": "DSP_1_P23", - "P24": "DSP_1_P24", - "P25": "DSP_1_P25", - "P26": "DSP_1_P26", - "P27": "DSP_1_P27", - "P28": "DSP_1_P28", - "P29": "DSP_1_P29", - "P3": "DSP_1_P3", - "P30": "DSP_1_P30", - "P31": "DSP_1_P31", - "P32": "DSP_1_P32", - "P33": "DSP_1_P33", - "P34": "DSP_1_P34", - "P35": "DSP_1_P35", - "P36": "DSP_1_P36", - "P37": "DSP_1_P37", - "P38": "DSP_1_P38", - "P39": "DSP_1_P39", - "P4": "DSP_1_P4", - "P40": "DSP_1_P40", - "P41": "DSP_1_P41", - "P42": "DSP_1_P42", - "P43": "DSP_1_P43", - "P44": "DSP_1_P44", - "P45": "DSP_1_P45", - "P46": "DSP_1_P46", - "P47": "DSP_1_P47", - "P5": "DSP_1_P5", - "P6": "DSP_1_P6", - "P7": "DSP_1_P7", - "P8": "DSP_1_P8", - "P9": "DSP_1_P9", - "PATTERNBDETECT": "DSP_1_PATTERNBDETECT", - "PATTERNDETECT": "DSP_1_PATTERNDETECT", - "PCIN0": "DSP_1_PCIN0", - "PCIN1": "DSP_1_PCIN1", - "PCIN10": "DSP_1_PCIN10", - "PCIN11": "DSP_1_PCIN11", - "PCIN12": "DSP_1_PCIN12", - "PCIN13": "DSP_1_PCIN13", - "PCIN14": "DSP_1_PCIN14", - "PCIN15": "DSP_1_PCIN15", - "PCIN16": "DSP_1_PCIN16", - "PCIN17": "DSP_1_PCIN17", - "PCIN18": "DSP_1_PCIN18", - "PCIN19": "DSP_1_PCIN19", - "PCIN2": "DSP_1_PCIN2", - "PCIN20": "DSP_1_PCIN20", - "PCIN21": "DSP_1_PCIN21", - "PCIN22": "DSP_1_PCIN22", - "PCIN23": "DSP_1_PCIN23", - "PCIN24": "DSP_1_PCIN24", - "PCIN25": "DSP_1_PCIN25", - "PCIN26": "DSP_1_PCIN26", - "PCIN27": "DSP_1_PCIN27", - "PCIN28": "DSP_1_PCIN28", - "PCIN29": "DSP_1_PCIN29", - "PCIN3": "DSP_1_PCIN3", - "PCIN30": "DSP_1_PCIN30", - "PCIN31": "DSP_1_PCIN31", - "PCIN32": "DSP_1_PCIN32", - "PCIN33": "DSP_1_PCIN33", - "PCIN34": "DSP_1_PCIN34", - "PCIN35": "DSP_1_PCIN35", - "PCIN36": "DSP_1_PCIN36", - "PCIN37": "DSP_1_PCIN37", - "PCIN38": "DSP_1_PCIN38", - "PCIN39": "DSP_1_PCIN39", - "PCIN4": "DSP_1_PCIN4", - "PCIN40": "DSP_1_PCIN40", - "PCIN41": "DSP_1_PCIN41", - "PCIN42": "DSP_1_PCIN42", - "PCIN43": "DSP_1_PCIN43", - "PCIN44": "DSP_1_PCIN44", - "PCIN45": "DSP_1_PCIN45", - "PCIN46": "DSP_1_PCIN46", - "PCIN47": "DSP_1_PCIN47", - "PCIN5": "DSP_1_PCIN5", - "PCIN6": "DSP_1_PCIN6", - "PCIN7": "DSP_1_PCIN7", - "PCIN8": "DSP_1_PCIN8", - "PCIN9": "DSP_1_PCIN9", - "PCOUT0": "DSP_1_PCOUT0", - "PCOUT1": "DSP_1_PCOUT1", - "PCOUT10": "DSP_1_PCOUT10", - "PCOUT11": "DSP_1_PCOUT11", - "PCOUT12": "DSP_1_PCOUT12", - "PCOUT13": "DSP_1_PCOUT13", - "PCOUT14": "DSP_1_PCOUT14", - "PCOUT15": "DSP_1_PCOUT15", - "PCOUT16": "DSP_1_PCOUT16", - "PCOUT17": "DSP_1_PCOUT17", - "PCOUT18": "DSP_1_PCOUT18", - "PCOUT19": "DSP_1_PCOUT19", - "PCOUT2": "DSP_1_PCOUT2", - "PCOUT20": "DSP_1_PCOUT20", - "PCOUT21": "DSP_1_PCOUT21", - "PCOUT22": "DSP_1_PCOUT22", - "PCOUT23": "DSP_1_PCOUT23", - "PCOUT24": "DSP_1_PCOUT24", - "PCOUT25": "DSP_1_PCOUT25", - "PCOUT26": "DSP_1_PCOUT26", - "PCOUT27": "DSP_1_PCOUT27", - "PCOUT28": "DSP_1_PCOUT28", - "PCOUT29": "DSP_1_PCOUT29", - "PCOUT3": "DSP_1_PCOUT3", - "PCOUT30": "DSP_1_PCOUT30", - "PCOUT31": "DSP_1_PCOUT31", - "PCOUT32": "DSP_1_PCOUT32", - "PCOUT33": "DSP_1_PCOUT33", - "PCOUT34": "DSP_1_PCOUT34", - "PCOUT35": "DSP_1_PCOUT35", - "PCOUT36": "DSP_1_PCOUT36", - "PCOUT37": "DSP_1_PCOUT37", - "PCOUT38": "DSP_1_PCOUT38", - "PCOUT39": "DSP_1_PCOUT39", - "PCOUT4": "DSP_1_PCOUT4", - "PCOUT40": "DSP_1_PCOUT40", - "PCOUT41": "DSP_1_PCOUT41", - "PCOUT42": "DSP_1_PCOUT42", - "PCOUT43": "DSP_1_PCOUT43", - "PCOUT44": "DSP_1_PCOUT44", - "PCOUT45": "DSP_1_PCOUT45", - "PCOUT46": "DSP_1_PCOUT46", - "PCOUT47": "DSP_1_PCOUT47", - "PCOUT5": "DSP_1_PCOUT5", - "PCOUT6": "DSP_1_PCOUT6", - "PCOUT7": "DSP_1_PCOUT7", - "PCOUT8": "DSP_1_PCOUT8", - "PCOUT9": "DSP_1_PCOUT9", - "RSTA": "DSP_1_RSTA", - "RSTALLCARRYIN": "DSP_1_RSTALLCARRYIN", - "RSTALUMODE": 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"res": "0.0", + "wire": "DSP_VCC_L" + } }, "type": "TIEOFF", "x_coord": 0, @@ -6425,2050 +22683,4834 @@ } ], "tile_type": "DSP_L", - "wires": [ - "DSP_0_A0", - "DSP_0_A1", - "DSP_0_A10", - "DSP_0_A11", - "DSP_0_A12", - "DSP_0_A13", - "DSP_0_A14", - "DSP_0_A15", - "DSP_0_A16", - "DSP_0_A17", - "DSP_0_A18", - "DSP_0_A19", - "DSP_0_A2", - "DSP_0_A20", - "DSP_0_A21", - "DSP_0_A22", - "DSP_0_A23", - "DSP_0_A24", - "DSP_0_A25", - "DSP_0_A26", - "DSP_0_A27", - "DSP_0_A28", - "DSP_0_A29", - "DSP_0_A3", - "DSP_0_A4", - "DSP_0_A5", - "DSP_0_A6", - "DSP_0_A7", - "DSP_0_A8", - "DSP_0_A9", - "DSP_0_ACIN0", - "DSP_0_ACIN1", - "DSP_0_ACIN10", - "DSP_0_ACIN11", - "DSP_0_ACIN12", - "DSP_0_ACIN13", - "DSP_0_ACIN14", - "DSP_0_ACIN15", - "DSP_0_ACIN16", - "DSP_0_ACIN17", - "DSP_0_ACIN18", - "DSP_0_ACIN19", - "DSP_0_ACIN2", - "DSP_0_ACIN20", - "DSP_0_ACIN21", - "DSP_0_ACIN22", - "DSP_0_ACIN23", - "DSP_0_ACIN24", - "DSP_0_ACIN25", - "DSP_0_ACIN26", - "DSP_0_ACIN27", - "DSP_0_ACIN28", - "DSP_0_ACIN29", - "DSP_0_ACIN3", - "DSP_0_ACIN4", - "DSP_0_ACIN5", - "DSP_0_ACIN6", - "DSP_0_ACIN7", - "DSP_0_ACIN8", - "DSP_0_ACIN9", - "DSP_0_ACOUT0", - "DSP_0_ACOUT1", - "DSP_0_ACOUT10", - "DSP_0_ACOUT11", - "DSP_0_ACOUT12", - "DSP_0_ACOUT13", - "DSP_0_ACOUT14", - "DSP_0_ACOUT15", - "DSP_0_ACOUT16", - "DSP_0_ACOUT17", - "DSP_0_ACOUT18", - "DSP_0_ACOUT19", - "DSP_0_ACOUT2", - "DSP_0_ACOUT20", - "DSP_0_ACOUT21", - "DSP_0_ACOUT22", - "DSP_0_ACOUT23", - "DSP_0_ACOUT24", - "DSP_0_ACOUT25", - "DSP_0_ACOUT26", - "DSP_0_ACOUT27", - "DSP_0_ACOUT28", - "DSP_0_ACOUT29", - "DSP_0_ACOUT3", - "DSP_0_ACOUT4", - "DSP_0_ACOUT5", - "DSP_0_ACOUT6", - "DSP_0_ACOUT7", - "DSP_0_ACOUT8", - "DSP_0_ACOUT9", - "DSP_0_ALUMODE0", - "DSP_0_ALUMODE1", - "DSP_0_ALUMODE2", - "DSP_0_ALUMODE3", - "DSP_0_B0", - "DSP_0_B1", - "DSP_0_B10", - "DSP_0_B11", - "DSP_0_B12", - "DSP_0_B13", - "DSP_0_B14", - "DSP_0_B15", - "DSP_0_B16", - "DSP_0_B17", - "DSP_0_B2", - "DSP_0_B3", - "DSP_0_B4", - "DSP_0_B5", - "DSP_0_B6", - "DSP_0_B7", - "DSP_0_B8", - "DSP_0_B9", - "DSP_0_BCIN0", - "DSP_0_BCIN1", - "DSP_0_BCIN10", - "DSP_0_BCIN11", - "DSP_0_BCIN12", - "DSP_0_BCIN13", - "DSP_0_BCIN14", - "DSP_0_BCIN15", - "DSP_0_BCIN16", - "DSP_0_BCIN17", - "DSP_0_BCIN2", - "DSP_0_BCIN3", - "DSP_0_BCIN4", - "DSP_0_BCIN5", - "DSP_0_BCIN6", - "DSP_0_BCIN7", - "DSP_0_BCIN8", - "DSP_0_BCIN9", - "DSP_0_BCOUT0", - "DSP_0_BCOUT1", - "DSP_0_BCOUT10", - "DSP_0_BCOUT11", - "DSP_0_BCOUT12", - "DSP_0_BCOUT13", - "DSP_0_BCOUT14", - "DSP_0_BCOUT15", - "DSP_0_BCOUT16", - "DSP_0_BCOUT17", - "DSP_0_BCOUT2", - "DSP_0_BCOUT3", - "DSP_0_BCOUT4", - "DSP_0_BCOUT5", - "DSP_0_BCOUT6", - "DSP_0_BCOUT7", - "DSP_0_BCOUT8", - "DSP_0_BCOUT9", - "DSP_0_C0", - "DSP_0_C1", - "DSP_0_C10", - "DSP_0_C11", - "DSP_0_C12", - "DSP_0_C13", - "DSP_0_C14", - "DSP_0_C15", - "DSP_0_C16", - "DSP_0_C17", - "DSP_0_C18", - "DSP_0_C19", - "DSP_0_C2", - "DSP_0_C20", - "DSP_0_C21", - "DSP_0_C22", - "DSP_0_C23", - "DSP_0_C24", - "DSP_0_C25", - "DSP_0_C26", - "DSP_0_C27", - "DSP_0_C28", - "DSP_0_C29", - "DSP_0_C3", - "DSP_0_C30", - "DSP_0_C31", - "DSP_0_C32", - "DSP_0_C33", - "DSP_0_C34", - "DSP_0_C35", - "DSP_0_C36", - "DSP_0_C37", - "DSP_0_C38", - "DSP_0_C39", - "DSP_0_C4", - "DSP_0_C40", - "DSP_0_C41", - "DSP_0_C42", - "DSP_0_C43", - "DSP_0_C44", - "DSP_0_C45", - "DSP_0_C46", - "DSP_0_C47", - "DSP_0_C5", - "DSP_0_C6", - "DSP_0_C7", - "DSP_0_C8", - "DSP_0_C9", - "DSP_0_CARRYCASCIN", - "DSP_0_CARRYCASCOUT", - "DSP_0_CARRYIN", - "DSP_0_CARRYINSEL0", - "DSP_0_CARRYINSEL1", - "DSP_0_CARRYINSEL2", - "DSP_0_CARRYOUT0", - "DSP_0_CARRYOUT1", - "DSP_0_CARRYOUT2", - "DSP_0_CARRYOUT3", - "DSP_0_CEA1", - "DSP_0_CEA2", - "DSP_0_CEAD", - "DSP_0_CEALUMODE", - "DSP_0_CEB1", - "DSP_0_CEB2", - "DSP_0_CEC", - "DSP_0_CECARRYIN", - "DSP_0_CECTRL", - "DSP_0_CED", - "DSP_0_CEINMODE", - "DSP_0_CEM", - "DSP_0_CEP", - "DSP_0_CLK", - "DSP_0_D0", - "DSP_0_D1", - "DSP_0_D10", - "DSP_0_D11", - "DSP_0_D12", - "DSP_0_D13", - "DSP_0_D14", - "DSP_0_D15", - "DSP_0_D16", - "DSP_0_D17", - "DSP_0_D18", - "DSP_0_D19", - "DSP_0_D2", - "DSP_0_D20", - "DSP_0_D21", - "DSP_0_D22", - "DSP_0_D23", - "DSP_0_D24", - "DSP_0_D3", - "DSP_0_D4", - "DSP_0_D5", - "DSP_0_D6", - "DSP_0_D7", - "DSP_0_D8", - "DSP_0_D9", - "DSP_0_INMODE0", - "DSP_0_INMODE1", - "DSP_0_INMODE2", - "DSP_0_INMODE3", - "DSP_0_INMODE4", - "DSP_0_MULTSIGNIN", - "DSP_0_MULTSIGNOUT", - "DSP_0_OPMODE0", - "DSP_0_OPMODE1", - "DSP_0_OPMODE2", - "DSP_0_OPMODE3", - "DSP_0_OPMODE4", - "DSP_0_OPMODE5", - "DSP_0_OPMODE6", - "DSP_0_OVERFLOW", - "DSP_0_P0", - "DSP_0_P1", - "DSP_0_P10", - "DSP_0_P11", - "DSP_0_P12", - "DSP_0_P13", - "DSP_0_P14", - "DSP_0_P15", - "DSP_0_P16", - "DSP_0_P17", - "DSP_0_P18", - "DSP_0_P19", - "DSP_0_P2", - "DSP_0_P20", - "DSP_0_P21", - "DSP_0_P22", - "DSP_0_P23", - "DSP_0_P24", - "DSP_0_P25", - "DSP_0_P26", - "DSP_0_P27", - "DSP_0_P28", - "DSP_0_P29", - "DSP_0_P3", - "DSP_0_P30", - "DSP_0_P31", - "DSP_0_P32", - "DSP_0_P33", - "DSP_0_P34", - "DSP_0_P35", - "DSP_0_P36", - "DSP_0_P37", - "DSP_0_P38", - "DSP_0_P39", - "DSP_0_P4", - "DSP_0_P40", - "DSP_0_P41", - "DSP_0_P42", - "DSP_0_P43", - "DSP_0_P44", - "DSP_0_P45", - "DSP_0_P46", - "DSP_0_P47", - "DSP_0_P5", - "DSP_0_P6", - "DSP_0_P7", - "DSP_0_P8", - "DSP_0_P9", - "DSP_0_PATTERNBDETECT", - "DSP_0_PATTERNDETECT", - "DSP_0_PCIN0", - "DSP_0_PCIN1", - "DSP_0_PCIN10", - "DSP_0_PCIN11", - "DSP_0_PCIN12", - "DSP_0_PCIN13", - "DSP_0_PCIN14", - "DSP_0_PCIN15", - "DSP_0_PCIN16", - "DSP_0_PCIN17", - "DSP_0_PCIN18", - "DSP_0_PCIN19", - "DSP_0_PCIN2", - "DSP_0_PCIN20", - "DSP_0_PCIN21", - "DSP_0_PCIN22", - "DSP_0_PCIN23", - "DSP_0_PCIN24", - "DSP_0_PCIN25", - "DSP_0_PCIN26", - "DSP_0_PCIN27", - "DSP_0_PCIN28", - "DSP_0_PCIN29", - "DSP_0_PCIN3", - "DSP_0_PCIN30", - "DSP_0_PCIN31", - "DSP_0_PCIN32", - "DSP_0_PCIN33", - "DSP_0_PCIN34", - "DSP_0_PCIN35", - "DSP_0_PCIN36", - "DSP_0_PCIN37", - "DSP_0_PCIN38", - "DSP_0_PCIN39", - "DSP_0_PCIN4", - "DSP_0_PCIN40", - "DSP_0_PCIN41", - "DSP_0_PCIN42", - "DSP_0_PCIN43", - "DSP_0_PCIN44", - "DSP_0_PCIN45", - "DSP_0_PCIN46", - "DSP_0_PCIN47", - "DSP_0_PCIN5", - "DSP_0_PCIN6", - "DSP_0_PCIN7", - "DSP_0_PCIN8", - "DSP_0_PCIN9", - "DSP_0_PCOUT0", - "DSP_0_PCOUT1", - "DSP_0_PCOUT10", - "DSP_0_PCOUT11", - "DSP_0_PCOUT12", - "DSP_0_PCOUT13", - "DSP_0_PCOUT14", - "DSP_0_PCOUT15", - "DSP_0_PCOUT16", - "DSP_0_PCOUT17", - "DSP_0_PCOUT18", - "DSP_0_PCOUT19", - "DSP_0_PCOUT2", - "DSP_0_PCOUT20", - "DSP_0_PCOUT21", - "DSP_0_PCOUT22", - "DSP_0_PCOUT23", - "DSP_0_PCOUT24", - "DSP_0_PCOUT25", - "DSP_0_PCOUT26", - "DSP_0_PCOUT27", - "DSP_0_PCOUT28", - "DSP_0_PCOUT29", - "DSP_0_PCOUT3", - "DSP_0_PCOUT30", - "DSP_0_PCOUT31", - "DSP_0_PCOUT32", - "DSP_0_PCOUT33", - "DSP_0_PCOUT34", - "DSP_0_PCOUT35", - "DSP_0_PCOUT36", - "DSP_0_PCOUT37", - "DSP_0_PCOUT38", - "DSP_0_PCOUT39", - "DSP_0_PCOUT4", - "DSP_0_PCOUT40", - "DSP_0_PCOUT41", - "DSP_0_PCOUT42", - "DSP_0_PCOUT43", - "DSP_0_PCOUT44", - "DSP_0_PCOUT45", - "DSP_0_PCOUT46", - "DSP_0_PCOUT47", - "DSP_0_PCOUT5", - "DSP_0_PCOUT6", - "DSP_0_PCOUT7", - "DSP_0_PCOUT8", - "DSP_0_PCOUT9", - "DSP_0_RSTA", - "DSP_0_RSTALLCARRYIN", - "DSP_0_RSTALUMODE", - "DSP_0_RSTB", - "DSP_0_RSTC", - "DSP_0_RSTCTRL", - "DSP_0_RSTD", - "DSP_0_RSTINMODE", - "DSP_0_RSTM", - "DSP_0_RSTP", - "DSP_0_UNDERFLOW", - "DSP_1_A0", - "DSP_1_A1", - "DSP_1_A10", - "DSP_1_A11", - "DSP_1_A12", - "DSP_1_A13", - "DSP_1_A14", - "DSP_1_A15", - "DSP_1_A16", - "DSP_1_A17", - "DSP_1_A18", - "DSP_1_A19", - "DSP_1_A2", - "DSP_1_A20", - "DSP_1_A21", - "DSP_1_A22", - "DSP_1_A23", - "DSP_1_A24", - "DSP_1_A25", - "DSP_1_A26", - "DSP_1_A27", - "DSP_1_A28", - "DSP_1_A29", - "DSP_1_A3", - "DSP_1_A4", - "DSP_1_A5", - "DSP_1_A6", - "DSP_1_A7", - "DSP_1_A8", - "DSP_1_A9", - "DSP_1_ACIN0", - "DSP_1_ACIN1", - "DSP_1_ACIN10", - "DSP_1_ACIN11", - "DSP_1_ACIN12", - "DSP_1_ACIN13", - "DSP_1_ACIN14", - "DSP_1_ACIN15", - "DSP_1_ACIN16", - "DSP_1_ACIN17", - "DSP_1_ACIN18", - "DSP_1_ACIN19", - "DSP_1_ACIN2", - "DSP_1_ACIN20", - "DSP_1_ACIN21", - "DSP_1_ACIN22", - "DSP_1_ACIN23", - "DSP_1_ACIN24", - "DSP_1_ACIN25", - "DSP_1_ACIN26", - "DSP_1_ACIN27", - "DSP_1_ACIN28", - "DSP_1_ACIN29", - "DSP_1_ACIN3", - "DSP_1_ACIN4", - "DSP_1_ACIN5", - "DSP_1_ACIN6", - "DSP_1_ACIN7", - "DSP_1_ACIN8", - "DSP_1_ACIN9", - "DSP_1_ACOUT0", - "DSP_1_ACOUT1", - "DSP_1_ACOUT10", - "DSP_1_ACOUT11", - "DSP_1_ACOUT12", - "DSP_1_ACOUT13", - "DSP_1_ACOUT14", - "DSP_1_ACOUT15", - "DSP_1_ACOUT16", - "DSP_1_ACOUT17", - "DSP_1_ACOUT18", - "DSP_1_ACOUT19", - "DSP_1_ACOUT2", - "DSP_1_ACOUT20", - "DSP_1_ACOUT21", - "DSP_1_ACOUT22", - "DSP_1_ACOUT23", - "DSP_1_ACOUT24", - "DSP_1_ACOUT25", - "DSP_1_ACOUT26", - "DSP_1_ACOUT27", - "DSP_1_ACOUT28", - "DSP_1_ACOUT29", - "DSP_1_ACOUT3", - "DSP_1_ACOUT4", - "DSP_1_ACOUT5", - "DSP_1_ACOUT6", - "DSP_1_ACOUT7", - "DSP_1_ACOUT8", - "DSP_1_ACOUT9", - "DSP_1_ALUMODE0", - "DSP_1_ALUMODE1", - "DSP_1_ALUMODE2", - "DSP_1_ALUMODE3", - "DSP_1_B0", - "DSP_1_B1", - "DSP_1_B10", - "DSP_1_B11", - "DSP_1_B12", - "DSP_1_B13", - "DSP_1_B14", - "DSP_1_B15", - "DSP_1_B16", - "DSP_1_B17", - "DSP_1_B2", - "DSP_1_B3", - "DSP_1_B4", - "DSP_1_B5", - "DSP_1_B6", - "DSP_1_B7", - "DSP_1_B8", - "DSP_1_B9", - "DSP_1_BCIN0", - "DSP_1_BCIN1", - "DSP_1_BCIN10", - "DSP_1_BCIN11", - "DSP_1_BCIN12", - "DSP_1_BCIN13", - "DSP_1_BCIN14", - "DSP_1_BCIN15", - "DSP_1_BCIN16", - "DSP_1_BCIN17", - "DSP_1_BCIN2", - "DSP_1_BCIN3", - "DSP_1_BCIN4", - "DSP_1_BCIN5", - "DSP_1_BCIN6", - "DSP_1_BCIN7", - "DSP_1_BCIN8", - "DSP_1_BCIN9", - "DSP_1_BCOUT0", - "DSP_1_BCOUT1", - "DSP_1_BCOUT10", - "DSP_1_BCOUT11", - "DSP_1_BCOUT12", - "DSP_1_BCOUT13", - "DSP_1_BCOUT14", - "DSP_1_BCOUT15", - "DSP_1_BCOUT16", - "DSP_1_BCOUT17", - "DSP_1_BCOUT2", - "DSP_1_BCOUT3", - "DSP_1_BCOUT4", - "DSP_1_BCOUT5", - "DSP_1_BCOUT6", - "DSP_1_BCOUT7", - "DSP_1_BCOUT8", - "DSP_1_BCOUT9", - "DSP_1_C0", - "DSP_1_C1", - "DSP_1_C10", - "DSP_1_C11", - "DSP_1_C12", - "DSP_1_C13", - "DSP_1_C14", - "DSP_1_C15", - "DSP_1_C16", - "DSP_1_C17", - "DSP_1_C18", - "DSP_1_C19", - "DSP_1_C2", - "DSP_1_C20", - "DSP_1_C21", - "DSP_1_C22", - "DSP_1_C23", - "DSP_1_C24", - "DSP_1_C25", - "DSP_1_C26", - "DSP_1_C27", - "DSP_1_C28", - "DSP_1_C29", - "DSP_1_C3", - "DSP_1_C30", - "DSP_1_C31", - "DSP_1_C32", - "DSP_1_C33", - "DSP_1_C34", - "DSP_1_C35", - "DSP_1_C36", - "DSP_1_C37", - "DSP_1_C38", - "DSP_1_C39", - "DSP_1_C4", - "DSP_1_C40", - "DSP_1_C41", - "DSP_1_C42", - "DSP_1_C43", - "DSP_1_C44", - "DSP_1_C45", - "DSP_1_C46", - "DSP_1_C47", - "DSP_1_C5", - "DSP_1_C6", - "DSP_1_C7", - "DSP_1_C8", - "DSP_1_C9", - "DSP_1_CARRYCASCIN", - "DSP_1_CARRYCASCOUT", - "DSP_1_CARRYIN", - "DSP_1_CARRYINSEL0", - "DSP_1_CARRYINSEL1", - "DSP_1_CARRYINSEL2", - "DSP_1_CARRYOUT0", - "DSP_1_CARRYOUT1", - "DSP_1_CARRYOUT2", - "DSP_1_CARRYOUT3", - "DSP_1_CEA1", - "DSP_1_CEA2", - "DSP_1_CEAD", - "DSP_1_CEALUMODE", - "DSP_1_CEB1", - "DSP_1_CEB2", - "DSP_1_CEC", - "DSP_1_CECARRYIN", - "DSP_1_CECTRL", - "DSP_1_CED", - "DSP_1_CEINMODE", - "DSP_1_CEM", - "DSP_1_CEP", - "DSP_1_CLK", - "DSP_1_D0", - "DSP_1_D1", - "DSP_1_D10", - "DSP_1_D11", - "DSP_1_D12", - "DSP_1_D13", - "DSP_1_D14", - "DSP_1_D15", - "DSP_1_D16", - "DSP_1_D17", - "DSP_1_D18", - "DSP_1_D19", - "DSP_1_D2", - "DSP_1_D20", - "DSP_1_D21", - "DSP_1_D22", - "DSP_1_D23", - "DSP_1_D24", - "DSP_1_D3", - "DSP_1_D4", - "DSP_1_D5", - "DSP_1_D6", - "DSP_1_D7", - "DSP_1_D8", - "DSP_1_D9", - "DSP_1_INMODE0", - "DSP_1_INMODE1", - "DSP_1_INMODE2", - "DSP_1_INMODE3", - "DSP_1_INMODE4", - "DSP_1_MULTSIGNIN", - "DSP_1_MULTSIGNOUT", - "DSP_1_OPMODE0", - "DSP_1_OPMODE1", - "DSP_1_OPMODE2", - "DSP_1_OPMODE3", - "DSP_1_OPMODE4", - "DSP_1_OPMODE5", - "DSP_1_OPMODE6", - "DSP_1_OVERFLOW", - "DSP_1_P0", - "DSP_1_P1", - "DSP_1_P10", - "DSP_1_P11", - "DSP_1_P12", - "DSP_1_P13", - "DSP_1_P14", - "DSP_1_P15", - "DSP_1_P16", - "DSP_1_P17", - "DSP_1_P18", - "DSP_1_P19", - "DSP_1_P2", - "DSP_1_P20", - "DSP_1_P21", - "DSP_1_P22", - "DSP_1_P23", - "DSP_1_P24", - "DSP_1_P25", - "DSP_1_P26", - "DSP_1_P27", - "DSP_1_P28", - "DSP_1_P29", - "DSP_1_P3", - "DSP_1_P30", - "DSP_1_P31", - "DSP_1_P32", - "DSP_1_P33", - "DSP_1_P34", - "DSP_1_P35", - "DSP_1_P36", - "DSP_1_P37", - "DSP_1_P38", - "DSP_1_P39", - "DSP_1_P4", - "DSP_1_P40", - "DSP_1_P41", - "DSP_1_P42", - "DSP_1_P43", - "DSP_1_P44", - "DSP_1_P45", - "DSP_1_P46", - "DSP_1_P47", - "DSP_1_P5", - "DSP_1_P6", - "DSP_1_P7", - "DSP_1_P8", - "DSP_1_P9", - "DSP_1_PATTERNBDETECT", - "DSP_1_PATTERNDETECT", - "DSP_1_PCIN0", - "DSP_1_PCIN1", - "DSP_1_PCIN10", - "DSP_1_PCIN11", - "DSP_1_PCIN12", - "DSP_1_PCIN13", - "DSP_1_PCIN14", - "DSP_1_PCIN15", - "DSP_1_PCIN16", - "DSP_1_PCIN17", - "DSP_1_PCIN18", - "DSP_1_PCIN19", - "DSP_1_PCIN2", - "DSP_1_PCIN20", - "DSP_1_PCIN21", - "DSP_1_PCIN22", - "DSP_1_PCIN23", - "DSP_1_PCIN24", - "DSP_1_PCIN25", - "DSP_1_PCIN26", - "DSP_1_PCIN27", - "DSP_1_PCIN28", - "DSP_1_PCIN29", - "DSP_1_PCIN3", - "DSP_1_PCIN30", - "DSP_1_PCIN31", - "DSP_1_PCIN32", - "DSP_1_PCIN33", - "DSP_1_PCIN34", - "DSP_1_PCIN35", - "DSP_1_PCIN36", - "DSP_1_PCIN37", - "DSP_1_PCIN38", - "DSP_1_PCIN39", - "DSP_1_PCIN4", - "DSP_1_PCIN40", - "DSP_1_PCIN41", - "DSP_1_PCIN42", - "DSP_1_PCIN43", - "DSP_1_PCIN44", - "DSP_1_PCIN45", - "DSP_1_PCIN46", - "DSP_1_PCIN47", - "DSP_1_PCIN5", - "DSP_1_PCIN6", - "DSP_1_PCIN7", - "DSP_1_PCIN8", - "DSP_1_PCIN9", - "DSP_1_PCOUT0", - "DSP_1_PCOUT1", - "DSP_1_PCOUT10", - "DSP_1_PCOUT11", - "DSP_1_PCOUT12", - "DSP_1_PCOUT13", - "DSP_1_PCOUT14", - "DSP_1_PCOUT15", - "DSP_1_PCOUT16", - "DSP_1_PCOUT17", - "DSP_1_PCOUT18", - "DSP_1_PCOUT19", - "DSP_1_PCOUT2", - "DSP_1_PCOUT20", - "DSP_1_PCOUT21", - "DSP_1_PCOUT22", - "DSP_1_PCOUT23", - "DSP_1_PCOUT24", - "DSP_1_PCOUT25", - "DSP_1_PCOUT26", - "DSP_1_PCOUT27", - "DSP_1_PCOUT28", - "DSP_1_PCOUT29", - "DSP_1_PCOUT3", - "DSP_1_PCOUT30", - "DSP_1_PCOUT31", - "DSP_1_PCOUT32", - "DSP_1_PCOUT33", - "DSP_1_PCOUT34", - "DSP_1_PCOUT35", - "DSP_1_PCOUT36", - "DSP_1_PCOUT37", - "DSP_1_PCOUT38", - "DSP_1_PCOUT39", - "DSP_1_PCOUT4", - "DSP_1_PCOUT40", - "DSP_1_PCOUT41", - "DSP_1_PCOUT42", - "DSP_1_PCOUT43", - "DSP_1_PCOUT44", - "DSP_1_PCOUT45", - "DSP_1_PCOUT46", - "DSP_1_PCOUT47", - "DSP_1_PCOUT5", - "DSP_1_PCOUT6", - "DSP_1_PCOUT7", - "DSP_1_PCOUT8", - "DSP_1_PCOUT9", - "DSP_1_RSTA", - "DSP_1_RSTALLCARRYIN", - "DSP_1_RSTALUMODE", - "DSP_1_RSTB", - "DSP_1_RSTC", - "DSP_1_RSTCTRL", - "DSP_1_RSTD", - "DSP_1_RSTINMODE", - "DSP_1_RSTM", - "DSP_1_RSTP", - "DSP_1_UNDERFLOW", - "DSP_ACOUT0", - "DSP_ACOUT1", - "DSP_ACOUT10", - "DSP_ACOUT11", - "DSP_ACOUT12", - "DSP_ACOUT13", - "DSP_ACOUT14", - "DSP_ACOUT15", - "DSP_ACOUT16", - "DSP_ACOUT17", - "DSP_ACOUT18", - "DSP_ACOUT19", - "DSP_ACOUT2", - "DSP_ACOUT20", - "DSP_ACOUT21", - "DSP_ACOUT22", - "DSP_ACOUT23", - "DSP_ACOUT24", - "DSP_ACOUT25", - "DSP_ACOUT26", - "DSP_ACOUT27", - "DSP_ACOUT28", - "DSP_ACOUT29", - "DSP_ACOUT3", - "DSP_ACOUT4", - "DSP_ACOUT5", - "DSP_ACOUT6", - "DSP_ACOUT7", - "DSP_ACOUT8", - "DSP_ACOUT9", - "DSP_BCOUT0", - "DSP_BCOUT1", - "DSP_BCOUT10", - "DSP_BCOUT11", - "DSP_BCOUT12", - "DSP_BCOUT13", - "DSP_BCOUT14", - "DSP_BCOUT15", - "DSP_BCOUT16", - "DSP_BCOUT17", - "DSP_BCOUT2", - "DSP_BCOUT3", - "DSP_BCOUT4", - "DSP_BCOUT5", - "DSP_BCOUT6", - "DSP_BCOUT7", - "DSP_BCOUT8", - "DSP_BCOUT9", - "DSP_BLOCK_OUTS_B0_0", - "DSP_BLOCK_OUTS_B0_1", - "DSP_BLOCK_OUTS_B0_2", - "DSP_BLOCK_OUTS_B0_3", - "DSP_BLOCK_OUTS_B0_4", - "DSP_BLOCK_OUTS_B1_0", - "DSP_BLOCK_OUTS_B1_1", - "DSP_BLOCK_OUTS_B1_2", - "DSP_BLOCK_OUTS_B1_3", - "DSP_BLOCK_OUTS_B1_4", - "DSP_BLOCK_OUTS_B2_0", - "DSP_BLOCK_OUTS_B2_1", - "DSP_BLOCK_OUTS_B2_2", - "DSP_BLOCK_OUTS_B2_3", - "DSP_BLOCK_OUTS_B2_4", - "DSP_BLOCK_OUTS_B3_0", - "DSP_BLOCK_OUTS_B3_1", - "DSP_BLOCK_OUTS_B3_2", - "DSP_BLOCK_OUTS_B3_3", - "DSP_BLOCK_OUTS_B3_4", - "DSP_BYP0_0", - "DSP_BYP0_1", - "DSP_BYP0_2", - "DSP_BYP0_3", - "DSP_BYP0_4", - "DSP_BYP1_0", - "DSP_BYP1_1", - "DSP_BYP1_2", - "DSP_BYP1_3", - "DSP_BYP1_4", - "DSP_BYP2_0", - "DSP_BYP2_1", - "DSP_BYP2_2", - "DSP_BYP2_3", - "DSP_BYP2_4", - "DSP_BYP3_0", - "DSP_BYP3_1", - "DSP_BYP3_2", - "DSP_BYP3_3", - "DSP_BYP3_4", - "DSP_BYP4_0", - "DSP_BYP4_1", - "DSP_BYP4_2", - "DSP_BYP4_3", - "DSP_BYP4_4", - "DSP_BYP5_0", - "DSP_BYP5_1", - "DSP_BYP5_2", - "DSP_BYP5_3", - "DSP_BYP5_4", - "DSP_BYP6_0", - "DSP_BYP6_1", - "DSP_BYP6_2", - "DSP_BYP6_3", - "DSP_BYP6_4", - "DSP_BYP7_0", - "DSP_BYP7_1", - "DSP_BYP7_2", - "DSP_BYP7_3", - "DSP_BYP7_4", - "DSP_CARRYCASCOUT", - "DSP_CLK0_0", - "DSP_CLK0_1", - "DSP_CLK0_2", - "DSP_CLK0_3", - "DSP_CLK0_4", - "DSP_CLK1_0", - "DSP_CLK1_1", - "DSP_CLK1_2", - "DSP_CLK1_3", - "DSP_CLK1_4", - "DSP_CTRL0_0", - "DSP_CTRL0_1", - "DSP_CTRL0_2", - "DSP_CTRL0_3", - "DSP_CTRL0_4", - "DSP_CTRL1_0", - "DSP_CTRL1_1", - "DSP_CTRL1_2", - "DSP_CTRL1_3", - "DSP_CTRL1_4", - "DSP_EE2A0_0", - "DSP_EE2A0_1", - "DSP_EE2A0_2", - "DSP_EE2A0_3", - "DSP_EE2A0_4", - "DSP_EE2A1_0", - "DSP_EE2A1_1", - "DSP_EE2A1_2", - "DSP_EE2A1_3", - "DSP_EE2A1_4", - "DSP_EE2A2_0", - "DSP_EE2A2_1", - "DSP_EE2A2_2", - "DSP_EE2A2_3", - "DSP_EE2A2_4", - "DSP_EE2A3_0", - "DSP_EE2A3_1", - "DSP_EE2A3_2", - "DSP_EE2A3_3", - "DSP_EE2A3_4", - "DSP_EE2BEG0_0", - "DSP_EE2BEG0_1", - "DSP_EE2BEG0_2", - "DSP_EE2BEG0_3", - "DSP_EE2BEG0_4", - "DSP_EE2BEG1_0", - "DSP_EE2BEG1_1", - "DSP_EE2BEG1_2", - "DSP_EE2BEG1_3", - "DSP_EE2BEG1_4", - "DSP_EE2BEG2_0", - "DSP_EE2BEG2_1", - "DSP_EE2BEG2_2", - "DSP_EE2BEG2_3", - "DSP_EE2BEG2_4", - "DSP_EE2BEG3_0", - "DSP_EE2BEG3_1", - "DSP_EE2BEG3_2", - "DSP_EE2BEG3_3", - "DSP_EE2BEG3_4", - "DSP_EE4A0_0", - "DSP_EE4A0_1", - "DSP_EE4A0_2", - "DSP_EE4A0_3", - "DSP_EE4A0_4", - "DSP_EE4A1_0", - "DSP_EE4A1_1", - "DSP_EE4A1_2", - "DSP_EE4A1_3", - "DSP_EE4A1_4", - "DSP_EE4A2_0", - "DSP_EE4A2_1", - "DSP_EE4A2_2", - "DSP_EE4A2_3", - "DSP_EE4A2_4", - "DSP_EE4A3_0", - "DSP_EE4A3_1", - "DSP_EE4A3_2", - "DSP_EE4A3_3", - "DSP_EE4A3_4", - "DSP_EE4B0_0", - "DSP_EE4B0_1", - "DSP_EE4B0_2", - "DSP_EE4B0_3", - "DSP_EE4B0_4", - "DSP_EE4B1_0", - "DSP_EE4B1_1", - "DSP_EE4B1_2", - "DSP_EE4B1_3", - "DSP_EE4B1_4", - "DSP_EE4B2_0", - "DSP_EE4B2_1", - "DSP_EE4B2_2", - "DSP_EE4B2_3", - "DSP_EE4B2_4", - "DSP_EE4B3_0", - "DSP_EE4B3_1", - "DSP_EE4B3_2", - "DSP_EE4B3_3", - "DSP_EE4B3_4", - "DSP_EE4BEG0_0", - "DSP_EE4BEG0_1", - "DSP_EE4BEG0_2", - "DSP_EE4BEG0_3", - "DSP_EE4BEG0_4", - "DSP_EE4BEG1_0", - "DSP_EE4BEG1_1", - "DSP_EE4BEG1_2", - "DSP_EE4BEG1_3", - "DSP_EE4BEG1_4", - "DSP_EE4BEG2_0", - "DSP_EE4BEG2_1", - "DSP_EE4BEG2_2", - "DSP_EE4BEG2_3", - "DSP_EE4BEG2_4", - "DSP_EE4BEG3_0", - "DSP_EE4BEG3_1", - "DSP_EE4BEG3_2", - "DSP_EE4BEG3_3", - "DSP_EE4BEG3_4", - "DSP_EE4C0_0", - "DSP_EE4C0_1", - "DSP_EE4C0_2", - "DSP_EE4C0_3", - "DSP_EE4C0_4", - "DSP_EE4C1_0", - "DSP_EE4C1_1", - "DSP_EE4C1_2", - "DSP_EE4C1_3", - "DSP_EE4C1_4", - "DSP_EE4C2_0", - "DSP_EE4C2_1", - "DSP_EE4C2_2", - "DSP_EE4C2_3", - "DSP_EE4C2_4", - "DSP_EE4C3_0", - "DSP_EE4C3_1", - "DSP_EE4C3_2", - "DSP_EE4C3_3", - "DSP_EE4C3_4", - "DSP_EL1BEG0_0", - "DSP_EL1BEG0_1", - "DSP_EL1BEG0_2", - "DSP_EL1BEG0_3", - "DSP_EL1BEG0_4", - "DSP_EL1BEG1_0", - "DSP_EL1BEG1_1", - "DSP_EL1BEG1_2", - "DSP_EL1BEG1_3", - "DSP_EL1BEG1_4", - "DSP_EL1BEG2_0", - "DSP_EL1BEG2_1", - "DSP_EL1BEG2_2", - "DSP_EL1BEG2_3", - "DSP_EL1BEG2_4", - "DSP_EL1BEG3_0", - "DSP_EL1BEG3_1", - "DSP_EL1BEG3_2", - "DSP_EL1BEG3_3", - "DSP_EL1BEG3_4", - "DSP_ER1BEG0_0", - "DSP_ER1BEG0_1", - "DSP_ER1BEG0_2", - "DSP_ER1BEG0_3", - "DSP_ER1BEG0_4", - "DSP_ER1BEG1_0", - "DSP_ER1BEG1_1", - "DSP_ER1BEG1_2", - "DSP_ER1BEG1_3", - "DSP_ER1BEG1_4", - "DSP_ER1BEG2_0", - "DSP_ER1BEG2_1", - "DSP_ER1BEG2_2", - "DSP_ER1BEG2_3", - "DSP_ER1BEG2_4", - "DSP_ER1BEG3_0", - "DSP_ER1BEG3_1", - "DSP_ER1BEG3_2", - "DSP_ER1BEG3_3", - "DSP_ER1BEG3_4", - "DSP_FAN0_0", - "DSP_FAN0_1", - "DSP_FAN0_2", - "DSP_FAN0_3", - "DSP_FAN0_4", - "DSP_FAN1_0", - "DSP_FAN1_1", - "DSP_FAN1_2", - "DSP_FAN1_3", - "DSP_FAN1_4", - "DSP_FAN2_0", - "DSP_FAN2_1", - "DSP_FAN2_2", - "DSP_FAN2_3", - "DSP_FAN2_4", - "DSP_FAN3_0", - "DSP_FAN3_1", - "DSP_FAN3_2", - "DSP_FAN3_3", - "DSP_FAN3_4", - "DSP_FAN4_0", - "DSP_FAN4_1", - "DSP_FAN4_2", - "DSP_FAN4_3", - "DSP_FAN4_4", - "DSP_FAN5_0", - "DSP_FAN5_1", - "DSP_FAN5_2", - "DSP_FAN5_3", - "DSP_FAN5_4", - "DSP_FAN6_0", - "DSP_FAN6_1", - "DSP_FAN6_2", - "DSP_FAN6_3", - "DSP_FAN6_4", - "DSP_FAN7_0", - "DSP_FAN7_1", - "DSP_FAN7_2", - "DSP_FAN7_3", - "DSP_FAN7_4", - "DSP_GND_L", - "DSP_IMUX0_0", - "DSP_IMUX0_1", - "DSP_IMUX0_2", - "DSP_IMUX0_3", - "DSP_IMUX0_4", - "DSP_IMUX10_0", - "DSP_IMUX10_1", - "DSP_IMUX10_2", - "DSP_IMUX10_3", - "DSP_IMUX10_4", - "DSP_IMUX11_0", - "DSP_IMUX11_1", - "DSP_IMUX11_2", - "DSP_IMUX11_3", - "DSP_IMUX11_4", - "DSP_IMUX12_0", - "DSP_IMUX12_1", - "DSP_IMUX12_2", - "DSP_IMUX12_3", - "DSP_IMUX12_4", - "DSP_IMUX13_0", - "DSP_IMUX13_1", - "DSP_IMUX13_2", - "DSP_IMUX13_3", - "DSP_IMUX13_4", - "DSP_IMUX14_0", - "DSP_IMUX14_1", - "DSP_IMUX14_2", - "DSP_IMUX14_3", - "DSP_IMUX14_4", - "DSP_IMUX15_0", - "DSP_IMUX15_1", - "DSP_IMUX15_2", - "DSP_IMUX15_3", - "DSP_IMUX15_4", - "DSP_IMUX16_0", - "DSP_IMUX16_1", - "DSP_IMUX16_2", - "DSP_IMUX16_3", - "DSP_IMUX16_4", - "DSP_IMUX17_0", - "DSP_IMUX17_1", - "DSP_IMUX17_2", - "DSP_IMUX17_3", - "DSP_IMUX17_4", - "DSP_IMUX18_0", - "DSP_IMUX18_1", - "DSP_IMUX18_2", - "DSP_IMUX18_3", - "DSP_IMUX18_4", - "DSP_IMUX19_0", - "DSP_IMUX19_1", - "DSP_IMUX19_2", - "DSP_IMUX19_3", - "DSP_IMUX19_4", - "DSP_IMUX1_0", - "DSP_IMUX1_1", - "DSP_IMUX1_2", - "DSP_IMUX1_3", - "DSP_IMUX1_4", - "DSP_IMUX20_0", - "DSP_IMUX20_1", - "DSP_IMUX20_2", - "DSP_IMUX20_3", - "DSP_IMUX20_4", - "DSP_IMUX21_0", - "DSP_IMUX21_1", - "DSP_IMUX21_2", - "DSP_IMUX21_3", - "DSP_IMUX21_4", - "DSP_IMUX22_0", - "DSP_IMUX22_1", - "DSP_IMUX22_2", - "DSP_IMUX22_3", - "DSP_IMUX22_4", - "DSP_IMUX23_0", - "DSP_IMUX23_1", - "DSP_IMUX23_2", - "DSP_IMUX23_3", - "DSP_IMUX23_4", - "DSP_IMUX24_0", - "DSP_IMUX24_1", - "DSP_IMUX24_2", - "DSP_IMUX24_3", - "DSP_IMUX24_4", - "DSP_IMUX25_0", - "DSP_IMUX25_1", - "DSP_IMUX25_2", - "DSP_IMUX25_3", - "DSP_IMUX25_4", - "DSP_IMUX26_0", - "DSP_IMUX26_1", - "DSP_IMUX26_2", - "DSP_IMUX26_3", - "DSP_IMUX26_4", - "DSP_IMUX27_0", - "DSP_IMUX27_1", - "DSP_IMUX27_2", - "DSP_IMUX27_3", - "DSP_IMUX27_4", - "DSP_IMUX28_0", - "DSP_IMUX28_1", - "DSP_IMUX28_2", - "DSP_IMUX28_3", - "DSP_IMUX28_4", - "DSP_IMUX29_0", - "DSP_IMUX29_1", - "DSP_IMUX29_2", - "DSP_IMUX29_3", - "DSP_IMUX29_4", - "DSP_IMUX2_0", - "DSP_IMUX2_1", - "DSP_IMUX2_2", - "DSP_IMUX2_3", - "DSP_IMUX2_4", - "DSP_IMUX30_0", - "DSP_IMUX30_1", - "DSP_IMUX30_2", - "DSP_IMUX30_3", - "DSP_IMUX30_4", - "DSP_IMUX31_0", - "DSP_IMUX31_1", - "DSP_IMUX31_2", - "DSP_IMUX31_3", - "DSP_IMUX31_4", - "DSP_IMUX32_0", - "DSP_IMUX32_1", - "DSP_IMUX32_2", - "DSP_IMUX32_3", - "DSP_IMUX32_4", - "DSP_IMUX33_0", - "DSP_IMUX33_1", - "DSP_IMUX33_2", - "DSP_IMUX33_3", - "DSP_IMUX33_4", - "DSP_IMUX34_0", - "DSP_IMUX34_1", - "DSP_IMUX34_2", - "DSP_IMUX34_3", - "DSP_IMUX34_4", - "DSP_IMUX35_0", - "DSP_IMUX35_1", - "DSP_IMUX35_2", - "DSP_IMUX35_3", - "DSP_IMUX35_4", - "DSP_IMUX36_0", - "DSP_IMUX36_1", - "DSP_IMUX36_2", - "DSP_IMUX36_3", - "DSP_IMUX36_4", - "DSP_IMUX37_0", - "DSP_IMUX37_1", - "DSP_IMUX37_2", - "DSP_IMUX37_3", - "DSP_IMUX37_4", - "DSP_IMUX38_0", - "DSP_IMUX38_1", - "DSP_IMUX38_2", - "DSP_IMUX38_3", - "DSP_IMUX38_4", - "DSP_IMUX39_0", - "DSP_IMUX39_1", - "DSP_IMUX39_2", - "DSP_IMUX39_3", - "DSP_IMUX39_4", - "DSP_IMUX3_0", - "DSP_IMUX3_1", - "DSP_IMUX3_2", - "DSP_IMUX3_3", - "DSP_IMUX3_4", - "DSP_IMUX40_0", - "DSP_IMUX40_1", - "DSP_IMUX40_2", - "DSP_IMUX40_3", - "DSP_IMUX40_4", - "DSP_IMUX41_0", - "DSP_IMUX41_1", - "DSP_IMUX41_2", - "DSP_IMUX41_3", - "DSP_IMUX41_4", - "DSP_IMUX42_0", - "DSP_IMUX42_1", - "DSP_IMUX42_2", - "DSP_IMUX42_3", - "DSP_IMUX42_4", - "DSP_IMUX43_0", - "DSP_IMUX43_1", - "DSP_IMUX43_2", - "DSP_IMUX43_3", - "DSP_IMUX43_4", - "DSP_IMUX44_0", - "DSP_IMUX44_1", - "DSP_IMUX44_2", - "DSP_IMUX44_3", - "DSP_IMUX44_4", - "DSP_IMUX45_0", - "DSP_IMUX45_1", - "DSP_IMUX45_2", - "DSP_IMUX45_3", - "DSP_IMUX45_4", - "DSP_IMUX46_0", - "DSP_IMUX46_1", - "DSP_IMUX46_2", - "DSP_IMUX46_3", - "DSP_IMUX46_4", - "DSP_IMUX47_0", - "DSP_IMUX47_1", - "DSP_IMUX47_2", - "DSP_IMUX47_3", - "DSP_IMUX47_4", - "DSP_IMUX4_0", - "DSP_IMUX4_1", - "DSP_IMUX4_2", - "DSP_IMUX4_3", - "DSP_IMUX4_4", - "DSP_IMUX5_0", - "DSP_IMUX5_1", - "DSP_IMUX5_2", - "DSP_IMUX5_3", - "DSP_IMUX5_4", - "DSP_IMUX6_0", - "DSP_IMUX6_1", - "DSP_IMUX6_2", - "DSP_IMUX6_3", - "DSP_IMUX6_4", - "DSP_IMUX7_0", - "DSP_IMUX7_1", - "DSP_IMUX7_2", - "DSP_IMUX7_3", - "DSP_IMUX7_4", - "DSP_IMUX8_0", - "DSP_IMUX8_1", - "DSP_IMUX8_2", - "DSP_IMUX8_3", - "DSP_IMUX8_4", - "DSP_IMUX9_0", - "DSP_IMUX9_1", - "DSP_IMUX9_2", - "DSP_IMUX9_3", - "DSP_IMUX9_4", - "DSP_LH10_0", - "DSP_LH10_1", - "DSP_LH10_2", - "DSP_LH10_3", - "DSP_LH10_4", - "DSP_LH11_0", - "DSP_LH11_1", - "DSP_LH11_2", - "DSP_LH11_3", - "DSP_LH11_4", - "DSP_LH12_0", - "DSP_LH12_1", - "DSP_LH12_2", - "DSP_LH12_3", - "DSP_LH12_4", - "DSP_LH1_0", - "DSP_LH1_1", - "DSP_LH1_2", - "DSP_LH1_3", - "DSP_LH1_4", - "DSP_LH2_0", - "DSP_LH2_1", - "DSP_LH2_2", - "DSP_LH2_3", - "DSP_LH2_4", - "DSP_LH3_0", - "DSP_LH3_1", - "DSP_LH3_2", - "DSP_LH3_3", - "DSP_LH3_4", - "DSP_LH4_0", - "DSP_LH4_1", - "DSP_LH4_2", - "DSP_LH4_3", - "DSP_LH4_4", - "DSP_LH5_0", - "DSP_LH5_1", - "DSP_LH5_2", - "DSP_LH5_3", - "DSP_LH5_4", - "DSP_LH6_0", - "DSP_LH6_1", - "DSP_LH6_2", - "DSP_LH6_3", - "DSP_LH6_4", - "DSP_LH7_0", - "DSP_LH7_1", - "DSP_LH7_2", - "DSP_LH7_3", - "DSP_LH7_4", - "DSP_LH8_0", - "DSP_LH8_1", - "DSP_LH8_2", - "DSP_LH8_3", - "DSP_LH8_4", - "DSP_LH9_0", - "DSP_LH9_1", - "DSP_LH9_2", - "DSP_LH9_3", - "DSP_LH9_4", - "DSP_LOGIC_OUTS_B0_0", - "DSP_LOGIC_OUTS_B0_1", - "DSP_LOGIC_OUTS_B0_2", - "DSP_LOGIC_OUTS_B0_3", - "DSP_LOGIC_OUTS_B0_4", - "DSP_LOGIC_OUTS_B10_0", - "DSP_LOGIC_OUTS_B10_1", - "DSP_LOGIC_OUTS_B10_2", - "DSP_LOGIC_OUTS_B10_3", - "DSP_LOGIC_OUTS_B10_4", - "DSP_LOGIC_OUTS_B11_0", - "DSP_LOGIC_OUTS_B11_1", - "DSP_LOGIC_OUTS_B11_2", - "DSP_LOGIC_OUTS_B11_3", - "DSP_LOGIC_OUTS_B11_4", - "DSP_LOGIC_OUTS_B12_0", - "DSP_LOGIC_OUTS_B12_1", - "DSP_LOGIC_OUTS_B12_2", - "DSP_LOGIC_OUTS_B12_3", - "DSP_LOGIC_OUTS_B12_4", - "DSP_LOGIC_OUTS_B13_0", - "DSP_LOGIC_OUTS_B13_1", - "DSP_LOGIC_OUTS_B13_2", - "DSP_LOGIC_OUTS_B13_3", - "DSP_LOGIC_OUTS_B13_4", - "DSP_LOGIC_OUTS_B14_0", - "DSP_LOGIC_OUTS_B14_1", - "DSP_LOGIC_OUTS_B14_2", - "DSP_LOGIC_OUTS_B14_3", - "DSP_LOGIC_OUTS_B14_4", - "DSP_LOGIC_OUTS_B15_0", - "DSP_LOGIC_OUTS_B15_1", - "DSP_LOGIC_OUTS_B15_2", - "DSP_LOGIC_OUTS_B15_3", - "DSP_LOGIC_OUTS_B15_4", - "DSP_LOGIC_OUTS_B16_0", - "DSP_LOGIC_OUTS_B16_1", - "DSP_LOGIC_OUTS_B16_2", - "DSP_LOGIC_OUTS_B16_3", - "DSP_LOGIC_OUTS_B16_4", - "DSP_LOGIC_OUTS_B17_0", - "DSP_LOGIC_OUTS_B17_1", - "DSP_LOGIC_OUTS_B17_2", - "DSP_LOGIC_OUTS_B17_3", - "DSP_LOGIC_OUTS_B17_4", - "DSP_LOGIC_OUTS_B18_0", - "DSP_LOGIC_OUTS_B18_1", - "DSP_LOGIC_OUTS_B18_2", - "DSP_LOGIC_OUTS_B18_3", - "DSP_LOGIC_OUTS_B18_4", - "DSP_LOGIC_OUTS_B19_0", - "DSP_LOGIC_OUTS_B19_1", - "DSP_LOGIC_OUTS_B19_2", - "DSP_LOGIC_OUTS_B19_3", - "DSP_LOGIC_OUTS_B19_4", - "DSP_LOGIC_OUTS_B1_0", - "DSP_LOGIC_OUTS_B1_1", - "DSP_LOGIC_OUTS_B1_2", - "DSP_LOGIC_OUTS_B1_3", - "DSP_LOGIC_OUTS_B1_4", - "DSP_LOGIC_OUTS_B20_0", - "DSP_LOGIC_OUTS_B20_1", - "DSP_LOGIC_OUTS_B20_2", - "DSP_LOGIC_OUTS_B20_3", - "DSP_LOGIC_OUTS_B20_4", - "DSP_LOGIC_OUTS_B21_0", - "DSP_LOGIC_OUTS_B21_1", - "DSP_LOGIC_OUTS_B21_2", - "DSP_LOGIC_OUTS_B21_3", - "DSP_LOGIC_OUTS_B21_4", - "DSP_LOGIC_OUTS_B22_0", - "DSP_LOGIC_OUTS_B22_1", - "DSP_LOGIC_OUTS_B22_2", - "DSP_LOGIC_OUTS_B22_3", - "DSP_LOGIC_OUTS_B22_4", - "DSP_LOGIC_OUTS_B23_0", - "DSP_LOGIC_OUTS_B23_1", - "DSP_LOGIC_OUTS_B23_2", - "DSP_LOGIC_OUTS_B23_3", - "DSP_LOGIC_OUTS_B23_4", - "DSP_LOGIC_OUTS_B2_0", - "DSP_LOGIC_OUTS_B2_1", - "DSP_LOGIC_OUTS_B2_2", - "DSP_LOGIC_OUTS_B2_3", - "DSP_LOGIC_OUTS_B2_4", - "DSP_LOGIC_OUTS_B3_0", - "DSP_LOGIC_OUTS_B3_1", - "DSP_LOGIC_OUTS_B3_2", - "DSP_LOGIC_OUTS_B3_3", - "DSP_LOGIC_OUTS_B3_4", - "DSP_LOGIC_OUTS_B4_0", - "DSP_LOGIC_OUTS_B4_1", - "DSP_LOGIC_OUTS_B4_2", - "DSP_LOGIC_OUTS_B4_3", - "DSP_LOGIC_OUTS_B4_4", - "DSP_LOGIC_OUTS_B5_0", - "DSP_LOGIC_OUTS_B5_1", - "DSP_LOGIC_OUTS_B5_2", - "DSP_LOGIC_OUTS_B5_3", - "DSP_LOGIC_OUTS_B5_4", - "DSP_LOGIC_OUTS_B6_0", - "DSP_LOGIC_OUTS_B6_1", - "DSP_LOGIC_OUTS_B6_2", - "DSP_LOGIC_OUTS_B6_3", - "DSP_LOGIC_OUTS_B6_4", - "DSP_LOGIC_OUTS_B7_0", - "DSP_LOGIC_OUTS_B7_1", - "DSP_LOGIC_OUTS_B7_2", - "DSP_LOGIC_OUTS_B7_3", - "DSP_LOGIC_OUTS_B7_4", - "DSP_LOGIC_OUTS_B8_0", - "DSP_LOGIC_OUTS_B8_1", - "DSP_LOGIC_OUTS_B8_2", - "DSP_LOGIC_OUTS_B8_3", - "DSP_LOGIC_OUTS_B8_4", - "DSP_LOGIC_OUTS_B9_0", - "DSP_LOGIC_OUTS_B9_1", - "DSP_LOGIC_OUTS_B9_2", - "DSP_LOGIC_OUTS_B9_3", - "DSP_LOGIC_OUTS_B9_4", - "DSP_MONITOR_N_0", - "DSP_MONITOR_N_1", - "DSP_MONITOR_N_2", - "DSP_MONITOR_N_3", - "DSP_MONITOR_N_4", - "DSP_MONITOR_P_0", - "DSP_MONITOR_P_1", - "DSP_MONITOR_P_2", - "DSP_MONITOR_P_3", - "DSP_MONITOR_P_4", - "DSP_MULTSIGNOUT", - "DSP_NE2A0_0", - "DSP_NE2A0_1", - "DSP_NE2A0_2", - "DSP_NE2A0_3", - "DSP_NE2A0_4", - "DSP_NE2A1_0", - "DSP_NE2A1_1", - "DSP_NE2A1_2", - "DSP_NE2A1_3", - "DSP_NE2A1_4", - "DSP_NE2A2_0", - "DSP_NE2A2_1", - "DSP_NE2A2_2", - "DSP_NE2A2_3", - "DSP_NE2A2_4", - "DSP_NE2A3_0", - "DSP_NE2A3_1", - "DSP_NE2A3_2", - "DSP_NE2A3_3", - "DSP_NE2A3_4", - "DSP_NE4BEG0_0", - "DSP_NE4BEG0_1", - "DSP_NE4BEG0_2", - "DSP_NE4BEG0_3", - "DSP_NE4BEG0_4", - "DSP_NE4BEG1_0", - "DSP_NE4BEG1_1", - "DSP_NE4BEG1_2", - "DSP_NE4BEG1_3", - "DSP_NE4BEG1_4", - "DSP_NE4BEG2_0", - "DSP_NE4BEG2_1", - "DSP_NE4BEG2_2", - "DSP_NE4BEG2_3", - "DSP_NE4BEG2_4", - "DSP_NE4BEG3_0", - "DSP_NE4BEG3_1", - "DSP_NE4BEG3_2", - "DSP_NE4BEG3_3", - "DSP_NE4BEG3_4", - "DSP_NE4C0_0", - "DSP_NE4C0_1", - "DSP_NE4C0_2", - "DSP_NE4C0_3", - "DSP_NE4C0_4", - "DSP_NE4C1_0", - "DSP_NE4C1_1", - "DSP_NE4C1_2", - "DSP_NE4C1_3", - "DSP_NE4C1_4", - "DSP_NE4C2_0", - "DSP_NE4C2_1", - "DSP_NE4C2_2", - "DSP_NE4C2_3", - "DSP_NE4C2_4", - "DSP_NE4C3_0", - "DSP_NE4C3_1", - "DSP_NE4C3_2", - "DSP_NE4C3_3", - "DSP_NE4C3_4", - "DSP_NW2A0_0", - "DSP_NW2A0_1", - "DSP_NW2A0_2", - "DSP_NW2A0_3", - "DSP_NW2A0_4", - "DSP_NW2A1_0", - "DSP_NW2A1_1", - "DSP_NW2A1_2", - "DSP_NW2A1_3", - "DSP_NW2A1_4", - "DSP_NW2A2_0", - "DSP_NW2A2_1", - "DSP_NW2A2_2", - "DSP_NW2A2_3", - "DSP_NW2A2_4", - "DSP_NW2A3_0", - "DSP_NW2A3_1", - "DSP_NW2A3_2", - "DSP_NW2A3_3", - "DSP_NW2A3_4", - "DSP_NW4A0_0", - "DSP_NW4A0_1", - "DSP_NW4A0_2", - "DSP_NW4A0_3", - "DSP_NW4A0_4", - "DSP_NW4A1_0", - "DSP_NW4A1_1", - "DSP_NW4A1_2", - "DSP_NW4A1_3", - "DSP_NW4A1_4", - "DSP_NW4A2_0", - "DSP_NW4A2_1", - "DSP_NW4A2_2", - "DSP_NW4A2_3", - "DSP_NW4A2_4", - "DSP_NW4A3_0", - "DSP_NW4A3_1", - "DSP_NW4A3_2", - "DSP_NW4A3_3", - "DSP_NW4A3_4", - "DSP_NW4END0_0", - "DSP_NW4END0_1", - "DSP_NW4END0_2", - "DSP_NW4END0_3", - "DSP_NW4END0_4", - "DSP_NW4END1_0", - "DSP_NW4END1_1", - "DSP_NW4END1_2", - "DSP_NW4END1_3", - "DSP_NW4END1_4", - "DSP_NW4END2_0", - "DSP_NW4END2_1", - "DSP_NW4END2_2", - "DSP_NW4END2_3", - "DSP_NW4END2_4", - "DSP_NW4END3_0", - "DSP_NW4END3_1", - "DSP_NW4END3_2", - "DSP_NW4END3_3", - "DSP_NW4END3_4", - "DSP_PCOUT0", - "DSP_PCOUT1", - "DSP_PCOUT10", - "DSP_PCOUT11", - "DSP_PCOUT12", - "DSP_PCOUT13", - "DSP_PCOUT14", - "DSP_PCOUT15", - "DSP_PCOUT16", - "DSP_PCOUT17", - "DSP_PCOUT18", - "DSP_PCOUT19", - "DSP_PCOUT2", - "DSP_PCOUT20", - "DSP_PCOUT21", - "DSP_PCOUT22", - "DSP_PCOUT23", - "DSP_PCOUT24", - "DSP_PCOUT25", - "DSP_PCOUT26", - "DSP_PCOUT27", - "DSP_PCOUT28", - "DSP_PCOUT29", - "DSP_PCOUT3", - "DSP_PCOUT30", - "DSP_PCOUT31", - "DSP_PCOUT32", - "DSP_PCOUT33", - "DSP_PCOUT34", - "DSP_PCOUT35", - "DSP_PCOUT36", - "DSP_PCOUT37", - "DSP_PCOUT38", - "DSP_PCOUT39", - "DSP_PCOUT4", - "DSP_PCOUT40", - "DSP_PCOUT41", - "DSP_PCOUT42", - "DSP_PCOUT43", - "DSP_PCOUT44", - "DSP_PCOUT45", - "DSP_PCOUT46", - "DSP_PCOUT47", - "DSP_PCOUT5", - "DSP_PCOUT6", - "DSP_PCOUT7", - "DSP_PCOUT8", - "DSP_PCOUT9", - "DSP_SE2A0_0", - "DSP_SE2A0_1", - "DSP_SE2A0_2", - "DSP_SE2A0_3", - "DSP_SE2A0_4", - "DSP_SE2A1_0", - "DSP_SE2A1_1", - "DSP_SE2A1_2", - "DSP_SE2A1_3", - "DSP_SE2A1_4", - "DSP_SE2A2_0", - "DSP_SE2A2_1", - "DSP_SE2A2_2", - "DSP_SE2A2_3", - "DSP_SE2A2_4", - "DSP_SE2A3_0", - "DSP_SE2A3_1", - "DSP_SE2A3_2", - "DSP_SE2A3_3", - "DSP_SE2A3_4", - "DSP_SE4BEG0_0", - "DSP_SE4BEG0_1", - "DSP_SE4BEG0_2", - "DSP_SE4BEG0_3", - "DSP_SE4BEG0_4", - "DSP_SE4BEG1_0", - "DSP_SE4BEG1_1", - "DSP_SE4BEG1_2", - "DSP_SE4BEG1_3", - "DSP_SE4BEG1_4", - "DSP_SE4BEG2_0", - "DSP_SE4BEG2_1", - "DSP_SE4BEG2_2", - "DSP_SE4BEG2_3", - "DSP_SE4BEG2_4", - "DSP_SE4BEG3_0", - "DSP_SE4BEG3_1", - "DSP_SE4BEG3_2", - "DSP_SE4BEG3_3", - "DSP_SE4BEG3_4", - "DSP_SE4C0_0", - "DSP_SE4C0_1", - "DSP_SE4C0_2", - "DSP_SE4C0_3", - "DSP_SE4C0_4", - "DSP_SE4C1_0", - "DSP_SE4C1_1", - "DSP_SE4C1_2", - "DSP_SE4C1_3", - "DSP_SE4C1_4", - "DSP_SE4C2_0", - "DSP_SE4C2_1", - "DSP_SE4C2_2", - "DSP_SE4C2_3", - "DSP_SE4C2_4", - "DSP_SE4C3_0", - "DSP_SE4C3_1", - "DSP_SE4C3_2", - "DSP_SE4C3_3", - "DSP_SE4C3_4", - "DSP_SW2A0_0", - "DSP_SW2A0_1", - "DSP_SW2A0_2", - "DSP_SW2A0_3", - "DSP_SW2A0_4", - "DSP_SW2A1_0", - "DSP_SW2A1_1", - "DSP_SW2A1_2", - "DSP_SW2A1_3", - "DSP_SW2A1_4", - "DSP_SW2A2_0", - "DSP_SW2A2_1", - "DSP_SW2A2_2", - "DSP_SW2A2_3", - "DSP_SW2A2_4", - "DSP_SW2A3_0", - "DSP_SW2A3_1", - "DSP_SW2A3_2", - "DSP_SW2A3_3", - "DSP_SW2A3_4", - "DSP_SW4A0_0", - "DSP_SW4A0_1", - "DSP_SW4A0_2", - "DSP_SW4A0_3", - "DSP_SW4A0_4", - "DSP_SW4A1_0", - "DSP_SW4A1_1", - "DSP_SW4A1_2", - "DSP_SW4A1_3", - "DSP_SW4A1_4", - "DSP_SW4A2_0", - "DSP_SW4A2_1", - "DSP_SW4A2_2", - "DSP_SW4A2_3", - "DSP_SW4A2_4", - "DSP_SW4A3_0", - "DSP_SW4A3_1", - "DSP_SW4A3_2", - "DSP_SW4A3_3", - "DSP_SW4A3_4", - "DSP_SW4END0_0", - "DSP_SW4END0_1", - "DSP_SW4END0_2", - "DSP_SW4END0_3", - "DSP_SW4END0_4", - "DSP_SW4END1_0", - "DSP_SW4END1_1", - "DSP_SW4END1_2", - "DSP_SW4END1_3", - "DSP_SW4END1_4", - "DSP_SW4END2_0", - "DSP_SW4END2_1", - "DSP_SW4END2_2", - "DSP_SW4END2_3", - "DSP_SW4END2_4", - "DSP_SW4END3_0", - "DSP_SW4END3_1", - "DSP_SW4END3_2", - "DSP_SW4END3_3", - "DSP_SW4END3_4", - "DSP_VCC_L", - "DSP_WL1END0_0", - "DSP_WL1END0_1", - "DSP_WL1END0_2", - "DSP_WL1END0_3", - "DSP_WL1END0_4", - "DSP_WL1END1_0", - "DSP_WL1END1_1", - "DSP_WL1END1_2", - "DSP_WL1END1_3", - "DSP_WL1END1_4", - "DSP_WL1END2_0", - "DSP_WL1END2_1", - "DSP_WL1END2_2", - "DSP_WL1END2_3", - "DSP_WL1END2_4", - "DSP_WL1END3_0", - "DSP_WL1END3_1", - "DSP_WL1END3_2", - "DSP_WL1END3_3", - "DSP_WL1END3_4", - "DSP_WR1END0_0", - "DSP_WR1END0_1", - "DSP_WR1END0_2", - "DSP_WR1END0_3", - "DSP_WR1END0_4", - "DSP_WR1END1_0", - "DSP_WR1END1_1", - "DSP_WR1END1_2", - "DSP_WR1END1_3", - "DSP_WR1END1_4", - "DSP_WR1END2_0", - "DSP_WR1END2_1", - "DSP_WR1END2_2", - "DSP_WR1END2_3", - "DSP_WR1END2_4", - "DSP_WR1END3_0", - "DSP_WR1END3_1", - "DSP_WR1END3_2", - "DSP_WR1END3_3", - "DSP_WR1END3_4", - "DSP_WW2A0_0", - "DSP_WW2A0_1", - "DSP_WW2A0_2", - "DSP_WW2A0_3", - "DSP_WW2A0_4", - "DSP_WW2A1_0", - "DSP_WW2A1_1", - "DSP_WW2A1_2", - "DSP_WW2A1_3", - "DSP_WW2A1_4", - "DSP_WW2A2_0", - "DSP_WW2A2_1", - "DSP_WW2A2_2", - "DSP_WW2A2_3", - "DSP_WW2A2_4", - "DSP_WW2A3_0", - "DSP_WW2A3_1", - "DSP_WW2A3_2", - "DSP_WW2A3_3", - "DSP_WW2A3_4", - "DSP_WW2END0_0", - "DSP_WW2END0_1", - "DSP_WW2END0_2", - "DSP_WW2END0_3", - "DSP_WW2END0_4", - "DSP_WW2END1_0", - "DSP_WW2END1_1", - "DSP_WW2END1_2", - "DSP_WW2END1_3", - "DSP_WW2END1_4", - "DSP_WW2END2_0", - "DSP_WW2END2_1", - "DSP_WW2END2_2", - "DSP_WW2END2_3", - "DSP_WW2END2_4", - "DSP_WW2END3_0", - "DSP_WW2END3_1", - "DSP_WW2END3_2", - "DSP_WW2END3_3", - "DSP_WW2END3_4", - "DSP_WW4A0_0", - "DSP_WW4A0_1", - "DSP_WW4A0_2", - "DSP_WW4A0_3", - "DSP_WW4A0_4", - "DSP_WW4A1_0", - "DSP_WW4A1_1", - "DSP_WW4A1_2", - "DSP_WW4A1_3", - "DSP_WW4A1_4", - "DSP_WW4A2_0", - "DSP_WW4A2_1", - "DSP_WW4A2_2", - "DSP_WW4A2_3", - "DSP_WW4A2_4", - "DSP_WW4A3_0", - "DSP_WW4A3_1", - "DSP_WW4A3_2", - "DSP_WW4A3_3", - "DSP_WW4A3_4", - "DSP_WW4B0_0", - "DSP_WW4B0_1", - "DSP_WW4B0_2", - "DSP_WW4B0_3", - "DSP_WW4B0_4", - "DSP_WW4B1_0", - "DSP_WW4B1_1", - "DSP_WW4B1_2", - "DSP_WW4B1_3", - "DSP_WW4B1_4", - "DSP_WW4B2_0", - "DSP_WW4B2_1", - "DSP_WW4B2_2", - "DSP_WW4B2_3", - "DSP_WW4B2_4", - "DSP_WW4B3_0", - "DSP_WW4B3_1", - "DSP_WW4B3_2", - "DSP_WW4B3_3", - "DSP_WW4B3_4", - "DSP_WW4C0_0", - "DSP_WW4C0_1", - "DSP_WW4C0_2", - "DSP_WW4C0_3", - "DSP_WW4C0_4", - "DSP_WW4C1_0", - "DSP_WW4C1_1", - "DSP_WW4C1_2", - "DSP_WW4C1_3", - "DSP_WW4C1_4", - "DSP_WW4C2_0", - "DSP_WW4C2_1", - "DSP_WW4C2_2", - "DSP_WW4C2_3", - "DSP_WW4C2_4", - "DSP_WW4C3_0", - "DSP_WW4C3_1", - "DSP_WW4C3_2", - "DSP_WW4C3_3", - "DSP_WW4C3_4", - "DSP_WW4END0_0", - "DSP_WW4END0_1", - "DSP_WW4END0_2", - "DSP_WW4END0_3", - "DSP_WW4END0_4", - "DSP_WW4END1_0", - "DSP_WW4END1_1", - "DSP_WW4END1_2", - "DSP_WW4END1_3", - "DSP_WW4END1_4", - "DSP_WW4END2_0", - "DSP_WW4END2_1", - "DSP_WW4END2_2", - "DSP_WW4END2_3", - "DSP_WW4END2_4", - "DSP_WW4END3_0", - "DSP_WW4END3_1", - "DSP_WW4END3_2", - "DSP_WW4END3_3", - "DSP_WW4END3_4" - ] + "wires": { + "DSP_0_A0": { + "cap": "57.597", + "res": "0.000" + }, + "DSP_0_A1": { + "cap": "57.597", + "res": "0.000" + }, + "DSP_0_A10": { + "cap": "57.597", + "res": "0.000" + }, + "DSP_0_A11": { + "cap": "57.597", + "res": "0.000" + }, + "DSP_0_A12": { + "cap": "57.597", + "res": "0.000" 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"res": "47.430" + }, + "DSP_WW4C0_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C0_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C0_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C0_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C0_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C1_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C1_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C1_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C1_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C1_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C2_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C2_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C2_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C2_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C2_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C3_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C3_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C3_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C3_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C3_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END0_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END0_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END0_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END0_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END0_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END1_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END1_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END1_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END1_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END1_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END2_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END2_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END2_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END2_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END2_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END3_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END3_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END3_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END3_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END3_4": { + "cap": "11.000", + "res": "47.430" + } + } } diff --git a/zynq7/tile_type_DSP_R.json b/zynq7/tile_type_DSP_R.json index e0e7135..e583080 100644 --- a/zynq7/tile_type_DSP_R.json +++ b/zynq7/tile_type_DSP_R.json @@ -2,5560 +2,14294 @@ "pips": { "DSP_R.DSP_0_ACOUT0->DSP_1_ACIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT0" }, "DSP_R.DSP_0_ACOUT1->DSP_1_ACIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT1" }, "DSP_R.DSP_0_ACOUT10->DSP_1_ACIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT10" }, "DSP_R.DSP_0_ACOUT11->DSP_1_ACIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT11" }, "DSP_R.DSP_0_ACOUT12->DSP_1_ACIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT12" }, "DSP_R.DSP_0_ACOUT13->DSP_1_ACIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT13" }, "DSP_R.DSP_0_ACOUT14->DSP_1_ACIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT14" }, "DSP_R.DSP_0_ACOUT15->DSP_1_ACIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT15" }, "DSP_R.DSP_0_ACOUT16->DSP_1_ACIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT16" }, "DSP_R.DSP_0_ACOUT17->DSP_1_ACIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT17" }, "DSP_R.DSP_0_ACOUT18->DSP_1_ACIN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT18" }, "DSP_R.DSP_0_ACOUT19->DSP_1_ACIN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT19" }, "DSP_R.DSP_0_ACOUT2->DSP_1_ACIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT2" }, "DSP_R.DSP_0_ACOUT20->DSP_1_ACIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT20" }, "DSP_R.DSP_0_ACOUT21->DSP_1_ACIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT21" }, "DSP_R.DSP_0_ACOUT22->DSP_1_ACIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT22" }, "DSP_R.DSP_0_ACOUT23->DSP_1_ACIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT23" }, "DSP_R.DSP_0_ACOUT24->DSP_1_ACIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT24" }, "DSP_R.DSP_0_ACOUT25->DSP_1_ACIN25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT25" }, "DSP_R.DSP_0_ACOUT26->DSP_1_ACIN26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT26" }, "DSP_R.DSP_0_ACOUT27->DSP_1_ACIN27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT27" }, "DSP_R.DSP_0_ACOUT28->DSP_1_ACIN28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT28" }, "DSP_R.DSP_0_ACOUT29->DSP_1_ACIN29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT29" }, "DSP_R.DSP_0_ACOUT3->DSP_1_ACIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT3" }, "DSP_R.DSP_0_ACOUT4->DSP_1_ACIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT4" }, "DSP_R.DSP_0_ACOUT5->DSP_1_ACIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT5" }, "DSP_R.DSP_0_ACOUT6->DSP_1_ACIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT6" }, "DSP_R.DSP_0_ACOUT7->DSP_1_ACIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT7" }, "DSP_R.DSP_0_ACOUT8->DSP_1_ACIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT8" }, "DSP_R.DSP_0_ACOUT9->DSP_1_ACIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT9" }, "DSP_R.DSP_0_BCOUT0->DSP_1_BCIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT0" }, "DSP_R.DSP_0_BCOUT1->DSP_1_BCIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT1" }, "DSP_R.DSP_0_BCOUT10->DSP_1_BCIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT10" }, "DSP_R.DSP_0_BCOUT11->DSP_1_BCIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT11" }, "DSP_R.DSP_0_BCOUT12->DSP_1_BCIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT12" }, "DSP_R.DSP_0_BCOUT13->DSP_1_BCIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT13" }, "DSP_R.DSP_0_BCOUT14->DSP_1_BCIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT14" }, "DSP_R.DSP_0_BCOUT15->DSP_1_BCIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT15" }, "DSP_R.DSP_0_BCOUT16->DSP_1_BCIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT16" }, "DSP_R.DSP_0_BCOUT17->DSP_1_BCIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT17" }, "DSP_R.DSP_0_BCOUT2->DSP_1_BCIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT2" }, "DSP_R.DSP_0_BCOUT3->DSP_1_BCIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT3" }, "DSP_R.DSP_0_BCOUT4->DSP_1_BCIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT4" }, "DSP_R.DSP_0_BCOUT5->DSP_1_BCIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT5" }, "DSP_R.DSP_0_BCOUT6->DSP_1_BCIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT6" }, "DSP_R.DSP_0_BCOUT7->DSP_1_BCIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT7" }, "DSP_R.DSP_0_BCOUT8->DSP_1_BCIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT8" }, "DSP_R.DSP_0_BCOUT9->DSP_1_BCIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT9" }, "DSP_R.DSP_0_CARRYCASCOUT->DSP_1_CARRYCASCIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYCASCIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYCASCOUT" }, "DSP_R.DSP_0_CARRYOUT0->DSP_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT0" }, "DSP_R.DSP_0_CARRYOUT1->DSP_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT1" }, "DSP_R.DSP_0_CARRYOUT2->DSP_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT2" }, "DSP_R.DSP_0_CARRYOUT3->DSP_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT3" }, "DSP_R.DSP_0_MULTSIGNOUT->DSP_1_MULTSIGNIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_MULTSIGNIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_MULTSIGNOUT" }, "DSP_R.DSP_0_OVERFLOW->DSP_LOGIC_OUTS_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_OVERFLOW" }, "DSP_R.DSP_0_P0->DSP_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P0" }, "DSP_R.DSP_0_P1->DSP_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P1" }, "DSP_R.DSP_0_P10->DSP_LOGIC_OUTS_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P10" }, "DSP_R.DSP_0_P11->DSP_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P11" }, "DSP_R.DSP_0_P12->DSP_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P12" }, "DSP_R.DSP_0_P13->DSP_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P13" }, "DSP_R.DSP_0_P14->DSP_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P14" }, "DSP_R.DSP_0_P15->DSP_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P15" }, "DSP_R.DSP_0_P16->DSP_LOGIC_OUTS_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P16" }, "DSP_R.DSP_0_P17->DSP_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P17" }, "DSP_R.DSP_0_P18->DSP_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P18" }, "DSP_R.DSP_0_P19->DSP_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P19" }, "DSP_R.DSP_0_P2->DSP_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P2" }, "DSP_R.DSP_0_P20->DSP_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P20" }, "DSP_R.DSP_0_P21->DSP_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P21" }, "DSP_R.DSP_0_P22->DSP_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P22" }, "DSP_R.DSP_0_P23->DSP_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P23" }, "DSP_R.DSP_0_P24->DSP_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P24" }, "DSP_R.DSP_0_P25->DSP_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P25" }, "DSP_R.DSP_0_P26->DSP_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P26" }, "DSP_R.DSP_0_P27->DSP_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P27" }, "DSP_R.DSP_0_P28->DSP_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P28" }, "DSP_R.DSP_0_P29->DSP_LOGIC_OUTS_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P29" }, "DSP_R.DSP_0_P3->DSP_LOGIC_OUTS_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P3" }, "DSP_R.DSP_0_P30->DSP_LOGIC_OUTS_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P30" }, "DSP_R.DSP_0_P31->DSP_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P31" }, "DSP_R.DSP_0_P32->DSP_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P32" }, "DSP_R.DSP_0_P33->DSP_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P33" }, "DSP_R.DSP_0_P34->DSP_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P34" }, "DSP_R.DSP_0_P35->DSP_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P35" }, "DSP_R.DSP_0_P36->DSP_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P36" }, "DSP_R.DSP_0_P37->DSP_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P37" }, "DSP_R.DSP_0_P38->DSP_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P38" }, "DSP_R.DSP_0_P39->DSP_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P39" }, "DSP_R.DSP_0_P4->DSP_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P4" }, "DSP_R.DSP_0_P40->DSP_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P40" }, "DSP_R.DSP_0_P41->DSP_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P41" }, "DSP_R.DSP_0_P42->DSP_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P42" }, "DSP_R.DSP_0_P43->DSP_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P43" }, "DSP_R.DSP_0_P44->DSP_LOGIC_OUTS_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P44" }, "DSP_R.DSP_0_P45->DSP_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P45" }, "DSP_R.DSP_0_P46->DSP_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P46" }, "DSP_R.DSP_0_P47->DSP_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P47" }, "DSP_R.DSP_0_P5->DSP_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P5" }, "DSP_R.DSP_0_P6->DSP_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P6" }, "DSP_R.DSP_0_P7->DSP_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P7" }, "DSP_R.DSP_0_P8->DSP_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P8" }, "DSP_R.DSP_0_P9->DSP_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P9" }, "DSP_R.DSP_0_PATTERNBDETECT->DSP_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PATTERNBDETECT" }, "DSP_R.DSP_0_PATTERNDETECT->DSP_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PATTERNDETECT" }, "DSP_R.DSP_0_PCOUT0->DSP_1_PCIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT0" }, "DSP_R.DSP_0_PCOUT1->DSP_1_PCIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT1" }, "DSP_R.DSP_0_PCOUT10->DSP_1_PCIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT10" }, "DSP_R.DSP_0_PCOUT11->DSP_1_PCIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT11" }, "DSP_R.DSP_0_PCOUT12->DSP_1_PCIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT12" }, "DSP_R.DSP_0_PCOUT13->DSP_1_PCIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT13" }, "DSP_R.DSP_0_PCOUT14->DSP_1_PCIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT14" }, "DSP_R.DSP_0_PCOUT15->DSP_1_PCIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT15" }, "DSP_R.DSP_0_PCOUT16->DSP_1_PCIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT16" }, "DSP_R.DSP_0_PCOUT17->DSP_1_PCIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT17" }, "DSP_R.DSP_0_PCOUT18->DSP_1_PCIN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT18" }, "DSP_R.DSP_0_PCOUT19->DSP_1_PCIN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT19" }, "DSP_R.DSP_0_PCOUT2->DSP_1_PCIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT2" }, "DSP_R.DSP_0_PCOUT20->DSP_1_PCIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT20" }, "DSP_R.DSP_0_PCOUT21->DSP_1_PCIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT21" }, "DSP_R.DSP_0_PCOUT22->DSP_1_PCIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT22" }, "DSP_R.DSP_0_PCOUT23->DSP_1_PCIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT23" }, "DSP_R.DSP_0_PCOUT24->DSP_1_PCIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT24" }, "DSP_R.DSP_0_PCOUT25->DSP_1_PCIN25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT25" }, "DSP_R.DSP_0_PCOUT26->DSP_1_PCIN26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT26" }, "DSP_R.DSP_0_PCOUT27->DSP_1_PCIN27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT27" }, "DSP_R.DSP_0_PCOUT28->DSP_1_PCIN28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT28" }, "DSP_R.DSP_0_PCOUT29->DSP_1_PCIN29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT29" }, "DSP_R.DSP_0_PCOUT3->DSP_1_PCIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT3" }, "DSP_R.DSP_0_PCOUT30->DSP_1_PCIN30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT30" }, "DSP_R.DSP_0_PCOUT31->DSP_1_PCIN31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT31" }, "DSP_R.DSP_0_PCOUT32->DSP_1_PCIN32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT32" }, "DSP_R.DSP_0_PCOUT33->DSP_1_PCIN33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT33" }, "DSP_R.DSP_0_PCOUT34->DSP_1_PCIN34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT34" }, "DSP_R.DSP_0_PCOUT35->DSP_1_PCIN35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT35" }, "DSP_R.DSP_0_PCOUT36->DSP_1_PCIN36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT36" }, "DSP_R.DSP_0_PCOUT37->DSP_1_PCIN37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT37" }, "DSP_R.DSP_0_PCOUT38->DSP_1_PCIN38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT38" }, "DSP_R.DSP_0_PCOUT39->DSP_1_PCIN39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT39" }, "DSP_R.DSP_0_PCOUT4->DSP_1_PCIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT4" }, "DSP_R.DSP_0_PCOUT40->DSP_1_PCIN40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT40" }, "DSP_R.DSP_0_PCOUT41->DSP_1_PCIN41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT41" }, "DSP_R.DSP_0_PCOUT42->DSP_1_PCIN42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT42" }, "DSP_R.DSP_0_PCOUT43->DSP_1_PCIN43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT43" }, "DSP_R.DSP_0_PCOUT44->DSP_1_PCIN44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT44" }, "DSP_R.DSP_0_PCOUT45->DSP_1_PCIN45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT45" }, "DSP_R.DSP_0_PCOUT46->DSP_1_PCIN46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT46" }, "DSP_R.DSP_0_PCOUT47->DSP_1_PCIN47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT47" }, "DSP_R.DSP_0_PCOUT5->DSP_1_PCIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT5" }, "DSP_R.DSP_0_PCOUT6->DSP_1_PCIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT6" }, "DSP_R.DSP_0_PCOUT7->DSP_1_PCIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT7" }, "DSP_R.DSP_0_PCOUT8->DSP_1_PCIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT8" }, "DSP_R.DSP_0_PCOUT9->DSP_1_PCIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT9" }, "DSP_R.DSP_0_UNDERFLOW->DSP_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_UNDERFLOW" }, "DSP_R.DSP_1_ACOUT0->DSP_ACOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT0" }, "DSP_R.DSP_1_ACOUT1->DSP_ACOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT1" }, "DSP_R.DSP_1_ACOUT10->DSP_ACOUT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT10" }, "DSP_R.DSP_1_ACOUT11->DSP_ACOUT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT11" }, "DSP_R.DSP_1_ACOUT12->DSP_ACOUT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT12" }, "DSP_R.DSP_1_ACOUT13->DSP_ACOUT13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT13" }, "DSP_R.DSP_1_ACOUT14->DSP_ACOUT14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT14" }, "DSP_R.DSP_1_ACOUT15->DSP_ACOUT15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT15" }, "DSP_R.DSP_1_ACOUT16->DSP_ACOUT16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT16" }, "DSP_R.DSP_1_ACOUT17->DSP_ACOUT17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT17" }, "DSP_R.DSP_1_ACOUT18->DSP_ACOUT18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT18" }, "DSP_R.DSP_1_ACOUT19->DSP_ACOUT19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT19" }, "DSP_R.DSP_1_ACOUT2->DSP_ACOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT2" }, "DSP_R.DSP_1_ACOUT20->DSP_ACOUT20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT20" }, "DSP_R.DSP_1_ACOUT21->DSP_ACOUT21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT21" }, "DSP_R.DSP_1_ACOUT22->DSP_ACOUT22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT22" }, "DSP_R.DSP_1_ACOUT23->DSP_ACOUT23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT23" }, "DSP_R.DSP_1_ACOUT24->DSP_ACOUT24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT24" }, "DSP_R.DSP_1_ACOUT25->DSP_ACOUT25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT25" }, "DSP_R.DSP_1_ACOUT26->DSP_ACOUT26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT26" }, "DSP_R.DSP_1_ACOUT27->DSP_ACOUT27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT27" }, "DSP_R.DSP_1_ACOUT28->DSP_ACOUT28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT28" }, "DSP_R.DSP_1_ACOUT29->DSP_ACOUT29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT29" }, "DSP_R.DSP_1_ACOUT3->DSP_ACOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT3" }, "DSP_R.DSP_1_ACOUT4->DSP_ACOUT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT4" }, "DSP_R.DSP_1_ACOUT5->DSP_ACOUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT5" }, "DSP_R.DSP_1_ACOUT6->DSP_ACOUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT6" }, "DSP_R.DSP_1_ACOUT7->DSP_ACOUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT7" }, "DSP_R.DSP_1_ACOUT8->DSP_ACOUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT8" }, "DSP_R.DSP_1_ACOUT9->DSP_ACOUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT9" }, "DSP_R.DSP_1_BCOUT0->DSP_BCOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT0" }, "DSP_R.DSP_1_BCOUT1->DSP_BCOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT1" }, "DSP_R.DSP_1_BCOUT10->DSP_BCOUT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT10" }, "DSP_R.DSP_1_BCOUT11->DSP_BCOUT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT11" }, "DSP_R.DSP_1_BCOUT12->DSP_BCOUT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT12" }, "DSP_R.DSP_1_BCOUT13->DSP_BCOUT13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT13" }, "DSP_R.DSP_1_BCOUT14->DSP_BCOUT14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT14" }, "DSP_R.DSP_1_BCOUT15->DSP_BCOUT15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT15" }, "DSP_R.DSP_1_BCOUT16->DSP_BCOUT16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT16" }, "DSP_R.DSP_1_BCOUT17->DSP_BCOUT17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT17" }, "DSP_R.DSP_1_BCOUT2->DSP_BCOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT2" }, "DSP_R.DSP_1_BCOUT3->DSP_BCOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT3" }, "DSP_R.DSP_1_BCOUT4->DSP_BCOUT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT4" }, "DSP_R.DSP_1_BCOUT5->DSP_BCOUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT5" }, "DSP_R.DSP_1_BCOUT6->DSP_BCOUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT6" }, "DSP_R.DSP_1_BCOUT7->DSP_BCOUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT7" }, "DSP_R.DSP_1_BCOUT8->DSP_BCOUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT8" }, "DSP_R.DSP_1_BCOUT9->DSP_BCOUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT9" }, "DSP_R.DSP_1_CARRYCASCOUT->DSP_CARRYCASCOUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_CARRYCASCOUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYCASCOUT" }, "DSP_R.DSP_1_CARRYOUT0->DSP_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT0" }, "DSP_R.DSP_1_CARRYOUT1->DSP_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT1" }, "DSP_R.DSP_1_CARRYOUT2->DSP_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT2" }, "DSP_R.DSP_1_CARRYOUT3->DSP_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT3" }, "DSP_R.DSP_1_MULTSIGNOUT->DSP_MULTSIGNOUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_MULTSIGNOUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_MULTSIGNOUT" }, "DSP_R.DSP_1_OVERFLOW->DSP_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_OVERFLOW" }, "DSP_R.DSP_1_P0->DSP_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P0" }, "DSP_R.DSP_1_P1->DSP_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P1" }, "DSP_R.DSP_1_P10->DSP_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P10" }, "DSP_R.DSP_1_P11->DSP_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P11" }, "DSP_R.DSP_1_P12->DSP_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P12" }, "DSP_R.DSP_1_P13->DSP_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P13" }, "DSP_R.DSP_1_P14->DSP_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P14" }, "DSP_R.DSP_1_P15->DSP_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P15" }, "DSP_R.DSP_1_P16->DSP_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P16" }, "DSP_R.DSP_1_P17->DSP_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P17" }, "DSP_R.DSP_1_P18->DSP_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P18" }, "DSP_R.DSP_1_P19->DSP_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P19" }, "DSP_R.DSP_1_P2->DSP_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P2" }, "DSP_R.DSP_1_P20->DSP_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P20" }, "DSP_R.DSP_1_P21->DSP_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P21" }, "DSP_R.DSP_1_P22->DSP_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P22" }, "DSP_R.DSP_1_P23->DSP_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P23" }, "DSP_R.DSP_1_P24->DSP_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P24" }, "DSP_R.DSP_1_P25->DSP_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P25" }, "DSP_R.DSP_1_P26->DSP_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P26" }, "DSP_R.DSP_1_P27->DSP_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P27" }, "DSP_R.DSP_1_P28->DSP_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P28" }, "DSP_R.DSP_1_P29->DSP_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P29" }, "DSP_R.DSP_1_P3->DSP_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P3" }, "DSP_R.DSP_1_P30->DSP_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P30" }, "DSP_R.DSP_1_P31->DSP_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P31" }, "DSP_R.DSP_1_P32->DSP_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P32" }, "DSP_R.DSP_1_P33->DSP_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P33" }, "DSP_R.DSP_1_P34->DSP_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P34" }, "DSP_R.DSP_1_P35->DSP_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P35" }, "DSP_R.DSP_1_P36->DSP_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P36" }, "DSP_R.DSP_1_P37->DSP_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P37" }, "DSP_R.DSP_1_P38->DSP_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P38" }, "DSP_R.DSP_1_P39->DSP_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P39" }, "DSP_R.DSP_1_P4->DSP_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P4" }, "DSP_R.DSP_1_P40->DSP_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P40" }, "DSP_R.DSP_1_P41->DSP_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P41" }, "DSP_R.DSP_1_P42->DSP_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P42" }, "DSP_R.DSP_1_P43->DSP_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P43" }, "DSP_R.DSP_1_P44->DSP_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P44" }, "DSP_R.DSP_1_P45->DSP_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P45" }, "DSP_R.DSP_1_P46->DSP_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P46" }, "DSP_R.DSP_1_P47->DSP_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P47" }, "DSP_R.DSP_1_P5->DSP_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P5" }, "DSP_R.DSP_1_P6->DSP_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P6" }, "DSP_R.DSP_1_P7->DSP_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P7" }, "DSP_R.DSP_1_P8->DSP_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P8" }, "DSP_R.DSP_1_P9->DSP_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P9" }, "DSP_R.DSP_1_PATTERNBDETECT->DSP_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PATTERNBDETECT" }, "DSP_R.DSP_1_PATTERNDETECT->DSP_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PATTERNDETECT" }, "DSP_R.DSP_1_PCOUT0->DSP_PCOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT0" }, "DSP_R.DSP_1_PCOUT1->DSP_PCOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT1" }, "DSP_R.DSP_1_PCOUT10->DSP_PCOUT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT10" }, "DSP_R.DSP_1_PCOUT11->DSP_PCOUT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT11" }, "DSP_R.DSP_1_PCOUT12->DSP_PCOUT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT12" }, "DSP_R.DSP_1_PCOUT13->DSP_PCOUT13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT13" }, "DSP_R.DSP_1_PCOUT14->DSP_PCOUT14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT14" }, "DSP_R.DSP_1_PCOUT15->DSP_PCOUT15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT15" }, "DSP_R.DSP_1_PCOUT16->DSP_PCOUT16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT16" }, "DSP_R.DSP_1_PCOUT17->DSP_PCOUT17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT17" }, "DSP_R.DSP_1_PCOUT18->DSP_PCOUT18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT18" }, "DSP_R.DSP_1_PCOUT19->DSP_PCOUT19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT19" }, "DSP_R.DSP_1_PCOUT2->DSP_PCOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT2" }, "DSP_R.DSP_1_PCOUT20->DSP_PCOUT20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT20" }, "DSP_R.DSP_1_PCOUT21->DSP_PCOUT21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT21" }, "DSP_R.DSP_1_PCOUT22->DSP_PCOUT22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT22" }, "DSP_R.DSP_1_PCOUT23->DSP_PCOUT23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT23" }, "DSP_R.DSP_1_PCOUT24->DSP_PCOUT24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT24" }, "DSP_R.DSP_1_PCOUT25->DSP_PCOUT25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT25" }, "DSP_R.DSP_1_PCOUT26->DSP_PCOUT26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT26" }, "DSP_R.DSP_1_PCOUT27->DSP_PCOUT27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT27" }, "DSP_R.DSP_1_PCOUT28->DSP_PCOUT28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT28" }, "DSP_R.DSP_1_PCOUT29->DSP_PCOUT29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT29" }, "DSP_R.DSP_1_PCOUT3->DSP_PCOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT3" }, "DSP_R.DSP_1_PCOUT30->DSP_PCOUT30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT30" }, "DSP_R.DSP_1_PCOUT31->DSP_PCOUT31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT31" }, "DSP_R.DSP_1_PCOUT32->DSP_PCOUT32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT32" }, "DSP_R.DSP_1_PCOUT33->DSP_PCOUT33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT33" }, "DSP_R.DSP_1_PCOUT34->DSP_PCOUT34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT34" }, "DSP_R.DSP_1_PCOUT35->DSP_PCOUT35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT35" }, "DSP_R.DSP_1_PCOUT36->DSP_PCOUT36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT36" }, "DSP_R.DSP_1_PCOUT37->DSP_PCOUT37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT37" }, "DSP_R.DSP_1_PCOUT38->DSP_PCOUT38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT38" }, "DSP_R.DSP_1_PCOUT39->DSP_PCOUT39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT39" }, "DSP_R.DSP_1_PCOUT4->DSP_PCOUT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT4" }, "DSP_R.DSP_1_PCOUT40->DSP_PCOUT40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT40" }, "DSP_R.DSP_1_PCOUT41->DSP_PCOUT41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT41" }, "DSP_R.DSP_1_PCOUT42->DSP_PCOUT42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT42" }, "DSP_R.DSP_1_PCOUT43->DSP_PCOUT43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT43" }, "DSP_R.DSP_1_PCOUT44->DSP_PCOUT44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT44" }, "DSP_R.DSP_1_PCOUT45->DSP_PCOUT45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT45" }, "DSP_R.DSP_1_PCOUT46->DSP_PCOUT46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT46" }, "DSP_R.DSP_1_PCOUT47->DSP_PCOUT47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT47" }, "DSP_R.DSP_1_PCOUT5->DSP_PCOUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT5" }, "DSP_R.DSP_1_PCOUT6->DSP_PCOUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT6" }, "DSP_R.DSP_1_PCOUT7->DSP_PCOUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT7" }, "DSP_R.DSP_1_PCOUT8->DSP_PCOUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT8" }, "DSP_R.DSP_1_PCOUT9->DSP_PCOUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT9" }, "DSP_R.DSP_1_UNDERFLOW->DSP_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_UNDERFLOW" }, "DSP_R.DSP_BYP0_0->DSP_0_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_0" }, "DSP_R.DSP_BYP0_1->DSP_0_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_1" }, "DSP_R.DSP_BYP0_2->DSP_0_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_2" }, "DSP_R.DSP_BYP0_3->DSP_1_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_3" }, "DSP_R.DSP_BYP0_4->DSP_1_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_4" }, "DSP_R.DSP_BYP1_0->DSP_0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_0" }, "DSP_R.DSP_BYP1_1->DSP_0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_1" }, "DSP_R.DSP_BYP1_2->DSP_0_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_2" }, "DSP_R.DSP_BYP1_3->DSP_0_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_3" }, "DSP_R.DSP_BYP1_4->DSP_0_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_4" }, "DSP_R.DSP_BYP2_0->DSP_0_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_0" }, "DSP_R.DSP_BYP2_1->DSP_1_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_1" }, "DSP_R.DSP_BYP2_2->DSP_0_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_2" }, "DSP_R.DSP_BYP2_3->DSP_0_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_3" }, "DSP_R.DSP_BYP2_4->DSP_1_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_4" }, "DSP_R.DSP_BYP3_0->DSP_0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_0" }, "DSP_R.DSP_BYP3_1->DSP_0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_1" }, "DSP_R.DSP_BYP3_2->DSP_0_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_2" }, "DSP_R.DSP_BYP3_3->DSP_0_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_3" }, "DSP_R.DSP_BYP3_4->DSP_0_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_4" }, "DSP_R.DSP_BYP4_0->DSP_0_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_0" }, "DSP_R.DSP_BYP4_1->DSP_0_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_1" }, "DSP_R.DSP_BYP4_2->DSP_1_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_2" }, "DSP_R.DSP_BYP4_3->DSP_1_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_3" }, "DSP_R.DSP_BYP4_4->DSP_1_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_4" }, "DSP_R.DSP_BYP5_0->DSP_0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_0" }, "DSP_R.DSP_BYP5_1->DSP_0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_1" }, "DSP_R.DSP_BYP5_2->DSP_0_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_2" }, "DSP_R.DSP_BYP5_3->DSP_0_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_3" }, "DSP_R.DSP_BYP5_4->DSP_0_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_4" }, "DSP_R.DSP_BYP6_0->DSP_0_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_0" }, "DSP_R.DSP_BYP6_1->DSP_0_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_1" }, "DSP_R.DSP_BYP6_2->DSP_0_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_2" }, "DSP_R.DSP_BYP6_3->DSP_0_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_3" }, "DSP_R.DSP_BYP6_4->DSP_1_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_4" }, "DSP_R.DSP_BYP7_0->DSP_0_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_0" }, "DSP_R.DSP_BYP7_1->DSP_0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_1" }, "DSP_R.DSP_BYP7_2->DSP_0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_2" }, "DSP_R.DSP_BYP7_3->DSP_0_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_3" }, "DSP_R.DSP_BYP7_4->DSP_0_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_4" }, "DSP_R.DSP_CLK0_1->DSP_0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CLK0_1" }, "DSP_R.DSP_CLK0_3->DSP_1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CLK0_3" }, "DSP_R.DSP_CTRL0_0->DSP_0_RSTP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_0" }, "DSP_R.DSP_CTRL0_1->DSP_0_RSTC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_1" }, "DSP_R.DSP_CTRL0_2->DSP_0_RSTB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_2" }, "DSP_R.DSP_CTRL0_3->DSP_1_RSTC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_3" }, "DSP_R.DSP_CTRL0_4->DSP_1_RSTP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_4" }, "DSP_R.DSP_CTRL1_0->DSP_0_RSTA": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTA", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_0" }, "DSP_R.DSP_CTRL1_1->DSP_0_RSTM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_1" }, "DSP_R.DSP_CTRL1_2->DSP_1_RSTA": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTA", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_2" }, "DSP_R.DSP_CTRL1_3->DSP_1_RSTM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_3" }, "DSP_R.DSP_CTRL1_4->DSP_1_RSTB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_4" }, "DSP_R.DSP_FAN0_0->DSP_0_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_0" }, "DSP_R.DSP_FAN0_1->DSP_0_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_1" }, "DSP_R.DSP_FAN0_2->DSP_1_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_2" }, "DSP_R.DSP_FAN0_3->DSP_1_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_3" }, "DSP_R.DSP_FAN0_4->DSP_1_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_4" }, "DSP_R.DSP_FAN1_0->DSP_1_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_0" }, "DSP_R.DSP_FAN1_1->DSP_1_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_1" }, "DSP_R.DSP_FAN1_2->DSP_0_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_2" }, "DSP_R.DSP_FAN1_3->DSP_0_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_3" }, "DSP_R.DSP_FAN2_0->DSP_0_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_0" }, "DSP_R.DSP_FAN2_2->DSP_1_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_2" }, "DSP_R.DSP_FAN2_3->DSP_1_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_3" }, "DSP_R.DSP_FAN2_4->DSP_1_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_4" }, "DSP_R.DSP_FAN3_0->DSP_1_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_0" }, "DSP_R.DSP_FAN3_1->DSP_1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_1" }, "DSP_R.DSP_FAN3_2->DSP_1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_2" }, "DSP_R.DSP_FAN3_3->DSP_1_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_3" }, "DSP_R.DSP_FAN3_4->DSP_1_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_4" }, "DSP_R.DSP_FAN4_0->DSP_1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_0" }, "DSP_R.DSP_FAN4_1->DSP_1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_1" }, "DSP_R.DSP_FAN4_2->DSP_1_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_2" }, "DSP_R.DSP_FAN4_3->DSP_1_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_3" }, "DSP_R.DSP_FAN4_4->DSP_1_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_4" }, "DSP_R.DSP_FAN5_0->DSP_1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_0" }, "DSP_R.DSP_FAN5_1->DSP_1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_1" }, "DSP_R.DSP_FAN5_2->DSP_1_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_2" }, "DSP_R.DSP_FAN5_3->DSP_1_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_3" }, "DSP_R.DSP_FAN5_4->DSP_1_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_4" }, "DSP_R.DSP_FAN6_0->DSP_1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_0" }, "DSP_R.DSP_FAN6_1->DSP_1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_1" }, "DSP_R.DSP_FAN6_2->DSP_1_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_2" }, "DSP_R.DSP_FAN6_3->DSP_1_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_3" }, "DSP_R.DSP_FAN6_4->DSP_1_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_4" }, "DSP_R.DSP_FAN7_0->DSP_1_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_0" }, "DSP_R.DSP_FAN7_1->DSP_0_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_1" }, "DSP_R.DSP_FAN7_2->DSP_0_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_2" }, "DSP_R.DSP_FAN7_3->DSP_1_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_3" }, "DSP_R.DSP_FAN7_4->DSP_1_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_4" }, "DSP_R.DSP_GND_R->DSP_0_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_IMUX0_0->DSP_1_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_0" }, "DSP_R.DSP_IMUX0_1->DSP_0_CEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_1" }, "DSP_R.DSP_IMUX0_2->DSP_0_CECARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CECARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_2" }, "DSP_R.DSP_IMUX0_3->DSP_1_B15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_3" }, "DSP_R.DSP_IMUX0_4->DSP_1_ALUMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_4" }, "DSP_R.DSP_IMUX10_0->DSP_1_C21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_0" }, "DSP_R.DSP_IMUX10_1->DSP_1_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_1" }, "DSP_R.DSP_IMUX10_2->DSP_1_C29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_2" }, "DSP_R.DSP_IMUX10_3->DSP_1_C33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_3" }, "DSP_R.DSP_IMUX10_4->DSP_1_C39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_4" }, "DSP_R.DSP_IMUX11_0->DSP_1_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_0" }, "DSP_R.DSP_IMUX11_1->DSP_1_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_1" }, "DSP_R.DSP_IMUX11_2->DSP_1_A9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_2" }, "DSP_R.DSP_IMUX11_3->DSP_1_CECTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CECTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_3" }, "DSP_R.DSP_IMUX11_4->DSP_1_C46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_4" }, "DSP_R.DSP_IMUX12_0->DSP_1_C22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_0" }, "DSP_R.DSP_IMUX12_1->DSP_1_C26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_1" }, "DSP_R.DSP_IMUX12_2->DSP_0_OPMODE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_2" }, "DSP_R.DSP_IMUX12_3->DSP_1_C34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_3" }, "DSP_R.DSP_IMUX12_4->DSP_1_C38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_4" }, "DSP_R.DSP_IMUX13_0->DSP_1_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_0" }, "DSP_R.DSP_IMUX13_1->DSP_1_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_1" }, "DSP_R.DSP_IMUX13_2->DSP_1_A10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_2" }, "DSP_R.DSP_IMUX13_3->DSP_0_ALUMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_3" }, "DSP_R.DSP_IMUX13_4->DSP_1_C18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_4" }, "DSP_R.DSP_IMUX14_0->DSP_1_B0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_0" }, "DSP_R.DSP_IMUX14_1->DSP_1_C24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_1" }, "DSP_R.DSP_IMUX14_2->DSP_1_B8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_2" }, "DSP_R.DSP_IMUX14_3->DSP_0_CARRYINSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_3" }, "DSP_R.DSP_IMUX14_4->DSP_1_RSTCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_4" }, "DSP_R.DSP_IMUX15_0->DSP_1_A0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_0" }, "DSP_R.DSP_IMUX15_1->DSP_1_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_1" }, "DSP_R.DSP_IMUX15_2->DSP_1_A8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_2" }, "DSP_R.DSP_IMUX15_3->DSP_1_CARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_3" }, "DSP_R.DSP_IMUX15_4->DSP_1_RSTALLCARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTALLCARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_4" }, "DSP_R.DSP_IMUX16_0->DSP_0_C41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_0" }, "DSP_R.DSP_IMUX16_1->DSP_0_B7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_1" }, "DSP_R.DSP_IMUX16_2->DSP_0_B11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_2" }, "DSP_R.DSP_IMUX16_3->DSP_1_CEB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_3" }, "DSP_R.DSP_IMUX16_4->DSP_1_OPMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_4" }, "DSP_R.DSP_IMUX17_0->DSP_0_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_0" }, "DSP_R.DSP_IMUX17_1->DSP_0_A7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_1" }, "DSP_R.DSP_IMUX17_2->DSP_0_A11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_2" }, "DSP_R.DSP_IMUX17_3->DSP_1_CEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_3" }, "DSP_R.DSP_IMUX17_4->DSP_1_OPMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_4" }, "DSP_R.DSP_IMUX18_0->DSP_0_C21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_0" }, "DSP_R.DSP_IMUX18_1->DSP_0_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_1" }, "DSP_R.DSP_IMUX18_2->DSP_0_B9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_2" }, "DSP_R.DSP_IMUX18_3->DSP_0_C33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_3" }, "DSP_R.DSP_IMUX18_4->DSP_0_C39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_4" }, "DSP_R.DSP_IMUX19_0->DSP_0_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_0" }, "DSP_R.DSP_IMUX19_1->DSP_0_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_1" }, "DSP_R.DSP_IMUX19_2->DSP_0_A9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_2" }, "DSP_R.DSP_IMUX19_3->DSP_1_CEM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_3" }, "DSP_R.DSP_IMUX19_4->DSP_0_C46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_4" }, "DSP_R.DSP_IMUX1_0->DSP_0_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_0" }, "DSP_R.DSP_IMUX1_1->DSP_0_CEB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_1" }, "DSP_R.DSP_IMUX1_2->DSP_0_CEM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_2" }, "DSP_R.DSP_IMUX1_3->DSP_1_B13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_3" }, "DSP_R.DSP_IMUX1_4->DSP_0_C19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_4" }, "DSP_R.DSP_IMUX20_0->DSP_0_C22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_0" }, "DSP_R.DSP_IMUX20_1->DSP_0_C26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_1" }, "DSP_R.DSP_IMUX20_2->DSP_0_OPMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_2" }, "DSP_R.DSP_IMUX20_3->DSP_0_C34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_3" }, "DSP_R.DSP_IMUX20_4->DSP_0_C38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_4" }, "DSP_R.DSP_IMUX21_0->DSP_0_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_0" }, "DSP_R.DSP_IMUX21_1->DSP_0_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_1" }, "DSP_R.DSP_IMUX21_2->DSP_0_A10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_2" }, "DSP_R.DSP_IMUX21_3->DSP_0_ALUMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_3" }, "DSP_R.DSP_IMUX21_4->DSP_0_C18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_4" }, "DSP_R.DSP_IMUX22_0->DSP_0_B0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_0" }, "DSP_R.DSP_IMUX22_1->DSP_0_C24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_1" }, "DSP_R.DSP_IMUX22_2->DSP_0_B8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_2" }, "DSP_R.DSP_IMUX22_3->DSP_1_C32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_3" }, "DSP_R.DSP_IMUX22_4->DSP_1_RSTALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_4" }, "DSP_R.DSP_IMUX23_0->DSP_0_A0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_0" }, "DSP_R.DSP_IMUX23_1->DSP_0_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_1" }, "DSP_R.DSP_IMUX23_2->DSP_0_A8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_2" }, "DSP_R.DSP_IMUX23_3->DSP_0_CARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_3" }, "DSP_R.DSP_IMUX23_4->DSP_1_RSTINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_4" }, "DSP_R.DSP_IMUX24_0->DSP_1_C23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_0" }, "DSP_R.DSP_IMUX24_1->DSP_1_C27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_1" }, "DSP_R.DSP_IMUX24_2->DSP_1_C31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_2" }, "DSP_R.DSP_IMUX24_3->DSP_1_C35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_3" }, "DSP_R.DSP_IMUX24_4->DSP_1_C37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_4" }, "DSP_R.DSP_IMUX25_0->DSP_1_C43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_0" }, "DSP_R.DSP_IMUX25_1->DSP_1_C7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_1" }, "DSP_R.DSP_IMUX25_2->DSP_1_C11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_2" }, "DSP_R.DSP_IMUX25_3->DSP_1_C15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_3" }, "DSP_R.DSP_IMUX25_4->DSP_1_C47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_4" }, "DSP_R.DSP_IMUX26_0->DSP_1_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_0" }, "DSP_R.DSP_IMUX26_1->DSP_1_C25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_1" }, "DSP_R.DSP_IMUX26_2->DSP_1_CEP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_2" }, "DSP_R.DSP_IMUX26_3->DSP_1_CECARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CECARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_3" }, "DSP_R.DSP_IMUX26_4->DSP_1_C44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_4" }, "DSP_R.DSP_IMUX27_0->DSP_1_C40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_0" }, "DSP_R.DSP_IMUX27_1->DSP_1_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_1" }, "DSP_R.DSP_IMUX27_2->DSP_0_OPMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_2" }, "DSP_R.DSP_IMUX27_3->DSP_1_C13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_3" }, "DSP_R.DSP_IMUX27_4->DSP_1_C17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_4" }, "DSP_R.DSP_IMUX28_0->DSP_1_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_0" }, "DSP_R.DSP_IMUX28_1->DSP_1_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_1" }, "DSP_R.DSP_IMUX28_2->DSP_1_C30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_2" }, "DSP_R.DSP_IMUX28_3->DSP_1_OPMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_3" }, "DSP_R.DSP_IMUX28_4->DSP_1_CARRYINSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_4" }, "DSP_R.DSP_IMUX29_0->DSP_1_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_0" }, "DSP_R.DSP_IMUX29_1->DSP_1_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_1" }, "DSP_R.DSP_IMUX29_2->DSP_1_C10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_2" }, "DSP_R.DSP_IMUX29_3->DSP_1_C14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_3" }, "DSP_R.DSP_IMUX29_4->DSP_1_C45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_4" }, "DSP_R.DSP_IMUX2_0->DSP_1_C42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_0" }, "DSP_R.DSP_IMUX2_1->DSP_0_RSTALLCARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTALLCARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_1" }, "DSP_R.DSP_IMUX2_2->DSP_0_C29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_2" }, "DSP_R.DSP_IMUX2_3->DSP_0_B15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_3" }, "DSP_R.DSP_IMUX2_4->DSP_1_B17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_4" }, "DSP_R.DSP_IMUX30_0->DSP_1_C20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_0" }, "DSP_R.DSP_IMUX30_1->DSP_1_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_1" }, "DSP_R.DSP_IMUX30_2->DSP_0_OPMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_2" }, "DSP_R.DSP_IMUX30_3->DSP_0_CARRYINSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_3" }, "DSP_R.DSP_IMUX30_4->DSP_1_C36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_4" }, "DSP_R.DSP_IMUX31_0->DSP_1_C0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_0" }, "DSP_R.DSP_IMUX31_1->DSP_1_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_1" }, "DSP_R.DSP_IMUX31_2->DSP_1_C8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_2" }, "DSP_R.DSP_IMUX31_3->DSP_1_C12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_3" }, "DSP_R.DSP_IMUX31_4->DSP_1_C16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_4" }, "DSP_R.DSP_IMUX32_0->DSP_0_C23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_0" }, "DSP_R.DSP_IMUX32_1->DSP_0_C27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_1" }, "DSP_R.DSP_IMUX32_2->DSP_0_C31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_2" }, "DSP_R.DSP_IMUX32_3->DSP_0_C35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_3" }, "DSP_R.DSP_IMUX32_4->DSP_0_C37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_4" }, "DSP_R.DSP_IMUX33_0->DSP_0_C43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_0" }, "DSP_R.DSP_IMUX33_1->DSP_0_C7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_1" }, "DSP_R.DSP_IMUX33_2->DSP_0_C11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_2" }, "DSP_R.DSP_IMUX33_3->DSP_0_C15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_3" }, "DSP_R.DSP_IMUX33_4->DSP_0_C47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_4" }, "DSP_R.DSP_IMUX34_0->DSP_0_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_0" }, "DSP_R.DSP_IMUX34_1->DSP_0_C25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_1" }, "DSP_R.DSP_IMUX34_2->DSP_0_CEP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_2" }, "DSP_R.DSP_IMUX34_3->DSP_1_CEC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_3" }, "DSP_R.DSP_IMUX34_4->DSP_0_C44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_4" }, "DSP_R.DSP_IMUX35_0->DSP_0_C40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_0" }, "DSP_R.DSP_IMUX35_1->DSP_0_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_1" }, "DSP_R.DSP_IMUX35_2->DSP_0_OPMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_2" }, "DSP_R.DSP_IMUX35_3->DSP_0_C13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_3" }, "DSP_R.DSP_IMUX35_4->DSP_0_C17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_4" }, "DSP_R.DSP_IMUX36_0->DSP_0_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_0" }, "DSP_R.DSP_IMUX36_1->DSP_0_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_1" }, "DSP_R.DSP_IMUX36_2->DSP_0_B10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_2" }, "DSP_R.DSP_IMUX36_3->DSP_1_OPMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_3" }, "DSP_R.DSP_IMUX36_4->DSP_1_CARRYINSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_4" }, "DSP_R.DSP_IMUX37_0->DSP_0_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_0" }, "DSP_R.DSP_IMUX37_1->DSP_0_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_1" }, "DSP_R.DSP_IMUX37_2->DSP_0_C10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_2" }, "DSP_R.DSP_IMUX37_3->DSP_0_C14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_3" }, "DSP_R.DSP_IMUX37_4->DSP_0_C45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_4" }, "DSP_R.DSP_IMUX38_0->DSP_0_C20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_0" }, "DSP_R.DSP_IMUX38_1->DSP_0_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_1" }, "DSP_R.DSP_IMUX38_2->DSP_0_OPMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_2" }, "DSP_R.DSP_IMUX38_3->DSP_0_C32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_3" }, "DSP_R.DSP_IMUX38_4->DSP_0_C36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_4" }, "DSP_R.DSP_IMUX39_0->DSP_0_C0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_0" }, "DSP_R.DSP_IMUX39_1->DSP_0_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_1" }, "DSP_R.DSP_IMUX39_2->DSP_0_C8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_2" }, "DSP_R.DSP_IMUX39_3->DSP_0_C12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_3" }, "DSP_R.DSP_IMUX39_4->DSP_0_C16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_4" }, "DSP_R.DSP_IMUX3_0->DSP_0_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_0" }, "DSP_R.DSP_IMUX3_1->DSP_0_RSTALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_1" }, "DSP_R.DSP_IMUX3_2->DSP_0_C9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_2" }, "DSP_R.DSP_IMUX3_3->DSP_0_B13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_3" }, "DSP_R.DSP_IMUX3_4->DSP_0_B17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_4" }, "DSP_R.DSP_IMUX40_0->DSP_0_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_0" }, "DSP_R.DSP_IMUX40_1->DSP_0_CEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_1" }, "DSP_R.DSP_IMUX40_2->DSP_0_CEC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_2" }, "DSP_R.DSP_IMUX40_3->DSP_1_B14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_3" }, "DSP_R.DSP_IMUX40_4->DSP_1_ALUMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_4" }, "DSP_R.DSP_IMUX41_0->DSP_1_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_0" }, "DSP_R.DSP_IMUX41_1->DSP_0_CEB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_1" }, "DSP_R.DSP_IMUX41_2->DSP_0_CECTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CECTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_2" }, "DSP_R.DSP_IMUX41_3->DSP_1_B12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_3" }, "DSP_R.DSP_IMUX41_4->DSP_1_C19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_4" }, "DSP_R.DSP_IMUX42_0->DSP_0_C42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_0" }, "DSP_R.DSP_IMUX42_1->DSP_0_RSTINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_1" }, "DSP_R.DSP_IMUX42_2->DSP_1_B9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_2" }, "DSP_R.DSP_IMUX42_3->DSP_0_B14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_3" }, "DSP_R.DSP_IMUX42_4->DSP_1_B16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_4" }, "DSP_R.DSP_IMUX43_0->DSP_1_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_0" }, "DSP_R.DSP_IMUX43_1->DSP_0_RSTCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_1" }, "DSP_R.DSP_IMUX43_2->DSP_1_C9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_2" }, "DSP_R.DSP_IMUX43_3->DSP_0_B12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_3" }, "DSP_R.DSP_IMUX43_4->DSP_0_B16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_4" }, "DSP_R.DSP_IMUX44_0->DSP_1_A22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_0" }, "DSP_R.DSP_IMUX44_1->DSP_1_A26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_1" }, "DSP_R.DSP_IMUX44_2->DSP_1_B10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_2" }, "DSP_R.DSP_IMUX44_3->DSP_1_A14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_3" }, "DSP_R.DSP_IMUX44_4->DSP_1_A18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_4" }, "DSP_R.DSP_IMUX45_0->DSP_1_A20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_0" }, "DSP_R.DSP_IMUX45_1->DSP_1_A24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_1" }, "DSP_R.DSP_IMUX45_2->DSP_1_A28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_2" }, "DSP_R.DSP_IMUX45_3->DSP_1_A12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_3" }, "DSP_R.DSP_IMUX45_4->DSP_1_A16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_4" }, "DSP_R.DSP_IMUX46_0->DSP_0_A22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_0" }, "DSP_R.DSP_IMUX46_1->DSP_0_A26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_1" }, "DSP_R.DSP_IMUX46_2->DSP_1_C28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_2" }, "DSP_R.DSP_IMUX46_3->DSP_0_A14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_3" }, "DSP_R.DSP_IMUX46_4->DSP_0_A18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_4" }, "DSP_R.DSP_IMUX47_0->DSP_0_A20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_0" }, "DSP_R.DSP_IMUX47_1->DSP_0_A24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_1" }, "DSP_R.DSP_IMUX47_2->DSP_0_A28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_2" }, "DSP_R.DSP_IMUX47_3->DSP_0_A12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_3" }, "DSP_R.DSP_IMUX47_4->DSP_0_A16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_4" }, "DSP_R.DSP_IMUX4_0->DSP_1_A23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_0" }, "DSP_R.DSP_IMUX4_1->DSP_1_A27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_1" }, "DSP_R.DSP_IMUX4_2->DSP_0_C30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_2" }, "DSP_R.DSP_IMUX4_3->DSP_1_A15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_3" }, "DSP_R.DSP_IMUX4_4->DSP_1_A19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_4" }, "DSP_R.DSP_IMUX5_0->DSP_1_A21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_0" }, "DSP_R.DSP_IMUX5_1->DSP_1_A25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_1" }, "DSP_R.DSP_IMUX5_2->DSP_1_A29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_2" }, "DSP_R.DSP_IMUX5_3->DSP_1_A13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_3" }, "DSP_R.DSP_IMUX5_4->DSP_1_A17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_4" }, "DSP_R.DSP_IMUX6_0->DSP_0_A23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_0" }, "DSP_R.DSP_IMUX6_1->DSP_0_A27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_1" }, "DSP_R.DSP_IMUX6_2->DSP_0_C28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_2" }, "DSP_R.DSP_IMUX6_3->DSP_0_A15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_3" }, "DSP_R.DSP_IMUX6_4->DSP_0_A19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_4" }, "DSP_R.DSP_IMUX7_0->DSP_0_A21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_0" }, "DSP_R.DSP_IMUX7_1->DSP_0_A25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_1" }, "DSP_R.DSP_IMUX7_2->DSP_0_A29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_2" }, "DSP_R.DSP_IMUX7_3->DSP_0_A13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_3" }, "DSP_R.DSP_IMUX7_4->DSP_0_A17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_4" }, "DSP_R.DSP_IMUX8_0->DSP_1_C41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_0" }, "DSP_R.DSP_IMUX8_1->DSP_1_B7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_1" }, "DSP_R.DSP_IMUX8_2->DSP_1_B11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_2" }, "DSP_R.DSP_IMUX8_3->DSP_1_CEB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_3" }, "DSP_R.DSP_IMUX8_4->DSP_1_OPMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_4" }, "DSP_R.DSP_IMUX9_0->DSP_1_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_0" }, "DSP_R.DSP_IMUX9_1->DSP_1_A7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_1" }, "DSP_R.DSP_IMUX9_2->DSP_1_A11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_2" }, "DSP_R.DSP_IMUX9_3->DSP_1_CEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_3" }, "DSP_R.DSP_IMUX9_4->DSP_1_OPMODE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_4" }, "DSP_R.DSP_VCC_R->DSP_0_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" } }, @@ -5564,423 +14298,4176 @@ "name": "X0Y0", "prefix": "DSP48", "site_pins": { - "A0": "DSP_0_A0", - "A1": "DSP_0_A1", - "A10": "DSP_0_A10", - "A11": "DSP_0_A11", - "A12": "DSP_0_A12", - "A13": "DSP_0_A13", - "A14": "DSP_0_A14", - "A15": "DSP_0_A15", - "A16": "DSP_0_A16", - "A17": "DSP_0_A17", - "A18": "DSP_0_A18", - "A19": "DSP_0_A19", - "A2": "DSP_0_A2", - "A20": "DSP_0_A20", - "A21": "DSP_0_A21", - "A22": "DSP_0_A22", - "A23": "DSP_0_A23", - "A24": "DSP_0_A24", - "A25": "DSP_0_A25", - "A26": "DSP_0_A26", - "A27": "DSP_0_A27", - "A28": "DSP_0_A28", - "A29": "DSP_0_A29", - "A3": "DSP_0_A3", - "A4": "DSP_0_A4", - "A5": "DSP_0_A5", - "A6": "DSP_0_A6", - "A7": "DSP_0_A7", - "A8": "DSP_0_A8", - "A9": "DSP_0_A9", - "ACIN0": "DSP_0_ACIN0", - "ACIN1": "DSP_0_ACIN1", - "ACIN10": "DSP_0_ACIN10", - "ACIN11": "DSP_0_ACIN11", - "ACIN12": "DSP_0_ACIN12", - "ACIN13": "DSP_0_ACIN13", - "ACIN14": "DSP_0_ACIN14", - "ACIN15": "DSP_0_ACIN15", - "ACIN16": "DSP_0_ACIN16", - "ACIN17": "DSP_0_ACIN17", - "ACIN18": "DSP_0_ACIN18", - "ACIN19": "DSP_0_ACIN19", - "ACIN2": "DSP_0_ACIN2", - "ACIN20": "DSP_0_ACIN20", - "ACIN21": "DSP_0_ACIN21", - "ACIN22": "DSP_0_ACIN22", - "ACIN23": "DSP_0_ACIN23", - "ACIN24": "DSP_0_ACIN24", - "ACIN25": "DSP_0_ACIN25", - "ACIN26": "DSP_0_ACIN26", - "ACIN27": "DSP_0_ACIN27", - "ACIN28": "DSP_0_ACIN28", - "ACIN29": "DSP_0_ACIN29", - "ACIN3": "DSP_0_ACIN3", - "ACIN4": "DSP_0_ACIN4", - "ACIN5": "DSP_0_ACIN5", - "ACIN6": "DSP_0_ACIN6", - "ACIN7": "DSP_0_ACIN7", - "ACIN8": "DSP_0_ACIN8", - "ACIN9": "DSP_0_ACIN9", - "ACOUT0": "DSP_0_ACOUT0", - "ACOUT1": "DSP_0_ACOUT1", - "ACOUT10": "DSP_0_ACOUT10", - "ACOUT11": "DSP_0_ACOUT11", - "ACOUT12": "DSP_0_ACOUT12", - "ACOUT13": "DSP_0_ACOUT13", - "ACOUT14": "DSP_0_ACOUT14", - "ACOUT15": "DSP_0_ACOUT15", - "ACOUT16": "DSP_0_ACOUT16", - "ACOUT17": "DSP_0_ACOUT17", - "ACOUT18": "DSP_0_ACOUT18", - "ACOUT19": "DSP_0_ACOUT19", - "ACOUT2": "DSP_0_ACOUT2", - "ACOUT20": "DSP_0_ACOUT20", - "ACOUT21": "DSP_0_ACOUT21", - "ACOUT22": "DSP_0_ACOUT22", - "ACOUT23": "DSP_0_ACOUT23", - "ACOUT24": "DSP_0_ACOUT24", - "ACOUT25": "DSP_0_ACOUT25", - "ACOUT26": "DSP_0_ACOUT26", - "ACOUT27": "DSP_0_ACOUT27", - "ACOUT28": "DSP_0_ACOUT28", - "ACOUT29": "DSP_0_ACOUT29", - "ACOUT3": "DSP_0_ACOUT3", - "ACOUT4": "DSP_0_ACOUT4", - "ACOUT5": "DSP_0_ACOUT5", - "ACOUT6": "DSP_0_ACOUT6", - "ACOUT7": "DSP_0_ACOUT7", - "ACOUT8": "DSP_0_ACOUT8", - "ACOUT9": "DSP_0_ACOUT9", - "ALUMODE0": "DSP_0_ALUMODE0", - "ALUMODE1": "DSP_0_ALUMODE1", - "ALUMODE2": "DSP_0_ALUMODE2", - "ALUMODE3": "DSP_0_ALUMODE3", - "B0": "DSP_0_B0", - "B1": "DSP_0_B1", - "B10": "DSP_0_B10", - "B11": "DSP_0_B11", - "B12": "DSP_0_B12", - "B13": "DSP_0_B13", - "B14": "DSP_0_B14", - "B15": "DSP_0_B15", - "B16": "DSP_0_B16", - "B17": "DSP_0_B17", - "B2": "DSP_0_B2", - "B3": "DSP_0_B3", - "B4": "DSP_0_B4", - "B5": "DSP_0_B5", - "B6": "DSP_0_B6", - "B7": "DSP_0_B7", - "B8": "DSP_0_B8", - "B9": "DSP_0_B9", - "BCIN0": "DSP_0_BCIN0", - "BCIN1": "DSP_0_BCIN1", - "BCIN10": "DSP_0_BCIN10", - "BCIN11": "DSP_0_BCIN11", - "BCIN12": "DSP_0_BCIN12", - "BCIN13": "DSP_0_BCIN13", - "BCIN14": "DSP_0_BCIN14", - "BCIN15": "DSP_0_BCIN15", - "BCIN16": "DSP_0_BCIN16", - "BCIN17": "DSP_0_BCIN17", - "BCIN2": "DSP_0_BCIN2", - "BCIN3": "DSP_0_BCIN3", - "BCIN4": "DSP_0_BCIN4", - "BCIN5": "DSP_0_BCIN5", - "BCIN6": "DSP_0_BCIN6", - "BCIN7": "DSP_0_BCIN7", - "BCIN8": "DSP_0_BCIN8", - "BCIN9": "DSP_0_BCIN9", - "BCOUT0": "DSP_0_BCOUT0", - "BCOUT1": "DSP_0_BCOUT1", - "BCOUT10": "DSP_0_BCOUT10", - "BCOUT11": "DSP_0_BCOUT11", - "BCOUT12": "DSP_0_BCOUT12", - "BCOUT13": "DSP_0_BCOUT13", - "BCOUT14": "DSP_0_BCOUT14", - "BCOUT15": "DSP_0_BCOUT15", - "BCOUT16": "DSP_0_BCOUT16", - "BCOUT17": "DSP_0_BCOUT17", - "BCOUT2": "DSP_0_BCOUT2", - "BCOUT3": "DSP_0_BCOUT3", - "BCOUT4": "DSP_0_BCOUT4", - "BCOUT5": "DSP_0_BCOUT5", - "BCOUT6": "DSP_0_BCOUT6", - "BCOUT7": "DSP_0_BCOUT7", - "BCOUT8": "DSP_0_BCOUT8", - "BCOUT9": "DSP_0_BCOUT9", - "C0": "DSP_0_C0", - "C1": "DSP_0_C1", - "C10": "DSP_0_C10", - "C11": "DSP_0_C11", - "C12": "DSP_0_C12", - "C13": "DSP_0_C13", - "C14": "DSP_0_C14", - "C15": "DSP_0_C15", - "C16": "DSP_0_C16", - "C17": "DSP_0_C17", - "C18": "DSP_0_C18", - "C19": "DSP_0_C19", - "C2": "DSP_0_C2", - "C20": "DSP_0_C20", - "C21": "DSP_0_C21", - "C22": "DSP_0_C22", - "C23": "DSP_0_C23", - "C24": "DSP_0_C24", - "C25": "DSP_0_C25", - "C26": "DSP_0_C26", - "C27": "DSP_0_C27", - "C28": "DSP_0_C28", - "C29": "DSP_0_C29", - "C3": "DSP_0_C3", - "C30": "DSP_0_C30", - "C31": "DSP_0_C31", - "C32": "DSP_0_C32", - "C33": "DSP_0_C33", - "C34": "DSP_0_C34", - "C35": "DSP_0_C35", - "C36": "DSP_0_C36", - "C37": "DSP_0_C37", - "C38": "DSP_0_C38", - "C39": "DSP_0_C39", - "C4": "DSP_0_C4", - "C40": "DSP_0_C40", - "C41": "DSP_0_C41", - "C42": "DSP_0_C42", - "C43": "DSP_0_C43", - "C44": "DSP_0_C44", - "C45": "DSP_0_C45", - "C46": "DSP_0_C46", - "C47": "DSP_0_C47", - "C5": "DSP_0_C5", - "C6": "DSP_0_C6", - "C7": "DSP_0_C7", - "C8": "DSP_0_C8", - "C9": "DSP_0_C9", - "CARRYCASCIN": "DSP_0_CARRYCASCIN", - "CARRYCASCOUT": "DSP_0_CARRYCASCOUT", - "CARRYIN": "DSP_0_CARRYIN", - "CARRYINSEL0": "DSP_0_CARRYINSEL0", - "CARRYINSEL1": "DSP_0_CARRYINSEL1", - "CARRYINSEL2": "DSP_0_CARRYINSEL2", - "CARRYOUT0": "DSP_0_CARRYOUT0", - "CARRYOUT1": "DSP_0_CARRYOUT1", - "CARRYOUT2": "DSP_0_CARRYOUT2", - "CARRYOUT3": "DSP_0_CARRYOUT3", - "CEA1": "DSP_0_CEA1", - "CEA2": "DSP_0_CEA2", - "CEAD": "DSP_0_CEAD", - "CEALUMODE": "DSP_0_CEALUMODE", - "CEB1": "DSP_0_CEB1", - "CEB2": "DSP_0_CEB2", - "CEC": "DSP_0_CEC", - "CECARRYIN": "DSP_0_CECARRYIN", - "CECTRL": "DSP_0_CECTRL", - "CED": "DSP_0_CED", - "CEINMODE": "DSP_0_CEINMODE", - "CEM": "DSP_0_CEM", - "CEP": "DSP_0_CEP", - "CLK": "DSP_0_CLK", - "D0": "DSP_0_D0", - "D1": "DSP_0_D1", - "D10": "DSP_0_D10", - "D11": "DSP_0_D11", - "D12": "DSP_0_D12", - "D13": "DSP_0_D13", - "D14": "DSP_0_D14", - "D15": "DSP_0_D15", - "D16": "DSP_0_D16", - "D17": "DSP_0_D17", - "D18": "DSP_0_D18", - "D19": "DSP_0_D19", - "D2": "DSP_0_D2", - "D20": "DSP_0_D20", - "D21": "DSP_0_D21", - "D22": "DSP_0_D22", - "D23": "DSP_0_D23", - "D24": "DSP_0_D24", - "D3": "DSP_0_D3", - "D4": "DSP_0_D4", - "D5": "DSP_0_D5", - "D6": "DSP_0_D6", - "D7": "DSP_0_D7", - "D8": "DSP_0_D8", - "D9": "DSP_0_D9", - "INMODE0": "DSP_0_INMODE0", - "INMODE1": "DSP_0_INMODE1", - "INMODE2": "DSP_0_INMODE2", - "INMODE3": "DSP_0_INMODE3", - "INMODE4": "DSP_0_INMODE4", - "MULTSIGNIN": "DSP_0_MULTSIGNIN", - "MULTSIGNOUT": "DSP_0_MULTSIGNOUT", - "OPMODE0": "DSP_0_OPMODE0", - "OPMODE1": "DSP_0_OPMODE1", - "OPMODE2": "DSP_0_OPMODE2", - "OPMODE3": "DSP_0_OPMODE3", - "OPMODE4": "DSP_0_OPMODE4", - "OPMODE5": "DSP_0_OPMODE5", - "OPMODE6": "DSP_0_OPMODE6", - "OVERFLOW": "DSP_0_OVERFLOW", - "P0": "DSP_0_P0", - "P1": "DSP_0_P1", - "P10": "DSP_0_P10", - "P11": "DSP_0_P11", - "P12": "DSP_0_P12", - "P13": "DSP_0_P13", - "P14": "DSP_0_P14", - "P15": "DSP_0_P15", - "P16": "DSP_0_P16", - "P17": "DSP_0_P17", - "P18": "DSP_0_P18", - "P19": "DSP_0_P19", - "P2": "DSP_0_P2", - "P20": "DSP_0_P20", - "P21": "DSP_0_P21", - "P22": "DSP_0_P22", - "P23": "DSP_0_P23", - "P24": "DSP_0_P24", - "P25": "DSP_0_P25", - "P26": "DSP_0_P26", - "P27": "DSP_0_P27", - "P28": "DSP_0_P28", - "P29": "DSP_0_P29", - "P3": "DSP_0_P3", - "P30": "DSP_0_P30", - "P31": "DSP_0_P31", - "P32": "DSP_0_P32", - "P33": "DSP_0_P33", - "P34": "DSP_0_P34", - "P35": "DSP_0_P35", - "P36": "DSP_0_P36", - "P37": "DSP_0_P37", - "P38": "DSP_0_P38", - "P39": "DSP_0_P39", - "P4": "DSP_0_P4", - "P40": "DSP_0_P40", - "P41": "DSP_0_P41", - "P42": "DSP_0_P42", - "P43": "DSP_0_P43", - "P44": "DSP_0_P44", - "P45": "DSP_0_P45", - "P46": "DSP_0_P46", - "P47": "DSP_0_P47", - "P5": "DSP_0_P5", - "P6": "DSP_0_P6", - "P7": "DSP_0_P7", - "P8": "DSP_0_P8", - "P9": "DSP_0_P9", - "PATTERNBDETECT": "DSP_0_PATTERNBDETECT", - "PATTERNDETECT": "DSP_0_PATTERNDETECT", - "PCIN0": "DSP_0_PCIN0", - "PCIN1": "DSP_0_PCIN1", - "PCIN10": "DSP_0_PCIN10", - "PCIN11": "DSP_0_PCIN11", - "PCIN12": "DSP_0_PCIN12", - "PCIN13": "DSP_0_PCIN13", - "PCIN14": "DSP_0_PCIN14", - "PCIN15": "DSP_0_PCIN15", - "PCIN16": "DSP_0_PCIN16", - "PCIN17": "DSP_0_PCIN17", - "PCIN18": "DSP_0_PCIN18", - "PCIN19": "DSP_0_PCIN19", - "PCIN2": "DSP_0_PCIN2", - "PCIN20": "DSP_0_PCIN20", - "PCIN21": "DSP_0_PCIN21", - "PCIN22": "DSP_0_PCIN22", - "PCIN23": "DSP_0_PCIN23", - "PCIN24": "DSP_0_PCIN24", - "PCIN25": "DSP_0_PCIN25", - "PCIN26": "DSP_0_PCIN26", - "PCIN27": "DSP_0_PCIN27", - "PCIN28": "DSP_0_PCIN28", - "PCIN29": "DSP_0_PCIN29", - "PCIN3": "DSP_0_PCIN3", - "PCIN30": "DSP_0_PCIN30", - "PCIN31": "DSP_0_PCIN31", - "PCIN32": "DSP_0_PCIN32", - "PCIN33": "DSP_0_PCIN33", - "PCIN34": "DSP_0_PCIN34", - "PCIN35": "DSP_0_PCIN35", - "PCIN36": "DSP_0_PCIN36", - "PCIN37": "DSP_0_PCIN37", - "PCIN38": "DSP_0_PCIN38", - "PCIN39": "DSP_0_PCIN39", - "PCIN4": "DSP_0_PCIN4", - "PCIN40": "DSP_0_PCIN40", - "PCIN41": "DSP_0_PCIN41", - "PCIN42": "DSP_0_PCIN42", - "PCIN43": "DSP_0_PCIN43", - "PCIN44": "DSP_0_PCIN44", - "PCIN45": "DSP_0_PCIN45", - "PCIN46": "DSP_0_PCIN46", - "PCIN47": "DSP_0_PCIN47", - "PCIN5": "DSP_0_PCIN5", - "PCIN6": "DSP_0_PCIN6", - "PCIN7": "DSP_0_PCIN7", - "PCIN8": "DSP_0_PCIN8", - "PCIN9": "DSP_0_PCIN9", - "PCOUT0": "DSP_0_PCOUT0", - "PCOUT1": "DSP_0_PCOUT1", - "PCOUT10": "DSP_0_PCOUT10", - "PCOUT11": "DSP_0_PCOUT11", - "PCOUT12": "DSP_0_PCOUT12", - "PCOUT13": "DSP_0_PCOUT13", - "PCOUT14": "DSP_0_PCOUT14", - "PCOUT15": "DSP_0_PCOUT15", - "PCOUT16": "DSP_0_PCOUT16", - "PCOUT17": "DSP_0_PCOUT17", - "PCOUT18": "DSP_0_PCOUT18", - "PCOUT19": "DSP_0_PCOUT19", - "PCOUT2": "DSP_0_PCOUT2", - "PCOUT20": "DSP_0_PCOUT20", - "PCOUT21": "DSP_0_PCOUT21", - "PCOUT22": "DSP_0_PCOUT22", - "PCOUT23": "DSP_0_PCOUT23", - "PCOUT24": "DSP_0_PCOUT24", - "PCOUT25": "DSP_0_PCOUT25", - "PCOUT26": "DSP_0_PCOUT26", - "PCOUT27": "DSP_0_PCOUT27", - "PCOUT28": "DSP_0_PCOUT28", - "PCOUT29": "DSP_0_PCOUT29", - "PCOUT3": "DSP_0_PCOUT3", - "PCOUT30": "DSP_0_PCOUT30", - "PCOUT31": "DSP_0_PCOUT31", - "PCOUT32": "DSP_0_PCOUT32", - "PCOUT33": "DSP_0_PCOUT33", - "PCOUT34": "DSP_0_PCOUT34", - "PCOUT35": "DSP_0_PCOUT35", - "PCOUT36": "DSP_0_PCOUT36", - "PCOUT37": "DSP_0_PCOUT37", - "PCOUT38": "DSP_0_PCOUT38", - "PCOUT39": "DSP_0_PCOUT39", - "PCOUT4": "DSP_0_PCOUT4", - "PCOUT40": "DSP_0_PCOUT40", - "PCOUT41": "DSP_0_PCOUT41", - "PCOUT42": "DSP_0_PCOUT42", - "PCOUT43": "DSP_0_PCOUT43", - "PCOUT44": "DSP_0_PCOUT44", - "PCOUT45": "DSP_0_PCOUT45", - "PCOUT46": "DSP_0_PCOUT46", - "PCOUT47": "DSP_0_PCOUT47", - "PCOUT5": "DSP_0_PCOUT5", - "PCOUT6": "DSP_0_PCOUT6", - "PCOUT7": "DSP_0_PCOUT7", - "PCOUT8": "DSP_0_PCOUT8", - "PCOUT9": "DSP_0_PCOUT9", - "RSTA": "DSP_0_RSTA", - "RSTALLCARRYIN": "DSP_0_RSTALLCARRYIN", - "RSTALUMODE": "DSP_0_RSTALUMODE", - "RSTB": "DSP_0_RSTB", - "RSTC": "DSP_0_RSTC", - "RSTCTRL": "DSP_0_RSTCTRL", - "RSTD": "DSP_0_RSTD", - "RSTINMODE": "DSP_0_RSTINMODE", - "RSTM": "DSP_0_RSTM", - "RSTP": "DSP_0_RSTP", - "UNDERFLOW": "DSP_0_UNDERFLOW" + "A0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_0_A0" + }, + "A1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_0_A1" + }, + "A10": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_0_A10" + }, + "A11": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_0_A11" + }, + "A12": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_0_A12" + }, + "A13": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_0_A13" + }, + "A14": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_0_A14" + }, + "A15": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_0_A15" + }, + "A16": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_0_A16" + }, + "A17": { + "cap": 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"BCOUT17": "DSP_1_BCOUT17", - "BCOUT2": "DSP_1_BCOUT2", - "BCOUT3": "DSP_1_BCOUT3", - "BCOUT4": "DSP_1_BCOUT4", - "BCOUT5": "DSP_1_BCOUT5", - "BCOUT6": "DSP_1_BCOUT6", - "BCOUT7": "DSP_1_BCOUT7", - "BCOUT8": "DSP_1_BCOUT8", - "BCOUT9": "DSP_1_BCOUT9", - "C0": "DSP_1_C0", - "C1": "DSP_1_C1", - "C10": "DSP_1_C10", - "C11": "DSP_1_C11", - "C12": "DSP_1_C12", - "C13": "DSP_1_C13", - "C14": "DSP_1_C14", - "C15": "DSP_1_C15", - "C16": "DSP_1_C16", - "C17": "DSP_1_C17", - "C18": "DSP_1_C18", - "C19": "DSP_1_C19", - "C2": "DSP_1_C2", - "C20": "DSP_1_C20", - "C21": "DSP_1_C21", - "C22": "DSP_1_C22", - "C23": "DSP_1_C23", - "C24": "DSP_1_C24", - "C25": "DSP_1_C25", - "C26": "DSP_1_C26", - "C27": "DSP_1_C27", - "C28": "DSP_1_C28", - "C29": "DSP_1_C29", - "C3": "DSP_1_C3", - "C30": "DSP_1_C30", - "C31": "DSP_1_C31", - "C32": "DSP_1_C32", - "C33": "DSP_1_C33", - "C34": "DSP_1_C34", - "C35": "DSP_1_C35", - "C36": "DSP_1_C36", - "C37": "DSP_1_C37", - "C38": "DSP_1_C38", - "C39": "DSP_1_C39", - "C4": "DSP_1_C4", - "C40": "DSP_1_C40", - "C41": "DSP_1_C41", - "C42": "DSP_1_C42", - "C43": "DSP_1_C43", - "C44": "DSP_1_C44", - "C45": "DSP_1_C45", - "C46": "DSP_1_C46", - "C47": "DSP_1_C47", - "C5": "DSP_1_C5", - "C6": "DSP_1_C6", - "C7": "DSP_1_C7", - "C8": "DSP_1_C8", - "C9": "DSP_1_C9", - "CARRYCASCIN": "DSP_1_CARRYCASCIN", - "CARRYCASCOUT": "DSP_1_CARRYCASCOUT", - "CARRYIN": "DSP_1_CARRYIN", - "CARRYINSEL0": "DSP_1_CARRYINSEL0", - "CARRYINSEL1": "DSP_1_CARRYINSEL1", - "CARRYINSEL2": "DSP_1_CARRYINSEL2", - "CARRYOUT0": "DSP_1_CARRYOUT0", - "CARRYOUT1": "DSP_1_CARRYOUT1", - "CARRYOUT2": "DSP_1_CARRYOUT2", - "CARRYOUT3": "DSP_1_CARRYOUT3", - "CEA1": "DSP_1_CEA1", - "CEA2": "DSP_1_CEA2", - "CEAD": "DSP_1_CEAD", - "CEALUMODE": "DSP_1_CEALUMODE", - "CEB1": "DSP_1_CEB1", - "CEB2": "DSP_1_CEB2", - "CEC": "DSP_1_CEC", - "CECARRYIN": "DSP_1_CECARRYIN", - "CECTRL": "DSP_1_CECTRL", - "CED": "DSP_1_CED", - "CEINMODE": "DSP_1_CEINMODE", - "CEM": "DSP_1_CEM", - "CEP": "DSP_1_CEP", - "CLK": "DSP_1_CLK", - "D0": "DSP_1_D0", - "D1": "DSP_1_D1", - "D10": "DSP_1_D10", - "D11": "DSP_1_D11", - "D12": "DSP_1_D12", - "D13": "DSP_1_D13", - "D14": "DSP_1_D14", - "D15": "DSP_1_D15", - "D16": "DSP_1_D16", - "D17": "DSP_1_D17", - "D18": "DSP_1_D18", - "D19": "DSP_1_D19", - "D2": "DSP_1_D2", - "D20": "DSP_1_D20", - "D21": "DSP_1_D21", - "D22": "DSP_1_D22", - "D23": "DSP_1_D23", - "D24": "DSP_1_D24", - "D3": "DSP_1_D3", - "D4": "DSP_1_D4", - "D5": "DSP_1_D5", - "D6": "DSP_1_D6", - "D7": "DSP_1_D7", - "D8": "DSP_1_D8", - "D9": "DSP_1_D9", - "INMODE0": "DSP_1_INMODE0", - "INMODE1": "DSP_1_INMODE1", - "INMODE2": "DSP_1_INMODE2", - "INMODE3": "DSP_1_INMODE3", - "INMODE4": "DSP_1_INMODE4", - "MULTSIGNIN": "DSP_1_MULTSIGNIN", - "MULTSIGNOUT": "DSP_1_MULTSIGNOUT", - "OPMODE0": "DSP_1_OPMODE0", - "OPMODE1": "DSP_1_OPMODE1", - "OPMODE2": "DSP_1_OPMODE2", - "OPMODE3": "DSP_1_OPMODE3", - "OPMODE4": "DSP_1_OPMODE4", - "OPMODE5": "DSP_1_OPMODE5", - "OPMODE6": "DSP_1_OPMODE6", - "OVERFLOW": "DSP_1_OVERFLOW", - "P0": "DSP_1_P0", - "P1": "DSP_1_P1", - "P10": "DSP_1_P10", - "P11": "DSP_1_P11", - "P12": "DSP_1_P12", - "P13": "DSP_1_P13", - "P14": "DSP_1_P14", - "P15": "DSP_1_P15", - "P16": "DSP_1_P16", - "P17": "DSP_1_P17", - "P18": "DSP_1_P18", - "P19": "DSP_1_P19", - "P2": "DSP_1_P2", - "P20": "DSP_1_P20", - "P21": "DSP_1_P21", - "P22": "DSP_1_P22", - "P23": "DSP_1_P23", - "P24": "DSP_1_P24", - "P25": "DSP_1_P25", - "P26": "DSP_1_P26", - "P27": "DSP_1_P27", - "P28": "DSP_1_P28", - "P29": "DSP_1_P29", - "P3": "DSP_1_P3", - "P30": "DSP_1_P30", - "P31": "DSP_1_P31", - "P32": "DSP_1_P32", - "P33": "DSP_1_P33", - "P34": "DSP_1_P34", - "P35": "DSP_1_P35", - "P36": "DSP_1_P36", - "P37": "DSP_1_P37", - "P38": "DSP_1_P38", - "P39": "DSP_1_P39", - "P4": "DSP_1_P4", - "P40": "DSP_1_P40", - "P41": "DSP_1_P41", - "P42": "DSP_1_P42", - "P43": "DSP_1_P43", - "P44": "DSP_1_P44", - "P45": "DSP_1_P45", - "P46": "DSP_1_P46", - "P47": "DSP_1_P47", - "P5": "DSP_1_P5", - "P6": "DSP_1_P6", - "P7": "DSP_1_P7", - "P8": "DSP_1_P8", - "P9": "DSP_1_P9", - "PATTERNBDETECT": "DSP_1_PATTERNBDETECT", - "PATTERNDETECT": "DSP_1_PATTERNDETECT", - "PCIN0": "DSP_1_PCIN0", - "PCIN1": "DSP_1_PCIN1", - "PCIN10": "DSP_1_PCIN10", - "PCIN11": "DSP_1_PCIN11", - "PCIN12": "DSP_1_PCIN12", - "PCIN13": "DSP_1_PCIN13", - "PCIN14": "DSP_1_PCIN14", - "PCIN15": "DSP_1_PCIN15", - "PCIN16": "DSP_1_PCIN16", - "PCIN17": "DSP_1_PCIN17", - "PCIN18": "DSP_1_PCIN18", - "PCIN19": "DSP_1_PCIN19", - "PCIN2": "DSP_1_PCIN2", - "PCIN20": "DSP_1_PCIN20", - "PCIN21": "DSP_1_PCIN21", - "PCIN22": "DSP_1_PCIN22", - "PCIN23": "DSP_1_PCIN23", - "PCIN24": "DSP_1_PCIN24", - "PCIN25": "DSP_1_PCIN25", - "PCIN26": "DSP_1_PCIN26", - "PCIN27": "DSP_1_PCIN27", - "PCIN28": "DSP_1_PCIN28", - "PCIN29": "DSP_1_PCIN29", - "PCIN3": "DSP_1_PCIN3", - "PCIN30": "DSP_1_PCIN30", - "PCIN31": "DSP_1_PCIN31", - "PCIN32": "DSP_1_PCIN32", - "PCIN33": "DSP_1_PCIN33", - "PCIN34": "DSP_1_PCIN34", - "PCIN35": "DSP_1_PCIN35", - "PCIN36": "DSP_1_PCIN36", - "PCIN37": "DSP_1_PCIN37", - "PCIN38": "DSP_1_PCIN38", - "PCIN39": "DSP_1_PCIN39", - "PCIN4": "DSP_1_PCIN4", - "PCIN40": "DSP_1_PCIN40", - "PCIN41": "DSP_1_PCIN41", - "PCIN42": "DSP_1_PCIN42", - "PCIN43": "DSP_1_PCIN43", - "PCIN44": "DSP_1_PCIN44", - "PCIN45": "DSP_1_PCIN45", - "PCIN46": "DSP_1_PCIN46", - "PCIN47": "DSP_1_PCIN47", - "PCIN5": "DSP_1_PCIN5", - "PCIN6": "DSP_1_PCIN6", - "PCIN7": "DSP_1_PCIN7", - "PCIN8": "DSP_1_PCIN8", - "PCIN9": "DSP_1_PCIN9", - "PCOUT0": "DSP_1_PCOUT0", - "PCOUT1": "DSP_1_PCOUT1", - "PCOUT10": "DSP_1_PCOUT10", - "PCOUT11": "DSP_1_PCOUT11", - "PCOUT12": "DSP_1_PCOUT12", - "PCOUT13": "DSP_1_PCOUT13", - "PCOUT14": "DSP_1_PCOUT14", - "PCOUT15": "DSP_1_PCOUT15", - "PCOUT16": "DSP_1_PCOUT16", - "PCOUT17": "DSP_1_PCOUT17", - "PCOUT18": "DSP_1_PCOUT18", - "PCOUT19": "DSP_1_PCOUT19", - "PCOUT2": "DSP_1_PCOUT2", - "PCOUT20": "DSP_1_PCOUT20", - "PCOUT21": "DSP_1_PCOUT21", - "PCOUT22": "DSP_1_PCOUT22", - "PCOUT23": "DSP_1_PCOUT23", - "PCOUT24": "DSP_1_PCOUT24", - "PCOUT25": "DSP_1_PCOUT25", - "PCOUT26": "DSP_1_PCOUT26", - "PCOUT27": "DSP_1_PCOUT27", - "PCOUT28": "DSP_1_PCOUT28", - "PCOUT29": "DSP_1_PCOUT29", - "PCOUT3": "DSP_1_PCOUT3", - "PCOUT30": "DSP_1_PCOUT30", - "PCOUT31": "DSP_1_PCOUT31", - "PCOUT32": "DSP_1_PCOUT32", - "PCOUT33": "DSP_1_PCOUT33", - "PCOUT34": "DSP_1_PCOUT34", - "PCOUT35": "DSP_1_PCOUT35", - "PCOUT36": "DSP_1_PCOUT36", - "PCOUT37": "DSP_1_PCOUT37", - "PCOUT38": "DSP_1_PCOUT38", - "PCOUT39": "DSP_1_PCOUT39", - "PCOUT4": "DSP_1_PCOUT4", - "PCOUT40": "DSP_1_PCOUT40", - "PCOUT41": "DSP_1_PCOUT41", - "PCOUT42": "DSP_1_PCOUT42", - "PCOUT43": "DSP_1_PCOUT43", - "PCOUT44": "DSP_1_PCOUT44", - "PCOUT45": "DSP_1_PCOUT45", - "PCOUT46": "DSP_1_PCOUT46", - "PCOUT47": "DSP_1_PCOUT47", - "PCOUT5": "DSP_1_PCOUT5", - "PCOUT6": "DSP_1_PCOUT6", - "PCOUT7": "DSP_1_PCOUT7", - "PCOUT8": "DSP_1_PCOUT8", - "PCOUT9": "DSP_1_PCOUT9", - "RSTA": "DSP_1_RSTA", - "RSTALLCARRYIN": "DSP_1_RSTALLCARRYIN", - "RSTALUMODE": "DSP_1_RSTALUMODE", - "RSTB": "DSP_1_RSTB", - "RSTC": "DSP_1_RSTC", - "RSTCTRL": "DSP_1_RSTCTRL", - "RSTD": "DSP_1_RSTD", - "RSTINMODE": "DSP_1_RSTINMODE", - "RSTM": "DSP_1_RSTM", - "RSTP": "DSP_1_RSTP", - "UNDERFLOW": "DSP_1_UNDERFLOW" + "A0": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A0" + }, + "A1": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A1" + }, + "A10": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A10" + }, + "A11": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A11" + }, + "A12": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A12" + }, + "A13": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A13" + }, + "A14": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A14" + }, + "A15": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A15" + }, + "A16": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A16" + }, + "A17": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A17" + }, + "A18": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A18" + }, + "A19": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A19" + }, + "A2": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A2" + }, + "A20": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A20" + }, + "A21": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A21" + }, + "A22": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A22" + }, + "A23": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A23" + }, + "A24": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A24" + }, + "A25": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A25" + }, + "A26": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A26" + }, + "A27": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A27" + }, + "A28": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A28" + }, + "A29": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "DSP_1_A29" + }, + "A3": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + 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"res": "0.0", + "wire": "DSP_VCC_R" + } }, "type": "TIEOFF", "x_coord": 0, @@ -6425,2050 +22683,4834 @@ } ], "tile_type": "DSP_R", - "wires": [ - "DSP_0_A0", - "DSP_0_A1", - "DSP_0_A10", - "DSP_0_A11", - "DSP_0_A12", - "DSP_0_A13", - "DSP_0_A14", - "DSP_0_A15", - "DSP_0_A16", - "DSP_0_A17", - "DSP_0_A18", - "DSP_0_A19", - "DSP_0_A2", - "DSP_0_A20", - "DSP_0_A21", - "DSP_0_A22", - "DSP_0_A23", - "DSP_0_A24", - "DSP_0_A25", - "DSP_0_A26", - "DSP_0_A27", - "DSP_0_A28", - "DSP_0_A29", - "DSP_0_A3", - "DSP_0_A4", - "DSP_0_A5", - "DSP_0_A6", - "DSP_0_A7", - "DSP_0_A8", - "DSP_0_A9", - "DSP_0_ACIN0", - "DSP_0_ACIN1", - "DSP_0_ACIN10", - "DSP_0_ACIN11", - "DSP_0_ACIN12", - "DSP_0_ACIN13", - "DSP_0_ACIN14", - "DSP_0_ACIN15", - "DSP_0_ACIN16", - "DSP_0_ACIN17", - "DSP_0_ACIN18", - "DSP_0_ACIN19", - "DSP_0_ACIN2", - "DSP_0_ACIN20", - "DSP_0_ACIN21", - "DSP_0_ACIN22", - "DSP_0_ACIN23", - "DSP_0_ACIN24", - "DSP_0_ACIN25", - "DSP_0_ACIN26", - "DSP_0_ACIN27", - "DSP_0_ACIN28", - "DSP_0_ACIN29", - "DSP_0_ACIN3", - "DSP_0_ACIN4", - "DSP_0_ACIN5", - "DSP_0_ACIN6", - "DSP_0_ACIN7", - "DSP_0_ACIN8", - "DSP_0_ACIN9", - "DSP_0_ACOUT0", - "DSP_0_ACOUT1", - "DSP_0_ACOUT10", - "DSP_0_ACOUT11", - "DSP_0_ACOUT12", - "DSP_0_ACOUT13", - "DSP_0_ACOUT14", - "DSP_0_ACOUT15", - "DSP_0_ACOUT16", - "DSP_0_ACOUT17", - "DSP_0_ACOUT18", - "DSP_0_ACOUT19", - "DSP_0_ACOUT2", - "DSP_0_ACOUT20", - "DSP_0_ACOUT21", - "DSP_0_ACOUT22", - "DSP_0_ACOUT23", - "DSP_0_ACOUT24", - "DSP_0_ACOUT25", - "DSP_0_ACOUT26", - "DSP_0_ACOUT27", - "DSP_0_ACOUT28", - "DSP_0_ACOUT29", - "DSP_0_ACOUT3", - "DSP_0_ACOUT4", - "DSP_0_ACOUT5", - "DSP_0_ACOUT6", - "DSP_0_ACOUT7", - "DSP_0_ACOUT8", - "DSP_0_ACOUT9", - "DSP_0_ALUMODE0", - "DSP_0_ALUMODE1", - "DSP_0_ALUMODE2", - "DSP_0_ALUMODE3", - "DSP_0_B0", - "DSP_0_B1", - "DSP_0_B10", - "DSP_0_B11", - "DSP_0_B12", - "DSP_0_B13", - "DSP_0_B14", - "DSP_0_B15", - "DSP_0_B16", - "DSP_0_B17", - "DSP_0_B2", - "DSP_0_B3", - "DSP_0_B4", - "DSP_0_B5", - "DSP_0_B6", - "DSP_0_B7", - "DSP_0_B8", - "DSP_0_B9", - "DSP_0_BCIN0", - "DSP_0_BCIN1", - "DSP_0_BCIN10", - "DSP_0_BCIN11", - "DSP_0_BCIN12", - "DSP_0_BCIN13", - "DSP_0_BCIN14", - "DSP_0_BCIN15", - "DSP_0_BCIN16", - "DSP_0_BCIN17", - "DSP_0_BCIN2", - "DSP_0_BCIN3", - "DSP_0_BCIN4", - "DSP_0_BCIN5", - "DSP_0_BCIN6", - "DSP_0_BCIN7", - "DSP_0_BCIN8", - "DSP_0_BCIN9", - "DSP_0_BCOUT0", - "DSP_0_BCOUT1", - "DSP_0_BCOUT10", - "DSP_0_BCOUT11", - "DSP_0_BCOUT12", - "DSP_0_BCOUT13", - "DSP_0_BCOUT14", - "DSP_0_BCOUT15", - "DSP_0_BCOUT16", - "DSP_0_BCOUT17", - "DSP_0_BCOUT2", - "DSP_0_BCOUT3", - "DSP_0_BCOUT4", - "DSP_0_BCOUT5", - "DSP_0_BCOUT6", - "DSP_0_BCOUT7", - "DSP_0_BCOUT8", - "DSP_0_BCOUT9", - "DSP_0_C0", - "DSP_0_C1", - "DSP_0_C10", - "DSP_0_C11", - "DSP_0_C12", - "DSP_0_C13", - "DSP_0_C14", - "DSP_0_C15", - "DSP_0_C16", - "DSP_0_C17", - "DSP_0_C18", - "DSP_0_C19", - "DSP_0_C2", - "DSP_0_C20", - "DSP_0_C21", - "DSP_0_C22", - "DSP_0_C23", - "DSP_0_C24", - "DSP_0_C25", - "DSP_0_C26", - "DSP_0_C27", - "DSP_0_C28", - "DSP_0_C29", - "DSP_0_C3", - "DSP_0_C30", - "DSP_0_C31", - "DSP_0_C32", - "DSP_0_C33", - "DSP_0_C34", - "DSP_0_C35", - "DSP_0_C36", - "DSP_0_C37", - "DSP_0_C38", - "DSP_0_C39", - "DSP_0_C4", - "DSP_0_C40", - "DSP_0_C41", - "DSP_0_C42", - "DSP_0_C43", - "DSP_0_C44", - "DSP_0_C45", - "DSP_0_C46", - "DSP_0_C47", - "DSP_0_C5", - "DSP_0_C6", - "DSP_0_C7", - "DSP_0_C8", - "DSP_0_C9", - "DSP_0_CARRYCASCIN", - "DSP_0_CARRYCASCOUT", - "DSP_0_CARRYIN", - "DSP_0_CARRYINSEL0", - "DSP_0_CARRYINSEL1", - "DSP_0_CARRYINSEL2", - "DSP_0_CARRYOUT0", - "DSP_0_CARRYOUT1", - "DSP_0_CARRYOUT2", - "DSP_0_CARRYOUT3", - "DSP_0_CEA1", - "DSP_0_CEA2", - "DSP_0_CEAD", - "DSP_0_CEALUMODE", - "DSP_0_CEB1", - "DSP_0_CEB2", - "DSP_0_CEC", - "DSP_0_CECARRYIN", - "DSP_0_CECTRL", - "DSP_0_CED", - "DSP_0_CEINMODE", - "DSP_0_CEM", - "DSP_0_CEP", - "DSP_0_CLK", - "DSP_0_D0", - "DSP_0_D1", - "DSP_0_D10", - "DSP_0_D11", - "DSP_0_D12", - "DSP_0_D13", - "DSP_0_D14", - "DSP_0_D15", - "DSP_0_D16", - "DSP_0_D17", - "DSP_0_D18", - "DSP_0_D19", - "DSP_0_D2", - "DSP_0_D20", - "DSP_0_D21", - "DSP_0_D22", - "DSP_0_D23", - "DSP_0_D24", - "DSP_0_D3", - "DSP_0_D4", - "DSP_0_D5", - "DSP_0_D6", - "DSP_0_D7", - "DSP_0_D8", - "DSP_0_D9", - "DSP_0_INMODE0", - "DSP_0_INMODE1", - "DSP_0_INMODE2", - "DSP_0_INMODE3", - "DSP_0_INMODE4", - "DSP_0_MULTSIGNIN", - "DSP_0_MULTSIGNOUT", - "DSP_0_OPMODE0", - "DSP_0_OPMODE1", - "DSP_0_OPMODE2", - "DSP_0_OPMODE3", - "DSP_0_OPMODE4", - "DSP_0_OPMODE5", - "DSP_0_OPMODE6", - "DSP_0_OVERFLOW", - "DSP_0_P0", - "DSP_0_P1", - "DSP_0_P10", - "DSP_0_P11", - "DSP_0_P12", - "DSP_0_P13", - "DSP_0_P14", - "DSP_0_P15", - "DSP_0_P16", - "DSP_0_P17", - "DSP_0_P18", - "DSP_0_P19", - "DSP_0_P2", - "DSP_0_P20", - "DSP_0_P21", - "DSP_0_P22", - "DSP_0_P23", - "DSP_0_P24", - "DSP_0_P25", - "DSP_0_P26", - "DSP_0_P27", - "DSP_0_P28", - "DSP_0_P29", - "DSP_0_P3", - "DSP_0_P30", - "DSP_0_P31", - "DSP_0_P32", - "DSP_0_P33", - "DSP_0_P34", - "DSP_0_P35", - "DSP_0_P36", - "DSP_0_P37", - "DSP_0_P38", - "DSP_0_P39", - "DSP_0_P4", - "DSP_0_P40", - "DSP_0_P41", - "DSP_0_P42", - "DSP_0_P43", - "DSP_0_P44", - "DSP_0_P45", - "DSP_0_P46", - "DSP_0_P47", - "DSP_0_P5", - "DSP_0_P6", - "DSP_0_P7", - "DSP_0_P8", - "DSP_0_P9", - "DSP_0_PATTERNBDETECT", - "DSP_0_PATTERNDETECT", - "DSP_0_PCIN0", - "DSP_0_PCIN1", - "DSP_0_PCIN10", - "DSP_0_PCIN11", - "DSP_0_PCIN12", - "DSP_0_PCIN13", - "DSP_0_PCIN14", - "DSP_0_PCIN15", - "DSP_0_PCIN16", - "DSP_0_PCIN17", - "DSP_0_PCIN18", - "DSP_0_PCIN19", - "DSP_0_PCIN2", - "DSP_0_PCIN20", - "DSP_0_PCIN21", - "DSP_0_PCIN22", - "DSP_0_PCIN23", - "DSP_0_PCIN24", - "DSP_0_PCIN25", - "DSP_0_PCIN26", - "DSP_0_PCIN27", - "DSP_0_PCIN28", - "DSP_0_PCIN29", - "DSP_0_PCIN3", - "DSP_0_PCIN30", - "DSP_0_PCIN31", - "DSP_0_PCIN32", - "DSP_0_PCIN33", - "DSP_0_PCIN34", - "DSP_0_PCIN35", - "DSP_0_PCIN36", - "DSP_0_PCIN37", - "DSP_0_PCIN38", - "DSP_0_PCIN39", - "DSP_0_PCIN4", - "DSP_0_PCIN40", - "DSP_0_PCIN41", - "DSP_0_PCIN42", - "DSP_0_PCIN43", - "DSP_0_PCIN44", - "DSP_0_PCIN45", - "DSP_0_PCIN46", - "DSP_0_PCIN47", - "DSP_0_PCIN5", - "DSP_0_PCIN6", - "DSP_0_PCIN7", - "DSP_0_PCIN8", - "DSP_0_PCIN9", - "DSP_0_PCOUT0", - "DSP_0_PCOUT1", - "DSP_0_PCOUT10", - "DSP_0_PCOUT11", - "DSP_0_PCOUT12", - "DSP_0_PCOUT13", - "DSP_0_PCOUT14", - "DSP_0_PCOUT15", - "DSP_0_PCOUT16", - "DSP_0_PCOUT17", - "DSP_0_PCOUT18", - "DSP_0_PCOUT19", - "DSP_0_PCOUT2", - "DSP_0_PCOUT20", - "DSP_0_PCOUT21", - "DSP_0_PCOUT22", - "DSP_0_PCOUT23", - "DSP_0_PCOUT24", - "DSP_0_PCOUT25", - "DSP_0_PCOUT26", - "DSP_0_PCOUT27", - "DSP_0_PCOUT28", - "DSP_0_PCOUT29", - "DSP_0_PCOUT3", - "DSP_0_PCOUT30", - "DSP_0_PCOUT31", - "DSP_0_PCOUT32", - "DSP_0_PCOUT33", - "DSP_0_PCOUT34", - "DSP_0_PCOUT35", - "DSP_0_PCOUT36", - "DSP_0_PCOUT37", - "DSP_0_PCOUT38", - "DSP_0_PCOUT39", - "DSP_0_PCOUT4", - "DSP_0_PCOUT40", - "DSP_0_PCOUT41", - "DSP_0_PCOUT42", - "DSP_0_PCOUT43", - "DSP_0_PCOUT44", - "DSP_0_PCOUT45", - "DSP_0_PCOUT46", - "DSP_0_PCOUT47", - "DSP_0_PCOUT5", - "DSP_0_PCOUT6", - "DSP_0_PCOUT7", - "DSP_0_PCOUT8", - "DSP_0_PCOUT9", - "DSP_0_RSTA", - "DSP_0_RSTALLCARRYIN", - "DSP_0_RSTALUMODE", - "DSP_0_RSTB", - "DSP_0_RSTC", - "DSP_0_RSTCTRL", - "DSP_0_RSTD", - "DSP_0_RSTINMODE", - "DSP_0_RSTM", - "DSP_0_RSTP", - "DSP_0_UNDERFLOW", - "DSP_1_A0", - "DSP_1_A1", - "DSP_1_A10", - "DSP_1_A11", - "DSP_1_A12", - "DSP_1_A13", - "DSP_1_A14", - "DSP_1_A15", - "DSP_1_A16", - "DSP_1_A17", - "DSP_1_A18", - "DSP_1_A19", - "DSP_1_A2", - "DSP_1_A20", - "DSP_1_A21", - "DSP_1_A22", - "DSP_1_A23", - "DSP_1_A24", - "DSP_1_A25", - "DSP_1_A26", - "DSP_1_A27", - "DSP_1_A28", - "DSP_1_A29", - "DSP_1_A3", - "DSP_1_A4", - "DSP_1_A5", - "DSP_1_A6", - "DSP_1_A7", - "DSP_1_A8", - "DSP_1_A9", - "DSP_1_ACIN0", - "DSP_1_ACIN1", - "DSP_1_ACIN10", - "DSP_1_ACIN11", - "DSP_1_ACIN12", - "DSP_1_ACIN13", - "DSP_1_ACIN14", - "DSP_1_ACIN15", - "DSP_1_ACIN16", - "DSP_1_ACIN17", - "DSP_1_ACIN18", - "DSP_1_ACIN19", - "DSP_1_ACIN2", - "DSP_1_ACIN20", - "DSP_1_ACIN21", - "DSP_1_ACIN22", - "DSP_1_ACIN23", - "DSP_1_ACIN24", - "DSP_1_ACIN25", - "DSP_1_ACIN26", - "DSP_1_ACIN27", - "DSP_1_ACIN28", - "DSP_1_ACIN29", - "DSP_1_ACIN3", - "DSP_1_ACIN4", - "DSP_1_ACIN5", - "DSP_1_ACIN6", - "DSP_1_ACIN7", - "DSP_1_ACIN8", - "DSP_1_ACIN9", - "DSP_1_ACOUT0", - "DSP_1_ACOUT1", - "DSP_1_ACOUT10", - "DSP_1_ACOUT11", - "DSP_1_ACOUT12", - "DSP_1_ACOUT13", - "DSP_1_ACOUT14", - "DSP_1_ACOUT15", - "DSP_1_ACOUT16", - "DSP_1_ACOUT17", - "DSP_1_ACOUT18", - "DSP_1_ACOUT19", - "DSP_1_ACOUT2", - "DSP_1_ACOUT20", - "DSP_1_ACOUT21", - "DSP_1_ACOUT22", - "DSP_1_ACOUT23", - "DSP_1_ACOUT24", - "DSP_1_ACOUT25", - "DSP_1_ACOUT26", - "DSP_1_ACOUT27", - "DSP_1_ACOUT28", - "DSP_1_ACOUT29", - "DSP_1_ACOUT3", - "DSP_1_ACOUT4", - "DSP_1_ACOUT5", - "DSP_1_ACOUT6", - "DSP_1_ACOUT7", - "DSP_1_ACOUT8", - "DSP_1_ACOUT9", - "DSP_1_ALUMODE0", - "DSP_1_ALUMODE1", - "DSP_1_ALUMODE2", - "DSP_1_ALUMODE3", - "DSP_1_B0", - "DSP_1_B1", - "DSP_1_B10", - "DSP_1_B11", - "DSP_1_B12", - "DSP_1_B13", - "DSP_1_B14", - "DSP_1_B15", - "DSP_1_B16", - "DSP_1_B17", - "DSP_1_B2", - "DSP_1_B3", - "DSP_1_B4", - "DSP_1_B5", - "DSP_1_B6", - "DSP_1_B7", - "DSP_1_B8", - "DSP_1_B9", - "DSP_1_BCIN0", - "DSP_1_BCIN1", - "DSP_1_BCIN10", - "DSP_1_BCIN11", - "DSP_1_BCIN12", - "DSP_1_BCIN13", - "DSP_1_BCIN14", - "DSP_1_BCIN15", - "DSP_1_BCIN16", - "DSP_1_BCIN17", - "DSP_1_BCIN2", - "DSP_1_BCIN3", - "DSP_1_BCIN4", - "DSP_1_BCIN5", - "DSP_1_BCIN6", - "DSP_1_BCIN7", - "DSP_1_BCIN8", - "DSP_1_BCIN9", - "DSP_1_BCOUT0", - "DSP_1_BCOUT1", - "DSP_1_BCOUT10", - "DSP_1_BCOUT11", - "DSP_1_BCOUT12", - "DSP_1_BCOUT13", - "DSP_1_BCOUT14", - "DSP_1_BCOUT15", - "DSP_1_BCOUT16", - "DSP_1_BCOUT17", - "DSP_1_BCOUT2", - "DSP_1_BCOUT3", - "DSP_1_BCOUT4", - "DSP_1_BCOUT5", - "DSP_1_BCOUT6", - "DSP_1_BCOUT7", - "DSP_1_BCOUT8", - "DSP_1_BCOUT9", - "DSP_1_C0", - "DSP_1_C1", - "DSP_1_C10", - "DSP_1_C11", - "DSP_1_C12", - "DSP_1_C13", - "DSP_1_C14", - "DSP_1_C15", - "DSP_1_C16", - "DSP_1_C17", - "DSP_1_C18", - "DSP_1_C19", - "DSP_1_C2", - "DSP_1_C20", - "DSP_1_C21", - "DSP_1_C22", - "DSP_1_C23", - "DSP_1_C24", - "DSP_1_C25", - "DSP_1_C26", - "DSP_1_C27", - "DSP_1_C28", - "DSP_1_C29", - "DSP_1_C3", - "DSP_1_C30", - "DSP_1_C31", - "DSP_1_C32", - "DSP_1_C33", - "DSP_1_C34", - "DSP_1_C35", - "DSP_1_C36", - "DSP_1_C37", - "DSP_1_C38", - "DSP_1_C39", - "DSP_1_C4", - "DSP_1_C40", - "DSP_1_C41", - "DSP_1_C42", - "DSP_1_C43", - "DSP_1_C44", - "DSP_1_C45", - "DSP_1_C46", - "DSP_1_C47", - "DSP_1_C5", - "DSP_1_C6", - "DSP_1_C7", - "DSP_1_C8", - "DSP_1_C9", - "DSP_1_CARRYCASCIN", - "DSP_1_CARRYCASCOUT", - "DSP_1_CARRYIN", - "DSP_1_CARRYINSEL0", - "DSP_1_CARRYINSEL1", - "DSP_1_CARRYINSEL2", - "DSP_1_CARRYOUT0", - "DSP_1_CARRYOUT1", - "DSP_1_CARRYOUT2", - "DSP_1_CARRYOUT3", - "DSP_1_CEA1", - "DSP_1_CEA2", - "DSP_1_CEAD", - "DSP_1_CEALUMODE", - "DSP_1_CEB1", - "DSP_1_CEB2", - "DSP_1_CEC", - "DSP_1_CECARRYIN", - "DSP_1_CECTRL", - "DSP_1_CED", - "DSP_1_CEINMODE", - "DSP_1_CEM", - "DSP_1_CEP", - "DSP_1_CLK", - "DSP_1_D0", - "DSP_1_D1", - "DSP_1_D10", - "DSP_1_D11", - "DSP_1_D12", - "DSP_1_D13", - "DSP_1_D14", - "DSP_1_D15", - "DSP_1_D16", - "DSP_1_D17", - "DSP_1_D18", - "DSP_1_D19", - "DSP_1_D2", - "DSP_1_D20", - "DSP_1_D21", - "DSP_1_D22", - "DSP_1_D23", - "DSP_1_D24", - "DSP_1_D3", - "DSP_1_D4", - "DSP_1_D5", - "DSP_1_D6", - "DSP_1_D7", - "DSP_1_D8", - "DSP_1_D9", - "DSP_1_INMODE0", - "DSP_1_INMODE1", - "DSP_1_INMODE2", - "DSP_1_INMODE3", - "DSP_1_INMODE4", - "DSP_1_MULTSIGNIN", - "DSP_1_MULTSIGNOUT", - "DSP_1_OPMODE0", - "DSP_1_OPMODE1", - "DSP_1_OPMODE2", - "DSP_1_OPMODE3", - "DSP_1_OPMODE4", - "DSP_1_OPMODE5", - "DSP_1_OPMODE6", - "DSP_1_OVERFLOW", - "DSP_1_P0", - "DSP_1_P1", - "DSP_1_P10", - "DSP_1_P11", - "DSP_1_P12", - "DSP_1_P13", - "DSP_1_P14", - "DSP_1_P15", - "DSP_1_P16", - "DSP_1_P17", - "DSP_1_P18", - "DSP_1_P19", - "DSP_1_P2", - "DSP_1_P20", - "DSP_1_P21", - "DSP_1_P22", - "DSP_1_P23", - "DSP_1_P24", - "DSP_1_P25", - "DSP_1_P26", - "DSP_1_P27", - "DSP_1_P28", - "DSP_1_P29", - "DSP_1_P3", - "DSP_1_P30", - "DSP_1_P31", - "DSP_1_P32", - "DSP_1_P33", - "DSP_1_P34", - "DSP_1_P35", - "DSP_1_P36", - "DSP_1_P37", - "DSP_1_P38", - "DSP_1_P39", - "DSP_1_P4", - "DSP_1_P40", - "DSP_1_P41", - "DSP_1_P42", - "DSP_1_P43", - "DSP_1_P44", - "DSP_1_P45", - "DSP_1_P46", - "DSP_1_P47", - "DSP_1_P5", - "DSP_1_P6", - "DSP_1_P7", - "DSP_1_P8", - "DSP_1_P9", - "DSP_1_PATTERNBDETECT", - "DSP_1_PATTERNDETECT", - "DSP_1_PCIN0", - "DSP_1_PCIN1", - "DSP_1_PCIN10", - "DSP_1_PCIN11", - "DSP_1_PCIN12", - "DSP_1_PCIN13", - "DSP_1_PCIN14", - "DSP_1_PCIN15", - "DSP_1_PCIN16", - "DSP_1_PCIN17", - "DSP_1_PCIN18", - "DSP_1_PCIN19", - "DSP_1_PCIN2", - "DSP_1_PCIN20", - "DSP_1_PCIN21", - "DSP_1_PCIN22", - "DSP_1_PCIN23", - "DSP_1_PCIN24", - "DSP_1_PCIN25", - "DSP_1_PCIN26", - "DSP_1_PCIN27", - "DSP_1_PCIN28", - "DSP_1_PCIN29", - "DSP_1_PCIN3", - "DSP_1_PCIN30", - "DSP_1_PCIN31", - "DSP_1_PCIN32", - "DSP_1_PCIN33", - "DSP_1_PCIN34", - "DSP_1_PCIN35", - "DSP_1_PCIN36", - "DSP_1_PCIN37", - "DSP_1_PCIN38", - "DSP_1_PCIN39", - "DSP_1_PCIN4", - "DSP_1_PCIN40", - "DSP_1_PCIN41", - "DSP_1_PCIN42", - "DSP_1_PCIN43", - "DSP_1_PCIN44", - "DSP_1_PCIN45", - "DSP_1_PCIN46", - "DSP_1_PCIN47", - "DSP_1_PCIN5", - "DSP_1_PCIN6", - "DSP_1_PCIN7", - "DSP_1_PCIN8", - "DSP_1_PCIN9", - "DSP_1_PCOUT0", - "DSP_1_PCOUT1", - "DSP_1_PCOUT10", - "DSP_1_PCOUT11", - "DSP_1_PCOUT12", - "DSP_1_PCOUT13", - "DSP_1_PCOUT14", - "DSP_1_PCOUT15", - "DSP_1_PCOUT16", - "DSP_1_PCOUT17", - "DSP_1_PCOUT18", - "DSP_1_PCOUT19", - "DSP_1_PCOUT2", - "DSP_1_PCOUT20", - "DSP_1_PCOUT21", - "DSP_1_PCOUT22", - "DSP_1_PCOUT23", - "DSP_1_PCOUT24", - "DSP_1_PCOUT25", - "DSP_1_PCOUT26", - "DSP_1_PCOUT27", - "DSP_1_PCOUT28", - "DSP_1_PCOUT29", - "DSP_1_PCOUT3", - "DSP_1_PCOUT30", - "DSP_1_PCOUT31", - "DSP_1_PCOUT32", - "DSP_1_PCOUT33", - "DSP_1_PCOUT34", - "DSP_1_PCOUT35", - "DSP_1_PCOUT36", - "DSP_1_PCOUT37", - "DSP_1_PCOUT38", - "DSP_1_PCOUT39", - "DSP_1_PCOUT4", - "DSP_1_PCOUT40", - "DSP_1_PCOUT41", - "DSP_1_PCOUT42", - "DSP_1_PCOUT43", - "DSP_1_PCOUT44", - "DSP_1_PCOUT45", - "DSP_1_PCOUT46", - "DSP_1_PCOUT47", - "DSP_1_PCOUT5", - "DSP_1_PCOUT6", - "DSP_1_PCOUT7", - "DSP_1_PCOUT8", - "DSP_1_PCOUT9", - "DSP_1_RSTA", - "DSP_1_RSTALLCARRYIN", - "DSP_1_RSTALUMODE", - "DSP_1_RSTB", - "DSP_1_RSTC", - "DSP_1_RSTCTRL", - "DSP_1_RSTD", - "DSP_1_RSTINMODE", - "DSP_1_RSTM", - "DSP_1_RSTP", - "DSP_1_UNDERFLOW", - "DSP_ACOUT0", - "DSP_ACOUT1", - "DSP_ACOUT10", - "DSP_ACOUT11", - "DSP_ACOUT12", - "DSP_ACOUT13", - "DSP_ACOUT14", - "DSP_ACOUT15", - "DSP_ACOUT16", - "DSP_ACOUT17", - "DSP_ACOUT18", - "DSP_ACOUT19", - "DSP_ACOUT2", - "DSP_ACOUT20", - "DSP_ACOUT21", - "DSP_ACOUT22", - "DSP_ACOUT23", - "DSP_ACOUT24", - "DSP_ACOUT25", - "DSP_ACOUT26", - "DSP_ACOUT27", - "DSP_ACOUT28", - "DSP_ACOUT29", - "DSP_ACOUT3", - "DSP_ACOUT4", - "DSP_ACOUT5", - "DSP_ACOUT6", - "DSP_ACOUT7", - "DSP_ACOUT8", - "DSP_ACOUT9", - "DSP_BCOUT0", - "DSP_BCOUT1", - "DSP_BCOUT10", - "DSP_BCOUT11", - "DSP_BCOUT12", - "DSP_BCOUT13", - "DSP_BCOUT14", - "DSP_BCOUT15", - "DSP_BCOUT16", - "DSP_BCOUT17", - "DSP_BCOUT2", - "DSP_BCOUT3", - "DSP_BCOUT4", - "DSP_BCOUT5", - "DSP_BCOUT6", - "DSP_BCOUT7", - "DSP_BCOUT8", - "DSP_BCOUT9", - "DSP_BLOCK_OUTS_B0_0", - "DSP_BLOCK_OUTS_B0_1", - "DSP_BLOCK_OUTS_B0_2", - "DSP_BLOCK_OUTS_B0_3", - "DSP_BLOCK_OUTS_B0_4", - "DSP_BLOCK_OUTS_B1_0", - "DSP_BLOCK_OUTS_B1_1", - "DSP_BLOCK_OUTS_B1_2", - "DSP_BLOCK_OUTS_B1_3", - "DSP_BLOCK_OUTS_B1_4", - "DSP_BLOCK_OUTS_B2_0", - "DSP_BLOCK_OUTS_B2_1", - "DSP_BLOCK_OUTS_B2_2", - "DSP_BLOCK_OUTS_B2_3", - "DSP_BLOCK_OUTS_B2_4", - "DSP_BLOCK_OUTS_B3_0", - "DSP_BLOCK_OUTS_B3_1", - "DSP_BLOCK_OUTS_B3_2", - "DSP_BLOCK_OUTS_B3_3", - "DSP_BLOCK_OUTS_B3_4", - "DSP_BYP0_0", - "DSP_BYP0_1", - "DSP_BYP0_2", - "DSP_BYP0_3", - "DSP_BYP0_4", - "DSP_BYP1_0", - "DSP_BYP1_1", - "DSP_BYP1_2", - "DSP_BYP1_3", - "DSP_BYP1_4", - "DSP_BYP2_0", - "DSP_BYP2_1", - "DSP_BYP2_2", - "DSP_BYP2_3", - "DSP_BYP2_4", - "DSP_BYP3_0", - "DSP_BYP3_1", - "DSP_BYP3_2", - "DSP_BYP3_3", - "DSP_BYP3_4", - "DSP_BYP4_0", - "DSP_BYP4_1", - "DSP_BYP4_2", - "DSP_BYP4_3", - "DSP_BYP4_4", - "DSP_BYP5_0", - "DSP_BYP5_1", - "DSP_BYP5_2", - "DSP_BYP5_3", - "DSP_BYP5_4", - "DSP_BYP6_0", - "DSP_BYP6_1", - "DSP_BYP6_2", - "DSP_BYP6_3", - "DSP_BYP6_4", - "DSP_BYP7_0", - "DSP_BYP7_1", - "DSP_BYP7_2", - "DSP_BYP7_3", - "DSP_BYP7_4", - "DSP_CARRYCASCOUT", - "DSP_CLK0_0", - "DSP_CLK0_1", - "DSP_CLK0_2", - "DSP_CLK0_3", - "DSP_CLK0_4", - "DSP_CLK1_0", - "DSP_CLK1_1", - "DSP_CLK1_2", - "DSP_CLK1_3", - "DSP_CLK1_4", - "DSP_CTRL0_0", - "DSP_CTRL0_1", - "DSP_CTRL0_2", - "DSP_CTRL0_3", - "DSP_CTRL0_4", - "DSP_CTRL1_0", - "DSP_CTRL1_1", - "DSP_CTRL1_2", - "DSP_CTRL1_3", - "DSP_CTRL1_4", - "DSP_EE2A0_0", - "DSP_EE2A0_1", - "DSP_EE2A0_2", - "DSP_EE2A0_3", - "DSP_EE2A0_4", - "DSP_EE2A1_0", - "DSP_EE2A1_1", - "DSP_EE2A1_2", - "DSP_EE2A1_3", - "DSP_EE2A1_4", - "DSP_EE2A2_0", - "DSP_EE2A2_1", - "DSP_EE2A2_2", - "DSP_EE2A2_3", - "DSP_EE2A2_4", - "DSP_EE2A3_0", - "DSP_EE2A3_1", - "DSP_EE2A3_2", - "DSP_EE2A3_3", - "DSP_EE2A3_4", - "DSP_EE2BEG0_0", - "DSP_EE2BEG0_1", - "DSP_EE2BEG0_2", - "DSP_EE2BEG0_3", - "DSP_EE2BEG0_4", - "DSP_EE2BEG1_0", - "DSP_EE2BEG1_1", - "DSP_EE2BEG1_2", - "DSP_EE2BEG1_3", - "DSP_EE2BEG1_4", - "DSP_EE2BEG2_0", - "DSP_EE2BEG2_1", - "DSP_EE2BEG2_2", - "DSP_EE2BEG2_3", - "DSP_EE2BEG2_4", - "DSP_EE2BEG3_0", - "DSP_EE2BEG3_1", - "DSP_EE2BEG3_2", - "DSP_EE2BEG3_3", - "DSP_EE2BEG3_4", - "DSP_EE4A0_0", - "DSP_EE4A0_1", - "DSP_EE4A0_2", - "DSP_EE4A0_3", - "DSP_EE4A0_4", - "DSP_EE4A1_0", - "DSP_EE4A1_1", - "DSP_EE4A1_2", - "DSP_EE4A1_3", - "DSP_EE4A1_4", - "DSP_EE4A2_0", - "DSP_EE4A2_1", - "DSP_EE4A2_2", - "DSP_EE4A2_3", - "DSP_EE4A2_4", - "DSP_EE4A3_0", - "DSP_EE4A3_1", - "DSP_EE4A3_2", - "DSP_EE4A3_3", - "DSP_EE4A3_4", - "DSP_EE4B0_0", - "DSP_EE4B0_1", - "DSP_EE4B0_2", - "DSP_EE4B0_3", - "DSP_EE4B0_4", - "DSP_EE4B1_0", - "DSP_EE4B1_1", - "DSP_EE4B1_2", - "DSP_EE4B1_3", - "DSP_EE4B1_4", - "DSP_EE4B2_0", - "DSP_EE4B2_1", - "DSP_EE4B2_2", - "DSP_EE4B2_3", - "DSP_EE4B2_4", - "DSP_EE4B3_0", - "DSP_EE4B3_1", - "DSP_EE4B3_2", - "DSP_EE4B3_3", - "DSP_EE4B3_4", - "DSP_EE4BEG0_0", - "DSP_EE4BEG0_1", - "DSP_EE4BEG0_2", - "DSP_EE4BEG0_3", - "DSP_EE4BEG0_4", - "DSP_EE4BEG1_0", - "DSP_EE4BEG1_1", - "DSP_EE4BEG1_2", - "DSP_EE4BEG1_3", - "DSP_EE4BEG1_4", - "DSP_EE4BEG2_0", - "DSP_EE4BEG2_1", - "DSP_EE4BEG2_2", - "DSP_EE4BEG2_3", - "DSP_EE4BEG2_4", - "DSP_EE4BEG3_0", - "DSP_EE4BEG3_1", - "DSP_EE4BEG3_2", - "DSP_EE4BEG3_3", - "DSP_EE4BEG3_4", - "DSP_EE4C0_0", - "DSP_EE4C0_1", - "DSP_EE4C0_2", - "DSP_EE4C0_3", - "DSP_EE4C0_4", - "DSP_EE4C1_0", - "DSP_EE4C1_1", - "DSP_EE4C1_2", - "DSP_EE4C1_3", - "DSP_EE4C1_4", - "DSP_EE4C2_0", - "DSP_EE4C2_1", - "DSP_EE4C2_2", - "DSP_EE4C2_3", - "DSP_EE4C2_4", - "DSP_EE4C3_0", - "DSP_EE4C3_1", - "DSP_EE4C3_2", - "DSP_EE4C3_3", - "DSP_EE4C3_4", - "DSP_EL1BEG0_0", - "DSP_EL1BEG0_1", - "DSP_EL1BEG0_2", - "DSP_EL1BEG0_3", - "DSP_EL1BEG0_4", - "DSP_EL1BEG1_0", - "DSP_EL1BEG1_1", - "DSP_EL1BEG1_2", - "DSP_EL1BEG1_3", - "DSP_EL1BEG1_4", - "DSP_EL1BEG2_0", - "DSP_EL1BEG2_1", - "DSP_EL1BEG2_2", - "DSP_EL1BEG2_3", - "DSP_EL1BEG2_4", - "DSP_EL1BEG3_0", - "DSP_EL1BEG3_1", - "DSP_EL1BEG3_2", - "DSP_EL1BEG3_3", - "DSP_EL1BEG3_4", - "DSP_ER1BEG0_0", - "DSP_ER1BEG0_1", - "DSP_ER1BEG0_2", - "DSP_ER1BEG0_3", - "DSP_ER1BEG0_4", - "DSP_ER1BEG1_0", - "DSP_ER1BEG1_1", - "DSP_ER1BEG1_2", - "DSP_ER1BEG1_3", - "DSP_ER1BEG1_4", - "DSP_ER1BEG2_0", - "DSP_ER1BEG2_1", - "DSP_ER1BEG2_2", - "DSP_ER1BEG2_3", - "DSP_ER1BEG2_4", - "DSP_ER1BEG3_0", - "DSP_ER1BEG3_1", - "DSP_ER1BEG3_2", - "DSP_ER1BEG3_3", - "DSP_ER1BEG3_4", - "DSP_FAN0_0", - "DSP_FAN0_1", - "DSP_FAN0_2", - "DSP_FAN0_3", - "DSP_FAN0_4", - "DSP_FAN1_0", - "DSP_FAN1_1", - "DSP_FAN1_2", - "DSP_FAN1_3", - "DSP_FAN1_4", - "DSP_FAN2_0", - "DSP_FAN2_1", - "DSP_FAN2_2", - "DSP_FAN2_3", - "DSP_FAN2_4", - "DSP_FAN3_0", - "DSP_FAN3_1", - "DSP_FAN3_2", - "DSP_FAN3_3", - "DSP_FAN3_4", - "DSP_FAN4_0", - "DSP_FAN4_1", - "DSP_FAN4_2", - "DSP_FAN4_3", - "DSP_FAN4_4", - "DSP_FAN5_0", - "DSP_FAN5_1", - "DSP_FAN5_2", - "DSP_FAN5_3", - "DSP_FAN5_4", - "DSP_FAN6_0", - "DSP_FAN6_1", - "DSP_FAN6_2", - "DSP_FAN6_3", - "DSP_FAN6_4", - "DSP_FAN7_0", - "DSP_FAN7_1", - "DSP_FAN7_2", - "DSP_FAN7_3", - "DSP_FAN7_4", - "DSP_GND_R", - "DSP_IMUX0_0", - "DSP_IMUX0_1", - "DSP_IMUX0_2", - "DSP_IMUX0_3", - "DSP_IMUX0_4", - "DSP_IMUX10_0", - "DSP_IMUX10_1", - "DSP_IMUX10_2", - "DSP_IMUX10_3", - "DSP_IMUX10_4", - "DSP_IMUX11_0", - "DSP_IMUX11_1", - "DSP_IMUX11_2", - "DSP_IMUX11_3", - "DSP_IMUX11_4", - "DSP_IMUX12_0", - "DSP_IMUX12_1", - "DSP_IMUX12_2", - "DSP_IMUX12_3", - "DSP_IMUX12_4", - "DSP_IMUX13_0", - "DSP_IMUX13_1", - "DSP_IMUX13_2", - "DSP_IMUX13_3", - "DSP_IMUX13_4", - "DSP_IMUX14_0", - "DSP_IMUX14_1", - "DSP_IMUX14_2", - "DSP_IMUX14_3", - "DSP_IMUX14_4", - "DSP_IMUX15_0", - "DSP_IMUX15_1", - "DSP_IMUX15_2", - "DSP_IMUX15_3", - "DSP_IMUX15_4", - "DSP_IMUX16_0", - "DSP_IMUX16_1", - "DSP_IMUX16_2", - "DSP_IMUX16_3", - "DSP_IMUX16_4", - "DSP_IMUX17_0", - "DSP_IMUX17_1", - "DSP_IMUX17_2", - "DSP_IMUX17_3", - "DSP_IMUX17_4", - "DSP_IMUX18_0", - "DSP_IMUX18_1", - "DSP_IMUX18_2", - "DSP_IMUX18_3", - "DSP_IMUX18_4", - "DSP_IMUX19_0", - "DSP_IMUX19_1", - "DSP_IMUX19_2", - "DSP_IMUX19_3", - "DSP_IMUX19_4", - "DSP_IMUX1_0", - "DSP_IMUX1_1", - "DSP_IMUX1_2", - "DSP_IMUX1_3", - "DSP_IMUX1_4", - "DSP_IMUX20_0", - "DSP_IMUX20_1", - "DSP_IMUX20_2", - "DSP_IMUX20_3", - "DSP_IMUX20_4", - "DSP_IMUX21_0", - "DSP_IMUX21_1", - "DSP_IMUX21_2", - "DSP_IMUX21_3", - "DSP_IMUX21_4", - "DSP_IMUX22_0", - "DSP_IMUX22_1", - "DSP_IMUX22_2", - "DSP_IMUX22_3", - "DSP_IMUX22_4", - "DSP_IMUX23_0", - "DSP_IMUX23_1", - "DSP_IMUX23_2", - "DSP_IMUX23_3", - "DSP_IMUX23_4", - "DSP_IMUX24_0", - "DSP_IMUX24_1", - "DSP_IMUX24_2", - "DSP_IMUX24_3", - "DSP_IMUX24_4", - "DSP_IMUX25_0", - "DSP_IMUX25_1", - "DSP_IMUX25_2", - "DSP_IMUX25_3", - "DSP_IMUX25_4", - "DSP_IMUX26_0", - "DSP_IMUX26_1", - "DSP_IMUX26_2", - "DSP_IMUX26_3", - "DSP_IMUX26_4", - "DSP_IMUX27_0", - "DSP_IMUX27_1", - "DSP_IMUX27_2", - "DSP_IMUX27_3", - "DSP_IMUX27_4", - "DSP_IMUX28_0", - "DSP_IMUX28_1", - "DSP_IMUX28_2", - "DSP_IMUX28_3", - "DSP_IMUX28_4", - "DSP_IMUX29_0", - "DSP_IMUX29_1", - "DSP_IMUX29_2", - "DSP_IMUX29_3", - "DSP_IMUX29_4", - "DSP_IMUX2_0", - "DSP_IMUX2_1", - "DSP_IMUX2_2", - "DSP_IMUX2_3", - "DSP_IMUX2_4", - "DSP_IMUX30_0", - "DSP_IMUX30_1", - "DSP_IMUX30_2", - "DSP_IMUX30_3", - "DSP_IMUX30_4", - "DSP_IMUX31_0", - "DSP_IMUX31_1", - "DSP_IMUX31_2", - "DSP_IMUX31_3", - "DSP_IMUX31_4", - "DSP_IMUX32_0", - "DSP_IMUX32_1", - "DSP_IMUX32_2", - "DSP_IMUX32_3", - "DSP_IMUX32_4", - "DSP_IMUX33_0", - "DSP_IMUX33_1", - "DSP_IMUX33_2", - "DSP_IMUX33_3", - "DSP_IMUX33_4", - "DSP_IMUX34_0", - "DSP_IMUX34_1", - "DSP_IMUX34_2", - "DSP_IMUX34_3", - "DSP_IMUX34_4", - "DSP_IMUX35_0", - "DSP_IMUX35_1", - "DSP_IMUX35_2", - "DSP_IMUX35_3", - "DSP_IMUX35_4", - "DSP_IMUX36_0", - "DSP_IMUX36_1", - "DSP_IMUX36_2", - "DSP_IMUX36_3", - "DSP_IMUX36_4", - "DSP_IMUX37_0", - "DSP_IMUX37_1", - "DSP_IMUX37_2", - "DSP_IMUX37_3", - "DSP_IMUX37_4", - "DSP_IMUX38_0", - "DSP_IMUX38_1", - "DSP_IMUX38_2", - "DSP_IMUX38_3", - "DSP_IMUX38_4", - "DSP_IMUX39_0", - "DSP_IMUX39_1", - "DSP_IMUX39_2", - "DSP_IMUX39_3", - "DSP_IMUX39_4", - "DSP_IMUX3_0", - "DSP_IMUX3_1", - "DSP_IMUX3_2", - "DSP_IMUX3_3", - "DSP_IMUX3_4", - "DSP_IMUX40_0", - "DSP_IMUX40_1", - "DSP_IMUX40_2", - "DSP_IMUX40_3", - "DSP_IMUX40_4", - "DSP_IMUX41_0", - "DSP_IMUX41_1", - "DSP_IMUX41_2", - "DSP_IMUX41_3", - "DSP_IMUX41_4", - "DSP_IMUX42_0", - "DSP_IMUX42_1", - "DSP_IMUX42_2", - "DSP_IMUX42_3", - "DSP_IMUX42_4", - "DSP_IMUX43_0", - "DSP_IMUX43_1", - "DSP_IMUX43_2", - "DSP_IMUX43_3", - "DSP_IMUX43_4", - "DSP_IMUX44_0", - "DSP_IMUX44_1", - "DSP_IMUX44_2", - "DSP_IMUX44_3", - "DSP_IMUX44_4", - "DSP_IMUX45_0", - "DSP_IMUX45_1", - "DSP_IMUX45_2", - "DSP_IMUX45_3", - "DSP_IMUX45_4", - "DSP_IMUX46_0", - "DSP_IMUX46_1", - "DSP_IMUX46_2", - "DSP_IMUX46_3", - "DSP_IMUX46_4", - "DSP_IMUX47_0", - "DSP_IMUX47_1", - "DSP_IMUX47_2", - "DSP_IMUX47_3", - "DSP_IMUX47_4", - "DSP_IMUX4_0", - "DSP_IMUX4_1", - "DSP_IMUX4_2", - "DSP_IMUX4_3", - "DSP_IMUX4_4", - "DSP_IMUX5_0", - "DSP_IMUX5_1", - "DSP_IMUX5_2", - "DSP_IMUX5_3", - "DSP_IMUX5_4", - "DSP_IMUX6_0", - "DSP_IMUX6_1", - "DSP_IMUX6_2", - "DSP_IMUX6_3", - "DSP_IMUX6_4", - "DSP_IMUX7_0", - "DSP_IMUX7_1", - "DSP_IMUX7_2", - "DSP_IMUX7_3", - "DSP_IMUX7_4", - "DSP_IMUX8_0", - "DSP_IMUX8_1", - "DSP_IMUX8_2", - "DSP_IMUX8_3", - "DSP_IMUX8_4", - "DSP_IMUX9_0", - "DSP_IMUX9_1", - "DSP_IMUX9_2", - "DSP_IMUX9_3", - "DSP_IMUX9_4", - "DSP_LH10_0", - "DSP_LH10_1", - "DSP_LH10_2", - "DSP_LH10_3", - "DSP_LH10_4", - "DSP_LH11_0", - "DSP_LH11_1", - "DSP_LH11_2", - "DSP_LH11_3", - "DSP_LH11_4", - "DSP_LH12_0", - "DSP_LH12_1", - "DSP_LH12_2", - "DSP_LH12_3", - "DSP_LH12_4", - "DSP_LH1_0", - "DSP_LH1_1", - "DSP_LH1_2", - "DSP_LH1_3", - "DSP_LH1_4", - "DSP_LH2_0", - "DSP_LH2_1", - "DSP_LH2_2", - "DSP_LH2_3", - "DSP_LH2_4", - "DSP_LH3_0", - "DSP_LH3_1", - "DSP_LH3_2", - "DSP_LH3_3", - "DSP_LH3_4", - "DSP_LH4_0", - "DSP_LH4_1", - "DSP_LH4_2", - "DSP_LH4_3", - "DSP_LH4_4", - "DSP_LH5_0", - "DSP_LH5_1", - "DSP_LH5_2", - "DSP_LH5_3", - "DSP_LH5_4", - "DSP_LH6_0", - "DSP_LH6_1", - "DSP_LH6_2", - "DSP_LH6_3", - "DSP_LH6_4", - "DSP_LH7_0", - "DSP_LH7_1", - "DSP_LH7_2", - "DSP_LH7_3", - "DSP_LH7_4", - "DSP_LH8_0", - "DSP_LH8_1", - "DSP_LH8_2", - "DSP_LH8_3", - "DSP_LH8_4", - "DSP_LH9_0", - "DSP_LH9_1", - "DSP_LH9_2", - "DSP_LH9_3", - "DSP_LH9_4", - "DSP_LOGIC_OUTS_B0_0", - "DSP_LOGIC_OUTS_B0_1", - "DSP_LOGIC_OUTS_B0_2", - "DSP_LOGIC_OUTS_B0_3", - "DSP_LOGIC_OUTS_B0_4", - "DSP_LOGIC_OUTS_B10_0", - "DSP_LOGIC_OUTS_B10_1", - "DSP_LOGIC_OUTS_B10_2", - "DSP_LOGIC_OUTS_B10_3", - "DSP_LOGIC_OUTS_B10_4", - "DSP_LOGIC_OUTS_B11_0", - "DSP_LOGIC_OUTS_B11_1", - "DSP_LOGIC_OUTS_B11_2", - "DSP_LOGIC_OUTS_B11_3", - "DSP_LOGIC_OUTS_B11_4", - "DSP_LOGIC_OUTS_B12_0", - "DSP_LOGIC_OUTS_B12_1", - "DSP_LOGIC_OUTS_B12_2", - "DSP_LOGIC_OUTS_B12_3", - "DSP_LOGIC_OUTS_B12_4", - "DSP_LOGIC_OUTS_B13_0", - "DSP_LOGIC_OUTS_B13_1", - "DSP_LOGIC_OUTS_B13_2", - "DSP_LOGIC_OUTS_B13_3", - "DSP_LOGIC_OUTS_B13_4", - "DSP_LOGIC_OUTS_B14_0", - "DSP_LOGIC_OUTS_B14_1", - "DSP_LOGIC_OUTS_B14_2", - "DSP_LOGIC_OUTS_B14_3", - "DSP_LOGIC_OUTS_B14_4", - "DSP_LOGIC_OUTS_B15_0", - "DSP_LOGIC_OUTS_B15_1", - "DSP_LOGIC_OUTS_B15_2", - "DSP_LOGIC_OUTS_B15_3", - "DSP_LOGIC_OUTS_B15_4", - "DSP_LOGIC_OUTS_B16_0", - "DSP_LOGIC_OUTS_B16_1", - "DSP_LOGIC_OUTS_B16_2", - "DSP_LOGIC_OUTS_B16_3", - "DSP_LOGIC_OUTS_B16_4", - "DSP_LOGIC_OUTS_B17_0", - "DSP_LOGIC_OUTS_B17_1", - "DSP_LOGIC_OUTS_B17_2", - "DSP_LOGIC_OUTS_B17_3", - "DSP_LOGIC_OUTS_B17_4", - "DSP_LOGIC_OUTS_B18_0", - "DSP_LOGIC_OUTS_B18_1", - "DSP_LOGIC_OUTS_B18_2", - "DSP_LOGIC_OUTS_B18_3", - "DSP_LOGIC_OUTS_B18_4", - "DSP_LOGIC_OUTS_B19_0", - "DSP_LOGIC_OUTS_B19_1", - "DSP_LOGIC_OUTS_B19_2", - "DSP_LOGIC_OUTS_B19_3", - "DSP_LOGIC_OUTS_B19_4", - "DSP_LOGIC_OUTS_B1_0", - "DSP_LOGIC_OUTS_B1_1", - "DSP_LOGIC_OUTS_B1_2", - "DSP_LOGIC_OUTS_B1_3", - "DSP_LOGIC_OUTS_B1_4", - "DSP_LOGIC_OUTS_B20_0", - "DSP_LOGIC_OUTS_B20_1", - "DSP_LOGIC_OUTS_B20_2", - "DSP_LOGIC_OUTS_B20_3", - "DSP_LOGIC_OUTS_B20_4", - "DSP_LOGIC_OUTS_B21_0", - "DSP_LOGIC_OUTS_B21_1", - "DSP_LOGIC_OUTS_B21_2", - "DSP_LOGIC_OUTS_B21_3", - "DSP_LOGIC_OUTS_B21_4", - "DSP_LOGIC_OUTS_B22_0", - "DSP_LOGIC_OUTS_B22_1", - "DSP_LOGIC_OUTS_B22_2", - "DSP_LOGIC_OUTS_B22_3", - "DSP_LOGIC_OUTS_B22_4", - "DSP_LOGIC_OUTS_B23_0", - "DSP_LOGIC_OUTS_B23_1", - "DSP_LOGIC_OUTS_B23_2", - "DSP_LOGIC_OUTS_B23_3", - "DSP_LOGIC_OUTS_B23_4", - "DSP_LOGIC_OUTS_B2_0", - "DSP_LOGIC_OUTS_B2_1", - "DSP_LOGIC_OUTS_B2_2", - "DSP_LOGIC_OUTS_B2_3", - "DSP_LOGIC_OUTS_B2_4", - "DSP_LOGIC_OUTS_B3_0", - "DSP_LOGIC_OUTS_B3_1", - "DSP_LOGIC_OUTS_B3_2", - "DSP_LOGIC_OUTS_B3_3", - "DSP_LOGIC_OUTS_B3_4", - "DSP_LOGIC_OUTS_B4_0", - "DSP_LOGIC_OUTS_B4_1", - "DSP_LOGIC_OUTS_B4_2", - "DSP_LOGIC_OUTS_B4_3", - "DSP_LOGIC_OUTS_B4_4", - "DSP_LOGIC_OUTS_B5_0", - "DSP_LOGIC_OUTS_B5_1", - "DSP_LOGIC_OUTS_B5_2", - "DSP_LOGIC_OUTS_B5_3", - "DSP_LOGIC_OUTS_B5_4", - "DSP_LOGIC_OUTS_B6_0", - "DSP_LOGIC_OUTS_B6_1", - "DSP_LOGIC_OUTS_B6_2", - "DSP_LOGIC_OUTS_B6_3", - "DSP_LOGIC_OUTS_B6_4", - "DSP_LOGIC_OUTS_B7_0", - "DSP_LOGIC_OUTS_B7_1", - "DSP_LOGIC_OUTS_B7_2", - "DSP_LOGIC_OUTS_B7_3", - "DSP_LOGIC_OUTS_B7_4", - "DSP_LOGIC_OUTS_B8_0", - "DSP_LOGIC_OUTS_B8_1", - "DSP_LOGIC_OUTS_B8_2", - "DSP_LOGIC_OUTS_B8_3", - "DSP_LOGIC_OUTS_B8_4", - "DSP_LOGIC_OUTS_B9_0", - "DSP_LOGIC_OUTS_B9_1", - "DSP_LOGIC_OUTS_B9_2", - "DSP_LOGIC_OUTS_B9_3", - "DSP_LOGIC_OUTS_B9_4", - "DSP_MONITOR_N_0", - "DSP_MONITOR_N_1", - "DSP_MONITOR_N_2", - "DSP_MONITOR_N_3", - "DSP_MONITOR_N_4", - "DSP_MONITOR_P_0", - "DSP_MONITOR_P_1", - "DSP_MONITOR_P_2", - "DSP_MONITOR_P_3", - "DSP_MONITOR_P_4", - "DSP_MULTSIGNOUT", - "DSP_NE2A0_0", - "DSP_NE2A0_1", - "DSP_NE2A0_2", - "DSP_NE2A0_3", - "DSP_NE2A0_4", - "DSP_NE2A1_0", - "DSP_NE2A1_1", - "DSP_NE2A1_2", - "DSP_NE2A1_3", - "DSP_NE2A1_4", - "DSP_NE2A2_0", - "DSP_NE2A2_1", - "DSP_NE2A2_2", - "DSP_NE2A2_3", - "DSP_NE2A2_4", - "DSP_NE2A3_0", - "DSP_NE2A3_1", - "DSP_NE2A3_2", - "DSP_NE2A3_3", - "DSP_NE2A3_4", - "DSP_NE4BEG0_0", - "DSP_NE4BEG0_1", - "DSP_NE4BEG0_2", - "DSP_NE4BEG0_3", - "DSP_NE4BEG0_4", - "DSP_NE4BEG1_0", - "DSP_NE4BEG1_1", - "DSP_NE4BEG1_2", - "DSP_NE4BEG1_3", - "DSP_NE4BEG1_4", - "DSP_NE4BEG2_0", - "DSP_NE4BEG2_1", - "DSP_NE4BEG2_2", - "DSP_NE4BEG2_3", - "DSP_NE4BEG2_4", - "DSP_NE4BEG3_0", - "DSP_NE4BEG3_1", - "DSP_NE4BEG3_2", - "DSP_NE4BEG3_3", - "DSP_NE4BEG3_4", - "DSP_NE4C0_0", - "DSP_NE4C0_1", - "DSP_NE4C0_2", - "DSP_NE4C0_3", - "DSP_NE4C0_4", - "DSP_NE4C1_0", - "DSP_NE4C1_1", - "DSP_NE4C1_2", - "DSP_NE4C1_3", - "DSP_NE4C1_4", - "DSP_NE4C2_0", - "DSP_NE4C2_1", - "DSP_NE4C2_2", - "DSP_NE4C2_3", - "DSP_NE4C2_4", - "DSP_NE4C3_0", - "DSP_NE4C3_1", - "DSP_NE4C3_2", - "DSP_NE4C3_3", - "DSP_NE4C3_4", - "DSP_NW2A0_0", - "DSP_NW2A0_1", - "DSP_NW2A0_2", - "DSP_NW2A0_3", - "DSP_NW2A0_4", - "DSP_NW2A1_0", - "DSP_NW2A1_1", - "DSP_NW2A1_2", - "DSP_NW2A1_3", - "DSP_NW2A1_4", - "DSP_NW2A2_0", - "DSP_NW2A2_1", - "DSP_NW2A2_2", - "DSP_NW2A2_3", - "DSP_NW2A2_4", - "DSP_NW2A3_0", - "DSP_NW2A3_1", - "DSP_NW2A3_2", - "DSP_NW2A3_3", - "DSP_NW2A3_4", - "DSP_NW4A0_0", - "DSP_NW4A0_1", - "DSP_NW4A0_2", - "DSP_NW4A0_3", - "DSP_NW4A0_4", - "DSP_NW4A1_0", - "DSP_NW4A1_1", - "DSP_NW4A1_2", - "DSP_NW4A1_3", - "DSP_NW4A1_4", - "DSP_NW4A2_0", - "DSP_NW4A2_1", - "DSP_NW4A2_2", - "DSP_NW4A2_3", - "DSP_NW4A2_4", - "DSP_NW4A3_0", - "DSP_NW4A3_1", - "DSP_NW4A3_2", - "DSP_NW4A3_3", - "DSP_NW4A3_4", - "DSP_NW4END0_0", - "DSP_NW4END0_1", - "DSP_NW4END0_2", - "DSP_NW4END0_3", - "DSP_NW4END0_4", - "DSP_NW4END1_0", - "DSP_NW4END1_1", - "DSP_NW4END1_2", - "DSP_NW4END1_3", - "DSP_NW4END1_4", - "DSP_NW4END2_0", - "DSP_NW4END2_1", - "DSP_NW4END2_2", - "DSP_NW4END2_3", - "DSP_NW4END2_4", - "DSP_NW4END3_0", - "DSP_NW4END3_1", - "DSP_NW4END3_2", - "DSP_NW4END3_3", - "DSP_NW4END3_4", - "DSP_PCOUT0", - "DSP_PCOUT1", - "DSP_PCOUT10", - "DSP_PCOUT11", - "DSP_PCOUT12", - "DSP_PCOUT13", - "DSP_PCOUT14", - "DSP_PCOUT15", - "DSP_PCOUT16", - "DSP_PCOUT17", - "DSP_PCOUT18", - "DSP_PCOUT19", - "DSP_PCOUT2", - "DSP_PCOUT20", - "DSP_PCOUT21", - "DSP_PCOUT22", - "DSP_PCOUT23", - "DSP_PCOUT24", - "DSP_PCOUT25", - "DSP_PCOUT26", - "DSP_PCOUT27", - "DSP_PCOUT28", - "DSP_PCOUT29", - "DSP_PCOUT3", - "DSP_PCOUT30", - "DSP_PCOUT31", - "DSP_PCOUT32", - "DSP_PCOUT33", - "DSP_PCOUT34", - "DSP_PCOUT35", - "DSP_PCOUT36", - "DSP_PCOUT37", - "DSP_PCOUT38", - "DSP_PCOUT39", - "DSP_PCOUT4", - "DSP_PCOUT40", - "DSP_PCOUT41", - "DSP_PCOUT42", - "DSP_PCOUT43", - "DSP_PCOUT44", - "DSP_PCOUT45", - "DSP_PCOUT46", - "DSP_PCOUT47", - "DSP_PCOUT5", - "DSP_PCOUT6", - "DSP_PCOUT7", - "DSP_PCOUT8", - "DSP_PCOUT9", - "DSP_SE2A0_0", - "DSP_SE2A0_1", - "DSP_SE2A0_2", - "DSP_SE2A0_3", - "DSP_SE2A0_4", - "DSP_SE2A1_0", - "DSP_SE2A1_1", - "DSP_SE2A1_2", - "DSP_SE2A1_3", - "DSP_SE2A1_4", - "DSP_SE2A2_0", - "DSP_SE2A2_1", - "DSP_SE2A2_2", - "DSP_SE2A2_3", - "DSP_SE2A2_4", - "DSP_SE2A3_0", - "DSP_SE2A3_1", - "DSP_SE2A3_2", - "DSP_SE2A3_3", - "DSP_SE2A3_4", - "DSP_SE4BEG0_0", - "DSP_SE4BEG0_1", - "DSP_SE4BEG0_2", - "DSP_SE4BEG0_3", - "DSP_SE4BEG0_4", - "DSP_SE4BEG1_0", - "DSP_SE4BEG1_1", - "DSP_SE4BEG1_2", - "DSP_SE4BEG1_3", - "DSP_SE4BEG1_4", - "DSP_SE4BEG2_0", - "DSP_SE4BEG2_1", - "DSP_SE4BEG2_2", - "DSP_SE4BEG2_3", - "DSP_SE4BEG2_4", - "DSP_SE4BEG3_0", - "DSP_SE4BEG3_1", - "DSP_SE4BEG3_2", - "DSP_SE4BEG3_3", - "DSP_SE4BEG3_4", - "DSP_SE4C0_0", - "DSP_SE4C0_1", - "DSP_SE4C0_2", - "DSP_SE4C0_3", - "DSP_SE4C0_4", - "DSP_SE4C1_0", - "DSP_SE4C1_1", - "DSP_SE4C1_2", - "DSP_SE4C1_3", - "DSP_SE4C1_4", - "DSP_SE4C2_0", - "DSP_SE4C2_1", - "DSP_SE4C2_2", - "DSP_SE4C2_3", - "DSP_SE4C2_4", - "DSP_SE4C3_0", - "DSP_SE4C3_1", - "DSP_SE4C3_2", - "DSP_SE4C3_3", - "DSP_SE4C3_4", - "DSP_SW2A0_0", - "DSP_SW2A0_1", - "DSP_SW2A0_2", - "DSP_SW2A0_3", - "DSP_SW2A0_4", - "DSP_SW2A1_0", - "DSP_SW2A1_1", - "DSP_SW2A1_2", - "DSP_SW2A1_3", - "DSP_SW2A1_4", - "DSP_SW2A2_0", - "DSP_SW2A2_1", - "DSP_SW2A2_2", - "DSP_SW2A2_3", - "DSP_SW2A2_4", - "DSP_SW2A3_0", - "DSP_SW2A3_1", - "DSP_SW2A3_2", - "DSP_SW2A3_3", - "DSP_SW2A3_4", - "DSP_SW4A0_0", - "DSP_SW4A0_1", - "DSP_SW4A0_2", - "DSP_SW4A0_3", - "DSP_SW4A0_4", - "DSP_SW4A1_0", - "DSP_SW4A1_1", - "DSP_SW4A1_2", - "DSP_SW4A1_3", - "DSP_SW4A1_4", - "DSP_SW4A2_0", - "DSP_SW4A2_1", - "DSP_SW4A2_2", - "DSP_SW4A2_3", - "DSP_SW4A2_4", - "DSP_SW4A3_0", - "DSP_SW4A3_1", - "DSP_SW4A3_2", - "DSP_SW4A3_3", - "DSP_SW4A3_4", - "DSP_SW4END0_0", - "DSP_SW4END0_1", - "DSP_SW4END0_2", - "DSP_SW4END0_3", - "DSP_SW4END0_4", - "DSP_SW4END1_0", - "DSP_SW4END1_1", - "DSP_SW4END1_2", - "DSP_SW4END1_3", - "DSP_SW4END1_4", - "DSP_SW4END2_0", - "DSP_SW4END2_1", - "DSP_SW4END2_2", - "DSP_SW4END2_3", - "DSP_SW4END2_4", - "DSP_SW4END3_0", - "DSP_SW4END3_1", - "DSP_SW4END3_2", - "DSP_SW4END3_3", - "DSP_SW4END3_4", - "DSP_VCC_R", - "DSP_WL1END0_0", - "DSP_WL1END0_1", - "DSP_WL1END0_2", - "DSP_WL1END0_3", - "DSP_WL1END0_4", - "DSP_WL1END1_0", - "DSP_WL1END1_1", - "DSP_WL1END1_2", - "DSP_WL1END1_3", - "DSP_WL1END1_4", - "DSP_WL1END2_0", - "DSP_WL1END2_1", - "DSP_WL1END2_2", - "DSP_WL1END2_3", - "DSP_WL1END2_4", - "DSP_WL1END3_0", - "DSP_WL1END3_1", - "DSP_WL1END3_2", - "DSP_WL1END3_3", - "DSP_WL1END3_4", - "DSP_WR1END0_0", - "DSP_WR1END0_1", - "DSP_WR1END0_2", - "DSP_WR1END0_3", - "DSP_WR1END0_4", - "DSP_WR1END1_0", - "DSP_WR1END1_1", - "DSP_WR1END1_2", - "DSP_WR1END1_3", - "DSP_WR1END1_4", - "DSP_WR1END2_0", - "DSP_WR1END2_1", - "DSP_WR1END2_2", - "DSP_WR1END2_3", - "DSP_WR1END2_4", - "DSP_WR1END3_0", - "DSP_WR1END3_1", - "DSP_WR1END3_2", - "DSP_WR1END3_3", - "DSP_WR1END3_4", - "DSP_WW2A0_0", - "DSP_WW2A0_1", - "DSP_WW2A0_2", - "DSP_WW2A0_3", - "DSP_WW2A0_4", - "DSP_WW2A1_0", - "DSP_WW2A1_1", - "DSP_WW2A1_2", - "DSP_WW2A1_3", - "DSP_WW2A1_4", - "DSP_WW2A2_0", - "DSP_WW2A2_1", - "DSP_WW2A2_2", - "DSP_WW2A2_3", - "DSP_WW2A2_4", - "DSP_WW2A3_0", - "DSP_WW2A3_1", - "DSP_WW2A3_2", - "DSP_WW2A3_3", - "DSP_WW2A3_4", - "DSP_WW2END0_0", - "DSP_WW2END0_1", - "DSP_WW2END0_2", - "DSP_WW2END0_3", - "DSP_WW2END0_4", - "DSP_WW2END1_0", - "DSP_WW2END1_1", - "DSP_WW2END1_2", - "DSP_WW2END1_3", - "DSP_WW2END1_4", - "DSP_WW2END2_0", - "DSP_WW2END2_1", - "DSP_WW2END2_2", - "DSP_WW2END2_3", - "DSP_WW2END2_4", - "DSP_WW2END3_0", - "DSP_WW2END3_1", - "DSP_WW2END3_2", - "DSP_WW2END3_3", - "DSP_WW2END3_4", - "DSP_WW4A0_0", - "DSP_WW4A0_1", - "DSP_WW4A0_2", - "DSP_WW4A0_3", - "DSP_WW4A0_4", - "DSP_WW4A1_0", - "DSP_WW4A1_1", - "DSP_WW4A1_2", - "DSP_WW4A1_3", - "DSP_WW4A1_4", - "DSP_WW4A2_0", - "DSP_WW4A2_1", - "DSP_WW4A2_2", - "DSP_WW4A2_3", - "DSP_WW4A2_4", - "DSP_WW4A3_0", - "DSP_WW4A3_1", - "DSP_WW4A3_2", - "DSP_WW4A3_3", - "DSP_WW4A3_4", - "DSP_WW4B0_0", - "DSP_WW4B0_1", - "DSP_WW4B0_2", - "DSP_WW4B0_3", - "DSP_WW4B0_4", - "DSP_WW4B1_0", - "DSP_WW4B1_1", - "DSP_WW4B1_2", - "DSP_WW4B1_3", - "DSP_WW4B1_4", - "DSP_WW4B2_0", - "DSP_WW4B2_1", - "DSP_WW4B2_2", - "DSP_WW4B2_3", - "DSP_WW4B2_4", - "DSP_WW4B3_0", - "DSP_WW4B3_1", - "DSP_WW4B3_2", - "DSP_WW4B3_3", - "DSP_WW4B3_4", - "DSP_WW4C0_0", - "DSP_WW4C0_1", - "DSP_WW4C0_2", - "DSP_WW4C0_3", - "DSP_WW4C0_4", - "DSP_WW4C1_0", - "DSP_WW4C1_1", - "DSP_WW4C1_2", - "DSP_WW4C1_3", - "DSP_WW4C1_4", - "DSP_WW4C2_0", - "DSP_WW4C2_1", - "DSP_WW4C2_2", - "DSP_WW4C2_3", - "DSP_WW4C2_4", - "DSP_WW4C3_0", - "DSP_WW4C3_1", - "DSP_WW4C3_2", - "DSP_WW4C3_3", - "DSP_WW4C3_4", - "DSP_WW4END0_0", - "DSP_WW4END0_1", - "DSP_WW4END0_2", - "DSP_WW4END0_3", - "DSP_WW4END0_4", - "DSP_WW4END1_0", - "DSP_WW4END1_1", - "DSP_WW4END1_2", - "DSP_WW4END1_3", - "DSP_WW4END1_4", - "DSP_WW4END2_0", - "DSP_WW4END2_1", - "DSP_WW4END2_2", - "DSP_WW4END2_3", - "DSP_WW4END2_4", - "DSP_WW4END3_0", - "DSP_WW4END3_1", - "DSP_WW4END3_2", - "DSP_WW4END3_3", - "DSP_WW4END3_4" - ] + "wires": { + "DSP_0_A0": { + "cap": "57.597", + "res": "0.000" + }, + "DSP_0_A1": { + "cap": "57.597", + "res": "0.000" + }, + "DSP_0_A10": { + "cap": "57.597", + "res": "0.000" + }, + "DSP_0_A11": { + "cap": "57.597", + "res": "0.000" + }, + "DSP_0_A12": { + "cap": "57.597", + "res": "0.000" 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"DSP_WL1END1_2": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WL1END1_3": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WL1END1_4": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WL1END2_0": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WL1END2_1": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WL1END2_2": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WL1END2_3": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WL1END2_4": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WL1END3_0": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WL1END3_1": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WL1END3_2": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WL1END3_3": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WL1END3_4": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END0_0": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END0_1": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END0_2": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END0_3": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END0_4": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END1_0": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END1_1": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END1_2": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END1_3": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END1_4": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END2_0": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END2_1": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END2_2": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END2_3": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END2_4": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END3_0": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END3_1": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END3_2": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END3_3": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WR1END3_4": { + "cap": "11.900", + "res": "47.430" + }, + "DSP_WW2A0_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A0_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A0_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A0_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A0_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A1_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A1_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A1_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A1_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A1_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A2_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A2_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A2_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A2_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A2_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A3_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A3_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A3_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A3_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2A3_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END0_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END0_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END0_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END0_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END0_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END1_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END1_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END1_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END1_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END1_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END2_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END2_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END2_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END2_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END2_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END3_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END3_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END3_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END3_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW2END3_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A0_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A0_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A0_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A0_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A0_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A1_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A1_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A1_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A1_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A1_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A2_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A2_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A2_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A2_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A2_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A3_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A3_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A3_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A3_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4A3_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B0_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B0_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B0_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B0_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B0_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B1_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B1_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B1_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B1_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B1_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B2_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B2_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B2_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B2_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B2_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B3_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B3_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B3_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B3_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4B3_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C0_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C0_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C0_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C0_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C0_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C1_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C1_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C1_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C1_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C1_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C2_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C2_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C2_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C2_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C2_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C3_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C3_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C3_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C3_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4C3_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END0_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END0_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END0_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END0_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END0_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END1_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END1_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END1_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END1_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END1_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END2_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END2_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END2_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END2_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END2_4": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END3_0": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END3_1": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END3_2": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END3_3": { + "cap": "11.000", + "res": "47.430" + }, + "DSP_WW4END3_4": { + "cap": "11.000", + "res": "47.430" + } + } } diff --git a/zynq7/tile_type_HCLK_BRAM.json b/zynq7/tile_type_HCLK_BRAM.json index 5e5a40f..edbe22c 100644 --- a/zynq7/tile_type_HCLK_BRAM.json +++ b/zynq7/tile_type_HCLK_BRAM.json @@ -2,107 +2,107 @@ "pips": {}, "sites": [], "tile_type": "HCLK_BRAM", - "wires": [ - "HCLK_BRAM_CASCADEA_L", - "HCLK_BRAM_CASCADEA_R", - "HCLK_BRAM_CASCADEB_L", - "HCLK_BRAM_CASCADEB_R", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9", - "HCLK_BRAM_CK_BUFHCLK0", - "HCLK_BRAM_CK_BUFHCLK1", - "HCLK_BRAM_CK_BUFHCLK10", - "HCLK_BRAM_CK_BUFHCLK11", - "HCLK_BRAM_CK_BUFHCLK2", - "HCLK_BRAM_CK_BUFHCLK3", - "HCLK_BRAM_CK_BUFHCLK4", - "HCLK_BRAM_CK_BUFHCLK5", - "HCLK_BRAM_CK_BUFHCLK6", - "HCLK_BRAM_CK_BUFHCLK7", - "HCLK_BRAM_CK_BUFHCLK8", - "HCLK_BRAM_CK_BUFHCLK9", - "HCLK_BRAM_CK_BUFRCLK0", - "HCLK_BRAM_CK_BUFRCLK1", - "HCLK_BRAM_CK_BUFRCLK2", - "HCLK_BRAM_CK_BUFRCLK3", - "HCLK_BRAM_CK_IN0", - "HCLK_BRAM_CK_IN1", - "HCLK_BRAM_CK_IN10", - "HCLK_BRAM_CK_IN11", - "HCLK_BRAM_CK_IN12", - "HCLK_BRAM_CK_IN13", - "HCLK_BRAM_CK_IN2", - "HCLK_BRAM_CK_IN3", - "HCLK_BRAM_CK_IN4", - "HCLK_BRAM_CK_IN5", - "HCLK_BRAM_CK_IN6", - "HCLK_BRAM_CK_IN7", - "HCLK_BRAM_CK_IN8", - "HCLK_BRAM_CK_IN9", - "HCLK_BRAM_PMVBRAM_O", - "HCLK_BRAM_PMVBRAM_ODIV2", - "HCLK_BRAM_PMVBRAM_ODIV4", - "HCLK_BRAM_PMVBRAM_SELECT1", - "HCLK_BRAM_PMVBRAM_SELECT2", - "HCLK_BRAM_PMVBRAM_SELECT3", - "HCLK_BRAM_PMVBRAM_SELECT4" - ] + "wires": { + "HCLK_BRAM_CASCADEA_L": null, + "HCLK_BRAM_CASCADEA_R": null, + "HCLK_BRAM_CASCADEB_L": null, + "HCLK_BRAM_CASCADEB_R": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9": null, + "HCLK_BRAM_CK_BUFHCLK0": null, + "HCLK_BRAM_CK_BUFHCLK1": null, + "HCLK_BRAM_CK_BUFHCLK10": null, + "HCLK_BRAM_CK_BUFHCLK11": null, + "HCLK_BRAM_CK_BUFHCLK2": null, + "HCLK_BRAM_CK_BUFHCLK3": null, + "HCLK_BRAM_CK_BUFHCLK4": null, + "HCLK_BRAM_CK_BUFHCLK5": null, + "HCLK_BRAM_CK_BUFHCLK6": null, + "HCLK_BRAM_CK_BUFHCLK7": null, + "HCLK_BRAM_CK_BUFHCLK8": null, + "HCLK_BRAM_CK_BUFHCLK9": null, + "HCLK_BRAM_CK_BUFRCLK0": null, + "HCLK_BRAM_CK_BUFRCLK1": null, + "HCLK_BRAM_CK_BUFRCLK2": null, + "HCLK_BRAM_CK_BUFRCLK3": null, + "HCLK_BRAM_CK_IN0": null, + "HCLK_BRAM_CK_IN1": null, + "HCLK_BRAM_CK_IN10": null, + "HCLK_BRAM_CK_IN11": null, + "HCLK_BRAM_CK_IN12": null, + "HCLK_BRAM_CK_IN13": null, + "HCLK_BRAM_CK_IN2": null, + "HCLK_BRAM_CK_IN3": null, + "HCLK_BRAM_CK_IN4": null, + "HCLK_BRAM_CK_IN5": null, + "HCLK_BRAM_CK_IN6": null, + "HCLK_BRAM_CK_IN7": null, + "HCLK_BRAM_CK_IN8": null, + "HCLK_BRAM_CK_IN9": null, + "HCLK_BRAM_PMVBRAM_O": null, + "HCLK_BRAM_PMVBRAM_ODIV2": null, + "HCLK_BRAM_PMVBRAM_ODIV4": null, + "HCLK_BRAM_PMVBRAM_SELECT1": null, + "HCLK_BRAM_PMVBRAM_SELECT2": null, + "HCLK_BRAM_PMVBRAM_SELECT3": null, + "HCLK_BRAM_PMVBRAM_SELECT4": null + } } diff --git a/zynq7/tile_type_HCLK_CLB.json b/zynq7/tile_type_HCLK_CLB.json index d435e59..97d4443 100644 --- a/zynq7/tile_type_HCLK_CLB.json +++ b/zynq7/tile_type_HCLK_CLB.json @@ -2,48 +2,60 @@ "pips": {}, "sites": [], "tile_type": "HCLK_CLB", - "wires": [ - "HCLK_CLB_CK_BUFHCLK0", - "HCLK_CLB_CK_BUFHCLK1", - "HCLK_CLB_CK_BUFHCLK10", - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_CLB_CK_BUFHCLK2", - "HCLK_CLB_CK_BUFHCLK3", - "HCLK_CLB_CK_BUFHCLK4", - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_CLB_CK_BUFHCLK6", - "HCLK_CLB_CK_BUFHCLK7", - "HCLK_CLB_CK_BUFHCLK8", - "HCLK_CLB_CK_BUFHCLK9", - "HCLK_CLB_CK_BUFRCLK0", - "HCLK_CLB_CK_BUFRCLK1", - "HCLK_CLB_CK_BUFRCLK2", - "HCLK_CLB_CK_BUFRCLK3", - "HCLK_CLB_CK_IN0", - "HCLK_CLB_CK_IN1", - "HCLK_CLB_CK_IN10", - "HCLK_CLB_CK_IN11", - "HCLK_CLB_CK_IN12", - "HCLK_CLB_CK_IN13", - "HCLK_CLB_CK_IN2", - "HCLK_CLB_CK_IN3", - "HCLK_CLB_CK_IN4", - "HCLK_CLB_CK_IN5", - "HCLK_CLB_CK_IN6", - "HCLK_CLB_CK_IN7", - "HCLK_CLB_CK_IN8", - "HCLK_CLB_CK_IN9", - "HCLK_CLB_COUT0_L", - "HCLK_CLB_COUT0_R", - "HCLK_CLB_COUT1_L", - "HCLK_CLB_COUT1_R", - "HCLK_CLB_PERFCLK0", - "HCLK_CLB_PERFCLK1", - "HCLK_CLB_PERFCLK2", - "HCLK_CLB_PERFCLK3", - "HCLK_CLB_REFCK_EASTCLK0", - "HCLK_CLB_REFCK_EASTCLK1", - "HCLK_CLB_REFCK_WESTCLK0", - "HCLK_CLB_REFCK_WESTCLK1" - ] + "wires": { + "HCLK_CLB_CK_BUFHCLK0": null, + "HCLK_CLB_CK_BUFHCLK1": null, + "HCLK_CLB_CK_BUFHCLK10": null, + "HCLK_CLB_CK_BUFHCLK11": null, + "HCLK_CLB_CK_BUFHCLK2": null, + "HCLK_CLB_CK_BUFHCLK3": null, + "HCLK_CLB_CK_BUFHCLK4": null, + "HCLK_CLB_CK_BUFHCLK5": null, + "HCLK_CLB_CK_BUFHCLK6": null, + "HCLK_CLB_CK_BUFHCLK7": null, + "HCLK_CLB_CK_BUFHCLK8": null, + "HCLK_CLB_CK_BUFHCLK9": null, + "HCLK_CLB_CK_BUFRCLK0": null, + "HCLK_CLB_CK_BUFRCLK1": null, + "HCLK_CLB_CK_BUFRCLK2": null, + "HCLK_CLB_CK_BUFRCLK3": null, + "HCLK_CLB_CK_IN0": null, + "HCLK_CLB_CK_IN1": null, + "HCLK_CLB_CK_IN10": null, + "HCLK_CLB_CK_IN11": null, + "HCLK_CLB_CK_IN12": null, + "HCLK_CLB_CK_IN13": null, + "HCLK_CLB_CK_IN2": null, + "HCLK_CLB_CK_IN3": null, + "HCLK_CLB_CK_IN4": null, + "HCLK_CLB_CK_IN5": null, + "HCLK_CLB_CK_IN6": null, + "HCLK_CLB_CK_IN7": null, + "HCLK_CLB_CK_IN8": null, + "HCLK_CLB_CK_IN9": null, + "HCLK_CLB_COUT0_L": { + "cap": "13.000", + "res": "0.000" + }, + "HCLK_CLB_COUT0_R": { + "cap": "13.000", + "res": "0.000" + }, + "HCLK_CLB_COUT1_L": { + "cap": "13.000", + "res": "0.000" + }, + "HCLK_CLB_COUT1_R": { + "cap": "13.000", + "res": "0.000" + }, + "HCLK_CLB_PERFCLK0": null, + "HCLK_CLB_PERFCLK1": null, + "HCLK_CLB_PERFCLK2": null, + "HCLK_CLB_PERFCLK3": null, + "HCLK_CLB_REFCK_EASTCLK0": null, + "HCLK_CLB_REFCK_EASTCLK1": null, + "HCLK_CLB_REFCK_WESTCLK0": null, + "HCLK_CLB_REFCK_WESTCLK1": null + } } diff --git a/zynq7/tile_type_HCLK_CMT_L.json b/zynq7/tile_type_HCLK_CMT_L.json index 59a5956..4a59bca 100644 --- a/zynq7/tile_type_HCLK_CMT_L.json +++ b/zynq7/tile_type_HCLK_CMT_L.json @@ -2,6876 +2,27478 @@ "pips": { "HCLK_CMT_L.HCLK_CMT_BUFMRCE_O0->>HCLK_CMT_BUFMR_PHASEREF0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_PHASEREF0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_BUFMRCE_O0" }, "HCLK_CMT_L.HCLK_CMT_BUFMRCE_O1->>HCLK_CMT_BUFMR_PHASEREF1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_PHASEREF1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_BUFMRCE_O1" }, "HCLK_CMT_L.HCLK_CMT_BUFMR_CE0->HCLK_CMT_BUFMRCE_CEINP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_CMT_BUFMRCE_CEINP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_CMT_BUFMR_CE0" }, "HCLK_CMT_L.HCLK_CMT_BUFMR_CE1->HCLK_CMT_BUFMRCE_CEINP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_CMT_BUFMRCE_CEINP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_CMT_BUFMR_CE1" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.237", + "0.250", + "0.598", + "0.655" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.237", + "0.250", + "0.598", + "0.655" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.290", + "0.313", + "0.755", + "0.832" + ], + "in_cap": null, + "res": null + }, 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"0.168", + "0.185", + "0.500", + "0.550" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": 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"dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.163", + "0.180", + "0.478", + "0.525" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.163", + "0.180", + "0.478", + "0.525" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.163", + "0.180", + "0.478", + "0.525" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.163", + "0.180", + "0.478", + "0.525" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.163", + "0.180", + "0.478", + "0.525" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.163", + "0.180", + "0.478", + "0.525" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.185", + "0.500", + "0.550" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": 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"dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], 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"HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": 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"delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.085", + "0.094", + "0.260", + "0.286" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.163", + "0.180", + "0.478", + "0.525" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.163", + "0.180", + "0.478", + "0.525" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.163", + "0.180", + "0.478", + "0.525" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.163", + "0.180", + "0.478", + "0.525" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.163", + "0.180", + "0.478", + "0.525" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.163", + "0.180", + "0.478", + "0.525" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.185", + "0.500", + "0.550" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.185", + "0.500", + "0.550" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.185", + "0.500", + "0.550" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.185", + "0.500", + "0.550" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFRCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.168", + "0.185", + "0.500", + "0.550" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.168", + "0.185", + "0.500", + "0.550" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFRCLK3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_0->>HCLK_CMT_BUFMR_INP0": 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"0.147", + "0.444", + "0.488" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.147", + "0.444", + "0.488" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLKINT_0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.165", + "0.182", + "0.495", + "0.545" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.165", + "0.182", + "0.495", + "0.545" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLKINT_1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.165", + "0.182", + "0.495", + "0.545" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.165", + "0.182", + "0.495", + "0.545" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLKINT_1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_MUX_OUT_FREQ_REF1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.147", + "0.444", + "0.488" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.147", + "0.444", + "0.488" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLKINT_1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_2->>HCLK_CMT_MUX_OUT_FREQ_REF2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.147", + "0.444", + "0.488" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.147", + "0.444", + "0.488" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLKINT_2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.147", + "0.444", + "0.488" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.147", + "0.444", + "0.488" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLKINT_3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, 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"res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN8": { 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}, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", 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"HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + 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"0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { 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"0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", 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"0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + 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"0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.125", + "0.138", + "0.387", + "0.426" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, 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"HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + 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"0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.081", + "0.090", + "0.251", + "0.276" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.158", + "0.174", + "0.468", + "0.515" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.167", + "0.184", + "0.498", + "0.548" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, 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null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, 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null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN0": { 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"src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.207", + "0.573", + "0.631" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_CK_IN2": { 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}, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN0": { 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null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, 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null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, 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"0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + 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null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, 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"0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN3": { 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null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ 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"delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.202", + "0.223", + "0.568", + "0.625" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.299", + "0.330", + "0.795", + "0.874" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3" }, "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF0->>HCLK_CMT_FREQ_REF_NS0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_FREQ_REF_NS0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0" }, "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF1->>HCLK_CMT_FREQ_REF_NS1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_FREQ_REF_NS1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1" }, "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF2->>HCLK_CMT_FREQ_REF_NS2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_FREQ_REF_NS2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2" }, "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF3->>HCLK_CMT_FREQ_REF_NS3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_FREQ_REF_NS3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.147", + "0.162", + "0.411", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" } }, @@ -6880,9 +27482,36 @@ "name": "X0Y1", "prefix": "BUFMRCE", "site_pins": { - "CE": "HCLK_CMT_BUFMRCE_CEINP1", - "I": "HCLK_CMT_BUFMR_INP1", - "O": "HCLK_CMT_BUFMRCE_O1" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "HCLK_CMT_BUFMRCE_CEINP1" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "HCLK_CMT_BUFMR_INP1" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "HCLK_CMT_BUFMRCE_O1" + } }, "type": "BUFMRCE", "x_coord": 0, @@ -6892,9 +27521,36 @@ "name": "X0Y0", "prefix": "BUFMRCE", "site_pins": { - "CE": "HCLK_CMT_BUFMRCE_CEINP0", - "I": "HCLK_CMT_BUFMR_INP0", - "O": "HCLK_CMT_BUFMRCE_O0" + "CE": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "HCLK_CMT_BUFMRCE_CEINP0" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "HCLK_CMT_BUFMR_INP0" + }, + "O": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "res": "0.0", + "wire": "HCLK_CMT_BUFMRCE_O0" + } }, "type": "BUFMRCE", "x_coord": 0, @@ -6902,146 +27558,146 @@ } ], "tile_type": "HCLK_CMT_L", - "wires": [ - "HCLK_CMT_BUFMRCE_CEINP0", - "HCLK_CMT_BUFMRCE_CEINP1", - "HCLK_CMT_BUFMRCE_O0", - "HCLK_CMT_BUFMRCE_O1", - "HCLK_CMT_BUFMR_CE0", - "HCLK_CMT_BUFMR_CE1", - "HCLK_CMT_BUFMR_INP0", - "HCLK_CMT_BUFMR_INP1", - "HCLK_CMT_BUFMR_PHASEREF0", - "HCLK_CMT_BUFMR_PHASEREF1", - "HCLK_CMT_CCIO0", - "HCLK_CMT_CCIO1", - "HCLK_CMT_CCIO2", - "HCLK_CMT_CCIO3", - "HCLK_CMT_CK_BUFHCLK0", - "HCLK_CMT_CK_BUFHCLK1", - "HCLK_CMT_CK_BUFHCLK10", - "HCLK_CMT_CK_BUFHCLK11", - "HCLK_CMT_CK_BUFHCLK2", - "HCLK_CMT_CK_BUFHCLK3", - "HCLK_CMT_CK_BUFHCLK4", - "HCLK_CMT_CK_BUFHCLK5", - "HCLK_CMT_CK_BUFHCLK6", - "HCLK_CMT_CK_BUFHCLK7", - "HCLK_CMT_CK_BUFHCLK8", - "HCLK_CMT_CK_BUFHCLK9", - "HCLK_CMT_CK_BUFRCLK0", - "HCLK_CMT_CK_BUFRCLK1", - "HCLK_CMT_CK_BUFRCLK2", - "HCLK_CMT_CK_BUFRCLK3", - "HCLK_CMT_CK_IN0", - "HCLK_CMT_CK_IN1", - "HCLK_CMT_CK_IN10", - "HCLK_CMT_CK_IN11", - "HCLK_CMT_CK_IN12", - "HCLK_CMT_CK_IN13", - "HCLK_CMT_CK_IN2", - "HCLK_CMT_CK_IN3", - "HCLK_CMT_CK_IN4", - "HCLK_CMT_CK_IN5", - "HCLK_CMT_CK_IN6", - "HCLK_CMT_CK_IN7", - "HCLK_CMT_CK_IN8", - "HCLK_CMT_CK_IN9", - "HCLK_CMT_ECALIB0", - "HCLK_CMT_ECALIB1", - "HCLK_CMT_FREQ_PHASER_REFMUX_0", - "HCLK_CMT_FREQ_PHASER_REFMUX_1", - "HCLK_CMT_FREQ_PHASER_REFMUX_2", - "HCLK_CMT_FREQ_REF_NS0", - "HCLK_CMT_FREQ_REF_NS1", - "HCLK_CMT_FREQ_REF_NS2", - "HCLK_CMT_FREQ_REF_NS3", - "HCLK_CMT_IBURST0", - "HCLK_CMT_IBURST1", - "HCLK_CMT_IBURSTPENDING0", - "HCLK_CMT_IBURSTPENDING1", - "HCLK_CMT_MUX_CLKINT_0", - "HCLK_CMT_MUX_CLKINT_1", - "HCLK_CMT_MUX_CLKINT_2", - "HCLK_CMT_MUX_CLKINT_3", - "HCLK_CMT_MUX_CLK_0", - "HCLK_CMT_MUX_CLK_1", - "HCLK_CMT_MUX_CLK_10", - "HCLK_CMT_MUX_CLK_11", - "HCLK_CMT_MUX_CLK_12", - "HCLK_CMT_MUX_CLK_13", - "HCLK_CMT_MUX_CLK_2", - "HCLK_CMT_MUX_CLK_3", - "HCLK_CMT_MUX_CLK_4", - "HCLK_CMT_MUX_CLK_5", - "HCLK_CMT_MUX_CLK_6", - "HCLK_CMT_MUX_CLK_7", - "HCLK_CMT_MUX_CLK_8", - "HCLK_CMT_MUX_CLK_9", - "HCLK_CMT_MUX_CLK_LEAF_DN0", - "HCLK_CMT_MUX_CLK_LEAF_DN1", - "HCLK_CMT_MUX_CLK_LEAF_UP0", - "HCLK_CMT_MUX_CLK_LEAF_UP1", - "HCLK_CMT_MUX_CLK_MMCM0", - "HCLK_CMT_MUX_CLK_MMCM1", - "HCLK_CMT_MUX_CLK_MMCM10", - "HCLK_CMT_MUX_CLK_MMCM11", - "HCLK_CMT_MUX_CLK_MMCM12", - "HCLK_CMT_MUX_CLK_MMCM13", - "HCLK_CMT_MUX_CLK_MMCM2", - "HCLK_CMT_MUX_CLK_MMCM3", - "HCLK_CMT_MUX_CLK_MMCM4", - "HCLK_CMT_MUX_CLK_MMCM5", - "HCLK_CMT_MUX_CLK_MMCM6", - "HCLK_CMT_MUX_CLK_MMCM7", - "HCLK_CMT_MUX_CLK_MMCM8", - "HCLK_CMT_MUX_CLK_MMCM9", - "HCLK_CMT_MUX_CLK_PLL0", - "HCLK_CMT_MUX_CLK_PLL1", - "HCLK_CMT_MUX_CLK_PLL2", - "HCLK_CMT_MUX_CLK_PLL3", - "HCLK_CMT_MUX_CLK_PLL4", - "HCLK_CMT_MUX_CLK_PLL5", - "HCLK_CMT_MUX_CLK_PLL6", - "HCLK_CMT_MUX_CLK_PLL7", - "HCLK_CMT_MUX_MMCM_CLKFBIN", - "HCLK_CMT_MUX_MMCM_CLKIN1", - "HCLK_CMT_MUX_MMCM_CLKIN2", - "HCLK_CMT_MUX_MMCM_MUXED0", - "HCLK_CMT_MUX_MMCM_MUXED1", - "HCLK_CMT_MUX_MMCM_MUXED2", - "HCLK_CMT_MUX_MMCM_MUXED3", - "HCLK_CMT_MUX_OUT_FREQ_REF0", - "HCLK_CMT_MUX_OUT_FREQ_REF1", - "HCLK_CMT_MUX_OUT_FREQ_REF2", - "HCLK_CMT_MUX_OUT_FREQ_REF3", - "HCLK_CMT_MUX_PHSR_PERFCLK0", - "HCLK_CMT_MUX_PHSR_PERFCLK1", - "HCLK_CMT_MUX_PHSR_PERFCLK2", - "HCLK_CMT_MUX_PHSR_PERFCLK3", - "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "HCLK_CMT_MUX_PLLE2_CLKIN1", - "HCLK_CMT_MUX_PLLE2_CLKIN2", - "HCLK_CMT_OBURSTPENDING0", - "HCLK_CMT_OBURSTPENDING1", - "HCLK_CMT_PHASEREF_ABOVE0", - "HCLK_CMT_PHASEREF_ABOVE1", - "HCLK_CMT_PHASEREF_BELOW0", - "HCLK_CMT_PHASEREF_BELOW1", - "HCLK_CMT_PHASERIN_RCLK0", - "HCLK_CMT_PHASERIN_RCLK1", - "HCLK_CMT_PHASERIN_RCLK2", - "HCLK_CMT_PHASERIN_RCLK3", - "HCLK_CMT_PHY_CONTROL_IRANKA0", - "HCLK_CMT_PHY_CONTROL_IRANKA1", - "HCLK_CMT_PHY_CONTROL_IRANKB0", - "HCLK_CMT_PHY_CONTROL_IRANKB1", - "HCLK_CMT_PHY_SYNC_BB", - "HCLK_CMT_PREF_BOUNCE0", - "HCLK_CMT_PREF_BOUNCE1", - "HCLK_CMT_PREF_BOUNCE2", - "HCLK_CMT_PREF_BOUNCE3", - "HCLK_CMT_PREF_CLKOUT", - "HCLK_CMT_PREF_TMUXOUT" - ] + "wires": { + "HCLK_CMT_BUFMRCE_CEINP0": null, + "HCLK_CMT_BUFMRCE_CEINP1": null, + "HCLK_CMT_BUFMRCE_O0": null, + "HCLK_CMT_BUFMRCE_O1": null, + "HCLK_CMT_BUFMR_CE0": null, + "HCLK_CMT_BUFMR_CE1": null, + "HCLK_CMT_BUFMR_INP0": null, + "HCLK_CMT_BUFMR_INP1": null, + "HCLK_CMT_BUFMR_PHASEREF0": null, + "HCLK_CMT_BUFMR_PHASEREF1": null, + "HCLK_CMT_CCIO0": null, + "HCLK_CMT_CCIO1": null, + "HCLK_CMT_CCIO2": null, + "HCLK_CMT_CCIO3": null, + "HCLK_CMT_CK_BUFHCLK0": null, + "HCLK_CMT_CK_BUFHCLK1": null, + "HCLK_CMT_CK_BUFHCLK10": null, + "HCLK_CMT_CK_BUFHCLK11": null, + "HCLK_CMT_CK_BUFHCLK2": null, + "HCLK_CMT_CK_BUFHCLK3": null, + "HCLK_CMT_CK_BUFHCLK4": null, + "HCLK_CMT_CK_BUFHCLK5": null, + "HCLK_CMT_CK_BUFHCLK6": null, + "HCLK_CMT_CK_BUFHCLK7": null, + "HCLK_CMT_CK_BUFHCLK8": null, + "HCLK_CMT_CK_BUFHCLK9": null, + "HCLK_CMT_CK_BUFRCLK0": null, + "HCLK_CMT_CK_BUFRCLK1": null, + "HCLK_CMT_CK_BUFRCLK2": null, + "HCLK_CMT_CK_BUFRCLK3": null, + "HCLK_CMT_CK_IN0": null, + "HCLK_CMT_CK_IN1": null, + "HCLK_CMT_CK_IN10": null, + "HCLK_CMT_CK_IN11": null, + "HCLK_CMT_CK_IN12": null, + "HCLK_CMT_CK_IN13": null, + "HCLK_CMT_CK_IN2": null, + "HCLK_CMT_CK_IN3": null, + "HCLK_CMT_CK_IN4": null, + "HCLK_CMT_CK_IN5": null, + "HCLK_CMT_CK_IN6": null, + "HCLK_CMT_CK_IN7": null, + "HCLK_CMT_CK_IN8": null, + "HCLK_CMT_CK_IN9": null, + "HCLK_CMT_ECALIB0": null, + "HCLK_CMT_ECALIB1": null, + "HCLK_CMT_FREQ_PHASER_REFMUX_0": null, + "HCLK_CMT_FREQ_PHASER_REFMUX_1": null, + "HCLK_CMT_FREQ_PHASER_REFMUX_2": null, + "HCLK_CMT_FREQ_REF_NS0": null, + "HCLK_CMT_FREQ_REF_NS1": null, + "HCLK_CMT_FREQ_REF_NS2": null, + "HCLK_CMT_FREQ_REF_NS3": null, + "HCLK_CMT_IBURST0": null, + "HCLK_CMT_IBURST1": null, + "HCLK_CMT_IBURSTPENDING0": null, + "HCLK_CMT_IBURSTPENDING1": null, + "HCLK_CMT_MUX_CLKINT_0": null, + "HCLK_CMT_MUX_CLKINT_1": null, + "HCLK_CMT_MUX_CLKINT_2": null, + "HCLK_CMT_MUX_CLKINT_3": null, + "HCLK_CMT_MUX_CLK_0": null, + "HCLK_CMT_MUX_CLK_1": null, + "HCLK_CMT_MUX_CLK_10": null, + "HCLK_CMT_MUX_CLK_11": null, + "HCLK_CMT_MUX_CLK_12": null, + "HCLK_CMT_MUX_CLK_13": null, + "HCLK_CMT_MUX_CLK_2": null, + "HCLK_CMT_MUX_CLK_3": null, + "HCLK_CMT_MUX_CLK_4": null, + "HCLK_CMT_MUX_CLK_5": null, + "HCLK_CMT_MUX_CLK_6": null, + "HCLK_CMT_MUX_CLK_7": null, + "HCLK_CMT_MUX_CLK_8": null, + "HCLK_CMT_MUX_CLK_9": null, + "HCLK_CMT_MUX_CLK_LEAF_DN0": null, + "HCLK_CMT_MUX_CLK_LEAF_DN1": null, + "HCLK_CMT_MUX_CLK_LEAF_UP0": null, + "HCLK_CMT_MUX_CLK_LEAF_UP1": null, + "HCLK_CMT_MUX_CLK_MMCM0": null, + "HCLK_CMT_MUX_CLK_MMCM1": null, + "HCLK_CMT_MUX_CLK_MMCM10": null, + "HCLK_CMT_MUX_CLK_MMCM11": null, + "HCLK_CMT_MUX_CLK_MMCM12": null, + "HCLK_CMT_MUX_CLK_MMCM13": null, + "HCLK_CMT_MUX_CLK_MMCM2": null, + "HCLK_CMT_MUX_CLK_MMCM3": null, + "HCLK_CMT_MUX_CLK_MMCM4": null, + "HCLK_CMT_MUX_CLK_MMCM5": null, + "HCLK_CMT_MUX_CLK_MMCM6": null, + "HCLK_CMT_MUX_CLK_MMCM7": null, + "HCLK_CMT_MUX_CLK_MMCM8": null, + "HCLK_CMT_MUX_CLK_MMCM9": null, + "HCLK_CMT_MUX_CLK_PLL0": null, + "HCLK_CMT_MUX_CLK_PLL1": null, + "HCLK_CMT_MUX_CLK_PLL2": null, + "HCLK_CMT_MUX_CLK_PLL3": null, + "HCLK_CMT_MUX_CLK_PLL4": null, + "HCLK_CMT_MUX_CLK_PLL5": null, + "HCLK_CMT_MUX_CLK_PLL6": null, + "HCLK_CMT_MUX_CLK_PLL7": null, + "HCLK_CMT_MUX_MMCM_CLKFBIN": null, + "HCLK_CMT_MUX_MMCM_CLKIN1": null, + "HCLK_CMT_MUX_MMCM_CLKIN2": null, + "HCLK_CMT_MUX_MMCM_MUXED0": null, + "HCLK_CMT_MUX_MMCM_MUXED1": null, + "HCLK_CMT_MUX_MMCM_MUXED2": null, + "HCLK_CMT_MUX_MMCM_MUXED3": null, + "HCLK_CMT_MUX_OUT_FREQ_REF0": null, + "HCLK_CMT_MUX_OUT_FREQ_REF1": null, + "HCLK_CMT_MUX_OUT_FREQ_REF2": null, + "HCLK_CMT_MUX_OUT_FREQ_REF3": null, + "HCLK_CMT_MUX_PHSR_PERFCLK0": null, + "HCLK_CMT_MUX_PHSR_PERFCLK1": null, + "HCLK_CMT_MUX_PHSR_PERFCLK2": null, + "HCLK_CMT_MUX_PHSR_PERFCLK3": null, + "HCLK_CMT_MUX_PLLE2_CLKFBIN": null, + "HCLK_CMT_MUX_PLLE2_CLKIN1": null, + "HCLK_CMT_MUX_PLLE2_CLKIN2": null, + "HCLK_CMT_OBURSTPENDING0": null, + "HCLK_CMT_OBURSTPENDING1": null, + "HCLK_CMT_PHASEREF_ABOVE0": null, + "HCLK_CMT_PHASEREF_ABOVE1": null, + "HCLK_CMT_PHASEREF_BELOW0": null, + "HCLK_CMT_PHASEREF_BELOW1": null, + "HCLK_CMT_PHASERIN_RCLK0": null, + "HCLK_CMT_PHASERIN_RCLK1": null, + "HCLK_CMT_PHASERIN_RCLK2": null, + "HCLK_CMT_PHASERIN_RCLK3": null, + "HCLK_CMT_PHY_CONTROL_IRANKA0": null, + "HCLK_CMT_PHY_CONTROL_IRANKA1": null, + "HCLK_CMT_PHY_CONTROL_IRANKB0": null, + "HCLK_CMT_PHY_CONTROL_IRANKB1": null, + "HCLK_CMT_PHY_SYNC_BB": null, + "HCLK_CMT_PREF_BOUNCE0": null, + "HCLK_CMT_PREF_BOUNCE1": null, + "HCLK_CMT_PREF_BOUNCE2": null, + "HCLK_CMT_PREF_BOUNCE3": null, + "HCLK_CMT_PREF_CLKOUT": null, + "HCLK_CMT_PREF_TMUXOUT": null + } } diff --git a/zynq7/tile_type_HCLK_DSP_L.json b/zynq7/tile_type_HCLK_DSP_L.json index 0750914..fe1b9f0 100644 --- a/zynq7/tile_type_HCLK_DSP_L.json +++ b/zynq7/tile_type_HCLK_DSP_L.json @@ -2,134 +2,428 @@ "pips": {}, "sites": [], "tile_type": "HCLK_DSP_L", - "wires": [ - "HCLK_DSP_ACIN0", - "HCLK_DSP_ACIN1", - "HCLK_DSP_ACIN10", - "HCLK_DSP_ACIN11", - "HCLK_DSP_ACIN12", - "HCLK_DSP_ACIN13", - "HCLK_DSP_ACIN14", - "HCLK_DSP_ACIN15", - "HCLK_DSP_ACIN16", - "HCLK_DSP_ACIN17", - "HCLK_DSP_ACIN18", - "HCLK_DSP_ACIN19", - "HCLK_DSP_ACIN2", - "HCLK_DSP_ACIN20", - "HCLK_DSP_ACIN21", - "HCLK_DSP_ACIN22", - "HCLK_DSP_ACIN23", - "HCLK_DSP_ACIN24", - "HCLK_DSP_ACIN25", - "HCLK_DSP_ACIN26", - "HCLK_DSP_ACIN27", - "HCLK_DSP_ACIN28", - "HCLK_DSP_ACIN29", - "HCLK_DSP_ACIN3", - "HCLK_DSP_ACIN4", - "HCLK_DSP_ACIN5", - "HCLK_DSP_ACIN6", - "HCLK_DSP_ACIN7", - "HCLK_DSP_ACIN8", - "HCLK_DSP_ACIN9", - "HCLK_DSP_BCIN0", - "HCLK_DSP_BCIN1", - "HCLK_DSP_BCIN10", - "HCLK_DSP_BCIN11", - "HCLK_DSP_BCIN12", - "HCLK_DSP_BCIN13", - "HCLK_DSP_BCIN14", - "HCLK_DSP_BCIN15", - "HCLK_DSP_BCIN16", - "HCLK_DSP_BCIN17", - "HCLK_DSP_BCIN2", - "HCLK_DSP_BCIN3", - "HCLK_DSP_BCIN4", - "HCLK_DSP_BCIN5", - "HCLK_DSP_BCIN6", - "HCLK_DSP_BCIN7", - "HCLK_DSP_BCIN8", - "HCLK_DSP_BCIN9", - "HCLK_DSP_CARRYCASCIN", - "HCLK_DSP_CK_BUFHCLK0", - "HCLK_DSP_CK_BUFHCLK1", - "HCLK_DSP_CK_BUFHCLK10", - "HCLK_DSP_CK_BUFHCLK11", - "HCLK_DSP_CK_BUFHCLK2", - "HCLK_DSP_CK_BUFHCLK3", - "HCLK_DSP_CK_BUFHCLK4", - "HCLK_DSP_CK_BUFHCLK5", - "HCLK_DSP_CK_BUFHCLK6", - "HCLK_DSP_CK_BUFHCLK7", - "HCLK_DSP_CK_BUFHCLK8", - "HCLK_DSP_CK_BUFHCLK9", - "HCLK_DSP_CK_BUFRCLK0", - "HCLK_DSP_CK_BUFRCLK1", - "HCLK_DSP_CK_BUFRCLK2", - "HCLK_DSP_CK_BUFRCLK3", - "HCLK_DSP_CK_IN0", - "HCLK_DSP_CK_IN1", - "HCLK_DSP_CK_IN10", - "HCLK_DSP_CK_IN11", - "HCLK_DSP_CK_IN12", - "HCLK_DSP_CK_IN13", - "HCLK_DSP_CK_IN2", - "HCLK_DSP_CK_IN3", - "HCLK_DSP_CK_IN4", - "HCLK_DSP_CK_IN5", - "HCLK_DSP_CK_IN6", - "HCLK_DSP_CK_IN7", - "HCLK_DSP_CK_IN8", - "HCLK_DSP_CK_IN9", - "HCLK_DSP_MULTSIGNIN", - "HCLK_DSP_PCIN0", - "HCLK_DSP_PCIN1", - "HCLK_DSP_PCIN10", - "HCLK_DSP_PCIN11", - "HCLK_DSP_PCIN12", - "HCLK_DSP_PCIN13", - "HCLK_DSP_PCIN14", - "HCLK_DSP_PCIN15", - "HCLK_DSP_PCIN16", - "HCLK_DSP_PCIN17", - "HCLK_DSP_PCIN18", - "HCLK_DSP_PCIN19", - "HCLK_DSP_PCIN2", - "HCLK_DSP_PCIN20", - "HCLK_DSP_PCIN21", - "HCLK_DSP_PCIN22", - "HCLK_DSP_PCIN23", - "HCLK_DSP_PCIN24", - "HCLK_DSP_PCIN25", - "HCLK_DSP_PCIN26", - "HCLK_DSP_PCIN27", - "HCLK_DSP_PCIN28", - "HCLK_DSP_PCIN29", - "HCLK_DSP_PCIN3", - "HCLK_DSP_PCIN30", - "HCLK_DSP_PCIN31", - "HCLK_DSP_PCIN32", - "HCLK_DSP_PCIN33", - "HCLK_DSP_PCIN34", - "HCLK_DSP_PCIN35", - "HCLK_DSP_PCIN36", - "HCLK_DSP_PCIN37", - "HCLK_DSP_PCIN38", - "HCLK_DSP_PCIN39", - "HCLK_DSP_PCIN4", - "HCLK_DSP_PCIN40", - "HCLK_DSP_PCIN41", - "HCLK_DSP_PCIN42", - "HCLK_DSP_PCIN43", - "HCLK_DSP_PCIN44", - "HCLK_DSP_PCIN45", - "HCLK_DSP_PCIN46", - "HCLK_DSP_PCIN47", - "HCLK_DSP_PCIN5", - "HCLK_DSP_PCIN6", - "HCLK_DSP_PCIN7", - "HCLK_DSP_PCIN8", - "HCLK_DSP_PCIN9" - ] + "wires": { + "HCLK_DSP_ACIN0": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN1": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN10": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN11": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN12": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN13": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN14": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN15": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN16": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN17": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN18": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN19": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN2": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN20": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN21": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN22": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN23": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN24": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN25": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN26": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN27": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN28": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN29": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN3": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN4": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN5": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN6": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN7": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN8": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN9": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN0": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN1": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN10": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN11": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN12": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN13": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN14": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN15": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN16": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN17": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN2": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN3": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN4": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN5": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN6": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN7": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN8": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN9": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_CARRYCASCIN": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_CK_BUFHCLK0": null, + "HCLK_DSP_CK_BUFHCLK1": null, + "HCLK_DSP_CK_BUFHCLK10": null, + "HCLK_DSP_CK_BUFHCLK11": null, + "HCLK_DSP_CK_BUFHCLK2": null, + "HCLK_DSP_CK_BUFHCLK3": null, + "HCLK_DSP_CK_BUFHCLK4": null, + "HCLK_DSP_CK_BUFHCLK5": null, + "HCLK_DSP_CK_BUFHCLK6": null, + "HCLK_DSP_CK_BUFHCLK7": null, + "HCLK_DSP_CK_BUFHCLK8": null, + "HCLK_DSP_CK_BUFHCLK9": null, + "HCLK_DSP_CK_BUFRCLK0": null, + "HCLK_DSP_CK_BUFRCLK1": null, + "HCLK_DSP_CK_BUFRCLK2": null, + "HCLK_DSP_CK_BUFRCLK3": null, + "HCLK_DSP_CK_IN0": null, + "HCLK_DSP_CK_IN1": null, + "HCLK_DSP_CK_IN10": null, + "HCLK_DSP_CK_IN11": null, + "HCLK_DSP_CK_IN12": null, + "HCLK_DSP_CK_IN13": null, + "HCLK_DSP_CK_IN2": null, + "HCLK_DSP_CK_IN3": null, + "HCLK_DSP_CK_IN4": null, + "HCLK_DSP_CK_IN5": null, + "HCLK_DSP_CK_IN6": null, + "HCLK_DSP_CK_IN7": null, + "HCLK_DSP_CK_IN8": null, + "HCLK_DSP_CK_IN9": null, + "HCLK_DSP_MULTSIGNIN": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN0": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN1": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN10": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN11": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN12": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN13": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN14": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN15": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN16": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN17": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN18": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN19": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN2": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN20": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN21": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN22": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN23": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN24": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN25": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN26": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN27": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN28": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN29": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN3": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN30": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN31": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN32": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN33": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN34": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN35": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN36": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN37": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN38": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN39": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN4": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN40": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN41": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN42": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN43": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN44": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN45": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN46": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN47": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN5": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN6": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN7": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN8": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN9": { + "cap": "31.166", + "res": "0.000" + } + } } diff --git a/zynq7/tile_type_HCLK_DSP_R.json b/zynq7/tile_type_HCLK_DSP_R.json index 909e88d..c1969e4 100644 --- a/zynq7/tile_type_HCLK_DSP_R.json +++ b/zynq7/tile_type_HCLK_DSP_R.json @@ -2,134 +2,428 @@ "pips": {}, "sites": [], "tile_type": "HCLK_DSP_R", - "wires": [ - "HCLK_DSP_ACIN0", - "HCLK_DSP_ACIN1", - "HCLK_DSP_ACIN10", - "HCLK_DSP_ACIN11", - "HCLK_DSP_ACIN12", - "HCLK_DSP_ACIN13", - "HCLK_DSP_ACIN14", - "HCLK_DSP_ACIN15", - "HCLK_DSP_ACIN16", - "HCLK_DSP_ACIN17", - "HCLK_DSP_ACIN18", - "HCLK_DSP_ACIN19", - "HCLK_DSP_ACIN2", - "HCLK_DSP_ACIN20", - "HCLK_DSP_ACIN21", - "HCLK_DSP_ACIN22", - "HCLK_DSP_ACIN23", - "HCLK_DSP_ACIN24", - "HCLK_DSP_ACIN25", - "HCLK_DSP_ACIN26", - "HCLK_DSP_ACIN27", - "HCLK_DSP_ACIN28", - "HCLK_DSP_ACIN29", - "HCLK_DSP_ACIN3", - "HCLK_DSP_ACIN4", - "HCLK_DSP_ACIN5", - "HCLK_DSP_ACIN6", - "HCLK_DSP_ACIN7", - "HCLK_DSP_ACIN8", - "HCLK_DSP_ACIN9", - "HCLK_DSP_BCIN0", - "HCLK_DSP_BCIN1", - "HCLK_DSP_BCIN10", - "HCLK_DSP_BCIN11", - "HCLK_DSP_BCIN12", - "HCLK_DSP_BCIN13", - "HCLK_DSP_BCIN14", - "HCLK_DSP_BCIN15", - "HCLK_DSP_BCIN16", - "HCLK_DSP_BCIN17", - "HCLK_DSP_BCIN2", - "HCLK_DSP_BCIN3", - "HCLK_DSP_BCIN4", - "HCLK_DSP_BCIN5", - "HCLK_DSP_BCIN6", - "HCLK_DSP_BCIN7", - "HCLK_DSP_BCIN8", - "HCLK_DSP_BCIN9", - "HCLK_DSP_CARRYCASCIN", - "HCLK_DSP_CK_BUFHCLK0", - "HCLK_DSP_CK_BUFHCLK1", - "HCLK_DSP_CK_BUFHCLK10", - "HCLK_DSP_CK_BUFHCLK11", - "HCLK_DSP_CK_BUFHCLK2", - "HCLK_DSP_CK_BUFHCLK3", - "HCLK_DSP_CK_BUFHCLK4", - "HCLK_DSP_CK_BUFHCLK5", - "HCLK_DSP_CK_BUFHCLK6", - "HCLK_DSP_CK_BUFHCLK7", - "HCLK_DSP_CK_BUFHCLK8", - "HCLK_DSP_CK_BUFHCLK9", - "HCLK_DSP_CK_BUFRCLK0", - "HCLK_DSP_CK_BUFRCLK1", - "HCLK_DSP_CK_BUFRCLK2", - "HCLK_DSP_CK_BUFRCLK3", - "HCLK_DSP_CK_IN0", - "HCLK_DSP_CK_IN1", - "HCLK_DSP_CK_IN10", - "HCLK_DSP_CK_IN11", - "HCLK_DSP_CK_IN12", - "HCLK_DSP_CK_IN13", - "HCLK_DSP_CK_IN2", - "HCLK_DSP_CK_IN3", - "HCLK_DSP_CK_IN4", - "HCLK_DSP_CK_IN5", - "HCLK_DSP_CK_IN6", - "HCLK_DSP_CK_IN7", - "HCLK_DSP_CK_IN8", - "HCLK_DSP_CK_IN9", - "HCLK_DSP_MULTSIGNIN", - "HCLK_DSP_PCIN0", - "HCLK_DSP_PCIN1", - "HCLK_DSP_PCIN10", - "HCLK_DSP_PCIN11", - "HCLK_DSP_PCIN12", - "HCLK_DSP_PCIN13", - "HCLK_DSP_PCIN14", - "HCLK_DSP_PCIN15", - "HCLK_DSP_PCIN16", - "HCLK_DSP_PCIN17", - "HCLK_DSP_PCIN18", - "HCLK_DSP_PCIN19", - "HCLK_DSP_PCIN2", - "HCLK_DSP_PCIN20", - "HCLK_DSP_PCIN21", - "HCLK_DSP_PCIN22", - "HCLK_DSP_PCIN23", - "HCLK_DSP_PCIN24", - "HCLK_DSP_PCIN25", - "HCLK_DSP_PCIN26", - "HCLK_DSP_PCIN27", - "HCLK_DSP_PCIN28", - "HCLK_DSP_PCIN29", - "HCLK_DSP_PCIN3", - "HCLK_DSP_PCIN30", - "HCLK_DSP_PCIN31", - "HCLK_DSP_PCIN32", - "HCLK_DSP_PCIN33", - "HCLK_DSP_PCIN34", - "HCLK_DSP_PCIN35", - "HCLK_DSP_PCIN36", - "HCLK_DSP_PCIN37", - "HCLK_DSP_PCIN38", - "HCLK_DSP_PCIN39", - "HCLK_DSP_PCIN4", - "HCLK_DSP_PCIN40", - "HCLK_DSP_PCIN41", - "HCLK_DSP_PCIN42", - "HCLK_DSP_PCIN43", - "HCLK_DSP_PCIN44", - "HCLK_DSP_PCIN45", - "HCLK_DSP_PCIN46", - "HCLK_DSP_PCIN47", - "HCLK_DSP_PCIN5", - "HCLK_DSP_PCIN6", - "HCLK_DSP_PCIN7", - "HCLK_DSP_PCIN8", - "HCLK_DSP_PCIN9" - ] + "wires": { + "HCLK_DSP_ACIN0": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN1": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN10": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN11": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN12": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN13": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN14": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN15": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN16": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN17": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN18": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN19": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN2": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN20": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN21": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN22": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN23": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN24": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN25": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN26": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN27": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN28": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN29": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN3": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN4": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN5": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN6": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN7": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN8": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_ACIN9": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN0": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN1": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN10": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN11": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN12": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN13": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN14": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN15": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN16": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN17": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN2": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN3": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN4": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN5": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN6": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN7": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN8": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_BCIN9": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_CARRYCASCIN": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_CK_BUFHCLK0": null, + "HCLK_DSP_CK_BUFHCLK1": null, + "HCLK_DSP_CK_BUFHCLK10": null, + "HCLK_DSP_CK_BUFHCLK11": null, + "HCLK_DSP_CK_BUFHCLK2": null, + "HCLK_DSP_CK_BUFHCLK3": null, + "HCLK_DSP_CK_BUFHCLK4": null, + "HCLK_DSP_CK_BUFHCLK5": null, + "HCLK_DSP_CK_BUFHCLK6": null, + "HCLK_DSP_CK_BUFHCLK7": null, + "HCLK_DSP_CK_BUFHCLK8": null, + "HCLK_DSP_CK_BUFHCLK9": null, + "HCLK_DSP_CK_BUFRCLK0": null, + "HCLK_DSP_CK_BUFRCLK1": null, + "HCLK_DSP_CK_BUFRCLK2": null, + "HCLK_DSP_CK_BUFRCLK3": null, + "HCLK_DSP_CK_IN0": null, + "HCLK_DSP_CK_IN1": null, + "HCLK_DSP_CK_IN10": null, + "HCLK_DSP_CK_IN11": null, + "HCLK_DSP_CK_IN12": null, + "HCLK_DSP_CK_IN13": null, + "HCLK_DSP_CK_IN2": null, + "HCLK_DSP_CK_IN3": null, + "HCLK_DSP_CK_IN4": null, + "HCLK_DSP_CK_IN5": null, + "HCLK_DSP_CK_IN6": null, + "HCLK_DSP_CK_IN7": null, + "HCLK_DSP_CK_IN8": null, + "HCLK_DSP_CK_IN9": null, + "HCLK_DSP_MULTSIGNIN": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN0": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN1": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN10": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN11": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN12": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN13": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN14": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN15": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN16": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN17": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN18": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN19": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN2": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN20": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN21": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN22": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN23": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN24": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN25": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN26": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN27": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN28": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN29": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN3": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN30": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN31": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN32": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN33": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN34": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN35": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN36": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN37": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN38": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN39": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN4": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN40": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN41": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN42": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN43": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN44": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN45": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN46": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN47": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN5": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN6": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN7": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN8": { + "cap": "31.166", + "res": "0.000" + }, + "HCLK_DSP_PCIN9": { + "cap": "31.166", + "res": "0.000" + } + } } diff --git a/zynq7/tile_type_HCLK_FEEDTHRU_1.json b/zynq7/tile_type_HCLK_FEEDTHRU_1.json index 58cd290..7eb6ca1 100644 --- a/zynq7/tile_type_HCLK_FEEDTHRU_1.json +++ b/zynq7/tile_type_HCLK_FEEDTHRU_1.json @@ -2,36 +2,36 @@ "pips": {}, "sites": [], "tile_type": "HCLK_FEEDTHRU_1", - "wires": [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK0", - "HCLK_FEEDTHRU_1_CK_BUFHCLK1", - "HCLK_FEEDTHRU_1_CK_BUFHCLK10", - "HCLK_FEEDTHRU_1_CK_BUFHCLK11", - "HCLK_FEEDTHRU_1_CK_BUFHCLK2", - "HCLK_FEEDTHRU_1_CK_BUFHCLK3", - "HCLK_FEEDTHRU_1_CK_BUFHCLK4", - "HCLK_FEEDTHRU_1_CK_BUFHCLK5", - "HCLK_FEEDTHRU_1_CK_BUFHCLK6", - "HCLK_FEEDTHRU_1_CK_BUFHCLK7", - "HCLK_FEEDTHRU_1_CK_BUFHCLK8", - "HCLK_FEEDTHRU_1_CK_BUFHCLK9", - "HCLK_FEEDTHRU_1_CK_BUFRCLK0", - "HCLK_FEEDTHRU_1_CK_BUFRCLK1", - "HCLK_FEEDTHRU_1_CK_BUFRCLK2", - "HCLK_FEEDTHRU_1_CK_BUFRCLK3", - "HCLK_FEEDTHRU_1_CK_IN0", - "HCLK_FEEDTHRU_1_CK_IN1", - "HCLK_FEEDTHRU_1_CK_IN10", - "HCLK_FEEDTHRU_1_CK_IN11", - "HCLK_FEEDTHRU_1_CK_IN12", - "HCLK_FEEDTHRU_1_CK_IN13", - "HCLK_FEEDTHRU_1_CK_IN2", - "HCLK_FEEDTHRU_1_CK_IN3", - "HCLK_FEEDTHRU_1_CK_IN4", - "HCLK_FEEDTHRU_1_CK_IN5", - "HCLK_FEEDTHRU_1_CK_IN6", - "HCLK_FEEDTHRU_1_CK_IN7", - "HCLK_FEEDTHRU_1_CK_IN8", - "HCLK_FEEDTHRU_1_CK_IN9" - ] + "wires": { + "HCLK_FEEDTHRU_1_CK_BUFHCLK0": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK1": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK10": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK11": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK2": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK3": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK4": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK5": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK6": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK7": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK8": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK9": null, + "HCLK_FEEDTHRU_1_CK_BUFRCLK0": null, + "HCLK_FEEDTHRU_1_CK_BUFRCLK1": null, + "HCLK_FEEDTHRU_1_CK_BUFRCLK2": null, + "HCLK_FEEDTHRU_1_CK_BUFRCLK3": null, + "HCLK_FEEDTHRU_1_CK_IN0": null, + "HCLK_FEEDTHRU_1_CK_IN1": null, + "HCLK_FEEDTHRU_1_CK_IN10": null, + "HCLK_FEEDTHRU_1_CK_IN11": null, + "HCLK_FEEDTHRU_1_CK_IN12": null, + "HCLK_FEEDTHRU_1_CK_IN13": null, + "HCLK_FEEDTHRU_1_CK_IN2": null, + "HCLK_FEEDTHRU_1_CK_IN3": null, + "HCLK_FEEDTHRU_1_CK_IN4": null, + "HCLK_FEEDTHRU_1_CK_IN5": null, + "HCLK_FEEDTHRU_1_CK_IN6": null, + "HCLK_FEEDTHRU_1_CK_IN7": null, + "HCLK_FEEDTHRU_1_CK_IN8": null, + "HCLK_FEEDTHRU_1_CK_IN9": null + } } diff --git a/zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json b/zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json index f874f8e..6f8867b 100644 --- a/zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json +++ b/zynq7/tile_type_HCLK_FEEDTHRU_1_PELE.json @@ -2,68 +2,68 @@ "pips": {}, "sites": [], "tile_type": "HCLK_FEEDTHRU_1_PELE", - "wires": [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK0", - "HCLK_FEEDTHRU_1_CK_BUFHCLK1", - "HCLK_FEEDTHRU_1_CK_BUFHCLK10", - "HCLK_FEEDTHRU_1_CK_BUFHCLK11", - "HCLK_FEEDTHRU_1_CK_BUFHCLK2", - "HCLK_FEEDTHRU_1_CK_BUFHCLK3", - "HCLK_FEEDTHRU_1_CK_BUFHCLK4", - "HCLK_FEEDTHRU_1_CK_BUFHCLK5", - "HCLK_FEEDTHRU_1_CK_BUFHCLK6", - "HCLK_FEEDTHRU_1_CK_BUFHCLK7", - "HCLK_FEEDTHRU_1_CK_BUFHCLK8", - "HCLK_FEEDTHRU_1_CK_BUFHCLK9", - "HCLK_FEEDTHRU_1_CK_BUFRCLK0", - "HCLK_FEEDTHRU_1_CK_BUFRCLK1", - "HCLK_FEEDTHRU_1_CK_BUFRCLK2", - "HCLK_FEEDTHRU_1_CK_BUFRCLK3", - "HCLK_FEEDTHRU_1_CK_IN0", - "HCLK_FEEDTHRU_1_CK_IN1", - "HCLK_FEEDTHRU_1_CK_IN10", - "HCLK_FEEDTHRU_1_CK_IN11", - "HCLK_FEEDTHRU_1_CK_IN12", - "HCLK_FEEDTHRU_1_CK_IN13", - "HCLK_FEEDTHRU_1_CK_IN2", - "HCLK_FEEDTHRU_1_CK_IN3", - "HCLK_FEEDTHRU_1_CK_IN4", - "HCLK_FEEDTHRU_1_CK_IN5", - "HCLK_FEEDTHRU_1_CK_IN6", - "HCLK_FEEDTHRU_1_CK_IN7", - "HCLK_FEEDTHRU_1_CK_IN8", - "HCLK_FEEDTHRU_1_CK_IN9", - "MONITOR_VERT_HCLK_VAUXN0", - "MONITOR_VERT_HCLK_VAUXN1", - "MONITOR_VERT_HCLK_VAUXN10", - "MONITOR_VERT_HCLK_VAUXN11", - "MONITOR_VERT_HCLK_VAUXN12", - "MONITOR_VERT_HCLK_VAUXN13", - "MONITOR_VERT_HCLK_VAUXN14", - "MONITOR_VERT_HCLK_VAUXN15", - "MONITOR_VERT_HCLK_VAUXN2", - "MONITOR_VERT_HCLK_VAUXN3", - "MONITOR_VERT_HCLK_VAUXN4", - "MONITOR_VERT_HCLK_VAUXN5", - "MONITOR_VERT_HCLK_VAUXN6", - "MONITOR_VERT_HCLK_VAUXN7", - "MONITOR_VERT_HCLK_VAUXN8", - "MONITOR_VERT_HCLK_VAUXN9", - "MONITOR_VERT_HCLK_VAUXP0", - "MONITOR_VERT_HCLK_VAUXP1", - "MONITOR_VERT_HCLK_VAUXP10", - "MONITOR_VERT_HCLK_VAUXP11", - "MONITOR_VERT_HCLK_VAUXP12", - "MONITOR_VERT_HCLK_VAUXP13", - "MONITOR_VERT_HCLK_VAUXP14", - "MONITOR_VERT_HCLK_VAUXP15", - "MONITOR_VERT_HCLK_VAUXP2", - "MONITOR_VERT_HCLK_VAUXP3", - "MONITOR_VERT_HCLK_VAUXP4", - "MONITOR_VERT_HCLK_VAUXP5", - "MONITOR_VERT_HCLK_VAUXP6", - "MONITOR_VERT_HCLK_VAUXP7", - "MONITOR_VERT_HCLK_VAUXP8", - "MONITOR_VERT_HCLK_VAUXP9" - ] + "wires": { + "HCLK_FEEDTHRU_1_CK_BUFHCLK0": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK1": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK10": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK11": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK2": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK3": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK4": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK5": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK6": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK7": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK8": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK9": null, + "HCLK_FEEDTHRU_1_CK_BUFRCLK0": null, + "HCLK_FEEDTHRU_1_CK_BUFRCLK1": null, + "HCLK_FEEDTHRU_1_CK_BUFRCLK2": null, + "HCLK_FEEDTHRU_1_CK_BUFRCLK3": null, + "HCLK_FEEDTHRU_1_CK_IN0": null, + "HCLK_FEEDTHRU_1_CK_IN1": null, + "HCLK_FEEDTHRU_1_CK_IN10": null, + "HCLK_FEEDTHRU_1_CK_IN11": null, + "HCLK_FEEDTHRU_1_CK_IN12": null, + "HCLK_FEEDTHRU_1_CK_IN13": null, + "HCLK_FEEDTHRU_1_CK_IN2": null, + "HCLK_FEEDTHRU_1_CK_IN3": null, + "HCLK_FEEDTHRU_1_CK_IN4": null, + "HCLK_FEEDTHRU_1_CK_IN5": null, + "HCLK_FEEDTHRU_1_CK_IN6": null, + "HCLK_FEEDTHRU_1_CK_IN7": null, + "HCLK_FEEDTHRU_1_CK_IN8": null, + "HCLK_FEEDTHRU_1_CK_IN9": null, + "MONITOR_VERT_HCLK_VAUXN0": null, + "MONITOR_VERT_HCLK_VAUXN1": null, + "MONITOR_VERT_HCLK_VAUXN10": null, + "MONITOR_VERT_HCLK_VAUXN11": null, + "MONITOR_VERT_HCLK_VAUXN12": null, + "MONITOR_VERT_HCLK_VAUXN13": null, + "MONITOR_VERT_HCLK_VAUXN14": null, + "MONITOR_VERT_HCLK_VAUXN15": null, + "MONITOR_VERT_HCLK_VAUXN2": null, + "MONITOR_VERT_HCLK_VAUXN3": null, + "MONITOR_VERT_HCLK_VAUXN4": null, + "MONITOR_VERT_HCLK_VAUXN5": null, + "MONITOR_VERT_HCLK_VAUXN6": null, + "MONITOR_VERT_HCLK_VAUXN7": null, + "MONITOR_VERT_HCLK_VAUXN8": null, + "MONITOR_VERT_HCLK_VAUXN9": null, + "MONITOR_VERT_HCLK_VAUXP0": null, + "MONITOR_VERT_HCLK_VAUXP1": null, + "MONITOR_VERT_HCLK_VAUXP10": null, + "MONITOR_VERT_HCLK_VAUXP11": null, + "MONITOR_VERT_HCLK_VAUXP12": null, + "MONITOR_VERT_HCLK_VAUXP13": null, + "MONITOR_VERT_HCLK_VAUXP14": null, + "MONITOR_VERT_HCLK_VAUXP15": null, + "MONITOR_VERT_HCLK_VAUXP2": null, + "MONITOR_VERT_HCLK_VAUXP3": null, + "MONITOR_VERT_HCLK_VAUXP4": null, + "MONITOR_VERT_HCLK_VAUXP5": null, + "MONITOR_VERT_HCLK_VAUXP6": null, + "MONITOR_VERT_HCLK_VAUXP7": null, + "MONITOR_VERT_HCLK_VAUXP8": null, + "MONITOR_VERT_HCLK_VAUXP9": null + } } diff --git a/zynq7/tile_type_HCLK_FEEDTHRU_2.json b/zynq7/tile_type_HCLK_FEEDTHRU_2.json index df05939..076baf9 100644 --- a/zynq7/tile_type_HCLK_FEEDTHRU_2.json +++ b/zynq7/tile_type_HCLK_FEEDTHRU_2.json @@ -2,36 +2,36 @@ "pips": {}, "sites": [], "tile_type": "HCLK_FEEDTHRU_2", - "wires": [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK0", - "HCLK_FEEDTHRU_2_CK_BUFHCLK1", - "HCLK_FEEDTHRU_2_CK_BUFHCLK10", - "HCLK_FEEDTHRU_2_CK_BUFHCLK11", - "HCLK_FEEDTHRU_2_CK_BUFHCLK2", - "HCLK_FEEDTHRU_2_CK_BUFHCLK3", - "HCLK_FEEDTHRU_2_CK_BUFHCLK4", - "HCLK_FEEDTHRU_2_CK_BUFHCLK5", - "HCLK_FEEDTHRU_2_CK_BUFHCLK6", - "HCLK_FEEDTHRU_2_CK_BUFHCLK7", - "HCLK_FEEDTHRU_2_CK_BUFHCLK8", - "HCLK_FEEDTHRU_2_CK_BUFHCLK9", - "HCLK_FEEDTHRU_2_CK_BUFRCLK0", - "HCLK_FEEDTHRU_2_CK_BUFRCLK1", - "HCLK_FEEDTHRU_2_CK_BUFRCLK2", - "HCLK_FEEDTHRU_2_CK_BUFRCLK3", - "HCLK_FEEDTHRU_2_CK_IN0", - "HCLK_FEEDTHRU_2_CK_IN1", - "HCLK_FEEDTHRU_2_CK_IN10", - "HCLK_FEEDTHRU_2_CK_IN11", - "HCLK_FEEDTHRU_2_CK_IN12", - "HCLK_FEEDTHRU_2_CK_IN13", - "HCLK_FEEDTHRU_2_CK_IN2", - "HCLK_FEEDTHRU_2_CK_IN3", - "HCLK_FEEDTHRU_2_CK_IN4", - "HCLK_FEEDTHRU_2_CK_IN5", - "HCLK_FEEDTHRU_2_CK_IN6", - "HCLK_FEEDTHRU_2_CK_IN7", - "HCLK_FEEDTHRU_2_CK_IN8", - "HCLK_FEEDTHRU_2_CK_IN9" - ] + "wires": { + "HCLK_FEEDTHRU_2_CK_BUFHCLK0": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK1": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK10": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK11": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK2": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK3": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK4": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK5": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK6": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK7": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK8": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK9": null, + "HCLK_FEEDTHRU_2_CK_BUFRCLK0": null, + "HCLK_FEEDTHRU_2_CK_BUFRCLK1": null, + "HCLK_FEEDTHRU_2_CK_BUFRCLK2": null, + "HCLK_FEEDTHRU_2_CK_BUFRCLK3": null, + "HCLK_FEEDTHRU_2_CK_IN0": null, + "HCLK_FEEDTHRU_2_CK_IN1": null, + "HCLK_FEEDTHRU_2_CK_IN10": null, + "HCLK_FEEDTHRU_2_CK_IN11": null, + "HCLK_FEEDTHRU_2_CK_IN12": null, + "HCLK_FEEDTHRU_2_CK_IN13": null, + "HCLK_FEEDTHRU_2_CK_IN2": null, + "HCLK_FEEDTHRU_2_CK_IN3": null, + "HCLK_FEEDTHRU_2_CK_IN4": null, + "HCLK_FEEDTHRU_2_CK_IN5": null, + "HCLK_FEEDTHRU_2_CK_IN6": null, + "HCLK_FEEDTHRU_2_CK_IN7": null, + "HCLK_FEEDTHRU_2_CK_IN8": null, + "HCLK_FEEDTHRU_2_CK_IN9": null + } } diff --git a/zynq7/tile_type_HCLK_FIFO_L.json b/zynq7/tile_type_HCLK_FIFO_L.json index 258356f..5b11755 100644 --- a/zynq7/tile_type_HCLK_FIFO_L.json +++ b/zynq7/tile_type_HCLK_FIFO_L.json @@ -2,44 +2,44 @@ "pips": {}, "sites": [], "tile_type": "HCLK_FIFO_L", - "wires": [ - "HCLK_FIFO_CCIO0", - "HCLK_FIFO_CCIO1", - "HCLK_FIFO_CCIO2", - "HCLK_FIFO_CCIO3", - "HCLK_FIFO_CK_BUFHCLK0", - "HCLK_FIFO_CK_BUFHCLK1", - "HCLK_FIFO_CK_BUFHCLK10", - "HCLK_FIFO_CK_BUFHCLK11", - "HCLK_FIFO_CK_BUFHCLK2", - "HCLK_FIFO_CK_BUFHCLK3", - "HCLK_FIFO_CK_BUFHCLK4", - "HCLK_FIFO_CK_BUFHCLK5", - "HCLK_FIFO_CK_BUFHCLK6", - "HCLK_FIFO_CK_BUFHCLK7", - "HCLK_FIFO_CK_BUFHCLK8", - "HCLK_FIFO_CK_BUFHCLK9", - "HCLK_FIFO_CK_BUFRCLK0", - "HCLK_FIFO_CK_BUFRCLK1", - "HCLK_FIFO_CK_BUFRCLK2", - "HCLK_FIFO_CK_BUFRCLK3", - "HCLK_FIFO_CK_IN0", - "HCLK_FIFO_CK_IN1", - "HCLK_FIFO_CK_IN10", - "HCLK_FIFO_CK_IN11", - "HCLK_FIFO_CK_IN12", - "HCLK_FIFO_CK_IN13", - "HCLK_FIFO_CK_IN2", - "HCLK_FIFO_CK_IN3", - "HCLK_FIFO_CK_IN4", - "HCLK_FIFO_CK_IN5", - "HCLK_FIFO_CK_IN6", - "HCLK_FIFO_CK_IN7", - "HCLK_FIFO_CK_IN8", - "HCLK_FIFO_CK_IN9", - "HCLK_FIFO_PERFCLK0", - "HCLK_FIFO_PERFCLK1", - "HCLK_FIFO_PERFCLK2", - "HCLK_FIFO_PERFCLK3" - ] + "wires": { + "HCLK_FIFO_CCIO0": null, + "HCLK_FIFO_CCIO1": null, + "HCLK_FIFO_CCIO2": null, + "HCLK_FIFO_CCIO3": null, + "HCLK_FIFO_CK_BUFHCLK0": null, + "HCLK_FIFO_CK_BUFHCLK1": null, + "HCLK_FIFO_CK_BUFHCLK10": null, + "HCLK_FIFO_CK_BUFHCLK11": null, + "HCLK_FIFO_CK_BUFHCLK2": null, + "HCLK_FIFO_CK_BUFHCLK3": null, + "HCLK_FIFO_CK_BUFHCLK4": null, + "HCLK_FIFO_CK_BUFHCLK5": null, + "HCLK_FIFO_CK_BUFHCLK6": null, + "HCLK_FIFO_CK_BUFHCLK7": null, + "HCLK_FIFO_CK_BUFHCLK8": null, + "HCLK_FIFO_CK_BUFHCLK9": null, + "HCLK_FIFO_CK_BUFRCLK0": null, + "HCLK_FIFO_CK_BUFRCLK1": null, + "HCLK_FIFO_CK_BUFRCLK2": null, + "HCLK_FIFO_CK_BUFRCLK3": null, + "HCLK_FIFO_CK_IN0": null, + "HCLK_FIFO_CK_IN1": null, + "HCLK_FIFO_CK_IN10": null, + "HCLK_FIFO_CK_IN11": null, + "HCLK_FIFO_CK_IN12": null, + "HCLK_FIFO_CK_IN13": null, + "HCLK_FIFO_CK_IN2": null, + "HCLK_FIFO_CK_IN3": null, + "HCLK_FIFO_CK_IN4": null, + "HCLK_FIFO_CK_IN5": null, + "HCLK_FIFO_CK_IN6": null, + "HCLK_FIFO_CK_IN7": null, + "HCLK_FIFO_CK_IN8": null, + "HCLK_FIFO_CK_IN9": null, + "HCLK_FIFO_PERFCLK0": null, + "HCLK_FIFO_PERFCLK1": null, + "HCLK_FIFO_PERFCLK2": null, + "HCLK_FIFO_PERFCLK3": null + } } diff --git a/zynq7/tile_type_HCLK_INT_INTERFACE.json b/zynq7/tile_type_HCLK_INT_INTERFACE.json index 93e55e2..df45c5e 100644 --- a/zynq7/tile_type_HCLK_INT_INTERFACE.json +++ b/zynq7/tile_type_HCLK_INT_INTERFACE.json @@ -2,48 +2,48 @@ "pips": {}, "sites": [], "tile_type": "HCLK_INT_INTERFACE", - "wires": [ - "HCLK_INT_INTERFACE_CCIO0", - "HCLK_INT_INTERFACE_CCIO1", - "HCLK_INT_INTERFACE_CCIO2", - "HCLK_INT_INTERFACE_CCIO3", - "HCLK_INT_INTERFACE_CK_BUFHCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK10", - "HCLK_INT_INTERFACE_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_BUFRCLK3", - "HCLK_INT_INTERFACE_CK_IN0", - "HCLK_INT_INTERFACE_CK_IN1", - "HCLK_INT_INTERFACE_CK_IN10", - "HCLK_INT_INTERFACE_CK_IN11", - "HCLK_INT_INTERFACE_CK_IN12", - "HCLK_INT_INTERFACE_CK_IN13", - "HCLK_INT_INTERFACE_CK_IN2", - "HCLK_INT_INTERFACE_CK_IN3", - "HCLK_INT_INTERFACE_CK_IN4", - "HCLK_INT_INTERFACE_CK_IN5", - "HCLK_INT_INTERFACE_CK_IN6", - "HCLK_INT_INTERFACE_CK_IN7", - "HCLK_INT_INTERFACE_CK_IN8", - "HCLK_INT_INTERFACE_CK_IN9", - "HCLK_INT_INTERFACE_PERFCLK0", - "HCLK_INT_INTERFACE_PERFCLK1", - "HCLK_INT_INTERFACE_PERFCLK2", - "HCLK_INT_INTERFACE_PERFCLK3", - "HCLK_INT_INTERFACE_REFCK_EASTCLK0", - "HCLK_INT_INTERFACE_REFCK_EASTCLK1", - "HCLK_INT_INTERFACE_REFCK_WESTCLK0", - "HCLK_INT_INTERFACE_REFCK_WESTCLK1" - ] + "wires": { + "HCLK_INT_INTERFACE_CCIO0": null, + "HCLK_INT_INTERFACE_CCIO1": null, + "HCLK_INT_INTERFACE_CCIO2": null, + "HCLK_INT_INTERFACE_CCIO3": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK0": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK1": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK10": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK11": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK2": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK3": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK4": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK5": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK6": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK7": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK8": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK9": null, + "HCLK_INT_INTERFACE_CK_BUFRCLK0": null, + "HCLK_INT_INTERFACE_CK_BUFRCLK1": null, + "HCLK_INT_INTERFACE_CK_BUFRCLK2": null, + "HCLK_INT_INTERFACE_CK_BUFRCLK3": null, + "HCLK_INT_INTERFACE_CK_IN0": null, + "HCLK_INT_INTERFACE_CK_IN1": null, + "HCLK_INT_INTERFACE_CK_IN10": null, + "HCLK_INT_INTERFACE_CK_IN11": null, + "HCLK_INT_INTERFACE_CK_IN12": null, + "HCLK_INT_INTERFACE_CK_IN13": null, + "HCLK_INT_INTERFACE_CK_IN2": null, + "HCLK_INT_INTERFACE_CK_IN3": null, + "HCLK_INT_INTERFACE_CK_IN4": null, + "HCLK_INT_INTERFACE_CK_IN5": null, + "HCLK_INT_INTERFACE_CK_IN6": null, + "HCLK_INT_INTERFACE_CK_IN7": null, + "HCLK_INT_INTERFACE_CK_IN8": null, + "HCLK_INT_INTERFACE_CK_IN9": null, + "HCLK_INT_INTERFACE_PERFCLK0": null, + "HCLK_INT_INTERFACE_PERFCLK1": null, + "HCLK_INT_INTERFACE_PERFCLK2": null, + "HCLK_INT_INTERFACE_PERFCLK3": null, + "HCLK_INT_INTERFACE_REFCK_EASTCLK0": null, + "HCLK_INT_INTERFACE_REFCK_EASTCLK1": null, + "HCLK_INT_INTERFACE_REFCK_WESTCLK0": null, + "HCLK_INT_INTERFACE_REFCK_WESTCLK1": null + } } diff --git a/zynq7/tile_type_HCLK_IOB.json b/zynq7/tile_type_HCLK_IOB.json index bf06214..c2b3463 100644 --- a/zynq7/tile_type_HCLK_IOB.json +++ b/zynq7/tile_type_HCLK_IOB.json @@ -2,40 +2,82 @@ "pips": {}, "sites": [], "tile_type": "HCLK_IOB", - "wires": [ - "HCLK_IOB_CK_BUFHCLK0", - "HCLK_IOB_CK_BUFHCLK1", - "HCLK_IOB_CK_BUFHCLK10", - "HCLK_IOB_CK_BUFHCLK11", - "HCLK_IOB_CK_BUFHCLK2", - "HCLK_IOB_CK_BUFHCLK3", - "HCLK_IOB_CK_BUFHCLK4", - "HCLK_IOB_CK_BUFHCLK5", - "HCLK_IOB_CK_BUFHCLK6", - "HCLK_IOB_CK_BUFHCLK7", - "HCLK_IOB_CK_BUFHCLK8", - "HCLK_IOB_CK_BUFHCLK9", - "HCLK_IOB_CK_BUFRCLK0", - "HCLK_IOB_CK_BUFRCLK1", - "HCLK_IOB_CK_BUFRCLK2", - "HCLK_IOB_CK_BUFRCLK3", - "HCLK_IOB_CK_IN0", - "HCLK_IOB_CK_IN1", - "HCLK_IOB_CK_IN10", - "HCLK_IOB_CK_IN11", - "HCLK_IOB_CK_IN12", - "HCLK_IOB_CK_IN13", - "HCLK_IOB_CK_IN2", - "HCLK_IOB_CK_IN3", - "HCLK_IOB_CK_IN4", - "HCLK_IOB_CK_IN5", - "HCLK_IOB_CK_IN6", - "HCLK_IOB_CK_IN7", - "HCLK_IOB_CK_IN8", - "HCLK_IOB_CK_IN9", - "HCLK_IOB_PERFCLK0", - "HCLK_IOB_PERFCLK1", - "HCLK_IOB_PERFCLK2", - "HCLK_IOB_PERFCLK3" - ] + "wires": { + "HCLK_IOB_CK_BUFHCLK0": null, + "HCLK_IOB_CK_BUFHCLK1": null, + "HCLK_IOB_CK_BUFHCLK10": null, + "HCLK_IOB_CK_BUFHCLK11": null, + "HCLK_IOB_CK_BUFHCLK2": null, + "HCLK_IOB_CK_BUFHCLK3": null, + "HCLK_IOB_CK_BUFHCLK4": null, + "HCLK_IOB_CK_BUFHCLK5": null, + "HCLK_IOB_CK_BUFHCLK6": null, + "HCLK_IOB_CK_BUFHCLK7": null, + "HCLK_IOB_CK_BUFHCLK8": null, + "HCLK_IOB_CK_BUFHCLK9": null, + "HCLK_IOB_CK_BUFRCLK0": null, + "HCLK_IOB_CK_BUFRCLK1": null, + "HCLK_IOB_CK_BUFRCLK2": null, + "HCLK_IOB_CK_BUFRCLK3": null, + "HCLK_IOB_CK_IN0": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_CK_IN1": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_CK_IN10": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_CK_IN11": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_CK_IN12": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_CK_IN13": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_CK_IN2": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_CK_IN3": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_CK_IN4": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_CK_IN5": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_CK_IN6": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_CK_IN7": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_CK_IN8": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_CK_IN9": { + "cap": "0.001", + "res": "0.001" + }, + "HCLK_IOB_PERFCLK0": null, + "HCLK_IOB_PERFCLK1": null, + "HCLK_IOB_PERFCLK2": null, + "HCLK_IOB_PERFCLK3": null + } } diff --git a/zynq7/tile_type_HCLK_IOI3.json b/zynq7/tile_type_HCLK_IOI3.json index 422034a..47fa6b7 100644 --- a/zynq7/tile_type_HCLK_IOI3.json +++ b/zynq7/tile_type_HCLK_IOI3.json @@ -2,1710 +2,6754 @@ "pips": { "HCLK_IOI3.HCLK_IOI_BUFIO_O0->>HCLK_IOI_IOCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_IOCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_BUFIO_O0" }, "HCLK_IOI3.HCLK_IOI_BUFIO_O1->>HCLK_IOI_IOCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_IOCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_BUFIO_O1" }, "HCLK_IOI3.HCLK_IOI_BUFIO_O2->>HCLK_IOI_IOCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_IOCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_BUFIO_O2" }, "HCLK_IOI3.HCLK_IOI_BUFIO_O3->>HCLK_IOI_IOCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_IOCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_BUFIO_O3" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK0->>HCLK_IOI_CK_IGCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK1->>HCLK_IOI_CK_IGCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK10->>HCLK_IOI_CK_IGCLK10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK10" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK11->>HCLK_IOI_CK_IGCLK11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK11" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK2->>HCLK_IOI_CK_IGCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK2" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK3->>HCLK_IOI_CK_IGCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK3" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK4->>HCLK_IOI_CK_IGCLK4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK4" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK5->>HCLK_IOI_CK_IGCLK5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK5" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK6->>HCLK_IOI_CK_IGCLK6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK6" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK7->>HCLK_IOI_CK_IGCLK7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK7" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK8->>HCLK_IOI_CK_IGCLK8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK9->>HCLK_IOI_CK_IGCLK9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.139", + "0.335", + "0.368" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK0->>HCLK_IOI_RCLK2IO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.148", + "0.170", + "0.405", + "0.447" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_RCLK2IO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.148", + "0.170", + "0.405", + "0.447" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_BUFRCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK1->>HCLK_IOI_RCLK2IO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.148", + "0.170", + "0.405", + "0.447" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_RCLK2IO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.148", + "0.170", + "0.405", + "0.447" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_BUFRCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK2->>HCLK_IOI_RCLK2IO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.148", + "0.170", + "0.405", + "0.447" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_RCLK2IO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.148", + "0.170", + "0.405", + "0.447" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_BUFRCLK2" }, "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK3->>HCLK_IOI_RCLK2IO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.148", + "0.170", + "0.405", + "0.447" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_RCLK2IO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.148", + "0.170", + "0.405", + "0.447" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_BUFRCLK3" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + 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"delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + 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}, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, 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"dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": 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"0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": 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"delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_I2IOCLK_BOT0->>HCLK_IOI_IO_PLL_CLK2_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.190", + "0.195", + "0.206" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.190", + "0.195", + "0.206" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_I2IOCLK_BOT0" }, "HCLK_IOI3.HCLK_IOI_I2IOCLK_BOT1->>HCLK_IOI_IO_PLL_CLK3_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.190", + "0.195", + "0.206" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.190", + "0.195", + "0.206" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_I2IOCLK_BOT1" }, "HCLK_IOI3.HCLK_IOI_I2IOCLK_TOP0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.190", + "0.195", + "0.206" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.190", + "0.195", + "0.206" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_I2IOCLK_TOP0" }, "HCLK_IOI3.HCLK_IOI_I2IOCLK_TOP1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.190", + "0.195", + "0.206" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.100", + "0.190", + "0.195", + "0.206" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_I2IOCLK_TOP1" }, "HCLK_IOI3.HCLK_IOI_IOCLK_PLL0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_IOCLK_PLL0" }, "HCLK_IOI3.HCLK_IOI_IOCLK_PLL1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_IOCLK_PLL1" }, "HCLK_IOI3.HCLK_IOI_IOCLK_PLL2->>HCLK_IOI_IO_PLL_CLK2_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_IOCLK_PLL2" }, "HCLK_IOI3.HCLK_IOI_IOCLK_PLL3->>HCLK_IOI_IO_PLL_CLK3_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_IOCLK_PLL3" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_IO_PLL_CLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.032", + "0.036", + "0.063", + "0.073" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.032", + "0.036", + "0.063", + "0.073" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_RCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.059", + "0.067", + "0.152", + "0.175" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.059", + "0.067", + "0.152", + "0.175" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_IO_PLL_CLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.032", + "0.036", + "0.063", + "0.073" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.032", + "0.036", + "0.063", + "0.073" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_RCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.059", + "0.067", + "0.152", + "0.175" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.059", + "0.067", + "0.152", + "0.175" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_IO_PLL_CLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.032", + "0.036", + "0.063", + "0.073" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.032", + "0.036", + "0.063", + "0.073" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_RCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.059", + "0.067", + "0.152", + "0.175" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.059", + "0.067", + "0.152", + "0.175" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_IO_PLL_CLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.032", + "0.036", + "0.063", + "0.073" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.032", + "0.036", + "0.063", + "0.073" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_RCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.059", + "0.067", + "0.152", + "0.175" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.059", + "0.067", + "0.152", + "0.175" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT0->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT0" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT1->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT1" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT2->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT2" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT3->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT3" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT4->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT4" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT5->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT5" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP0->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP0" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP1->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP1" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP2->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP2" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP3->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP3" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP4->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP4" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP5->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP5" }, "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK1" }, "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX2" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI3.HCLK_IOI_RCLK_OUT0->>HCLK_IOI_RCLK2RCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2RCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_OUT0" }, "HCLK_IOI3.HCLK_IOI_RCLK_OUT1->>HCLK_IOI_RCLK2RCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2RCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_OUT1" }, "HCLK_IOI3.HCLK_IOI_RCLK_OUT2->>HCLK_IOI_RCLK2RCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2RCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_OUT2" }, "HCLK_IOI3.HCLK_IOI_RCLK_OUT3->>HCLK_IOI_RCLK2RCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2RCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_OUT3" }, "HCLK_IOI3.HCLK_RCLK_DIV_CE0->HCLK_IOI_BUFR0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CE0" }, "HCLK_IOI3.HCLK_RCLK_DIV_CE1->HCLK_IOI_BUFR1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CE1" }, "HCLK_IOI3.HCLK_RCLK_DIV_CE2->HCLK_IOI_BUFR2_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR2_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CE2" }, "HCLK_IOI3.HCLK_RCLK_DIV_CE3->HCLK_IOI_BUFR3_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR3_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CE3" }, "HCLK_IOI3.HCLK_RCLK_DIV_CLR0->HCLK_IOI_BUFR0_CLR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR0_CLR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CLR0" }, "HCLK_IOI3.HCLK_RCLK_DIV_CLR1->HCLK_IOI_BUFR1_CLR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR1_CLR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CLR1" }, "HCLK_IOI3.HCLK_RCLK_DIV_CLR2->HCLK_IOI_BUFR2_CLR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR2_CLR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CLR2" }, "HCLK_IOI3.HCLK_RCLK_DIV_CLR3->HCLK_IOI_BUFR3_CLR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR3_CLR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CLR3" } }, @@ -1714,8 +6758,26 @@ "name": "X0Y1", "prefix": "BUFIO", "site_pins": { - "I": "HCLK_IOI_IO_PLL_CLK3", - "O": "HCLK_IOI_BUFIO_O3" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IO_PLL_CLK3" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_BUFIO_O3" + } }, "type": "BUFIO", "x_coord": 0, @@ -1725,8 +6787,26 @@ "name": "X0Y0", "prefix": "BUFIO", "site_pins": { - "I": "HCLK_IOI_IO_PLL_CLK2", - "O": "HCLK_IOI_BUFIO_O2" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IO_PLL_CLK2" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_BUFIO_O2" + } }, "type": "BUFIO", "x_coord": 0, @@ -1736,8 +6816,26 @@ "name": "X0Y3", "prefix": "BUFIO", "site_pins": { - "I": "HCLK_IOI_IO_PLL_CLK1", - "O": "HCLK_IOI_BUFIO_O1" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IO_PLL_CLK1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_BUFIO_O1" + } }, "type": "BUFIO", "x_coord": 0, @@ -1747,8 +6845,26 @@ "name": "X0Y2", "prefix": "BUFIO", "site_pins": { - "I": "HCLK_IOI_IO_PLL_CLK0", - "O": "HCLK_IOI_BUFIO_O0" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IO_PLL_CLK0" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_BUFIO_O0" + } }, "type": "BUFIO", "x_coord": 0, @@ -1758,10 +6874,46 @@ "name": "X0Y1", "prefix": "BUFR", "site_pins": { - "CE": "HCLK_IOI_BUFR3_CE", - "CLR": "HCLK_IOI_BUFR3_CLR", - "I": "HCLK_IOI_RCLK_BEFORE_DIV3", - "O": "HCLK_IOI_RCLK_OUT3" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR3_CE" + }, + "CLR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR3_CLR" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_RCLK_BEFORE_DIV3" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_RCLK_OUT3" + } }, "type": "BUFR", "x_coord": 0, @@ -1771,10 +6923,46 @@ "name": "X0Y0", "prefix": "BUFR", "site_pins": { - "CE": "HCLK_IOI_BUFR2_CE", - "CLR": "HCLK_IOI_BUFR2_CLR", - "I": "HCLK_IOI_RCLK_BEFORE_DIV2", - "O": "HCLK_IOI_RCLK_OUT2" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR2_CE" + }, + "CLR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR2_CLR" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_RCLK_BEFORE_DIV2" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_RCLK_OUT2" + } }, "type": "BUFR", "x_coord": 0, @@ -1784,10 +6972,46 @@ "name": "X0Y3", "prefix": "BUFR", "site_pins": { - "CE": "HCLK_IOI_BUFR1_CE", - "CLR": "HCLK_IOI_BUFR1_CLR", - "I": "HCLK_IOI_RCLK_BEFORE_DIV1", - "O": "HCLK_IOI_RCLK_OUT1" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR1_CE" + }, + "CLR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR1_CLR" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_RCLK_BEFORE_DIV1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_RCLK_OUT1" + } }, "type": "BUFR", "x_coord": 0, @@ -1797,10 +7021,46 @@ "name": "X0Y2", "prefix": "BUFR", "site_pins": { - "CE": "HCLK_IOI_BUFR0_CE", - "CLR": "HCLK_IOI_BUFR0_CLR", - "I": "HCLK_IOI_RCLK_BEFORE_DIV0", - "O": "HCLK_IOI_RCLK_OUT0" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR0_CE" + }, + "CLR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR0_CLR" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_RCLK_BEFORE_DIV0" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_RCLK_OUT0" + } }, "type": "BUFR", "x_coord": 0, @@ -1810,13 +7070,76 @@ "name": "X0Y0", "prefix": "IDELAYCTRL", "site_pins": { - "DNPULSEOUT": "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", - "OUTN1": "HCLK_IOI_IDELAYCTRL_OUTN1", - "OUTN65": "HCLK_IOI_IDELAYCTRL_OUTN65", - "RDY": "HCLK_IOI_IDELAYCTRL_RDY", - "REFCLK": "HCLK_IOI_IDELAYCTRL_REFCLK", - "RST": "HCLK_IOI_IDELAYCTRL_RST", - "UPPULSEOUT": "HCLK_IOI_IDELAYCTRL_UPPULSEOUT" + "DNPULSEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_IDELAYCTRL_DNPULSEOUT" + }, + "OUTN1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_IDELAYCTRL_OUTN1" + }, + "OUTN65": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_IDELAYCTRL_OUTN65" + }, + "RDY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_IDELAYCTRL_RDY" + }, + "REFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "RST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IDELAYCTRL_RST" + }, + "UPPULSEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_IDELAYCTRL_UPPULSEOUT" + } }, "type": "IDELAYCTRL", "x_coord": 0, @@ -1824,131 +7147,131 @@ } ], "tile_type": "HCLK_IOI3", - "wires": [ - "HCLK_IOI_BUFIO_O0", - "HCLK_IOI_BUFIO_O1", - "HCLK_IOI_BUFIO_O2", - "HCLK_IOI_BUFIO_O3", - "HCLK_IOI_BUFR0_CE", - "HCLK_IOI_BUFR0_CLR", - "HCLK_IOI_BUFR1_CE", - "HCLK_IOI_BUFR1_CLR", - "HCLK_IOI_BUFR2_CE", - "HCLK_IOI_BUFR2_CLR", - "HCLK_IOI_BUFR3_CE", - "HCLK_IOI_BUFR3_CLR", - "HCLK_IOI_CK_BUFHCLK0", - "HCLK_IOI_CK_BUFHCLK1", - "HCLK_IOI_CK_BUFHCLK10", - "HCLK_IOI_CK_BUFHCLK11", - "HCLK_IOI_CK_BUFHCLK2", - "HCLK_IOI_CK_BUFHCLK3", - "HCLK_IOI_CK_BUFHCLK4", - "HCLK_IOI_CK_BUFHCLK5", - "HCLK_IOI_CK_BUFHCLK6", - "HCLK_IOI_CK_BUFHCLK7", - "HCLK_IOI_CK_BUFHCLK8", - "HCLK_IOI_CK_BUFHCLK9", - "HCLK_IOI_CK_BUFRCLK0", - "HCLK_IOI_CK_BUFRCLK1", - "HCLK_IOI_CK_BUFRCLK2", - "HCLK_IOI_CK_BUFRCLK3", - "HCLK_IOI_CK_IGCLK0", - "HCLK_IOI_CK_IGCLK1", - "HCLK_IOI_CK_IGCLK10", - "HCLK_IOI_CK_IGCLK11", - "HCLK_IOI_CK_IGCLK2", - "HCLK_IOI_CK_IGCLK3", - "HCLK_IOI_CK_IGCLK4", - "HCLK_IOI_CK_IGCLK5", - "HCLK_IOI_CK_IGCLK6", - "HCLK_IOI_CK_IGCLK7", - "HCLK_IOI_CK_IGCLK8", - "HCLK_IOI_CK_IGCLK9", - "HCLK_IOI_CK_IN0", - "HCLK_IOI_CK_IN1", - "HCLK_IOI_CK_IN10", - "HCLK_IOI_CK_IN11", - "HCLK_IOI_CK_IN12", - "HCLK_IOI_CK_IN13", - "HCLK_IOI_CK_IN2", - "HCLK_IOI_CK_IN3", - "HCLK_IOI_CK_IN4", - "HCLK_IOI_CK_IN5", - "HCLK_IOI_CK_IN6", - "HCLK_IOI_CK_IN7", - "HCLK_IOI_CK_IN8", - "HCLK_IOI_CK_IN9", - "HCLK_IOI_I2IOCLK_BOT0", - "HCLK_IOI_I2IOCLK_BOT1", - "HCLK_IOI_I2IOCLK_TOP0", - "HCLK_IOI_I2IOCLK_TOP1", - "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", - "HCLK_IOI_IDELAYCTRL_OUTN1", - "HCLK_IOI_IDELAYCTRL_OUTN65", - "HCLK_IOI_IDELAYCTRL_RDY", - "HCLK_IOI_IDELAYCTRL_REFCLK", - "HCLK_IOI_IDELAYCTRL_RST", - "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", - "HCLK_IOI_IOCLK0", - "HCLK_IOI_IOCLK1", - "HCLK_IOI_IOCLK2", - "HCLK_IOI_IOCLK3", - "HCLK_IOI_IOCLK_PLL0", - "HCLK_IOI_IOCLK_PLL1", - "HCLK_IOI_IOCLK_PLL2", - "HCLK_IOI_IOCLK_PLL3", - "HCLK_IOI_IO_PLL_CLK0", - "HCLK_IOI_IO_PLL_CLK0_DMUX", - "HCLK_IOI_IO_PLL_CLK1", - "HCLK_IOI_IO_PLL_CLK1_DMUX", - "HCLK_IOI_IO_PLL_CLK2", - "HCLK_IOI_IO_PLL_CLK2_DMUX", - "HCLK_IOI_IO_PLL_CLK3", - "HCLK_IOI_IO_PLL_CLK3_DMUX", - "HCLK_IOI_LEAF_GCLK_BOT0", - "HCLK_IOI_LEAF_GCLK_BOT1", - "HCLK_IOI_LEAF_GCLK_BOT2", - "HCLK_IOI_LEAF_GCLK_BOT3", - "HCLK_IOI_LEAF_GCLK_BOT4", - "HCLK_IOI_LEAF_GCLK_BOT5", - "HCLK_IOI_LEAF_GCLK_TOP0", - "HCLK_IOI_LEAF_GCLK_TOP1", - "HCLK_IOI_LEAF_GCLK_TOP2", - "HCLK_IOI_LEAF_GCLK_TOP3", - "HCLK_IOI_LEAF_GCLK_TOP4", - "HCLK_IOI_LEAF_GCLK_TOP5", - "HCLK_IOI_RCLK0", - "HCLK_IOI_RCLK1", - "HCLK_IOI_RCLK2", - "HCLK_IOI_RCLK2IO0", - "HCLK_IOI_RCLK2IO1", - "HCLK_IOI_RCLK2IO2", - "HCLK_IOI_RCLK2IO3", - "HCLK_IOI_RCLK2RCLK0", - "HCLK_IOI_RCLK2RCLK1", - "HCLK_IOI_RCLK2RCLK2", - "HCLK_IOI_RCLK2RCLK3", - "HCLK_IOI_RCLK3", - "HCLK_IOI_RCLK_BEFORE_DIV0", - "HCLK_IOI_RCLK_BEFORE_DIV1", - "HCLK_IOI_RCLK_BEFORE_DIV2", - "HCLK_IOI_RCLK_BEFORE_DIV3", - "HCLK_IOI_RCLK_IMUX0", - "HCLK_IOI_RCLK_IMUX1", - "HCLK_IOI_RCLK_IMUX2", - "HCLK_IOI_RCLK_IMUX3", - "HCLK_IOI_RCLK_OUT0", - "HCLK_IOI_RCLK_OUT1", - "HCLK_IOI_RCLK_OUT2", - "HCLK_IOI_RCLK_OUT3", - "HCLK_RCLK_DIV_CE0", - "HCLK_RCLK_DIV_CE1", - "HCLK_RCLK_DIV_CE2", - "HCLK_RCLK_DIV_CE3", - "HCLK_RCLK_DIV_CLR0", - "HCLK_RCLK_DIV_CLR1", - "HCLK_RCLK_DIV_CLR2", - "HCLK_RCLK_DIV_CLR3" - ] + "wires": { + "HCLK_IOI_BUFIO_O0": null, + "HCLK_IOI_BUFIO_O1": null, + "HCLK_IOI_BUFIO_O2": null, + "HCLK_IOI_BUFIO_O3": null, + "HCLK_IOI_BUFR0_CE": null, + "HCLK_IOI_BUFR0_CLR": null, + "HCLK_IOI_BUFR1_CE": null, + "HCLK_IOI_BUFR1_CLR": null, + "HCLK_IOI_BUFR2_CE": null, + "HCLK_IOI_BUFR2_CLR": null, + "HCLK_IOI_BUFR3_CE": null, + "HCLK_IOI_BUFR3_CLR": null, + "HCLK_IOI_CK_BUFHCLK0": null, + "HCLK_IOI_CK_BUFHCLK1": null, + "HCLK_IOI_CK_BUFHCLK10": null, + "HCLK_IOI_CK_BUFHCLK11": null, + "HCLK_IOI_CK_BUFHCLK2": null, + "HCLK_IOI_CK_BUFHCLK3": null, + "HCLK_IOI_CK_BUFHCLK4": null, + "HCLK_IOI_CK_BUFHCLK5": null, + "HCLK_IOI_CK_BUFHCLK6": null, + "HCLK_IOI_CK_BUFHCLK7": null, + "HCLK_IOI_CK_BUFHCLK8": null, + "HCLK_IOI_CK_BUFHCLK9": null, + "HCLK_IOI_CK_BUFRCLK0": null, + "HCLK_IOI_CK_BUFRCLK1": null, + "HCLK_IOI_CK_BUFRCLK2": null, + "HCLK_IOI_CK_BUFRCLK3": null, + "HCLK_IOI_CK_IGCLK0": null, + "HCLK_IOI_CK_IGCLK1": null, + "HCLK_IOI_CK_IGCLK10": null, + "HCLK_IOI_CK_IGCLK11": null, + "HCLK_IOI_CK_IGCLK2": null, + "HCLK_IOI_CK_IGCLK3": null, + "HCLK_IOI_CK_IGCLK4": null, + "HCLK_IOI_CK_IGCLK5": null, + "HCLK_IOI_CK_IGCLK6": null, + "HCLK_IOI_CK_IGCLK7": null, + "HCLK_IOI_CK_IGCLK8": null, + "HCLK_IOI_CK_IGCLK9": null, + "HCLK_IOI_CK_IN0": null, + "HCLK_IOI_CK_IN1": null, + "HCLK_IOI_CK_IN10": null, + "HCLK_IOI_CK_IN11": null, + "HCLK_IOI_CK_IN12": null, + "HCLK_IOI_CK_IN13": null, + "HCLK_IOI_CK_IN2": null, + "HCLK_IOI_CK_IN3": null, + "HCLK_IOI_CK_IN4": null, + "HCLK_IOI_CK_IN5": null, + "HCLK_IOI_CK_IN6": null, + "HCLK_IOI_CK_IN7": null, + "HCLK_IOI_CK_IN8": null, + "HCLK_IOI_CK_IN9": null, + "HCLK_IOI_I2IOCLK_BOT0": null, + "HCLK_IOI_I2IOCLK_BOT1": null, + "HCLK_IOI_I2IOCLK_TOP0": null, + "HCLK_IOI_I2IOCLK_TOP1": null, + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT": null, + "HCLK_IOI_IDELAYCTRL_OUTN1": null, + "HCLK_IOI_IDELAYCTRL_OUTN65": null, + "HCLK_IOI_IDELAYCTRL_RDY": null, + "HCLK_IOI_IDELAYCTRL_REFCLK": null, + "HCLK_IOI_IDELAYCTRL_RST": null, + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT": null, + "HCLK_IOI_IOCLK0": null, + "HCLK_IOI_IOCLK1": null, + "HCLK_IOI_IOCLK2": null, + "HCLK_IOI_IOCLK3": null, + "HCLK_IOI_IOCLK_PLL0": null, + "HCLK_IOI_IOCLK_PLL1": null, + "HCLK_IOI_IOCLK_PLL2": null, + "HCLK_IOI_IOCLK_PLL3": null, + "HCLK_IOI_IO_PLL_CLK0": null, + "HCLK_IOI_IO_PLL_CLK0_DMUX": null, + "HCLK_IOI_IO_PLL_CLK1": null, + "HCLK_IOI_IO_PLL_CLK1_DMUX": null, + "HCLK_IOI_IO_PLL_CLK2": null, + "HCLK_IOI_IO_PLL_CLK2_DMUX": null, + "HCLK_IOI_IO_PLL_CLK3": null, + "HCLK_IOI_IO_PLL_CLK3_DMUX": null, + "HCLK_IOI_LEAF_GCLK_BOT0": null, + "HCLK_IOI_LEAF_GCLK_BOT1": null, + "HCLK_IOI_LEAF_GCLK_BOT2": null, + "HCLK_IOI_LEAF_GCLK_BOT3": null, + "HCLK_IOI_LEAF_GCLK_BOT4": null, + "HCLK_IOI_LEAF_GCLK_BOT5": null, + "HCLK_IOI_LEAF_GCLK_TOP0": null, + "HCLK_IOI_LEAF_GCLK_TOP1": null, + "HCLK_IOI_LEAF_GCLK_TOP2": null, + "HCLK_IOI_LEAF_GCLK_TOP3": null, + "HCLK_IOI_LEAF_GCLK_TOP4": null, + "HCLK_IOI_LEAF_GCLK_TOP5": null, + "HCLK_IOI_RCLK0": null, + "HCLK_IOI_RCLK1": null, + "HCLK_IOI_RCLK2": null, + "HCLK_IOI_RCLK2IO0": null, + "HCLK_IOI_RCLK2IO1": null, + "HCLK_IOI_RCLK2IO2": null, + "HCLK_IOI_RCLK2IO3": null, + "HCLK_IOI_RCLK2RCLK0": null, + "HCLK_IOI_RCLK2RCLK1": null, + "HCLK_IOI_RCLK2RCLK2": null, + "HCLK_IOI_RCLK2RCLK3": null, + "HCLK_IOI_RCLK3": null, + "HCLK_IOI_RCLK_BEFORE_DIV0": null, + "HCLK_IOI_RCLK_BEFORE_DIV1": null, + "HCLK_IOI_RCLK_BEFORE_DIV2": null, + "HCLK_IOI_RCLK_BEFORE_DIV3": null, + "HCLK_IOI_RCLK_IMUX0": null, + "HCLK_IOI_RCLK_IMUX1": null, + "HCLK_IOI_RCLK_IMUX2": null, + "HCLK_IOI_RCLK_IMUX3": null, + "HCLK_IOI_RCLK_OUT0": null, + "HCLK_IOI_RCLK_OUT1": null, + "HCLK_IOI_RCLK_OUT2": null, + "HCLK_IOI_RCLK_OUT3": null, + "HCLK_RCLK_DIV_CE0": null, + "HCLK_RCLK_DIV_CE1": null, + "HCLK_RCLK_DIV_CE2": null, + "HCLK_RCLK_DIV_CE3": null, + "HCLK_RCLK_DIV_CLR0": null, + "HCLK_RCLK_DIV_CLR1": null, + "HCLK_RCLK_DIV_CLR2": null, + "HCLK_RCLK_DIV_CLR3": null + } } diff --git a/zynq7/tile_type_HCLK_L.json b/zynq7/tile_type_HCLK_L.json index 7fe9cbe..fd6fea2 100644 --- a/zynq7/tile_type_HCLK_L.json +++ b/zynq7/tile_type_HCLK_L.json @@ -2,1694 +2,6545 @@ "pips": { "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_CK_INOUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_CK_INOUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_CK_INOUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_CK_INOUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_CK_INOUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_CK_INOUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_CK_INOUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_CK_INOUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + 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"src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + 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"src_wire": "HCLK_CK_OUTIN_L1" }, "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L1" }, "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L1" }, "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L1" }, "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L1" }, "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L1" }, "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L1" }, "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L1" }, "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L1" }, "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L1" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + 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"dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + 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"src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" } }, "sites": [], "tile_type": "HCLK_L", - "wires": [ - "HCLK_BYP_BOUNCE2", - "HCLK_BYP_BOUNCE3", - "HCLK_BYP_BOUNCE6", - "HCLK_BYP_BOUNCE7", - "HCLK_CCIO0", - "HCLK_CCIO1", - "HCLK_CCIO2", - "HCLK_CCIO3", - "HCLK_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK9", - "HCLK_CK_BUFRCLK0", - "HCLK_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK3", - "HCLK_CK_IN0", - "HCLK_CK_IN1", - "HCLK_CK_IN10", - "HCLK_CK_IN11", - "HCLK_CK_IN12", - "HCLK_CK_IN13", - "HCLK_CK_IN2", - "HCLK_CK_IN3", - "HCLK_CK_IN4", - "HCLK_CK_IN5", - "HCLK_CK_IN6", - "HCLK_CK_IN7", - "HCLK_CK_IN8", - "HCLK_CK_IN9", - "HCLK_CK_INOUT_L0", - "HCLK_CK_INOUT_L1", - "HCLK_CK_INOUT_L2", - "HCLK_CK_INOUT_L3", - "HCLK_CK_INOUT_L4", - "HCLK_CK_INOUT_L5", - "HCLK_CK_INOUT_L6", - "HCLK_CK_INOUT_L7", - "HCLK_CK_OUTIN_L0", - "HCLK_CK_OUTIN_L1", - "HCLK_CK_OUTIN_L2", - "HCLK_CK_OUTIN_L3", - "HCLK_CK_OUTIN_L4", - "HCLK_CK_OUTIN_L5", - "HCLK_CK_OUTIN_L6", - "HCLK_CK_OUTIN_L7", - "HCLK_EL1BEG3", - "HCLK_EL1END_S3_0", - "HCLK_ER1BEG_S0", - "HCLK_ER1END3", - "HCLK_FAN_BOUNCE_S3_0", - "HCLK_FAN_BOUNCE_S3_2", - "HCLK_FAN_BOUNCE_S3_4", - "HCLK_FAN_BOUNCE_S3_6", - "HCLK_INT_PERFCLK0", - "HCLK_INT_PERFCLK1", - "HCLK_INT_PERFCLK2", - "HCLK_INT_PERFCLK3", - "HCLK_LEAF_CLK_B_BOTL0", - "HCLK_LEAF_CLK_B_BOTL1", - "HCLK_LEAF_CLK_B_BOTL2", - "HCLK_LEAF_CLK_B_BOTL3", - "HCLK_LEAF_CLK_B_BOTL4", - "HCLK_LEAF_CLK_B_BOTL5", - "HCLK_LEAF_CLK_B_TOPL0", - "HCLK_LEAF_CLK_B_TOPL1", - "HCLK_LEAF_CLK_B_TOPL2", - "HCLK_LEAF_CLK_B_TOPL3", - "HCLK_LEAF_CLK_B_TOPL4", - "HCLK_LEAF_CLK_B_TOPL5", - "HCLK_LV0", - "HCLK_LV1", - "HCLK_LV10", - "HCLK_LV11", - "HCLK_LV12", - "HCLK_LV13", - "HCLK_LV14", - "HCLK_LV15", - "HCLK_LV16", - "HCLK_LV17", - "HCLK_LV2", - "HCLK_LV3", - "HCLK_LV4", - "HCLK_LV5", - "HCLK_LV6", - "HCLK_LV7", - "HCLK_LV8", - "HCLK_LV9", - "HCLK_LVB1", - "HCLK_LVB10", - "HCLK_LVB11", - "HCLK_LVB12", - "HCLK_LVB2", - "HCLK_LVB3", - "HCLK_LVB4", - "HCLK_LVB5", - "HCLK_LVB6", - "HCLK_LVB7", - "HCLK_LVB8", - "HCLK_LVB9", - "HCLK_NE2BEG0", - "HCLK_NE2BEG1", - "HCLK_NE2BEG2", - "HCLK_NE2BEG3", - "HCLK_NE2END_S3_0", - "HCLK_NE6A0", - "HCLK_NE6A1", - "HCLK_NE6A2", - "HCLK_NE6A3", - "HCLK_NE6B0", - "HCLK_NE6B1", - "HCLK_NE6B2", - "HCLK_NE6B3", - "HCLK_NE6C0", - "HCLK_NE6C1", - "HCLK_NE6C2", - "HCLK_NE6C3", - "HCLK_NE6D0", - "HCLK_NE6D1", - "HCLK_NE6D2", - "HCLK_NE6D3", - "HCLK_NL1BEG0", - "HCLK_NL1BEG1", - "HCLK_NL1BEG2", - "HCLK_NL1END_S3_0", - "HCLK_NN2A0", - "HCLK_NN2A1", - "HCLK_NN2A2", - "HCLK_NN2A3", - "HCLK_NN2BEG0", - "HCLK_NN2BEG1", - "HCLK_NN2BEG2", - "HCLK_NN2BEG3", - "HCLK_NN2END_S2_0", - "HCLK_NN6A0", - "HCLK_NN6A1", - "HCLK_NN6A2", - "HCLK_NN6A3", - "HCLK_NN6B0", - "HCLK_NN6B1", - "HCLK_NN6B2", - "HCLK_NN6B3", - "HCLK_NN6BEG0", - "HCLK_NN6BEG1", - "HCLK_NN6BEG2", - "HCLK_NN6BEG3", - "HCLK_NN6C0", - "HCLK_NN6C1", - "HCLK_NN6C2", - "HCLK_NN6C3", - "HCLK_NN6D0", - "HCLK_NN6D1", - "HCLK_NN6D2", - "HCLK_NN6D3", - "HCLK_NN6E0", - "HCLK_NN6E1", - "HCLK_NN6E2", - "HCLK_NN6E3", - "HCLK_NN6END_S1_0", - "HCLK_NR1BEG0", - "HCLK_NR1BEG1", - "HCLK_NR1BEG2", - "HCLK_NR1BEG3", - "HCLK_NW2A0", - "HCLK_NW2A1", - "HCLK_NW2A2", - "HCLK_NW2A3", - "HCLK_NW2END_S0_0", - "HCLK_NW6A0", - "HCLK_NW6A1", - "HCLK_NW6A2", - "HCLK_NW6A3", - "HCLK_NW6B0", - "HCLK_NW6B1", - "HCLK_NW6B2", - "HCLK_NW6B3", - "HCLK_NW6C0", - "HCLK_NW6C1", - "HCLK_NW6C2", - "HCLK_NW6C3", - "HCLK_NW6D0", - "HCLK_NW6D1", - "HCLK_NW6D2", - "HCLK_NW6D3", - "HCLK_NW6END_S0_0", - "HCLK_REFCK_EASTCLK0", - "HCLK_REFCK_EASTCLK1", - "HCLK_REFCK_WESTCLK0", - "HCLK_REFCK_WESTCLK1", - "HCLK_SE2A0", - "HCLK_SE2A1", - "HCLK_SE2A2", - "HCLK_SE2A3", - "HCLK_SE6B0", - "HCLK_SE6B1", - "HCLK_SE6B2", - "HCLK_SE6B3", - "HCLK_SE6C0", - "HCLK_SE6C1", - "HCLK_SE6C2", - "HCLK_SE6C3", - "HCLK_SE6D0", - "HCLK_SE6D1", - "HCLK_SE6D2", - "HCLK_SE6D3", - "HCLK_SE6E0", - "HCLK_SE6E1", - "HCLK_SE6E2", - "HCLK_SE6E3", - "HCLK_SL1END0", - "HCLK_SL1END1", - "HCLK_SL1END2", - "HCLK_SL1END3", - "HCLK_SR1BEG3", - "HCLK_SR1END1", - "HCLK_SR1END2", - "HCLK_SR1END_N3_3", - "HCLK_SS2A0", - "HCLK_SS2A1", - "HCLK_SS2A2", - "HCLK_SS2A3", - "HCLK_SS2BEG3", - "HCLK_SS2END0", - "HCLK_SS2END1", - "HCLK_SS2END2", - "HCLK_SS2END_N0_3", - "HCLK_SS6A0", - "HCLK_SS6A1", - "HCLK_SS6A2", - "HCLK_SS6A3", - "HCLK_SS6B0", - "HCLK_SS6B1", - "HCLK_SS6B2", - "HCLK_SS6B3", - "HCLK_SS6C0", - "HCLK_SS6C1", - "HCLK_SS6C2", - "HCLK_SS6C3", - "HCLK_SS6D0", - "HCLK_SS6D1", - "HCLK_SS6D2", - "HCLK_SS6D3", - "HCLK_SS6E0", - "HCLK_SS6E1", - "HCLK_SS6E2", - "HCLK_SS6E3", - "HCLK_SS6END0", - "HCLK_SS6END1", - "HCLK_SS6END2", - "HCLK_SS6END3", - "HCLK_SS6END_N0_3", - "HCLK_SW2A3", - "HCLK_SW2END0", - "HCLK_SW2END1", - "HCLK_SW2END2", - "HCLK_SW2END_N0_3", - "HCLK_SW6B0", - "HCLK_SW6B1", - "HCLK_SW6B2", - "HCLK_SW6B3", - "HCLK_SW6C0", - "HCLK_SW6C1", - "HCLK_SW6C2", - "HCLK_SW6C3", - "HCLK_SW6D0", - "HCLK_SW6D1", - "HCLK_SW6D2", - "HCLK_SW6D3", - "HCLK_SW6E0", - "HCLK_SW6E1", - "HCLK_SW6E2", - "HCLK_SW6E3", - "HCLK_SW6END3", - "HCLK_WL1BEG3", - "HCLK_WL1END3", - "HCLK_WR1BEG_S0", - "HCLK_WR1END_S1_0", - "HCLK_WW2END3", - "HCLK_WW4END_S0_0" - ] + "wires": { + "HCLK_BYP_BOUNCE2": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_BYP_BOUNCE3": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_BYP_BOUNCE6": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_BYP_BOUNCE7": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_CCIO0": null, + "HCLK_CCIO1": null, + "HCLK_CCIO2": null, + "HCLK_CCIO3": null, + "HCLK_CK_BUFHCLK0": null, + "HCLK_CK_BUFHCLK1": null, + "HCLK_CK_BUFHCLK10": null, + "HCLK_CK_BUFHCLK11": null, + "HCLK_CK_BUFHCLK2": null, + "HCLK_CK_BUFHCLK3": null, + "HCLK_CK_BUFHCLK4": null, + "HCLK_CK_BUFHCLK5": null, + "HCLK_CK_BUFHCLK6": null, + "HCLK_CK_BUFHCLK7": null, + "HCLK_CK_BUFHCLK8": null, + "HCLK_CK_BUFHCLK9": null, + "HCLK_CK_BUFRCLK0": null, + "HCLK_CK_BUFRCLK1": null, + "HCLK_CK_BUFRCLK2": null, + "HCLK_CK_BUFRCLK3": null, + "HCLK_CK_IN0": null, + "HCLK_CK_IN1": null, + "HCLK_CK_IN10": null, + "HCLK_CK_IN11": null, + "HCLK_CK_IN12": null, + "HCLK_CK_IN13": null, + "HCLK_CK_IN2": null, + "HCLK_CK_IN3": null, + "HCLK_CK_IN4": null, + "HCLK_CK_IN5": null, + "HCLK_CK_IN6": null, + "HCLK_CK_IN7": null, + "HCLK_CK_IN8": null, + "HCLK_CK_IN9": null, + "HCLK_CK_INOUT_L0": null, + "HCLK_CK_INOUT_L1": null, + "HCLK_CK_INOUT_L2": null, + "HCLK_CK_INOUT_L3": null, + "HCLK_CK_INOUT_L4": null, + "HCLK_CK_INOUT_L5": null, + "HCLK_CK_INOUT_L6": null, + "HCLK_CK_INOUT_L7": null, + "HCLK_CK_OUTIN_L0": null, + "HCLK_CK_OUTIN_L1": null, + "HCLK_CK_OUTIN_L2": null, + "HCLK_CK_OUTIN_L3": null, + "HCLK_CK_OUTIN_L4": null, + "HCLK_CK_OUTIN_L5": null, + "HCLK_CK_OUTIN_L6": null, + "HCLK_CK_OUTIN_L7": null, + "HCLK_EL1BEG3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_EL1END_S3_0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_ER1BEG_S0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_ER1END3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_FAN_BOUNCE_S3_0": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_FAN_BOUNCE_S3_2": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_FAN_BOUNCE_S3_4": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_FAN_BOUNCE_S3_6": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_INT_PERFCLK0": null, + "HCLK_INT_PERFCLK1": null, + "HCLK_INT_PERFCLK2": null, + "HCLK_INT_PERFCLK3": null, + "HCLK_LEAF_CLK_B_BOTL0": null, + "HCLK_LEAF_CLK_B_BOTL1": null, + "HCLK_LEAF_CLK_B_BOTL2": null, + "HCLK_LEAF_CLK_B_BOTL3": null, + "HCLK_LEAF_CLK_B_BOTL4": null, + "HCLK_LEAF_CLK_B_BOTL5": null, + "HCLK_LEAF_CLK_B_TOPL0": null, + "HCLK_LEAF_CLK_B_TOPL1": null, + "HCLK_LEAF_CLK_B_TOPL2": null, + "HCLK_LEAF_CLK_B_TOPL3": null, + "HCLK_LEAF_CLK_B_TOPL4": null, + "HCLK_LEAF_CLK_B_TOPL5": null, + "HCLK_LV0": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV1": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV10": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV11": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV12": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV13": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV14": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV15": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV16": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV17": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV2": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV3": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV4": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV5": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV6": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV7": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV8": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV9": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB1": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB10": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB11": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB12": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB2": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB3": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB4": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB5": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB6": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB7": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB8": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB9": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_NE2BEG0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NE2BEG1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NE2BEG2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NE2BEG3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NE2END_S3_0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NE6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NL1BEG0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NL1BEG1": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NL1BEG2": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NL1END_S3_0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NN2A0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2A1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2A2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2A3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2BEG0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2BEG1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2BEG2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2BEG3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2END_S2_0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6END_S1_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NR1BEG0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NR1BEG1": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NR1BEG2": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NR1BEG3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NW2A0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NW2A1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NW2A2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NW2A3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NW2END_S0_0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NW6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6END_S0_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_REFCK_EASTCLK0": null, + "HCLK_REFCK_EASTCLK1": null, + "HCLK_REFCK_WESTCLK0": null, + "HCLK_REFCK_WESTCLK1": null, + "HCLK_SE2A0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SE2A1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SE2A2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SE2A3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SE6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SL1END0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SL1END1": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SL1END2": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SL1END3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SR1BEG3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SR1END1": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SR1END2": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SR1END_N3_3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SS2A0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2A1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2A2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2A3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2BEG3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2END0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2END1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2END2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2END_N0_3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END_N0_3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW2A3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SW2END0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SW2END1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SW2END2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SW2END_N0_3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SW6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WL1BEG3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_WL1END3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_WR1BEG_S0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_WR1END_S1_0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_WW2END3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_WW4END_S0_0": { + "cap": "17.411", + "res": "154.960" + } + } } diff --git a/zynq7/tile_type_HCLK_R.json b/zynq7/tile_type_HCLK_R.json index 7ef8574..0be9f75 100644 --- a/zynq7/tile_type_HCLK_R.json +++ b/zynq7/tile_type_HCLK_R.json @@ -2,1694 +2,6545 @@ "pips": { "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_CK_INOUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_CK_INOUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT4": { "can_invert": "0", + "dst_to_src": { + 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"delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK3" }, "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK3" }, "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": 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"delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R5" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.072", + "0.074", + "0.191", + "0.193" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" } }, "sites": [], "tile_type": "HCLK_R", - "wires": [ - "HCLK_BYP_BOUNCE2", - "HCLK_BYP_BOUNCE3", - "HCLK_BYP_BOUNCE6", - "HCLK_BYP_BOUNCE7", - "HCLK_CCIO0", - "HCLK_CCIO1", - "HCLK_CCIO2", - "HCLK_CCIO3", - "HCLK_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK9", - "HCLK_CK_BUFRCLK0", - "HCLK_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK3", - "HCLK_CK_IN0", - "HCLK_CK_IN1", - "HCLK_CK_IN10", - "HCLK_CK_IN11", - "HCLK_CK_IN12", - "HCLK_CK_IN13", - "HCLK_CK_IN2", - "HCLK_CK_IN3", - "HCLK_CK_IN4", - "HCLK_CK_IN5", - "HCLK_CK_IN6", - "HCLK_CK_IN7", - "HCLK_CK_IN8", - "HCLK_CK_IN9", - "HCLK_CK_INOUT_R0", - "HCLK_CK_INOUT_R1", - "HCLK_CK_INOUT_R2", - "HCLK_CK_INOUT_R3", - "HCLK_CK_INOUT_R4", - "HCLK_CK_INOUT_R5", - "HCLK_CK_INOUT_R6", - "HCLK_CK_INOUT_R7", - "HCLK_CK_OUTIN_R0", - "HCLK_CK_OUTIN_R1", - "HCLK_CK_OUTIN_R2", - "HCLK_CK_OUTIN_R3", - "HCLK_CK_OUTIN_R4", - "HCLK_CK_OUTIN_R5", - "HCLK_CK_OUTIN_R6", - "HCLK_CK_OUTIN_R7", - "HCLK_EL1BEG3", - "HCLK_EL1END_S3_0", - "HCLK_ER1BEG_S0", - "HCLK_ER1END3", - "HCLK_FAN_BOUNCE_S3_0", - "HCLK_FAN_BOUNCE_S3_2", - "HCLK_FAN_BOUNCE_S3_4", - "HCLK_FAN_BOUNCE_S3_6", - "HCLK_INT_PERFCLK0", - "HCLK_INT_PERFCLK1", - "HCLK_INT_PERFCLK2", - "HCLK_INT_PERFCLK3", - "HCLK_LEAF_CLK_B_BOT0", - "HCLK_LEAF_CLK_B_BOT1", - "HCLK_LEAF_CLK_B_BOT2", - "HCLK_LEAF_CLK_B_BOT3", - "HCLK_LEAF_CLK_B_BOT4", - "HCLK_LEAF_CLK_B_BOT5", - "HCLK_LEAF_CLK_B_TOP0", - "HCLK_LEAF_CLK_B_TOP1", - "HCLK_LEAF_CLK_B_TOP2", - "HCLK_LEAF_CLK_B_TOP3", - "HCLK_LEAF_CLK_B_TOP4", - "HCLK_LEAF_CLK_B_TOP5", - "HCLK_LV0", - "HCLK_LV1", - "HCLK_LV10", - "HCLK_LV11", - "HCLK_LV12", - "HCLK_LV13", - "HCLK_LV14", - "HCLK_LV15", - "HCLK_LV16", - "HCLK_LV17", - "HCLK_LV2", - "HCLK_LV3", - "HCLK_LV4", - "HCLK_LV5", - "HCLK_LV6", - "HCLK_LV7", - "HCLK_LV8", - "HCLK_LV9", - "HCLK_LVB1", - "HCLK_LVB10", - "HCLK_LVB11", - "HCLK_LVB12", - "HCLK_LVB2", - "HCLK_LVB3", - "HCLK_LVB4", - "HCLK_LVB5", - "HCLK_LVB6", - "HCLK_LVB7", - "HCLK_LVB8", - "HCLK_LVB9", - "HCLK_NE2BEG0", - "HCLK_NE2BEG1", - "HCLK_NE2BEG2", - "HCLK_NE2BEG3", - "HCLK_NE2END_S3_0", - "HCLK_NE6A0", - "HCLK_NE6A1", - "HCLK_NE6A2", - "HCLK_NE6A3", - "HCLK_NE6B0", - "HCLK_NE6B1", - "HCLK_NE6B2", - "HCLK_NE6B3", - "HCLK_NE6C0", - "HCLK_NE6C1", - "HCLK_NE6C2", - "HCLK_NE6C3", - "HCLK_NE6D0", - "HCLK_NE6D1", - "HCLK_NE6D2", - "HCLK_NE6D3", - "HCLK_NL1BEG0", - "HCLK_NL1BEG1", - "HCLK_NL1BEG2", - "HCLK_NL1END_S3_0", - "HCLK_NN2A0", - "HCLK_NN2A1", - "HCLK_NN2A2", - "HCLK_NN2A3", - "HCLK_NN2BEG0", - "HCLK_NN2BEG1", - "HCLK_NN2BEG2", - "HCLK_NN2BEG3", - "HCLK_NN2END_S2_0", - "HCLK_NN6A0", - "HCLK_NN6A1", - "HCLK_NN6A2", - "HCLK_NN6A3", - "HCLK_NN6B0", - "HCLK_NN6B1", - "HCLK_NN6B2", - "HCLK_NN6B3", - "HCLK_NN6BEG0", - "HCLK_NN6BEG1", - "HCLK_NN6BEG2", - "HCLK_NN6BEG3", - "HCLK_NN6C0", - "HCLK_NN6C1", - "HCLK_NN6C2", - "HCLK_NN6C3", - "HCLK_NN6D0", - "HCLK_NN6D1", - "HCLK_NN6D2", - "HCLK_NN6D3", - "HCLK_NN6E0", - "HCLK_NN6E1", - "HCLK_NN6E2", - "HCLK_NN6E3", - "HCLK_NN6END_S1_0", - "HCLK_NR1BEG0", - "HCLK_NR1BEG1", - "HCLK_NR1BEG2", - "HCLK_NR1BEG3", - "HCLK_NW2A0", - "HCLK_NW2A1", - "HCLK_NW2A2", - "HCLK_NW2A3", - "HCLK_NW2END_S0_0", - "HCLK_NW6A0", - "HCLK_NW6A1", - "HCLK_NW6A2", - "HCLK_NW6A3", - "HCLK_NW6B0", - "HCLK_NW6B1", - "HCLK_NW6B2", - "HCLK_NW6B3", - "HCLK_NW6C0", - "HCLK_NW6C1", - "HCLK_NW6C2", - "HCLK_NW6C3", - "HCLK_NW6D0", - "HCLK_NW6D1", - "HCLK_NW6D2", - "HCLK_NW6D3", - "HCLK_NW6END_S0_0", - "HCLK_REFCK_EASTCLK0", - "HCLK_REFCK_EASTCLK1", - "HCLK_REFCK_WESTCLK0", - "HCLK_REFCK_WESTCLK1", - "HCLK_SE2A0", - "HCLK_SE2A1", - "HCLK_SE2A2", - "HCLK_SE2A3", - "HCLK_SE6B0", - "HCLK_SE6B1", - "HCLK_SE6B2", - "HCLK_SE6B3", - "HCLK_SE6C0", - "HCLK_SE6C1", - "HCLK_SE6C2", - "HCLK_SE6C3", - "HCLK_SE6D0", - "HCLK_SE6D1", - "HCLK_SE6D2", - "HCLK_SE6D3", - "HCLK_SE6E0", - "HCLK_SE6E1", - "HCLK_SE6E2", - "HCLK_SE6E3", - "HCLK_SL1END0", - "HCLK_SL1END1", - "HCLK_SL1END2", - "HCLK_SL1END3", - "HCLK_SR1BEG3", - "HCLK_SR1END1", - "HCLK_SR1END2", - "HCLK_SR1END_N3_3", - "HCLK_SS2A0", - "HCLK_SS2A1", - "HCLK_SS2A2", - "HCLK_SS2A3", - "HCLK_SS2BEG3", - "HCLK_SS2END0", - "HCLK_SS2END1", - "HCLK_SS2END2", - "HCLK_SS2END_N0_3", - "HCLK_SS6A0", - "HCLK_SS6A1", - "HCLK_SS6A2", - "HCLK_SS6A3", - "HCLK_SS6B0", - "HCLK_SS6B1", - "HCLK_SS6B2", - "HCLK_SS6B3", - "HCLK_SS6C0", - "HCLK_SS6C1", - "HCLK_SS6C2", - "HCLK_SS6C3", - "HCLK_SS6D0", - "HCLK_SS6D1", - "HCLK_SS6D2", - "HCLK_SS6D3", - "HCLK_SS6E0", - "HCLK_SS6E1", - "HCLK_SS6E2", - "HCLK_SS6E3", - "HCLK_SS6END0", - "HCLK_SS6END1", - "HCLK_SS6END2", - "HCLK_SS6END3", - "HCLK_SS6END_N0_3", - "HCLK_SW2A3", - "HCLK_SW2END0", - "HCLK_SW2END1", - "HCLK_SW2END2", - "HCLK_SW2END_N0_3", - "HCLK_SW6B0", - "HCLK_SW6B1", - "HCLK_SW6B2", - "HCLK_SW6B3", - "HCLK_SW6C0", - "HCLK_SW6C1", - "HCLK_SW6C2", - "HCLK_SW6C3", - "HCLK_SW6D0", - "HCLK_SW6D1", - "HCLK_SW6D2", - "HCLK_SW6D3", - "HCLK_SW6E0", - "HCLK_SW6E1", - "HCLK_SW6E2", - "HCLK_SW6E3", - "HCLK_SW6END3", - "HCLK_WL1BEG3", - "HCLK_WL1END3", - "HCLK_WR1BEG_S0", - "HCLK_WR1END_S1_0", - "HCLK_WW2END3", - "HCLK_WW4END_S0_0" - ] + "wires": { + "HCLK_BYP_BOUNCE2": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_BYP_BOUNCE3": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_BYP_BOUNCE6": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_BYP_BOUNCE7": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_CCIO0": null, + "HCLK_CCIO1": null, + "HCLK_CCIO2": null, + "HCLK_CCIO3": null, + "HCLK_CK_BUFHCLK0": null, + "HCLK_CK_BUFHCLK1": null, + "HCLK_CK_BUFHCLK10": null, + "HCLK_CK_BUFHCLK11": null, + "HCLK_CK_BUFHCLK2": null, + "HCLK_CK_BUFHCLK3": null, + "HCLK_CK_BUFHCLK4": null, + "HCLK_CK_BUFHCLK5": null, + "HCLK_CK_BUFHCLK6": null, + "HCLK_CK_BUFHCLK7": null, + "HCLK_CK_BUFHCLK8": null, + "HCLK_CK_BUFHCLK9": null, + "HCLK_CK_BUFRCLK0": null, + "HCLK_CK_BUFRCLK1": null, + "HCLK_CK_BUFRCLK2": null, + "HCLK_CK_BUFRCLK3": null, + "HCLK_CK_IN0": null, + "HCLK_CK_IN1": null, + "HCLK_CK_IN10": null, + "HCLK_CK_IN11": null, + "HCLK_CK_IN12": null, + "HCLK_CK_IN13": null, + "HCLK_CK_IN2": null, + "HCLK_CK_IN3": null, + "HCLK_CK_IN4": null, + "HCLK_CK_IN5": null, + "HCLK_CK_IN6": null, + "HCLK_CK_IN7": null, + "HCLK_CK_IN8": null, + "HCLK_CK_IN9": null, + "HCLK_CK_INOUT_R0": null, + "HCLK_CK_INOUT_R1": null, + "HCLK_CK_INOUT_R2": null, + "HCLK_CK_INOUT_R3": null, + "HCLK_CK_INOUT_R4": null, + "HCLK_CK_INOUT_R5": null, + "HCLK_CK_INOUT_R6": null, + "HCLK_CK_INOUT_R7": null, + "HCLK_CK_OUTIN_R0": null, + "HCLK_CK_OUTIN_R1": null, + "HCLK_CK_OUTIN_R2": null, + "HCLK_CK_OUTIN_R3": null, + "HCLK_CK_OUTIN_R4": null, + "HCLK_CK_OUTIN_R5": null, + "HCLK_CK_OUTIN_R6": null, + "HCLK_CK_OUTIN_R7": null, + "HCLK_EL1BEG3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_EL1END_S3_0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_ER1BEG_S0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_ER1END3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_FAN_BOUNCE_S3_0": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_FAN_BOUNCE_S3_2": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_FAN_BOUNCE_S3_4": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_FAN_BOUNCE_S3_6": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_INT_PERFCLK0": null, + "HCLK_INT_PERFCLK1": null, + "HCLK_INT_PERFCLK2": null, + "HCLK_INT_PERFCLK3": null, + "HCLK_LEAF_CLK_B_BOT0": null, + "HCLK_LEAF_CLK_B_BOT1": null, + "HCLK_LEAF_CLK_B_BOT2": null, + "HCLK_LEAF_CLK_B_BOT3": null, + "HCLK_LEAF_CLK_B_BOT4": null, + "HCLK_LEAF_CLK_B_BOT5": null, + "HCLK_LEAF_CLK_B_TOP0": null, + "HCLK_LEAF_CLK_B_TOP1": null, + "HCLK_LEAF_CLK_B_TOP2": null, + "HCLK_LEAF_CLK_B_TOP3": null, + "HCLK_LEAF_CLK_B_TOP4": null, + "HCLK_LEAF_CLK_B_TOP5": null, + "HCLK_LV0": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV1": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV10": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV11": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV12": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV13": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV14": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV15": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV16": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV17": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV2": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV3": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV4": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV5": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV6": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV7": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV8": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV9": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB1": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB10": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB11": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB12": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB2": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB3": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB4": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB5": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB6": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB7": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB8": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB9": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_NE2BEG0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NE2BEG1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NE2BEG2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NE2BEG3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NE2END_S3_0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NE6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NL1BEG0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NL1BEG1": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NL1BEG2": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NL1END_S3_0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NN2A0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2A1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2A2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2A3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2BEG0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2BEG1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2BEG2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2BEG3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN2END_S2_0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NN6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6END_S1_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NR1BEG0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NR1BEG1": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NR1BEG2": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NR1BEG3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_NW2A0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NW2A1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NW2A2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NW2A3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NW2END_S0_0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_NW6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6END_S0_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_REFCK_EASTCLK0": null, + "HCLK_REFCK_EASTCLK1": null, + "HCLK_REFCK_WESTCLK0": null, + "HCLK_REFCK_WESTCLK1": null, + "HCLK_SE2A0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SE2A1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SE2A2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SE2A3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SE6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SL1END0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SL1END1": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SL1END2": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SL1END3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SR1BEG3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SR1END1": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SR1END2": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SR1END_N3_3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_SS2A0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2A1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2A2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2A3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2BEG3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2END0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2END1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2END2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS2END_N0_3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SS6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END_N0_3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW2A3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SW2END0": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SW2END1": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SW2END2": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SW2END_N0_3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_SW6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WL1BEG3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_WL1END3": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_WR1BEG_S0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_WR1END_S1_0": { + "cap": "21.478", + "res": "154.960" + }, + "HCLK_WW2END3": { + "cap": "22.944", + "res": "154.960" + }, + "HCLK_WW4END_S0_0": { + "cap": "17.411", + "res": "154.960" + } + } } diff --git a/zynq7/tile_type_HCLK_TERM.json b/zynq7/tile_type_HCLK_TERM.json index 0138939..bb3a3bf 100644 --- a/zynq7/tile_type_HCLK_TERM.json +++ b/zynq7/tile_type_HCLK_TERM.json @@ -2,44 +2,44 @@ "pips": {}, "sites": [], "tile_type": "HCLK_TERM", - "wires": [ - "HCLK_TERM_CCIO0", - "HCLK_TERM_CCIO1", - "HCLK_TERM_CCIO2", - "HCLK_TERM_CCIO3", - "HCLK_TERM_CK_BUFHCLK0", - "HCLK_TERM_CK_BUFHCLK1", - "HCLK_TERM_CK_BUFHCLK10", - "HCLK_TERM_CK_BUFHCLK11", - "HCLK_TERM_CK_BUFHCLK2", - "HCLK_TERM_CK_BUFHCLK3", - "HCLK_TERM_CK_BUFHCLK4", - "HCLK_TERM_CK_BUFHCLK5", - "HCLK_TERM_CK_BUFHCLK6", - "HCLK_TERM_CK_BUFHCLK7", - "HCLK_TERM_CK_BUFHCLK8", - "HCLK_TERM_CK_BUFHCLK9", - "HCLK_TERM_CK_BUFRCLK0", - "HCLK_TERM_CK_BUFRCLK1", - "HCLK_TERM_CK_BUFRCLK2", - "HCLK_TERM_CK_BUFRCLK3", - "HCLK_TERM_CK_IN0", - "HCLK_TERM_CK_IN1", - "HCLK_TERM_CK_IN10", - "HCLK_TERM_CK_IN11", - "HCLK_TERM_CK_IN12", - "HCLK_TERM_CK_IN13", - "HCLK_TERM_CK_IN2", - "HCLK_TERM_CK_IN3", - "HCLK_TERM_CK_IN4", - "HCLK_TERM_CK_IN5", - "HCLK_TERM_CK_IN6", - "HCLK_TERM_CK_IN7", - "HCLK_TERM_CK_IN8", - "HCLK_TERM_CK_IN9", - "HCLK_TERM_PERFCLK0", - "HCLK_TERM_PERFCLK1", - "HCLK_TERM_PERFCLK2", - "HCLK_TERM_PERFCLK3" - ] + "wires": { + "HCLK_TERM_CCIO0": null, + "HCLK_TERM_CCIO1": null, + "HCLK_TERM_CCIO2": null, + "HCLK_TERM_CCIO3": null, + "HCLK_TERM_CK_BUFHCLK0": null, + "HCLK_TERM_CK_BUFHCLK1": null, + "HCLK_TERM_CK_BUFHCLK10": null, + "HCLK_TERM_CK_BUFHCLK11": null, + "HCLK_TERM_CK_BUFHCLK2": null, + "HCLK_TERM_CK_BUFHCLK3": null, + "HCLK_TERM_CK_BUFHCLK4": null, + "HCLK_TERM_CK_BUFHCLK5": null, + "HCLK_TERM_CK_BUFHCLK6": null, + "HCLK_TERM_CK_BUFHCLK7": null, + "HCLK_TERM_CK_BUFHCLK8": null, + "HCLK_TERM_CK_BUFHCLK9": null, + "HCLK_TERM_CK_BUFRCLK0": null, + "HCLK_TERM_CK_BUFRCLK1": null, + "HCLK_TERM_CK_BUFRCLK2": null, + "HCLK_TERM_CK_BUFRCLK3": null, + "HCLK_TERM_CK_IN0": null, + "HCLK_TERM_CK_IN1": null, + "HCLK_TERM_CK_IN10": null, + "HCLK_TERM_CK_IN11": null, + "HCLK_TERM_CK_IN12": null, + "HCLK_TERM_CK_IN13": null, + "HCLK_TERM_CK_IN2": null, + "HCLK_TERM_CK_IN3": null, + "HCLK_TERM_CK_IN4": null, + "HCLK_TERM_CK_IN5": null, + "HCLK_TERM_CK_IN6": null, + "HCLK_TERM_CK_IN7": null, + "HCLK_TERM_CK_IN8": null, + "HCLK_TERM_CK_IN9": null, + "HCLK_TERM_PERFCLK0": null, + "HCLK_TERM_PERFCLK1": null, + "HCLK_TERM_PERFCLK2": null, + "HCLK_TERM_PERFCLK3": null + } } diff --git a/zynq7/tile_type_HCLK_VBRK.json b/zynq7/tile_type_HCLK_VBRK.json index 2525d57..628c7e8 100644 --- a/zynq7/tile_type_HCLK_VBRK.json +++ b/zynq7/tile_type_HCLK_VBRK.json @@ -2,44 +2,44 @@ "pips": {}, "sites": [], "tile_type": "HCLK_VBRK", - "wires": [ - "HCLK_VBRK_CK_BUFHCLK0", - "HCLK_VBRK_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK10", - "HCLK_VBRK_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK8", - "HCLK_VBRK_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK1", - "HCLK_VBRK_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK3", - "HCLK_VBRK_MUX_CLK0", - "HCLK_VBRK_MUX_CLK1", - "HCLK_VBRK_MUX_CLK10", - "HCLK_VBRK_MUX_CLK11", - "HCLK_VBRK_MUX_CLK12", - "HCLK_VBRK_MUX_CLK13", - "HCLK_VBRK_MUX_CLK2", - "HCLK_VBRK_MUX_CLK3", - "HCLK_VBRK_MUX_CLK4", - "HCLK_VBRK_MUX_CLK5", - "HCLK_VBRK_MUX_CLK6", - "HCLK_VBRK_MUX_CLK7", - "HCLK_VBRK_MUX_CLK8", - "HCLK_VBRK_MUX_CLK9", - "HCLK_VBRK_PHSR_PERFCLK0", - "HCLK_VBRK_PHSR_PERFCLK1", - "HCLK_VBRK_PHSR_PERFCLK2", - "HCLK_VBRK_PHSR_PERFCLK3", - "HCLK_VBRK_REFCK_EASTCLK0", - "HCLK_VBRK_REFCK_EASTCLK1", - "HCLK_VBRK_REFCK_WESTCLK0", - "HCLK_VBRK_REFCK_WESTCLK1" - ] + "wires": { + "HCLK_VBRK_CK_BUFHCLK0": null, + "HCLK_VBRK_CK_BUFHCLK1": null, + "HCLK_VBRK_CK_BUFHCLK10": null, + "HCLK_VBRK_CK_BUFHCLK11": null, + "HCLK_VBRK_CK_BUFHCLK2": null, + "HCLK_VBRK_CK_BUFHCLK3": null, + "HCLK_VBRK_CK_BUFHCLK4": null, + "HCLK_VBRK_CK_BUFHCLK5": null, + "HCLK_VBRK_CK_BUFHCLK6": null, + "HCLK_VBRK_CK_BUFHCLK7": null, + "HCLK_VBRK_CK_BUFHCLK8": null, + "HCLK_VBRK_CK_BUFHCLK9": null, + "HCLK_VBRK_CK_BUFRCLK0": null, + "HCLK_VBRK_CK_BUFRCLK1": null, + "HCLK_VBRK_CK_BUFRCLK2": null, + "HCLK_VBRK_CK_BUFRCLK3": null, + "HCLK_VBRK_MUX_CLK0": null, + "HCLK_VBRK_MUX_CLK1": null, + "HCLK_VBRK_MUX_CLK10": null, + "HCLK_VBRK_MUX_CLK11": null, + "HCLK_VBRK_MUX_CLK12": null, + "HCLK_VBRK_MUX_CLK13": null, + "HCLK_VBRK_MUX_CLK2": null, + "HCLK_VBRK_MUX_CLK3": null, + "HCLK_VBRK_MUX_CLK4": null, + "HCLK_VBRK_MUX_CLK5": null, + "HCLK_VBRK_MUX_CLK6": null, + "HCLK_VBRK_MUX_CLK7": null, + "HCLK_VBRK_MUX_CLK8": null, + "HCLK_VBRK_MUX_CLK9": null, + "HCLK_VBRK_PHSR_PERFCLK0": null, + "HCLK_VBRK_PHSR_PERFCLK1": null, + "HCLK_VBRK_PHSR_PERFCLK2": null, + "HCLK_VBRK_PHSR_PERFCLK3": null, + "HCLK_VBRK_REFCK_EASTCLK0": null, + "HCLK_VBRK_REFCK_EASTCLK1": null, + "HCLK_VBRK_REFCK_WESTCLK0": null, + "HCLK_VBRK_REFCK_WESTCLK1": null + } } diff --git a/zynq7/tile_type_HCLK_VFRAME.json b/zynq7/tile_type_HCLK_VFRAME.json index ca01e96..5f5152a 100644 --- a/zynq7/tile_type_HCLK_VFRAME.json +++ b/zynq7/tile_type_HCLK_VFRAME.json @@ -2,36 +2,36 @@ "pips": {}, "sites": [], "tile_type": "HCLK_VFRAME", - "wires": [ - "HCLK_VFRAME_CK_BUFHCLK0", - "HCLK_VFRAME_CK_BUFHCLK1", - "HCLK_VFRAME_CK_BUFHCLK10", - "HCLK_VFRAME_CK_BUFHCLK11", - "HCLK_VFRAME_CK_BUFHCLK2", - "HCLK_VFRAME_CK_BUFHCLK3", - "HCLK_VFRAME_CK_BUFHCLK4", - "HCLK_VFRAME_CK_BUFHCLK5", - "HCLK_VFRAME_CK_BUFHCLK6", - "HCLK_VFRAME_CK_BUFHCLK7", - "HCLK_VFRAME_CK_BUFHCLK8", - "HCLK_VFRAME_CK_BUFHCLK9", - "HCLK_VFRAME_CK_BUFRCLK0", - "HCLK_VFRAME_CK_BUFRCLK1", - "HCLK_VFRAME_CK_BUFRCLK2", - "HCLK_VFRAME_CK_BUFRCLK3", - "HCLK_VFRAME_CK_IN0", - "HCLK_VFRAME_CK_IN1", - "HCLK_VFRAME_CK_IN10", - "HCLK_VFRAME_CK_IN11", - "HCLK_VFRAME_CK_IN12", - "HCLK_VFRAME_CK_IN13", - "HCLK_VFRAME_CK_IN2", - "HCLK_VFRAME_CK_IN3", - "HCLK_VFRAME_CK_IN4", - "HCLK_VFRAME_CK_IN5", - "HCLK_VFRAME_CK_IN6", - "HCLK_VFRAME_CK_IN7", - "HCLK_VFRAME_CK_IN8", - "HCLK_VFRAME_CK_IN9" - ] + "wires": { + "HCLK_VFRAME_CK_BUFHCLK0": null, + "HCLK_VFRAME_CK_BUFHCLK1": null, + "HCLK_VFRAME_CK_BUFHCLK10": null, + "HCLK_VFRAME_CK_BUFHCLK11": null, + "HCLK_VFRAME_CK_BUFHCLK2": null, + "HCLK_VFRAME_CK_BUFHCLK3": null, + "HCLK_VFRAME_CK_BUFHCLK4": null, + "HCLK_VFRAME_CK_BUFHCLK5": null, + "HCLK_VFRAME_CK_BUFHCLK6": null, + "HCLK_VFRAME_CK_BUFHCLK7": null, + "HCLK_VFRAME_CK_BUFHCLK8": null, + "HCLK_VFRAME_CK_BUFHCLK9": null, + "HCLK_VFRAME_CK_BUFRCLK0": null, + "HCLK_VFRAME_CK_BUFRCLK1": null, + "HCLK_VFRAME_CK_BUFRCLK2": null, + "HCLK_VFRAME_CK_BUFRCLK3": null, + "HCLK_VFRAME_CK_IN0": null, + "HCLK_VFRAME_CK_IN1": null, + "HCLK_VFRAME_CK_IN10": null, + "HCLK_VFRAME_CK_IN11": null, + "HCLK_VFRAME_CK_IN12": null, + "HCLK_VFRAME_CK_IN13": null, + "HCLK_VFRAME_CK_IN2": null, + "HCLK_VFRAME_CK_IN3": null, + "HCLK_VFRAME_CK_IN4": null, + "HCLK_VFRAME_CK_IN5": null, + "HCLK_VFRAME_CK_IN6": null, + "HCLK_VFRAME_CK_IN7": null, + "HCLK_VFRAME_CK_IN8": null, + "HCLK_VFRAME_CK_IN9": null + } } diff --git a/zynq7/tile_type_INT_FEEDTHRU_1.json b/zynq7/tile_type_INT_FEEDTHRU_1.json index eecff34..8504c78 100644 --- a/zynq7/tile_type_INT_FEEDTHRU_1.json +++ b/zynq7/tile_type_INT_FEEDTHRU_1.json @@ -2,132 +2,132 @@ "pips": {}, "sites": [], "tile_type": "INT_FEEDTHRU_1", - "wires": [ - "INT_FEEDTHRU_1_EE2A0", - "INT_FEEDTHRU_1_EE2A1", - "INT_FEEDTHRU_1_EE2A2", - "INT_FEEDTHRU_1_EE2A3", - "INT_FEEDTHRU_1_EE2BEG0", - "INT_FEEDTHRU_1_EE2BEG1", - "INT_FEEDTHRU_1_EE2BEG2", - "INT_FEEDTHRU_1_EE2BEG3", - "INT_FEEDTHRU_1_EE4A0", - "INT_FEEDTHRU_1_EE4A1", - "INT_FEEDTHRU_1_EE4A2", - "INT_FEEDTHRU_1_EE4A3", - "INT_FEEDTHRU_1_EE4B0", - "INT_FEEDTHRU_1_EE4B1", - "INT_FEEDTHRU_1_EE4B2", - "INT_FEEDTHRU_1_EE4B3", - "INT_FEEDTHRU_1_EE4BEG0", - "INT_FEEDTHRU_1_EE4BEG1", - "INT_FEEDTHRU_1_EE4BEG2", - "INT_FEEDTHRU_1_EE4BEG3", - "INT_FEEDTHRU_1_EE4C0", - "INT_FEEDTHRU_1_EE4C1", - "INT_FEEDTHRU_1_EE4C2", - "INT_FEEDTHRU_1_EE4C3", - "INT_FEEDTHRU_1_EL1BEG0", - "INT_FEEDTHRU_1_EL1BEG1", - "INT_FEEDTHRU_1_EL1BEG2", - "INT_FEEDTHRU_1_EL1BEG3", - "INT_FEEDTHRU_1_ER1BEG0", - "INT_FEEDTHRU_1_ER1BEG1", - "INT_FEEDTHRU_1_ER1BEG2", - "INT_FEEDTHRU_1_ER1BEG3", - "INT_FEEDTHRU_1_LH1", - "INT_FEEDTHRU_1_LH10", - "INT_FEEDTHRU_1_LH11", - "INT_FEEDTHRU_1_LH12", - "INT_FEEDTHRU_1_LH2", - "INT_FEEDTHRU_1_LH3", - "INT_FEEDTHRU_1_LH4", - "INT_FEEDTHRU_1_LH5", - "INT_FEEDTHRU_1_LH6", - "INT_FEEDTHRU_1_LH7", - "INT_FEEDTHRU_1_LH8", - "INT_FEEDTHRU_1_LH9", - "INT_FEEDTHRU_1_MONITOR_N", - "INT_FEEDTHRU_1_MONITOR_P", - "INT_FEEDTHRU_1_NE2A0", - "INT_FEEDTHRU_1_NE2A1", - "INT_FEEDTHRU_1_NE2A2", - "INT_FEEDTHRU_1_NE2A3", - "INT_FEEDTHRU_1_NE4BEG0", - "INT_FEEDTHRU_1_NE4BEG1", - "INT_FEEDTHRU_1_NE4BEG2", - "INT_FEEDTHRU_1_NE4BEG3", - "INT_FEEDTHRU_1_NE4C0", - "INT_FEEDTHRU_1_NE4C1", - "INT_FEEDTHRU_1_NE4C2", - "INT_FEEDTHRU_1_NE4C3", - "INT_FEEDTHRU_1_NW2A0", - "INT_FEEDTHRU_1_NW2A1", - "INT_FEEDTHRU_1_NW2A2", - "INT_FEEDTHRU_1_NW2A3", - "INT_FEEDTHRU_1_NW4A0", - "INT_FEEDTHRU_1_NW4A1", - "INT_FEEDTHRU_1_NW4A2", - "INT_FEEDTHRU_1_NW4A3", - "INT_FEEDTHRU_1_NW4END0", - "INT_FEEDTHRU_1_NW4END1", - "INT_FEEDTHRU_1_NW4END2", - "INT_FEEDTHRU_1_NW4END3", - "INT_FEEDTHRU_1_SE2A0", - "INT_FEEDTHRU_1_SE2A1", - "INT_FEEDTHRU_1_SE2A2", - "INT_FEEDTHRU_1_SE2A3", - "INT_FEEDTHRU_1_SE4BEG0", - "INT_FEEDTHRU_1_SE4BEG1", - "INT_FEEDTHRU_1_SE4BEG2", - "INT_FEEDTHRU_1_SE4BEG3", - "INT_FEEDTHRU_1_SE4C0", - "INT_FEEDTHRU_1_SE4C1", - "INT_FEEDTHRU_1_SE4C2", - "INT_FEEDTHRU_1_SE4C3", - "INT_FEEDTHRU_1_SW2A0", - "INT_FEEDTHRU_1_SW2A1", - "INT_FEEDTHRU_1_SW2A2", - "INT_FEEDTHRU_1_SW2A3", - "INT_FEEDTHRU_1_SW4A0", - "INT_FEEDTHRU_1_SW4A1", - "INT_FEEDTHRU_1_SW4A2", - "INT_FEEDTHRU_1_SW4A3", - "INT_FEEDTHRU_1_SW4END0", - "INT_FEEDTHRU_1_SW4END1", - "INT_FEEDTHRU_1_SW4END2", - "INT_FEEDTHRU_1_SW4END3", - "INT_FEEDTHRU_1_WL1END0", - "INT_FEEDTHRU_1_WL1END1", - "INT_FEEDTHRU_1_WL1END2", - "INT_FEEDTHRU_1_WL1END3", - "INT_FEEDTHRU_1_WR1END0", - "INT_FEEDTHRU_1_WR1END1", - "INT_FEEDTHRU_1_WR1END2", - "INT_FEEDTHRU_1_WR1END3", - "INT_FEEDTHRU_1_WW2A0", - "INT_FEEDTHRU_1_WW2A1", - "INT_FEEDTHRU_1_WW2A2", - "INT_FEEDTHRU_1_WW2A3", - "INT_FEEDTHRU_1_WW2END0", - "INT_FEEDTHRU_1_WW2END1", - "INT_FEEDTHRU_1_WW2END2", - "INT_FEEDTHRU_1_WW2END3", - "INT_FEEDTHRU_1_WW4A0", - "INT_FEEDTHRU_1_WW4A1", - "INT_FEEDTHRU_1_WW4A2", - "INT_FEEDTHRU_1_WW4A3", - "INT_FEEDTHRU_1_WW4B0", - "INT_FEEDTHRU_1_WW4B1", - "INT_FEEDTHRU_1_WW4B2", - "INT_FEEDTHRU_1_WW4B3", - "INT_FEEDTHRU_1_WW4C0", - "INT_FEEDTHRU_1_WW4C1", - "INT_FEEDTHRU_1_WW4C2", - "INT_FEEDTHRU_1_WW4C3", - "INT_FEEDTHRU_1_WW4END0", - "INT_FEEDTHRU_1_WW4END1", - "INT_FEEDTHRU_1_WW4END2", - "INT_FEEDTHRU_1_WW4END3" - ] + "wires": { + "INT_FEEDTHRU_1_EE2A0": null, + "INT_FEEDTHRU_1_EE2A1": null, + "INT_FEEDTHRU_1_EE2A2": null, + "INT_FEEDTHRU_1_EE2A3": null, + "INT_FEEDTHRU_1_EE2BEG0": null, + "INT_FEEDTHRU_1_EE2BEG1": null, + "INT_FEEDTHRU_1_EE2BEG2": null, + "INT_FEEDTHRU_1_EE2BEG3": null, + "INT_FEEDTHRU_1_EE4A0": null, + "INT_FEEDTHRU_1_EE4A1": null, + "INT_FEEDTHRU_1_EE4A2": null, + "INT_FEEDTHRU_1_EE4A3": null, + "INT_FEEDTHRU_1_EE4B0": null, + "INT_FEEDTHRU_1_EE4B1": null, + "INT_FEEDTHRU_1_EE4B2": null, + "INT_FEEDTHRU_1_EE4B3": null, + "INT_FEEDTHRU_1_EE4BEG0": null, + "INT_FEEDTHRU_1_EE4BEG1": null, + "INT_FEEDTHRU_1_EE4BEG2": null, + "INT_FEEDTHRU_1_EE4BEG3": null, + "INT_FEEDTHRU_1_EE4C0": null, + "INT_FEEDTHRU_1_EE4C1": null, + "INT_FEEDTHRU_1_EE4C2": null, + "INT_FEEDTHRU_1_EE4C3": null, + "INT_FEEDTHRU_1_EL1BEG0": null, + "INT_FEEDTHRU_1_EL1BEG1": null, + "INT_FEEDTHRU_1_EL1BEG2": null, + "INT_FEEDTHRU_1_EL1BEG3": null, + "INT_FEEDTHRU_1_ER1BEG0": null, + "INT_FEEDTHRU_1_ER1BEG1": null, + "INT_FEEDTHRU_1_ER1BEG2": null, + "INT_FEEDTHRU_1_ER1BEG3": null, + "INT_FEEDTHRU_1_LH1": null, + "INT_FEEDTHRU_1_LH10": null, + "INT_FEEDTHRU_1_LH11": null, + "INT_FEEDTHRU_1_LH12": null, + "INT_FEEDTHRU_1_LH2": null, + "INT_FEEDTHRU_1_LH3": null, + "INT_FEEDTHRU_1_LH4": null, + "INT_FEEDTHRU_1_LH5": null, + "INT_FEEDTHRU_1_LH6": null, + "INT_FEEDTHRU_1_LH7": null, + "INT_FEEDTHRU_1_LH8": null, + "INT_FEEDTHRU_1_LH9": null, + "INT_FEEDTHRU_1_MONITOR_N": null, + "INT_FEEDTHRU_1_MONITOR_P": null, + "INT_FEEDTHRU_1_NE2A0": null, + "INT_FEEDTHRU_1_NE2A1": null, + "INT_FEEDTHRU_1_NE2A2": null, + "INT_FEEDTHRU_1_NE2A3": null, + "INT_FEEDTHRU_1_NE4BEG0": null, + "INT_FEEDTHRU_1_NE4BEG1": null, + "INT_FEEDTHRU_1_NE4BEG2": null, + "INT_FEEDTHRU_1_NE4BEG3": null, + "INT_FEEDTHRU_1_NE4C0": null, + "INT_FEEDTHRU_1_NE4C1": null, + "INT_FEEDTHRU_1_NE4C2": null, + "INT_FEEDTHRU_1_NE4C3": null, + "INT_FEEDTHRU_1_NW2A0": null, + "INT_FEEDTHRU_1_NW2A1": null, + "INT_FEEDTHRU_1_NW2A2": null, + "INT_FEEDTHRU_1_NW2A3": null, + "INT_FEEDTHRU_1_NW4A0": null, + "INT_FEEDTHRU_1_NW4A1": null, + "INT_FEEDTHRU_1_NW4A2": null, + "INT_FEEDTHRU_1_NW4A3": null, + "INT_FEEDTHRU_1_NW4END0": null, + "INT_FEEDTHRU_1_NW4END1": null, + "INT_FEEDTHRU_1_NW4END2": null, + "INT_FEEDTHRU_1_NW4END3": null, + "INT_FEEDTHRU_1_SE2A0": null, + "INT_FEEDTHRU_1_SE2A1": null, + "INT_FEEDTHRU_1_SE2A2": null, + "INT_FEEDTHRU_1_SE2A3": null, + "INT_FEEDTHRU_1_SE4BEG0": null, + "INT_FEEDTHRU_1_SE4BEG1": null, + "INT_FEEDTHRU_1_SE4BEG2": null, + "INT_FEEDTHRU_1_SE4BEG3": null, + "INT_FEEDTHRU_1_SE4C0": null, + "INT_FEEDTHRU_1_SE4C1": null, + "INT_FEEDTHRU_1_SE4C2": null, + "INT_FEEDTHRU_1_SE4C3": null, + "INT_FEEDTHRU_1_SW2A0": null, + "INT_FEEDTHRU_1_SW2A1": null, + "INT_FEEDTHRU_1_SW2A2": null, + "INT_FEEDTHRU_1_SW2A3": null, + "INT_FEEDTHRU_1_SW4A0": null, + "INT_FEEDTHRU_1_SW4A1": null, + "INT_FEEDTHRU_1_SW4A2": null, + "INT_FEEDTHRU_1_SW4A3": null, + "INT_FEEDTHRU_1_SW4END0": null, + "INT_FEEDTHRU_1_SW4END1": null, + "INT_FEEDTHRU_1_SW4END2": null, + "INT_FEEDTHRU_1_SW4END3": null, + "INT_FEEDTHRU_1_WL1END0": null, + "INT_FEEDTHRU_1_WL1END1": null, + "INT_FEEDTHRU_1_WL1END2": null, + "INT_FEEDTHRU_1_WL1END3": null, + "INT_FEEDTHRU_1_WR1END0": null, + "INT_FEEDTHRU_1_WR1END1": null, + "INT_FEEDTHRU_1_WR1END2": null, + "INT_FEEDTHRU_1_WR1END3": null, + "INT_FEEDTHRU_1_WW2A0": null, + "INT_FEEDTHRU_1_WW2A1": null, + "INT_FEEDTHRU_1_WW2A2": null, + "INT_FEEDTHRU_1_WW2A3": null, + "INT_FEEDTHRU_1_WW2END0": null, + "INT_FEEDTHRU_1_WW2END1": null, + "INT_FEEDTHRU_1_WW2END2": null, + "INT_FEEDTHRU_1_WW2END3": null, + "INT_FEEDTHRU_1_WW4A0": null, + "INT_FEEDTHRU_1_WW4A1": null, + "INT_FEEDTHRU_1_WW4A2": null, + "INT_FEEDTHRU_1_WW4A3": null, + "INT_FEEDTHRU_1_WW4B0": null, + "INT_FEEDTHRU_1_WW4B1": null, + "INT_FEEDTHRU_1_WW4B2": null, + "INT_FEEDTHRU_1_WW4B3": null, + "INT_FEEDTHRU_1_WW4C0": null, + "INT_FEEDTHRU_1_WW4C1": null, + "INT_FEEDTHRU_1_WW4C2": null, + "INT_FEEDTHRU_1_WW4C3": null, + "INT_FEEDTHRU_1_WW4END0": null, + "INT_FEEDTHRU_1_WW4END1": null, + "INT_FEEDTHRU_1_WW4END2": null, + "INT_FEEDTHRU_1_WW4END3": null + } } diff --git a/zynq7/tile_type_INT_FEEDTHRU_2.json b/zynq7/tile_type_INT_FEEDTHRU_2.json index ea9fb16..5820f86 100644 --- a/zynq7/tile_type_INT_FEEDTHRU_2.json +++ b/zynq7/tile_type_INT_FEEDTHRU_2.json @@ -2,132 +2,132 @@ "pips": {}, "sites": [], "tile_type": "INT_FEEDTHRU_2", - "wires": [ - "INT_FEEDTHRU_2_EE2A0", - "INT_FEEDTHRU_2_EE2A1", - "INT_FEEDTHRU_2_EE2A2", - "INT_FEEDTHRU_2_EE2A3", - "INT_FEEDTHRU_2_EE2BEG0", - "INT_FEEDTHRU_2_EE2BEG1", - "INT_FEEDTHRU_2_EE2BEG2", - "INT_FEEDTHRU_2_EE2BEG3", - "INT_FEEDTHRU_2_EE4A0", - "INT_FEEDTHRU_2_EE4A1", - "INT_FEEDTHRU_2_EE4A2", - "INT_FEEDTHRU_2_EE4A3", - "INT_FEEDTHRU_2_EE4B0", - "INT_FEEDTHRU_2_EE4B1", - "INT_FEEDTHRU_2_EE4B2", - "INT_FEEDTHRU_2_EE4B3", - "INT_FEEDTHRU_2_EE4BEG0", - "INT_FEEDTHRU_2_EE4BEG1", - "INT_FEEDTHRU_2_EE4BEG2", - "INT_FEEDTHRU_2_EE4BEG3", - "INT_FEEDTHRU_2_EE4C0", - "INT_FEEDTHRU_2_EE4C1", - "INT_FEEDTHRU_2_EE4C2", - "INT_FEEDTHRU_2_EE4C3", - "INT_FEEDTHRU_2_EL1BEG0", - "INT_FEEDTHRU_2_EL1BEG1", - "INT_FEEDTHRU_2_EL1BEG2", - "INT_FEEDTHRU_2_EL1BEG3", - "INT_FEEDTHRU_2_ER1BEG0", - "INT_FEEDTHRU_2_ER1BEG1", - "INT_FEEDTHRU_2_ER1BEG2", - "INT_FEEDTHRU_2_ER1BEG3", - "INT_FEEDTHRU_2_LH1", - "INT_FEEDTHRU_2_LH10", - "INT_FEEDTHRU_2_LH11", - "INT_FEEDTHRU_2_LH12", - "INT_FEEDTHRU_2_LH2", - "INT_FEEDTHRU_2_LH3", - "INT_FEEDTHRU_2_LH4", - "INT_FEEDTHRU_2_LH5", - "INT_FEEDTHRU_2_LH6", - "INT_FEEDTHRU_2_LH7", - "INT_FEEDTHRU_2_LH8", - "INT_FEEDTHRU_2_LH9", - "INT_FEEDTHRU_2_MONITOR_N", - "INT_FEEDTHRU_2_MONITOR_P", - "INT_FEEDTHRU_2_NE2A0", - "INT_FEEDTHRU_2_NE2A1", - "INT_FEEDTHRU_2_NE2A2", - "INT_FEEDTHRU_2_NE2A3", - "INT_FEEDTHRU_2_NE4BEG0", - "INT_FEEDTHRU_2_NE4BEG1", - "INT_FEEDTHRU_2_NE4BEG2", - "INT_FEEDTHRU_2_NE4BEG3", - "INT_FEEDTHRU_2_NE4C0", - "INT_FEEDTHRU_2_NE4C1", - "INT_FEEDTHRU_2_NE4C2", - "INT_FEEDTHRU_2_NE4C3", - "INT_FEEDTHRU_2_NW2A0", - "INT_FEEDTHRU_2_NW2A1", - "INT_FEEDTHRU_2_NW2A2", - "INT_FEEDTHRU_2_NW2A3", - "INT_FEEDTHRU_2_NW4A0", - "INT_FEEDTHRU_2_NW4A1", - "INT_FEEDTHRU_2_NW4A2", - "INT_FEEDTHRU_2_NW4A3", - "INT_FEEDTHRU_2_NW4END0", - "INT_FEEDTHRU_2_NW4END1", - "INT_FEEDTHRU_2_NW4END2", - "INT_FEEDTHRU_2_NW4END3", - "INT_FEEDTHRU_2_SE2A0", - "INT_FEEDTHRU_2_SE2A1", - "INT_FEEDTHRU_2_SE2A2", - "INT_FEEDTHRU_2_SE2A3", - "INT_FEEDTHRU_2_SE4BEG0", - "INT_FEEDTHRU_2_SE4BEG1", - "INT_FEEDTHRU_2_SE4BEG2", - "INT_FEEDTHRU_2_SE4BEG3", - "INT_FEEDTHRU_2_SE4C0", - "INT_FEEDTHRU_2_SE4C1", - "INT_FEEDTHRU_2_SE4C2", - "INT_FEEDTHRU_2_SE4C3", - "INT_FEEDTHRU_2_SW2A0", - "INT_FEEDTHRU_2_SW2A1", - "INT_FEEDTHRU_2_SW2A2", - "INT_FEEDTHRU_2_SW2A3", - "INT_FEEDTHRU_2_SW4A0", - "INT_FEEDTHRU_2_SW4A1", - "INT_FEEDTHRU_2_SW4A2", - "INT_FEEDTHRU_2_SW4A3", - "INT_FEEDTHRU_2_SW4END0", - "INT_FEEDTHRU_2_SW4END1", - "INT_FEEDTHRU_2_SW4END2", - "INT_FEEDTHRU_2_SW4END3", - "INT_FEEDTHRU_2_WL1END0", - "INT_FEEDTHRU_2_WL1END1", - "INT_FEEDTHRU_2_WL1END2", - "INT_FEEDTHRU_2_WL1END3", - "INT_FEEDTHRU_2_WR1END0", - "INT_FEEDTHRU_2_WR1END1", - "INT_FEEDTHRU_2_WR1END2", - "INT_FEEDTHRU_2_WR1END3", - "INT_FEEDTHRU_2_WW2A0", - "INT_FEEDTHRU_2_WW2A1", - "INT_FEEDTHRU_2_WW2A2", - "INT_FEEDTHRU_2_WW2A3", - "INT_FEEDTHRU_2_WW2END0", - "INT_FEEDTHRU_2_WW2END1", - "INT_FEEDTHRU_2_WW2END2", - "INT_FEEDTHRU_2_WW2END3", - "INT_FEEDTHRU_2_WW4A0", - "INT_FEEDTHRU_2_WW4A1", - "INT_FEEDTHRU_2_WW4A2", - "INT_FEEDTHRU_2_WW4A3", - "INT_FEEDTHRU_2_WW4B0", - "INT_FEEDTHRU_2_WW4B1", - "INT_FEEDTHRU_2_WW4B2", - "INT_FEEDTHRU_2_WW4B3", - "INT_FEEDTHRU_2_WW4C0", - "INT_FEEDTHRU_2_WW4C1", - "INT_FEEDTHRU_2_WW4C2", - "INT_FEEDTHRU_2_WW4C3", - "INT_FEEDTHRU_2_WW4END0", - "INT_FEEDTHRU_2_WW4END1", - "INT_FEEDTHRU_2_WW4END2", - "INT_FEEDTHRU_2_WW4END3" - ] + "wires": { + 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"INT_INTERFACE_PSS_IMUX_B11", - "INT_INTERFACE_PSS_IMUX_B12", - "INT_INTERFACE_PSS_IMUX_B13", - "INT_INTERFACE_PSS_IMUX_B14", - "INT_INTERFACE_PSS_IMUX_B15", - "INT_INTERFACE_PSS_IMUX_B16", - "INT_INTERFACE_PSS_IMUX_B17", - "INT_INTERFACE_PSS_IMUX_B18", - "INT_INTERFACE_PSS_IMUX_B19", - "INT_INTERFACE_PSS_IMUX_B2", - "INT_INTERFACE_PSS_IMUX_B20", - "INT_INTERFACE_PSS_IMUX_B21", - "INT_INTERFACE_PSS_IMUX_B22", - "INT_INTERFACE_PSS_IMUX_B23", - "INT_INTERFACE_PSS_IMUX_B24", - "INT_INTERFACE_PSS_IMUX_B25", - "INT_INTERFACE_PSS_IMUX_B26", - "INT_INTERFACE_PSS_IMUX_B27", - "INT_INTERFACE_PSS_IMUX_B28", - "INT_INTERFACE_PSS_IMUX_B29", - "INT_INTERFACE_PSS_IMUX_B3", - "INT_INTERFACE_PSS_IMUX_B30", - "INT_INTERFACE_PSS_IMUX_B31", - "INT_INTERFACE_PSS_IMUX_B32", - "INT_INTERFACE_PSS_IMUX_B33", - "INT_INTERFACE_PSS_IMUX_B34", - "INT_INTERFACE_PSS_IMUX_B35", - "INT_INTERFACE_PSS_IMUX_B36", - "INT_INTERFACE_PSS_IMUX_B37", - "INT_INTERFACE_PSS_IMUX_B38", - "INT_INTERFACE_PSS_IMUX_B39", - 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"INT_INTERFACE_PSS_LOGIC_OUTS_L_B22", - "INT_INTERFACE_PSS_LOGIC_OUTS_L_B23", - "INT_INTERFACE_PSS_LOGIC_OUTS_L_B3", - "INT_INTERFACE_PSS_LOGIC_OUTS_L_B4", - "INT_INTERFACE_PSS_LOGIC_OUTS_L_B5", - "INT_INTERFACE_PSS_LOGIC_OUTS_L_B6", - "INT_INTERFACE_PSS_LOGIC_OUTS_L_B7", - "INT_INTERFACE_PSS_LOGIC_OUTS_L_B8", - "INT_INTERFACE_PSS_LOGIC_OUTS_L_B9", - "L_TERM_INT_LH0", - "L_TERM_INT_LH1", - "L_TERM_INT_LH2", - "L_TERM_INT_LH3", - "L_TERM_INT_LH4", - "L_TERM_INT_LH5", - "L_TERM_INT_NW2BEG0", - "L_TERM_INT_NW2BEG1", - "L_TERM_INT_NW2BEG2", - "L_TERM_INT_NW2BEG3", - "L_TERM_INT_NW4BEG0", - "L_TERM_INT_NW4BEG1", - "L_TERM_INT_NW4BEG2", - "L_TERM_INT_NW4BEG3", - "L_TERM_INT_NW4C0", - "L_TERM_INT_NW4C1", - "L_TERM_INT_NW4C2", - "L_TERM_INT_NW4C3", - "L_TERM_INT_SW2BEG0", - "L_TERM_INT_SW2BEG1", - "L_TERM_INT_SW2BEG2", - "L_TERM_INT_SW2BEG3", - "L_TERM_INT_SW4BEG0", - "L_TERM_INT_SW4BEG1", - "L_TERM_INT_SW4BEG2", - "L_TERM_INT_SW4BEG3", - "L_TERM_INT_SW4C0", - "L_TERM_INT_SW4C1", - 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"INT_INTERFACE_EE2BEG2", - "INT_INTERFACE_EE2BEG3", - "INT_INTERFACE_EE4A0", - "INT_INTERFACE_EE4A1", - "INT_INTERFACE_EE4A2", - "INT_INTERFACE_EE4A3", - "INT_INTERFACE_EE4B0", - "INT_INTERFACE_EE4B1", - "INT_INTERFACE_EE4B2", - "INT_INTERFACE_EE4B3", - "INT_INTERFACE_EE4BEG0", - "INT_INTERFACE_EE4BEG1", - "INT_INTERFACE_EE4BEG2", - "INT_INTERFACE_EE4BEG3", - "INT_INTERFACE_EE4C0", - "INT_INTERFACE_EE4C1", - "INT_INTERFACE_EE4C2", - "INT_INTERFACE_EE4C3", - "INT_INTERFACE_EL1BEG0", - "INT_INTERFACE_EL1BEG1", - "INT_INTERFACE_EL1BEG2", - "INT_INTERFACE_EL1BEG3", - "INT_INTERFACE_ER1BEG0", - "INT_INTERFACE_ER1BEG1", - "INT_INTERFACE_ER1BEG2", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_FAN0", - "INT_INTERFACE_FAN1", - "INT_INTERFACE_FAN2", - "INT_INTERFACE_FAN3", - "INT_INTERFACE_FAN4", - "INT_INTERFACE_FAN5", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_FAN7", - "INT_INTERFACE_IMUX0", - "INT_INTERFACE_IMUX1", - "INT_INTERFACE_IMUX10", - "INT_INTERFACE_IMUX11", - "INT_INTERFACE_IMUX12", - "INT_INTERFACE_IMUX13", - "INT_INTERFACE_IMUX14", - "INT_INTERFACE_IMUX15", - "INT_INTERFACE_IMUX16", - "INT_INTERFACE_IMUX17", - "INT_INTERFACE_IMUX18", - "INT_INTERFACE_IMUX19", - "INT_INTERFACE_IMUX2", - "INT_INTERFACE_IMUX20", - "INT_INTERFACE_IMUX21", - "INT_INTERFACE_IMUX22", - "INT_INTERFACE_IMUX23", - "INT_INTERFACE_IMUX24", - "INT_INTERFACE_IMUX25", - "INT_INTERFACE_IMUX26", - "INT_INTERFACE_IMUX27", - "INT_INTERFACE_IMUX28", - "INT_INTERFACE_IMUX29", - "INT_INTERFACE_IMUX3", - "INT_INTERFACE_IMUX30", - "INT_INTERFACE_IMUX31", - "INT_INTERFACE_IMUX32", - "INT_INTERFACE_IMUX33", - "INT_INTERFACE_IMUX34", - "INT_INTERFACE_IMUX35", - "INT_INTERFACE_IMUX36", - "INT_INTERFACE_IMUX37", - "INT_INTERFACE_IMUX38", - "INT_INTERFACE_IMUX39", - "INT_INTERFACE_IMUX4", - "INT_INTERFACE_IMUX40", - "INT_INTERFACE_IMUX41", - "INT_INTERFACE_IMUX42", - "INT_INTERFACE_IMUX43", - "INT_INTERFACE_IMUX44", - "INT_INTERFACE_IMUX45", - "INT_INTERFACE_IMUX46", - "INT_INTERFACE_IMUX47", - "INT_INTERFACE_IMUX5", - "INT_INTERFACE_IMUX6", - "INT_INTERFACE_IMUX7", - "INT_INTERFACE_IMUX8", - "INT_INTERFACE_IMUX9", - "INT_INTERFACE_LH1", - "INT_INTERFACE_LH10", - "INT_INTERFACE_LH11", - "INT_INTERFACE_LH12", - "INT_INTERFACE_LH2", - "INT_INTERFACE_LH3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_LH5", - "INT_INTERFACE_LH6", - "INT_INTERFACE_LH7", - "INT_INTERFACE_LH8", - "INT_INTERFACE_LH9", - "INT_INTERFACE_LOGIC_OUTS0", - "INT_INTERFACE_LOGIC_OUTS1", - "INT_INTERFACE_LOGIC_OUTS10", - "INT_INTERFACE_LOGIC_OUTS11", - "INT_INTERFACE_LOGIC_OUTS12", - "INT_INTERFACE_LOGIC_OUTS13", - "INT_INTERFACE_LOGIC_OUTS14", - "INT_INTERFACE_LOGIC_OUTS15", - "INT_INTERFACE_LOGIC_OUTS16", - "INT_INTERFACE_LOGIC_OUTS17", - "INT_INTERFACE_LOGIC_OUTS18", - "INT_INTERFACE_LOGIC_OUTS19", - "INT_INTERFACE_LOGIC_OUTS2", - "INT_INTERFACE_LOGIC_OUTS20", - "INT_INTERFACE_LOGIC_OUTS21", - "INT_INTERFACE_LOGIC_OUTS22", - "INT_INTERFACE_LOGIC_OUTS23", - "INT_INTERFACE_LOGIC_OUTS3", - "INT_INTERFACE_LOGIC_OUTS4", - "INT_INTERFACE_LOGIC_OUTS5", - "INT_INTERFACE_LOGIC_OUTS6", - "INT_INTERFACE_LOGIC_OUTS7", - "INT_INTERFACE_LOGIC_OUTS8", - "INT_INTERFACE_LOGIC_OUTS9", - "INT_INTERFACE_LOGIC_OUTS_B0", - "INT_INTERFACE_LOGIC_OUTS_B1", - "INT_INTERFACE_LOGIC_OUTS_B10", - "INT_INTERFACE_LOGIC_OUTS_B11", - "INT_INTERFACE_LOGIC_OUTS_B12", - "INT_INTERFACE_LOGIC_OUTS_B13", - "INT_INTERFACE_LOGIC_OUTS_B14", - "INT_INTERFACE_LOGIC_OUTS_B15", - "INT_INTERFACE_LOGIC_OUTS_B16", - "INT_INTERFACE_LOGIC_OUTS_B17", - "INT_INTERFACE_LOGIC_OUTS_B18", - "INT_INTERFACE_LOGIC_OUTS_B19", - "INT_INTERFACE_LOGIC_OUTS_B2", - "INT_INTERFACE_LOGIC_OUTS_B20", - "INT_INTERFACE_LOGIC_OUTS_B21", - "INT_INTERFACE_LOGIC_OUTS_B22", - "INT_INTERFACE_LOGIC_OUTS_B23", - "INT_INTERFACE_LOGIC_OUTS_B3", - "INT_INTERFACE_LOGIC_OUTS_B4", - "INT_INTERFACE_LOGIC_OUTS_B5", - "INT_INTERFACE_LOGIC_OUTS_B6", - "INT_INTERFACE_LOGIC_OUTS_B7", - "INT_INTERFACE_LOGIC_OUTS_B8", - "INT_INTERFACE_LOGIC_OUTS_B9", - "INT_INTERFACE_MONITOR_N", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_NE2A1", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_NE4BEG2", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_NE4C1", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_NW4A1", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_PHASER_TO_IO_ICLK", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", - "INT_INTERFACE_PHASER_TO_IO_OCLK", - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_WW4A0", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_WW4END3", - "L_INT_INTER_DQS_IOTOPHASER" - ] + "wires": { + "INT_INTERFACE_BLOCK_OUTS_B0": null, + "INT_INTERFACE_BLOCK_OUTS_B1": null, + "INT_INTERFACE_BLOCK_OUTS_B2": null, + "INT_INTERFACE_BLOCK_OUTS_B3": null, + "INT_INTERFACE_BYP0": null, + "INT_INTERFACE_BYP1": null, + "INT_INTERFACE_BYP2": null, + "INT_INTERFACE_BYP3": null, + "INT_INTERFACE_BYP4": null, + "INT_INTERFACE_BYP5": null, + "INT_INTERFACE_BYP6": null, + "INT_INTERFACE_BYP7": null, + "INT_INTERFACE_CLK0": null, + "INT_INTERFACE_CLK1": null, + "INT_INTERFACE_CTRL0": null, + "INT_INTERFACE_CTRL1": null, + "INT_INTERFACE_EE2A0": null, + "INT_INTERFACE_EE2A1": null, + "INT_INTERFACE_EE2A2": null, + "INT_INTERFACE_EE2A3": null, + "INT_INTERFACE_EE2BEG0": null, + "INT_INTERFACE_EE2BEG1": null, + "INT_INTERFACE_EE2BEG2": null, + "INT_INTERFACE_EE2BEG3": null, + "INT_INTERFACE_EE4A0": null, + "INT_INTERFACE_EE4A1": null, + "INT_INTERFACE_EE4A2": null, + "INT_INTERFACE_EE4A3": null, + "INT_INTERFACE_EE4B0": null, + "INT_INTERFACE_EE4B1": null, + "INT_INTERFACE_EE4B2": null, + "INT_INTERFACE_EE4B3": null, + "INT_INTERFACE_EE4BEG0": null, + "INT_INTERFACE_EE4BEG1": null, + "INT_INTERFACE_EE4BEG2": null, + "INT_INTERFACE_EE4BEG3": null, + "INT_INTERFACE_EE4C0": null, + "INT_INTERFACE_EE4C1": null, + "INT_INTERFACE_EE4C2": null, + "INT_INTERFACE_EE4C3": null, + "INT_INTERFACE_EL1BEG0": null, + "INT_INTERFACE_EL1BEG1": null, + "INT_INTERFACE_EL1BEG2": null, + "INT_INTERFACE_EL1BEG3": null, + "INT_INTERFACE_ER1BEG0": null, + "INT_INTERFACE_ER1BEG1": null, + "INT_INTERFACE_ER1BEG2": null, + "INT_INTERFACE_ER1BEG3": null, + "INT_INTERFACE_FAN0": null, + "INT_INTERFACE_FAN1": null, + "INT_INTERFACE_FAN2": null, + "INT_INTERFACE_FAN3": null, + "INT_INTERFACE_FAN4": null, + "INT_INTERFACE_FAN5": null, + "INT_INTERFACE_FAN6": null, + "INT_INTERFACE_FAN7": null, + "INT_INTERFACE_IMUX0": null, + "INT_INTERFACE_IMUX1": null, + "INT_INTERFACE_IMUX10": null, + "INT_INTERFACE_IMUX11": null, + "INT_INTERFACE_IMUX12": null, + "INT_INTERFACE_IMUX13": null, + "INT_INTERFACE_IMUX14": null, + "INT_INTERFACE_IMUX15": null, + "INT_INTERFACE_IMUX16": null, + "INT_INTERFACE_IMUX17": null, + "INT_INTERFACE_IMUX18": null, + "INT_INTERFACE_IMUX19": null, + "INT_INTERFACE_IMUX2": null, + "INT_INTERFACE_IMUX20": null, + "INT_INTERFACE_IMUX21": null, + "INT_INTERFACE_IMUX22": null, + "INT_INTERFACE_IMUX23": null, + "INT_INTERFACE_IMUX24": null, + "INT_INTERFACE_IMUX25": null, + "INT_INTERFACE_IMUX26": null, + "INT_INTERFACE_IMUX27": null, + "INT_INTERFACE_IMUX28": null, + "INT_INTERFACE_IMUX29": null, + "INT_INTERFACE_IMUX3": null, + "INT_INTERFACE_IMUX30": null, + "INT_INTERFACE_IMUX31": null, + "INT_INTERFACE_IMUX32": null, + "INT_INTERFACE_IMUX33": null, + "INT_INTERFACE_IMUX34": null, + "INT_INTERFACE_IMUX35": null, + "INT_INTERFACE_IMUX36": null, + "INT_INTERFACE_IMUX37": null, + "INT_INTERFACE_IMUX38": null, + "INT_INTERFACE_IMUX39": null, + "INT_INTERFACE_IMUX4": null, + "INT_INTERFACE_IMUX40": null, + "INT_INTERFACE_IMUX41": null, + "INT_INTERFACE_IMUX42": null, + "INT_INTERFACE_IMUX43": null, + "INT_INTERFACE_IMUX44": null, + "INT_INTERFACE_IMUX45": null, + "INT_INTERFACE_IMUX46": null, + "INT_INTERFACE_IMUX47": null, + "INT_INTERFACE_IMUX5": null, + "INT_INTERFACE_IMUX6": null, + "INT_INTERFACE_IMUX7": null, + "INT_INTERFACE_IMUX8": null, + "INT_INTERFACE_IMUX9": null, + "INT_INTERFACE_LH1": null, + "INT_INTERFACE_LH10": null, + "INT_INTERFACE_LH11": null, + "INT_INTERFACE_LH12": null, + "INT_INTERFACE_LH2": null, + "INT_INTERFACE_LH3": null, + "INT_INTERFACE_LH4": null, + "INT_INTERFACE_LH5": null, + "INT_INTERFACE_LH6": null, + "INT_INTERFACE_LH7": null, + "INT_INTERFACE_LH8": null, + "INT_INTERFACE_LH9": null, + "INT_INTERFACE_LOGIC_OUTS0": null, + "INT_INTERFACE_LOGIC_OUTS1": null, + "INT_INTERFACE_LOGIC_OUTS10": null, + "INT_INTERFACE_LOGIC_OUTS11": null, + "INT_INTERFACE_LOGIC_OUTS12": null, + "INT_INTERFACE_LOGIC_OUTS13": null, + "INT_INTERFACE_LOGIC_OUTS14": null, + "INT_INTERFACE_LOGIC_OUTS15": null, + "INT_INTERFACE_LOGIC_OUTS16": null, + "INT_INTERFACE_LOGIC_OUTS17": null, + "INT_INTERFACE_LOGIC_OUTS18": null, + "INT_INTERFACE_LOGIC_OUTS19": null, + "INT_INTERFACE_LOGIC_OUTS2": null, + "INT_INTERFACE_LOGIC_OUTS20": null, + "INT_INTERFACE_LOGIC_OUTS21": null, + "INT_INTERFACE_LOGIC_OUTS22": null, + "INT_INTERFACE_LOGIC_OUTS23": null, + "INT_INTERFACE_LOGIC_OUTS3": null, + "INT_INTERFACE_LOGIC_OUTS4": null, + "INT_INTERFACE_LOGIC_OUTS5": null, + "INT_INTERFACE_LOGIC_OUTS6": null, + "INT_INTERFACE_LOGIC_OUTS7": null, + "INT_INTERFACE_LOGIC_OUTS8": null, + "INT_INTERFACE_LOGIC_OUTS9": null, + "INT_INTERFACE_LOGIC_OUTS_B0": null, + "INT_INTERFACE_LOGIC_OUTS_B1": null, + "INT_INTERFACE_LOGIC_OUTS_B10": null, + "INT_INTERFACE_LOGIC_OUTS_B11": null, + "INT_INTERFACE_LOGIC_OUTS_B12": null, + "INT_INTERFACE_LOGIC_OUTS_B13": null, + "INT_INTERFACE_LOGIC_OUTS_B14": null, + "INT_INTERFACE_LOGIC_OUTS_B15": null, + "INT_INTERFACE_LOGIC_OUTS_B16": null, + "INT_INTERFACE_LOGIC_OUTS_B17": null, + "INT_INTERFACE_LOGIC_OUTS_B18": null, + "INT_INTERFACE_LOGIC_OUTS_B19": null, + "INT_INTERFACE_LOGIC_OUTS_B2": null, + "INT_INTERFACE_LOGIC_OUTS_B20": null, + "INT_INTERFACE_LOGIC_OUTS_B21": null, + "INT_INTERFACE_LOGIC_OUTS_B22": null, + "INT_INTERFACE_LOGIC_OUTS_B23": null, + "INT_INTERFACE_LOGIC_OUTS_B3": null, + "INT_INTERFACE_LOGIC_OUTS_B4": null, + "INT_INTERFACE_LOGIC_OUTS_B5": null, + "INT_INTERFACE_LOGIC_OUTS_B6": null, + "INT_INTERFACE_LOGIC_OUTS_B7": null, + "INT_INTERFACE_LOGIC_OUTS_B8": null, + "INT_INTERFACE_LOGIC_OUTS_B9": null, + "INT_INTERFACE_MONITOR_N": null, + "INT_INTERFACE_MONITOR_P": null, + "INT_INTERFACE_NE2A0": null, + "INT_INTERFACE_NE2A1": null, + "INT_INTERFACE_NE2A2": null, + "INT_INTERFACE_NE2A3": null, + "INT_INTERFACE_NE4BEG0": null, + "INT_INTERFACE_NE4BEG1": null, + "INT_INTERFACE_NE4BEG2": null, + "INT_INTERFACE_NE4BEG3": null, + "INT_INTERFACE_NE4C0": null, + "INT_INTERFACE_NE4C1": null, + "INT_INTERFACE_NE4C2": null, + "INT_INTERFACE_NE4C3": null, + "INT_INTERFACE_NW2A0": null, + "INT_INTERFACE_NW2A1": null, + "INT_INTERFACE_NW2A2": null, + "INT_INTERFACE_NW2A3": null, + "INT_INTERFACE_NW4A0": null, + "INT_INTERFACE_NW4A1": null, + "INT_INTERFACE_NW4A2": null, + "INT_INTERFACE_NW4A3": null, + "INT_INTERFACE_NW4END0": null, + "INT_INTERFACE_NW4END1": null, + "INT_INTERFACE_NW4END2": null, + "INT_INTERFACE_NW4END3": null, + "INT_INTERFACE_PHASER_TO_IO_ICLK": null, + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90": null, + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV": null, + "INT_INTERFACE_SE2A0": null, + "INT_INTERFACE_SE2A1": null, + "INT_INTERFACE_SE2A2": null, + "INT_INTERFACE_SE2A3": null, + "INT_INTERFACE_SE4BEG0": null, + "INT_INTERFACE_SE4BEG1": null, + "INT_INTERFACE_SE4BEG2": null, + "INT_INTERFACE_SE4BEG3": null, + "INT_INTERFACE_SE4C0": null, + "INT_INTERFACE_SE4C1": null, + "INT_INTERFACE_SE4C2": null, + "INT_INTERFACE_SE4C3": null, + "INT_INTERFACE_SW2A0": null, + "INT_INTERFACE_SW2A1": null, + "INT_INTERFACE_SW2A2": null, + "INT_INTERFACE_SW2A3": null, + "INT_INTERFACE_SW4A0": null, + "INT_INTERFACE_SW4A1": null, + "INT_INTERFACE_SW4A2": null, + "INT_INTERFACE_SW4A3": null, + "INT_INTERFACE_SW4END0": null, + "INT_INTERFACE_SW4END1": null, + "INT_INTERFACE_SW4END2": null, + "INT_INTERFACE_SW4END3": null, + "INT_INTERFACE_WL1END0": null, + "INT_INTERFACE_WL1END1": null, + "INT_INTERFACE_WL1END2": null, + "INT_INTERFACE_WL1END3": null, + "INT_INTERFACE_WR1END0": null, + "INT_INTERFACE_WR1END1": null, + "INT_INTERFACE_WR1END2": null, + "INT_INTERFACE_WR1END3": null, + "INT_INTERFACE_WW2A0": null, + "INT_INTERFACE_WW2A1": null, + "INT_INTERFACE_WW2A2": null, + "INT_INTERFACE_WW2A3": null, + "INT_INTERFACE_WW2END0": null, + "INT_INTERFACE_WW2END1": null, + "INT_INTERFACE_WW2END2": null, + "INT_INTERFACE_WW2END3": null, + "INT_INTERFACE_WW4A0": null, + "INT_INTERFACE_WW4A1": null, + "INT_INTERFACE_WW4A2": null, + "INT_INTERFACE_WW4A3": null, + "INT_INTERFACE_WW4B0": null, + "INT_INTERFACE_WW4B1": null, + "INT_INTERFACE_WW4B2": null, + "INT_INTERFACE_WW4B3": null, + "INT_INTERFACE_WW4C0": null, + "INT_INTERFACE_WW4C1": null, + "INT_INTERFACE_WW4C2": null, + "INT_INTERFACE_WW4C3": null, + "INT_INTERFACE_WW4END0": null, + "INT_INTERFACE_WW4END1": null, + "INT_INTERFACE_WW4END2": null, + "INT_INTERFACE_WW4END3": null, + "L_INT_INTER_DQS_IOTOPHASER": null + } } diff --git a/zynq7/tile_type_INT_L.json b/zynq7/tile_type_INT_L.json index 0323024..71d2eff 100644 --- a/zynq7/tile_type_INT_L.json +++ b/zynq7/tile_type_INT_L.json @@ -2,26161 +2,104638 @@ "pips": { "INT_L.BYP_ALT0->>BYP_BOUNCE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.049", + "0.059", + "0.147", + "0.178" + ], + "in_cap": "0.000", + "res": "1476.4880625" + }, "dst_wire": "BYP_BOUNCE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.049", + "0.059", + "0.147", + "0.178" + ], + "in_cap": "0.000", + "res": "1476.4880625" + }, "src_wire": "BYP_ALT0" }, "INT_L.BYP_ALT0->>BYP_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.055", + "0.148", + "0.179" + ], + "in_cap": "0.000", + "res": "3489.880625" + }, "dst_wire": "BYP_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.045", + "0.055", + "0.148", + "0.179" + ], + "in_cap": "0.000", + "res": "3489.880625" + }, "src_wire": "BYP_ALT0" }, "INT_L.BYP_ALT1->>BYP_BOUNCE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.049", + "0.059", + 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"WR1BEG_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.043", + "0.103", + "0.124" + ], + "in_cap": "8.429", + "res": "1162.20225" + }, "src_wire": "WW4END3" }, "INT_L.WW4END3->>WW2BEG2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.052", + "0.063", + "0.118", + "0.142" + ], + "in_cap": "8.473", + "res": "1185.1186875" + }, "dst_wire": "WW2BEG2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.052", + "0.063", + "0.118", + "0.142" + ], + "in_cap": "8.473", + "res": "1185.1186875" + }, "src_wire": "WW4END3" }, "INT_L.WW4END3->>WW4BEG3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.059", + "0.072", + "0.138", + "0.167" + ], + "in_cap": "9.404", + "res": "1237.5" + }, "dst_wire": "WW4BEG3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.059", + "0.072", + "0.138", + "0.167" + ], + "in_cap": "9.404", + "res": "1237.5" + }, "src_wire": "WW4END3" }, "INT_L.WW4END_S0_0->>ER1BEG_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.036", + "0.044", + "0.103", + "0.124" + ], + "in_cap": "8.429", + "res": "1162.20225" + }, "dst_wire": "ER1BEG_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.036", + "0.044", + "0.103", + "0.124" + ], + "in_cap": "8.429", + "res": "1162.20225" + }, "src_wire": "WW4END_S0_0" }, "INT_L.WW4END_S0_0->>SR1BEG_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.046", + "0.056", + "0.109", + "0.132" + ], + "in_cap": "8.429", + "res": "1162.20225" + }, "dst_wire": "SR1BEG_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.046", + "0.056", + "0.109", + "0.132" + ], + "in_cap": "8.429", + "res": "1162.20225" + }, "src_wire": "WW4END_S0_0" }, "INT_L.WW4END_S0_0->>SS2BEG3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.049", + "0.059", + "0.108", + "0.131" + ], + "in_cap": "8.473", + "res": "1185.1186875" + }, "dst_wire": "SS2BEG3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.049", + "0.059", + "0.108", + "0.131" + ], + "in_cap": "8.473", + "res": "1185.1186875" + }, "src_wire": "WW4END_S0_0" }, "INT_L.WW4END_S0_0->>SS6BEG3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.071", + "0.086", + "0.156", + "0.189" + ], + "in_cap": "9.979", + "res": "1584.5231875" + }, "dst_wire": "SS6BEG3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.071", + "0.086", + "0.156", + "0.189" + ], + "in_cap": "9.979", + "res": "1584.5231875" + }, "src_wire": "WW4END_S0_0" }, "INT_L.WW4END_S0_0->>SW2BEG3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.041", + "0.113", + "0.137" + ], + "in_cap": "8.473", + "res": "1185.1186875" + }, "dst_wire": "SW2BEG3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.041", + "0.113", + "0.137" + ], + "in_cap": "8.473", + "res": "1185.1186875" + }, "src_wire": "WW4END_S0_0" }, "INT_L.WW4END_S0_0->>SW6BEG3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.065", + "0.079", + "0.149", + "0.180" + ], + "in_cap": "9.979", + "res": "1584.5231875" + }, "dst_wire": "SW6BEG3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.065", + "0.079", + "0.149", + "0.180" + ], + "in_cap": "9.979", + "res": "1584.5231875" + }, "src_wire": "WW4END_S0_0" }, "INT_L.WW4END_S0_0->>WL1BEG2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.034", + "0.042", + "0.103", + "0.124" + ], + "in_cap": "8.429", + "res": "1162.20225" + }, "dst_wire": "WL1BEG2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.034", + "0.042", + "0.103", + "0.124" + ], + "in_cap": "8.429", + "res": "1162.20225" + }, "src_wire": "WW4END_S0_0" }, "INT_L.WW4END_S0_0->>WW2BEG3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.052", + "0.063", + "0.118", + "0.142" + ], + "in_cap": "8.473", + "res": "1185.1186875" + }, "dst_wire": "WW2BEG3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.052", + "0.063", + "0.118", + "0.142" + ], + "in_cap": "8.473", + "res": "1185.1186875" + }, "src_wire": "WW4END_S0_0" } }, @@ -26165,8 +104642,26 @@ "name": "X0Y0", "prefix": "TIEOFF", "site_pins": { - "HARD0": "GND_WIRE", - "HARD1": "VCC_WIRE" + "HARD0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GND_WIRE" + }, + "HARD1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "VCC_WIRE" + } }, "type": "TIEOFF", "x_coord": 0, @@ -26174,606 +104669,702 @@ } ], "tile_type": "INT_L", - "wires": [ - "BYP_ALT0", - "BYP_ALT1", - "BYP_ALT2", - "BYP_ALT3", - "BYP_ALT4", - "BYP_ALT5", - "BYP_ALT6", - "BYP_ALT7", - "BYP_BOUNCE0", - "BYP_BOUNCE1", - "BYP_BOUNCE2", - "BYP_BOUNCE3", - "BYP_BOUNCE4", - "BYP_BOUNCE5", - "BYP_BOUNCE6", - "BYP_BOUNCE7", - "BYP_BOUNCE_N3_2", - "BYP_BOUNCE_N3_3", - "BYP_BOUNCE_N3_6", - "BYP_BOUNCE_N3_7", - "BYP_L0", - "BYP_L1", - "BYP_L2", - "BYP_L3", - "BYP_L4", - "BYP_L5", - "BYP_L6", - "BYP_L7", - "CLK_L0", - "CLK_L1", - "CTRL_L0", - "CTRL_L1", - "EE2A0", - "EE2A1", - "EE2A2", - "EE2A3", - "EE2BEG0", - "EE2BEG1", - "EE2BEG2", - "EE2BEG3", - "EE2END0", - "EE2END1", - "EE2END2", - "EE2END3", - "EE4A0", - "EE4A1", - "EE4A2", - "EE4A3", - "EE4B0", - "EE4B1", - "EE4B2", - "EE4B3", - "EE4BEG0", - "EE4BEG1", - "EE4BEG2", - "EE4BEG3", - "EE4C0", - "EE4C1", - "EE4C2", - "EE4C3", - "EE4END0", - "EE4END1", - "EE4END2", - "EE4END3", - "EL1BEG0", - "EL1BEG1", - "EL1BEG2", - "EL1BEG3", - "EL1BEG_N3", - "EL1END0", - "EL1END1", - "EL1END2", - "EL1END3", - "EL1END_S3_0", - "ER1BEG0", - "ER1BEG1", - "ER1BEG2", - "ER1BEG3", - "ER1BEG_S0", - "ER1END0", - "ER1END1", - "ER1END2", - "ER1END3", - "ER1END_N3_3", - "FAN_ALT0", - "FAN_ALT1", - "FAN_ALT2", - "FAN_ALT3", - "FAN_ALT4", - "FAN_ALT5", - "FAN_ALT6", - "FAN_ALT7", - "FAN_BOUNCE0", - "FAN_BOUNCE1", - "FAN_BOUNCE2", - "FAN_BOUNCE3", - "FAN_BOUNCE4", - "FAN_BOUNCE5", - "FAN_BOUNCE6", - "FAN_BOUNCE7", - "FAN_BOUNCE_S3_0", - "FAN_BOUNCE_S3_2", - "FAN_BOUNCE_S3_4", - "FAN_BOUNCE_S3_6", - "FAN_L0", - "FAN_L1", - "FAN_L2", - "FAN_L3", - "FAN_L4", - "FAN_L5", - "FAN_L6", - "FAN_L7", - "GCLK_L_B0", - "GCLK_L_B1", - "GCLK_L_B10", - "GCLK_L_B10_EAST", - "GCLK_L_B10_WEST", - "GCLK_L_B11", - "GCLK_L_B11_EAST", - "GCLK_L_B11_WEST", - "GCLK_L_B2", - "GCLK_L_B3", - "GCLK_L_B4", - "GCLK_L_B5", - "GCLK_L_B6", - "GCLK_L_B6_EAST", - "GCLK_L_B6_WEST", - "GCLK_L_B7", - "GCLK_L_B7_EAST", - "GCLK_L_B7_WEST", - "GCLK_L_B8", - "GCLK_L_B8_EAST", - "GCLK_L_B8_WEST", - "GCLK_L_B9", - "GCLK_L_B9_EAST", - "GCLK_L_B9_WEST", - "GFAN0", - "GFAN1", - "GND_WIRE", - "IMUX_L0", - "IMUX_L1", - "IMUX_L10", - "IMUX_L11", - "IMUX_L12", - "IMUX_L13", - "IMUX_L14", - "IMUX_L15", - "IMUX_L16", - "IMUX_L17", - "IMUX_L18", - "IMUX_L19", - "IMUX_L2", - "IMUX_L20", - "IMUX_L21", - "IMUX_L22", - "IMUX_L23", - "IMUX_L24", - "IMUX_L25", - "IMUX_L26", - "IMUX_L27", - "IMUX_L28", - "IMUX_L29", - "IMUX_L3", - "IMUX_L30", - "IMUX_L31", - "IMUX_L32", - "IMUX_L33", - "IMUX_L34", - "IMUX_L35", - "IMUX_L36", - "IMUX_L37", - "IMUX_L38", - "IMUX_L39", - "IMUX_L4", - "IMUX_L40", - "IMUX_L41", - "IMUX_L42", - "IMUX_L43", - "IMUX_L44", - "IMUX_L45", - "IMUX_L46", - "IMUX_L47", - "IMUX_L5", - "IMUX_L6", - "IMUX_L7", - "IMUX_L8", - "IMUX_L9", - "INT_DQS_IOTOPHASER", - "INT_PHASER_TO_IO_ICLK", - "INT_PHASER_TO_IO_ICLKDIV", - "INT_PHASER_TO_IO_OCLK", - "INT_PHASER_TO_IO_OCLK1X_90", - "INT_PHASER_TO_IO_OCLKDIV", - "LH0", - "LH1", - "LH10", - "LH11", - "LH12", - "LH2", - "LH3", - "LH4", - "LH5", - "LH6", - "LH7", - "LH8", - "LH9", - "LOGIC_OUTS_L0", - "LOGIC_OUTS_L1", - "LOGIC_OUTS_L10", - "LOGIC_OUTS_L11", - "LOGIC_OUTS_L12", - "LOGIC_OUTS_L13", - "LOGIC_OUTS_L14", - "LOGIC_OUTS_L15", - "LOGIC_OUTS_L16", - "LOGIC_OUTS_L17", - "LOGIC_OUTS_L18", - "LOGIC_OUTS_L19", - "LOGIC_OUTS_L2", - "LOGIC_OUTS_L20", - "LOGIC_OUTS_L21", - "LOGIC_OUTS_L22", - "LOGIC_OUTS_L23", - "LOGIC_OUTS_L3", - "LOGIC_OUTS_L4", - "LOGIC_OUTS_L5", - "LOGIC_OUTS_L6", - "LOGIC_OUTS_L7", - "LOGIC_OUTS_L8", - "LOGIC_OUTS_L9", - "LVB_L0", - "LVB_L1", - "LVB_L10", - "LVB_L11", - "LVB_L12", - "LVB_L2", - "LVB_L3", - "LVB_L4", - "LVB_L5", - "LVB_L6", - "LVB_L7", - "LVB_L8", - "LVB_L9", - "LV_L0", - "LV_L1", - "LV_L10", - "LV_L11", - "LV_L12", - "LV_L13", - "LV_L14", - "LV_L15", - "LV_L16", - "LV_L17", - "LV_L18", - "LV_L2", - "LV_L3", - "LV_L4", - "LV_L5", - "LV_L6", - "LV_L7", - "LV_L8", - "LV_L9", - "MONITOR_N", - "MONITOR_P", - "NE2A0", - "NE2A1", - "NE2A2", - "NE2A3", - "NE2BEG0", - "NE2BEG1", - "NE2BEG2", - "NE2BEG3", - "NE2END0", - "NE2END1", - "NE2END2", - "NE2END3", - "NE2END_S3_0", - "NE6A0", - "NE6A1", - "NE6A2", - "NE6A3", - "NE6B0", - "NE6B1", - "NE6B2", - "NE6B3", - "NE6BEG0", - "NE6BEG1", - "NE6BEG2", - "NE6BEG3", - "NE6C0", - "NE6C1", - "NE6C2", - "NE6C3", - "NE6D0", - "NE6D1", - "NE6D2", - "NE6D3", - "NE6E0", - "NE6E1", - "NE6E2", - "NE6E3", - "NE6END0", - "NE6END1", - "NE6END2", - "NE6END3", - "NL1BEG0", - "NL1BEG1", - "NL1BEG2", - "NL1BEG_N3", - "NL1END0", - "NL1END1", - "NL1END2", - "NL1END_S3_0", - "NN2A0", - "NN2A1", - "NN2A2", - "NN2A3", - "NN2BEG0", - "NN2BEG1", - "NN2BEG2", - "NN2BEG3", - "NN2END0", - "NN2END1", - "NN2END2", - "NN2END3", - "NN2END_S2_0", - "NN6A0", - "NN6A1", - "NN6A2", - "NN6A3", - "NN6B0", - "NN6B1", - "NN6B2", - "NN6B3", - "NN6BEG0", - "NN6BEG1", - "NN6BEG2", - "NN6BEG3", - "NN6C0", - "NN6C1", - "NN6C2", - "NN6C3", - "NN6D0", - "NN6D1", - "NN6D2", - "NN6D3", - "NN6E0", - "NN6E1", - "NN6E2", - "NN6E3", - "NN6END0", - "NN6END1", - "NN6END2", - "NN6END3", - "NN6END_S1_0", - "NR1BEG0", - "NR1BEG1", - "NR1BEG2", - "NR1BEG3", - "NR1END0", - "NR1END1", - "NR1END2", - "NR1END3", - "NW2A0", - "NW2A1", - "NW2A2", - "NW2A3", - "NW2BEG0", - "NW2BEG1", - "NW2BEG2", - "NW2BEG3", - "NW2END0", - "NW2END1", - "NW2END2", - "NW2END3", - "NW2END_S0_0", - "NW6A0", - "NW6A1", - "NW6A2", - "NW6A3", - "NW6B0", - "NW6B1", - "NW6B2", - "NW6B3", - "NW6BEG0", - "NW6BEG1", - "NW6BEG2", - "NW6BEG3", - "NW6C0", - "NW6C1", - "NW6C2", - "NW6C3", - "NW6D0", - "NW6D1", - "NW6D2", - "NW6D3", - "NW6E0", - "NW6E1", - "NW6E2", - "NW6E3", - "NW6END0", - "NW6END1", - "NW6END2", - "NW6END3", - "NW6END_S0_0", - "SE2A0", - "SE2A1", - "SE2A2", - "SE2A3", - "SE2BEG0", - "SE2BEG1", - "SE2BEG2", - "SE2BEG3", - "SE2END0", - "SE2END1", - "SE2END2", - "SE2END3", - "SE6A0", - "SE6A1", - "SE6A2", - "SE6A3", - "SE6B0", - "SE6B1", - "SE6B2", - "SE6B3", - "SE6BEG0", - "SE6BEG1", - "SE6BEG2", - "SE6BEG3", - "SE6C0", - "SE6C1", - "SE6C2", - "SE6C3", - "SE6D0", - "SE6D1", - "SE6D2", - "SE6D3", - "SE6E0", - "SE6E1", - "SE6E2", - "SE6E3", - "SE6END0", - "SE6END1", - "SE6END2", - "SE6END3", - "SL1BEG0", - "SL1BEG1", - "SL1BEG2", - "SL1BEG3", - "SL1END0", - "SL1END1", - "SL1END2", - "SL1END3", - "SR1BEG1", - "SR1BEG2", - "SR1BEG3", - "SR1BEG_S0", - "SR1END1", - "SR1END2", - "SR1END3", - "SR1END_N3_3", - "SS2A0", - "SS2A1", - "SS2A2", - "SS2A3", - "SS2BEG0", - "SS2BEG1", - "SS2BEG2", - "SS2BEG3", - "SS2END0", - "SS2END1", - "SS2END2", - "SS2END3", - "SS2END_N0_3", - "SS6A0", - "SS6A1", - "SS6A2", - "SS6A3", - "SS6B0", - "SS6B1", - "SS6B2", - "SS6B3", - "SS6BEG0", - "SS6BEG1", - "SS6BEG2", - "SS6BEG3", - "SS6C0", - "SS6C1", - "SS6C2", - "SS6C3", - "SS6D0", - "SS6D1", - "SS6D2", - "SS6D3", - "SS6E0", - "SS6E1", - "SS6E2", - "SS6E3", - "SS6END0", - "SS6END1", - "SS6END2", - "SS6END3", - "SS6END_N0_3", - "SW2A0", - "SW2A1", - "SW2A2", - "SW2A3", - "SW2BEG0", - "SW2BEG1", - "SW2BEG2", - "SW2BEG3", - "SW2END0", - "SW2END1", - "SW2END2", - "SW2END3", - "SW2END_N0_3", - "SW6A0", - "SW6A1", - "SW6A2", - "SW6A3", - "SW6B0", - "SW6B1", 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"delay": [ + "0.052", + "0.063", + "0.118", + "0.142" + ], + "in_cap": "8.473", + "res": "1185.1186875" + }, "dst_wire": "WW2BEG3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.052", + "0.063", + "0.118", + "0.142" + ], + "in_cap": "8.473", + "res": "1185.1186875" + }, "src_wire": "WW4END_S0_0" } }, @@ -26165,8 +104642,26 @@ "name": "X0Y0", "prefix": "TIEOFF", "site_pins": { - "HARD0": "GND_WIRE", - "HARD1": "VCC_WIRE" + "HARD0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GND_WIRE" + }, + "HARD1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "VCC_WIRE" + } }, "type": "TIEOFF", "x_coord": 0, @@ -26174,606 +104669,702 @@ } ], "tile_type": "INT_R", - "wires": [ - "BYP0", - "BYP1", - "BYP2", - "BYP3", - "BYP4", - "BYP5", - "BYP6", - "BYP7", - "BYP_ALT0", - "BYP_ALT1", - "BYP_ALT2", - "BYP_ALT3", - "BYP_ALT4", - "BYP_ALT5", - "BYP_ALT6", - "BYP_ALT7", - "BYP_BOUNCE0", - "BYP_BOUNCE1", - "BYP_BOUNCE2", - "BYP_BOUNCE3", - "BYP_BOUNCE4", - "BYP_BOUNCE5", - "BYP_BOUNCE6", - "BYP_BOUNCE7", - "BYP_BOUNCE_N3_2", - "BYP_BOUNCE_N3_3", - "BYP_BOUNCE_N3_6", - "BYP_BOUNCE_N3_7", - "CLK0", - "CLK1", - "CTRL0", - "CTRL1", - "EE2A0", - "EE2A1", - "EE2A2", - "EE2A3", - "EE2BEG0", - "EE2BEG1", - "EE2BEG2", - "EE2BEG3", - "EE2END0", - "EE2END1", - "EE2END2", - "EE2END3", - "EE4A0", - "EE4A1", - "EE4A2", - "EE4A3", - "EE4B0", - "EE4B1", - "EE4B2", - "EE4B3", - "EE4BEG0", - "EE4BEG1", - "EE4BEG2", - "EE4BEG3", - "EE4C0", - "EE4C1", - "EE4C2", - "EE4C3", - "EE4END0", - "EE4END1", - "EE4END2", - "EE4END3", - "EL1BEG0", - "EL1BEG1", - "EL1BEG2", - "EL1BEG3", - "EL1BEG_N3", - "EL1END0", - "EL1END1", - "EL1END2", - "EL1END3", - "EL1END_S3_0", - "ER1BEG0", - "ER1BEG1", - "ER1BEG2", - "ER1BEG3", - "ER1BEG_S0", - "ER1END0", - "ER1END1", - "ER1END2", - "ER1END3", - "ER1END_N3_3", - "FAN0", - "FAN1", - "FAN2", - "FAN3", - "FAN4", - "FAN5", - "FAN6", - "FAN7", - "FAN_ALT0", - "FAN_ALT1", - "FAN_ALT2", - "FAN_ALT3", - "FAN_ALT4", - "FAN_ALT5", - "FAN_ALT6", - "FAN_ALT7", - "FAN_BOUNCE0", - "FAN_BOUNCE1", - "FAN_BOUNCE2", - "FAN_BOUNCE3", - "FAN_BOUNCE4", - "FAN_BOUNCE5", - "FAN_BOUNCE6", - "FAN_BOUNCE7", - "FAN_BOUNCE_S3_0", - "FAN_BOUNCE_S3_2", - "FAN_BOUNCE_S3_4", - "FAN_BOUNCE_S3_6", - "GCLK_B0", - "GCLK_B0_EAST", - "GCLK_B0_WEST", - "GCLK_B1", - "GCLK_B10", - "GCLK_B11", - "GCLK_B1_EAST", - "GCLK_B1_WEST", - "GCLK_B2", - "GCLK_B2_EAST", - "GCLK_B2_WEST", - "GCLK_B3", - "GCLK_B3_EAST", - "GCLK_B3_WEST", - "GCLK_B4", - "GCLK_B4_EAST", - "GCLK_B4_WEST", - "GCLK_B5", - "GCLK_B5_EAST", - "GCLK_B5_WEST", - "GCLK_B6", - "GCLK_B7", - "GCLK_B8", - "GCLK_B9", - "GFAN0", - "GFAN1", - "GND_WIRE", - "IMUX0", - "IMUX1", - "IMUX10", - "IMUX11", - "IMUX12", - "IMUX13", - "IMUX14", - "IMUX15", - "IMUX16", - "IMUX17", - "IMUX18", - "IMUX19", - "IMUX2", - "IMUX20", - "IMUX21", - "IMUX22", - "IMUX23", - "IMUX24", - "IMUX25", - "IMUX26", - "IMUX27", - "IMUX28", - "IMUX29", - "IMUX3", - "IMUX30", - "IMUX31", - "IMUX32", - "IMUX33", - "IMUX34", - "IMUX35", - "IMUX36", - "IMUX37", - "IMUX38", - "IMUX39", - "IMUX4", - "IMUX40", - "IMUX41", - "IMUX42", - "IMUX43", - "IMUX44", - "IMUX45", - "IMUX46", - "IMUX47", - "IMUX5", - "IMUX6", - "IMUX7", - "IMUX8", - "IMUX9", - "INT_DQS_IOTOPHASER", - "INT_PHASER_TO_IO_ICLK", - "INT_PHASER_TO_IO_ICLKDIV", - "INT_PHASER_TO_IO_OCLK", - "INT_PHASER_TO_IO_OCLK1X_90", - "INT_PHASER_TO_IO_OCLKDIV", - "LH0", - "LH1", - "LH10", - "LH11", - "LH12", - "LH2", - "LH3", - "LH4", - "LH5", - "LH6", - "LH7", - "LH8", - "LH9", - "LOGIC_OUTS0", - "LOGIC_OUTS1", - "LOGIC_OUTS10", - "LOGIC_OUTS11", - "LOGIC_OUTS12", - "LOGIC_OUTS13", - "LOGIC_OUTS14", - "LOGIC_OUTS15", - "LOGIC_OUTS16", - "LOGIC_OUTS17", - "LOGIC_OUTS18", - "LOGIC_OUTS19", - "LOGIC_OUTS2", - "LOGIC_OUTS20", - "LOGIC_OUTS21", - "LOGIC_OUTS22", - "LOGIC_OUTS23", - "LOGIC_OUTS3", - "LOGIC_OUTS4", - "LOGIC_OUTS5", - "LOGIC_OUTS6", - "LOGIC_OUTS7", - "LOGIC_OUTS8", - "LOGIC_OUTS9", - "LV0", - "LV1", - "LV10", - "LV11", - "LV12", - "LV13", - "LV14", - "LV15", - "LV16", - "LV17", - "LV18", - "LV2", - "LV3", - "LV4", - "LV5", - "LV6", - "LV7", - "LV8", - "LV9", - "LVB0", - "LVB1", - "LVB10", - "LVB11", - "LVB12", - "LVB2", - "LVB3", - "LVB4", - "LVB5", - "LVB6", - "LVB7", - "LVB8", - "LVB9", - "MONITOR_N", - "MONITOR_P", - "NE2A0", - "NE2A1", - "NE2A2", - "NE2A3", - "NE2BEG0", - "NE2BEG1", - "NE2BEG2", - "NE2BEG3", - "NE2END0", - "NE2END1", - "NE2END2", - "NE2END3", - "NE2END_S3_0", - "NE6A0", - "NE6A1", - "NE6A2", - "NE6A3", - "NE6B0", - "NE6B1", - "NE6B2", - "NE6B3", - "NE6BEG0", - "NE6BEG1", - "NE6BEG2", - "NE6BEG3", - "NE6C0", - "NE6C1", - "NE6C2", - "NE6C3", - "NE6D0", - "NE6D1", - "NE6D2", - "NE6D3", - "NE6E0", - "NE6E1", - "NE6E2", - "NE6E3", - "NE6END0", - "NE6END1", - "NE6END2", - "NE6END3", - "NL1BEG0", - "NL1BEG1", - "NL1BEG2", - "NL1BEG_N3", - "NL1END0", - "NL1END1", - "NL1END2", - "NL1END_S3_0", - "NN2A0", - "NN2A1", - "NN2A2", - "NN2A3", - "NN2BEG0", - "NN2BEG1", - "NN2BEG2", - "NN2BEG3", - "NN2END0", - "NN2END1", - "NN2END2", - "NN2END3", - "NN2END_S2_0", - "NN6A0", - "NN6A1", - "NN6A2", - "NN6A3", - "NN6B0", - "NN6B1", - "NN6B2", - "NN6B3", - "NN6BEG0", - "NN6BEG1", - "NN6BEG2", - "NN6BEG3", - "NN6C0", - "NN6C1", - "NN6C2", - "NN6C3", - "NN6D0", - "NN6D1", - "NN6D2", - "NN6D3", - "NN6E0", - "NN6E1", - "NN6E2", - "NN6E3", - "NN6END0", - "NN6END1", - "NN6END2", - "NN6END3", - "NN6END_S1_0", - "NR1BEG0", - "NR1BEG1", - "NR1BEG2", - "NR1BEG3", - "NR1END0", - "NR1END1", - "NR1END2", - "NR1END3", - "NW2A0", - "NW2A1", - "NW2A2", - "NW2A3", - "NW2BEG0", - "NW2BEG1", - "NW2BEG2", - "NW2BEG3", - "NW2END0", - "NW2END1", - "NW2END2", - "NW2END3", - "NW2END_S0_0", - "NW6A0", - "NW6A1", - "NW6A2", - "NW6A3", - "NW6B0", - "NW6B1", - "NW6B2", - "NW6B3", - "NW6BEG0", - "NW6BEG1", - "NW6BEG2", - "NW6BEG3", - "NW6C0", - "NW6C1", - "NW6C2", - "NW6C3", - "NW6D0", - "NW6D1", - "NW6D2", - "NW6D3", - "NW6E0", - "NW6E1", - "NW6E2", - "NW6E3", - "NW6END0", - "NW6END1", - "NW6END2", - "NW6END3", - "NW6END_S0_0", - "SE2A0", - "SE2A1", - "SE2A2", - "SE2A3", - "SE2BEG0", - "SE2BEG1", - "SE2BEG2", - "SE2BEG3", - "SE2END0", - "SE2END1", - "SE2END2", - "SE2END3", - "SE6A0", - "SE6A1", - "SE6A2", - "SE6A3", - "SE6B0", - "SE6B1", - "SE6B2", - "SE6B3", - "SE6BEG0", - "SE6BEG1", - "SE6BEG2", - "SE6BEG3", - "SE6C0", - "SE6C1", - "SE6C2", - "SE6C3", - "SE6D0", - "SE6D1", - "SE6D2", - "SE6D3", - "SE6E0", - "SE6E1", - "SE6E2", - "SE6E3", - "SE6END0", - "SE6END1", - "SE6END2", - "SE6END3", - "SL1BEG0", - "SL1BEG1", - "SL1BEG2", - "SL1BEG3", - "SL1END0", - "SL1END1", - "SL1END2", - "SL1END3", - "SR1BEG1", - "SR1BEG2", - "SR1BEG3", - "SR1BEG_S0", - "SR1END1", - "SR1END2", - "SR1END3", - "SR1END_N3_3", - "SS2A0", - "SS2A1", - "SS2A2", - "SS2A3", - "SS2BEG0", - "SS2BEG1", - "SS2BEG2", - "SS2BEG3", - "SS2END0", - "SS2END1", - "SS2END2", - "SS2END3", - "SS2END_N0_3", - "SS6A0", - "SS6A1", - "SS6A2", - "SS6A3", - "SS6B0", - "SS6B1", - "SS6B2", - "SS6B3", - "SS6BEG0", - "SS6BEG1", - "SS6BEG2", - "SS6BEG3", - "SS6C0", - "SS6C1", - "SS6C2", - "SS6C3", - "SS6D0", - "SS6D1", - "SS6D2", - "SS6D3", - "SS6E0", - "SS6E1", - "SS6E2", - "SS6E3", - "SS6END0", - "SS6END1", - "SS6END2", - "SS6END3", - "SS6END_N0_3", - "SW2A0", - "SW2A1", - "SW2A2", - "SW2A3", - "SW2BEG0", - "SW2BEG1", - "SW2BEG2", - "SW2BEG3", - "SW2END0", - "SW2END1", - "SW2END2", - "SW2END3", - "SW2END_N0_3", - "SW6A0", - "SW6A1", - "SW6A2", - "SW6A3", - "SW6B0", - "SW6B1", - "SW6B2", - "SW6B3", - "SW6BEG0", - "SW6BEG1", - "SW6BEG2", - "SW6BEG3", - "SW6C0", - "SW6C1", - "SW6C2", - "SW6C3", - "SW6D0", - "SW6D1", - "SW6D2", - "SW6D3", - "SW6E0", - "SW6E1", - "SW6E2", - "SW6E3", - "SW6END0", - "SW6END1", - "SW6END2", - "SW6END3", - "SW6END_N0_3", - "VCC_WIRE", - "WL1BEG0", - "WL1BEG1", - "WL1BEG2", - "WL1BEG3", - "WL1BEG_N3", - "WL1END0", - "WL1END1", - "WL1END2", - "WL1END3", - "WL1END_N1_3", - "WR1BEG0", - "WR1BEG1", - "WR1BEG2", - "WR1BEG3", - "WR1BEG_S0", - "WR1END0", - "WR1END1", - "WR1END2", - "WR1END3", - "WR1END_S1_0", - "WW2A0", - "WW2A1", - "WW2A2", - "WW2A3", - "WW2BEG0", - "WW2BEG1", - "WW2BEG2", - "WW2BEG3", - "WW2END0", - "WW2END1", - "WW2END2", - "WW2END3", - "WW2END_N0_3", - "WW4A0", - "WW4A1", - "WW4A2", - "WW4A3", - "WW4B0", - "WW4B1", - "WW4B2", - "WW4B3", - "WW4BEG0", - "WW4BEG1", - "WW4BEG2", - "WW4BEG3", - "WW4C0", - "WW4C1", - "WW4C2", - "WW4C3", - "WW4END0", - "WW4END1", - "WW4END2", - "WW4END3", - "WW4END_S0_0" - ] + "wires": { + "BYP0": null, + "BYP1": null, + "BYP2": null, + "BYP3": null, + "BYP4": null, + "BYP5": null, + "BYP6": null, + "BYP7": null, + "BYP_ALT0": null, + "BYP_ALT1": null, + "BYP_ALT2": null, + "BYP_ALT3": null, + "BYP_ALT4": null, + "BYP_ALT5": null, + "BYP_ALT6": null, + "BYP_ALT7": null, + "BYP_BOUNCE0": null, + "BYP_BOUNCE1": null, + "BYP_BOUNCE2": null, + "BYP_BOUNCE3": null, + "BYP_BOUNCE4": null, + "BYP_BOUNCE5": null, + "BYP_BOUNCE6": null, + "BYP_BOUNCE7": null, + "BYP_BOUNCE_N3_2": null, + "BYP_BOUNCE_N3_3": null, + "BYP_BOUNCE_N3_6": null, + "BYP_BOUNCE_N3_7": null, + "CLK0": null, + "CLK1": null, + "CTRL0": null, + "CTRL1": null, + "EE2A0": null, + "EE2A1": null, + "EE2A2": null, + "EE2A3": null, + "EE2BEG0": null, + "EE2BEG1": null, + "EE2BEG2": null, + "EE2BEG3": null, + "EE2END0": null, + "EE2END1": null, + "EE2END2": null, + "EE2END3": null, + "EE4A0": null, + "EE4A1": null, + "EE4A2": null, + "EE4A3": null, + "EE4B0": null, + "EE4B1": null, + "EE4B2": null, + "EE4B3": null, + "EE4BEG0": null, + "EE4BEG1": null, + "EE4BEG2": null, + "EE4BEG3": null, + "EE4C0": null, + "EE4C1": null, + "EE4C2": null, + "EE4C3": null, + "EE4END0": null, + "EE4END1": null, + "EE4END2": null, + "EE4END3": null, + "EL1BEG0": null, + "EL1BEG1": null, + "EL1BEG2": null, + "EL1BEG3": null, + "EL1BEG_N3": null, + "EL1END0": null, + "EL1END1": null, + "EL1END2": null, + "EL1END3": null, + "EL1END_S3_0": null, + "ER1BEG0": null, + "ER1BEG1": null, + "ER1BEG2": null, + "ER1BEG3": null, + "ER1BEG_S0": null, + "ER1END0": null, + "ER1END1": null, + "ER1END2": null, + "ER1END3": null, + "ER1END_N3_3": null, + "FAN0": null, + "FAN1": null, + "FAN2": null, + "FAN3": null, + "FAN4": null, + "FAN5": null, + "FAN6": null, + "FAN7": null, + "FAN_ALT0": null, + "FAN_ALT1": null, + "FAN_ALT2": null, + "FAN_ALT3": null, + "FAN_ALT4": null, + "FAN_ALT5": null, + "FAN_ALT6": null, + "FAN_ALT7": null, + "FAN_BOUNCE0": null, + "FAN_BOUNCE1": null, + "FAN_BOUNCE2": null, + "FAN_BOUNCE3": null, + "FAN_BOUNCE4": null, + "FAN_BOUNCE5": null, + "FAN_BOUNCE6": null, + "FAN_BOUNCE7": null, + "FAN_BOUNCE_S3_0": null, + "FAN_BOUNCE_S3_2": null, + "FAN_BOUNCE_S3_4": null, + "FAN_BOUNCE_S3_6": null, + "GCLK_B0": null, + "GCLK_B0_EAST": null, + "GCLK_B0_WEST": null, + "GCLK_B1": null, + "GCLK_B10": null, + "GCLK_B11": null, + "GCLK_B1_EAST": null, + "GCLK_B1_WEST": null, + "GCLK_B2": null, + "GCLK_B2_EAST": null, + "GCLK_B2_WEST": null, + "GCLK_B3": null, + "GCLK_B3_EAST": null, + "GCLK_B3_WEST": null, + "GCLK_B4": null, + "GCLK_B4_EAST": null, + "GCLK_B4_WEST": null, + "GCLK_B5": null, + "GCLK_B5_EAST": null, + "GCLK_B5_WEST": null, + "GCLK_B6": null, + "GCLK_B7": null, + "GCLK_B8": null, + "GCLK_B9": null, + "GFAN0": null, + "GFAN1": null, + "GND_WIRE": null, + "IMUX0": null, + "IMUX1": null, + "IMUX10": null, + "IMUX11": null, + "IMUX12": null, + "IMUX13": null, + "IMUX14": null, + "IMUX15": null, + "IMUX16": null, + "IMUX17": null, + "IMUX18": null, + "IMUX19": null, + "IMUX2": null, + "IMUX20": null, + "IMUX21": null, + "IMUX22": null, + "IMUX23": null, + "IMUX24": null, + "IMUX25": null, + "IMUX26": null, + "IMUX27": null, + "IMUX28": null, + "IMUX29": null, + "IMUX3": null, + "IMUX30": null, + "IMUX31": null, + "IMUX32": null, + "IMUX33": null, + "IMUX34": null, + "IMUX35": null, + "IMUX36": null, + "IMUX37": null, + "IMUX38": null, + "IMUX39": null, + "IMUX4": null, + "IMUX40": null, + "IMUX41": null, + "IMUX42": null, + "IMUX43": null, + "IMUX44": null, + "IMUX45": null, + "IMUX46": null, + "IMUX47": null, + "IMUX5": null, + "IMUX6": null, + "IMUX7": null, + "IMUX8": null, + "IMUX9": null, + "INT_DQS_IOTOPHASER": null, + "INT_PHASER_TO_IO_ICLK": null, + "INT_PHASER_TO_IO_ICLKDIV": null, + "INT_PHASER_TO_IO_OCLK": null, + "INT_PHASER_TO_IO_OCLK1X_90": null, + "INT_PHASER_TO_IO_OCLKDIV": null, + "LH0": null, + "LH1": null, + "LH10": null, + "LH11": null, + "LH12": null, + "LH2": null, + "LH3": null, + "LH4": null, + "LH5": null, + "LH6": null, + "LH7": null, + "LH8": null, + "LH9": null, + "LOGIC_OUTS0": null, + "LOGIC_OUTS1": null, + "LOGIC_OUTS10": null, + "LOGIC_OUTS11": null, + "LOGIC_OUTS12": null, + "LOGIC_OUTS13": null, + "LOGIC_OUTS14": null, + "LOGIC_OUTS15": null, + "LOGIC_OUTS16": null, + "LOGIC_OUTS17": null, + "LOGIC_OUTS18": null, + "LOGIC_OUTS19": null, + "LOGIC_OUTS2": null, + "LOGIC_OUTS20": null, + "LOGIC_OUTS21": null, + "LOGIC_OUTS22": null, + "LOGIC_OUTS23": null, + "LOGIC_OUTS3": null, + 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"INT_INTERFACE_WW4C1": null, + "INT_INTERFACE_WW4C2": null, + "INT_INTERFACE_WW4C3": null, + "INT_INTERFACE_WW4END0": null, + "INT_INTERFACE_WW4END1": null, + "INT_INTERFACE_WW4END2": null, + "INT_INTERFACE_WW4END3": null, + "L_INT_INTER_DQS_IOTOPHASER": null + } } diff --git a/zynq7/tile_type_MONITOR_BOT_PELE1.json b/zynq7/tile_type_MONITOR_BOT_PELE1.json index fc90800..dad9275 100644 --- a/zynq7/tile_type_MONITOR_BOT_PELE1.json +++ b/zynq7/tile_type_MONITOR_BOT_PELE1.json @@ -2,779 +2,2000 @@ "pips": { "MONITOR_BOT_PELE1.MONITOR_ALM0->MONITOR_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM0" }, "MONITOR_BOT_PELE1.MONITOR_ALM1->MONITOR_LOGIC_OUTS_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM1" }, "MONITOR_BOT_PELE1.MONITOR_ALM2->MONITOR_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM2" }, "MONITOR_BOT_PELE1.MONITOR_ALM3->MONITOR_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM3" }, "MONITOR_BOT_PELE1.MONITOR_ALM4->MONITOR_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM4" }, "MONITOR_BOT_PELE1.MONITOR_ALM5->MONITOR_LOGIC_OUTS_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM5" }, "MONITOR_BOT_PELE1.MONITOR_ALM6->MONITOR_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM6" }, "MONITOR_BOT_PELE1.MONITOR_ALM7->MONITOR_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM7" }, "MONITOR_BOT_PELE1.MONITOR_BUSY->MONITOR_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_BUSY" }, "MONITOR_BOT_PELE1.MONITOR_CHANNEL0->MONITOR_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CHANNEL0" }, "MONITOR_BOT_PELE1.MONITOR_CHANNEL1->MONITOR_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CHANNEL1" }, "MONITOR_BOT_PELE1.MONITOR_CHANNEL2->MONITOR_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CHANNEL2" }, "MONITOR_BOT_PELE1.MONITOR_CHANNEL3->MONITOR_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CHANNEL3" }, "MONITOR_BOT_PELE1.MONITOR_CHANNEL4->MONITOR_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CHANNEL4" }, "MONITOR_BOT_PELE1.MONITOR_CLK1_0->MONITOR_DCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CLK1_0" }, "MONITOR_BOT_PELE1.MONITOR_CLK1_1->MONITOR_CONVSTCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_CONVSTCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CLK1_1" }, "MONITOR_BOT_PELE1.MONITOR_CTRL1_2->MONITOR_RESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_RESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CTRL1_2" }, "MONITOR_BOT_PELE1.MONITOR_DO0->MONITOR_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO0" }, "MONITOR_BOT_PELE1.MONITOR_DO1->MONITOR_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO1" }, "MONITOR_BOT_PELE1.MONITOR_DO10->MONITOR_LOGIC_OUTS_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO10" }, "MONITOR_BOT_PELE1.MONITOR_DO11->MONITOR_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO11" }, "MONITOR_BOT_PELE1.MONITOR_DO12->MONITOR_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO12" }, "MONITOR_BOT_PELE1.MONITOR_DO13->MONITOR_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO13" }, "MONITOR_BOT_PELE1.MONITOR_DO14->MONITOR_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO14" }, "MONITOR_BOT_PELE1.MONITOR_DO15->MONITOR_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO15" }, "MONITOR_BOT_PELE1.MONITOR_DO2->MONITOR_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO2" }, "MONITOR_BOT_PELE1.MONITOR_DO3->MONITOR_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO3" }, "MONITOR_BOT_PELE1.MONITOR_DO4->MONITOR_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO4" }, "MONITOR_BOT_PELE1.MONITOR_DO5->MONITOR_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO5" }, "MONITOR_BOT_PELE1.MONITOR_DO6->MONITOR_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO6" }, "MONITOR_BOT_PELE1.MONITOR_DO7->MONITOR_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO7" }, "MONITOR_BOT_PELE1.MONITOR_DO8->MONITOR_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO8" }, "MONITOR_BOT_PELE1.MONITOR_DO9->MONITOR_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO9" }, "MONITOR_BOT_PELE1.MONITOR_DRDY->MONITOR_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DRDY" }, "MONITOR_BOT_PELE1.MONITOR_EOC->MONITOR_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_EOC" }, "MONITOR_BOT_PELE1.MONITOR_EOS->MONITOR_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_EOS" }, "MONITOR_BOT_PELE1.MONITOR_HORIZ_VAUXN10_RIGHT->MONITOR_VERT_VAUXN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN10_RIGHT" }, "MONITOR_BOT_PELE1.MONITOR_HORIZ_VAUXN11_RIGHT->MONITOR_VERT_VAUXN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN11_RIGHT" }, "MONITOR_BOT_PELE1.MONITOR_HORIZ_VAUXN3_RIGHT->MONITOR_VERT_VAUXN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN3_RIGHT" }, "MONITOR_BOT_PELE1.MONITOR_HORIZ_VAUXP10_RIGHT->MONITOR_VERT_VAUXP10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP10_RIGHT" }, "MONITOR_BOT_PELE1.MONITOR_HORIZ_VAUXP11_RIGHT->MONITOR_VERT_VAUXP11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP11_RIGHT" }, "MONITOR_BOT_PELE1.MONITOR_HORIZ_VAUXP3_RIGHT->MONITOR_VERT_VAUXP3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP3_RIGHT" }, "MONITOR_BOT_PELE1.MONITOR_IMUX28_0->MONITOR_DI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX28_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX29_0->MONITOR_DI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX29_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX30_0->MONITOR_DI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX30_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX31_0->MONITOR_DI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX31_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX32_0->MONITOR_DI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX32_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX33_0->MONITOR_DI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX33_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX34_0->MONITOR_DI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX34_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX34_1->MONITOR_DADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX34_1" }, "MONITOR_BOT_PELE1.MONITOR_IMUX35_0->MONITOR_DI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX35_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX35_1->MONITOR_DADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX35_1" }, "MONITOR_BOT_PELE1.MONITOR_IMUX36_0->MONITOR_DI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX36_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX36_1->MONITOR_DADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX36_1" }, "MONITOR_BOT_PELE1.MONITOR_IMUX37_0->MONITOR_DI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX37_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX37_1->MONITOR_DADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX37_1" }, "MONITOR_BOT_PELE1.MONITOR_IMUX38_0->MONITOR_DI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX38_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX38_1->MONITOR_DADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX38_1" }, "MONITOR_BOT_PELE1.MONITOR_IMUX39_0->MONITOR_DI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX39_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX39_1->MONITOR_DADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX39_1" }, "MONITOR_BOT_PELE1.MONITOR_IMUX40_0->MONITOR_DI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX40_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX40_1->MONITOR_DADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX40_1" }, "MONITOR_BOT_PELE1.MONITOR_IMUX41_0->MONITOR_DI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX41_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX41_1->MONITOR_DEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX41_1" }, "MONITOR_BOT_PELE1.MONITOR_IMUX42_0->MONITOR_DI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX42_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX42_1->MONITOR_DWE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DWE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX42_1" }, "MONITOR_BOT_PELE1.MONITOR_IMUX43_0->MONITOR_DI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX43_0" }, "MONITOR_BOT_PELE1.MONITOR_IMUX43_1->MONITOR_CONVST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_CONVST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX43_1" }, "MONITOR_BOT_PELE1.MONITOR_JTAGBUSY->MONITOR_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_JTAGBUSY" }, "MONITOR_BOT_PELE1.MONITOR_JTAGLOCKED->MONITOR_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_JTAGLOCKED" }, "MONITOR_BOT_PELE1.MONITOR_JTAGMODIFIED->MONITOR_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_JTAGMODIFIED" }, "MONITOR_BOT_PELE1.MONITOR_MUXADDR0->MONITOR_LOGIC_OUTS_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_MUXADDR0" }, "MONITOR_BOT_PELE1.MONITOR_MUXADDR1->MONITOR_LOGIC_OUTS_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_MUXADDR1" }, "MONITOR_BOT_PELE1.MONITOR_MUXADDR2->MONITOR_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_MUXADDR2" }, "MONITOR_BOT_PELE1.MONITOR_MUXADDR3->MONITOR_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_MUXADDR3" }, "MONITOR_BOT_PELE1.MONITOR_MUXADDR4->MONITOR_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_MUXADDR4" }, "MONITOR_BOT_PELE1.MONITOR_OT->MONITOR_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_OT" }, "MONITOR_BOT_PELE1.MONITOR_SEG_VN->MONITOR_VN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_SEG_VN" }, "MONITOR_BOT_PELE1.MONITOR_SEG_VP->MONITOR_VP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_SEG_VP" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN0->MONITOR_VAUXN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN0" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN1->MONITOR_VAUXN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN1" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN10->MONITOR_VAUXN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN10" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN11->MONITOR_VAUXN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN11" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN12->MONITOR_VAUXN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN12" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN13->MONITOR_VAUXN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN13" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN14->MONITOR_VAUXN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN14" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN15->MONITOR_VAUXN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN15" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN2->MONITOR_VAUXN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN2" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN3->MONITOR_VAUXN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN3" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN4->MONITOR_VAUXN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN4" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN5->MONITOR_VAUXN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN5" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN6->MONITOR_VAUXN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN6" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN7->MONITOR_VAUXN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN7" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN8->MONITOR_VAUXN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN8" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXN9->MONITOR_VAUXN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN9" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP0->MONITOR_VAUXP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP0" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP1->MONITOR_VAUXP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP1" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP10->MONITOR_VAUXP10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP10" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP11->MONITOR_VAUXP11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP11" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP12->MONITOR_VAUXP12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP12" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP13->MONITOR_VAUXP13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP13" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP14->MONITOR_VAUXP14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP14" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP15->MONITOR_VAUXP15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP15" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP2->MONITOR_VAUXP2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP2" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP3->MONITOR_VAUXP3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP3" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP4->MONITOR_VAUXP4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP4" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP5->MONITOR_VAUXP5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP5" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP6->MONITOR_VAUXP6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP6" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP7->MONITOR_VAUXP7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP7" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP8->MONITOR_VAUXP8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP8" }, "MONITOR_BOT_PELE1.MONITOR_VERT_VAUXP9->MONITOR_VAUXP9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP9" } }, @@ -783,7 +2004,16 @@ "name": "X0Y1", "prefix": "IPAD", "site_pins": { - "O": "MONITOR_SEG_VN" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "MONITOR_SEG_VN" + } }, "type": "IPAD", "x_coord": 0, @@ -793,7 +2023,16 @@ "name": "X0Y0", "prefix": "IPAD", "site_pins": { - "O": "MONITOR_SEG_VP" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "MONITOR_SEG_VP" + } }, "type": "IPAD", "x_coord": 0, @@ -803,226 +2042,2206 @@ "name": "X0Y0", "prefix": "XADC", "site_pins": { - "ALM0": "MONITOR_ALM0", - "ALM1": "MONITOR_ALM1", - "ALM2": "MONITOR_ALM2", - "ALM3": "MONITOR_ALM3", - "ALM4": "MONITOR_ALM4", - "ALM5": "MONITOR_ALM5", - "ALM6": "MONITOR_ALM6", - "ALM7": "MONITOR_ALM7", - "BUSY": "MONITOR_BUSY", - "CHANNEL0": "MONITOR_CHANNEL0", - "CHANNEL1": "MONITOR_CHANNEL1", - "CHANNEL2": "MONITOR_CHANNEL2", - "CHANNEL3": "MONITOR_CHANNEL3", - "CHANNEL4": "MONITOR_CHANNEL4", - "CONVST": "MONITOR_CONVST", - "CONVSTCLK": "MONITOR_CONVSTCLK", - "DADDR0": "MONITOR_DADDR0", - "DADDR1": "MONITOR_DADDR1", - "DADDR2": "MONITOR_DADDR2", - "DADDR3": "MONITOR_DADDR3", - "DADDR4": "MONITOR_DADDR4", - "DADDR5": "MONITOR_DADDR5", - "DADDR6": "MONITOR_DADDR6", - "DCLK": "MONITOR_DCLK", - "DEN": "MONITOR_DEN", - "DI0": "MONITOR_DI0", - "DI1": "MONITOR_DI1", - "DI10": "MONITOR_DI10", - "DI11": "MONITOR_DI11", - "DI12": "MONITOR_DI12", - "DI13": "MONITOR_DI13", - "DI14": "MONITOR_DI14", - "DI15": "MONITOR_DI15", - "DI2": "MONITOR_DI2", - "DI3": "MONITOR_DI3", - "DI4": "MONITOR_DI4", - "DI5": "MONITOR_DI5", - "DI6": "MONITOR_DI6", - "DI7": "MONITOR_DI7", - "DI8": "MONITOR_DI8", - "DI9": "MONITOR_DI9", - "DO0": "MONITOR_DO0", - "DO1": "MONITOR_DO1", - "DO10": "MONITOR_DO10", - "DO11": "MONITOR_DO11", - "DO12": "MONITOR_DO12", - "DO13": "MONITOR_DO13", - "DO14": "MONITOR_DO14", - "DO15": "MONITOR_DO15", - "DO2": "MONITOR_DO2", - "DO3": "MONITOR_DO3", - "DO4": "MONITOR_DO4", - "DO5": "MONITOR_DO5", - "DO6": "MONITOR_DO6", - "DO7": "MONITOR_DO7", - "DO8": "MONITOR_DO8", - "DO9": "MONITOR_DO9", - "DRDY": "MONITOR_DRDY", - "DWE": "MONITOR_DWE", - "EOC": "MONITOR_EOC", - "EOS": "MONITOR_EOS", - "JTAGBUSY": "MONITOR_JTAGBUSY", - "JTAGLOCKED": "MONITOR_JTAGLOCKED", - "JTAGMODIFIED": "MONITOR_JTAGMODIFIED", - "MUXADDR0": "MONITOR_MUXADDR0", - "MUXADDR1": "MONITOR_MUXADDR1", - "MUXADDR2": "MONITOR_MUXADDR2", - "MUXADDR3": "MONITOR_MUXADDR3", - "MUXADDR4": "MONITOR_MUXADDR4", - "OT": "MONITOR_OT", - "RESET": "MONITOR_RESET", - "TESTADCCLK0": "MONITOR_TESTADCCLK0", - "TESTADCCLK1": "MONITOR_TESTADCCLK1", - "TESTADCCLK2": "MONITOR_TESTADCCLK2", - "TESTADCCLK3": "MONITOR_TESTADCCLK3", - "TESTADCIN0": "MONITOR_TESTADCIN0", - "TESTADCIN1": "MONITOR_TESTADCIN1", - "TESTADCIN10": "MONITOR_TESTADCIN10", - "TESTADCIN11": "MONITOR_TESTADCIN11", - "TESTADCIN12": "MONITOR_TESTADCIN12", - "TESTADCIN13": "MONITOR_TESTADCIN13", - "TESTADCIN14": "MONITOR_TESTADCIN14", - "TESTADCIN15": "MONITOR_TESTADCIN15", - "TESTADCIN16": "MONITOR_TESTADCIN16", - "TESTADCIN17": "MONITOR_TESTADCIN17", - "TESTADCIN18": "MONITOR_TESTADCIN18", - "TESTADCIN19": "MONITOR_TESTADCIN19", - "TESTADCIN2": "MONITOR_TESTADCIN2", - "TESTADCIN20": "MONITOR_TESTADCIN20", - "TESTADCIN21": "MONITOR_TESTADCIN21", - "TESTADCIN210": "MONITOR_TESTADCIN210", - "TESTADCIN211": "MONITOR_TESTADCIN211", - "TESTADCIN212": "MONITOR_TESTADCIN212", - "TESTADCIN213": "MONITOR_TESTADCIN213", - "TESTADCIN214": "MONITOR_TESTADCIN214", - "TESTADCIN215": "MONITOR_TESTADCIN215", - "TESTADCIN216": "MONITOR_TESTADCIN216", - "TESTADCIN217": "MONITOR_TESTADCIN217", - "TESTADCIN218": "MONITOR_TESTADCIN218", - "TESTADCIN219": "MONITOR_TESTADCIN219", - "TESTADCIN22": "MONITOR_TESTADCIN22", - "TESTADCIN23": "MONITOR_TESTADCIN23", - "TESTADCIN24": "MONITOR_TESTADCIN24", - "TESTADCIN25": "MONITOR_TESTADCIN25", - "TESTADCIN26": "MONITOR_TESTADCIN26", - "TESTADCIN27": "MONITOR_TESTADCIN27", - "TESTADCIN28": "MONITOR_TESTADCIN28", - "TESTADCIN29": "MONITOR_TESTADCIN29", - "TESTADCIN3": "MONITOR_TESTADCIN3", - "TESTADCIN4": "MONITOR_TESTADCIN4", - "TESTADCIN5": "MONITOR_TESTADCIN5", - "TESTADCIN6": "MONITOR_TESTADCIN6", - "TESTADCIN7": "MONITOR_TESTADCIN7", - "TESTADCIN8": "MONITOR_TESTADCIN8", - "TESTADCIN9": "MONITOR_TESTADCIN9", - "TESTADCOUT0": "MONITOR_TESTADCOUT0", - "TESTADCOUT1": "MONITOR_TESTADCOUT1", - "TESTADCOUT10": "MONITOR_TESTADCOUT10", - "TESTADCOUT11": "MONITOR_TESTADCOUT11", - "TESTADCOUT12": "MONITOR_TESTADCOUT12", - "TESTADCOUT13": "MONITOR_TESTADCOUT13", - "TESTADCOUT14": "MONITOR_TESTADCOUT14", - "TESTADCOUT15": "MONITOR_TESTADCOUT15", - "TESTADCOUT16": "MONITOR_TESTADCOUT16", - "TESTADCOUT17": "MONITOR_TESTADCOUT17", - "TESTADCOUT18": "MONITOR_TESTADCOUT18", - "TESTADCOUT19": "MONITOR_TESTADCOUT19", - "TESTADCOUT2": "MONITOR_TESTADCOUT2", - "TESTADCOUT3": "MONITOR_TESTADCOUT3", - "TESTADCOUT4": "MONITOR_TESTADCOUT4", - "TESTADCOUT5": "MONITOR_TESTADCOUT5", - "TESTADCOUT6": "MONITOR_TESTADCOUT6", - "TESTADCOUT7": "MONITOR_TESTADCOUT7", - "TESTADCOUT8": "MONITOR_TESTADCOUT8", - "TESTADCOUT9": "MONITOR_TESTADCOUT9", - "TESTCAPTURE": "MONITOR_TESTCAPTURE", - "TESTDB0": "MONITOR_TESTDB0", - "TESTDB1": "MONITOR_TESTDB1", - "TESTDB10": "MONITOR_TESTDB10", - "TESTDB11": "MONITOR_TESTDB11", - "TESTDB12": "MONITOR_TESTDB12", - "TESTDB13": "MONITOR_TESTDB13", - "TESTDB14": "MONITOR_TESTDB14", - "TESTDB15": "MONITOR_TESTDB15", - "TESTDB2": "MONITOR_TESTDB2", - "TESTDB3": "MONITOR_TESTDB3", - "TESTDB4": "MONITOR_TESTDB4", - "TESTDB5": "MONITOR_TESTDB5", - "TESTDB6": "MONITOR_TESTDB6", - "TESTDB7": "MONITOR_TESTDB7", - "TESTDB8": "MONITOR_TESTDB8", - "TESTDB9": "MONITOR_TESTDB9", - "TESTDRCK": "MONITOR_TESTDRCK", - "TESTENJTAG": "MONITOR_TESTENJTAG", - "TESTRST": "MONITOR_TESTRST", - "TESTSCANCLK0": "MONITOR_TESTSCANCLK0", - "TESTSCANCLK1": "MONITOR_TESTSCANCLK1", - "TESTSCANCLK2": "MONITOR_TESTSCANCLK2", - "TESTSCANCLK3": "MONITOR_TESTSCANCLK3", - "TESTSCANCLK4": "MONITOR_TESTSCANCLK4", - "TESTSCANMODE0": "MONITOR_TESTSCANMODE0", - "TESTSCANMODE1": "MONITOR_TESTSCANMODE1", - "TESTSCANMODE2": "MONITOR_TESTSCANMODE2", - "TESTSCANMODE3": "MONITOR_TESTSCANMODE3", - "TESTSCANMODE4": "MONITOR_TESTSCANMODE4", - "TESTSCANRESET": "MONITOR_TESTSCANRESET", - "TESTSE0": "MONITOR_TESTSE0", - "TESTSE1": "MONITOR_TESTSE1", - "TESTSE2": "MONITOR_TESTSE2", - "TESTSE3": "MONITOR_TESTSE3", - "TESTSE4": "MONITOR_TESTSE4", - "TESTSEL": "MONITOR_TESTSEL", - "TESTSHIFT": "MONITOR_TESTSHIFT", - "TESTSI0": "MONITOR_TESTSI0", - "TESTSI1": "MONITOR_TESTSI1", - "TESTSI2": "MONITOR_TESTSI2", - "TESTSI3": "MONITOR_TESTSI3", - "TESTSI4": "MONITOR_TESTSI4", - "TESTSO0": "MONITOR_TESTSO0", - "TESTSO1": "MONITOR_TESTSO1", - "TESTSO2": "MONITOR_TESTSO2", - "TESTSO3": "MONITOR_TESTSO3", - "TESTSO4": "MONITOR_TESTSO4", - "TESTTDI": "MONITOR_TESTTDI", - "TESTTDO": "MONITOR_TESTTDO", - "TESTUPDATE": "MONITOR_TESTUPDATE", - "VAUXN0": "MONITOR_VAUXN0", - "VAUXN1": "MONITOR_VAUXN1", - "VAUXN10": "MONITOR_VAUXN10", - "VAUXN11": "MONITOR_VAUXN11", - "VAUXN12": "MONITOR_VAUXN12", - "VAUXN13": "MONITOR_VAUXN13", - "VAUXN14": "MONITOR_VAUXN14", - "VAUXN15": "MONITOR_VAUXN15", - "VAUXN2": "MONITOR_VAUXN2", - "VAUXN3": "MONITOR_VAUXN3", - "VAUXN4": "MONITOR_VAUXN4", - "VAUXN5": "MONITOR_VAUXN5", - "VAUXN6": "MONITOR_VAUXN6", - "VAUXN7": "MONITOR_VAUXN7", - "VAUXN8": "MONITOR_VAUXN8", - "VAUXN9": "MONITOR_VAUXN9", - "VAUXP0": "MONITOR_VAUXP0", - "VAUXP1": "MONITOR_VAUXP1", - "VAUXP10": "MONITOR_VAUXP10", - "VAUXP11": "MONITOR_VAUXP11", - "VAUXP12": "MONITOR_VAUXP12", - "VAUXP13": "MONITOR_VAUXP13", - "VAUXP14": "MONITOR_VAUXP14", - "VAUXP15": "MONITOR_VAUXP15", - "VAUXP2": "MONITOR_VAUXP2", - "VAUXP3": "MONITOR_VAUXP3", - "VAUXP4": "MONITOR_VAUXP4", - "VAUXP5": "MONITOR_VAUXP5", - "VAUXP6": "MONITOR_VAUXP6", - "VAUXP7": "MONITOR_VAUXP7", - "VAUXP8": "MONITOR_VAUXP8", - "VAUXP9": "MONITOR_VAUXP9", - "VN": "MONITOR_VN", - "VP": "MONITOR_VP" + "ALM0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM0" + }, + "ALM1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM1" + }, + "ALM2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM2" + }, + "ALM3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM3" + }, + "ALM4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM4" + }, + "ALM5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM5" + }, + "ALM6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM6" + }, + "ALM7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM7" + }, + "BUSY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_BUSY" + }, + "CHANNEL0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_CHANNEL0" + }, + "CHANNEL1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_CHANNEL1" + }, + "CHANNEL2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_CHANNEL2" + }, + "CHANNEL3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_CHANNEL3" + }, + "CHANNEL4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_CHANNEL4" + }, + "CONVST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_CONVST" + }, + "CONVSTCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_CONVSTCLK" + }, + "DADDR0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DADDR0" + }, + "DADDR1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DADDR1" + }, + "DADDR2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DADDR2" + }, + "DADDR3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DADDR3" + }, + "DADDR4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DADDR4" + }, + "DADDR5": { + "cap": "0.000", + "delay": [ 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"0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP7" + }, + "VAUXP8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP8" + }, + "VAUXP9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP9" + }, + "VN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VN" + }, + "VP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VP" + } }, "type": "XADC", "x_coord": 0, @@ -1030,2466 +4249,2466 @@ } ], "tile_type": "MONITOR_BOT_PELE1", - "wires": [ - "MONITOR_ALM0", - "MONITOR_ALM1", - "MONITOR_ALM2", - "MONITOR_ALM3", - "MONITOR_ALM4", - "MONITOR_ALM5", - "MONITOR_ALM6", - "MONITOR_ALM7", - "MONITOR_BLOCK_OUTS_B0_0", - "MONITOR_BLOCK_OUTS_B0_1", - "MONITOR_BLOCK_OUTS_B0_2", - "MONITOR_BLOCK_OUTS_B0_3", - "MONITOR_BLOCK_OUTS_B0_4", - "MONITOR_BLOCK_OUTS_B0_5", - "MONITOR_BLOCK_OUTS_B0_6", - "MONITOR_BLOCK_OUTS_B0_7", - "MONITOR_BLOCK_OUTS_B0_8", - "MONITOR_BLOCK_OUTS_B0_9", - "MONITOR_BLOCK_OUTS_B1_0", - "MONITOR_BLOCK_OUTS_B1_1", - "MONITOR_BLOCK_OUTS_B1_2", - "MONITOR_BLOCK_OUTS_B1_3", - "MONITOR_BLOCK_OUTS_B1_4", - "MONITOR_BLOCK_OUTS_B1_5", - "MONITOR_BLOCK_OUTS_B1_6", - "MONITOR_BLOCK_OUTS_B1_7", - "MONITOR_BLOCK_OUTS_B1_8", - "MONITOR_BLOCK_OUTS_B1_9", - "MONITOR_BLOCK_OUTS_B2_0", - "MONITOR_BLOCK_OUTS_B2_1", - "MONITOR_BLOCK_OUTS_B2_2", - "MONITOR_BLOCK_OUTS_B2_3", - "MONITOR_BLOCK_OUTS_B2_4", - "MONITOR_BLOCK_OUTS_B2_5", - "MONITOR_BLOCK_OUTS_B2_6", - "MONITOR_BLOCK_OUTS_B2_7", - "MONITOR_BLOCK_OUTS_B2_8", - "MONITOR_BLOCK_OUTS_B2_9", - "MONITOR_BLOCK_OUTS_B3_0", - "MONITOR_BLOCK_OUTS_B3_1", - "MONITOR_BLOCK_OUTS_B3_2", - "MONITOR_BLOCK_OUTS_B3_3", - "MONITOR_BLOCK_OUTS_B3_4", - "MONITOR_BLOCK_OUTS_B3_5", - "MONITOR_BLOCK_OUTS_B3_6", - "MONITOR_BLOCK_OUTS_B3_7", - "MONITOR_BLOCK_OUTS_B3_8", - "MONITOR_BLOCK_OUTS_B3_9", - "MONITOR_BUSY", - "MONITOR_BYP0_0", - "MONITOR_BYP0_1", - "MONITOR_BYP0_2", - "MONITOR_BYP0_3", - "MONITOR_BYP0_4", - "MONITOR_BYP0_5", - "MONITOR_BYP0_6", - "MONITOR_BYP0_7", - "MONITOR_BYP0_8", - "MONITOR_BYP0_9", - "MONITOR_BYP1_0", - "MONITOR_BYP1_1", - "MONITOR_BYP1_2", - "MONITOR_BYP1_3", - "MONITOR_BYP1_4", - "MONITOR_BYP1_5", - "MONITOR_BYP1_6", - "MONITOR_BYP1_7", - "MONITOR_BYP1_8", - "MONITOR_BYP1_9", - "MONITOR_BYP2_0", - "MONITOR_BYP2_1", - "MONITOR_BYP2_2", - "MONITOR_BYP2_3", - "MONITOR_BYP2_4", - "MONITOR_BYP2_5", - "MONITOR_BYP2_6", - "MONITOR_BYP2_7", - "MONITOR_BYP2_8", - "MONITOR_BYP2_9", - "MONITOR_BYP3_0", - "MONITOR_BYP3_1", - "MONITOR_BYP3_2", - "MONITOR_BYP3_3", - "MONITOR_BYP3_4", - "MONITOR_BYP3_5", - "MONITOR_BYP3_6", - "MONITOR_BYP3_7", - "MONITOR_BYP3_8", - "MONITOR_BYP3_9", - "MONITOR_BYP4_0", - "MONITOR_BYP4_1", - "MONITOR_BYP4_2", - "MONITOR_BYP4_3", - "MONITOR_BYP4_4", - "MONITOR_BYP4_5", - "MONITOR_BYP4_6", - "MONITOR_BYP4_7", - "MONITOR_BYP4_8", - "MONITOR_BYP4_9", - "MONITOR_BYP5_0", - "MONITOR_BYP5_1", - "MONITOR_BYP5_2", - "MONITOR_BYP5_3", - "MONITOR_BYP5_4", - "MONITOR_BYP5_5", - "MONITOR_BYP5_6", - "MONITOR_BYP5_7", - "MONITOR_BYP5_8", - "MONITOR_BYP5_9", - "MONITOR_BYP6_0", - "MONITOR_BYP6_1", - "MONITOR_BYP6_2", - "MONITOR_BYP6_3", - "MONITOR_BYP6_4", - "MONITOR_BYP6_5", - "MONITOR_BYP6_6", - "MONITOR_BYP6_7", - "MONITOR_BYP6_8", - "MONITOR_BYP6_9", - "MONITOR_BYP7_0", - "MONITOR_BYP7_1", - "MONITOR_BYP7_2", - "MONITOR_BYP7_3", - "MONITOR_BYP7_4", - "MONITOR_BYP7_5", - "MONITOR_BYP7_6", - "MONITOR_BYP7_7", - "MONITOR_BYP7_8", - "MONITOR_BYP7_9", - "MONITOR_CHANNEL0", - "MONITOR_CHANNEL1", - "MONITOR_CHANNEL2", - "MONITOR_CHANNEL3", - "MONITOR_CHANNEL4", - "MONITOR_CLK0_0", - "MONITOR_CLK0_1", - "MONITOR_CLK0_2", - "MONITOR_CLK0_3", - "MONITOR_CLK0_4", - "MONITOR_CLK0_5", - "MONITOR_CLK0_6", - "MONITOR_CLK0_7", - "MONITOR_CLK0_8", - "MONITOR_CLK0_9", - "MONITOR_CLK1_0", - "MONITOR_CLK1_1", - "MONITOR_CLK1_2", - "MONITOR_CLK1_3", - "MONITOR_CLK1_4", - "MONITOR_CLK1_5", - "MONITOR_CLK1_6", - "MONITOR_CLK1_7", - "MONITOR_CLK1_8", - "MONITOR_CLK1_9", - "MONITOR_CONVST", - "MONITOR_CONVSTCLK", - "MONITOR_CTRL0_0", - "MONITOR_CTRL0_1", - "MONITOR_CTRL0_2", - "MONITOR_CTRL0_3", - "MONITOR_CTRL0_4", - "MONITOR_CTRL0_5", - "MONITOR_CTRL0_6", - "MONITOR_CTRL0_7", - "MONITOR_CTRL0_8", - "MONITOR_CTRL0_9", - "MONITOR_CTRL1_0", - "MONITOR_CTRL1_1", - "MONITOR_CTRL1_2", - "MONITOR_CTRL1_3", - "MONITOR_CTRL1_4", - "MONITOR_CTRL1_5", - "MONITOR_CTRL1_6", - "MONITOR_CTRL1_7", - "MONITOR_CTRL1_8", - "MONITOR_CTRL1_9", - "MONITOR_DADDR0", - "MONITOR_DADDR1", - "MONITOR_DADDR2", - "MONITOR_DADDR3", - "MONITOR_DADDR4", - "MONITOR_DADDR5", - "MONITOR_DADDR6", - "MONITOR_DCLK", - "MONITOR_DEN", - "MONITOR_DI0", - "MONITOR_DI1", - "MONITOR_DI10", - "MONITOR_DI11", - "MONITOR_DI12", - "MONITOR_DI13", - "MONITOR_DI14", - "MONITOR_DI15", - "MONITOR_DI2", - "MONITOR_DI3", - "MONITOR_DI4", - "MONITOR_DI5", - "MONITOR_DI6", - "MONITOR_DI7", - "MONITOR_DI8", - "MONITOR_DI9", - "MONITOR_DO0", - "MONITOR_DO1", - "MONITOR_DO10", - "MONITOR_DO11", - "MONITOR_DO12", - "MONITOR_DO13", - "MONITOR_DO14", - "MONITOR_DO15", - "MONITOR_DO2", - "MONITOR_DO3", - "MONITOR_DO4", - "MONITOR_DO5", - "MONITOR_DO6", - "MONITOR_DO7", - "MONITOR_DO8", - "MONITOR_DO9", - "MONITOR_DRDY", - "MONITOR_DWE", - "MONITOR_EE2A0_0", - "MONITOR_EE2A0_1", - "MONITOR_EE2A0_2", - "MONITOR_EE2A0_3", - "MONITOR_EE2A0_4", - "MONITOR_EE2A0_5", - "MONITOR_EE2A0_6", - "MONITOR_EE2A0_7", - "MONITOR_EE2A0_8", - "MONITOR_EE2A0_9", - "MONITOR_EE2A1_0", - "MONITOR_EE2A1_1", - "MONITOR_EE2A1_2", - "MONITOR_EE2A1_3", - "MONITOR_EE2A1_4", - "MONITOR_EE2A1_5", - "MONITOR_EE2A1_6", - "MONITOR_EE2A1_7", - "MONITOR_EE2A1_8", - "MONITOR_EE2A1_9", - "MONITOR_EE2A2_0", - "MONITOR_EE2A2_1", - "MONITOR_EE2A2_2", - "MONITOR_EE2A2_3", - "MONITOR_EE2A2_4", - "MONITOR_EE2A2_5", - "MONITOR_EE2A2_6", - "MONITOR_EE2A2_7", - "MONITOR_EE2A2_8", - "MONITOR_EE2A2_9", - "MONITOR_EE2A3_0", - "MONITOR_EE2A3_1", - "MONITOR_EE2A3_2", - "MONITOR_EE2A3_3", - "MONITOR_EE2A3_4", - "MONITOR_EE2A3_5", - "MONITOR_EE2A3_6", - "MONITOR_EE2A3_7", - "MONITOR_EE2A3_8", - "MONITOR_EE2A3_9", - "MONITOR_EE2BEG0_0", - "MONITOR_EE2BEG0_1", - "MONITOR_EE2BEG0_2", - "MONITOR_EE2BEG0_3", - "MONITOR_EE2BEG0_4", - "MONITOR_EE2BEG0_5", - "MONITOR_EE2BEG0_6", - "MONITOR_EE2BEG0_7", - "MONITOR_EE2BEG0_8", - "MONITOR_EE2BEG0_9", - "MONITOR_EE2BEG1_0", - "MONITOR_EE2BEG1_1", - "MONITOR_EE2BEG1_2", - "MONITOR_EE2BEG1_3", - "MONITOR_EE2BEG1_4", - "MONITOR_EE2BEG1_5", - "MONITOR_EE2BEG1_6", - "MONITOR_EE2BEG1_7", - "MONITOR_EE2BEG1_8", - "MONITOR_EE2BEG1_9", - "MONITOR_EE2BEG2_0", - "MONITOR_EE2BEG2_1", - "MONITOR_EE2BEG2_2", - "MONITOR_EE2BEG2_3", - "MONITOR_EE2BEG2_4", - "MONITOR_EE2BEG2_5", - "MONITOR_EE2BEG2_6", - "MONITOR_EE2BEG2_7", - "MONITOR_EE2BEG2_8", - "MONITOR_EE2BEG2_9", - "MONITOR_EE2BEG3_0", - "MONITOR_EE2BEG3_1", - "MONITOR_EE2BEG3_2", - "MONITOR_EE2BEG3_3", - "MONITOR_EE2BEG3_4", - "MONITOR_EE2BEG3_5", - "MONITOR_EE2BEG3_6", - "MONITOR_EE2BEG3_7", - "MONITOR_EE2BEG3_8", - "MONITOR_EE2BEG3_9", - "MONITOR_EE4A0_0", - "MONITOR_EE4A0_1", - "MONITOR_EE4A0_2", - "MONITOR_EE4A0_3", - "MONITOR_EE4A0_4", - "MONITOR_EE4A0_5", - "MONITOR_EE4A0_6", - "MONITOR_EE4A0_7", - "MONITOR_EE4A0_8", - "MONITOR_EE4A0_9", - "MONITOR_EE4A1_0", - "MONITOR_EE4A1_1", - "MONITOR_EE4A1_2", - "MONITOR_EE4A1_3", - "MONITOR_EE4A1_4", - "MONITOR_EE4A1_5", - "MONITOR_EE4A1_6", - "MONITOR_EE4A1_7", - "MONITOR_EE4A1_8", - "MONITOR_EE4A1_9", - "MONITOR_EE4A2_0", - "MONITOR_EE4A2_1", - "MONITOR_EE4A2_2", - "MONITOR_EE4A2_3", - "MONITOR_EE4A2_4", - "MONITOR_EE4A2_5", - "MONITOR_EE4A2_6", - "MONITOR_EE4A2_7", - "MONITOR_EE4A2_8", - "MONITOR_EE4A2_9", - "MONITOR_EE4A3_0", - "MONITOR_EE4A3_1", - "MONITOR_EE4A3_2", - "MONITOR_EE4A3_3", - "MONITOR_EE4A3_4", - "MONITOR_EE4A3_5", - "MONITOR_EE4A3_6", - "MONITOR_EE4A3_7", - "MONITOR_EE4A3_8", - "MONITOR_EE4A3_9", - "MONITOR_EE4B0_0", - "MONITOR_EE4B0_1", - "MONITOR_EE4B0_2", - "MONITOR_EE4B0_3", - "MONITOR_EE4B0_4", - "MONITOR_EE4B0_5", - "MONITOR_EE4B0_6", - "MONITOR_EE4B0_7", - "MONITOR_EE4B0_8", - "MONITOR_EE4B0_9", - "MONITOR_EE4B1_0", - "MONITOR_EE4B1_1", - "MONITOR_EE4B1_2", - "MONITOR_EE4B1_3", - "MONITOR_EE4B1_4", - "MONITOR_EE4B1_5", - "MONITOR_EE4B1_6", - "MONITOR_EE4B1_7", - "MONITOR_EE4B1_8", - "MONITOR_EE4B1_9", - "MONITOR_EE4B2_0", - "MONITOR_EE4B2_1", - "MONITOR_EE4B2_2", - "MONITOR_EE4B2_3", - "MONITOR_EE4B2_4", - "MONITOR_EE4B2_5", - "MONITOR_EE4B2_6", - "MONITOR_EE4B2_7", - "MONITOR_EE4B2_8", - "MONITOR_EE4B2_9", - "MONITOR_EE4B3_0", - "MONITOR_EE4B3_1", - "MONITOR_EE4B3_2", - "MONITOR_EE4B3_3", - "MONITOR_EE4B3_4", - "MONITOR_EE4B3_5", - "MONITOR_EE4B3_6", - "MONITOR_EE4B3_7", - "MONITOR_EE4B3_8", - "MONITOR_EE4B3_9", - "MONITOR_EE4BEG0_0", - "MONITOR_EE4BEG0_1", - "MONITOR_EE4BEG0_2", - "MONITOR_EE4BEG0_3", - "MONITOR_EE4BEG0_4", - "MONITOR_EE4BEG0_5", - "MONITOR_EE4BEG0_6", - "MONITOR_EE4BEG0_7", - "MONITOR_EE4BEG0_8", - "MONITOR_EE4BEG0_9", - "MONITOR_EE4BEG1_0", - "MONITOR_EE4BEG1_1", - "MONITOR_EE4BEG1_2", - "MONITOR_EE4BEG1_3", - "MONITOR_EE4BEG1_4", - "MONITOR_EE4BEG1_5", - "MONITOR_EE4BEG1_6", - "MONITOR_EE4BEG1_7", - "MONITOR_EE4BEG1_8", - "MONITOR_EE4BEG1_9", - "MONITOR_EE4BEG2_0", - "MONITOR_EE4BEG2_1", - "MONITOR_EE4BEG2_2", - "MONITOR_EE4BEG2_3", - "MONITOR_EE4BEG2_4", - "MONITOR_EE4BEG2_5", - "MONITOR_EE4BEG2_6", - "MONITOR_EE4BEG2_7", - "MONITOR_EE4BEG2_8", - "MONITOR_EE4BEG2_9", - "MONITOR_EE4BEG3_0", - "MONITOR_EE4BEG3_1", - "MONITOR_EE4BEG3_2", - "MONITOR_EE4BEG3_3", - "MONITOR_EE4BEG3_4", - "MONITOR_EE4BEG3_5", - "MONITOR_EE4BEG3_6", - "MONITOR_EE4BEG3_7", - "MONITOR_EE4BEG3_8", - "MONITOR_EE4BEG3_9", - "MONITOR_EE4C0_0", - "MONITOR_EE4C0_1", - "MONITOR_EE4C0_2", - "MONITOR_EE4C0_3", - "MONITOR_EE4C0_4", - "MONITOR_EE4C0_5", - "MONITOR_EE4C0_6", - "MONITOR_EE4C0_7", - "MONITOR_EE4C0_8", - "MONITOR_EE4C0_9", - "MONITOR_EE4C1_0", - "MONITOR_EE4C1_1", - "MONITOR_EE4C1_2", - "MONITOR_EE4C1_3", - "MONITOR_EE4C1_4", - "MONITOR_EE4C1_5", - "MONITOR_EE4C1_6", - "MONITOR_EE4C1_7", - "MONITOR_EE4C1_8", - "MONITOR_EE4C1_9", - "MONITOR_EE4C2_0", - "MONITOR_EE4C2_1", - "MONITOR_EE4C2_2", - "MONITOR_EE4C2_3", - "MONITOR_EE4C2_4", - "MONITOR_EE4C2_5", - "MONITOR_EE4C2_6", - "MONITOR_EE4C2_7", - "MONITOR_EE4C2_8", - "MONITOR_EE4C2_9", - "MONITOR_EE4C3_0", - "MONITOR_EE4C3_1", - "MONITOR_EE4C3_2", - "MONITOR_EE4C3_3", - "MONITOR_EE4C3_4", - "MONITOR_EE4C3_5", - "MONITOR_EE4C3_6", - "MONITOR_EE4C3_7", - "MONITOR_EE4C3_8", - "MONITOR_EE4C3_9", - "MONITOR_EL1BEG0_0", - "MONITOR_EL1BEG0_1", - "MONITOR_EL1BEG0_2", - "MONITOR_EL1BEG0_3", - "MONITOR_EL1BEG0_4", - "MONITOR_EL1BEG0_5", - "MONITOR_EL1BEG0_6", - "MONITOR_EL1BEG0_7", - "MONITOR_EL1BEG0_8", - "MONITOR_EL1BEG0_9", - "MONITOR_EL1BEG1_0", - "MONITOR_EL1BEG1_1", - "MONITOR_EL1BEG1_2", - "MONITOR_EL1BEG1_3", - "MONITOR_EL1BEG1_4", - "MONITOR_EL1BEG1_5", - "MONITOR_EL1BEG1_6", - "MONITOR_EL1BEG1_7", - "MONITOR_EL1BEG1_8", - "MONITOR_EL1BEG1_9", - "MONITOR_EL1BEG2_0", - "MONITOR_EL1BEG2_1", - "MONITOR_EL1BEG2_2", - "MONITOR_EL1BEG2_3", - "MONITOR_EL1BEG2_4", - "MONITOR_EL1BEG2_5", - "MONITOR_EL1BEG2_6", - "MONITOR_EL1BEG2_7", - "MONITOR_EL1BEG2_8", - "MONITOR_EL1BEG2_9", - "MONITOR_EL1BEG3_0", - "MONITOR_EL1BEG3_1", - "MONITOR_EL1BEG3_2", - "MONITOR_EL1BEG3_3", - "MONITOR_EL1BEG3_4", - "MONITOR_EL1BEG3_5", - "MONITOR_EL1BEG3_6", - "MONITOR_EL1BEG3_7", - "MONITOR_EL1BEG3_8", - "MONITOR_EL1BEG3_9", - "MONITOR_EOC", - "MONITOR_EOS", - "MONITOR_ER1BEG0_0", - "MONITOR_ER1BEG0_1", - "MONITOR_ER1BEG0_2", - "MONITOR_ER1BEG0_3", - "MONITOR_ER1BEG0_4", - "MONITOR_ER1BEG0_5", - "MONITOR_ER1BEG0_6", - "MONITOR_ER1BEG0_7", - "MONITOR_ER1BEG0_8", - "MONITOR_ER1BEG0_9", - "MONITOR_ER1BEG1_0", - "MONITOR_ER1BEG1_1", - "MONITOR_ER1BEG1_2", - "MONITOR_ER1BEG1_3", - "MONITOR_ER1BEG1_4", - "MONITOR_ER1BEG1_5", - "MONITOR_ER1BEG1_6", - "MONITOR_ER1BEG1_7", - "MONITOR_ER1BEG1_8", - "MONITOR_ER1BEG1_9", - "MONITOR_ER1BEG2_0", - "MONITOR_ER1BEG2_1", - "MONITOR_ER1BEG2_2", - "MONITOR_ER1BEG2_3", - "MONITOR_ER1BEG2_4", - "MONITOR_ER1BEG2_5", - "MONITOR_ER1BEG2_6", - "MONITOR_ER1BEG2_7", - "MONITOR_ER1BEG2_8", - "MONITOR_ER1BEG2_9", - "MONITOR_ER1BEG3_0", - "MONITOR_ER1BEG3_1", - "MONITOR_ER1BEG3_2", - "MONITOR_ER1BEG3_3", - "MONITOR_ER1BEG3_4", - "MONITOR_ER1BEG3_5", - "MONITOR_ER1BEG3_6", - "MONITOR_ER1BEG3_7", - "MONITOR_ER1BEG3_8", - "MONITOR_ER1BEG3_9", - "MONITOR_FAN0_0", - "MONITOR_FAN0_1", - "MONITOR_FAN0_2", - "MONITOR_FAN0_3", - "MONITOR_FAN0_4", - "MONITOR_FAN0_5", - "MONITOR_FAN0_6", - "MONITOR_FAN0_7", - "MONITOR_FAN0_8", - "MONITOR_FAN0_9", - "MONITOR_FAN1_0", - "MONITOR_FAN1_1", - "MONITOR_FAN1_2", - "MONITOR_FAN1_3", - "MONITOR_FAN1_4", - "MONITOR_FAN1_5", - "MONITOR_FAN1_6", - "MONITOR_FAN1_7", - "MONITOR_FAN1_8", - "MONITOR_FAN1_9", - "MONITOR_FAN2_0", - "MONITOR_FAN2_1", - "MONITOR_FAN2_2", - "MONITOR_FAN2_3", - "MONITOR_FAN2_4", - "MONITOR_FAN2_5", - "MONITOR_FAN2_6", - "MONITOR_FAN2_7", - "MONITOR_FAN2_8", - "MONITOR_FAN2_9", - "MONITOR_FAN3_0", - "MONITOR_FAN3_1", - "MONITOR_FAN3_2", - "MONITOR_FAN3_3", - "MONITOR_FAN3_4", - "MONITOR_FAN3_5", - "MONITOR_FAN3_6", - "MONITOR_FAN3_7", - "MONITOR_FAN3_8", - "MONITOR_FAN3_9", - "MONITOR_FAN4_0", - "MONITOR_FAN4_1", - "MONITOR_FAN4_2", - "MONITOR_FAN4_3", - "MONITOR_FAN4_4", - "MONITOR_FAN4_5", - "MONITOR_FAN4_6", - "MONITOR_FAN4_7", - "MONITOR_FAN4_8", - "MONITOR_FAN4_9", - "MONITOR_FAN5_0", - "MONITOR_FAN5_1", - "MONITOR_FAN5_2", - "MONITOR_FAN5_3", - "MONITOR_FAN5_4", - "MONITOR_FAN5_5", - "MONITOR_FAN5_6", - "MONITOR_FAN5_7", - "MONITOR_FAN5_8", - "MONITOR_FAN5_9", - "MONITOR_FAN6_0", - "MONITOR_FAN6_1", - "MONITOR_FAN6_2", - "MONITOR_FAN6_3", - "MONITOR_FAN6_4", - "MONITOR_FAN6_5", - "MONITOR_FAN6_6", - "MONITOR_FAN6_7", - "MONITOR_FAN6_8", - "MONITOR_FAN6_9", - "MONITOR_FAN7_0", - "MONITOR_FAN7_1", - "MONITOR_FAN7_2", - "MONITOR_FAN7_3", - "MONITOR_FAN7_4", - "MONITOR_FAN7_5", - "MONITOR_FAN7_6", - "MONITOR_FAN7_7", - "MONITOR_FAN7_8", - "MONITOR_FAN7_9", - "MONITOR_HORIZ_VAUXN10_RIGHT", - "MONITOR_HORIZ_VAUXN11_RIGHT", - "MONITOR_HORIZ_VAUXN3_RIGHT", - "MONITOR_HORIZ_VAUXP10_RIGHT", - "MONITOR_HORIZ_VAUXP11_RIGHT", - "MONITOR_HORIZ_VAUXP3_RIGHT", - "MONITOR_IMUX0_0", - "MONITOR_IMUX0_1", - "MONITOR_IMUX0_2", - "MONITOR_IMUX0_3", - "MONITOR_IMUX0_4", - "MONITOR_IMUX0_5", - "MONITOR_IMUX0_6", - "MONITOR_IMUX0_7", - "MONITOR_IMUX0_8", - "MONITOR_IMUX0_9", - "MONITOR_IMUX10_0", - "MONITOR_IMUX10_1", - "MONITOR_IMUX10_2", - "MONITOR_IMUX10_3", - "MONITOR_IMUX10_4", - "MONITOR_IMUX10_5", - "MONITOR_IMUX10_6", - "MONITOR_IMUX10_7", - "MONITOR_IMUX10_8", - "MONITOR_IMUX10_9", - "MONITOR_IMUX11_0", - "MONITOR_IMUX11_1", - "MONITOR_IMUX11_2", - "MONITOR_IMUX11_3", - "MONITOR_IMUX11_4", - "MONITOR_IMUX11_5", - "MONITOR_IMUX11_6", - "MONITOR_IMUX11_7", - "MONITOR_IMUX11_8", - "MONITOR_IMUX11_9", - "MONITOR_IMUX12_0", - "MONITOR_IMUX12_1", - "MONITOR_IMUX12_2", - "MONITOR_IMUX12_3", - "MONITOR_IMUX12_4", - "MONITOR_IMUX12_5", - "MONITOR_IMUX12_6", - "MONITOR_IMUX12_7", - "MONITOR_IMUX12_8", - "MONITOR_IMUX12_9", - "MONITOR_IMUX13_0", - "MONITOR_IMUX13_1", - "MONITOR_IMUX13_2", - "MONITOR_IMUX13_3", - "MONITOR_IMUX13_4", - "MONITOR_IMUX13_5", - "MONITOR_IMUX13_6", - "MONITOR_IMUX13_7", - "MONITOR_IMUX13_8", - "MONITOR_IMUX13_9", - "MONITOR_IMUX14_0", - "MONITOR_IMUX14_1", - "MONITOR_IMUX14_2", - "MONITOR_IMUX14_3", - "MONITOR_IMUX14_4", - "MONITOR_IMUX14_5", - "MONITOR_IMUX14_6", - "MONITOR_IMUX14_7", - "MONITOR_IMUX14_8", - "MONITOR_IMUX14_9", - "MONITOR_IMUX15_0", - "MONITOR_IMUX15_1", - "MONITOR_IMUX15_2", - "MONITOR_IMUX15_3", - "MONITOR_IMUX15_4", - "MONITOR_IMUX15_5", - "MONITOR_IMUX15_6", - "MONITOR_IMUX15_7", - "MONITOR_IMUX15_8", - "MONITOR_IMUX15_9", - "MONITOR_IMUX16_0", - "MONITOR_IMUX16_1", - "MONITOR_IMUX16_2", - "MONITOR_IMUX16_3", - "MONITOR_IMUX16_4", - "MONITOR_IMUX16_5", - "MONITOR_IMUX16_6", - "MONITOR_IMUX16_7", - "MONITOR_IMUX16_8", - "MONITOR_IMUX16_9", - "MONITOR_IMUX17_0", - "MONITOR_IMUX17_1", - "MONITOR_IMUX17_2", - "MONITOR_IMUX17_3", - "MONITOR_IMUX17_4", - "MONITOR_IMUX17_5", - "MONITOR_IMUX17_6", - "MONITOR_IMUX17_7", - "MONITOR_IMUX17_8", - "MONITOR_IMUX17_9", - "MONITOR_IMUX18_0", - "MONITOR_IMUX18_1", - "MONITOR_IMUX18_2", - "MONITOR_IMUX18_3", - "MONITOR_IMUX18_4", - "MONITOR_IMUX18_5", - "MONITOR_IMUX18_6", - "MONITOR_IMUX18_7", - "MONITOR_IMUX18_8", - "MONITOR_IMUX18_9", - "MONITOR_IMUX19_0", - "MONITOR_IMUX19_1", - "MONITOR_IMUX19_2", - "MONITOR_IMUX19_3", - "MONITOR_IMUX19_4", - "MONITOR_IMUX19_5", - "MONITOR_IMUX19_6", - "MONITOR_IMUX19_7", - "MONITOR_IMUX19_8", - "MONITOR_IMUX19_9", - "MONITOR_IMUX1_0", - "MONITOR_IMUX1_1", - "MONITOR_IMUX1_2", - "MONITOR_IMUX1_3", - "MONITOR_IMUX1_4", - "MONITOR_IMUX1_5", - "MONITOR_IMUX1_6", - "MONITOR_IMUX1_7", - "MONITOR_IMUX1_8", - "MONITOR_IMUX1_9", - "MONITOR_IMUX20_0", - "MONITOR_IMUX20_1", - "MONITOR_IMUX20_2", - "MONITOR_IMUX20_3", - "MONITOR_IMUX20_4", - "MONITOR_IMUX20_5", - "MONITOR_IMUX20_6", - "MONITOR_IMUX20_7", - "MONITOR_IMUX20_8", - "MONITOR_IMUX20_9", - "MONITOR_IMUX21_0", - "MONITOR_IMUX21_1", - "MONITOR_IMUX21_2", - "MONITOR_IMUX21_3", - "MONITOR_IMUX21_4", - "MONITOR_IMUX21_5", - "MONITOR_IMUX21_6", - "MONITOR_IMUX21_7", - "MONITOR_IMUX21_8", - "MONITOR_IMUX21_9", - "MONITOR_IMUX22_0", - "MONITOR_IMUX22_1", - "MONITOR_IMUX22_2", - "MONITOR_IMUX22_3", - "MONITOR_IMUX22_4", - "MONITOR_IMUX22_5", - "MONITOR_IMUX22_6", - "MONITOR_IMUX22_7", - "MONITOR_IMUX22_8", - "MONITOR_IMUX22_9", - "MONITOR_IMUX23_0", - "MONITOR_IMUX23_1", - "MONITOR_IMUX23_2", - "MONITOR_IMUX23_3", - "MONITOR_IMUX23_4", - "MONITOR_IMUX23_5", - "MONITOR_IMUX23_6", - "MONITOR_IMUX23_7", - "MONITOR_IMUX23_8", - "MONITOR_IMUX23_9", - "MONITOR_IMUX24_0", - "MONITOR_IMUX24_1", - "MONITOR_IMUX24_2", - "MONITOR_IMUX24_3", - "MONITOR_IMUX24_4", - "MONITOR_IMUX24_5", - "MONITOR_IMUX24_6", - "MONITOR_IMUX24_7", - "MONITOR_IMUX24_8", - "MONITOR_IMUX24_9", - "MONITOR_IMUX25_0", - "MONITOR_IMUX25_1", - "MONITOR_IMUX25_2", - "MONITOR_IMUX25_3", - "MONITOR_IMUX25_4", - "MONITOR_IMUX25_5", - "MONITOR_IMUX25_6", - "MONITOR_IMUX25_7", - "MONITOR_IMUX25_8", - "MONITOR_IMUX25_9", - "MONITOR_IMUX26_0", - "MONITOR_IMUX26_1", - "MONITOR_IMUX26_2", - "MONITOR_IMUX26_3", - "MONITOR_IMUX26_4", - "MONITOR_IMUX26_5", - "MONITOR_IMUX26_6", - "MONITOR_IMUX26_7", - "MONITOR_IMUX26_8", - "MONITOR_IMUX26_9", - "MONITOR_IMUX27_0", - "MONITOR_IMUX27_1", - "MONITOR_IMUX27_2", - "MONITOR_IMUX27_3", - "MONITOR_IMUX27_4", - "MONITOR_IMUX27_5", - "MONITOR_IMUX27_6", - "MONITOR_IMUX27_7", - "MONITOR_IMUX27_8", - "MONITOR_IMUX27_9", - "MONITOR_IMUX28_0", - "MONITOR_IMUX28_1", - "MONITOR_IMUX28_2", - "MONITOR_IMUX28_3", - "MONITOR_IMUX28_4", - "MONITOR_IMUX28_5", - "MONITOR_IMUX28_6", - "MONITOR_IMUX28_7", - "MONITOR_IMUX28_8", - "MONITOR_IMUX28_9", - "MONITOR_IMUX29_0", - "MONITOR_IMUX29_1", - "MONITOR_IMUX29_2", - "MONITOR_IMUX29_3", - "MONITOR_IMUX29_4", - "MONITOR_IMUX29_5", - "MONITOR_IMUX29_6", - "MONITOR_IMUX29_7", - "MONITOR_IMUX29_8", - "MONITOR_IMUX29_9", - "MONITOR_IMUX2_0", - "MONITOR_IMUX2_1", - "MONITOR_IMUX2_2", - "MONITOR_IMUX2_3", - "MONITOR_IMUX2_4", - "MONITOR_IMUX2_5", - "MONITOR_IMUX2_6", - "MONITOR_IMUX2_7", - "MONITOR_IMUX2_8", - "MONITOR_IMUX2_9", - "MONITOR_IMUX30_0", - "MONITOR_IMUX30_1", - "MONITOR_IMUX30_2", - "MONITOR_IMUX30_3", - "MONITOR_IMUX30_4", - "MONITOR_IMUX30_5", - "MONITOR_IMUX30_6", - "MONITOR_IMUX30_7", - "MONITOR_IMUX30_8", - "MONITOR_IMUX30_9", - "MONITOR_IMUX31_0", - "MONITOR_IMUX31_1", - "MONITOR_IMUX31_2", - "MONITOR_IMUX31_3", - "MONITOR_IMUX31_4", - "MONITOR_IMUX31_5", - "MONITOR_IMUX31_6", - "MONITOR_IMUX31_7", - "MONITOR_IMUX31_8", - "MONITOR_IMUX31_9", - "MONITOR_IMUX32_0", - "MONITOR_IMUX32_1", - "MONITOR_IMUX32_2", - "MONITOR_IMUX32_3", - "MONITOR_IMUX32_4", - "MONITOR_IMUX32_5", - "MONITOR_IMUX32_6", - "MONITOR_IMUX32_7", - "MONITOR_IMUX32_8", - "MONITOR_IMUX32_9", - "MONITOR_IMUX33_0", - "MONITOR_IMUX33_1", - "MONITOR_IMUX33_2", - "MONITOR_IMUX33_3", - "MONITOR_IMUX33_4", - "MONITOR_IMUX33_5", - "MONITOR_IMUX33_6", - "MONITOR_IMUX33_7", - "MONITOR_IMUX33_8", - "MONITOR_IMUX33_9", - "MONITOR_IMUX34_0", - "MONITOR_IMUX34_1", - "MONITOR_IMUX34_2", - "MONITOR_IMUX34_3", - "MONITOR_IMUX34_4", - "MONITOR_IMUX34_5", - "MONITOR_IMUX34_6", - "MONITOR_IMUX34_7", - "MONITOR_IMUX34_8", - "MONITOR_IMUX34_9", - "MONITOR_IMUX35_0", - "MONITOR_IMUX35_1", - "MONITOR_IMUX35_2", - "MONITOR_IMUX35_3", - "MONITOR_IMUX35_4", - "MONITOR_IMUX35_5", - "MONITOR_IMUX35_6", - "MONITOR_IMUX35_7", - "MONITOR_IMUX35_8", - "MONITOR_IMUX35_9", - "MONITOR_IMUX36_0", - "MONITOR_IMUX36_1", - "MONITOR_IMUX36_2", - "MONITOR_IMUX36_3", - "MONITOR_IMUX36_4", - "MONITOR_IMUX36_5", - "MONITOR_IMUX36_6", - "MONITOR_IMUX36_7", - "MONITOR_IMUX36_8", - "MONITOR_IMUX36_9", - "MONITOR_IMUX37_0", - "MONITOR_IMUX37_1", - "MONITOR_IMUX37_2", - "MONITOR_IMUX37_3", - "MONITOR_IMUX37_4", - "MONITOR_IMUX37_5", - "MONITOR_IMUX37_6", - "MONITOR_IMUX37_7", - "MONITOR_IMUX37_8", - "MONITOR_IMUX37_9", - "MONITOR_IMUX38_0", - "MONITOR_IMUX38_1", - "MONITOR_IMUX38_2", - "MONITOR_IMUX38_3", - "MONITOR_IMUX38_4", - "MONITOR_IMUX38_5", - "MONITOR_IMUX38_6", - "MONITOR_IMUX38_7", - "MONITOR_IMUX38_8", - "MONITOR_IMUX38_9", - "MONITOR_IMUX39_0", - "MONITOR_IMUX39_1", - "MONITOR_IMUX39_2", - "MONITOR_IMUX39_3", - "MONITOR_IMUX39_4", - "MONITOR_IMUX39_5", - "MONITOR_IMUX39_6", - "MONITOR_IMUX39_7", - "MONITOR_IMUX39_8", - "MONITOR_IMUX39_9", - "MONITOR_IMUX3_0", - "MONITOR_IMUX3_1", - "MONITOR_IMUX3_2", - "MONITOR_IMUX3_3", - "MONITOR_IMUX3_4", - "MONITOR_IMUX3_5", - "MONITOR_IMUX3_6", - "MONITOR_IMUX3_7", - "MONITOR_IMUX3_8", - "MONITOR_IMUX3_9", - "MONITOR_IMUX40_0", - "MONITOR_IMUX40_1", - "MONITOR_IMUX40_2", - "MONITOR_IMUX40_3", - "MONITOR_IMUX40_4", - "MONITOR_IMUX40_5", - "MONITOR_IMUX40_6", - "MONITOR_IMUX40_7", - "MONITOR_IMUX40_8", - "MONITOR_IMUX40_9", - "MONITOR_IMUX41_0", - "MONITOR_IMUX41_1", - "MONITOR_IMUX41_2", - "MONITOR_IMUX41_3", - "MONITOR_IMUX41_4", - "MONITOR_IMUX41_5", - "MONITOR_IMUX41_6", - "MONITOR_IMUX41_7", - "MONITOR_IMUX41_8", - "MONITOR_IMUX41_9", - "MONITOR_IMUX42_0", - "MONITOR_IMUX42_1", - "MONITOR_IMUX42_2", - "MONITOR_IMUX42_3", - "MONITOR_IMUX42_4", - "MONITOR_IMUX42_5", - "MONITOR_IMUX42_6", - "MONITOR_IMUX42_7", - "MONITOR_IMUX42_8", - "MONITOR_IMUX42_9", - "MONITOR_IMUX43_0", - "MONITOR_IMUX43_1", - "MONITOR_IMUX43_2", - "MONITOR_IMUX43_3", - "MONITOR_IMUX43_4", - "MONITOR_IMUX43_5", - "MONITOR_IMUX43_6", - "MONITOR_IMUX43_7", - "MONITOR_IMUX43_8", - "MONITOR_IMUX43_9", - "MONITOR_IMUX44_0", - "MONITOR_IMUX44_1", - "MONITOR_IMUX44_2", - "MONITOR_IMUX44_3", - "MONITOR_IMUX44_4", - "MONITOR_IMUX44_5", - "MONITOR_IMUX44_6", - "MONITOR_IMUX44_7", - "MONITOR_IMUX44_8", - "MONITOR_IMUX44_9", - "MONITOR_IMUX45_0", - "MONITOR_IMUX45_1", - "MONITOR_IMUX45_2", - "MONITOR_IMUX45_3", - "MONITOR_IMUX45_4", - "MONITOR_IMUX45_5", - "MONITOR_IMUX45_6", - "MONITOR_IMUX45_7", - "MONITOR_IMUX45_8", - "MONITOR_IMUX45_9", - "MONITOR_IMUX46_0", - "MONITOR_IMUX46_1", - "MONITOR_IMUX46_2", - "MONITOR_IMUX46_3", - "MONITOR_IMUX46_4", - "MONITOR_IMUX46_5", - "MONITOR_IMUX46_6", - "MONITOR_IMUX46_7", - "MONITOR_IMUX46_8", - "MONITOR_IMUX46_9", - "MONITOR_IMUX47_0", - "MONITOR_IMUX47_1", - "MONITOR_IMUX47_2", - "MONITOR_IMUX47_3", - "MONITOR_IMUX47_4", - "MONITOR_IMUX47_5", - "MONITOR_IMUX47_6", - "MONITOR_IMUX47_7", - "MONITOR_IMUX47_8", - "MONITOR_IMUX47_9", - "MONITOR_IMUX4_0", - "MONITOR_IMUX4_1", - "MONITOR_IMUX4_2", - "MONITOR_IMUX4_3", - "MONITOR_IMUX4_4", - "MONITOR_IMUX4_5", - "MONITOR_IMUX4_6", - "MONITOR_IMUX4_7", - "MONITOR_IMUX4_8", - "MONITOR_IMUX4_9", - "MONITOR_IMUX5_0", - "MONITOR_IMUX5_1", - "MONITOR_IMUX5_2", - "MONITOR_IMUX5_3", - "MONITOR_IMUX5_4", - "MONITOR_IMUX5_5", - "MONITOR_IMUX5_6", - "MONITOR_IMUX5_7", - "MONITOR_IMUX5_8", - "MONITOR_IMUX5_9", - "MONITOR_IMUX6_0", - "MONITOR_IMUX6_1", - "MONITOR_IMUX6_2", - "MONITOR_IMUX6_3", - "MONITOR_IMUX6_4", - "MONITOR_IMUX6_5", - "MONITOR_IMUX6_6", - "MONITOR_IMUX6_7", - "MONITOR_IMUX6_8", - "MONITOR_IMUX6_9", - "MONITOR_IMUX7_0", - "MONITOR_IMUX7_1", - "MONITOR_IMUX7_2", - "MONITOR_IMUX7_3", - "MONITOR_IMUX7_4", - "MONITOR_IMUX7_5", - "MONITOR_IMUX7_6", - "MONITOR_IMUX7_7", - "MONITOR_IMUX7_8", - "MONITOR_IMUX7_9", - "MONITOR_IMUX8_0", - "MONITOR_IMUX8_1", - "MONITOR_IMUX8_2", - "MONITOR_IMUX8_3", - "MONITOR_IMUX8_4", - "MONITOR_IMUX8_5", - "MONITOR_IMUX8_6", - "MONITOR_IMUX8_7", - "MONITOR_IMUX8_8", - "MONITOR_IMUX8_9", - "MONITOR_IMUX9_0", - "MONITOR_IMUX9_1", - "MONITOR_IMUX9_2", - "MONITOR_IMUX9_3", - "MONITOR_IMUX9_4", - "MONITOR_IMUX9_5", - "MONITOR_IMUX9_6", - "MONITOR_IMUX9_7", - "MONITOR_IMUX9_8", - "MONITOR_IMUX9_9", - "MONITOR_JTAGBUSY", - "MONITOR_JTAGLOCKED", - "MONITOR_JTAGMODIFIED", - "MONITOR_LH10_0", - "MONITOR_LH10_1", - "MONITOR_LH10_2", - "MONITOR_LH10_3", - "MONITOR_LH10_4", - "MONITOR_LH10_5", - "MONITOR_LH10_6", - "MONITOR_LH10_7", - "MONITOR_LH10_8", - "MONITOR_LH10_9", - "MONITOR_LH11_0", - "MONITOR_LH11_1", - "MONITOR_LH11_2", - "MONITOR_LH11_3", - "MONITOR_LH11_4", - "MONITOR_LH11_5", - "MONITOR_LH11_6", - "MONITOR_LH11_7", - "MONITOR_LH11_8", - "MONITOR_LH11_9", - "MONITOR_LH12_0", - "MONITOR_LH12_1", - "MONITOR_LH12_2", - "MONITOR_LH12_3", - "MONITOR_LH12_4", - "MONITOR_LH12_5", - "MONITOR_LH12_6", - "MONITOR_LH12_7", - "MONITOR_LH12_8", - "MONITOR_LH12_9", - "MONITOR_LH1_0", - "MONITOR_LH1_1", - "MONITOR_LH1_2", - "MONITOR_LH1_3", - "MONITOR_LH1_4", - "MONITOR_LH1_5", - "MONITOR_LH1_6", - "MONITOR_LH1_7", - "MONITOR_LH1_8", - "MONITOR_LH1_9", - "MONITOR_LH2_0", - "MONITOR_LH2_1", - "MONITOR_LH2_2", - "MONITOR_LH2_3", - "MONITOR_LH2_4", - "MONITOR_LH2_5", - "MONITOR_LH2_6", - "MONITOR_LH2_7", - "MONITOR_LH2_8", - "MONITOR_LH2_9", - "MONITOR_LH3_0", - "MONITOR_LH3_1", - "MONITOR_LH3_2", - "MONITOR_LH3_3", - "MONITOR_LH3_4", - "MONITOR_LH3_5", - "MONITOR_LH3_6", - "MONITOR_LH3_7", - "MONITOR_LH3_8", - "MONITOR_LH3_9", - "MONITOR_LH4_0", - "MONITOR_LH4_1", - "MONITOR_LH4_2", - "MONITOR_LH4_3", - "MONITOR_LH4_4", - "MONITOR_LH4_5", - "MONITOR_LH4_6", - "MONITOR_LH4_7", - "MONITOR_LH4_8", - "MONITOR_LH4_9", - "MONITOR_LH5_0", - "MONITOR_LH5_1", - "MONITOR_LH5_2", - "MONITOR_LH5_3", - "MONITOR_LH5_4", - "MONITOR_LH5_5", - "MONITOR_LH5_6", - "MONITOR_LH5_7", - "MONITOR_LH5_8", - "MONITOR_LH5_9", - "MONITOR_LH6_0", - "MONITOR_LH6_1", - "MONITOR_LH6_2", - "MONITOR_LH6_3", - "MONITOR_LH6_4", - "MONITOR_LH6_5", - "MONITOR_LH6_6", - "MONITOR_LH6_7", - "MONITOR_LH6_8", - "MONITOR_LH6_9", - "MONITOR_LH7_0", - "MONITOR_LH7_1", - "MONITOR_LH7_2", - "MONITOR_LH7_3", - "MONITOR_LH7_4", - "MONITOR_LH7_5", - "MONITOR_LH7_6", - "MONITOR_LH7_7", - "MONITOR_LH7_8", - "MONITOR_LH7_9", - "MONITOR_LH8_0", - "MONITOR_LH8_1", - "MONITOR_LH8_2", - "MONITOR_LH8_3", - "MONITOR_LH8_4", - "MONITOR_LH8_5", - "MONITOR_LH8_6", - "MONITOR_LH8_7", - "MONITOR_LH8_8", - "MONITOR_LH8_9", - "MONITOR_LH9_0", - "MONITOR_LH9_1", - "MONITOR_LH9_2", - "MONITOR_LH9_3", - "MONITOR_LH9_4", - "MONITOR_LH9_5", - "MONITOR_LH9_6", - "MONITOR_LH9_7", - "MONITOR_LH9_8", - "MONITOR_LH9_9", - "MONITOR_LOGIC_OUTS_B0_0", - "MONITOR_LOGIC_OUTS_B0_1", - "MONITOR_LOGIC_OUTS_B0_2", - "MONITOR_LOGIC_OUTS_B0_3", - "MONITOR_LOGIC_OUTS_B0_4", - "MONITOR_LOGIC_OUTS_B0_5", - "MONITOR_LOGIC_OUTS_B0_6", - "MONITOR_LOGIC_OUTS_B0_7", - "MONITOR_LOGIC_OUTS_B0_8", - "MONITOR_LOGIC_OUTS_B0_9", - "MONITOR_LOGIC_OUTS_B10_0", - "MONITOR_LOGIC_OUTS_B10_1", - "MONITOR_LOGIC_OUTS_B10_2", - "MONITOR_LOGIC_OUTS_B10_3", - "MONITOR_LOGIC_OUTS_B10_4", - "MONITOR_LOGIC_OUTS_B10_5", - "MONITOR_LOGIC_OUTS_B10_6", - "MONITOR_LOGIC_OUTS_B10_7", - "MONITOR_LOGIC_OUTS_B10_8", - "MONITOR_LOGIC_OUTS_B10_9", - "MONITOR_LOGIC_OUTS_B11_0", - "MONITOR_LOGIC_OUTS_B11_1", - "MONITOR_LOGIC_OUTS_B11_2", - "MONITOR_LOGIC_OUTS_B11_3", - "MONITOR_LOGIC_OUTS_B11_4", - "MONITOR_LOGIC_OUTS_B11_5", - "MONITOR_LOGIC_OUTS_B11_6", - "MONITOR_LOGIC_OUTS_B11_7", - "MONITOR_LOGIC_OUTS_B11_8", - "MONITOR_LOGIC_OUTS_B11_9", - "MONITOR_LOGIC_OUTS_B12_0", - "MONITOR_LOGIC_OUTS_B12_1", - "MONITOR_LOGIC_OUTS_B12_2", - "MONITOR_LOGIC_OUTS_B12_3", - "MONITOR_LOGIC_OUTS_B12_4", - "MONITOR_LOGIC_OUTS_B12_5", - "MONITOR_LOGIC_OUTS_B12_6", - "MONITOR_LOGIC_OUTS_B12_7", - "MONITOR_LOGIC_OUTS_B12_8", - "MONITOR_LOGIC_OUTS_B12_9", - "MONITOR_LOGIC_OUTS_B13_0", - "MONITOR_LOGIC_OUTS_B13_1", - "MONITOR_LOGIC_OUTS_B13_2", - "MONITOR_LOGIC_OUTS_B13_3", - "MONITOR_LOGIC_OUTS_B13_4", - "MONITOR_LOGIC_OUTS_B13_5", - "MONITOR_LOGIC_OUTS_B13_6", - "MONITOR_LOGIC_OUTS_B13_7", - "MONITOR_LOGIC_OUTS_B13_8", - "MONITOR_LOGIC_OUTS_B13_9", - "MONITOR_LOGIC_OUTS_B14_0", - "MONITOR_LOGIC_OUTS_B14_1", - "MONITOR_LOGIC_OUTS_B14_2", - "MONITOR_LOGIC_OUTS_B14_3", - "MONITOR_LOGIC_OUTS_B14_4", - "MONITOR_LOGIC_OUTS_B14_5", - "MONITOR_LOGIC_OUTS_B14_6", - "MONITOR_LOGIC_OUTS_B14_7", - "MONITOR_LOGIC_OUTS_B14_8", - "MONITOR_LOGIC_OUTS_B14_9", - "MONITOR_LOGIC_OUTS_B15_0", - "MONITOR_LOGIC_OUTS_B15_1", - "MONITOR_LOGIC_OUTS_B15_2", - "MONITOR_LOGIC_OUTS_B15_3", - "MONITOR_LOGIC_OUTS_B15_4", - "MONITOR_LOGIC_OUTS_B15_5", - "MONITOR_LOGIC_OUTS_B15_6", - "MONITOR_LOGIC_OUTS_B15_7", - "MONITOR_LOGIC_OUTS_B15_8", - "MONITOR_LOGIC_OUTS_B15_9", - "MONITOR_LOGIC_OUTS_B16_0", - "MONITOR_LOGIC_OUTS_B16_1", - "MONITOR_LOGIC_OUTS_B16_2", - "MONITOR_LOGIC_OUTS_B16_3", - "MONITOR_LOGIC_OUTS_B16_4", - "MONITOR_LOGIC_OUTS_B16_5", - "MONITOR_LOGIC_OUTS_B16_6", - "MONITOR_LOGIC_OUTS_B16_7", - "MONITOR_LOGIC_OUTS_B16_8", - "MONITOR_LOGIC_OUTS_B16_9", - "MONITOR_LOGIC_OUTS_B17_0", - "MONITOR_LOGIC_OUTS_B17_1", - "MONITOR_LOGIC_OUTS_B17_2", - "MONITOR_LOGIC_OUTS_B17_3", - "MONITOR_LOGIC_OUTS_B17_4", - "MONITOR_LOGIC_OUTS_B17_5", - "MONITOR_LOGIC_OUTS_B17_6", - "MONITOR_LOGIC_OUTS_B17_7", - "MONITOR_LOGIC_OUTS_B17_8", - "MONITOR_LOGIC_OUTS_B17_9", - "MONITOR_LOGIC_OUTS_B18_0", - "MONITOR_LOGIC_OUTS_B18_1", - "MONITOR_LOGIC_OUTS_B18_2", - "MONITOR_LOGIC_OUTS_B18_3", - "MONITOR_LOGIC_OUTS_B18_4", - "MONITOR_LOGIC_OUTS_B18_5", - "MONITOR_LOGIC_OUTS_B18_6", - "MONITOR_LOGIC_OUTS_B18_7", - "MONITOR_LOGIC_OUTS_B18_8", - "MONITOR_LOGIC_OUTS_B18_9", - "MONITOR_LOGIC_OUTS_B19_0", - "MONITOR_LOGIC_OUTS_B19_1", - "MONITOR_LOGIC_OUTS_B19_2", - "MONITOR_LOGIC_OUTS_B19_3", - "MONITOR_LOGIC_OUTS_B19_4", - "MONITOR_LOGIC_OUTS_B19_5", - "MONITOR_LOGIC_OUTS_B19_6", - "MONITOR_LOGIC_OUTS_B19_7", - "MONITOR_LOGIC_OUTS_B19_8", - "MONITOR_LOGIC_OUTS_B19_9", - "MONITOR_LOGIC_OUTS_B1_0", - "MONITOR_LOGIC_OUTS_B1_1", - "MONITOR_LOGIC_OUTS_B1_2", - "MONITOR_LOGIC_OUTS_B1_3", - "MONITOR_LOGIC_OUTS_B1_4", - "MONITOR_LOGIC_OUTS_B1_5", - "MONITOR_LOGIC_OUTS_B1_6", - "MONITOR_LOGIC_OUTS_B1_7", - "MONITOR_LOGIC_OUTS_B1_8", - "MONITOR_LOGIC_OUTS_B1_9", - "MONITOR_LOGIC_OUTS_B20_0", - "MONITOR_LOGIC_OUTS_B20_1", - "MONITOR_LOGIC_OUTS_B20_2", - "MONITOR_LOGIC_OUTS_B20_3", - "MONITOR_LOGIC_OUTS_B20_4", - "MONITOR_LOGIC_OUTS_B20_5", - "MONITOR_LOGIC_OUTS_B20_6", - "MONITOR_LOGIC_OUTS_B20_7", - "MONITOR_LOGIC_OUTS_B20_8", - "MONITOR_LOGIC_OUTS_B20_9", - "MONITOR_LOGIC_OUTS_B21_0", - "MONITOR_LOGIC_OUTS_B21_1", - "MONITOR_LOGIC_OUTS_B21_2", - "MONITOR_LOGIC_OUTS_B21_3", - "MONITOR_LOGIC_OUTS_B21_4", - "MONITOR_LOGIC_OUTS_B21_5", - "MONITOR_LOGIC_OUTS_B21_6", - "MONITOR_LOGIC_OUTS_B21_7", - "MONITOR_LOGIC_OUTS_B21_8", - "MONITOR_LOGIC_OUTS_B21_9", - "MONITOR_LOGIC_OUTS_B22_0", - "MONITOR_LOGIC_OUTS_B22_1", - "MONITOR_LOGIC_OUTS_B22_2", - "MONITOR_LOGIC_OUTS_B22_3", - "MONITOR_LOGIC_OUTS_B22_4", - "MONITOR_LOGIC_OUTS_B22_5", - "MONITOR_LOGIC_OUTS_B22_6", - "MONITOR_LOGIC_OUTS_B22_7", - "MONITOR_LOGIC_OUTS_B22_8", - "MONITOR_LOGIC_OUTS_B22_9", - "MONITOR_LOGIC_OUTS_B23_0", - "MONITOR_LOGIC_OUTS_B23_1", - "MONITOR_LOGIC_OUTS_B23_2", - "MONITOR_LOGIC_OUTS_B23_3", - "MONITOR_LOGIC_OUTS_B23_4", - "MONITOR_LOGIC_OUTS_B23_5", - "MONITOR_LOGIC_OUTS_B23_6", - "MONITOR_LOGIC_OUTS_B23_7", - "MONITOR_LOGIC_OUTS_B23_8", - "MONITOR_LOGIC_OUTS_B23_9", - "MONITOR_LOGIC_OUTS_B2_0", - "MONITOR_LOGIC_OUTS_B2_1", - "MONITOR_LOGIC_OUTS_B2_2", - "MONITOR_LOGIC_OUTS_B2_3", - "MONITOR_LOGIC_OUTS_B2_4", - "MONITOR_LOGIC_OUTS_B2_5", - "MONITOR_LOGIC_OUTS_B2_6", - "MONITOR_LOGIC_OUTS_B2_7", - "MONITOR_LOGIC_OUTS_B2_8", - "MONITOR_LOGIC_OUTS_B2_9", - "MONITOR_LOGIC_OUTS_B3_0", - "MONITOR_LOGIC_OUTS_B3_1", - "MONITOR_LOGIC_OUTS_B3_2", - "MONITOR_LOGIC_OUTS_B3_3", - "MONITOR_LOGIC_OUTS_B3_4", - "MONITOR_LOGIC_OUTS_B3_5", - "MONITOR_LOGIC_OUTS_B3_6", - "MONITOR_LOGIC_OUTS_B3_7", - "MONITOR_LOGIC_OUTS_B3_8", - "MONITOR_LOGIC_OUTS_B3_9", - "MONITOR_LOGIC_OUTS_B4_0", - "MONITOR_LOGIC_OUTS_B4_1", - "MONITOR_LOGIC_OUTS_B4_2", - "MONITOR_LOGIC_OUTS_B4_3", - "MONITOR_LOGIC_OUTS_B4_4", - "MONITOR_LOGIC_OUTS_B4_5", - "MONITOR_LOGIC_OUTS_B4_6", - "MONITOR_LOGIC_OUTS_B4_7", - "MONITOR_LOGIC_OUTS_B4_8", - "MONITOR_LOGIC_OUTS_B4_9", - "MONITOR_LOGIC_OUTS_B5_0", - "MONITOR_LOGIC_OUTS_B5_1", - "MONITOR_LOGIC_OUTS_B5_2", - "MONITOR_LOGIC_OUTS_B5_3", - "MONITOR_LOGIC_OUTS_B5_4", - "MONITOR_LOGIC_OUTS_B5_5", - "MONITOR_LOGIC_OUTS_B5_6", - "MONITOR_LOGIC_OUTS_B5_7", - "MONITOR_LOGIC_OUTS_B5_8", - "MONITOR_LOGIC_OUTS_B5_9", - "MONITOR_LOGIC_OUTS_B6_0", - "MONITOR_LOGIC_OUTS_B6_1", - "MONITOR_LOGIC_OUTS_B6_2", - "MONITOR_LOGIC_OUTS_B6_3", - "MONITOR_LOGIC_OUTS_B6_4", - "MONITOR_LOGIC_OUTS_B6_5", - "MONITOR_LOGIC_OUTS_B6_6", - "MONITOR_LOGIC_OUTS_B6_7", - "MONITOR_LOGIC_OUTS_B6_8", - "MONITOR_LOGIC_OUTS_B6_9", - "MONITOR_LOGIC_OUTS_B7_0", - "MONITOR_LOGIC_OUTS_B7_1", - "MONITOR_LOGIC_OUTS_B7_2", - "MONITOR_LOGIC_OUTS_B7_3", - "MONITOR_LOGIC_OUTS_B7_4", - "MONITOR_LOGIC_OUTS_B7_5", - "MONITOR_LOGIC_OUTS_B7_6", - "MONITOR_LOGIC_OUTS_B7_7", - "MONITOR_LOGIC_OUTS_B7_8", - "MONITOR_LOGIC_OUTS_B7_9", - "MONITOR_LOGIC_OUTS_B8_0", - "MONITOR_LOGIC_OUTS_B8_1", - "MONITOR_LOGIC_OUTS_B8_2", - "MONITOR_LOGIC_OUTS_B8_3", - "MONITOR_LOGIC_OUTS_B8_4", - "MONITOR_LOGIC_OUTS_B8_5", - "MONITOR_LOGIC_OUTS_B8_6", - "MONITOR_LOGIC_OUTS_B8_7", - "MONITOR_LOGIC_OUTS_B8_8", - "MONITOR_LOGIC_OUTS_B8_9", - "MONITOR_LOGIC_OUTS_B9_0", - "MONITOR_LOGIC_OUTS_B9_1", - "MONITOR_LOGIC_OUTS_B9_2", - "MONITOR_LOGIC_OUTS_B9_3", - "MONITOR_LOGIC_OUTS_B9_4", - "MONITOR_LOGIC_OUTS_B9_5", - "MONITOR_LOGIC_OUTS_B9_6", - "MONITOR_LOGIC_OUTS_B9_7", - "MONITOR_LOGIC_OUTS_B9_8", - "MONITOR_LOGIC_OUTS_B9_9", - "MONITOR_MUXADDR0", - "MONITOR_MUXADDR1", - "MONITOR_MUXADDR2", - "MONITOR_MUXADDR3", - "MONITOR_MUXADDR4", - "MONITOR_NE2A0_0", - "MONITOR_NE2A0_1", - "MONITOR_NE2A0_2", - "MONITOR_NE2A0_3", - "MONITOR_NE2A0_4", - "MONITOR_NE2A0_5", - "MONITOR_NE2A0_6", - "MONITOR_NE2A0_7", - "MONITOR_NE2A0_8", - "MONITOR_NE2A0_9", - "MONITOR_NE2A1_0", - "MONITOR_NE2A1_1", - "MONITOR_NE2A1_2", - "MONITOR_NE2A1_3", - "MONITOR_NE2A1_4", - "MONITOR_NE2A1_5", - "MONITOR_NE2A1_6", - "MONITOR_NE2A1_7", - "MONITOR_NE2A1_8", - "MONITOR_NE2A1_9", - "MONITOR_NE2A2_0", - "MONITOR_NE2A2_1", - "MONITOR_NE2A2_2", - "MONITOR_NE2A2_3", - "MONITOR_NE2A2_4", - "MONITOR_NE2A2_5", - "MONITOR_NE2A2_6", - "MONITOR_NE2A2_7", - "MONITOR_NE2A2_8", - "MONITOR_NE2A2_9", - "MONITOR_NE2A3_0", - "MONITOR_NE2A3_1", - "MONITOR_NE2A3_2", - "MONITOR_NE2A3_3", - "MONITOR_NE2A3_4", - "MONITOR_NE2A3_5", - "MONITOR_NE2A3_6", - "MONITOR_NE2A3_7", - "MONITOR_NE2A3_8", - "MONITOR_NE2A3_9", - "MONITOR_NE4BEG0_0", - "MONITOR_NE4BEG0_1", - "MONITOR_NE4BEG0_2", - "MONITOR_NE4BEG0_3", - "MONITOR_NE4BEG0_4", - "MONITOR_NE4BEG0_5", - "MONITOR_NE4BEG0_6", - "MONITOR_NE4BEG0_7", - "MONITOR_NE4BEG0_8", - "MONITOR_NE4BEG0_9", - "MONITOR_NE4BEG1_0", - "MONITOR_NE4BEG1_1", - "MONITOR_NE4BEG1_2", - "MONITOR_NE4BEG1_3", - "MONITOR_NE4BEG1_4", - "MONITOR_NE4BEG1_5", - "MONITOR_NE4BEG1_6", - "MONITOR_NE4BEG1_7", - "MONITOR_NE4BEG1_8", - "MONITOR_NE4BEG1_9", - "MONITOR_NE4BEG2_0", - "MONITOR_NE4BEG2_1", - "MONITOR_NE4BEG2_2", - "MONITOR_NE4BEG2_3", - "MONITOR_NE4BEG2_4", - "MONITOR_NE4BEG2_5", - "MONITOR_NE4BEG2_6", - "MONITOR_NE4BEG2_7", - "MONITOR_NE4BEG2_8", - "MONITOR_NE4BEG2_9", - "MONITOR_NE4BEG3_0", - "MONITOR_NE4BEG3_1", - "MONITOR_NE4BEG3_2", - "MONITOR_NE4BEG3_3", - "MONITOR_NE4BEG3_4", - "MONITOR_NE4BEG3_5", - "MONITOR_NE4BEG3_6", - "MONITOR_NE4BEG3_7", - "MONITOR_NE4BEG3_8", - "MONITOR_NE4BEG3_9", - "MONITOR_NE4C0_0", - "MONITOR_NE4C0_1", - "MONITOR_NE4C0_2", - "MONITOR_NE4C0_3", - "MONITOR_NE4C0_4", - "MONITOR_NE4C0_5", - "MONITOR_NE4C0_6", - "MONITOR_NE4C0_7", - "MONITOR_NE4C0_8", - "MONITOR_NE4C0_9", - "MONITOR_NE4C1_0", - "MONITOR_NE4C1_1", - "MONITOR_NE4C1_2", - "MONITOR_NE4C1_3", - "MONITOR_NE4C1_4", - "MONITOR_NE4C1_5", - "MONITOR_NE4C1_6", - "MONITOR_NE4C1_7", - "MONITOR_NE4C1_8", - "MONITOR_NE4C1_9", - "MONITOR_NE4C2_0", - "MONITOR_NE4C2_1", - "MONITOR_NE4C2_2", - "MONITOR_NE4C2_3", - "MONITOR_NE4C2_4", - "MONITOR_NE4C2_5", - "MONITOR_NE4C2_6", - "MONITOR_NE4C2_7", - "MONITOR_NE4C2_8", - "MONITOR_NE4C2_9", - "MONITOR_NE4C3_0", - "MONITOR_NE4C3_1", - "MONITOR_NE4C3_2", - "MONITOR_NE4C3_3", - "MONITOR_NE4C3_4", - "MONITOR_NE4C3_5", - "MONITOR_NE4C3_6", - "MONITOR_NE4C3_7", - "MONITOR_NE4C3_8", - "MONITOR_NE4C3_9", - "MONITOR_NW2A0_0", - "MONITOR_NW2A0_1", - "MONITOR_NW2A0_2", - "MONITOR_NW2A0_3", - "MONITOR_NW2A0_4", - "MONITOR_NW2A0_5", - "MONITOR_NW2A0_6", - "MONITOR_NW2A0_7", - "MONITOR_NW2A0_8", - "MONITOR_NW2A0_9", - "MONITOR_NW2A1_0", - "MONITOR_NW2A1_1", - "MONITOR_NW2A1_2", - "MONITOR_NW2A1_3", - "MONITOR_NW2A1_4", - "MONITOR_NW2A1_5", - "MONITOR_NW2A1_6", - "MONITOR_NW2A1_7", - "MONITOR_NW2A1_8", - "MONITOR_NW2A1_9", - "MONITOR_NW2A2_0", - "MONITOR_NW2A2_1", - "MONITOR_NW2A2_2", - "MONITOR_NW2A2_3", - "MONITOR_NW2A2_4", - "MONITOR_NW2A2_5", - "MONITOR_NW2A2_6", - "MONITOR_NW2A2_7", - "MONITOR_NW2A2_8", - "MONITOR_NW2A2_9", - "MONITOR_NW2A3_0", - "MONITOR_NW2A3_1", - "MONITOR_NW2A3_2", - "MONITOR_NW2A3_3", - "MONITOR_NW2A3_4", - "MONITOR_NW2A3_5", - "MONITOR_NW2A3_6", - "MONITOR_NW2A3_7", - "MONITOR_NW2A3_8", - "MONITOR_NW2A3_9", - "MONITOR_NW4A0_0", - "MONITOR_NW4A0_1", - "MONITOR_NW4A0_2", - "MONITOR_NW4A0_3", - "MONITOR_NW4A0_4", - "MONITOR_NW4A0_5", - "MONITOR_NW4A0_6", - "MONITOR_NW4A0_7", - "MONITOR_NW4A0_8", - "MONITOR_NW4A0_9", - "MONITOR_NW4A1_0", - "MONITOR_NW4A1_1", - "MONITOR_NW4A1_2", - "MONITOR_NW4A1_3", - "MONITOR_NW4A1_4", - "MONITOR_NW4A1_5", - "MONITOR_NW4A1_6", - "MONITOR_NW4A1_7", - "MONITOR_NW4A1_8", - "MONITOR_NW4A1_9", - "MONITOR_NW4A2_0", - "MONITOR_NW4A2_1", - "MONITOR_NW4A2_2", - "MONITOR_NW4A2_3", - "MONITOR_NW4A2_4", - "MONITOR_NW4A2_5", - "MONITOR_NW4A2_6", - "MONITOR_NW4A2_7", - "MONITOR_NW4A2_8", - "MONITOR_NW4A2_9", - "MONITOR_NW4A3_0", - "MONITOR_NW4A3_1", - "MONITOR_NW4A3_2", - "MONITOR_NW4A3_3", - "MONITOR_NW4A3_4", - "MONITOR_NW4A3_5", - "MONITOR_NW4A3_6", - "MONITOR_NW4A3_7", - "MONITOR_NW4A3_8", - "MONITOR_NW4A3_9", - "MONITOR_NW4END0_0", - "MONITOR_NW4END0_1", - "MONITOR_NW4END0_2", - "MONITOR_NW4END0_3", - "MONITOR_NW4END0_4", - "MONITOR_NW4END0_5", - "MONITOR_NW4END0_6", - "MONITOR_NW4END0_7", - "MONITOR_NW4END0_8", - "MONITOR_NW4END0_9", - "MONITOR_NW4END1_0", - "MONITOR_NW4END1_1", - "MONITOR_NW4END1_2", - "MONITOR_NW4END1_3", - "MONITOR_NW4END1_4", - "MONITOR_NW4END1_5", - "MONITOR_NW4END1_6", - "MONITOR_NW4END1_7", - "MONITOR_NW4END1_8", - "MONITOR_NW4END1_9", - "MONITOR_NW4END2_0", - "MONITOR_NW4END2_1", - "MONITOR_NW4END2_2", - "MONITOR_NW4END2_3", - "MONITOR_NW4END2_4", - "MONITOR_NW4END2_5", - "MONITOR_NW4END2_6", - "MONITOR_NW4END2_7", - "MONITOR_NW4END2_8", - "MONITOR_NW4END2_9", - "MONITOR_NW4END3_0", - "MONITOR_NW4END3_1", - "MONITOR_NW4END3_2", - "MONITOR_NW4END3_3", - "MONITOR_NW4END3_4", - "MONITOR_NW4END3_5", - "MONITOR_NW4END3_6", - "MONITOR_NW4END3_7", - "MONITOR_NW4END3_8", - "MONITOR_NW4END3_9", - "MONITOR_OT", - "MONITOR_RESET", - "MONITOR_SE2A0_0", - "MONITOR_SE2A0_1", - "MONITOR_SE2A0_2", - "MONITOR_SE2A0_3", - "MONITOR_SE2A0_4", - "MONITOR_SE2A0_5", - "MONITOR_SE2A0_6", - "MONITOR_SE2A0_7", - "MONITOR_SE2A0_8", - "MONITOR_SE2A0_9", - "MONITOR_SE2A1_0", - "MONITOR_SE2A1_1", - "MONITOR_SE2A1_2", - "MONITOR_SE2A1_3", - "MONITOR_SE2A1_4", - "MONITOR_SE2A1_5", - "MONITOR_SE2A1_6", - "MONITOR_SE2A1_7", - "MONITOR_SE2A1_8", - "MONITOR_SE2A1_9", - "MONITOR_SE2A2_0", - "MONITOR_SE2A2_1", - "MONITOR_SE2A2_2", - "MONITOR_SE2A2_3", - "MONITOR_SE2A2_4", - "MONITOR_SE2A2_5", - "MONITOR_SE2A2_6", - "MONITOR_SE2A2_7", - "MONITOR_SE2A2_8", - "MONITOR_SE2A2_9", - "MONITOR_SE2A3_0", - "MONITOR_SE2A3_1", - "MONITOR_SE2A3_2", - "MONITOR_SE2A3_3", - "MONITOR_SE2A3_4", - "MONITOR_SE2A3_5", - "MONITOR_SE2A3_6", - "MONITOR_SE2A3_7", - "MONITOR_SE2A3_8", - "MONITOR_SE2A3_9", - "MONITOR_SE4BEG0_0", - "MONITOR_SE4BEG0_1", - "MONITOR_SE4BEG0_2", - "MONITOR_SE4BEG0_3", - "MONITOR_SE4BEG0_4", - "MONITOR_SE4BEG0_5", - "MONITOR_SE4BEG0_6", - "MONITOR_SE4BEG0_7", - "MONITOR_SE4BEG0_8", - "MONITOR_SE4BEG0_9", - "MONITOR_SE4BEG1_0", - "MONITOR_SE4BEG1_1", - "MONITOR_SE4BEG1_2", - "MONITOR_SE4BEG1_3", - "MONITOR_SE4BEG1_4", - "MONITOR_SE4BEG1_5", - "MONITOR_SE4BEG1_6", - "MONITOR_SE4BEG1_7", - "MONITOR_SE4BEG1_8", - "MONITOR_SE4BEG1_9", - "MONITOR_SE4BEG2_0", - "MONITOR_SE4BEG2_1", - "MONITOR_SE4BEG2_2", - "MONITOR_SE4BEG2_3", - "MONITOR_SE4BEG2_4", - "MONITOR_SE4BEG2_5", - "MONITOR_SE4BEG2_6", - "MONITOR_SE4BEG2_7", - "MONITOR_SE4BEG2_8", - "MONITOR_SE4BEG2_9", - "MONITOR_SE4BEG3_0", - "MONITOR_SE4BEG3_1", - "MONITOR_SE4BEG3_2", - "MONITOR_SE4BEG3_3", - "MONITOR_SE4BEG3_4", - "MONITOR_SE4BEG3_5", - "MONITOR_SE4BEG3_6", - "MONITOR_SE4BEG3_7", - "MONITOR_SE4BEG3_8", - "MONITOR_SE4BEG3_9", - "MONITOR_SE4C0_0", - "MONITOR_SE4C0_1", - "MONITOR_SE4C0_2", - "MONITOR_SE4C0_3", - "MONITOR_SE4C0_4", - "MONITOR_SE4C0_5", - "MONITOR_SE4C0_6", - "MONITOR_SE4C0_7", - "MONITOR_SE4C0_8", - "MONITOR_SE4C0_9", - "MONITOR_SE4C1_0", - "MONITOR_SE4C1_1", - "MONITOR_SE4C1_2", - "MONITOR_SE4C1_3", - "MONITOR_SE4C1_4", - "MONITOR_SE4C1_5", - "MONITOR_SE4C1_6", - "MONITOR_SE4C1_7", - "MONITOR_SE4C1_8", - "MONITOR_SE4C1_9", - "MONITOR_SE4C2_0", - "MONITOR_SE4C2_1", - "MONITOR_SE4C2_2", - "MONITOR_SE4C2_3", - "MONITOR_SE4C2_4", - "MONITOR_SE4C2_5", - "MONITOR_SE4C2_6", - "MONITOR_SE4C2_7", - "MONITOR_SE4C2_8", - "MONITOR_SE4C2_9", - "MONITOR_SE4C3_0", - "MONITOR_SE4C3_1", - "MONITOR_SE4C3_2", - "MONITOR_SE4C3_3", - "MONITOR_SE4C3_4", - "MONITOR_SE4C3_5", - "MONITOR_SE4C3_6", - "MONITOR_SE4C3_7", - "MONITOR_SE4C3_8", - "MONITOR_SE4C3_9", - "MONITOR_SEG_VN", - "MONITOR_SEG_VP", - "MONITOR_SW2A0_0", - "MONITOR_SW2A0_1", - "MONITOR_SW2A0_2", - "MONITOR_SW2A0_3", - "MONITOR_SW2A0_4", - "MONITOR_SW2A0_5", - "MONITOR_SW2A0_6", - "MONITOR_SW2A0_7", - "MONITOR_SW2A0_8", - "MONITOR_SW2A0_9", - "MONITOR_SW2A1_0", - "MONITOR_SW2A1_1", - "MONITOR_SW2A1_2", - "MONITOR_SW2A1_3", - "MONITOR_SW2A1_4", - "MONITOR_SW2A1_5", - "MONITOR_SW2A1_6", - "MONITOR_SW2A1_7", - "MONITOR_SW2A1_8", - "MONITOR_SW2A1_9", - "MONITOR_SW2A2_0", - "MONITOR_SW2A2_1", - "MONITOR_SW2A2_2", - "MONITOR_SW2A2_3", - "MONITOR_SW2A2_4", - "MONITOR_SW2A2_5", - "MONITOR_SW2A2_6", - "MONITOR_SW2A2_7", - "MONITOR_SW2A2_8", - "MONITOR_SW2A2_9", - "MONITOR_SW2A3_0", - "MONITOR_SW2A3_1", - "MONITOR_SW2A3_2", - "MONITOR_SW2A3_3", - "MONITOR_SW2A3_4", - "MONITOR_SW2A3_5", - "MONITOR_SW2A3_6", - "MONITOR_SW2A3_7", - "MONITOR_SW2A3_8", - "MONITOR_SW2A3_9", - "MONITOR_SW4A0_0", - "MONITOR_SW4A0_1", - "MONITOR_SW4A0_2", - "MONITOR_SW4A0_3", - "MONITOR_SW4A0_4", - "MONITOR_SW4A0_5", - "MONITOR_SW4A0_6", - "MONITOR_SW4A0_7", - "MONITOR_SW4A0_8", - "MONITOR_SW4A0_9", - "MONITOR_SW4A1_0", - "MONITOR_SW4A1_1", - "MONITOR_SW4A1_2", - "MONITOR_SW4A1_3", - "MONITOR_SW4A1_4", - "MONITOR_SW4A1_5", - "MONITOR_SW4A1_6", - "MONITOR_SW4A1_7", - "MONITOR_SW4A1_8", - "MONITOR_SW4A1_9", - "MONITOR_SW4A2_0", - "MONITOR_SW4A2_1", - "MONITOR_SW4A2_2", - "MONITOR_SW4A2_3", - "MONITOR_SW4A2_4", - "MONITOR_SW4A2_5", - "MONITOR_SW4A2_6", - "MONITOR_SW4A2_7", - "MONITOR_SW4A2_8", - "MONITOR_SW4A2_9", - "MONITOR_SW4A3_0", - "MONITOR_SW4A3_1", - "MONITOR_SW4A3_2", - "MONITOR_SW4A3_3", - "MONITOR_SW4A3_4", - "MONITOR_SW4A3_5", - "MONITOR_SW4A3_6", - "MONITOR_SW4A3_7", - "MONITOR_SW4A3_8", - "MONITOR_SW4A3_9", - "MONITOR_SW4END0_0", - "MONITOR_SW4END0_1", - "MONITOR_SW4END0_2", - "MONITOR_SW4END0_3", - "MONITOR_SW4END0_4", - "MONITOR_SW4END0_5", - "MONITOR_SW4END0_6", - "MONITOR_SW4END0_7", - "MONITOR_SW4END0_8", - "MONITOR_SW4END0_9", - "MONITOR_SW4END1_0", - "MONITOR_SW4END1_1", - "MONITOR_SW4END1_2", - "MONITOR_SW4END1_3", - "MONITOR_SW4END1_4", - "MONITOR_SW4END1_5", - "MONITOR_SW4END1_6", - "MONITOR_SW4END1_7", - "MONITOR_SW4END1_8", - "MONITOR_SW4END1_9", - "MONITOR_SW4END2_0", - "MONITOR_SW4END2_1", - "MONITOR_SW4END2_2", - "MONITOR_SW4END2_3", - "MONITOR_SW4END2_4", - "MONITOR_SW4END2_5", - "MONITOR_SW4END2_6", - "MONITOR_SW4END2_7", - "MONITOR_SW4END2_8", - "MONITOR_SW4END2_9", - "MONITOR_SW4END3_0", - "MONITOR_SW4END3_1", - "MONITOR_SW4END3_2", - "MONITOR_SW4END3_3", - "MONITOR_SW4END3_4", - "MONITOR_SW4END3_5", - "MONITOR_SW4END3_6", - "MONITOR_SW4END3_7", - "MONITOR_SW4END3_8", - "MONITOR_SW4END3_9", - "MONITOR_TESTADCCLK0", - "MONITOR_TESTADCCLK1", - "MONITOR_TESTADCCLK2", - "MONITOR_TESTADCCLK3", - "MONITOR_TESTADCIN0", - "MONITOR_TESTADCIN1", - "MONITOR_TESTADCIN10", - "MONITOR_TESTADCIN11", - "MONITOR_TESTADCIN12", - "MONITOR_TESTADCIN13", - "MONITOR_TESTADCIN14", - "MONITOR_TESTADCIN15", - "MONITOR_TESTADCIN16", - "MONITOR_TESTADCIN17", - "MONITOR_TESTADCIN18", - "MONITOR_TESTADCIN19", - "MONITOR_TESTADCIN2", - "MONITOR_TESTADCIN20", - "MONITOR_TESTADCIN21", - "MONITOR_TESTADCIN210", - "MONITOR_TESTADCIN211", - "MONITOR_TESTADCIN212", - "MONITOR_TESTADCIN213", - "MONITOR_TESTADCIN214", - "MONITOR_TESTADCIN215", - "MONITOR_TESTADCIN216", - "MONITOR_TESTADCIN217", - "MONITOR_TESTADCIN218", - "MONITOR_TESTADCIN219", - "MONITOR_TESTADCIN22", - "MONITOR_TESTADCIN23", - "MONITOR_TESTADCIN24", - "MONITOR_TESTADCIN25", - "MONITOR_TESTADCIN26", - "MONITOR_TESTADCIN27", - "MONITOR_TESTADCIN28", - "MONITOR_TESTADCIN29", - "MONITOR_TESTADCIN3", - "MONITOR_TESTADCIN4", - "MONITOR_TESTADCIN5", - "MONITOR_TESTADCIN6", - "MONITOR_TESTADCIN7", - "MONITOR_TESTADCIN8", - "MONITOR_TESTADCIN9", - "MONITOR_TESTADCOUT0", - "MONITOR_TESTADCOUT1", - "MONITOR_TESTADCOUT10", - "MONITOR_TESTADCOUT11", - "MONITOR_TESTADCOUT12", - "MONITOR_TESTADCOUT13", - "MONITOR_TESTADCOUT14", - "MONITOR_TESTADCOUT15", - "MONITOR_TESTADCOUT16", - "MONITOR_TESTADCOUT17", - "MONITOR_TESTADCOUT18", - "MONITOR_TESTADCOUT19", - "MONITOR_TESTADCOUT2", - "MONITOR_TESTADCOUT3", - "MONITOR_TESTADCOUT4", - "MONITOR_TESTADCOUT5", - "MONITOR_TESTADCOUT6", - "MONITOR_TESTADCOUT7", - "MONITOR_TESTADCOUT8", - "MONITOR_TESTADCOUT9", - "MONITOR_TESTCAPTURE", - "MONITOR_TESTDB0", - "MONITOR_TESTDB1", - "MONITOR_TESTDB10", - "MONITOR_TESTDB11", - "MONITOR_TESTDB12", - "MONITOR_TESTDB13", - "MONITOR_TESTDB14", - "MONITOR_TESTDB15", - "MONITOR_TESTDB2", - "MONITOR_TESTDB3", - "MONITOR_TESTDB4", - "MONITOR_TESTDB5", - "MONITOR_TESTDB6", - "MONITOR_TESTDB7", - "MONITOR_TESTDB8", - "MONITOR_TESTDB9", - "MONITOR_TESTDRCK", - "MONITOR_TESTENJTAG", - "MONITOR_TESTRST", - "MONITOR_TESTSCANCLK0", - "MONITOR_TESTSCANCLK1", - "MONITOR_TESTSCANCLK2", - "MONITOR_TESTSCANCLK3", - "MONITOR_TESTSCANCLK4", - "MONITOR_TESTSCANMODE0", - "MONITOR_TESTSCANMODE1", - "MONITOR_TESTSCANMODE2", - "MONITOR_TESTSCANMODE3", - "MONITOR_TESTSCANMODE4", - "MONITOR_TESTSCANRESET", - "MONITOR_TESTSE0", - "MONITOR_TESTSE1", - "MONITOR_TESTSE2", - "MONITOR_TESTSE3", - "MONITOR_TESTSE4", - "MONITOR_TESTSEL", - "MONITOR_TESTSHIFT", - "MONITOR_TESTSI0", - "MONITOR_TESTSI1", - "MONITOR_TESTSI2", - "MONITOR_TESTSI3", - "MONITOR_TESTSI4", - "MONITOR_TESTSO0", - "MONITOR_TESTSO1", - "MONITOR_TESTSO2", - "MONITOR_TESTSO3", - "MONITOR_TESTSO4", - "MONITOR_TESTTDI", - "MONITOR_TESTTDO", - "MONITOR_TESTUPDATE", - "MONITOR_VAUXN0", - "MONITOR_VAUXN1", - "MONITOR_VAUXN10", - "MONITOR_VAUXN11", - "MONITOR_VAUXN12", - "MONITOR_VAUXN13", - "MONITOR_VAUXN14", - "MONITOR_VAUXN15", - "MONITOR_VAUXN2", - "MONITOR_VAUXN3", - "MONITOR_VAUXN4", - "MONITOR_VAUXN5", - "MONITOR_VAUXN6", - "MONITOR_VAUXN7", - "MONITOR_VAUXN8", - "MONITOR_VAUXN9", - "MONITOR_VAUXP0", - "MONITOR_VAUXP1", - "MONITOR_VAUXP10", - "MONITOR_VAUXP11", - "MONITOR_VAUXP12", - "MONITOR_VAUXP13", - "MONITOR_VAUXP14", - "MONITOR_VAUXP15", - "MONITOR_VAUXP2", - "MONITOR_VAUXP3", - "MONITOR_VAUXP4", - "MONITOR_VAUXP5", - "MONITOR_VAUXP6", - "MONITOR_VAUXP7", - "MONITOR_VAUXP8", - "MONITOR_VAUXP9", - "MONITOR_VERT_VAUXN0", - "MONITOR_VERT_VAUXN1", - "MONITOR_VERT_VAUXN10", - "MONITOR_VERT_VAUXN11", - "MONITOR_VERT_VAUXN12", - "MONITOR_VERT_VAUXN13", - "MONITOR_VERT_VAUXN14", - "MONITOR_VERT_VAUXN15", - "MONITOR_VERT_VAUXN2", - "MONITOR_VERT_VAUXN3", - "MONITOR_VERT_VAUXN4", - "MONITOR_VERT_VAUXN5", - "MONITOR_VERT_VAUXN6", - "MONITOR_VERT_VAUXN7", - "MONITOR_VERT_VAUXN8", - "MONITOR_VERT_VAUXN9", - "MONITOR_VERT_VAUXP0", - "MONITOR_VERT_VAUXP1", - "MONITOR_VERT_VAUXP10", - "MONITOR_VERT_VAUXP11", - "MONITOR_VERT_VAUXP12", - "MONITOR_VERT_VAUXP13", - "MONITOR_VERT_VAUXP14", - "MONITOR_VERT_VAUXP15", - "MONITOR_VERT_VAUXP2", - "MONITOR_VERT_VAUXP3", - "MONITOR_VERT_VAUXP4", - "MONITOR_VERT_VAUXP5", - "MONITOR_VERT_VAUXP6", - "MONITOR_VERT_VAUXP7", - "MONITOR_VERT_VAUXP8", - "MONITOR_VERT_VAUXP9", - "MONITOR_VN", - "MONITOR_VP", - "MONITOR_WL1END0_0", - "MONITOR_WL1END0_1", - "MONITOR_WL1END0_2", - "MONITOR_WL1END0_3", - "MONITOR_WL1END0_4", - "MONITOR_WL1END0_5", - "MONITOR_WL1END0_6", - "MONITOR_WL1END0_7", - "MONITOR_WL1END0_8", - "MONITOR_WL1END0_9", - "MONITOR_WL1END1_0", - "MONITOR_WL1END1_1", - "MONITOR_WL1END1_2", - "MONITOR_WL1END1_3", - "MONITOR_WL1END1_4", - "MONITOR_WL1END1_5", - "MONITOR_WL1END1_6", - "MONITOR_WL1END1_7", - "MONITOR_WL1END1_8", - "MONITOR_WL1END1_9", - "MONITOR_WL1END2_0", - "MONITOR_WL1END2_1", - "MONITOR_WL1END2_2", - "MONITOR_WL1END2_3", - "MONITOR_WL1END2_4", - "MONITOR_WL1END2_5", - "MONITOR_WL1END2_6", - "MONITOR_WL1END2_7", - "MONITOR_WL1END2_8", - "MONITOR_WL1END2_9", - "MONITOR_WL1END3_0", - "MONITOR_WL1END3_1", - "MONITOR_WL1END3_2", - "MONITOR_WL1END3_3", - "MONITOR_WL1END3_4", - "MONITOR_WL1END3_5", - "MONITOR_WL1END3_6", - "MONITOR_WL1END3_7", - "MONITOR_WL1END3_8", - "MONITOR_WL1END3_9", - "MONITOR_WR1END0_0", - "MONITOR_WR1END0_1", - "MONITOR_WR1END0_2", - "MONITOR_WR1END0_3", - "MONITOR_WR1END0_4", - "MONITOR_WR1END0_5", - "MONITOR_WR1END0_6", - "MONITOR_WR1END0_7", - "MONITOR_WR1END0_8", - "MONITOR_WR1END0_9", - "MONITOR_WR1END1_0", - "MONITOR_WR1END1_1", - "MONITOR_WR1END1_2", - "MONITOR_WR1END1_3", - "MONITOR_WR1END1_4", - "MONITOR_WR1END1_5", - "MONITOR_WR1END1_6", - "MONITOR_WR1END1_7", - "MONITOR_WR1END1_8", - "MONITOR_WR1END1_9", - "MONITOR_WR1END2_0", - "MONITOR_WR1END2_1", - "MONITOR_WR1END2_2", - "MONITOR_WR1END2_3", - "MONITOR_WR1END2_4", - "MONITOR_WR1END2_5", - "MONITOR_WR1END2_6", - "MONITOR_WR1END2_7", - "MONITOR_WR1END2_8", - "MONITOR_WR1END2_9", - "MONITOR_WR1END3_0", - "MONITOR_WR1END3_1", - "MONITOR_WR1END3_2", - "MONITOR_WR1END3_3", - "MONITOR_WR1END3_4", - "MONITOR_WR1END3_5", - "MONITOR_WR1END3_6", - "MONITOR_WR1END3_7", - "MONITOR_WR1END3_8", - "MONITOR_WR1END3_9", - "MONITOR_WW2A0_0", - "MONITOR_WW2A0_1", - "MONITOR_WW2A0_2", - "MONITOR_WW2A0_3", - "MONITOR_WW2A0_4", - "MONITOR_WW2A0_5", - "MONITOR_WW2A0_6", - "MONITOR_WW2A0_7", - "MONITOR_WW2A0_8", - "MONITOR_WW2A0_9", - "MONITOR_WW2A1_0", - "MONITOR_WW2A1_1", - "MONITOR_WW2A1_2", - "MONITOR_WW2A1_3", - "MONITOR_WW2A1_4", - "MONITOR_WW2A1_5", - "MONITOR_WW2A1_6", - "MONITOR_WW2A1_7", - "MONITOR_WW2A1_8", - "MONITOR_WW2A1_9", - "MONITOR_WW2A2_0", - "MONITOR_WW2A2_1", - "MONITOR_WW2A2_2", - "MONITOR_WW2A2_3", - "MONITOR_WW2A2_4", - "MONITOR_WW2A2_5", - "MONITOR_WW2A2_6", - "MONITOR_WW2A2_7", - "MONITOR_WW2A2_8", - "MONITOR_WW2A2_9", - "MONITOR_WW2A3_0", - "MONITOR_WW2A3_1", - "MONITOR_WW2A3_2", - "MONITOR_WW2A3_3", - "MONITOR_WW2A3_4", - "MONITOR_WW2A3_5", - "MONITOR_WW2A3_6", - "MONITOR_WW2A3_7", - "MONITOR_WW2A3_8", - "MONITOR_WW2A3_9", - "MONITOR_WW2END0_0", - "MONITOR_WW2END0_1", - "MONITOR_WW2END0_2", - "MONITOR_WW2END0_3", - "MONITOR_WW2END0_4", - "MONITOR_WW2END0_5", - "MONITOR_WW2END0_6", - "MONITOR_WW2END0_7", - "MONITOR_WW2END0_8", - "MONITOR_WW2END0_9", - "MONITOR_WW2END1_0", - "MONITOR_WW2END1_1", - "MONITOR_WW2END1_2", - "MONITOR_WW2END1_3", - "MONITOR_WW2END1_4", - "MONITOR_WW2END1_5", - "MONITOR_WW2END1_6", - "MONITOR_WW2END1_7", - "MONITOR_WW2END1_8", - "MONITOR_WW2END1_9", - "MONITOR_WW2END2_0", - "MONITOR_WW2END2_1", - "MONITOR_WW2END2_2", - "MONITOR_WW2END2_3", - "MONITOR_WW2END2_4", - "MONITOR_WW2END2_5", - "MONITOR_WW2END2_6", - "MONITOR_WW2END2_7", - "MONITOR_WW2END2_8", - "MONITOR_WW2END2_9", - "MONITOR_WW2END3_0", - "MONITOR_WW2END3_1", - "MONITOR_WW2END3_2", - "MONITOR_WW2END3_3", - "MONITOR_WW2END3_4", - "MONITOR_WW2END3_5", - "MONITOR_WW2END3_6", - "MONITOR_WW2END3_7", - "MONITOR_WW2END3_8", - "MONITOR_WW2END3_9", - "MONITOR_WW4A0_0", - "MONITOR_WW4A0_1", - "MONITOR_WW4A0_2", - "MONITOR_WW4A0_3", - "MONITOR_WW4A0_4", - "MONITOR_WW4A0_5", - "MONITOR_WW4A0_6", - "MONITOR_WW4A0_7", - "MONITOR_WW4A0_8", - "MONITOR_WW4A0_9", - "MONITOR_WW4A1_0", - "MONITOR_WW4A1_1", - "MONITOR_WW4A1_2", - "MONITOR_WW4A1_3", - "MONITOR_WW4A1_4", - "MONITOR_WW4A1_5", - "MONITOR_WW4A1_6", - "MONITOR_WW4A1_7", - "MONITOR_WW4A1_8", - "MONITOR_WW4A1_9", - "MONITOR_WW4A2_0", - "MONITOR_WW4A2_1", - "MONITOR_WW4A2_2", - "MONITOR_WW4A2_3", - "MONITOR_WW4A2_4", - "MONITOR_WW4A2_5", - "MONITOR_WW4A2_6", - "MONITOR_WW4A2_7", - "MONITOR_WW4A2_8", - "MONITOR_WW4A2_9", - "MONITOR_WW4A3_0", - "MONITOR_WW4A3_1", - "MONITOR_WW4A3_2", - "MONITOR_WW4A3_3", - "MONITOR_WW4A3_4", - "MONITOR_WW4A3_5", - "MONITOR_WW4A3_6", - "MONITOR_WW4A3_7", - "MONITOR_WW4A3_8", - "MONITOR_WW4A3_9", - "MONITOR_WW4B0_0", - "MONITOR_WW4B0_1", - "MONITOR_WW4B0_2", - "MONITOR_WW4B0_3", - "MONITOR_WW4B0_4", - "MONITOR_WW4B0_5", - "MONITOR_WW4B0_6", - "MONITOR_WW4B0_7", - "MONITOR_WW4B0_8", - "MONITOR_WW4B0_9", - "MONITOR_WW4B1_0", - "MONITOR_WW4B1_1", - "MONITOR_WW4B1_2", - "MONITOR_WW4B1_3", - "MONITOR_WW4B1_4", - "MONITOR_WW4B1_5", - "MONITOR_WW4B1_6", - "MONITOR_WW4B1_7", - "MONITOR_WW4B1_8", - "MONITOR_WW4B1_9", - "MONITOR_WW4B2_0", - "MONITOR_WW4B2_1", - "MONITOR_WW4B2_2", - "MONITOR_WW4B2_3", - "MONITOR_WW4B2_4", - "MONITOR_WW4B2_5", - "MONITOR_WW4B2_6", - "MONITOR_WW4B2_7", - "MONITOR_WW4B2_8", - "MONITOR_WW4B2_9", - "MONITOR_WW4B3_0", - "MONITOR_WW4B3_1", - "MONITOR_WW4B3_2", - "MONITOR_WW4B3_3", - "MONITOR_WW4B3_4", - "MONITOR_WW4B3_5", - "MONITOR_WW4B3_6", - "MONITOR_WW4B3_7", - "MONITOR_WW4B3_8", - "MONITOR_WW4B3_9", - "MONITOR_WW4C0_0", - "MONITOR_WW4C0_1", - "MONITOR_WW4C0_2", - "MONITOR_WW4C0_3", - "MONITOR_WW4C0_4", - "MONITOR_WW4C0_5", - "MONITOR_WW4C0_6", - "MONITOR_WW4C0_7", - "MONITOR_WW4C0_8", - "MONITOR_WW4C0_9", - "MONITOR_WW4C1_0", - "MONITOR_WW4C1_1", - "MONITOR_WW4C1_2", - "MONITOR_WW4C1_3", - "MONITOR_WW4C1_4", - "MONITOR_WW4C1_5", - "MONITOR_WW4C1_6", - "MONITOR_WW4C1_7", - "MONITOR_WW4C1_8", - "MONITOR_WW4C1_9", - "MONITOR_WW4C2_0", - "MONITOR_WW4C2_1", - "MONITOR_WW4C2_2", - "MONITOR_WW4C2_3", - "MONITOR_WW4C2_4", - "MONITOR_WW4C2_5", - "MONITOR_WW4C2_6", - "MONITOR_WW4C2_7", - "MONITOR_WW4C2_8", - "MONITOR_WW4C2_9", - "MONITOR_WW4C3_0", - "MONITOR_WW4C3_1", - "MONITOR_WW4C3_2", - "MONITOR_WW4C3_3", - "MONITOR_WW4C3_4", - "MONITOR_WW4C3_5", - "MONITOR_WW4C3_6", - "MONITOR_WW4C3_7", - "MONITOR_WW4C3_8", - "MONITOR_WW4C3_9", - "MONITOR_WW4END0_0", - "MONITOR_WW4END0_1", - "MONITOR_WW4END0_2", - "MONITOR_WW4END0_3", - "MONITOR_WW4END0_4", - "MONITOR_WW4END0_5", - "MONITOR_WW4END0_6", - "MONITOR_WW4END0_7", - "MONITOR_WW4END0_8", - "MONITOR_WW4END0_9", - "MONITOR_WW4END1_0", - "MONITOR_WW4END1_1", - "MONITOR_WW4END1_2", - "MONITOR_WW4END1_3", - "MONITOR_WW4END1_4", - "MONITOR_WW4END1_5", - "MONITOR_WW4END1_6", - "MONITOR_WW4END1_7", - "MONITOR_WW4END1_8", - "MONITOR_WW4END1_9", - "MONITOR_WW4END2_0", - "MONITOR_WW4END2_1", - "MONITOR_WW4END2_2", - "MONITOR_WW4END2_3", - "MONITOR_WW4END2_4", - "MONITOR_WW4END2_5", - "MONITOR_WW4END2_6", - "MONITOR_WW4END2_7", - "MONITOR_WW4END2_8", - "MONITOR_WW4END2_9", - "MONITOR_WW4END3_0", - "MONITOR_WW4END3_1", - "MONITOR_WW4END3_2", - "MONITOR_WW4END3_3", - "MONITOR_WW4END3_4", - "MONITOR_WW4END3_5", - "MONITOR_WW4END3_6", - "MONITOR_WW4END3_7", - "MONITOR_WW4END3_8", - "MONITOR_WW4END3_9" - ] + "wires": { + "MONITOR_ALM0": null, + "MONITOR_ALM1": null, + "MONITOR_ALM2": null, + "MONITOR_ALM3": null, + "MONITOR_ALM4": null, + "MONITOR_ALM5": null, + "MONITOR_ALM6": null, + "MONITOR_ALM7": null, + "MONITOR_BLOCK_OUTS_B0_0": null, + "MONITOR_BLOCK_OUTS_B0_1": null, + "MONITOR_BLOCK_OUTS_B0_2": null, + "MONITOR_BLOCK_OUTS_B0_3": null, + "MONITOR_BLOCK_OUTS_B0_4": null, + "MONITOR_BLOCK_OUTS_B0_5": null, + "MONITOR_BLOCK_OUTS_B0_6": null, + "MONITOR_BLOCK_OUTS_B0_7": null, + "MONITOR_BLOCK_OUTS_B0_8": null, + "MONITOR_BLOCK_OUTS_B0_9": null, + "MONITOR_BLOCK_OUTS_B1_0": null, + "MONITOR_BLOCK_OUTS_B1_1": null, + "MONITOR_BLOCK_OUTS_B1_2": null, + "MONITOR_BLOCK_OUTS_B1_3": null, + "MONITOR_BLOCK_OUTS_B1_4": null, + "MONITOR_BLOCK_OUTS_B1_5": null, + "MONITOR_BLOCK_OUTS_B1_6": null, + "MONITOR_BLOCK_OUTS_B1_7": null, + "MONITOR_BLOCK_OUTS_B1_8": null, + "MONITOR_BLOCK_OUTS_B1_9": null, + "MONITOR_BLOCK_OUTS_B2_0": null, + "MONITOR_BLOCK_OUTS_B2_1": null, + "MONITOR_BLOCK_OUTS_B2_2": null, + "MONITOR_BLOCK_OUTS_B2_3": null, + "MONITOR_BLOCK_OUTS_B2_4": null, + "MONITOR_BLOCK_OUTS_B2_5": null, + "MONITOR_BLOCK_OUTS_B2_6": null, + "MONITOR_BLOCK_OUTS_B2_7": null, + "MONITOR_BLOCK_OUTS_B2_8": null, + "MONITOR_BLOCK_OUTS_B2_9": null, + "MONITOR_BLOCK_OUTS_B3_0": null, + "MONITOR_BLOCK_OUTS_B3_1": null, + "MONITOR_BLOCK_OUTS_B3_2": null, + "MONITOR_BLOCK_OUTS_B3_3": null, + "MONITOR_BLOCK_OUTS_B3_4": null, + "MONITOR_BLOCK_OUTS_B3_5": null, + "MONITOR_BLOCK_OUTS_B3_6": null, + "MONITOR_BLOCK_OUTS_B3_7": null, + "MONITOR_BLOCK_OUTS_B3_8": null, + "MONITOR_BLOCK_OUTS_B3_9": null, + "MONITOR_BUSY": null, + "MONITOR_BYP0_0": null, + "MONITOR_BYP0_1": null, + "MONITOR_BYP0_2": null, + "MONITOR_BYP0_3": null, + "MONITOR_BYP0_4": null, + "MONITOR_BYP0_5": null, + "MONITOR_BYP0_6": null, + "MONITOR_BYP0_7": null, + "MONITOR_BYP0_8": null, + "MONITOR_BYP0_9": null, + "MONITOR_BYP1_0": null, + "MONITOR_BYP1_1": null, + "MONITOR_BYP1_2": null, + "MONITOR_BYP1_3": null, + "MONITOR_BYP1_4": null, + "MONITOR_BYP1_5": null, + "MONITOR_BYP1_6": null, + "MONITOR_BYP1_7": null, + "MONITOR_BYP1_8": null, + "MONITOR_BYP1_9": null, + "MONITOR_BYP2_0": null, + "MONITOR_BYP2_1": null, + "MONITOR_BYP2_2": null, + "MONITOR_BYP2_3": null, + "MONITOR_BYP2_4": null, + "MONITOR_BYP2_5": null, + "MONITOR_BYP2_6": null, + "MONITOR_BYP2_7": null, + "MONITOR_BYP2_8": null, + "MONITOR_BYP2_9": null, + "MONITOR_BYP3_0": null, + "MONITOR_BYP3_1": null, + "MONITOR_BYP3_2": null, + "MONITOR_BYP3_3": null, + "MONITOR_BYP3_4": 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null, + "MONITOR_CTRL0_4": null, + "MONITOR_CTRL0_5": null, + "MONITOR_CTRL0_6": null, + "MONITOR_CTRL0_7": null, + "MONITOR_CTRL0_8": null, + "MONITOR_CTRL0_9": null, + "MONITOR_CTRL1_0": null, + "MONITOR_CTRL1_1": null, + "MONITOR_CTRL1_2": null, + "MONITOR_CTRL1_3": null, + "MONITOR_CTRL1_4": null, + "MONITOR_CTRL1_5": null, + "MONITOR_CTRL1_6": null, + "MONITOR_CTRL1_7": null, + "MONITOR_CTRL1_8": null, + "MONITOR_CTRL1_9": null, + "MONITOR_DADDR0": null, + "MONITOR_DADDR1": null, + "MONITOR_DADDR2": null, + "MONITOR_DADDR3": null, + "MONITOR_DADDR4": null, + "MONITOR_DADDR5": null, + "MONITOR_DADDR6": null, + "MONITOR_DCLK": null, + "MONITOR_DEN": null, + "MONITOR_DI0": null, + "MONITOR_DI1": null, + "MONITOR_DI10": null, + "MONITOR_DI11": null, + "MONITOR_DI12": null, + "MONITOR_DI13": null, + "MONITOR_DI14": null, + "MONITOR_DI15": null, + "MONITOR_DI2": null, + "MONITOR_DI3": null, + "MONITOR_DI4": null, + "MONITOR_DI5": null, + "MONITOR_DI6": null, + "MONITOR_DI7": null, + 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"MONITOR_WW4B1_0": null, + "MONITOR_WW4B1_1": null, + "MONITOR_WW4B1_2": null, + "MONITOR_WW4B1_3": null, + "MONITOR_WW4B1_4": null, + "MONITOR_WW4B1_5": null, + "MONITOR_WW4B1_6": null, + "MONITOR_WW4B1_7": null, + "MONITOR_WW4B1_8": null, + "MONITOR_WW4B1_9": null, + "MONITOR_WW4B2_0": null, + "MONITOR_WW4B2_1": null, + "MONITOR_WW4B2_2": null, + "MONITOR_WW4B2_3": null, + "MONITOR_WW4B2_4": null, + "MONITOR_WW4B2_5": null, + "MONITOR_WW4B2_6": null, + "MONITOR_WW4B2_7": null, + "MONITOR_WW4B2_8": null, + "MONITOR_WW4B2_9": null, + "MONITOR_WW4B3_0": null, + "MONITOR_WW4B3_1": null, + "MONITOR_WW4B3_2": null, + "MONITOR_WW4B3_3": null, + "MONITOR_WW4B3_4": null, + "MONITOR_WW4B3_5": null, + "MONITOR_WW4B3_6": null, + "MONITOR_WW4B3_7": null, + "MONITOR_WW4B3_8": null, + "MONITOR_WW4B3_9": null, + "MONITOR_WW4C0_0": null, + "MONITOR_WW4C0_1": null, + "MONITOR_WW4C0_2": null, + "MONITOR_WW4C0_3": null, + "MONITOR_WW4C0_4": null, + "MONITOR_WW4C0_5": null, + "MONITOR_WW4C0_6": null, + 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"MONITOR_WW4END3_8": null, + "MONITOR_WW4END3_9": null + } } diff --git a/zynq7/tile_type_MONITOR_MID_PELE1.json b/zynq7/tile_type_MONITOR_MID_PELE1.json index 787f86f..e168b65 100644 --- a/zynq7/tile_type_MONITOR_MID_PELE1.json +++ b/zynq7/tile_type_MONITOR_MID_PELE1.json @@ -2,2287 +2,2353 @@ "pips": { "MONITOR_MID_PELE1.MONITOR_HORIZ_VAUXN1_RIGHT->MONITOR_VERT_VAUXN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN1_RIGHT" }, "MONITOR_MID_PELE1.MONITOR_HORIZ_VAUXN2_RIGHT->MONITOR_VERT_VAUXN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN2_RIGHT" }, "MONITOR_MID_PELE1.MONITOR_HORIZ_VAUXN9_RIGHT->MONITOR_VERT_VAUXN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN9_RIGHT" }, "MONITOR_MID_PELE1.MONITOR_HORIZ_VAUXP1_RIGHT->MONITOR_VERT_VAUXP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP1_RIGHT" }, "MONITOR_MID_PELE1.MONITOR_HORIZ_VAUXP2_RIGHT->MONITOR_VERT_VAUXP2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP2_RIGHT" }, "MONITOR_MID_PELE1.MONITOR_HORIZ_VAUXP9_RIGHT->MONITOR_VERT_VAUXP9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP9_RIGHT" } }, "sites": [], "tile_type": "MONITOR_MID_PELE1", - "wires": [ - "MONITOR_BLOCK_OUTS_B0_0", - "MONITOR_BLOCK_OUTS_B0_1", - "MONITOR_BLOCK_OUTS_B0_2", - "MONITOR_BLOCK_OUTS_B0_3", - "MONITOR_BLOCK_OUTS_B0_4", - "MONITOR_BLOCK_OUTS_B0_5", - "MONITOR_BLOCK_OUTS_B0_6", - "MONITOR_BLOCK_OUTS_B0_7", - "MONITOR_BLOCK_OUTS_B0_8", - "MONITOR_BLOCK_OUTS_B0_9", - "MONITOR_BLOCK_OUTS_B1_0", - "MONITOR_BLOCK_OUTS_B1_1", - "MONITOR_BLOCK_OUTS_B1_2", - "MONITOR_BLOCK_OUTS_B1_3", - "MONITOR_BLOCK_OUTS_B1_4", - "MONITOR_BLOCK_OUTS_B1_5", - "MONITOR_BLOCK_OUTS_B1_6", - "MONITOR_BLOCK_OUTS_B1_7", - "MONITOR_BLOCK_OUTS_B1_8", - "MONITOR_BLOCK_OUTS_B1_9", - "MONITOR_BLOCK_OUTS_B2_0", - "MONITOR_BLOCK_OUTS_B2_1", - "MONITOR_BLOCK_OUTS_B2_2", - "MONITOR_BLOCK_OUTS_B2_3", - "MONITOR_BLOCK_OUTS_B2_4", - "MONITOR_BLOCK_OUTS_B2_5", - "MONITOR_BLOCK_OUTS_B2_6", - "MONITOR_BLOCK_OUTS_B2_7", - "MONITOR_BLOCK_OUTS_B2_8", - "MONITOR_BLOCK_OUTS_B2_9", - "MONITOR_BLOCK_OUTS_B3_0", - "MONITOR_BLOCK_OUTS_B3_1", - "MONITOR_BLOCK_OUTS_B3_2", - "MONITOR_BLOCK_OUTS_B3_3", - "MONITOR_BLOCK_OUTS_B3_4", - "MONITOR_BLOCK_OUTS_B3_5", - "MONITOR_BLOCK_OUTS_B3_6", - "MONITOR_BLOCK_OUTS_B3_7", - "MONITOR_BLOCK_OUTS_B3_8", - "MONITOR_BLOCK_OUTS_B3_9", - "MONITOR_BYP0_0", - "MONITOR_BYP0_1", - "MONITOR_BYP0_2", - "MONITOR_BYP0_3", - "MONITOR_BYP0_4", - "MONITOR_BYP0_5", - "MONITOR_BYP0_6", - "MONITOR_BYP0_7", - "MONITOR_BYP0_8", - "MONITOR_BYP0_9", - "MONITOR_BYP1_0", - "MONITOR_BYP1_1", - "MONITOR_BYP1_2", - "MONITOR_BYP1_3", - "MONITOR_BYP1_4", - "MONITOR_BYP1_5", - "MONITOR_BYP1_6", - "MONITOR_BYP1_7", - "MONITOR_BYP1_8", - "MONITOR_BYP1_9", - "MONITOR_BYP2_0", - "MONITOR_BYP2_1", - "MONITOR_BYP2_2", - "MONITOR_BYP2_3", - "MONITOR_BYP2_4", - "MONITOR_BYP2_5", - "MONITOR_BYP2_6", - "MONITOR_BYP2_7", - "MONITOR_BYP2_8", - "MONITOR_BYP2_9", - "MONITOR_BYP3_0", - "MONITOR_BYP3_1", - "MONITOR_BYP3_2", - "MONITOR_BYP3_3", - "MONITOR_BYP3_4", - "MONITOR_BYP3_5", - "MONITOR_BYP3_6", - "MONITOR_BYP3_7", - "MONITOR_BYP3_8", - "MONITOR_BYP3_9", - "MONITOR_BYP4_0", - "MONITOR_BYP4_1", - "MONITOR_BYP4_2", - "MONITOR_BYP4_3", - "MONITOR_BYP4_4", - "MONITOR_BYP4_5", - "MONITOR_BYP4_6", - "MONITOR_BYP4_7", - "MONITOR_BYP4_8", - "MONITOR_BYP4_9", - "MONITOR_BYP5_0", - "MONITOR_BYP5_1", - "MONITOR_BYP5_2", - "MONITOR_BYP5_3", - "MONITOR_BYP5_4", - "MONITOR_BYP5_5", - "MONITOR_BYP5_6", - "MONITOR_BYP5_7", - "MONITOR_BYP5_8", - "MONITOR_BYP5_9", - "MONITOR_BYP6_0", - "MONITOR_BYP6_1", - "MONITOR_BYP6_2", - "MONITOR_BYP6_3", - "MONITOR_BYP6_4", - "MONITOR_BYP6_5", - "MONITOR_BYP6_6", - "MONITOR_BYP6_7", - "MONITOR_BYP6_8", - "MONITOR_BYP6_9", - "MONITOR_BYP7_0", - "MONITOR_BYP7_1", - "MONITOR_BYP7_2", - "MONITOR_BYP7_3", - "MONITOR_BYP7_4", - "MONITOR_BYP7_5", - "MONITOR_BYP7_6", - "MONITOR_BYP7_7", - "MONITOR_BYP7_8", - "MONITOR_BYP7_9", - "MONITOR_CLK0_0", - "MONITOR_CLK0_1", - "MONITOR_CLK0_2", - "MONITOR_CLK0_3", - "MONITOR_CLK0_4", - "MONITOR_CLK0_5", - "MONITOR_CLK0_6", - "MONITOR_CLK0_7", - "MONITOR_CLK0_8", - "MONITOR_CLK0_9", - "MONITOR_CLK1_0", - "MONITOR_CLK1_1", - "MONITOR_CLK1_2", - "MONITOR_CLK1_3", - "MONITOR_CLK1_4", - "MONITOR_CLK1_5", - "MONITOR_CLK1_6", - "MONITOR_CLK1_7", - "MONITOR_CLK1_8", - "MONITOR_CLK1_9", - "MONITOR_CTRL0_0", - "MONITOR_CTRL0_1", - "MONITOR_CTRL0_2", - "MONITOR_CTRL0_3", - "MONITOR_CTRL0_4", - "MONITOR_CTRL0_5", - "MONITOR_CTRL0_6", - "MONITOR_CTRL0_7", - "MONITOR_CTRL0_8", - "MONITOR_CTRL0_9", - "MONITOR_CTRL1_0", - "MONITOR_CTRL1_1", - "MONITOR_CTRL1_2", - "MONITOR_CTRL1_3", - "MONITOR_CTRL1_4", - "MONITOR_CTRL1_5", - "MONITOR_CTRL1_6", - "MONITOR_CTRL1_7", - "MONITOR_CTRL1_8", - "MONITOR_CTRL1_9", - "MONITOR_EE2A0_0", - "MONITOR_EE2A0_1", - "MONITOR_EE2A0_2", - "MONITOR_EE2A0_3", - "MONITOR_EE2A0_4", - "MONITOR_EE2A0_5", - "MONITOR_EE2A0_6", - "MONITOR_EE2A0_7", - "MONITOR_EE2A0_8", - "MONITOR_EE2A0_9", - "MONITOR_EE2A1_0", - "MONITOR_EE2A1_1", - "MONITOR_EE2A1_2", - "MONITOR_EE2A1_3", - "MONITOR_EE2A1_4", - "MONITOR_EE2A1_5", - "MONITOR_EE2A1_6", - "MONITOR_EE2A1_7", - "MONITOR_EE2A1_8", - "MONITOR_EE2A1_9", - "MONITOR_EE2A2_0", - "MONITOR_EE2A2_1", - "MONITOR_EE2A2_2", - "MONITOR_EE2A2_3", - "MONITOR_EE2A2_4", - "MONITOR_EE2A2_5", - "MONITOR_EE2A2_6", - "MONITOR_EE2A2_7", - "MONITOR_EE2A2_8", - "MONITOR_EE2A2_9", - "MONITOR_EE2A3_0", - "MONITOR_EE2A3_1", - "MONITOR_EE2A3_2", - "MONITOR_EE2A3_3", - "MONITOR_EE2A3_4", - "MONITOR_EE2A3_5", - "MONITOR_EE2A3_6", - "MONITOR_EE2A3_7", - "MONITOR_EE2A3_8", - "MONITOR_EE2A3_9", - "MONITOR_EE2BEG0_0", - "MONITOR_EE2BEG0_1", - "MONITOR_EE2BEG0_2", - "MONITOR_EE2BEG0_3", - "MONITOR_EE2BEG0_4", - "MONITOR_EE2BEG0_5", - "MONITOR_EE2BEG0_6", - "MONITOR_EE2BEG0_7", - "MONITOR_EE2BEG0_8", - "MONITOR_EE2BEG0_9", - "MONITOR_EE2BEG1_0", - "MONITOR_EE2BEG1_1", - "MONITOR_EE2BEG1_2", - "MONITOR_EE2BEG1_3", - "MONITOR_EE2BEG1_4", - "MONITOR_EE2BEG1_5", - "MONITOR_EE2BEG1_6", - "MONITOR_EE2BEG1_7", - "MONITOR_EE2BEG1_8", - "MONITOR_EE2BEG1_9", - "MONITOR_EE2BEG2_0", - "MONITOR_EE2BEG2_1", - "MONITOR_EE2BEG2_2", - "MONITOR_EE2BEG2_3", - "MONITOR_EE2BEG2_4", - "MONITOR_EE2BEG2_5", - "MONITOR_EE2BEG2_6", - "MONITOR_EE2BEG2_7", - "MONITOR_EE2BEG2_8", - "MONITOR_EE2BEG2_9", - "MONITOR_EE2BEG3_0", - "MONITOR_EE2BEG3_1", - "MONITOR_EE2BEG3_2", - "MONITOR_EE2BEG3_3", - "MONITOR_EE2BEG3_4", - "MONITOR_EE2BEG3_5", - "MONITOR_EE2BEG3_6", - "MONITOR_EE2BEG3_7", - "MONITOR_EE2BEG3_8", - "MONITOR_EE2BEG3_9", - "MONITOR_EE4A0_0", - "MONITOR_EE4A0_1", - "MONITOR_EE4A0_2", - "MONITOR_EE4A0_3", - "MONITOR_EE4A0_4", - "MONITOR_EE4A0_5", - "MONITOR_EE4A0_6", - "MONITOR_EE4A0_7", - "MONITOR_EE4A0_8", - "MONITOR_EE4A0_9", - "MONITOR_EE4A1_0", - "MONITOR_EE4A1_1", - "MONITOR_EE4A1_2", - "MONITOR_EE4A1_3", - "MONITOR_EE4A1_4", - "MONITOR_EE4A1_5", - "MONITOR_EE4A1_6", - "MONITOR_EE4A1_7", - "MONITOR_EE4A1_8", - "MONITOR_EE4A1_9", - "MONITOR_EE4A2_0", - "MONITOR_EE4A2_1", - "MONITOR_EE4A2_2", - "MONITOR_EE4A2_3", - "MONITOR_EE4A2_4", - "MONITOR_EE4A2_5", - "MONITOR_EE4A2_6", - "MONITOR_EE4A2_7", - "MONITOR_EE4A2_8", - "MONITOR_EE4A2_9", - "MONITOR_EE4A3_0", - "MONITOR_EE4A3_1", - "MONITOR_EE4A3_2", - "MONITOR_EE4A3_3", - "MONITOR_EE4A3_4", - "MONITOR_EE4A3_5", - "MONITOR_EE4A3_6", - "MONITOR_EE4A3_7", - "MONITOR_EE4A3_8", - "MONITOR_EE4A3_9", - "MONITOR_EE4B0_0", - "MONITOR_EE4B0_1", - "MONITOR_EE4B0_2", - "MONITOR_EE4B0_3", - "MONITOR_EE4B0_4", - "MONITOR_EE4B0_5", - "MONITOR_EE4B0_6", - "MONITOR_EE4B0_7", - "MONITOR_EE4B0_8", - "MONITOR_EE4B0_9", - "MONITOR_EE4B1_0", - "MONITOR_EE4B1_1", - "MONITOR_EE4B1_2", - "MONITOR_EE4B1_3", - "MONITOR_EE4B1_4", - "MONITOR_EE4B1_5", - "MONITOR_EE4B1_6", - "MONITOR_EE4B1_7", - "MONITOR_EE4B1_8", - "MONITOR_EE4B1_9", - "MONITOR_EE4B2_0", - "MONITOR_EE4B2_1", - "MONITOR_EE4B2_2", - "MONITOR_EE4B2_3", - "MONITOR_EE4B2_4", - "MONITOR_EE4B2_5", - "MONITOR_EE4B2_6", - "MONITOR_EE4B2_7", - "MONITOR_EE4B2_8", - "MONITOR_EE4B2_9", - "MONITOR_EE4B3_0", - "MONITOR_EE4B3_1", - "MONITOR_EE4B3_2", - "MONITOR_EE4B3_3", - "MONITOR_EE4B3_4", - "MONITOR_EE4B3_5", - "MONITOR_EE4B3_6", - "MONITOR_EE4B3_7", - "MONITOR_EE4B3_8", - "MONITOR_EE4B3_9", - "MONITOR_EE4BEG0_0", - "MONITOR_EE4BEG0_1", - "MONITOR_EE4BEG0_2", - "MONITOR_EE4BEG0_3", - "MONITOR_EE4BEG0_4", - "MONITOR_EE4BEG0_5", - "MONITOR_EE4BEG0_6", - "MONITOR_EE4BEG0_7", - "MONITOR_EE4BEG0_8", - "MONITOR_EE4BEG0_9", - "MONITOR_EE4BEG1_0", - "MONITOR_EE4BEG1_1", - "MONITOR_EE4BEG1_2", - "MONITOR_EE4BEG1_3", - "MONITOR_EE4BEG1_4", - "MONITOR_EE4BEG1_5", - "MONITOR_EE4BEG1_6", - "MONITOR_EE4BEG1_7", - "MONITOR_EE4BEG1_8", - "MONITOR_EE4BEG1_9", - "MONITOR_EE4BEG2_0", - "MONITOR_EE4BEG2_1", - "MONITOR_EE4BEG2_2", - "MONITOR_EE4BEG2_3", - "MONITOR_EE4BEG2_4", - "MONITOR_EE4BEG2_5", - "MONITOR_EE4BEG2_6", - "MONITOR_EE4BEG2_7", - "MONITOR_EE4BEG2_8", - "MONITOR_EE4BEG2_9", - "MONITOR_EE4BEG3_0", - "MONITOR_EE4BEG3_1", - "MONITOR_EE4BEG3_2", - "MONITOR_EE4BEG3_3", - "MONITOR_EE4BEG3_4", - "MONITOR_EE4BEG3_5", - "MONITOR_EE4BEG3_6", - "MONITOR_EE4BEG3_7", - "MONITOR_EE4BEG3_8", - "MONITOR_EE4BEG3_9", - "MONITOR_EE4C0_0", - "MONITOR_EE4C0_1", - "MONITOR_EE4C0_2", - "MONITOR_EE4C0_3", - "MONITOR_EE4C0_4", - "MONITOR_EE4C0_5", - "MONITOR_EE4C0_6", - "MONITOR_EE4C0_7", - "MONITOR_EE4C0_8", - "MONITOR_EE4C0_9", - "MONITOR_EE4C1_0", - "MONITOR_EE4C1_1", - "MONITOR_EE4C1_2", - "MONITOR_EE4C1_3", - "MONITOR_EE4C1_4", - "MONITOR_EE4C1_5", - "MONITOR_EE4C1_6", - "MONITOR_EE4C1_7", - "MONITOR_EE4C1_8", - "MONITOR_EE4C1_9", - "MONITOR_EE4C2_0", - "MONITOR_EE4C2_1", - "MONITOR_EE4C2_2", - "MONITOR_EE4C2_3", - "MONITOR_EE4C2_4", - "MONITOR_EE4C2_5", - "MONITOR_EE4C2_6", - "MONITOR_EE4C2_7", - "MONITOR_EE4C2_8", - "MONITOR_EE4C2_9", - "MONITOR_EE4C3_0", - "MONITOR_EE4C3_1", - "MONITOR_EE4C3_2", - "MONITOR_EE4C3_3", - "MONITOR_EE4C3_4", - "MONITOR_EE4C3_5", - "MONITOR_EE4C3_6", - "MONITOR_EE4C3_7", - "MONITOR_EE4C3_8", - "MONITOR_EE4C3_9", - "MONITOR_EL1BEG0_0", - "MONITOR_EL1BEG0_1", - "MONITOR_EL1BEG0_2", - "MONITOR_EL1BEG0_3", - "MONITOR_EL1BEG0_4", - "MONITOR_EL1BEG0_5", - "MONITOR_EL1BEG0_6", - "MONITOR_EL1BEG0_7", - "MONITOR_EL1BEG0_8", - "MONITOR_EL1BEG0_9", - "MONITOR_EL1BEG1_0", - "MONITOR_EL1BEG1_1", - "MONITOR_EL1BEG1_2", - "MONITOR_EL1BEG1_3", - "MONITOR_EL1BEG1_4", - "MONITOR_EL1BEG1_5", - "MONITOR_EL1BEG1_6", - "MONITOR_EL1BEG1_7", - "MONITOR_EL1BEG1_8", - "MONITOR_EL1BEG1_9", - "MONITOR_EL1BEG2_0", - "MONITOR_EL1BEG2_1", - "MONITOR_EL1BEG2_2", - "MONITOR_EL1BEG2_3", - "MONITOR_EL1BEG2_4", - "MONITOR_EL1BEG2_5", - "MONITOR_EL1BEG2_6", - "MONITOR_EL1BEG2_7", - "MONITOR_EL1BEG2_8", - "MONITOR_EL1BEG2_9", - "MONITOR_EL1BEG3_0", - "MONITOR_EL1BEG3_1", - "MONITOR_EL1BEG3_2", - "MONITOR_EL1BEG3_3", - "MONITOR_EL1BEG3_4", - "MONITOR_EL1BEG3_5", - "MONITOR_EL1BEG3_6", - "MONITOR_EL1BEG3_7", - "MONITOR_EL1BEG3_8", - "MONITOR_EL1BEG3_9", - "MONITOR_ER1BEG0_0", - "MONITOR_ER1BEG0_1", - "MONITOR_ER1BEG0_2", - "MONITOR_ER1BEG0_3", - "MONITOR_ER1BEG0_4", - "MONITOR_ER1BEG0_5", - "MONITOR_ER1BEG0_6", - "MONITOR_ER1BEG0_7", - "MONITOR_ER1BEG0_8", - "MONITOR_ER1BEG0_9", - "MONITOR_ER1BEG1_0", - "MONITOR_ER1BEG1_1", - "MONITOR_ER1BEG1_2", - "MONITOR_ER1BEG1_3", - "MONITOR_ER1BEG1_4", - "MONITOR_ER1BEG1_5", - "MONITOR_ER1BEG1_6", - "MONITOR_ER1BEG1_7", - "MONITOR_ER1BEG1_8", - "MONITOR_ER1BEG1_9", - "MONITOR_ER1BEG2_0", - "MONITOR_ER1BEG2_1", - "MONITOR_ER1BEG2_2", - "MONITOR_ER1BEG2_3", - "MONITOR_ER1BEG2_4", - "MONITOR_ER1BEG2_5", - "MONITOR_ER1BEG2_6", - "MONITOR_ER1BEG2_7", - "MONITOR_ER1BEG2_8", - "MONITOR_ER1BEG2_9", - "MONITOR_ER1BEG3_0", - "MONITOR_ER1BEG3_1", - "MONITOR_ER1BEG3_2", - "MONITOR_ER1BEG3_3", - "MONITOR_ER1BEG3_4", - "MONITOR_ER1BEG3_5", - "MONITOR_ER1BEG3_6", - "MONITOR_ER1BEG3_7", - "MONITOR_ER1BEG3_8", - "MONITOR_ER1BEG3_9", - "MONITOR_FAN0_0", - "MONITOR_FAN0_1", - "MONITOR_FAN0_2", - "MONITOR_FAN0_3", - "MONITOR_FAN0_4", - "MONITOR_FAN0_5", - "MONITOR_FAN0_6", - "MONITOR_FAN0_7", - "MONITOR_FAN0_8", - "MONITOR_FAN0_9", - "MONITOR_FAN1_0", - "MONITOR_FAN1_1", - "MONITOR_FAN1_2", - "MONITOR_FAN1_3", - "MONITOR_FAN1_4", - "MONITOR_FAN1_5", - "MONITOR_FAN1_6", - "MONITOR_FAN1_7", - "MONITOR_FAN1_8", - "MONITOR_FAN1_9", - "MONITOR_FAN2_0", - "MONITOR_FAN2_1", - "MONITOR_FAN2_2", - "MONITOR_FAN2_3", - "MONITOR_FAN2_4", - "MONITOR_FAN2_5", - "MONITOR_FAN2_6", - "MONITOR_FAN2_7", - "MONITOR_FAN2_8", - "MONITOR_FAN2_9", - "MONITOR_FAN3_0", - "MONITOR_FAN3_1", - "MONITOR_FAN3_2", - "MONITOR_FAN3_3", - "MONITOR_FAN3_4", - "MONITOR_FAN3_5", - "MONITOR_FAN3_6", - "MONITOR_FAN3_7", - "MONITOR_FAN3_8", - "MONITOR_FAN3_9", - "MONITOR_FAN4_0", - "MONITOR_FAN4_1", - "MONITOR_FAN4_2", - "MONITOR_FAN4_3", - "MONITOR_FAN4_4", - "MONITOR_FAN4_5", - "MONITOR_FAN4_6", - "MONITOR_FAN4_7", - "MONITOR_FAN4_8", - "MONITOR_FAN4_9", - "MONITOR_FAN5_0", - "MONITOR_FAN5_1", - "MONITOR_FAN5_2", - "MONITOR_FAN5_3", - "MONITOR_FAN5_4", - "MONITOR_FAN5_5", - "MONITOR_FAN5_6", - "MONITOR_FAN5_7", - "MONITOR_FAN5_8", - "MONITOR_FAN5_9", - "MONITOR_FAN6_0", - "MONITOR_FAN6_1", - "MONITOR_FAN6_2", - "MONITOR_FAN6_3", - "MONITOR_FAN6_4", - "MONITOR_FAN6_5", - "MONITOR_FAN6_6", - "MONITOR_FAN6_7", - "MONITOR_FAN6_8", - "MONITOR_FAN6_9", - "MONITOR_FAN7_0", - "MONITOR_FAN7_1", - "MONITOR_FAN7_2", - "MONITOR_FAN7_3", - "MONITOR_FAN7_4", - "MONITOR_FAN7_5", - "MONITOR_FAN7_6", - "MONITOR_FAN7_7", - "MONITOR_FAN7_8", - "MONITOR_FAN7_9", - "MONITOR_HORIZ_VAUXN1_RIGHT", - "MONITOR_HORIZ_VAUXN2_RIGHT", - "MONITOR_HORIZ_VAUXN9_RIGHT", - "MONITOR_HORIZ_VAUXP1_RIGHT", - "MONITOR_HORIZ_VAUXP2_RIGHT", - "MONITOR_HORIZ_VAUXP9_RIGHT", - "MONITOR_IMUX0_0", - "MONITOR_IMUX0_1", - "MONITOR_IMUX0_2", - "MONITOR_IMUX0_3", - "MONITOR_IMUX0_4", - "MONITOR_IMUX0_5", - "MONITOR_IMUX0_6", - "MONITOR_IMUX0_7", - "MONITOR_IMUX0_8", - "MONITOR_IMUX0_9", - "MONITOR_IMUX10_0", - "MONITOR_IMUX10_1", - "MONITOR_IMUX10_2", - "MONITOR_IMUX10_3", - "MONITOR_IMUX10_4", - "MONITOR_IMUX10_5", - "MONITOR_IMUX10_6", - "MONITOR_IMUX10_7", - "MONITOR_IMUX10_8", - "MONITOR_IMUX10_9", - "MONITOR_IMUX11_0", - "MONITOR_IMUX11_1", - "MONITOR_IMUX11_2", - "MONITOR_IMUX11_3", - "MONITOR_IMUX11_4", - "MONITOR_IMUX11_5", - "MONITOR_IMUX11_6", - "MONITOR_IMUX11_7", - "MONITOR_IMUX11_8", - "MONITOR_IMUX11_9", - "MONITOR_IMUX12_0", - "MONITOR_IMUX12_1", - "MONITOR_IMUX12_2", - "MONITOR_IMUX12_3", - "MONITOR_IMUX12_4", - "MONITOR_IMUX12_5", - "MONITOR_IMUX12_6", - "MONITOR_IMUX12_7", - "MONITOR_IMUX12_8", - "MONITOR_IMUX12_9", - "MONITOR_IMUX13_0", - "MONITOR_IMUX13_1", - "MONITOR_IMUX13_2", - "MONITOR_IMUX13_3", - "MONITOR_IMUX13_4", - "MONITOR_IMUX13_5", - "MONITOR_IMUX13_6", - "MONITOR_IMUX13_7", - "MONITOR_IMUX13_8", - "MONITOR_IMUX13_9", - "MONITOR_IMUX14_0", - "MONITOR_IMUX14_1", - "MONITOR_IMUX14_2", - "MONITOR_IMUX14_3", - "MONITOR_IMUX14_4", - "MONITOR_IMUX14_5", - "MONITOR_IMUX14_6", - "MONITOR_IMUX14_7", - "MONITOR_IMUX14_8", - "MONITOR_IMUX14_9", - "MONITOR_IMUX15_0", - "MONITOR_IMUX15_1", - "MONITOR_IMUX15_2", - "MONITOR_IMUX15_3", - "MONITOR_IMUX15_4", - "MONITOR_IMUX15_5", - "MONITOR_IMUX15_6", - "MONITOR_IMUX15_7", - "MONITOR_IMUX15_8", - "MONITOR_IMUX15_9", - "MONITOR_IMUX16_0", - "MONITOR_IMUX16_1", - "MONITOR_IMUX16_2", - "MONITOR_IMUX16_3", - "MONITOR_IMUX16_4", - "MONITOR_IMUX16_5", - "MONITOR_IMUX16_6", - "MONITOR_IMUX16_7", - "MONITOR_IMUX16_8", - "MONITOR_IMUX16_9", - "MONITOR_IMUX17_0", - "MONITOR_IMUX17_1", - "MONITOR_IMUX17_2", - "MONITOR_IMUX17_3", - "MONITOR_IMUX17_4", - "MONITOR_IMUX17_5", - "MONITOR_IMUX17_6", - "MONITOR_IMUX17_7", - "MONITOR_IMUX17_8", - "MONITOR_IMUX17_9", - "MONITOR_IMUX18_0", - "MONITOR_IMUX18_1", - "MONITOR_IMUX18_2", - "MONITOR_IMUX18_3", - "MONITOR_IMUX18_4", - "MONITOR_IMUX18_5", - "MONITOR_IMUX18_6", - "MONITOR_IMUX18_7", - "MONITOR_IMUX18_8", - "MONITOR_IMUX18_9", - "MONITOR_IMUX19_0", - "MONITOR_IMUX19_1", - "MONITOR_IMUX19_2", - "MONITOR_IMUX19_3", - "MONITOR_IMUX19_4", - "MONITOR_IMUX19_5", - "MONITOR_IMUX19_6", - "MONITOR_IMUX19_7", - "MONITOR_IMUX19_8", - "MONITOR_IMUX19_9", - "MONITOR_IMUX1_0", - "MONITOR_IMUX1_1", - "MONITOR_IMUX1_2", - "MONITOR_IMUX1_3", - "MONITOR_IMUX1_4", - "MONITOR_IMUX1_5", - "MONITOR_IMUX1_6", - "MONITOR_IMUX1_7", - "MONITOR_IMUX1_8", - "MONITOR_IMUX1_9", - "MONITOR_IMUX20_0", - "MONITOR_IMUX20_1", - "MONITOR_IMUX20_2", - "MONITOR_IMUX20_3", - "MONITOR_IMUX20_4", - "MONITOR_IMUX20_5", - "MONITOR_IMUX20_6", - "MONITOR_IMUX20_7", - "MONITOR_IMUX20_8", - "MONITOR_IMUX20_9", - "MONITOR_IMUX21_0", - "MONITOR_IMUX21_1", - "MONITOR_IMUX21_2", - "MONITOR_IMUX21_3", - "MONITOR_IMUX21_4", - "MONITOR_IMUX21_5", - "MONITOR_IMUX21_6", - "MONITOR_IMUX21_7", - "MONITOR_IMUX21_8", - "MONITOR_IMUX21_9", - "MONITOR_IMUX22_0", - "MONITOR_IMUX22_1", - "MONITOR_IMUX22_2", - "MONITOR_IMUX22_3", - "MONITOR_IMUX22_4", - "MONITOR_IMUX22_5", - "MONITOR_IMUX22_6", - "MONITOR_IMUX22_7", - "MONITOR_IMUX22_8", - "MONITOR_IMUX22_9", - "MONITOR_IMUX23_0", - "MONITOR_IMUX23_1", - "MONITOR_IMUX23_2", - "MONITOR_IMUX23_3", - "MONITOR_IMUX23_4", - "MONITOR_IMUX23_5", - "MONITOR_IMUX23_6", - "MONITOR_IMUX23_7", - "MONITOR_IMUX23_8", - "MONITOR_IMUX23_9", - "MONITOR_IMUX24_0", - "MONITOR_IMUX24_1", - "MONITOR_IMUX24_2", - "MONITOR_IMUX24_3", - "MONITOR_IMUX24_4", - "MONITOR_IMUX24_5", - "MONITOR_IMUX24_6", - "MONITOR_IMUX24_7", - "MONITOR_IMUX24_8", - "MONITOR_IMUX24_9", - "MONITOR_IMUX25_0", - "MONITOR_IMUX25_1", - "MONITOR_IMUX25_2", - "MONITOR_IMUX25_3", - "MONITOR_IMUX25_4", - "MONITOR_IMUX25_5", - "MONITOR_IMUX25_6", - "MONITOR_IMUX25_7", - "MONITOR_IMUX25_8", - "MONITOR_IMUX25_9", - "MONITOR_IMUX26_0", - "MONITOR_IMUX26_1", - "MONITOR_IMUX26_2", - "MONITOR_IMUX26_3", - "MONITOR_IMUX26_4", - "MONITOR_IMUX26_5", - "MONITOR_IMUX26_6", - "MONITOR_IMUX26_7", - "MONITOR_IMUX26_8", - "MONITOR_IMUX26_9", - "MONITOR_IMUX27_0", - "MONITOR_IMUX27_1", - "MONITOR_IMUX27_2", - "MONITOR_IMUX27_3", - "MONITOR_IMUX27_4", - "MONITOR_IMUX27_5", - "MONITOR_IMUX27_6", - "MONITOR_IMUX27_7", - "MONITOR_IMUX27_8", - "MONITOR_IMUX27_9", - "MONITOR_IMUX28_0", - "MONITOR_IMUX28_1", - "MONITOR_IMUX28_2", - "MONITOR_IMUX28_3", - "MONITOR_IMUX28_4", - "MONITOR_IMUX28_5", - "MONITOR_IMUX28_6", - "MONITOR_IMUX28_7", - "MONITOR_IMUX28_8", - "MONITOR_IMUX28_9", - "MONITOR_IMUX29_0", - "MONITOR_IMUX29_1", - "MONITOR_IMUX29_2", - "MONITOR_IMUX29_3", - "MONITOR_IMUX29_4", - "MONITOR_IMUX29_5", - "MONITOR_IMUX29_6", - "MONITOR_IMUX29_7", - "MONITOR_IMUX29_8", - "MONITOR_IMUX29_9", - "MONITOR_IMUX2_0", - "MONITOR_IMUX2_1", - "MONITOR_IMUX2_2", - "MONITOR_IMUX2_3", - "MONITOR_IMUX2_4", - "MONITOR_IMUX2_5", - "MONITOR_IMUX2_6", - "MONITOR_IMUX2_7", - "MONITOR_IMUX2_8", - "MONITOR_IMUX2_9", - "MONITOR_IMUX30_0", - "MONITOR_IMUX30_1", - "MONITOR_IMUX30_2", - "MONITOR_IMUX30_3", - "MONITOR_IMUX30_4", - "MONITOR_IMUX30_5", - "MONITOR_IMUX30_6", - "MONITOR_IMUX30_7", - "MONITOR_IMUX30_8", - "MONITOR_IMUX30_9", - "MONITOR_IMUX31_0", - "MONITOR_IMUX31_1", - "MONITOR_IMUX31_2", - "MONITOR_IMUX31_3", - "MONITOR_IMUX31_4", - "MONITOR_IMUX31_5", - "MONITOR_IMUX31_6", - "MONITOR_IMUX31_7", - "MONITOR_IMUX31_8", - "MONITOR_IMUX31_9", - "MONITOR_IMUX32_0", - "MONITOR_IMUX32_1", - "MONITOR_IMUX32_2", - "MONITOR_IMUX32_3", - "MONITOR_IMUX32_4", - "MONITOR_IMUX32_5", - "MONITOR_IMUX32_6", - "MONITOR_IMUX32_7", - "MONITOR_IMUX32_8", - "MONITOR_IMUX32_9", - "MONITOR_IMUX33_0", - "MONITOR_IMUX33_1", - "MONITOR_IMUX33_2", - "MONITOR_IMUX33_3", - "MONITOR_IMUX33_4", - "MONITOR_IMUX33_5", - "MONITOR_IMUX33_6", - "MONITOR_IMUX33_7", - "MONITOR_IMUX33_8", - "MONITOR_IMUX33_9", - "MONITOR_IMUX34_0", - "MONITOR_IMUX34_1", - "MONITOR_IMUX34_2", - "MONITOR_IMUX34_3", - "MONITOR_IMUX34_4", - "MONITOR_IMUX34_5", - "MONITOR_IMUX34_6", - "MONITOR_IMUX34_7", - "MONITOR_IMUX34_8", - "MONITOR_IMUX34_9", - "MONITOR_IMUX35_0", - "MONITOR_IMUX35_1", - "MONITOR_IMUX35_2", - "MONITOR_IMUX35_3", - "MONITOR_IMUX35_4", - "MONITOR_IMUX35_5", - "MONITOR_IMUX35_6", - "MONITOR_IMUX35_7", - "MONITOR_IMUX35_8", - "MONITOR_IMUX35_9", - "MONITOR_IMUX36_0", - "MONITOR_IMUX36_1", - "MONITOR_IMUX36_2", - "MONITOR_IMUX36_3", - "MONITOR_IMUX36_4", - "MONITOR_IMUX36_5", - "MONITOR_IMUX36_6", - "MONITOR_IMUX36_7", - "MONITOR_IMUX36_8", - "MONITOR_IMUX36_9", - "MONITOR_IMUX37_0", - "MONITOR_IMUX37_1", - "MONITOR_IMUX37_2", - "MONITOR_IMUX37_3", - "MONITOR_IMUX37_4", - "MONITOR_IMUX37_5", - "MONITOR_IMUX37_6", - "MONITOR_IMUX37_7", - "MONITOR_IMUX37_8", - "MONITOR_IMUX37_9", - "MONITOR_IMUX38_0", - "MONITOR_IMUX38_1", - "MONITOR_IMUX38_2", - "MONITOR_IMUX38_3", - "MONITOR_IMUX38_4", - "MONITOR_IMUX38_5", - "MONITOR_IMUX38_6", - "MONITOR_IMUX38_7", - "MONITOR_IMUX38_8", - "MONITOR_IMUX38_9", - "MONITOR_IMUX39_0", - "MONITOR_IMUX39_1", - "MONITOR_IMUX39_2", - "MONITOR_IMUX39_3", - "MONITOR_IMUX39_4", - "MONITOR_IMUX39_5", - "MONITOR_IMUX39_6", - "MONITOR_IMUX39_7", - "MONITOR_IMUX39_8", - "MONITOR_IMUX39_9", - "MONITOR_IMUX3_0", - "MONITOR_IMUX3_1", - "MONITOR_IMUX3_2", - "MONITOR_IMUX3_3", - "MONITOR_IMUX3_4", - "MONITOR_IMUX3_5", - "MONITOR_IMUX3_6", - "MONITOR_IMUX3_7", - "MONITOR_IMUX3_8", - "MONITOR_IMUX3_9", - "MONITOR_IMUX40_0", - "MONITOR_IMUX40_1", - "MONITOR_IMUX40_2", - "MONITOR_IMUX40_3", - "MONITOR_IMUX40_4", - "MONITOR_IMUX40_5", - "MONITOR_IMUX40_6", - "MONITOR_IMUX40_7", - "MONITOR_IMUX40_8", - "MONITOR_IMUX40_9", - "MONITOR_IMUX41_0", - "MONITOR_IMUX41_1", - "MONITOR_IMUX41_2", - "MONITOR_IMUX41_3", - "MONITOR_IMUX41_4", - "MONITOR_IMUX41_5", - "MONITOR_IMUX41_6", - "MONITOR_IMUX41_7", - "MONITOR_IMUX41_8", - "MONITOR_IMUX41_9", - "MONITOR_IMUX42_0", - "MONITOR_IMUX42_1", - "MONITOR_IMUX42_2", - "MONITOR_IMUX42_3", - "MONITOR_IMUX42_4", - "MONITOR_IMUX42_5", - "MONITOR_IMUX42_6", - "MONITOR_IMUX42_7", - "MONITOR_IMUX42_8", - "MONITOR_IMUX42_9", - "MONITOR_IMUX43_0", - "MONITOR_IMUX43_1", - "MONITOR_IMUX43_2", - "MONITOR_IMUX43_3", - "MONITOR_IMUX43_4", - "MONITOR_IMUX43_5", - "MONITOR_IMUX43_6", - "MONITOR_IMUX43_7", - "MONITOR_IMUX43_8", - "MONITOR_IMUX43_9", - "MONITOR_IMUX44_0", - "MONITOR_IMUX44_1", - "MONITOR_IMUX44_2", - "MONITOR_IMUX44_3", - "MONITOR_IMUX44_4", - "MONITOR_IMUX44_5", - "MONITOR_IMUX44_6", - "MONITOR_IMUX44_7", - "MONITOR_IMUX44_8", - "MONITOR_IMUX44_9", - "MONITOR_IMUX45_0", - "MONITOR_IMUX45_1", - "MONITOR_IMUX45_2", - "MONITOR_IMUX45_3", - "MONITOR_IMUX45_4", - "MONITOR_IMUX45_5", - "MONITOR_IMUX45_6", - "MONITOR_IMUX45_7", - "MONITOR_IMUX45_8", - "MONITOR_IMUX45_9", - "MONITOR_IMUX46_0", - "MONITOR_IMUX46_1", - "MONITOR_IMUX46_2", - "MONITOR_IMUX46_3", - "MONITOR_IMUX46_4", - "MONITOR_IMUX46_5", - "MONITOR_IMUX46_6", - "MONITOR_IMUX46_7", - "MONITOR_IMUX46_8", - "MONITOR_IMUX46_9", - "MONITOR_IMUX47_0", - "MONITOR_IMUX47_1", - "MONITOR_IMUX47_2", - "MONITOR_IMUX47_3", - "MONITOR_IMUX47_4", - "MONITOR_IMUX47_5", - "MONITOR_IMUX47_6", - "MONITOR_IMUX47_7", - "MONITOR_IMUX47_8", - "MONITOR_IMUX47_9", - "MONITOR_IMUX4_0", - "MONITOR_IMUX4_1", - "MONITOR_IMUX4_2", - "MONITOR_IMUX4_3", - "MONITOR_IMUX4_4", - "MONITOR_IMUX4_5", - "MONITOR_IMUX4_6", - "MONITOR_IMUX4_7", - "MONITOR_IMUX4_8", - "MONITOR_IMUX4_9", - "MONITOR_IMUX5_0", - "MONITOR_IMUX5_1", - "MONITOR_IMUX5_2", - "MONITOR_IMUX5_3", - "MONITOR_IMUX5_4", - "MONITOR_IMUX5_5", - "MONITOR_IMUX5_6", - "MONITOR_IMUX5_7", - "MONITOR_IMUX5_8", - "MONITOR_IMUX5_9", - "MONITOR_IMUX6_0", - "MONITOR_IMUX6_1", - "MONITOR_IMUX6_2", - "MONITOR_IMUX6_3", - "MONITOR_IMUX6_4", - "MONITOR_IMUX6_5", - "MONITOR_IMUX6_6", - "MONITOR_IMUX6_7", - "MONITOR_IMUX6_8", - "MONITOR_IMUX6_9", - "MONITOR_IMUX7_0", - "MONITOR_IMUX7_1", - "MONITOR_IMUX7_2", - "MONITOR_IMUX7_3", - "MONITOR_IMUX7_4", - "MONITOR_IMUX7_5", - "MONITOR_IMUX7_6", - "MONITOR_IMUX7_7", - "MONITOR_IMUX7_8", - "MONITOR_IMUX7_9", - "MONITOR_IMUX8_0", - "MONITOR_IMUX8_1", - "MONITOR_IMUX8_2", - "MONITOR_IMUX8_3", - "MONITOR_IMUX8_4", - "MONITOR_IMUX8_5", - "MONITOR_IMUX8_6", - "MONITOR_IMUX8_7", - "MONITOR_IMUX8_8", - "MONITOR_IMUX8_9", - "MONITOR_IMUX9_0", - "MONITOR_IMUX9_1", - "MONITOR_IMUX9_2", - "MONITOR_IMUX9_3", - "MONITOR_IMUX9_4", - "MONITOR_IMUX9_5", - "MONITOR_IMUX9_6", - "MONITOR_IMUX9_7", - "MONITOR_IMUX9_8", - "MONITOR_IMUX9_9", - "MONITOR_LH10_0", - "MONITOR_LH10_1", - "MONITOR_LH10_2", - "MONITOR_LH10_3", - "MONITOR_LH10_4", - "MONITOR_LH10_5", - "MONITOR_LH10_6", - "MONITOR_LH10_7", - "MONITOR_LH10_8", - "MONITOR_LH10_9", - "MONITOR_LH11_0", - "MONITOR_LH11_1", - "MONITOR_LH11_2", - "MONITOR_LH11_3", - "MONITOR_LH11_4", - "MONITOR_LH11_5", - "MONITOR_LH11_6", - "MONITOR_LH11_7", - "MONITOR_LH11_8", - "MONITOR_LH11_9", - "MONITOR_LH12_0", - "MONITOR_LH12_1", - "MONITOR_LH12_2", - "MONITOR_LH12_3", - "MONITOR_LH12_4", - "MONITOR_LH12_5", - "MONITOR_LH12_6", - "MONITOR_LH12_7", - "MONITOR_LH12_8", - "MONITOR_LH12_9", - "MONITOR_LH1_0", - "MONITOR_LH1_1", - "MONITOR_LH1_2", - "MONITOR_LH1_3", - "MONITOR_LH1_4", - "MONITOR_LH1_5", - "MONITOR_LH1_6", - "MONITOR_LH1_7", - "MONITOR_LH1_8", - "MONITOR_LH1_9", - "MONITOR_LH2_0", - "MONITOR_LH2_1", - "MONITOR_LH2_2", - "MONITOR_LH2_3", - "MONITOR_LH2_4", - "MONITOR_LH2_5", - "MONITOR_LH2_6", - "MONITOR_LH2_7", - "MONITOR_LH2_8", - "MONITOR_LH2_9", - "MONITOR_LH3_0", - "MONITOR_LH3_1", - "MONITOR_LH3_2", - "MONITOR_LH3_3", - "MONITOR_LH3_4", - "MONITOR_LH3_5", - "MONITOR_LH3_6", - "MONITOR_LH3_7", - "MONITOR_LH3_8", - "MONITOR_LH3_9", - "MONITOR_LH4_0", - "MONITOR_LH4_1", - "MONITOR_LH4_2", - "MONITOR_LH4_3", - "MONITOR_LH4_4", - "MONITOR_LH4_5", - "MONITOR_LH4_6", - "MONITOR_LH4_7", - "MONITOR_LH4_8", - "MONITOR_LH4_9", - "MONITOR_LH5_0", - "MONITOR_LH5_1", - "MONITOR_LH5_2", - "MONITOR_LH5_3", - "MONITOR_LH5_4", - "MONITOR_LH5_5", - "MONITOR_LH5_6", - "MONITOR_LH5_7", - "MONITOR_LH5_8", - "MONITOR_LH5_9", - "MONITOR_LH6_0", - "MONITOR_LH6_1", - "MONITOR_LH6_2", - "MONITOR_LH6_3", - "MONITOR_LH6_4", - "MONITOR_LH6_5", - "MONITOR_LH6_6", - "MONITOR_LH6_7", - "MONITOR_LH6_8", - "MONITOR_LH6_9", - "MONITOR_LH7_0", - "MONITOR_LH7_1", - "MONITOR_LH7_2", - "MONITOR_LH7_3", - "MONITOR_LH7_4", - "MONITOR_LH7_5", - "MONITOR_LH7_6", - "MONITOR_LH7_7", - "MONITOR_LH7_8", - "MONITOR_LH7_9", - "MONITOR_LH8_0", - "MONITOR_LH8_1", - "MONITOR_LH8_2", - "MONITOR_LH8_3", - "MONITOR_LH8_4", - "MONITOR_LH8_5", - "MONITOR_LH8_6", - "MONITOR_LH8_7", - "MONITOR_LH8_8", - "MONITOR_LH8_9", - "MONITOR_LH9_0", - "MONITOR_LH9_1", - "MONITOR_LH9_2", - "MONITOR_LH9_3", - "MONITOR_LH9_4", - "MONITOR_LH9_5", - "MONITOR_LH9_6", - "MONITOR_LH9_7", - "MONITOR_LH9_8", - "MONITOR_LH9_9", - "MONITOR_LOGIC_OUTS_B0_0", - "MONITOR_LOGIC_OUTS_B0_1", - "MONITOR_LOGIC_OUTS_B0_2", - "MONITOR_LOGIC_OUTS_B0_3", - "MONITOR_LOGIC_OUTS_B0_4", - "MONITOR_LOGIC_OUTS_B0_5", - "MONITOR_LOGIC_OUTS_B0_6", - "MONITOR_LOGIC_OUTS_B0_7", - "MONITOR_LOGIC_OUTS_B0_8", - "MONITOR_LOGIC_OUTS_B0_9", - "MONITOR_LOGIC_OUTS_B10_0", - "MONITOR_LOGIC_OUTS_B10_1", - "MONITOR_LOGIC_OUTS_B10_2", - "MONITOR_LOGIC_OUTS_B10_3", - "MONITOR_LOGIC_OUTS_B10_4", - "MONITOR_LOGIC_OUTS_B10_5", - "MONITOR_LOGIC_OUTS_B10_6", - "MONITOR_LOGIC_OUTS_B10_7", - "MONITOR_LOGIC_OUTS_B10_8", - "MONITOR_LOGIC_OUTS_B10_9", - "MONITOR_LOGIC_OUTS_B11_0", - "MONITOR_LOGIC_OUTS_B11_1", - "MONITOR_LOGIC_OUTS_B11_2", - "MONITOR_LOGIC_OUTS_B11_3", - "MONITOR_LOGIC_OUTS_B11_4", - "MONITOR_LOGIC_OUTS_B11_5", - "MONITOR_LOGIC_OUTS_B11_6", - "MONITOR_LOGIC_OUTS_B11_7", - "MONITOR_LOGIC_OUTS_B11_8", - "MONITOR_LOGIC_OUTS_B11_9", - "MONITOR_LOGIC_OUTS_B12_0", - "MONITOR_LOGIC_OUTS_B12_1", - "MONITOR_LOGIC_OUTS_B12_2", - "MONITOR_LOGIC_OUTS_B12_3", - "MONITOR_LOGIC_OUTS_B12_4", - "MONITOR_LOGIC_OUTS_B12_5", - "MONITOR_LOGIC_OUTS_B12_6", - "MONITOR_LOGIC_OUTS_B12_7", - "MONITOR_LOGIC_OUTS_B12_8", - "MONITOR_LOGIC_OUTS_B12_9", - "MONITOR_LOGIC_OUTS_B13_0", - "MONITOR_LOGIC_OUTS_B13_1", - "MONITOR_LOGIC_OUTS_B13_2", - "MONITOR_LOGIC_OUTS_B13_3", - "MONITOR_LOGIC_OUTS_B13_4", - "MONITOR_LOGIC_OUTS_B13_5", - "MONITOR_LOGIC_OUTS_B13_6", - "MONITOR_LOGIC_OUTS_B13_7", - "MONITOR_LOGIC_OUTS_B13_8", - "MONITOR_LOGIC_OUTS_B13_9", - "MONITOR_LOGIC_OUTS_B14_0", - "MONITOR_LOGIC_OUTS_B14_1", - "MONITOR_LOGIC_OUTS_B14_2", - "MONITOR_LOGIC_OUTS_B14_3", - "MONITOR_LOGIC_OUTS_B14_4", - "MONITOR_LOGIC_OUTS_B14_5", - "MONITOR_LOGIC_OUTS_B14_6", - "MONITOR_LOGIC_OUTS_B14_7", - "MONITOR_LOGIC_OUTS_B14_8", - "MONITOR_LOGIC_OUTS_B14_9", - "MONITOR_LOGIC_OUTS_B15_0", - "MONITOR_LOGIC_OUTS_B15_1", - "MONITOR_LOGIC_OUTS_B15_2", - "MONITOR_LOGIC_OUTS_B15_3", - "MONITOR_LOGIC_OUTS_B15_4", - "MONITOR_LOGIC_OUTS_B15_5", - "MONITOR_LOGIC_OUTS_B15_6", - "MONITOR_LOGIC_OUTS_B15_7", - "MONITOR_LOGIC_OUTS_B15_8", - "MONITOR_LOGIC_OUTS_B15_9", - "MONITOR_LOGIC_OUTS_B16_0", - "MONITOR_LOGIC_OUTS_B16_1", - "MONITOR_LOGIC_OUTS_B16_2", - "MONITOR_LOGIC_OUTS_B16_3", - "MONITOR_LOGIC_OUTS_B16_4", - "MONITOR_LOGIC_OUTS_B16_5", - "MONITOR_LOGIC_OUTS_B16_6", - "MONITOR_LOGIC_OUTS_B16_7", - "MONITOR_LOGIC_OUTS_B16_8", - "MONITOR_LOGIC_OUTS_B16_9", - "MONITOR_LOGIC_OUTS_B17_0", - "MONITOR_LOGIC_OUTS_B17_1", - "MONITOR_LOGIC_OUTS_B17_2", - "MONITOR_LOGIC_OUTS_B17_3", - "MONITOR_LOGIC_OUTS_B17_4", - "MONITOR_LOGIC_OUTS_B17_5", - "MONITOR_LOGIC_OUTS_B17_6", - "MONITOR_LOGIC_OUTS_B17_7", - "MONITOR_LOGIC_OUTS_B17_8", - "MONITOR_LOGIC_OUTS_B17_9", - "MONITOR_LOGIC_OUTS_B18_0", - "MONITOR_LOGIC_OUTS_B18_1", - "MONITOR_LOGIC_OUTS_B18_2", - "MONITOR_LOGIC_OUTS_B18_3", - "MONITOR_LOGIC_OUTS_B18_4", - "MONITOR_LOGIC_OUTS_B18_5", - "MONITOR_LOGIC_OUTS_B18_6", - "MONITOR_LOGIC_OUTS_B18_7", - "MONITOR_LOGIC_OUTS_B18_8", - "MONITOR_LOGIC_OUTS_B18_9", - "MONITOR_LOGIC_OUTS_B19_0", - "MONITOR_LOGIC_OUTS_B19_1", - "MONITOR_LOGIC_OUTS_B19_2", - "MONITOR_LOGIC_OUTS_B19_3", - "MONITOR_LOGIC_OUTS_B19_4", - "MONITOR_LOGIC_OUTS_B19_5", - "MONITOR_LOGIC_OUTS_B19_6", - "MONITOR_LOGIC_OUTS_B19_7", - "MONITOR_LOGIC_OUTS_B19_8", - "MONITOR_LOGIC_OUTS_B19_9", - "MONITOR_LOGIC_OUTS_B1_0", - "MONITOR_LOGIC_OUTS_B1_1", - "MONITOR_LOGIC_OUTS_B1_2", - "MONITOR_LOGIC_OUTS_B1_3", - "MONITOR_LOGIC_OUTS_B1_4", - "MONITOR_LOGIC_OUTS_B1_5", - "MONITOR_LOGIC_OUTS_B1_6", - "MONITOR_LOGIC_OUTS_B1_7", - "MONITOR_LOGIC_OUTS_B1_8", - "MONITOR_LOGIC_OUTS_B1_9", - "MONITOR_LOGIC_OUTS_B20_0", - "MONITOR_LOGIC_OUTS_B20_1", - "MONITOR_LOGIC_OUTS_B20_2", - "MONITOR_LOGIC_OUTS_B20_3", - "MONITOR_LOGIC_OUTS_B20_4", - "MONITOR_LOGIC_OUTS_B20_5", - "MONITOR_LOGIC_OUTS_B20_6", - "MONITOR_LOGIC_OUTS_B20_7", - "MONITOR_LOGIC_OUTS_B20_8", - "MONITOR_LOGIC_OUTS_B20_9", - "MONITOR_LOGIC_OUTS_B21_0", - "MONITOR_LOGIC_OUTS_B21_1", - "MONITOR_LOGIC_OUTS_B21_2", - "MONITOR_LOGIC_OUTS_B21_3", - "MONITOR_LOGIC_OUTS_B21_4", - "MONITOR_LOGIC_OUTS_B21_5", - "MONITOR_LOGIC_OUTS_B21_6", - "MONITOR_LOGIC_OUTS_B21_7", - "MONITOR_LOGIC_OUTS_B21_8", - "MONITOR_LOGIC_OUTS_B21_9", - "MONITOR_LOGIC_OUTS_B22_0", - "MONITOR_LOGIC_OUTS_B22_1", - "MONITOR_LOGIC_OUTS_B22_2", - "MONITOR_LOGIC_OUTS_B22_3", - "MONITOR_LOGIC_OUTS_B22_4", - "MONITOR_LOGIC_OUTS_B22_5", - "MONITOR_LOGIC_OUTS_B22_6", - "MONITOR_LOGIC_OUTS_B22_7", - "MONITOR_LOGIC_OUTS_B22_8", - "MONITOR_LOGIC_OUTS_B22_9", - "MONITOR_LOGIC_OUTS_B23_0", - "MONITOR_LOGIC_OUTS_B23_1", - "MONITOR_LOGIC_OUTS_B23_2", - "MONITOR_LOGIC_OUTS_B23_3", - "MONITOR_LOGIC_OUTS_B23_4", - "MONITOR_LOGIC_OUTS_B23_5", - "MONITOR_LOGIC_OUTS_B23_6", - "MONITOR_LOGIC_OUTS_B23_7", - "MONITOR_LOGIC_OUTS_B23_8", - "MONITOR_LOGIC_OUTS_B23_9", - "MONITOR_LOGIC_OUTS_B2_0", - "MONITOR_LOGIC_OUTS_B2_1", - "MONITOR_LOGIC_OUTS_B2_2", - "MONITOR_LOGIC_OUTS_B2_3", - "MONITOR_LOGIC_OUTS_B2_4", - "MONITOR_LOGIC_OUTS_B2_5", - "MONITOR_LOGIC_OUTS_B2_6", - "MONITOR_LOGIC_OUTS_B2_7", - "MONITOR_LOGIC_OUTS_B2_8", - "MONITOR_LOGIC_OUTS_B2_9", - "MONITOR_LOGIC_OUTS_B3_0", - "MONITOR_LOGIC_OUTS_B3_1", - "MONITOR_LOGIC_OUTS_B3_2", - "MONITOR_LOGIC_OUTS_B3_3", - "MONITOR_LOGIC_OUTS_B3_4", - "MONITOR_LOGIC_OUTS_B3_5", - "MONITOR_LOGIC_OUTS_B3_6", - "MONITOR_LOGIC_OUTS_B3_7", - "MONITOR_LOGIC_OUTS_B3_8", - "MONITOR_LOGIC_OUTS_B3_9", - "MONITOR_LOGIC_OUTS_B4_0", - "MONITOR_LOGIC_OUTS_B4_1", - "MONITOR_LOGIC_OUTS_B4_2", - "MONITOR_LOGIC_OUTS_B4_3", - "MONITOR_LOGIC_OUTS_B4_4", - "MONITOR_LOGIC_OUTS_B4_5", - "MONITOR_LOGIC_OUTS_B4_6", - "MONITOR_LOGIC_OUTS_B4_7", - "MONITOR_LOGIC_OUTS_B4_8", - "MONITOR_LOGIC_OUTS_B4_9", - "MONITOR_LOGIC_OUTS_B5_0", - "MONITOR_LOGIC_OUTS_B5_1", - "MONITOR_LOGIC_OUTS_B5_2", - "MONITOR_LOGIC_OUTS_B5_3", - "MONITOR_LOGIC_OUTS_B5_4", - "MONITOR_LOGIC_OUTS_B5_5", - "MONITOR_LOGIC_OUTS_B5_6", - "MONITOR_LOGIC_OUTS_B5_7", - "MONITOR_LOGIC_OUTS_B5_8", - "MONITOR_LOGIC_OUTS_B5_9", - "MONITOR_LOGIC_OUTS_B6_0", - "MONITOR_LOGIC_OUTS_B6_1", - "MONITOR_LOGIC_OUTS_B6_2", - "MONITOR_LOGIC_OUTS_B6_3", - "MONITOR_LOGIC_OUTS_B6_4", - "MONITOR_LOGIC_OUTS_B6_5", - "MONITOR_LOGIC_OUTS_B6_6", - "MONITOR_LOGIC_OUTS_B6_7", - "MONITOR_LOGIC_OUTS_B6_8", - "MONITOR_LOGIC_OUTS_B6_9", - "MONITOR_LOGIC_OUTS_B7_0", - "MONITOR_LOGIC_OUTS_B7_1", - "MONITOR_LOGIC_OUTS_B7_2", - "MONITOR_LOGIC_OUTS_B7_3", - "MONITOR_LOGIC_OUTS_B7_4", - "MONITOR_LOGIC_OUTS_B7_5", - "MONITOR_LOGIC_OUTS_B7_6", - "MONITOR_LOGIC_OUTS_B7_7", - "MONITOR_LOGIC_OUTS_B7_8", - "MONITOR_LOGIC_OUTS_B7_9", - "MONITOR_LOGIC_OUTS_B8_0", - "MONITOR_LOGIC_OUTS_B8_1", - "MONITOR_LOGIC_OUTS_B8_2", - "MONITOR_LOGIC_OUTS_B8_3", - "MONITOR_LOGIC_OUTS_B8_4", - "MONITOR_LOGIC_OUTS_B8_5", - "MONITOR_LOGIC_OUTS_B8_6", - "MONITOR_LOGIC_OUTS_B8_7", - "MONITOR_LOGIC_OUTS_B8_8", - "MONITOR_LOGIC_OUTS_B8_9", - "MONITOR_LOGIC_OUTS_B9_0", - "MONITOR_LOGIC_OUTS_B9_1", - "MONITOR_LOGIC_OUTS_B9_2", - "MONITOR_LOGIC_OUTS_B9_3", - "MONITOR_LOGIC_OUTS_B9_4", - "MONITOR_LOGIC_OUTS_B9_5", - "MONITOR_LOGIC_OUTS_B9_6", - "MONITOR_LOGIC_OUTS_B9_7", - "MONITOR_LOGIC_OUTS_B9_8", - "MONITOR_LOGIC_OUTS_B9_9", - "MONITOR_NE2A0_0", - "MONITOR_NE2A0_1", - "MONITOR_NE2A0_2", - "MONITOR_NE2A0_3", - "MONITOR_NE2A0_4", - "MONITOR_NE2A0_5", - "MONITOR_NE2A0_6", - "MONITOR_NE2A0_7", - "MONITOR_NE2A0_8", - "MONITOR_NE2A0_9", - "MONITOR_NE2A1_0", - "MONITOR_NE2A1_1", - "MONITOR_NE2A1_2", - "MONITOR_NE2A1_3", - "MONITOR_NE2A1_4", - "MONITOR_NE2A1_5", - "MONITOR_NE2A1_6", - "MONITOR_NE2A1_7", - "MONITOR_NE2A1_8", - "MONITOR_NE2A1_9", - "MONITOR_NE2A2_0", - "MONITOR_NE2A2_1", - "MONITOR_NE2A2_2", - "MONITOR_NE2A2_3", - "MONITOR_NE2A2_4", - "MONITOR_NE2A2_5", - "MONITOR_NE2A2_6", - "MONITOR_NE2A2_7", - "MONITOR_NE2A2_8", - "MONITOR_NE2A2_9", - "MONITOR_NE2A3_0", - "MONITOR_NE2A3_1", - "MONITOR_NE2A3_2", - "MONITOR_NE2A3_3", - "MONITOR_NE2A3_4", - "MONITOR_NE2A3_5", - "MONITOR_NE2A3_6", - "MONITOR_NE2A3_7", - "MONITOR_NE2A3_8", - "MONITOR_NE2A3_9", - "MONITOR_NE4BEG0_0", - "MONITOR_NE4BEG0_1", - "MONITOR_NE4BEG0_2", - "MONITOR_NE4BEG0_3", - "MONITOR_NE4BEG0_4", - "MONITOR_NE4BEG0_5", - "MONITOR_NE4BEG0_6", - "MONITOR_NE4BEG0_7", - "MONITOR_NE4BEG0_8", - "MONITOR_NE4BEG0_9", - "MONITOR_NE4BEG1_0", - "MONITOR_NE4BEG1_1", - "MONITOR_NE4BEG1_2", - "MONITOR_NE4BEG1_3", - "MONITOR_NE4BEG1_4", - "MONITOR_NE4BEG1_5", - "MONITOR_NE4BEG1_6", - "MONITOR_NE4BEG1_7", - "MONITOR_NE4BEG1_8", - "MONITOR_NE4BEG1_9", - "MONITOR_NE4BEG2_0", - "MONITOR_NE4BEG2_1", - "MONITOR_NE4BEG2_2", - "MONITOR_NE4BEG2_3", - "MONITOR_NE4BEG2_4", - "MONITOR_NE4BEG2_5", - "MONITOR_NE4BEG2_6", - "MONITOR_NE4BEG2_7", - "MONITOR_NE4BEG2_8", - "MONITOR_NE4BEG2_9", - "MONITOR_NE4BEG3_0", - "MONITOR_NE4BEG3_1", - "MONITOR_NE4BEG3_2", - "MONITOR_NE4BEG3_3", - "MONITOR_NE4BEG3_4", - "MONITOR_NE4BEG3_5", - "MONITOR_NE4BEG3_6", - "MONITOR_NE4BEG3_7", - "MONITOR_NE4BEG3_8", - "MONITOR_NE4BEG3_9", - "MONITOR_NE4C0_0", - "MONITOR_NE4C0_1", - "MONITOR_NE4C0_2", - "MONITOR_NE4C0_3", - "MONITOR_NE4C0_4", - "MONITOR_NE4C0_5", - "MONITOR_NE4C0_6", - "MONITOR_NE4C0_7", - "MONITOR_NE4C0_8", - "MONITOR_NE4C0_9", - "MONITOR_NE4C1_0", - "MONITOR_NE4C1_1", - "MONITOR_NE4C1_2", - "MONITOR_NE4C1_3", - "MONITOR_NE4C1_4", - "MONITOR_NE4C1_5", - "MONITOR_NE4C1_6", - "MONITOR_NE4C1_7", - "MONITOR_NE4C1_8", - "MONITOR_NE4C1_9", - "MONITOR_NE4C2_0", - "MONITOR_NE4C2_1", - "MONITOR_NE4C2_2", - "MONITOR_NE4C2_3", - "MONITOR_NE4C2_4", - "MONITOR_NE4C2_5", - "MONITOR_NE4C2_6", - "MONITOR_NE4C2_7", - "MONITOR_NE4C2_8", - "MONITOR_NE4C2_9", - "MONITOR_NE4C3_0", - "MONITOR_NE4C3_1", - "MONITOR_NE4C3_2", - "MONITOR_NE4C3_3", - "MONITOR_NE4C3_4", - "MONITOR_NE4C3_5", - "MONITOR_NE4C3_6", - "MONITOR_NE4C3_7", - "MONITOR_NE4C3_8", - "MONITOR_NE4C3_9", - "MONITOR_NW2A0_0", - "MONITOR_NW2A0_1", - "MONITOR_NW2A0_2", - "MONITOR_NW2A0_3", - "MONITOR_NW2A0_4", - "MONITOR_NW2A0_5", - "MONITOR_NW2A0_6", - "MONITOR_NW2A0_7", - "MONITOR_NW2A0_8", - "MONITOR_NW2A0_9", - "MONITOR_NW2A1_0", - "MONITOR_NW2A1_1", - "MONITOR_NW2A1_2", - "MONITOR_NW2A1_3", - "MONITOR_NW2A1_4", - "MONITOR_NW2A1_5", - "MONITOR_NW2A1_6", - "MONITOR_NW2A1_7", - "MONITOR_NW2A1_8", - "MONITOR_NW2A1_9", - "MONITOR_NW2A2_0", - "MONITOR_NW2A2_1", - "MONITOR_NW2A2_2", - "MONITOR_NW2A2_3", - "MONITOR_NW2A2_4", - "MONITOR_NW2A2_5", - "MONITOR_NW2A2_6", - "MONITOR_NW2A2_7", - "MONITOR_NW2A2_8", - "MONITOR_NW2A2_9", - "MONITOR_NW2A3_0", - "MONITOR_NW2A3_1", - "MONITOR_NW2A3_2", - "MONITOR_NW2A3_3", - "MONITOR_NW2A3_4", - "MONITOR_NW2A3_5", - "MONITOR_NW2A3_6", - "MONITOR_NW2A3_7", - "MONITOR_NW2A3_8", - "MONITOR_NW2A3_9", - "MONITOR_NW4A0_0", - "MONITOR_NW4A0_1", - "MONITOR_NW4A0_2", - "MONITOR_NW4A0_3", - "MONITOR_NW4A0_4", - "MONITOR_NW4A0_5", - "MONITOR_NW4A0_6", - "MONITOR_NW4A0_7", - "MONITOR_NW4A0_8", - "MONITOR_NW4A0_9", - "MONITOR_NW4A1_0", - "MONITOR_NW4A1_1", - "MONITOR_NW4A1_2", - "MONITOR_NW4A1_3", - "MONITOR_NW4A1_4", - "MONITOR_NW4A1_5", - "MONITOR_NW4A1_6", - "MONITOR_NW4A1_7", - "MONITOR_NW4A1_8", - "MONITOR_NW4A1_9", - "MONITOR_NW4A2_0", - "MONITOR_NW4A2_1", - "MONITOR_NW4A2_2", - "MONITOR_NW4A2_3", - "MONITOR_NW4A2_4", - "MONITOR_NW4A2_5", - "MONITOR_NW4A2_6", - "MONITOR_NW4A2_7", - "MONITOR_NW4A2_8", - "MONITOR_NW4A2_9", - "MONITOR_NW4A3_0", - "MONITOR_NW4A3_1", - "MONITOR_NW4A3_2", - "MONITOR_NW4A3_3", - "MONITOR_NW4A3_4", - "MONITOR_NW4A3_5", - "MONITOR_NW4A3_6", - "MONITOR_NW4A3_7", - "MONITOR_NW4A3_8", - "MONITOR_NW4A3_9", - "MONITOR_NW4END0_0", - "MONITOR_NW4END0_1", - "MONITOR_NW4END0_2", - "MONITOR_NW4END0_3", - "MONITOR_NW4END0_4", - "MONITOR_NW4END0_5", - "MONITOR_NW4END0_6", - "MONITOR_NW4END0_7", - "MONITOR_NW4END0_8", - "MONITOR_NW4END0_9", - "MONITOR_NW4END1_0", - "MONITOR_NW4END1_1", - "MONITOR_NW4END1_2", - "MONITOR_NW4END1_3", - "MONITOR_NW4END1_4", - "MONITOR_NW4END1_5", - "MONITOR_NW4END1_6", - "MONITOR_NW4END1_7", - "MONITOR_NW4END1_8", - "MONITOR_NW4END1_9", - "MONITOR_NW4END2_0", - "MONITOR_NW4END2_1", - "MONITOR_NW4END2_2", - "MONITOR_NW4END2_3", - "MONITOR_NW4END2_4", - "MONITOR_NW4END2_5", - "MONITOR_NW4END2_6", - "MONITOR_NW4END2_7", - "MONITOR_NW4END2_8", - "MONITOR_NW4END2_9", - "MONITOR_NW4END3_0", - "MONITOR_NW4END3_1", - "MONITOR_NW4END3_2", - "MONITOR_NW4END3_3", - "MONITOR_NW4END3_4", - "MONITOR_NW4END3_5", - "MONITOR_NW4END3_6", - "MONITOR_NW4END3_7", - "MONITOR_NW4END3_8", - "MONITOR_NW4END3_9", - "MONITOR_SE2A0_0", - "MONITOR_SE2A0_1", - "MONITOR_SE2A0_2", - "MONITOR_SE2A0_3", - "MONITOR_SE2A0_4", - "MONITOR_SE2A0_5", - "MONITOR_SE2A0_6", - "MONITOR_SE2A0_7", - "MONITOR_SE2A0_8", - "MONITOR_SE2A0_9", - "MONITOR_SE2A1_0", - "MONITOR_SE2A1_1", - "MONITOR_SE2A1_2", - "MONITOR_SE2A1_3", - "MONITOR_SE2A1_4", - "MONITOR_SE2A1_5", - "MONITOR_SE2A1_6", - "MONITOR_SE2A1_7", - "MONITOR_SE2A1_8", - "MONITOR_SE2A1_9", - "MONITOR_SE2A2_0", - "MONITOR_SE2A2_1", - "MONITOR_SE2A2_2", - "MONITOR_SE2A2_3", - "MONITOR_SE2A2_4", - "MONITOR_SE2A2_5", - "MONITOR_SE2A2_6", - "MONITOR_SE2A2_7", - "MONITOR_SE2A2_8", - "MONITOR_SE2A2_9", - "MONITOR_SE2A3_0", - "MONITOR_SE2A3_1", - "MONITOR_SE2A3_2", - "MONITOR_SE2A3_3", - "MONITOR_SE2A3_4", - "MONITOR_SE2A3_5", - "MONITOR_SE2A3_6", - "MONITOR_SE2A3_7", - "MONITOR_SE2A3_8", - "MONITOR_SE2A3_9", - "MONITOR_SE4BEG0_0", - "MONITOR_SE4BEG0_1", - "MONITOR_SE4BEG0_2", - "MONITOR_SE4BEG0_3", - "MONITOR_SE4BEG0_4", - "MONITOR_SE4BEG0_5", - "MONITOR_SE4BEG0_6", - "MONITOR_SE4BEG0_7", - "MONITOR_SE4BEG0_8", - "MONITOR_SE4BEG0_9", - "MONITOR_SE4BEG1_0", - "MONITOR_SE4BEG1_1", - "MONITOR_SE4BEG1_2", - "MONITOR_SE4BEG1_3", - "MONITOR_SE4BEG1_4", - "MONITOR_SE4BEG1_5", - "MONITOR_SE4BEG1_6", - "MONITOR_SE4BEG1_7", - "MONITOR_SE4BEG1_8", - "MONITOR_SE4BEG1_9", - "MONITOR_SE4BEG2_0", - "MONITOR_SE4BEG2_1", - "MONITOR_SE4BEG2_2", - "MONITOR_SE4BEG2_3", - "MONITOR_SE4BEG2_4", - "MONITOR_SE4BEG2_5", - "MONITOR_SE4BEG2_6", - "MONITOR_SE4BEG2_7", - "MONITOR_SE4BEG2_8", - "MONITOR_SE4BEG2_9", - "MONITOR_SE4BEG3_0", - "MONITOR_SE4BEG3_1", - "MONITOR_SE4BEG3_2", - "MONITOR_SE4BEG3_3", - "MONITOR_SE4BEG3_4", - "MONITOR_SE4BEG3_5", - "MONITOR_SE4BEG3_6", - "MONITOR_SE4BEG3_7", - "MONITOR_SE4BEG3_8", - "MONITOR_SE4BEG3_9", - "MONITOR_SE4C0_0", - "MONITOR_SE4C0_1", - "MONITOR_SE4C0_2", - "MONITOR_SE4C0_3", - "MONITOR_SE4C0_4", - "MONITOR_SE4C0_5", - "MONITOR_SE4C0_6", - "MONITOR_SE4C0_7", - "MONITOR_SE4C0_8", - "MONITOR_SE4C0_9", - "MONITOR_SE4C1_0", - "MONITOR_SE4C1_1", - "MONITOR_SE4C1_2", - "MONITOR_SE4C1_3", - "MONITOR_SE4C1_4", - "MONITOR_SE4C1_5", - "MONITOR_SE4C1_6", - "MONITOR_SE4C1_7", - "MONITOR_SE4C1_8", - "MONITOR_SE4C1_9", - "MONITOR_SE4C2_0", - "MONITOR_SE4C2_1", - "MONITOR_SE4C2_2", - "MONITOR_SE4C2_3", - "MONITOR_SE4C2_4", - "MONITOR_SE4C2_5", - "MONITOR_SE4C2_6", - "MONITOR_SE4C2_7", - "MONITOR_SE4C2_8", - "MONITOR_SE4C2_9", - "MONITOR_SE4C3_0", - "MONITOR_SE4C3_1", - "MONITOR_SE4C3_2", - "MONITOR_SE4C3_3", - "MONITOR_SE4C3_4", - "MONITOR_SE4C3_5", - "MONITOR_SE4C3_6", - "MONITOR_SE4C3_7", - "MONITOR_SE4C3_8", - "MONITOR_SE4C3_9", - "MONITOR_SW2A0_0", - "MONITOR_SW2A0_1", - "MONITOR_SW2A0_2", - "MONITOR_SW2A0_3", - "MONITOR_SW2A0_4", - "MONITOR_SW2A0_5", - "MONITOR_SW2A0_6", - "MONITOR_SW2A0_7", - "MONITOR_SW2A0_8", - "MONITOR_SW2A0_9", - "MONITOR_SW2A1_0", - "MONITOR_SW2A1_1", - "MONITOR_SW2A1_2", - "MONITOR_SW2A1_3", - "MONITOR_SW2A1_4", - "MONITOR_SW2A1_5", - "MONITOR_SW2A1_6", - "MONITOR_SW2A1_7", - "MONITOR_SW2A1_8", - "MONITOR_SW2A1_9", - "MONITOR_SW2A2_0", - "MONITOR_SW2A2_1", - "MONITOR_SW2A2_2", - "MONITOR_SW2A2_3", - "MONITOR_SW2A2_4", - "MONITOR_SW2A2_5", - "MONITOR_SW2A2_6", - "MONITOR_SW2A2_7", - "MONITOR_SW2A2_8", - "MONITOR_SW2A2_9", - "MONITOR_SW2A3_0", - "MONITOR_SW2A3_1", - "MONITOR_SW2A3_2", - "MONITOR_SW2A3_3", - "MONITOR_SW2A3_4", - "MONITOR_SW2A3_5", - "MONITOR_SW2A3_6", - "MONITOR_SW2A3_7", - "MONITOR_SW2A3_8", - "MONITOR_SW2A3_9", - "MONITOR_SW4A0_0", - "MONITOR_SW4A0_1", - "MONITOR_SW4A0_2", - "MONITOR_SW4A0_3", - "MONITOR_SW4A0_4", - "MONITOR_SW4A0_5", - "MONITOR_SW4A0_6", - "MONITOR_SW4A0_7", - "MONITOR_SW4A0_8", - "MONITOR_SW4A0_9", - "MONITOR_SW4A1_0", - "MONITOR_SW4A1_1", - "MONITOR_SW4A1_2", - "MONITOR_SW4A1_3", - "MONITOR_SW4A1_4", - "MONITOR_SW4A1_5", - "MONITOR_SW4A1_6", - "MONITOR_SW4A1_7", - "MONITOR_SW4A1_8", - "MONITOR_SW4A1_9", - "MONITOR_SW4A2_0", - "MONITOR_SW4A2_1", - "MONITOR_SW4A2_2", - "MONITOR_SW4A2_3", - "MONITOR_SW4A2_4", - "MONITOR_SW4A2_5", - "MONITOR_SW4A2_6", - "MONITOR_SW4A2_7", - "MONITOR_SW4A2_8", - "MONITOR_SW4A2_9", - "MONITOR_SW4A3_0", - "MONITOR_SW4A3_1", - "MONITOR_SW4A3_2", - "MONITOR_SW4A3_3", - "MONITOR_SW4A3_4", - "MONITOR_SW4A3_5", - "MONITOR_SW4A3_6", - "MONITOR_SW4A3_7", - "MONITOR_SW4A3_8", - "MONITOR_SW4A3_9", - "MONITOR_SW4END0_0", - "MONITOR_SW4END0_1", - "MONITOR_SW4END0_2", - "MONITOR_SW4END0_3", - "MONITOR_SW4END0_4", - "MONITOR_SW4END0_5", - "MONITOR_SW4END0_6", - "MONITOR_SW4END0_7", - "MONITOR_SW4END0_8", - "MONITOR_SW4END0_9", - "MONITOR_SW4END1_0", - "MONITOR_SW4END1_1", - "MONITOR_SW4END1_2", - "MONITOR_SW4END1_3", - "MONITOR_SW4END1_4", - "MONITOR_SW4END1_5", - "MONITOR_SW4END1_6", - "MONITOR_SW4END1_7", - "MONITOR_SW4END1_8", - "MONITOR_SW4END1_9", - "MONITOR_SW4END2_0", - "MONITOR_SW4END2_1", - "MONITOR_SW4END2_2", - "MONITOR_SW4END2_3", - "MONITOR_SW4END2_4", - "MONITOR_SW4END2_5", - "MONITOR_SW4END2_6", - "MONITOR_SW4END2_7", - "MONITOR_SW4END2_8", - "MONITOR_SW4END2_9", - "MONITOR_SW4END3_0", - "MONITOR_SW4END3_1", - "MONITOR_SW4END3_2", - "MONITOR_SW4END3_3", - "MONITOR_SW4END3_4", - "MONITOR_SW4END3_5", - "MONITOR_SW4END3_6", - "MONITOR_SW4END3_7", - "MONITOR_SW4END3_8", - "MONITOR_SW4END3_9", - "MONITOR_VERT_VAUXN0", - "MONITOR_VERT_VAUXN1", - "MONITOR_VERT_VAUXN10", - "MONITOR_VERT_VAUXN11", - "MONITOR_VERT_VAUXN12", - "MONITOR_VERT_VAUXN13", - "MONITOR_VERT_VAUXN14", - "MONITOR_VERT_VAUXN15", - "MONITOR_VERT_VAUXN2", - "MONITOR_VERT_VAUXN3", - "MONITOR_VERT_VAUXN4", - "MONITOR_VERT_VAUXN5", - "MONITOR_VERT_VAUXN6", - "MONITOR_VERT_VAUXN7", - "MONITOR_VERT_VAUXN8", - "MONITOR_VERT_VAUXN9", - "MONITOR_VERT_VAUXP0", - "MONITOR_VERT_VAUXP1", - "MONITOR_VERT_VAUXP10", - "MONITOR_VERT_VAUXP11", - "MONITOR_VERT_VAUXP12", - "MONITOR_VERT_VAUXP13", - "MONITOR_VERT_VAUXP14", - "MONITOR_VERT_VAUXP15", - "MONITOR_VERT_VAUXP2", - "MONITOR_VERT_VAUXP3", - "MONITOR_VERT_VAUXP4", - "MONITOR_VERT_VAUXP5", - "MONITOR_VERT_VAUXP6", - "MONITOR_VERT_VAUXP7", - "MONITOR_VERT_VAUXP8", - "MONITOR_VERT_VAUXP9", - "MONITOR_WL1END0_0", - "MONITOR_WL1END0_1", - "MONITOR_WL1END0_2", - "MONITOR_WL1END0_3", - "MONITOR_WL1END0_4", - "MONITOR_WL1END0_5", - "MONITOR_WL1END0_6", - "MONITOR_WL1END0_7", - "MONITOR_WL1END0_8", - "MONITOR_WL1END0_9", - "MONITOR_WL1END1_0", - "MONITOR_WL1END1_1", - "MONITOR_WL1END1_2", - "MONITOR_WL1END1_3", - "MONITOR_WL1END1_4", - "MONITOR_WL1END1_5", - "MONITOR_WL1END1_6", - "MONITOR_WL1END1_7", - "MONITOR_WL1END1_8", - "MONITOR_WL1END1_9", - "MONITOR_WL1END2_0", - "MONITOR_WL1END2_1", - "MONITOR_WL1END2_2", - "MONITOR_WL1END2_3", - "MONITOR_WL1END2_4", - "MONITOR_WL1END2_5", - "MONITOR_WL1END2_6", - "MONITOR_WL1END2_7", - "MONITOR_WL1END2_8", - "MONITOR_WL1END2_9", - "MONITOR_WL1END3_0", - "MONITOR_WL1END3_1", - "MONITOR_WL1END3_2", - "MONITOR_WL1END3_3", - "MONITOR_WL1END3_4", - "MONITOR_WL1END3_5", - "MONITOR_WL1END3_6", - "MONITOR_WL1END3_7", - "MONITOR_WL1END3_8", - "MONITOR_WL1END3_9", - "MONITOR_WR1END0_0", - "MONITOR_WR1END0_1", - "MONITOR_WR1END0_2", - "MONITOR_WR1END0_3", - "MONITOR_WR1END0_4", - "MONITOR_WR1END0_5", - "MONITOR_WR1END0_6", - "MONITOR_WR1END0_7", - "MONITOR_WR1END0_8", - "MONITOR_WR1END0_9", - "MONITOR_WR1END1_0", - "MONITOR_WR1END1_1", - "MONITOR_WR1END1_2", - "MONITOR_WR1END1_3", - "MONITOR_WR1END1_4", - "MONITOR_WR1END1_5", - "MONITOR_WR1END1_6", - "MONITOR_WR1END1_7", - "MONITOR_WR1END1_8", - "MONITOR_WR1END1_9", - "MONITOR_WR1END2_0", - "MONITOR_WR1END2_1", - "MONITOR_WR1END2_2", - "MONITOR_WR1END2_3", - "MONITOR_WR1END2_4", - "MONITOR_WR1END2_5", - "MONITOR_WR1END2_6", - "MONITOR_WR1END2_7", - "MONITOR_WR1END2_8", - "MONITOR_WR1END2_9", - "MONITOR_WR1END3_0", - "MONITOR_WR1END3_1", - "MONITOR_WR1END3_2", - "MONITOR_WR1END3_3", - "MONITOR_WR1END3_4", - "MONITOR_WR1END3_5", - "MONITOR_WR1END3_6", - "MONITOR_WR1END3_7", - "MONITOR_WR1END3_8", - "MONITOR_WR1END3_9", - "MONITOR_WW2A0_0", - "MONITOR_WW2A0_1", - "MONITOR_WW2A0_2", - "MONITOR_WW2A0_3", - "MONITOR_WW2A0_4", - "MONITOR_WW2A0_5", - "MONITOR_WW2A0_6", - "MONITOR_WW2A0_7", - "MONITOR_WW2A0_8", - "MONITOR_WW2A0_9", - "MONITOR_WW2A1_0", - "MONITOR_WW2A1_1", - "MONITOR_WW2A1_2", - "MONITOR_WW2A1_3", - "MONITOR_WW2A1_4", - "MONITOR_WW2A1_5", - "MONITOR_WW2A1_6", - "MONITOR_WW2A1_7", - "MONITOR_WW2A1_8", - "MONITOR_WW2A1_9", - "MONITOR_WW2A2_0", - "MONITOR_WW2A2_1", - "MONITOR_WW2A2_2", - "MONITOR_WW2A2_3", - "MONITOR_WW2A2_4", - "MONITOR_WW2A2_5", - "MONITOR_WW2A2_6", - "MONITOR_WW2A2_7", - "MONITOR_WW2A2_8", - "MONITOR_WW2A2_9", - "MONITOR_WW2A3_0", - "MONITOR_WW2A3_1", - "MONITOR_WW2A3_2", - "MONITOR_WW2A3_3", - "MONITOR_WW2A3_4", - "MONITOR_WW2A3_5", - "MONITOR_WW2A3_6", - "MONITOR_WW2A3_7", - "MONITOR_WW2A3_8", - "MONITOR_WW2A3_9", - "MONITOR_WW2END0_0", - "MONITOR_WW2END0_1", - "MONITOR_WW2END0_2", - "MONITOR_WW2END0_3", - "MONITOR_WW2END0_4", - "MONITOR_WW2END0_5", - "MONITOR_WW2END0_6", - "MONITOR_WW2END0_7", - "MONITOR_WW2END0_8", - "MONITOR_WW2END0_9", - "MONITOR_WW2END1_0", - "MONITOR_WW2END1_1", - "MONITOR_WW2END1_2", - "MONITOR_WW2END1_3", - "MONITOR_WW2END1_4", - "MONITOR_WW2END1_5", - "MONITOR_WW2END1_6", - "MONITOR_WW2END1_7", - "MONITOR_WW2END1_8", - "MONITOR_WW2END1_9", - "MONITOR_WW2END2_0", - "MONITOR_WW2END2_1", - "MONITOR_WW2END2_2", - "MONITOR_WW2END2_3", - "MONITOR_WW2END2_4", - "MONITOR_WW2END2_5", - "MONITOR_WW2END2_6", - "MONITOR_WW2END2_7", - "MONITOR_WW2END2_8", - "MONITOR_WW2END2_9", - "MONITOR_WW2END3_0", - "MONITOR_WW2END3_1", - "MONITOR_WW2END3_2", - "MONITOR_WW2END3_3", - "MONITOR_WW2END3_4", - "MONITOR_WW2END3_5", - "MONITOR_WW2END3_6", - "MONITOR_WW2END3_7", - "MONITOR_WW2END3_8", - "MONITOR_WW2END3_9", - "MONITOR_WW4A0_0", - "MONITOR_WW4A0_1", - "MONITOR_WW4A0_2", - "MONITOR_WW4A0_3", - "MONITOR_WW4A0_4", - "MONITOR_WW4A0_5", - "MONITOR_WW4A0_6", - "MONITOR_WW4A0_7", - "MONITOR_WW4A0_8", - "MONITOR_WW4A0_9", - "MONITOR_WW4A1_0", - "MONITOR_WW4A1_1", - "MONITOR_WW4A1_2", - "MONITOR_WW4A1_3", - "MONITOR_WW4A1_4", - "MONITOR_WW4A1_5", - "MONITOR_WW4A1_6", - "MONITOR_WW4A1_7", - "MONITOR_WW4A1_8", - "MONITOR_WW4A1_9", - "MONITOR_WW4A2_0", - "MONITOR_WW4A2_1", - "MONITOR_WW4A2_2", - "MONITOR_WW4A2_3", - "MONITOR_WW4A2_4", - "MONITOR_WW4A2_5", - "MONITOR_WW4A2_6", - "MONITOR_WW4A2_7", - "MONITOR_WW4A2_8", - "MONITOR_WW4A2_9", - "MONITOR_WW4A3_0", - "MONITOR_WW4A3_1", - "MONITOR_WW4A3_2", - "MONITOR_WW4A3_3", - "MONITOR_WW4A3_4", - "MONITOR_WW4A3_5", - "MONITOR_WW4A3_6", - "MONITOR_WW4A3_7", - "MONITOR_WW4A3_8", - "MONITOR_WW4A3_9", - "MONITOR_WW4B0_0", - "MONITOR_WW4B0_1", - "MONITOR_WW4B0_2", - "MONITOR_WW4B0_3", - "MONITOR_WW4B0_4", - "MONITOR_WW4B0_5", - "MONITOR_WW4B0_6", - "MONITOR_WW4B0_7", - "MONITOR_WW4B0_8", - "MONITOR_WW4B0_9", - "MONITOR_WW4B1_0", - "MONITOR_WW4B1_1", - "MONITOR_WW4B1_2", - "MONITOR_WW4B1_3", - "MONITOR_WW4B1_4", - "MONITOR_WW4B1_5", - "MONITOR_WW4B1_6", - "MONITOR_WW4B1_7", - "MONITOR_WW4B1_8", - "MONITOR_WW4B1_9", - "MONITOR_WW4B2_0", - "MONITOR_WW4B2_1", - "MONITOR_WW4B2_2", - "MONITOR_WW4B2_3", - "MONITOR_WW4B2_4", - "MONITOR_WW4B2_5", - "MONITOR_WW4B2_6", - "MONITOR_WW4B2_7", - "MONITOR_WW4B2_8", - "MONITOR_WW4B2_9", - "MONITOR_WW4B3_0", - "MONITOR_WW4B3_1", - "MONITOR_WW4B3_2", - "MONITOR_WW4B3_3", - "MONITOR_WW4B3_4", - "MONITOR_WW4B3_5", - "MONITOR_WW4B3_6", - "MONITOR_WW4B3_7", - "MONITOR_WW4B3_8", - "MONITOR_WW4B3_9", - "MONITOR_WW4C0_0", - "MONITOR_WW4C0_1", - "MONITOR_WW4C0_2", - "MONITOR_WW4C0_3", - "MONITOR_WW4C0_4", - "MONITOR_WW4C0_5", - "MONITOR_WW4C0_6", - "MONITOR_WW4C0_7", - "MONITOR_WW4C0_8", - "MONITOR_WW4C0_9", - "MONITOR_WW4C1_0", - "MONITOR_WW4C1_1", - "MONITOR_WW4C1_2", - "MONITOR_WW4C1_3", - "MONITOR_WW4C1_4", - "MONITOR_WW4C1_5", - "MONITOR_WW4C1_6", - "MONITOR_WW4C1_7", - "MONITOR_WW4C1_8", - "MONITOR_WW4C1_9", - "MONITOR_WW4C2_0", - "MONITOR_WW4C2_1", - "MONITOR_WW4C2_2", - "MONITOR_WW4C2_3", - "MONITOR_WW4C2_4", - "MONITOR_WW4C2_5", - "MONITOR_WW4C2_6", - "MONITOR_WW4C2_7", - "MONITOR_WW4C2_8", - "MONITOR_WW4C2_9", - "MONITOR_WW4C3_0", - "MONITOR_WW4C3_1", - "MONITOR_WW4C3_2", - "MONITOR_WW4C3_3", - "MONITOR_WW4C3_4", - "MONITOR_WW4C3_5", - "MONITOR_WW4C3_6", - "MONITOR_WW4C3_7", - "MONITOR_WW4C3_8", - "MONITOR_WW4C3_9", - "MONITOR_WW4END0_0", - "MONITOR_WW4END0_1", - "MONITOR_WW4END0_2", - "MONITOR_WW4END0_3", - "MONITOR_WW4END0_4", - "MONITOR_WW4END0_5", - "MONITOR_WW4END0_6", - "MONITOR_WW4END0_7", - "MONITOR_WW4END0_8", - "MONITOR_WW4END0_9", - "MONITOR_WW4END1_0", - "MONITOR_WW4END1_1", - "MONITOR_WW4END1_2", - "MONITOR_WW4END1_3", - "MONITOR_WW4END1_4", - "MONITOR_WW4END1_5", - "MONITOR_WW4END1_6", - "MONITOR_WW4END1_7", - "MONITOR_WW4END1_8", - "MONITOR_WW4END1_9", - "MONITOR_WW4END2_0", - "MONITOR_WW4END2_1", - "MONITOR_WW4END2_2", - "MONITOR_WW4END2_3", - "MONITOR_WW4END2_4", - "MONITOR_WW4END2_5", - "MONITOR_WW4END2_6", - "MONITOR_WW4END2_7", - "MONITOR_WW4END2_8", - "MONITOR_WW4END2_9", - "MONITOR_WW4END3_0", - "MONITOR_WW4END3_1", - "MONITOR_WW4END3_2", - "MONITOR_WW4END3_3", - "MONITOR_WW4END3_4", - "MONITOR_WW4END3_5", - "MONITOR_WW4END3_6", - "MONITOR_WW4END3_7", - "MONITOR_WW4END3_8", - "MONITOR_WW4END3_9" - ] + "wires": { + "MONITOR_BLOCK_OUTS_B0_0": null, + "MONITOR_BLOCK_OUTS_B0_1": null, + "MONITOR_BLOCK_OUTS_B0_2": null, + "MONITOR_BLOCK_OUTS_B0_3": null, + "MONITOR_BLOCK_OUTS_B0_4": null, + "MONITOR_BLOCK_OUTS_B0_5": null, + "MONITOR_BLOCK_OUTS_B0_6": null, + "MONITOR_BLOCK_OUTS_B0_7": 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"MONITOR_WW4B1_0": null, + "MONITOR_WW4B1_1": null, + "MONITOR_WW4B1_2": null, + "MONITOR_WW4B1_3": null, + "MONITOR_WW4B1_4": null, + "MONITOR_WW4B1_5": null, + "MONITOR_WW4B1_6": null, + "MONITOR_WW4B1_7": null, + "MONITOR_WW4B1_8": null, + "MONITOR_WW4B1_9": null, + "MONITOR_WW4B2_0": null, + "MONITOR_WW4B2_1": null, + "MONITOR_WW4B2_2": null, + "MONITOR_WW4B2_3": null, + "MONITOR_WW4B2_4": null, + "MONITOR_WW4B2_5": null, + "MONITOR_WW4B2_6": null, + "MONITOR_WW4B2_7": null, + "MONITOR_WW4B2_8": null, + "MONITOR_WW4B2_9": null, + "MONITOR_WW4B3_0": null, + "MONITOR_WW4B3_1": null, + "MONITOR_WW4B3_2": null, + "MONITOR_WW4B3_3": null, + "MONITOR_WW4B3_4": null, + "MONITOR_WW4B3_5": null, + "MONITOR_WW4B3_6": null, + "MONITOR_WW4B3_7": null, + "MONITOR_WW4B3_8": null, + "MONITOR_WW4B3_9": null, + "MONITOR_WW4C0_0": null, + "MONITOR_WW4C0_1": null, + "MONITOR_WW4C0_2": null, + "MONITOR_WW4C0_3": null, + "MONITOR_WW4C0_4": null, + "MONITOR_WW4C0_5": null, + "MONITOR_WW4C0_6": null, + "MONITOR_WW4C0_7": null, + "MONITOR_WW4C0_8": null, + "MONITOR_WW4C0_9": null, + "MONITOR_WW4C1_0": null, + "MONITOR_WW4C1_1": null, + "MONITOR_WW4C1_2": null, + "MONITOR_WW4C1_3": null, + "MONITOR_WW4C1_4": null, + "MONITOR_WW4C1_5": null, + "MONITOR_WW4C1_6": null, + "MONITOR_WW4C1_7": null, + "MONITOR_WW4C1_8": null, + "MONITOR_WW4C1_9": null, + "MONITOR_WW4C2_0": null, + "MONITOR_WW4C2_1": null, + "MONITOR_WW4C2_2": null, + "MONITOR_WW4C2_3": null, + "MONITOR_WW4C2_4": null, + "MONITOR_WW4C2_5": null, + "MONITOR_WW4C2_6": null, + "MONITOR_WW4C2_7": null, + "MONITOR_WW4C2_8": null, + "MONITOR_WW4C2_9": null, + "MONITOR_WW4C3_0": null, + "MONITOR_WW4C3_1": null, + "MONITOR_WW4C3_2": null, + "MONITOR_WW4C3_3": null, + "MONITOR_WW4C3_4": null, + "MONITOR_WW4C3_5": null, + "MONITOR_WW4C3_6": null, + "MONITOR_WW4C3_7": null, + "MONITOR_WW4C3_8": null, + "MONITOR_WW4C3_9": null, + "MONITOR_WW4END0_0": null, + "MONITOR_WW4END0_1": null, + "MONITOR_WW4END0_2": null, + "MONITOR_WW4END0_3": null, + "MONITOR_WW4END0_4": null, + "MONITOR_WW4END0_5": null, + "MONITOR_WW4END0_6": null, + "MONITOR_WW4END0_7": null, + "MONITOR_WW4END0_8": null, + "MONITOR_WW4END0_9": null, + "MONITOR_WW4END1_0": null, + "MONITOR_WW4END1_1": null, + "MONITOR_WW4END1_2": null, + "MONITOR_WW4END1_3": null, + "MONITOR_WW4END1_4": null, + "MONITOR_WW4END1_5": null, + "MONITOR_WW4END1_6": null, + "MONITOR_WW4END1_7": null, + "MONITOR_WW4END1_8": null, + "MONITOR_WW4END1_9": null, + "MONITOR_WW4END2_0": null, + "MONITOR_WW4END2_1": null, + "MONITOR_WW4END2_2": null, + "MONITOR_WW4END2_3": null, + "MONITOR_WW4END2_4": null, + "MONITOR_WW4END2_5": null, + "MONITOR_WW4END2_6": null, + "MONITOR_WW4END2_7": null, + "MONITOR_WW4END2_8": null, + "MONITOR_WW4END2_9": null, + "MONITOR_WW4END3_0": null, + "MONITOR_WW4END3_1": null, + "MONITOR_WW4END3_2": null, + "MONITOR_WW4END3_3": null, + "MONITOR_WW4END3_4": null, + "MONITOR_WW4END3_5": null, + "MONITOR_WW4END3_6": null, + "MONITOR_WW4END3_7": null, + "MONITOR_WW4END3_8": null, + "MONITOR_WW4END3_9": null + } } diff --git a/zynq7/tile_type_MONITOR_TOP_PELE1.json b/zynq7/tile_type_MONITOR_TOP_PELE1.json index 9068d26..782e1b8 100644 --- a/zynq7/tile_type_MONITOR_TOP_PELE1.json +++ b/zynq7/tile_type_MONITOR_TOP_PELE1.json @@ -2,1171 +2,1215 @@ "pips": { "MONITOR_TOP_PELE1.MONITOR_HORIZ_VAUXN0_RIGHT->MONITOR_VERT_SHORT_VAUXN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_SHORT_VAUXN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN0_RIGHT" }, "MONITOR_TOP_PELE1.MONITOR_HORIZ_VAUXN8_RIGHT->MONITOR_VERT_SHORT_VAUXN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_SHORT_VAUXN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN8_RIGHT" }, "MONITOR_TOP_PELE1.MONITOR_HORIZ_VAUXP0_RIGHT->MONITOR_VERT_SHORT_VAUXP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_SHORT_VAUXP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP0_RIGHT" }, "MONITOR_TOP_PELE1.MONITOR_HORIZ_VAUXP8_RIGHT->MONITOR_VERT_SHORT_VAUXP8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_SHORT_VAUXP8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP8_RIGHT" } }, "sites": [], "tile_type": "MONITOR_TOP_PELE1", - "wires": [ - "MONITOR_BLOCK_OUTS_B0_0", - "MONITOR_BLOCK_OUTS_B0_1", - "MONITOR_BLOCK_OUTS_B0_2", - "MONITOR_BLOCK_OUTS_B0_3", - "MONITOR_BLOCK_OUTS_B0_4", - "MONITOR_BLOCK_OUTS_B1_0", - "MONITOR_BLOCK_OUTS_B1_1", - "MONITOR_BLOCK_OUTS_B1_2", - "MONITOR_BLOCK_OUTS_B1_3", - "MONITOR_BLOCK_OUTS_B1_4", - "MONITOR_BLOCK_OUTS_B2_0", - "MONITOR_BLOCK_OUTS_B2_1", - "MONITOR_BLOCK_OUTS_B2_2", - "MONITOR_BLOCK_OUTS_B2_3", - "MONITOR_BLOCK_OUTS_B2_4", - "MONITOR_BLOCK_OUTS_B3_0", - "MONITOR_BLOCK_OUTS_B3_1", - "MONITOR_BLOCK_OUTS_B3_2", - "MONITOR_BLOCK_OUTS_B3_3", - "MONITOR_BLOCK_OUTS_B3_4", - "MONITOR_BYP0_0", - "MONITOR_BYP0_1", - "MONITOR_BYP0_2", - "MONITOR_BYP0_3", - "MONITOR_BYP0_4", - "MONITOR_BYP1_0", - "MONITOR_BYP1_1", - "MONITOR_BYP1_2", - "MONITOR_BYP1_3", - "MONITOR_BYP1_4", - "MONITOR_BYP2_0", - "MONITOR_BYP2_1", - "MONITOR_BYP2_2", - "MONITOR_BYP2_3", - "MONITOR_BYP2_4", - "MONITOR_BYP3_0", - "MONITOR_BYP3_1", - "MONITOR_BYP3_2", - "MONITOR_BYP3_3", - "MONITOR_BYP3_4", - "MONITOR_BYP4_0", - "MONITOR_BYP4_1", - "MONITOR_BYP4_2", - "MONITOR_BYP4_3", - "MONITOR_BYP4_4", - "MONITOR_BYP5_0", - "MONITOR_BYP5_1", - "MONITOR_BYP5_2", - "MONITOR_BYP5_3", - "MONITOR_BYP5_4", - "MONITOR_BYP6_0", - "MONITOR_BYP6_1", - "MONITOR_BYP6_2", - "MONITOR_BYP6_3", - "MONITOR_BYP6_4", - "MONITOR_BYP7_0", - "MONITOR_BYP7_1", - "MONITOR_BYP7_2", - "MONITOR_BYP7_3", - "MONITOR_BYP7_4", - "MONITOR_CLK0_0", - "MONITOR_CLK0_1", - "MONITOR_CLK0_2", - "MONITOR_CLK0_3", - "MONITOR_CLK0_4", - "MONITOR_CLK1_0", - "MONITOR_CLK1_1", - "MONITOR_CLK1_2", - "MONITOR_CLK1_3", - "MONITOR_CLK1_4", - "MONITOR_CTRL0_0", - "MONITOR_CTRL0_1", - "MONITOR_CTRL0_2", - "MONITOR_CTRL0_3", - "MONITOR_CTRL0_4", - "MONITOR_CTRL1_0", - "MONITOR_CTRL1_1", - "MONITOR_CTRL1_2", - "MONITOR_CTRL1_3", - "MONITOR_CTRL1_4", - "MONITOR_EE2A0_0", - "MONITOR_EE2A0_1", - "MONITOR_EE2A0_2", - "MONITOR_EE2A0_3", - "MONITOR_EE2A0_4", - "MONITOR_EE2A1_0", - "MONITOR_EE2A1_1", - "MONITOR_EE2A1_2", - "MONITOR_EE2A1_3", - "MONITOR_EE2A1_4", - "MONITOR_EE2A2_0", - "MONITOR_EE2A2_1", - "MONITOR_EE2A2_2", - "MONITOR_EE2A2_3", - "MONITOR_EE2A2_4", - "MONITOR_EE2A3_0", - "MONITOR_EE2A3_1", - "MONITOR_EE2A3_2", - "MONITOR_EE2A3_3", - "MONITOR_EE2A3_4", - "MONITOR_EE2BEG0_0", - "MONITOR_EE2BEG0_1", - "MONITOR_EE2BEG0_2", - "MONITOR_EE2BEG0_3", - "MONITOR_EE2BEG0_4", - "MONITOR_EE2BEG1_0", - "MONITOR_EE2BEG1_1", - "MONITOR_EE2BEG1_2", - "MONITOR_EE2BEG1_3", - "MONITOR_EE2BEG1_4", - "MONITOR_EE2BEG2_0", - "MONITOR_EE2BEG2_1", - "MONITOR_EE2BEG2_2", - "MONITOR_EE2BEG2_3", - "MONITOR_EE2BEG2_4", - "MONITOR_EE2BEG3_0", - "MONITOR_EE2BEG3_1", - "MONITOR_EE2BEG3_2", - "MONITOR_EE2BEG3_3", - "MONITOR_EE2BEG3_4", - "MONITOR_EE4A0_0", - "MONITOR_EE4A0_1", - "MONITOR_EE4A0_2", - "MONITOR_EE4A0_3", - "MONITOR_EE4A0_4", - "MONITOR_EE4A1_0", - "MONITOR_EE4A1_1", - "MONITOR_EE4A1_2", - "MONITOR_EE4A1_3", - "MONITOR_EE4A1_4", - "MONITOR_EE4A2_0", - "MONITOR_EE4A2_1", - "MONITOR_EE4A2_2", - "MONITOR_EE4A2_3", - "MONITOR_EE4A2_4", - "MONITOR_EE4A3_0", - "MONITOR_EE4A3_1", - "MONITOR_EE4A3_2", - "MONITOR_EE4A3_3", - "MONITOR_EE4A3_4", - "MONITOR_EE4B0_0", - "MONITOR_EE4B0_1", - "MONITOR_EE4B0_2", - "MONITOR_EE4B0_3", - "MONITOR_EE4B0_4", - "MONITOR_EE4B1_0", - "MONITOR_EE4B1_1", - "MONITOR_EE4B1_2", - "MONITOR_EE4B1_3", - "MONITOR_EE4B1_4", - "MONITOR_EE4B2_0", - "MONITOR_EE4B2_1", - "MONITOR_EE4B2_2", - "MONITOR_EE4B2_3", - "MONITOR_EE4B2_4", - "MONITOR_EE4B3_0", - "MONITOR_EE4B3_1", - "MONITOR_EE4B3_2", - "MONITOR_EE4B3_3", - "MONITOR_EE4B3_4", - "MONITOR_EE4BEG0_0", - "MONITOR_EE4BEG0_1", - "MONITOR_EE4BEG0_2", - "MONITOR_EE4BEG0_3", - "MONITOR_EE4BEG0_4", - "MONITOR_EE4BEG1_0", - "MONITOR_EE4BEG1_1", - "MONITOR_EE4BEG1_2", - "MONITOR_EE4BEG1_3", - "MONITOR_EE4BEG1_4", - "MONITOR_EE4BEG2_0", - "MONITOR_EE4BEG2_1", - "MONITOR_EE4BEG2_2", - "MONITOR_EE4BEG2_3", - "MONITOR_EE4BEG2_4", - "MONITOR_EE4BEG3_0", - "MONITOR_EE4BEG3_1", - "MONITOR_EE4BEG3_2", - "MONITOR_EE4BEG3_3", - "MONITOR_EE4BEG3_4", - "MONITOR_EE4C0_0", - "MONITOR_EE4C0_1", - "MONITOR_EE4C0_2", - "MONITOR_EE4C0_3", - "MONITOR_EE4C0_4", - "MONITOR_EE4C1_0", - "MONITOR_EE4C1_1", - "MONITOR_EE4C1_2", - "MONITOR_EE4C1_3", - "MONITOR_EE4C1_4", - "MONITOR_EE4C2_0", - "MONITOR_EE4C2_1", - "MONITOR_EE4C2_2", - "MONITOR_EE4C2_3", - "MONITOR_EE4C2_4", - "MONITOR_EE4C3_0", - "MONITOR_EE4C3_1", - "MONITOR_EE4C3_2", - "MONITOR_EE4C3_3", - "MONITOR_EE4C3_4", - "MONITOR_EL1BEG0_0", - "MONITOR_EL1BEG0_1", - "MONITOR_EL1BEG0_2", - "MONITOR_EL1BEG0_3", - "MONITOR_EL1BEG0_4", - "MONITOR_EL1BEG1_0", - "MONITOR_EL1BEG1_1", - "MONITOR_EL1BEG1_2", - "MONITOR_EL1BEG1_3", - "MONITOR_EL1BEG1_4", - "MONITOR_EL1BEG2_0", - "MONITOR_EL1BEG2_1", - "MONITOR_EL1BEG2_2", - "MONITOR_EL1BEG2_3", - "MONITOR_EL1BEG2_4", - "MONITOR_EL1BEG3_0", - "MONITOR_EL1BEG3_1", - "MONITOR_EL1BEG3_2", - "MONITOR_EL1BEG3_3", - "MONITOR_EL1BEG3_4", - "MONITOR_ER1BEG0_0", - "MONITOR_ER1BEG0_1", - "MONITOR_ER1BEG0_2", - "MONITOR_ER1BEG0_3", - "MONITOR_ER1BEG0_4", - "MONITOR_ER1BEG1_0", - "MONITOR_ER1BEG1_1", - "MONITOR_ER1BEG1_2", - "MONITOR_ER1BEG1_3", - "MONITOR_ER1BEG1_4", - "MONITOR_ER1BEG2_0", - "MONITOR_ER1BEG2_1", - "MONITOR_ER1BEG2_2", - "MONITOR_ER1BEG2_3", - "MONITOR_ER1BEG2_4", - "MONITOR_ER1BEG3_0", - "MONITOR_ER1BEG3_1", - "MONITOR_ER1BEG3_2", - "MONITOR_ER1BEG3_3", - "MONITOR_ER1BEG3_4", - "MONITOR_FAN0_0", - "MONITOR_FAN0_1", - "MONITOR_FAN0_2", - "MONITOR_FAN0_3", - "MONITOR_FAN0_4", - "MONITOR_FAN1_0", - "MONITOR_FAN1_1", - "MONITOR_FAN1_2", - "MONITOR_FAN1_3", - "MONITOR_FAN1_4", - "MONITOR_FAN2_0", - "MONITOR_FAN2_1", - "MONITOR_FAN2_2", - "MONITOR_FAN2_3", - "MONITOR_FAN2_4", - "MONITOR_FAN3_0", - "MONITOR_FAN3_1", - "MONITOR_FAN3_2", - "MONITOR_FAN3_3", - "MONITOR_FAN3_4", - "MONITOR_FAN4_0", - "MONITOR_FAN4_1", - "MONITOR_FAN4_2", - "MONITOR_FAN4_3", - "MONITOR_FAN4_4", - "MONITOR_FAN5_0", - "MONITOR_FAN5_1", - "MONITOR_FAN5_2", - "MONITOR_FAN5_3", - "MONITOR_FAN5_4", - "MONITOR_FAN6_0", - "MONITOR_FAN6_1", - "MONITOR_FAN6_2", - "MONITOR_FAN6_3", - "MONITOR_FAN6_4", - "MONITOR_FAN7_0", - "MONITOR_FAN7_1", - "MONITOR_FAN7_2", - "MONITOR_FAN7_3", - "MONITOR_FAN7_4", - "MONITOR_HORIZ_VAUXN0_RIGHT", - "MONITOR_HORIZ_VAUXN8_RIGHT", - "MONITOR_HORIZ_VAUXP0_RIGHT", - "MONITOR_HORIZ_VAUXP8_RIGHT", - "MONITOR_IMUX0_0", - "MONITOR_IMUX0_1", - "MONITOR_IMUX0_2", - "MONITOR_IMUX0_3", - "MONITOR_IMUX0_4", - "MONITOR_IMUX10_0", - "MONITOR_IMUX10_1", - "MONITOR_IMUX10_2", - "MONITOR_IMUX10_3", - "MONITOR_IMUX10_4", - "MONITOR_IMUX11_0", - "MONITOR_IMUX11_1", - "MONITOR_IMUX11_2", - "MONITOR_IMUX11_3", - "MONITOR_IMUX11_4", - "MONITOR_IMUX12_0", - "MONITOR_IMUX12_1", - "MONITOR_IMUX12_2", - "MONITOR_IMUX12_3", - "MONITOR_IMUX12_4", - "MONITOR_IMUX13_0", - "MONITOR_IMUX13_1", - "MONITOR_IMUX13_2", - "MONITOR_IMUX13_3", - "MONITOR_IMUX13_4", - "MONITOR_IMUX14_0", - "MONITOR_IMUX14_1", - "MONITOR_IMUX14_2", - "MONITOR_IMUX14_3", - "MONITOR_IMUX14_4", - "MONITOR_IMUX15_0", - "MONITOR_IMUX15_1", - "MONITOR_IMUX15_2", - "MONITOR_IMUX15_3", - "MONITOR_IMUX15_4", - "MONITOR_IMUX16_0", - "MONITOR_IMUX16_1", - "MONITOR_IMUX16_2", - "MONITOR_IMUX16_3", - "MONITOR_IMUX16_4", - "MONITOR_IMUX17_0", - "MONITOR_IMUX17_1", - "MONITOR_IMUX17_2", - "MONITOR_IMUX17_3", - "MONITOR_IMUX17_4", - "MONITOR_IMUX18_0", - "MONITOR_IMUX18_1", - "MONITOR_IMUX18_2", - "MONITOR_IMUX18_3", - "MONITOR_IMUX18_4", - "MONITOR_IMUX19_0", - "MONITOR_IMUX19_1", - "MONITOR_IMUX19_2", - "MONITOR_IMUX19_3", - "MONITOR_IMUX19_4", - "MONITOR_IMUX1_0", - "MONITOR_IMUX1_1", - "MONITOR_IMUX1_2", - "MONITOR_IMUX1_3", - "MONITOR_IMUX1_4", - "MONITOR_IMUX20_0", - "MONITOR_IMUX20_1", - "MONITOR_IMUX20_2", - "MONITOR_IMUX20_3", - "MONITOR_IMUX20_4", - "MONITOR_IMUX21_0", - "MONITOR_IMUX21_1", - "MONITOR_IMUX21_2", - "MONITOR_IMUX21_3", - "MONITOR_IMUX21_4", - "MONITOR_IMUX22_0", - "MONITOR_IMUX22_1", - "MONITOR_IMUX22_2", - "MONITOR_IMUX22_3", - "MONITOR_IMUX22_4", - "MONITOR_IMUX23_0", - "MONITOR_IMUX23_1", - "MONITOR_IMUX23_2", - "MONITOR_IMUX23_3", - "MONITOR_IMUX23_4", - "MONITOR_IMUX24_0", - "MONITOR_IMUX24_1", - "MONITOR_IMUX24_2", - "MONITOR_IMUX24_3", - "MONITOR_IMUX24_4", - "MONITOR_IMUX25_0", - "MONITOR_IMUX25_1", - "MONITOR_IMUX25_2", - "MONITOR_IMUX25_3", - "MONITOR_IMUX25_4", - "MONITOR_IMUX26_0", - "MONITOR_IMUX26_1", - "MONITOR_IMUX26_2", - "MONITOR_IMUX26_3", - "MONITOR_IMUX26_4", - "MONITOR_IMUX27_0", - "MONITOR_IMUX27_1", - "MONITOR_IMUX27_2", - "MONITOR_IMUX27_3", - "MONITOR_IMUX27_4", - "MONITOR_IMUX28_0", - "MONITOR_IMUX28_1", - "MONITOR_IMUX28_2", - "MONITOR_IMUX28_3", - "MONITOR_IMUX28_4", - "MONITOR_IMUX29_0", - "MONITOR_IMUX29_1", - "MONITOR_IMUX29_2", - "MONITOR_IMUX29_3", - "MONITOR_IMUX29_4", - "MONITOR_IMUX2_0", - "MONITOR_IMUX2_1", - "MONITOR_IMUX2_2", - "MONITOR_IMUX2_3", - "MONITOR_IMUX2_4", - "MONITOR_IMUX30_0", - "MONITOR_IMUX30_1", - "MONITOR_IMUX30_2", - "MONITOR_IMUX30_3", - "MONITOR_IMUX30_4", - "MONITOR_IMUX31_0", - "MONITOR_IMUX31_1", - "MONITOR_IMUX31_2", - "MONITOR_IMUX31_3", - "MONITOR_IMUX31_4", - "MONITOR_IMUX32_0", - "MONITOR_IMUX32_1", - "MONITOR_IMUX32_2", - "MONITOR_IMUX32_3", - "MONITOR_IMUX32_4", - "MONITOR_IMUX33_0", - "MONITOR_IMUX33_1", - "MONITOR_IMUX33_2", - "MONITOR_IMUX33_3", - "MONITOR_IMUX33_4", - "MONITOR_IMUX34_0", - "MONITOR_IMUX34_1", - "MONITOR_IMUX34_2", - "MONITOR_IMUX34_3", - "MONITOR_IMUX34_4", - "MONITOR_IMUX35_0", - "MONITOR_IMUX35_1", - "MONITOR_IMUX35_2", - "MONITOR_IMUX35_3", - "MONITOR_IMUX35_4", - "MONITOR_IMUX36_0", - "MONITOR_IMUX36_1", - "MONITOR_IMUX36_2", - "MONITOR_IMUX36_3", - "MONITOR_IMUX36_4", - "MONITOR_IMUX37_0", - "MONITOR_IMUX37_1", - "MONITOR_IMUX37_2", - "MONITOR_IMUX37_3", - "MONITOR_IMUX37_4", - "MONITOR_IMUX38_0", - "MONITOR_IMUX38_1", - "MONITOR_IMUX38_2", - "MONITOR_IMUX38_3", - "MONITOR_IMUX38_4", - "MONITOR_IMUX39_0", - "MONITOR_IMUX39_1", - "MONITOR_IMUX39_2", - "MONITOR_IMUX39_3", - "MONITOR_IMUX39_4", - "MONITOR_IMUX3_0", - "MONITOR_IMUX3_1", - "MONITOR_IMUX3_2", - "MONITOR_IMUX3_3", - "MONITOR_IMUX3_4", - "MONITOR_IMUX40_0", - "MONITOR_IMUX40_1", - "MONITOR_IMUX40_2", - "MONITOR_IMUX40_3", - "MONITOR_IMUX40_4", - "MONITOR_IMUX41_0", - "MONITOR_IMUX41_1", - "MONITOR_IMUX41_2", - "MONITOR_IMUX41_3", - "MONITOR_IMUX41_4", - "MONITOR_IMUX42_0", - "MONITOR_IMUX42_1", - "MONITOR_IMUX42_2", - "MONITOR_IMUX42_3", - "MONITOR_IMUX42_4", - "MONITOR_IMUX43_0", - "MONITOR_IMUX43_1", - "MONITOR_IMUX43_2", - "MONITOR_IMUX43_3", - "MONITOR_IMUX43_4", - "MONITOR_IMUX44_0", - "MONITOR_IMUX44_1", - "MONITOR_IMUX44_2", - "MONITOR_IMUX44_3", - "MONITOR_IMUX44_4", - "MONITOR_IMUX45_0", - "MONITOR_IMUX45_1", - "MONITOR_IMUX45_2", - "MONITOR_IMUX45_3", - "MONITOR_IMUX45_4", - "MONITOR_IMUX46_0", - "MONITOR_IMUX46_1", - "MONITOR_IMUX46_2", - "MONITOR_IMUX46_3", - "MONITOR_IMUX46_4", - "MONITOR_IMUX47_0", - "MONITOR_IMUX47_1", - "MONITOR_IMUX47_2", - "MONITOR_IMUX47_3", - "MONITOR_IMUX47_4", - "MONITOR_IMUX4_0", - "MONITOR_IMUX4_1", - "MONITOR_IMUX4_2", - "MONITOR_IMUX4_3", - "MONITOR_IMUX4_4", - "MONITOR_IMUX5_0", - "MONITOR_IMUX5_1", - "MONITOR_IMUX5_2", - "MONITOR_IMUX5_3", - "MONITOR_IMUX5_4", - "MONITOR_IMUX6_0", - "MONITOR_IMUX6_1", - "MONITOR_IMUX6_2", - "MONITOR_IMUX6_3", - "MONITOR_IMUX6_4", - "MONITOR_IMUX7_0", - "MONITOR_IMUX7_1", - "MONITOR_IMUX7_2", - "MONITOR_IMUX7_3", - "MONITOR_IMUX7_4", - "MONITOR_IMUX8_0", - "MONITOR_IMUX8_1", - "MONITOR_IMUX8_2", - "MONITOR_IMUX8_3", - "MONITOR_IMUX8_4", - "MONITOR_IMUX9_0", - "MONITOR_IMUX9_1", - "MONITOR_IMUX9_2", - "MONITOR_IMUX9_3", - "MONITOR_IMUX9_4", - "MONITOR_LH10_0", - "MONITOR_LH10_1", - "MONITOR_LH10_2", - "MONITOR_LH10_3", - "MONITOR_LH10_4", - "MONITOR_LH11_0", - "MONITOR_LH11_1", - "MONITOR_LH11_2", - "MONITOR_LH11_3", - "MONITOR_LH11_4", - "MONITOR_LH12_0", - "MONITOR_LH12_1", - "MONITOR_LH12_2", - "MONITOR_LH12_3", - "MONITOR_LH12_4", - "MONITOR_LH1_0", - "MONITOR_LH1_1", - "MONITOR_LH1_2", - "MONITOR_LH1_3", - "MONITOR_LH1_4", - "MONITOR_LH2_0", - "MONITOR_LH2_1", - "MONITOR_LH2_2", - "MONITOR_LH2_3", - "MONITOR_LH2_4", - "MONITOR_LH3_0", - "MONITOR_LH3_1", - "MONITOR_LH3_2", - "MONITOR_LH3_3", - "MONITOR_LH3_4", - "MONITOR_LH4_0", - "MONITOR_LH4_1", - "MONITOR_LH4_2", - "MONITOR_LH4_3", - "MONITOR_LH4_4", - "MONITOR_LH5_0", - "MONITOR_LH5_1", - "MONITOR_LH5_2", - "MONITOR_LH5_3", - "MONITOR_LH5_4", - "MONITOR_LH6_0", - "MONITOR_LH6_1", - "MONITOR_LH6_2", - "MONITOR_LH6_3", - "MONITOR_LH6_4", - "MONITOR_LH7_0", - "MONITOR_LH7_1", - "MONITOR_LH7_2", - "MONITOR_LH7_3", - "MONITOR_LH7_4", - "MONITOR_LH8_0", - "MONITOR_LH8_1", - "MONITOR_LH8_2", - "MONITOR_LH8_3", - "MONITOR_LH8_4", - "MONITOR_LH9_0", - "MONITOR_LH9_1", - "MONITOR_LH9_2", - "MONITOR_LH9_3", - "MONITOR_LH9_4", - "MONITOR_LOGIC_OUTS_B0_0", - "MONITOR_LOGIC_OUTS_B0_1", - "MONITOR_LOGIC_OUTS_B0_2", - "MONITOR_LOGIC_OUTS_B0_3", - "MONITOR_LOGIC_OUTS_B0_4", - "MONITOR_LOGIC_OUTS_B10_0", - "MONITOR_LOGIC_OUTS_B10_1", - "MONITOR_LOGIC_OUTS_B10_2", - "MONITOR_LOGIC_OUTS_B10_3", - "MONITOR_LOGIC_OUTS_B10_4", - "MONITOR_LOGIC_OUTS_B11_0", - "MONITOR_LOGIC_OUTS_B11_1", - "MONITOR_LOGIC_OUTS_B11_2", - "MONITOR_LOGIC_OUTS_B11_3", - "MONITOR_LOGIC_OUTS_B11_4", - "MONITOR_LOGIC_OUTS_B12_0", - "MONITOR_LOGIC_OUTS_B12_1", - "MONITOR_LOGIC_OUTS_B12_2", - "MONITOR_LOGIC_OUTS_B12_3", - "MONITOR_LOGIC_OUTS_B12_4", - "MONITOR_LOGIC_OUTS_B13_0", - "MONITOR_LOGIC_OUTS_B13_1", - "MONITOR_LOGIC_OUTS_B13_2", - "MONITOR_LOGIC_OUTS_B13_3", - "MONITOR_LOGIC_OUTS_B13_4", - "MONITOR_LOGIC_OUTS_B14_0", - "MONITOR_LOGIC_OUTS_B14_1", - "MONITOR_LOGIC_OUTS_B14_2", - "MONITOR_LOGIC_OUTS_B14_3", - "MONITOR_LOGIC_OUTS_B14_4", - "MONITOR_LOGIC_OUTS_B15_0", - "MONITOR_LOGIC_OUTS_B15_1", - "MONITOR_LOGIC_OUTS_B15_2", - "MONITOR_LOGIC_OUTS_B15_3", - "MONITOR_LOGIC_OUTS_B15_4", - "MONITOR_LOGIC_OUTS_B16_0", - "MONITOR_LOGIC_OUTS_B16_1", - "MONITOR_LOGIC_OUTS_B16_2", - "MONITOR_LOGIC_OUTS_B16_3", - "MONITOR_LOGIC_OUTS_B16_4", - "MONITOR_LOGIC_OUTS_B17_0", - "MONITOR_LOGIC_OUTS_B17_1", - "MONITOR_LOGIC_OUTS_B17_2", - "MONITOR_LOGIC_OUTS_B17_3", - "MONITOR_LOGIC_OUTS_B17_4", - "MONITOR_LOGIC_OUTS_B18_0", - "MONITOR_LOGIC_OUTS_B18_1", - "MONITOR_LOGIC_OUTS_B18_2", - "MONITOR_LOGIC_OUTS_B18_3", - "MONITOR_LOGIC_OUTS_B18_4", - "MONITOR_LOGIC_OUTS_B19_0", - "MONITOR_LOGIC_OUTS_B19_1", - "MONITOR_LOGIC_OUTS_B19_2", - "MONITOR_LOGIC_OUTS_B19_3", - "MONITOR_LOGIC_OUTS_B19_4", - "MONITOR_LOGIC_OUTS_B1_0", - "MONITOR_LOGIC_OUTS_B1_1", - "MONITOR_LOGIC_OUTS_B1_2", - "MONITOR_LOGIC_OUTS_B1_3", - "MONITOR_LOGIC_OUTS_B1_4", - "MONITOR_LOGIC_OUTS_B20_0", - "MONITOR_LOGIC_OUTS_B20_1", - "MONITOR_LOGIC_OUTS_B20_2", - "MONITOR_LOGIC_OUTS_B20_3", - "MONITOR_LOGIC_OUTS_B20_4", - "MONITOR_LOGIC_OUTS_B21_0", - "MONITOR_LOGIC_OUTS_B21_1", - "MONITOR_LOGIC_OUTS_B21_2", - "MONITOR_LOGIC_OUTS_B21_3", - "MONITOR_LOGIC_OUTS_B21_4", - "MONITOR_LOGIC_OUTS_B22_0", - "MONITOR_LOGIC_OUTS_B22_1", - "MONITOR_LOGIC_OUTS_B22_2", - "MONITOR_LOGIC_OUTS_B22_3", - "MONITOR_LOGIC_OUTS_B22_4", - "MONITOR_LOGIC_OUTS_B23_0", - "MONITOR_LOGIC_OUTS_B23_1", - "MONITOR_LOGIC_OUTS_B23_2", - "MONITOR_LOGIC_OUTS_B23_3", - "MONITOR_LOGIC_OUTS_B23_4", - "MONITOR_LOGIC_OUTS_B2_0", - "MONITOR_LOGIC_OUTS_B2_1", - "MONITOR_LOGIC_OUTS_B2_2", - "MONITOR_LOGIC_OUTS_B2_3", - "MONITOR_LOGIC_OUTS_B2_4", - "MONITOR_LOGIC_OUTS_B3_0", - "MONITOR_LOGIC_OUTS_B3_1", - "MONITOR_LOGIC_OUTS_B3_2", - "MONITOR_LOGIC_OUTS_B3_3", - "MONITOR_LOGIC_OUTS_B3_4", - "MONITOR_LOGIC_OUTS_B4_0", - "MONITOR_LOGIC_OUTS_B4_1", - "MONITOR_LOGIC_OUTS_B4_2", - "MONITOR_LOGIC_OUTS_B4_3", - "MONITOR_LOGIC_OUTS_B4_4", - "MONITOR_LOGIC_OUTS_B5_0", - "MONITOR_LOGIC_OUTS_B5_1", - "MONITOR_LOGIC_OUTS_B5_2", - "MONITOR_LOGIC_OUTS_B5_3", - "MONITOR_LOGIC_OUTS_B5_4", - "MONITOR_LOGIC_OUTS_B6_0", - "MONITOR_LOGIC_OUTS_B6_1", - "MONITOR_LOGIC_OUTS_B6_2", - "MONITOR_LOGIC_OUTS_B6_3", - "MONITOR_LOGIC_OUTS_B6_4", - "MONITOR_LOGIC_OUTS_B7_0", - "MONITOR_LOGIC_OUTS_B7_1", - "MONITOR_LOGIC_OUTS_B7_2", - "MONITOR_LOGIC_OUTS_B7_3", - "MONITOR_LOGIC_OUTS_B7_4", - "MONITOR_LOGIC_OUTS_B8_0", - "MONITOR_LOGIC_OUTS_B8_1", - "MONITOR_LOGIC_OUTS_B8_2", - "MONITOR_LOGIC_OUTS_B8_3", - "MONITOR_LOGIC_OUTS_B8_4", - "MONITOR_LOGIC_OUTS_B9_0", - "MONITOR_LOGIC_OUTS_B9_1", - "MONITOR_LOGIC_OUTS_B9_2", - "MONITOR_LOGIC_OUTS_B9_3", - "MONITOR_LOGIC_OUTS_B9_4", - "MONITOR_NE2A0_0", - "MONITOR_NE2A0_1", - "MONITOR_NE2A0_2", - "MONITOR_NE2A0_3", - "MONITOR_NE2A0_4", - "MONITOR_NE2A1_0", - "MONITOR_NE2A1_1", - "MONITOR_NE2A1_2", - "MONITOR_NE2A1_3", - "MONITOR_NE2A1_4", - "MONITOR_NE2A2_0", - "MONITOR_NE2A2_1", - "MONITOR_NE2A2_2", - "MONITOR_NE2A2_3", - "MONITOR_NE2A2_4", - "MONITOR_NE2A3_0", - "MONITOR_NE2A3_1", - "MONITOR_NE2A3_2", - "MONITOR_NE2A3_3", - "MONITOR_NE2A3_4", - "MONITOR_NE4BEG0_0", - "MONITOR_NE4BEG0_1", - "MONITOR_NE4BEG0_2", - "MONITOR_NE4BEG0_3", - "MONITOR_NE4BEG0_4", - "MONITOR_NE4BEG1_0", - "MONITOR_NE4BEG1_1", - "MONITOR_NE4BEG1_2", - "MONITOR_NE4BEG1_3", - "MONITOR_NE4BEG1_4", - "MONITOR_NE4BEG2_0", - "MONITOR_NE4BEG2_1", - "MONITOR_NE4BEG2_2", - "MONITOR_NE4BEG2_3", - "MONITOR_NE4BEG2_4", - "MONITOR_NE4BEG3_0", - "MONITOR_NE4BEG3_1", - "MONITOR_NE4BEG3_2", - "MONITOR_NE4BEG3_3", - "MONITOR_NE4BEG3_4", - "MONITOR_NE4C0_0", - "MONITOR_NE4C0_1", - "MONITOR_NE4C0_2", - "MONITOR_NE4C0_3", - "MONITOR_NE4C0_4", - "MONITOR_NE4C1_0", - "MONITOR_NE4C1_1", - "MONITOR_NE4C1_2", - "MONITOR_NE4C1_3", - "MONITOR_NE4C1_4", - "MONITOR_NE4C2_0", - "MONITOR_NE4C2_1", - "MONITOR_NE4C2_2", - "MONITOR_NE4C2_3", - "MONITOR_NE4C2_4", - "MONITOR_NE4C3_0", - "MONITOR_NE4C3_1", - "MONITOR_NE4C3_2", - "MONITOR_NE4C3_3", - "MONITOR_NE4C3_4", - "MONITOR_NW2A0_0", - "MONITOR_NW2A0_1", - "MONITOR_NW2A0_2", - "MONITOR_NW2A0_3", - "MONITOR_NW2A0_4", - "MONITOR_NW2A1_0", - "MONITOR_NW2A1_1", - "MONITOR_NW2A1_2", - "MONITOR_NW2A1_3", - "MONITOR_NW2A1_4", - "MONITOR_NW2A2_0", - "MONITOR_NW2A2_1", - "MONITOR_NW2A2_2", - "MONITOR_NW2A2_3", - "MONITOR_NW2A2_4", - "MONITOR_NW2A3_0", - "MONITOR_NW2A3_1", - "MONITOR_NW2A3_2", - "MONITOR_NW2A3_3", - "MONITOR_NW2A3_4", - "MONITOR_NW4A0_0", - "MONITOR_NW4A0_1", - "MONITOR_NW4A0_2", - "MONITOR_NW4A0_3", - "MONITOR_NW4A0_4", - "MONITOR_NW4A1_0", - "MONITOR_NW4A1_1", - "MONITOR_NW4A1_2", - "MONITOR_NW4A1_3", - "MONITOR_NW4A1_4", - "MONITOR_NW4A2_0", - "MONITOR_NW4A2_1", - "MONITOR_NW4A2_2", - "MONITOR_NW4A2_3", - "MONITOR_NW4A2_4", - "MONITOR_NW4A3_0", - "MONITOR_NW4A3_1", - "MONITOR_NW4A3_2", - "MONITOR_NW4A3_3", - "MONITOR_NW4A3_4", - "MONITOR_NW4END0_0", - "MONITOR_NW4END0_1", - "MONITOR_NW4END0_2", - "MONITOR_NW4END0_3", - "MONITOR_NW4END0_4", - "MONITOR_NW4END1_0", - "MONITOR_NW4END1_1", - "MONITOR_NW4END1_2", - "MONITOR_NW4END1_3", - "MONITOR_NW4END1_4", - "MONITOR_NW4END2_0", - "MONITOR_NW4END2_1", - "MONITOR_NW4END2_2", - "MONITOR_NW4END2_3", - "MONITOR_NW4END2_4", - "MONITOR_NW4END3_0", - "MONITOR_NW4END3_1", - "MONITOR_NW4END3_2", - "MONITOR_NW4END3_3", - "MONITOR_NW4END3_4", - "MONITOR_SE2A0_0", - "MONITOR_SE2A0_1", - "MONITOR_SE2A0_2", - "MONITOR_SE2A0_3", - "MONITOR_SE2A0_4", - "MONITOR_SE2A1_0", - "MONITOR_SE2A1_1", - "MONITOR_SE2A1_2", - "MONITOR_SE2A1_3", - "MONITOR_SE2A1_4", - "MONITOR_SE2A2_0", - "MONITOR_SE2A2_1", - "MONITOR_SE2A2_2", - "MONITOR_SE2A2_3", - "MONITOR_SE2A2_4", - "MONITOR_SE2A3_0", - "MONITOR_SE2A3_1", - "MONITOR_SE2A3_2", - "MONITOR_SE2A3_3", - "MONITOR_SE2A3_4", - "MONITOR_SE4BEG0_0", - "MONITOR_SE4BEG0_1", - "MONITOR_SE4BEG0_2", - "MONITOR_SE4BEG0_3", - "MONITOR_SE4BEG0_4", - "MONITOR_SE4BEG1_0", - "MONITOR_SE4BEG1_1", - "MONITOR_SE4BEG1_2", - "MONITOR_SE4BEG1_3", - "MONITOR_SE4BEG1_4", - "MONITOR_SE4BEG2_0", - "MONITOR_SE4BEG2_1", - "MONITOR_SE4BEG2_2", - "MONITOR_SE4BEG2_3", - "MONITOR_SE4BEG2_4", - "MONITOR_SE4BEG3_0", - "MONITOR_SE4BEG3_1", - "MONITOR_SE4BEG3_2", - "MONITOR_SE4BEG3_3", - "MONITOR_SE4BEG3_4", - "MONITOR_SE4C0_0", - "MONITOR_SE4C0_1", - "MONITOR_SE4C0_2", - "MONITOR_SE4C0_3", - "MONITOR_SE4C0_4", - "MONITOR_SE4C1_0", - "MONITOR_SE4C1_1", - "MONITOR_SE4C1_2", - "MONITOR_SE4C1_3", - "MONITOR_SE4C1_4", - "MONITOR_SE4C2_0", - "MONITOR_SE4C2_1", - "MONITOR_SE4C2_2", - "MONITOR_SE4C2_3", - "MONITOR_SE4C2_4", - "MONITOR_SE4C3_0", - "MONITOR_SE4C3_1", - "MONITOR_SE4C3_2", - "MONITOR_SE4C3_3", - "MONITOR_SE4C3_4", - "MONITOR_SW2A0_0", - "MONITOR_SW2A0_1", - "MONITOR_SW2A0_2", - "MONITOR_SW2A0_3", - "MONITOR_SW2A0_4", - "MONITOR_SW2A1_0", - "MONITOR_SW2A1_1", - "MONITOR_SW2A1_2", - "MONITOR_SW2A1_3", - "MONITOR_SW2A1_4", - "MONITOR_SW2A2_0", - "MONITOR_SW2A2_1", - "MONITOR_SW2A2_2", - "MONITOR_SW2A2_3", - "MONITOR_SW2A2_4", - "MONITOR_SW2A3_0", - "MONITOR_SW2A3_1", - "MONITOR_SW2A3_2", - "MONITOR_SW2A3_3", - "MONITOR_SW2A3_4", - "MONITOR_SW4A0_0", - "MONITOR_SW4A0_1", - "MONITOR_SW4A0_2", - "MONITOR_SW4A0_3", - "MONITOR_SW4A0_4", - "MONITOR_SW4A1_0", - "MONITOR_SW4A1_1", - "MONITOR_SW4A1_2", - "MONITOR_SW4A1_3", - "MONITOR_SW4A1_4", - "MONITOR_SW4A2_0", - "MONITOR_SW4A2_1", - "MONITOR_SW4A2_2", - "MONITOR_SW4A2_3", - "MONITOR_SW4A2_4", - "MONITOR_SW4A3_0", - "MONITOR_SW4A3_1", - "MONITOR_SW4A3_2", - "MONITOR_SW4A3_3", - "MONITOR_SW4A3_4", - "MONITOR_SW4END0_0", - "MONITOR_SW4END0_1", - "MONITOR_SW4END0_2", - "MONITOR_SW4END0_3", - "MONITOR_SW4END0_4", - "MONITOR_SW4END1_0", - "MONITOR_SW4END1_1", - "MONITOR_SW4END1_2", - "MONITOR_SW4END1_3", - "MONITOR_SW4END1_4", - "MONITOR_SW4END2_0", - "MONITOR_SW4END2_1", - "MONITOR_SW4END2_2", - "MONITOR_SW4END2_3", - "MONITOR_SW4END2_4", - "MONITOR_SW4END3_0", - "MONITOR_SW4END3_1", - "MONITOR_SW4END3_2", - "MONITOR_SW4END3_3", - "MONITOR_SW4END3_4", - "MONITOR_VERT_SHORT_VAUXN0", - "MONITOR_VERT_SHORT_VAUXN1", - "MONITOR_VERT_SHORT_VAUXN10", - "MONITOR_VERT_SHORT_VAUXN11", - "MONITOR_VERT_SHORT_VAUXN12", - "MONITOR_VERT_SHORT_VAUXN13", - "MONITOR_VERT_SHORT_VAUXN14", - "MONITOR_VERT_SHORT_VAUXN15", - "MONITOR_VERT_SHORT_VAUXN2", - "MONITOR_VERT_SHORT_VAUXN3", - "MONITOR_VERT_SHORT_VAUXN4", - "MONITOR_VERT_SHORT_VAUXN5", - "MONITOR_VERT_SHORT_VAUXN6", - "MONITOR_VERT_SHORT_VAUXN7", - "MONITOR_VERT_SHORT_VAUXN8", - "MONITOR_VERT_SHORT_VAUXN9", - "MONITOR_VERT_SHORT_VAUXP0", - "MONITOR_VERT_SHORT_VAUXP1", - "MONITOR_VERT_SHORT_VAUXP10", - "MONITOR_VERT_SHORT_VAUXP11", - "MONITOR_VERT_SHORT_VAUXP12", - "MONITOR_VERT_SHORT_VAUXP13", - "MONITOR_VERT_SHORT_VAUXP14", - "MONITOR_VERT_SHORT_VAUXP15", - "MONITOR_VERT_SHORT_VAUXP2", - "MONITOR_VERT_SHORT_VAUXP3", - "MONITOR_VERT_SHORT_VAUXP4", - "MONITOR_VERT_SHORT_VAUXP5", - "MONITOR_VERT_SHORT_VAUXP6", - "MONITOR_VERT_SHORT_VAUXP7", - "MONITOR_VERT_SHORT_VAUXP8", - "MONITOR_VERT_SHORT_VAUXP9", - "MONITOR_WL1END0_0", - "MONITOR_WL1END0_1", - "MONITOR_WL1END0_2", - "MONITOR_WL1END0_3", - "MONITOR_WL1END0_4", - "MONITOR_WL1END1_0", - "MONITOR_WL1END1_1", - "MONITOR_WL1END1_2", - "MONITOR_WL1END1_3", - "MONITOR_WL1END1_4", - "MONITOR_WL1END2_0", - "MONITOR_WL1END2_1", - "MONITOR_WL1END2_2", - "MONITOR_WL1END2_3", - "MONITOR_WL1END2_4", - "MONITOR_WL1END3_0", - "MONITOR_WL1END3_1", - "MONITOR_WL1END3_2", - "MONITOR_WL1END3_3", - "MONITOR_WL1END3_4", - "MONITOR_WR1END0_0", - "MONITOR_WR1END0_1", - "MONITOR_WR1END0_2", - "MONITOR_WR1END0_3", - "MONITOR_WR1END0_4", - "MONITOR_WR1END1_0", - "MONITOR_WR1END1_1", - "MONITOR_WR1END1_2", - "MONITOR_WR1END1_3", - "MONITOR_WR1END1_4", - "MONITOR_WR1END2_0", - "MONITOR_WR1END2_1", - "MONITOR_WR1END2_2", - "MONITOR_WR1END2_3", - "MONITOR_WR1END2_4", - "MONITOR_WR1END3_0", - "MONITOR_WR1END3_1", - "MONITOR_WR1END3_2", - "MONITOR_WR1END3_3", - "MONITOR_WR1END3_4", - "MONITOR_WW2A0_0", - "MONITOR_WW2A0_1", - "MONITOR_WW2A0_2", - "MONITOR_WW2A0_3", - "MONITOR_WW2A0_4", - "MONITOR_WW2A1_0", - "MONITOR_WW2A1_1", - "MONITOR_WW2A1_2", - "MONITOR_WW2A1_3", - "MONITOR_WW2A1_4", - "MONITOR_WW2A2_0", - "MONITOR_WW2A2_1", - "MONITOR_WW2A2_2", - "MONITOR_WW2A2_3", - "MONITOR_WW2A2_4", - "MONITOR_WW2A3_0", - "MONITOR_WW2A3_1", - "MONITOR_WW2A3_2", - "MONITOR_WW2A3_3", - "MONITOR_WW2A3_4", - "MONITOR_WW2END0_0", - "MONITOR_WW2END0_1", - "MONITOR_WW2END0_2", - "MONITOR_WW2END0_3", - "MONITOR_WW2END0_4", - "MONITOR_WW2END1_0", - "MONITOR_WW2END1_1", - "MONITOR_WW2END1_2", - "MONITOR_WW2END1_3", - "MONITOR_WW2END1_4", - "MONITOR_WW2END2_0", - "MONITOR_WW2END2_1", - "MONITOR_WW2END2_2", - "MONITOR_WW2END2_3", - "MONITOR_WW2END2_4", - "MONITOR_WW2END3_0", - "MONITOR_WW2END3_1", - "MONITOR_WW2END3_2", - "MONITOR_WW2END3_3", - "MONITOR_WW2END3_4", - "MONITOR_WW4A0_0", - "MONITOR_WW4A0_1", - "MONITOR_WW4A0_2", - "MONITOR_WW4A0_3", - "MONITOR_WW4A0_4", - "MONITOR_WW4A1_0", - "MONITOR_WW4A1_1", - "MONITOR_WW4A1_2", - "MONITOR_WW4A1_3", - "MONITOR_WW4A1_4", - "MONITOR_WW4A2_0", - "MONITOR_WW4A2_1", - "MONITOR_WW4A2_2", - "MONITOR_WW4A2_3", - "MONITOR_WW4A2_4", - "MONITOR_WW4A3_0", - "MONITOR_WW4A3_1", - "MONITOR_WW4A3_2", - "MONITOR_WW4A3_3", - "MONITOR_WW4A3_4", - "MONITOR_WW4B0_0", - "MONITOR_WW4B0_1", - "MONITOR_WW4B0_2", - "MONITOR_WW4B0_3", - "MONITOR_WW4B0_4", - "MONITOR_WW4B1_0", - "MONITOR_WW4B1_1", - "MONITOR_WW4B1_2", - "MONITOR_WW4B1_3", - "MONITOR_WW4B1_4", - "MONITOR_WW4B2_0", - "MONITOR_WW4B2_1", - "MONITOR_WW4B2_2", - "MONITOR_WW4B2_3", - "MONITOR_WW4B2_4", - "MONITOR_WW4B3_0", - "MONITOR_WW4B3_1", - "MONITOR_WW4B3_2", - "MONITOR_WW4B3_3", - "MONITOR_WW4B3_4", - "MONITOR_WW4C0_0", - "MONITOR_WW4C0_1", - "MONITOR_WW4C0_2", - "MONITOR_WW4C0_3", - "MONITOR_WW4C0_4", - "MONITOR_WW4C1_0", - "MONITOR_WW4C1_1", - "MONITOR_WW4C1_2", - "MONITOR_WW4C1_3", - "MONITOR_WW4C1_4", - "MONITOR_WW4C2_0", - "MONITOR_WW4C2_1", - "MONITOR_WW4C2_2", - "MONITOR_WW4C2_3", - "MONITOR_WW4C2_4", - "MONITOR_WW4C3_0", - "MONITOR_WW4C3_1", - "MONITOR_WW4C3_2", - "MONITOR_WW4C3_3", - "MONITOR_WW4C3_4", - "MONITOR_WW4END0_0", - "MONITOR_WW4END0_1", - "MONITOR_WW4END0_2", - "MONITOR_WW4END0_3", - "MONITOR_WW4END0_4", - "MONITOR_WW4END1_0", - "MONITOR_WW4END1_1", - "MONITOR_WW4END1_2", - "MONITOR_WW4END1_3", - "MONITOR_WW4END1_4", - "MONITOR_WW4END2_0", - "MONITOR_WW4END2_1", - "MONITOR_WW4END2_2", - "MONITOR_WW4END2_3", - "MONITOR_WW4END2_4", - "MONITOR_WW4END3_0", - "MONITOR_WW4END3_1", - "MONITOR_WW4END3_2", - "MONITOR_WW4END3_3", - "MONITOR_WW4END3_4" - ] + "wires": { + "MONITOR_BLOCK_OUTS_B0_0": null, + "MONITOR_BLOCK_OUTS_B0_1": null, + "MONITOR_BLOCK_OUTS_B0_2": null, + "MONITOR_BLOCK_OUTS_B0_3": null, + "MONITOR_BLOCK_OUTS_B0_4": null, + "MONITOR_BLOCK_OUTS_B1_0": null, + "MONITOR_BLOCK_OUTS_B1_1": null, + "MONITOR_BLOCK_OUTS_B1_2": null, + "MONITOR_BLOCK_OUTS_B1_3": null, + "MONITOR_BLOCK_OUTS_B1_4": null, + "MONITOR_BLOCK_OUTS_B2_0": null, + "MONITOR_BLOCK_OUTS_B2_1": null, + "MONITOR_BLOCK_OUTS_B2_2": null, + "MONITOR_BLOCK_OUTS_B2_3": null, + "MONITOR_BLOCK_OUTS_B2_4": null, + "MONITOR_BLOCK_OUTS_B3_0": null, + "MONITOR_BLOCK_OUTS_B3_1": null, + "MONITOR_BLOCK_OUTS_B3_2": null, + "MONITOR_BLOCK_OUTS_B3_3": null, + "MONITOR_BLOCK_OUTS_B3_4": null, + "MONITOR_BYP0_0": null, + "MONITOR_BYP0_1": null, + "MONITOR_BYP0_2": null, + "MONITOR_BYP0_3": null, + "MONITOR_BYP0_4": null, + "MONITOR_BYP1_0": null, + "MONITOR_BYP1_1": null, + "MONITOR_BYP1_2": null, + "MONITOR_BYP1_3": null, + "MONITOR_BYP1_4": null, + "MONITOR_BYP2_0": null, + "MONITOR_BYP2_1": null, + "MONITOR_BYP2_2": null, + "MONITOR_BYP2_3": null, + "MONITOR_BYP2_4": null, + "MONITOR_BYP3_0": null, + "MONITOR_BYP3_1": null, + "MONITOR_BYP3_2": null, + "MONITOR_BYP3_3": null, + "MONITOR_BYP3_4": null, + "MONITOR_BYP4_0": null, + "MONITOR_BYP4_1": null, + "MONITOR_BYP4_2": null, + "MONITOR_BYP4_3": null, + "MONITOR_BYP4_4": null, + "MONITOR_BYP5_0": null, + "MONITOR_BYP5_1": null, + "MONITOR_BYP5_2": null, + "MONITOR_BYP5_3": null, + "MONITOR_BYP5_4": null, + "MONITOR_BYP6_0": null, + "MONITOR_BYP6_1": null, + "MONITOR_BYP6_2": null, + "MONITOR_BYP6_3": null, + "MONITOR_BYP6_4": null, + "MONITOR_BYP7_0": null, + "MONITOR_BYP7_1": null, + "MONITOR_BYP7_2": null, + "MONITOR_BYP7_3": null, + "MONITOR_BYP7_4": null, + "MONITOR_CLK0_0": null, + "MONITOR_CLK0_1": null, + "MONITOR_CLK0_2": null, + "MONITOR_CLK0_3": null, + "MONITOR_CLK0_4": null, + "MONITOR_CLK1_0": null, + "MONITOR_CLK1_1": null, + "MONITOR_CLK1_2": null, + "MONITOR_CLK1_3": null, + "MONITOR_CLK1_4": null, + "MONITOR_CTRL0_0": null, + "MONITOR_CTRL0_1": null, + "MONITOR_CTRL0_2": null, + "MONITOR_CTRL0_3": null, + "MONITOR_CTRL0_4": null, + "MONITOR_CTRL1_0": null, + "MONITOR_CTRL1_1": null, + "MONITOR_CTRL1_2": null, + "MONITOR_CTRL1_3": null, + "MONITOR_CTRL1_4": null, + "MONITOR_EE2A0_0": null, + "MONITOR_EE2A0_1": null, + "MONITOR_EE2A0_2": null, + "MONITOR_EE2A0_3": null, + "MONITOR_EE2A0_4": null, + "MONITOR_EE2A1_0": null, + "MONITOR_EE2A1_1": null, + "MONITOR_EE2A1_2": null, + "MONITOR_EE2A1_3": null, + "MONITOR_EE2A1_4": null, + "MONITOR_EE2A2_0": null, + "MONITOR_EE2A2_1": null, + "MONITOR_EE2A2_2": null, + "MONITOR_EE2A2_3": null, + "MONITOR_EE2A2_4": null, + "MONITOR_EE2A3_0": null, + "MONITOR_EE2A3_1": null, + "MONITOR_EE2A3_2": null, + "MONITOR_EE2A3_3": null, + "MONITOR_EE2A3_4": null, + "MONITOR_EE2BEG0_0": null, + "MONITOR_EE2BEG0_1": null, + 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null, + "MONITOR_WW4END3_2": null, + "MONITOR_WW4END3_3": null, + "MONITOR_WW4END3_4": null + } } diff --git a/zynq7/tile_type_NULL.json b/zynq7/tile_type_NULL.json index 1c00b3c..11b43a3 100644 --- a/zynq7/tile_type_NULL.json +++ b/zynq7/tile_type_NULL.json @@ -2,7 +2,7 @@ "pips": {}, "sites": [], "tile_type": "NULL", - "wires": [ - "DUMMYFOO" - ] + "wires": { + "DUMMYFOO": null + } } diff --git a/zynq7/tile_type_PCIE_NULL.json b/zynq7/tile_type_PCIE_NULL.json index 374eb7c..526cbce 100644 --- a/zynq7/tile_type_PCIE_NULL.json +++ b/zynq7/tile_type_PCIE_NULL.json @@ -2,7 +2,7 @@ "pips": {}, "sites": [], "tile_type": "PCIE_NULL", - "wires": [ - "DUMMYFOO" - ] + "wires": { + "DUMMYFOO": null + } } diff --git a/zynq7/tile_type_PSS0.json b/zynq7/tile_type_PSS0.json index 4cecd95..9ca2f60 100644 --- a/zynq7/tile_type_PSS0.json +++ b/zynq7/tile_type_PSS0.json @@ -2,13687 +2,39927 @@ "pips": { "PSS0.PSS0_LOGIC_OUTS0_0->PSS_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_0" }, "PSS0.PSS0_LOGIC_OUTS0_1->PSS_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_1" }, "PSS0.PSS0_LOGIC_OUTS0_10->PSS_LOGIC_OUTS0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_10" }, "PSS0.PSS0_LOGIC_OUTS0_11->PSS_LOGIC_OUTS0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_11" }, "PSS0.PSS0_LOGIC_OUTS0_12->PSS_LOGIC_OUTS0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_12" }, "PSS0.PSS0_LOGIC_OUTS0_13->PSS_LOGIC_OUTS0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_13" }, "PSS0.PSS0_LOGIC_OUTS0_14->PSS_LOGIC_OUTS0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_14" }, "PSS0.PSS0_LOGIC_OUTS0_15->PSS_LOGIC_OUTS0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_15" }, "PSS0.PSS0_LOGIC_OUTS0_16->PSS_LOGIC_OUTS0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_16" }, "PSS0.PSS0_LOGIC_OUTS0_17->PSS_LOGIC_OUTS0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_17" }, "PSS0.PSS0_LOGIC_OUTS0_18->PSS_LOGIC_OUTS0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_18" }, "PSS0.PSS0_LOGIC_OUTS0_19->PSS_LOGIC_OUTS0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_19" }, "PSS0.PSS0_LOGIC_OUTS0_2->PSS_LOGIC_OUTS0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_2" }, "PSS0.PSS0_LOGIC_OUTS0_3->PSS_LOGIC_OUTS0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_3" }, "PSS0.PSS0_LOGIC_OUTS0_4->PSS_LOGIC_OUTS0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_4" }, "PSS0.PSS0_LOGIC_OUTS0_5->PSS_LOGIC_OUTS0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_5" }, "PSS0.PSS0_LOGIC_OUTS0_6->PSS_LOGIC_OUTS0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_6" }, "PSS0.PSS0_LOGIC_OUTS0_7->PSS_LOGIC_OUTS0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_7" }, "PSS0.PSS0_LOGIC_OUTS0_8->PSS_LOGIC_OUTS0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_8" }, "PSS0.PSS0_LOGIC_OUTS0_9->PSS_LOGIC_OUTS0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_9" }, "PSS0.PSS0_LOGIC_OUTS10_0->PSS_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_0" }, "PSS0.PSS0_LOGIC_OUTS10_1->PSS_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_1" }, "PSS0.PSS0_LOGIC_OUTS10_10->PSS_LOGIC_OUTS10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_10" }, "PSS0.PSS0_LOGIC_OUTS10_11->PSS_LOGIC_OUTS10_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_11" }, "PSS0.PSS0_LOGIC_OUTS10_12->PSS_LOGIC_OUTS10_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_12" }, "PSS0.PSS0_LOGIC_OUTS10_13->PSS_LOGIC_OUTS10_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_13" }, "PSS0.PSS0_LOGIC_OUTS10_14->PSS_LOGIC_OUTS10_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_14" }, "PSS0.PSS0_LOGIC_OUTS10_15->PSS_LOGIC_OUTS10_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_15" }, "PSS0.PSS0_LOGIC_OUTS10_16->PSS_LOGIC_OUTS10_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_16" }, "PSS0.PSS0_LOGIC_OUTS10_17->PSS_LOGIC_OUTS10_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_17" }, "PSS0.PSS0_LOGIC_OUTS10_18->PSS_LOGIC_OUTS10_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_18" }, "PSS0.PSS0_LOGIC_OUTS10_19->PSS_LOGIC_OUTS10_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_19" }, "PSS0.PSS0_LOGIC_OUTS10_2->PSS_LOGIC_OUTS10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_2" }, "PSS0.PSS0_LOGIC_OUTS10_3->PSS_LOGIC_OUTS10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_3" }, "PSS0.PSS0_LOGIC_OUTS10_4->PSS_LOGIC_OUTS10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_4" }, "PSS0.PSS0_LOGIC_OUTS10_5->PSS_LOGIC_OUTS10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_5" }, "PSS0.PSS0_LOGIC_OUTS10_6->PSS_LOGIC_OUTS10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_6" }, "PSS0.PSS0_LOGIC_OUTS10_7->PSS_LOGIC_OUTS10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_7" }, "PSS0.PSS0_LOGIC_OUTS10_8->PSS_LOGIC_OUTS10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_8" }, "PSS0.PSS0_LOGIC_OUTS10_9->PSS_LOGIC_OUTS10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_9" }, "PSS0.PSS0_LOGIC_OUTS11_0->PSS_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_0" }, "PSS0.PSS0_LOGIC_OUTS11_1->PSS_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_1" }, "PSS0.PSS0_LOGIC_OUTS11_10->PSS_LOGIC_OUTS11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_10" }, "PSS0.PSS0_LOGIC_OUTS11_11->PSS_LOGIC_OUTS11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_11" }, "PSS0.PSS0_LOGIC_OUTS11_12->PSS_LOGIC_OUTS11_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_12" }, "PSS0.PSS0_LOGIC_OUTS11_13->PSS_LOGIC_OUTS11_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_13" }, "PSS0.PSS0_LOGIC_OUTS11_14->PSS_LOGIC_OUTS11_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_14" }, "PSS0.PSS0_LOGIC_OUTS11_15->PSS_LOGIC_OUTS11_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_15" }, "PSS0.PSS0_LOGIC_OUTS11_16->PSS_LOGIC_OUTS11_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_16" }, "PSS0.PSS0_LOGIC_OUTS11_17->PSS_LOGIC_OUTS11_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_17" }, "PSS0.PSS0_LOGIC_OUTS11_18->PSS_LOGIC_OUTS11_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_18" }, "PSS0.PSS0_LOGIC_OUTS11_19->PSS_LOGIC_OUTS11_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_19" }, "PSS0.PSS0_LOGIC_OUTS11_2->PSS_LOGIC_OUTS11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_2" }, "PSS0.PSS0_LOGIC_OUTS11_3->PSS_LOGIC_OUTS11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_3" }, "PSS0.PSS0_LOGIC_OUTS11_4->PSS_LOGIC_OUTS11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_4" }, "PSS0.PSS0_LOGIC_OUTS11_5->PSS_LOGIC_OUTS11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_5" }, "PSS0.PSS0_LOGIC_OUTS11_6->PSS_LOGIC_OUTS11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_6" }, "PSS0.PSS0_LOGIC_OUTS11_7->PSS_LOGIC_OUTS11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_7" }, "PSS0.PSS0_LOGIC_OUTS11_8->PSS_LOGIC_OUTS11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_8" }, "PSS0.PSS0_LOGIC_OUTS11_9->PSS_LOGIC_OUTS11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_9" }, "PSS0.PSS0_LOGIC_OUTS12_0->PSS_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_0" }, "PSS0.PSS0_LOGIC_OUTS12_1->PSS_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_1" }, "PSS0.PSS0_LOGIC_OUTS12_10->PSS_LOGIC_OUTS12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_10" }, "PSS0.PSS0_LOGIC_OUTS12_11->PSS_LOGIC_OUTS12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_11" }, "PSS0.PSS0_LOGIC_OUTS12_12->PSS_LOGIC_OUTS12_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_12" }, "PSS0.PSS0_LOGIC_OUTS12_13->PSS_LOGIC_OUTS12_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_13" }, "PSS0.PSS0_LOGIC_OUTS12_14->PSS_LOGIC_OUTS12_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_14" }, "PSS0.PSS0_LOGIC_OUTS12_15->PSS_LOGIC_OUTS12_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_15" }, "PSS0.PSS0_LOGIC_OUTS12_16->PSS_LOGIC_OUTS12_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_16" }, "PSS0.PSS0_LOGIC_OUTS12_17->PSS_LOGIC_OUTS12_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_17" }, "PSS0.PSS0_LOGIC_OUTS12_18->PSS_LOGIC_OUTS12_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_18" }, "PSS0.PSS0_LOGIC_OUTS12_19->PSS_LOGIC_OUTS12_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_19" }, "PSS0.PSS0_LOGIC_OUTS12_2->PSS_LOGIC_OUTS12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_2" }, "PSS0.PSS0_LOGIC_OUTS12_3->PSS_LOGIC_OUTS12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_3" }, "PSS0.PSS0_LOGIC_OUTS12_4->PSS_LOGIC_OUTS12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_4" }, "PSS0.PSS0_LOGIC_OUTS12_5->PSS_LOGIC_OUTS12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_5" }, "PSS0.PSS0_LOGIC_OUTS12_6->PSS_LOGIC_OUTS12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_6" }, "PSS0.PSS0_LOGIC_OUTS12_7->PSS_LOGIC_OUTS12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_7" }, "PSS0.PSS0_LOGIC_OUTS12_8->PSS_LOGIC_OUTS12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_8" }, "PSS0.PSS0_LOGIC_OUTS12_9->PSS_LOGIC_OUTS12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_9" }, "PSS0.PSS0_LOGIC_OUTS13_0->PSS_LOGIC_OUTS13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_0" }, "PSS0.PSS0_LOGIC_OUTS13_1->PSS_LOGIC_OUTS13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_1" }, "PSS0.PSS0_LOGIC_OUTS13_10->PSS_LOGIC_OUTS13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_10" }, "PSS0.PSS0_LOGIC_OUTS13_11->PSS_LOGIC_OUTS13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_11" }, "PSS0.PSS0_LOGIC_OUTS13_12->PSS_LOGIC_OUTS13_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_12" }, "PSS0.PSS0_LOGIC_OUTS13_13->PSS_LOGIC_OUTS13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_13" }, "PSS0.PSS0_LOGIC_OUTS13_14->PSS_LOGIC_OUTS13_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_14" }, "PSS0.PSS0_LOGIC_OUTS13_15->PSS_LOGIC_OUTS13_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_15" }, "PSS0.PSS0_LOGIC_OUTS13_16->PSS_LOGIC_OUTS13_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_16" }, "PSS0.PSS0_LOGIC_OUTS13_17->PSS_LOGIC_OUTS13_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_17" }, "PSS0.PSS0_LOGIC_OUTS13_18->PSS_LOGIC_OUTS13_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_18" }, "PSS0.PSS0_LOGIC_OUTS13_19->PSS_LOGIC_OUTS13_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_19" }, "PSS0.PSS0_LOGIC_OUTS13_2->PSS_LOGIC_OUTS13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_2" }, "PSS0.PSS0_LOGIC_OUTS13_3->PSS_LOGIC_OUTS13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_3" }, "PSS0.PSS0_LOGIC_OUTS13_4->PSS_LOGIC_OUTS13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_4" }, "PSS0.PSS0_LOGIC_OUTS13_5->PSS_LOGIC_OUTS13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_5" }, "PSS0.PSS0_LOGIC_OUTS13_6->PSS_LOGIC_OUTS13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_6" }, "PSS0.PSS0_LOGIC_OUTS13_7->PSS_LOGIC_OUTS13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_7" }, "PSS0.PSS0_LOGIC_OUTS13_8->PSS_LOGIC_OUTS13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_8" }, "PSS0.PSS0_LOGIC_OUTS13_9->PSS_LOGIC_OUTS13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_9" }, "PSS0.PSS0_LOGIC_OUTS14_0->PSS_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_0" }, "PSS0.PSS0_LOGIC_OUTS14_1->PSS_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_1" }, "PSS0.PSS0_LOGIC_OUTS14_10->PSS_LOGIC_OUTS14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_10" }, "PSS0.PSS0_LOGIC_OUTS14_11->PSS_LOGIC_OUTS14_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_11" }, "PSS0.PSS0_LOGIC_OUTS14_12->PSS_LOGIC_OUTS14_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_12" }, "PSS0.PSS0_LOGIC_OUTS14_13->PSS_LOGIC_OUTS14_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_13" }, "PSS0.PSS0_LOGIC_OUTS14_14->PSS_LOGIC_OUTS14_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_14" }, "PSS0.PSS0_LOGIC_OUTS14_15->PSS_LOGIC_OUTS14_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_15" }, "PSS0.PSS0_LOGIC_OUTS14_16->PSS_LOGIC_OUTS14_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_16" }, "PSS0.PSS0_LOGIC_OUTS14_17->PSS_LOGIC_OUTS14_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_17" }, "PSS0.PSS0_LOGIC_OUTS14_18->PSS_LOGIC_OUTS14_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_18" }, "PSS0.PSS0_LOGIC_OUTS14_19->PSS_LOGIC_OUTS14_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_19" }, "PSS0.PSS0_LOGIC_OUTS14_2->PSS_LOGIC_OUTS14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_2" }, "PSS0.PSS0_LOGIC_OUTS14_3->PSS_LOGIC_OUTS14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_3" }, "PSS0.PSS0_LOGIC_OUTS14_4->PSS_LOGIC_OUTS14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_4" }, "PSS0.PSS0_LOGIC_OUTS14_5->PSS_LOGIC_OUTS14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_5" }, "PSS0.PSS0_LOGIC_OUTS14_6->PSS_LOGIC_OUTS14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_6" }, "PSS0.PSS0_LOGIC_OUTS14_7->PSS_LOGIC_OUTS14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_7" }, "PSS0.PSS0_LOGIC_OUTS14_8->PSS_LOGIC_OUTS14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_8" }, "PSS0.PSS0_LOGIC_OUTS14_9->PSS_LOGIC_OUTS14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_9" }, "PSS0.PSS0_LOGIC_OUTS15_0->PSS_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_0" }, "PSS0.PSS0_LOGIC_OUTS15_1->PSS_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_1" }, "PSS0.PSS0_LOGIC_OUTS15_10->PSS_LOGIC_OUTS15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_10" }, "PSS0.PSS0_LOGIC_OUTS15_11->PSS_LOGIC_OUTS15_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_11" }, "PSS0.PSS0_LOGIC_OUTS15_12->PSS_LOGIC_OUTS15_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_12" }, "PSS0.PSS0_LOGIC_OUTS15_13->PSS_LOGIC_OUTS15_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_13" }, "PSS0.PSS0_LOGIC_OUTS15_14->PSS_LOGIC_OUTS15_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_14" }, "PSS0.PSS0_LOGIC_OUTS15_15->PSS_LOGIC_OUTS15_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_15" }, "PSS0.PSS0_LOGIC_OUTS15_16->PSS_LOGIC_OUTS15_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_16" }, "PSS0.PSS0_LOGIC_OUTS15_17->PSS_LOGIC_OUTS15_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_17" }, "PSS0.PSS0_LOGIC_OUTS15_18->PSS_LOGIC_OUTS15_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_18" }, "PSS0.PSS0_LOGIC_OUTS15_19->PSS_LOGIC_OUTS15_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_19" }, "PSS0.PSS0_LOGIC_OUTS15_2->PSS_LOGIC_OUTS15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_2" }, "PSS0.PSS0_LOGIC_OUTS15_3->PSS_LOGIC_OUTS15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_3" }, "PSS0.PSS0_LOGIC_OUTS15_4->PSS_LOGIC_OUTS15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_4" }, "PSS0.PSS0_LOGIC_OUTS15_5->PSS_LOGIC_OUTS15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_5" }, "PSS0.PSS0_LOGIC_OUTS15_6->PSS_LOGIC_OUTS15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_6" }, "PSS0.PSS0_LOGIC_OUTS15_7->PSS_LOGIC_OUTS15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_7" }, "PSS0.PSS0_LOGIC_OUTS15_8->PSS_LOGIC_OUTS15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_8" }, "PSS0.PSS0_LOGIC_OUTS15_9->PSS_LOGIC_OUTS15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_9" }, "PSS0.PSS0_LOGIC_OUTS16_0->PSS_LOGIC_OUTS16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_0" }, "PSS0.PSS0_LOGIC_OUTS16_1->PSS_LOGIC_OUTS16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_1" }, "PSS0.PSS0_LOGIC_OUTS16_10->PSS_LOGIC_OUTS16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_10" }, "PSS0.PSS0_LOGIC_OUTS16_11->PSS_LOGIC_OUTS16_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_11" }, "PSS0.PSS0_LOGIC_OUTS16_12->PSS_LOGIC_OUTS16_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_12" }, "PSS0.PSS0_LOGIC_OUTS16_13->PSS_LOGIC_OUTS16_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_13" }, "PSS0.PSS0_LOGIC_OUTS16_14->PSS_LOGIC_OUTS16_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_14" }, "PSS0.PSS0_LOGIC_OUTS16_15->PSS_LOGIC_OUTS16_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_15" }, "PSS0.PSS0_LOGIC_OUTS16_16->PSS_LOGIC_OUTS16_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_16" }, "PSS0.PSS0_LOGIC_OUTS16_17->PSS_LOGIC_OUTS16_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_17" }, "PSS0.PSS0_LOGIC_OUTS16_18->PSS_LOGIC_OUTS16_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_18" }, "PSS0.PSS0_LOGIC_OUTS16_19->PSS_LOGIC_OUTS16_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_19" }, "PSS0.PSS0_LOGIC_OUTS16_2->PSS_LOGIC_OUTS16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_2" }, "PSS0.PSS0_LOGIC_OUTS16_3->PSS_LOGIC_OUTS16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_3" }, "PSS0.PSS0_LOGIC_OUTS16_4->PSS_LOGIC_OUTS16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_4" }, "PSS0.PSS0_LOGIC_OUTS16_5->PSS_LOGIC_OUTS16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_5" }, "PSS0.PSS0_LOGIC_OUTS16_6->PSS_LOGIC_OUTS16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_6" }, "PSS0.PSS0_LOGIC_OUTS16_7->PSS_LOGIC_OUTS16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_7" }, "PSS0.PSS0_LOGIC_OUTS16_8->PSS_LOGIC_OUTS16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_8" }, "PSS0.PSS0_LOGIC_OUTS16_9->PSS_LOGIC_OUTS16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_9" }, "PSS0.PSS0_LOGIC_OUTS17_0->PSS_LOGIC_OUTS17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_0" }, "PSS0.PSS0_LOGIC_OUTS17_1->PSS_LOGIC_OUTS17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_1" }, "PSS0.PSS0_LOGIC_OUTS17_10->PSS_LOGIC_OUTS17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_10" }, "PSS0.PSS0_LOGIC_OUTS17_11->PSS_LOGIC_OUTS17_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_11" }, "PSS0.PSS0_LOGIC_OUTS17_12->PSS_LOGIC_OUTS17_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_12" }, "PSS0.PSS0_LOGIC_OUTS17_13->PSS_LOGIC_OUTS17_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_13" }, "PSS0.PSS0_LOGIC_OUTS17_14->PSS_LOGIC_OUTS17_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_14" }, "PSS0.PSS0_LOGIC_OUTS17_15->PSS_LOGIC_OUTS17_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_15" }, "PSS0.PSS0_LOGIC_OUTS17_16->PSS_LOGIC_OUTS17_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_16" }, "PSS0.PSS0_LOGIC_OUTS17_17->PSS_LOGIC_OUTS17_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_17" }, "PSS0.PSS0_LOGIC_OUTS17_18->PSS_LOGIC_OUTS17_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_18" }, "PSS0.PSS0_LOGIC_OUTS17_19->PSS_LOGIC_OUTS17_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_19" }, "PSS0.PSS0_LOGIC_OUTS17_2->PSS_LOGIC_OUTS17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_2" }, "PSS0.PSS0_LOGIC_OUTS17_3->PSS_LOGIC_OUTS17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_3" }, "PSS0.PSS0_LOGIC_OUTS17_4->PSS_LOGIC_OUTS17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_4" }, "PSS0.PSS0_LOGIC_OUTS17_5->PSS_LOGIC_OUTS17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_5" }, "PSS0.PSS0_LOGIC_OUTS17_6->PSS_LOGIC_OUTS17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_6" }, "PSS0.PSS0_LOGIC_OUTS17_7->PSS_LOGIC_OUTS17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_7" }, "PSS0.PSS0_LOGIC_OUTS17_8->PSS_LOGIC_OUTS17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_8" }, "PSS0.PSS0_LOGIC_OUTS17_9->PSS_LOGIC_OUTS17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_9" }, "PSS0.PSS0_LOGIC_OUTS18_0->PSS_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_0" }, "PSS0.PSS0_LOGIC_OUTS18_1->PSS_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_1" }, "PSS0.PSS0_LOGIC_OUTS18_10->PSS_LOGIC_OUTS18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_10" }, "PSS0.PSS0_LOGIC_OUTS18_11->PSS_LOGIC_OUTS18_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_11" }, "PSS0.PSS0_LOGIC_OUTS18_12->PSS_LOGIC_OUTS18_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_12" }, "PSS0.PSS0_LOGIC_OUTS18_13->PSS_LOGIC_OUTS18_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_13" }, "PSS0.PSS0_LOGIC_OUTS18_14->PSS_LOGIC_OUTS18_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_14" }, "PSS0.PSS0_LOGIC_OUTS18_15->PSS_LOGIC_OUTS18_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_15" }, "PSS0.PSS0_LOGIC_OUTS18_16->PSS_LOGIC_OUTS18_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_16" }, "PSS0.PSS0_LOGIC_OUTS18_17->PSS_LOGIC_OUTS18_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_17" }, "PSS0.PSS0_LOGIC_OUTS18_18->PSS_LOGIC_OUTS18_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_18" }, "PSS0.PSS0_LOGIC_OUTS18_19->PSS_LOGIC_OUTS18_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_19" }, "PSS0.PSS0_LOGIC_OUTS18_2->PSS_LOGIC_OUTS18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_2" }, "PSS0.PSS0_LOGIC_OUTS18_3->PSS_LOGIC_OUTS18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_3" }, "PSS0.PSS0_LOGIC_OUTS18_4->PSS_LOGIC_OUTS18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_4" }, "PSS0.PSS0_LOGIC_OUTS18_5->PSS_LOGIC_OUTS18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_5" }, "PSS0.PSS0_LOGIC_OUTS18_6->PSS_LOGIC_OUTS18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_6" }, "PSS0.PSS0_LOGIC_OUTS18_7->PSS_LOGIC_OUTS18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_7" }, "PSS0.PSS0_LOGIC_OUTS18_8->PSS_LOGIC_OUTS18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_8" }, "PSS0.PSS0_LOGIC_OUTS18_9->PSS_LOGIC_OUTS18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_9" }, "PSS0.PSS0_LOGIC_OUTS19_0->PSS_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_0" }, "PSS0.PSS0_LOGIC_OUTS19_1->PSS_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_1" }, "PSS0.PSS0_LOGIC_OUTS19_10->PSS_LOGIC_OUTS19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_10" }, "PSS0.PSS0_LOGIC_OUTS19_11->PSS_LOGIC_OUTS19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_11" }, "PSS0.PSS0_LOGIC_OUTS19_12->PSS_LOGIC_OUTS19_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_12" }, "PSS0.PSS0_LOGIC_OUTS19_13->PSS_LOGIC_OUTS19_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_13" }, "PSS0.PSS0_LOGIC_OUTS19_14->PSS_LOGIC_OUTS19_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_14" }, "PSS0.PSS0_LOGIC_OUTS19_15->PSS_LOGIC_OUTS19_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_15" }, "PSS0.PSS0_LOGIC_OUTS19_16->PSS_LOGIC_OUTS19_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_16" }, "PSS0.PSS0_LOGIC_OUTS19_17->PSS_LOGIC_OUTS19_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_17" }, "PSS0.PSS0_LOGIC_OUTS19_18->PSS_LOGIC_OUTS19_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_18" }, "PSS0.PSS0_LOGIC_OUTS19_19->PSS_LOGIC_OUTS19_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_19" }, "PSS0.PSS0_LOGIC_OUTS19_2->PSS_LOGIC_OUTS19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_2" }, "PSS0.PSS0_LOGIC_OUTS19_3->PSS_LOGIC_OUTS19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_3" }, "PSS0.PSS0_LOGIC_OUTS19_4->PSS_LOGIC_OUTS19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_4" }, "PSS0.PSS0_LOGIC_OUTS19_5->PSS_LOGIC_OUTS19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_5" }, "PSS0.PSS0_LOGIC_OUTS19_6->PSS_LOGIC_OUTS19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_6" }, "PSS0.PSS0_LOGIC_OUTS19_7->PSS_LOGIC_OUTS19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_7" }, "PSS0.PSS0_LOGIC_OUTS19_8->PSS_LOGIC_OUTS19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_8" }, "PSS0.PSS0_LOGIC_OUTS19_9->PSS_LOGIC_OUTS19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_9" }, "PSS0.PSS0_LOGIC_OUTS1_0->PSS_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_0" }, "PSS0.PSS0_LOGIC_OUTS1_1->PSS_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_1" }, "PSS0.PSS0_LOGIC_OUTS1_10->PSS_LOGIC_OUTS1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_10" }, "PSS0.PSS0_LOGIC_OUTS1_11->PSS_LOGIC_OUTS1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_11" }, "PSS0.PSS0_LOGIC_OUTS1_12->PSS_LOGIC_OUTS1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_12" }, "PSS0.PSS0_LOGIC_OUTS1_13->PSS_LOGIC_OUTS1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_13" }, "PSS0.PSS0_LOGIC_OUTS1_14->PSS_LOGIC_OUTS1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_14" }, "PSS0.PSS0_LOGIC_OUTS1_15->PSS_LOGIC_OUTS1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_15" }, "PSS0.PSS0_LOGIC_OUTS1_16->PSS_LOGIC_OUTS1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_16" }, "PSS0.PSS0_LOGIC_OUTS1_17->PSS_LOGIC_OUTS1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_17" }, "PSS0.PSS0_LOGIC_OUTS1_18->PSS_LOGIC_OUTS1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_18" }, "PSS0.PSS0_LOGIC_OUTS1_19->PSS_LOGIC_OUTS1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_19" }, "PSS0.PSS0_LOGIC_OUTS1_2->PSS_LOGIC_OUTS1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_2" }, "PSS0.PSS0_LOGIC_OUTS1_3->PSS_LOGIC_OUTS1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_3" }, "PSS0.PSS0_LOGIC_OUTS1_4->PSS_LOGIC_OUTS1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_4" }, "PSS0.PSS0_LOGIC_OUTS1_5->PSS_LOGIC_OUTS1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_5" }, "PSS0.PSS0_LOGIC_OUTS1_6->PSS_LOGIC_OUTS1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_6" }, "PSS0.PSS0_LOGIC_OUTS1_7->PSS_LOGIC_OUTS1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_7" }, "PSS0.PSS0_LOGIC_OUTS1_8->PSS_LOGIC_OUTS1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_8" }, "PSS0.PSS0_LOGIC_OUTS1_9->PSS_LOGIC_OUTS1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_9" }, "PSS0.PSS0_LOGIC_OUTS20_0->PSS_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_0" }, "PSS0.PSS0_LOGIC_OUTS20_1->PSS_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_1" }, "PSS0.PSS0_LOGIC_OUTS20_10->PSS_LOGIC_OUTS20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_10" }, "PSS0.PSS0_LOGIC_OUTS20_11->PSS_LOGIC_OUTS20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_11" }, "PSS0.PSS0_LOGIC_OUTS20_12->PSS_LOGIC_OUTS20_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_12" }, "PSS0.PSS0_LOGIC_OUTS20_13->PSS_LOGIC_OUTS20_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_13" }, "PSS0.PSS0_LOGIC_OUTS20_14->PSS_LOGIC_OUTS20_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_14" }, "PSS0.PSS0_LOGIC_OUTS20_15->PSS_LOGIC_OUTS20_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_15" }, "PSS0.PSS0_LOGIC_OUTS20_16->PSS_LOGIC_OUTS20_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_16" }, "PSS0.PSS0_LOGIC_OUTS20_17->PSS_LOGIC_OUTS20_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_17" }, "PSS0.PSS0_LOGIC_OUTS20_18->PSS_LOGIC_OUTS20_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_18" }, "PSS0.PSS0_LOGIC_OUTS20_19->PSS_LOGIC_OUTS20_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_19" }, "PSS0.PSS0_LOGIC_OUTS20_2->PSS_LOGIC_OUTS20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_2" }, "PSS0.PSS0_LOGIC_OUTS20_3->PSS_LOGIC_OUTS20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_3" }, "PSS0.PSS0_LOGIC_OUTS20_4->PSS_LOGIC_OUTS20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_4" }, "PSS0.PSS0_LOGIC_OUTS20_5->PSS_LOGIC_OUTS20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_5" }, "PSS0.PSS0_LOGIC_OUTS20_6->PSS_LOGIC_OUTS20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_6" }, "PSS0.PSS0_LOGIC_OUTS20_7->PSS_LOGIC_OUTS20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_7" }, "PSS0.PSS0_LOGIC_OUTS20_8->PSS_LOGIC_OUTS20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_8" }, "PSS0.PSS0_LOGIC_OUTS20_9->PSS_LOGIC_OUTS20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_9" }, "PSS0.PSS0_LOGIC_OUTS21_0->PSS_LOGIC_OUTS21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_0" }, "PSS0.PSS0_LOGIC_OUTS21_1->PSS_LOGIC_OUTS21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_1" }, "PSS0.PSS0_LOGIC_OUTS21_10->PSS_LOGIC_OUTS21_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_10" }, "PSS0.PSS0_LOGIC_OUTS21_11->PSS_LOGIC_OUTS21_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_11" }, "PSS0.PSS0_LOGIC_OUTS21_12->PSS_LOGIC_OUTS21_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_12" }, "PSS0.PSS0_LOGIC_OUTS21_13->PSS_LOGIC_OUTS21_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_13" }, "PSS0.PSS0_LOGIC_OUTS21_14->PSS_LOGIC_OUTS21_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_14" }, "PSS0.PSS0_LOGIC_OUTS21_15->PSS_LOGIC_OUTS21_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_15" }, "PSS0.PSS0_LOGIC_OUTS21_16->PSS_LOGIC_OUTS21_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_16" }, "PSS0.PSS0_LOGIC_OUTS21_17->PSS_LOGIC_OUTS21_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_17" }, "PSS0.PSS0_LOGIC_OUTS21_18->PSS_LOGIC_OUTS21_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_18" }, "PSS0.PSS0_LOGIC_OUTS21_19->PSS_LOGIC_OUTS21_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_19" }, "PSS0.PSS0_LOGIC_OUTS21_2->PSS_LOGIC_OUTS21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_2" }, "PSS0.PSS0_LOGIC_OUTS21_3->PSS_LOGIC_OUTS21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_3" }, "PSS0.PSS0_LOGIC_OUTS21_4->PSS_LOGIC_OUTS21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_4" }, "PSS0.PSS0_LOGIC_OUTS21_5->PSS_LOGIC_OUTS21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_5" }, "PSS0.PSS0_LOGIC_OUTS21_6->PSS_LOGIC_OUTS21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_6" }, "PSS0.PSS0_LOGIC_OUTS21_7->PSS_LOGIC_OUTS21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_7" }, "PSS0.PSS0_LOGIC_OUTS21_8->PSS_LOGIC_OUTS21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_8" }, "PSS0.PSS0_LOGIC_OUTS21_9->PSS_LOGIC_OUTS21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_9" }, "PSS0.PSS0_LOGIC_OUTS22_0->PSS_LOGIC_OUTS22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_0" }, "PSS0.PSS0_LOGIC_OUTS22_1->PSS_LOGIC_OUTS22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_1" }, "PSS0.PSS0_LOGIC_OUTS22_10->PSS_LOGIC_OUTS22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_10" }, "PSS0.PSS0_LOGIC_OUTS22_11->PSS_LOGIC_OUTS22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_11" }, "PSS0.PSS0_LOGIC_OUTS22_12->PSS_LOGIC_OUTS22_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_12" }, "PSS0.PSS0_LOGIC_OUTS22_13->PSS_LOGIC_OUTS22_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_13" }, "PSS0.PSS0_LOGIC_OUTS22_14->PSS_LOGIC_OUTS22_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_14" }, "PSS0.PSS0_LOGIC_OUTS22_15->PSS_LOGIC_OUTS22_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_15" }, "PSS0.PSS0_LOGIC_OUTS22_16->PSS_LOGIC_OUTS22_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_16" }, "PSS0.PSS0_LOGIC_OUTS22_17->PSS_LOGIC_OUTS22_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_17" }, "PSS0.PSS0_LOGIC_OUTS22_18->PSS_LOGIC_OUTS22_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_18" }, "PSS0.PSS0_LOGIC_OUTS22_19->PSS_LOGIC_OUTS22_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_19" }, "PSS0.PSS0_LOGIC_OUTS22_2->PSS_LOGIC_OUTS22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_2" }, "PSS0.PSS0_LOGIC_OUTS22_3->PSS_LOGIC_OUTS22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_3" }, "PSS0.PSS0_LOGIC_OUTS22_4->PSS_LOGIC_OUTS22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_4" }, "PSS0.PSS0_LOGIC_OUTS22_5->PSS_LOGIC_OUTS22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_5" }, "PSS0.PSS0_LOGIC_OUTS22_6->PSS_LOGIC_OUTS22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_6" }, "PSS0.PSS0_LOGIC_OUTS22_7->PSS_LOGIC_OUTS22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_7" }, "PSS0.PSS0_LOGIC_OUTS22_8->PSS_LOGIC_OUTS22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_8" }, "PSS0.PSS0_LOGIC_OUTS22_9->PSS_LOGIC_OUTS22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_9" }, "PSS0.PSS0_LOGIC_OUTS23_0->PSS_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_0" }, "PSS0.PSS0_LOGIC_OUTS23_1->PSS_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_1" }, "PSS0.PSS0_LOGIC_OUTS23_10->PSS_LOGIC_OUTS23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_10" }, "PSS0.PSS0_LOGIC_OUTS23_11->PSS_LOGIC_OUTS23_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_11" }, "PSS0.PSS0_LOGIC_OUTS23_12->PSS_LOGIC_OUTS23_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_12" }, "PSS0.PSS0_LOGIC_OUTS23_13->PSS_LOGIC_OUTS23_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_13" }, "PSS0.PSS0_LOGIC_OUTS23_14->PSS_LOGIC_OUTS23_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_14" }, "PSS0.PSS0_LOGIC_OUTS23_15->PSS_LOGIC_OUTS23_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_15" }, "PSS0.PSS0_LOGIC_OUTS23_16->PSS_LOGIC_OUTS23_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_16" }, "PSS0.PSS0_LOGIC_OUTS23_17->PSS_LOGIC_OUTS23_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_17" }, "PSS0.PSS0_LOGIC_OUTS23_18->PSS_LOGIC_OUTS23_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_18" }, "PSS0.PSS0_LOGIC_OUTS23_19->PSS_LOGIC_OUTS23_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_19" }, "PSS0.PSS0_LOGIC_OUTS23_2->PSS_LOGIC_OUTS23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_2" }, "PSS0.PSS0_LOGIC_OUTS23_3->PSS_LOGIC_OUTS23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_3" }, "PSS0.PSS0_LOGIC_OUTS23_4->PSS_LOGIC_OUTS23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_4" }, "PSS0.PSS0_LOGIC_OUTS23_5->PSS_LOGIC_OUTS23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_5" }, "PSS0.PSS0_LOGIC_OUTS23_6->PSS_LOGIC_OUTS23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_6" }, "PSS0.PSS0_LOGIC_OUTS23_7->PSS_LOGIC_OUTS23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_7" }, "PSS0.PSS0_LOGIC_OUTS23_8->PSS_LOGIC_OUTS23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_8" }, "PSS0.PSS0_LOGIC_OUTS23_9->PSS_LOGIC_OUTS23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_9" }, "PSS0.PSS0_LOGIC_OUTS2_0->PSS_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_0" }, "PSS0.PSS0_LOGIC_OUTS2_1->PSS_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_1" }, "PSS0.PSS0_LOGIC_OUTS2_10->PSS_LOGIC_OUTS2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_10" }, "PSS0.PSS0_LOGIC_OUTS2_11->PSS_LOGIC_OUTS2_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_11" }, "PSS0.PSS0_LOGIC_OUTS2_12->PSS_LOGIC_OUTS2_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_12" }, "PSS0.PSS0_LOGIC_OUTS2_13->PSS_LOGIC_OUTS2_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_13" }, "PSS0.PSS0_LOGIC_OUTS2_14->PSS_LOGIC_OUTS2_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_14" }, "PSS0.PSS0_LOGIC_OUTS2_15->PSS_LOGIC_OUTS2_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_15" }, "PSS0.PSS0_LOGIC_OUTS2_16->PSS_LOGIC_OUTS2_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_16" }, "PSS0.PSS0_LOGIC_OUTS2_17->PSS_LOGIC_OUTS2_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_17" }, "PSS0.PSS0_LOGIC_OUTS2_18->PSS_LOGIC_OUTS2_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_18" }, "PSS0.PSS0_LOGIC_OUTS2_19->PSS_LOGIC_OUTS2_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_19" }, "PSS0.PSS0_LOGIC_OUTS2_2->PSS_LOGIC_OUTS2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_2" }, "PSS0.PSS0_LOGIC_OUTS2_3->PSS_LOGIC_OUTS2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_3" }, "PSS0.PSS0_LOGIC_OUTS2_4->PSS_LOGIC_OUTS2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_4" }, "PSS0.PSS0_LOGIC_OUTS2_5->PSS_LOGIC_OUTS2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_5" }, "PSS0.PSS0_LOGIC_OUTS2_6->PSS_LOGIC_OUTS2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_6" }, "PSS0.PSS0_LOGIC_OUTS2_7->PSS_LOGIC_OUTS2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_7" }, "PSS0.PSS0_LOGIC_OUTS2_8->PSS_LOGIC_OUTS2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_8" }, "PSS0.PSS0_LOGIC_OUTS2_9->PSS_LOGIC_OUTS2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_9" }, "PSS0.PSS0_LOGIC_OUTS3_0->PSS_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_0" }, "PSS0.PSS0_LOGIC_OUTS3_1->PSS_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_1" }, "PSS0.PSS0_LOGIC_OUTS3_10->PSS_LOGIC_OUTS3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_10" }, "PSS0.PSS0_LOGIC_OUTS3_11->PSS_LOGIC_OUTS3_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_11" }, "PSS0.PSS0_LOGIC_OUTS3_12->PSS_LOGIC_OUTS3_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_12" }, "PSS0.PSS0_LOGIC_OUTS3_13->PSS_LOGIC_OUTS3_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_13" }, "PSS0.PSS0_LOGIC_OUTS3_14->PSS_LOGIC_OUTS3_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_14" }, "PSS0.PSS0_LOGIC_OUTS3_15->PSS_LOGIC_OUTS3_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_15" }, "PSS0.PSS0_LOGIC_OUTS3_16->PSS_LOGIC_OUTS3_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_16" }, "PSS0.PSS0_LOGIC_OUTS3_17->PSS_LOGIC_OUTS3_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_17" }, "PSS0.PSS0_LOGIC_OUTS3_18->PSS_LOGIC_OUTS3_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_18" }, "PSS0.PSS0_LOGIC_OUTS3_19->PSS_LOGIC_OUTS3_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_19" }, "PSS0.PSS0_LOGIC_OUTS3_2->PSS_LOGIC_OUTS3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_2" }, "PSS0.PSS0_LOGIC_OUTS3_3->PSS_LOGIC_OUTS3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_3" }, "PSS0.PSS0_LOGIC_OUTS3_4->PSS_LOGIC_OUTS3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_4" }, "PSS0.PSS0_LOGIC_OUTS3_5->PSS_LOGIC_OUTS3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_5" }, "PSS0.PSS0_LOGIC_OUTS3_6->PSS_LOGIC_OUTS3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_6" }, "PSS0.PSS0_LOGIC_OUTS3_7->PSS_LOGIC_OUTS3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_7" }, "PSS0.PSS0_LOGIC_OUTS3_8->PSS_LOGIC_OUTS3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_8" }, "PSS0.PSS0_LOGIC_OUTS3_9->PSS_LOGIC_OUTS3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_9" }, "PSS0.PSS0_LOGIC_OUTS4_0->PSS_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_0" }, "PSS0.PSS0_LOGIC_OUTS4_1->PSS_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_1" }, "PSS0.PSS0_LOGIC_OUTS4_10->PSS_LOGIC_OUTS4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_10" }, "PSS0.PSS0_LOGIC_OUTS4_11->PSS_LOGIC_OUTS4_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_11" }, "PSS0.PSS0_LOGIC_OUTS4_12->PSS_LOGIC_OUTS4_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_12" }, "PSS0.PSS0_LOGIC_OUTS4_13->PSS_LOGIC_OUTS4_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_13" }, "PSS0.PSS0_LOGIC_OUTS4_14->PSS_LOGIC_OUTS4_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_14" }, "PSS0.PSS0_LOGIC_OUTS4_15->PSS_LOGIC_OUTS4_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_15" }, "PSS0.PSS0_LOGIC_OUTS4_16->PSS_LOGIC_OUTS4_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_16" }, "PSS0.PSS0_LOGIC_OUTS4_17->PSS_LOGIC_OUTS4_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_17" }, "PSS0.PSS0_LOGIC_OUTS4_18->PSS_LOGIC_OUTS4_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_18" }, "PSS0.PSS0_LOGIC_OUTS4_19->PSS_LOGIC_OUTS4_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_19" }, "PSS0.PSS0_LOGIC_OUTS4_2->PSS_LOGIC_OUTS4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_2" }, "PSS0.PSS0_LOGIC_OUTS4_3->PSS_LOGIC_OUTS4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_3" }, "PSS0.PSS0_LOGIC_OUTS4_4->PSS_LOGIC_OUTS4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_4" }, "PSS0.PSS0_LOGIC_OUTS4_5->PSS_LOGIC_OUTS4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_5" }, "PSS0.PSS0_LOGIC_OUTS4_6->PSS_LOGIC_OUTS4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_6" }, "PSS0.PSS0_LOGIC_OUTS4_7->PSS_LOGIC_OUTS4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_7" }, "PSS0.PSS0_LOGIC_OUTS4_8->PSS_LOGIC_OUTS4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_8" }, "PSS0.PSS0_LOGIC_OUTS4_9->PSS_LOGIC_OUTS4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_9" }, "PSS0.PSS0_LOGIC_OUTS5_0->PSS_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_0" }, "PSS0.PSS0_LOGIC_OUTS5_1->PSS_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_1" }, "PSS0.PSS0_LOGIC_OUTS5_10->PSS_LOGIC_OUTS5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_10" }, "PSS0.PSS0_LOGIC_OUTS5_11->PSS_LOGIC_OUTS5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_11" }, "PSS0.PSS0_LOGIC_OUTS5_12->PSS_LOGIC_OUTS5_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_12" }, "PSS0.PSS0_LOGIC_OUTS5_13->PSS_LOGIC_OUTS5_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_13" }, "PSS0.PSS0_LOGIC_OUTS5_14->PSS_LOGIC_OUTS5_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_14" }, "PSS0.PSS0_LOGIC_OUTS5_15->PSS_LOGIC_OUTS5_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_15" }, "PSS0.PSS0_LOGIC_OUTS5_16->PSS_LOGIC_OUTS5_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_16" }, "PSS0.PSS0_LOGIC_OUTS5_17->PSS_LOGIC_OUTS5_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_17" }, "PSS0.PSS0_LOGIC_OUTS5_18->PSS_LOGIC_OUTS5_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_18" }, "PSS0.PSS0_LOGIC_OUTS5_19->PSS_LOGIC_OUTS5_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_19" }, "PSS0.PSS0_LOGIC_OUTS5_2->PSS_LOGIC_OUTS5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_2" }, "PSS0.PSS0_LOGIC_OUTS5_3->PSS_LOGIC_OUTS5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_3" }, "PSS0.PSS0_LOGIC_OUTS5_4->PSS_LOGIC_OUTS5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_4" }, "PSS0.PSS0_LOGIC_OUTS5_5->PSS_LOGIC_OUTS5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_5" }, "PSS0.PSS0_LOGIC_OUTS5_6->PSS_LOGIC_OUTS5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_6" }, "PSS0.PSS0_LOGIC_OUTS5_7->PSS_LOGIC_OUTS5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_7" }, "PSS0.PSS0_LOGIC_OUTS5_8->PSS_LOGIC_OUTS5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_8" }, "PSS0.PSS0_LOGIC_OUTS5_9->PSS_LOGIC_OUTS5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_9" }, "PSS0.PSS0_LOGIC_OUTS6_0->PSS_LOGIC_OUTS6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_0" }, "PSS0.PSS0_LOGIC_OUTS6_1->PSS_LOGIC_OUTS6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_1" }, "PSS0.PSS0_LOGIC_OUTS6_10->PSS_LOGIC_OUTS6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_10" }, "PSS0.PSS0_LOGIC_OUTS6_11->PSS_LOGIC_OUTS6_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_11" }, "PSS0.PSS0_LOGIC_OUTS6_12->PSS_LOGIC_OUTS6_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_12" }, "PSS0.PSS0_LOGIC_OUTS6_13->PSS_LOGIC_OUTS6_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_13" }, "PSS0.PSS0_LOGIC_OUTS6_14->PSS_LOGIC_OUTS6_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_14" }, "PSS0.PSS0_LOGIC_OUTS6_15->PSS_LOGIC_OUTS6_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_15" }, "PSS0.PSS0_LOGIC_OUTS6_16->PSS_LOGIC_OUTS6_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_16" }, "PSS0.PSS0_LOGIC_OUTS6_17->PSS_LOGIC_OUTS6_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_17" }, "PSS0.PSS0_LOGIC_OUTS6_18->PSS_LOGIC_OUTS6_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_18" }, "PSS0.PSS0_LOGIC_OUTS6_19->PSS_LOGIC_OUTS6_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_19" }, "PSS0.PSS0_LOGIC_OUTS6_2->PSS_LOGIC_OUTS6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_2" }, "PSS0.PSS0_LOGIC_OUTS6_3->PSS_LOGIC_OUTS6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_3" }, "PSS0.PSS0_LOGIC_OUTS6_4->PSS_LOGIC_OUTS6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_4" }, "PSS0.PSS0_LOGIC_OUTS6_5->PSS_LOGIC_OUTS6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_5" }, "PSS0.PSS0_LOGIC_OUTS6_6->PSS_LOGIC_OUTS6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_6" }, "PSS0.PSS0_LOGIC_OUTS6_7->PSS_LOGIC_OUTS6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_7" }, "PSS0.PSS0_LOGIC_OUTS6_8->PSS_LOGIC_OUTS6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_8" }, "PSS0.PSS0_LOGIC_OUTS6_9->PSS_LOGIC_OUTS6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_9" }, "PSS0.PSS0_LOGIC_OUTS7_0->PSS_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_0" }, "PSS0.PSS0_LOGIC_OUTS7_1->PSS_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_1" }, "PSS0.PSS0_LOGIC_OUTS7_10->PSS_LOGIC_OUTS7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_10" }, "PSS0.PSS0_LOGIC_OUTS7_11->PSS_LOGIC_OUTS7_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_11" }, "PSS0.PSS0_LOGIC_OUTS7_12->PSS_LOGIC_OUTS7_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_12" }, "PSS0.PSS0_LOGIC_OUTS7_13->PSS_LOGIC_OUTS7_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_13" }, "PSS0.PSS0_LOGIC_OUTS7_14->PSS_LOGIC_OUTS7_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_14" }, "PSS0.PSS0_LOGIC_OUTS7_15->PSS_LOGIC_OUTS7_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_15" }, "PSS0.PSS0_LOGIC_OUTS7_16->PSS_LOGIC_OUTS7_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_16" }, "PSS0.PSS0_LOGIC_OUTS7_17->PSS_LOGIC_OUTS7_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_17" }, "PSS0.PSS0_LOGIC_OUTS7_18->PSS_LOGIC_OUTS7_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_18" }, "PSS0.PSS0_LOGIC_OUTS7_19->PSS_LOGIC_OUTS7_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_19" }, "PSS0.PSS0_LOGIC_OUTS7_2->PSS_LOGIC_OUTS7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_2" }, "PSS0.PSS0_LOGIC_OUTS7_3->PSS_LOGIC_OUTS7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_3" }, "PSS0.PSS0_LOGIC_OUTS7_4->PSS_LOGIC_OUTS7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_4" }, "PSS0.PSS0_LOGIC_OUTS7_5->PSS_LOGIC_OUTS7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_5" }, "PSS0.PSS0_LOGIC_OUTS7_6->PSS_LOGIC_OUTS7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_6" }, "PSS0.PSS0_LOGIC_OUTS7_7->PSS_LOGIC_OUTS7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_7" }, "PSS0.PSS0_LOGIC_OUTS7_8->PSS_LOGIC_OUTS7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_8" }, "PSS0.PSS0_LOGIC_OUTS7_9->PSS_LOGIC_OUTS7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_9" }, "PSS0.PSS0_LOGIC_OUTS8_0->PSS_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_0" }, "PSS0.PSS0_LOGIC_OUTS8_1->PSS_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_1" }, "PSS0.PSS0_LOGIC_OUTS8_10->PSS_LOGIC_OUTS8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_10" }, "PSS0.PSS0_LOGIC_OUTS8_11->PSS_LOGIC_OUTS8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_11" }, "PSS0.PSS0_LOGIC_OUTS8_12->PSS_LOGIC_OUTS8_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_12" }, "PSS0.PSS0_LOGIC_OUTS8_13->PSS_LOGIC_OUTS8_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_13" }, "PSS0.PSS0_LOGIC_OUTS8_14->PSS_LOGIC_OUTS8_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_14" }, "PSS0.PSS0_LOGIC_OUTS8_15->PSS_LOGIC_OUTS8_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_15" }, "PSS0.PSS0_LOGIC_OUTS8_16->PSS_LOGIC_OUTS8_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_16" }, "PSS0.PSS0_LOGIC_OUTS8_17->PSS_LOGIC_OUTS8_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_17" }, "PSS0.PSS0_LOGIC_OUTS8_18->PSS_LOGIC_OUTS8_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_18" }, "PSS0.PSS0_LOGIC_OUTS8_19->PSS_LOGIC_OUTS8_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_19" }, "PSS0.PSS0_LOGIC_OUTS8_2->PSS_LOGIC_OUTS8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_2" }, "PSS0.PSS0_LOGIC_OUTS8_3->PSS_LOGIC_OUTS8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_3" }, "PSS0.PSS0_LOGIC_OUTS8_4->PSS_LOGIC_OUTS8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_4" }, "PSS0.PSS0_LOGIC_OUTS8_5->PSS_LOGIC_OUTS8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_5" }, "PSS0.PSS0_LOGIC_OUTS8_6->PSS_LOGIC_OUTS8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_6" }, "PSS0.PSS0_LOGIC_OUTS8_7->PSS_LOGIC_OUTS8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_7" }, "PSS0.PSS0_LOGIC_OUTS8_8->PSS_LOGIC_OUTS8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_8" }, "PSS0.PSS0_LOGIC_OUTS8_9->PSS_LOGIC_OUTS8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_9" }, "PSS0.PSS0_LOGIC_OUTS9_0->PSS_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_0" }, "PSS0.PSS0_LOGIC_OUTS9_1->PSS_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_1" }, "PSS0.PSS0_LOGIC_OUTS9_10->PSS_LOGIC_OUTS9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_10" }, "PSS0.PSS0_LOGIC_OUTS9_11->PSS_LOGIC_OUTS9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_11" }, "PSS0.PSS0_LOGIC_OUTS9_12->PSS_LOGIC_OUTS9_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_12" }, "PSS0.PSS0_LOGIC_OUTS9_13->PSS_LOGIC_OUTS9_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_13" }, "PSS0.PSS0_LOGIC_OUTS9_14->PSS_LOGIC_OUTS9_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_14" }, "PSS0.PSS0_LOGIC_OUTS9_15->PSS_LOGIC_OUTS9_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_15" }, "PSS0.PSS0_LOGIC_OUTS9_16->PSS_LOGIC_OUTS9_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_16" }, "PSS0.PSS0_LOGIC_OUTS9_17->PSS_LOGIC_OUTS9_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_17" }, "PSS0.PSS0_LOGIC_OUTS9_18->PSS_LOGIC_OUTS9_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_18" }, "PSS0.PSS0_LOGIC_OUTS9_19->PSS_LOGIC_OUTS9_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_19" }, "PSS0.PSS0_LOGIC_OUTS9_2->PSS_LOGIC_OUTS9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_2" }, "PSS0.PSS0_LOGIC_OUTS9_3->PSS_LOGIC_OUTS9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_3" }, "PSS0.PSS0_LOGIC_OUTS9_4->PSS_LOGIC_OUTS9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_4" }, "PSS0.PSS0_LOGIC_OUTS9_5->PSS_LOGIC_OUTS9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_5" }, "PSS0.PSS0_LOGIC_OUTS9_6->PSS_LOGIC_OUTS9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_6" }, "PSS0.PSS0_LOGIC_OUTS9_7->PSS_LOGIC_OUTS9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_7" }, "PSS0.PSS0_LOGIC_OUTS9_8->PSS_LOGIC_OUTS9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_8" }, "PSS0.PSS0_LOGIC_OUTS9_9->PSS_LOGIC_OUTS9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_9" }, "PSS0.PSS_CLK_B0_0->PSS0_CLK_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_0" }, "PSS0.PSS_CLK_B0_1->PSS0_CLK_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_1" }, "PSS0.PSS_CLK_B0_10->PSS0_CLK_B0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_10" }, "PSS0.PSS_CLK_B0_11->PSS0_CLK_B0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_11" }, "PSS0.PSS_CLK_B0_12->PSS0_CLK_B0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_12" }, "PSS0.PSS_CLK_B0_13->PSS0_CLK_B0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_13" }, "PSS0.PSS_CLK_B0_14->PSS0_CLK_B0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_14" }, "PSS0.PSS_CLK_B0_15->PSS0_CLK_B0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_15" }, "PSS0.PSS_CLK_B0_16->PSS0_CLK_B0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_16" }, "PSS0.PSS_CLK_B0_17->PSS0_CLK_B0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_17" }, "PSS0.PSS_CLK_B0_18->PSS0_CLK_B0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_18" }, "PSS0.PSS_CLK_B0_19->PSS0_CLK_B0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_19" }, "PSS0.PSS_CLK_B0_2->PSS0_CLK_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_2" }, "PSS0.PSS_CLK_B0_3->PSS0_CLK_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_3" }, "PSS0.PSS_CLK_B0_4->PSS0_CLK_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_4" }, "PSS0.PSS_CLK_B0_5->PSS0_CLK_B0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_5" }, "PSS0.PSS_CLK_B0_6->PSS0_CLK_B0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_6" }, "PSS0.PSS_CLK_B0_7->PSS0_CLK_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_7" }, "PSS0.PSS_CLK_B0_8->PSS0_CLK_B0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_8" }, "PSS0.PSS_CLK_B0_9->PSS0_CLK_B0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_9" }, "PSS0.PSS_CLK_B1_0->PSS0_CLK_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_0" }, "PSS0.PSS_CLK_B1_1->PSS0_CLK_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_1" }, "PSS0.PSS_CLK_B1_10->PSS0_CLK_B1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_10" }, "PSS0.PSS_CLK_B1_11->PSS0_CLK_B1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_11" }, "PSS0.PSS_CLK_B1_12->PSS0_CLK_B1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_12" }, "PSS0.PSS_CLK_B1_13->PSS0_CLK_B1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_13" }, "PSS0.PSS_CLK_B1_14->PSS0_CLK_B1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_14" }, "PSS0.PSS_CLK_B1_15->PSS0_CLK_B1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_15" }, "PSS0.PSS_CLK_B1_16->PSS0_CLK_B1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_16" }, "PSS0.PSS_CLK_B1_17->PSS0_CLK_B1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_17" }, "PSS0.PSS_CLK_B1_18->PSS0_CLK_B1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_18" }, "PSS0.PSS_CLK_B1_19->PSS0_CLK_B1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_19" }, "PSS0.PSS_CLK_B1_2->PSS0_CLK_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_2" }, "PSS0.PSS_CLK_B1_3->PSS0_CLK_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_3" }, "PSS0.PSS_CLK_B1_4->PSS0_CLK_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_4" }, "PSS0.PSS_CLK_B1_5->PSS0_CLK_B1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_5" }, "PSS0.PSS_CLK_B1_6->PSS0_CLK_B1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_6" }, "PSS0.PSS_CLK_B1_7->PSS0_CLK_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_7" }, "PSS0.PSS_CLK_B1_8->PSS0_CLK_B1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_8" }, "PSS0.PSS_CLK_B1_9->PSS0_CLK_B1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_9" }, "PSS0.PSS_IMUX_B0_0->PSS0_IMUX_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_0" }, "PSS0.PSS_IMUX_B0_1->PSS0_IMUX_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_1" }, "PSS0.PSS_IMUX_B0_10->PSS0_IMUX_B0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_10" }, "PSS0.PSS_IMUX_B0_11->PSS0_IMUX_B0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_11" }, "PSS0.PSS_IMUX_B0_12->PSS0_IMUX_B0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_12" }, "PSS0.PSS_IMUX_B0_13->PSS0_IMUX_B0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_13" }, "PSS0.PSS_IMUX_B0_14->PSS0_IMUX_B0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_14" }, "PSS0.PSS_IMUX_B0_15->PSS0_IMUX_B0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_15" }, "PSS0.PSS_IMUX_B0_16->PSS0_IMUX_B0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_16" }, "PSS0.PSS_IMUX_B0_17->PSS0_IMUX_B0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_17" }, "PSS0.PSS_IMUX_B0_18->PSS0_IMUX_B0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_18" }, "PSS0.PSS_IMUX_B0_19->PSS0_IMUX_B0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_19" }, "PSS0.PSS_IMUX_B0_2->PSS0_IMUX_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_2" }, "PSS0.PSS_IMUX_B0_3->PSS0_IMUX_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_3" }, "PSS0.PSS_IMUX_B0_4->PSS0_IMUX_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_4" }, "PSS0.PSS_IMUX_B0_5->PSS0_IMUX_B0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_5" }, "PSS0.PSS_IMUX_B0_6->PSS0_IMUX_B0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_6" }, "PSS0.PSS_IMUX_B0_7->PSS0_IMUX_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_7" }, "PSS0.PSS_IMUX_B0_8->PSS0_IMUX_B0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_8" }, "PSS0.PSS_IMUX_B0_9->PSS0_IMUX_B0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_9" }, "PSS0.PSS_IMUX_B10_0->PSS0_IMUX_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_0" }, "PSS0.PSS_IMUX_B10_1->PSS0_IMUX_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_1" }, "PSS0.PSS_IMUX_B10_10->PSS0_IMUX_B10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_10" }, "PSS0.PSS_IMUX_B10_11->PSS0_IMUX_B10_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_11" }, "PSS0.PSS_IMUX_B10_12->PSS0_IMUX_B10_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_12" }, "PSS0.PSS_IMUX_B10_13->PSS0_IMUX_B10_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_13" }, "PSS0.PSS_IMUX_B10_14->PSS0_IMUX_B10_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_14" }, "PSS0.PSS_IMUX_B10_15->PSS0_IMUX_B10_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_15" }, "PSS0.PSS_IMUX_B10_16->PSS0_IMUX_B10_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_16" }, "PSS0.PSS_IMUX_B10_17->PSS0_IMUX_B10_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_17" }, "PSS0.PSS_IMUX_B10_18->PSS0_IMUX_B10_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_18" }, "PSS0.PSS_IMUX_B10_19->PSS0_IMUX_B10_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_19" }, "PSS0.PSS_IMUX_B10_2->PSS0_IMUX_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_2" }, "PSS0.PSS_IMUX_B10_3->PSS0_IMUX_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_3" }, "PSS0.PSS_IMUX_B10_4->PSS0_IMUX_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_4" }, "PSS0.PSS_IMUX_B10_5->PSS0_IMUX_B10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_5" }, "PSS0.PSS_IMUX_B10_6->PSS0_IMUX_B10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_6" }, "PSS0.PSS_IMUX_B10_7->PSS0_IMUX_B10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_7" }, "PSS0.PSS_IMUX_B10_8->PSS0_IMUX_B10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_8" }, "PSS0.PSS_IMUX_B10_9->PSS0_IMUX_B10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_9" }, "PSS0.PSS_IMUX_B11_0->PSS0_IMUX_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_0" }, "PSS0.PSS_IMUX_B11_1->PSS0_IMUX_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_1" }, "PSS0.PSS_IMUX_B11_10->PSS0_IMUX_B11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_10" }, "PSS0.PSS_IMUX_B11_11->PSS0_IMUX_B11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_11" }, "PSS0.PSS_IMUX_B11_12->PSS0_IMUX_B11_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_12" }, "PSS0.PSS_IMUX_B11_13->PSS0_IMUX_B11_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_13" }, "PSS0.PSS_IMUX_B11_14->PSS0_IMUX_B11_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_14" }, "PSS0.PSS_IMUX_B11_15->PSS0_IMUX_B11_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_15" }, "PSS0.PSS_IMUX_B11_16->PSS0_IMUX_B11_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_16" }, "PSS0.PSS_IMUX_B11_17->PSS0_IMUX_B11_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_17" }, "PSS0.PSS_IMUX_B11_18->PSS0_IMUX_B11_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_18" }, "PSS0.PSS_IMUX_B11_19->PSS0_IMUX_B11_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_19" }, "PSS0.PSS_IMUX_B11_2->PSS0_IMUX_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_2" }, "PSS0.PSS_IMUX_B11_3->PSS0_IMUX_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_3" }, "PSS0.PSS_IMUX_B11_4->PSS0_IMUX_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_4" }, "PSS0.PSS_IMUX_B11_5->PSS0_IMUX_B11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_5" }, "PSS0.PSS_IMUX_B11_6->PSS0_IMUX_B11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_6" }, "PSS0.PSS_IMUX_B11_7->PSS0_IMUX_B11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_7" }, "PSS0.PSS_IMUX_B11_8->PSS0_IMUX_B11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_8" }, "PSS0.PSS_IMUX_B11_9->PSS0_IMUX_B11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_9" }, "PSS0.PSS_IMUX_B12_0->PSS0_IMUX_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_0" }, "PSS0.PSS_IMUX_B12_1->PSS0_IMUX_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_1" }, "PSS0.PSS_IMUX_B12_10->PSS0_IMUX_B12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_10" }, "PSS0.PSS_IMUX_B12_11->PSS0_IMUX_B12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_11" }, "PSS0.PSS_IMUX_B12_12->PSS0_IMUX_B12_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_12" }, "PSS0.PSS_IMUX_B12_13->PSS0_IMUX_B12_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_13" }, "PSS0.PSS_IMUX_B12_14->PSS0_IMUX_B12_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_14" }, "PSS0.PSS_IMUX_B12_15->PSS0_IMUX_B12_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_15" }, "PSS0.PSS_IMUX_B12_16->PSS0_IMUX_B12_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_16" }, "PSS0.PSS_IMUX_B12_17->PSS0_IMUX_B12_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_17" }, "PSS0.PSS_IMUX_B12_18->PSS0_IMUX_B12_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_18" }, "PSS0.PSS_IMUX_B12_19->PSS0_IMUX_B12_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_19" }, "PSS0.PSS_IMUX_B12_2->PSS0_IMUX_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_2" }, "PSS0.PSS_IMUX_B12_3->PSS0_IMUX_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_3" }, "PSS0.PSS_IMUX_B12_4->PSS0_IMUX_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_4" }, "PSS0.PSS_IMUX_B12_5->PSS0_IMUX_B12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_5" }, "PSS0.PSS_IMUX_B12_6->PSS0_IMUX_B12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_6" }, "PSS0.PSS_IMUX_B12_7->PSS0_IMUX_B12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_7" }, "PSS0.PSS_IMUX_B12_8->PSS0_IMUX_B12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_8" }, "PSS0.PSS_IMUX_B12_9->PSS0_IMUX_B12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_9" }, "PSS0.PSS_IMUX_B13_0->PSS0_IMUX_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_0" }, "PSS0.PSS_IMUX_B13_1->PSS0_IMUX_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_1" }, "PSS0.PSS_IMUX_B13_10->PSS0_IMUX_B13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_10" }, "PSS0.PSS_IMUX_B13_11->PSS0_IMUX_B13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_11" }, "PSS0.PSS_IMUX_B13_12->PSS0_IMUX_B13_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_12" }, "PSS0.PSS_IMUX_B13_13->PSS0_IMUX_B13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_13" }, "PSS0.PSS_IMUX_B13_14->PSS0_IMUX_B13_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_14" }, "PSS0.PSS_IMUX_B13_15->PSS0_IMUX_B13_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_15" }, "PSS0.PSS_IMUX_B13_16->PSS0_IMUX_B13_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_16" }, "PSS0.PSS_IMUX_B13_17->PSS0_IMUX_B13_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_17" }, "PSS0.PSS_IMUX_B13_18->PSS0_IMUX_B13_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_18" }, "PSS0.PSS_IMUX_B13_19->PSS0_IMUX_B13_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_19" }, "PSS0.PSS_IMUX_B13_2->PSS0_IMUX_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_2" }, "PSS0.PSS_IMUX_B13_3->PSS0_IMUX_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_3" }, "PSS0.PSS_IMUX_B13_4->PSS0_IMUX_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_4" }, "PSS0.PSS_IMUX_B13_5->PSS0_IMUX_B13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_5" }, "PSS0.PSS_IMUX_B13_6->PSS0_IMUX_B13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_6" }, "PSS0.PSS_IMUX_B13_7->PSS0_IMUX_B13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_7" }, "PSS0.PSS_IMUX_B13_8->PSS0_IMUX_B13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_8" }, "PSS0.PSS_IMUX_B13_9->PSS0_IMUX_B13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_9" }, "PSS0.PSS_IMUX_B14_0->PSS0_IMUX_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_0" }, "PSS0.PSS_IMUX_B14_1->PSS0_IMUX_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_1" }, "PSS0.PSS_IMUX_B14_10->PSS0_IMUX_B14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_10" }, "PSS0.PSS_IMUX_B14_11->PSS0_IMUX_B14_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_11" }, "PSS0.PSS_IMUX_B14_12->PSS0_IMUX_B14_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_12" }, "PSS0.PSS_IMUX_B14_13->PSS0_IMUX_B14_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_13" }, "PSS0.PSS_IMUX_B14_14->PSS0_IMUX_B14_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_14" }, "PSS0.PSS_IMUX_B14_15->PSS0_IMUX_B14_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_15" }, "PSS0.PSS_IMUX_B14_16->PSS0_IMUX_B14_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_16" }, "PSS0.PSS_IMUX_B14_17->PSS0_IMUX_B14_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_17" }, "PSS0.PSS_IMUX_B14_18->PSS0_IMUX_B14_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_18" }, "PSS0.PSS_IMUX_B14_19->PSS0_IMUX_B14_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_19" }, "PSS0.PSS_IMUX_B14_2->PSS0_IMUX_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_2" }, "PSS0.PSS_IMUX_B14_3->PSS0_IMUX_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_3" }, "PSS0.PSS_IMUX_B14_4->PSS0_IMUX_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_4" }, "PSS0.PSS_IMUX_B14_5->PSS0_IMUX_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_5" }, "PSS0.PSS_IMUX_B14_6->PSS0_IMUX_B14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_6" }, "PSS0.PSS_IMUX_B14_7->PSS0_IMUX_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_7" }, "PSS0.PSS_IMUX_B14_8->PSS0_IMUX_B14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_8" }, "PSS0.PSS_IMUX_B14_9->PSS0_IMUX_B14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_9" }, "PSS0.PSS_IMUX_B15_0->PSS0_IMUX_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_0" }, "PSS0.PSS_IMUX_B15_1->PSS0_IMUX_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_1" }, "PSS0.PSS_IMUX_B15_10->PSS0_IMUX_B15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_10" }, "PSS0.PSS_IMUX_B15_11->PSS0_IMUX_B15_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_11" }, "PSS0.PSS_IMUX_B15_12->PSS0_IMUX_B15_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_12" }, "PSS0.PSS_IMUX_B15_13->PSS0_IMUX_B15_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_13" }, "PSS0.PSS_IMUX_B15_14->PSS0_IMUX_B15_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_14" }, "PSS0.PSS_IMUX_B15_15->PSS0_IMUX_B15_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_15" }, "PSS0.PSS_IMUX_B15_16->PSS0_IMUX_B15_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_16" }, "PSS0.PSS_IMUX_B15_17->PSS0_IMUX_B15_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_17" }, "PSS0.PSS_IMUX_B15_18->PSS0_IMUX_B15_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_18" }, "PSS0.PSS_IMUX_B15_19->PSS0_IMUX_B15_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_19" }, "PSS0.PSS_IMUX_B15_2->PSS0_IMUX_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_2" }, "PSS0.PSS_IMUX_B15_3->PSS0_IMUX_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_3" }, "PSS0.PSS_IMUX_B15_4->PSS0_IMUX_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_4" }, "PSS0.PSS_IMUX_B15_5->PSS0_IMUX_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_5" }, "PSS0.PSS_IMUX_B15_6->PSS0_IMUX_B15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_6" }, "PSS0.PSS_IMUX_B15_7->PSS0_IMUX_B15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_7" }, "PSS0.PSS_IMUX_B15_8->PSS0_IMUX_B15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_8" }, "PSS0.PSS_IMUX_B15_9->PSS0_IMUX_B15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_9" }, "PSS0.PSS_IMUX_B16_0->PSS0_IMUX_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_0" }, "PSS0.PSS_IMUX_B16_1->PSS0_IMUX_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_1" }, "PSS0.PSS_IMUX_B16_10->PSS0_IMUX_B16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_10" }, "PSS0.PSS_IMUX_B16_11->PSS0_IMUX_B16_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_11" }, "PSS0.PSS_IMUX_B16_12->PSS0_IMUX_B16_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_12" }, "PSS0.PSS_IMUX_B16_13->PSS0_IMUX_B16_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_13" }, "PSS0.PSS_IMUX_B16_14->PSS0_IMUX_B16_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_14" }, "PSS0.PSS_IMUX_B16_15->PSS0_IMUX_B16_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_15" }, "PSS0.PSS_IMUX_B16_16->PSS0_IMUX_B16_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_16" }, "PSS0.PSS_IMUX_B16_17->PSS0_IMUX_B16_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_17" }, "PSS0.PSS_IMUX_B16_18->PSS0_IMUX_B16_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_18" }, "PSS0.PSS_IMUX_B16_19->PSS0_IMUX_B16_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_19" }, "PSS0.PSS_IMUX_B16_2->PSS0_IMUX_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_2" }, "PSS0.PSS_IMUX_B16_3->PSS0_IMUX_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_3" }, "PSS0.PSS_IMUX_B16_4->PSS0_IMUX_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_4" }, "PSS0.PSS_IMUX_B16_5->PSS0_IMUX_B16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_5" }, "PSS0.PSS_IMUX_B16_6->PSS0_IMUX_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_6" }, "PSS0.PSS_IMUX_B16_7->PSS0_IMUX_B16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_7" }, "PSS0.PSS_IMUX_B16_8->PSS0_IMUX_B16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_8" }, "PSS0.PSS_IMUX_B16_9->PSS0_IMUX_B16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_9" }, "PSS0.PSS_IMUX_B17_0->PSS0_IMUX_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_0" }, "PSS0.PSS_IMUX_B17_1->PSS0_IMUX_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_1" }, "PSS0.PSS_IMUX_B17_10->PSS0_IMUX_B17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_10" }, "PSS0.PSS_IMUX_B17_11->PSS0_IMUX_B17_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_11" }, "PSS0.PSS_IMUX_B17_12->PSS0_IMUX_B17_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_12" }, "PSS0.PSS_IMUX_B17_13->PSS0_IMUX_B17_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_13" }, "PSS0.PSS_IMUX_B17_14->PSS0_IMUX_B17_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_14" }, "PSS0.PSS_IMUX_B17_15->PSS0_IMUX_B17_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_15" }, "PSS0.PSS_IMUX_B17_16->PSS0_IMUX_B17_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_16" }, "PSS0.PSS_IMUX_B17_17->PSS0_IMUX_B17_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_17" }, "PSS0.PSS_IMUX_B17_18->PSS0_IMUX_B17_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_18" }, "PSS0.PSS_IMUX_B17_19->PSS0_IMUX_B17_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_19" }, "PSS0.PSS_IMUX_B17_2->PSS0_IMUX_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_2" }, "PSS0.PSS_IMUX_B17_3->PSS0_IMUX_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_3" }, "PSS0.PSS_IMUX_B17_4->PSS0_IMUX_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_4" }, "PSS0.PSS_IMUX_B17_5->PSS0_IMUX_B17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_5" }, "PSS0.PSS_IMUX_B17_6->PSS0_IMUX_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_6" }, "PSS0.PSS_IMUX_B17_7->PSS0_IMUX_B17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_7" }, "PSS0.PSS_IMUX_B17_8->PSS0_IMUX_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_8" }, "PSS0.PSS_IMUX_B17_9->PSS0_IMUX_B17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_9" }, "PSS0.PSS_IMUX_B18_0->PSS0_IMUX_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_0" }, "PSS0.PSS_IMUX_B18_1->PSS0_IMUX_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_1" }, "PSS0.PSS_IMUX_B18_10->PSS0_IMUX_B18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_10" }, "PSS0.PSS_IMUX_B18_11->PSS0_IMUX_B18_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_11" }, "PSS0.PSS_IMUX_B18_12->PSS0_IMUX_B18_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_12" }, "PSS0.PSS_IMUX_B18_13->PSS0_IMUX_B18_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_13" }, "PSS0.PSS_IMUX_B18_14->PSS0_IMUX_B18_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_14" }, "PSS0.PSS_IMUX_B18_15->PSS0_IMUX_B18_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_15" }, "PSS0.PSS_IMUX_B18_16->PSS0_IMUX_B18_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_16" }, "PSS0.PSS_IMUX_B18_17->PSS0_IMUX_B18_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_17" }, "PSS0.PSS_IMUX_B18_18->PSS0_IMUX_B18_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_18" }, "PSS0.PSS_IMUX_B18_19->PSS0_IMUX_B18_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_19" }, "PSS0.PSS_IMUX_B18_2->PSS0_IMUX_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_2" }, "PSS0.PSS_IMUX_B18_3->PSS0_IMUX_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_3" }, "PSS0.PSS_IMUX_B18_4->PSS0_IMUX_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_4" }, "PSS0.PSS_IMUX_B18_5->PSS0_IMUX_B18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_5" }, "PSS0.PSS_IMUX_B18_6->PSS0_IMUX_B18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_6" }, "PSS0.PSS_IMUX_B18_7->PSS0_IMUX_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_7" }, "PSS0.PSS_IMUX_B18_8->PSS0_IMUX_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_8" }, "PSS0.PSS_IMUX_B18_9->PSS0_IMUX_B18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_9" }, "PSS0.PSS_IMUX_B19_0->PSS0_IMUX_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_0" }, "PSS0.PSS_IMUX_B19_1->PSS0_IMUX_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_1" }, "PSS0.PSS_IMUX_B19_10->PSS0_IMUX_B19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_10" }, "PSS0.PSS_IMUX_B19_11->PSS0_IMUX_B19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_11" }, "PSS0.PSS_IMUX_B19_12->PSS0_IMUX_B19_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_12" }, "PSS0.PSS_IMUX_B19_13->PSS0_IMUX_B19_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_13" }, "PSS0.PSS_IMUX_B19_14->PSS0_IMUX_B19_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_14" }, "PSS0.PSS_IMUX_B19_15->PSS0_IMUX_B19_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_15" }, "PSS0.PSS_IMUX_B19_16->PSS0_IMUX_B19_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_16" }, "PSS0.PSS_IMUX_B19_17->PSS0_IMUX_B19_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_17" }, "PSS0.PSS_IMUX_B19_18->PSS0_IMUX_B19_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_18" }, "PSS0.PSS_IMUX_B19_19->PSS0_IMUX_B19_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_19" }, "PSS0.PSS_IMUX_B19_2->PSS0_IMUX_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_2" }, "PSS0.PSS_IMUX_B19_3->PSS0_IMUX_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_3" }, "PSS0.PSS_IMUX_B19_4->PSS0_IMUX_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_4" }, "PSS0.PSS_IMUX_B19_5->PSS0_IMUX_B19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_5" }, "PSS0.PSS_IMUX_B19_6->PSS0_IMUX_B19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_6" }, "PSS0.PSS_IMUX_B19_7->PSS0_IMUX_B19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_7" }, "PSS0.PSS_IMUX_B19_8->PSS0_IMUX_B19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_8" }, "PSS0.PSS_IMUX_B19_9->PSS0_IMUX_B19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_9" }, "PSS0.PSS_IMUX_B1_0->PSS0_IMUX_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_0" }, "PSS0.PSS_IMUX_B1_1->PSS0_IMUX_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_1" }, "PSS0.PSS_IMUX_B1_10->PSS0_IMUX_B1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_10" }, "PSS0.PSS_IMUX_B1_11->PSS0_IMUX_B1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_11" }, "PSS0.PSS_IMUX_B1_12->PSS0_IMUX_B1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_12" }, "PSS0.PSS_IMUX_B1_13->PSS0_IMUX_B1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_13" }, "PSS0.PSS_IMUX_B1_14->PSS0_IMUX_B1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_14" }, "PSS0.PSS_IMUX_B1_15->PSS0_IMUX_B1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_15" }, "PSS0.PSS_IMUX_B1_16->PSS0_IMUX_B1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_16" }, "PSS0.PSS_IMUX_B1_17->PSS0_IMUX_B1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_17" }, "PSS0.PSS_IMUX_B1_18->PSS0_IMUX_B1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_18" }, "PSS0.PSS_IMUX_B1_19->PSS0_IMUX_B1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_19" }, "PSS0.PSS_IMUX_B1_2->PSS0_IMUX_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_2" }, "PSS0.PSS_IMUX_B1_3->PSS0_IMUX_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_3" }, "PSS0.PSS_IMUX_B1_4->PSS0_IMUX_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_4" }, "PSS0.PSS_IMUX_B1_5->PSS0_IMUX_B1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_5" }, "PSS0.PSS_IMUX_B1_6->PSS0_IMUX_B1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_6" }, "PSS0.PSS_IMUX_B1_7->PSS0_IMUX_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_7" }, "PSS0.PSS_IMUX_B1_8->PSS0_IMUX_B1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_8" }, "PSS0.PSS_IMUX_B1_9->PSS0_IMUX_B1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_9" }, "PSS0.PSS_IMUX_B20_0->PSS0_IMUX_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_0" }, "PSS0.PSS_IMUX_B20_1->PSS0_IMUX_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_1" }, "PSS0.PSS_IMUX_B20_10->PSS0_IMUX_B20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_10" }, "PSS0.PSS_IMUX_B20_11->PSS0_IMUX_B20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_11" }, "PSS0.PSS_IMUX_B20_12->PSS0_IMUX_B20_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_12" }, "PSS0.PSS_IMUX_B20_13->PSS0_IMUX_B20_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_13" }, "PSS0.PSS_IMUX_B20_14->PSS0_IMUX_B20_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_14" }, "PSS0.PSS_IMUX_B20_15->PSS0_IMUX_B20_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_15" }, "PSS0.PSS_IMUX_B20_16->PSS0_IMUX_B20_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_16" }, "PSS0.PSS_IMUX_B20_17->PSS0_IMUX_B20_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_17" }, "PSS0.PSS_IMUX_B20_18->PSS0_IMUX_B20_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_18" }, "PSS0.PSS_IMUX_B20_19->PSS0_IMUX_B20_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_19" }, "PSS0.PSS_IMUX_B20_2->PSS0_IMUX_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_2" }, "PSS0.PSS_IMUX_B20_3->PSS0_IMUX_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_3" }, "PSS0.PSS_IMUX_B20_4->PSS0_IMUX_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_4" }, "PSS0.PSS_IMUX_B20_5->PSS0_IMUX_B20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_5" }, "PSS0.PSS_IMUX_B20_6->PSS0_IMUX_B20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_6" }, "PSS0.PSS_IMUX_B20_7->PSS0_IMUX_B20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_7" }, "PSS0.PSS_IMUX_B20_8->PSS0_IMUX_B20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_8" }, "PSS0.PSS_IMUX_B20_9->PSS0_IMUX_B20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_9" }, "PSS0.PSS_IMUX_B21_0->PSS0_IMUX_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_0" }, "PSS0.PSS_IMUX_B21_1->PSS0_IMUX_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_1" }, "PSS0.PSS_IMUX_B21_10->PSS0_IMUX_B21_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_10" }, "PSS0.PSS_IMUX_B21_11->PSS0_IMUX_B21_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_11" }, "PSS0.PSS_IMUX_B21_12->PSS0_IMUX_B21_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_12" }, "PSS0.PSS_IMUX_B21_13->PSS0_IMUX_B21_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_13" }, "PSS0.PSS_IMUX_B21_14->PSS0_IMUX_B21_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_14" }, "PSS0.PSS_IMUX_B21_15->PSS0_IMUX_B21_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_15" }, "PSS0.PSS_IMUX_B21_16->PSS0_IMUX_B21_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_16" }, "PSS0.PSS_IMUX_B21_17->PSS0_IMUX_B21_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_17" }, "PSS0.PSS_IMUX_B21_18->PSS0_IMUX_B21_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_18" }, "PSS0.PSS_IMUX_B21_19->PSS0_IMUX_B21_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_19" }, "PSS0.PSS_IMUX_B21_2->PSS0_IMUX_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_2" }, "PSS0.PSS_IMUX_B21_3->PSS0_IMUX_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_3" }, "PSS0.PSS_IMUX_B21_4->PSS0_IMUX_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_4" }, "PSS0.PSS_IMUX_B21_5->PSS0_IMUX_B21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_5" }, "PSS0.PSS_IMUX_B21_6->PSS0_IMUX_B21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_6" }, "PSS0.PSS_IMUX_B21_7->PSS0_IMUX_B21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_7" }, "PSS0.PSS_IMUX_B21_8->PSS0_IMUX_B21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_8" }, "PSS0.PSS_IMUX_B21_9->PSS0_IMUX_B21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_9" }, "PSS0.PSS_IMUX_B22_0->PSS0_IMUX_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_0" }, "PSS0.PSS_IMUX_B22_1->PSS0_IMUX_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_1" }, "PSS0.PSS_IMUX_B22_10->PSS0_IMUX_B22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_10" }, "PSS0.PSS_IMUX_B22_11->PSS0_IMUX_B22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_11" }, "PSS0.PSS_IMUX_B22_12->PSS0_IMUX_B22_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_12" }, "PSS0.PSS_IMUX_B22_13->PSS0_IMUX_B22_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_13" }, "PSS0.PSS_IMUX_B22_14->PSS0_IMUX_B22_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_14" }, "PSS0.PSS_IMUX_B22_15->PSS0_IMUX_B22_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_15" }, "PSS0.PSS_IMUX_B22_16->PSS0_IMUX_B22_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_16" }, "PSS0.PSS_IMUX_B22_17->PSS0_IMUX_B22_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_17" }, "PSS0.PSS_IMUX_B22_18->PSS0_IMUX_B22_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_18" }, "PSS0.PSS_IMUX_B22_19->PSS0_IMUX_B22_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_19" }, "PSS0.PSS_IMUX_B22_2->PSS0_IMUX_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_2" }, "PSS0.PSS_IMUX_B22_3->PSS0_IMUX_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_3" }, "PSS0.PSS_IMUX_B22_4->PSS0_IMUX_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_4" }, "PSS0.PSS_IMUX_B22_5->PSS0_IMUX_B22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_5" }, "PSS0.PSS_IMUX_B22_6->PSS0_IMUX_B22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_6" }, "PSS0.PSS_IMUX_B22_7->PSS0_IMUX_B22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_7" }, "PSS0.PSS_IMUX_B22_8->PSS0_IMUX_B22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_8" }, "PSS0.PSS_IMUX_B22_9->PSS0_IMUX_B22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_9" }, "PSS0.PSS_IMUX_B23_0->PSS0_IMUX_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_0" }, "PSS0.PSS_IMUX_B23_1->PSS0_IMUX_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_1" }, "PSS0.PSS_IMUX_B23_10->PSS0_IMUX_B23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_10" }, "PSS0.PSS_IMUX_B23_11->PSS0_IMUX_B23_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_11" }, "PSS0.PSS_IMUX_B23_12->PSS0_IMUX_B23_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_12" }, "PSS0.PSS_IMUX_B23_13->PSS0_IMUX_B23_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_13" }, "PSS0.PSS_IMUX_B23_14->PSS0_IMUX_B23_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_14" }, "PSS0.PSS_IMUX_B23_15->PSS0_IMUX_B23_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_15" }, "PSS0.PSS_IMUX_B23_16->PSS0_IMUX_B23_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_16" }, "PSS0.PSS_IMUX_B23_17->PSS0_IMUX_B23_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_17" }, "PSS0.PSS_IMUX_B23_18->PSS0_IMUX_B23_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_18" }, "PSS0.PSS_IMUX_B23_19->PSS0_IMUX_B23_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_19" }, "PSS0.PSS_IMUX_B23_2->PSS0_IMUX_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_2" }, "PSS0.PSS_IMUX_B23_3->PSS0_IMUX_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_3" }, "PSS0.PSS_IMUX_B23_4->PSS0_IMUX_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_4" }, "PSS0.PSS_IMUX_B23_5->PSS0_IMUX_B23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_5" }, "PSS0.PSS_IMUX_B23_6->PSS0_IMUX_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_6" }, "PSS0.PSS_IMUX_B23_7->PSS0_IMUX_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_7" }, "PSS0.PSS_IMUX_B23_8->PSS0_IMUX_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_8" }, "PSS0.PSS_IMUX_B23_9->PSS0_IMUX_B23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_9" }, "PSS0.PSS_IMUX_B24_0->PSS0_IMUX_B24_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_0" }, "PSS0.PSS_IMUX_B24_1->PSS0_IMUX_B24_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_1" }, "PSS0.PSS_IMUX_B24_10->PSS0_IMUX_B24_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_10" }, "PSS0.PSS_IMUX_B24_11->PSS0_IMUX_B24_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_11" }, "PSS0.PSS_IMUX_B24_12->PSS0_IMUX_B24_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_12" }, "PSS0.PSS_IMUX_B24_13->PSS0_IMUX_B24_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_13" }, "PSS0.PSS_IMUX_B24_14->PSS0_IMUX_B24_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_14" }, "PSS0.PSS_IMUX_B24_15->PSS0_IMUX_B24_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_15" }, "PSS0.PSS_IMUX_B24_16->PSS0_IMUX_B24_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_16" }, "PSS0.PSS_IMUX_B24_17->PSS0_IMUX_B24_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_17" }, "PSS0.PSS_IMUX_B24_18->PSS0_IMUX_B24_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_18" }, "PSS0.PSS_IMUX_B24_19->PSS0_IMUX_B24_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_19" }, "PSS0.PSS_IMUX_B24_2->PSS0_IMUX_B24_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_2" }, "PSS0.PSS_IMUX_B24_3->PSS0_IMUX_B24_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_3" }, "PSS0.PSS_IMUX_B24_4->PSS0_IMUX_B24_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_4" }, "PSS0.PSS_IMUX_B24_5->PSS0_IMUX_B24_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_5" }, "PSS0.PSS_IMUX_B24_6->PSS0_IMUX_B24_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_6" }, "PSS0.PSS_IMUX_B24_7->PSS0_IMUX_B24_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_7" }, "PSS0.PSS_IMUX_B24_8->PSS0_IMUX_B24_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_8" }, "PSS0.PSS_IMUX_B24_9->PSS0_IMUX_B24_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_9" }, "PSS0.PSS_IMUX_B25_0->PSS0_IMUX_B25_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_0" }, "PSS0.PSS_IMUX_B25_1->PSS0_IMUX_B25_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_1" }, "PSS0.PSS_IMUX_B25_10->PSS0_IMUX_B25_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_10" }, "PSS0.PSS_IMUX_B25_11->PSS0_IMUX_B25_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_11" }, "PSS0.PSS_IMUX_B25_12->PSS0_IMUX_B25_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_12" }, "PSS0.PSS_IMUX_B25_13->PSS0_IMUX_B25_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_13" }, "PSS0.PSS_IMUX_B25_14->PSS0_IMUX_B25_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_14" }, "PSS0.PSS_IMUX_B25_15->PSS0_IMUX_B25_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_15" }, "PSS0.PSS_IMUX_B25_16->PSS0_IMUX_B25_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_16" }, "PSS0.PSS_IMUX_B25_17->PSS0_IMUX_B25_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_17" }, "PSS0.PSS_IMUX_B25_18->PSS0_IMUX_B25_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_18" }, "PSS0.PSS_IMUX_B25_19->PSS0_IMUX_B25_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_19" }, "PSS0.PSS_IMUX_B25_2->PSS0_IMUX_B25_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_2" }, "PSS0.PSS_IMUX_B25_3->PSS0_IMUX_B25_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_3" }, "PSS0.PSS_IMUX_B25_4->PSS0_IMUX_B25_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_4" }, "PSS0.PSS_IMUX_B25_5->PSS0_IMUX_B25_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_5" }, "PSS0.PSS_IMUX_B25_6->PSS0_IMUX_B25_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_6" }, "PSS0.PSS_IMUX_B25_7->PSS0_IMUX_B25_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_7" }, "PSS0.PSS_IMUX_B25_8->PSS0_IMUX_B25_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_8" }, "PSS0.PSS_IMUX_B25_9->PSS0_IMUX_B25_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_9" }, "PSS0.PSS_IMUX_B26_0->PSS0_IMUX_B26_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_0" }, "PSS0.PSS_IMUX_B26_1->PSS0_IMUX_B26_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_1" }, "PSS0.PSS_IMUX_B26_10->PSS0_IMUX_B26_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_10" }, "PSS0.PSS_IMUX_B26_11->PSS0_IMUX_B26_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_11" }, "PSS0.PSS_IMUX_B26_12->PSS0_IMUX_B26_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_12" }, "PSS0.PSS_IMUX_B26_13->PSS0_IMUX_B26_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_13" }, "PSS0.PSS_IMUX_B26_14->PSS0_IMUX_B26_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_14" }, "PSS0.PSS_IMUX_B26_15->PSS0_IMUX_B26_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_15" }, "PSS0.PSS_IMUX_B26_16->PSS0_IMUX_B26_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_16" }, "PSS0.PSS_IMUX_B26_17->PSS0_IMUX_B26_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_17" }, "PSS0.PSS_IMUX_B26_18->PSS0_IMUX_B26_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_18" }, "PSS0.PSS_IMUX_B26_19->PSS0_IMUX_B26_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_19" }, "PSS0.PSS_IMUX_B26_2->PSS0_IMUX_B26_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_2" }, "PSS0.PSS_IMUX_B26_3->PSS0_IMUX_B26_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_3" }, "PSS0.PSS_IMUX_B26_4->PSS0_IMUX_B26_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_4" }, "PSS0.PSS_IMUX_B26_5->PSS0_IMUX_B26_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_5" }, "PSS0.PSS_IMUX_B26_6->PSS0_IMUX_B26_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_6" }, "PSS0.PSS_IMUX_B26_7->PSS0_IMUX_B26_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_7" }, "PSS0.PSS_IMUX_B26_8->PSS0_IMUX_B26_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_8" }, "PSS0.PSS_IMUX_B26_9->PSS0_IMUX_B26_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_9" }, "PSS0.PSS_IMUX_B27_0->PSS0_IMUX_B27_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_0" }, "PSS0.PSS_IMUX_B27_1->PSS0_IMUX_B27_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_1" }, "PSS0.PSS_IMUX_B27_10->PSS0_IMUX_B27_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_10" }, "PSS0.PSS_IMUX_B27_11->PSS0_IMUX_B27_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_11" }, "PSS0.PSS_IMUX_B27_12->PSS0_IMUX_B27_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_12" }, "PSS0.PSS_IMUX_B27_13->PSS0_IMUX_B27_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_13" }, "PSS0.PSS_IMUX_B27_14->PSS0_IMUX_B27_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_14" }, "PSS0.PSS_IMUX_B27_15->PSS0_IMUX_B27_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_15" }, "PSS0.PSS_IMUX_B27_16->PSS0_IMUX_B27_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_16" }, "PSS0.PSS_IMUX_B27_17->PSS0_IMUX_B27_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_17" }, "PSS0.PSS_IMUX_B27_18->PSS0_IMUX_B27_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_18" }, "PSS0.PSS_IMUX_B27_19->PSS0_IMUX_B27_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_19" }, "PSS0.PSS_IMUX_B27_2->PSS0_IMUX_B27_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_2" }, "PSS0.PSS_IMUX_B27_3->PSS0_IMUX_B27_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_3" }, "PSS0.PSS_IMUX_B27_4->PSS0_IMUX_B27_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_4" }, "PSS0.PSS_IMUX_B27_5->PSS0_IMUX_B27_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_5" }, "PSS0.PSS_IMUX_B27_6->PSS0_IMUX_B27_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_6" }, "PSS0.PSS_IMUX_B27_7->PSS0_IMUX_B27_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_7" }, "PSS0.PSS_IMUX_B27_8->PSS0_IMUX_B27_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_8" }, "PSS0.PSS_IMUX_B27_9->PSS0_IMUX_B27_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_9" }, "PSS0.PSS_IMUX_B28_0->PSS0_IMUX_B28_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_0" }, "PSS0.PSS_IMUX_B28_1->PSS0_IMUX_B28_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_1" }, "PSS0.PSS_IMUX_B28_10->PSS0_IMUX_B28_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_10" }, "PSS0.PSS_IMUX_B28_11->PSS0_IMUX_B28_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_11" }, "PSS0.PSS_IMUX_B28_12->PSS0_IMUX_B28_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_12" }, "PSS0.PSS_IMUX_B28_13->PSS0_IMUX_B28_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_13" }, "PSS0.PSS_IMUX_B28_14->PSS0_IMUX_B28_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_14" }, "PSS0.PSS_IMUX_B28_15->PSS0_IMUX_B28_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_15" }, "PSS0.PSS_IMUX_B28_16->PSS0_IMUX_B28_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_16" }, "PSS0.PSS_IMUX_B28_17->PSS0_IMUX_B28_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_17" }, "PSS0.PSS_IMUX_B28_18->PSS0_IMUX_B28_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_18" }, "PSS0.PSS_IMUX_B28_19->PSS0_IMUX_B28_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_19" }, "PSS0.PSS_IMUX_B28_2->PSS0_IMUX_B28_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_2" }, "PSS0.PSS_IMUX_B28_3->PSS0_IMUX_B28_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_3" }, "PSS0.PSS_IMUX_B28_4->PSS0_IMUX_B28_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_4" }, "PSS0.PSS_IMUX_B28_5->PSS0_IMUX_B28_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_5" }, "PSS0.PSS_IMUX_B28_6->PSS0_IMUX_B28_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_6" }, "PSS0.PSS_IMUX_B28_7->PSS0_IMUX_B28_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_7" }, "PSS0.PSS_IMUX_B28_8->PSS0_IMUX_B28_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_8" }, "PSS0.PSS_IMUX_B28_9->PSS0_IMUX_B28_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_9" }, "PSS0.PSS_IMUX_B29_0->PSS0_IMUX_B29_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_0" }, "PSS0.PSS_IMUX_B29_1->PSS0_IMUX_B29_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_1" }, "PSS0.PSS_IMUX_B29_10->PSS0_IMUX_B29_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_10" }, "PSS0.PSS_IMUX_B29_11->PSS0_IMUX_B29_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_11" }, "PSS0.PSS_IMUX_B29_12->PSS0_IMUX_B29_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_12" }, "PSS0.PSS_IMUX_B29_13->PSS0_IMUX_B29_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_13" }, "PSS0.PSS_IMUX_B29_14->PSS0_IMUX_B29_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_14" }, "PSS0.PSS_IMUX_B29_15->PSS0_IMUX_B29_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_15" }, "PSS0.PSS_IMUX_B29_16->PSS0_IMUX_B29_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_16" }, "PSS0.PSS_IMUX_B29_17->PSS0_IMUX_B29_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_17" }, "PSS0.PSS_IMUX_B29_18->PSS0_IMUX_B29_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_18" }, "PSS0.PSS_IMUX_B29_19->PSS0_IMUX_B29_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_19" }, "PSS0.PSS_IMUX_B29_2->PSS0_IMUX_B29_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_2" }, "PSS0.PSS_IMUX_B29_3->PSS0_IMUX_B29_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_3" }, "PSS0.PSS_IMUX_B29_4->PSS0_IMUX_B29_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_4" }, "PSS0.PSS_IMUX_B29_5->PSS0_IMUX_B29_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_5" }, "PSS0.PSS_IMUX_B29_6->PSS0_IMUX_B29_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_6" }, "PSS0.PSS_IMUX_B29_7->PSS0_IMUX_B29_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_7" }, "PSS0.PSS_IMUX_B29_8->PSS0_IMUX_B29_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_8" }, "PSS0.PSS_IMUX_B29_9->PSS0_IMUX_B29_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_9" }, "PSS0.PSS_IMUX_B2_0->PSS0_IMUX_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_0" }, "PSS0.PSS_IMUX_B2_1->PSS0_IMUX_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_1" }, "PSS0.PSS_IMUX_B2_10->PSS0_IMUX_B2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_10" }, "PSS0.PSS_IMUX_B2_11->PSS0_IMUX_B2_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_11" }, "PSS0.PSS_IMUX_B2_12->PSS0_IMUX_B2_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_12" }, "PSS0.PSS_IMUX_B2_13->PSS0_IMUX_B2_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_13" }, "PSS0.PSS_IMUX_B2_14->PSS0_IMUX_B2_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_14" }, "PSS0.PSS_IMUX_B2_15->PSS0_IMUX_B2_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_15" }, "PSS0.PSS_IMUX_B2_16->PSS0_IMUX_B2_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_16" }, "PSS0.PSS_IMUX_B2_17->PSS0_IMUX_B2_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_17" }, "PSS0.PSS_IMUX_B2_18->PSS0_IMUX_B2_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_18" }, "PSS0.PSS_IMUX_B2_19->PSS0_IMUX_B2_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_19" }, "PSS0.PSS_IMUX_B2_2->PSS0_IMUX_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_2" }, "PSS0.PSS_IMUX_B2_3->PSS0_IMUX_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_3" }, "PSS0.PSS_IMUX_B2_4->PSS0_IMUX_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_4" }, "PSS0.PSS_IMUX_B2_5->PSS0_IMUX_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_5" }, "PSS0.PSS_IMUX_B2_6->PSS0_IMUX_B2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_6" }, "PSS0.PSS_IMUX_B2_7->PSS0_IMUX_B2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_7" }, "PSS0.PSS_IMUX_B2_8->PSS0_IMUX_B2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_8" }, "PSS0.PSS_IMUX_B2_9->PSS0_IMUX_B2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_9" }, "PSS0.PSS_IMUX_B30_0->PSS0_IMUX_B30_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_0" }, "PSS0.PSS_IMUX_B30_1->PSS0_IMUX_B30_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_1" }, "PSS0.PSS_IMUX_B30_10->PSS0_IMUX_B30_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_10" }, "PSS0.PSS_IMUX_B30_11->PSS0_IMUX_B30_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_11" }, "PSS0.PSS_IMUX_B30_12->PSS0_IMUX_B30_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_12" }, "PSS0.PSS_IMUX_B30_13->PSS0_IMUX_B30_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_13" }, "PSS0.PSS_IMUX_B30_14->PSS0_IMUX_B30_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_14" }, "PSS0.PSS_IMUX_B30_15->PSS0_IMUX_B30_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_15" }, "PSS0.PSS_IMUX_B30_16->PSS0_IMUX_B30_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_16" }, "PSS0.PSS_IMUX_B30_17->PSS0_IMUX_B30_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_17" }, "PSS0.PSS_IMUX_B30_18->PSS0_IMUX_B30_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_18" }, "PSS0.PSS_IMUX_B30_19->PSS0_IMUX_B30_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_19" }, "PSS0.PSS_IMUX_B30_2->PSS0_IMUX_B30_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_2" }, "PSS0.PSS_IMUX_B30_3->PSS0_IMUX_B30_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_3" }, "PSS0.PSS_IMUX_B30_4->PSS0_IMUX_B30_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_4" }, "PSS0.PSS_IMUX_B30_5->PSS0_IMUX_B30_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_5" }, "PSS0.PSS_IMUX_B30_6->PSS0_IMUX_B30_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_6" }, "PSS0.PSS_IMUX_B30_7->PSS0_IMUX_B30_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_7" }, "PSS0.PSS_IMUX_B30_8->PSS0_IMUX_B30_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_8" }, "PSS0.PSS_IMUX_B30_9->PSS0_IMUX_B30_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_9" }, "PSS0.PSS_IMUX_B31_0->PSS0_IMUX_B31_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_0" }, "PSS0.PSS_IMUX_B31_1->PSS0_IMUX_B31_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_1" }, "PSS0.PSS_IMUX_B31_10->PSS0_IMUX_B31_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_10" }, "PSS0.PSS_IMUX_B31_11->PSS0_IMUX_B31_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_11" }, "PSS0.PSS_IMUX_B31_12->PSS0_IMUX_B31_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_12" }, "PSS0.PSS_IMUX_B31_13->PSS0_IMUX_B31_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_13" }, "PSS0.PSS_IMUX_B31_14->PSS0_IMUX_B31_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_14" }, "PSS0.PSS_IMUX_B31_15->PSS0_IMUX_B31_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_15" }, "PSS0.PSS_IMUX_B31_16->PSS0_IMUX_B31_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_16" }, "PSS0.PSS_IMUX_B31_17->PSS0_IMUX_B31_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_17" }, "PSS0.PSS_IMUX_B31_18->PSS0_IMUX_B31_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_18" }, "PSS0.PSS_IMUX_B31_19->PSS0_IMUX_B31_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_19" }, "PSS0.PSS_IMUX_B31_2->PSS0_IMUX_B31_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_2" }, "PSS0.PSS_IMUX_B31_3->PSS0_IMUX_B31_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_3" }, "PSS0.PSS_IMUX_B31_4->PSS0_IMUX_B31_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_4" }, "PSS0.PSS_IMUX_B31_5->PSS0_IMUX_B31_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_5" }, "PSS0.PSS_IMUX_B31_6->PSS0_IMUX_B31_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_6" }, "PSS0.PSS_IMUX_B31_7->PSS0_IMUX_B31_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_7" }, "PSS0.PSS_IMUX_B31_8->PSS0_IMUX_B31_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_8" }, "PSS0.PSS_IMUX_B31_9->PSS0_IMUX_B31_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_9" }, "PSS0.PSS_IMUX_B32_0->PSS0_IMUX_B32_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_0" }, "PSS0.PSS_IMUX_B32_1->PSS0_IMUX_B32_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_1" }, "PSS0.PSS_IMUX_B32_10->PSS0_IMUX_B32_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_10" }, "PSS0.PSS_IMUX_B32_11->PSS0_IMUX_B32_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_11" }, "PSS0.PSS_IMUX_B32_12->PSS0_IMUX_B32_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_12" }, "PSS0.PSS_IMUX_B32_13->PSS0_IMUX_B32_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_13" }, "PSS0.PSS_IMUX_B32_14->PSS0_IMUX_B32_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_14" }, "PSS0.PSS_IMUX_B32_15->PSS0_IMUX_B32_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_15" }, "PSS0.PSS_IMUX_B32_16->PSS0_IMUX_B32_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_16" }, "PSS0.PSS_IMUX_B32_17->PSS0_IMUX_B32_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_17" }, "PSS0.PSS_IMUX_B32_18->PSS0_IMUX_B32_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_18" }, "PSS0.PSS_IMUX_B32_19->PSS0_IMUX_B32_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_19" }, "PSS0.PSS_IMUX_B32_2->PSS0_IMUX_B32_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_2" }, "PSS0.PSS_IMUX_B32_3->PSS0_IMUX_B32_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_3" }, "PSS0.PSS_IMUX_B32_4->PSS0_IMUX_B32_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_4" }, "PSS0.PSS_IMUX_B32_5->PSS0_IMUX_B32_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_5" }, "PSS0.PSS_IMUX_B32_6->PSS0_IMUX_B32_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_6" }, "PSS0.PSS_IMUX_B32_7->PSS0_IMUX_B32_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_7" }, "PSS0.PSS_IMUX_B32_8->PSS0_IMUX_B32_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_8" }, "PSS0.PSS_IMUX_B32_9->PSS0_IMUX_B32_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_9" }, "PSS0.PSS_IMUX_B33_0->PSS0_IMUX_B33_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_0" }, "PSS0.PSS_IMUX_B33_1->PSS0_IMUX_B33_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_1" }, "PSS0.PSS_IMUX_B33_10->PSS0_IMUX_B33_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_10" }, "PSS0.PSS_IMUX_B33_11->PSS0_IMUX_B33_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_11" }, "PSS0.PSS_IMUX_B33_12->PSS0_IMUX_B33_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_12" }, "PSS0.PSS_IMUX_B33_13->PSS0_IMUX_B33_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_13" }, "PSS0.PSS_IMUX_B33_14->PSS0_IMUX_B33_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_14" }, "PSS0.PSS_IMUX_B33_15->PSS0_IMUX_B33_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_15" }, "PSS0.PSS_IMUX_B33_16->PSS0_IMUX_B33_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_16" }, "PSS0.PSS_IMUX_B33_17->PSS0_IMUX_B33_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_17" }, "PSS0.PSS_IMUX_B33_18->PSS0_IMUX_B33_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_18" }, "PSS0.PSS_IMUX_B33_19->PSS0_IMUX_B33_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_19" }, "PSS0.PSS_IMUX_B33_2->PSS0_IMUX_B33_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_2" }, "PSS0.PSS_IMUX_B33_3->PSS0_IMUX_B33_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_3" }, "PSS0.PSS_IMUX_B33_4->PSS0_IMUX_B33_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_4" }, "PSS0.PSS_IMUX_B33_5->PSS0_IMUX_B33_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_5" }, "PSS0.PSS_IMUX_B33_6->PSS0_IMUX_B33_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_6" }, "PSS0.PSS_IMUX_B33_7->PSS0_IMUX_B33_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_7" }, "PSS0.PSS_IMUX_B33_8->PSS0_IMUX_B33_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_8" }, "PSS0.PSS_IMUX_B33_9->PSS0_IMUX_B33_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_9" }, "PSS0.PSS_IMUX_B34_0->PSS0_IMUX_B34_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_0" }, "PSS0.PSS_IMUX_B34_1->PSS0_IMUX_B34_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_1" }, "PSS0.PSS_IMUX_B34_10->PSS0_IMUX_B34_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_10" }, "PSS0.PSS_IMUX_B34_11->PSS0_IMUX_B34_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_11" }, "PSS0.PSS_IMUX_B34_12->PSS0_IMUX_B34_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_12" }, "PSS0.PSS_IMUX_B34_13->PSS0_IMUX_B34_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_13" }, "PSS0.PSS_IMUX_B34_14->PSS0_IMUX_B34_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_14" }, "PSS0.PSS_IMUX_B34_15->PSS0_IMUX_B34_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_15" }, "PSS0.PSS_IMUX_B34_16->PSS0_IMUX_B34_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_16" }, "PSS0.PSS_IMUX_B34_17->PSS0_IMUX_B34_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_17" }, "PSS0.PSS_IMUX_B34_18->PSS0_IMUX_B34_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_18" }, "PSS0.PSS_IMUX_B34_19->PSS0_IMUX_B34_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_19" }, "PSS0.PSS_IMUX_B34_2->PSS0_IMUX_B34_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_2" }, "PSS0.PSS_IMUX_B34_3->PSS0_IMUX_B34_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_3" }, "PSS0.PSS_IMUX_B34_4->PSS0_IMUX_B34_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_4" }, "PSS0.PSS_IMUX_B34_5->PSS0_IMUX_B34_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_5" }, "PSS0.PSS_IMUX_B34_6->PSS0_IMUX_B34_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_6" }, "PSS0.PSS_IMUX_B34_7->PSS0_IMUX_B34_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_7" }, "PSS0.PSS_IMUX_B34_8->PSS0_IMUX_B34_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_8" }, "PSS0.PSS_IMUX_B34_9->PSS0_IMUX_B34_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_9" }, "PSS0.PSS_IMUX_B35_0->PSS0_IMUX_B35_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_0" }, "PSS0.PSS_IMUX_B35_1->PSS0_IMUX_B35_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_1" }, "PSS0.PSS_IMUX_B35_10->PSS0_IMUX_B35_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_10" }, "PSS0.PSS_IMUX_B35_11->PSS0_IMUX_B35_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_11" }, "PSS0.PSS_IMUX_B35_12->PSS0_IMUX_B35_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_12" }, "PSS0.PSS_IMUX_B35_13->PSS0_IMUX_B35_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_13" }, "PSS0.PSS_IMUX_B35_14->PSS0_IMUX_B35_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_14" }, "PSS0.PSS_IMUX_B35_15->PSS0_IMUX_B35_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_15" }, "PSS0.PSS_IMUX_B35_16->PSS0_IMUX_B35_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_16" }, "PSS0.PSS_IMUX_B35_17->PSS0_IMUX_B35_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_17" }, "PSS0.PSS_IMUX_B35_18->PSS0_IMUX_B35_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_18" }, "PSS0.PSS_IMUX_B35_19->PSS0_IMUX_B35_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_19" }, "PSS0.PSS_IMUX_B35_2->PSS0_IMUX_B35_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_2" }, "PSS0.PSS_IMUX_B35_3->PSS0_IMUX_B35_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_3" }, "PSS0.PSS_IMUX_B35_4->PSS0_IMUX_B35_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_4" }, "PSS0.PSS_IMUX_B35_5->PSS0_IMUX_B35_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_5" }, "PSS0.PSS_IMUX_B35_6->PSS0_IMUX_B35_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_6" }, "PSS0.PSS_IMUX_B35_7->PSS0_IMUX_B35_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_7" }, "PSS0.PSS_IMUX_B35_8->PSS0_IMUX_B35_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_8" }, "PSS0.PSS_IMUX_B35_9->PSS0_IMUX_B35_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_9" }, "PSS0.PSS_IMUX_B36_0->PSS0_IMUX_B36_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_0" }, "PSS0.PSS_IMUX_B36_1->PSS0_IMUX_B36_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_1" }, "PSS0.PSS_IMUX_B36_10->PSS0_IMUX_B36_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_10" }, "PSS0.PSS_IMUX_B36_11->PSS0_IMUX_B36_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_11" }, "PSS0.PSS_IMUX_B36_12->PSS0_IMUX_B36_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_12" }, "PSS0.PSS_IMUX_B36_13->PSS0_IMUX_B36_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_13" }, "PSS0.PSS_IMUX_B36_14->PSS0_IMUX_B36_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_14" }, "PSS0.PSS_IMUX_B36_15->PSS0_IMUX_B36_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_15" }, "PSS0.PSS_IMUX_B36_16->PSS0_IMUX_B36_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_16" }, "PSS0.PSS_IMUX_B36_17->PSS0_IMUX_B36_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_17" }, "PSS0.PSS_IMUX_B36_18->PSS0_IMUX_B36_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_18" }, "PSS0.PSS_IMUX_B36_19->PSS0_IMUX_B36_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_19" }, "PSS0.PSS_IMUX_B36_2->PSS0_IMUX_B36_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_2" }, "PSS0.PSS_IMUX_B36_3->PSS0_IMUX_B36_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_3" }, "PSS0.PSS_IMUX_B36_4->PSS0_IMUX_B36_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_4" }, "PSS0.PSS_IMUX_B36_5->PSS0_IMUX_B36_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_5" }, "PSS0.PSS_IMUX_B36_6->PSS0_IMUX_B36_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_6" }, "PSS0.PSS_IMUX_B36_7->PSS0_IMUX_B36_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_7" }, "PSS0.PSS_IMUX_B36_8->PSS0_IMUX_B36_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_8" }, "PSS0.PSS_IMUX_B36_9->PSS0_IMUX_B36_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_9" }, "PSS0.PSS_IMUX_B37_0->PSS0_IMUX_B37_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_0" }, "PSS0.PSS_IMUX_B37_1->PSS0_IMUX_B37_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_1" }, "PSS0.PSS_IMUX_B37_10->PSS0_IMUX_B37_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_10" }, "PSS0.PSS_IMUX_B37_11->PSS0_IMUX_B37_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_11" }, "PSS0.PSS_IMUX_B37_12->PSS0_IMUX_B37_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_12" }, "PSS0.PSS_IMUX_B37_13->PSS0_IMUX_B37_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_13" }, "PSS0.PSS_IMUX_B37_14->PSS0_IMUX_B37_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_14" }, "PSS0.PSS_IMUX_B37_15->PSS0_IMUX_B37_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_15" }, "PSS0.PSS_IMUX_B37_16->PSS0_IMUX_B37_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_16" }, "PSS0.PSS_IMUX_B37_17->PSS0_IMUX_B37_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_17" }, "PSS0.PSS_IMUX_B37_18->PSS0_IMUX_B37_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_18" }, "PSS0.PSS_IMUX_B37_19->PSS0_IMUX_B37_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_19" }, "PSS0.PSS_IMUX_B37_2->PSS0_IMUX_B37_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_2" }, "PSS0.PSS_IMUX_B37_3->PSS0_IMUX_B37_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_3" }, "PSS0.PSS_IMUX_B37_4->PSS0_IMUX_B37_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_4" }, "PSS0.PSS_IMUX_B37_5->PSS0_IMUX_B37_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_5" }, "PSS0.PSS_IMUX_B37_6->PSS0_IMUX_B37_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_6" }, "PSS0.PSS_IMUX_B37_7->PSS0_IMUX_B37_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_7" }, "PSS0.PSS_IMUX_B37_8->PSS0_IMUX_B37_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_8" }, "PSS0.PSS_IMUX_B37_9->PSS0_IMUX_B37_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_9" }, "PSS0.PSS_IMUX_B38_0->PSS0_IMUX_B38_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_0" }, "PSS0.PSS_IMUX_B38_1->PSS0_IMUX_B38_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_1" }, "PSS0.PSS_IMUX_B38_10->PSS0_IMUX_B38_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_10" }, "PSS0.PSS_IMUX_B38_11->PSS0_IMUX_B38_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_11" }, "PSS0.PSS_IMUX_B38_12->PSS0_IMUX_B38_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_12" }, "PSS0.PSS_IMUX_B38_13->PSS0_IMUX_B38_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_13" }, "PSS0.PSS_IMUX_B38_14->PSS0_IMUX_B38_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_14" }, "PSS0.PSS_IMUX_B38_15->PSS0_IMUX_B38_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_15" }, "PSS0.PSS_IMUX_B38_16->PSS0_IMUX_B38_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_16" }, "PSS0.PSS_IMUX_B38_17->PSS0_IMUX_B38_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_17" }, "PSS0.PSS_IMUX_B38_18->PSS0_IMUX_B38_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_18" }, "PSS0.PSS_IMUX_B38_19->PSS0_IMUX_B38_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_19" }, "PSS0.PSS_IMUX_B38_2->PSS0_IMUX_B38_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_2" }, "PSS0.PSS_IMUX_B38_3->PSS0_IMUX_B38_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_3" }, "PSS0.PSS_IMUX_B38_4->PSS0_IMUX_B38_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_4" }, "PSS0.PSS_IMUX_B38_5->PSS0_IMUX_B38_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_5" }, "PSS0.PSS_IMUX_B38_6->PSS0_IMUX_B38_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_6" }, "PSS0.PSS_IMUX_B38_7->PSS0_IMUX_B38_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_7" }, "PSS0.PSS_IMUX_B38_8->PSS0_IMUX_B38_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_8" }, "PSS0.PSS_IMUX_B38_9->PSS0_IMUX_B38_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_9" }, "PSS0.PSS_IMUX_B39_0->PSS0_IMUX_B39_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_0" }, "PSS0.PSS_IMUX_B39_1->PSS0_IMUX_B39_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_1" }, "PSS0.PSS_IMUX_B39_10->PSS0_IMUX_B39_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_10" }, "PSS0.PSS_IMUX_B39_11->PSS0_IMUX_B39_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_11" }, "PSS0.PSS_IMUX_B39_12->PSS0_IMUX_B39_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_12" }, "PSS0.PSS_IMUX_B39_13->PSS0_IMUX_B39_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_13" }, "PSS0.PSS_IMUX_B39_14->PSS0_IMUX_B39_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_14" }, "PSS0.PSS_IMUX_B39_15->PSS0_IMUX_B39_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_15" }, "PSS0.PSS_IMUX_B39_16->PSS0_IMUX_B39_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_16" }, "PSS0.PSS_IMUX_B39_17->PSS0_IMUX_B39_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_17" }, "PSS0.PSS_IMUX_B39_18->PSS0_IMUX_B39_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_18" }, "PSS0.PSS_IMUX_B39_19->PSS0_IMUX_B39_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_19" }, "PSS0.PSS_IMUX_B39_2->PSS0_IMUX_B39_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_2" }, "PSS0.PSS_IMUX_B39_3->PSS0_IMUX_B39_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_3" }, "PSS0.PSS_IMUX_B39_4->PSS0_IMUX_B39_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_4" }, "PSS0.PSS_IMUX_B39_5->PSS0_IMUX_B39_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_5" }, "PSS0.PSS_IMUX_B39_6->PSS0_IMUX_B39_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_6" }, "PSS0.PSS_IMUX_B39_7->PSS0_IMUX_B39_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_7" }, "PSS0.PSS_IMUX_B39_8->PSS0_IMUX_B39_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_8" }, "PSS0.PSS_IMUX_B39_9->PSS0_IMUX_B39_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_9" }, "PSS0.PSS_IMUX_B3_0->PSS0_IMUX_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_0" }, "PSS0.PSS_IMUX_B3_1->PSS0_IMUX_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_1" }, "PSS0.PSS_IMUX_B3_10->PSS0_IMUX_B3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_10" }, "PSS0.PSS_IMUX_B3_11->PSS0_IMUX_B3_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_11" }, "PSS0.PSS_IMUX_B3_12->PSS0_IMUX_B3_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_12" }, "PSS0.PSS_IMUX_B3_13->PSS0_IMUX_B3_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_13" }, "PSS0.PSS_IMUX_B3_14->PSS0_IMUX_B3_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_14" }, "PSS0.PSS_IMUX_B3_15->PSS0_IMUX_B3_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_15" }, "PSS0.PSS_IMUX_B3_16->PSS0_IMUX_B3_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_16" }, "PSS0.PSS_IMUX_B3_17->PSS0_IMUX_B3_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_17" }, "PSS0.PSS_IMUX_B3_18->PSS0_IMUX_B3_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_18" }, "PSS0.PSS_IMUX_B3_19->PSS0_IMUX_B3_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_19" }, "PSS0.PSS_IMUX_B3_2->PSS0_IMUX_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_2" }, "PSS0.PSS_IMUX_B3_3->PSS0_IMUX_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_3" }, "PSS0.PSS_IMUX_B3_4->PSS0_IMUX_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_4" }, "PSS0.PSS_IMUX_B3_5->PSS0_IMUX_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_5" }, "PSS0.PSS_IMUX_B3_6->PSS0_IMUX_B3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_6" }, "PSS0.PSS_IMUX_B3_7->PSS0_IMUX_B3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_7" }, "PSS0.PSS_IMUX_B3_8->PSS0_IMUX_B3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_8" }, "PSS0.PSS_IMUX_B3_9->PSS0_IMUX_B3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_9" }, "PSS0.PSS_IMUX_B40_0->PSS0_IMUX_B40_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_0" }, "PSS0.PSS_IMUX_B40_1->PSS0_IMUX_B40_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_1" }, "PSS0.PSS_IMUX_B40_10->PSS0_IMUX_B40_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_10" }, "PSS0.PSS_IMUX_B40_11->PSS0_IMUX_B40_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_11" }, "PSS0.PSS_IMUX_B40_12->PSS0_IMUX_B40_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_12" }, "PSS0.PSS_IMUX_B40_13->PSS0_IMUX_B40_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_13" }, "PSS0.PSS_IMUX_B40_14->PSS0_IMUX_B40_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_14" }, "PSS0.PSS_IMUX_B40_15->PSS0_IMUX_B40_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_15" }, "PSS0.PSS_IMUX_B40_16->PSS0_IMUX_B40_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_16" }, "PSS0.PSS_IMUX_B40_17->PSS0_IMUX_B40_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_17" }, "PSS0.PSS_IMUX_B40_18->PSS0_IMUX_B40_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_18" }, "PSS0.PSS_IMUX_B40_19->PSS0_IMUX_B40_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_19" }, "PSS0.PSS_IMUX_B40_2->PSS0_IMUX_B40_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_2" }, "PSS0.PSS_IMUX_B40_3->PSS0_IMUX_B40_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_3" }, "PSS0.PSS_IMUX_B40_4->PSS0_IMUX_B40_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_4" }, "PSS0.PSS_IMUX_B40_5->PSS0_IMUX_B40_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_5" }, "PSS0.PSS_IMUX_B40_6->PSS0_IMUX_B40_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_6" }, "PSS0.PSS_IMUX_B40_7->PSS0_IMUX_B40_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_7" }, "PSS0.PSS_IMUX_B40_8->PSS0_IMUX_B40_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_8" }, "PSS0.PSS_IMUX_B40_9->PSS0_IMUX_B40_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_9" }, "PSS0.PSS_IMUX_B41_0->PSS0_IMUX_B41_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_0" }, "PSS0.PSS_IMUX_B41_1->PSS0_IMUX_B41_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_1" }, "PSS0.PSS_IMUX_B41_10->PSS0_IMUX_B41_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_10" }, "PSS0.PSS_IMUX_B41_11->PSS0_IMUX_B41_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_11" }, "PSS0.PSS_IMUX_B41_12->PSS0_IMUX_B41_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_12" }, "PSS0.PSS_IMUX_B41_13->PSS0_IMUX_B41_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_13" }, "PSS0.PSS_IMUX_B41_14->PSS0_IMUX_B41_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_14" }, "PSS0.PSS_IMUX_B41_15->PSS0_IMUX_B41_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_15" }, "PSS0.PSS_IMUX_B41_16->PSS0_IMUX_B41_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_16" }, "PSS0.PSS_IMUX_B41_17->PSS0_IMUX_B41_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_17" }, "PSS0.PSS_IMUX_B41_18->PSS0_IMUX_B41_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_18" }, "PSS0.PSS_IMUX_B41_19->PSS0_IMUX_B41_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_19" }, "PSS0.PSS_IMUX_B41_2->PSS0_IMUX_B41_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_2" }, "PSS0.PSS_IMUX_B41_3->PSS0_IMUX_B41_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_3" }, "PSS0.PSS_IMUX_B41_4->PSS0_IMUX_B41_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_4" }, "PSS0.PSS_IMUX_B41_5->PSS0_IMUX_B41_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_5" }, "PSS0.PSS_IMUX_B41_6->PSS0_IMUX_B41_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_6" }, "PSS0.PSS_IMUX_B41_7->PSS0_IMUX_B41_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_7" }, "PSS0.PSS_IMUX_B41_8->PSS0_IMUX_B41_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_8" }, "PSS0.PSS_IMUX_B41_9->PSS0_IMUX_B41_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_9" }, "PSS0.PSS_IMUX_B42_0->PSS0_IMUX_B42_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_0" }, "PSS0.PSS_IMUX_B42_1->PSS0_IMUX_B42_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_1" }, "PSS0.PSS_IMUX_B42_10->PSS0_IMUX_B42_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_10" }, "PSS0.PSS_IMUX_B42_11->PSS0_IMUX_B42_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_11" }, "PSS0.PSS_IMUX_B42_12->PSS0_IMUX_B42_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_12" }, "PSS0.PSS_IMUX_B42_13->PSS0_IMUX_B42_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_13" }, "PSS0.PSS_IMUX_B42_14->PSS0_IMUX_B42_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_14" }, "PSS0.PSS_IMUX_B42_15->PSS0_IMUX_B42_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_15" }, "PSS0.PSS_IMUX_B42_16->PSS0_IMUX_B42_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_16" }, "PSS0.PSS_IMUX_B42_17->PSS0_IMUX_B42_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_17" }, "PSS0.PSS_IMUX_B42_18->PSS0_IMUX_B42_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_18" }, "PSS0.PSS_IMUX_B42_19->PSS0_IMUX_B42_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_19" }, "PSS0.PSS_IMUX_B42_2->PSS0_IMUX_B42_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_2" }, "PSS0.PSS_IMUX_B42_3->PSS0_IMUX_B42_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_3" }, "PSS0.PSS_IMUX_B42_4->PSS0_IMUX_B42_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_4" }, "PSS0.PSS_IMUX_B42_5->PSS0_IMUX_B42_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_5" }, "PSS0.PSS_IMUX_B42_6->PSS0_IMUX_B42_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_6" }, "PSS0.PSS_IMUX_B42_7->PSS0_IMUX_B42_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_7" }, "PSS0.PSS_IMUX_B42_8->PSS0_IMUX_B42_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_8" }, "PSS0.PSS_IMUX_B42_9->PSS0_IMUX_B42_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_9" }, "PSS0.PSS_IMUX_B43_0->PSS0_IMUX_B43_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_0" }, "PSS0.PSS_IMUX_B43_1->PSS0_IMUX_B43_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_1" }, "PSS0.PSS_IMUX_B43_10->PSS0_IMUX_B43_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_10" }, "PSS0.PSS_IMUX_B43_11->PSS0_IMUX_B43_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_11" }, "PSS0.PSS_IMUX_B43_12->PSS0_IMUX_B43_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_12" }, "PSS0.PSS_IMUX_B43_13->PSS0_IMUX_B43_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_13" }, "PSS0.PSS_IMUX_B43_14->PSS0_IMUX_B43_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_14" }, "PSS0.PSS_IMUX_B43_15->PSS0_IMUX_B43_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_15" }, "PSS0.PSS_IMUX_B43_16->PSS0_IMUX_B43_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_16" }, "PSS0.PSS_IMUX_B43_17->PSS0_IMUX_B43_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_17" }, "PSS0.PSS_IMUX_B43_18->PSS0_IMUX_B43_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_18" }, "PSS0.PSS_IMUX_B43_19->PSS0_IMUX_B43_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_19" }, "PSS0.PSS_IMUX_B43_2->PSS0_IMUX_B43_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_2" }, "PSS0.PSS_IMUX_B43_3->PSS0_IMUX_B43_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_3" }, "PSS0.PSS_IMUX_B43_4->PSS0_IMUX_B43_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_4" }, "PSS0.PSS_IMUX_B43_5->PSS0_IMUX_B43_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_5" }, "PSS0.PSS_IMUX_B43_6->PSS0_IMUX_B43_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_6" }, "PSS0.PSS_IMUX_B43_7->PSS0_IMUX_B43_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_7" }, "PSS0.PSS_IMUX_B43_8->PSS0_IMUX_B43_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_8" }, "PSS0.PSS_IMUX_B43_9->PSS0_IMUX_B43_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_9" }, "PSS0.PSS_IMUX_B44_0->PSS0_IMUX_B44_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_0" }, "PSS0.PSS_IMUX_B44_1->PSS0_IMUX_B44_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_1" }, "PSS0.PSS_IMUX_B44_10->PSS0_IMUX_B44_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_10" }, "PSS0.PSS_IMUX_B44_11->PSS0_IMUX_B44_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_11" }, "PSS0.PSS_IMUX_B44_12->PSS0_IMUX_B44_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_12" }, "PSS0.PSS_IMUX_B44_13->PSS0_IMUX_B44_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_13" }, "PSS0.PSS_IMUX_B44_14->PSS0_IMUX_B44_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_14" }, "PSS0.PSS_IMUX_B44_15->PSS0_IMUX_B44_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_15" }, "PSS0.PSS_IMUX_B44_16->PSS0_IMUX_B44_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_16" }, "PSS0.PSS_IMUX_B44_17->PSS0_IMUX_B44_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_17" }, "PSS0.PSS_IMUX_B44_18->PSS0_IMUX_B44_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_18" }, "PSS0.PSS_IMUX_B44_19->PSS0_IMUX_B44_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_19" }, "PSS0.PSS_IMUX_B44_2->PSS0_IMUX_B44_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_2" }, "PSS0.PSS_IMUX_B44_3->PSS0_IMUX_B44_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_3" }, "PSS0.PSS_IMUX_B44_4->PSS0_IMUX_B44_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_4" }, "PSS0.PSS_IMUX_B44_5->PSS0_IMUX_B44_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_5" }, "PSS0.PSS_IMUX_B44_6->PSS0_IMUX_B44_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_6" }, "PSS0.PSS_IMUX_B44_7->PSS0_IMUX_B44_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_7" }, "PSS0.PSS_IMUX_B44_8->PSS0_IMUX_B44_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_8" }, "PSS0.PSS_IMUX_B44_9->PSS0_IMUX_B44_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_9" }, "PSS0.PSS_IMUX_B45_0->PSS0_IMUX_B45_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_0" }, "PSS0.PSS_IMUX_B45_1->PSS0_IMUX_B45_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_1" }, "PSS0.PSS_IMUX_B45_10->PSS0_IMUX_B45_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_10" }, "PSS0.PSS_IMUX_B45_11->PSS0_IMUX_B45_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_11" }, "PSS0.PSS_IMUX_B45_12->PSS0_IMUX_B45_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_12" }, "PSS0.PSS_IMUX_B45_13->PSS0_IMUX_B45_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_13" }, "PSS0.PSS_IMUX_B45_14->PSS0_IMUX_B45_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_14" }, "PSS0.PSS_IMUX_B45_15->PSS0_IMUX_B45_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_15" }, "PSS0.PSS_IMUX_B45_16->PSS0_IMUX_B45_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_16" }, "PSS0.PSS_IMUX_B45_17->PSS0_IMUX_B45_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_17" }, "PSS0.PSS_IMUX_B45_18->PSS0_IMUX_B45_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_18" }, "PSS0.PSS_IMUX_B45_19->PSS0_IMUX_B45_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_19" }, "PSS0.PSS_IMUX_B45_2->PSS0_IMUX_B45_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_2" }, "PSS0.PSS_IMUX_B45_3->PSS0_IMUX_B45_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_3" }, "PSS0.PSS_IMUX_B45_4->PSS0_IMUX_B45_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_4" }, "PSS0.PSS_IMUX_B45_5->PSS0_IMUX_B45_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_5" }, "PSS0.PSS_IMUX_B45_6->PSS0_IMUX_B45_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_6" }, "PSS0.PSS_IMUX_B45_7->PSS0_IMUX_B45_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_7" }, "PSS0.PSS_IMUX_B45_8->PSS0_IMUX_B45_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_8" }, "PSS0.PSS_IMUX_B45_9->PSS0_IMUX_B45_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_9" }, "PSS0.PSS_IMUX_B46_0->PSS0_IMUX_B46_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_0" }, "PSS0.PSS_IMUX_B46_1->PSS0_IMUX_B46_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_1" }, "PSS0.PSS_IMUX_B46_10->PSS0_IMUX_B46_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_10" }, "PSS0.PSS_IMUX_B46_11->PSS0_IMUX_B46_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_11" }, "PSS0.PSS_IMUX_B46_12->PSS0_IMUX_B46_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_12" }, "PSS0.PSS_IMUX_B46_13->PSS0_IMUX_B46_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_13" }, "PSS0.PSS_IMUX_B46_14->PSS0_IMUX_B46_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_14" }, "PSS0.PSS_IMUX_B46_15->PSS0_IMUX_B46_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_15" }, "PSS0.PSS_IMUX_B46_16->PSS0_IMUX_B46_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_16" }, "PSS0.PSS_IMUX_B46_17->PSS0_IMUX_B46_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_17" }, "PSS0.PSS_IMUX_B46_18->PSS0_IMUX_B46_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_18" }, "PSS0.PSS_IMUX_B46_19->PSS0_IMUX_B46_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_19" }, "PSS0.PSS_IMUX_B46_2->PSS0_IMUX_B46_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_2" }, "PSS0.PSS_IMUX_B46_3->PSS0_IMUX_B46_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_3" }, "PSS0.PSS_IMUX_B46_4->PSS0_IMUX_B46_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_4" }, "PSS0.PSS_IMUX_B46_5->PSS0_IMUX_B46_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_5" }, "PSS0.PSS_IMUX_B46_6->PSS0_IMUX_B46_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_6" }, "PSS0.PSS_IMUX_B46_7->PSS0_IMUX_B46_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_7" }, "PSS0.PSS_IMUX_B46_8->PSS0_IMUX_B46_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_8" }, "PSS0.PSS_IMUX_B46_9->PSS0_IMUX_B46_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_9" }, "PSS0.PSS_IMUX_B47_0->PSS0_IMUX_B47_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_0" }, "PSS0.PSS_IMUX_B47_1->PSS0_IMUX_B47_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_1" }, "PSS0.PSS_IMUX_B47_10->PSS0_IMUX_B47_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_10" }, "PSS0.PSS_IMUX_B47_11->PSS0_IMUX_B47_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_11" }, "PSS0.PSS_IMUX_B47_12->PSS0_IMUX_B47_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_12" }, "PSS0.PSS_IMUX_B47_13->PSS0_IMUX_B47_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_13" }, "PSS0.PSS_IMUX_B47_14->PSS0_IMUX_B47_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_14" }, "PSS0.PSS_IMUX_B47_15->PSS0_IMUX_B47_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_15" }, "PSS0.PSS_IMUX_B47_16->PSS0_IMUX_B47_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_16" }, "PSS0.PSS_IMUX_B47_17->PSS0_IMUX_B47_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_17" }, "PSS0.PSS_IMUX_B47_18->PSS0_IMUX_B47_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_18" }, "PSS0.PSS_IMUX_B47_19->PSS0_IMUX_B47_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_19" }, "PSS0.PSS_IMUX_B47_2->PSS0_IMUX_B47_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_2" }, "PSS0.PSS_IMUX_B47_3->PSS0_IMUX_B47_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_3" }, "PSS0.PSS_IMUX_B47_4->PSS0_IMUX_B47_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_4" }, "PSS0.PSS_IMUX_B47_5->PSS0_IMUX_B47_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_5" }, "PSS0.PSS_IMUX_B47_6->PSS0_IMUX_B47_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_6" }, "PSS0.PSS_IMUX_B47_7->PSS0_IMUX_B47_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_7" }, "PSS0.PSS_IMUX_B47_8->PSS0_IMUX_B47_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_8" }, "PSS0.PSS_IMUX_B47_9->PSS0_IMUX_B47_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_9" }, "PSS0.PSS_IMUX_B4_0->PSS0_IMUX_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_0" }, "PSS0.PSS_IMUX_B4_1->PSS0_IMUX_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_1" }, "PSS0.PSS_IMUX_B4_10->PSS0_IMUX_B4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_10" }, "PSS0.PSS_IMUX_B4_11->PSS0_IMUX_B4_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_11" }, "PSS0.PSS_IMUX_B4_12->PSS0_IMUX_B4_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_12" }, "PSS0.PSS_IMUX_B4_13->PSS0_IMUX_B4_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_13" }, "PSS0.PSS_IMUX_B4_14->PSS0_IMUX_B4_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_14" }, "PSS0.PSS_IMUX_B4_15->PSS0_IMUX_B4_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_15" }, "PSS0.PSS_IMUX_B4_16->PSS0_IMUX_B4_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_16" }, "PSS0.PSS_IMUX_B4_17->PSS0_IMUX_B4_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_17" }, "PSS0.PSS_IMUX_B4_18->PSS0_IMUX_B4_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_18" }, "PSS0.PSS_IMUX_B4_19->PSS0_IMUX_B4_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_19" }, "PSS0.PSS_IMUX_B4_2->PSS0_IMUX_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_2" }, "PSS0.PSS_IMUX_B4_3->PSS0_IMUX_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_3" }, "PSS0.PSS_IMUX_B4_4->PSS0_IMUX_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_4" }, "PSS0.PSS_IMUX_B4_5->PSS0_IMUX_B4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_5" }, "PSS0.PSS_IMUX_B4_6->PSS0_IMUX_B4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_6" }, "PSS0.PSS_IMUX_B4_7->PSS0_IMUX_B4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_7" }, "PSS0.PSS_IMUX_B4_8->PSS0_IMUX_B4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_8" }, "PSS0.PSS_IMUX_B4_9->PSS0_IMUX_B4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_9" }, "PSS0.PSS_IMUX_B5_0->PSS0_IMUX_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_0" }, "PSS0.PSS_IMUX_B5_1->PSS0_IMUX_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_1" }, "PSS0.PSS_IMUX_B5_10->PSS0_IMUX_B5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_10" }, "PSS0.PSS_IMUX_B5_11->PSS0_IMUX_B5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_11" }, "PSS0.PSS_IMUX_B5_12->PSS0_IMUX_B5_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_12" }, "PSS0.PSS_IMUX_B5_13->PSS0_IMUX_B5_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_13" }, "PSS0.PSS_IMUX_B5_14->PSS0_IMUX_B5_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_14" }, "PSS0.PSS_IMUX_B5_15->PSS0_IMUX_B5_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_15" }, "PSS0.PSS_IMUX_B5_16->PSS0_IMUX_B5_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_16" }, "PSS0.PSS_IMUX_B5_17->PSS0_IMUX_B5_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_17" }, "PSS0.PSS_IMUX_B5_18->PSS0_IMUX_B5_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_18" }, "PSS0.PSS_IMUX_B5_19->PSS0_IMUX_B5_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_19" }, "PSS0.PSS_IMUX_B5_2->PSS0_IMUX_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_2" }, "PSS0.PSS_IMUX_B5_3->PSS0_IMUX_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_3" }, "PSS0.PSS_IMUX_B5_4->PSS0_IMUX_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_4" }, "PSS0.PSS_IMUX_B5_5->PSS0_IMUX_B5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_5" }, "PSS0.PSS_IMUX_B5_6->PSS0_IMUX_B5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_6" }, "PSS0.PSS_IMUX_B5_7->PSS0_IMUX_B5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_7" }, "PSS0.PSS_IMUX_B5_8->PSS0_IMUX_B5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_8" }, "PSS0.PSS_IMUX_B5_9->PSS0_IMUX_B5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_9" }, "PSS0.PSS_IMUX_B6_0->PSS0_IMUX_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_0" }, "PSS0.PSS_IMUX_B6_1->PSS0_IMUX_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_1" }, "PSS0.PSS_IMUX_B6_10->PSS0_IMUX_B6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_10" }, "PSS0.PSS_IMUX_B6_11->PSS0_IMUX_B6_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_11" }, "PSS0.PSS_IMUX_B6_12->PSS0_IMUX_B6_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_12" }, "PSS0.PSS_IMUX_B6_13->PSS0_IMUX_B6_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_13" }, "PSS0.PSS_IMUX_B6_14->PSS0_IMUX_B6_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_14" }, "PSS0.PSS_IMUX_B6_15->PSS0_IMUX_B6_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_15" }, "PSS0.PSS_IMUX_B6_16->PSS0_IMUX_B6_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_16" }, "PSS0.PSS_IMUX_B6_17->PSS0_IMUX_B6_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_17" }, "PSS0.PSS_IMUX_B6_18->PSS0_IMUX_B6_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_18" }, "PSS0.PSS_IMUX_B6_19->PSS0_IMUX_B6_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_19" }, "PSS0.PSS_IMUX_B6_2->PSS0_IMUX_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_2" }, "PSS0.PSS_IMUX_B6_3->PSS0_IMUX_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_3" }, "PSS0.PSS_IMUX_B6_4->PSS0_IMUX_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_4" }, "PSS0.PSS_IMUX_B6_5->PSS0_IMUX_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_5" }, "PSS0.PSS_IMUX_B6_6->PSS0_IMUX_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_6" }, "PSS0.PSS_IMUX_B6_7->PSS0_IMUX_B6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_7" }, "PSS0.PSS_IMUX_B6_8->PSS0_IMUX_B6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_8" }, "PSS0.PSS_IMUX_B6_9->PSS0_IMUX_B6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_9" }, "PSS0.PSS_IMUX_B7_0->PSS0_IMUX_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_0" }, "PSS0.PSS_IMUX_B7_1->PSS0_IMUX_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_1" }, "PSS0.PSS_IMUX_B7_10->PSS0_IMUX_B7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_10" }, "PSS0.PSS_IMUX_B7_11->PSS0_IMUX_B7_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_11" }, "PSS0.PSS_IMUX_B7_12->PSS0_IMUX_B7_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_12" }, "PSS0.PSS_IMUX_B7_13->PSS0_IMUX_B7_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_13" }, "PSS0.PSS_IMUX_B7_14->PSS0_IMUX_B7_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_14" }, "PSS0.PSS_IMUX_B7_15->PSS0_IMUX_B7_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_15" }, "PSS0.PSS_IMUX_B7_16->PSS0_IMUX_B7_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_16" }, "PSS0.PSS_IMUX_B7_17->PSS0_IMUX_B7_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_17" }, "PSS0.PSS_IMUX_B7_18->PSS0_IMUX_B7_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_18" }, "PSS0.PSS_IMUX_B7_19->PSS0_IMUX_B7_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_19" }, "PSS0.PSS_IMUX_B7_2->PSS0_IMUX_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_2" }, "PSS0.PSS_IMUX_B7_3->PSS0_IMUX_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_3" }, "PSS0.PSS_IMUX_B7_4->PSS0_IMUX_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_4" }, "PSS0.PSS_IMUX_B7_5->PSS0_IMUX_B7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_5" }, "PSS0.PSS_IMUX_B7_6->PSS0_IMUX_B7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_6" }, "PSS0.PSS_IMUX_B7_7->PSS0_IMUX_B7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_7" }, "PSS0.PSS_IMUX_B7_8->PSS0_IMUX_B7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_8" }, "PSS0.PSS_IMUX_B7_9->PSS0_IMUX_B7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_9" }, "PSS0.PSS_IMUX_B8_0->PSS0_IMUX_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_0" }, "PSS0.PSS_IMUX_B8_1->PSS0_IMUX_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_1" }, "PSS0.PSS_IMUX_B8_10->PSS0_IMUX_B8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_10" }, "PSS0.PSS_IMUX_B8_11->PSS0_IMUX_B8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_11" }, "PSS0.PSS_IMUX_B8_12->PSS0_IMUX_B8_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_12" }, "PSS0.PSS_IMUX_B8_13->PSS0_IMUX_B8_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_13" }, "PSS0.PSS_IMUX_B8_14->PSS0_IMUX_B8_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_14" }, "PSS0.PSS_IMUX_B8_15->PSS0_IMUX_B8_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_15" }, "PSS0.PSS_IMUX_B8_16->PSS0_IMUX_B8_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_16" }, "PSS0.PSS_IMUX_B8_17->PSS0_IMUX_B8_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_17" }, "PSS0.PSS_IMUX_B8_18->PSS0_IMUX_B8_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_18" }, "PSS0.PSS_IMUX_B8_19->PSS0_IMUX_B8_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_19" }, "PSS0.PSS_IMUX_B8_2->PSS0_IMUX_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_2" }, "PSS0.PSS_IMUX_B8_3->PSS0_IMUX_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_3" }, "PSS0.PSS_IMUX_B8_4->PSS0_IMUX_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_4" }, "PSS0.PSS_IMUX_B8_5->PSS0_IMUX_B8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_5" }, "PSS0.PSS_IMUX_B8_6->PSS0_IMUX_B8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_6" }, "PSS0.PSS_IMUX_B8_7->PSS0_IMUX_B8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_7" }, "PSS0.PSS_IMUX_B8_8->PSS0_IMUX_B8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_8" }, "PSS0.PSS_IMUX_B8_9->PSS0_IMUX_B8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_9" }, "PSS0.PSS_IMUX_B9_0->PSS0_IMUX_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_0" }, "PSS0.PSS_IMUX_B9_1->PSS0_IMUX_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_1" }, "PSS0.PSS_IMUX_B9_10->PSS0_IMUX_B9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_10" }, "PSS0.PSS_IMUX_B9_11->PSS0_IMUX_B9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_11" }, "PSS0.PSS_IMUX_B9_12->PSS0_IMUX_B9_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_12" }, "PSS0.PSS_IMUX_B9_13->PSS0_IMUX_B9_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_13" }, "PSS0.PSS_IMUX_B9_14->PSS0_IMUX_B9_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_14" }, "PSS0.PSS_IMUX_B9_15->PSS0_IMUX_B9_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_15" }, "PSS0.PSS_IMUX_B9_16->PSS0_IMUX_B9_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_16" }, "PSS0.PSS_IMUX_B9_17->PSS0_IMUX_B9_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_17" }, "PSS0.PSS_IMUX_B9_18->PSS0_IMUX_B9_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_18" }, "PSS0.PSS_IMUX_B9_19->PSS0_IMUX_B9_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_19" }, "PSS0.PSS_IMUX_B9_2->PSS0_IMUX_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_2" }, "PSS0.PSS_IMUX_B9_3->PSS0_IMUX_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_3" }, "PSS0.PSS_IMUX_B9_4->PSS0_IMUX_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_4" }, "PSS0.PSS_IMUX_B9_5->PSS0_IMUX_B9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_5" }, "PSS0.PSS_IMUX_B9_6->PSS0_IMUX_B9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_6" }, "PSS0.PSS_IMUX_B9_7->PSS0_IMUX_B9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_7" }, "PSS0.PSS_IMUX_B9_8->PSS0_IMUX_B9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_8" }, "PSS0.PSS_IMUX_B9_9->PSS0_IMUX_B9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_9" } }, "sites": [], "tile_type": "PSS0", - "wires": [ - "PSS0_CLK_B0_0", - "PSS0_CLK_B0_1", - "PSS0_CLK_B0_10", - "PSS0_CLK_B0_11", - "PSS0_CLK_B0_12", - "PSS0_CLK_B0_13", - "PSS0_CLK_B0_14", - "PSS0_CLK_B0_15", - "PSS0_CLK_B0_16", - "PSS0_CLK_B0_17", - "PSS0_CLK_B0_18", - "PSS0_CLK_B0_19", - "PSS0_CLK_B0_2", - "PSS0_CLK_B0_3", - "PSS0_CLK_B0_4", - "PSS0_CLK_B0_5", - "PSS0_CLK_B0_6", - "PSS0_CLK_B0_7", - "PSS0_CLK_B0_8", - "PSS0_CLK_B0_9", - "PSS0_CLK_B1_0", - "PSS0_CLK_B1_1", - "PSS0_CLK_B1_10", - "PSS0_CLK_B1_11", - "PSS0_CLK_B1_12", - "PSS0_CLK_B1_13", - "PSS0_CLK_B1_14", - "PSS0_CLK_B1_15", - "PSS0_CLK_B1_16", - "PSS0_CLK_B1_17", - "PSS0_CLK_B1_18", - "PSS0_CLK_B1_19", - "PSS0_CLK_B1_2", - "PSS0_CLK_B1_3", - "PSS0_CLK_B1_4", - "PSS0_CLK_B1_5", - "PSS0_CLK_B1_6", - "PSS0_CLK_B1_7", - "PSS0_CLK_B1_8", - "PSS0_CLK_B1_9", - "PSS0_IMUX_B0_0", - "PSS0_IMUX_B0_1", - "PSS0_IMUX_B0_10", - "PSS0_IMUX_B0_11", - "PSS0_IMUX_B0_12", - "PSS0_IMUX_B0_13", - "PSS0_IMUX_B0_14", - "PSS0_IMUX_B0_15", - "PSS0_IMUX_B0_16", - "PSS0_IMUX_B0_17", - "PSS0_IMUX_B0_18", - "PSS0_IMUX_B0_19", - "PSS0_IMUX_B0_2", - "PSS0_IMUX_B0_3", - "PSS0_IMUX_B0_4", - "PSS0_IMUX_B0_5", - "PSS0_IMUX_B0_6", - "PSS0_IMUX_B0_7", - "PSS0_IMUX_B0_8", - "PSS0_IMUX_B0_9", - "PSS0_IMUX_B10_0", - "PSS0_IMUX_B10_1", - "PSS0_IMUX_B10_10", - "PSS0_IMUX_B10_11", - "PSS0_IMUX_B10_12", - "PSS0_IMUX_B10_13", - "PSS0_IMUX_B10_14", - "PSS0_IMUX_B10_15", - "PSS0_IMUX_B10_16", - "PSS0_IMUX_B10_17", - "PSS0_IMUX_B10_18", - "PSS0_IMUX_B10_19", - "PSS0_IMUX_B10_2", - "PSS0_IMUX_B10_3", - "PSS0_IMUX_B10_4", - "PSS0_IMUX_B10_5", - "PSS0_IMUX_B10_6", - "PSS0_IMUX_B10_7", - "PSS0_IMUX_B10_8", - "PSS0_IMUX_B10_9", - "PSS0_IMUX_B11_0", - "PSS0_IMUX_B11_1", - "PSS0_IMUX_B11_10", - "PSS0_IMUX_B11_11", - "PSS0_IMUX_B11_12", - "PSS0_IMUX_B11_13", - "PSS0_IMUX_B11_14", - "PSS0_IMUX_B11_15", - "PSS0_IMUX_B11_16", - "PSS0_IMUX_B11_17", - "PSS0_IMUX_B11_18", - "PSS0_IMUX_B11_19", - "PSS0_IMUX_B11_2", - "PSS0_IMUX_B11_3", - "PSS0_IMUX_B11_4", - "PSS0_IMUX_B11_5", - "PSS0_IMUX_B11_6", - "PSS0_IMUX_B11_7", - "PSS0_IMUX_B11_8", - "PSS0_IMUX_B11_9", - "PSS0_IMUX_B12_0", - "PSS0_IMUX_B12_1", - "PSS0_IMUX_B12_10", - "PSS0_IMUX_B12_11", - "PSS0_IMUX_B12_12", - "PSS0_IMUX_B12_13", - "PSS0_IMUX_B12_14", - "PSS0_IMUX_B12_15", - "PSS0_IMUX_B12_16", - "PSS0_IMUX_B12_17", - "PSS0_IMUX_B12_18", - "PSS0_IMUX_B12_19", - "PSS0_IMUX_B12_2", - "PSS0_IMUX_B12_3", - "PSS0_IMUX_B12_4", - "PSS0_IMUX_B12_5", - "PSS0_IMUX_B12_6", - "PSS0_IMUX_B12_7", - "PSS0_IMUX_B12_8", - "PSS0_IMUX_B12_9", - "PSS0_IMUX_B13_0", - "PSS0_IMUX_B13_1", - "PSS0_IMUX_B13_10", - "PSS0_IMUX_B13_11", - "PSS0_IMUX_B13_12", - "PSS0_IMUX_B13_13", - "PSS0_IMUX_B13_14", - "PSS0_IMUX_B13_15", - "PSS0_IMUX_B13_16", - "PSS0_IMUX_B13_17", - "PSS0_IMUX_B13_18", - "PSS0_IMUX_B13_19", - "PSS0_IMUX_B13_2", - "PSS0_IMUX_B13_3", - "PSS0_IMUX_B13_4", - "PSS0_IMUX_B13_5", - "PSS0_IMUX_B13_6", - "PSS0_IMUX_B13_7", - "PSS0_IMUX_B13_8", - "PSS0_IMUX_B13_9", - "PSS0_IMUX_B14_0", - "PSS0_IMUX_B14_1", - "PSS0_IMUX_B14_10", - "PSS0_IMUX_B14_11", - "PSS0_IMUX_B14_12", - "PSS0_IMUX_B14_13", - "PSS0_IMUX_B14_14", - "PSS0_IMUX_B14_15", - "PSS0_IMUX_B14_16", - "PSS0_IMUX_B14_17", - "PSS0_IMUX_B14_18", - "PSS0_IMUX_B14_19", - "PSS0_IMUX_B14_2", - "PSS0_IMUX_B14_3", - "PSS0_IMUX_B14_4", - "PSS0_IMUX_B14_5", - "PSS0_IMUX_B14_6", - "PSS0_IMUX_B14_7", - "PSS0_IMUX_B14_8", - "PSS0_IMUX_B14_9", - "PSS0_IMUX_B15_0", - "PSS0_IMUX_B15_1", - "PSS0_IMUX_B15_10", - "PSS0_IMUX_B15_11", - "PSS0_IMUX_B15_12", - "PSS0_IMUX_B15_13", - "PSS0_IMUX_B15_14", - "PSS0_IMUX_B15_15", - "PSS0_IMUX_B15_16", - "PSS0_IMUX_B15_17", - "PSS0_IMUX_B15_18", - "PSS0_IMUX_B15_19", - "PSS0_IMUX_B15_2", - "PSS0_IMUX_B15_3", - "PSS0_IMUX_B15_4", - "PSS0_IMUX_B15_5", - "PSS0_IMUX_B15_6", - "PSS0_IMUX_B15_7", - "PSS0_IMUX_B15_8", - "PSS0_IMUX_B15_9", - "PSS0_IMUX_B16_0", - "PSS0_IMUX_B16_1", - "PSS0_IMUX_B16_10", - "PSS0_IMUX_B16_11", - "PSS0_IMUX_B16_12", - "PSS0_IMUX_B16_13", - "PSS0_IMUX_B16_14", - "PSS0_IMUX_B16_15", - "PSS0_IMUX_B16_16", - "PSS0_IMUX_B16_17", - "PSS0_IMUX_B16_18", - "PSS0_IMUX_B16_19", - "PSS0_IMUX_B16_2", - "PSS0_IMUX_B16_3", - "PSS0_IMUX_B16_4", - "PSS0_IMUX_B16_5", - "PSS0_IMUX_B16_6", - "PSS0_IMUX_B16_7", - "PSS0_IMUX_B16_8", - "PSS0_IMUX_B16_9", - "PSS0_IMUX_B17_0", - "PSS0_IMUX_B17_1", - "PSS0_IMUX_B17_10", - "PSS0_IMUX_B17_11", - "PSS0_IMUX_B17_12", - "PSS0_IMUX_B17_13", - "PSS0_IMUX_B17_14", - "PSS0_IMUX_B17_15", - "PSS0_IMUX_B17_16", - "PSS0_IMUX_B17_17", - "PSS0_IMUX_B17_18", - "PSS0_IMUX_B17_19", - "PSS0_IMUX_B17_2", - "PSS0_IMUX_B17_3", - "PSS0_IMUX_B17_4", - "PSS0_IMUX_B17_5", - "PSS0_IMUX_B17_6", - "PSS0_IMUX_B17_7", - "PSS0_IMUX_B17_8", - "PSS0_IMUX_B17_9", - "PSS0_IMUX_B18_0", - "PSS0_IMUX_B18_1", - "PSS0_IMUX_B18_10", - "PSS0_IMUX_B18_11", - "PSS0_IMUX_B18_12", - "PSS0_IMUX_B18_13", - "PSS0_IMUX_B18_14", - "PSS0_IMUX_B18_15", - "PSS0_IMUX_B18_16", - "PSS0_IMUX_B18_17", - "PSS0_IMUX_B18_18", - "PSS0_IMUX_B18_19", - "PSS0_IMUX_B18_2", - "PSS0_IMUX_B18_3", - "PSS0_IMUX_B18_4", - "PSS0_IMUX_B18_5", - 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"PSS0_IMUX_B41_13", - "PSS0_IMUX_B41_14", - "PSS0_IMUX_B41_15", - "PSS0_IMUX_B41_16", - "PSS0_IMUX_B41_17", - "PSS0_IMUX_B41_18", - "PSS0_IMUX_B41_19", - "PSS0_IMUX_B41_2", - "PSS0_IMUX_B41_3", - "PSS0_IMUX_B41_4", - "PSS0_IMUX_B41_5", - "PSS0_IMUX_B41_6", - "PSS0_IMUX_B41_7", - "PSS0_IMUX_B41_8", - "PSS0_IMUX_B41_9", - "PSS0_IMUX_B42_0", - "PSS0_IMUX_B42_1", - "PSS0_IMUX_B42_10", - "PSS0_IMUX_B42_11", - "PSS0_IMUX_B42_12", - "PSS0_IMUX_B42_13", - "PSS0_IMUX_B42_14", - "PSS0_IMUX_B42_15", - "PSS0_IMUX_B42_16", - "PSS0_IMUX_B42_17", - "PSS0_IMUX_B42_18", - "PSS0_IMUX_B42_19", - "PSS0_IMUX_B42_2", - "PSS0_IMUX_B42_3", - "PSS0_IMUX_B42_4", - "PSS0_IMUX_B42_5", - "PSS0_IMUX_B42_6", - "PSS0_IMUX_B42_7", - "PSS0_IMUX_B42_8", - "PSS0_IMUX_B42_9", - "PSS0_IMUX_B43_0", - "PSS0_IMUX_B43_1", - "PSS0_IMUX_B43_10", - "PSS0_IMUX_B43_11", - "PSS0_IMUX_B43_12", - "PSS0_IMUX_B43_13", - "PSS0_IMUX_B43_14", - "PSS0_IMUX_B43_15", - "PSS0_IMUX_B43_16", - "PSS0_IMUX_B43_17", - "PSS0_IMUX_B43_18", - "PSS0_IMUX_B43_19", - "PSS0_IMUX_B43_2", - "PSS0_IMUX_B43_3", - "PSS0_IMUX_B43_4", - "PSS0_IMUX_B43_5", - "PSS0_IMUX_B43_6", - "PSS0_IMUX_B43_7", - "PSS0_IMUX_B43_8", - "PSS0_IMUX_B43_9", - "PSS0_IMUX_B44_0", - "PSS0_IMUX_B44_1", - "PSS0_IMUX_B44_10", - "PSS0_IMUX_B44_11", - "PSS0_IMUX_B44_12", - "PSS0_IMUX_B44_13", - "PSS0_IMUX_B44_14", - "PSS0_IMUX_B44_15", - "PSS0_IMUX_B44_16", - "PSS0_IMUX_B44_17", - "PSS0_IMUX_B44_18", - "PSS0_IMUX_B44_19", - "PSS0_IMUX_B44_2", - "PSS0_IMUX_B44_3", - "PSS0_IMUX_B44_4", - "PSS0_IMUX_B44_5", - "PSS0_IMUX_B44_6", - "PSS0_IMUX_B44_7", - "PSS0_IMUX_B44_8", - "PSS0_IMUX_B44_9", - "PSS0_IMUX_B45_0", - "PSS0_IMUX_B45_1", - "PSS0_IMUX_B45_10", - "PSS0_IMUX_B45_11", - "PSS0_IMUX_B45_12", - "PSS0_IMUX_B45_13", - "PSS0_IMUX_B45_14", - "PSS0_IMUX_B45_15", - "PSS0_IMUX_B45_16", - "PSS0_IMUX_B45_17", - "PSS0_IMUX_B45_18", - "PSS0_IMUX_B45_19", - "PSS0_IMUX_B45_2", - "PSS0_IMUX_B45_3", - "PSS0_IMUX_B45_4", - "PSS0_IMUX_B45_5", - "PSS0_IMUX_B45_6", - "PSS0_IMUX_B45_7", - "PSS0_IMUX_B45_8", - "PSS0_IMUX_B45_9", - "PSS0_IMUX_B46_0", - "PSS0_IMUX_B46_1", - "PSS0_IMUX_B46_10", - "PSS0_IMUX_B46_11", - "PSS0_IMUX_B46_12", - "PSS0_IMUX_B46_13", - "PSS0_IMUX_B46_14", - "PSS0_IMUX_B46_15", - "PSS0_IMUX_B46_16", - "PSS0_IMUX_B46_17", - "PSS0_IMUX_B46_18", - "PSS0_IMUX_B46_19", - "PSS0_IMUX_B46_2", - "PSS0_IMUX_B46_3", - "PSS0_IMUX_B46_4", - "PSS0_IMUX_B46_5", - "PSS0_IMUX_B46_6", - "PSS0_IMUX_B46_7", - "PSS0_IMUX_B46_8", - "PSS0_IMUX_B46_9", - "PSS0_IMUX_B47_0", - "PSS0_IMUX_B47_1", - "PSS0_IMUX_B47_10", - "PSS0_IMUX_B47_11", - "PSS0_IMUX_B47_12", - "PSS0_IMUX_B47_13", - "PSS0_IMUX_B47_14", - "PSS0_IMUX_B47_15", - "PSS0_IMUX_B47_16", - "PSS0_IMUX_B47_17", - "PSS0_IMUX_B47_18", - "PSS0_IMUX_B47_19", - "PSS0_IMUX_B47_2", - "PSS0_IMUX_B47_3", - "PSS0_IMUX_B47_4", - "PSS0_IMUX_B47_5", - "PSS0_IMUX_B47_6", - "PSS0_IMUX_B47_7", - "PSS0_IMUX_B47_8", - "PSS0_IMUX_B47_9", - "PSS0_IMUX_B4_0", - "PSS0_IMUX_B4_1", - "PSS0_IMUX_B4_10", - "PSS0_IMUX_B4_11", - "PSS0_IMUX_B4_12", - "PSS0_IMUX_B4_13", - "PSS0_IMUX_B4_14", - "PSS0_IMUX_B4_15", - "PSS0_IMUX_B4_16", - "PSS0_IMUX_B4_17", - "PSS0_IMUX_B4_18", - "PSS0_IMUX_B4_19", - "PSS0_IMUX_B4_2", - "PSS0_IMUX_B4_3", - "PSS0_IMUX_B4_4", - "PSS0_IMUX_B4_5", - "PSS0_IMUX_B4_6", - "PSS0_IMUX_B4_7", - "PSS0_IMUX_B4_8", - "PSS0_IMUX_B4_9", - "PSS0_IMUX_B5_0", - "PSS0_IMUX_B5_1", - "PSS0_IMUX_B5_10", - "PSS0_IMUX_B5_11", - "PSS0_IMUX_B5_12", - "PSS0_IMUX_B5_13", - "PSS0_IMUX_B5_14", - "PSS0_IMUX_B5_15", - "PSS0_IMUX_B5_16", - "PSS0_IMUX_B5_17", - "PSS0_IMUX_B5_18", - "PSS0_IMUX_B5_19", - "PSS0_IMUX_B5_2", - "PSS0_IMUX_B5_3", - "PSS0_IMUX_B5_4", - "PSS0_IMUX_B5_5", - "PSS0_IMUX_B5_6", - "PSS0_IMUX_B5_7", - "PSS0_IMUX_B5_8", - "PSS0_IMUX_B5_9", - "PSS0_IMUX_B6_0", - "PSS0_IMUX_B6_1", - "PSS0_IMUX_B6_10", - "PSS0_IMUX_B6_11", - "PSS0_IMUX_B6_12", - "PSS0_IMUX_B6_13", - "PSS0_IMUX_B6_14", - "PSS0_IMUX_B6_15", - "PSS0_IMUX_B6_16", - "PSS0_IMUX_B6_17", - "PSS0_IMUX_B6_18", - "PSS0_IMUX_B6_19", - "PSS0_IMUX_B6_2", - "PSS0_IMUX_B6_3", - "PSS0_IMUX_B6_4", - "PSS0_IMUX_B6_5", - "PSS0_IMUX_B6_6", - "PSS0_IMUX_B6_7", - "PSS0_IMUX_B6_8", - "PSS0_IMUX_B6_9", - "PSS0_IMUX_B7_0", - "PSS0_IMUX_B7_1", - "PSS0_IMUX_B7_10", - "PSS0_IMUX_B7_11", - "PSS0_IMUX_B7_12", - "PSS0_IMUX_B7_13", - "PSS0_IMUX_B7_14", - "PSS0_IMUX_B7_15", - "PSS0_IMUX_B7_16", - "PSS0_IMUX_B7_17", - "PSS0_IMUX_B7_18", - "PSS0_IMUX_B7_19", - "PSS0_IMUX_B7_2", - "PSS0_IMUX_B7_3", - "PSS0_IMUX_B7_4", - "PSS0_IMUX_B7_5", - "PSS0_IMUX_B7_6", - "PSS0_IMUX_B7_7", - "PSS0_IMUX_B7_8", - "PSS0_IMUX_B7_9", - "PSS0_IMUX_B8_0", - "PSS0_IMUX_B8_1", - "PSS0_IMUX_B8_10", - "PSS0_IMUX_B8_11", - "PSS0_IMUX_B8_12", - "PSS0_IMUX_B8_13", - "PSS0_IMUX_B8_14", - "PSS0_IMUX_B8_15", - "PSS0_IMUX_B8_16", - "PSS0_IMUX_B8_17", - "PSS0_IMUX_B8_18", - "PSS0_IMUX_B8_19", - "PSS0_IMUX_B8_2", - "PSS0_IMUX_B8_3", - "PSS0_IMUX_B8_4", - "PSS0_IMUX_B8_5", - "PSS0_IMUX_B8_6", - "PSS0_IMUX_B8_7", - "PSS0_IMUX_B8_8", - "PSS0_IMUX_B8_9", - "PSS0_IMUX_B9_0", - "PSS0_IMUX_B9_1", - "PSS0_IMUX_B9_10", - "PSS0_IMUX_B9_11", - "PSS0_IMUX_B9_12", - "PSS0_IMUX_B9_13", - "PSS0_IMUX_B9_14", - "PSS0_IMUX_B9_15", - "PSS0_IMUX_B9_16", - "PSS0_IMUX_B9_17", - "PSS0_IMUX_B9_18", - "PSS0_IMUX_B9_19", - "PSS0_IMUX_B9_2", - "PSS0_IMUX_B9_3", - "PSS0_IMUX_B9_4", - "PSS0_IMUX_B9_5", - "PSS0_IMUX_B9_6", - "PSS0_IMUX_B9_7", - "PSS0_IMUX_B9_8", - "PSS0_IMUX_B9_9", - "PSS0_LOGIC_OUTS0_0", - "PSS0_LOGIC_OUTS0_1", - "PSS0_LOGIC_OUTS0_10", - "PSS0_LOGIC_OUTS0_11", - "PSS0_LOGIC_OUTS0_12", - "PSS0_LOGIC_OUTS0_13", - "PSS0_LOGIC_OUTS0_14", - "PSS0_LOGIC_OUTS0_15", - "PSS0_LOGIC_OUTS0_16", - "PSS0_LOGIC_OUTS0_17", - "PSS0_LOGIC_OUTS0_18", - "PSS0_LOGIC_OUTS0_19", - "PSS0_LOGIC_OUTS0_2", - "PSS0_LOGIC_OUTS0_3", - "PSS0_LOGIC_OUTS0_4", - "PSS0_LOGIC_OUTS0_5", - "PSS0_LOGIC_OUTS0_6", - "PSS0_LOGIC_OUTS0_7", - "PSS0_LOGIC_OUTS0_8", - "PSS0_LOGIC_OUTS0_9", - "PSS0_LOGIC_OUTS10_0", - "PSS0_LOGIC_OUTS10_1", - "PSS0_LOGIC_OUTS10_10", - "PSS0_LOGIC_OUTS10_11", - "PSS0_LOGIC_OUTS10_12", - "PSS0_LOGIC_OUTS10_13", - "PSS0_LOGIC_OUTS10_14", - "PSS0_LOGIC_OUTS10_15", - "PSS0_LOGIC_OUTS10_16", - "PSS0_LOGIC_OUTS10_17", - "PSS0_LOGIC_OUTS10_18", - "PSS0_LOGIC_OUTS10_19", - "PSS0_LOGIC_OUTS10_2", - "PSS0_LOGIC_OUTS10_3", - "PSS0_LOGIC_OUTS10_4", - "PSS0_LOGIC_OUTS10_5", - "PSS0_LOGIC_OUTS10_6", - "PSS0_LOGIC_OUTS10_7", - "PSS0_LOGIC_OUTS10_8", - "PSS0_LOGIC_OUTS10_9", - "PSS0_LOGIC_OUTS11_0", - "PSS0_LOGIC_OUTS11_1", - "PSS0_LOGIC_OUTS11_10", - "PSS0_LOGIC_OUTS11_11", - "PSS0_LOGIC_OUTS11_12", - "PSS0_LOGIC_OUTS11_13", - "PSS0_LOGIC_OUTS11_14", - "PSS0_LOGIC_OUTS11_15", - "PSS0_LOGIC_OUTS11_16", - "PSS0_LOGIC_OUTS11_17", - "PSS0_LOGIC_OUTS11_18", - "PSS0_LOGIC_OUTS11_19", - "PSS0_LOGIC_OUTS11_2", - "PSS0_LOGIC_OUTS11_3", - "PSS0_LOGIC_OUTS11_4", - "PSS0_LOGIC_OUTS11_5", - "PSS0_LOGIC_OUTS11_6", - "PSS0_LOGIC_OUTS11_7", - "PSS0_LOGIC_OUTS11_8", - "PSS0_LOGIC_OUTS11_9", - "PSS0_LOGIC_OUTS12_0", - "PSS0_LOGIC_OUTS12_1", - "PSS0_LOGIC_OUTS12_10", - "PSS0_LOGIC_OUTS12_11", - "PSS0_LOGIC_OUTS12_12", - "PSS0_LOGIC_OUTS12_13", - "PSS0_LOGIC_OUTS12_14", - "PSS0_LOGIC_OUTS12_15", - "PSS0_LOGIC_OUTS12_16", - "PSS0_LOGIC_OUTS12_17", - "PSS0_LOGIC_OUTS12_18", - "PSS0_LOGIC_OUTS12_19", - "PSS0_LOGIC_OUTS12_2", - "PSS0_LOGIC_OUTS12_3", - "PSS0_LOGIC_OUTS12_4", - "PSS0_LOGIC_OUTS12_5", - "PSS0_LOGIC_OUTS12_6", - "PSS0_LOGIC_OUTS12_7", - "PSS0_LOGIC_OUTS12_8", - "PSS0_LOGIC_OUTS12_9", - "PSS0_LOGIC_OUTS13_0", - "PSS0_LOGIC_OUTS13_1", - "PSS0_LOGIC_OUTS13_10", - "PSS0_LOGIC_OUTS13_11", - "PSS0_LOGIC_OUTS13_12", - "PSS0_LOGIC_OUTS13_13", - "PSS0_LOGIC_OUTS13_14", - "PSS0_LOGIC_OUTS13_15", - "PSS0_LOGIC_OUTS13_16", - "PSS0_LOGIC_OUTS13_17", - "PSS0_LOGIC_OUTS13_18", - "PSS0_LOGIC_OUTS13_19", - "PSS0_LOGIC_OUTS13_2", - "PSS0_LOGIC_OUTS13_3", - "PSS0_LOGIC_OUTS13_4", - "PSS0_LOGIC_OUTS13_5", - "PSS0_LOGIC_OUTS13_6", - "PSS0_LOGIC_OUTS13_7", - "PSS0_LOGIC_OUTS13_8", - "PSS0_LOGIC_OUTS13_9", - "PSS0_LOGIC_OUTS14_0", - "PSS0_LOGIC_OUTS14_1", - "PSS0_LOGIC_OUTS14_10", - "PSS0_LOGIC_OUTS14_11", - "PSS0_LOGIC_OUTS14_12", - "PSS0_LOGIC_OUTS14_13", - "PSS0_LOGIC_OUTS14_14", - "PSS0_LOGIC_OUTS14_15", - "PSS0_LOGIC_OUTS14_16", - "PSS0_LOGIC_OUTS14_17", - "PSS0_LOGIC_OUTS14_18", - "PSS0_LOGIC_OUTS14_19", - "PSS0_LOGIC_OUTS14_2", - "PSS0_LOGIC_OUTS14_3", - "PSS0_LOGIC_OUTS14_4", - "PSS0_LOGIC_OUTS14_5", - "PSS0_LOGIC_OUTS14_6", - "PSS0_LOGIC_OUTS14_7", - "PSS0_LOGIC_OUTS14_8", - "PSS0_LOGIC_OUTS14_9", - "PSS0_LOGIC_OUTS15_0", - "PSS0_LOGIC_OUTS15_1", - "PSS0_LOGIC_OUTS15_10", - "PSS0_LOGIC_OUTS15_11", - "PSS0_LOGIC_OUTS15_12", - "PSS0_LOGIC_OUTS15_13", - "PSS0_LOGIC_OUTS15_14", - "PSS0_LOGIC_OUTS15_15", - "PSS0_LOGIC_OUTS15_16", - "PSS0_LOGIC_OUTS15_17", - "PSS0_LOGIC_OUTS15_18", - "PSS0_LOGIC_OUTS15_19", - "PSS0_LOGIC_OUTS15_2", - "PSS0_LOGIC_OUTS15_3", - "PSS0_LOGIC_OUTS15_4", - "PSS0_LOGIC_OUTS15_5", - "PSS0_LOGIC_OUTS15_6", - "PSS0_LOGIC_OUTS15_7", - "PSS0_LOGIC_OUTS15_8", - "PSS0_LOGIC_OUTS15_9", - "PSS0_LOGIC_OUTS16_0", - "PSS0_LOGIC_OUTS16_1", - "PSS0_LOGIC_OUTS16_10", - "PSS0_LOGIC_OUTS16_11", - "PSS0_LOGIC_OUTS16_12", - "PSS0_LOGIC_OUTS16_13", - "PSS0_LOGIC_OUTS16_14", - "PSS0_LOGIC_OUTS16_15", - "PSS0_LOGIC_OUTS16_16", - "PSS0_LOGIC_OUTS16_17", - "PSS0_LOGIC_OUTS16_18", - "PSS0_LOGIC_OUTS16_19", - "PSS0_LOGIC_OUTS16_2", - "PSS0_LOGIC_OUTS16_3", - "PSS0_LOGIC_OUTS16_4", - "PSS0_LOGIC_OUTS16_5", - "PSS0_LOGIC_OUTS16_6", - "PSS0_LOGIC_OUTS16_7", - "PSS0_LOGIC_OUTS16_8", - "PSS0_LOGIC_OUTS16_9", - "PSS0_LOGIC_OUTS17_0", - "PSS0_LOGIC_OUTS17_1", - "PSS0_LOGIC_OUTS17_10", - "PSS0_LOGIC_OUTS17_11", - "PSS0_LOGIC_OUTS17_12", - "PSS0_LOGIC_OUTS17_13", - "PSS0_LOGIC_OUTS17_14", - "PSS0_LOGIC_OUTS17_15", - "PSS0_LOGIC_OUTS17_16", - "PSS0_LOGIC_OUTS17_17", - "PSS0_LOGIC_OUTS17_18", - "PSS0_LOGIC_OUTS17_19", - "PSS0_LOGIC_OUTS17_2", - "PSS0_LOGIC_OUTS17_3", - "PSS0_LOGIC_OUTS17_4", - "PSS0_LOGIC_OUTS17_5", - "PSS0_LOGIC_OUTS17_6", - "PSS0_LOGIC_OUTS17_7", - "PSS0_LOGIC_OUTS17_8", - "PSS0_LOGIC_OUTS17_9", - "PSS0_LOGIC_OUTS18_0", - "PSS0_LOGIC_OUTS18_1", - "PSS0_LOGIC_OUTS18_10", - "PSS0_LOGIC_OUTS18_11", - "PSS0_LOGIC_OUTS18_12", - "PSS0_LOGIC_OUTS18_13", - "PSS0_LOGIC_OUTS18_14", - "PSS0_LOGIC_OUTS18_15", - "PSS0_LOGIC_OUTS18_16", - "PSS0_LOGIC_OUTS18_17", - "PSS0_LOGIC_OUTS18_18", - "PSS0_LOGIC_OUTS18_19", - "PSS0_LOGIC_OUTS18_2", - "PSS0_LOGIC_OUTS18_3", - "PSS0_LOGIC_OUTS18_4", - "PSS0_LOGIC_OUTS18_5", - "PSS0_LOGIC_OUTS18_6", - "PSS0_LOGIC_OUTS18_7", - "PSS0_LOGIC_OUTS18_8", - "PSS0_LOGIC_OUTS18_9", - "PSS0_LOGIC_OUTS19_0", - "PSS0_LOGIC_OUTS19_1", - "PSS0_LOGIC_OUTS19_10", - "PSS0_LOGIC_OUTS19_11", - "PSS0_LOGIC_OUTS19_12", - "PSS0_LOGIC_OUTS19_13", - "PSS0_LOGIC_OUTS19_14", - "PSS0_LOGIC_OUTS19_15", - "PSS0_LOGIC_OUTS19_16", - "PSS0_LOGIC_OUTS19_17", - "PSS0_LOGIC_OUTS19_18", - "PSS0_LOGIC_OUTS19_19", - "PSS0_LOGIC_OUTS19_2", - "PSS0_LOGIC_OUTS19_3", - "PSS0_LOGIC_OUTS19_4", - "PSS0_LOGIC_OUTS19_5", - "PSS0_LOGIC_OUTS19_6", - "PSS0_LOGIC_OUTS19_7", - "PSS0_LOGIC_OUTS19_8", - "PSS0_LOGIC_OUTS19_9", - "PSS0_LOGIC_OUTS1_0", - "PSS0_LOGIC_OUTS1_1", - "PSS0_LOGIC_OUTS1_10", - "PSS0_LOGIC_OUTS1_11", - "PSS0_LOGIC_OUTS1_12", - "PSS0_LOGIC_OUTS1_13", - "PSS0_LOGIC_OUTS1_14", - "PSS0_LOGIC_OUTS1_15", - "PSS0_LOGIC_OUTS1_16", - "PSS0_LOGIC_OUTS1_17", - "PSS0_LOGIC_OUTS1_18", - "PSS0_LOGIC_OUTS1_19", - "PSS0_LOGIC_OUTS1_2", - "PSS0_LOGIC_OUTS1_3", - "PSS0_LOGIC_OUTS1_4", - "PSS0_LOGIC_OUTS1_5", - "PSS0_LOGIC_OUTS1_6", - "PSS0_LOGIC_OUTS1_7", - "PSS0_LOGIC_OUTS1_8", - "PSS0_LOGIC_OUTS1_9", - "PSS0_LOGIC_OUTS20_0", - "PSS0_LOGIC_OUTS20_1", - "PSS0_LOGIC_OUTS20_10", - "PSS0_LOGIC_OUTS20_11", - "PSS0_LOGIC_OUTS20_12", - "PSS0_LOGIC_OUTS20_13", - "PSS0_LOGIC_OUTS20_14", - "PSS0_LOGIC_OUTS20_15", - "PSS0_LOGIC_OUTS20_16", - "PSS0_LOGIC_OUTS20_17", - "PSS0_LOGIC_OUTS20_18", - "PSS0_LOGIC_OUTS20_19", - "PSS0_LOGIC_OUTS20_2", - "PSS0_LOGIC_OUTS20_3", - "PSS0_LOGIC_OUTS20_4", - "PSS0_LOGIC_OUTS20_5", - "PSS0_LOGIC_OUTS20_6", - "PSS0_LOGIC_OUTS20_7", - "PSS0_LOGIC_OUTS20_8", - "PSS0_LOGIC_OUTS20_9", - "PSS0_LOGIC_OUTS21_0", - "PSS0_LOGIC_OUTS21_1", - "PSS0_LOGIC_OUTS21_10", - "PSS0_LOGIC_OUTS21_11", - "PSS0_LOGIC_OUTS21_12", - "PSS0_LOGIC_OUTS21_13", - "PSS0_LOGIC_OUTS21_14", - "PSS0_LOGIC_OUTS21_15", - "PSS0_LOGIC_OUTS21_16", - "PSS0_LOGIC_OUTS21_17", - "PSS0_LOGIC_OUTS21_18", - "PSS0_LOGIC_OUTS21_19", - "PSS0_LOGIC_OUTS21_2", - "PSS0_LOGIC_OUTS21_3", - "PSS0_LOGIC_OUTS21_4", - "PSS0_LOGIC_OUTS21_5", - "PSS0_LOGIC_OUTS21_6", - "PSS0_LOGIC_OUTS21_7", - "PSS0_LOGIC_OUTS21_8", - "PSS0_LOGIC_OUTS21_9", - "PSS0_LOGIC_OUTS22_0", - "PSS0_LOGIC_OUTS22_1", - "PSS0_LOGIC_OUTS22_10", - "PSS0_LOGIC_OUTS22_11", - "PSS0_LOGIC_OUTS22_12", - "PSS0_LOGIC_OUTS22_13", - "PSS0_LOGIC_OUTS22_14", - "PSS0_LOGIC_OUTS22_15", - "PSS0_LOGIC_OUTS22_16", - "PSS0_LOGIC_OUTS22_17", - "PSS0_LOGIC_OUTS22_18", - "PSS0_LOGIC_OUTS22_19", - "PSS0_LOGIC_OUTS22_2", - "PSS0_LOGIC_OUTS22_3", - "PSS0_LOGIC_OUTS22_4", - "PSS0_LOGIC_OUTS22_5", - "PSS0_LOGIC_OUTS22_6", - "PSS0_LOGIC_OUTS22_7", - "PSS0_LOGIC_OUTS22_8", - "PSS0_LOGIC_OUTS22_9", - "PSS0_LOGIC_OUTS23_0", - "PSS0_LOGIC_OUTS23_1", - "PSS0_LOGIC_OUTS23_10", - "PSS0_LOGIC_OUTS23_11", - "PSS0_LOGIC_OUTS23_12", - "PSS0_LOGIC_OUTS23_13", - "PSS0_LOGIC_OUTS23_14", - "PSS0_LOGIC_OUTS23_15", - "PSS0_LOGIC_OUTS23_16", - "PSS0_LOGIC_OUTS23_17", - "PSS0_LOGIC_OUTS23_18", - "PSS0_LOGIC_OUTS23_19", - "PSS0_LOGIC_OUTS23_2", - "PSS0_LOGIC_OUTS23_3", - "PSS0_LOGIC_OUTS23_4", - "PSS0_LOGIC_OUTS23_5", - "PSS0_LOGIC_OUTS23_6", - "PSS0_LOGIC_OUTS23_7", - "PSS0_LOGIC_OUTS23_8", - "PSS0_LOGIC_OUTS23_9", - "PSS0_LOGIC_OUTS2_0", - "PSS0_LOGIC_OUTS2_1", - "PSS0_LOGIC_OUTS2_10", - "PSS0_LOGIC_OUTS2_11", - "PSS0_LOGIC_OUTS2_12", - "PSS0_LOGIC_OUTS2_13", - "PSS0_LOGIC_OUTS2_14", - "PSS0_LOGIC_OUTS2_15", - "PSS0_LOGIC_OUTS2_16", - "PSS0_LOGIC_OUTS2_17", - "PSS0_LOGIC_OUTS2_18", - "PSS0_LOGIC_OUTS2_19", - "PSS0_LOGIC_OUTS2_2", - "PSS0_LOGIC_OUTS2_3", - "PSS0_LOGIC_OUTS2_4", - "PSS0_LOGIC_OUTS2_5", - "PSS0_LOGIC_OUTS2_6", - "PSS0_LOGIC_OUTS2_7", - "PSS0_LOGIC_OUTS2_8", - "PSS0_LOGIC_OUTS2_9", - "PSS0_LOGIC_OUTS3_0", - "PSS0_LOGIC_OUTS3_1", - "PSS0_LOGIC_OUTS3_10", - "PSS0_LOGIC_OUTS3_11", - "PSS0_LOGIC_OUTS3_12", - "PSS0_LOGIC_OUTS3_13", - "PSS0_LOGIC_OUTS3_14", - "PSS0_LOGIC_OUTS3_15", - "PSS0_LOGIC_OUTS3_16", - "PSS0_LOGIC_OUTS3_17", - "PSS0_LOGIC_OUTS3_18", - "PSS0_LOGIC_OUTS3_19", - "PSS0_LOGIC_OUTS3_2", - "PSS0_LOGIC_OUTS3_3", - "PSS0_LOGIC_OUTS3_4", - "PSS0_LOGIC_OUTS3_5", - "PSS0_LOGIC_OUTS3_6", - "PSS0_LOGIC_OUTS3_7", - "PSS0_LOGIC_OUTS3_8", - "PSS0_LOGIC_OUTS3_9", - "PSS0_LOGIC_OUTS4_0", - "PSS0_LOGIC_OUTS4_1", - "PSS0_LOGIC_OUTS4_10", - "PSS0_LOGIC_OUTS4_11", - "PSS0_LOGIC_OUTS4_12", - "PSS0_LOGIC_OUTS4_13", - "PSS0_LOGIC_OUTS4_14", - "PSS0_LOGIC_OUTS4_15", - "PSS0_LOGIC_OUTS4_16", - "PSS0_LOGIC_OUTS4_17", - "PSS0_LOGIC_OUTS4_18", - "PSS0_LOGIC_OUTS4_19", - "PSS0_LOGIC_OUTS4_2", - "PSS0_LOGIC_OUTS4_3", - "PSS0_LOGIC_OUTS4_4", - "PSS0_LOGIC_OUTS4_5", - "PSS0_LOGIC_OUTS4_6", - "PSS0_LOGIC_OUTS4_7", - "PSS0_LOGIC_OUTS4_8", - "PSS0_LOGIC_OUTS4_9", - "PSS0_LOGIC_OUTS5_0", - "PSS0_LOGIC_OUTS5_1", - "PSS0_LOGIC_OUTS5_10", - "PSS0_LOGIC_OUTS5_11", - "PSS0_LOGIC_OUTS5_12", - "PSS0_LOGIC_OUTS5_13", - "PSS0_LOGIC_OUTS5_14", - "PSS0_LOGIC_OUTS5_15", - "PSS0_LOGIC_OUTS5_16", - "PSS0_LOGIC_OUTS5_17", - "PSS0_LOGIC_OUTS5_18", - "PSS0_LOGIC_OUTS5_19", - "PSS0_LOGIC_OUTS5_2", - "PSS0_LOGIC_OUTS5_3", - "PSS0_LOGIC_OUTS5_4", - "PSS0_LOGIC_OUTS5_5", - "PSS0_LOGIC_OUTS5_6", - "PSS0_LOGIC_OUTS5_7", - "PSS0_LOGIC_OUTS5_8", - "PSS0_LOGIC_OUTS5_9", - "PSS0_LOGIC_OUTS6_0", - "PSS0_LOGIC_OUTS6_1", - "PSS0_LOGIC_OUTS6_10", - "PSS0_LOGIC_OUTS6_11", - "PSS0_LOGIC_OUTS6_12", - "PSS0_LOGIC_OUTS6_13", - "PSS0_LOGIC_OUTS6_14", - "PSS0_LOGIC_OUTS6_15", - "PSS0_LOGIC_OUTS6_16", - "PSS0_LOGIC_OUTS6_17", - "PSS0_LOGIC_OUTS6_18", - "PSS0_LOGIC_OUTS6_19", - "PSS0_LOGIC_OUTS6_2", - "PSS0_LOGIC_OUTS6_3", - "PSS0_LOGIC_OUTS6_4", - "PSS0_LOGIC_OUTS6_5", - "PSS0_LOGIC_OUTS6_6", - "PSS0_LOGIC_OUTS6_7", - "PSS0_LOGIC_OUTS6_8", - "PSS0_LOGIC_OUTS6_9", - "PSS0_LOGIC_OUTS7_0", - "PSS0_LOGIC_OUTS7_1", - "PSS0_LOGIC_OUTS7_10", - "PSS0_LOGIC_OUTS7_11", - "PSS0_LOGIC_OUTS7_12", - "PSS0_LOGIC_OUTS7_13", - "PSS0_LOGIC_OUTS7_14", - "PSS0_LOGIC_OUTS7_15", - "PSS0_LOGIC_OUTS7_16", - "PSS0_LOGIC_OUTS7_17", - "PSS0_LOGIC_OUTS7_18", - "PSS0_LOGIC_OUTS7_19", - "PSS0_LOGIC_OUTS7_2", - "PSS0_LOGIC_OUTS7_3", - "PSS0_LOGIC_OUTS7_4", - "PSS0_LOGIC_OUTS7_5", - "PSS0_LOGIC_OUTS7_6", - "PSS0_LOGIC_OUTS7_7", - "PSS0_LOGIC_OUTS7_8", - "PSS0_LOGIC_OUTS7_9", - "PSS0_LOGIC_OUTS8_0", - "PSS0_LOGIC_OUTS8_1", - "PSS0_LOGIC_OUTS8_10", - "PSS0_LOGIC_OUTS8_11", - "PSS0_LOGIC_OUTS8_12", - "PSS0_LOGIC_OUTS8_13", - "PSS0_LOGIC_OUTS8_14", - "PSS0_LOGIC_OUTS8_15", - "PSS0_LOGIC_OUTS8_16", - "PSS0_LOGIC_OUTS8_17", - "PSS0_LOGIC_OUTS8_18", - "PSS0_LOGIC_OUTS8_19", - "PSS0_LOGIC_OUTS8_2", - "PSS0_LOGIC_OUTS8_3", - "PSS0_LOGIC_OUTS8_4", - "PSS0_LOGIC_OUTS8_5", - "PSS0_LOGIC_OUTS8_6", - "PSS0_LOGIC_OUTS8_7", - "PSS0_LOGIC_OUTS8_8", - "PSS0_LOGIC_OUTS8_9", - "PSS0_LOGIC_OUTS9_0", - "PSS0_LOGIC_OUTS9_1", - "PSS0_LOGIC_OUTS9_10", - "PSS0_LOGIC_OUTS9_11", - "PSS0_LOGIC_OUTS9_12", - "PSS0_LOGIC_OUTS9_13", - "PSS0_LOGIC_OUTS9_14", - "PSS0_LOGIC_OUTS9_15", - "PSS0_LOGIC_OUTS9_16", - "PSS0_LOGIC_OUTS9_17", - "PSS0_LOGIC_OUTS9_18", - "PSS0_LOGIC_OUTS9_19", - "PSS0_LOGIC_OUTS9_2", - "PSS0_LOGIC_OUTS9_3", - "PSS0_LOGIC_OUTS9_4", - "PSS0_LOGIC_OUTS9_5", - "PSS0_LOGIC_OUTS9_6", - "PSS0_LOGIC_OUTS9_7", - "PSS0_LOGIC_OUTS9_8", - "PSS0_LOGIC_OUTS9_9", - "PSS_BYP_B0_0", - "PSS_BYP_B0_1", - "PSS_BYP_B0_10", - "PSS_BYP_B0_11", - "PSS_BYP_B0_12", - "PSS_BYP_B0_13", - "PSS_BYP_B0_14", - "PSS_BYP_B0_15", - "PSS_BYP_B0_16", - "PSS_BYP_B0_17", - "PSS_BYP_B0_18", - "PSS_BYP_B0_19", - "PSS_BYP_B0_2", - "PSS_BYP_B0_3", - "PSS_BYP_B0_4", - "PSS_BYP_B0_5", - "PSS_BYP_B0_6", - "PSS_BYP_B0_7", - "PSS_BYP_B0_8", - "PSS_BYP_B0_9", - "PSS_BYP_B1_0", - "PSS_BYP_B1_1", - "PSS_BYP_B1_10", - "PSS_BYP_B1_11", - "PSS_BYP_B1_12", - "PSS_BYP_B1_13", - "PSS_BYP_B1_14", - "PSS_BYP_B1_15", - "PSS_BYP_B1_16", - "PSS_BYP_B1_17", - "PSS_BYP_B1_18", - "PSS_BYP_B1_19", - "PSS_BYP_B1_2", - "PSS_BYP_B1_3", - "PSS_BYP_B1_4", - "PSS_BYP_B1_5", - "PSS_BYP_B1_6", - "PSS_BYP_B1_7", - "PSS_BYP_B1_8", - "PSS_BYP_B1_9", - "PSS_BYP_B2_0", - "PSS_BYP_B2_1", - "PSS_BYP_B2_10", - "PSS_BYP_B2_11", - "PSS_BYP_B2_12", - "PSS_BYP_B2_13", - "PSS_BYP_B2_14", - "PSS_BYP_B2_15", - "PSS_BYP_B2_16", - "PSS_BYP_B2_17", - "PSS_BYP_B2_18", - "PSS_BYP_B2_19", - "PSS_BYP_B2_2", - "PSS_BYP_B2_3", - "PSS_BYP_B2_4", - "PSS_BYP_B2_5", - "PSS_BYP_B2_6", - "PSS_BYP_B2_7", - "PSS_BYP_B2_8", - "PSS_BYP_B2_9", - "PSS_BYP_B3_0", - "PSS_BYP_B3_1", - "PSS_BYP_B3_10", - "PSS_BYP_B3_11", - "PSS_BYP_B3_12", - "PSS_BYP_B3_13", - "PSS_BYP_B3_14", - "PSS_BYP_B3_15", - "PSS_BYP_B3_16", - "PSS_BYP_B3_17", - "PSS_BYP_B3_18", - "PSS_BYP_B3_19", - "PSS_BYP_B3_2", - "PSS_BYP_B3_3", - "PSS_BYP_B3_4", - "PSS_BYP_B3_5", - "PSS_BYP_B3_6", - "PSS_BYP_B3_7", - "PSS_BYP_B3_8", - "PSS_BYP_B3_9", - "PSS_BYP_B4_0", - "PSS_BYP_B4_1", - "PSS_BYP_B4_10", - "PSS_BYP_B4_11", - "PSS_BYP_B4_12", - "PSS_BYP_B4_13", - "PSS_BYP_B4_14", - "PSS_BYP_B4_15", - "PSS_BYP_B4_16", - "PSS_BYP_B4_17", - "PSS_BYP_B4_18", - "PSS_BYP_B4_19", - "PSS_BYP_B4_2", - "PSS_BYP_B4_3", - "PSS_BYP_B4_4", - "PSS_BYP_B4_5", - "PSS_BYP_B4_6", - "PSS_BYP_B4_7", - "PSS_BYP_B4_8", - "PSS_BYP_B4_9", - "PSS_BYP_B5_0", - "PSS_BYP_B5_1", - "PSS_BYP_B5_10", - "PSS_BYP_B5_11", - "PSS_BYP_B5_12", - "PSS_BYP_B5_13", - "PSS_BYP_B5_14", - "PSS_BYP_B5_15", - "PSS_BYP_B5_16", - "PSS_BYP_B5_17", - "PSS_BYP_B5_18", - "PSS_BYP_B5_19", - "PSS_BYP_B5_2", - "PSS_BYP_B5_3", - "PSS_BYP_B5_4", - "PSS_BYP_B5_5", - "PSS_BYP_B5_6", - "PSS_BYP_B5_7", - "PSS_BYP_B5_8", - "PSS_BYP_B5_9", - "PSS_BYP_B6_0", - "PSS_BYP_B6_1", - "PSS_BYP_B6_10", - "PSS_BYP_B6_11", - "PSS_BYP_B6_12", - "PSS_BYP_B6_13", - "PSS_BYP_B6_14", - "PSS_BYP_B6_15", - "PSS_BYP_B6_16", - "PSS_BYP_B6_17", - "PSS_BYP_B6_18", - "PSS_BYP_B6_19", - "PSS_BYP_B6_2", - "PSS_BYP_B6_3", - "PSS_BYP_B6_4", - "PSS_BYP_B6_5", - "PSS_BYP_B6_6", - "PSS_BYP_B6_7", - "PSS_BYP_B6_8", - "PSS_BYP_B6_9", - "PSS_BYP_B7_0", - "PSS_BYP_B7_1", - "PSS_BYP_B7_10", - "PSS_BYP_B7_11", - "PSS_BYP_B7_12", - "PSS_BYP_B7_13", - "PSS_BYP_B7_14", - "PSS_BYP_B7_15", - "PSS_BYP_B7_16", - "PSS_BYP_B7_17", - "PSS_BYP_B7_18", - "PSS_BYP_B7_19", - "PSS_BYP_B7_2", - "PSS_BYP_B7_3", - "PSS_BYP_B7_4", - "PSS_BYP_B7_5", - "PSS_BYP_B7_6", - "PSS_BYP_B7_7", - "PSS_BYP_B7_8", - "PSS_BYP_B7_9", - "PSS_CLK_B0_0", - "PSS_CLK_B0_1", - "PSS_CLK_B0_10", - "PSS_CLK_B0_11", - "PSS_CLK_B0_12", - "PSS_CLK_B0_13", - "PSS_CLK_B0_14", - "PSS_CLK_B0_15", - "PSS_CLK_B0_16", - "PSS_CLK_B0_17", - "PSS_CLK_B0_18", - "PSS_CLK_B0_19", - "PSS_CLK_B0_2", - "PSS_CLK_B0_3", - "PSS_CLK_B0_4", - "PSS_CLK_B0_5", - "PSS_CLK_B0_6", - "PSS_CLK_B0_7", - "PSS_CLK_B0_8", - "PSS_CLK_B0_9", - "PSS_CLK_B1_0", - "PSS_CLK_B1_1", - "PSS_CLK_B1_10", - "PSS_CLK_B1_11", - "PSS_CLK_B1_12", - "PSS_CLK_B1_13", - "PSS_CLK_B1_14", - "PSS_CLK_B1_15", - "PSS_CLK_B1_16", - "PSS_CLK_B1_17", - "PSS_CLK_B1_18", - "PSS_CLK_B1_19", - "PSS_CLK_B1_2", - "PSS_CLK_B1_3", - "PSS_CLK_B1_4", - "PSS_CLK_B1_5", - "PSS_CLK_B1_6", - "PSS_CLK_B1_7", - "PSS_CLK_B1_8", - "PSS_CLK_B1_9", - "PSS_CTRL_B0_0", - "PSS_CTRL_B0_1", - "PSS_CTRL_B0_10", - "PSS_CTRL_B0_11", - "PSS_CTRL_B0_12", - "PSS_CTRL_B0_13", - "PSS_CTRL_B0_14", - "PSS_CTRL_B0_15", - "PSS_CTRL_B0_16", - "PSS_CTRL_B0_17", - "PSS_CTRL_B0_18", - "PSS_CTRL_B0_19", - "PSS_CTRL_B0_2", - "PSS_CTRL_B0_3", - "PSS_CTRL_B0_4", - "PSS_CTRL_B0_5", - "PSS_CTRL_B0_6", - "PSS_CTRL_B0_7", - "PSS_CTRL_B0_8", - "PSS_CTRL_B0_9", - "PSS_CTRL_B1_0", - "PSS_CTRL_B1_1", - "PSS_CTRL_B1_10", - "PSS_CTRL_B1_11", - "PSS_CTRL_B1_12", - "PSS_CTRL_B1_13", - "PSS_CTRL_B1_14", - "PSS_CTRL_B1_15", - "PSS_CTRL_B1_16", - "PSS_CTRL_B1_17", - "PSS_CTRL_B1_18", - "PSS_CTRL_B1_19", - "PSS_CTRL_B1_2", - "PSS_CTRL_B1_3", - "PSS_CTRL_B1_4", - "PSS_CTRL_B1_5", - "PSS_CTRL_B1_6", - "PSS_CTRL_B1_7", - "PSS_CTRL_B1_8", - "PSS_CTRL_B1_9", - "PSS_FAN_B0_0", - "PSS_FAN_B0_1", - "PSS_FAN_B0_10", - "PSS_FAN_B0_11", - "PSS_FAN_B0_12", - "PSS_FAN_B0_13", - "PSS_FAN_B0_14", - "PSS_FAN_B0_15", - "PSS_FAN_B0_16", - "PSS_FAN_B0_17", - "PSS_FAN_B0_18", - "PSS_FAN_B0_19", - "PSS_FAN_B0_2", - "PSS_FAN_B0_3", - "PSS_FAN_B0_4", - "PSS_FAN_B0_5", - "PSS_FAN_B0_6", - "PSS_FAN_B0_7", - "PSS_FAN_B0_8", - "PSS_FAN_B0_9", - "PSS_FAN_B1_0", - "PSS_FAN_B1_1", - "PSS_FAN_B1_10", - "PSS_FAN_B1_11", - "PSS_FAN_B1_12", - "PSS_FAN_B1_13", - "PSS_FAN_B1_14", - "PSS_FAN_B1_15", - "PSS_FAN_B1_16", - "PSS_FAN_B1_17", - "PSS_FAN_B1_18", - "PSS_FAN_B1_19", - "PSS_FAN_B1_2", - "PSS_FAN_B1_3", - "PSS_FAN_B1_4", - "PSS_FAN_B1_5", - "PSS_FAN_B1_6", - "PSS_FAN_B1_7", - "PSS_FAN_B1_8", - "PSS_FAN_B1_9", - "PSS_FAN_B2_0", - "PSS_FAN_B2_1", - "PSS_FAN_B2_10", - "PSS_FAN_B2_11", - "PSS_FAN_B2_12", - "PSS_FAN_B2_13", - "PSS_FAN_B2_14", - "PSS_FAN_B2_15", - "PSS_FAN_B2_16", - "PSS_FAN_B2_17", - "PSS_FAN_B2_18", - "PSS_FAN_B2_19", - "PSS_FAN_B2_2", - "PSS_FAN_B2_3", - "PSS_FAN_B2_4", - "PSS_FAN_B2_5", - "PSS_FAN_B2_6", - "PSS_FAN_B2_7", - "PSS_FAN_B2_8", - "PSS_FAN_B2_9", - "PSS_FAN_B3_0", - "PSS_FAN_B3_1", - "PSS_FAN_B3_10", - "PSS_FAN_B3_11", - "PSS_FAN_B3_12", - "PSS_FAN_B3_13", - "PSS_FAN_B3_14", - "PSS_FAN_B3_15", - "PSS_FAN_B3_16", - "PSS_FAN_B3_17", - "PSS_FAN_B3_18", - "PSS_FAN_B3_19", - "PSS_FAN_B3_2", - "PSS_FAN_B3_3", - "PSS_FAN_B3_4", - "PSS_FAN_B3_5", - "PSS_FAN_B3_6", - "PSS_FAN_B3_7", - "PSS_FAN_B3_8", - "PSS_FAN_B3_9", - "PSS_FAN_B4_0", - "PSS_FAN_B4_1", - "PSS_FAN_B4_10", - "PSS_FAN_B4_11", - "PSS_FAN_B4_12", - "PSS_FAN_B4_13", - "PSS_FAN_B4_14", - "PSS_FAN_B4_15", - "PSS_FAN_B4_16", - "PSS_FAN_B4_17", - "PSS_FAN_B4_18", - "PSS_FAN_B4_19", - "PSS_FAN_B4_2", - "PSS_FAN_B4_3", - "PSS_FAN_B4_4", - "PSS_FAN_B4_5", - "PSS_FAN_B4_6", - "PSS_FAN_B4_7", - "PSS_FAN_B4_8", - "PSS_FAN_B4_9", - "PSS_FAN_B5_0", - "PSS_FAN_B5_1", - "PSS_FAN_B5_10", - "PSS_FAN_B5_11", - "PSS_FAN_B5_12", - "PSS_FAN_B5_13", - "PSS_FAN_B5_14", - "PSS_FAN_B5_15", - "PSS_FAN_B5_16", - "PSS_FAN_B5_17", - "PSS_FAN_B5_18", - "PSS_FAN_B5_19", - "PSS_FAN_B5_2", - "PSS_FAN_B5_3", - "PSS_FAN_B5_4", - "PSS_FAN_B5_5", - "PSS_FAN_B5_6", - "PSS_FAN_B5_7", - "PSS_FAN_B5_8", - "PSS_FAN_B5_9", - "PSS_FAN_B6_0", - "PSS_FAN_B6_1", - "PSS_FAN_B6_10", - "PSS_FAN_B6_11", - "PSS_FAN_B6_12", - "PSS_FAN_B6_13", - "PSS_FAN_B6_14", - "PSS_FAN_B6_15", - "PSS_FAN_B6_16", - "PSS_FAN_B6_17", - "PSS_FAN_B6_18", - "PSS_FAN_B6_19", - "PSS_FAN_B6_2", - "PSS_FAN_B6_3", - "PSS_FAN_B6_4", - "PSS_FAN_B6_5", - "PSS_FAN_B6_6", - "PSS_FAN_B6_7", - "PSS_FAN_B6_8", - "PSS_FAN_B6_9", - "PSS_FAN_B7_0", - "PSS_FAN_B7_1", - "PSS_FAN_B7_10", - "PSS_FAN_B7_11", - "PSS_FAN_B7_12", - "PSS_FAN_B7_13", - "PSS_FAN_B7_14", - "PSS_FAN_B7_15", - "PSS_FAN_B7_16", - "PSS_FAN_B7_17", - "PSS_FAN_B7_18", - "PSS_FAN_B7_19", - "PSS_FAN_B7_2", - "PSS_FAN_B7_3", - "PSS_FAN_B7_4", - "PSS_FAN_B7_5", - "PSS_FAN_B7_6", - "PSS_FAN_B7_7", - "PSS_FAN_B7_8", - "PSS_FAN_B7_9", - "PSS_IMUX_B0_0", - "PSS_IMUX_B0_1", - "PSS_IMUX_B0_10", - "PSS_IMUX_B0_11", - "PSS_IMUX_B0_12", - "PSS_IMUX_B0_13", - "PSS_IMUX_B0_14", - "PSS_IMUX_B0_15", - "PSS_IMUX_B0_16", - "PSS_IMUX_B0_17", - "PSS_IMUX_B0_18", - "PSS_IMUX_B0_19", - "PSS_IMUX_B0_2", - "PSS_IMUX_B0_3", - "PSS_IMUX_B0_4", - "PSS_IMUX_B0_5", - "PSS_IMUX_B0_6", - "PSS_IMUX_B0_7", - "PSS_IMUX_B0_8", - "PSS_IMUX_B0_9", - "PSS_IMUX_B10_0", - "PSS_IMUX_B10_1", - "PSS_IMUX_B10_10", - "PSS_IMUX_B10_11", - "PSS_IMUX_B10_12", - "PSS_IMUX_B10_13", - "PSS_IMUX_B10_14", - "PSS_IMUX_B10_15", - "PSS_IMUX_B10_16", - "PSS_IMUX_B10_17", - "PSS_IMUX_B10_18", - "PSS_IMUX_B10_19", - "PSS_IMUX_B10_2", - "PSS_IMUX_B10_3", - "PSS_IMUX_B10_4", - "PSS_IMUX_B10_5", - "PSS_IMUX_B10_6", - "PSS_IMUX_B10_7", - "PSS_IMUX_B10_8", - "PSS_IMUX_B10_9", - "PSS_IMUX_B11_0", - "PSS_IMUX_B11_1", - "PSS_IMUX_B11_10", - "PSS_IMUX_B11_11", - "PSS_IMUX_B11_12", - "PSS_IMUX_B11_13", - "PSS_IMUX_B11_14", - "PSS_IMUX_B11_15", - "PSS_IMUX_B11_16", - "PSS_IMUX_B11_17", - "PSS_IMUX_B11_18", - "PSS_IMUX_B11_19", - "PSS_IMUX_B11_2", - "PSS_IMUX_B11_3", - "PSS_IMUX_B11_4", - "PSS_IMUX_B11_5", - "PSS_IMUX_B11_6", - "PSS_IMUX_B11_7", - "PSS_IMUX_B11_8", - "PSS_IMUX_B11_9", - "PSS_IMUX_B12_0", - "PSS_IMUX_B12_1", - "PSS_IMUX_B12_10", - "PSS_IMUX_B12_11", - "PSS_IMUX_B12_12", - "PSS_IMUX_B12_13", - "PSS_IMUX_B12_14", - "PSS_IMUX_B12_15", - "PSS_IMUX_B12_16", - "PSS_IMUX_B12_17", - "PSS_IMUX_B12_18", - "PSS_IMUX_B12_19", - "PSS_IMUX_B12_2", - "PSS_IMUX_B12_3", - "PSS_IMUX_B12_4", - "PSS_IMUX_B12_5", - "PSS_IMUX_B12_6", - "PSS_IMUX_B12_7", - "PSS_IMUX_B12_8", - "PSS_IMUX_B12_9", - "PSS_IMUX_B13_0", - "PSS_IMUX_B13_1", - "PSS_IMUX_B13_10", - "PSS_IMUX_B13_11", - "PSS_IMUX_B13_12", - "PSS_IMUX_B13_13", - "PSS_IMUX_B13_14", - "PSS_IMUX_B13_15", - "PSS_IMUX_B13_16", - "PSS_IMUX_B13_17", - "PSS_IMUX_B13_18", - "PSS_IMUX_B13_19", - "PSS_IMUX_B13_2", - "PSS_IMUX_B13_3", - "PSS_IMUX_B13_4", - "PSS_IMUX_B13_5", - "PSS_IMUX_B13_6", - "PSS_IMUX_B13_7", - "PSS_IMUX_B13_8", - "PSS_IMUX_B13_9", - "PSS_IMUX_B14_0", - "PSS_IMUX_B14_1", - "PSS_IMUX_B14_10", - "PSS_IMUX_B14_11", - "PSS_IMUX_B14_12", - "PSS_IMUX_B14_13", - "PSS_IMUX_B14_14", - "PSS_IMUX_B14_15", - "PSS_IMUX_B14_16", - "PSS_IMUX_B14_17", - "PSS_IMUX_B14_18", - "PSS_IMUX_B14_19", - "PSS_IMUX_B14_2", - "PSS_IMUX_B14_3", - "PSS_IMUX_B14_4", - "PSS_IMUX_B14_5", - "PSS_IMUX_B14_6", - "PSS_IMUX_B14_7", - "PSS_IMUX_B14_8", - "PSS_IMUX_B14_9", - "PSS_IMUX_B15_0", - "PSS_IMUX_B15_1", - "PSS_IMUX_B15_10", - "PSS_IMUX_B15_11", - "PSS_IMUX_B15_12", - "PSS_IMUX_B15_13", - "PSS_IMUX_B15_14", - "PSS_IMUX_B15_15", - "PSS_IMUX_B15_16", - "PSS_IMUX_B15_17", - "PSS_IMUX_B15_18", - "PSS_IMUX_B15_19", - "PSS_IMUX_B15_2", - "PSS_IMUX_B15_3", - "PSS_IMUX_B15_4", - "PSS_IMUX_B15_5", - "PSS_IMUX_B15_6", - "PSS_IMUX_B15_7", - "PSS_IMUX_B15_8", - "PSS_IMUX_B15_9", - "PSS_IMUX_B16_0", - "PSS_IMUX_B16_1", - "PSS_IMUX_B16_10", - "PSS_IMUX_B16_11", - "PSS_IMUX_B16_12", - "PSS_IMUX_B16_13", - "PSS_IMUX_B16_14", - "PSS_IMUX_B16_15", - "PSS_IMUX_B16_16", - "PSS_IMUX_B16_17", - "PSS_IMUX_B16_18", - "PSS_IMUX_B16_19", - "PSS_IMUX_B16_2", - "PSS_IMUX_B16_3", - "PSS_IMUX_B16_4", - "PSS_IMUX_B16_5", - "PSS_IMUX_B16_6", - "PSS_IMUX_B16_7", - "PSS_IMUX_B16_8", - "PSS_IMUX_B16_9", - "PSS_IMUX_B17_0", - "PSS_IMUX_B17_1", - "PSS_IMUX_B17_10", - "PSS_IMUX_B17_11", - "PSS_IMUX_B17_12", - "PSS_IMUX_B17_13", - "PSS_IMUX_B17_14", - "PSS_IMUX_B17_15", - "PSS_IMUX_B17_16", - "PSS_IMUX_B17_17", - "PSS_IMUX_B17_18", - "PSS_IMUX_B17_19", - "PSS_IMUX_B17_2", - "PSS_IMUX_B17_3", - "PSS_IMUX_B17_4", - "PSS_IMUX_B17_5", - "PSS_IMUX_B17_6", - "PSS_IMUX_B17_7", - "PSS_IMUX_B17_8", - "PSS_IMUX_B17_9", - "PSS_IMUX_B18_0", - "PSS_IMUX_B18_1", - "PSS_IMUX_B18_10", - "PSS_IMUX_B18_11", - "PSS_IMUX_B18_12", - "PSS_IMUX_B18_13", - "PSS_IMUX_B18_14", - "PSS_IMUX_B18_15", - "PSS_IMUX_B18_16", - "PSS_IMUX_B18_17", - "PSS_IMUX_B18_18", - "PSS_IMUX_B18_19", - "PSS_IMUX_B18_2", - "PSS_IMUX_B18_3", - "PSS_IMUX_B18_4", - "PSS_IMUX_B18_5", - "PSS_IMUX_B18_6", - "PSS_IMUX_B18_7", - "PSS_IMUX_B18_8", - "PSS_IMUX_B18_9", - "PSS_IMUX_B19_0", - "PSS_IMUX_B19_1", - "PSS_IMUX_B19_10", - "PSS_IMUX_B19_11", - "PSS_IMUX_B19_12", - "PSS_IMUX_B19_13", - "PSS_IMUX_B19_14", - "PSS_IMUX_B19_15", - "PSS_IMUX_B19_16", - "PSS_IMUX_B19_17", - "PSS_IMUX_B19_18", - "PSS_IMUX_B19_19", - "PSS_IMUX_B19_2", - "PSS_IMUX_B19_3", - "PSS_IMUX_B19_4", - "PSS_IMUX_B19_5", - "PSS_IMUX_B19_6", - "PSS_IMUX_B19_7", - "PSS_IMUX_B19_8", - "PSS_IMUX_B19_9", - "PSS_IMUX_B1_0", - "PSS_IMUX_B1_1", - "PSS_IMUX_B1_10", - "PSS_IMUX_B1_11", - "PSS_IMUX_B1_12", - "PSS_IMUX_B1_13", - "PSS_IMUX_B1_14", - "PSS_IMUX_B1_15", - "PSS_IMUX_B1_16", - "PSS_IMUX_B1_17", - "PSS_IMUX_B1_18", - "PSS_IMUX_B1_19", - "PSS_IMUX_B1_2", - "PSS_IMUX_B1_3", - "PSS_IMUX_B1_4", - "PSS_IMUX_B1_5", - "PSS_IMUX_B1_6", - "PSS_IMUX_B1_7", - "PSS_IMUX_B1_8", - "PSS_IMUX_B1_9", - "PSS_IMUX_B20_0", - "PSS_IMUX_B20_1", - "PSS_IMUX_B20_10", - "PSS_IMUX_B20_11", - "PSS_IMUX_B20_12", - "PSS_IMUX_B20_13", - "PSS_IMUX_B20_14", - "PSS_IMUX_B20_15", - "PSS_IMUX_B20_16", - "PSS_IMUX_B20_17", - "PSS_IMUX_B20_18", - "PSS_IMUX_B20_19", - "PSS_IMUX_B20_2", - "PSS_IMUX_B20_3", - "PSS_IMUX_B20_4", - "PSS_IMUX_B20_5", - "PSS_IMUX_B20_6", - "PSS_IMUX_B20_7", - "PSS_IMUX_B20_8", - "PSS_IMUX_B20_9", - "PSS_IMUX_B21_0", - "PSS_IMUX_B21_1", - "PSS_IMUX_B21_10", - "PSS_IMUX_B21_11", - "PSS_IMUX_B21_12", - "PSS_IMUX_B21_13", - "PSS_IMUX_B21_14", - "PSS_IMUX_B21_15", - "PSS_IMUX_B21_16", - "PSS_IMUX_B21_17", - "PSS_IMUX_B21_18", - "PSS_IMUX_B21_19", - "PSS_IMUX_B21_2", - "PSS_IMUX_B21_3", - "PSS_IMUX_B21_4", - "PSS_IMUX_B21_5", - "PSS_IMUX_B21_6", - "PSS_IMUX_B21_7", - "PSS_IMUX_B21_8", - "PSS_IMUX_B21_9", - "PSS_IMUX_B22_0", - "PSS_IMUX_B22_1", - "PSS_IMUX_B22_10", - "PSS_IMUX_B22_11", - "PSS_IMUX_B22_12", - "PSS_IMUX_B22_13", - "PSS_IMUX_B22_14", - "PSS_IMUX_B22_15", - "PSS_IMUX_B22_16", - "PSS_IMUX_B22_17", - "PSS_IMUX_B22_18", - "PSS_IMUX_B22_19", - "PSS_IMUX_B22_2", - "PSS_IMUX_B22_3", - "PSS_IMUX_B22_4", - "PSS_IMUX_B22_5", - "PSS_IMUX_B22_6", - "PSS_IMUX_B22_7", - "PSS_IMUX_B22_8", - "PSS_IMUX_B22_9", - "PSS_IMUX_B23_0", - "PSS_IMUX_B23_1", - "PSS_IMUX_B23_10", - "PSS_IMUX_B23_11", - "PSS_IMUX_B23_12", - "PSS_IMUX_B23_13", - "PSS_IMUX_B23_14", - "PSS_IMUX_B23_15", - "PSS_IMUX_B23_16", - "PSS_IMUX_B23_17", - "PSS_IMUX_B23_18", - "PSS_IMUX_B23_19", - "PSS_IMUX_B23_2", - "PSS_IMUX_B23_3", - "PSS_IMUX_B23_4", - "PSS_IMUX_B23_5", - "PSS_IMUX_B23_6", - "PSS_IMUX_B23_7", - "PSS_IMUX_B23_8", - "PSS_IMUX_B23_9", - "PSS_IMUX_B24_0", - "PSS_IMUX_B24_1", - "PSS_IMUX_B24_10", - "PSS_IMUX_B24_11", - "PSS_IMUX_B24_12", - "PSS_IMUX_B24_13", - "PSS_IMUX_B24_14", - "PSS_IMUX_B24_15", - "PSS_IMUX_B24_16", - "PSS_IMUX_B24_17", - "PSS_IMUX_B24_18", - "PSS_IMUX_B24_19", - "PSS_IMUX_B24_2", - "PSS_IMUX_B24_3", - "PSS_IMUX_B24_4", - "PSS_IMUX_B24_5", - "PSS_IMUX_B24_6", - "PSS_IMUX_B24_7", - "PSS_IMUX_B24_8", - "PSS_IMUX_B24_9", - "PSS_IMUX_B25_0", - "PSS_IMUX_B25_1", - "PSS_IMUX_B25_10", - "PSS_IMUX_B25_11", - "PSS_IMUX_B25_12", - "PSS_IMUX_B25_13", - "PSS_IMUX_B25_14", - "PSS_IMUX_B25_15", - "PSS_IMUX_B25_16", - "PSS_IMUX_B25_17", - "PSS_IMUX_B25_18", - "PSS_IMUX_B25_19", - "PSS_IMUX_B25_2", - "PSS_IMUX_B25_3", - "PSS_IMUX_B25_4", - "PSS_IMUX_B25_5", - "PSS_IMUX_B25_6", - "PSS_IMUX_B25_7", - "PSS_IMUX_B25_8", - "PSS_IMUX_B25_9", - "PSS_IMUX_B26_0", - "PSS_IMUX_B26_1", - "PSS_IMUX_B26_10", - "PSS_IMUX_B26_11", - "PSS_IMUX_B26_12", - "PSS_IMUX_B26_13", - "PSS_IMUX_B26_14", - "PSS_IMUX_B26_15", - "PSS_IMUX_B26_16", - "PSS_IMUX_B26_17", - "PSS_IMUX_B26_18", - "PSS_IMUX_B26_19", - "PSS_IMUX_B26_2", - "PSS_IMUX_B26_3", - "PSS_IMUX_B26_4", - "PSS_IMUX_B26_5", - "PSS_IMUX_B26_6", - "PSS_IMUX_B26_7", - "PSS_IMUX_B26_8", - "PSS_IMUX_B26_9", - "PSS_IMUX_B27_0", - "PSS_IMUX_B27_1", - "PSS_IMUX_B27_10", - "PSS_IMUX_B27_11", - "PSS_IMUX_B27_12", - "PSS_IMUX_B27_13", - "PSS_IMUX_B27_14", - "PSS_IMUX_B27_15", - "PSS_IMUX_B27_16", - "PSS_IMUX_B27_17", - "PSS_IMUX_B27_18", - "PSS_IMUX_B27_19", - "PSS_IMUX_B27_2", - "PSS_IMUX_B27_3", - "PSS_IMUX_B27_4", - "PSS_IMUX_B27_5", - "PSS_IMUX_B27_6", - "PSS_IMUX_B27_7", - "PSS_IMUX_B27_8", - "PSS_IMUX_B27_9", - "PSS_IMUX_B28_0", - "PSS_IMUX_B28_1", - "PSS_IMUX_B28_10", - "PSS_IMUX_B28_11", - "PSS_IMUX_B28_12", - "PSS_IMUX_B28_13", - "PSS_IMUX_B28_14", - "PSS_IMUX_B28_15", - "PSS_IMUX_B28_16", - "PSS_IMUX_B28_17", - "PSS_IMUX_B28_18", - "PSS_IMUX_B28_19", - "PSS_IMUX_B28_2", - "PSS_IMUX_B28_3", - "PSS_IMUX_B28_4", - "PSS_IMUX_B28_5", - "PSS_IMUX_B28_6", - "PSS_IMUX_B28_7", - "PSS_IMUX_B28_8", - "PSS_IMUX_B28_9", - "PSS_IMUX_B29_0", - "PSS_IMUX_B29_1", - "PSS_IMUX_B29_10", - "PSS_IMUX_B29_11", - "PSS_IMUX_B29_12", - "PSS_IMUX_B29_13", - "PSS_IMUX_B29_14", - "PSS_IMUX_B29_15", - "PSS_IMUX_B29_16", - "PSS_IMUX_B29_17", - "PSS_IMUX_B29_18", - "PSS_IMUX_B29_19", - "PSS_IMUX_B29_2", - "PSS_IMUX_B29_3", - "PSS_IMUX_B29_4", - "PSS_IMUX_B29_5", - "PSS_IMUX_B29_6", - "PSS_IMUX_B29_7", - "PSS_IMUX_B29_8", - "PSS_IMUX_B29_9", - "PSS_IMUX_B2_0", - "PSS_IMUX_B2_1", - "PSS_IMUX_B2_10", - "PSS_IMUX_B2_11", - "PSS_IMUX_B2_12", - "PSS_IMUX_B2_13", - "PSS_IMUX_B2_14", - "PSS_IMUX_B2_15", - "PSS_IMUX_B2_16", - "PSS_IMUX_B2_17", - "PSS_IMUX_B2_18", - "PSS_IMUX_B2_19", - "PSS_IMUX_B2_2", - "PSS_IMUX_B2_3", - "PSS_IMUX_B2_4", - "PSS_IMUX_B2_5", - "PSS_IMUX_B2_6", - "PSS_IMUX_B2_7", - "PSS_IMUX_B2_8", - "PSS_IMUX_B2_9", - "PSS_IMUX_B30_0", - "PSS_IMUX_B30_1", - "PSS_IMUX_B30_10", - "PSS_IMUX_B30_11", - "PSS_IMUX_B30_12", - "PSS_IMUX_B30_13", - "PSS_IMUX_B30_14", - "PSS_IMUX_B30_15", - "PSS_IMUX_B30_16", - "PSS_IMUX_B30_17", - "PSS_IMUX_B30_18", - "PSS_IMUX_B30_19", - "PSS_IMUX_B30_2", - "PSS_IMUX_B30_3", - "PSS_IMUX_B30_4", - "PSS_IMUX_B30_5", - "PSS_IMUX_B30_6", - "PSS_IMUX_B30_7", - "PSS_IMUX_B30_8", - "PSS_IMUX_B30_9", - "PSS_IMUX_B31_0", - "PSS_IMUX_B31_1", - "PSS_IMUX_B31_10", - "PSS_IMUX_B31_11", - "PSS_IMUX_B31_12", - "PSS_IMUX_B31_13", - "PSS_IMUX_B31_14", - "PSS_IMUX_B31_15", - "PSS_IMUX_B31_16", - "PSS_IMUX_B31_17", - "PSS_IMUX_B31_18", - "PSS_IMUX_B31_19", - "PSS_IMUX_B31_2", - "PSS_IMUX_B31_3", - "PSS_IMUX_B31_4", - "PSS_IMUX_B31_5", - "PSS_IMUX_B31_6", - "PSS_IMUX_B31_7", - "PSS_IMUX_B31_8", - "PSS_IMUX_B31_9", - "PSS_IMUX_B32_0", - "PSS_IMUX_B32_1", - "PSS_IMUX_B32_10", - "PSS_IMUX_B32_11", - "PSS_IMUX_B32_12", - "PSS_IMUX_B32_13", - "PSS_IMUX_B32_14", - "PSS_IMUX_B32_15", - "PSS_IMUX_B32_16", - "PSS_IMUX_B32_17", - "PSS_IMUX_B32_18", - "PSS_IMUX_B32_19", - "PSS_IMUX_B32_2", - "PSS_IMUX_B32_3", - "PSS_IMUX_B32_4", - "PSS_IMUX_B32_5", - "PSS_IMUX_B32_6", - "PSS_IMUX_B32_7", - "PSS_IMUX_B32_8", - "PSS_IMUX_B32_9", - "PSS_IMUX_B33_0", - "PSS_IMUX_B33_1", - "PSS_IMUX_B33_10", - "PSS_IMUX_B33_11", - "PSS_IMUX_B33_12", - "PSS_IMUX_B33_13", - "PSS_IMUX_B33_14", - "PSS_IMUX_B33_15", - "PSS_IMUX_B33_16", - "PSS_IMUX_B33_17", - "PSS_IMUX_B33_18", - "PSS_IMUX_B33_19", - "PSS_IMUX_B33_2", - "PSS_IMUX_B33_3", - "PSS_IMUX_B33_4", - "PSS_IMUX_B33_5", - "PSS_IMUX_B33_6", - "PSS_IMUX_B33_7", - "PSS_IMUX_B33_8", - "PSS_IMUX_B33_9", - "PSS_IMUX_B34_0", - "PSS_IMUX_B34_1", - "PSS_IMUX_B34_10", - "PSS_IMUX_B34_11", - "PSS_IMUX_B34_12", - "PSS_IMUX_B34_13", - "PSS_IMUX_B34_14", - "PSS_IMUX_B34_15", - "PSS_IMUX_B34_16", - "PSS_IMUX_B34_17", - "PSS_IMUX_B34_18", - "PSS_IMUX_B34_19", - "PSS_IMUX_B34_2", - "PSS_IMUX_B34_3", - "PSS_IMUX_B34_4", - "PSS_IMUX_B34_5", - "PSS_IMUX_B34_6", - "PSS_IMUX_B34_7", - "PSS_IMUX_B34_8", - "PSS_IMUX_B34_9", - "PSS_IMUX_B35_0", - "PSS_IMUX_B35_1", - "PSS_IMUX_B35_10", - "PSS_IMUX_B35_11", - "PSS_IMUX_B35_12", - "PSS_IMUX_B35_13", - "PSS_IMUX_B35_14", - "PSS_IMUX_B35_15", - "PSS_IMUX_B35_16", - "PSS_IMUX_B35_17", - "PSS_IMUX_B35_18", - "PSS_IMUX_B35_19", - "PSS_IMUX_B35_2", - "PSS_IMUX_B35_3", - "PSS_IMUX_B35_4", - "PSS_IMUX_B35_5", - "PSS_IMUX_B35_6", - "PSS_IMUX_B35_7", - "PSS_IMUX_B35_8", - "PSS_IMUX_B35_9", - "PSS_IMUX_B36_0", - "PSS_IMUX_B36_1", - "PSS_IMUX_B36_10", - "PSS_IMUX_B36_11", - "PSS_IMUX_B36_12", - "PSS_IMUX_B36_13", - "PSS_IMUX_B36_14", - "PSS_IMUX_B36_15", - "PSS_IMUX_B36_16", - "PSS_IMUX_B36_17", - "PSS_IMUX_B36_18", - "PSS_IMUX_B36_19", - "PSS_IMUX_B36_2", - "PSS_IMUX_B36_3", - "PSS_IMUX_B36_4", - "PSS_IMUX_B36_5", - "PSS_IMUX_B36_6", - "PSS_IMUX_B36_7", - "PSS_IMUX_B36_8", - "PSS_IMUX_B36_9", - "PSS_IMUX_B37_0", - "PSS_IMUX_B37_1", - "PSS_IMUX_B37_10", - "PSS_IMUX_B37_11", - "PSS_IMUX_B37_12", - "PSS_IMUX_B37_13", - "PSS_IMUX_B37_14", - "PSS_IMUX_B37_15", - "PSS_IMUX_B37_16", - "PSS_IMUX_B37_17", - "PSS_IMUX_B37_18", - "PSS_IMUX_B37_19", - "PSS_IMUX_B37_2", - "PSS_IMUX_B37_3", - "PSS_IMUX_B37_4", - "PSS_IMUX_B37_5", - "PSS_IMUX_B37_6", - "PSS_IMUX_B37_7", - "PSS_IMUX_B37_8", - "PSS_IMUX_B37_9", - "PSS_IMUX_B38_0", - "PSS_IMUX_B38_1", - "PSS_IMUX_B38_10", - "PSS_IMUX_B38_11", - "PSS_IMUX_B38_12", - "PSS_IMUX_B38_13", - "PSS_IMUX_B38_14", - "PSS_IMUX_B38_15", - "PSS_IMUX_B38_16", - "PSS_IMUX_B38_17", - "PSS_IMUX_B38_18", - "PSS_IMUX_B38_19", - "PSS_IMUX_B38_2", - "PSS_IMUX_B38_3", - "PSS_IMUX_B38_4", - "PSS_IMUX_B38_5", - "PSS_IMUX_B38_6", - "PSS_IMUX_B38_7", - "PSS_IMUX_B38_8", - "PSS_IMUX_B38_9", - "PSS_IMUX_B39_0", - "PSS_IMUX_B39_1", - "PSS_IMUX_B39_10", - "PSS_IMUX_B39_11", - "PSS_IMUX_B39_12", - "PSS_IMUX_B39_13", - "PSS_IMUX_B39_14", - "PSS_IMUX_B39_15", - "PSS_IMUX_B39_16", - "PSS_IMUX_B39_17", - "PSS_IMUX_B39_18", - "PSS_IMUX_B39_19", - "PSS_IMUX_B39_2", - "PSS_IMUX_B39_3", - "PSS_IMUX_B39_4", - "PSS_IMUX_B39_5", - "PSS_IMUX_B39_6", - "PSS_IMUX_B39_7", - "PSS_IMUX_B39_8", - "PSS_IMUX_B39_9", - "PSS_IMUX_B3_0", - "PSS_IMUX_B3_1", - "PSS_IMUX_B3_10", - "PSS_IMUX_B3_11", - "PSS_IMUX_B3_12", - "PSS_IMUX_B3_13", - "PSS_IMUX_B3_14", - "PSS_IMUX_B3_15", - "PSS_IMUX_B3_16", - "PSS_IMUX_B3_17", - "PSS_IMUX_B3_18", - "PSS_IMUX_B3_19", - "PSS_IMUX_B3_2", - "PSS_IMUX_B3_3", - "PSS_IMUX_B3_4", - "PSS_IMUX_B3_5", - "PSS_IMUX_B3_6", - "PSS_IMUX_B3_7", - "PSS_IMUX_B3_8", - "PSS_IMUX_B3_9", - "PSS_IMUX_B40_0", - "PSS_IMUX_B40_1", - "PSS_IMUX_B40_10", - "PSS_IMUX_B40_11", - "PSS_IMUX_B40_12", - "PSS_IMUX_B40_13", - "PSS_IMUX_B40_14", - "PSS_IMUX_B40_15", - "PSS_IMUX_B40_16", - "PSS_IMUX_B40_17", - "PSS_IMUX_B40_18", - "PSS_IMUX_B40_19", - "PSS_IMUX_B40_2", - "PSS_IMUX_B40_3", - "PSS_IMUX_B40_4", - "PSS_IMUX_B40_5", - "PSS_IMUX_B40_6", - "PSS_IMUX_B40_7", - "PSS_IMUX_B40_8", - "PSS_IMUX_B40_9", - "PSS_IMUX_B41_0", - "PSS_IMUX_B41_1", - "PSS_IMUX_B41_10", - "PSS_IMUX_B41_11", - "PSS_IMUX_B41_12", - "PSS_IMUX_B41_13", - "PSS_IMUX_B41_14", - "PSS_IMUX_B41_15", - "PSS_IMUX_B41_16", - "PSS_IMUX_B41_17", - "PSS_IMUX_B41_18", - "PSS_IMUX_B41_19", - "PSS_IMUX_B41_2", - "PSS_IMUX_B41_3", - "PSS_IMUX_B41_4", - "PSS_IMUX_B41_5", - "PSS_IMUX_B41_6", - "PSS_IMUX_B41_7", - "PSS_IMUX_B41_8", - "PSS_IMUX_B41_9", - "PSS_IMUX_B42_0", - "PSS_IMUX_B42_1", - "PSS_IMUX_B42_10", - "PSS_IMUX_B42_11", - "PSS_IMUX_B42_12", - "PSS_IMUX_B42_13", - "PSS_IMUX_B42_14", - "PSS_IMUX_B42_15", - "PSS_IMUX_B42_16", - "PSS_IMUX_B42_17", - "PSS_IMUX_B42_18", - "PSS_IMUX_B42_19", - "PSS_IMUX_B42_2", - "PSS_IMUX_B42_3", - "PSS_IMUX_B42_4", - "PSS_IMUX_B42_5", - "PSS_IMUX_B42_6", - "PSS_IMUX_B42_7", - "PSS_IMUX_B42_8", - "PSS_IMUX_B42_9", - "PSS_IMUX_B43_0", - "PSS_IMUX_B43_1", - "PSS_IMUX_B43_10", - "PSS_IMUX_B43_11", - "PSS_IMUX_B43_12", - "PSS_IMUX_B43_13", - "PSS_IMUX_B43_14", - "PSS_IMUX_B43_15", - "PSS_IMUX_B43_16", - "PSS_IMUX_B43_17", - "PSS_IMUX_B43_18", - "PSS_IMUX_B43_19", - "PSS_IMUX_B43_2", - "PSS_IMUX_B43_3", - "PSS_IMUX_B43_4", - "PSS_IMUX_B43_5", - "PSS_IMUX_B43_6", - "PSS_IMUX_B43_7", - "PSS_IMUX_B43_8", - "PSS_IMUX_B43_9", - "PSS_IMUX_B44_0", - "PSS_IMUX_B44_1", - "PSS_IMUX_B44_10", - "PSS_IMUX_B44_11", - "PSS_IMUX_B44_12", - "PSS_IMUX_B44_13", - "PSS_IMUX_B44_14", - "PSS_IMUX_B44_15", - "PSS_IMUX_B44_16", - "PSS_IMUX_B44_17", - "PSS_IMUX_B44_18", - "PSS_IMUX_B44_19", - "PSS_IMUX_B44_2", - "PSS_IMUX_B44_3", - "PSS_IMUX_B44_4", - "PSS_IMUX_B44_5", - "PSS_IMUX_B44_6", - "PSS_IMUX_B44_7", - "PSS_IMUX_B44_8", - "PSS_IMUX_B44_9", - "PSS_IMUX_B45_0", - "PSS_IMUX_B45_1", - "PSS_IMUX_B45_10", - "PSS_IMUX_B45_11", - "PSS_IMUX_B45_12", - "PSS_IMUX_B45_13", - "PSS_IMUX_B45_14", - "PSS_IMUX_B45_15", - "PSS_IMUX_B45_16", - "PSS_IMUX_B45_17", - "PSS_IMUX_B45_18", - "PSS_IMUX_B45_19", - "PSS_IMUX_B45_2", - "PSS_IMUX_B45_3", - "PSS_IMUX_B45_4", - "PSS_IMUX_B45_5", - "PSS_IMUX_B45_6", - "PSS_IMUX_B45_7", - "PSS_IMUX_B45_8", - "PSS_IMUX_B45_9", - "PSS_IMUX_B46_0", - "PSS_IMUX_B46_1", - "PSS_IMUX_B46_10", - "PSS_IMUX_B46_11", - "PSS_IMUX_B46_12", - "PSS_IMUX_B46_13", - "PSS_IMUX_B46_14", - "PSS_IMUX_B46_15", - "PSS_IMUX_B46_16", - "PSS_IMUX_B46_17", - "PSS_IMUX_B46_18", - "PSS_IMUX_B46_19", - "PSS_IMUX_B46_2", - "PSS_IMUX_B46_3", - "PSS_IMUX_B46_4", - "PSS_IMUX_B46_5", - "PSS_IMUX_B46_6", - "PSS_IMUX_B46_7", - "PSS_IMUX_B46_8", - "PSS_IMUX_B46_9", - "PSS_IMUX_B47_0", - "PSS_IMUX_B47_1", - "PSS_IMUX_B47_10", - "PSS_IMUX_B47_11", - "PSS_IMUX_B47_12", - "PSS_IMUX_B47_13", - "PSS_IMUX_B47_14", - "PSS_IMUX_B47_15", - "PSS_IMUX_B47_16", - "PSS_IMUX_B47_17", - "PSS_IMUX_B47_18", - "PSS_IMUX_B47_19", - "PSS_IMUX_B47_2", - "PSS_IMUX_B47_3", - "PSS_IMUX_B47_4", - "PSS_IMUX_B47_5", - "PSS_IMUX_B47_6", - "PSS_IMUX_B47_7", - "PSS_IMUX_B47_8", - "PSS_IMUX_B47_9", - "PSS_IMUX_B4_0", - "PSS_IMUX_B4_1", - "PSS_IMUX_B4_10", - "PSS_IMUX_B4_11", - "PSS_IMUX_B4_12", - "PSS_IMUX_B4_13", - "PSS_IMUX_B4_14", - "PSS_IMUX_B4_15", - "PSS_IMUX_B4_16", - "PSS_IMUX_B4_17", - "PSS_IMUX_B4_18", - "PSS_IMUX_B4_19", - "PSS_IMUX_B4_2", - "PSS_IMUX_B4_3", - "PSS_IMUX_B4_4", - "PSS_IMUX_B4_5", - "PSS_IMUX_B4_6", - "PSS_IMUX_B4_7", - "PSS_IMUX_B4_8", - "PSS_IMUX_B4_9", - "PSS_IMUX_B5_0", - "PSS_IMUX_B5_1", - "PSS_IMUX_B5_10", - "PSS_IMUX_B5_11", - "PSS_IMUX_B5_12", - "PSS_IMUX_B5_13", - "PSS_IMUX_B5_14", - "PSS_IMUX_B5_15", - "PSS_IMUX_B5_16", - "PSS_IMUX_B5_17", - "PSS_IMUX_B5_18", - "PSS_IMUX_B5_19", - "PSS_IMUX_B5_2", - "PSS_IMUX_B5_3", - "PSS_IMUX_B5_4", - "PSS_IMUX_B5_5", - "PSS_IMUX_B5_6", - "PSS_IMUX_B5_7", - "PSS_IMUX_B5_8", - "PSS_IMUX_B5_9", - "PSS_IMUX_B6_0", - "PSS_IMUX_B6_1", - "PSS_IMUX_B6_10", - "PSS_IMUX_B6_11", - "PSS_IMUX_B6_12", - "PSS_IMUX_B6_13", - "PSS_IMUX_B6_14", - "PSS_IMUX_B6_15", - "PSS_IMUX_B6_16", - "PSS_IMUX_B6_17", - "PSS_IMUX_B6_18", - "PSS_IMUX_B6_19", - "PSS_IMUX_B6_2", - "PSS_IMUX_B6_3", - "PSS_IMUX_B6_4", - "PSS_IMUX_B6_5", - "PSS_IMUX_B6_6", - "PSS_IMUX_B6_7", - "PSS_IMUX_B6_8", - "PSS_IMUX_B6_9", - "PSS_IMUX_B7_0", - "PSS_IMUX_B7_1", - "PSS_IMUX_B7_10", - "PSS_IMUX_B7_11", - "PSS_IMUX_B7_12", - "PSS_IMUX_B7_13", - "PSS_IMUX_B7_14", - "PSS_IMUX_B7_15", - "PSS_IMUX_B7_16", - "PSS_IMUX_B7_17", - "PSS_IMUX_B7_18", - "PSS_IMUX_B7_19", - "PSS_IMUX_B7_2", - "PSS_IMUX_B7_3", - "PSS_IMUX_B7_4", - "PSS_IMUX_B7_5", - "PSS_IMUX_B7_6", - "PSS_IMUX_B7_7", - "PSS_IMUX_B7_8", - "PSS_IMUX_B7_9", - "PSS_IMUX_B8_0", - "PSS_IMUX_B8_1", - "PSS_IMUX_B8_10", - "PSS_IMUX_B8_11", - "PSS_IMUX_B8_12", - "PSS_IMUX_B8_13", - "PSS_IMUX_B8_14", - "PSS_IMUX_B8_15", - "PSS_IMUX_B8_16", - "PSS_IMUX_B8_17", - "PSS_IMUX_B8_18", - "PSS_IMUX_B8_19", - "PSS_IMUX_B8_2", - "PSS_IMUX_B8_3", - "PSS_IMUX_B8_4", - "PSS_IMUX_B8_5", - "PSS_IMUX_B8_6", - "PSS_IMUX_B8_7", - "PSS_IMUX_B8_8", - "PSS_IMUX_B8_9", - "PSS_IMUX_B9_0", - "PSS_IMUX_B9_1", - "PSS_IMUX_B9_10", - "PSS_IMUX_B9_11", - "PSS_IMUX_B9_12", - "PSS_IMUX_B9_13", - "PSS_IMUX_B9_14", - "PSS_IMUX_B9_15", - "PSS_IMUX_B9_16", - "PSS_IMUX_B9_17", - "PSS_IMUX_B9_18", - "PSS_IMUX_B9_19", - "PSS_IMUX_B9_2", - "PSS_IMUX_B9_3", - "PSS_IMUX_B9_4", - "PSS_IMUX_B9_5", - "PSS_IMUX_B9_6", - "PSS_IMUX_B9_7", - "PSS_IMUX_B9_8", - "PSS_IMUX_B9_9", - "PSS_LOGIC_OUTS0_0", - "PSS_LOGIC_OUTS0_1", - "PSS_LOGIC_OUTS0_10", - "PSS_LOGIC_OUTS0_11", - "PSS_LOGIC_OUTS0_12", - "PSS_LOGIC_OUTS0_13", - "PSS_LOGIC_OUTS0_14", - "PSS_LOGIC_OUTS0_15", - "PSS_LOGIC_OUTS0_16", - "PSS_LOGIC_OUTS0_17", - "PSS_LOGIC_OUTS0_18", - "PSS_LOGIC_OUTS0_19", - "PSS_LOGIC_OUTS0_2", - "PSS_LOGIC_OUTS0_3", - "PSS_LOGIC_OUTS0_4", - "PSS_LOGIC_OUTS0_5", - "PSS_LOGIC_OUTS0_6", - "PSS_LOGIC_OUTS0_7", - "PSS_LOGIC_OUTS0_8", - "PSS_LOGIC_OUTS0_9", - "PSS_LOGIC_OUTS10_0", - "PSS_LOGIC_OUTS10_1", - "PSS_LOGIC_OUTS10_10", - "PSS_LOGIC_OUTS10_11", - "PSS_LOGIC_OUTS10_12", - "PSS_LOGIC_OUTS10_13", - "PSS_LOGIC_OUTS10_14", - "PSS_LOGIC_OUTS10_15", - "PSS_LOGIC_OUTS10_16", - "PSS_LOGIC_OUTS10_17", - "PSS_LOGIC_OUTS10_18", - "PSS_LOGIC_OUTS10_19", - "PSS_LOGIC_OUTS10_2", - "PSS_LOGIC_OUTS10_3", - "PSS_LOGIC_OUTS10_4", - "PSS_LOGIC_OUTS10_5", - "PSS_LOGIC_OUTS10_6", - "PSS_LOGIC_OUTS10_7", - "PSS_LOGIC_OUTS10_8", - "PSS_LOGIC_OUTS10_9", - "PSS_LOGIC_OUTS11_0", - "PSS_LOGIC_OUTS11_1", - "PSS_LOGIC_OUTS11_10", - "PSS_LOGIC_OUTS11_11", - "PSS_LOGIC_OUTS11_12", - "PSS_LOGIC_OUTS11_13", - "PSS_LOGIC_OUTS11_14", - "PSS_LOGIC_OUTS11_15", - "PSS_LOGIC_OUTS11_16", - "PSS_LOGIC_OUTS11_17", - "PSS_LOGIC_OUTS11_18", - "PSS_LOGIC_OUTS11_19", - "PSS_LOGIC_OUTS11_2", - "PSS_LOGIC_OUTS11_3", - "PSS_LOGIC_OUTS11_4", - "PSS_LOGIC_OUTS11_5", - "PSS_LOGIC_OUTS11_6", - "PSS_LOGIC_OUTS11_7", - "PSS_LOGIC_OUTS11_8", - "PSS_LOGIC_OUTS11_9", - "PSS_LOGIC_OUTS12_0", - "PSS_LOGIC_OUTS12_1", - "PSS_LOGIC_OUTS12_10", - "PSS_LOGIC_OUTS12_11", - "PSS_LOGIC_OUTS12_12", - "PSS_LOGIC_OUTS12_13", - "PSS_LOGIC_OUTS12_14", - "PSS_LOGIC_OUTS12_15", - "PSS_LOGIC_OUTS12_16", - "PSS_LOGIC_OUTS12_17", - "PSS_LOGIC_OUTS12_18", - "PSS_LOGIC_OUTS12_19", - "PSS_LOGIC_OUTS12_2", - "PSS_LOGIC_OUTS12_3", - "PSS_LOGIC_OUTS12_4", - "PSS_LOGIC_OUTS12_5", - "PSS_LOGIC_OUTS12_6", - "PSS_LOGIC_OUTS12_7", - "PSS_LOGIC_OUTS12_8", - "PSS_LOGIC_OUTS12_9", - "PSS_LOGIC_OUTS13_0", - "PSS_LOGIC_OUTS13_1", - "PSS_LOGIC_OUTS13_10", - "PSS_LOGIC_OUTS13_11", - "PSS_LOGIC_OUTS13_12", - "PSS_LOGIC_OUTS13_13", - "PSS_LOGIC_OUTS13_14", - "PSS_LOGIC_OUTS13_15", - "PSS_LOGIC_OUTS13_16", - "PSS_LOGIC_OUTS13_17", - "PSS_LOGIC_OUTS13_18", - "PSS_LOGIC_OUTS13_19", - "PSS_LOGIC_OUTS13_2", - "PSS_LOGIC_OUTS13_3", - "PSS_LOGIC_OUTS13_4", - "PSS_LOGIC_OUTS13_5", - "PSS_LOGIC_OUTS13_6", - "PSS_LOGIC_OUTS13_7", - "PSS_LOGIC_OUTS13_8", - "PSS_LOGIC_OUTS13_9", - "PSS_LOGIC_OUTS14_0", - "PSS_LOGIC_OUTS14_1", - "PSS_LOGIC_OUTS14_10", - "PSS_LOGIC_OUTS14_11", - "PSS_LOGIC_OUTS14_12", - "PSS_LOGIC_OUTS14_13", - "PSS_LOGIC_OUTS14_14", - "PSS_LOGIC_OUTS14_15", - "PSS_LOGIC_OUTS14_16", - "PSS_LOGIC_OUTS14_17", - "PSS_LOGIC_OUTS14_18", - "PSS_LOGIC_OUTS14_19", - "PSS_LOGIC_OUTS14_2", - "PSS_LOGIC_OUTS14_3", - "PSS_LOGIC_OUTS14_4", - "PSS_LOGIC_OUTS14_5", - "PSS_LOGIC_OUTS14_6", - "PSS_LOGIC_OUTS14_7", - "PSS_LOGIC_OUTS14_8", - "PSS_LOGIC_OUTS14_9", - "PSS_LOGIC_OUTS15_0", - "PSS_LOGIC_OUTS15_1", - "PSS_LOGIC_OUTS15_10", - "PSS_LOGIC_OUTS15_11", - "PSS_LOGIC_OUTS15_12", - "PSS_LOGIC_OUTS15_13", - "PSS_LOGIC_OUTS15_14", - "PSS_LOGIC_OUTS15_15", - "PSS_LOGIC_OUTS15_16", - "PSS_LOGIC_OUTS15_17", - "PSS_LOGIC_OUTS15_18", - "PSS_LOGIC_OUTS15_19", - "PSS_LOGIC_OUTS15_2", - "PSS_LOGIC_OUTS15_3", - "PSS_LOGIC_OUTS15_4", - "PSS_LOGIC_OUTS15_5", - "PSS_LOGIC_OUTS15_6", - "PSS_LOGIC_OUTS15_7", - "PSS_LOGIC_OUTS15_8", - "PSS_LOGIC_OUTS15_9", - "PSS_LOGIC_OUTS16_0", - "PSS_LOGIC_OUTS16_1", - "PSS_LOGIC_OUTS16_10", - "PSS_LOGIC_OUTS16_11", - "PSS_LOGIC_OUTS16_12", - "PSS_LOGIC_OUTS16_13", - "PSS_LOGIC_OUTS16_14", - "PSS_LOGIC_OUTS16_15", - "PSS_LOGIC_OUTS16_16", - "PSS_LOGIC_OUTS16_17", - "PSS_LOGIC_OUTS16_18", - "PSS_LOGIC_OUTS16_19", - "PSS_LOGIC_OUTS16_2", - "PSS_LOGIC_OUTS16_3", - "PSS_LOGIC_OUTS16_4", - "PSS_LOGIC_OUTS16_5", - "PSS_LOGIC_OUTS16_6", - "PSS_LOGIC_OUTS16_7", - "PSS_LOGIC_OUTS16_8", - "PSS_LOGIC_OUTS16_9", - "PSS_LOGIC_OUTS17_0", - "PSS_LOGIC_OUTS17_1", - "PSS_LOGIC_OUTS17_10", - "PSS_LOGIC_OUTS17_11", - "PSS_LOGIC_OUTS17_12", - "PSS_LOGIC_OUTS17_13", - "PSS_LOGIC_OUTS17_14", - "PSS_LOGIC_OUTS17_15", - "PSS_LOGIC_OUTS17_16", - "PSS_LOGIC_OUTS17_17", - "PSS_LOGIC_OUTS17_18", - "PSS_LOGIC_OUTS17_19", - "PSS_LOGIC_OUTS17_2", - "PSS_LOGIC_OUTS17_3", - "PSS_LOGIC_OUTS17_4", - "PSS_LOGIC_OUTS17_5", - "PSS_LOGIC_OUTS17_6", - "PSS_LOGIC_OUTS17_7", - "PSS_LOGIC_OUTS17_8", - "PSS_LOGIC_OUTS17_9", - "PSS_LOGIC_OUTS18_0", - "PSS_LOGIC_OUTS18_1", - "PSS_LOGIC_OUTS18_10", - "PSS_LOGIC_OUTS18_11", - "PSS_LOGIC_OUTS18_12", - "PSS_LOGIC_OUTS18_13", - "PSS_LOGIC_OUTS18_14", - "PSS_LOGIC_OUTS18_15", - "PSS_LOGIC_OUTS18_16", - "PSS_LOGIC_OUTS18_17", - "PSS_LOGIC_OUTS18_18", - "PSS_LOGIC_OUTS18_19", - "PSS_LOGIC_OUTS18_2", - "PSS_LOGIC_OUTS18_3", - "PSS_LOGIC_OUTS18_4", - "PSS_LOGIC_OUTS18_5", - "PSS_LOGIC_OUTS18_6", - "PSS_LOGIC_OUTS18_7", - "PSS_LOGIC_OUTS18_8", - "PSS_LOGIC_OUTS18_9", - "PSS_LOGIC_OUTS19_0", - "PSS_LOGIC_OUTS19_1", - "PSS_LOGIC_OUTS19_10", - "PSS_LOGIC_OUTS19_11", - "PSS_LOGIC_OUTS19_12", - "PSS_LOGIC_OUTS19_13", - "PSS_LOGIC_OUTS19_14", - "PSS_LOGIC_OUTS19_15", - "PSS_LOGIC_OUTS19_16", - "PSS_LOGIC_OUTS19_17", - "PSS_LOGIC_OUTS19_18", - "PSS_LOGIC_OUTS19_19", - "PSS_LOGIC_OUTS19_2", - "PSS_LOGIC_OUTS19_3", - "PSS_LOGIC_OUTS19_4", - "PSS_LOGIC_OUTS19_5", - "PSS_LOGIC_OUTS19_6", - "PSS_LOGIC_OUTS19_7", - "PSS_LOGIC_OUTS19_8", - "PSS_LOGIC_OUTS19_9", - "PSS_LOGIC_OUTS1_0", - "PSS_LOGIC_OUTS1_1", - "PSS_LOGIC_OUTS1_10", - "PSS_LOGIC_OUTS1_11", - "PSS_LOGIC_OUTS1_12", - "PSS_LOGIC_OUTS1_13", - "PSS_LOGIC_OUTS1_14", - "PSS_LOGIC_OUTS1_15", - "PSS_LOGIC_OUTS1_16", - "PSS_LOGIC_OUTS1_17", - "PSS_LOGIC_OUTS1_18", - "PSS_LOGIC_OUTS1_19", - "PSS_LOGIC_OUTS1_2", - "PSS_LOGIC_OUTS1_3", - "PSS_LOGIC_OUTS1_4", - "PSS_LOGIC_OUTS1_5", - "PSS_LOGIC_OUTS1_6", - "PSS_LOGIC_OUTS1_7", - "PSS_LOGIC_OUTS1_8", - "PSS_LOGIC_OUTS1_9", - "PSS_LOGIC_OUTS20_0", - "PSS_LOGIC_OUTS20_1", - "PSS_LOGIC_OUTS20_10", - "PSS_LOGIC_OUTS20_11", - "PSS_LOGIC_OUTS20_12", - "PSS_LOGIC_OUTS20_13", - "PSS_LOGIC_OUTS20_14", - "PSS_LOGIC_OUTS20_15", - "PSS_LOGIC_OUTS20_16", - "PSS_LOGIC_OUTS20_17", - "PSS_LOGIC_OUTS20_18", - "PSS_LOGIC_OUTS20_19", - "PSS_LOGIC_OUTS20_2", - "PSS_LOGIC_OUTS20_3", - "PSS_LOGIC_OUTS20_4", - "PSS_LOGIC_OUTS20_5", - "PSS_LOGIC_OUTS20_6", - "PSS_LOGIC_OUTS20_7", - "PSS_LOGIC_OUTS20_8", - "PSS_LOGIC_OUTS20_9", - "PSS_LOGIC_OUTS21_0", - "PSS_LOGIC_OUTS21_1", - "PSS_LOGIC_OUTS21_10", - "PSS_LOGIC_OUTS21_11", - "PSS_LOGIC_OUTS21_12", - "PSS_LOGIC_OUTS21_13", - "PSS_LOGIC_OUTS21_14", - "PSS_LOGIC_OUTS21_15", - "PSS_LOGIC_OUTS21_16", - "PSS_LOGIC_OUTS21_17", - "PSS_LOGIC_OUTS21_18", - "PSS_LOGIC_OUTS21_19", - "PSS_LOGIC_OUTS21_2", - "PSS_LOGIC_OUTS21_3", - "PSS_LOGIC_OUTS21_4", - "PSS_LOGIC_OUTS21_5", - "PSS_LOGIC_OUTS21_6", - "PSS_LOGIC_OUTS21_7", - "PSS_LOGIC_OUTS21_8", - "PSS_LOGIC_OUTS21_9", - "PSS_LOGIC_OUTS22_0", - "PSS_LOGIC_OUTS22_1", - "PSS_LOGIC_OUTS22_10", - "PSS_LOGIC_OUTS22_11", - "PSS_LOGIC_OUTS22_12", - "PSS_LOGIC_OUTS22_13", - "PSS_LOGIC_OUTS22_14", - "PSS_LOGIC_OUTS22_15", - "PSS_LOGIC_OUTS22_16", - "PSS_LOGIC_OUTS22_17", - "PSS_LOGIC_OUTS22_18", - "PSS_LOGIC_OUTS22_19", - "PSS_LOGIC_OUTS22_2", - "PSS_LOGIC_OUTS22_3", - "PSS_LOGIC_OUTS22_4", - "PSS_LOGIC_OUTS22_5", - "PSS_LOGIC_OUTS22_6", - "PSS_LOGIC_OUTS22_7", - "PSS_LOGIC_OUTS22_8", - "PSS_LOGIC_OUTS22_9", - "PSS_LOGIC_OUTS23_0", - "PSS_LOGIC_OUTS23_1", - "PSS_LOGIC_OUTS23_10", - "PSS_LOGIC_OUTS23_11", - "PSS_LOGIC_OUTS23_12", - "PSS_LOGIC_OUTS23_13", - "PSS_LOGIC_OUTS23_14", - "PSS_LOGIC_OUTS23_15", - "PSS_LOGIC_OUTS23_16", - "PSS_LOGIC_OUTS23_17", - "PSS_LOGIC_OUTS23_18", - "PSS_LOGIC_OUTS23_19", - "PSS_LOGIC_OUTS23_2", - "PSS_LOGIC_OUTS23_3", - "PSS_LOGIC_OUTS23_4", - "PSS_LOGIC_OUTS23_5", - "PSS_LOGIC_OUTS23_6", - "PSS_LOGIC_OUTS23_7", - "PSS_LOGIC_OUTS23_8", - "PSS_LOGIC_OUTS23_9", - "PSS_LOGIC_OUTS2_0", - "PSS_LOGIC_OUTS2_1", - "PSS_LOGIC_OUTS2_10", - "PSS_LOGIC_OUTS2_11", - "PSS_LOGIC_OUTS2_12", - "PSS_LOGIC_OUTS2_13", - "PSS_LOGIC_OUTS2_14", - "PSS_LOGIC_OUTS2_15", - "PSS_LOGIC_OUTS2_16", - "PSS_LOGIC_OUTS2_17", - "PSS_LOGIC_OUTS2_18", - "PSS_LOGIC_OUTS2_19", - "PSS_LOGIC_OUTS2_2", - "PSS_LOGIC_OUTS2_3", - "PSS_LOGIC_OUTS2_4", - "PSS_LOGIC_OUTS2_5", - "PSS_LOGIC_OUTS2_6", - "PSS_LOGIC_OUTS2_7", - "PSS_LOGIC_OUTS2_8", - "PSS_LOGIC_OUTS2_9", - "PSS_LOGIC_OUTS3_0", - "PSS_LOGIC_OUTS3_1", - "PSS_LOGIC_OUTS3_10", - "PSS_LOGIC_OUTS3_11", - "PSS_LOGIC_OUTS3_12", - "PSS_LOGIC_OUTS3_13", - "PSS_LOGIC_OUTS3_14", - "PSS_LOGIC_OUTS3_15", - "PSS_LOGIC_OUTS3_16", - "PSS_LOGIC_OUTS3_17", - "PSS_LOGIC_OUTS3_18", - "PSS_LOGIC_OUTS3_19", - "PSS_LOGIC_OUTS3_2", - "PSS_LOGIC_OUTS3_3", - "PSS_LOGIC_OUTS3_4", - "PSS_LOGIC_OUTS3_5", - "PSS_LOGIC_OUTS3_6", - "PSS_LOGIC_OUTS3_7", - "PSS_LOGIC_OUTS3_8", - "PSS_LOGIC_OUTS3_9", - "PSS_LOGIC_OUTS4_0", - "PSS_LOGIC_OUTS4_1", - "PSS_LOGIC_OUTS4_10", - "PSS_LOGIC_OUTS4_11", - "PSS_LOGIC_OUTS4_12", - "PSS_LOGIC_OUTS4_13", - "PSS_LOGIC_OUTS4_14", - "PSS_LOGIC_OUTS4_15", - "PSS_LOGIC_OUTS4_16", - "PSS_LOGIC_OUTS4_17", - "PSS_LOGIC_OUTS4_18", - "PSS_LOGIC_OUTS4_19", - "PSS_LOGIC_OUTS4_2", - "PSS_LOGIC_OUTS4_3", - "PSS_LOGIC_OUTS4_4", - "PSS_LOGIC_OUTS4_5", - "PSS_LOGIC_OUTS4_6", - "PSS_LOGIC_OUTS4_7", - "PSS_LOGIC_OUTS4_8", - "PSS_LOGIC_OUTS4_9", - "PSS_LOGIC_OUTS5_0", - "PSS_LOGIC_OUTS5_1", - "PSS_LOGIC_OUTS5_10", - "PSS_LOGIC_OUTS5_11", - "PSS_LOGIC_OUTS5_12", - "PSS_LOGIC_OUTS5_13", - "PSS_LOGIC_OUTS5_14", - "PSS_LOGIC_OUTS5_15", - "PSS_LOGIC_OUTS5_16", - "PSS_LOGIC_OUTS5_17", - "PSS_LOGIC_OUTS5_18", - "PSS_LOGIC_OUTS5_19", - "PSS_LOGIC_OUTS5_2", - "PSS_LOGIC_OUTS5_3", - "PSS_LOGIC_OUTS5_4", - "PSS_LOGIC_OUTS5_5", - "PSS_LOGIC_OUTS5_6", - "PSS_LOGIC_OUTS5_7", - "PSS_LOGIC_OUTS5_8", - "PSS_LOGIC_OUTS5_9", - "PSS_LOGIC_OUTS6_0", - "PSS_LOGIC_OUTS6_1", - "PSS_LOGIC_OUTS6_10", - "PSS_LOGIC_OUTS6_11", - "PSS_LOGIC_OUTS6_12", - "PSS_LOGIC_OUTS6_13", - "PSS_LOGIC_OUTS6_14", - "PSS_LOGIC_OUTS6_15", - "PSS_LOGIC_OUTS6_16", - "PSS_LOGIC_OUTS6_17", - "PSS_LOGIC_OUTS6_18", - "PSS_LOGIC_OUTS6_19", - "PSS_LOGIC_OUTS6_2", - "PSS_LOGIC_OUTS6_3", - "PSS_LOGIC_OUTS6_4", - "PSS_LOGIC_OUTS6_5", - "PSS_LOGIC_OUTS6_6", - "PSS_LOGIC_OUTS6_7", - "PSS_LOGIC_OUTS6_8", - "PSS_LOGIC_OUTS6_9", - "PSS_LOGIC_OUTS7_0", - "PSS_LOGIC_OUTS7_1", - "PSS_LOGIC_OUTS7_10", - "PSS_LOGIC_OUTS7_11", - "PSS_LOGIC_OUTS7_12", - "PSS_LOGIC_OUTS7_13", - "PSS_LOGIC_OUTS7_14", - "PSS_LOGIC_OUTS7_15", - "PSS_LOGIC_OUTS7_16", - "PSS_LOGIC_OUTS7_17", - "PSS_LOGIC_OUTS7_18", - "PSS_LOGIC_OUTS7_19", - "PSS_LOGIC_OUTS7_2", - "PSS_LOGIC_OUTS7_3", - "PSS_LOGIC_OUTS7_4", - "PSS_LOGIC_OUTS7_5", - "PSS_LOGIC_OUTS7_6", - "PSS_LOGIC_OUTS7_7", - "PSS_LOGIC_OUTS7_8", - "PSS_LOGIC_OUTS7_9", - "PSS_LOGIC_OUTS8_0", - "PSS_LOGIC_OUTS8_1", - "PSS_LOGIC_OUTS8_10", - "PSS_LOGIC_OUTS8_11", - "PSS_LOGIC_OUTS8_12", - "PSS_LOGIC_OUTS8_13", - "PSS_LOGIC_OUTS8_14", - "PSS_LOGIC_OUTS8_15", - "PSS_LOGIC_OUTS8_16", - "PSS_LOGIC_OUTS8_17", - "PSS_LOGIC_OUTS8_18", - "PSS_LOGIC_OUTS8_19", - "PSS_LOGIC_OUTS8_2", - "PSS_LOGIC_OUTS8_3", - "PSS_LOGIC_OUTS8_4", - "PSS_LOGIC_OUTS8_5", - "PSS_LOGIC_OUTS8_6", - "PSS_LOGIC_OUTS8_7", - "PSS_LOGIC_OUTS8_8", - "PSS_LOGIC_OUTS8_9", - "PSS_LOGIC_OUTS9_0", - "PSS_LOGIC_OUTS9_1", - "PSS_LOGIC_OUTS9_10", - "PSS_LOGIC_OUTS9_11", - "PSS_LOGIC_OUTS9_12", - "PSS_LOGIC_OUTS9_13", - "PSS_LOGIC_OUTS9_14", - "PSS_LOGIC_OUTS9_15", - "PSS_LOGIC_OUTS9_16", - "PSS_LOGIC_OUTS9_17", - "PSS_LOGIC_OUTS9_18", - "PSS_LOGIC_OUTS9_19", - "PSS_LOGIC_OUTS9_2", - "PSS_LOGIC_OUTS9_3", - "PSS_LOGIC_OUTS9_4", - "PSS_LOGIC_OUTS9_5", - "PSS_LOGIC_OUTS9_6", - "PSS_LOGIC_OUTS9_7", - "PSS_LOGIC_OUTS9_8", - "PSS_LOGIC_OUTS9_9" - ] + "wires": { + "PSS0_CLK_B0_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_18": { + "cap": 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"10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS5_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS5_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS5_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS5_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS5_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS5_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_9": { + "cap": "10.823", + "res": "0.000" + } + } } diff --git a/zynq7/tile_type_PSS1.json b/zynq7/tile_type_PSS1.json index 0a71c51..3163331 100644 --- a/zynq7/tile_type_PSS1.json +++ b/zynq7/tile_type_PSS1.json @@ -2,27043 +2,78539 @@ "pips": { "PSS1.PSS0_CLK_B0_0->PSS1_CLK_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_0" }, "PSS1.PSS0_CLK_B0_1->PSS1_CLK_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_1" }, "PSS1.PSS0_CLK_B0_10->PSS1_CLK_B0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_10" }, "PSS1.PSS0_CLK_B0_11->PSS1_CLK_B0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_11" }, "PSS1.PSS0_CLK_B0_12->PSS1_CLK_B0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_12" }, "PSS1.PSS0_CLK_B0_13->PSS1_CLK_B0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_13" }, "PSS1.PSS0_CLK_B0_14->PSS1_CLK_B0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_14" }, "PSS1.PSS0_CLK_B0_15->PSS1_CLK_B0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_15" }, "PSS1.PSS0_CLK_B0_16->PSS1_CLK_B0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_16" }, "PSS1.PSS0_CLK_B0_17->PSS1_CLK_B0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_17" }, "PSS1.PSS0_CLK_B0_18->PSS1_CLK_B0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_18" }, "PSS1.PSS0_CLK_B0_19->PSS1_CLK_B0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_19" }, "PSS1.PSS0_CLK_B0_2->PSS1_CLK_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_2" }, "PSS1.PSS0_CLK_B0_3->PSS1_CLK_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_3" }, "PSS1.PSS0_CLK_B0_4->PSS1_CLK_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_4" }, "PSS1.PSS0_CLK_B0_5->PSS1_CLK_B0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_5" }, "PSS1.PSS0_CLK_B0_6->PSS1_CLK_B0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_6" }, "PSS1.PSS0_CLK_B0_7->PSS1_CLK_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_7" }, "PSS1.PSS0_CLK_B0_8->PSS1_CLK_B0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_8" }, "PSS1.PSS0_CLK_B0_9->PSS1_CLK_B0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_9" }, "PSS1.PSS0_CLK_B1_0->PSS1_CLK_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_0" }, "PSS1.PSS0_CLK_B1_1->PSS1_CLK_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_1" }, "PSS1.PSS0_CLK_B1_10->PSS1_CLK_B1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_10" }, "PSS1.PSS0_CLK_B1_11->PSS1_CLK_B1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_11" }, "PSS1.PSS0_CLK_B1_12->PSS1_CLK_B1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_12" }, "PSS1.PSS0_CLK_B1_13->PSS1_CLK_B1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_13" }, "PSS1.PSS0_CLK_B1_14->PSS1_CLK_B1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_14" }, "PSS1.PSS0_CLK_B1_15->PSS1_CLK_B1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_15" }, "PSS1.PSS0_CLK_B1_16->PSS1_CLK_B1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_16" }, "PSS1.PSS0_CLK_B1_17->PSS1_CLK_B1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_17" }, "PSS1.PSS0_CLK_B1_18->PSS1_CLK_B1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_18" }, "PSS1.PSS0_CLK_B1_19->PSS1_CLK_B1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_19" }, "PSS1.PSS0_CLK_B1_2->PSS1_CLK_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_2" }, "PSS1.PSS0_CLK_B1_3->PSS1_CLK_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_3" }, "PSS1.PSS0_CLK_B1_4->PSS1_CLK_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_4" }, "PSS1.PSS0_CLK_B1_5->PSS1_CLK_B1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_5" }, "PSS1.PSS0_CLK_B1_6->PSS1_CLK_B1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_6" }, "PSS1.PSS0_CLK_B1_7->PSS1_CLK_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_7" }, "PSS1.PSS0_CLK_B1_8->PSS1_CLK_B1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_8" }, "PSS1.PSS0_CLK_B1_9->PSS1_CLK_B1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_9" }, "PSS1.PSS0_IMUX_B0_0->PSS1_IMUX_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_0" }, "PSS1.PSS0_IMUX_B0_1->PSS1_IMUX_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_1" }, "PSS1.PSS0_IMUX_B0_10->PSS1_IMUX_B0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_10" }, "PSS1.PSS0_IMUX_B0_11->PSS1_IMUX_B0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_11" }, "PSS1.PSS0_IMUX_B0_12->PSS1_IMUX_B0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_12" }, "PSS1.PSS0_IMUX_B0_13->PSS1_IMUX_B0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_13" }, "PSS1.PSS0_IMUX_B0_14->PSS1_IMUX_B0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_14" }, "PSS1.PSS0_IMUX_B0_15->PSS1_IMUX_B0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_15" }, "PSS1.PSS0_IMUX_B0_16->PSS1_IMUX_B0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_16" }, "PSS1.PSS0_IMUX_B0_17->PSS1_IMUX_B0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_17" }, "PSS1.PSS0_IMUX_B0_18->PSS1_IMUX_B0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_18" }, "PSS1.PSS0_IMUX_B0_19->PSS1_IMUX_B0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_19" }, "PSS1.PSS0_IMUX_B0_2->PSS1_IMUX_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_2" }, "PSS1.PSS0_IMUX_B0_3->PSS1_IMUX_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_3" }, "PSS1.PSS0_IMUX_B0_4->PSS1_IMUX_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_4" }, "PSS1.PSS0_IMUX_B0_5->PSS1_IMUX_B0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_5" }, "PSS1.PSS0_IMUX_B0_6->PSS1_IMUX_B0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_6" }, "PSS1.PSS0_IMUX_B0_7->PSS1_IMUX_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_7" }, "PSS1.PSS0_IMUX_B0_8->PSS1_IMUX_B0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_8" }, "PSS1.PSS0_IMUX_B0_9->PSS1_IMUX_B0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_9" }, "PSS1.PSS0_IMUX_B10_0->PSS1_IMUX_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_0" }, "PSS1.PSS0_IMUX_B10_1->PSS1_IMUX_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_1" }, "PSS1.PSS0_IMUX_B10_10->PSS1_IMUX_B10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_10" }, "PSS1.PSS0_IMUX_B10_11->PSS1_IMUX_B10_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_11" }, "PSS1.PSS0_IMUX_B10_12->PSS1_IMUX_B10_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_12" }, "PSS1.PSS0_IMUX_B10_13->PSS1_IMUX_B10_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_13" }, "PSS1.PSS0_IMUX_B10_14->PSS1_IMUX_B10_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_14" }, "PSS1.PSS0_IMUX_B10_15->PSS1_IMUX_B10_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_15" }, "PSS1.PSS0_IMUX_B10_16->PSS1_IMUX_B10_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_16" }, "PSS1.PSS0_IMUX_B10_17->PSS1_IMUX_B10_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_17" }, "PSS1.PSS0_IMUX_B10_18->PSS1_IMUX_B10_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_18" }, "PSS1.PSS0_IMUX_B10_19->PSS1_IMUX_B10_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_19" }, "PSS1.PSS0_IMUX_B10_2->PSS1_IMUX_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_2" }, "PSS1.PSS0_IMUX_B10_3->PSS1_IMUX_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_3" }, "PSS1.PSS0_IMUX_B10_4->PSS1_IMUX_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_4" }, "PSS1.PSS0_IMUX_B10_5->PSS1_IMUX_B10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_5" }, "PSS1.PSS0_IMUX_B10_6->PSS1_IMUX_B10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_6" }, "PSS1.PSS0_IMUX_B10_7->PSS1_IMUX_B10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_7" }, "PSS1.PSS0_IMUX_B10_8->PSS1_IMUX_B10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_8" }, "PSS1.PSS0_IMUX_B10_9->PSS1_IMUX_B10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_9" }, "PSS1.PSS0_IMUX_B11_0->PSS1_IMUX_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_0" }, "PSS1.PSS0_IMUX_B11_1->PSS1_IMUX_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_1" }, "PSS1.PSS0_IMUX_B11_10->PSS1_IMUX_B11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_10" }, "PSS1.PSS0_IMUX_B11_11->PSS1_IMUX_B11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_11" }, "PSS1.PSS0_IMUX_B11_12->PSS1_IMUX_B11_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_12" }, "PSS1.PSS0_IMUX_B11_13->PSS1_IMUX_B11_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_13" }, "PSS1.PSS0_IMUX_B11_14->PSS1_IMUX_B11_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_14" }, "PSS1.PSS0_IMUX_B11_15->PSS1_IMUX_B11_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_15" }, "PSS1.PSS0_IMUX_B11_16->PSS1_IMUX_B11_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_16" }, "PSS1.PSS0_IMUX_B11_17->PSS1_IMUX_B11_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_17" }, "PSS1.PSS0_IMUX_B11_18->PSS1_IMUX_B11_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_18" }, "PSS1.PSS0_IMUX_B11_19->PSS1_IMUX_B11_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_19" }, "PSS1.PSS0_IMUX_B11_2->PSS1_IMUX_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_2" }, "PSS1.PSS0_IMUX_B11_3->PSS1_IMUX_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_3" }, "PSS1.PSS0_IMUX_B11_4->PSS1_IMUX_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_4" }, "PSS1.PSS0_IMUX_B11_5->PSS1_IMUX_B11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_5" }, "PSS1.PSS0_IMUX_B11_6->PSS1_IMUX_B11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_6" }, "PSS1.PSS0_IMUX_B11_7->PSS1_IMUX_B11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_7" }, "PSS1.PSS0_IMUX_B11_8->PSS1_IMUX_B11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_8" }, "PSS1.PSS0_IMUX_B11_9->PSS1_IMUX_B11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_9" }, "PSS1.PSS0_IMUX_B12_0->PSS1_IMUX_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_0" }, "PSS1.PSS0_IMUX_B12_1->PSS1_IMUX_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_1" }, "PSS1.PSS0_IMUX_B12_10->PSS1_IMUX_B12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_10" }, "PSS1.PSS0_IMUX_B12_11->PSS1_IMUX_B12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_11" }, "PSS1.PSS0_IMUX_B12_12->PSS1_IMUX_B12_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_12" }, "PSS1.PSS0_IMUX_B12_13->PSS1_IMUX_B12_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_13" }, "PSS1.PSS0_IMUX_B12_14->PSS1_IMUX_B12_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_14" }, "PSS1.PSS0_IMUX_B12_15->PSS1_IMUX_B12_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_15" }, "PSS1.PSS0_IMUX_B12_16->PSS1_IMUX_B12_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_16" }, "PSS1.PSS0_IMUX_B12_17->PSS1_IMUX_B12_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_17" }, "PSS1.PSS0_IMUX_B12_18->PSS1_IMUX_B12_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_18" }, "PSS1.PSS0_IMUX_B12_19->PSS1_IMUX_B12_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_19" }, "PSS1.PSS0_IMUX_B12_2->PSS1_IMUX_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_2" }, "PSS1.PSS0_IMUX_B12_3->PSS1_IMUX_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_3" }, "PSS1.PSS0_IMUX_B12_4->PSS1_IMUX_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_4" }, "PSS1.PSS0_IMUX_B12_5->PSS1_IMUX_B12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_5" }, "PSS1.PSS0_IMUX_B12_6->PSS1_IMUX_B12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_6" }, "PSS1.PSS0_IMUX_B12_7->PSS1_IMUX_B12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_7" }, "PSS1.PSS0_IMUX_B12_8->PSS1_IMUX_B12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_8" }, "PSS1.PSS0_IMUX_B12_9->PSS1_IMUX_B12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_9" }, "PSS1.PSS0_IMUX_B13_0->PSS1_IMUX_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_0" }, "PSS1.PSS0_IMUX_B13_1->PSS1_IMUX_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_1" }, "PSS1.PSS0_IMUX_B13_10->PSS1_IMUX_B13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_10" }, "PSS1.PSS0_IMUX_B13_11->PSS1_IMUX_B13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_11" }, "PSS1.PSS0_IMUX_B13_12->PSS1_IMUX_B13_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_12" }, "PSS1.PSS0_IMUX_B13_13->PSS1_IMUX_B13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_13" }, "PSS1.PSS0_IMUX_B13_14->PSS1_IMUX_B13_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_14" }, "PSS1.PSS0_IMUX_B13_15->PSS1_IMUX_B13_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_15" }, "PSS1.PSS0_IMUX_B13_16->PSS1_IMUX_B13_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_16" }, "PSS1.PSS0_IMUX_B13_17->PSS1_IMUX_B13_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_17" }, "PSS1.PSS0_IMUX_B13_18->PSS1_IMUX_B13_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_18" }, "PSS1.PSS0_IMUX_B13_19->PSS1_IMUX_B13_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_19" }, "PSS1.PSS0_IMUX_B13_2->PSS1_IMUX_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_2" }, "PSS1.PSS0_IMUX_B13_3->PSS1_IMUX_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_3" }, "PSS1.PSS0_IMUX_B13_4->PSS1_IMUX_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_4" }, "PSS1.PSS0_IMUX_B13_5->PSS1_IMUX_B13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_5" }, "PSS1.PSS0_IMUX_B13_6->PSS1_IMUX_B13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_6" }, "PSS1.PSS0_IMUX_B13_7->PSS1_IMUX_B13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_7" }, "PSS1.PSS0_IMUX_B13_8->PSS1_IMUX_B13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_8" }, "PSS1.PSS0_IMUX_B13_9->PSS1_IMUX_B13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_9" }, "PSS1.PSS0_IMUX_B14_0->PSS1_IMUX_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_0" }, "PSS1.PSS0_IMUX_B14_1->PSS1_IMUX_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_1" }, "PSS1.PSS0_IMUX_B14_10->PSS1_IMUX_B14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_10" }, "PSS1.PSS0_IMUX_B14_11->PSS1_IMUX_B14_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_11" }, "PSS1.PSS0_IMUX_B14_12->PSS1_IMUX_B14_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_12" }, "PSS1.PSS0_IMUX_B14_13->PSS1_IMUX_B14_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_13" }, "PSS1.PSS0_IMUX_B14_14->PSS1_IMUX_B14_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_14" }, "PSS1.PSS0_IMUX_B14_15->PSS1_IMUX_B14_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_15" }, "PSS1.PSS0_IMUX_B14_16->PSS1_IMUX_B14_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_16" }, "PSS1.PSS0_IMUX_B14_17->PSS1_IMUX_B14_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_17" }, "PSS1.PSS0_IMUX_B14_18->PSS1_IMUX_B14_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_18" }, "PSS1.PSS0_IMUX_B14_19->PSS1_IMUX_B14_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_19" }, "PSS1.PSS0_IMUX_B14_2->PSS1_IMUX_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_2" }, "PSS1.PSS0_IMUX_B14_3->PSS1_IMUX_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_3" }, "PSS1.PSS0_IMUX_B14_4->PSS1_IMUX_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_4" }, "PSS1.PSS0_IMUX_B14_5->PSS1_IMUX_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_5" }, "PSS1.PSS0_IMUX_B14_6->PSS1_IMUX_B14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_6" }, "PSS1.PSS0_IMUX_B14_7->PSS1_IMUX_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_7" }, "PSS1.PSS0_IMUX_B14_8->PSS1_IMUX_B14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_8" }, "PSS1.PSS0_IMUX_B14_9->PSS1_IMUX_B14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_9" }, "PSS1.PSS0_IMUX_B15_0->PSS1_IMUX_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_0" }, "PSS1.PSS0_IMUX_B15_1->PSS1_IMUX_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_1" }, "PSS1.PSS0_IMUX_B15_10->PSS1_IMUX_B15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_10" }, "PSS1.PSS0_IMUX_B15_11->PSS1_IMUX_B15_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_11" }, "PSS1.PSS0_IMUX_B15_12->PSS1_IMUX_B15_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_12" }, "PSS1.PSS0_IMUX_B15_13->PSS1_IMUX_B15_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_13" }, "PSS1.PSS0_IMUX_B15_14->PSS1_IMUX_B15_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_14" }, "PSS1.PSS0_IMUX_B15_15->PSS1_IMUX_B15_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_15" }, "PSS1.PSS0_IMUX_B15_16->PSS1_IMUX_B15_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_16" }, "PSS1.PSS0_IMUX_B15_17->PSS1_IMUX_B15_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_17" }, "PSS1.PSS0_IMUX_B15_18->PSS1_IMUX_B15_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_18" }, "PSS1.PSS0_IMUX_B15_19->PSS1_IMUX_B15_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_19" }, "PSS1.PSS0_IMUX_B15_2->PSS1_IMUX_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_2" }, "PSS1.PSS0_IMUX_B15_3->PSS1_IMUX_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_3" }, "PSS1.PSS0_IMUX_B15_4->PSS1_IMUX_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_4" }, "PSS1.PSS0_IMUX_B15_5->PSS1_IMUX_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_5" }, "PSS1.PSS0_IMUX_B15_6->PSS1_IMUX_B15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_6" }, "PSS1.PSS0_IMUX_B15_7->PSS1_IMUX_B15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_7" }, "PSS1.PSS0_IMUX_B15_8->PSS1_IMUX_B15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_8" }, "PSS1.PSS0_IMUX_B15_9->PSS1_IMUX_B15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_9" }, "PSS1.PSS0_IMUX_B16_0->PSS1_IMUX_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_0" }, "PSS1.PSS0_IMUX_B16_1->PSS1_IMUX_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_1" }, "PSS1.PSS0_IMUX_B16_10->PSS1_IMUX_B16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_10" }, "PSS1.PSS0_IMUX_B16_11->PSS1_IMUX_B16_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_11" }, "PSS1.PSS0_IMUX_B16_12->PSS1_IMUX_B16_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_12" }, "PSS1.PSS0_IMUX_B16_13->PSS1_IMUX_B16_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_13" }, "PSS1.PSS0_IMUX_B16_14->PSS1_IMUX_B16_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_14" }, "PSS1.PSS0_IMUX_B16_15->PSS1_IMUX_B16_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_15" }, "PSS1.PSS0_IMUX_B16_16->PSS1_IMUX_B16_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_16" }, "PSS1.PSS0_IMUX_B16_17->PSS1_IMUX_B16_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_17" }, "PSS1.PSS0_IMUX_B16_18->PSS1_IMUX_B16_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_18" }, "PSS1.PSS0_IMUX_B16_19->PSS1_IMUX_B16_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_19" }, "PSS1.PSS0_IMUX_B16_2->PSS1_IMUX_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_2" }, "PSS1.PSS0_IMUX_B16_3->PSS1_IMUX_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_3" }, "PSS1.PSS0_IMUX_B16_4->PSS1_IMUX_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_4" }, "PSS1.PSS0_IMUX_B16_5->PSS1_IMUX_B16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_5" }, "PSS1.PSS0_IMUX_B16_6->PSS1_IMUX_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_6" }, "PSS1.PSS0_IMUX_B16_7->PSS1_IMUX_B16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_7" }, "PSS1.PSS0_IMUX_B16_8->PSS1_IMUX_B16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_8" }, "PSS1.PSS0_IMUX_B16_9->PSS1_IMUX_B16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_9" }, "PSS1.PSS0_IMUX_B17_0->PSS1_IMUX_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_0" }, "PSS1.PSS0_IMUX_B17_1->PSS1_IMUX_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_1" }, "PSS1.PSS0_IMUX_B17_10->PSS1_IMUX_B17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_10" }, "PSS1.PSS0_IMUX_B17_11->PSS1_IMUX_B17_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_11" }, "PSS1.PSS0_IMUX_B17_12->PSS1_IMUX_B17_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_12" }, "PSS1.PSS0_IMUX_B17_13->PSS1_IMUX_B17_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_13" }, "PSS1.PSS0_IMUX_B17_14->PSS1_IMUX_B17_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_14" }, "PSS1.PSS0_IMUX_B17_15->PSS1_IMUX_B17_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_15" }, "PSS1.PSS0_IMUX_B17_16->PSS1_IMUX_B17_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_16" }, "PSS1.PSS0_IMUX_B17_17->PSS1_IMUX_B17_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_17" }, "PSS1.PSS0_IMUX_B17_18->PSS1_IMUX_B17_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_18" }, "PSS1.PSS0_IMUX_B17_19->PSS1_IMUX_B17_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_19" }, "PSS1.PSS0_IMUX_B17_2->PSS1_IMUX_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_2" }, "PSS1.PSS0_IMUX_B17_3->PSS1_IMUX_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_3" }, "PSS1.PSS0_IMUX_B17_4->PSS1_IMUX_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_4" }, "PSS1.PSS0_IMUX_B17_5->PSS1_IMUX_B17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_5" }, "PSS1.PSS0_IMUX_B17_6->PSS1_IMUX_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_6" }, "PSS1.PSS0_IMUX_B17_7->PSS1_IMUX_B17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_7" }, "PSS1.PSS0_IMUX_B17_8->PSS1_IMUX_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_8" }, "PSS1.PSS0_IMUX_B17_9->PSS1_IMUX_B17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_9" }, "PSS1.PSS0_IMUX_B18_0->PSS1_IMUX_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_0" }, "PSS1.PSS0_IMUX_B18_1->PSS1_IMUX_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_1" }, "PSS1.PSS0_IMUX_B18_10->PSS1_IMUX_B18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_10" }, "PSS1.PSS0_IMUX_B18_11->PSS1_IMUX_B18_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_11" }, "PSS1.PSS0_IMUX_B18_12->PSS1_IMUX_B18_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_12" }, "PSS1.PSS0_IMUX_B18_13->PSS1_IMUX_B18_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_13" }, "PSS1.PSS0_IMUX_B18_14->PSS1_IMUX_B18_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_14" }, "PSS1.PSS0_IMUX_B18_15->PSS1_IMUX_B18_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_15" }, "PSS1.PSS0_IMUX_B18_16->PSS1_IMUX_B18_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_16" }, "PSS1.PSS0_IMUX_B18_17->PSS1_IMUX_B18_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_17" }, "PSS1.PSS0_IMUX_B18_18->PSS1_IMUX_B18_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_18" }, "PSS1.PSS0_IMUX_B18_19->PSS1_IMUX_B18_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_19" }, "PSS1.PSS0_IMUX_B18_2->PSS1_IMUX_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_2" }, "PSS1.PSS0_IMUX_B18_3->PSS1_IMUX_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_3" }, "PSS1.PSS0_IMUX_B18_4->PSS1_IMUX_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_4" }, "PSS1.PSS0_IMUX_B18_5->PSS1_IMUX_B18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_5" }, "PSS1.PSS0_IMUX_B18_6->PSS1_IMUX_B18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_6" }, "PSS1.PSS0_IMUX_B18_7->PSS1_IMUX_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_7" }, "PSS1.PSS0_IMUX_B18_8->PSS1_IMUX_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_8" }, "PSS1.PSS0_IMUX_B18_9->PSS1_IMUX_B18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_9" }, "PSS1.PSS0_IMUX_B19_0->PSS1_IMUX_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_0" }, "PSS1.PSS0_IMUX_B19_1->PSS1_IMUX_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_1" }, "PSS1.PSS0_IMUX_B19_10->PSS1_IMUX_B19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_10" }, "PSS1.PSS0_IMUX_B19_11->PSS1_IMUX_B19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_11" }, "PSS1.PSS0_IMUX_B19_12->PSS1_IMUX_B19_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_12" }, "PSS1.PSS0_IMUX_B19_13->PSS1_IMUX_B19_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_13" }, "PSS1.PSS0_IMUX_B19_14->PSS1_IMUX_B19_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_14" }, "PSS1.PSS0_IMUX_B19_15->PSS1_IMUX_B19_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_15" }, "PSS1.PSS0_IMUX_B19_16->PSS1_IMUX_B19_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_16" }, "PSS1.PSS0_IMUX_B19_17->PSS1_IMUX_B19_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_17" }, "PSS1.PSS0_IMUX_B19_18->PSS1_IMUX_B19_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_18" }, "PSS1.PSS0_IMUX_B19_19->PSS1_IMUX_B19_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_19" }, "PSS1.PSS0_IMUX_B19_2->PSS1_IMUX_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_2" }, "PSS1.PSS0_IMUX_B19_3->PSS1_IMUX_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_3" }, "PSS1.PSS0_IMUX_B19_4->PSS1_IMUX_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_4" }, "PSS1.PSS0_IMUX_B19_5->PSS1_IMUX_B19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_5" }, "PSS1.PSS0_IMUX_B19_6->PSS1_IMUX_B19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_6" }, "PSS1.PSS0_IMUX_B19_7->PSS1_IMUX_B19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_7" }, "PSS1.PSS0_IMUX_B19_8->PSS1_IMUX_B19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_8" }, "PSS1.PSS0_IMUX_B19_9->PSS1_IMUX_B19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_9" }, "PSS1.PSS0_IMUX_B1_0->PSS1_IMUX_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_0" }, "PSS1.PSS0_IMUX_B1_1->PSS1_IMUX_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_1" }, "PSS1.PSS0_IMUX_B1_10->PSS1_IMUX_B1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_10" }, "PSS1.PSS0_IMUX_B1_11->PSS1_IMUX_B1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_11" }, "PSS1.PSS0_IMUX_B1_12->PSS1_IMUX_B1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_12" }, "PSS1.PSS0_IMUX_B1_13->PSS1_IMUX_B1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_13" }, "PSS1.PSS0_IMUX_B1_14->PSS1_IMUX_B1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_14" }, "PSS1.PSS0_IMUX_B1_15->PSS1_IMUX_B1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_15" }, "PSS1.PSS0_IMUX_B1_16->PSS1_IMUX_B1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_16" }, "PSS1.PSS0_IMUX_B1_17->PSS1_IMUX_B1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_17" }, "PSS1.PSS0_IMUX_B1_18->PSS1_IMUX_B1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_18" }, "PSS1.PSS0_IMUX_B1_19->PSS1_IMUX_B1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_19" }, "PSS1.PSS0_IMUX_B1_2->PSS1_IMUX_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_2" }, "PSS1.PSS0_IMUX_B1_3->PSS1_IMUX_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_3" }, "PSS1.PSS0_IMUX_B1_4->PSS1_IMUX_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_4" }, "PSS1.PSS0_IMUX_B1_5->PSS1_IMUX_B1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_5" }, "PSS1.PSS0_IMUX_B1_6->PSS1_IMUX_B1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_6" }, "PSS1.PSS0_IMUX_B1_7->PSS1_IMUX_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_7" }, "PSS1.PSS0_IMUX_B1_8->PSS1_IMUX_B1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_8" }, "PSS1.PSS0_IMUX_B1_9->PSS1_IMUX_B1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_9" }, "PSS1.PSS0_IMUX_B20_0->PSS1_IMUX_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_0" }, "PSS1.PSS0_IMUX_B20_1->PSS1_IMUX_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_1" }, "PSS1.PSS0_IMUX_B20_10->PSS1_IMUX_B20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_10" }, "PSS1.PSS0_IMUX_B20_11->PSS1_IMUX_B20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_11" }, "PSS1.PSS0_IMUX_B20_12->PSS1_IMUX_B20_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_12" }, "PSS1.PSS0_IMUX_B20_13->PSS1_IMUX_B20_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_13" }, "PSS1.PSS0_IMUX_B20_14->PSS1_IMUX_B20_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_14" }, "PSS1.PSS0_IMUX_B20_15->PSS1_IMUX_B20_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_15" }, "PSS1.PSS0_IMUX_B20_16->PSS1_IMUX_B20_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_16" }, "PSS1.PSS0_IMUX_B20_17->PSS1_IMUX_B20_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_17" }, "PSS1.PSS0_IMUX_B20_18->PSS1_IMUX_B20_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_18" }, "PSS1.PSS0_IMUX_B20_19->PSS1_IMUX_B20_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_19" }, "PSS1.PSS0_IMUX_B20_2->PSS1_IMUX_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_2" }, "PSS1.PSS0_IMUX_B20_3->PSS1_IMUX_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_3" }, "PSS1.PSS0_IMUX_B20_4->PSS1_IMUX_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_4" }, "PSS1.PSS0_IMUX_B20_5->PSS1_IMUX_B20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_5" }, "PSS1.PSS0_IMUX_B20_6->PSS1_IMUX_B20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_6" }, "PSS1.PSS0_IMUX_B20_7->PSS1_IMUX_B20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_7" }, "PSS1.PSS0_IMUX_B20_8->PSS1_IMUX_B20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_8" }, "PSS1.PSS0_IMUX_B20_9->PSS1_IMUX_B20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_9" }, "PSS1.PSS0_IMUX_B21_0->PSS1_IMUX_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_0" }, "PSS1.PSS0_IMUX_B21_1->PSS1_IMUX_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_1" }, "PSS1.PSS0_IMUX_B21_10->PSS1_IMUX_B21_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_10" }, "PSS1.PSS0_IMUX_B21_11->PSS1_IMUX_B21_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_11" }, "PSS1.PSS0_IMUX_B21_12->PSS1_IMUX_B21_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_12" }, "PSS1.PSS0_IMUX_B21_13->PSS1_IMUX_B21_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_13" }, "PSS1.PSS0_IMUX_B21_14->PSS1_IMUX_B21_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_14" }, "PSS1.PSS0_IMUX_B21_15->PSS1_IMUX_B21_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_15" }, "PSS1.PSS0_IMUX_B21_16->PSS1_IMUX_B21_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_16" }, "PSS1.PSS0_IMUX_B21_17->PSS1_IMUX_B21_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_17" }, "PSS1.PSS0_IMUX_B21_18->PSS1_IMUX_B21_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_18" }, "PSS1.PSS0_IMUX_B21_19->PSS1_IMUX_B21_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_19" }, "PSS1.PSS0_IMUX_B21_2->PSS1_IMUX_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_2" }, "PSS1.PSS0_IMUX_B21_3->PSS1_IMUX_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_3" }, "PSS1.PSS0_IMUX_B21_4->PSS1_IMUX_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_4" }, "PSS1.PSS0_IMUX_B21_5->PSS1_IMUX_B21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_5" }, "PSS1.PSS0_IMUX_B21_6->PSS1_IMUX_B21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_6" }, "PSS1.PSS0_IMUX_B21_7->PSS1_IMUX_B21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_7" }, "PSS1.PSS0_IMUX_B21_8->PSS1_IMUX_B21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_8" }, "PSS1.PSS0_IMUX_B21_9->PSS1_IMUX_B21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_9" }, "PSS1.PSS0_IMUX_B22_0->PSS1_IMUX_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_0" }, "PSS1.PSS0_IMUX_B22_1->PSS1_IMUX_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_1" }, "PSS1.PSS0_IMUX_B22_10->PSS1_IMUX_B22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_10" }, "PSS1.PSS0_IMUX_B22_11->PSS1_IMUX_B22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_11" }, "PSS1.PSS0_IMUX_B22_12->PSS1_IMUX_B22_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_12" }, "PSS1.PSS0_IMUX_B22_13->PSS1_IMUX_B22_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_13" }, "PSS1.PSS0_IMUX_B22_14->PSS1_IMUX_B22_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_14" }, "PSS1.PSS0_IMUX_B22_15->PSS1_IMUX_B22_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_15" }, "PSS1.PSS0_IMUX_B22_16->PSS1_IMUX_B22_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_16" }, "PSS1.PSS0_IMUX_B22_17->PSS1_IMUX_B22_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_17" }, "PSS1.PSS0_IMUX_B22_18->PSS1_IMUX_B22_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_18" }, "PSS1.PSS0_IMUX_B22_19->PSS1_IMUX_B22_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_19" }, "PSS1.PSS0_IMUX_B22_2->PSS1_IMUX_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_2" }, "PSS1.PSS0_IMUX_B22_3->PSS1_IMUX_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_3" }, "PSS1.PSS0_IMUX_B22_4->PSS1_IMUX_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_4" }, "PSS1.PSS0_IMUX_B22_5->PSS1_IMUX_B22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_5" }, "PSS1.PSS0_IMUX_B22_6->PSS1_IMUX_B22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_6" }, "PSS1.PSS0_IMUX_B22_7->PSS1_IMUX_B22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_7" }, "PSS1.PSS0_IMUX_B22_8->PSS1_IMUX_B22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_8" }, "PSS1.PSS0_IMUX_B22_9->PSS1_IMUX_B22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_9" }, "PSS1.PSS0_IMUX_B23_0->PSS1_IMUX_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_0" }, "PSS1.PSS0_IMUX_B23_1->PSS1_IMUX_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_1" }, "PSS1.PSS0_IMUX_B23_10->PSS1_IMUX_B23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_10" }, "PSS1.PSS0_IMUX_B23_11->PSS1_IMUX_B23_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_11" }, "PSS1.PSS0_IMUX_B23_12->PSS1_IMUX_B23_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_12" }, "PSS1.PSS0_IMUX_B23_13->PSS1_IMUX_B23_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_13" }, "PSS1.PSS0_IMUX_B23_14->PSS1_IMUX_B23_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_14" }, "PSS1.PSS0_IMUX_B23_15->PSS1_IMUX_B23_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_15" }, "PSS1.PSS0_IMUX_B23_16->PSS1_IMUX_B23_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_16" }, "PSS1.PSS0_IMUX_B23_17->PSS1_IMUX_B23_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_17" }, "PSS1.PSS0_IMUX_B23_18->PSS1_IMUX_B23_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_18" }, "PSS1.PSS0_IMUX_B23_19->PSS1_IMUX_B23_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_19" }, "PSS1.PSS0_IMUX_B23_2->PSS1_IMUX_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_2" }, "PSS1.PSS0_IMUX_B23_3->PSS1_IMUX_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_3" }, "PSS1.PSS0_IMUX_B23_4->PSS1_IMUX_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_4" }, "PSS1.PSS0_IMUX_B23_5->PSS1_IMUX_B23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_5" }, "PSS1.PSS0_IMUX_B23_6->PSS1_IMUX_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_6" }, "PSS1.PSS0_IMUX_B23_7->PSS1_IMUX_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_7" }, "PSS1.PSS0_IMUX_B23_8->PSS1_IMUX_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_8" }, "PSS1.PSS0_IMUX_B23_9->PSS1_IMUX_B23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_9" }, "PSS1.PSS0_IMUX_B24_0->PSS1_IMUX_B24_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_0" }, "PSS1.PSS0_IMUX_B24_1->PSS1_IMUX_B24_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_1" }, "PSS1.PSS0_IMUX_B24_10->PSS1_IMUX_B24_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_10" }, "PSS1.PSS0_IMUX_B24_11->PSS1_IMUX_B24_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_11" }, "PSS1.PSS0_IMUX_B24_12->PSS1_IMUX_B24_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_12" }, "PSS1.PSS0_IMUX_B24_13->PSS1_IMUX_B24_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_13" }, "PSS1.PSS0_IMUX_B24_14->PSS1_IMUX_B24_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_14" }, "PSS1.PSS0_IMUX_B24_15->PSS1_IMUX_B24_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_15" }, "PSS1.PSS0_IMUX_B24_16->PSS1_IMUX_B24_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_16" }, "PSS1.PSS0_IMUX_B24_17->PSS1_IMUX_B24_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_17" }, "PSS1.PSS0_IMUX_B24_18->PSS1_IMUX_B24_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_18" }, "PSS1.PSS0_IMUX_B24_19->PSS1_IMUX_B24_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_19" }, "PSS1.PSS0_IMUX_B24_2->PSS1_IMUX_B24_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_2" }, "PSS1.PSS0_IMUX_B24_3->PSS1_IMUX_B24_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_3" }, "PSS1.PSS0_IMUX_B24_4->PSS1_IMUX_B24_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_4" }, "PSS1.PSS0_IMUX_B24_5->PSS1_IMUX_B24_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_5" }, "PSS1.PSS0_IMUX_B24_6->PSS1_IMUX_B24_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_6" }, "PSS1.PSS0_IMUX_B24_7->PSS1_IMUX_B24_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_7" }, "PSS1.PSS0_IMUX_B24_8->PSS1_IMUX_B24_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_8" }, "PSS1.PSS0_IMUX_B24_9->PSS1_IMUX_B24_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_9" }, "PSS1.PSS0_IMUX_B25_0->PSS1_IMUX_B25_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_0" }, "PSS1.PSS0_IMUX_B25_1->PSS1_IMUX_B25_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_1" }, "PSS1.PSS0_IMUX_B25_10->PSS1_IMUX_B25_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_10" }, "PSS1.PSS0_IMUX_B25_11->PSS1_IMUX_B25_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_11" }, "PSS1.PSS0_IMUX_B25_12->PSS1_IMUX_B25_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_12" }, "PSS1.PSS0_IMUX_B25_13->PSS1_IMUX_B25_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_13" }, "PSS1.PSS0_IMUX_B25_14->PSS1_IMUX_B25_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_14" }, "PSS1.PSS0_IMUX_B25_15->PSS1_IMUX_B25_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_15" }, "PSS1.PSS0_IMUX_B25_16->PSS1_IMUX_B25_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_16" }, "PSS1.PSS0_IMUX_B25_17->PSS1_IMUX_B25_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_17" }, "PSS1.PSS0_IMUX_B25_18->PSS1_IMUX_B25_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_18" }, "PSS1.PSS0_IMUX_B25_19->PSS1_IMUX_B25_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_19" }, "PSS1.PSS0_IMUX_B25_2->PSS1_IMUX_B25_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_2" }, "PSS1.PSS0_IMUX_B25_3->PSS1_IMUX_B25_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_3" }, "PSS1.PSS0_IMUX_B25_4->PSS1_IMUX_B25_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_4" }, "PSS1.PSS0_IMUX_B25_5->PSS1_IMUX_B25_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_5" }, "PSS1.PSS0_IMUX_B25_6->PSS1_IMUX_B25_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_6" }, "PSS1.PSS0_IMUX_B25_7->PSS1_IMUX_B25_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_7" }, "PSS1.PSS0_IMUX_B25_8->PSS1_IMUX_B25_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_8" }, "PSS1.PSS0_IMUX_B25_9->PSS1_IMUX_B25_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_9" }, "PSS1.PSS0_IMUX_B26_0->PSS1_IMUX_B26_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_0" }, "PSS1.PSS0_IMUX_B26_1->PSS1_IMUX_B26_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_1" }, "PSS1.PSS0_IMUX_B26_10->PSS1_IMUX_B26_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_10" }, "PSS1.PSS0_IMUX_B26_11->PSS1_IMUX_B26_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_11" }, "PSS1.PSS0_IMUX_B26_12->PSS1_IMUX_B26_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_12" }, "PSS1.PSS0_IMUX_B26_13->PSS1_IMUX_B26_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_13" }, "PSS1.PSS0_IMUX_B26_14->PSS1_IMUX_B26_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_14" }, "PSS1.PSS0_IMUX_B26_15->PSS1_IMUX_B26_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_15" }, "PSS1.PSS0_IMUX_B26_16->PSS1_IMUX_B26_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_16" }, "PSS1.PSS0_IMUX_B26_17->PSS1_IMUX_B26_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_17" }, "PSS1.PSS0_IMUX_B26_18->PSS1_IMUX_B26_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_18" }, "PSS1.PSS0_IMUX_B26_19->PSS1_IMUX_B26_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_19" }, "PSS1.PSS0_IMUX_B26_2->PSS1_IMUX_B26_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_2" }, "PSS1.PSS0_IMUX_B26_3->PSS1_IMUX_B26_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_3" }, "PSS1.PSS0_IMUX_B26_4->PSS1_IMUX_B26_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_4" }, "PSS1.PSS0_IMUX_B26_5->PSS1_IMUX_B26_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_5" }, "PSS1.PSS0_IMUX_B26_6->PSS1_IMUX_B26_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_6" }, "PSS1.PSS0_IMUX_B26_7->PSS1_IMUX_B26_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_7" }, "PSS1.PSS0_IMUX_B26_8->PSS1_IMUX_B26_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_8" }, "PSS1.PSS0_IMUX_B26_9->PSS1_IMUX_B26_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_9" }, "PSS1.PSS0_IMUX_B27_0->PSS1_IMUX_B27_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_0" }, "PSS1.PSS0_IMUX_B27_1->PSS1_IMUX_B27_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_1" }, "PSS1.PSS0_IMUX_B27_10->PSS1_IMUX_B27_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_10" }, "PSS1.PSS0_IMUX_B27_11->PSS1_IMUX_B27_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_11" }, "PSS1.PSS0_IMUX_B27_12->PSS1_IMUX_B27_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_12" }, "PSS1.PSS0_IMUX_B27_13->PSS1_IMUX_B27_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_13" }, "PSS1.PSS0_IMUX_B27_14->PSS1_IMUX_B27_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_14" }, "PSS1.PSS0_IMUX_B27_15->PSS1_IMUX_B27_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_15" }, "PSS1.PSS0_IMUX_B27_16->PSS1_IMUX_B27_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_16" }, "PSS1.PSS0_IMUX_B27_17->PSS1_IMUX_B27_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_17" }, "PSS1.PSS0_IMUX_B27_18->PSS1_IMUX_B27_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_18" }, "PSS1.PSS0_IMUX_B27_19->PSS1_IMUX_B27_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_19" }, "PSS1.PSS0_IMUX_B27_2->PSS1_IMUX_B27_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_2" }, "PSS1.PSS0_IMUX_B27_3->PSS1_IMUX_B27_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_3" }, "PSS1.PSS0_IMUX_B27_4->PSS1_IMUX_B27_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_4" }, "PSS1.PSS0_IMUX_B27_5->PSS1_IMUX_B27_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_5" }, "PSS1.PSS0_IMUX_B27_6->PSS1_IMUX_B27_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_6" }, "PSS1.PSS0_IMUX_B27_7->PSS1_IMUX_B27_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_7" }, "PSS1.PSS0_IMUX_B27_8->PSS1_IMUX_B27_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_8" }, "PSS1.PSS0_IMUX_B27_9->PSS1_IMUX_B27_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_9" }, "PSS1.PSS0_IMUX_B28_0->PSS1_IMUX_B28_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_0" }, "PSS1.PSS0_IMUX_B28_1->PSS1_IMUX_B28_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_1" }, "PSS1.PSS0_IMUX_B28_10->PSS1_IMUX_B28_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_10" }, "PSS1.PSS0_IMUX_B28_11->PSS1_IMUX_B28_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_11" }, "PSS1.PSS0_IMUX_B28_12->PSS1_IMUX_B28_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_12" }, "PSS1.PSS0_IMUX_B28_13->PSS1_IMUX_B28_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_13" }, "PSS1.PSS0_IMUX_B28_14->PSS1_IMUX_B28_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_14" }, "PSS1.PSS0_IMUX_B28_15->PSS1_IMUX_B28_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_15" }, "PSS1.PSS0_IMUX_B28_16->PSS1_IMUX_B28_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_16" }, "PSS1.PSS0_IMUX_B28_17->PSS1_IMUX_B28_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_17" }, "PSS1.PSS0_IMUX_B28_18->PSS1_IMUX_B28_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_18" }, "PSS1.PSS0_IMUX_B28_19->PSS1_IMUX_B28_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_19" }, "PSS1.PSS0_IMUX_B28_2->PSS1_IMUX_B28_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_2" }, "PSS1.PSS0_IMUX_B28_3->PSS1_IMUX_B28_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_3" }, "PSS1.PSS0_IMUX_B28_4->PSS1_IMUX_B28_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_4" }, "PSS1.PSS0_IMUX_B28_5->PSS1_IMUX_B28_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_5" }, "PSS1.PSS0_IMUX_B28_6->PSS1_IMUX_B28_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_6" }, "PSS1.PSS0_IMUX_B28_7->PSS1_IMUX_B28_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_7" }, "PSS1.PSS0_IMUX_B28_8->PSS1_IMUX_B28_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_8" }, "PSS1.PSS0_IMUX_B28_9->PSS1_IMUX_B28_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_9" }, "PSS1.PSS0_IMUX_B29_0->PSS1_IMUX_B29_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_0" }, "PSS1.PSS0_IMUX_B29_1->PSS1_IMUX_B29_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_1" }, "PSS1.PSS0_IMUX_B29_10->PSS1_IMUX_B29_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_10" }, "PSS1.PSS0_IMUX_B29_11->PSS1_IMUX_B29_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_11" }, "PSS1.PSS0_IMUX_B29_12->PSS1_IMUX_B29_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_12" }, "PSS1.PSS0_IMUX_B29_13->PSS1_IMUX_B29_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_13" }, "PSS1.PSS0_IMUX_B29_14->PSS1_IMUX_B29_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_14" }, "PSS1.PSS0_IMUX_B29_15->PSS1_IMUX_B29_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_15" }, "PSS1.PSS0_IMUX_B29_16->PSS1_IMUX_B29_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_16" }, "PSS1.PSS0_IMUX_B29_17->PSS1_IMUX_B29_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_17" }, "PSS1.PSS0_IMUX_B29_18->PSS1_IMUX_B29_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_18" }, "PSS1.PSS0_IMUX_B29_19->PSS1_IMUX_B29_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_19" }, "PSS1.PSS0_IMUX_B29_2->PSS1_IMUX_B29_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_2" }, "PSS1.PSS0_IMUX_B29_3->PSS1_IMUX_B29_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_3" }, "PSS1.PSS0_IMUX_B29_4->PSS1_IMUX_B29_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_4" }, "PSS1.PSS0_IMUX_B29_5->PSS1_IMUX_B29_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_5" }, "PSS1.PSS0_IMUX_B29_6->PSS1_IMUX_B29_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_6" }, "PSS1.PSS0_IMUX_B29_7->PSS1_IMUX_B29_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_7" }, "PSS1.PSS0_IMUX_B29_8->PSS1_IMUX_B29_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_8" }, "PSS1.PSS0_IMUX_B29_9->PSS1_IMUX_B29_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_9" }, "PSS1.PSS0_IMUX_B2_0->PSS1_IMUX_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_0" }, "PSS1.PSS0_IMUX_B2_1->PSS1_IMUX_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_1" }, "PSS1.PSS0_IMUX_B2_10->PSS1_IMUX_B2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_10" }, "PSS1.PSS0_IMUX_B2_11->PSS1_IMUX_B2_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_11" }, "PSS1.PSS0_IMUX_B2_12->PSS1_IMUX_B2_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_12" }, "PSS1.PSS0_IMUX_B2_13->PSS1_IMUX_B2_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_13" }, "PSS1.PSS0_IMUX_B2_14->PSS1_IMUX_B2_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_14" }, "PSS1.PSS0_IMUX_B2_15->PSS1_IMUX_B2_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_15" }, "PSS1.PSS0_IMUX_B2_16->PSS1_IMUX_B2_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_16" }, "PSS1.PSS0_IMUX_B2_17->PSS1_IMUX_B2_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_17" }, "PSS1.PSS0_IMUX_B2_18->PSS1_IMUX_B2_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_18" }, "PSS1.PSS0_IMUX_B2_19->PSS1_IMUX_B2_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_19" }, "PSS1.PSS0_IMUX_B2_2->PSS1_IMUX_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_2" }, "PSS1.PSS0_IMUX_B2_3->PSS1_IMUX_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_3" }, "PSS1.PSS0_IMUX_B2_4->PSS1_IMUX_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_4" }, "PSS1.PSS0_IMUX_B2_5->PSS1_IMUX_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_5" }, "PSS1.PSS0_IMUX_B2_6->PSS1_IMUX_B2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_6" }, "PSS1.PSS0_IMUX_B2_7->PSS1_IMUX_B2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_7" }, "PSS1.PSS0_IMUX_B2_8->PSS1_IMUX_B2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_8" }, "PSS1.PSS0_IMUX_B2_9->PSS1_IMUX_B2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_9" }, "PSS1.PSS0_IMUX_B30_0->PSS1_IMUX_B30_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_0" }, "PSS1.PSS0_IMUX_B30_1->PSS1_IMUX_B30_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_1" }, "PSS1.PSS0_IMUX_B30_10->PSS1_IMUX_B30_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_10" }, "PSS1.PSS0_IMUX_B30_11->PSS1_IMUX_B30_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_11" }, "PSS1.PSS0_IMUX_B30_12->PSS1_IMUX_B30_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_12" }, "PSS1.PSS0_IMUX_B30_13->PSS1_IMUX_B30_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_13" }, "PSS1.PSS0_IMUX_B30_14->PSS1_IMUX_B30_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_14" }, "PSS1.PSS0_IMUX_B30_15->PSS1_IMUX_B30_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_15" }, "PSS1.PSS0_IMUX_B30_16->PSS1_IMUX_B30_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_16" }, "PSS1.PSS0_IMUX_B30_17->PSS1_IMUX_B30_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_17" }, "PSS1.PSS0_IMUX_B30_18->PSS1_IMUX_B30_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_18" }, "PSS1.PSS0_IMUX_B30_19->PSS1_IMUX_B30_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_19" }, "PSS1.PSS0_IMUX_B30_2->PSS1_IMUX_B30_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_2" }, "PSS1.PSS0_IMUX_B30_3->PSS1_IMUX_B30_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_3" }, "PSS1.PSS0_IMUX_B30_4->PSS1_IMUX_B30_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_4" }, "PSS1.PSS0_IMUX_B30_5->PSS1_IMUX_B30_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_5" }, "PSS1.PSS0_IMUX_B30_6->PSS1_IMUX_B30_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_6" }, "PSS1.PSS0_IMUX_B30_7->PSS1_IMUX_B30_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_7" }, "PSS1.PSS0_IMUX_B30_8->PSS1_IMUX_B30_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_8" }, "PSS1.PSS0_IMUX_B30_9->PSS1_IMUX_B30_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_9" }, "PSS1.PSS0_IMUX_B31_0->PSS1_IMUX_B31_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_0" }, "PSS1.PSS0_IMUX_B31_1->PSS1_IMUX_B31_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_1" }, "PSS1.PSS0_IMUX_B31_10->PSS1_IMUX_B31_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_10" }, "PSS1.PSS0_IMUX_B31_11->PSS1_IMUX_B31_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_11" }, "PSS1.PSS0_IMUX_B31_12->PSS1_IMUX_B31_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_12" }, "PSS1.PSS0_IMUX_B31_13->PSS1_IMUX_B31_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_13" }, "PSS1.PSS0_IMUX_B31_14->PSS1_IMUX_B31_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_14" }, "PSS1.PSS0_IMUX_B31_15->PSS1_IMUX_B31_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_15" }, "PSS1.PSS0_IMUX_B31_16->PSS1_IMUX_B31_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_16" }, "PSS1.PSS0_IMUX_B31_17->PSS1_IMUX_B31_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_17" }, "PSS1.PSS0_IMUX_B31_18->PSS1_IMUX_B31_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_18" }, "PSS1.PSS0_IMUX_B31_19->PSS1_IMUX_B31_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_19" }, "PSS1.PSS0_IMUX_B31_2->PSS1_IMUX_B31_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_2" }, "PSS1.PSS0_IMUX_B31_3->PSS1_IMUX_B31_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_3" }, "PSS1.PSS0_IMUX_B31_4->PSS1_IMUX_B31_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_4" }, "PSS1.PSS0_IMUX_B31_5->PSS1_IMUX_B31_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_5" }, "PSS1.PSS0_IMUX_B31_6->PSS1_IMUX_B31_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_6" }, "PSS1.PSS0_IMUX_B31_7->PSS1_IMUX_B31_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_7" }, "PSS1.PSS0_IMUX_B31_8->PSS1_IMUX_B31_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_8" }, "PSS1.PSS0_IMUX_B31_9->PSS1_IMUX_B31_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_9" }, "PSS1.PSS0_IMUX_B32_0->PSS1_IMUX_B32_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_0" }, "PSS1.PSS0_IMUX_B32_1->PSS1_IMUX_B32_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_1" }, "PSS1.PSS0_IMUX_B32_10->PSS1_IMUX_B32_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_10" }, "PSS1.PSS0_IMUX_B32_11->PSS1_IMUX_B32_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_11" }, "PSS1.PSS0_IMUX_B32_12->PSS1_IMUX_B32_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_12" }, "PSS1.PSS0_IMUX_B32_13->PSS1_IMUX_B32_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_13" }, "PSS1.PSS0_IMUX_B32_14->PSS1_IMUX_B32_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_14" }, "PSS1.PSS0_IMUX_B32_15->PSS1_IMUX_B32_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_15" }, "PSS1.PSS0_IMUX_B32_16->PSS1_IMUX_B32_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_16" }, "PSS1.PSS0_IMUX_B32_17->PSS1_IMUX_B32_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_17" }, "PSS1.PSS0_IMUX_B32_18->PSS1_IMUX_B32_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_18" }, "PSS1.PSS0_IMUX_B32_19->PSS1_IMUX_B32_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_19" }, "PSS1.PSS0_IMUX_B32_2->PSS1_IMUX_B32_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_2" }, "PSS1.PSS0_IMUX_B32_3->PSS1_IMUX_B32_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_3" }, "PSS1.PSS0_IMUX_B32_4->PSS1_IMUX_B32_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_4" }, "PSS1.PSS0_IMUX_B32_5->PSS1_IMUX_B32_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_5" }, "PSS1.PSS0_IMUX_B32_6->PSS1_IMUX_B32_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_6" }, "PSS1.PSS0_IMUX_B32_7->PSS1_IMUX_B32_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_7" }, "PSS1.PSS0_IMUX_B32_8->PSS1_IMUX_B32_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_8" }, "PSS1.PSS0_IMUX_B32_9->PSS1_IMUX_B32_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_9" }, "PSS1.PSS0_IMUX_B33_0->PSS1_IMUX_B33_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_0" }, "PSS1.PSS0_IMUX_B33_1->PSS1_IMUX_B33_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_1" }, "PSS1.PSS0_IMUX_B33_10->PSS1_IMUX_B33_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_10" }, "PSS1.PSS0_IMUX_B33_11->PSS1_IMUX_B33_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_11" }, "PSS1.PSS0_IMUX_B33_12->PSS1_IMUX_B33_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_12" }, "PSS1.PSS0_IMUX_B33_13->PSS1_IMUX_B33_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_13" }, "PSS1.PSS0_IMUX_B33_14->PSS1_IMUX_B33_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_14" }, "PSS1.PSS0_IMUX_B33_15->PSS1_IMUX_B33_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_15" }, "PSS1.PSS0_IMUX_B33_16->PSS1_IMUX_B33_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_16" }, "PSS1.PSS0_IMUX_B33_17->PSS1_IMUX_B33_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_17" }, "PSS1.PSS0_IMUX_B33_18->PSS1_IMUX_B33_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_18" }, "PSS1.PSS0_IMUX_B33_19->PSS1_IMUX_B33_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_19" }, "PSS1.PSS0_IMUX_B33_2->PSS1_IMUX_B33_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_2" }, "PSS1.PSS0_IMUX_B33_3->PSS1_IMUX_B33_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_3" }, "PSS1.PSS0_IMUX_B33_4->PSS1_IMUX_B33_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_4" }, "PSS1.PSS0_IMUX_B33_5->PSS1_IMUX_B33_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_5" }, "PSS1.PSS0_IMUX_B33_6->PSS1_IMUX_B33_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_6" }, "PSS1.PSS0_IMUX_B33_7->PSS1_IMUX_B33_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_7" }, "PSS1.PSS0_IMUX_B33_8->PSS1_IMUX_B33_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_8" }, "PSS1.PSS0_IMUX_B33_9->PSS1_IMUX_B33_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_9" }, "PSS1.PSS0_IMUX_B34_0->PSS1_IMUX_B34_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_0" }, "PSS1.PSS0_IMUX_B34_1->PSS1_IMUX_B34_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_1" }, "PSS1.PSS0_IMUX_B34_10->PSS1_IMUX_B34_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_10" }, "PSS1.PSS0_IMUX_B34_11->PSS1_IMUX_B34_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_11" }, "PSS1.PSS0_IMUX_B34_12->PSS1_IMUX_B34_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_12" }, "PSS1.PSS0_IMUX_B34_13->PSS1_IMUX_B34_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_13" }, "PSS1.PSS0_IMUX_B34_14->PSS1_IMUX_B34_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_14" }, "PSS1.PSS0_IMUX_B34_15->PSS1_IMUX_B34_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_15" }, "PSS1.PSS0_IMUX_B34_16->PSS1_IMUX_B34_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_16" }, "PSS1.PSS0_IMUX_B34_17->PSS1_IMUX_B34_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_17" }, "PSS1.PSS0_IMUX_B34_18->PSS1_IMUX_B34_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_18" }, "PSS1.PSS0_IMUX_B34_19->PSS1_IMUX_B34_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_19" }, "PSS1.PSS0_IMUX_B34_2->PSS1_IMUX_B34_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_2" }, "PSS1.PSS0_IMUX_B34_3->PSS1_IMUX_B34_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_3" }, "PSS1.PSS0_IMUX_B34_4->PSS1_IMUX_B34_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_4" }, "PSS1.PSS0_IMUX_B34_5->PSS1_IMUX_B34_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_5" }, "PSS1.PSS0_IMUX_B34_6->PSS1_IMUX_B34_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_6" }, "PSS1.PSS0_IMUX_B34_7->PSS1_IMUX_B34_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_7" }, "PSS1.PSS0_IMUX_B34_8->PSS1_IMUX_B34_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_8" }, "PSS1.PSS0_IMUX_B34_9->PSS1_IMUX_B34_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_9" }, "PSS1.PSS0_IMUX_B35_0->PSS1_IMUX_B35_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_0" }, "PSS1.PSS0_IMUX_B35_1->PSS1_IMUX_B35_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_1" }, "PSS1.PSS0_IMUX_B35_10->PSS1_IMUX_B35_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_10" }, "PSS1.PSS0_IMUX_B35_11->PSS1_IMUX_B35_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_11" }, "PSS1.PSS0_IMUX_B35_12->PSS1_IMUX_B35_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_12" }, "PSS1.PSS0_IMUX_B35_13->PSS1_IMUX_B35_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_13" }, "PSS1.PSS0_IMUX_B35_14->PSS1_IMUX_B35_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_14" }, "PSS1.PSS0_IMUX_B35_15->PSS1_IMUX_B35_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_15" }, "PSS1.PSS0_IMUX_B35_16->PSS1_IMUX_B35_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_16" }, "PSS1.PSS0_IMUX_B35_17->PSS1_IMUX_B35_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_17" }, "PSS1.PSS0_IMUX_B35_18->PSS1_IMUX_B35_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_18" }, "PSS1.PSS0_IMUX_B35_19->PSS1_IMUX_B35_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_19" }, "PSS1.PSS0_IMUX_B35_2->PSS1_IMUX_B35_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_2" }, "PSS1.PSS0_IMUX_B35_3->PSS1_IMUX_B35_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_3" }, "PSS1.PSS0_IMUX_B35_4->PSS1_IMUX_B35_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_4" }, "PSS1.PSS0_IMUX_B35_5->PSS1_IMUX_B35_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_5" }, "PSS1.PSS0_IMUX_B35_6->PSS1_IMUX_B35_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_6" }, "PSS1.PSS0_IMUX_B35_7->PSS1_IMUX_B35_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_7" }, "PSS1.PSS0_IMUX_B35_8->PSS1_IMUX_B35_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_8" }, "PSS1.PSS0_IMUX_B35_9->PSS1_IMUX_B35_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_9" }, "PSS1.PSS0_IMUX_B36_0->PSS1_IMUX_B36_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_0" }, "PSS1.PSS0_IMUX_B36_1->PSS1_IMUX_B36_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_1" }, "PSS1.PSS0_IMUX_B36_10->PSS1_IMUX_B36_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_10" }, "PSS1.PSS0_IMUX_B36_11->PSS1_IMUX_B36_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_11" }, "PSS1.PSS0_IMUX_B36_12->PSS1_IMUX_B36_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_12" }, "PSS1.PSS0_IMUX_B36_13->PSS1_IMUX_B36_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_13" }, "PSS1.PSS0_IMUX_B36_14->PSS1_IMUX_B36_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_14" }, "PSS1.PSS0_IMUX_B36_15->PSS1_IMUX_B36_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_15" }, "PSS1.PSS0_IMUX_B36_16->PSS1_IMUX_B36_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_16" }, "PSS1.PSS0_IMUX_B36_17->PSS1_IMUX_B36_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_17" }, "PSS1.PSS0_IMUX_B36_18->PSS1_IMUX_B36_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_18" }, "PSS1.PSS0_IMUX_B36_19->PSS1_IMUX_B36_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_19" }, "PSS1.PSS0_IMUX_B36_2->PSS1_IMUX_B36_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_2" }, "PSS1.PSS0_IMUX_B36_3->PSS1_IMUX_B36_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_3" }, "PSS1.PSS0_IMUX_B36_4->PSS1_IMUX_B36_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_4" }, "PSS1.PSS0_IMUX_B36_5->PSS1_IMUX_B36_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_5" }, "PSS1.PSS0_IMUX_B36_6->PSS1_IMUX_B36_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_6" }, "PSS1.PSS0_IMUX_B36_7->PSS1_IMUX_B36_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_7" }, "PSS1.PSS0_IMUX_B36_8->PSS1_IMUX_B36_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_8" }, "PSS1.PSS0_IMUX_B36_9->PSS1_IMUX_B36_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_9" }, "PSS1.PSS0_IMUX_B37_0->PSS1_IMUX_B37_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_0" }, "PSS1.PSS0_IMUX_B37_1->PSS1_IMUX_B37_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_1" }, "PSS1.PSS0_IMUX_B37_10->PSS1_IMUX_B37_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_10" }, "PSS1.PSS0_IMUX_B37_11->PSS1_IMUX_B37_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_11" }, "PSS1.PSS0_IMUX_B37_12->PSS1_IMUX_B37_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_12" }, "PSS1.PSS0_IMUX_B37_13->PSS1_IMUX_B37_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_13" }, "PSS1.PSS0_IMUX_B37_14->PSS1_IMUX_B37_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_14" }, "PSS1.PSS0_IMUX_B37_15->PSS1_IMUX_B37_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_15" }, "PSS1.PSS0_IMUX_B37_16->PSS1_IMUX_B37_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_16" }, "PSS1.PSS0_IMUX_B37_17->PSS1_IMUX_B37_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_17" }, "PSS1.PSS0_IMUX_B37_18->PSS1_IMUX_B37_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_18" }, "PSS1.PSS0_IMUX_B37_19->PSS1_IMUX_B37_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_19" }, "PSS1.PSS0_IMUX_B37_2->PSS1_IMUX_B37_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_2" }, "PSS1.PSS0_IMUX_B37_3->PSS1_IMUX_B37_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_3" }, "PSS1.PSS0_IMUX_B37_4->PSS1_IMUX_B37_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_4" }, "PSS1.PSS0_IMUX_B37_5->PSS1_IMUX_B37_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_5" }, "PSS1.PSS0_IMUX_B37_6->PSS1_IMUX_B37_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_6" }, "PSS1.PSS0_IMUX_B37_7->PSS1_IMUX_B37_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_7" }, "PSS1.PSS0_IMUX_B37_8->PSS1_IMUX_B37_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_8" }, "PSS1.PSS0_IMUX_B37_9->PSS1_IMUX_B37_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_9" }, "PSS1.PSS0_IMUX_B38_0->PSS1_IMUX_B38_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_0" }, "PSS1.PSS0_IMUX_B38_1->PSS1_IMUX_B38_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_1" }, "PSS1.PSS0_IMUX_B38_10->PSS1_IMUX_B38_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_10" }, "PSS1.PSS0_IMUX_B38_11->PSS1_IMUX_B38_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_11" }, "PSS1.PSS0_IMUX_B38_12->PSS1_IMUX_B38_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_12" }, "PSS1.PSS0_IMUX_B38_13->PSS1_IMUX_B38_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_13" }, "PSS1.PSS0_IMUX_B38_14->PSS1_IMUX_B38_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_14" }, "PSS1.PSS0_IMUX_B38_15->PSS1_IMUX_B38_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_15" }, "PSS1.PSS0_IMUX_B38_16->PSS1_IMUX_B38_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_16" }, "PSS1.PSS0_IMUX_B38_17->PSS1_IMUX_B38_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_17" }, "PSS1.PSS0_IMUX_B38_18->PSS1_IMUX_B38_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_18" }, "PSS1.PSS0_IMUX_B38_19->PSS1_IMUX_B38_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_19" }, "PSS1.PSS0_IMUX_B38_2->PSS1_IMUX_B38_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_2" }, "PSS1.PSS0_IMUX_B38_3->PSS1_IMUX_B38_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_3" }, "PSS1.PSS0_IMUX_B38_4->PSS1_IMUX_B38_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_4" }, "PSS1.PSS0_IMUX_B38_5->PSS1_IMUX_B38_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_5" }, "PSS1.PSS0_IMUX_B38_6->PSS1_IMUX_B38_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_6" }, "PSS1.PSS0_IMUX_B38_7->PSS1_IMUX_B38_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_7" }, "PSS1.PSS0_IMUX_B38_8->PSS1_IMUX_B38_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_8" }, "PSS1.PSS0_IMUX_B38_9->PSS1_IMUX_B38_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_9" }, "PSS1.PSS0_IMUX_B39_0->PSS1_IMUX_B39_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_0" }, "PSS1.PSS0_IMUX_B39_1->PSS1_IMUX_B39_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_1" }, "PSS1.PSS0_IMUX_B39_10->PSS1_IMUX_B39_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_10" }, "PSS1.PSS0_IMUX_B39_11->PSS1_IMUX_B39_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_11" }, "PSS1.PSS0_IMUX_B39_12->PSS1_IMUX_B39_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_12" }, "PSS1.PSS0_IMUX_B39_13->PSS1_IMUX_B39_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_13" }, "PSS1.PSS0_IMUX_B39_14->PSS1_IMUX_B39_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_14" }, "PSS1.PSS0_IMUX_B39_15->PSS1_IMUX_B39_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_15" }, "PSS1.PSS0_IMUX_B39_16->PSS1_IMUX_B39_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_16" }, "PSS1.PSS0_IMUX_B39_17->PSS1_IMUX_B39_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_17" }, "PSS1.PSS0_IMUX_B39_18->PSS1_IMUX_B39_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_18" }, "PSS1.PSS0_IMUX_B39_19->PSS1_IMUX_B39_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_19" }, "PSS1.PSS0_IMUX_B39_2->PSS1_IMUX_B39_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_2" }, "PSS1.PSS0_IMUX_B39_3->PSS1_IMUX_B39_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_3" }, "PSS1.PSS0_IMUX_B39_4->PSS1_IMUX_B39_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_4" }, "PSS1.PSS0_IMUX_B39_5->PSS1_IMUX_B39_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_5" }, "PSS1.PSS0_IMUX_B39_6->PSS1_IMUX_B39_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_6" }, "PSS1.PSS0_IMUX_B39_7->PSS1_IMUX_B39_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_7" }, "PSS1.PSS0_IMUX_B39_8->PSS1_IMUX_B39_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_8" }, "PSS1.PSS0_IMUX_B39_9->PSS1_IMUX_B39_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_9" }, "PSS1.PSS0_IMUX_B3_0->PSS1_IMUX_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_0" }, "PSS1.PSS0_IMUX_B3_1->PSS1_IMUX_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_1" }, "PSS1.PSS0_IMUX_B3_10->PSS1_IMUX_B3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_10" }, "PSS1.PSS0_IMUX_B3_11->PSS1_IMUX_B3_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_11" }, "PSS1.PSS0_IMUX_B3_12->PSS1_IMUX_B3_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_12" }, "PSS1.PSS0_IMUX_B3_13->PSS1_IMUX_B3_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_13" }, "PSS1.PSS0_IMUX_B3_14->PSS1_IMUX_B3_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_14" }, "PSS1.PSS0_IMUX_B3_15->PSS1_IMUX_B3_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_15" }, "PSS1.PSS0_IMUX_B3_16->PSS1_IMUX_B3_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_16" }, "PSS1.PSS0_IMUX_B3_17->PSS1_IMUX_B3_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_17" }, "PSS1.PSS0_IMUX_B3_18->PSS1_IMUX_B3_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_18" }, "PSS1.PSS0_IMUX_B3_19->PSS1_IMUX_B3_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_19" }, "PSS1.PSS0_IMUX_B3_2->PSS1_IMUX_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_2" }, "PSS1.PSS0_IMUX_B3_3->PSS1_IMUX_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_3" }, "PSS1.PSS0_IMUX_B3_4->PSS1_IMUX_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_4" }, "PSS1.PSS0_IMUX_B3_5->PSS1_IMUX_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_5" }, "PSS1.PSS0_IMUX_B3_6->PSS1_IMUX_B3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_6" }, "PSS1.PSS0_IMUX_B3_7->PSS1_IMUX_B3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_7" }, "PSS1.PSS0_IMUX_B3_8->PSS1_IMUX_B3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_8" }, "PSS1.PSS0_IMUX_B3_9->PSS1_IMUX_B3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_9" }, "PSS1.PSS0_IMUX_B40_0->PSS1_IMUX_B40_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_0" }, "PSS1.PSS0_IMUX_B40_1->PSS1_IMUX_B40_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_1" }, "PSS1.PSS0_IMUX_B40_10->PSS1_IMUX_B40_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_10" }, "PSS1.PSS0_IMUX_B40_11->PSS1_IMUX_B40_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_11" }, "PSS1.PSS0_IMUX_B40_12->PSS1_IMUX_B40_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_12" }, "PSS1.PSS0_IMUX_B40_13->PSS1_IMUX_B40_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_13" }, "PSS1.PSS0_IMUX_B40_14->PSS1_IMUX_B40_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_14" }, "PSS1.PSS0_IMUX_B40_15->PSS1_IMUX_B40_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_15" }, "PSS1.PSS0_IMUX_B40_16->PSS1_IMUX_B40_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_16" }, "PSS1.PSS0_IMUX_B40_17->PSS1_IMUX_B40_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_17" }, "PSS1.PSS0_IMUX_B40_18->PSS1_IMUX_B40_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_18" }, "PSS1.PSS0_IMUX_B40_19->PSS1_IMUX_B40_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_19" }, "PSS1.PSS0_IMUX_B40_2->PSS1_IMUX_B40_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_2" }, "PSS1.PSS0_IMUX_B40_3->PSS1_IMUX_B40_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_3" }, "PSS1.PSS0_IMUX_B40_4->PSS1_IMUX_B40_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_4" }, "PSS1.PSS0_IMUX_B40_5->PSS1_IMUX_B40_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_5" }, "PSS1.PSS0_IMUX_B40_6->PSS1_IMUX_B40_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_6" }, "PSS1.PSS0_IMUX_B40_7->PSS1_IMUX_B40_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_7" }, "PSS1.PSS0_IMUX_B40_8->PSS1_IMUX_B40_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_8" }, "PSS1.PSS0_IMUX_B40_9->PSS1_IMUX_B40_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_9" }, "PSS1.PSS0_IMUX_B41_0->PSS1_IMUX_B41_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_0" }, "PSS1.PSS0_IMUX_B41_1->PSS1_IMUX_B41_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_1" }, "PSS1.PSS0_IMUX_B41_10->PSS1_IMUX_B41_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_10" }, "PSS1.PSS0_IMUX_B41_11->PSS1_IMUX_B41_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_11" }, "PSS1.PSS0_IMUX_B41_12->PSS1_IMUX_B41_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_12" }, "PSS1.PSS0_IMUX_B41_13->PSS1_IMUX_B41_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_13" }, "PSS1.PSS0_IMUX_B41_14->PSS1_IMUX_B41_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_14" }, "PSS1.PSS0_IMUX_B41_15->PSS1_IMUX_B41_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_15" }, "PSS1.PSS0_IMUX_B41_16->PSS1_IMUX_B41_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_16" }, "PSS1.PSS0_IMUX_B41_17->PSS1_IMUX_B41_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_17" }, "PSS1.PSS0_IMUX_B41_18->PSS1_IMUX_B41_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_18" }, "PSS1.PSS0_IMUX_B41_19->PSS1_IMUX_B41_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_19" }, "PSS1.PSS0_IMUX_B41_2->PSS1_IMUX_B41_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_2" }, "PSS1.PSS0_IMUX_B41_3->PSS1_IMUX_B41_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_3" }, "PSS1.PSS0_IMUX_B41_4->PSS1_IMUX_B41_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_4" }, "PSS1.PSS0_IMUX_B41_5->PSS1_IMUX_B41_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_5" }, "PSS1.PSS0_IMUX_B41_6->PSS1_IMUX_B41_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_6" }, "PSS1.PSS0_IMUX_B41_7->PSS1_IMUX_B41_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_7" }, "PSS1.PSS0_IMUX_B41_8->PSS1_IMUX_B41_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_8" }, "PSS1.PSS0_IMUX_B41_9->PSS1_IMUX_B41_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_9" }, "PSS1.PSS0_IMUX_B42_0->PSS1_IMUX_B42_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_0" }, "PSS1.PSS0_IMUX_B42_1->PSS1_IMUX_B42_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_1" }, "PSS1.PSS0_IMUX_B42_10->PSS1_IMUX_B42_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_10" }, "PSS1.PSS0_IMUX_B42_11->PSS1_IMUX_B42_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_11" }, "PSS1.PSS0_IMUX_B42_12->PSS1_IMUX_B42_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_12" }, "PSS1.PSS0_IMUX_B42_13->PSS1_IMUX_B42_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_13" }, "PSS1.PSS0_IMUX_B42_14->PSS1_IMUX_B42_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_14" }, "PSS1.PSS0_IMUX_B42_15->PSS1_IMUX_B42_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_15" }, "PSS1.PSS0_IMUX_B42_16->PSS1_IMUX_B42_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_16" }, "PSS1.PSS0_IMUX_B42_17->PSS1_IMUX_B42_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_17" }, "PSS1.PSS0_IMUX_B42_18->PSS1_IMUX_B42_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_18" }, "PSS1.PSS0_IMUX_B42_19->PSS1_IMUX_B42_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_19" }, "PSS1.PSS0_IMUX_B42_2->PSS1_IMUX_B42_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_2" }, "PSS1.PSS0_IMUX_B42_3->PSS1_IMUX_B42_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_3" }, "PSS1.PSS0_IMUX_B42_4->PSS1_IMUX_B42_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_4" }, "PSS1.PSS0_IMUX_B42_5->PSS1_IMUX_B42_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_5" }, "PSS1.PSS0_IMUX_B42_6->PSS1_IMUX_B42_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_6" }, "PSS1.PSS0_IMUX_B42_7->PSS1_IMUX_B42_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_7" }, "PSS1.PSS0_IMUX_B42_8->PSS1_IMUX_B42_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_8" }, "PSS1.PSS0_IMUX_B42_9->PSS1_IMUX_B42_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_9" }, "PSS1.PSS0_IMUX_B43_0->PSS1_IMUX_B43_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_0" }, "PSS1.PSS0_IMUX_B43_1->PSS1_IMUX_B43_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_1" }, "PSS1.PSS0_IMUX_B43_10->PSS1_IMUX_B43_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_10" }, "PSS1.PSS0_IMUX_B43_11->PSS1_IMUX_B43_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_11" }, "PSS1.PSS0_IMUX_B43_12->PSS1_IMUX_B43_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_12" }, "PSS1.PSS0_IMUX_B43_13->PSS1_IMUX_B43_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_13" }, "PSS1.PSS0_IMUX_B43_14->PSS1_IMUX_B43_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_14" }, "PSS1.PSS0_IMUX_B43_15->PSS1_IMUX_B43_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_15" }, "PSS1.PSS0_IMUX_B43_16->PSS1_IMUX_B43_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_16" }, "PSS1.PSS0_IMUX_B43_17->PSS1_IMUX_B43_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_17" }, "PSS1.PSS0_IMUX_B43_18->PSS1_IMUX_B43_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_18" }, "PSS1.PSS0_IMUX_B43_19->PSS1_IMUX_B43_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_19" }, "PSS1.PSS0_IMUX_B43_2->PSS1_IMUX_B43_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_2" }, "PSS1.PSS0_IMUX_B43_3->PSS1_IMUX_B43_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_3" }, "PSS1.PSS0_IMUX_B43_4->PSS1_IMUX_B43_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_4" }, "PSS1.PSS0_IMUX_B43_5->PSS1_IMUX_B43_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_5" }, "PSS1.PSS0_IMUX_B43_6->PSS1_IMUX_B43_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_6" }, "PSS1.PSS0_IMUX_B43_7->PSS1_IMUX_B43_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_7" }, "PSS1.PSS0_IMUX_B43_8->PSS1_IMUX_B43_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_8" }, "PSS1.PSS0_IMUX_B43_9->PSS1_IMUX_B43_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_9" }, "PSS1.PSS0_IMUX_B44_0->PSS1_IMUX_B44_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_0" }, "PSS1.PSS0_IMUX_B44_1->PSS1_IMUX_B44_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_1" }, "PSS1.PSS0_IMUX_B44_10->PSS1_IMUX_B44_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_10" }, "PSS1.PSS0_IMUX_B44_11->PSS1_IMUX_B44_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_11" }, "PSS1.PSS0_IMUX_B44_12->PSS1_IMUX_B44_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_12" }, "PSS1.PSS0_IMUX_B44_13->PSS1_IMUX_B44_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_13" }, "PSS1.PSS0_IMUX_B44_14->PSS1_IMUX_B44_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_14" }, "PSS1.PSS0_IMUX_B44_15->PSS1_IMUX_B44_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_15" }, "PSS1.PSS0_IMUX_B44_16->PSS1_IMUX_B44_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_16" }, "PSS1.PSS0_IMUX_B44_17->PSS1_IMUX_B44_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_17" }, "PSS1.PSS0_IMUX_B44_18->PSS1_IMUX_B44_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_18" }, "PSS1.PSS0_IMUX_B44_19->PSS1_IMUX_B44_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_19" }, "PSS1.PSS0_IMUX_B44_2->PSS1_IMUX_B44_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_2" }, "PSS1.PSS0_IMUX_B44_3->PSS1_IMUX_B44_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_3" }, "PSS1.PSS0_IMUX_B44_4->PSS1_IMUX_B44_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_4" }, "PSS1.PSS0_IMUX_B44_5->PSS1_IMUX_B44_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_5" }, "PSS1.PSS0_IMUX_B44_6->PSS1_IMUX_B44_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_6" }, "PSS1.PSS0_IMUX_B44_7->PSS1_IMUX_B44_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_7" }, "PSS1.PSS0_IMUX_B44_8->PSS1_IMUX_B44_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_8" }, "PSS1.PSS0_IMUX_B44_9->PSS1_IMUX_B44_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_9" }, "PSS1.PSS0_IMUX_B45_0->PSS1_IMUX_B45_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_0" }, "PSS1.PSS0_IMUX_B45_1->PSS1_IMUX_B45_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_1" }, "PSS1.PSS0_IMUX_B45_10->PSS1_IMUX_B45_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_10" }, "PSS1.PSS0_IMUX_B45_11->PSS1_IMUX_B45_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_11" }, "PSS1.PSS0_IMUX_B45_12->PSS1_IMUX_B45_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_12" }, "PSS1.PSS0_IMUX_B45_13->PSS1_IMUX_B45_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_13" }, "PSS1.PSS0_IMUX_B45_14->PSS1_IMUX_B45_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_14" }, "PSS1.PSS0_IMUX_B45_15->PSS1_IMUX_B45_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_15" }, "PSS1.PSS0_IMUX_B45_16->PSS1_IMUX_B45_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_16" }, "PSS1.PSS0_IMUX_B45_17->PSS1_IMUX_B45_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_17" }, "PSS1.PSS0_IMUX_B45_18->PSS1_IMUX_B45_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_18" }, "PSS1.PSS0_IMUX_B45_19->PSS1_IMUX_B45_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_19" }, "PSS1.PSS0_IMUX_B45_2->PSS1_IMUX_B45_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_2" }, "PSS1.PSS0_IMUX_B45_3->PSS1_IMUX_B45_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_3" }, "PSS1.PSS0_IMUX_B45_4->PSS1_IMUX_B45_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_4" }, "PSS1.PSS0_IMUX_B45_5->PSS1_IMUX_B45_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_5" }, "PSS1.PSS0_IMUX_B45_6->PSS1_IMUX_B45_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_6" }, "PSS1.PSS0_IMUX_B45_7->PSS1_IMUX_B45_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_7" }, "PSS1.PSS0_IMUX_B45_8->PSS1_IMUX_B45_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_8" }, "PSS1.PSS0_IMUX_B45_9->PSS1_IMUX_B45_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_9" }, "PSS1.PSS0_IMUX_B46_0->PSS1_IMUX_B46_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_0" }, "PSS1.PSS0_IMUX_B46_1->PSS1_IMUX_B46_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_1" }, "PSS1.PSS0_IMUX_B46_10->PSS1_IMUX_B46_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_10" }, "PSS1.PSS0_IMUX_B46_11->PSS1_IMUX_B46_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_11" }, "PSS1.PSS0_IMUX_B46_12->PSS1_IMUX_B46_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_12" }, "PSS1.PSS0_IMUX_B46_13->PSS1_IMUX_B46_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_13" }, "PSS1.PSS0_IMUX_B46_14->PSS1_IMUX_B46_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_14" }, "PSS1.PSS0_IMUX_B46_15->PSS1_IMUX_B46_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_15" }, "PSS1.PSS0_IMUX_B46_16->PSS1_IMUX_B46_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_16" }, "PSS1.PSS0_IMUX_B46_17->PSS1_IMUX_B46_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_17" }, "PSS1.PSS0_IMUX_B46_18->PSS1_IMUX_B46_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_18" }, "PSS1.PSS0_IMUX_B46_19->PSS1_IMUX_B46_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_19" }, "PSS1.PSS0_IMUX_B46_2->PSS1_IMUX_B46_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_2" }, "PSS1.PSS0_IMUX_B46_3->PSS1_IMUX_B46_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_3" }, "PSS1.PSS0_IMUX_B46_4->PSS1_IMUX_B46_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_4" }, "PSS1.PSS0_IMUX_B46_5->PSS1_IMUX_B46_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_5" }, "PSS1.PSS0_IMUX_B46_6->PSS1_IMUX_B46_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_6" }, "PSS1.PSS0_IMUX_B46_7->PSS1_IMUX_B46_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_7" }, "PSS1.PSS0_IMUX_B46_8->PSS1_IMUX_B46_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_8" }, "PSS1.PSS0_IMUX_B46_9->PSS1_IMUX_B46_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_9" }, "PSS1.PSS0_IMUX_B47_0->PSS1_IMUX_B47_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_0" }, "PSS1.PSS0_IMUX_B47_1->PSS1_IMUX_B47_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_1" }, "PSS1.PSS0_IMUX_B47_10->PSS1_IMUX_B47_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_10" }, "PSS1.PSS0_IMUX_B47_11->PSS1_IMUX_B47_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_11" }, "PSS1.PSS0_IMUX_B47_12->PSS1_IMUX_B47_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_12" }, "PSS1.PSS0_IMUX_B47_13->PSS1_IMUX_B47_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_13" }, "PSS1.PSS0_IMUX_B47_14->PSS1_IMUX_B47_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_14" }, "PSS1.PSS0_IMUX_B47_15->PSS1_IMUX_B47_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_15" }, "PSS1.PSS0_IMUX_B47_16->PSS1_IMUX_B47_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_16" }, "PSS1.PSS0_IMUX_B47_17->PSS1_IMUX_B47_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_17" }, "PSS1.PSS0_IMUX_B47_18->PSS1_IMUX_B47_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_18" }, "PSS1.PSS0_IMUX_B47_19->PSS1_IMUX_B47_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_19" }, "PSS1.PSS0_IMUX_B47_2->PSS1_IMUX_B47_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_2" }, "PSS1.PSS0_IMUX_B47_3->PSS1_IMUX_B47_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_3" }, "PSS1.PSS0_IMUX_B47_4->PSS1_IMUX_B47_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_4" }, "PSS1.PSS0_IMUX_B47_5->PSS1_IMUX_B47_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_5" }, "PSS1.PSS0_IMUX_B47_6->PSS1_IMUX_B47_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_6" }, "PSS1.PSS0_IMUX_B47_7->PSS1_IMUX_B47_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_7" }, "PSS1.PSS0_IMUX_B47_8->PSS1_IMUX_B47_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_8" }, "PSS1.PSS0_IMUX_B47_9->PSS1_IMUX_B47_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_9" }, "PSS1.PSS0_IMUX_B4_0->PSS1_IMUX_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_0" }, "PSS1.PSS0_IMUX_B4_1->PSS1_IMUX_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_1" }, "PSS1.PSS0_IMUX_B4_10->PSS1_IMUX_B4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_10" }, "PSS1.PSS0_IMUX_B4_11->PSS1_IMUX_B4_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_11" }, "PSS1.PSS0_IMUX_B4_12->PSS1_IMUX_B4_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_12" }, "PSS1.PSS0_IMUX_B4_13->PSS1_IMUX_B4_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_13" }, "PSS1.PSS0_IMUX_B4_14->PSS1_IMUX_B4_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_14" }, "PSS1.PSS0_IMUX_B4_15->PSS1_IMUX_B4_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_15" }, "PSS1.PSS0_IMUX_B4_16->PSS1_IMUX_B4_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_16" }, "PSS1.PSS0_IMUX_B4_17->PSS1_IMUX_B4_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_17" }, "PSS1.PSS0_IMUX_B4_18->PSS1_IMUX_B4_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_18" }, "PSS1.PSS0_IMUX_B4_19->PSS1_IMUX_B4_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_19" }, "PSS1.PSS0_IMUX_B4_2->PSS1_IMUX_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_2" }, "PSS1.PSS0_IMUX_B4_3->PSS1_IMUX_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_3" }, "PSS1.PSS0_IMUX_B4_4->PSS1_IMUX_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_4" }, "PSS1.PSS0_IMUX_B4_5->PSS1_IMUX_B4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_5" }, "PSS1.PSS0_IMUX_B4_6->PSS1_IMUX_B4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_6" }, "PSS1.PSS0_IMUX_B4_7->PSS1_IMUX_B4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_7" }, "PSS1.PSS0_IMUX_B4_8->PSS1_IMUX_B4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_8" }, "PSS1.PSS0_IMUX_B4_9->PSS1_IMUX_B4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_9" }, "PSS1.PSS0_IMUX_B5_0->PSS1_IMUX_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_0" }, "PSS1.PSS0_IMUX_B5_1->PSS1_IMUX_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_1" }, "PSS1.PSS0_IMUX_B5_10->PSS1_IMUX_B5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_10" }, "PSS1.PSS0_IMUX_B5_11->PSS1_IMUX_B5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_11" }, "PSS1.PSS0_IMUX_B5_12->PSS1_IMUX_B5_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_12" }, "PSS1.PSS0_IMUX_B5_13->PSS1_IMUX_B5_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_13" }, "PSS1.PSS0_IMUX_B5_14->PSS1_IMUX_B5_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_14" }, "PSS1.PSS0_IMUX_B5_15->PSS1_IMUX_B5_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_15" }, "PSS1.PSS0_IMUX_B5_16->PSS1_IMUX_B5_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_16" }, "PSS1.PSS0_IMUX_B5_17->PSS1_IMUX_B5_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_17" }, "PSS1.PSS0_IMUX_B5_18->PSS1_IMUX_B5_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_18" }, "PSS1.PSS0_IMUX_B5_19->PSS1_IMUX_B5_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_19" }, "PSS1.PSS0_IMUX_B5_2->PSS1_IMUX_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_2" }, "PSS1.PSS0_IMUX_B5_3->PSS1_IMUX_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_3" }, "PSS1.PSS0_IMUX_B5_4->PSS1_IMUX_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_4" }, "PSS1.PSS0_IMUX_B5_5->PSS1_IMUX_B5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_5" }, "PSS1.PSS0_IMUX_B5_6->PSS1_IMUX_B5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_6" }, "PSS1.PSS0_IMUX_B5_7->PSS1_IMUX_B5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_7" }, "PSS1.PSS0_IMUX_B5_8->PSS1_IMUX_B5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_8" }, "PSS1.PSS0_IMUX_B5_9->PSS1_IMUX_B5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_9" }, "PSS1.PSS0_IMUX_B6_0->PSS1_IMUX_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_0" }, "PSS1.PSS0_IMUX_B6_1->PSS1_IMUX_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_1" }, "PSS1.PSS0_IMUX_B6_10->PSS1_IMUX_B6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_10" }, "PSS1.PSS0_IMUX_B6_11->PSS1_IMUX_B6_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_11" }, "PSS1.PSS0_IMUX_B6_12->PSS1_IMUX_B6_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_12" }, "PSS1.PSS0_IMUX_B6_13->PSS1_IMUX_B6_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_13" }, "PSS1.PSS0_IMUX_B6_14->PSS1_IMUX_B6_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_14" }, "PSS1.PSS0_IMUX_B6_15->PSS1_IMUX_B6_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_15" }, "PSS1.PSS0_IMUX_B6_16->PSS1_IMUX_B6_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_16" }, "PSS1.PSS0_IMUX_B6_17->PSS1_IMUX_B6_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_17" }, "PSS1.PSS0_IMUX_B6_18->PSS1_IMUX_B6_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_18" }, "PSS1.PSS0_IMUX_B6_19->PSS1_IMUX_B6_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_19" }, "PSS1.PSS0_IMUX_B6_2->PSS1_IMUX_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_2" }, "PSS1.PSS0_IMUX_B6_3->PSS1_IMUX_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_3" }, "PSS1.PSS0_IMUX_B6_4->PSS1_IMUX_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_4" }, "PSS1.PSS0_IMUX_B6_5->PSS1_IMUX_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_5" }, "PSS1.PSS0_IMUX_B6_6->PSS1_IMUX_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_6" }, "PSS1.PSS0_IMUX_B6_7->PSS1_IMUX_B6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_7" }, "PSS1.PSS0_IMUX_B6_8->PSS1_IMUX_B6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_8" }, "PSS1.PSS0_IMUX_B6_9->PSS1_IMUX_B6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_9" }, "PSS1.PSS0_IMUX_B7_0->PSS1_IMUX_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_0" }, "PSS1.PSS0_IMUX_B7_1->PSS1_IMUX_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_1" }, "PSS1.PSS0_IMUX_B7_10->PSS1_IMUX_B7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_10" }, "PSS1.PSS0_IMUX_B7_11->PSS1_IMUX_B7_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_11" }, "PSS1.PSS0_IMUX_B7_12->PSS1_IMUX_B7_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_12" }, "PSS1.PSS0_IMUX_B7_13->PSS1_IMUX_B7_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_13" }, "PSS1.PSS0_IMUX_B7_14->PSS1_IMUX_B7_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_14" }, "PSS1.PSS0_IMUX_B7_15->PSS1_IMUX_B7_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_15" }, "PSS1.PSS0_IMUX_B7_16->PSS1_IMUX_B7_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_16" }, "PSS1.PSS0_IMUX_B7_17->PSS1_IMUX_B7_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_17" }, "PSS1.PSS0_IMUX_B7_18->PSS1_IMUX_B7_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_18" }, "PSS1.PSS0_IMUX_B7_19->PSS1_IMUX_B7_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_19" }, "PSS1.PSS0_IMUX_B7_2->PSS1_IMUX_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_2" }, "PSS1.PSS0_IMUX_B7_3->PSS1_IMUX_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_3" }, "PSS1.PSS0_IMUX_B7_4->PSS1_IMUX_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_4" }, "PSS1.PSS0_IMUX_B7_5->PSS1_IMUX_B7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_5" }, "PSS1.PSS0_IMUX_B7_6->PSS1_IMUX_B7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_6" }, "PSS1.PSS0_IMUX_B7_7->PSS1_IMUX_B7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_7" }, "PSS1.PSS0_IMUX_B7_8->PSS1_IMUX_B7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_8" }, "PSS1.PSS0_IMUX_B7_9->PSS1_IMUX_B7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_9" }, "PSS1.PSS0_IMUX_B8_0->PSS1_IMUX_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_0" }, "PSS1.PSS0_IMUX_B8_1->PSS1_IMUX_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_1" }, "PSS1.PSS0_IMUX_B8_10->PSS1_IMUX_B8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_10" }, "PSS1.PSS0_IMUX_B8_11->PSS1_IMUX_B8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_11" }, "PSS1.PSS0_IMUX_B8_12->PSS1_IMUX_B8_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_12" }, "PSS1.PSS0_IMUX_B8_13->PSS1_IMUX_B8_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_13" }, "PSS1.PSS0_IMUX_B8_14->PSS1_IMUX_B8_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_14" }, "PSS1.PSS0_IMUX_B8_15->PSS1_IMUX_B8_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_15" }, "PSS1.PSS0_IMUX_B8_16->PSS1_IMUX_B8_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_16" }, "PSS1.PSS0_IMUX_B8_17->PSS1_IMUX_B8_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_17" }, "PSS1.PSS0_IMUX_B8_18->PSS1_IMUX_B8_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_18" }, "PSS1.PSS0_IMUX_B8_19->PSS1_IMUX_B8_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_19" }, "PSS1.PSS0_IMUX_B8_2->PSS1_IMUX_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_2" }, "PSS1.PSS0_IMUX_B8_3->PSS1_IMUX_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_3" }, "PSS1.PSS0_IMUX_B8_4->PSS1_IMUX_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_4" }, "PSS1.PSS0_IMUX_B8_5->PSS1_IMUX_B8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_5" }, "PSS1.PSS0_IMUX_B8_6->PSS1_IMUX_B8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_6" }, "PSS1.PSS0_IMUX_B8_7->PSS1_IMUX_B8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_7" }, "PSS1.PSS0_IMUX_B8_8->PSS1_IMUX_B8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_8" }, "PSS1.PSS0_IMUX_B8_9->PSS1_IMUX_B8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_9" }, "PSS1.PSS0_IMUX_B9_0->PSS1_IMUX_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_0" }, "PSS1.PSS0_IMUX_B9_1->PSS1_IMUX_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_1" }, "PSS1.PSS0_IMUX_B9_10->PSS1_IMUX_B9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_10" }, "PSS1.PSS0_IMUX_B9_11->PSS1_IMUX_B9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_11" }, "PSS1.PSS0_IMUX_B9_12->PSS1_IMUX_B9_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_12" }, "PSS1.PSS0_IMUX_B9_13->PSS1_IMUX_B9_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_13" }, "PSS1.PSS0_IMUX_B9_14->PSS1_IMUX_B9_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_14" }, "PSS1.PSS0_IMUX_B9_15->PSS1_IMUX_B9_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_15" }, "PSS1.PSS0_IMUX_B9_16->PSS1_IMUX_B9_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_16" }, "PSS1.PSS0_IMUX_B9_17->PSS1_IMUX_B9_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_17" }, "PSS1.PSS0_IMUX_B9_18->PSS1_IMUX_B9_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_18" }, "PSS1.PSS0_IMUX_B9_19->PSS1_IMUX_B9_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_19" }, "PSS1.PSS0_IMUX_B9_2->PSS1_IMUX_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_2" }, "PSS1.PSS0_IMUX_B9_3->PSS1_IMUX_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_3" }, "PSS1.PSS0_IMUX_B9_4->PSS1_IMUX_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_4" }, "PSS1.PSS0_IMUX_B9_5->PSS1_IMUX_B9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_5" }, "PSS1.PSS0_IMUX_B9_6->PSS1_IMUX_B9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_6" }, "PSS1.PSS0_IMUX_B9_7->PSS1_IMUX_B9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_7" }, "PSS1.PSS0_IMUX_B9_8->PSS1_IMUX_B9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_8" }, "PSS1.PSS0_IMUX_B9_9->PSS1_IMUX_B9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_9" }, "PSS1.PSS1_LOGIC_OUTS0_0->PSS0_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_0" }, "PSS1.PSS1_LOGIC_OUTS0_1->PSS0_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_1" }, "PSS1.PSS1_LOGIC_OUTS0_10->PSS0_LOGIC_OUTS0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_10" }, "PSS1.PSS1_LOGIC_OUTS0_11->PSS0_LOGIC_OUTS0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_11" }, "PSS1.PSS1_LOGIC_OUTS0_12->PSS0_LOGIC_OUTS0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_12" }, "PSS1.PSS1_LOGIC_OUTS0_13->PSS0_LOGIC_OUTS0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_13" }, "PSS1.PSS1_LOGIC_OUTS0_14->PSS0_LOGIC_OUTS0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_14" }, "PSS1.PSS1_LOGIC_OUTS0_15->PSS0_LOGIC_OUTS0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_15" }, "PSS1.PSS1_LOGIC_OUTS0_16->PSS0_LOGIC_OUTS0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_16" }, "PSS1.PSS1_LOGIC_OUTS0_17->PSS0_LOGIC_OUTS0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_17" }, "PSS1.PSS1_LOGIC_OUTS0_18->PSS0_LOGIC_OUTS0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_18" }, "PSS1.PSS1_LOGIC_OUTS0_19->PSS0_LOGIC_OUTS0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_19" }, "PSS1.PSS1_LOGIC_OUTS0_2->PSS0_LOGIC_OUTS0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_2" }, "PSS1.PSS1_LOGIC_OUTS0_20->PSS_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_20" }, "PSS1.PSS1_LOGIC_OUTS0_21->PSS_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_21" }, "PSS1.PSS1_LOGIC_OUTS0_22->PSS_LOGIC_OUTS0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_22" }, "PSS1.PSS1_LOGIC_OUTS0_23->PSS_LOGIC_OUTS0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_23" }, "PSS1.PSS1_LOGIC_OUTS0_24->PSS_LOGIC_OUTS0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_24" }, "PSS1.PSS1_LOGIC_OUTS0_25->PSS_LOGIC_OUTS0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_25" }, "PSS1.PSS1_LOGIC_OUTS0_26->PSS_LOGIC_OUTS0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_26" }, "PSS1.PSS1_LOGIC_OUTS0_27->PSS_LOGIC_OUTS0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_27" }, "PSS1.PSS1_LOGIC_OUTS0_28->PSS_LOGIC_OUTS0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_28" }, "PSS1.PSS1_LOGIC_OUTS0_29->PSS_LOGIC_OUTS0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_29" }, "PSS1.PSS1_LOGIC_OUTS0_3->PSS0_LOGIC_OUTS0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_3" }, "PSS1.PSS1_LOGIC_OUTS0_30->PSS_LOGIC_OUTS0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_30" }, "PSS1.PSS1_LOGIC_OUTS0_31->PSS_LOGIC_OUTS0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_31" }, "PSS1.PSS1_LOGIC_OUTS0_32->PSS_LOGIC_OUTS0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_32" }, "PSS1.PSS1_LOGIC_OUTS0_33->PSS_LOGIC_OUTS0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_33" }, "PSS1.PSS1_LOGIC_OUTS0_34->PSS_LOGIC_OUTS0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_34" }, "PSS1.PSS1_LOGIC_OUTS0_35->PSS_LOGIC_OUTS0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_35" }, "PSS1.PSS1_LOGIC_OUTS0_36->PSS_LOGIC_OUTS0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_36" }, "PSS1.PSS1_LOGIC_OUTS0_37->PSS_LOGIC_OUTS0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_37" }, "PSS1.PSS1_LOGIC_OUTS0_38->PSS_LOGIC_OUTS0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_38" }, "PSS1.PSS1_LOGIC_OUTS0_39->PSS_LOGIC_OUTS0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_39" }, "PSS1.PSS1_LOGIC_OUTS0_4->PSS0_LOGIC_OUTS0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_4" }, "PSS1.PSS1_LOGIC_OUTS0_5->PSS0_LOGIC_OUTS0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_5" }, "PSS1.PSS1_LOGIC_OUTS0_6->PSS0_LOGIC_OUTS0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_6" }, "PSS1.PSS1_LOGIC_OUTS0_7->PSS0_LOGIC_OUTS0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_7" }, "PSS1.PSS1_LOGIC_OUTS0_8->PSS0_LOGIC_OUTS0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_8" }, "PSS1.PSS1_LOGIC_OUTS0_9->PSS0_LOGIC_OUTS0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_9" }, "PSS1.PSS1_LOGIC_OUTS10_0->PSS0_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_0" }, "PSS1.PSS1_LOGIC_OUTS10_1->PSS0_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_1" }, "PSS1.PSS1_LOGIC_OUTS10_10->PSS0_LOGIC_OUTS10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_10" }, "PSS1.PSS1_LOGIC_OUTS10_11->PSS0_LOGIC_OUTS10_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_11" }, "PSS1.PSS1_LOGIC_OUTS10_12->PSS0_LOGIC_OUTS10_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_12" }, "PSS1.PSS1_LOGIC_OUTS10_13->PSS0_LOGIC_OUTS10_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_13" }, "PSS1.PSS1_LOGIC_OUTS10_14->PSS0_LOGIC_OUTS10_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_14" }, "PSS1.PSS1_LOGIC_OUTS10_15->PSS0_LOGIC_OUTS10_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_15" }, "PSS1.PSS1_LOGIC_OUTS10_16->PSS0_LOGIC_OUTS10_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_16" }, "PSS1.PSS1_LOGIC_OUTS10_17->PSS0_LOGIC_OUTS10_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_17" }, "PSS1.PSS1_LOGIC_OUTS10_18->PSS0_LOGIC_OUTS10_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_18" }, "PSS1.PSS1_LOGIC_OUTS10_19->PSS0_LOGIC_OUTS10_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_19" }, "PSS1.PSS1_LOGIC_OUTS10_2->PSS0_LOGIC_OUTS10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_2" }, "PSS1.PSS1_LOGIC_OUTS10_20->PSS_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_20" }, "PSS1.PSS1_LOGIC_OUTS10_21->PSS_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_21" }, "PSS1.PSS1_LOGIC_OUTS10_22->PSS_LOGIC_OUTS10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_22" }, "PSS1.PSS1_LOGIC_OUTS10_23->PSS_LOGIC_OUTS10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_23" }, "PSS1.PSS1_LOGIC_OUTS10_24->PSS_LOGIC_OUTS10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_24" }, "PSS1.PSS1_LOGIC_OUTS10_25->PSS_LOGIC_OUTS10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_25" }, "PSS1.PSS1_LOGIC_OUTS10_26->PSS_LOGIC_OUTS10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_26" }, "PSS1.PSS1_LOGIC_OUTS10_27->PSS_LOGIC_OUTS10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_27" }, "PSS1.PSS1_LOGIC_OUTS10_28->PSS_LOGIC_OUTS10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_28" }, "PSS1.PSS1_LOGIC_OUTS10_29->PSS_LOGIC_OUTS10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_29" }, "PSS1.PSS1_LOGIC_OUTS10_3->PSS0_LOGIC_OUTS10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_3" }, "PSS1.PSS1_LOGIC_OUTS10_30->PSS_LOGIC_OUTS10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_30" }, "PSS1.PSS1_LOGIC_OUTS10_31->PSS_LOGIC_OUTS10_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_31" }, "PSS1.PSS1_LOGIC_OUTS10_32->PSS_LOGIC_OUTS10_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_32" }, "PSS1.PSS1_LOGIC_OUTS10_33->PSS_LOGIC_OUTS10_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_33" }, "PSS1.PSS1_LOGIC_OUTS10_34->PSS_LOGIC_OUTS10_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_34" }, "PSS1.PSS1_LOGIC_OUTS10_35->PSS_LOGIC_OUTS10_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_35" }, "PSS1.PSS1_LOGIC_OUTS10_36->PSS_LOGIC_OUTS10_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_36" }, "PSS1.PSS1_LOGIC_OUTS10_37->PSS_LOGIC_OUTS10_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_37" }, "PSS1.PSS1_LOGIC_OUTS10_38->PSS_LOGIC_OUTS10_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_38" }, "PSS1.PSS1_LOGIC_OUTS10_39->PSS_LOGIC_OUTS10_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_39" }, "PSS1.PSS1_LOGIC_OUTS10_4->PSS0_LOGIC_OUTS10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_4" }, "PSS1.PSS1_LOGIC_OUTS10_5->PSS0_LOGIC_OUTS10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_5" }, "PSS1.PSS1_LOGIC_OUTS10_6->PSS0_LOGIC_OUTS10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_6" }, "PSS1.PSS1_LOGIC_OUTS10_7->PSS0_LOGIC_OUTS10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_7" }, "PSS1.PSS1_LOGIC_OUTS10_8->PSS0_LOGIC_OUTS10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_8" }, "PSS1.PSS1_LOGIC_OUTS10_9->PSS0_LOGIC_OUTS10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_9" }, "PSS1.PSS1_LOGIC_OUTS11_0->PSS0_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_0" }, "PSS1.PSS1_LOGIC_OUTS11_1->PSS0_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_1" }, "PSS1.PSS1_LOGIC_OUTS11_10->PSS0_LOGIC_OUTS11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_10" }, "PSS1.PSS1_LOGIC_OUTS11_11->PSS0_LOGIC_OUTS11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_11" }, "PSS1.PSS1_LOGIC_OUTS11_12->PSS0_LOGIC_OUTS11_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_12" }, "PSS1.PSS1_LOGIC_OUTS11_13->PSS0_LOGIC_OUTS11_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_13" }, "PSS1.PSS1_LOGIC_OUTS11_14->PSS0_LOGIC_OUTS11_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_14" }, "PSS1.PSS1_LOGIC_OUTS11_15->PSS0_LOGIC_OUTS11_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_15" }, "PSS1.PSS1_LOGIC_OUTS11_16->PSS0_LOGIC_OUTS11_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_16" }, "PSS1.PSS1_LOGIC_OUTS11_17->PSS0_LOGIC_OUTS11_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_17" }, "PSS1.PSS1_LOGIC_OUTS11_18->PSS0_LOGIC_OUTS11_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_18" }, "PSS1.PSS1_LOGIC_OUTS11_19->PSS0_LOGIC_OUTS11_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_19" }, "PSS1.PSS1_LOGIC_OUTS11_2->PSS0_LOGIC_OUTS11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_2" }, "PSS1.PSS1_LOGIC_OUTS11_20->PSS_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_20" }, "PSS1.PSS1_LOGIC_OUTS11_21->PSS_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_21" }, "PSS1.PSS1_LOGIC_OUTS11_22->PSS_LOGIC_OUTS11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_22" }, "PSS1.PSS1_LOGIC_OUTS11_23->PSS_LOGIC_OUTS11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_23" }, "PSS1.PSS1_LOGIC_OUTS11_24->PSS_LOGIC_OUTS11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_24" }, "PSS1.PSS1_LOGIC_OUTS11_25->PSS_LOGIC_OUTS11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_25" }, "PSS1.PSS1_LOGIC_OUTS11_26->PSS_LOGIC_OUTS11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_26" }, "PSS1.PSS1_LOGIC_OUTS11_27->PSS_LOGIC_OUTS11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_27" }, "PSS1.PSS1_LOGIC_OUTS11_28->PSS_LOGIC_OUTS11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_28" }, "PSS1.PSS1_LOGIC_OUTS11_29->PSS_LOGIC_OUTS11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_29" }, "PSS1.PSS1_LOGIC_OUTS11_3->PSS0_LOGIC_OUTS11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_3" }, "PSS1.PSS1_LOGIC_OUTS11_30->PSS_LOGIC_OUTS11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_30" }, "PSS1.PSS1_LOGIC_OUTS11_31->PSS_LOGIC_OUTS11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_31" }, "PSS1.PSS1_LOGIC_OUTS11_32->PSS_LOGIC_OUTS11_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_32" }, "PSS1.PSS1_LOGIC_OUTS11_33->PSS_LOGIC_OUTS11_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_33" }, "PSS1.PSS1_LOGIC_OUTS11_34->PSS_LOGIC_OUTS11_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_34" }, "PSS1.PSS1_LOGIC_OUTS11_35->PSS_LOGIC_OUTS11_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_35" }, "PSS1.PSS1_LOGIC_OUTS11_36->PSS_LOGIC_OUTS11_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_36" }, "PSS1.PSS1_LOGIC_OUTS11_37->PSS_LOGIC_OUTS11_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_37" }, "PSS1.PSS1_LOGIC_OUTS11_38->PSS_LOGIC_OUTS11_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_38" }, "PSS1.PSS1_LOGIC_OUTS11_39->PSS_LOGIC_OUTS11_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_39" }, "PSS1.PSS1_LOGIC_OUTS11_4->PSS0_LOGIC_OUTS11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_4" }, "PSS1.PSS1_LOGIC_OUTS11_5->PSS0_LOGIC_OUTS11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_5" }, "PSS1.PSS1_LOGIC_OUTS11_6->PSS0_LOGIC_OUTS11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_6" }, "PSS1.PSS1_LOGIC_OUTS11_7->PSS0_LOGIC_OUTS11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_7" }, "PSS1.PSS1_LOGIC_OUTS11_8->PSS0_LOGIC_OUTS11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_8" }, "PSS1.PSS1_LOGIC_OUTS11_9->PSS0_LOGIC_OUTS11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_9" }, "PSS1.PSS1_LOGIC_OUTS12_0->PSS0_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_0" }, "PSS1.PSS1_LOGIC_OUTS12_1->PSS0_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_1" }, "PSS1.PSS1_LOGIC_OUTS12_10->PSS0_LOGIC_OUTS12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_10" }, "PSS1.PSS1_LOGIC_OUTS12_11->PSS0_LOGIC_OUTS12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_11" }, "PSS1.PSS1_LOGIC_OUTS12_12->PSS0_LOGIC_OUTS12_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_12" }, "PSS1.PSS1_LOGIC_OUTS12_13->PSS0_LOGIC_OUTS12_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_13" }, "PSS1.PSS1_LOGIC_OUTS12_14->PSS0_LOGIC_OUTS12_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_14" }, "PSS1.PSS1_LOGIC_OUTS12_15->PSS0_LOGIC_OUTS12_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_15" }, "PSS1.PSS1_LOGIC_OUTS12_16->PSS0_LOGIC_OUTS12_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_16" }, "PSS1.PSS1_LOGIC_OUTS12_17->PSS0_LOGIC_OUTS12_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_17" }, "PSS1.PSS1_LOGIC_OUTS12_18->PSS0_LOGIC_OUTS12_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_18" }, "PSS1.PSS1_LOGIC_OUTS12_19->PSS0_LOGIC_OUTS12_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_19" }, "PSS1.PSS1_LOGIC_OUTS12_2->PSS0_LOGIC_OUTS12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_2" }, "PSS1.PSS1_LOGIC_OUTS12_20->PSS_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_20" }, "PSS1.PSS1_LOGIC_OUTS12_21->PSS_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_21" }, "PSS1.PSS1_LOGIC_OUTS12_22->PSS_LOGIC_OUTS12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_22" }, "PSS1.PSS1_LOGIC_OUTS12_23->PSS_LOGIC_OUTS12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_23" }, "PSS1.PSS1_LOGIC_OUTS12_24->PSS_LOGIC_OUTS12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_24" }, "PSS1.PSS1_LOGIC_OUTS12_25->PSS_LOGIC_OUTS12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_25" }, "PSS1.PSS1_LOGIC_OUTS12_26->PSS_LOGIC_OUTS12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_26" }, "PSS1.PSS1_LOGIC_OUTS12_27->PSS_LOGIC_OUTS12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_27" }, "PSS1.PSS1_LOGIC_OUTS12_28->PSS_LOGIC_OUTS12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_28" }, "PSS1.PSS1_LOGIC_OUTS12_29->PSS_LOGIC_OUTS12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_29" }, "PSS1.PSS1_LOGIC_OUTS12_3->PSS0_LOGIC_OUTS12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_3" }, "PSS1.PSS1_LOGIC_OUTS12_30->PSS_LOGIC_OUTS12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_30" }, "PSS1.PSS1_LOGIC_OUTS12_31->PSS_LOGIC_OUTS12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_31" }, "PSS1.PSS1_LOGIC_OUTS12_32->PSS_LOGIC_OUTS12_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_32" }, "PSS1.PSS1_LOGIC_OUTS12_33->PSS_LOGIC_OUTS12_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_33" }, "PSS1.PSS1_LOGIC_OUTS12_34->PSS_LOGIC_OUTS12_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_34" }, "PSS1.PSS1_LOGIC_OUTS12_35->PSS_LOGIC_OUTS12_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_35" }, "PSS1.PSS1_LOGIC_OUTS12_36->PSS_LOGIC_OUTS12_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_36" }, "PSS1.PSS1_LOGIC_OUTS12_37->PSS_LOGIC_OUTS12_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_37" }, "PSS1.PSS1_LOGIC_OUTS12_38->PSS_LOGIC_OUTS12_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_38" }, "PSS1.PSS1_LOGIC_OUTS12_39->PSS_LOGIC_OUTS12_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_39" }, "PSS1.PSS1_LOGIC_OUTS12_4->PSS0_LOGIC_OUTS12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_4" }, "PSS1.PSS1_LOGIC_OUTS12_5->PSS0_LOGIC_OUTS12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_5" }, "PSS1.PSS1_LOGIC_OUTS12_6->PSS0_LOGIC_OUTS12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_6" }, "PSS1.PSS1_LOGIC_OUTS12_7->PSS0_LOGIC_OUTS12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_7" }, "PSS1.PSS1_LOGIC_OUTS12_8->PSS0_LOGIC_OUTS12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_8" }, "PSS1.PSS1_LOGIC_OUTS12_9->PSS0_LOGIC_OUTS12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_9" }, "PSS1.PSS1_LOGIC_OUTS13_0->PSS0_LOGIC_OUTS13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_0" }, "PSS1.PSS1_LOGIC_OUTS13_1->PSS0_LOGIC_OUTS13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_1" }, "PSS1.PSS1_LOGIC_OUTS13_10->PSS0_LOGIC_OUTS13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_10" }, "PSS1.PSS1_LOGIC_OUTS13_11->PSS0_LOGIC_OUTS13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_11" }, "PSS1.PSS1_LOGIC_OUTS13_12->PSS0_LOGIC_OUTS13_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_12" }, "PSS1.PSS1_LOGIC_OUTS13_13->PSS0_LOGIC_OUTS13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_13" }, "PSS1.PSS1_LOGIC_OUTS13_14->PSS0_LOGIC_OUTS13_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_14" }, "PSS1.PSS1_LOGIC_OUTS13_15->PSS0_LOGIC_OUTS13_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_15" }, "PSS1.PSS1_LOGIC_OUTS13_16->PSS0_LOGIC_OUTS13_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_16" }, "PSS1.PSS1_LOGIC_OUTS13_17->PSS0_LOGIC_OUTS13_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_17" }, "PSS1.PSS1_LOGIC_OUTS13_18->PSS0_LOGIC_OUTS13_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_18" }, "PSS1.PSS1_LOGIC_OUTS13_19->PSS0_LOGIC_OUTS13_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_19" }, "PSS1.PSS1_LOGIC_OUTS13_2->PSS0_LOGIC_OUTS13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_2" }, "PSS1.PSS1_LOGIC_OUTS13_20->PSS_LOGIC_OUTS13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_20" }, "PSS1.PSS1_LOGIC_OUTS13_21->PSS_LOGIC_OUTS13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_21" }, "PSS1.PSS1_LOGIC_OUTS13_22->PSS_LOGIC_OUTS13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_22" }, "PSS1.PSS1_LOGIC_OUTS13_23->PSS_LOGIC_OUTS13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_23" }, "PSS1.PSS1_LOGIC_OUTS13_24->PSS_LOGIC_OUTS13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_24" }, "PSS1.PSS1_LOGIC_OUTS13_25->PSS_LOGIC_OUTS13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_25" }, "PSS1.PSS1_LOGIC_OUTS13_26->PSS_LOGIC_OUTS13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_26" }, "PSS1.PSS1_LOGIC_OUTS13_27->PSS_LOGIC_OUTS13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_27" }, "PSS1.PSS1_LOGIC_OUTS13_28->PSS_LOGIC_OUTS13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_28" }, "PSS1.PSS1_LOGIC_OUTS13_29->PSS_LOGIC_OUTS13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_29" }, "PSS1.PSS1_LOGIC_OUTS13_3->PSS0_LOGIC_OUTS13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_3" }, "PSS1.PSS1_LOGIC_OUTS13_30->PSS_LOGIC_OUTS13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_30" }, "PSS1.PSS1_LOGIC_OUTS13_31->PSS_LOGIC_OUTS13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_31" }, "PSS1.PSS1_LOGIC_OUTS13_32->PSS_LOGIC_OUTS13_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_32" }, "PSS1.PSS1_LOGIC_OUTS13_33->PSS_LOGIC_OUTS13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_33" }, "PSS1.PSS1_LOGIC_OUTS13_34->PSS_LOGIC_OUTS13_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_34" }, "PSS1.PSS1_LOGIC_OUTS13_35->PSS_LOGIC_OUTS13_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_35" }, "PSS1.PSS1_LOGIC_OUTS13_36->PSS_LOGIC_OUTS13_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_36" }, "PSS1.PSS1_LOGIC_OUTS13_37->PSS_LOGIC_OUTS13_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_37" }, "PSS1.PSS1_LOGIC_OUTS13_38->PSS_LOGIC_OUTS13_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_38" }, "PSS1.PSS1_LOGIC_OUTS13_39->PSS_LOGIC_OUTS13_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_39" }, "PSS1.PSS1_LOGIC_OUTS13_4->PSS0_LOGIC_OUTS13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_4" }, "PSS1.PSS1_LOGIC_OUTS13_5->PSS0_LOGIC_OUTS13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_5" }, "PSS1.PSS1_LOGIC_OUTS13_6->PSS0_LOGIC_OUTS13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_6" }, "PSS1.PSS1_LOGIC_OUTS13_7->PSS0_LOGIC_OUTS13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_7" }, "PSS1.PSS1_LOGIC_OUTS13_8->PSS0_LOGIC_OUTS13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_8" }, "PSS1.PSS1_LOGIC_OUTS13_9->PSS0_LOGIC_OUTS13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_9" }, "PSS1.PSS1_LOGIC_OUTS14_0->PSS0_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_0" }, "PSS1.PSS1_LOGIC_OUTS14_1->PSS0_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_1" }, "PSS1.PSS1_LOGIC_OUTS14_10->PSS0_LOGIC_OUTS14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_10" }, "PSS1.PSS1_LOGIC_OUTS14_11->PSS0_LOGIC_OUTS14_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_11" }, "PSS1.PSS1_LOGIC_OUTS14_12->PSS0_LOGIC_OUTS14_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_12" }, "PSS1.PSS1_LOGIC_OUTS14_13->PSS0_LOGIC_OUTS14_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_13" }, "PSS1.PSS1_LOGIC_OUTS14_14->PSS0_LOGIC_OUTS14_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_14" }, "PSS1.PSS1_LOGIC_OUTS14_15->PSS0_LOGIC_OUTS14_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_15" }, "PSS1.PSS1_LOGIC_OUTS14_16->PSS0_LOGIC_OUTS14_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_16" }, "PSS1.PSS1_LOGIC_OUTS14_17->PSS0_LOGIC_OUTS14_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_17" }, "PSS1.PSS1_LOGIC_OUTS14_18->PSS0_LOGIC_OUTS14_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_18" }, "PSS1.PSS1_LOGIC_OUTS14_19->PSS0_LOGIC_OUTS14_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_19" }, "PSS1.PSS1_LOGIC_OUTS14_2->PSS0_LOGIC_OUTS14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_2" }, "PSS1.PSS1_LOGIC_OUTS14_20->PSS_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_20" }, "PSS1.PSS1_LOGIC_OUTS14_21->PSS_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_21" }, "PSS1.PSS1_LOGIC_OUTS14_22->PSS_LOGIC_OUTS14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_22" }, "PSS1.PSS1_LOGIC_OUTS14_23->PSS_LOGIC_OUTS14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_23" }, "PSS1.PSS1_LOGIC_OUTS14_24->PSS_LOGIC_OUTS14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_24" }, "PSS1.PSS1_LOGIC_OUTS14_25->PSS_LOGIC_OUTS14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_25" }, "PSS1.PSS1_LOGIC_OUTS14_26->PSS_LOGIC_OUTS14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_26" }, "PSS1.PSS1_LOGIC_OUTS14_27->PSS_LOGIC_OUTS14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_27" }, "PSS1.PSS1_LOGIC_OUTS14_28->PSS_LOGIC_OUTS14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_28" }, "PSS1.PSS1_LOGIC_OUTS14_29->PSS_LOGIC_OUTS14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_29" }, "PSS1.PSS1_LOGIC_OUTS14_3->PSS0_LOGIC_OUTS14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_3" }, "PSS1.PSS1_LOGIC_OUTS14_30->PSS_LOGIC_OUTS14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_30" }, "PSS1.PSS1_LOGIC_OUTS14_31->PSS_LOGIC_OUTS14_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_31" }, "PSS1.PSS1_LOGIC_OUTS14_32->PSS_LOGIC_OUTS14_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_32" }, "PSS1.PSS1_LOGIC_OUTS14_33->PSS_LOGIC_OUTS14_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_33" }, "PSS1.PSS1_LOGIC_OUTS14_34->PSS_LOGIC_OUTS14_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_34" }, "PSS1.PSS1_LOGIC_OUTS14_35->PSS_LOGIC_OUTS14_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_35" }, "PSS1.PSS1_LOGIC_OUTS14_36->PSS_LOGIC_OUTS14_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_36" }, "PSS1.PSS1_LOGIC_OUTS14_37->PSS_LOGIC_OUTS14_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_37" }, "PSS1.PSS1_LOGIC_OUTS14_38->PSS_LOGIC_OUTS14_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_38" }, "PSS1.PSS1_LOGIC_OUTS14_39->PSS_LOGIC_OUTS14_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_39" }, "PSS1.PSS1_LOGIC_OUTS14_4->PSS0_LOGIC_OUTS14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_4" }, "PSS1.PSS1_LOGIC_OUTS14_5->PSS0_LOGIC_OUTS14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_5" }, "PSS1.PSS1_LOGIC_OUTS14_6->PSS0_LOGIC_OUTS14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_6" }, "PSS1.PSS1_LOGIC_OUTS14_7->PSS0_LOGIC_OUTS14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_7" }, "PSS1.PSS1_LOGIC_OUTS14_8->PSS0_LOGIC_OUTS14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_8" }, "PSS1.PSS1_LOGIC_OUTS14_9->PSS0_LOGIC_OUTS14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_9" }, "PSS1.PSS1_LOGIC_OUTS15_0->PSS0_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_0" }, "PSS1.PSS1_LOGIC_OUTS15_1->PSS0_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_1" }, "PSS1.PSS1_LOGIC_OUTS15_10->PSS0_LOGIC_OUTS15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_10" }, "PSS1.PSS1_LOGIC_OUTS15_11->PSS0_LOGIC_OUTS15_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_11" }, "PSS1.PSS1_LOGIC_OUTS15_12->PSS0_LOGIC_OUTS15_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_12" }, "PSS1.PSS1_LOGIC_OUTS15_13->PSS0_LOGIC_OUTS15_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_13" }, "PSS1.PSS1_LOGIC_OUTS15_14->PSS0_LOGIC_OUTS15_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_14" }, "PSS1.PSS1_LOGIC_OUTS15_15->PSS0_LOGIC_OUTS15_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_15" }, "PSS1.PSS1_LOGIC_OUTS15_16->PSS0_LOGIC_OUTS15_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_16" }, "PSS1.PSS1_LOGIC_OUTS15_17->PSS0_LOGIC_OUTS15_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_17" }, "PSS1.PSS1_LOGIC_OUTS15_18->PSS0_LOGIC_OUTS15_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_18" }, "PSS1.PSS1_LOGIC_OUTS15_19->PSS0_LOGIC_OUTS15_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_19" }, "PSS1.PSS1_LOGIC_OUTS15_2->PSS0_LOGIC_OUTS15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_2" }, "PSS1.PSS1_LOGIC_OUTS15_20->PSS_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_20" }, "PSS1.PSS1_LOGIC_OUTS15_21->PSS_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_21" }, "PSS1.PSS1_LOGIC_OUTS15_22->PSS_LOGIC_OUTS15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_22" }, "PSS1.PSS1_LOGIC_OUTS15_23->PSS_LOGIC_OUTS15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_23" }, "PSS1.PSS1_LOGIC_OUTS15_24->PSS_LOGIC_OUTS15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_24" }, "PSS1.PSS1_LOGIC_OUTS15_25->PSS_LOGIC_OUTS15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_25" }, "PSS1.PSS1_LOGIC_OUTS15_26->PSS_LOGIC_OUTS15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_26" }, "PSS1.PSS1_LOGIC_OUTS15_27->PSS_LOGIC_OUTS15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_27" }, "PSS1.PSS1_LOGIC_OUTS15_28->PSS_LOGIC_OUTS15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_28" }, "PSS1.PSS1_LOGIC_OUTS15_29->PSS_LOGIC_OUTS15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_29" }, "PSS1.PSS1_LOGIC_OUTS15_3->PSS0_LOGIC_OUTS15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_3" }, "PSS1.PSS1_LOGIC_OUTS15_30->PSS_LOGIC_OUTS15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_30" }, "PSS1.PSS1_LOGIC_OUTS15_31->PSS_LOGIC_OUTS15_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_31" }, "PSS1.PSS1_LOGIC_OUTS15_32->PSS_LOGIC_OUTS15_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_32" }, "PSS1.PSS1_LOGIC_OUTS15_33->PSS_LOGIC_OUTS15_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_33" }, "PSS1.PSS1_LOGIC_OUTS15_34->PSS_LOGIC_OUTS15_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_34" }, "PSS1.PSS1_LOGIC_OUTS15_35->PSS_LOGIC_OUTS15_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_35" }, "PSS1.PSS1_LOGIC_OUTS15_36->PSS_LOGIC_OUTS15_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_36" }, "PSS1.PSS1_LOGIC_OUTS15_37->PSS_LOGIC_OUTS15_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_37" }, "PSS1.PSS1_LOGIC_OUTS15_38->PSS_LOGIC_OUTS15_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_38" }, "PSS1.PSS1_LOGIC_OUTS15_39->PSS_LOGIC_OUTS15_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_39" }, "PSS1.PSS1_LOGIC_OUTS15_4->PSS0_LOGIC_OUTS15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_4" }, "PSS1.PSS1_LOGIC_OUTS15_5->PSS0_LOGIC_OUTS15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_5" }, "PSS1.PSS1_LOGIC_OUTS15_6->PSS0_LOGIC_OUTS15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_6" }, "PSS1.PSS1_LOGIC_OUTS15_7->PSS0_LOGIC_OUTS15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_7" }, "PSS1.PSS1_LOGIC_OUTS15_8->PSS0_LOGIC_OUTS15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_8" }, "PSS1.PSS1_LOGIC_OUTS15_9->PSS0_LOGIC_OUTS15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_9" }, "PSS1.PSS1_LOGIC_OUTS16_0->PSS0_LOGIC_OUTS16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_0" }, "PSS1.PSS1_LOGIC_OUTS16_1->PSS0_LOGIC_OUTS16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_1" }, "PSS1.PSS1_LOGIC_OUTS16_10->PSS0_LOGIC_OUTS16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_10" }, "PSS1.PSS1_LOGIC_OUTS16_11->PSS0_LOGIC_OUTS16_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_11" }, "PSS1.PSS1_LOGIC_OUTS16_12->PSS0_LOGIC_OUTS16_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_12" }, "PSS1.PSS1_LOGIC_OUTS16_13->PSS0_LOGIC_OUTS16_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_13" }, "PSS1.PSS1_LOGIC_OUTS16_14->PSS0_LOGIC_OUTS16_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_14" }, "PSS1.PSS1_LOGIC_OUTS16_15->PSS0_LOGIC_OUTS16_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_15" }, "PSS1.PSS1_LOGIC_OUTS16_16->PSS0_LOGIC_OUTS16_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_16" }, "PSS1.PSS1_LOGIC_OUTS16_17->PSS0_LOGIC_OUTS16_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_17" }, "PSS1.PSS1_LOGIC_OUTS16_18->PSS0_LOGIC_OUTS16_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_18" }, "PSS1.PSS1_LOGIC_OUTS16_19->PSS0_LOGIC_OUTS16_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_19" }, "PSS1.PSS1_LOGIC_OUTS16_2->PSS0_LOGIC_OUTS16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_2" }, "PSS1.PSS1_LOGIC_OUTS16_20->PSS_LOGIC_OUTS16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_20" }, "PSS1.PSS1_LOGIC_OUTS16_21->PSS_LOGIC_OUTS16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_21" }, "PSS1.PSS1_LOGIC_OUTS16_22->PSS_LOGIC_OUTS16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_22" }, "PSS1.PSS1_LOGIC_OUTS16_23->PSS_LOGIC_OUTS16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_23" }, "PSS1.PSS1_LOGIC_OUTS16_24->PSS_LOGIC_OUTS16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_24" }, "PSS1.PSS1_LOGIC_OUTS16_25->PSS_LOGIC_OUTS16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_25" }, "PSS1.PSS1_LOGIC_OUTS16_26->PSS_LOGIC_OUTS16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_26" }, "PSS1.PSS1_LOGIC_OUTS16_27->PSS_LOGIC_OUTS16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_27" }, "PSS1.PSS1_LOGIC_OUTS16_28->PSS_LOGIC_OUTS16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_28" }, "PSS1.PSS1_LOGIC_OUTS16_29->PSS_LOGIC_OUTS16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_29" }, "PSS1.PSS1_LOGIC_OUTS16_3->PSS0_LOGIC_OUTS16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_3" }, "PSS1.PSS1_LOGIC_OUTS16_30->PSS_LOGIC_OUTS16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_30" }, "PSS1.PSS1_LOGIC_OUTS16_31->PSS_LOGIC_OUTS16_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_31" }, "PSS1.PSS1_LOGIC_OUTS16_32->PSS_LOGIC_OUTS16_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_32" }, "PSS1.PSS1_LOGIC_OUTS16_33->PSS_LOGIC_OUTS16_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_33" }, "PSS1.PSS1_LOGIC_OUTS16_34->PSS_LOGIC_OUTS16_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_34" }, "PSS1.PSS1_LOGIC_OUTS16_35->PSS_LOGIC_OUTS16_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_35" }, "PSS1.PSS1_LOGIC_OUTS16_36->PSS_LOGIC_OUTS16_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_36" }, "PSS1.PSS1_LOGIC_OUTS16_37->PSS_LOGIC_OUTS16_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_37" }, "PSS1.PSS1_LOGIC_OUTS16_38->PSS_LOGIC_OUTS16_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_38" }, "PSS1.PSS1_LOGIC_OUTS16_39->PSS_LOGIC_OUTS16_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_39" }, "PSS1.PSS1_LOGIC_OUTS16_4->PSS0_LOGIC_OUTS16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_4" }, "PSS1.PSS1_LOGIC_OUTS16_5->PSS0_LOGIC_OUTS16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_5" }, "PSS1.PSS1_LOGIC_OUTS16_6->PSS0_LOGIC_OUTS16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_6" }, "PSS1.PSS1_LOGIC_OUTS16_7->PSS0_LOGIC_OUTS16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_7" }, "PSS1.PSS1_LOGIC_OUTS16_8->PSS0_LOGIC_OUTS16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_8" }, "PSS1.PSS1_LOGIC_OUTS16_9->PSS0_LOGIC_OUTS16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_9" }, "PSS1.PSS1_LOGIC_OUTS17_0->PSS0_LOGIC_OUTS17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_0" }, "PSS1.PSS1_LOGIC_OUTS17_1->PSS0_LOGIC_OUTS17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_1" }, "PSS1.PSS1_LOGIC_OUTS17_10->PSS0_LOGIC_OUTS17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_10" }, "PSS1.PSS1_LOGIC_OUTS17_11->PSS0_LOGIC_OUTS17_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_11" }, "PSS1.PSS1_LOGIC_OUTS17_12->PSS0_LOGIC_OUTS17_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_12" }, "PSS1.PSS1_LOGIC_OUTS17_13->PSS0_LOGIC_OUTS17_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_13" }, "PSS1.PSS1_LOGIC_OUTS17_14->PSS0_LOGIC_OUTS17_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_14" }, "PSS1.PSS1_LOGIC_OUTS17_15->PSS0_LOGIC_OUTS17_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_15" }, "PSS1.PSS1_LOGIC_OUTS17_16->PSS0_LOGIC_OUTS17_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_16" }, "PSS1.PSS1_LOGIC_OUTS17_17->PSS0_LOGIC_OUTS17_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_17" }, "PSS1.PSS1_LOGIC_OUTS17_18->PSS0_LOGIC_OUTS17_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_18" }, "PSS1.PSS1_LOGIC_OUTS17_19->PSS0_LOGIC_OUTS17_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_19" }, "PSS1.PSS1_LOGIC_OUTS17_2->PSS0_LOGIC_OUTS17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_2" }, "PSS1.PSS1_LOGIC_OUTS17_20->PSS_LOGIC_OUTS17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_20" }, "PSS1.PSS1_LOGIC_OUTS17_21->PSS_LOGIC_OUTS17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_21" }, "PSS1.PSS1_LOGIC_OUTS17_22->PSS_LOGIC_OUTS17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_22" }, "PSS1.PSS1_LOGIC_OUTS17_23->PSS_LOGIC_OUTS17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_23" }, "PSS1.PSS1_LOGIC_OUTS17_24->PSS_LOGIC_OUTS17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_24" }, "PSS1.PSS1_LOGIC_OUTS17_25->PSS_LOGIC_OUTS17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_25" }, "PSS1.PSS1_LOGIC_OUTS17_26->PSS_LOGIC_OUTS17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_26" }, "PSS1.PSS1_LOGIC_OUTS17_27->PSS_LOGIC_OUTS17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_27" }, "PSS1.PSS1_LOGIC_OUTS17_28->PSS_LOGIC_OUTS17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_28" }, "PSS1.PSS1_LOGIC_OUTS17_29->PSS_LOGIC_OUTS17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_29" }, "PSS1.PSS1_LOGIC_OUTS17_3->PSS0_LOGIC_OUTS17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_3" }, "PSS1.PSS1_LOGIC_OUTS17_30->PSS_LOGIC_OUTS17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_30" }, "PSS1.PSS1_LOGIC_OUTS17_31->PSS_LOGIC_OUTS17_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_31" }, "PSS1.PSS1_LOGIC_OUTS17_32->PSS_LOGIC_OUTS17_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_32" }, "PSS1.PSS1_LOGIC_OUTS17_33->PSS_LOGIC_OUTS17_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_33" }, "PSS1.PSS1_LOGIC_OUTS17_34->PSS_LOGIC_OUTS17_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_34" }, "PSS1.PSS1_LOGIC_OUTS17_35->PSS_LOGIC_OUTS17_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_35" }, "PSS1.PSS1_LOGIC_OUTS17_36->PSS_LOGIC_OUTS17_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_36" }, "PSS1.PSS1_LOGIC_OUTS17_37->PSS_LOGIC_OUTS17_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_37" }, "PSS1.PSS1_LOGIC_OUTS17_38->PSS_LOGIC_OUTS17_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_38" }, "PSS1.PSS1_LOGIC_OUTS17_39->PSS_LOGIC_OUTS17_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_39" }, "PSS1.PSS1_LOGIC_OUTS17_4->PSS0_LOGIC_OUTS17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_4" }, "PSS1.PSS1_LOGIC_OUTS17_5->PSS0_LOGIC_OUTS17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_5" }, "PSS1.PSS1_LOGIC_OUTS17_6->PSS0_LOGIC_OUTS17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_6" }, "PSS1.PSS1_LOGIC_OUTS17_7->PSS0_LOGIC_OUTS17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_7" }, "PSS1.PSS1_LOGIC_OUTS17_8->PSS0_LOGIC_OUTS17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_8" }, "PSS1.PSS1_LOGIC_OUTS17_9->PSS0_LOGIC_OUTS17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_9" }, "PSS1.PSS1_LOGIC_OUTS18_0->PSS0_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_0" }, "PSS1.PSS1_LOGIC_OUTS18_1->PSS0_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_1" }, "PSS1.PSS1_LOGIC_OUTS18_10->PSS0_LOGIC_OUTS18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_10" }, "PSS1.PSS1_LOGIC_OUTS18_11->PSS0_LOGIC_OUTS18_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_11" }, "PSS1.PSS1_LOGIC_OUTS18_12->PSS0_LOGIC_OUTS18_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_12" }, "PSS1.PSS1_LOGIC_OUTS18_13->PSS0_LOGIC_OUTS18_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_13" }, "PSS1.PSS1_LOGIC_OUTS18_14->PSS0_LOGIC_OUTS18_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_14" }, "PSS1.PSS1_LOGIC_OUTS18_15->PSS0_LOGIC_OUTS18_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_15" }, "PSS1.PSS1_LOGIC_OUTS18_16->PSS0_LOGIC_OUTS18_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_16" }, "PSS1.PSS1_LOGIC_OUTS18_17->PSS0_LOGIC_OUTS18_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_17" }, "PSS1.PSS1_LOGIC_OUTS18_18->PSS0_LOGIC_OUTS18_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_18" }, "PSS1.PSS1_LOGIC_OUTS18_19->PSS0_LOGIC_OUTS18_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_19" }, "PSS1.PSS1_LOGIC_OUTS18_2->PSS0_LOGIC_OUTS18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_2" }, "PSS1.PSS1_LOGIC_OUTS18_20->PSS_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_20" }, "PSS1.PSS1_LOGIC_OUTS18_21->PSS_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_21" }, "PSS1.PSS1_LOGIC_OUTS18_22->PSS_LOGIC_OUTS18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_22" }, "PSS1.PSS1_LOGIC_OUTS18_23->PSS_LOGIC_OUTS18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_23" }, "PSS1.PSS1_LOGIC_OUTS18_24->PSS_LOGIC_OUTS18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_24" }, "PSS1.PSS1_LOGIC_OUTS18_25->PSS_LOGIC_OUTS18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_25" }, "PSS1.PSS1_LOGIC_OUTS18_26->PSS_LOGIC_OUTS18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_26" }, "PSS1.PSS1_LOGIC_OUTS18_27->PSS_LOGIC_OUTS18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_27" }, "PSS1.PSS1_LOGIC_OUTS18_28->PSS_LOGIC_OUTS18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_28" }, "PSS1.PSS1_LOGIC_OUTS18_29->PSS_LOGIC_OUTS18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_29" }, "PSS1.PSS1_LOGIC_OUTS18_3->PSS0_LOGIC_OUTS18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_3" }, "PSS1.PSS1_LOGIC_OUTS18_30->PSS_LOGIC_OUTS18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_30" }, "PSS1.PSS1_LOGIC_OUTS18_31->PSS_LOGIC_OUTS18_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_31" }, "PSS1.PSS1_LOGIC_OUTS18_32->PSS_LOGIC_OUTS18_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_32" }, "PSS1.PSS1_LOGIC_OUTS18_33->PSS_LOGIC_OUTS18_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_33" }, "PSS1.PSS1_LOGIC_OUTS18_34->PSS_LOGIC_OUTS18_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_34" }, "PSS1.PSS1_LOGIC_OUTS18_35->PSS_LOGIC_OUTS18_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_35" }, "PSS1.PSS1_LOGIC_OUTS18_36->PSS_LOGIC_OUTS18_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_36" }, "PSS1.PSS1_LOGIC_OUTS18_37->PSS_LOGIC_OUTS18_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_37" }, "PSS1.PSS1_LOGIC_OUTS18_38->PSS_LOGIC_OUTS18_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_38" }, "PSS1.PSS1_LOGIC_OUTS18_39->PSS_LOGIC_OUTS18_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_39" }, "PSS1.PSS1_LOGIC_OUTS18_4->PSS0_LOGIC_OUTS18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_4" }, "PSS1.PSS1_LOGIC_OUTS18_5->PSS0_LOGIC_OUTS18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_5" }, "PSS1.PSS1_LOGIC_OUTS18_6->PSS0_LOGIC_OUTS18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_6" }, "PSS1.PSS1_LOGIC_OUTS18_7->PSS0_LOGIC_OUTS18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_7" }, "PSS1.PSS1_LOGIC_OUTS18_8->PSS0_LOGIC_OUTS18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_8" }, "PSS1.PSS1_LOGIC_OUTS18_9->PSS0_LOGIC_OUTS18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_9" }, "PSS1.PSS1_LOGIC_OUTS19_0->PSS0_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_0" }, "PSS1.PSS1_LOGIC_OUTS19_1->PSS0_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_1" }, "PSS1.PSS1_LOGIC_OUTS19_10->PSS0_LOGIC_OUTS19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_10" }, "PSS1.PSS1_LOGIC_OUTS19_11->PSS0_LOGIC_OUTS19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_11" }, "PSS1.PSS1_LOGIC_OUTS19_12->PSS0_LOGIC_OUTS19_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_12" }, "PSS1.PSS1_LOGIC_OUTS19_13->PSS0_LOGIC_OUTS19_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_13" }, "PSS1.PSS1_LOGIC_OUTS19_14->PSS0_LOGIC_OUTS19_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_14" }, "PSS1.PSS1_LOGIC_OUTS19_15->PSS0_LOGIC_OUTS19_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_15" }, "PSS1.PSS1_LOGIC_OUTS19_16->PSS0_LOGIC_OUTS19_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_16" }, "PSS1.PSS1_LOGIC_OUTS19_17->PSS0_LOGIC_OUTS19_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_17" }, "PSS1.PSS1_LOGIC_OUTS19_18->PSS0_LOGIC_OUTS19_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_18" }, "PSS1.PSS1_LOGIC_OUTS19_19->PSS0_LOGIC_OUTS19_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_19" }, "PSS1.PSS1_LOGIC_OUTS19_2->PSS0_LOGIC_OUTS19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_2" }, "PSS1.PSS1_LOGIC_OUTS19_20->PSS_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_20" }, "PSS1.PSS1_LOGIC_OUTS19_21->PSS_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_21" }, "PSS1.PSS1_LOGIC_OUTS19_22->PSS_LOGIC_OUTS19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_22" }, "PSS1.PSS1_LOGIC_OUTS19_23->PSS_LOGIC_OUTS19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_23" }, "PSS1.PSS1_LOGIC_OUTS19_24->PSS_LOGIC_OUTS19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_24" }, "PSS1.PSS1_LOGIC_OUTS19_25->PSS_LOGIC_OUTS19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_25" }, "PSS1.PSS1_LOGIC_OUTS19_26->PSS_LOGIC_OUTS19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_26" }, "PSS1.PSS1_LOGIC_OUTS19_27->PSS_LOGIC_OUTS19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_27" }, "PSS1.PSS1_LOGIC_OUTS19_28->PSS_LOGIC_OUTS19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_28" }, "PSS1.PSS1_LOGIC_OUTS19_29->PSS_LOGIC_OUTS19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_29" }, "PSS1.PSS1_LOGIC_OUTS19_3->PSS0_LOGIC_OUTS19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_3" }, "PSS1.PSS1_LOGIC_OUTS19_30->PSS_LOGIC_OUTS19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_30" }, "PSS1.PSS1_LOGIC_OUTS19_31->PSS_LOGIC_OUTS19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_31" }, "PSS1.PSS1_LOGIC_OUTS19_32->PSS_LOGIC_OUTS19_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_32" }, "PSS1.PSS1_LOGIC_OUTS19_33->PSS_LOGIC_OUTS19_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_33" }, "PSS1.PSS1_LOGIC_OUTS19_34->PSS_LOGIC_OUTS19_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_34" }, "PSS1.PSS1_LOGIC_OUTS19_35->PSS_LOGIC_OUTS19_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_35" }, "PSS1.PSS1_LOGIC_OUTS19_36->PSS_LOGIC_OUTS19_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_36" }, "PSS1.PSS1_LOGIC_OUTS19_37->PSS_LOGIC_OUTS19_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_37" }, "PSS1.PSS1_LOGIC_OUTS19_38->PSS_LOGIC_OUTS19_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_38" }, "PSS1.PSS1_LOGIC_OUTS19_39->PSS_LOGIC_OUTS19_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_39" }, "PSS1.PSS1_LOGIC_OUTS19_4->PSS0_LOGIC_OUTS19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_4" }, "PSS1.PSS1_LOGIC_OUTS19_5->PSS0_LOGIC_OUTS19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_5" }, "PSS1.PSS1_LOGIC_OUTS19_6->PSS0_LOGIC_OUTS19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_6" }, "PSS1.PSS1_LOGIC_OUTS19_7->PSS0_LOGIC_OUTS19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_7" }, "PSS1.PSS1_LOGIC_OUTS19_8->PSS0_LOGIC_OUTS19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_8" }, "PSS1.PSS1_LOGIC_OUTS19_9->PSS0_LOGIC_OUTS19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_9" }, "PSS1.PSS1_LOGIC_OUTS1_0->PSS0_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_0" }, "PSS1.PSS1_LOGIC_OUTS1_1->PSS0_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_1" }, "PSS1.PSS1_LOGIC_OUTS1_10->PSS0_LOGIC_OUTS1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_10" }, "PSS1.PSS1_LOGIC_OUTS1_11->PSS0_LOGIC_OUTS1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_11" }, "PSS1.PSS1_LOGIC_OUTS1_12->PSS0_LOGIC_OUTS1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_12" }, "PSS1.PSS1_LOGIC_OUTS1_13->PSS0_LOGIC_OUTS1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_13" }, "PSS1.PSS1_LOGIC_OUTS1_14->PSS0_LOGIC_OUTS1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_14" }, "PSS1.PSS1_LOGIC_OUTS1_15->PSS0_LOGIC_OUTS1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_15" }, "PSS1.PSS1_LOGIC_OUTS1_16->PSS0_LOGIC_OUTS1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_16" }, "PSS1.PSS1_LOGIC_OUTS1_17->PSS0_LOGIC_OUTS1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_17" }, "PSS1.PSS1_LOGIC_OUTS1_18->PSS0_LOGIC_OUTS1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_18" }, "PSS1.PSS1_LOGIC_OUTS1_19->PSS0_LOGIC_OUTS1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_19" }, "PSS1.PSS1_LOGIC_OUTS1_2->PSS0_LOGIC_OUTS1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_2" }, "PSS1.PSS1_LOGIC_OUTS1_20->PSS_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_20" }, "PSS1.PSS1_LOGIC_OUTS1_21->PSS_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_21" }, "PSS1.PSS1_LOGIC_OUTS1_22->PSS_LOGIC_OUTS1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_22" }, "PSS1.PSS1_LOGIC_OUTS1_23->PSS_LOGIC_OUTS1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_23" }, "PSS1.PSS1_LOGIC_OUTS1_24->PSS_LOGIC_OUTS1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_24" }, "PSS1.PSS1_LOGIC_OUTS1_25->PSS_LOGIC_OUTS1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_25" }, "PSS1.PSS1_LOGIC_OUTS1_26->PSS_LOGIC_OUTS1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_26" }, "PSS1.PSS1_LOGIC_OUTS1_27->PSS_LOGIC_OUTS1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_27" }, "PSS1.PSS1_LOGIC_OUTS1_28->PSS_LOGIC_OUTS1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_28" }, "PSS1.PSS1_LOGIC_OUTS1_29->PSS_LOGIC_OUTS1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_29" }, "PSS1.PSS1_LOGIC_OUTS1_3->PSS0_LOGIC_OUTS1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_3" }, "PSS1.PSS1_LOGIC_OUTS1_30->PSS_LOGIC_OUTS1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_30" }, "PSS1.PSS1_LOGIC_OUTS1_31->PSS_LOGIC_OUTS1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_31" }, "PSS1.PSS1_LOGIC_OUTS1_32->PSS_LOGIC_OUTS1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_32" }, "PSS1.PSS1_LOGIC_OUTS1_33->PSS_LOGIC_OUTS1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_33" }, "PSS1.PSS1_LOGIC_OUTS1_34->PSS_LOGIC_OUTS1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_34" }, "PSS1.PSS1_LOGIC_OUTS1_35->PSS_LOGIC_OUTS1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_35" }, "PSS1.PSS1_LOGIC_OUTS1_36->PSS_LOGIC_OUTS1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_36" }, "PSS1.PSS1_LOGIC_OUTS1_37->PSS_LOGIC_OUTS1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_37" }, "PSS1.PSS1_LOGIC_OUTS1_38->PSS_LOGIC_OUTS1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_38" }, "PSS1.PSS1_LOGIC_OUTS1_39->PSS_LOGIC_OUTS1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_39" }, "PSS1.PSS1_LOGIC_OUTS1_4->PSS0_LOGIC_OUTS1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_4" }, "PSS1.PSS1_LOGIC_OUTS1_5->PSS0_LOGIC_OUTS1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_5" }, "PSS1.PSS1_LOGIC_OUTS1_6->PSS0_LOGIC_OUTS1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_6" }, "PSS1.PSS1_LOGIC_OUTS1_7->PSS0_LOGIC_OUTS1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_7" }, "PSS1.PSS1_LOGIC_OUTS1_8->PSS0_LOGIC_OUTS1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_8" }, "PSS1.PSS1_LOGIC_OUTS1_9->PSS0_LOGIC_OUTS1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_9" }, "PSS1.PSS1_LOGIC_OUTS20_0->PSS0_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_0" }, "PSS1.PSS1_LOGIC_OUTS20_1->PSS0_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_1" }, "PSS1.PSS1_LOGIC_OUTS20_10->PSS0_LOGIC_OUTS20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_10" }, "PSS1.PSS1_LOGIC_OUTS20_11->PSS0_LOGIC_OUTS20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_11" }, "PSS1.PSS1_LOGIC_OUTS20_12->PSS0_LOGIC_OUTS20_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_12" }, "PSS1.PSS1_LOGIC_OUTS20_13->PSS0_LOGIC_OUTS20_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_13" }, "PSS1.PSS1_LOGIC_OUTS20_14->PSS0_LOGIC_OUTS20_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_14" }, "PSS1.PSS1_LOGIC_OUTS20_15->PSS0_LOGIC_OUTS20_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_15" }, "PSS1.PSS1_LOGIC_OUTS20_16->PSS0_LOGIC_OUTS20_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_16" }, "PSS1.PSS1_LOGIC_OUTS20_17->PSS0_LOGIC_OUTS20_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_17" }, "PSS1.PSS1_LOGIC_OUTS20_18->PSS0_LOGIC_OUTS20_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_18" }, "PSS1.PSS1_LOGIC_OUTS20_19->PSS0_LOGIC_OUTS20_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_19" }, "PSS1.PSS1_LOGIC_OUTS20_2->PSS0_LOGIC_OUTS20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_2" }, "PSS1.PSS1_LOGIC_OUTS20_20->PSS_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_20" }, "PSS1.PSS1_LOGIC_OUTS20_21->PSS_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_21" }, "PSS1.PSS1_LOGIC_OUTS20_22->PSS_LOGIC_OUTS20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_22" }, "PSS1.PSS1_LOGIC_OUTS20_23->PSS_LOGIC_OUTS20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_23" }, "PSS1.PSS1_LOGIC_OUTS20_24->PSS_LOGIC_OUTS20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_24" }, "PSS1.PSS1_LOGIC_OUTS20_25->PSS_LOGIC_OUTS20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_25" }, "PSS1.PSS1_LOGIC_OUTS20_26->PSS_LOGIC_OUTS20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_26" }, "PSS1.PSS1_LOGIC_OUTS20_27->PSS_LOGIC_OUTS20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_27" }, "PSS1.PSS1_LOGIC_OUTS20_28->PSS_LOGIC_OUTS20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_28" }, "PSS1.PSS1_LOGIC_OUTS20_29->PSS_LOGIC_OUTS20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_29" }, "PSS1.PSS1_LOGIC_OUTS20_3->PSS0_LOGIC_OUTS20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_3" }, "PSS1.PSS1_LOGIC_OUTS20_30->PSS_LOGIC_OUTS20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_30" }, "PSS1.PSS1_LOGIC_OUTS20_31->PSS_LOGIC_OUTS20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_31" }, "PSS1.PSS1_LOGIC_OUTS20_32->PSS_LOGIC_OUTS20_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_32" }, "PSS1.PSS1_LOGIC_OUTS20_33->PSS_LOGIC_OUTS20_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_33" }, "PSS1.PSS1_LOGIC_OUTS20_34->PSS_LOGIC_OUTS20_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_34" }, "PSS1.PSS1_LOGIC_OUTS20_35->PSS_LOGIC_OUTS20_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_35" }, "PSS1.PSS1_LOGIC_OUTS20_36->PSS_LOGIC_OUTS20_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_36" }, "PSS1.PSS1_LOGIC_OUTS20_37->PSS_LOGIC_OUTS20_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_37" }, "PSS1.PSS1_LOGIC_OUTS20_38->PSS_LOGIC_OUTS20_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_38" }, "PSS1.PSS1_LOGIC_OUTS20_39->PSS_LOGIC_OUTS20_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_39" }, "PSS1.PSS1_LOGIC_OUTS20_4->PSS0_LOGIC_OUTS20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_4" }, "PSS1.PSS1_LOGIC_OUTS20_5->PSS0_LOGIC_OUTS20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_5" }, "PSS1.PSS1_LOGIC_OUTS20_6->PSS0_LOGIC_OUTS20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_6" }, "PSS1.PSS1_LOGIC_OUTS20_7->PSS0_LOGIC_OUTS20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_7" }, "PSS1.PSS1_LOGIC_OUTS20_8->PSS0_LOGIC_OUTS20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_8" }, "PSS1.PSS1_LOGIC_OUTS20_9->PSS0_LOGIC_OUTS20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_9" }, "PSS1.PSS1_LOGIC_OUTS21_0->PSS0_LOGIC_OUTS21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_0" }, "PSS1.PSS1_LOGIC_OUTS21_1->PSS0_LOGIC_OUTS21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_1" }, "PSS1.PSS1_LOGIC_OUTS21_10->PSS0_LOGIC_OUTS21_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_10" }, "PSS1.PSS1_LOGIC_OUTS21_11->PSS0_LOGIC_OUTS21_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_11" }, "PSS1.PSS1_LOGIC_OUTS21_12->PSS0_LOGIC_OUTS21_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_12" }, "PSS1.PSS1_LOGIC_OUTS21_13->PSS0_LOGIC_OUTS21_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_13" }, "PSS1.PSS1_LOGIC_OUTS21_14->PSS0_LOGIC_OUTS21_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_14" }, "PSS1.PSS1_LOGIC_OUTS21_15->PSS0_LOGIC_OUTS21_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_15" }, "PSS1.PSS1_LOGIC_OUTS21_16->PSS0_LOGIC_OUTS21_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_16" }, "PSS1.PSS1_LOGIC_OUTS21_17->PSS0_LOGIC_OUTS21_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_17" }, "PSS1.PSS1_LOGIC_OUTS21_18->PSS0_LOGIC_OUTS21_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_18" }, "PSS1.PSS1_LOGIC_OUTS21_19->PSS0_LOGIC_OUTS21_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_19" }, "PSS1.PSS1_LOGIC_OUTS21_2->PSS0_LOGIC_OUTS21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_2" }, "PSS1.PSS1_LOGIC_OUTS21_20->PSS_LOGIC_OUTS21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_20" }, "PSS1.PSS1_LOGIC_OUTS21_21->PSS_LOGIC_OUTS21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_21" }, "PSS1.PSS1_LOGIC_OUTS21_22->PSS_LOGIC_OUTS21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_22" }, "PSS1.PSS1_LOGIC_OUTS21_23->PSS_LOGIC_OUTS21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_23" }, "PSS1.PSS1_LOGIC_OUTS21_24->PSS_LOGIC_OUTS21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_24" }, "PSS1.PSS1_LOGIC_OUTS21_25->PSS_LOGIC_OUTS21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_25" }, "PSS1.PSS1_LOGIC_OUTS21_26->PSS_LOGIC_OUTS21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_26" }, "PSS1.PSS1_LOGIC_OUTS21_27->PSS_LOGIC_OUTS21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_27" }, "PSS1.PSS1_LOGIC_OUTS21_28->PSS_LOGIC_OUTS21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_28" }, "PSS1.PSS1_LOGIC_OUTS21_29->PSS_LOGIC_OUTS21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_29" }, "PSS1.PSS1_LOGIC_OUTS21_3->PSS0_LOGIC_OUTS21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_3" }, "PSS1.PSS1_LOGIC_OUTS21_30->PSS_LOGIC_OUTS21_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_30" }, "PSS1.PSS1_LOGIC_OUTS21_31->PSS_LOGIC_OUTS21_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_31" }, "PSS1.PSS1_LOGIC_OUTS21_32->PSS_LOGIC_OUTS21_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_32" }, "PSS1.PSS1_LOGIC_OUTS21_33->PSS_LOGIC_OUTS21_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_33" }, "PSS1.PSS1_LOGIC_OUTS21_34->PSS_LOGIC_OUTS21_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_34" }, "PSS1.PSS1_LOGIC_OUTS21_35->PSS_LOGIC_OUTS21_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_35" }, "PSS1.PSS1_LOGIC_OUTS21_36->PSS_LOGIC_OUTS21_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_36" }, "PSS1.PSS1_LOGIC_OUTS21_37->PSS_LOGIC_OUTS21_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_37" }, "PSS1.PSS1_LOGIC_OUTS21_38->PSS_LOGIC_OUTS21_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_38" }, "PSS1.PSS1_LOGIC_OUTS21_39->PSS_LOGIC_OUTS21_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_39" }, "PSS1.PSS1_LOGIC_OUTS21_4->PSS0_LOGIC_OUTS21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_4" }, "PSS1.PSS1_LOGIC_OUTS21_5->PSS0_LOGIC_OUTS21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_5" }, "PSS1.PSS1_LOGIC_OUTS21_6->PSS0_LOGIC_OUTS21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_6" }, "PSS1.PSS1_LOGIC_OUTS21_7->PSS0_LOGIC_OUTS21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_7" }, "PSS1.PSS1_LOGIC_OUTS21_8->PSS0_LOGIC_OUTS21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_8" }, "PSS1.PSS1_LOGIC_OUTS21_9->PSS0_LOGIC_OUTS21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_9" }, "PSS1.PSS1_LOGIC_OUTS22_0->PSS0_LOGIC_OUTS22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_0" }, "PSS1.PSS1_LOGIC_OUTS22_1->PSS0_LOGIC_OUTS22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_1" }, "PSS1.PSS1_LOGIC_OUTS22_10->PSS0_LOGIC_OUTS22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_10" }, "PSS1.PSS1_LOGIC_OUTS22_11->PSS0_LOGIC_OUTS22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_11" }, "PSS1.PSS1_LOGIC_OUTS22_12->PSS0_LOGIC_OUTS22_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_12" }, "PSS1.PSS1_LOGIC_OUTS22_13->PSS0_LOGIC_OUTS22_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_13" }, "PSS1.PSS1_LOGIC_OUTS22_14->PSS0_LOGIC_OUTS22_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_14" }, "PSS1.PSS1_LOGIC_OUTS22_15->PSS0_LOGIC_OUTS22_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_15" }, "PSS1.PSS1_LOGIC_OUTS22_16->PSS0_LOGIC_OUTS22_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_16" }, "PSS1.PSS1_LOGIC_OUTS22_17->PSS0_LOGIC_OUTS22_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_17" }, "PSS1.PSS1_LOGIC_OUTS22_18->PSS0_LOGIC_OUTS22_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_18" }, "PSS1.PSS1_LOGIC_OUTS22_19->PSS0_LOGIC_OUTS22_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_19" }, "PSS1.PSS1_LOGIC_OUTS22_2->PSS0_LOGIC_OUTS22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_2" }, "PSS1.PSS1_LOGIC_OUTS22_20->PSS_LOGIC_OUTS22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_20" }, "PSS1.PSS1_LOGIC_OUTS22_21->PSS_LOGIC_OUTS22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_21" }, "PSS1.PSS1_LOGIC_OUTS22_22->PSS_LOGIC_OUTS22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_22" }, "PSS1.PSS1_LOGIC_OUTS22_23->PSS_LOGIC_OUTS22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_23" }, "PSS1.PSS1_LOGIC_OUTS22_24->PSS_LOGIC_OUTS22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_24" }, "PSS1.PSS1_LOGIC_OUTS22_25->PSS_LOGIC_OUTS22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_25" }, "PSS1.PSS1_LOGIC_OUTS22_26->PSS_LOGIC_OUTS22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_26" }, "PSS1.PSS1_LOGIC_OUTS22_27->PSS_LOGIC_OUTS22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_27" }, "PSS1.PSS1_LOGIC_OUTS22_28->PSS_LOGIC_OUTS22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_28" }, "PSS1.PSS1_LOGIC_OUTS22_29->PSS_LOGIC_OUTS22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_29" }, "PSS1.PSS1_LOGIC_OUTS22_3->PSS0_LOGIC_OUTS22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_3" }, "PSS1.PSS1_LOGIC_OUTS22_30->PSS_LOGIC_OUTS22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_30" }, "PSS1.PSS1_LOGIC_OUTS22_31->PSS_LOGIC_OUTS22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_31" }, "PSS1.PSS1_LOGIC_OUTS22_32->PSS_LOGIC_OUTS22_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_32" }, "PSS1.PSS1_LOGIC_OUTS22_33->PSS_LOGIC_OUTS22_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_33" }, "PSS1.PSS1_LOGIC_OUTS22_34->PSS_LOGIC_OUTS22_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_34" }, "PSS1.PSS1_LOGIC_OUTS22_35->PSS_LOGIC_OUTS22_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_35" }, "PSS1.PSS1_LOGIC_OUTS22_36->PSS_LOGIC_OUTS22_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_36" }, "PSS1.PSS1_LOGIC_OUTS22_37->PSS_LOGIC_OUTS22_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_37" }, "PSS1.PSS1_LOGIC_OUTS22_38->PSS_LOGIC_OUTS22_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_38" }, "PSS1.PSS1_LOGIC_OUTS22_39->PSS_LOGIC_OUTS22_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_39" }, "PSS1.PSS1_LOGIC_OUTS22_4->PSS0_LOGIC_OUTS22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_4" }, "PSS1.PSS1_LOGIC_OUTS22_5->PSS0_LOGIC_OUTS22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_5" }, "PSS1.PSS1_LOGIC_OUTS22_6->PSS0_LOGIC_OUTS22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_6" }, "PSS1.PSS1_LOGIC_OUTS22_7->PSS0_LOGIC_OUTS22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_7" }, "PSS1.PSS1_LOGIC_OUTS22_8->PSS0_LOGIC_OUTS22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_8" }, "PSS1.PSS1_LOGIC_OUTS22_9->PSS0_LOGIC_OUTS22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_9" }, "PSS1.PSS1_LOGIC_OUTS23_0->PSS0_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_0" }, "PSS1.PSS1_LOGIC_OUTS23_1->PSS0_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_1" }, "PSS1.PSS1_LOGIC_OUTS23_10->PSS0_LOGIC_OUTS23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_10" }, "PSS1.PSS1_LOGIC_OUTS23_11->PSS0_LOGIC_OUTS23_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_11" }, "PSS1.PSS1_LOGIC_OUTS23_12->PSS0_LOGIC_OUTS23_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_12" }, "PSS1.PSS1_LOGIC_OUTS23_13->PSS0_LOGIC_OUTS23_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_13" }, "PSS1.PSS1_LOGIC_OUTS23_14->PSS0_LOGIC_OUTS23_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_14" }, "PSS1.PSS1_LOGIC_OUTS23_15->PSS0_LOGIC_OUTS23_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_15" }, "PSS1.PSS1_LOGIC_OUTS23_16->PSS0_LOGIC_OUTS23_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_16" }, "PSS1.PSS1_LOGIC_OUTS23_17->PSS0_LOGIC_OUTS23_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_17" }, "PSS1.PSS1_LOGIC_OUTS23_18->PSS0_LOGIC_OUTS23_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_18" }, "PSS1.PSS1_LOGIC_OUTS23_19->PSS0_LOGIC_OUTS23_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_19" }, "PSS1.PSS1_LOGIC_OUTS23_2->PSS0_LOGIC_OUTS23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_2" }, "PSS1.PSS1_LOGIC_OUTS23_20->PSS_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_20" }, "PSS1.PSS1_LOGIC_OUTS23_21->PSS_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_21" }, "PSS1.PSS1_LOGIC_OUTS23_22->PSS_LOGIC_OUTS23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_22" }, "PSS1.PSS1_LOGIC_OUTS23_23->PSS_LOGIC_OUTS23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_23" }, "PSS1.PSS1_LOGIC_OUTS23_24->PSS_LOGIC_OUTS23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_24" }, "PSS1.PSS1_LOGIC_OUTS23_25->PSS_LOGIC_OUTS23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_25" }, "PSS1.PSS1_LOGIC_OUTS23_26->PSS_LOGIC_OUTS23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_26" }, "PSS1.PSS1_LOGIC_OUTS23_27->PSS_LOGIC_OUTS23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_27" }, "PSS1.PSS1_LOGIC_OUTS23_28->PSS_LOGIC_OUTS23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_28" }, "PSS1.PSS1_LOGIC_OUTS23_29->PSS_LOGIC_OUTS23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_29" }, "PSS1.PSS1_LOGIC_OUTS23_3->PSS0_LOGIC_OUTS23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_3" }, "PSS1.PSS1_LOGIC_OUTS23_30->PSS_LOGIC_OUTS23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_30" }, "PSS1.PSS1_LOGIC_OUTS23_31->PSS_LOGIC_OUTS23_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_31" }, "PSS1.PSS1_LOGIC_OUTS23_32->PSS_LOGIC_OUTS23_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_32" }, "PSS1.PSS1_LOGIC_OUTS23_33->PSS_LOGIC_OUTS23_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_33" }, "PSS1.PSS1_LOGIC_OUTS23_34->PSS_LOGIC_OUTS23_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_34" }, "PSS1.PSS1_LOGIC_OUTS23_35->PSS_LOGIC_OUTS23_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_35" }, "PSS1.PSS1_LOGIC_OUTS23_36->PSS_LOGIC_OUTS23_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_36" }, "PSS1.PSS1_LOGIC_OUTS23_37->PSS_LOGIC_OUTS23_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_37" }, "PSS1.PSS1_LOGIC_OUTS23_38->PSS_LOGIC_OUTS23_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_38" }, "PSS1.PSS1_LOGIC_OUTS23_39->PSS_LOGIC_OUTS23_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_39" }, "PSS1.PSS1_LOGIC_OUTS23_4->PSS0_LOGIC_OUTS23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_4" }, "PSS1.PSS1_LOGIC_OUTS23_5->PSS0_LOGIC_OUTS23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_5" }, "PSS1.PSS1_LOGIC_OUTS23_6->PSS0_LOGIC_OUTS23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_6" }, "PSS1.PSS1_LOGIC_OUTS23_7->PSS0_LOGIC_OUTS23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_7" }, "PSS1.PSS1_LOGIC_OUTS23_8->PSS0_LOGIC_OUTS23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_8" }, "PSS1.PSS1_LOGIC_OUTS23_9->PSS0_LOGIC_OUTS23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_9" }, "PSS1.PSS1_LOGIC_OUTS2_0->PSS0_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_0" }, "PSS1.PSS1_LOGIC_OUTS2_1->PSS0_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_1" }, "PSS1.PSS1_LOGIC_OUTS2_10->PSS0_LOGIC_OUTS2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_10" }, "PSS1.PSS1_LOGIC_OUTS2_11->PSS0_LOGIC_OUTS2_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_11" }, "PSS1.PSS1_LOGIC_OUTS2_12->PSS0_LOGIC_OUTS2_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_12" }, "PSS1.PSS1_LOGIC_OUTS2_13->PSS0_LOGIC_OUTS2_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_13" }, "PSS1.PSS1_LOGIC_OUTS2_14->PSS0_LOGIC_OUTS2_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_14" }, "PSS1.PSS1_LOGIC_OUTS2_15->PSS0_LOGIC_OUTS2_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_15" }, "PSS1.PSS1_LOGIC_OUTS2_16->PSS0_LOGIC_OUTS2_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_16" }, "PSS1.PSS1_LOGIC_OUTS2_17->PSS0_LOGIC_OUTS2_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_17" }, "PSS1.PSS1_LOGIC_OUTS2_18->PSS0_LOGIC_OUTS2_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_18" }, "PSS1.PSS1_LOGIC_OUTS2_19->PSS0_LOGIC_OUTS2_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_19" }, "PSS1.PSS1_LOGIC_OUTS2_2->PSS0_LOGIC_OUTS2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_2" }, "PSS1.PSS1_LOGIC_OUTS2_20->PSS_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_20" }, "PSS1.PSS1_LOGIC_OUTS2_21->PSS_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_21" }, "PSS1.PSS1_LOGIC_OUTS2_22->PSS_LOGIC_OUTS2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_22" }, "PSS1.PSS1_LOGIC_OUTS2_23->PSS_LOGIC_OUTS2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_23" }, "PSS1.PSS1_LOGIC_OUTS2_24->PSS_LOGIC_OUTS2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_24" }, "PSS1.PSS1_LOGIC_OUTS2_25->PSS_LOGIC_OUTS2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_25" }, "PSS1.PSS1_LOGIC_OUTS2_26->PSS_LOGIC_OUTS2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_26" }, "PSS1.PSS1_LOGIC_OUTS2_27->PSS_LOGIC_OUTS2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_27" }, "PSS1.PSS1_LOGIC_OUTS2_28->PSS_LOGIC_OUTS2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_28" }, "PSS1.PSS1_LOGIC_OUTS2_29->PSS_LOGIC_OUTS2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_29" }, "PSS1.PSS1_LOGIC_OUTS2_3->PSS0_LOGIC_OUTS2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_3" }, "PSS1.PSS1_LOGIC_OUTS2_30->PSS_LOGIC_OUTS2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_30" }, "PSS1.PSS1_LOGIC_OUTS2_31->PSS_LOGIC_OUTS2_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_31" }, "PSS1.PSS1_LOGIC_OUTS2_32->PSS_LOGIC_OUTS2_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_32" }, "PSS1.PSS1_LOGIC_OUTS2_33->PSS_LOGIC_OUTS2_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_33" }, "PSS1.PSS1_LOGIC_OUTS2_34->PSS_LOGIC_OUTS2_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_34" }, "PSS1.PSS1_LOGIC_OUTS2_35->PSS_LOGIC_OUTS2_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_35" }, "PSS1.PSS1_LOGIC_OUTS2_36->PSS_LOGIC_OUTS2_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_36" }, "PSS1.PSS1_LOGIC_OUTS2_37->PSS_LOGIC_OUTS2_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_37" }, "PSS1.PSS1_LOGIC_OUTS2_38->PSS_LOGIC_OUTS2_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_38" }, "PSS1.PSS1_LOGIC_OUTS2_39->PSS_LOGIC_OUTS2_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_39" }, "PSS1.PSS1_LOGIC_OUTS2_4->PSS0_LOGIC_OUTS2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_4" }, "PSS1.PSS1_LOGIC_OUTS2_5->PSS0_LOGIC_OUTS2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_5" }, "PSS1.PSS1_LOGIC_OUTS2_6->PSS0_LOGIC_OUTS2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_6" }, "PSS1.PSS1_LOGIC_OUTS2_7->PSS0_LOGIC_OUTS2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_7" }, "PSS1.PSS1_LOGIC_OUTS2_8->PSS0_LOGIC_OUTS2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_8" }, "PSS1.PSS1_LOGIC_OUTS2_9->PSS0_LOGIC_OUTS2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_9" }, "PSS1.PSS1_LOGIC_OUTS3_0->PSS0_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_0" }, "PSS1.PSS1_LOGIC_OUTS3_1->PSS0_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_1" }, "PSS1.PSS1_LOGIC_OUTS3_10->PSS0_LOGIC_OUTS3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_10" }, "PSS1.PSS1_LOGIC_OUTS3_11->PSS0_LOGIC_OUTS3_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_11" }, "PSS1.PSS1_LOGIC_OUTS3_12->PSS0_LOGIC_OUTS3_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_12" }, "PSS1.PSS1_LOGIC_OUTS3_13->PSS0_LOGIC_OUTS3_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_13" }, "PSS1.PSS1_LOGIC_OUTS3_14->PSS0_LOGIC_OUTS3_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_14" }, "PSS1.PSS1_LOGIC_OUTS3_15->PSS0_LOGIC_OUTS3_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_15" }, "PSS1.PSS1_LOGIC_OUTS3_16->PSS0_LOGIC_OUTS3_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_16" }, "PSS1.PSS1_LOGIC_OUTS3_17->PSS0_LOGIC_OUTS3_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_17" }, "PSS1.PSS1_LOGIC_OUTS3_18->PSS0_LOGIC_OUTS3_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_18" }, "PSS1.PSS1_LOGIC_OUTS3_19->PSS0_LOGIC_OUTS3_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_19" }, "PSS1.PSS1_LOGIC_OUTS3_2->PSS0_LOGIC_OUTS3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_2" }, "PSS1.PSS1_LOGIC_OUTS3_20->PSS_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_20" }, "PSS1.PSS1_LOGIC_OUTS3_21->PSS_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_21" }, "PSS1.PSS1_LOGIC_OUTS3_22->PSS_LOGIC_OUTS3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_22" }, "PSS1.PSS1_LOGIC_OUTS3_23->PSS_LOGIC_OUTS3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_23" }, "PSS1.PSS1_LOGIC_OUTS3_24->PSS_LOGIC_OUTS3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_24" }, "PSS1.PSS1_LOGIC_OUTS3_25->PSS_LOGIC_OUTS3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_25" }, "PSS1.PSS1_LOGIC_OUTS3_26->PSS_LOGIC_OUTS3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_26" }, "PSS1.PSS1_LOGIC_OUTS3_27->PSS_LOGIC_OUTS3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_27" }, "PSS1.PSS1_LOGIC_OUTS3_28->PSS_LOGIC_OUTS3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_28" }, "PSS1.PSS1_LOGIC_OUTS3_29->PSS_LOGIC_OUTS3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_29" }, "PSS1.PSS1_LOGIC_OUTS3_3->PSS0_LOGIC_OUTS3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_3" }, "PSS1.PSS1_LOGIC_OUTS3_30->PSS_LOGIC_OUTS3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_30" }, "PSS1.PSS1_LOGIC_OUTS3_31->PSS_LOGIC_OUTS3_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_31" }, "PSS1.PSS1_LOGIC_OUTS3_32->PSS_LOGIC_OUTS3_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_32" }, "PSS1.PSS1_LOGIC_OUTS3_33->PSS_LOGIC_OUTS3_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_33" }, "PSS1.PSS1_LOGIC_OUTS3_34->PSS_LOGIC_OUTS3_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_34" }, "PSS1.PSS1_LOGIC_OUTS3_35->PSS_LOGIC_OUTS3_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_35" }, "PSS1.PSS1_LOGIC_OUTS3_36->PSS_LOGIC_OUTS3_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_36" }, "PSS1.PSS1_LOGIC_OUTS3_37->PSS_LOGIC_OUTS3_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_37" }, "PSS1.PSS1_LOGIC_OUTS3_38->PSS_LOGIC_OUTS3_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_38" }, "PSS1.PSS1_LOGIC_OUTS3_39->PSS_LOGIC_OUTS3_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_39" }, "PSS1.PSS1_LOGIC_OUTS3_4->PSS0_LOGIC_OUTS3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_4" }, "PSS1.PSS1_LOGIC_OUTS3_5->PSS0_LOGIC_OUTS3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_5" }, "PSS1.PSS1_LOGIC_OUTS3_6->PSS0_LOGIC_OUTS3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_6" }, "PSS1.PSS1_LOGIC_OUTS3_7->PSS0_LOGIC_OUTS3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_7" }, "PSS1.PSS1_LOGIC_OUTS3_8->PSS0_LOGIC_OUTS3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_8" }, "PSS1.PSS1_LOGIC_OUTS3_9->PSS0_LOGIC_OUTS3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_9" }, "PSS1.PSS1_LOGIC_OUTS4_0->PSS0_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_0" }, "PSS1.PSS1_LOGIC_OUTS4_1->PSS0_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_1" }, "PSS1.PSS1_LOGIC_OUTS4_10->PSS0_LOGIC_OUTS4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_10" }, "PSS1.PSS1_LOGIC_OUTS4_11->PSS0_LOGIC_OUTS4_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_11" }, "PSS1.PSS1_LOGIC_OUTS4_12->PSS0_LOGIC_OUTS4_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_12" }, "PSS1.PSS1_LOGIC_OUTS4_13->PSS0_LOGIC_OUTS4_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_13" }, "PSS1.PSS1_LOGIC_OUTS4_14->PSS0_LOGIC_OUTS4_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_14" }, "PSS1.PSS1_LOGIC_OUTS4_15->PSS0_LOGIC_OUTS4_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_15" }, "PSS1.PSS1_LOGIC_OUTS4_16->PSS0_LOGIC_OUTS4_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_16" }, "PSS1.PSS1_LOGIC_OUTS4_17->PSS0_LOGIC_OUTS4_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_17" }, "PSS1.PSS1_LOGIC_OUTS4_18->PSS0_LOGIC_OUTS4_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_18" }, "PSS1.PSS1_LOGIC_OUTS4_19->PSS0_LOGIC_OUTS4_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_19" }, "PSS1.PSS1_LOGIC_OUTS4_2->PSS0_LOGIC_OUTS4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_2" }, "PSS1.PSS1_LOGIC_OUTS4_20->PSS_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_20" }, "PSS1.PSS1_LOGIC_OUTS4_21->PSS_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_21" }, "PSS1.PSS1_LOGIC_OUTS4_22->PSS_LOGIC_OUTS4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_22" }, "PSS1.PSS1_LOGIC_OUTS4_23->PSS_LOGIC_OUTS4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_23" }, "PSS1.PSS1_LOGIC_OUTS4_24->PSS_LOGIC_OUTS4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_24" }, "PSS1.PSS1_LOGIC_OUTS4_25->PSS_LOGIC_OUTS4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_25" }, "PSS1.PSS1_LOGIC_OUTS4_26->PSS_LOGIC_OUTS4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_26" }, "PSS1.PSS1_LOGIC_OUTS4_27->PSS_LOGIC_OUTS4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_27" }, "PSS1.PSS1_LOGIC_OUTS4_28->PSS_LOGIC_OUTS4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_28" }, "PSS1.PSS1_LOGIC_OUTS4_29->PSS_LOGIC_OUTS4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_29" }, "PSS1.PSS1_LOGIC_OUTS4_3->PSS0_LOGIC_OUTS4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_3" }, "PSS1.PSS1_LOGIC_OUTS4_30->PSS_LOGIC_OUTS4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_30" }, "PSS1.PSS1_LOGIC_OUTS4_31->PSS_LOGIC_OUTS4_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_31" }, "PSS1.PSS1_LOGIC_OUTS4_32->PSS_LOGIC_OUTS4_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_32" }, "PSS1.PSS1_LOGIC_OUTS4_33->PSS_LOGIC_OUTS4_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_33" }, "PSS1.PSS1_LOGIC_OUTS4_34->PSS_LOGIC_OUTS4_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_34" }, "PSS1.PSS1_LOGIC_OUTS4_35->PSS_LOGIC_OUTS4_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_35" }, "PSS1.PSS1_LOGIC_OUTS4_36->PSS_LOGIC_OUTS4_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_36" }, "PSS1.PSS1_LOGIC_OUTS4_37->PSS_LOGIC_OUTS4_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_37" }, "PSS1.PSS1_LOGIC_OUTS4_38->PSS_LOGIC_OUTS4_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_38" }, "PSS1.PSS1_LOGIC_OUTS4_39->PSS_LOGIC_OUTS4_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_39" }, "PSS1.PSS1_LOGIC_OUTS4_4->PSS0_LOGIC_OUTS4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_4" }, "PSS1.PSS1_LOGIC_OUTS4_5->PSS0_LOGIC_OUTS4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_5" }, "PSS1.PSS1_LOGIC_OUTS4_6->PSS0_LOGIC_OUTS4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_6" }, "PSS1.PSS1_LOGIC_OUTS4_7->PSS0_LOGIC_OUTS4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_7" }, "PSS1.PSS1_LOGIC_OUTS4_8->PSS0_LOGIC_OUTS4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_8" }, "PSS1.PSS1_LOGIC_OUTS4_9->PSS0_LOGIC_OUTS4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_9" }, "PSS1.PSS1_LOGIC_OUTS5_0->PSS0_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_0" }, "PSS1.PSS1_LOGIC_OUTS5_1->PSS0_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_1" }, "PSS1.PSS1_LOGIC_OUTS5_10->PSS0_LOGIC_OUTS5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_10" }, "PSS1.PSS1_LOGIC_OUTS5_11->PSS0_LOGIC_OUTS5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_11" }, "PSS1.PSS1_LOGIC_OUTS5_12->PSS0_LOGIC_OUTS5_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_12" }, "PSS1.PSS1_LOGIC_OUTS5_13->PSS0_LOGIC_OUTS5_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_13" }, "PSS1.PSS1_LOGIC_OUTS5_14->PSS0_LOGIC_OUTS5_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_14" }, "PSS1.PSS1_LOGIC_OUTS5_15->PSS0_LOGIC_OUTS5_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_15" }, "PSS1.PSS1_LOGIC_OUTS5_16->PSS0_LOGIC_OUTS5_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_16" }, "PSS1.PSS1_LOGIC_OUTS5_17->PSS0_LOGIC_OUTS5_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_17" }, "PSS1.PSS1_LOGIC_OUTS5_18->PSS0_LOGIC_OUTS5_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_18" }, "PSS1.PSS1_LOGIC_OUTS5_19->PSS0_LOGIC_OUTS5_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_19" }, "PSS1.PSS1_LOGIC_OUTS5_2->PSS0_LOGIC_OUTS5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_2" }, "PSS1.PSS1_LOGIC_OUTS5_20->PSS_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_20" }, "PSS1.PSS1_LOGIC_OUTS5_21->PSS_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_21" }, "PSS1.PSS1_LOGIC_OUTS5_22->PSS_LOGIC_OUTS5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_22" }, "PSS1.PSS1_LOGIC_OUTS5_23->PSS_LOGIC_OUTS5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_23" }, "PSS1.PSS1_LOGIC_OUTS5_24->PSS_LOGIC_OUTS5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_24" }, "PSS1.PSS1_LOGIC_OUTS5_25->PSS_LOGIC_OUTS5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_25" }, "PSS1.PSS1_LOGIC_OUTS5_26->PSS_LOGIC_OUTS5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_26" }, "PSS1.PSS1_LOGIC_OUTS5_27->PSS_LOGIC_OUTS5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_27" }, "PSS1.PSS1_LOGIC_OUTS5_28->PSS_LOGIC_OUTS5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_28" }, "PSS1.PSS1_LOGIC_OUTS5_29->PSS_LOGIC_OUTS5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_29" }, "PSS1.PSS1_LOGIC_OUTS5_3->PSS0_LOGIC_OUTS5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_3" }, "PSS1.PSS1_LOGIC_OUTS5_30->PSS_LOGIC_OUTS5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_30" }, "PSS1.PSS1_LOGIC_OUTS5_31->PSS_LOGIC_OUTS5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_31" }, "PSS1.PSS1_LOGIC_OUTS5_32->PSS_LOGIC_OUTS5_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_32" }, "PSS1.PSS1_LOGIC_OUTS5_33->PSS_LOGIC_OUTS5_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_33" }, "PSS1.PSS1_LOGIC_OUTS5_34->PSS_LOGIC_OUTS5_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_34" }, "PSS1.PSS1_LOGIC_OUTS5_35->PSS_LOGIC_OUTS5_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_35" }, "PSS1.PSS1_LOGIC_OUTS5_36->PSS_LOGIC_OUTS5_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_36" }, "PSS1.PSS1_LOGIC_OUTS5_37->PSS_LOGIC_OUTS5_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_37" }, "PSS1.PSS1_LOGIC_OUTS5_38->PSS_LOGIC_OUTS5_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_38" }, "PSS1.PSS1_LOGIC_OUTS5_39->PSS_LOGIC_OUTS5_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_39" }, "PSS1.PSS1_LOGIC_OUTS5_4->PSS0_LOGIC_OUTS5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_4" }, "PSS1.PSS1_LOGIC_OUTS5_5->PSS0_LOGIC_OUTS5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_5" }, "PSS1.PSS1_LOGIC_OUTS5_6->PSS0_LOGIC_OUTS5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_6" }, "PSS1.PSS1_LOGIC_OUTS5_7->PSS0_LOGIC_OUTS5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_7" }, "PSS1.PSS1_LOGIC_OUTS5_8->PSS0_LOGIC_OUTS5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_8" }, "PSS1.PSS1_LOGIC_OUTS5_9->PSS0_LOGIC_OUTS5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_9" }, "PSS1.PSS1_LOGIC_OUTS6_0->PSS0_LOGIC_OUTS6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_0" }, "PSS1.PSS1_LOGIC_OUTS6_1->PSS0_LOGIC_OUTS6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_1" }, "PSS1.PSS1_LOGIC_OUTS6_10->PSS0_LOGIC_OUTS6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_10" }, "PSS1.PSS1_LOGIC_OUTS6_11->PSS0_LOGIC_OUTS6_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_11" }, "PSS1.PSS1_LOGIC_OUTS6_12->PSS0_LOGIC_OUTS6_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_12" }, "PSS1.PSS1_LOGIC_OUTS6_13->PSS0_LOGIC_OUTS6_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_13" }, "PSS1.PSS1_LOGIC_OUTS6_14->PSS0_LOGIC_OUTS6_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_14" }, "PSS1.PSS1_LOGIC_OUTS6_15->PSS0_LOGIC_OUTS6_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_15" }, "PSS1.PSS1_LOGIC_OUTS6_16->PSS0_LOGIC_OUTS6_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_16" }, "PSS1.PSS1_LOGIC_OUTS6_17->PSS0_LOGIC_OUTS6_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_17" }, "PSS1.PSS1_LOGIC_OUTS6_18->PSS0_LOGIC_OUTS6_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_18" }, "PSS1.PSS1_LOGIC_OUTS6_19->PSS0_LOGIC_OUTS6_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_19" }, "PSS1.PSS1_LOGIC_OUTS6_2->PSS0_LOGIC_OUTS6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_2" }, "PSS1.PSS1_LOGIC_OUTS6_20->PSS_LOGIC_OUTS6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_20" }, "PSS1.PSS1_LOGIC_OUTS6_21->PSS_LOGIC_OUTS6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_21" }, "PSS1.PSS1_LOGIC_OUTS6_22->PSS_LOGIC_OUTS6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_22" }, "PSS1.PSS1_LOGIC_OUTS6_23->PSS_LOGIC_OUTS6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_23" }, "PSS1.PSS1_LOGIC_OUTS6_24->PSS_LOGIC_OUTS6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_24" }, "PSS1.PSS1_LOGIC_OUTS6_25->PSS_LOGIC_OUTS6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_25" }, "PSS1.PSS1_LOGIC_OUTS6_26->PSS_LOGIC_OUTS6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_26" }, "PSS1.PSS1_LOGIC_OUTS6_27->PSS_LOGIC_OUTS6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_27" }, "PSS1.PSS1_LOGIC_OUTS6_28->PSS_LOGIC_OUTS6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_28" }, "PSS1.PSS1_LOGIC_OUTS6_29->PSS_LOGIC_OUTS6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_29" }, "PSS1.PSS1_LOGIC_OUTS6_3->PSS0_LOGIC_OUTS6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_3" }, "PSS1.PSS1_LOGIC_OUTS6_30->PSS_LOGIC_OUTS6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_30" }, "PSS1.PSS1_LOGIC_OUTS6_31->PSS_LOGIC_OUTS6_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_31" }, "PSS1.PSS1_LOGIC_OUTS6_32->PSS_LOGIC_OUTS6_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_32" }, "PSS1.PSS1_LOGIC_OUTS6_33->PSS_LOGIC_OUTS6_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_33" }, "PSS1.PSS1_LOGIC_OUTS6_34->PSS_LOGIC_OUTS6_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_34" }, "PSS1.PSS1_LOGIC_OUTS6_35->PSS_LOGIC_OUTS6_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_35" }, "PSS1.PSS1_LOGIC_OUTS6_36->PSS_LOGIC_OUTS6_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_36" }, "PSS1.PSS1_LOGIC_OUTS6_37->PSS_LOGIC_OUTS6_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_37" }, "PSS1.PSS1_LOGIC_OUTS6_38->PSS_LOGIC_OUTS6_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_38" }, "PSS1.PSS1_LOGIC_OUTS6_39->PSS_LOGIC_OUTS6_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_39" }, "PSS1.PSS1_LOGIC_OUTS6_4->PSS0_LOGIC_OUTS6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_4" }, "PSS1.PSS1_LOGIC_OUTS6_5->PSS0_LOGIC_OUTS6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_5" }, "PSS1.PSS1_LOGIC_OUTS6_6->PSS0_LOGIC_OUTS6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_6" }, "PSS1.PSS1_LOGIC_OUTS6_7->PSS0_LOGIC_OUTS6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_7" }, "PSS1.PSS1_LOGIC_OUTS6_8->PSS0_LOGIC_OUTS6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_8" }, "PSS1.PSS1_LOGIC_OUTS6_9->PSS0_LOGIC_OUTS6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_9" }, "PSS1.PSS1_LOGIC_OUTS7_0->PSS0_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_0" }, "PSS1.PSS1_LOGIC_OUTS7_1->PSS0_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_1" }, "PSS1.PSS1_LOGIC_OUTS7_10->PSS0_LOGIC_OUTS7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_10" }, "PSS1.PSS1_LOGIC_OUTS7_11->PSS0_LOGIC_OUTS7_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_11" }, "PSS1.PSS1_LOGIC_OUTS7_12->PSS0_LOGIC_OUTS7_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_12" }, "PSS1.PSS1_LOGIC_OUTS7_13->PSS0_LOGIC_OUTS7_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_13" }, "PSS1.PSS1_LOGIC_OUTS7_14->PSS0_LOGIC_OUTS7_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_14" }, "PSS1.PSS1_LOGIC_OUTS7_15->PSS0_LOGIC_OUTS7_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_15" }, "PSS1.PSS1_LOGIC_OUTS7_16->PSS0_LOGIC_OUTS7_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_16" }, "PSS1.PSS1_LOGIC_OUTS7_17->PSS0_LOGIC_OUTS7_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_17" }, "PSS1.PSS1_LOGIC_OUTS7_18->PSS0_LOGIC_OUTS7_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_18" }, "PSS1.PSS1_LOGIC_OUTS7_19->PSS0_LOGIC_OUTS7_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_19" }, "PSS1.PSS1_LOGIC_OUTS7_2->PSS0_LOGIC_OUTS7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_2" }, "PSS1.PSS1_LOGIC_OUTS7_20->PSS_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_20" }, "PSS1.PSS1_LOGIC_OUTS7_21->PSS_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_21" }, "PSS1.PSS1_LOGIC_OUTS7_22->PSS_LOGIC_OUTS7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_22" }, "PSS1.PSS1_LOGIC_OUTS7_23->PSS_LOGIC_OUTS7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_23" }, "PSS1.PSS1_LOGIC_OUTS7_24->PSS_LOGIC_OUTS7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_24" }, "PSS1.PSS1_LOGIC_OUTS7_25->PSS_LOGIC_OUTS7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_25" }, "PSS1.PSS1_LOGIC_OUTS7_26->PSS_LOGIC_OUTS7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_26" }, "PSS1.PSS1_LOGIC_OUTS7_27->PSS_LOGIC_OUTS7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_27" }, "PSS1.PSS1_LOGIC_OUTS7_28->PSS_LOGIC_OUTS7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_28" }, "PSS1.PSS1_LOGIC_OUTS7_29->PSS_LOGIC_OUTS7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_29" }, "PSS1.PSS1_LOGIC_OUTS7_3->PSS0_LOGIC_OUTS7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_3" }, "PSS1.PSS1_LOGIC_OUTS7_30->PSS_LOGIC_OUTS7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_30" }, "PSS1.PSS1_LOGIC_OUTS7_31->PSS_LOGIC_OUTS7_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_31" }, "PSS1.PSS1_LOGIC_OUTS7_32->PSS_LOGIC_OUTS7_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_32" }, "PSS1.PSS1_LOGIC_OUTS7_33->PSS_LOGIC_OUTS7_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_33" }, "PSS1.PSS1_LOGIC_OUTS7_34->PSS_LOGIC_OUTS7_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_34" }, "PSS1.PSS1_LOGIC_OUTS7_35->PSS_LOGIC_OUTS7_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_35" }, "PSS1.PSS1_LOGIC_OUTS7_36->PSS_LOGIC_OUTS7_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_36" }, "PSS1.PSS1_LOGIC_OUTS7_37->PSS_LOGIC_OUTS7_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_37" }, "PSS1.PSS1_LOGIC_OUTS7_38->PSS_LOGIC_OUTS7_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_38" }, "PSS1.PSS1_LOGIC_OUTS7_39->PSS_LOGIC_OUTS7_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_39" }, "PSS1.PSS1_LOGIC_OUTS7_4->PSS0_LOGIC_OUTS7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_4" }, "PSS1.PSS1_LOGIC_OUTS7_5->PSS0_LOGIC_OUTS7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_5" }, "PSS1.PSS1_LOGIC_OUTS7_6->PSS0_LOGIC_OUTS7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_6" }, "PSS1.PSS1_LOGIC_OUTS7_7->PSS0_LOGIC_OUTS7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_7" }, "PSS1.PSS1_LOGIC_OUTS7_8->PSS0_LOGIC_OUTS7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_8" }, "PSS1.PSS1_LOGIC_OUTS7_9->PSS0_LOGIC_OUTS7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_9" }, "PSS1.PSS1_LOGIC_OUTS8_0->PSS0_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_0" }, "PSS1.PSS1_LOGIC_OUTS8_1->PSS0_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_1" }, "PSS1.PSS1_LOGIC_OUTS8_10->PSS0_LOGIC_OUTS8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_10" }, "PSS1.PSS1_LOGIC_OUTS8_11->PSS0_LOGIC_OUTS8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_11" }, "PSS1.PSS1_LOGIC_OUTS8_12->PSS0_LOGIC_OUTS8_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_12" }, "PSS1.PSS1_LOGIC_OUTS8_13->PSS0_LOGIC_OUTS8_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_13" }, "PSS1.PSS1_LOGIC_OUTS8_14->PSS0_LOGIC_OUTS8_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_14" }, "PSS1.PSS1_LOGIC_OUTS8_15->PSS0_LOGIC_OUTS8_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_15" }, "PSS1.PSS1_LOGIC_OUTS8_16->PSS0_LOGIC_OUTS8_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_16" }, "PSS1.PSS1_LOGIC_OUTS8_17->PSS0_LOGIC_OUTS8_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_17" }, "PSS1.PSS1_LOGIC_OUTS8_18->PSS0_LOGIC_OUTS8_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_18" }, "PSS1.PSS1_LOGIC_OUTS8_19->PSS0_LOGIC_OUTS8_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_19" }, "PSS1.PSS1_LOGIC_OUTS8_2->PSS0_LOGIC_OUTS8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_2" }, "PSS1.PSS1_LOGIC_OUTS8_20->PSS_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_20" }, "PSS1.PSS1_LOGIC_OUTS8_21->PSS_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_21" }, "PSS1.PSS1_LOGIC_OUTS8_22->PSS_LOGIC_OUTS8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_22" }, "PSS1.PSS1_LOGIC_OUTS8_23->PSS_LOGIC_OUTS8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_23" }, "PSS1.PSS1_LOGIC_OUTS8_24->PSS_LOGIC_OUTS8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_24" }, "PSS1.PSS1_LOGIC_OUTS8_25->PSS_LOGIC_OUTS8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_25" }, "PSS1.PSS1_LOGIC_OUTS8_26->PSS_LOGIC_OUTS8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_26" }, "PSS1.PSS1_LOGIC_OUTS8_27->PSS_LOGIC_OUTS8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_27" }, "PSS1.PSS1_LOGIC_OUTS8_28->PSS_LOGIC_OUTS8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_28" }, "PSS1.PSS1_LOGIC_OUTS8_29->PSS_LOGIC_OUTS8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_29" }, "PSS1.PSS1_LOGIC_OUTS8_3->PSS0_LOGIC_OUTS8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_3" }, "PSS1.PSS1_LOGIC_OUTS8_30->PSS_LOGIC_OUTS8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_30" }, "PSS1.PSS1_LOGIC_OUTS8_31->PSS_LOGIC_OUTS8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_31" }, "PSS1.PSS1_LOGIC_OUTS8_32->PSS_LOGIC_OUTS8_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_32" }, "PSS1.PSS1_LOGIC_OUTS8_33->PSS_LOGIC_OUTS8_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_33" }, "PSS1.PSS1_LOGIC_OUTS8_34->PSS_LOGIC_OUTS8_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_34" }, "PSS1.PSS1_LOGIC_OUTS8_35->PSS_LOGIC_OUTS8_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_35" }, "PSS1.PSS1_LOGIC_OUTS8_36->PSS_LOGIC_OUTS8_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_36" }, "PSS1.PSS1_LOGIC_OUTS8_37->PSS_LOGIC_OUTS8_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_37" }, "PSS1.PSS1_LOGIC_OUTS8_38->PSS_LOGIC_OUTS8_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_38" }, "PSS1.PSS1_LOGIC_OUTS8_39->PSS_LOGIC_OUTS8_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_39" }, "PSS1.PSS1_LOGIC_OUTS8_4->PSS0_LOGIC_OUTS8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_4" }, "PSS1.PSS1_LOGIC_OUTS8_5->PSS0_LOGIC_OUTS8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_5" }, "PSS1.PSS1_LOGIC_OUTS8_6->PSS0_LOGIC_OUTS8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_6" }, "PSS1.PSS1_LOGIC_OUTS8_7->PSS0_LOGIC_OUTS8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_7" }, "PSS1.PSS1_LOGIC_OUTS8_8->PSS0_LOGIC_OUTS8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_8" }, "PSS1.PSS1_LOGIC_OUTS8_9->PSS0_LOGIC_OUTS8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_9" }, "PSS1.PSS1_LOGIC_OUTS9_0->PSS0_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_0" }, "PSS1.PSS1_LOGIC_OUTS9_1->PSS0_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_1" }, "PSS1.PSS1_LOGIC_OUTS9_10->PSS0_LOGIC_OUTS9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_10" }, "PSS1.PSS1_LOGIC_OUTS9_11->PSS0_LOGIC_OUTS9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_11" }, "PSS1.PSS1_LOGIC_OUTS9_12->PSS0_LOGIC_OUTS9_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_12" }, "PSS1.PSS1_LOGIC_OUTS9_13->PSS0_LOGIC_OUTS9_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_13" }, "PSS1.PSS1_LOGIC_OUTS9_14->PSS0_LOGIC_OUTS9_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_14" }, "PSS1.PSS1_LOGIC_OUTS9_15->PSS0_LOGIC_OUTS9_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_15" }, "PSS1.PSS1_LOGIC_OUTS9_16->PSS0_LOGIC_OUTS9_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_16" }, "PSS1.PSS1_LOGIC_OUTS9_17->PSS0_LOGIC_OUTS9_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_17" }, "PSS1.PSS1_LOGIC_OUTS9_18->PSS0_LOGIC_OUTS9_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_18" }, "PSS1.PSS1_LOGIC_OUTS9_19->PSS0_LOGIC_OUTS9_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_19" }, "PSS1.PSS1_LOGIC_OUTS9_2->PSS0_LOGIC_OUTS9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_2" }, "PSS1.PSS1_LOGIC_OUTS9_20->PSS_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_20" }, "PSS1.PSS1_LOGIC_OUTS9_21->PSS_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_21" }, "PSS1.PSS1_LOGIC_OUTS9_22->PSS_LOGIC_OUTS9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_22" }, "PSS1.PSS1_LOGIC_OUTS9_23->PSS_LOGIC_OUTS9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_23" }, "PSS1.PSS1_LOGIC_OUTS9_24->PSS_LOGIC_OUTS9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_24" }, "PSS1.PSS1_LOGIC_OUTS9_25->PSS_LOGIC_OUTS9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_25" }, "PSS1.PSS1_LOGIC_OUTS9_26->PSS_LOGIC_OUTS9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_26" }, "PSS1.PSS1_LOGIC_OUTS9_27->PSS_LOGIC_OUTS9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_27" }, "PSS1.PSS1_LOGIC_OUTS9_28->PSS_LOGIC_OUTS9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_28" }, "PSS1.PSS1_LOGIC_OUTS9_29->PSS_LOGIC_OUTS9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_29" }, "PSS1.PSS1_LOGIC_OUTS9_3->PSS0_LOGIC_OUTS9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_3" }, "PSS1.PSS1_LOGIC_OUTS9_30->PSS_LOGIC_OUTS9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_30" }, "PSS1.PSS1_LOGIC_OUTS9_31->PSS_LOGIC_OUTS9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_31" }, "PSS1.PSS1_LOGIC_OUTS9_32->PSS_LOGIC_OUTS9_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_32" }, "PSS1.PSS1_LOGIC_OUTS9_33->PSS_LOGIC_OUTS9_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_33" }, "PSS1.PSS1_LOGIC_OUTS9_34->PSS_LOGIC_OUTS9_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_34" }, "PSS1.PSS1_LOGIC_OUTS9_35->PSS_LOGIC_OUTS9_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_35" }, "PSS1.PSS1_LOGIC_OUTS9_36->PSS_LOGIC_OUTS9_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_36" }, "PSS1.PSS1_LOGIC_OUTS9_37->PSS_LOGIC_OUTS9_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_37" }, "PSS1.PSS1_LOGIC_OUTS9_38->PSS_LOGIC_OUTS9_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_38" }, "PSS1.PSS1_LOGIC_OUTS9_39->PSS_LOGIC_OUTS9_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_39" }, "PSS1.PSS1_LOGIC_OUTS9_4->PSS0_LOGIC_OUTS9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_4" }, "PSS1.PSS1_LOGIC_OUTS9_5->PSS0_LOGIC_OUTS9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_5" }, "PSS1.PSS1_LOGIC_OUTS9_6->PSS0_LOGIC_OUTS9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_6" }, "PSS1.PSS1_LOGIC_OUTS9_7->PSS0_LOGIC_OUTS9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_7" }, "PSS1.PSS1_LOGIC_OUTS9_8->PSS0_LOGIC_OUTS9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_8" }, "PSS1.PSS1_LOGIC_OUTS9_9->PSS0_LOGIC_OUTS9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_9" }, "PSS1.PSS_CLK_B0_0->PSS1_CLK_B0_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_0" }, "PSS1.PSS_CLK_B0_1->PSS1_CLK_B0_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_1" }, "PSS1.PSS_CLK_B0_10->PSS1_CLK_B0_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_10" }, "PSS1.PSS_CLK_B0_11->PSS1_CLK_B0_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_11" }, "PSS1.PSS_CLK_B0_12->PSS1_CLK_B0_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_12" }, "PSS1.PSS_CLK_B0_13->PSS1_CLK_B0_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_13" }, "PSS1.PSS_CLK_B0_14->PSS1_CLK_B0_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_14" }, "PSS1.PSS_CLK_B0_15->PSS1_CLK_B0_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_15" }, "PSS1.PSS_CLK_B0_16->PSS1_CLK_B0_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_16" }, "PSS1.PSS_CLK_B0_17->PSS1_CLK_B0_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_17" }, "PSS1.PSS_CLK_B0_18->PSS1_CLK_B0_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_18" }, "PSS1.PSS_CLK_B0_19->PSS1_CLK_B0_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_19" }, "PSS1.PSS_CLK_B0_2->PSS1_CLK_B0_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_2" }, "PSS1.PSS_CLK_B0_3->PSS1_CLK_B0_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_3" }, "PSS1.PSS_CLK_B0_4->PSS1_CLK_B0_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_4" }, "PSS1.PSS_CLK_B0_5->PSS1_CLK_B0_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_5" }, "PSS1.PSS_CLK_B0_6->PSS1_CLK_B0_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_6" }, "PSS1.PSS_CLK_B0_7->PSS1_CLK_B0_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_7" }, "PSS1.PSS_CLK_B0_8->PSS1_CLK_B0_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_8" }, "PSS1.PSS_CLK_B0_9->PSS1_CLK_B0_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_9" }, "PSS1.PSS_CLK_B1_0->PSS1_CLK_B1_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_0" }, "PSS1.PSS_CLK_B1_1->PSS1_CLK_B1_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_1" }, "PSS1.PSS_CLK_B1_10->PSS1_CLK_B1_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_10" }, "PSS1.PSS_CLK_B1_11->PSS1_CLK_B1_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_11" }, "PSS1.PSS_CLK_B1_12->PSS1_CLK_B1_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_12" }, "PSS1.PSS_CLK_B1_13->PSS1_CLK_B1_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_13" }, "PSS1.PSS_CLK_B1_14->PSS1_CLK_B1_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_14" }, "PSS1.PSS_CLK_B1_15->PSS1_CLK_B1_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_15" }, "PSS1.PSS_CLK_B1_16->PSS1_CLK_B1_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_16" }, "PSS1.PSS_CLK_B1_17->PSS1_CLK_B1_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_17" }, "PSS1.PSS_CLK_B1_18->PSS1_CLK_B1_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_18" }, "PSS1.PSS_CLK_B1_19->PSS1_CLK_B1_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_19" }, "PSS1.PSS_CLK_B1_2->PSS1_CLK_B1_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_2" }, "PSS1.PSS_CLK_B1_3->PSS1_CLK_B1_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_3" }, "PSS1.PSS_CLK_B1_4->PSS1_CLK_B1_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_4" }, "PSS1.PSS_CLK_B1_5->PSS1_CLK_B1_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_5" }, "PSS1.PSS_CLK_B1_6->PSS1_CLK_B1_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_6" }, "PSS1.PSS_CLK_B1_7->PSS1_CLK_B1_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_7" }, "PSS1.PSS_CLK_B1_8->PSS1_CLK_B1_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_8" }, "PSS1.PSS_CLK_B1_9->PSS1_CLK_B1_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_9" }, "PSS1.PSS_FCLKCLK0->>PSS_HCLK_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PSS_HCLK_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PSS_FCLKCLK0" }, "PSS1.PSS_FCLKCLK1->>PSS_HCLK_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PSS_HCLK_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PSS_FCLKCLK1" }, "PSS1.PSS_FCLKCLK2->>PSS_HCLK_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PSS_HCLK_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PSS_FCLKCLK2" }, "PSS1.PSS_FCLKCLK3->>PSS_HCLK_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PSS_HCLK_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PSS_FCLKCLK3" }, "PSS1.PSS_IMUX_B0_0->PSS1_IMUX_B0_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_0" }, "PSS1.PSS_IMUX_B0_1->PSS1_IMUX_B0_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_1" }, "PSS1.PSS_IMUX_B0_10->PSS1_IMUX_B0_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_10" }, "PSS1.PSS_IMUX_B0_11->PSS1_IMUX_B0_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_11" }, "PSS1.PSS_IMUX_B0_12->PSS1_IMUX_B0_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_12" }, "PSS1.PSS_IMUX_B0_13->PSS1_IMUX_B0_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_13" }, "PSS1.PSS_IMUX_B0_14->PSS1_IMUX_B0_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_14" }, "PSS1.PSS_IMUX_B0_15->PSS1_IMUX_B0_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_15" }, "PSS1.PSS_IMUX_B0_16->PSS1_IMUX_B0_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_16" }, "PSS1.PSS_IMUX_B0_17->PSS1_IMUX_B0_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_17" }, "PSS1.PSS_IMUX_B0_18->PSS1_IMUX_B0_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_18" }, "PSS1.PSS_IMUX_B0_19->PSS1_IMUX_B0_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_19" }, "PSS1.PSS_IMUX_B0_2->PSS1_IMUX_B0_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_2" }, "PSS1.PSS_IMUX_B0_3->PSS1_IMUX_B0_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_3" }, "PSS1.PSS_IMUX_B0_4->PSS1_IMUX_B0_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_4" }, "PSS1.PSS_IMUX_B0_5->PSS1_IMUX_B0_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_5" }, "PSS1.PSS_IMUX_B0_6->PSS1_IMUX_B0_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_6" }, "PSS1.PSS_IMUX_B0_7->PSS1_IMUX_B0_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_7" }, "PSS1.PSS_IMUX_B0_8->PSS1_IMUX_B0_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_8" }, "PSS1.PSS_IMUX_B0_9->PSS1_IMUX_B0_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_9" }, "PSS1.PSS_IMUX_B10_0->PSS1_IMUX_B10_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_0" }, "PSS1.PSS_IMUX_B10_1->PSS1_IMUX_B10_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_1" }, "PSS1.PSS_IMUX_B10_10->PSS1_IMUX_B10_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_10" }, "PSS1.PSS_IMUX_B10_11->PSS1_IMUX_B10_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_11" }, "PSS1.PSS_IMUX_B10_12->PSS1_IMUX_B10_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_12" }, "PSS1.PSS_IMUX_B10_13->PSS1_IMUX_B10_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_13" }, "PSS1.PSS_IMUX_B10_14->PSS1_IMUX_B10_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_14" }, "PSS1.PSS_IMUX_B10_15->PSS1_IMUX_B10_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_15" }, "PSS1.PSS_IMUX_B10_16->PSS1_IMUX_B10_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_16" }, "PSS1.PSS_IMUX_B10_17->PSS1_IMUX_B10_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_17" }, "PSS1.PSS_IMUX_B10_18->PSS1_IMUX_B10_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_18" }, "PSS1.PSS_IMUX_B10_19->PSS1_IMUX_B10_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_19" }, "PSS1.PSS_IMUX_B10_2->PSS1_IMUX_B10_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_2" }, "PSS1.PSS_IMUX_B10_3->PSS1_IMUX_B10_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_3" }, "PSS1.PSS_IMUX_B10_4->PSS1_IMUX_B10_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_4" }, "PSS1.PSS_IMUX_B10_5->PSS1_IMUX_B10_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_5" }, "PSS1.PSS_IMUX_B10_6->PSS1_IMUX_B10_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_6" }, "PSS1.PSS_IMUX_B10_7->PSS1_IMUX_B10_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_7" }, "PSS1.PSS_IMUX_B10_8->PSS1_IMUX_B10_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_8" }, "PSS1.PSS_IMUX_B10_9->PSS1_IMUX_B10_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_9" }, "PSS1.PSS_IMUX_B11_0->PSS1_IMUX_B11_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_0" }, "PSS1.PSS_IMUX_B11_1->PSS1_IMUX_B11_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_1" }, "PSS1.PSS_IMUX_B11_10->PSS1_IMUX_B11_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_10" }, "PSS1.PSS_IMUX_B11_11->PSS1_IMUX_B11_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_11" }, "PSS1.PSS_IMUX_B11_12->PSS1_IMUX_B11_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_12" }, "PSS1.PSS_IMUX_B11_13->PSS1_IMUX_B11_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_13" }, "PSS1.PSS_IMUX_B11_14->PSS1_IMUX_B11_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_14" }, "PSS1.PSS_IMUX_B11_15->PSS1_IMUX_B11_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_15" }, "PSS1.PSS_IMUX_B11_16->PSS1_IMUX_B11_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_16" }, "PSS1.PSS_IMUX_B11_17->PSS1_IMUX_B11_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_17" }, "PSS1.PSS_IMUX_B11_18->PSS1_IMUX_B11_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_18" }, "PSS1.PSS_IMUX_B11_19->PSS1_IMUX_B11_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_19" }, "PSS1.PSS_IMUX_B11_2->PSS1_IMUX_B11_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_2" }, "PSS1.PSS_IMUX_B11_3->PSS1_IMUX_B11_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_3" }, "PSS1.PSS_IMUX_B11_4->PSS1_IMUX_B11_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_4" }, "PSS1.PSS_IMUX_B11_5->PSS1_IMUX_B11_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_5" }, "PSS1.PSS_IMUX_B11_6->PSS1_IMUX_B11_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_6" }, "PSS1.PSS_IMUX_B11_7->PSS1_IMUX_B11_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_7" }, "PSS1.PSS_IMUX_B11_8->PSS1_IMUX_B11_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_8" }, "PSS1.PSS_IMUX_B11_9->PSS1_IMUX_B11_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_9" }, "PSS1.PSS_IMUX_B12_0->PSS1_IMUX_B12_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_0" }, "PSS1.PSS_IMUX_B12_1->PSS1_IMUX_B12_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_1" }, "PSS1.PSS_IMUX_B12_10->PSS1_IMUX_B12_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_10" }, "PSS1.PSS_IMUX_B12_11->PSS1_IMUX_B12_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_11" }, "PSS1.PSS_IMUX_B12_12->PSS1_IMUX_B12_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_12" }, "PSS1.PSS_IMUX_B12_13->PSS1_IMUX_B12_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_13" }, "PSS1.PSS_IMUX_B12_14->PSS1_IMUX_B12_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_14" }, "PSS1.PSS_IMUX_B12_15->PSS1_IMUX_B12_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_15" }, "PSS1.PSS_IMUX_B12_16->PSS1_IMUX_B12_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_16" }, "PSS1.PSS_IMUX_B12_17->PSS1_IMUX_B12_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_17" }, "PSS1.PSS_IMUX_B12_18->PSS1_IMUX_B12_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_18" }, "PSS1.PSS_IMUX_B12_19->PSS1_IMUX_B12_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_19" }, "PSS1.PSS_IMUX_B12_2->PSS1_IMUX_B12_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_2" }, "PSS1.PSS_IMUX_B12_3->PSS1_IMUX_B12_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_3" }, "PSS1.PSS_IMUX_B12_4->PSS1_IMUX_B12_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_4" }, "PSS1.PSS_IMUX_B12_5->PSS1_IMUX_B12_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_5" }, "PSS1.PSS_IMUX_B12_6->PSS1_IMUX_B12_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_6" }, "PSS1.PSS_IMUX_B12_7->PSS1_IMUX_B12_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_7" }, "PSS1.PSS_IMUX_B12_8->PSS1_IMUX_B12_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_8" }, "PSS1.PSS_IMUX_B12_9->PSS1_IMUX_B12_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_9" }, "PSS1.PSS_IMUX_B13_0->PSS1_IMUX_B13_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_0" }, "PSS1.PSS_IMUX_B13_1->PSS1_IMUX_B13_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_1" }, "PSS1.PSS_IMUX_B13_10->PSS1_IMUX_B13_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_10" }, "PSS1.PSS_IMUX_B13_11->PSS1_IMUX_B13_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_11" }, "PSS1.PSS_IMUX_B13_12->PSS1_IMUX_B13_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_12" }, "PSS1.PSS_IMUX_B13_13->PSS1_IMUX_B13_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_13" }, "PSS1.PSS_IMUX_B13_14->PSS1_IMUX_B13_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_14" }, "PSS1.PSS_IMUX_B13_15->PSS1_IMUX_B13_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_15" }, "PSS1.PSS_IMUX_B13_16->PSS1_IMUX_B13_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_16" }, "PSS1.PSS_IMUX_B13_17->PSS1_IMUX_B13_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_17" }, "PSS1.PSS_IMUX_B13_18->PSS1_IMUX_B13_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_18" }, "PSS1.PSS_IMUX_B13_19->PSS1_IMUX_B13_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_19" }, "PSS1.PSS_IMUX_B13_2->PSS1_IMUX_B13_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_2" }, "PSS1.PSS_IMUX_B13_3->PSS1_IMUX_B13_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_3" }, "PSS1.PSS_IMUX_B13_4->PSS1_IMUX_B13_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_4" }, "PSS1.PSS_IMUX_B13_5->PSS1_IMUX_B13_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_5" }, "PSS1.PSS_IMUX_B13_6->PSS1_IMUX_B13_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_6" }, "PSS1.PSS_IMUX_B13_7->PSS1_IMUX_B13_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_7" }, "PSS1.PSS_IMUX_B13_8->PSS1_IMUX_B13_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_8" }, "PSS1.PSS_IMUX_B13_9->PSS1_IMUX_B13_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_9" }, "PSS1.PSS_IMUX_B14_0->PSS1_IMUX_B14_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_0" }, "PSS1.PSS_IMUX_B14_1->PSS1_IMUX_B14_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_1" }, "PSS1.PSS_IMUX_B14_10->PSS1_IMUX_B14_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_10" }, "PSS1.PSS_IMUX_B14_11->PSS1_IMUX_B14_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_11" }, "PSS1.PSS_IMUX_B14_12->PSS1_IMUX_B14_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_12" }, "PSS1.PSS_IMUX_B14_13->PSS1_IMUX_B14_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_13" }, "PSS1.PSS_IMUX_B14_14->PSS1_IMUX_B14_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_14" }, "PSS1.PSS_IMUX_B14_15->PSS1_IMUX_B14_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_15" }, "PSS1.PSS_IMUX_B14_16->PSS1_IMUX_B14_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_16" }, "PSS1.PSS_IMUX_B14_17->PSS1_IMUX_B14_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_17" }, "PSS1.PSS_IMUX_B14_18->PSS1_IMUX_B14_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_18" }, "PSS1.PSS_IMUX_B14_19->PSS1_IMUX_B14_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_19" }, "PSS1.PSS_IMUX_B14_2->PSS1_IMUX_B14_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_2" }, "PSS1.PSS_IMUX_B14_3->PSS1_IMUX_B14_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_3" }, "PSS1.PSS_IMUX_B14_4->PSS1_IMUX_B14_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_4" }, "PSS1.PSS_IMUX_B14_5->PSS1_IMUX_B14_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_5" }, "PSS1.PSS_IMUX_B14_6->PSS1_IMUX_B14_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_6" }, "PSS1.PSS_IMUX_B14_7->PSS1_IMUX_B14_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_7" }, "PSS1.PSS_IMUX_B14_8->PSS1_IMUX_B14_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_8" }, "PSS1.PSS_IMUX_B14_9->PSS1_IMUX_B14_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_9" }, "PSS1.PSS_IMUX_B15_0->PSS1_IMUX_B15_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_0" }, "PSS1.PSS_IMUX_B15_1->PSS1_IMUX_B15_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_1" }, "PSS1.PSS_IMUX_B15_10->PSS1_IMUX_B15_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_10" }, "PSS1.PSS_IMUX_B15_11->PSS1_IMUX_B15_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_11" }, "PSS1.PSS_IMUX_B15_12->PSS1_IMUX_B15_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_12" }, "PSS1.PSS_IMUX_B15_13->PSS1_IMUX_B15_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_13" }, "PSS1.PSS_IMUX_B15_14->PSS1_IMUX_B15_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_14" }, "PSS1.PSS_IMUX_B15_15->PSS1_IMUX_B15_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_15" }, "PSS1.PSS_IMUX_B15_16->PSS1_IMUX_B15_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_16" }, "PSS1.PSS_IMUX_B15_17->PSS1_IMUX_B15_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_17" }, "PSS1.PSS_IMUX_B15_18->PSS1_IMUX_B15_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_18" }, "PSS1.PSS_IMUX_B15_19->PSS1_IMUX_B15_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_19" }, "PSS1.PSS_IMUX_B15_2->PSS1_IMUX_B15_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_2" }, "PSS1.PSS_IMUX_B15_3->PSS1_IMUX_B15_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_3" }, "PSS1.PSS_IMUX_B15_4->PSS1_IMUX_B15_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_4" }, "PSS1.PSS_IMUX_B15_5->PSS1_IMUX_B15_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_5" }, "PSS1.PSS_IMUX_B15_6->PSS1_IMUX_B15_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_6" }, "PSS1.PSS_IMUX_B15_7->PSS1_IMUX_B15_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_7" }, "PSS1.PSS_IMUX_B15_8->PSS1_IMUX_B15_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_8" }, "PSS1.PSS_IMUX_B15_9->PSS1_IMUX_B15_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_9" }, "PSS1.PSS_IMUX_B16_0->PSS1_IMUX_B16_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_0" }, "PSS1.PSS_IMUX_B16_1->PSS1_IMUX_B16_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_1" }, "PSS1.PSS_IMUX_B16_10->PSS1_IMUX_B16_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_10" }, "PSS1.PSS_IMUX_B16_11->PSS1_IMUX_B16_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_11" }, "PSS1.PSS_IMUX_B16_12->PSS1_IMUX_B16_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_12" }, "PSS1.PSS_IMUX_B16_13->PSS1_IMUX_B16_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_13" }, "PSS1.PSS_IMUX_B16_14->PSS1_IMUX_B16_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_14" }, "PSS1.PSS_IMUX_B16_15->PSS1_IMUX_B16_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_15" }, "PSS1.PSS_IMUX_B16_16->PSS1_IMUX_B16_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_16" }, "PSS1.PSS_IMUX_B16_17->PSS1_IMUX_B16_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_17" }, "PSS1.PSS_IMUX_B16_18->PSS1_IMUX_B16_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_18" }, "PSS1.PSS_IMUX_B16_19->PSS1_IMUX_B16_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_19" }, "PSS1.PSS_IMUX_B16_2->PSS1_IMUX_B16_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_2" }, "PSS1.PSS_IMUX_B16_3->PSS1_IMUX_B16_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_3" }, "PSS1.PSS_IMUX_B16_4->PSS1_IMUX_B16_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_4" }, "PSS1.PSS_IMUX_B16_5->PSS1_IMUX_B16_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_5" }, "PSS1.PSS_IMUX_B16_6->PSS1_IMUX_B16_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_6" }, "PSS1.PSS_IMUX_B16_7->PSS1_IMUX_B16_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_7" }, "PSS1.PSS_IMUX_B16_8->PSS1_IMUX_B16_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_8" }, "PSS1.PSS_IMUX_B16_9->PSS1_IMUX_B16_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_9" }, "PSS1.PSS_IMUX_B17_0->PSS1_IMUX_B17_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_0" }, "PSS1.PSS_IMUX_B17_1->PSS1_IMUX_B17_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_1" }, "PSS1.PSS_IMUX_B17_10->PSS1_IMUX_B17_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_10" }, "PSS1.PSS_IMUX_B17_11->PSS1_IMUX_B17_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_11" }, "PSS1.PSS_IMUX_B17_12->PSS1_IMUX_B17_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_12" }, "PSS1.PSS_IMUX_B17_13->PSS1_IMUX_B17_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_13" }, "PSS1.PSS_IMUX_B17_14->PSS1_IMUX_B17_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_14" }, "PSS1.PSS_IMUX_B17_15->PSS1_IMUX_B17_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_15" }, "PSS1.PSS_IMUX_B17_16->PSS1_IMUX_B17_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_16" }, "PSS1.PSS_IMUX_B17_17->PSS1_IMUX_B17_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_17" }, "PSS1.PSS_IMUX_B17_18->PSS1_IMUX_B17_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_18" }, "PSS1.PSS_IMUX_B17_19->PSS1_IMUX_B17_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_19" }, "PSS1.PSS_IMUX_B17_2->PSS1_IMUX_B17_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_2" }, "PSS1.PSS_IMUX_B17_3->PSS1_IMUX_B17_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_3" }, "PSS1.PSS_IMUX_B17_4->PSS1_IMUX_B17_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_4" }, "PSS1.PSS_IMUX_B17_5->PSS1_IMUX_B17_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_5" }, "PSS1.PSS_IMUX_B17_6->PSS1_IMUX_B17_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_6" }, "PSS1.PSS_IMUX_B17_7->PSS1_IMUX_B17_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_7" }, "PSS1.PSS_IMUX_B17_8->PSS1_IMUX_B17_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_8" }, "PSS1.PSS_IMUX_B17_9->PSS1_IMUX_B17_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_9" }, "PSS1.PSS_IMUX_B18_0->PSS1_IMUX_B18_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_0" }, "PSS1.PSS_IMUX_B18_1->PSS1_IMUX_B18_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_1" }, "PSS1.PSS_IMUX_B18_10->PSS1_IMUX_B18_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_10" }, "PSS1.PSS_IMUX_B18_11->PSS1_IMUX_B18_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_11" }, "PSS1.PSS_IMUX_B18_12->PSS1_IMUX_B18_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_12" }, "PSS1.PSS_IMUX_B18_13->PSS1_IMUX_B18_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_13" }, "PSS1.PSS_IMUX_B18_14->PSS1_IMUX_B18_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_14" }, "PSS1.PSS_IMUX_B18_15->PSS1_IMUX_B18_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_15" }, "PSS1.PSS_IMUX_B18_16->PSS1_IMUX_B18_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_16" }, "PSS1.PSS_IMUX_B18_17->PSS1_IMUX_B18_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_17" }, "PSS1.PSS_IMUX_B18_18->PSS1_IMUX_B18_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_18" }, "PSS1.PSS_IMUX_B18_19->PSS1_IMUX_B18_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_19" }, "PSS1.PSS_IMUX_B18_2->PSS1_IMUX_B18_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_2" }, "PSS1.PSS_IMUX_B18_3->PSS1_IMUX_B18_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_3" }, "PSS1.PSS_IMUX_B18_4->PSS1_IMUX_B18_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_4" }, "PSS1.PSS_IMUX_B18_5->PSS1_IMUX_B18_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_5" }, "PSS1.PSS_IMUX_B18_6->PSS1_IMUX_B18_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_6" }, "PSS1.PSS_IMUX_B18_7->PSS1_IMUX_B18_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_7" }, "PSS1.PSS_IMUX_B18_8->PSS1_IMUX_B18_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_8" }, "PSS1.PSS_IMUX_B18_9->PSS1_IMUX_B18_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_9" }, "PSS1.PSS_IMUX_B19_0->PSS1_IMUX_B19_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_0" }, "PSS1.PSS_IMUX_B19_1->PSS1_IMUX_B19_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_1" }, "PSS1.PSS_IMUX_B19_10->PSS1_IMUX_B19_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_10" }, "PSS1.PSS_IMUX_B19_11->PSS1_IMUX_B19_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_11" }, "PSS1.PSS_IMUX_B19_12->PSS1_IMUX_B19_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_12" }, "PSS1.PSS_IMUX_B19_13->PSS1_IMUX_B19_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_13" }, "PSS1.PSS_IMUX_B19_14->PSS1_IMUX_B19_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_14" }, "PSS1.PSS_IMUX_B19_15->PSS1_IMUX_B19_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_15" }, "PSS1.PSS_IMUX_B19_16->PSS1_IMUX_B19_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_16" }, "PSS1.PSS_IMUX_B19_17->PSS1_IMUX_B19_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_17" }, "PSS1.PSS_IMUX_B19_18->PSS1_IMUX_B19_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_18" }, "PSS1.PSS_IMUX_B19_19->PSS1_IMUX_B19_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_19" }, "PSS1.PSS_IMUX_B19_2->PSS1_IMUX_B19_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_2" }, "PSS1.PSS_IMUX_B19_3->PSS1_IMUX_B19_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_3" }, "PSS1.PSS_IMUX_B19_4->PSS1_IMUX_B19_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_4" }, "PSS1.PSS_IMUX_B19_5->PSS1_IMUX_B19_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_5" }, "PSS1.PSS_IMUX_B19_6->PSS1_IMUX_B19_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_6" }, "PSS1.PSS_IMUX_B19_7->PSS1_IMUX_B19_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_7" }, "PSS1.PSS_IMUX_B19_8->PSS1_IMUX_B19_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_8" }, "PSS1.PSS_IMUX_B19_9->PSS1_IMUX_B19_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_9" }, "PSS1.PSS_IMUX_B1_0->PSS1_IMUX_B1_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_0" }, "PSS1.PSS_IMUX_B1_1->PSS1_IMUX_B1_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_1" }, "PSS1.PSS_IMUX_B1_10->PSS1_IMUX_B1_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_10" }, "PSS1.PSS_IMUX_B1_11->PSS1_IMUX_B1_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_11" }, "PSS1.PSS_IMUX_B1_12->PSS1_IMUX_B1_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_12" }, "PSS1.PSS_IMUX_B1_13->PSS1_IMUX_B1_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_13" }, "PSS1.PSS_IMUX_B1_14->PSS1_IMUX_B1_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_14" }, "PSS1.PSS_IMUX_B1_15->PSS1_IMUX_B1_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_15" }, "PSS1.PSS_IMUX_B1_16->PSS1_IMUX_B1_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_16" }, "PSS1.PSS_IMUX_B1_17->PSS1_IMUX_B1_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_17" }, "PSS1.PSS_IMUX_B1_18->PSS1_IMUX_B1_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_18" }, "PSS1.PSS_IMUX_B1_19->PSS1_IMUX_B1_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_19" }, "PSS1.PSS_IMUX_B1_2->PSS1_IMUX_B1_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_2" }, "PSS1.PSS_IMUX_B1_3->PSS1_IMUX_B1_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_3" }, "PSS1.PSS_IMUX_B1_4->PSS1_IMUX_B1_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_4" }, "PSS1.PSS_IMUX_B1_5->PSS1_IMUX_B1_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_5" }, "PSS1.PSS_IMUX_B1_6->PSS1_IMUX_B1_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_6" }, "PSS1.PSS_IMUX_B1_7->PSS1_IMUX_B1_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_7" }, "PSS1.PSS_IMUX_B1_8->PSS1_IMUX_B1_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_8" }, "PSS1.PSS_IMUX_B1_9->PSS1_IMUX_B1_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_9" }, "PSS1.PSS_IMUX_B20_0->PSS1_IMUX_B20_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_0" }, "PSS1.PSS_IMUX_B20_1->PSS1_IMUX_B20_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_1" }, "PSS1.PSS_IMUX_B20_10->PSS1_IMUX_B20_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_10" }, "PSS1.PSS_IMUX_B20_11->PSS1_IMUX_B20_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_11" }, "PSS1.PSS_IMUX_B20_12->PSS1_IMUX_B20_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_12" }, "PSS1.PSS_IMUX_B20_13->PSS1_IMUX_B20_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_13" }, "PSS1.PSS_IMUX_B20_14->PSS1_IMUX_B20_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_14" }, "PSS1.PSS_IMUX_B20_15->PSS1_IMUX_B20_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_15" }, "PSS1.PSS_IMUX_B20_16->PSS1_IMUX_B20_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_16" }, "PSS1.PSS_IMUX_B20_17->PSS1_IMUX_B20_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_17" }, "PSS1.PSS_IMUX_B20_18->PSS1_IMUX_B20_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_18" }, "PSS1.PSS_IMUX_B20_19->PSS1_IMUX_B20_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_19" }, "PSS1.PSS_IMUX_B20_2->PSS1_IMUX_B20_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_2" }, "PSS1.PSS_IMUX_B20_3->PSS1_IMUX_B20_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_3" }, "PSS1.PSS_IMUX_B20_4->PSS1_IMUX_B20_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_4" }, "PSS1.PSS_IMUX_B20_5->PSS1_IMUX_B20_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_5" }, "PSS1.PSS_IMUX_B20_6->PSS1_IMUX_B20_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_6" }, "PSS1.PSS_IMUX_B20_7->PSS1_IMUX_B20_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_7" }, "PSS1.PSS_IMUX_B20_8->PSS1_IMUX_B20_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_8" }, "PSS1.PSS_IMUX_B20_9->PSS1_IMUX_B20_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_9" }, "PSS1.PSS_IMUX_B21_0->PSS1_IMUX_B21_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_0" }, "PSS1.PSS_IMUX_B21_1->PSS1_IMUX_B21_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_1" }, "PSS1.PSS_IMUX_B21_10->PSS1_IMUX_B21_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_10" }, "PSS1.PSS_IMUX_B21_11->PSS1_IMUX_B21_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_11" }, "PSS1.PSS_IMUX_B21_12->PSS1_IMUX_B21_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_12" }, "PSS1.PSS_IMUX_B21_13->PSS1_IMUX_B21_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_13" }, "PSS1.PSS_IMUX_B21_14->PSS1_IMUX_B21_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_14" }, "PSS1.PSS_IMUX_B21_15->PSS1_IMUX_B21_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_15" }, "PSS1.PSS_IMUX_B21_16->PSS1_IMUX_B21_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_16" }, "PSS1.PSS_IMUX_B21_17->PSS1_IMUX_B21_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_17" }, "PSS1.PSS_IMUX_B21_18->PSS1_IMUX_B21_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_18" }, "PSS1.PSS_IMUX_B21_19->PSS1_IMUX_B21_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_19" }, "PSS1.PSS_IMUX_B21_2->PSS1_IMUX_B21_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_2" }, "PSS1.PSS_IMUX_B21_3->PSS1_IMUX_B21_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_3" }, "PSS1.PSS_IMUX_B21_4->PSS1_IMUX_B21_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_4" }, "PSS1.PSS_IMUX_B21_5->PSS1_IMUX_B21_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_5" }, "PSS1.PSS_IMUX_B21_6->PSS1_IMUX_B21_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_6" }, "PSS1.PSS_IMUX_B21_7->PSS1_IMUX_B21_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_7" }, "PSS1.PSS_IMUX_B21_8->PSS1_IMUX_B21_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_8" }, "PSS1.PSS_IMUX_B21_9->PSS1_IMUX_B21_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_9" }, "PSS1.PSS_IMUX_B22_0->PSS1_IMUX_B22_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_0" }, "PSS1.PSS_IMUX_B22_1->PSS1_IMUX_B22_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_1" }, "PSS1.PSS_IMUX_B22_10->PSS1_IMUX_B22_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_10" }, "PSS1.PSS_IMUX_B22_11->PSS1_IMUX_B22_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_11" }, "PSS1.PSS_IMUX_B22_12->PSS1_IMUX_B22_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_12" }, "PSS1.PSS_IMUX_B22_13->PSS1_IMUX_B22_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_13" }, "PSS1.PSS_IMUX_B22_14->PSS1_IMUX_B22_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_14" }, "PSS1.PSS_IMUX_B22_15->PSS1_IMUX_B22_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_15" }, "PSS1.PSS_IMUX_B22_16->PSS1_IMUX_B22_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_16" }, "PSS1.PSS_IMUX_B22_17->PSS1_IMUX_B22_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_17" }, "PSS1.PSS_IMUX_B22_18->PSS1_IMUX_B22_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_18" }, "PSS1.PSS_IMUX_B22_19->PSS1_IMUX_B22_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_19" }, "PSS1.PSS_IMUX_B22_2->PSS1_IMUX_B22_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_2" }, "PSS1.PSS_IMUX_B22_3->PSS1_IMUX_B22_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_3" }, "PSS1.PSS_IMUX_B22_4->PSS1_IMUX_B22_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_4" }, "PSS1.PSS_IMUX_B22_5->PSS1_IMUX_B22_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_5" }, "PSS1.PSS_IMUX_B22_6->PSS1_IMUX_B22_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_6" }, "PSS1.PSS_IMUX_B22_7->PSS1_IMUX_B22_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_7" }, "PSS1.PSS_IMUX_B22_8->PSS1_IMUX_B22_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_8" }, "PSS1.PSS_IMUX_B22_9->PSS1_IMUX_B22_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_9" }, "PSS1.PSS_IMUX_B23_0->PSS1_IMUX_B23_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_0" }, "PSS1.PSS_IMUX_B23_1->PSS1_IMUX_B23_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_1" }, "PSS1.PSS_IMUX_B23_10->PSS1_IMUX_B23_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_10" }, "PSS1.PSS_IMUX_B23_11->PSS1_IMUX_B23_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_11" }, "PSS1.PSS_IMUX_B23_12->PSS1_IMUX_B23_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_12" }, "PSS1.PSS_IMUX_B23_13->PSS1_IMUX_B23_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_13" }, "PSS1.PSS_IMUX_B23_14->PSS1_IMUX_B23_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_14" }, "PSS1.PSS_IMUX_B23_15->PSS1_IMUX_B23_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_15" }, "PSS1.PSS_IMUX_B23_16->PSS1_IMUX_B23_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_16" }, "PSS1.PSS_IMUX_B23_17->PSS1_IMUX_B23_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_17" }, "PSS1.PSS_IMUX_B23_18->PSS1_IMUX_B23_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_18" }, "PSS1.PSS_IMUX_B23_19->PSS1_IMUX_B23_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_19" }, "PSS1.PSS_IMUX_B23_2->PSS1_IMUX_B23_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_2" }, "PSS1.PSS_IMUX_B23_3->PSS1_IMUX_B23_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_3" }, "PSS1.PSS_IMUX_B23_4->PSS1_IMUX_B23_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_4" }, "PSS1.PSS_IMUX_B23_5->PSS1_IMUX_B23_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_5" }, "PSS1.PSS_IMUX_B23_6->PSS1_IMUX_B23_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_6" }, "PSS1.PSS_IMUX_B23_7->PSS1_IMUX_B23_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_7" }, "PSS1.PSS_IMUX_B23_8->PSS1_IMUX_B23_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_8" }, "PSS1.PSS_IMUX_B23_9->PSS1_IMUX_B23_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_9" }, "PSS1.PSS_IMUX_B24_0->PSS1_IMUX_B24_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_0" }, "PSS1.PSS_IMUX_B24_1->PSS1_IMUX_B24_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_1" }, "PSS1.PSS_IMUX_B24_10->PSS1_IMUX_B24_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_10" }, "PSS1.PSS_IMUX_B24_11->PSS1_IMUX_B24_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_11" }, "PSS1.PSS_IMUX_B24_12->PSS1_IMUX_B24_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_12" }, "PSS1.PSS_IMUX_B24_13->PSS1_IMUX_B24_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_13" }, "PSS1.PSS_IMUX_B24_14->PSS1_IMUX_B24_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_14" }, "PSS1.PSS_IMUX_B24_15->PSS1_IMUX_B24_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_15" }, "PSS1.PSS_IMUX_B24_16->PSS1_IMUX_B24_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_16" }, "PSS1.PSS_IMUX_B24_17->PSS1_IMUX_B24_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_17" }, "PSS1.PSS_IMUX_B24_18->PSS1_IMUX_B24_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_18" }, "PSS1.PSS_IMUX_B24_19->PSS1_IMUX_B24_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_19" }, "PSS1.PSS_IMUX_B24_2->PSS1_IMUX_B24_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_2" }, "PSS1.PSS_IMUX_B24_3->PSS1_IMUX_B24_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_3" }, "PSS1.PSS_IMUX_B24_4->PSS1_IMUX_B24_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_4" }, "PSS1.PSS_IMUX_B24_5->PSS1_IMUX_B24_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_5" }, "PSS1.PSS_IMUX_B24_6->PSS1_IMUX_B24_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_6" }, "PSS1.PSS_IMUX_B24_7->PSS1_IMUX_B24_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_7" }, "PSS1.PSS_IMUX_B24_8->PSS1_IMUX_B24_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_8" }, "PSS1.PSS_IMUX_B24_9->PSS1_IMUX_B24_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_9" }, "PSS1.PSS_IMUX_B25_0->PSS1_IMUX_B25_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_0" }, "PSS1.PSS_IMUX_B25_1->PSS1_IMUX_B25_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_1" }, "PSS1.PSS_IMUX_B25_10->PSS1_IMUX_B25_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_10" }, "PSS1.PSS_IMUX_B25_11->PSS1_IMUX_B25_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_11" }, "PSS1.PSS_IMUX_B25_12->PSS1_IMUX_B25_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_12" }, "PSS1.PSS_IMUX_B25_13->PSS1_IMUX_B25_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_13" }, "PSS1.PSS_IMUX_B25_14->PSS1_IMUX_B25_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_14" }, "PSS1.PSS_IMUX_B25_15->PSS1_IMUX_B25_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_15" }, "PSS1.PSS_IMUX_B25_16->PSS1_IMUX_B25_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_16" }, "PSS1.PSS_IMUX_B25_17->PSS1_IMUX_B25_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_17" }, "PSS1.PSS_IMUX_B25_18->PSS1_IMUX_B25_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_18" }, "PSS1.PSS_IMUX_B25_19->PSS1_IMUX_B25_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_19" }, "PSS1.PSS_IMUX_B25_2->PSS1_IMUX_B25_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_2" }, "PSS1.PSS_IMUX_B25_3->PSS1_IMUX_B25_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_3" }, "PSS1.PSS_IMUX_B25_4->PSS1_IMUX_B25_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_4" }, "PSS1.PSS_IMUX_B25_5->PSS1_IMUX_B25_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_5" }, "PSS1.PSS_IMUX_B25_6->PSS1_IMUX_B25_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_6" }, "PSS1.PSS_IMUX_B25_7->PSS1_IMUX_B25_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_7" }, "PSS1.PSS_IMUX_B25_8->PSS1_IMUX_B25_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_8" }, "PSS1.PSS_IMUX_B25_9->PSS1_IMUX_B25_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_9" }, "PSS1.PSS_IMUX_B26_0->PSS1_IMUX_B26_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_0" }, "PSS1.PSS_IMUX_B26_1->PSS1_IMUX_B26_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_1" }, "PSS1.PSS_IMUX_B26_10->PSS1_IMUX_B26_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_10" }, "PSS1.PSS_IMUX_B26_11->PSS1_IMUX_B26_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_11" }, "PSS1.PSS_IMUX_B26_12->PSS1_IMUX_B26_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_12" }, "PSS1.PSS_IMUX_B26_13->PSS1_IMUX_B26_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_13" }, "PSS1.PSS_IMUX_B26_14->PSS1_IMUX_B26_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_14" }, "PSS1.PSS_IMUX_B26_15->PSS1_IMUX_B26_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_15" }, "PSS1.PSS_IMUX_B26_16->PSS1_IMUX_B26_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_16" }, "PSS1.PSS_IMUX_B26_17->PSS1_IMUX_B26_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_17" }, "PSS1.PSS_IMUX_B26_18->PSS1_IMUX_B26_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_18" }, "PSS1.PSS_IMUX_B26_19->PSS1_IMUX_B26_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_19" }, "PSS1.PSS_IMUX_B26_2->PSS1_IMUX_B26_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_2" }, "PSS1.PSS_IMUX_B26_3->PSS1_IMUX_B26_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_3" }, "PSS1.PSS_IMUX_B26_4->PSS1_IMUX_B26_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_4" }, "PSS1.PSS_IMUX_B26_5->PSS1_IMUX_B26_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_5" }, "PSS1.PSS_IMUX_B26_6->PSS1_IMUX_B26_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_6" }, "PSS1.PSS_IMUX_B26_7->PSS1_IMUX_B26_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_7" }, "PSS1.PSS_IMUX_B26_8->PSS1_IMUX_B26_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_8" }, "PSS1.PSS_IMUX_B26_9->PSS1_IMUX_B26_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_9" }, "PSS1.PSS_IMUX_B27_0->PSS1_IMUX_B27_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_0" }, "PSS1.PSS_IMUX_B27_1->PSS1_IMUX_B27_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_1" }, "PSS1.PSS_IMUX_B27_10->PSS1_IMUX_B27_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_10" }, "PSS1.PSS_IMUX_B27_11->PSS1_IMUX_B27_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_11" }, "PSS1.PSS_IMUX_B27_12->PSS1_IMUX_B27_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_12" }, "PSS1.PSS_IMUX_B27_13->PSS1_IMUX_B27_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_13" }, "PSS1.PSS_IMUX_B27_14->PSS1_IMUX_B27_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_14" }, "PSS1.PSS_IMUX_B27_15->PSS1_IMUX_B27_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_15" }, "PSS1.PSS_IMUX_B27_16->PSS1_IMUX_B27_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_16" }, "PSS1.PSS_IMUX_B27_17->PSS1_IMUX_B27_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_17" }, "PSS1.PSS_IMUX_B27_18->PSS1_IMUX_B27_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_18" }, "PSS1.PSS_IMUX_B27_19->PSS1_IMUX_B27_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_19" }, "PSS1.PSS_IMUX_B27_2->PSS1_IMUX_B27_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_2" }, "PSS1.PSS_IMUX_B27_3->PSS1_IMUX_B27_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_3" }, "PSS1.PSS_IMUX_B27_4->PSS1_IMUX_B27_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_4" }, "PSS1.PSS_IMUX_B27_5->PSS1_IMUX_B27_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_5" }, "PSS1.PSS_IMUX_B27_6->PSS1_IMUX_B27_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_6" }, "PSS1.PSS_IMUX_B27_7->PSS1_IMUX_B27_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_7" }, "PSS1.PSS_IMUX_B27_8->PSS1_IMUX_B27_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_8" }, "PSS1.PSS_IMUX_B27_9->PSS1_IMUX_B27_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_9" }, "PSS1.PSS_IMUX_B28_0->PSS1_IMUX_B28_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_0" }, "PSS1.PSS_IMUX_B28_1->PSS1_IMUX_B28_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_1" }, "PSS1.PSS_IMUX_B28_10->PSS1_IMUX_B28_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_10" }, "PSS1.PSS_IMUX_B28_11->PSS1_IMUX_B28_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_11" }, "PSS1.PSS_IMUX_B28_12->PSS1_IMUX_B28_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_12" }, "PSS1.PSS_IMUX_B28_13->PSS1_IMUX_B28_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_13" }, "PSS1.PSS_IMUX_B28_14->PSS1_IMUX_B28_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_14" }, "PSS1.PSS_IMUX_B28_15->PSS1_IMUX_B28_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_15" }, "PSS1.PSS_IMUX_B28_16->PSS1_IMUX_B28_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_16" }, "PSS1.PSS_IMUX_B28_17->PSS1_IMUX_B28_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_17" }, "PSS1.PSS_IMUX_B28_18->PSS1_IMUX_B28_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_18" }, "PSS1.PSS_IMUX_B28_19->PSS1_IMUX_B28_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_19" }, "PSS1.PSS_IMUX_B28_2->PSS1_IMUX_B28_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_2" }, "PSS1.PSS_IMUX_B28_3->PSS1_IMUX_B28_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_3" }, "PSS1.PSS_IMUX_B28_4->PSS1_IMUX_B28_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_4" }, "PSS1.PSS_IMUX_B28_5->PSS1_IMUX_B28_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_5" }, "PSS1.PSS_IMUX_B28_6->PSS1_IMUX_B28_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_6" }, "PSS1.PSS_IMUX_B28_7->PSS1_IMUX_B28_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_7" }, "PSS1.PSS_IMUX_B28_8->PSS1_IMUX_B28_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_8" }, "PSS1.PSS_IMUX_B28_9->PSS1_IMUX_B28_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_9" }, "PSS1.PSS_IMUX_B29_0->PSS1_IMUX_B29_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_0" }, "PSS1.PSS_IMUX_B29_1->PSS1_IMUX_B29_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_1" }, "PSS1.PSS_IMUX_B29_10->PSS1_IMUX_B29_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_10" }, "PSS1.PSS_IMUX_B29_11->PSS1_IMUX_B29_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_11" }, "PSS1.PSS_IMUX_B29_12->PSS1_IMUX_B29_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_12" }, "PSS1.PSS_IMUX_B29_13->PSS1_IMUX_B29_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_13" }, "PSS1.PSS_IMUX_B29_14->PSS1_IMUX_B29_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_14" }, "PSS1.PSS_IMUX_B29_15->PSS1_IMUX_B29_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_15" }, "PSS1.PSS_IMUX_B29_16->PSS1_IMUX_B29_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_16" }, "PSS1.PSS_IMUX_B29_17->PSS1_IMUX_B29_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_17" }, "PSS1.PSS_IMUX_B29_18->PSS1_IMUX_B29_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_18" }, "PSS1.PSS_IMUX_B29_19->PSS1_IMUX_B29_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_19" }, "PSS1.PSS_IMUX_B29_2->PSS1_IMUX_B29_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_2" }, "PSS1.PSS_IMUX_B29_3->PSS1_IMUX_B29_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_3" }, "PSS1.PSS_IMUX_B29_4->PSS1_IMUX_B29_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_4" }, "PSS1.PSS_IMUX_B29_5->PSS1_IMUX_B29_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_5" }, "PSS1.PSS_IMUX_B29_6->PSS1_IMUX_B29_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_6" }, "PSS1.PSS_IMUX_B29_7->PSS1_IMUX_B29_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_7" }, "PSS1.PSS_IMUX_B29_8->PSS1_IMUX_B29_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_8" }, "PSS1.PSS_IMUX_B29_9->PSS1_IMUX_B29_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_9" }, "PSS1.PSS_IMUX_B2_0->PSS1_IMUX_B2_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_0" }, "PSS1.PSS_IMUX_B2_1->PSS1_IMUX_B2_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_1" }, "PSS1.PSS_IMUX_B2_10->PSS1_IMUX_B2_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_10" }, "PSS1.PSS_IMUX_B2_11->PSS1_IMUX_B2_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_11" }, "PSS1.PSS_IMUX_B2_12->PSS1_IMUX_B2_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_12" }, "PSS1.PSS_IMUX_B2_13->PSS1_IMUX_B2_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_13" }, "PSS1.PSS_IMUX_B2_14->PSS1_IMUX_B2_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_14" }, "PSS1.PSS_IMUX_B2_15->PSS1_IMUX_B2_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_15" }, "PSS1.PSS_IMUX_B2_16->PSS1_IMUX_B2_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_16" }, "PSS1.PSS_IMUX_B2_17->PSS1_IMUX_B2_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_17" }, "PSS1.PSS_IMUX_B2_18->PSS1_IMUX_B2_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_18" }, "PSS1.PSS_IMUX_B2_19->PSS1_IMUX_B2_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_19" }, "PSS1.PSS_IMUX_B2_2->PSS1_IMUX_B2_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_2" }, "PSS1.PSS_IMUX_B2_3->PSS1_IMUX_B2_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_3" }, "PSS1.PSS_IMUX_B2_4->PSS1_IMUX_B2_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_4" }, "PSS1.PSS_IMUX_B2_5->PSS1_IMUX_B2_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_5" }, "PSS1.PSS_IMUX_B2_6->PSS1_IMUX_B2_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_6" }, "PSS1.PSS_IMUX_B2_7->PSS1_IMUX_B2_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_7" }, "PSS1.PSS_IMUX_B2_8->PSS1_IMUX_B2_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_8" }, "PSS1.PSS_IMUX_B2_9->PSS1_IMUX_B2_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_9" }, "PSS1.PSS_IMUX_B30_0->PSS1_IMUX_B30_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_0" }, "PSS1.PSS_IMUX_B30_1->PSS1_IMUX_B30_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_1" }, "PSS1.PSS_IMUX_B30_10->PSS1_IMUX_B30_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_10" }, "PSS1.PSS_IMUX_B30_11->PSS1_IMUX_B30_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_11" }, "PSS1.PSS_IMUX_B30_12->PSS1_IMUX_B30_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_12" }, "PSS1.PSS_IMUX_B30_13->PSS1_IMUX_B30_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_13" }, "PSS1.PSS_IMUX_B30_14->PSS1_IMUX_B30_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_14" }, "PSS1.PSS_IMUX_B30_15->PSS1_IMUX_B30_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_15" }, "PSS1.PSS_IMUX_B30_16->PSS1_IMUX_B30_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_16" }, "PSS1.PSS_IMUX_B30_17->PSS1_IMUX_B30_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_17" }, "PSS1.PSS_IMUX_B30_18->PSS1_IMUX_B30_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_18" }, "PSS1.PSS_IMUX_B30_19->PSS1_IMUX_B30_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_19" }, "PSS1.PSS_IMUX_B30_2->PSS1_IMUX_B30_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_2" }, "PSS1.PSS_IMUX_B30_3->PSS1_IMUX_B30_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_3" }, "PSS1.PSS_IMUX_B30_4->PSS1_IMUX_B30_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_4" }, "PSS1.PSS_IMUX_B30_5->PSS1_IMUX_B30_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_5" }, "PSS1.PSS_IMUX_B30_6->PSS1_IMUX_B30_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_6" }, "PSS1.PSS_IMUX_B30_7->PSS1_IMUX_B30_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_7" }, "PSS1.PSS_IMUX_B30_8->PSS1_IMUX_B30_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_8" }, "PSS1.PSS_IMUX_B30_9->PSS1_IMUX_B30_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_9" }, "PSS1.PSS_IMUX_B31_0->PSS1_IMUX_B31_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_0" }, "PSS1.PSS_IMUX_B31_1->PSS1_IMUX_B31_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_1" }, "PSS1.PSS_IMUX_B31_10->PSS1_IMUX_B31_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_10" }, "PSS1.PSS_IMUX_B31_11->PSS1_IMUX_B31_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_11" }, "PSS1.PSS_IMUX_B31_12->PSS1_IMUX_B31_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_12" }, "PSS1.PSS_IMUX_B31_13->PSS1_IMUX_B31_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_13" }, "PSS1.PSS_IMUX_B31_14->PSS1_IMUX_B31_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_14" }, "PSS1.PSS_IMUX_B31_15->PSS1_IMUX_B31_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_15" }, "PSS1.PSS_IMUX_B31_16->PSS1_IMUX_B31_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_16" }, "PSS1.PSS_IMUX_B31_17->PSS1_IMUX_B31_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_17" }, "PSS1.PSS_IMUX_B31_18->PSS1_IMUX_B31_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_18" }, "PSS1.PSS_IMUX_B31_19->PSS1_IMUX_B31_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_19" }, "PSS1.PSS_IMUX_B31_2->PSS1_IMUX_B31_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_2" }, "PSS1.PSS_IMUX_B31_3->PSS1_IMUX_B31_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_3" }, "PSS1.PSS_IMUX_B31_4->PSS1_IMUX_B31_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_4" }, "PSS1.PSS_IMUX_B31_5->PSS1_IMUX_B31_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_5" }, "PSS1.PSS_IMUX_B31_6->PSS1_IMUX_B31_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_6" }, "PSS1.PSS_IMUX_B31_7->PSS1_IMUX_B31_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_7" }, "PSS1.PSS_IMUX_B31_8->PSS1_IMUX_B31_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_8" }, "PSS1.PSS_IMUX_B31_9->PSS1_IMUX_B31_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_9" }, "PSS1.PSS_IMUX_B32_0->PSS1_IMUX_B32_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_0" }, "PSS1.PSS_IMUX_B32_1->PSS1_IMUX_B32_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_1" }, "PSS1.PSS_IMUX_B32_10->PSS1_IMUX_B32_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_10" }, "PSS1.PSS_IMUX_B32_11->PSS1_IMUX_B32_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_11" }, "PSS1.PSS_IMUX_B32_12->PSS1_IMUX_B32_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_12" }, "PSS1.PSS_IMUX_B32_13->PSS1_IMUX_B32_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_13" }, "PSS1.PSS_IMUX_B32_14->PSS1_IMUX_B32_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_14" }, "PSS1.PSS_IMUX_B32_15->PSS1_IMUX_B32_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_15" }, "PSS1.PSS_IMUX_B32_16->PSS1_IMUX_B32_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_16" }, "PSS1.PSS_IMUX_B32_17->PSS1_IMUX_B32_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_17" }, "PSS1.PSS_IMUX_B32_18->PSS1_IMUX_B32_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_18" }, "PSS1.PSS_IMUX_B32_19->PSS1_IMUX_B32_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_19" }, "PSS1.PSS_IMUX_B32_2->PSS1_IMUX_B32_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_2" }, "PSS1.PSS_IMUX_B32_3->PSS1_IMUX_B32_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_3" }, "PSS1.PSS_IMUX_B32_4->PSS1_IMUX_B32_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_4" }, "PSS1.PSS_IMUX_B32_5->PSS1_IMUX_B32_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_5" }, "PSS1.PSS_IMUX_B32_6->PSS1_IMUX_B32_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_6" }, "PSS1.PSS_IMUX_B32_7->PSS1_IMUX_B32_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_7" }, "PSS1.PSS_IMUX_B32_8->PSS1_IMUX_B32_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_8" }, "PSS1.PSS_IMUX_B32_9->PSS1_IMUX_B32_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_9" }, "PSS1.PSS_IMUX_B33_0->PSS1_IMUX_B33_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_0" }, "PSS1.PSS_IMUX_B33_1->PSS1_IMUX_B33_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_1" }, "PSS1.PSS_IMUX_B33_10->PSS1_IMUX_B33_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_10" }, "PSS1.PSS_IMUX_B33_11->PSS1_IMUX_B33_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_11" }, "PSS1.PSS_IMUX_B33_12->PSS1_IMUX_B33_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_12" }, "PSS1.PSS_IMUX_B33_13->PSS1_IMUX_B33_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_13" }, "PSS1.PSS_IMUX_B33_14->PSS1_IMUX_B33_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_14" }, "PSS1.PSS_IMUX_B33_15->PSS1_IMUX_B33_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_15" }, "PSS1.PSS_IMUX_B33_16->PSS1_IMUX_B33_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_16" }, "PSS1.PSS_IMUX_B33_17->PSS1_IMUX_B33_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_17" }, "PSS1.PSS_IMUX_B33_18->PSS1_IMUX_B33_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_18" }, "PSS1.PSS_IMUX_B33_19->PSS1_IMUX_B33_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_19" }, "PSS1.PSS_IMUX_B33_2->PSS1_IMUX_B33_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_2" }, "PSS1.PSS_IMUX_B33_3->PSS1_IMUX_B33_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_3" }, "PSS1.PSS_IMUX_B33_4->PSS1_IMUX_B33_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_4" }, "PSS1.PSS_IMUX_B33_5->PSS1_IMUX_B33_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_5" }, "PSS1.PSS_IMUX_B33_6->PSS1_IMUX_B33_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_6" }, "PSS1.PSS_IMUX_B33_7->PSS1_IMUX_B33_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_7" }, "PSS1.PSS_IMUX_B33_8->PSS1_IMUX_B33_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_8" }, "PSS1.PSS_IMUX_B33_9->PSS1_IMUX_B33_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_9" }, "PSS1.PSS_IMUX_B34_0->PSS1_IMUX_B34_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_0" }, "PSS1.PSS_IMUX_B34_1->PSS1_IMUX_B34_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_1" }, "PSS1.PSS_IMUX_B34_10->PSS1_IMUX_B34_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_10" }, "PSS1.PSS_IMUX_B34_11->PSS1_IMUX_B34_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_11" }, "PSS1.PSS_IMUX_B34_12->PSS1_IMUX_B34_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_12" }, "PSS1.PSS_IMUX_B34_13->PSS1_IMUX_B34_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_13" }, "PSS1.PSS_IMUX_B34_14->PSS1_IMUX_B34_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_14" }, "PSS1.PSS_IMUX_B34_15->PSS1_IMUX_B34_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_15" }, "PSS1.PSS_IMUX_B34_16->PSS1_IMUX_B34_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_16" }, "PSS1.PSS_IMUX_B34_17->PSS1_IMUX_B34_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_17" }, "PSS1.PSS_IMUX_B34_18->PSS1_IMUX_B34_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_18" }, "PSS1.PSS_IMUX_B34_19->PSS1_IMUX_B34_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_19" }, "PSS1.PSS_IMUX_B34_2->PSS1_IMUX_B34_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_2" }, "PSS1.PSS_IMUX_B34_3->PSS1_IMUX_B34_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_3" }, "PSS1.PSS_IMUX_B34_4->PSS1_IMUX_B34_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_4" }, "PSS1.PSS_IMUX_B34_5->PSS1_IMUX_B34_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_5" }, "PSS1.PSS_IMUX_B34_6->PSS1_IMUX_B34_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_6" }, "PSS1.PSS_IMUX_B34_7->PSS1_IMUX_B34_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_7" }, "PSS1.PSS_IMUX_B34_8->PSS1_IMUX_B34_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_8" }, "PSS1.PSS_IMUX_B34_9->PSS1_IMUX_B34_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_9" }, "PSS1.PSS_IMUX_B35_0->PSS1_IMUX_B35_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_0" }, "PSS1.PSS_IMUX_B35_1->PSS1_IMUX_B35_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_1" }, "PSS1.PSS_IMUX_B35_10->PSS1_IMUX_B35_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_10" }, "PSS1.PSS_IMUX_B35_11->PSS1_IMUX_B35_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_11" }, "PSS1.PSS_IMUX_B35_12->PSS1_IMUX_B35_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_12" }, "PSS1.PSS_IMUX_B35_13->PSS1_IMUX_B35_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_13" }, "PSS1.PSS_IMUX_B35_14->PSS1_IMUX_B35_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_14" }, "PSS1.PSS_IMUX_B35_15->PSS1_IMUX_B35_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_15" }, "PSS1.PSS_IMUX_B35_16->PSS1_IMUX_B35_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_16" }, "PSS1.PSS_IMUX_B35_17->PSS1_IMUX_B35_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_17" }, "PSS1.PSS_IMUX_B35_18->PSS1_IMUX_B35_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_18" }, "PSS1.PSS_IMUX_B35_19->PSS1_IMUX_B35_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_19" }, "PSS1.PSS_IMUX_B35_2->PSS1_IMUX_B35_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_2" }, "PSS1.PSS_IMUX_B35_3->PSS1_IMUX_B35_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_3" }, "PSS1.PSS_IMUX_B35_4->PSS1_IMUX_B35_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_4" }, "PSS1.PSS_IMUX_B35_5->PSS1_IMUX_B35_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_5" }, "PSS1.PSS_IMUX_B35_6->PSS1_IMUX_B35_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_6" }, "PSS1.PSS_IMUX_B35_7->PSS1_IMUX_B35_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_7" }, "PSS1.PSS_IMUX_B35_8->PSS1_IMUX_B35_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_8" }, "PSS1.PSS_IMUX_B35_9->PSS1_IMUX_B35_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_9" }, "PSS1.PSS_IMUX_B36_0->PSS1_IMUX_B36_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_0" }, "PSS1.PSS_IMUX_B36_1->PSS1_IMUX_B36_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_1" }, "PSS1.PSS_IMUX_B36_10->PSS1_IMUX_B36_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_10" }, "PSS1.PSS_IMUX_B36_11->PSS1_IMUX_B36_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_11" }, "PSS1.PSS_IMUX_B36_12->PSS1_IMUX_B36_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_12" }, "PSS1.PSS_IMUX_B36_13->PSS1_IMUX_B36_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_13" }, "PSS1.PSS_IMUX_B36_14->PSS1_IMUX_B36_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_14" }, "PSS1.PSS_IMUX_B36_15->PSS1_IMUX_B36_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_15" }, "PSS1.PSS_IMUX_B36_16->PSS1_IMUX_B36_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_16" }, "PSS1.PSS_IMUX_B36_17->PSS1_IMUX_B36_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_17" }, "PSS1.PSS_IMUX_B36_18->PSS1_IMUX_B36_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_18" }, "PSS1.PSS_IMUX_B36_19->PSS1_IMUX_B36_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_19" }, "PSS1.PSS_IMUX_B36_2->PSS1_IMUX_B36_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_2" }, "PSS1.PSS_IMUX_B36_3->PSS1_IMUX_B36_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_3" }, "PSS1.PSS_IMUX_B36_4->PSS1_IMUX_B36_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_4" }, "PSS1.PSS_IMUX_B36_5->PSS1_IMUX_B36_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_5" }, "PSS1.PSS_IMUX_B36_6->PSS1_IMUX_B36_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_6" }, "PSS1.PSS_IMUX_B36_7->PSS1_IMUX_B36_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_7" }, "PSS1.PSS_IMUX_B36_8->PSS1_IMUX_B36_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_8" }, "PSS1.PSS_IMUX_B36_9->PSS1_IMUX_B36_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_9" }, "PSS1.PSS_IMUX_B37_0->PSS1_IMUX_B37_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_0" }, "PSS1.PSS_IMUX_B37_1->PSS1_IMUX_B37_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_1" }, "PSS1.PSS_IMUX_B37_10->PSS1_IMUX_B37_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_10" }, "PSS1.PSS_IMUX_B37_11->PSS1_IMUX_B37_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_11" }, "PSS1.PSS_IMUX_B37_12->PSS1_IMUX_B37_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_12" }, "PSS1.PSS_IMUX_B37_13->PSS1_IMUX_B37_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_13" }, "PSS1.PSS_IMUX_B37_14->PSS1_IMUX_B37_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_14" }, "PSS1.PSS_IMUX_B37_15->PSS1_IMUX_B37_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_15" }, "PSS1.PSS_IMUX_B37_16->PSS1_IMUX_B37_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_16" }, "PSS1.PSS_IMUX_B37_17->PSS1_IMUX_B37_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_17" }, "PSS1.PSS_IMUX_B37_18->PSS1_IMUX_B37_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_18" }, "PSS1.PSS_IMUX_B37_19->PSS1_IMUX_B37_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_19" }, "PSS1.PSS_IMUX_B37_2->PSS1_IMUX_B37_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_2" }, "PSS1.PSS_IMUX_B37_3->PSS1_IMUX_B37_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_3" }, "PSS1.PSS_IMUX_B37_4->PSS1_IMUX_B37_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_4" }, "PSS1.PSS_IMUX_B37_5->PSS1_IMUX_B37_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_5" }, "PSS1.PSS_IMUX_B37_6->PSS1_IMUX_B37_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_6" }, "PSS1.PSS_IMUX_B37_7->PSS1_IMUX_B37_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_7" }, "PSS1.PSS_IMUX_B37_8->PSS1_IMUX_B37_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_8" }, "PSS1.PSS_IMUX_B37_9->PSS1_IMUX_B37_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_9" }, "PSS1.PSS_IMUX_B38_0->PSS1_IMUX_B38_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_0" }, "PSS1.PSS_IMUX_B38_1->PSS1_IMUX_B38_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_1" }, "PSS1.PSS_IMUX_B38_10->PSS1_IMUX_B38_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_10" }, "PSS1.PSS_IMUX_B38_11->PSS1_IMUX_B38_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_11" }, "PSS1.PSS_IMUX_B38_12->PSS1_IMUX_B38_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_12" }, "PSS1.PSS_IMUX_B38_13->PSS1_IMUX_B38_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_13" }, "PSS1.PSS_IMUX_B38_14->PSS1_IMUX_B38_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_14" }, "PSS1.PSS_IMUX_B38_15->PSS1_IMUX_B38_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_15" }, "PSS1.PSS_IMUX_B38_16->PSS1_IMUX_B38_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_16" }, "PSS1.PSS_IMUX_B38_17->PSS1_IMUX_B38_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_17" }, "PSS1.PSS_IMUX_B38_18->PSS1_IMUX_B38_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_18" }, "PSS1.PSS_IMUX_B38_19->PSS1_IMUX_B38_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_19" }, "PSS1.PSS_IMUX_B38_2->PSS1_IMUX_B38_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_2" }, "PSS1.PSS_IMUX_B38_3->PSS1_IMUX_B38_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_3" }, "PSS1.PSS_IMUX_B38_4->PSS1_IMUX_B38_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_4" }, "PSS1.PSS_IMUX_B38_5->PSS1_IMUX_B38_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_5" }, "PSS1.PSS_IMUX_B38_6->PSS1_IMUX_B38_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_6" }, "PSS1.PSS_IMUX_B38_7->PSS1_IMUX_B38_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_7" }, "PSS1.PSS_IMUX_B38_8->PSS1_IMUX_B38_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_8" }, "PSS1.PSS_IMUX_B38_9->PSS1_IMUX_B38_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_9" }, "PSS1.PSS_IMUX_B39_0->PSS1_IMUX_B39_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_0" }, "PSS1.PSS_IMUX_B39_1->PSS1_IMUX_B39_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_1" }, "PSS1.PSS_IMUX_B39_10->PSS1_IMUX_B39_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_10" }, "PSS1.PSS_IMUX_B39_11->PSS1_IMUX_B39_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_11" }, "PSS1.PSS_IMUX_B39_12->PSS1_IMUX_B39_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_12" }, "PSS1.PSS_IMUX_B39_13->PSS1_IMUX_B39_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_13" }, "PSS1.PSS_IMUX_B39_14->PSS1_IMUX_B39_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_14" }, "PSS1.PSS_IMUX_B39_15->PSS1_IMUX_B39_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_15" }, "PSS1.PSS_IMUX_B39_16->PSS1_IMUX_B39_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_16" }, "PSS1.PSS_IMUX_B39_17->PSS1_IMUX_B39_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_17" }, "PSS1.PSS_IMUX_B39_18->PSS1_IMUX_B39_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_18" }, "PSS1.PSS_IMUX_B39_19->PSS1_IMUX_B39_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_19" }, "PSS1.PSS_IMUX_B39_2->PSS1_IMUX_B39_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_2" }, "PSS1.PSS_IMUX_B39_3->PSS1_IMUX_B39_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_3" }, "PSS1.PSS_IMUX_B39_4->PSS1_IMUX_B39_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_4" }, "PSS1.PSS_IMUX_B39_5->PSS1_IMUX_B39_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_5" }, "PSS1.PSS_IMUX_B39_6->PSS1_IMUX_B39_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_6" }, "PSS1.PSS_IMUX_B39_7->PSS1_IMUX_B39_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_7" }, "PSS1.PSS_IMUX_B39_8->PSS1_IMUX_B39_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_8" }, "PSS1.PSS_IMUX_B39_9->PSS1_IMUX_B39_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_9" }, "PSS1.PSS_IMUX_B3_0->PSS1_IMUX_B3_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_0" }, "PSS1.PSS_IMUX_B3_1->PSS1_IMUX_B3_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_1" }, "PSS1.PSS_IMUX_B3_10->PSS1_IMUX_B3_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_10" }, "PSS1.PSS_IMUX_B3_11->PSS1_IMUX_B3_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_11" }, "PSS1.PSS_IMUX_B3_12->PSS1_IMUX_B3_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_12" }, "PSS1.PSS_IMUX_B3_13->PSS1_IMUX_B3_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_13" }, "PSS1.PSS_IMUX_B3_14->PSS1_IMUX_B3_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_14" }, "PSS1.PSS_IMUX_B3_15->PSS1_IMUX_B3_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_15" }, "PSS1.PSS_IMUX_B3_16->PSS1_IMUX_B3_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_16" }, "PSS1.PSS_IMUX_B3_17->PSS1_IMUX_B3_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_17" }, "PSS1.PSS_IMUX_B3_18->PSS1_IMUX_B3_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_18" }, "PSS1.PSS_IMUX_B3_19->PSS1_IMUX_B3_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_19" }, "PSS1.PSS_IMUX_B3_2->PSS1_IMUX_B3_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_2" }, "PSS1.PSS_IMUX_B3_3->PSS1_IMUX_B3_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_3" }, "PSS1.PSS_IMUX_B3_4->PSS1_IMUX_B3_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_4" }, "PSS1.PSS_IMUX_B3_5->PSS1_IMUX_B3_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_5" }, "PSS1.PSS_IMUX_B3_6->PSS1_IMUX_B3_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_6" }, "PSS1.PSS_IMUX_B3_7->PSS1_IMUX_B3_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_7" }, "PSS1.PSS_IMUX_B3_8->PSS1_IMUX_B3_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_8" }, "PSS1.PSS_IMUX_B3_9->PSS1_IMUX_B3_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_9" }, "PSS1.PSS_IMUX_B40_0->PSS1_IMUX_B40_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_0" }, "PSS1.PSS_IMUX_B40_1->PSS1_IMUX_B40_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_1" }, "PSS1.PSS_IMUX_B40_10->PSS1_IMUX_B40_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_10" }, "PSS1.PSS_IMUX_B40_11->PSS1_IMUX_B40_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_11" }, "PSS1.PSS_IMUX_B40_12->PSS1_IMUX_B40_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_12" }, "PSS1.PSS_IMUX_B40_13->PSS1_IMUX_B40_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_13" }, "PSS1.PSS_IMUX_B40_14->PSS1_IMUX_B40_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_14" }, "PSS1.PSS_IMUX_B40_15->PSS1_IMUX_B40_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_15" }, "PSS1.PSS_IMUX_B40_16->PSS1_IMUX_B40_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_16" }, "PSS1.PSS_IMUX_B40_17->PSS1_IMUX_B40_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_17" }, "PSS1.PSS_IMUX_B40_18->PSS1_IMUX_B40_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_18" }, "PSS1.PSS_IMUX_B40_19->PSS1_IMUX_B40_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_19" }, "PSS1.PSS_IMUX_B40_2->PSS1_IMUX_B40_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_2" }, "PSS1.PSS_IMUX_B40_3->PSS1_IMUX_B40_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_3" }, "PSS1.PSS_IMUX_B40_4->PSS1_IMUX_B40_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_4" }, "PSS1.PSS_IMUX_B40_5->PSS1_IMUX_B40_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_5" }, "PSS1.PSS_IMUX_B40_6->PSS1_IMUX_B40_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_6" }, "PSS1.PSS_IMUX_B40_7->PSS1_IMUX_B40_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_7" }, "PSS1.PSS_IMUX_B40_8->PSS1_IMUX_B40_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_8" }, "PSS1.PSS_IMUX_B40_9->PSS1_IMUX_B40_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_9" }, "PSS1.PSS_IMUX_B41_0->PSS1_IMUX_B41_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_0" }, "PSS1.PSS_IMUX_B41_1->PSS1_IMUX_B41_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_1" }, "PSS1.PSS_IMUX_B41_10->PSS1_IMUX_B41_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_10" }, "PSS1.PSS_IMUX_B41_11->PSS1_IMUX_B41_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_11" }, "PSS1.PSS_IMUX_B41_12->PSS1_IMUX_B41_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_12" }, "PSS1.PSS_IMUX_B41_13->PSS1_IMUX_B41_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_13" }, "PSS1.PSS_IMUX_B41_14->PSS1_IMUX_B41_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_14" }, "PSS1.PSS_IMUX_B41_15->PSS1_IMUX_B41_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_15" }, "PSS1.PSS_IMUX_B41_16->PSS1_IMUX_B41_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_16" }, "PSS1.PSS_IMUX_B41_17->PSS1_IMUX_B41_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_17" }, "PSS1.PSS_IMUX_B41_18->PSS1_IMUX_B41_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_18" }, "PSS1.PSS_IMUX_B41_19->PSS1_IMUX_B41_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_19" }, "PSS1.PSS_IMUX_B41_2->PSS1_IMUX_B41_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_2" }, "PSS1.PSS_IMUX_B41_3->PSS1_IMUX_B41_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_3" }, "PSS1.PSS_IMUX_B41_4->PSS1_IMUX_B41_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_4" }, "PSS1.PSS_IMUX_B41_5->PSS1_IMUX_B41_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_5" }, "PSS1.PSS_IMUX_B41_6->PSS1_IMUX_B41_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_6" }, "PSS1.PSS_IMUX_B41_7->PSS1_IMUX_B41_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_7" }, "PSS1.PSS_IMUX_B41_8->PSS1_IMUX_B41_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_8" }, "PSS1.PSS_IMUX_B41_9->PSS1_IMUX_B41_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_9" }, "PSS1.PSS_IMUX_B42_0->PSS1_IMUX_B42_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_0" }, "PSS1.PSS_IMUX_B42_1->PSS1_IMUX_B42_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_1" }, "PSS1.PSS_IMUX_B42_10->PSS1_IMUX_B42_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_10" }, "PSS1.PSS_IMUX_B42_11->PSS1_IMUX_B42_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_11" }, "PSS1.PSS_IMUX_B42_12->PSS1_IMUX_B42_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_12" }, "PSS1.PSS_IMUX_B42_13->PSS1_IMUX_B42_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_13" }, "PSS1.PSS_IMUX_B42_14->PSS1_IMUX_B42_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_14" }, "PSS1.PSS_IMUX_B42_15->PSS1_IMUX_B42_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_15" }, "PSS1.PSS_IMUX_B42_16->PSS1_IMUX_B42_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_16" }, "PSS1.PSS_IMUX_B42_17->PSS1_IMUX_B42_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_17" }, "PSS1.PSS_IMUX_B42_18->PSS1_IMUX_B42_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_18" }, "PSS1.PSS_IMUX_B42_19->PSS1_IMUX_B42_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_19" }, "PSS1.PSS_IMUX_B42_2->PSS1_IMUX_B42_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_2" }, "PSS1.PSS_IMUX_B42_3->PSS1_IMUX_B42_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_3" }, "PSS1.PSS_IMUX_B42_4->PSS1_IMUX_B42_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_4" }, "PSS1.PSS_IMUX_B42_5->PSS1_IMUX_B42_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_5" }, "PSS1.PSS_IMUX_B42_6->PSS1_IMUX_B42_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_6" }, "PSS1.PSS_IMUX_B42_7->PSS1_IMUX_B42_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_7" }, "PSS1.PSS_IMUX_B42_8->PSS1_IMUX_B42_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_8" }, "PSS1.PSS_IMUX_B42_9->PSS1_IMUX_B42_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_9" }, "PSS1.PSS_IMUX_B43_0->PSS1_IMUX_B43_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_0" }, "PSS1.PSS_IMUX_B43_1->PSS1_IMUX_B43_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_1" }, "PSS1.PSS_IMUX_B43_10->PSS1_IMUX_B43_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_10" }, "PSS1.PSS_IMUX_B43_11->PSS1_IMUX_B43_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_11" }, "PSS1.PSS_IMUX_B43_12->PSS1_IMUX_B43_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_12" }, "PSS1.PSS_IMUX_B43_13->PSS1_IMUX_B43_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_13" }, "PSS1.PSS_IMUX_B43_14->PSS1_IMUX_B43_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_14" }, "PSS1.PSS_IMUX_B43_15->PSS1_IMUX_B43_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_15" }, "PSS1.PSS_IMUX_B43_16->PSS1_IMUX_B43_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_16" }, "PSS1.PSS_IMUX_B43_17->PSS1_IMUX_B43_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_17" }, "PSS1.PSS_IMUX_B43_18->PSS1_IMUX_B43_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_18" }, "PSS1.PSS_IMUX_B43_19->PSS1_IMUX_B43_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_19" }, "PSS1.PSS_IMUX_B43_2->PSS1_IMUX_B43_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_2" }, "PSS1.PSS_IMUX_B43_3->PSS1_IMUX_B43_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_3" }, "PSS1.PSS_IMUX_B43_4->PSS1_IMUX_B43_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_4" }, "PSS1.PSS_IMUX_B43_5->PSS1_IMUX_B43_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_5" }, "PSS1.PSS_IMUX_B43_6->PSS1_IMUX_B43_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_6" }, "PSS1.PSS_IMUX_B43_7->PSS1_IMUX_B43_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_7" }, "PSS1.PSS_IMUX_B43_8->PSS1_IMUX_B43_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_8" }, "PSS1.PSS_IMUX_B43_9->PSS1_IMUX_B43_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_9" }, "PSS1.PSS_IMUX_B44_0->PSS1_IMUX_B44_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_0" }, "PSS1.PSS_IMUX_B44_1->PSS1_IMUX_B44_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_1" }, "PSS1.PSS_IMUX_B44_10->PSS1_IMUX_B44_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_10" }, "PSS1.PSS_IMUX_B44_11->PSS1_IMUX_B44_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_11" }, "PSS1.PSS_IMUX_B44_12->PSS1_IMUX_B44_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_12" }, "PSS1.PSS_IMUX_B44_13->PSS1_IMUX_B44_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_13" }, "PSS1.PSS_IMUX_B44_14->PSS1_IMUX_B44_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_14" }, "PSS1.PSS_IMUX_B44_15->PSS1_IMUX_B44_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_15" }, "PSS1.PSS_IMUX_B44_16->PSS1_IMUX_B44_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_16" }, "PSS1.PSS_IMUX_B44_17->PSS1_IMUX_B44_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_17" }, "PSS1.PSS_IMUX_B44_18->PSS1_IMUX_B44_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_18" }, "PSS1.PSS_IMUX_B44_19->PSS1_IMUX_B44_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_19" }, "PSS1.PSS_IMUX_B44_2->PSS1_IMUX_B44_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_2" }, "PSS1.PSS_IMUX_B44_3->PSS1_IMUX_B44_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_3" }, "PSS1.PSS_IMUX_B44_4->PSS1_IMUX_B44_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_4" }, "PSS1.PSS_IMUX_B44_5->PSS1_IMUX_B44_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_5" }, "PSS1.PSS_IMUX_B44_6->PSS1_IMUX_B44_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_6" }, "PSS1.PSS_IMUX_B44_7->PSS1_IMUX_B44_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_7" }, "PSS1.PSS_IMUX_B44_8->PSS1_IMUX_B44_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_8" }, "PSS1.PSS_IMUX_B44_9->PSS1_IMUX_B44_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_9" }, "PSS1.PSS_IMUX_B45_0->PSS1_IMUX_B45_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_0" }, "PSS1.PSS_IMUX_B45_1->PSS1_IMUX_B45_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_1" }, "PSS1.PSS_IMUX_B45_10->PSS1_IMUX_B45_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_10" }, "PSS1.PSS_IMUX_B45_11->PSS1_IMUX_B45_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_11" }, "PSS1.PSS_IMUX_B45_12->PSS1_IMUX_B45_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_12" }, "PSS1.PSS_IMUX_B45_13->PSS1_IMUX_B45_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_13" }, "PSS1.PSS_IMUX_B45_14->PSS1_IMUX_B45_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_14" }, "PSS1.PSS_IMUX_B45_15->PSS1_IMUX_B45_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_15" }, "PSS1.PSS_IMUX_B45_16->PSS1_IMUX_B45_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_16" }, "PSS1.PSS_IMUX_B45_17->PSS1_IMUX_B45_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_17" }, "PSS1.PSS_IMUX_B45_18->PSS1_IMUX_B45_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_18" }, "PSS1.PSS_IMUX_B45_19->PSS1_IMUX_B45_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_19" }, "PSS1.PSS_IMUX_B45_2->PSS1_IMUX_B45_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_2" }, "PSS1.PSS_IMUX_B45_3->PSS1_IMUX_B45_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_3" }, "PSS1.PSS_IMUX_B45_4->PSS1_IMUX_B45_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_4" }, "PSS1.PSS_IMUX_B45_5->PSS1_IMUX_B45_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_5" }, "PSS1.PSS_IMUX_B45_6->PSS1_IMUX_B45_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_6" }, "PSS1.PSS_IMUX_B45_7->PSS1_IMUX_B45_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_7" }, "PSS1.PSS_IMUX_B45_8->PSS1_IMUX_B45_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_8" }, "PSS1.PSS_IMUX_B45_9->PSS1_IMUX_B45_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_9" }, "PSS1.PSS_IMUX_B46_0->PSS1_IMUX_B46_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_0" }, "PSS1.PSS_IMUX_B46_1->PSS1_IMUX_B46_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_1" }, "PSS1.PSS_IMUX_B46_10->PSS1_IMUX_B46_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_10" }, "PSS1.PSS_IMUX_B46_11->PSS1_IMUX_B46_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_11" }, "PSS1.PSS_IMUX_B46_12->PSS1_IMUX_B46_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_12" }, "PSS1.PSS_IMUX_B46_13->PSS1_IMUX_B46_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_13" }, "PSS1.PSS_IMUX_B46_14->PSS1_IMUX_B46_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_14" }, "PSS1.PSS_IMUX_B46_15->PSS1_IMUX_B46_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_15" }, "PSS1.PSS_IMUX_B46_16->PSS1_IMUX_B46_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_16" }, "PSS1.PSS_IMUX_B46_17->PSS1_IMUX_B46_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_17" }, "PSS1.PSS_IMUX_B46_18->PSS1_IMUX_B46_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_18" }, "PSS1.PSS_IMUX_B46_19->PSS1_IMUX_B46_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_19" }, "PSS1.PSS_IMUX_B46_2->PSS1_IMUX_B46_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_2" }, "PSS1.PSS_IMUX_B46_3->PSS1_IMUX_B46_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_3" }, "PSS1.PSS_IMUX_B46_4->PSS1_IMUX_B46_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_4" }, "PSS1.PSS_IMUX_B46_5->PSS1_IMUX_B46_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_5" }, "PSS1.PSS_IMUX_B46_6->PSS1_IMUX_B46_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_6" }, "PSS1.PSS_IMUX_B46_7->PSS1_IMUX_B46_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_7" }, "PSS1.PSS_IMUX_B46_8->PSS1_IMUX_B46_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_8" }, "PSS1.PSS_IMUX_B46_9->PSS1_IMUX_B46_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_9" }, "PSS1.PSS_IMUX_B47_0->PSS1_IMUX_B47_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_0" }, "PSS1.PSS_IMUX_B47_1->PSS1_IMUX_B47_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_1" }, "PSS1.PSS_IMUX_B47_10->PSS1_IMUX_B47_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_10" }, "PSS1.PSS_IMUX_B47_11->PSS1_IMUX_B47_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_11" }, "PSS1.PSS_IMUX_B47_12->PSS1_IMUX_B47_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_12" }, "PSS1.PSS_IMUX_B47_13->PSS1_IMUX_B47_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_13" }, "PSS1.PSS_IMUX_B47_14->PSS1_IMUX_B47_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_14" }, "PSS1.PSS_IMUX_B47_15->PSS1_IMUX_B47_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_15" }, "PSS1.PSS_IMUX_B47_16->PSS1_IMUX_B47_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_16" }, "PSS1.PSS_IMUX_B47_17->PSS1_IMUX_B47_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_17" }, "PSS1.PSS_IMUX_B47_18->PSS1_IMUX_B47_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_18" }, "PSS1.PSS_IMUX_B47_19->PSS1_IMUX_B47_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_19" }, "PSS1.PSS_IMUX_B47_2->PSS1_IMUX_B47_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_2" }, "PSS1.PSS_IMUX_B47_3->PSS1_IMUX_B47_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_3" }, "PSS1.PSS_IMUX_B47_4->PSS1_IMUX_B47_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_4" }, "PSS1.PSS_IMUX_B47_5->PSS1_IMUX_B47_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_5" }, "PSS1.PSS_IMUX_B47_6->PSS1_IMUX_B47_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_6" }, "PSS1.PSS_IMUX_B47_7->PSS1_IMUX_B47_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_7" }, "PSS1.PSS_IMUX_B47_8->PSS1_IMUX_B47_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_8" }, "PSS1.PSS_IMUX_B47_9->PSS1_IMUX_B47_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_9" }, "PSS1.PSS_IMUX_B4_0->PSS1_IMUX_B4_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_0" }, "PSS1.PSS_IMUX_B4_1->PSS1_IMUX_B4_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_1" }, "PSS1.PSS_IMUX_B4_10->PSS1_IMUX_B4_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_10" }, "PSS1.PSS_IMUX_B4_11->PSS1_IMUX_B4_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_11" }, "PSS1.PSS_IMUX_B4_12->PSS1_IMUX_B4_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_12" }, "PSS1.PSS_IMUX_B4_13->PSS1_IMUX_B4_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_13" }, "PSS1.PSS_IMUX_B4_14->PSS1_IMUX_B4_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_14" }, "PSS1.PSS_IMUX_B4_15->PSS1_IMUX_B4_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_15" }, "PSS1.PSS_IMUX_B4_16->PSS1_IMUX_B4_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_16" }, "PSS1.PSS_IMUX_B4_17->PSS1_IMUX_B4_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_17" }, "PSS1.PSS_IMUX_B4_18->PSS1_IMUX_B4_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_18" }, "PSS1.PSS_IMUX_B4_19->PSS1_IMUX_B4_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_19" }, "PSS1.PSS_IMUX_B4_2->PSS1_IMUX_B4_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_2" }, "PSS1.PSS_IMUX_B4_3->PSS1_IMUX_B4_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_3" }, "PSS1.PSS_IMUX_B4_4->PSS1_IMUX_B4_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_4" }, "PSS1.PSS_IMUX_B4_5->PSS1_IMUX_B4_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_5" }, "PSS1.PSS_IMUX_B4_6->PSS1_IMUX_B4_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_6" }, "PSS1.PSS_IMUX_B4_7->PSS1_IMUX_B4_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_7" }, "PSS1.PSS_IMUX_B4_8->PSS1_IMUX_B4_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_8" }, "PSS1.PSS_IMUX_B4_9->PSS1_IMUX_B4_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_9" }, "PSS1.PSS_IMUX_B5_0->PSS1_IMUX_B5_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_0" }, "PSS1.PSS_IMUX_B5_1->PSS1_IMUX_B5_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_1" }, "PSS1.PSS_IMUX_B5_10->PSS1_IMUX_B5_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_10" }, "PSS1.PSS_IMUX_B5_11->PSS1_IMUX_B5_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_11" }, "PSS1.PSS_IMUX_B5_12->PSS1_IMUX_B5_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_12" }, "PSS1.PSS_IMUX_B5_13->PSS1_IMUX_B5_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_13" }, "PSS1.PSS_IMUX_B5_14->PSS1_IMUX_B5_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_14" }, "PSS1.PSS_IMUX_B5_15->PSS1_IMUX_B5_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_15" }, "PSS1.PSS_IMUX_B5_16->PSS1_IMUX_B5_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_16" }, "PSS1.PSS_IMUX_B5_17->PSS1_IMUX_B5_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_17" }, "PSS1.PSS_IMUX_B5_18->PSS1_IMUX_B5_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_18" }, "PSS1.PSS_IMUX_B5_19->PSS1_IMUX_B5_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_19" }, "PSS1.PSS_IMUX_B5_2->PSS1_IMUX_B5_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_2" }, "PSS1.PSS_IMUX_B5_3->PSS1_IMUX_B5_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_3" }, "PSS1.PSS_IMUX_B5_4->PSS1_IMUX_B5_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_4" }, "PSS1.PSS_IMUX_B5_5->PSS1_IMUX_B5_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_5" }, "PSS1.PSS_IMUX_B5_6->PSS1_IMUX_B5_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_6" }, "PSS1.PSS_IMUX_B5_7->PSS1_IMUX_B5_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_7" }, "PSS1.PSS_IMUX_B5_8->PSS1_IMUX_B5_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_8" }, "PSS1.PSS_IMUX_B5_9->PSS1_IMUX_B5_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_9" }, "PSS1.PSS_IMUX_B6_0->PSS1_IMUX_B6_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_0" }, "PSS1.PSS_IMUX_B6_1->PSS1_IMUX_B6_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_1" }, "PSS1.PSS_IMUX_B6_10->PSS1_IMUX_B6_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_10" }, "PSS1.PSS_IMUX_B6_11->PSS1_IMUX_B6_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_11" }, "PSS1.PSS_IMUX_B6_12->PSS1_IMUX_B6_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_12" }, "PSS1.PSS_IMUX_B6_13->PSS1_IMUX_B6_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_13" }, "PSS1.PSS_IMUX_B6_14->PSS1_IMUX_B6_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_14" }, "PSS1.PSS_IMUX_B6_15->PSS1_IMUX_B6_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_15" }, "PSS1.PSS_IMUX_B6_16->PSS1_IMUX_B6_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_16" }, "PSS1.PSS_IMUX_B6_17->PSS1_IMUX_B6_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_17" }, "PSS1.PSS_IMUX_B6_18->PSS1_IMUX_B6_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_18" }, "PSS1.PSS_IMUX_B6_19->PSS1_IMUX_B6_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_19" }, "PSS1.PSS_IMUX_B6_2->PSS1_IMUX_B6_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_2" }, "PSS1.PSS_IMUX_B6_3->PSS1_IMUX_B6_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_3" }, "PSS1.PSS_IMUX_B6_4->PSS1_IMUX_B6_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_4" }, "PSS1.PSS_IMUX_B6_5->PSS1_IMUX_B6_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_5" }, "PSS1.PSS_IMUX_B6_6->PSS1_IMUX_B6_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_6" }, "PSS1.PSS_IMUX_B6_7->PSS1_IMUX_B6_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_7" }, "PSS1.PSS_IMUX_B6_8->PSS1_IMUX_B6_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_8" }, "PSS1.PSS_IMUX_B6_9->PSS1_IMUX_B6_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_9" }, "PSS1.PSS_IMUX_B7_0->PSS1_IMUX_B7_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_0" }, "PSS1.PSS_IMUX_B7_1->PSS1_IMUX_B7_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_1" }, "PSS1.PSS_IMUX_B7_10->PSS1_IMUX_B7_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_10" }, "PSS1.PSS_IMUX_B7_11->PSS1_IMUX_B7_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_11" }, "PSS1.PSS_IMUX_B7_12->PSS1_IMUX_B7_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_12" }, "PSS1.PSS_IMUX_B7_13->PSS1_IMUX_B7_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_13" }, "PSS1.PSS_IMUX_B7_14->PSS1_IMUX_B7_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_14" }, "PSS1.PSS_IMUX_B7_15->PSS1_IMUX_B7_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_15" }, "PSS1.PSS_IMUX_B7_16->PSS1_IMUX_B7_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_16" }, "PSS1.PSS_IMUX_B7_17->PSS1_IMUX_B7_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_17" }, "PSS1.PSS_IMUX_B7_18->PSS1_IMUX_B7_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_18" }, "PSS1.PSS_IMUX_B7_19->PSS1_IMUX_B7_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_19" }, "PSS1.PSS_IMUX_B7_2->PSS1_IMUX_B7_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_2" }, "PSS1.PSS_IMUX_B7_3->PSS1_IMUX_B7_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_3" }, "PSS1.PSS_IMUX_B7_4->PSS1_IMUX_B7_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_4" }, "PSS1.PSS_IMUX_B7_5->PSS1_IMUX_B7_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_5" }, "PSS1.PSS_IMUX_B7_6->PSS1_IMUX_B7_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_6" }, "PSS1.PSS_IMUX_B7_7->PSS1_IMUX_B7_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_7" }, "PSS1.PSS_IMUX_B7_8->PSS1_IMUX_B7_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_8" }, "PSS1.PSS_IMUX_B7_9->PSS1_IMUX_B7_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_9" }, "PSS1.PSS_IMUX_B8_0->PSS1_IMUX_B8_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_0" }, "PSS1.PSS_IMUX_B8_1->PSS1_IMUX_B8_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_1" }, "PSS1.PSS_IMUX_B8_10->PSS1_IMUX_B8_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_10" }, "PSS1.PSS_IMUX_B8_11->PSS1_IMUX_B8_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_11" }, "PSS1.PSS_IMUX_B8_12->PSS1_IMUX_B8_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_12" }, "PSS1.PSS_IMUX_B8_13->PSS1_IMUX_B8_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_13" }, "PSS1.PSS_IMUX_B8_14->PSS1_IMUX_B8_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_14" }, "PSS1.PSS_IMUX_B8_15->PSS1_IMUX_B8_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_15" }, "PSS1.PSS_IMUX_B8_16->PSS1_IMUX_B8_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_16" }, "PSS1.PSS_IMUX_B8_17->PSS1_IMUX_B8_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_17" }, "PSS1.PSS_IMUX_B8_18->PSS1_IMUX_B8_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_18" }, "PSS1.PSS_IMUX_B8_19->PSS1_IMUX_B8_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_19" }, "PSS1.PSS_IMUX_B8_2->PSS1_IMUX_B8_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_2" }, "PSS1.PSS_IMUX_B8_3->PSS1_IMUX_B8_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_3" }, "PSS1.PSS_IMUX_B8_4->PSS1_IMUX_B8_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_4" }, "PSS1.PSS_IMUX_B8_5->PSS1_IMUX_B8_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_5" }, "PSS1.PSS_IMUX_B8_6->PSS1_IMUX_B8_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_6" }, "PSS1.PSS_IMUX_B8_7->PSS1_IMUX_B8_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_7" }, "PSS1.PSS_IMUX_B8_8->PSS1_IMUX_B8_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_8" }, "PSS1.PSS_IMUX_B8_9->PSS1_IMUX_B8_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_9" }, "PSS1.PSS_IMUX_B9_0->PSS1_IMUX_B9_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_0" }, "PSS1.PSS_IMUX_B9_1->PSS1_IMUX_B9_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_1" }, "PSS1.PSS_IMUX_B9_10->PSS1_IMUX_B9_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_10" }, "PSS1.PSS_IMUX_B9_11->PSS1_IMUX_B9_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_11" }, "PSS1.PSS_IMUX_B9_12->PSS1_IMUX_B9_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_12" }, "PSS1.PSS_IMUX_B9_13->PSS1_IMUX_B9_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_13" }, "PSS1.PSS_IMUX_B9_14->PSS1_IMUX_B9_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_14" }, "PSS1.PSS_IMUX_B9_15->PSS1_IMUX_B9_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_15" }, "PSS1.PSS_IMUX_B9_16->PSS1_IMUX_B9_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_16" }, "PSS1.PSS_IMUX_B9_17->PSS1_IMUX_B9_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_17" }, "PSS1.PSS_IMUX_B9_18->PSS1_IMUX_B9_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_18" }, "PSS1.PSS_IMUX_B9_19->PSS1_IMUX_B9_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_19" }, "PSS1.PSS_IMUX_B9_2->PSS1_IMUX_B9_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_2" }, "PSS1.PSS_IMUX_B9_3->PSS1_IMUX_B9_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_3" }, "PSS1.PSS_IMUX_B9_4->PSS1_IMUX_B9_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_4" }, "PSS1.PSS_IMUX_B9_5->PSS1_IMUX_B9_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_5" }, "PSS1.PSS_IMUX_B9_6->PSS1_IMUX_B9_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_6" }, "PSS1.PSS_IMUX_B9_7->PSS1_IMUX_B9_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_7" }, "PSS1.PSS_IMUX_B9_8->PSS1_IMUX_B9_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_8" }, "PSS1.PSS_IMUX_B9_9->PSS1_IMUX_B9_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_9" } }, "sites": [], "tile_type": "PSS1", - "wires": [ - "PSS0_CLK_B0_0", - "PSS0_CLK_B0_1", - "PSS0_CLK_B0_10", - "PSS0_CLK_B0_11", - "PSS0_CLK_B0_12", - "PSS0_CLK_B0_13", - "PSS0_CLK_B0_14", - "PSS0_CLK_B0_15", - "PSS0_CLK_B0_16", - "PSS0_CLK_B0_17", - "PSS0_CLK_B0_18", - "PSS0_CLK_B0_19", - "PSS0_CLK_B0_2", - "PSS0_CLK_B0_3", - "PSS0_CLK_B0_4", - "PSS0_CLK_B0_5", - "PSS0_CLK_B0_6", - "PSS0_CLK_B0_7", - "PSS0_CLK_B0_8", - "PSS0_CLK_B0_9", - "PSS0_CLK_B1_0", - "PSS0_CLK_B1_1", - "PSS0_CLK_B1_10", - "PSS0_CLK_B1_11", - "PSS0_CLK_B1_12", - "PSS0_CLK_B1_13", - "PSS0_CLK_B1_14", - "PSS0_CLK_B1_15", - "PSS0_CLK_B1_16", - "PSS0_CLK_B1_17", - "PSS0_CLK_B1_18", - "PSS0_CLK_B1_19", - "PSS0_CLK_B1_2", - "PSS0_CLK_B1_3", - "PSS0_CLK_B1_4", - "PSS0_CLK_B1_5", - "PSS0_CLK_B1_6", - "PSS0_CLK_B1_7", - "PSS0_CLK_B1_8", - "PSS0_CLK_B1_9", - "PSS0_IMUX_B0_0", - "PSS0_IMUX_B0_1", - "PSS0_IMUX_B0_10", - "PSS0_IMUX_B0_11", - "PSS0_IMUX_B0_12", - "PSS0_IMUX_B0_13", - "PSS0_IMUX_B0_14", - "PSS0_IMUX_B0_15", - "PSS0_IMUX_B0_16", - "PSS0_IMUX_B0_17", - "PSS0_IMUX_B0_18", - "PSS0_IMUX_B0_19", - "PSS0_IMUX_B0_2", - "PSS0_IMUX_B0_3", - "PSS0_IMUX_B0_4", - "PSS0_IMUX_B0_5", - "PSS0_IMUX_B0_6", - "PSS0_IMUX_B0_7", - "PSS0_IMUX_B0_8", - "PSS0_IMUX_B0_9", - "PSS0_IMUX_B10_0", - "PSS0_IMUX_B10_1", - "PSS0_IMUX_B10_10", - "PSS0_IMUX_B10_11", - "PSS0_IMUX_B10_12", - "PSS0_IMUX_B10_13", - "PSS0_IMUX_B10_14", - "PSS0_IMUX_B10_15", - "PSS0_IMUX_B10_16", - "PSS0_IMUX_B10_17", - "PSS0_IMUX_B10_18", - "PSS0_IMUX_B10_19", - "PSS0_IMUX_B10_2", - "PSS0_IMUX_B10_3", - "PSS0_IMUX_B10_4", - "PSS0_IMUX_B10_5", - "PSS0_IMUX_B10_6", - "PSS0_IMUX_B10_7", - "PSS0_IMUX_B10_8", - "PSS0_IMUX_B10_9", - "PSS0_IMUX_B11_0", - "PSS0_IMUX_B11_1", - "PSS0_IMUX_B11_10", - "PSS0_IMUX_B11_11", - "PSS0_IMUX_B11_12", - "PSS0_IMUX_B11_13", - "PSS0_IMUX_B11_14", - "PSS0_IMUX_B11_15", - "PSS0_IMUX_B11_16", - "PSS0_IMUX_B11_17", - "PSS0_IMUX_B11_18", - "PSS0_IMUX_B11_19", - "PSS0_IMUX_B11_2", - "PSS0_IMUX_B11_3", - "PSS0_IMUX_B11_4", - "PSS0_IMUX_B11_5", - "PSS0_IMUX_B11_6", - "PSS0_IMUX_B11_7", - "PSS0_IMUX_B11_8", - "PSS0_IMUX_B11_9", - "PSS0_IMUX_B12_0", - "PSS0_IMUX_B12_1", - "PSS0_IMUX_B12_10", - "PSS0_IMUX_B12_11", - "PSS0_IMUX_B12_12", - "PSS0_IMUX_B12_13", - "PSS0_IMUX_B12_14", - "PSS0_IMUX_B12_15", - "PSS0_IMUX_B12_16", - "PSS0_IMUX_B12_17", - "PSS0_IMUX_B12_18", - "PSS0_IMUX_B12_19", - "PSS0_IMUX_B12_2", - "PSS0_IMUX_B12_3", - "PSS0_IMUX_B12_4", - "PSS0_IMUX_B12_5", - "PSS0_IMUX_B12_6", - "PSS0_IMUX_B12_7", - "PSS0_IMUX_B12_8", - "PSS0_IMUX_B12_9", - "PSS0_IMUX_B13_0", - "PSS0_IMUX_B13_1", - "PSS0_IMUX_B13_10", - "PSS0_IMUX_B13_11", - "PSS0_IMUX_B13_12", - "PSS0_IMUX_B13_13", - "PSS0_IMUX_B13_14", - "PSS0_IMUX_B13_15", - "PSS0_IMUX_B13_16", - "PSS0_IMUX_B13_17", - "PSS0_IMUX_B13_18", - "PSS0_IMUX_B13_19", - "PSS0_IMUX_B13_2", - "PSS0_IMUX_B13_3", - "PSS0_IMUX_B13_4", - "PSS0_IMUX_B13_5", - "PSS0_IMUX_B13_6", - "PSS0_IMUX_B13_7", - "PSS0_IMUX_B13_8", - "PSS0_IMUX_B13_9", - "PSS0_IMUX_B14_0", - "PSS0_IMUX_B14_1", - "PSS0_IMUX_B14_10", - "PSS0_IMUX_B14_11", - "PSS0_IMUX_B14_12", - "PSS0_IMUX_B14_13", - "PSS0_IMUX_B14_14", - "PSS0_IMUX_B14_15", - "PSS0_IMUX_B14_16", - "PSS0_IMUX_B14_17", - "PSS0_IMUX_B14_18", - "PSS0_IMUX_B14_19", - "PSS0_IMUX_B14_2", - "PSS0_IMUX_B14_3", - "PSS0_IMUX_B14_4", - "PSS0_IMUX_B14_5", - "PSS0_IMUX_B14_6", - "PSS0_IMUX_B14_7", - "PSS0_IMUX_B14_8", - "PSS0_IMUX_B14_9", - "PSS0_IMUX_B15_0", - "PSS0_IMUX_B15_1", - "PSS0_IMUX_B15_10", - "PSS0_IMUX_B15_11", - "PSS0_IMUX_B15_12", - "PSS0_IMUX_B15_13", - "PSS0_IMUX_B15_14", - "PSS0_IMUX_B15_15", - "PSS0_IMUX_B15_16", - "PSS0_IMUX_B15_17", - "PSS0_IMUX_B15_18", - "PSS0_IMUX_B15_19", - "PSS0_IMUX_B15_2", - "PSS0_IMUX_B15_3", - "PSS0_IMUX_B15_4", - "PSS0_IMUX_B15_5", - "PSS0_IMUX_B15_6", - "PSS0_IMUX_B15_7", - "PSS0_IMUX_B15_8", - "PSS0_IMUX_B15_9", - "PSS0_IMUX_B16_0", - "PSS0_IMUX_B16_1", - "PSS0_IMUX_B16_10", - "PSS0_IMUX_B16_11", - "PSS0_IMUX_B16_12", - "PSS0_IMUX_B16_13", - "PSS0_IMUX_B16_14", - "PSS0_IMUX_B16_15", - "PSS0_IMUX_B16_16", - "PSS0_IMUX_B16_17", - "PSS0_IMUX_B16_18", - "PSS0_IMUX_B16_19", - "PSS0_IMUX_B16_2", - "PSS0_IMUX_B16_3", - "PSS0_IMUX_B16_4", - "PSS0_IMUX_B16_5", - "PSS0_IMUX_B16_6", - "PSS0_IMUX_B16_7", - "PSS0_IMUX_B16_8", - "PSS0_IMUX_B16_9", - "PSS0_IMUX_B17_0", - "PSS0_IMUX_B17_1", - "PSS0_IMUX_B17_10", - "PSS0_IMUX_B17_11", - "PSS0_IMUX_B17_12", - "PSS0_IMUX_B17_13", - "PSS0_IMUX_B17_14", - "PSS0_IMUX_B17_15", - "PSS0_IMUX_B17_16", - "PSS0_IMUX_B17_17", - "PSS0_IMUX_B17_18", - "PSS0_IMUX_B17_19", - "PSS0_IMUX_B17_2", - "PSS0_IMUX_B17_3", - "PSS0_IMUX_B17_4", - "PSS0_IMUX_B17_5", - "PSS0_IMUX_B17_6", - "PSS0_IMUX_B17_7", - "PSS0_IMUX_B17_8", - "PSS0_IMUX_B17_9", - "PSS0_IMUX_B18_0", - "PSS0_IMUX_B18_1", - "PSS0_IMUX_B18_10", - "PSS0_IMUX_B18_11", - "PSS0_IMUX_B18_12", - "PSS0_IMUX_B18_13", - "PSS0_IMUX_B18_14", - "PSS0_IMUX_B18_15", - "PSS0_IMUX_B18_16", - "PSS0_IMUX_B18_17", - "PSS0_IMUX_B18_18", - "PSS0_IMUX_B18_19", - "PSS0_IMUX_B18_2", - "PSS0_IMUX_B18_3", - "PSS0_IMUX_B18_4", - "PSS0_IMUX_B18_5", - "PSS0_IMUX_B18_6", - "PSS0_IMUX_B18_7", - "PSS0_IMUX_B18_8", - "PSS0_IMUX_B18_9", - "PSS0_IMUX_B19_0", - "PSS0_IMUX_B19_1", - "PSS0_IMUX_B19_10", - "PSS0_IMUX_B19_11", - "PSS0_IMUX_B19_12", - "PSS0_IMUX_B19_13", - "PSS0_IMUX_B19_14", - "PSS0_IMUX_B19_15", - "PSS0_IMUX_B19_16", - "PSS0_IMUX_B19_17", - "PSS0_IMUX_B19_18", - "PSS0_IMUX_B19_19", - "PSS0_IMUX_B19_2", - "PSS0_IMUX_B19_3", - "PSS0_IMUX_B19_4", - "PSS0_IMUX_B19_5", - "PSS0_IMUX_B19_6", - "PSS0_IMUX_B19_7", - "PSS0_IMUX_B19_8", - "PSS0_IMUX_B19_9", - "PSS0_IMUX_B1_0", - "PSS0_IMUX_B1_1", - "PSS0_IMUX_B1_10", - "PSS0_IMUX_B1_11", - "PSS0_IMUX_B1_12", - "PSS0_IMUX_B1_13", - "PSS0_IMUX_B1_14", - "PSS0_IMUX_B1_15", - "PSS0_IMUX_B1_16", - "PSS0_IMUX_B1_17", - "PSS0_IMUX_B1_18", - "PSS0_IMUX_B1_19", - "PSS0_IMUX_B1_2", - "PSS0_IMUX_B1_3", - "PSS0_IMUX_B1_4", - "PSS0_IMUX_B1_5", - "PSS0_IMUX_B1_6", - "PSS0_IMUX_B1_7", - "PSS0_IMUX_B1_8", - "PSS0_IMUX_B1_9", - "PSS0_IMUX_B20_0", - "PSS0_IMUX_B20_1", - "PSS0_IMUX_B20_10", - "PSS0_IMUX_B20_11", - "PSS0_IMUX_B20_12", - "PSS0_IMUX_B20_13", - "PSS0_IMUX_B20_14", - "PSS0_IMUX_B20_15", - "PSS0_IMUX_B20_16", - "PSS0_IMUX_B20_17", - "PSS0_IMUX_B20_18", - "PSS0_IMUX_B20_19", - "PSS0_IMUX_B20_2", - "PSS0_IMUX_B20_3", - "PSS0_IMUX_B20_4", - "PSS0_IMUX_B20_5", - "PSS0_IMUX_B20_6", - "PSS0_IMUX_B20_7", - "PSS0_IMUX_B20_8", - "PSS0_IMUX_B20_9", - "PSS0_IMUX_B21_0", - "PSS0_IMUX_B21_1", - "PSS0_IMUX_B21_10", - "PSS0_IMUX_B21_11", - "PSS0_IMUX_B21_12", - "PSS0_IMUX_B21_13", - "PSS0_IMUX_B21_14", - "PSS0_IMUX_B21_15", - "PSS0_IMUX_B21_16", - "PSS0_IMUX_B21_17", - "PSS0_IMUX_B21_18", - "PSS0_IMUX_B21_19", - "PSS0_IMUX_B21_2", - "PSS0_IMUX_B21_3", - "PSS0_IMUX_B21_4", - "PSS0_IMUX_B21_5", - "PSS0_IMUX_B21_6", - "PSS0_IMUX_B21_7", - "PSS0_IMUX_B21_8", - "PSS0_IMUX_B21_9", - "PSS0_IMUX_B22_0", - "PSS0_IMUX_B22_1", - "PSS0_IMUX_B22_10", - "PSS0_IMUX_B22_11", - "PSS0_IMUX_B22_12", - "PSS0_IMUX_B22_13", - "PSS0_IMUX_B22_14", - "PSS0_IMUX_B22_15", - "PSS0_IMUX_B22_16", - "PSS0_IMUX_B22_17", - "PSS0_IMUX_B22_18", - "PSS0_IMUX_B22_19", - "PSS0_IMUX_B22_2", - "PSS0_IMUX_B22_3", - "PSS0_IMUX_B22_4", - "PSS0_IMUX_B22_5", - "PSS0_IMUX_B22_6", - "PSS0_IMUX_B22_7", - "PSS0_IMUX_B22_8", - "PSS0_IMUX_B22_9", - "PSS0_IMUX_B23_0", - "PSS0_IMUX_B23_1", - "PSS0_IMUX_B23_10", - "PSS0_IMUX_B23_11", - "PSS0_IMUX_B23_12", - "PSS0_IMUX_B23_13", - "PSS0_IMUX_B23_14", - "PSS0_IMUX_B23_15", - "PSS0_IMUX_B23_16", - "PSS0_IMUX_B23_17", - "PSS0_IMUX_B23_18", - "PSS0_IMUX_B23_19", - "PSS0_IMUX_B23_2", - "PSS0_IMUX_B23_3", - "PSS0_IMUX_B23_4", - "PSS0_IMUX_B23_5", - "PSS0_IMUX_B23_6", - "PSS0_IMUX_B23_7", - "PSS0_IMUX_B23_8", - "PSS0_IMUX_B23_9", - "PSS0_IMUX_B24_0", - "PSS0_IMUX_B24_1", - "PSS0_IMUX_B24_10", - "PSS0_IMUX_B24_11", - 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"PSS0_IMUX_B8_16", - "PSS0_IMUX_B8_17", - "PSS0_IMUX_B8_18", - "PSS0_IMUX_B8_19", - "PSS0_IMUX_B8_2", - "PSS0_IMUX_B8_3", - "PSS0_IMUX_B8_4", - "PSS0_IMUX_B8_5", - "PSS0_IMUX_B8_6", - "PSS0_IMUX_B8_7", - "PSS0_IMUX_B8_8", - "PSS0_IMUX_B8_9", - "PSS0_IMUX_B9_0", - "PSS0_IMUX_B9_1", - "PSS0_IMUX_B9_10", - "PSS0_IMUX_B9_11", - "PSS0_IMUX_B9_12", - "PSS0_IMUX_B9_13", - "PSS0_IMUX_B9_14", - "PSS0_IMUX_B9_15", - "PSS0_IMUX_B9_16", - "PSS0_IMUX_B9_17", - "PSS0_IMUX_B9_18", - "PSS0_IMUX_B9_19", - "PSS0_IMUX_B9_2", - "PSS0_IMUX_B9_3", - "PSS0_IMUX_B9_4", - "PSS0_IMUX_B9_5", - "PSS0_IMUX_B9_6", - "PSS0_IMUX_B9_7", - "PSS0_IMUX_B9_8", - "PSS0_IMUX_B9_9", - "PSS0_LOGIC_OUTS0_0", - "PSS0_LOGIC_OUTS0_1", - "PSS0_LOGIC_OUTS0_10", - "PSS0_LOGIC_OUTS0_11", - "PSS0_LOGIC_OUTS0_12", - "PSS0_LOGIC_OUTS0_13", - "PSS0_LOGIC_OUTS0_14", - "PSS0_LOGIC_OUTS0_15", - "PSS0_LOGIC_OUTS0_16", - "PSS0_LOGIC_OUTS0_17", - "PSS0_LOGIC_OUTS0_18", - "PSS0_LOGIC_OUTS0_19", - "PSS0_LOGIC_OUTS0_2", - "PSS0_LOGIC_OUTS0_3", - "PSS0_LOGIC_OUTS0_4", - "PSS0_LOGIC_OUTS0_5", - "PSS0_LOGIC_OUTS0_6", - "PSS0_LOGIC_OUTS0_7", - "PSS0_LOGIC_OUTS0_8", - "PSS0_LOGIC_OUTS0_9", - "PSS0_LOGIC_OUTS10_0", - "PSS0_LOGIC_OUTS10_1", - "PSS0_LOGIC_OUTS10_10", - "PSS0_LOGIC_OUTS10_11", - "PSS0_LOGIC_OUTS10_12", - "PSS0_LOGIC_OUTS10_13", - "PSS0_LOGIC_OUTS10_14", - "PSS0_LOGIC_OUTS10_15", - "PSS0_LOGIC_OUTS10_16", - "PSS0_LOGIC_OUTS10_17", - "PSS0_LOGIC_OUTS10_18", - "PSS0_LOGIC_OUTS10_19", - "PSS0_LOGIC_OUTS10_2", - "PSS0_LOGIC_OUTS10_3", - "PSS0_LOGIC_OUTS10_4", - "PSS0_LOGIC_OUTS10_5", - "PSS0_LOGIC_OUTS10_6", - "PSS0_LOGIC_OUTS10_7", - "PSS0_LOGIC_OUTS10_8", - "PSS0_LOGIC_OUTS10_9", - "PSS0_LOGIC_OUTS11_0", - "PSS0_LOGIC_OUTS11_1", - "PSS0_LOGIC_OUTS11_10", - "PSS0_LOGIC_OUTS11_11", - "PSS0_LOGIC_OUTS11_12", - "PSS0_LOGIC_OUTS11_13", - "PSS0_LOGIC_OUTS11_14", - "PSS0_LOGIC_OUTS11_15", - "PSS0_LOGIC_OUTS11_16", - "PSS0_LOGIC_OUTS11_17", - "PSS0_LOGIC_OUTS11_18", - "PSS0_LOGIC_OUTS11_19", - "PSS0_LOGIC_OUTS11_2", - "PSS0_LOGIC_OUTS11_3", - "PSS0_LOGIC_OUTS11_4", - "PSS0_LOGIC_OUTS11_5", - "PSS0_LOGIC_OUTS11_6", - "PSS0_LOGIC_OUTS11_7", - "PSS0_LOGIC_OUTS11_8", - "PSS0_LOGIC_OUTS11_9", - "PSS0_LOGIC_OUTS12_0", - "PSS0_LOGIC_OUTS12_1", - "PSS0_LOGIC_OUTS12_10", - "PSS0_LOGIC_OUTS12_11", - "PSS0_LOGIC_OUTS12_12", - "PSS0_LOGIC_OUTS12_13", - "PSS0_LOGIC_OUTS12_14", - "PSS0_LOGIC_OUTS12_15", - "PSS0_LOGIC_OUTS12_16", - "PSS0_LOGIC_OUTS12_17", - "PSS0_LOGIC_OUTS12_18", - "PSS0_LOGIC_OUTS12_19", - "PSS0_LOGIC_OUTS12_2", - "PSS0_LOGIC_OUTS12_3", - "PSS0_LOGIC_OUTS12_4", - "PSS0_LOGIC_OUTS12_5", - "PSS0_LOGIC_OUTS12_6", - "PSS0_LOGIC_OUTS12_7", - "PSS0_LOGIC_OUTS12_8", - "PSS0_LOGIC_OUTS12_9", - "PSS0_LOGIC_OUTS13_0", - "PSS0_LOGIC_OUTS13_1", - "PSS0_LOGIC_OUTS13_10", - "PSS0_LOGIC_OUTS13_11", - "PSS0_LOGIC_OUTS13_12", - "PSS0_LOGIC_OUTS13_13", - "PSS0_LOGIC_OUTS13_14", - "PSS0_LOGIC_OUTS13_15", - "PSS0_LOGIC_OUTS13_16", - "PSS0_LOGIC_OUTS13_17", - "PSS0_LOGIC_OUTS13_18", - "PSS0_LOGIC_OUTS13_19", - "PSS0_LOGIC_OUTS13_2", - "PSS0_LOGIC_OUTS13_3", - "PSS0_LOGIC_OUTS13_4", - "PSS0_LOGIC_OUTS13_5", - "PSS0_LOGIC_OUTS13_6", - "PSS0_LOGIC_OUTS13_7", - "PSS0_LOGIC_OUTS13_8", - "PSS0_LOGIC_OUTS13_9", - "PSS0_LOGIC_OUTS14_0", - "PSS0_LOGIC_OUTS14_1", - "PSS0_LOGIC_OUTS14_10", - "PSS0_LOGIC_OUTS14_11", - "PSS0_LOGIC_OUTS14_12", - "PSS0_LOGIC_OUTS14_13", - "PSS0_LOGIC_OUTS14_14", - "PSS0_LOGIC_OUTS14_15", - "PSS0_LOGIC_OUTS14_16", - "PSS0_LOGIC_OUTS14_17", - "PSS0_LOGIC_OUTS14_18", - "PSS0_LOGIC_OUTS14_19", - "PSS0_LOGIC_OUTS14_2", - "PSS0_LOGIC_OUTS14_3", - "PSS0_LOGIC_OUTS14_4", - "PSS0_LOGIC_OUTS14_5", - "PSS0_LOGIC_OUTS14_6", - "PSS0_LOGIC_OUTS14_7", - "PSS0_LOGIC_OUTS14_8", - "PSS0_LOGIC_OUTS14_9", - "PSS0_LOGIC_OUTS15_0", - "PSS0_LOGIC_OUTS15_1", - "PSS0_LOGIC_OUTS15_10", - "PSS0_LOGIC_OUTS15_11", - "PSS0_LOGIC_OUTS15_12", - "PSS0_LOGIC_OUTS15_13", - "PSS0_LOGIC_OUTS15_14", - "PSS0_LOGIC_OUTS15_15", - "PSS0_LOGIC_OUTS15_16", - "PSS0_LOGIC_OUTS15_17", - "PSS0_LOGIC_OUTS15_18", - "PSS0_LOGIC_OUTS15_19", - "PSS0_LOGIC_OUTS15_2", - "PSS0_LOGIC_OUTS15_3", - "PSS0_LOGIC_OUTS15_4", - "PSS0_LOGIC_OUTS15_5", - "PSS0_LOGIC_OUTS15_6", - "PSS0_LOGIC_OUTS15_7", - "PSS0_LOGIC_OUTS15_8", - "PSS0_LOGIC_OUTS15_9", - "PSS0_LOGIC_OUTS16_0", - "PSS0_LOGIC_OUTS16_1", - "PSS0_LOGIC_OUTS16_10", - "PSS0_LOGIC_OUTS16_11", - "PSS0_LOGIC_OUTS16_12", - "PSS0_LOGIC_OUTS16_13", - "PSS0_LOGIC_OUTS16_14", - "PSS0_LOGIC_OUTS16_15", - "PSS0_LOGIC_OUTS16_16", - "PSS0_LOGIC_OUTS16_17", - "PSS0_LOGIC_OUTS16_18", - "PSS0_LOGIC_OUTS16_19", - "PSS0_LOGIC_OUTS16_2", - "PSS0_LOGIC_OUTS16_3", - "PSS0_LOGIC_OUTS16_4", - "PSS0_LOGIC_OUTS16_5", - "PSS0_LOGIC_OUTS16_6", - "PSS0_LOGIC_OUTS16_7", - "PSS0_LOGIC_OUTS16_8", - "PSS0_LOGIC_OUTS16_9", - "PSS0_LOGIC_OUTS17_0", - "PSS0_LOGIC_OUTS17_1", - "PSS0_LOGIC_OUTS17_10", - "PSS0_LOGIC_OUTS17_11", - "PSS0_LOGIC_OUTS17_12", - "PSS0_LOGIC_OUTS17_13", - "PSS0_LOGIC_OUTS17_14", - "PSS0_LOGIC_OUTS17_15", - "PSS0_LOGIC_OUTS17_16", - "PSS0_LOGIC_OUTS17_17", - "PSS0_LOGIC_OUTS17_18", - "PSS0_LOGIC_OUTS17_19", - "PSS0_LOGIC_OUTS17_2", - "PSS0_LOGIC_OUTS17_3", - "PSS0_LOGIC_OUTS17_4", - "PSS0_LOGIC_OUTS17_5", - "PSS0_LOGIC_OUTS17_6", - "PSS0_LOGIC_OUTS17_7", - "PSS0_LOGIC_OUTS17_8", - "PSS0_LOGIC_OUTS17_9", - "PSS0_LOGIC_OUTS18_0", - "PSS0_LOGIC_OUTS18_1", - "PSS0_LOGIC_OUTS18_10", - "PSS0_LOGIC_OUTS18_11", - "PSS0_LOGIC_OUTS18_12", - "PSS0_LOGIC_OUTS18_13", - "PSS0_LOGIC_OUTS18_14", - "PSS0_LOGIC_OUTS18_15", - "PSS0_LOGIC_OUTS18_16", - "PSS0_LOGIC_OUTS18_17", - "PSS0_LOGIC_OUTS18_18", - "PSS0_LOGIC_OUTS18_19", - "PSS0_LOGIC_OUTS18_2", - "PSS0_LOGIC_OUTS18_3", - "PSS0_LOGIC_OUTS18_4", - "PSS0_LOGIC_OUTS18_5", - "PSS0_LOGIC_OUTS18_6", - "PSS0_LOGIC_OUTS18_7", - "PSS0_LOGIC_OUTS18_8", - "PSS0_LOGIC_OUTS18_9", - "PSS0_LOGIC_OUTS19_0", - "PSS0_LOGIC_OUTS19_1", - "PSS0_LOGIC_OUTS19_10", - "PSS0_LOGIC_OUTS19_11", - "PSS0_LOGIC_OUTS19_12", - "PSS0_LOGIC_OUTS19_13", - "PSS0_LOGIC_OUTS19_14", - "PSS0_LOGIC_OUTS19_15", - "PSS0_LOGIC_OUTS19_16", - "PSS0_LOGIC_OUTS19_17", - "PSS0_LOGIC_OUTS19_18", - "PSS0_LOGIC_OUTS19_19", - "PSS0_LOGIC_OUTS19_2", - "PSS0_LOGIC_OUTS19_3", - "PSS0_LOGIC_OUTS19_4", - "PSS0_LOGIC_OUTS19_5", - "PSS0_LOGIC_OUTS19_6", - "PSS0_LOGIC_OUTS19_7", - "PSS0_LOGIC_OUTS19_8", - "PSS0_LOGIC_OUTS19_9", - "PSS0_LOGIC_OUTS1_0", - "PSS0_LOGIC_OUTS1_1", - "PSS0_LOGIC_OUTS1_10", - "PSS0_LOGIC_OUTS1_11", - "PSS0_LOGIC_OUTS1_12", - "PSS0_LOGIC_OUTS1_13", - "PSS0_LOGIC_OUTS1_14", - "PSS0_LOGIC_OUTS1_15", - "PSS0_LOGIC_OUTS1_16", - "PSS0_LOGIC_OUTS1_17", - "PSS0_LOGIC_OUTS1_18", - "PSS0_LOGIC_OUTS1_19", - "PSS0_LOGIC_OUTS1_2", - "PSS0_LOGIC_OUTS1_3", - "PSS0_LOGIC_OUTS1_4", - "PSS0_LOGIC_OUTS1_5", - "PSS0_LOGIC_OUTS1_6", - "PSS0_LOGIC_OUTS1_7", - "PSS0_LOGIC_OUTS1_8", - "PSS0_LOGIC_OUTS1_9", - "PSS0_LOGIC_OUTS20_0", - "PSS0_LOGIC_OUTS20_1", - "PSS0_LOGIC_OUTS20_10", - "PSS0_LOGIC_OUTS20_11", - "PSS0_LOGIC_OUTS20_12", - "PSS0_LOGIC_OUTS20_13", - "PSS0_LOGIC_OUTS20_14", - "PSS0_LOGIC_OUTS20_15", - "PSS0_LOGIC_OUTS20_16", - "PSS0_LOGIC_OUTS20_17", - "PSS0_LOGIC_OUTS20_18", - "PSS0_LOGIC_OUTS20_19", - "PSS0_LOGIC_OUTS20_2", - "PSS0_LOGIC_OUTS20_3", - "PSS0_LOGIC_OUTS20_4", - "PSS0_LOGIC_OUTS20_5", - "PSS0_LOGIC_OUTS20_6", - "PSS0_LOGIC_OUTS20_7", - "PSS0_LOGIC_OUTS20_8", - "PSS0_LOGIC_OUTS20_9", - "PSS0_LOGIC_OUTS21_0", - "PSS0_LOGIC_OUTS21_1", - "PSS0_LOGIC_OUTS21_10", - "PSS0_LOGIC_OUTS21_11", - "PSS0_LOGIC_OUTS21_12", - "PSS0_LOGIC_OUTS21_13", - "PSS0_LOGIC_OUTS21_14", - "PSS0_LOGIC_OUTS21_15", - "PSS0_LOGIC_OUTS21_16", - "PSS0_LOGIC_OUTS21_17", - "PSS0_LOGIC_OUTS21_18", - "PSS0_LOGIC_OUTS21_19", - "PSS0_LOGIC_OUTS21_2", - "PSS0_LOGIC_OUTS21_3", - "PSS0_LOGIC_OUTS21_4", - "PSS0_LOGIC_OUTS21_5", - "PSS0_LOGIC_OUTS21_6", - "PSS0_LOGIC_OUTS21_7", - "PSS0_LOGIC_OUTS21_8", - "PSS0_LOGIC_OUTS21_9", - "PSS0_LOGIC_OUTS22_0", - "PSS0_LOGIC_OUTS22_1", - "PSS0_LOGIC_OUTS22_10", - "PSS0_LOGIC_OUTS22_11", - "PSS0_LOGIC_OUTS22_12", - "PSS0_LOGIC_OUTS22_13", - "PSS0_LOGIC_OUTS22_14", - "PSS0_LOGIC_OUTS22_15", - "PSS0_LOGIC_OUTS22_16", - "PSS0_LOGIC_OUTS22_17", - "PSS0_LOGIC_OUTS22_18", - "PSS0_LOGIC_OUTS22_19", - "PSS0_LOGIC_OUTS22_2", - "PSS0_LOGIC_OUTS22_3", - "PSS0_LOGIC_OUTS22_4", - "PSS0_LOGIC_OUTS22_5", - "PSS0_LOGIC_OUTS22_6", - "PSS0_LOGIC_OUTS22_7", - "PSS0_LOGIC_OUTS22_8", - "PSS0_LOGIC_OUTS22_9", - "PSS0_LOGIC_OUTS23_0", - "PSS0_LOGIC_OUTS23_1", - "PSS0_LOGIC_OUTS23_10", - "PSS0_LOGIC_OUTS23_11", - "PSS0_LOGIC_OUTS23_12", - "PSS0_LOGIC_OUTS23_13", - "PSS0_LOGIC_OUTS23_14", - "PSS0_LOGIC_OUTS23_15", - "PSS0_LOGIC_OUTS23_16", - "PSS0_LOGIC_OUTS23_17", - "PSS0_LOGIC_OUTS23_18", - "PSS0_LOGIC_OUTS23_19", - "PSS0_LOGIC_OUTS23_2", - "PSS0_LOGIC_OUTS23_3", - "PSS0_LOGIC_OUTS23_4", - "PSS0_LOGIC_OUTS23_5", - "PSS0_LOGIC_OUTS23_6", - "PSS0_LOGIC_OUTS23_7", - "PSS0_LOGIC_OUTS23_8", - "PSS0_LOGIC_OUTS23_9", - "PSS0_LOGIC_OUTS2_0", - "PSS0_LOGIC_OUTS2_1", - "PSS0_LOGIC_OUTS2_10", - "PSS0_LOGIC_OUTS2_11", - "PSS0_LOGIC_OUTS2_12", - "PSS0_LOGIC_OUTS2_13", - "PSS0_LOGIC_OUTS2_14", - "PSS0_LOGIC_OUTS2_15", - "PSS0_LOGIC_OUTS2_16", - "PSS0_LOGIC_OUTS2_17", - "PSS0_LOGIC_OUTS2_18", - "PSS0_LOGIC_OUTS2_19", - "PSS0_LOGIC_OUTS2_2", - "PSS0_LOGIC_OUTS2_3", - "PSS0_LOGIC_OUTS2_4", - "PSS0_LOGIC_OUTS2_5", - "PSS0_LOGIC_OUTS2_6", - "PSS0_LOGIC_OUTS2_7", - "PSS0_LOGIC_OUTS2_8", - "PSS0_LOGIC_OUTS2_9", - "PSS0_LOGIC_OUTS3_0", - "PSS0_LOGIC_OUTS3_1", - "PSS0_LOGIC_OUTS3_10", - "PSS0_LOGIC_OUTS3_11", - "PSS0_LOGIC_OUTS3_12", - "PSS0_LOGIC_OUTS3_13", - "PSS0_LOGIC_OUTS3_14", - "PSS0_LOGIC_OUTS3_15", - "PSS0_LOGIC_OUTS3_16", - "PSS0_LOGIC_OUTS3_17", - "PSS0_LOGIC_OUTS3_18", - "PSS0_LOGIC_OUTS3_19", - "PSS0_LOGIC_OUTS3_2", - "PSS0_LOGIC_OUTS3_3", - "PSS0_LOGIC_OUTS3_4", - "PSS0_LOGIC_OUTS3_5", - "PSS0_LOGIC_OUTS3_6", - "PSS0_LOGIC_OUTS3_7", - "PSS0_LOGIC_OUTS3_8", - "PSS0_LOGIC_OUTS3_9", - "PSS0_LOGIC_OUTS4_0", - "PSS0_LOGIC_OUTS4_1", - "PSS0_LOGIC_OUTS4_10", - "PSS0_LOGIC_OUTS4_11", - "PSS0_LOGIC_OUTS4_12", - "PSS0_LOGIC_OUTS4_13", - "PSS0_LOGIC_OUTS4_14", - "PSS0_LOGIC_OUTS4_15", - "PSS0_LOGIC_OUTS4_16", - "PSS0_LOGIC_OUTS4_17", - "PSS0_LOGIC_OUTS4_18", - "PSS0_LOGIC_OUTS4_19", - "PSS0_LOGIC_OUTS4_2", - "PSS0_LOGIC_OUTS4_3", - "PSS0_LOGIC_OUTS4_4", - "PSS0_LOGIC_OUTS4_5", - "PSS0_LOGIC_OUTS4_6", - "PSS0_LOGIC_OUTS4_7", - "PSS0_LOGIC_OUTS4_8", - "PSS0_LOGIC_OUTS4_9", - "PSS0_LOGIC_OUTS5_0", - "PSS0_LOGIC_OUTS5_1", - "PSS0_LOGIC_OUTS5_10", - "PSS0_LOGIC_OUTS5_11", - "PSS0_LOGIC_OUTS5_12", - "PSS0_LOGIC_OUTS5_13", - "PSS0_LOGIC_OUTS5_14", - "PSS0_LOGIC_OUTS5_15", - "PSS0_LOGIC_OUTS5_16", - "PSS0_LOGIC_OUTS5_17", - "PSS0_LOGIC_OUTS5_18", - "PSS0_LOGIC_OUTS5_19", - "PSS0_LOGIC_OUTS5_2", - "PSS0_LOGIC_OUTS5_3", - "PSS0_LOGIC_OUTS5_4", - "PSS0_LOGIC_OUTS5_5", - "PSS0_LOGIC_OUTS5_6", - "PSS0_LOGIC_OUTS5_7", - "PSS0_LOGIC_OUTS5_8", - "PSS0_LOGIC_OUTS5_9", - "PSS0_LOGIC_OUTS6_0", - "PSS0_LOGIC_OUTS6_1", - "PSS0_LOGIC_OUTS6_10", - "PSS0_LOGIC_OUTS6_11", - "PSS0_LOGIC_OUTS6_12", - "PSS0_LOGIC_OUTS6_13", - "PSS0_LOGIC_OUTS6_14", - "PSS0_LOGIC_OUTS6_15", - "PSS0_LOGIC_OUTS6_16", - "PSS0_LOGIC_OUTS6_17", - "PSS0_LOGIC_OUTS6_18", - "PSS0_LOGIC_OUTS6_19", - "PSS0_LOGIC_OUTS6_2", - "PSS0_LOGIC_OUTS6_3", - "PSS0_LOGIC_OUTS6_4", - "PSS0_LOGIC_OUTS6_5", - "PSS0_LOGIC_OUTS6_6", - "PSS0_LOGIC_OUTS6_7", - "PSS0_LOGIC_OUTS6_8", - "PSS0_LOGIC_OUTS6_9", - "PSS0_LOGIC_OUTS7_0", - "PSS0_LOGIC_OUTS7_1", - "PSS0_LOGIC_OUTS7_10", - "PSS0_LOGIC_OUTS7_11", - "PSS0_LOGIC_OUTS7_12", - "PSS0_LOGIC_OUTS7_13", - "PSS0_LOGIC_OUTS7_14", - "PSS0_LOGIC_OUTS7_15", - "PSS0_LOGIC_OUTS7_16", - "PSS0_LOGIC_OUTS7_17", - "PSS0_LOGIC_OUTS7_18", - "PSS0_LOGIC_OUTS7_19", - "PSS0_LOGIC_OUTS7_2", - "PSS0_LOGIC_OUTS7_3", - "PSS0_LOGIC_OUTS7_4", - "PSS0_LOGIC_OUTS7_5", - "PSS0_LOGIC_OUTS7_6", - "PSS0_LOGIC_OUTS7_7", - "PSS0_LOGIC_OUTS7_8", - "PSS0_LOGIC_OUTS7_9", - "PSS0_LOGIC_OUTS8_0", - "PSS0_LOGIC_OUTS8_1", - "PSS0_LOGIC_OUTS8_10", - "PSS0_LOGIC_OUTS8_11", - "PSS0_LOGIC_OUTS8_12", - "PSS0_LOGIC_OUTS8_13", - "PSS0_LOGIC_OUTS8_14", - "PSS0_LOGIC_OUTS8_15", - "PSS0_LOGIC_OUTS8_16", - "PSS0_LOGIC_OUTS8_17", - "PSS0_LOGIC_OUTS8_18", - "PSS0_LOGIC_OUTS8_19", - "PSS0_LOGIC_OUTS8_2", - "PSS0_LOGIC_OUTS8_3", - "PSS0_LOGIC_OUTS8_4", - "PSS0_LOGIC_OUTS8_5", - "PSS0_LOGIC_OUTS8_6", - "PSS0_LOGIC_OUTS8_7", - "PSS0_LOGIC_OUTS8_8", - "PSS0_LOGIC_OUTS8_9", - "PSS0_LOGIC_OUTS9_0", - "PSS0_LOGIC_OUTS9_1", - "PSS0_LOGIC_OUTS9_10", - "PSS0_LOGIC_OUTS9_11", - "PSS0_LOGIC_OUTS9_12", - "PSS0_LOGIC_OUTS9_13", - "PSS0_LOGIC_OUTS9_14", - "PSS0_LOGIC_OUTS9_15", - "PSS0_LOGIC_OUTS9_16", - "PSS0_LOGIC_OUTS9_17", - "PSS0_LOGIC_OUTS9_18", - "PSS0_LOGIC_OUTS9_19", - "PSS0_LOGIC_OUTS9_2", - "PSS0_LOGIC_OUTS9_3", - "PSS0_LOGIC_OUTS9_4", - "PSS0_LOGIC_OUTS9_5", - "PSS0_LOGIC_OUTS9_6", - "PSS0_LOGIC_OUTS9_7", - "PSS0_LOGIC_OUTS9_8", - "PSS0_LOGIC_OUTS9_9", - "PSS1_CLK_B0_0", - "PSS1_CLK_B0_1", - "PSS1_CLK_B0_10", - "PSS1_CLK_B0_11", - "PSS1_CLK_B0_12", - "PSS1_CLK_B0_13", - "PSS1_CLK_B0_14", - "PSS1_CLK_B0_15", - "PSS1_CLK_B0_16", - "PSS1_CLK_B0_17", - "PSS1_CLK_B0_18", - "PSS1_CLK_B0_19", - "PSS1_CLK_B0_2", - "PSS1_CLK_B0_20", - "PSS1_CLK_B0_21", - "PSS1_CLK_B0_22", - "PSS1_CLK_B0_23", - "PSS1_CLK_B0_24", - "PSS1_CLK_B0_25", - "PSS1_CLK_B0_26", - "PSS1_CLK_B0_27", - "PSS1_CLK_B0_28", - "PSS1_CLK_B0_29", - "PSS1_CLK_B0_3", - "PSS1_CLK_B0_30", - "PSS1_CLK_B0_31", - "PSS1_CLK_B0_32", - "PSS1_CLK_B0_33", - "PSS1_CLK_B0_34", - "PSS1_CLK_B0_35", - "PSS1_CLK_B0_36", - "PSS1_CLK_B0_37", - "PSS1_CLK_B0_38", - "PSS1_CLK_B0_39", - "PSS1_CLK_B0_4", - "PSS1_CLK_B0_5", - "PSS1_CLK_B0_6", - "PSS1_CLK_B0_7", - "PSS1_CLK_B0_8", - "PSS1_CLK_B0_9", - "PSS1_CLK_B1_0", - "PSS1_CLK_B1_1", - "PSS1_CLK_B1_10", - "PSS1_CLK_B1_11", - "PSS1_CLK_B1_12", - "PSS1_CLK_B1_13", - "PSS1_CLK_B1_14", - "PSS1_CLK_B1_15", - "PSS1_CLK_B1_16", - "PSS1_CLK_B1_17", - "PSS1_CLK_B1_18", - "PSS1_CLK_B1_19", - "PSS1_CLK_B1_2", - "PSS1_CLK_B1_20", - "PSS1_CLK_B1_21", - "PSS1_CLK_B1_22", - "PSS1_CLK_B1_23", - "PSS1_CLK_B1_24", - "PSS1_CLK_B1_25", - "PSS1_CLK_B1_26", - "PSS1_CLK_B1_27", - "PSS1_CLK_B1_28", - "PSS1_CLK_B1_29", - "PSS1_CLK_B1_3", - "PSS1_CLK_B1_30", - "PSS1_CLK_B1_31", - "PSS1_CLK_B1_32", - "PSS1_CLK_B1_33", - "PSS1_CLK_B1_34", - "PSS1_CLK_B1_35", - "PSS1_CLK_B1_36", - "PSS1_CLK_B1_37", - "PSS1_CLK_B1_38", - "PSS1_CLK_B1_39", - "PSS1_CLK_B1_4", - "PSS1_CLK_B1_5", - "PSS1_CLK_B1_6", - "PSS1_CLK_B1_7", - "PSS1_CLK_B1_8", - "PSS1_CLK_B1_9", - "PSS1_IMUX_B0_0", - "PSS1_IMUX_B0_1", - "PSS1_IMUX_B0_10", - "PSS1_IMUX_B0_11", - "PSS1_IMUX_B0_12", - "PSS1_IMUX_B0_13", - "PSS1_IMUX_B0_14", - "PSS1_IMUX_B0_15", - "PSS1_IMUX_B0_16", - "PSS1_IMUX_B0_17", - "PSS1_IMUX_B0_18", - "PSS1_IMUX_B0_19", - "PSS1_IMUX_B0_2", - "PSS1_IMUX_B0_20", - "PSS1_IMUX_B0_21", - "PSS1_IMUX_B0_22", - "PSS1_IMUX_B0_23", - "PSS1_IMUX_B0_24", - "PSS1_IMUX_B0_25", - "PSS1_IMUX_B0_26", - "PSS1_IMUX_B0_27", - "PSS1_IMUX_B0_28", - "PSS1_IMUX_B0_29", - "PSS1_IMUX_B0_3", - "PSS1_IMUX_B0_30", - "PSS1_IMUX_B0_31", - "PSS1_IMUX_B0_32", - "PSS1_IMUX_B0_33", - "PSS1_IMUX_B0_34", - "PSS1_IMUX_B0_35", - "PSS1_IMUX_B0_36", - "PSS1_IMUX_B0_37", - "PSS1_IMUX_B0_38", - "PSS1_IMUX_B0_39", - "PSS1_IMUX_B0_4", - "PSS1_IMUX_B0_5", - "PSS1_IMUX_B0_6", - "PSS1_IMUX_B0_7", - "PSS1_IMUX_B0_8", - "PSS1_IMUX_B0_9", - "PSS1_IMUX_B10_0", - "PSS1_IMUX_B10_1", - "PSS1_IMUX_B10_10", - "PSS1_IMUX_B10_11", - "PSS1_IMUX_B10_12", - "PSS1_IMUX_B10_13", - "PSS1_IMUX_B10_14", - "PSS1_IMUX_B10_15", - "PSS1_IMUX_B10_16", - "PSS1_IMUX_B10_17", - "PSS1_IMUX_B10_18", - "PSS1_IMUX_B10_19", - "PSS1_IMUX_B10_2", - "PSS1_IMUX_B10_20", - "PSS1_IMUX_B10_21", - "PSS1_IMUX_B10_22", - "PSS1_IMUX_B10_23", - "PSS1_IMUX_B10_24", - "PSS1_IMUX_B10_25", - "PSS1_IMUX_B10_26", - "PSS1_IMUX_B10_27", - "PSS1_IMUX_B10_28", - "PSS1_IMUX_B10_29", - "PSS1_IMUX_B10_3", - "PSS1_IMUX_B10_30", - "PSS1_IMUX_B10_31", - "PSS1_IMUX_B10_32", - "PSS1_IMUX_B10_33", - "PSS1_IMUX_B10_34", - "PSS1_IMUX_B10_35", - "PSS1_IMUX_B10_36", - "PSS1_IMUX_B10_37", - "PSS1_IMUX_B10_38", - "PSS1_IMUX_B10_39", - "PSS1_IMUX_B10_4", - "PSS1_IMUX_B10_5", - "PSS1_IMUX_B10_6", - "PSS1_IMUX_B10_7", - "PSS1_IMUX_B10_8", - "PSS1_IMUX_B10_9", - "PSS1_IMUX_B11_0", - "PSS1_IMUX_B11_1", - "PSS1_IMUX_B11_10", - "PSS1_IMUX_B11_11", - "PSS1_IMUX_B11_12", - "PSS1_IMUX_B11_13", - "PSS1_IMUX_B11_14", - "PSS1_IMUX_B11_15", - "PSS1_IMUX_B11_16", - "PSS1_IMUX_B11_17", - "PSS1_IMUX_B11_18", - "PSS1_IMUX_B11_19", - "PSS1_IMUX_B11_2", - "PSS1_IMUX_B11_20", - "PSS1_IMUX_B11_21", - "PSS1_IMUX_B11_22", - "PSS1_IMUX_B11_23", - "PSS1_IMUX_B11_24", - "PSS1_IMUX_B11_25", - "PSS1_IMUX_B11_26", - "PSS1_IMUX_B11_27", - "PSS1_IMUX_B11_28", - "PSS1_IMUX_B11_29", - "PSS1_IMUX_B11_3", - "PSS1_IMUX_B11_30", - "PSS1_IMUX_B11_31", - "PSS1_IMUX_B11_32", - "PSS1_IMUX_B11_33", - "PSS1_IMUX_B11_34", - "PSS1_IMUX_B11_35", - "PSS1_IMUX_B11_36", - "PSS1_IMUX_B11_37", - "PSS1_IMUX_B11_38", - "PSS1_IMUX_B11_39", - "PSS1_IMUX_B11_4", - "PSS1_IMUX_B11_5", - "PSS1_IMUX_B11_6", - "PSS1_IMUX_B11_7", - "PSS1_IMUX_B11_8", - "PSS1_IMUX_B11_9", - "PSS1_IMUX_B12_0", - "PSS1_IMUX_B12_1", - "PSS1_IMUX_B12_10", - "PSS1_IMUX_B12_11", - "PSS1_IMUX_B12_12", - "PSS1_IMUX_B12_13", - "PSS1_IMUX_B12_14", - "PSS1_IMUX_B12_15", - "PSS1_IMUX_B12_16", - "PSS1_IMUX_B12_17", - "PSS1_IMUX_B12_18", - "PSS1_IMUX_B12_19", - "PSS1_IMUX_B12_2", - "PSS1_IMUX_B12_20", - "PSS1_IMUX_B12_21", - "PSS1_IMUX_B12_22", - "PSS1_IMUX_B12_23", - "PSS1_IMUX_B12_24", - "PSS1_IMUX_B12_25", - "PSS1_IMUX_B12_26", - "PSS1_IMUX_B12_27", - "PSS1_IMUX_B12_28", - "PSS1_IMUX_B12_29", - "PSS1_IMUX_B12_3", - "PSS1_IMUX_B12_30", - "PSS1_IMUX_B12_31", - "PSS1_IMUX_B12_32", - "PSS1_IMUX_B12_33", - "PSS1_IMUX_B12_34", - "PSS1_IMUX_B12_35", - "PSS1_IMUX_B12_36", - "PSS1_IMUX_B12_37", - "PSS1_IMUX_B12_38", - "PSS1_IMUX_B12_39", - "PSS1_IMUX_B12_4", - "PSS1_IMUX_B12_5", - "PSS1_IMUX_B12_6", - "PSS1_IMUX_B12_7", - "PSS1_IMUX_B12_8", - "PSS1_IMUX_B12_9", - "PSS1_IMUX_B13_0", - "PSS1_IMUX_B13_1", - "PSS1_IMUX_B13_10", - "PSS1_IMUX_B13_11", - "PSS1_IMUX_B13_12", - "PSS1_IMUX_B13_13", - "PSS1_IMUX_B13_14", - "PSS1_IMUX_B13_15", - "PSS1_IMUX_B13_16", - "PSS1_IMUX_B13_17", - "PSS1_IMUX_B13_18", - "PSS1_IMUX_B13_19", - "PSS1_IMUX_B13_2", - "PSS1_IMUX_B13_20", - "PSS1_IMUX_B13_21", - "PSS1_IMUX_B13_22", - "PSS1_IMUX_B13_23", - "PSS1_IMUX_B13_24", - "PSS1_IMUX_B13_25", - "PSS1_IMUX_B13_26", - "PSS1_IMUX_B13_27", - "PSS1_IMUX_B13_28", - "PSS1_IMUX_B13_29", - "PSS1_IMUX_B13_3", - "PSS1_IMUX_B13_30", - "PSS1_IMUX_B13_31", - "PSS1_IMUX_B13_32", - "PSS1_IMUX_B13_33", - "PSS1_IMUX_B13_34", - "PSS1_IMUX_B13_35", - "PSS1_IMUX_B13_36", - "PSS1_IMUX_B13_37", - "PSS1_IMUX_B13_38", - "PSS1_IMUX_B13_39", - "PSS1_IMUX_B13_4", - "PSS1_IMUX_B13_5", - "PSS1_IMUX_B13_6", - "PSS1_IMUX_B13_7", - "PSS1_IMUX_B13_8", - "PSS1_IMUX_B13_9", - "PSS1_IMUX_B14_0", - "PSS1_IMUX_B14_1", - "PSS1_IMUX_B14_10", - "PSS1_IMUX_B14_11", - "PSS1_IMUX_B14_12", - "PSS1_IMUX_B14_13", - "PSS1_IMUX_B14_14", - "PSS1_IMUX_B14_15", - "PSS1_IMUX_B14_16", - "PSS1_IMUX_B14_17", - "PSS1_IMUX_B14_18", - "PSS1_IMUX_B14_19", - "PSS1_IMUX_B14_2", - "PSS1_IMUX_B14_20", - "PSS1_IMUX_B14_21", - "PSS1_IMUX_B14_22", - "PSS1_IMUX_B14_23", - "PSS1_IMUX_B14_24", - "PSS1_IMUX_B14_25", - "PSS1_IMUX_B14_26", - "PSS1_IMUX_B14_27", - "PSS1_IMUX_B14_28", - "PSS1_IMUX_B14_29", - "PSS1_IMUX_B14_3", - "PSS1_IMUX_B14_30", - "PSS1_IMUX_B14_31", - "PSS1_IMUX_B14_32", - "PSS1_IMUX_B14_33", - "PSS1_IMUX_B14_34", - "PSS1_IMUX_B14_35", - "PSS1_IMUX_B14_36", - "PSS1_IMUX_B14_37", - "PSS1_IMUX_B14_38", - "PSS1_IMUX_B14_39", - "PSS1_IMUX_B14_4", - "PSS1_IMUX_B14_5", - "PSS1_IMUX_B14_6", - "PSS1_IMUX_B14_7", - "PSS1_IMUX_B14_8", - "PSS1_IMUX_B14_9", - "PSS1_IMUX_B15_0", - "PSS1_IMUX_B15_1", - "PSS1_IMUX_B15_10", - "PSS1_IMUX_B15_11", - "PSS1_IMUX_B15_12", - "PSS1_IMUX_B15_13", - "PSS1_IMUX_B15_14", - "PSS1_IMUX_B15_15", - "PSS1_IMUX_B15_16", - "PSS1_IMUX_B15_17", - "PSS1_IMUX_B15_18", - "PSS1_IMUX_B15_19", - "PSS1_IMUX_B15_2", - "PSS1_IMUX_B15_20", - "PSS1_IMUX_B15_21", - "PSS1_IMUX_B15_22", - "PSS1_IMUX_B15_23", - "PSS1_IMUX_B15_24", - "PSS1_IMUX_B15_25", - "PSS1_IMUX_B15_26", - "PSS1_IMUX_B15_27", - "PSS1_IMUX_B15_28", - "PSS1_IMUX_B15_29", - "PSS1_IMUX_B15_3", - "PSS1_IMUX_B15_30", - "PSS1_IMUX_B15_31", - "PSS1_IMUX_B15_32", - "PSS1_IMUX_B15_33", - "PSS1_IMUX_B15_34", - "PSS1_IMUX_B15_35", - "PSS1_IMUX_B15_36", - "PSS1_IMUX_B15_37", - "PSS1_IMUX_B15_38", - "PSS1_IMUX_B15_39", - "PSS1_IMUX_B15_4", - "PSS1_IMUX_B15_5", - "PSS1_IMUX_B15_6", - "PSS1_IMUX_B15_7", - "PSS1_IMUX_B15_8", - "PSS1_IMUX_B15_9", - "PSS1_IMUX_B16_0", - "PSS1_IMUX_B16_1", - "PSS1_IMUX_B16_10", - "PSS1_IMUX_B16_11", - "PSS1_IMUX_B16_12", - "PSS1_IMUX_B16_13", - "PSS1_IMUX_B16_14", - "PSS1_IMUX_B16_15", - "PSS1_IMUX_B16_16", - "PSS1_IMUX_B16_17", - "PSS1_IMUX_B16_18", - "PSS1_IMUX_B16_19", - "PSS1_IMUX_B16_2", - "PSS1_IMUX_B16_20", - "PSS1_IMUX_B16_21", - "PSS1_IMUX_B16_22", - "PSS1_IMUX_B16_23", - "PSS1_IMUX_B16_24", - "PSS1_IMUX_B16_25", - "PSS1_IMUX_B16_26", - "PSS1_IMUX_B16_27", - "PSS1_IMUX_B16_28", - "PSS1_IMUX_B16_29", - "PSS1_IMUX_B16_3", - "PSS1_IMUX_B16_30", - "PSS1_IMUX_B16_31", - "PSS1_IMUX_B16_32", - "PSS1_IMUX_B16_33", - "PSS1_IMUX_B16_34", - "PSS1_IMUX_B16_35", - "PSS1_IMUX_B16_36", - "PSS1_IMUX_B16_37", - "PSS1_IMUX_B16_38", - "PSS1_IMUX_B16_39", - "PSS1_IMUX_B16_4", - "PSS1_IMUX_B16_5", - "PSS1_IMUX_B16_6", - "PSS1_IMUX_B16_7", - "PSS1_IMUX_B16_8", - "PSS1_IMUX_B16_9", - "PSS1_IMUX_B17_0", - "PSS1_IMUX_B17_1", - "PSS1_IMUX_B17_10", - "PSS1_IMUX_B17_11", - "PSS1_IMUX_B17_12", - "PSS1_IMUX_B17_13", - "PSS1_IMUX_B17_14", - "PSS1_IMUX_B17_15", - "PSS1_IMUX_B17_16", - "PSS1_IMUX_B17_17", - "PSS1_IMUX_B17_18", - "PSS1_IMUX_B17_19", - "PSS1_IMUX_B17_2", - "PSS1_IMUX_B17_20", - "PSS1_IMUX_B17_21", - "PSS1_IMUX_B17_22", - "PSS1_IMUX_B17_23", - "PSS1_IMUX_B17_24", - "PSS1_IMUX_B17_25", - "PSS1_IMUX_B17_26", - "PSS1_IMUX_B17_27", - "PSS1_IMUX_B17_28", - "PSS1_IMUX_B17_29", - "PSS1_IMUX_B17_3", - "PSS1_IMUX_B17_30", - "PSS1_IMUX_B17_31", - "PSS1_IMUX_B17_32", - "PSS1_IMUX_B17_33", - "PSS1_IMUX_B17_34", - "PSS1_IMUX_B17_35", - "PSS1_IMUX_B17_36", - "PSS1_IMUX_B17_37", - "PSS1_IMUX_B17_38", - "PSS1_IMUX_B17_39", - "PSS1_IMUX_B17_4", - "PSS1_IMUX_B17_5", - "PSS1_IMUX_B17_6", - "PSS1_IMUX_B17_7", - "PSS1_IMUX_B17_8", - "PSS1_IMUX_B17_9", - "PSS1_IMUX_B18_0", - "PSS1_IMUX_B18_1", - "PSS1_IMUX_B18_10", - "PSS1_IMUX_B18_11", - "PSS1_IMUX_B18_12", - "PSS1_IMUX_B18_13", - "PSS1_IMUX_B18_14", - "PSS1_IMUX_B18_15", - "PSS1_IMUX_B18_16", - "PSS1_IMUX_B18_17", - "PSS1_IMUX_B18_18", - "PSS1_IMUX_B18_19", - "PSS1_IMUX_B18_2", - "PSS1_IMUX_B18_20", - "PSS1_IMUX_B18_21", - "PSS1_IMUX_B18_22", - "PSS1_IMUX_B18_23", - "PSS1_IMUX_B18_24", - "PSS1_IMUX_B18_25", - "PSS1_IMUX_B18_26", - "PSS1_IMUX_B18_27", - "PSS1_IMUX_B18_28", - "PSS1_IMUX_B18_29", - "PSS1_IMUX_B18_3", - "PSS1_IMUX_B18_30", - "PSS1_IMUX_B18_31", - "PSS1_IMUX_B18_32", - "PSS1_IMUX_B18_33", - "PSS1_IMUX_B18_34", - "PSS1_IMUX_B18_35", - "PSS1_IMUX_B18_36", - "PSS1_IMUX_B18_37", - "PSS1_IMUX_B18_38", - "PSS1_IMUX_B18_39", - "PSS1_IMUX_B18_4", - "PSS1_IMUX_B18_5", - "PSS1_IMUX_B18_6", - "PSS1_IMUX_B18_7", - "PSS1_IMUX_B18_8", - "PSS1_IMUX_B18_9", - "PSS1_IMUX_B19_0", - "PSS1_IMUX_B19_1", - "PSS1_IMUX_B19_10", - "PSS1_IMUX_B19_11", - "PSS1_IMUX_B19_12", - "PSS1_IMUX_B19_13", - "PSS1_IMUX_B19_14", - "PSS1_IMUX_B19_15", - "PSS1_IMUX_B19_16", - "PSS1_IMUX_B19_17", - "PSS1_IMUX_B19_18", - "PSS1_IMUX_B19_19", - "PSS1_IMUX_B19_2", - "PSS1_IMUX_B19_20", - "PSS1_IMUX_B19_21", - "PSS1_IMUX_B19_22", - "PSS1_IMUX_B19_23", - "PSS1_IMUX_B19_24", - "PSS1_IMUX_B19_25", - "PSS1_IMUX_B19_26", - "PSS1_IMUX_B19_27", - "PSS1_IMUX_B19_28", - "PSS1_IMUX_B19_29", - "PSS1_IMUX_B19_3", - "PSS1_IMUX_B19_30", - "PSS1_IMUX_B19_31", - "PSS1_IMUX_B19_32", - "PSS1_IMUX_B19_33", - "PSS1_IMUX_B19_34", - "PSS1_IMUX_B19_35", - "PSS1_IMUX_B19_36", - "PSS1_IMUX_B19_37", - "PSS1_IMUX_B19_38", - "PSS1_IMUX_B19_39", - "PSS1_IMUX_B19_4", - "PSS1_IMUX_B19_5", - "PSS1_IMUX_B19_6", - "PSS1_IMUX_B19_7", - "PSS1_IMUX_B19_8", - "PSS1_IMUX_B19_9", - "PSS1_IMUX_B1_0", - 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"PSS1_IMUX_B21_21", - "PSS1_IMUX_B21_22", - "PSS1_IMUX_B21_23", - "PSS1_IMUX_B21_24", - "PSS1_IMUX_B21_25", - "PSS1_IMUX_B21_26", - "PSS1_IMUX_B21_27", - "PSS1_IMUX_B21_28", - "PSS1_IMUX_B21_29", - "PSS1_IMUX_B21_3", - "PSS1_IMUX_B21_30", - "PSS1_IMUX_B21_31", - "PSS1_IMUX_B21_32", - "PSS1_IMUX_B21_33", - "PSS1_IMUX_B21_34", - "PSS1_IMUX_B21_35", - "PSS1_IMUX_B21_36", - "PSS1_IMUX_B21_37", - "PSS1_IMUX_B21_38", - "PSS1_IMUX_B21_39", - "PSS1_IMUX_B21_4", - "PSS1_IMUX_B21_5", - "PSS1_IMUX_B21_6", - "PSS1_IMUX_B21_7", - "PSS1_IMUX_B21_8", - "PSS1_IMUX_B21_9", - "PSS1_IMUX_B22_0", - "PSS1_IMUX_B22_1", - "PSS1_IMUX_B22_10", - "PSS1_IMUX_B22_11", - "PSS1_IMUX_B22_12", - "PSS1_IMUX_B22_13", - "PSS1_IMUX_B22_14", - "PSS1_IMUX_B22_15", - "PSS1_IMUX_B22_16", - "PSS1_IMUX_B22_17", - "PSS1_IMUX_B22_18", - "PSS1_IMUX_B22_19", - "PSS1_IMUX_B22_2", - "PSS1_IMUX_B22_20", - "PSS1_IMUX_B22_21", - "PSS1_IMUX_B22_22", - "PSS1_IMUX_B22_23", - "PSS1_IMUX_B22_24", - "PSS1_IMUX_B22_25", - "PSS1_IMUX_B22_26", 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- "PSS1_IMUX_B23_32", - "PSS1_IMUX_B23_33", - "PSS1_IMUX_B23_34", - "PSS1_IMUX_B23_35", - "PSS1_IMUX_B23_36", - "PSS1_IMUX_B23_37", - "PSS1_IMUX_B23_38", - "PSS1_IMUX_B23_39", - "PSS1_IMUX_B23_4", - "PSS1_IMUX_B23_5", - "PSS1_IMUX_B23_6", - "PSS1_IMUX_B23_7", - "PSS1_IMUX_B23_8", - "PSS1_IMUX_B23_9", - "PSS1_IMUX_B24_0", - "PSS1_IMUX_B24_1", - "PSS1_IMUX_B24_10", - "PSS1_IMUX_B24_11", - "PSS1_IMUX_B24_12", - "PSS1_IMUX_B24_13", - "PSS1_IMUX_B24_14", - "PSS1_IMUX_B24_15", - "PSS1_IMUX_B24_16", - "PSS1_IMUX_B24_17", - "PSS1_IMUX_B24_18", - "PSS1_IMUX_B24_19", - "PSS1_IMUX_B24_2", - "PSS1_IMUX_B24_20", - "PSS1_IMUX_B24_21", - "PSS1_IMUX_B24_22", - "PSS1_IMUX_B24_23", - "PSS1_IMUX_B24_24", - "PSS1_IMUX_B24_25", - "PSS1_IMUX_B24_26", - "PSS1_IMUX_B24_27", - "PSS1_IMUX_B24_28", - "PSS1_IMUX_B24_29", - "PSS1_IMUX_B24_3", - "PSS1_IMUX_B24_30", - "PSS1_IMUX_B24_31", - "PSS1_IMUX_B24_32", - "PSS1_IMUX_B24_33", - "PSS1_IMUX_B24_34", - "PSS1_IMUX_B24_35", - "PSS1_IMUX_B24_36", - "PSS1_IMUX_B24_37", - "PSS1_IMUX_B24_38", - "PSS1_IMUX_B24_39", - "PSS1_IMUX_B24_4", - "PSS1_IMUX_B24_5", - "PSS1_IMUX_B24_6", - "PSS1_IMUX_B24_7", - "PSS1_IMUX_B24_8", - "PSS1_IMUX_B24_9", - "PSS1_IMUX_B25_0", - "PSS1_IMUX_B25_1", - "PSS1_IMUX_B25_10", - "PSS1_IMUX_B25_11", - "PSS1_IMUX_B25_12", - "PSS1_IMUX_B25_13", - "PSS1_IMUX_B25_14", - "PSS1_IMUX_B25_15", - "PSS1_IMUX_B25_16", - "PSS1_IMUX_B25_17", - "PSS1_IMUX_B25_18", - "PSS1_IMUX_B25_19", - "PSS1_IMUX_B25_2", - "PSS1_IMUX_B25_20", - "PSS1_IMUX_B25_21", - "PSS1_IMUX_B25_22", - "PSS1_IMUX_B25_23", - "PSS1_IMUX_B25_24", - "PSS1_IMUX_B25_25", - "PSS1_IMUX_B25_26", - "PSS1_IMUX_B25_27", - "PSS1_IMUX_B25_28", - "PSS1_IMUX_B25_29", - "PSS1_IMUX_B25_3", - "PSS1_IMUX_B25_30", - "PSS1_IMUX_B25_31", - "PSS1_IMUX_B25_32", - "PSS1_IMUX_B25_33", - "PSS1_IMUX_B25_34", - "PSS1_IMUX_B25_35", - "PSS1_IMUX_B25_36", - "PSS1_IMUX_B25_37", - "PSS1_IMUX_B25_38", - "PSS1_IMUX_B25_39", - "PSS1_IMUX_B25_4", - "PSS1_IMUX_B25_5", - "PSS1_IMUX_B25_6", - "PSS1_IMUX_B25_7", - "PSS1_IMUX_B25_8", - "PSS1_IMUX_B25_9", - "PSS1_IMUX_B26_0", - "PSS1_IMUX_B26_1", - "PSS1_IMUX_B26_10", - "PSS1_IMUX_B26_11", - "PSS1_IMUX_B26_12", - "PSS1_IMUX_B26_13", - "PSS1_IMUX_B26_14", - "PSS1_IMUX_B26_15", - "PSS1_IMUX_B26_16", - "PSS1_IMUX_B26_17", - "PSS1_IMUX_B26_18", - "PSS1_IMUX_B26_19", - "PSS1_IMUX_B26_2", - "PSS1_IMUX_B26_20", - "PSS1_IMUX_B26_21", - "PSS1_IMUX_B26_22", - "PSS1_IMUX_B26_23", - "PSS1_IMUX_B26_24", - "PSS1_IMUX_B26_25", - "PSS1_IMUX_B26_26", - "PSS1_IMUX_B26_27", - "PSS1_IMUX_B26_28", - "PSS1_IMUX_B26_29", - "PSS1_IMUX_B26_3", - "PSS1_IMUX_B26_30", - "PSS1_IMUX_B26_31", - "PSS1_IMUX_B26_32", - "PSS1_IMUX_B26_33", - "PSS1_IMUX_B26_34", - "PSS1_IMUX_B26_35", - "PSS1_IMUX_B26_36", - "PSS1_IMUX_B26_37", - "PSS1_IMUX_B26_38", - "PSS1_IMUX_B26_39", - "PSS1_IMUX_B26_4", - "PSS1_IMUX_B26_5", - "PSS1_IMUX_B26_6", - "PSS1_IMUX_B26_7", - "PSS1_IMUX_B26_8", - "PSS1_IMUX_B26_9", - "PSS1_IMUX_B27_0", - "PSS1_IMUX_B27_1", - "PSS1_IMUX_B27_10", - "PSS1_IMUX_B27_11", - "PSS1_IMUX_B27_12", - "PSS1_IMUX_B27_13", - "PSS1_IMUX_B27_14", - "PSS1_IMUX_B27_15", - "PSS1_IMUX_B27_16", - "PSS1_IMUX_B27_17", - "PSS1_IMUX_B27_18", - "PSS1_IMUX_B27_19", - "PSS1_IMUX_B27_2", - "PSS1_IMUX_B27_20", - "PSS1_IMUX_B27_21", - "PSS1_IMUX_B27_22", - "PSS1_IMUX_B27_23", - "PSS1_IMUX_B27_24", - "PSS1_IMUX_B27_25", - "PSS1_IMUX_B27_26", - "PSS1_IMUX_B27_27", - "PSS1_IMUX_B27_28", - "PSS1_IMUX_B27_29", - "PSS1_IMUX_B27_3", - "PSS1_IMUX_B27_30", - "PSS1_IMUX_B27_31", - "PSS1_IMUX_B27_32", - "PSS1_IMUX_B27_33", - "PSS1_IMUX_B27_34", - "PSS1_IMUX_B27_35", - "PSS1_IMUX_B27_36", - "PSS1_IMUX_B27_37", - "PSS1_IMUX_B27_38", - "PSS1_IMUX_B27_39", - "PSS1_IMUX_B27_4", - "PSS1_IMUX_B27_5", - "PSS1_IMUX_B27_6", - "PSS1_IMUX_B27_7", - "PSS1_IMUX_B27_8", - "PSS1_IMUX_B27_9", - "PSS1_IMUX_B28_0", - "PSS1_IMUX_B28_1", - "PSS1_IMUX_B28_10", - "PSS1_IMUX_B28_11", - "PSS1_IMUX_B28_12", - "PSS1_IMUX_B28_13", - "PSS1_IMUX_B28_14", - "PSS1_IMUX_B28_15", - "PSS1_IMUX_B28_16", - "PSS1_IMUX_B28_17", - "PSS1_IMUX_B28_18", - "PSS1_IMUX_B28_19", - "PSS1_IMUX_B28_2", - "PSS1_IMUX_B28_20", - "PSS1_IMUX_B28_21", - "PSS1_IMUX_B28_22", - "PSS1_IMUX_B28_23", - "PSS1_IMUX_B28_24", - "PSS1_IMUX_B28_25", - "PSS1_IMUX_B28_26", - "PSS1_IMUX_B28_27", - "PSS1_IMUX_B28_28", - "PSS1_IMUX_B28_29", - "PSS1_IMUX_B28_3", - "PSS1_IMUX_B28_30", - "PSS1_IMUX_B28_31", - "PSS1_IMUX_B28_32", - "PSS1_IMUX_B28_33", - "PSS1_IMUX_B28_34", - "PSS1_IMUX_B28_35", - "PSS1_IMUX_B28_36", - "PSS1_IMUX_B28_37", - "PSS1_IMUX_B28_38", - "PSS1_IMUX_B28_39", - "PSS1_IMUX_B28_4", - "PSS1_IMUX_B28_5", - "PSS1_IMUX_B28_6", - "PSS1_IMUX_B28_7", - "PSS1_IMUX_B28_8", - "PSS1_IMUX_B28_9", - "PSS1_IMUX_B29_0", - "PSS1_IMUX_B29_1", - "PSS1_IMUX_B29_10", - "PSS1_IMUX_B29_11", - "PSS1_IMUX_B29_12", - "PSS1_IMUX_B29_13", - "PSS1_IMUX_B29_14", - "PSS1_IMUX_B29_15", - "PSS1_IMUX_B29_16", - "PSS1_IMUX_B29_17", - "PSS1_IMUX_B29_18", - "PSS1_IMUX_B29_19", - "PSS1_IMUX_B29_2", - "PSS1_IMUX_B29_20", - "PSS1_IMUX_B29_21", - "PSS1_IMUX_B29_22", - "PSS1_IMUX_B29_23", - "PSS1_IMUX_B29_24", - "PSS1_IMUX_B29_25", - "PSS1_IMUX_B29_26", - "PSS1_IMUX_B29_27", - "PSS1_IMUX_B29_28", - "PSS1_IMUX_B29_29", - "PSS1_IMUX_B29_3", - "PSS1_IMUX_B29_30", - "PSS1_IMUX_B29_31", - "PSS1_IMUX_B29_32", - "PSS1_IMUX_B29_33", - "PSS1_IMUX_B29_34", - "PSS1_IMUX_B29_35", - "PSS1_IMUX_B29_36", - "PSS1_IMUX_B29_37", - "PSS1_IMUX_B29_38", - "PSS1_IMUX_B29_39", - "PSS1_IMUX_B29_4", - "PSS1_IMUX_B29_5", - "PSS1_IMUX_B29_6", - "PSS1_IMUX_B29_7", - "PSS1_IMUX_B29_8", - "PSS1_IMUX_B29_9", - "PSS1_IMUX_B2_0", - "PSS1_IMUX_B2_1", - "PSS1_IMUX_B2_10", - "PSS1_IMUX_B2_11", - "PSS1_IMUX_B2_12", - "PSS1_IMUX_B2_13", - "PSS1_IMUX_B2_14", - "PSS1_IMUX_B2_15", - "PSS1_IMUX_B2_16", - "PSS1_IMUX_B2_17", - "PSS1_IMUX_B2_18", - "PSS1_IMUX_B2_19", - "PSS1_IMUX_B2_2", - "PSS1_IMUX_B2_20", - "PSS1_IMUX_B2_21", - "PSS1_IMUX_B2_22", - "PSS1_IMUX_B2_23", - "PSS1_IMUX_B2_24", - "PSS1_IMUX_B2_25", - "PSS1_IMUX_B2_26", - "PSS1_IMUX_B2_27", - "PSS1_IMUX_B2_28", - "PSS1_IMUX_B2_29", - "PSS1_IMUX_B2_3", - "PSS1_IMUX_B2_30", - "PSS1_IMUX_B2_31", - "PSS1_IMUX_B2_32", - "PSS1_IMUX_B2_33", - "PSS1_IMUX_B2_34", - "PSS1_IMUX_B2_35", - "PSS1_IMUX_B2_36", - "PSS1_IMUX_B2_37", - "PSS1_IMUX_B2_38", - "PSS1_IMUX_B2_39", - "PSS1_IMUX_B2_4", - "PSS1_IMUX_B2_5", - "PSS1_IMUX_B2_6", - "PSS1_IMUX_B2_7", - "PSS1_IMUX_B2_8", - "PSS1_IMUX_B2_9", - "PSS1_IMUX_B30_0", - "PSS1_IMUX_B30_1", - "PSS1_IMUX_B30_10", - "PSS1_IMUX_B30_11", - "PSS1_IMUX_B30_12", - "PSS1_IMUX_B30_13", - "PSS1_IMUX_B30_14", - "PSS1_IMUX_B30_15", - "PSS1_IMUX_B30_16", - "PSS1_IMUX_B30_17", - "PSS1_IMUX_B30_18", - "PSS1_IMUX_B30_19", - "PSS1_IMUX_B30_2", - "PSS1_IMUX_B30_20", - "PSS1_IMUX_B30_21", - "PSS1_IMUX_B30_22", - "PSS1_IMUX_B30_23", - "PSS1_IMUX_B30_24", - "PSS1_IMUX_B30_25", - "PSS1_IMUX_B30_26", - "PSS1_IMUX_B30_27", - "PSS1_IMUX_B30_28", - "PSS1_IMUX_B30_29", - "PSS1_IMUX_B30_3", - "PSS1_IMUX_B30_30", - "PSS1_IMUX_B30_31", - "PSS1_IMUX_B30_32", - "PSS1_IMUX_B30_33", - "PSS1_IMUX_B30_34", - "PSS1_IMUX_B30_35", - "PSS1_IMUX_B30_36", - "PSS1_IMUX_B30_37", - "PSS1_IMUX_B30_38", - "PSS1_IMUX_B30_39", - "PSS1_IMUX_B30_4", - "PSS1_IMUX_B30_5", - "PSS1_IMUX_B30_6", - "PSS1_IMUX_B30_7", - "PSS1_IMUX_B30_8", - "PSS1_IMUX_B30_9", - "PSS1_IMUX_B31_0", - "PSS1_IMUX_B31_1", - "PSS1_IMUX_B31_10", - "PSS1_IMUX_B31_11", - "PSS1_IMUX_B31_12", - "PSS1_IMUX_B31_13", - "PSS1_IMUX_B31_14", - "PSS1_IMUX_B31_15", - "PSS1_IMUX_B31_16", - "PSS1_IMUX_B31_17", - "PSS1_IMUX_B31_18", - "PSS1_IMUX_B31_19", - "PSS1_IMUX_B31_2", - "PSS1_IMUX_B31_20", - "PSS1_IMUX_B31_21", - "PSS1_IMUX_B31_22", - "PSS1_IMUX_B31_23", - "PSS1_IMUX_B31_24", - "PSS1_IMUX_B31_25", - "PSS1_IMUX_B31_26", - "PSS1_IMUX_B31_27", - "PSS1_IMUX_B31_28", - "PSS1_IMUX_B31_29", - "PSS1_IMUX_B31_3", - "PSS1_IMUX_B31_30", - "PSS1_IMUX_B31_31", - "PSS1_IMUX_B31_32", - "PSS1_IMUX_B31_33", - "PSS1_IMUX_B31_34", - "PSS1_IMUX_B31_35", - "PSS1_IMUX_B31_36", - "PSS1_IMUX_B31_37", - "PSS1_IMUX_B31_38", - "PSS1_IMUX_B31_39", - "PSS1_IMUX_B31_4", - "PSS1_IMUX_B31_5", - "PSS1_IMUX_B31_6", - "PSS1_IMUX_B31_7", - "PSS1_IMUX_B31_8", - "PSS1_IMUX_B31_9", - "PSS1_IMUX_B32_0", - "PSS1_IMUX_B32_1", - "PSS1_IMUX_B32_10", - "PSS1_IMUX_B32_11", - "PSS1_IMUX_B32_12", - "PSS1_IMUX_B32_13", - "PSS1_IMUX_B32_14", - "PSS1_IMUX_B32_15", - "PSS1_IMUX_B32_16", - "PSS1_IMUX_B32_17", - "PSS1_IMUX_B32_18", - "PSS1_IMUX_B32_19", - "PSS1_IMUX_B32_2", - "PSS1_IMUX_B32_20", - "PSS1_IMUX_B32_21", - "PSS1_IMUX_B32_22", - "PSS1_IMUX_B32_23", - "PSS1_IMUX_B32_24", - "PSS1_IMUX_B32_25", - "PSS1_IMUX_B32_26", - "PSS1_IMUX_B32_27", - "PSS1_IMUX_B32_28", - "PSS1_IMUX_B32_29", - "PSS1_IMUX_B32_3", - "PSS1_IMUX_B32_30", - "PSS1_IMUX_B32_31", - "PSS1_IMUX_B32_32", - "PSS1_IMUX_B32_33", - "PSS1_IMUX_B32_34", - "PSS1_IMUX_B32_35", - "PSS1_IMUX_B32_36", - "PSS1_IMUX_B32_37", - "PSS1_IMUX_B32_38", - "PSS1_IMUX_B32_39", - "PSS1_IMUX_B32_4", - "PSS1_IMUX_B32_5", - "PSS1_IMUX_B32_6", - "PSS1_IMUX_B32_7", - "PSS1_IMUX_B32_8", - "PSS1_IMUX_B32_9", - "PSS1_IMUX_B33_0", - "PSS1_IMUX_B33_1", - "PSS1_IMUX_B33_10", - "PSS1_IMUX_B33_11", - "PSS1_IMUX_B33_12", - "PSS1_IMUX_B33_13", - "PSS1_IMUX_B33_14", - "PSS1_IMUX_B33_15", - "PSS1_IMUX_B33_16", - "PSS1_IMUX_B33_17", - "PSS1_IMUX_B33_18", - "PSS1_IMUX_B33_19", - "PSS1_IMUX_B33_2", - "PSS1_IMUX_B33_20", - "PSS1_IMUX_B33_21", - "PSS1_IMUX_B33_22", - "PSS1_IMUX_B33_23", - "PSS1_IMUX_B33_24", - "PSS1_IMUX_B33_25", - "PSS1_IMUX_B33_26", - "PSS1_IMUX_B33_27", - "PSS1_IMUX_B33_28", - "PSS1_IMUX_B33_29", - "PSS1_IMUX_B33_3", - "PSS1_IMUX_B33_30", - "PSS1_IMUX_B33_31", - "PSS1_IMUX_B33_32", - "PSS1_IMUX_B33_33", - "PSS1_IMUX_B33_34", - "PSS1_IMUX_B33_35", - "PSS1_IMUX_B33_36", - "PSS1_IMUX_B33_37", - "PSS1_IMUX_B33_38", - "PSS1_IMUX_B33_39", - "PSS1_IMUX_B33_4", - "PSS1_IMUX_B33_5", - "PSS1_IMUX_B33_6", - "PSS1_IMUX_B33_7", - "PSS1_IMUX_B33_8", - "PSS1_IMUX_B33_9", - "PSS1_IMUX_B34_0", - "PSS1_IMUX_B34_1", - "PSS1_IMUX_B34_10", - "PSS1_IMUX_B34_11", - "PSS1_IMUX_B34_12", - "PSS1_IMUX_B34_13", - "PSS1_IMUX_B34_14", - "PSS1_IMUX_B34_15", - "PSS1_IMUX_B34_16", - "PSS1_IMUX_B34_17", - "PSS1_IMUX_B34_18", - "PSS1_IMUX_B34_19", - "PSS1_IMUX_B34_2", - "PSS1_IMUX_B34_20", - "PSS1_IMUX_B34_21", - "PSS1_IMUX_B34_22", - "PSS1_IMUX_B34_23", - "PSS1_IMUX_B34_24", - "PSS1_IMUX_B34_25", - "PSS1_IMUX_B34_26", - "PSS1_IMUX_B34_27", - "PSS1_IMUX_B34_28", - "PSS1_IMUX_B34_29", - "PSS1_IMUX_B34_3", - "PSS1_IMUX_B34_30", - "PSS1_IMUX_B34_31", - "PSS1_IMUX_B34_32", - "PSS1_IMUX_B34_33", - "PSS1_IMUX_B34_34", - "PSS1_IMUX_B34_35", - "PSS1_IMUX_B34_36", - "PSS1_IMUX_B34_37", - "PSS1_IMUX_B34_38", - "PSS1_IMUX_B34_39", - "PSS1_IMUX_B34_4", - "PSS1_IMUX_B34_5", - "PSS1_IMUX_B34_6", - "PSS1_IMUX_B34_7", - "PSS1_IMUX_B34_8", - "PSS1_IMUX_B34_9", - "PSS1_IMUX_B35_0", - "PSS1_IMUX_B35_1", - "PSS1_IMUX_B35_10", - "PSS1_IMUX_B35_11", - "PSS1_IMUX_B35_12", - "PSS1_IMUX_B35_13", - "PSS1_IMUX_B35_14", - "PSS1_IMUX_B35_15", - "PSS1_IMUX_B35_16", - "PSS1_IMUX_B35_17", - "PSS1_IMUX_B35_18", - "PSS1_IMUX_B35_19", - "PSS1_IMUX_B35_2", - "PSS1_IMUX_B35_20", - "PSS1_IMUX_B35_21", - "PSS1_IMUX_B35_22", - "PSS1_IMUX_B35_23", - "PSS1_IMUX_B35_24", - "PSS1_IMUX_B35_25", - "PSS1_IMUX_B35_26", - "PSS1_IMUX_B35_27", - "PSS1_IMUX_B35_28", - "PSS1_IMUX_B35_29", - "PSS1_IMUX_B35_3", - "PSS1_IMUX_B35_30", - "PSS1_IMUX_B35_31", - "PSS1_IMUX_B35_32", - "PSS1_IMUX_B35_33", - "PSS1_IMUX_B35_34", - "PSS1_IMUX_B35_35", - "PSS1_IMUX_B35_36", - "PSS1_IMUX_B35_37", - "PSS1_IMUX_B35_38", - "PSS1_IMUX_B35_39", - "PSS1_IMUX_B35_4", - "PSS1_IMUX_B35_5", - "PSS1_IMUX_B35_6", - "PSS1_IMUX_B35_7", - "PSS1_IMUX_B35_8", - "PSS1_IMUX_B35_9", - "PSS1_IMUX_B36_0", - "PSS1_IMUX_B36_1", - "PSS1_IMUX_B36_10", - "PSS1_IMUX_B36_11", - "PSS1_IMUX_B36_12", - "PSS1_IMUX_B36_13", - "PSS1_IMUX_B36_14", - "PSS1_IMUX_B36_15", - "PSS1_IMUX_B36_16", - "PSS1_IMUX_B36_17", - "PSS1_IMUX_B36_18", - "PSS1_IMUX_B36_19", - "PSS1_IMUX_B36_2", - "PSS1_IMUX_B36_20", - "PSS1_IMUX_B36_21", - "PSS1_IMUX_B36_22", - "PSS1_IMUX_B36_23", - "PSS1_IMUX_B36_24", - "PSS1_IMUX_B36_25", - "PSS1_IMUX_B36_26", - "PSS1_IMUX_B36_27", - "PSS1_IMUX_B36_28", - "PSS1_IMUX_B36_29", - "PSS1_IMUX_B36_3", - "PSS1_IMUX_B36_30", - "PSS1_IMUX_B36_31", - "PSS1_IMUX_B36_32", - "PSS1_IMUX_B36_33", - "PSS1_IMUX_B36_34", - "PSS1_IMUX_B36_35", - "PSS1_IMUX_B36_36", - "PSS1_IMUX_B36_37", - "PSS1_IMUX_B36_38", - "PSS1_IMUX_B36_39", - "PSS1_IMUX_B36_4", - "PSS1_IMUX_B36_5", - "PSS1_IMUX_B36_6", - "PSS1_IMUX_B36_7", - "PSS1_IMUX_B36_8", - "PSS1_IMUX_B36_9", - "PSS1_IMUX_B37_0", - "PSS1_IMUX_B37_1", - "PSS1_IMUX_B37_10", - "PSS1_IMUX_B37_11", - "PSS1_IMUX_B37_12", - "PSS1_IMUX_B37_13", - "PSS1_IMUX_B37_14", - "PSS1_IMUX_B37_15", - "PSS1_IMUX_B37_16", - "PSS1_IMUX_B37_17", - "PSS1_IMUX_B37_18", - "PSS1_IMUX_B37_19", - "PSS1_IMUX_B37_2", - "PSS1_IMUX_B37_20", - "PSS1_IMUX_B37_21", - "PSS1_IMUX_B37_22", - "PSS1_IMUX_B37_23", - "PSS1_IMUX_B37_24", - "PSS1_IMUX_B37_25", - "PSS1_IMUX_B37_26", - "PSS1_IMUX_B37_27", - "PSS1_IMUX_B37_28", - "PSS1_IMUX_B37_29", - "PSS1_IMUX_B37_3", - "PSS1_IMUX_B37_30", - "PSS1_IMUX_B37_31", - "PSS1_IMUX_B37_32", - "PSS1_IMUX_B37_33", - "PSS1_IMUX_B37_34", - "PSS1_IMUX_B37_35", - "PSS1_IMUX_B37_36", - "PSS1_IMUX_B37_37", - "PSS1_IMUX_B37_38", - "PSS1_IMUX_B37_39", - "PSS1_IMUX_B37_4", - "PSS1_IMUX_B37_5", - "PSS1_IMUX_B37_6", - "PSS1_IMUX_B37_7", - "PSS1_IMUX_B37_8", - "PSS1_IMUX_B37_9", - "PSS1_IMUX_B38_0", - "PSS1_IMUX_B38_1", - "PSS1_IMUX_B38_10", - "PSS1_IMUX_B38_11", - "PSS1_IMUX_B38_12", - "PSS1_IMUX_B38_13", - "PSS1_IMUX_B38_14", - "PSS1_IMUX_B38_15", - "PSS1_IMUX_B38_16", - "PSS1_IMUX_B38_17", - "PSS1_IMUX_B38_18", - "PSS1_IMUX_B38_19", - "PSS1_IMUX_B38_2", - "PSS1_IMUX_B38_20", - "PSS1_IMUX_B38_21", - "PSS1_IMUX_B38_22", - "PSS1_IMUX_B38_23", - "PSS1_IMUX_B38_24", - "PSS1_IMUX_B38_25", - "PSS1_IMUX_B38_26", - "PSS1_IMUX_B38_27", - "PSS1_IMUX_B38_28", - "PSS1_IMUX_B38_29", - "PSS1_IMUX_B38_3", - "PSS1_IMUX_B38_30", - "PSS1_IMUX_B38_31", - "PSS1_IMUX_B38_32", - "PSS1_IMUX_B38_33", - "PSS1_IMUX_B38_34", - "PSS1_IMUX_B38_35", - "PSS1_IMUX_B38_36", - "PSS1_IMUX_B38_37", - "PSS1_IMUX_B38_38", - "PSS1_IMUX_B38_39", - "PSS1_IMUX_B38_4", - "PSS1_IMUX_B38_5", - "PSS1_IMUX_B38_6", - "PSS1_IMUX_B38_7", - "PSS1_IMUX_B38_8", - "PSS1_IMUX_B38_9", - "PSS1_IMUX_B39_0", - "PSS1_IMUX_B39_1", - "PSS1_IMUX_B39_10", - "PSS1_IMUX_B39_11", - "PSS1_IMUX_B39_12", - "PSS1_IMUX_B39_13", - "PSS1_IMUX_B39_14", - "PSS1_IMUX_B39_15", - "PSS1_IMUX_B39_16", - "PSS1_IMUX_B39_17", - "PSS1_IMUX_B39_18", - "PSS1_IMUX_B39_19", - "PSS1_IMUX_B39_2", - "PSS1_IMUX_B39_20", - "PSS1_IMUX_B39_21", - "PSS1_IMUX_B39_22", - "PSS1_IMUX_B39_23", - "PSS1_IMUX_B39_24", - "PSS1_IMUX_B39_25", - "PSS1_IMUX_B39_26", - "PSS1_IMUX_B39_27", - "PSS1_IMUX_B39_28", - "PSS1_IMUX_B39_29", - "PSS1_IMUX_B39_3", - "PSS1_IMUX_B39_30", - "PSS1_IMUX_B39_31", - "PSS1_IMUX_B39_32", - "PSS1_IMUX_B39_33", - "PSS1_IMUX_B39_34", - "PSS1_IMUX_B39_35", - "PSS1_IMUX_B39_36", - "PSS1_IMUX_B39_37", - "PSS1_IMUX_B39_38", - "PSS1_IMUX_B39_39", - "PSS1_IMUX_B39_4", - "PSS1_IMUX_B39_5", - "PSS1_IMUX_B39_6", - "PSS1_IMUX_B39_7", - "PSS1_IMUX_B39_8", - "PSS1_IMUX_B39_9", - "PSS1_IMUX_B3_0", - "PSS1_IMUX_B3_1", - "PSS1_IMUX_B3_10", - "PSS1_IMUX_B3_11", - "PSS1_IMUX_B3_12", - "PSS1_IMUX_B3_13", - "PSS1_IMUX_B3_14", - "PSS1_IMUX_B3_15", - "PSS1_IMUX_B3_16", - "PSS1_IMUX_B3_17", - "PSS1_IMUX_B3_18", - "PSS1_IMUX_B3_19", - "PSS1_IMUX_B3_2", - "PSS1_IMUX_B3_20", - "PSS1_IMUX_B3_21", - "PSS1_IMUX_B3_22", - "PSS1_IMUX_B3_23", - "PSS1_IMUX_B3_24", - "PSS1_IMUX_B3_25", - "PSS1_IMUX_B3_26", - "PSS1_IMUX_B3_27", - "PSS1_IMUX_B3_28", - "PSS1_IMUX_B3_29", - "PSS1_IMUX_B3_3", - "PSS1_IMUX_B3_30", - "PSS1_IMUX_B3_31", - "PSS1_IMUX_B3_32", - "PSS1_IMUX_B3_33", - "PSS1_IMUX_B3_34", - "PSS1_IMUX_B3_35", - "PSS1_IMUX_B3_36", - "PSS1_IMUX_B3_37", - "PSS1_IMUX_B3_38", - "PSS1_IMUX_B3_39", - "PSS1_IMUX_B3_4", - "PSS1_IMUX_B3_5", - "PSS1_IMUX_B3_6", - "PSS1_IMUX_B3_7", - "PSS1_IMUX_B3_8", - "PSS1_IMUX_B3_9", - "PSS1_IMUX_B40_0", - "PSS1_IMUX_B40_1", - "PSS1_IMUX_B40_10", - "PSS1_IMUX_B40_11", - "PSS1_IMUX_B40_12", - "PSS1_IMUX_B40_13", - "PSS1_IMUX_B40_14", - "PSS1_IMUX_B40_15", - "PSS1_IMUX_B40_16", - "PSS1_IMUX_B40_17", - "PSS1_IMUX_B40_18", - "PSS1_IMUX_B40_19", - "PSS1_IMUX_B40_2", - "PSS1_IMUX_B40_20", - "PSS1_IMUX_B40_21", - "PSS1_IMUX_B40_22", - "PSS1_IMUX_B40_23", - "PSS1_IMUX_B40_24", - "PSS1_IMUX_B40_25", - "PSS1_IMUX_B40_26", - "PSS1_IMUX_B40_27", - "PSS1_IMUX_B40_28", - "PSS1_IMUX_B40_29", - "PSS1_IMUX_B40_3", - "PSS1_IMUX_B40_30", - "PSS1_IMUX_B40_31", - "PSS1_IMUX_B40_32", - "PSS1_IMUX_B40_33", - "PSS1_IMUX_B40_34", - "PSS1_IMUX_B40_35", - "PSS1_IMUX_B40_36", - "PSS1_IMUX_B40_37", - "PSS1_IMUX_B40_38", - "PSS1_IMUX_B40_39", - "PSS1_IMUX_B40_4", - "PSS1_IMUX_B40_5", - "PSS1_IMUX_B40_6", - "PSS1_IMUX_B40_7", - "PSS1_IMUX_B40_8", - "PSS1_IMUX_B40_9", - "PSS1_IMUX_B41_0", - "PSS1_IMUX_B41_1", - "PSS1_IMUX_B41_10", - "PSS1_IMUX_B41_11", - "PSS1_IMUX_B41_12", - "PSS1_IMUX_B41_13", - "PSS1_IMUX_B41_14", - "PSS1_IMUX_B41_15", - "PSS1_IMUX_B41_16", - "PSS1_IMUX_B41_17", - "PSS1_IMUX_B41_18", - "PSS1_IMUX_B41_19", - "PSS1_IMUX_B41_2", - "PSS1_IMUX_B41_20", - "PSS1_IMUX_B41_21", - "PSS1_IMUX_B41_22", - "PSS1_IMUX_B41_23", - "PSS1_IMUX_B41_24", - "PSS1_IMUX_B41_25", - "PSS1_IMUX_B41_26", - "PSS1_IMUX_B41_27", - "PSS1_IMUX_B41_28", - "PSS1_IMUX_B41_29", - "PSS1_IMUX_B41_3", - "PSS1_IMUX_B41_30", - "PSS1_IMUX_B41_31", - "PSS1_IMUX_B41_32", - "PSS1_IMUX_B41_33", - "PSS1_IMUX_B41_34", - "PSS1_IMUX_B41_35", - "PSS1_IMUX_B41_36", - "PSS1_IMUX_B41_37", - "PSS1_IMUX_B41_38", - "PSS1_IMUX_B41_39", - "PSS1_IMUX_B41_4", - "PSS1_IMUX_B41_5", - "PSS1_IMUX_B41_6", - "PSS1_IMUX_B41_7", - "PSS1_IMUX_B41_8", - "PSS1_IMUX_B41_9", - "PSS1_IMUX_B42_0", - "PSS1_IMUX_B42_1", - "PSS1_IMUX_B42_10", - "PSS1_IMUX_B42_11", - "PSS1_IMUX_B42_12", - "PSS1_IMUX_B42_13", - "PSS1_IMUX_B42_14", - "PSS1_IMUX_B42_15", - "PSS1_IMUX_B42_16", - "PSS1_IMUX_B42_17", - "PSS1_IMUX_B42_18", - "PSS1_IMUX_B42_19", - "PSS1_IMUX_B42_2", - "PSS1_IMUX_B42_20", - "PSS1_IMUX_B42_21", - "PSS1_IMUX_B42_22", - "PSS1_IMUX_B42_23", - "PSS1_IMUX_B42_24", - "PSS1_IMUX_B42_25", - "PSS1_IMUX_B42_26", - "PSS1_IMUX_B42_27", - "PSS1_IMUX_B42_28", - "PSS1_IMUX_B42_29", - "PSS1_IMUX_B42_3", - "PSS1_IMUX_B42_30", - "PSS1_IMUX_B42_31", - "PSS1_IMUX_B42_32", - "PSS1_IMUX_B42_33", - "PSS1_IMUX_B42_34", - "PSS1_IMUX_B42_35", - "PSS1_IMUX_B42_36", - "PSS1_IMUX_B42_37", - "PSS1_IMUX_B42_38", - "PSS1_IMUX_B42_39", - "PSS1_IMUX_B42_4", - "PSS1_IMUX_B42_5", - "PSS1_IMUX_B42_6", - "PSS1_IMUX_B42_7", - "PSS1_IMUX_B42_8", - "PSS1_IMUX_B42_9", - "PSS1_IMUX_B43_0", - "PSS1_IMUX_B43_1", - "PSS1_IMUX_B43_10", - "PSS1_IMUX_B43_11", - "PSS1_IMUX_B43_12", - "PSS1_IMUX_B43_13", - "PSS1_IMUX_B43_14", - "PSS1_IMUX_B43_15", - "PSS1_IMUX_B43_16", - "PSS1_IMUX_B43_17", - "PSS1_IMUX_B43_18", - "PSS1_IMUX_B43_19", - "PSS1_IMUX_B43_2", - "PSS1_IMUX_B43_20", - "PSS1_IMUX_B43_21", - "PSS1_IMUX_B43_22", - "PSS1_IMUX_B43_23", - "PSS1_IMUX_B43_24", - "PSS1_IMUX_B43_25", - "PSS1_IMUX_B43_26", - "PSS1_IMUX_B43_27", - "PSS1_IMUX_B43_28", - "PSS1_IMUX_B43_29", - "PSS1_IMUX_B43_3", - "PSS1_IMUX_B43_30", - "PSS1_IMUX_B43_31", - "PSS1_IMUX_B43_32", - "PSS1_IMUX_B43_33", - "PSS1_IMUX_B43_34", - "PSS1_IMUX_B43_35", - "PSS1_IMUX_B43_36", - "PSS1_IMUX_B43_37", - "PSS1_IMUX_B43_38", - "PSS1_IMUX_B43_39", - "PSS1_IMUX_B43_4", - "PSS1_IMUX_B43_5", - "PSS1_IMUX_B43_6", - "PSS1_IMUX_B43_7", - "PSS1_IMUX_B43_8", - "PSS1_IMUX_B43_9", - "PSS1_IMUX_B44_0", - "PSS1_IMUX_B44_1", - "PSS1_IMUX_B44_10", - "PSS1_IMUX_B44_11", - "PSS1_IMUX_B44_12", - "PSS1_IMUX_B44_13", - "PSS1_IMUX_B44_14", - "PSS1_IMUX_B44_15", - "PSS1_IMUX_B44_16", - "PSS1_IMUX_B44_17", - "PSS1_IMUX_B44_18", - "PSS1_IMUX_B44_19", - "PSS1_IMUX_B44_2", - "PSS1_IMUX_B44_20", - "PSS1_IMUX_B44_21", - "PSS1_IMUX_B44_22", - "PSS1_IMUX_B44_23", - "PSS1_IMUX_B44_24", - "PSS1_IMUX_B44_25", - "PSS1_IMUX_B44_26", - "PSS1_IMUX_B44_27", - "PSS1_IMUX_B44_28", - "PSS1_IMUX_B44_29", - "PSS1_IMUX_B44_3", - "PSS1_IMUX_B44_30", - "PSS1_IMUX_B44_31", - "PSS1_IMUX_B44_32", - "PSS1_IMUX_B44_33", - "PSS1_IMUX_B44_34", - "PSS1_IMUX_B44_35", - "PSS1_IMUX_B44_36", - "PSS1_IMUX_B44_37", - "PSS1_IMUX_B44_38", - "PSS1_IMUX_B44_39", - "PSS1_IMUX_B44_4", - "PSS1_IMUX_B44_5", - "PSS1_IMUX_B44_6", - "PSS1_IMUX_B44_7", - "PSS1_IMUX_B44_8", - "PSS1_IMUX_B44_9", - "PSS1_IMUX_B45_0", - "PSS1_IMUX_B45_1", - "PSS1_IMUX_B45_10", - "PSS1_IMUX_B45_11", - "PSS1_IMUX_B45_12", - "PSS1_IMUX_B45_13", - "PSS1_IMUX_B45_14", - "PSS1_IMUX_B45_15", - "PSS1_IMUX_B45_16", - "PSS1_IMUX_B45_17", - "PSS1_IMUX_B45_18", - "PSS1_IMUX_B45_19", - "PSS1_IMUX_B45_2", - "PSS1_IMUX_B45_20", - "PSS1_IMUX_B45_21", - "PSS1_IMUX_B45_22", - "PSS1_IMUX_B45_23", - "PSS1_IMUX_B45_24", - "PSS1_IMUX_B45_25", - "PSS1_IMUX_B45_26", - "PSS1_IMUX_B45_27", - "PSS1_IMUX_B45_28", - "PSS1_IMUX_B45_29", - "PSS1_IMUX_B45_3", - "PSS1_IMUX_B45_30", - "PSS1_IMUX_B45_31", - "PSS1_IMUX_B45_32", - "PSS1_IMUX_B45_33", - "PSS1_IMUX_B45_34", - "PSS1_IMUX_B45_35", - "PSS1_IMUX_B45_36", - "PSS1_IMUX_B45_37", - "PSS1_IMUX_B45_38", - "PSS1_IMUX_B45_39", - "PSS1_IMUX_B45_4", - "PSS1_IMUX_B45_5", - "PSS1_IMUX_B45_6", - "PSS1_IMUX_B45_7", - "PSS1_IMUX_B45_8", - "PSS1_IMUX_B45_9", - "PSS1_IMUX_B46_0", - "PSS1_IMUX_B46_1", - "PSS1_IMUX_B46_10", - "PSS1_IMUX_B46_11", - "PSS1_IMUX_B46_12", - "PSS1_IMUX_B46_13", - "PSS1_IMUX_B46_14", - "PSS1_IMUX_B46_15", - "PSS1_IMUX_B46_16", - "PSS1_IMUX_B46_17", - "PSS1_IMUX_B46_18", - "PSS1_IMUX_B46_19", - "PSS1_IMUX_B46_2", - "PSS1_IMUX_B46_20", - "PSS1_IMUX_B46_21", - "PSS1_IMUX_B46_22", - "PSS1_IMUX_B46_23", - "PSS1_IMUX_B46_24", - "PSS1_IMUX_B46_25", - "PSS1_IMUX_B46_26", - "PSS1_IMUX_B46_27", - "PSS1_IMUX_B46_28", - "PSS1_IMUX_B46_29", - "PSS1_IMUX_B46_3", - "PSS1_IMUX_B46_30", - "PSS1_IMUX_B46_31", - "PSS1_IMUX_B46_32", - "PSS1_IMUX_B46_33", - "PSS1_IMUX_B46_34", - "PSS1_IMUX_B46_35", - "PSS1_IMUX_B46_36", - "PSS1_IMUX_B46_37", - "PSS1_IMUX_B46_38", - "PSS1_IMUX_B46_39", - "PSS1_IMUX_B46_4", - "PSS1_IMUX_B46_5", - "PSS1_IMUX_B46_6", - "PSS1_IMUX_B46_7", - "PSS1_IMUX_B46_8", - "PSS1_IMUX_B46_9", - "PSS1_IMUX_B47_0", - "PSS1_IMUX_B47_1", - "PSS1_IMUX_B47_10", - "PSS1_IMUX_B47_11", - "PSS1_IMUX_B47_12", - "PSS1_IMUX_B47_13", - "PSS1_IMUX_B47_14", - "PSS1_IMUX_B47_15", - "PSS1_IMUX_B47_16", - "PSS1_IMUX_B47_17", - "PSS1_IMUX_B47_18", - "PSS1_IMUX_B47_19", - "PSS1_IMUX_B47_2", - "PSS1_IMUX_B47_20", - "PSS1_IMUX_B47_21", - "PSS1_IMUX_B47_22", - "PSS1_IMUX_B47_23", - "PSS1_IMUX_B47_24", - "PSS1_IMUX_B47_25", - "PSS1_IMUX_B47_26", - "PSS1_IMUX_B47_27", - "PSS1_IMUX_B47_28", - "PSS1_IMUX_B47_29", - "PSS1_IMUX_B47_3", - "PSS1_IMUX_B47_30", - "PSS1_IMUX_B47_31", - "PSS1_IMUX_B47_32", - "PSS1_IMUX_B47_33", - "PSS1_IMUX_B47_34", - "PSS1_IMUX_B47_35", - "PSS1_IMUX_B47_36", - "PSS1_IMUX_B47_37", - "PSS1_IMUX_B47_38", - "PSS1_IMUX_B47_39", - "PSS1_IMUX_B47_4", - "PSS1_IMUX_B47_5", - "PSS1_IMUX_B47_6", - "PSS1_IMUX_B47_7", - "PSS1_IMUX_B47_8", - "PSS1_IMUX_B47_9", - "PSS1_IMUX_B4_0", - "PSS1_IMUX_B4_1", - "PSS1_IMUX_B4_10", - "PSS1_IMUX_B4_11", - "PSS1_IMUX_B4_12", - "PSS1_IMUX_B4_13", - "PSS1_IMUX_B4_14", - "PSS1_IMUX_B4_15", - "PSS1_IMUX_B4_16", - "PSS1_IMUX_B4_17", - "PSS1_IMUX_B4_18", - "PSS1_IMUX_B4_19", - "PSS1_IMUX_B4_2", - "PSS1_IMUX_B4_20", - "PSS1_IMUX_B4_21", - "PSS1_IMUX_B4_22", - "PSS1_IMUX_B4_23", - "PSS1_IMUX_B4_24", - "PSS1_IMUX_B4_25", - "PSS1_IMUX_B4_26", - "PSS1_IMUX_B4_27", - "PSS1_IMUX_B4_28", - "PSS1_IMUX_B4_29", - "PSS1_IMUX_B4_3", - "PSS1_IMUX_B4_30", - "PSS1_IMUX_B4_31", - "PSS1_IMUX_B4_32", - "PSS1_IMUX_B4_33", - "PSS1_IMUX_B4_34", - "PSS1_IMUX_B4_35", - "PSS1_IMUX_B4_36", - "PSS1_IMUX_B4_37", - "PSS1_IMUX_B4_38", - "PSS1_IMUX_B4_39", - "PSS1_IMUX_B4_4", - "PSS1_IMUX_B4_5", - "PSS1_IMUX_B4_6", - "PSS1_IMUX_B4_7", - "PSS1_IMUX_B4_8", - "PSS1_IMUX_B4_9", - "PSS1_IMUX_B5_0", - "PSS1_IMUX_B5_1", - "PSS1_IMUX_B5_10", - "PSS1_IMUX_B5_11", - "PSS1_IMUX_B5_12", - "PSS1_IMUX_B5_13", - "PSS1_IMUX_B5_14", - "PSS1_IMUX_B5_15", - "PSS1_IMUX_B5_16", - "PSS1_IMUX_B5_17", - "PSS1_IMUX_B5_18", - "PSS1_IMUX_B5_19", - "PSS1_IMUX_B5_2", - "PSS1_IMUX_B5_20", - "PSS1_IMUX_B5_21", - "PSS1_IMUX_B5_22", - "PSS1_IMUX_B5_23", - "PSS1_IMUX_B5_24", - "PSS1_IMUX_B5_25", - "PSS1_IMUX_B5_26", - "PSS1_IMUX_B5_27", - "PSS1_IMUX_B5_28", - "PSS1_IMUX_B5_29", - "PSS1_IMUX_B5_3", - "PSS1_IMUX_B5_30", - "PSS1_IMUX_B5_31", - "PSS1_IMUX_B5_32", - "PSS1_IMUX_B5_33", - "PSS1_IMUX_B5_34", - "PSS1_IMUX_B5_35", - "PSS1_IMUX_B5_36", - "PSS1_IMUX_B5_37", - "PSS1_IMUX_B5_38", - "PSS1_IMUX_B5_39", - "PSS1_IMUX_B5_4", - "PSS1_IMUX_B5_5", - "PSS1_IMUX_B5_6", - "PSS1_IMUX_B5_7", - "PSS1_IMUX_B5_8", - "PSS1_IMUX_B5_9", - "PSS1_IMUX_B6_0", - "PSS1_IMUX_B6_1", - "PSS1_IMUX_B6_10", - "PSS1_IMUX_B6_11", - "PSS1_IMUX_B6_12", - "PSS1_IMUX_B6_13", - "PSS1_IMUX_B6_14", - "PSS1_IMUX_B6_15", - "PSS1_IMUX_B6_16", - "PSS1_IMUX_B6_17", - "PSS1_IMUX_B6_18", - "PSS1_IMUX_B6_19", - "PSS1_IMUX_B6_2", - "PSS1_IMUX_B6_20", - "PSS1_IMUX_B6_21", - "PSS1_IMUX_B6_22", - "PSS1_IMUX_B6_23", - "PSS1_IMUX_B6_24", - "PSS1_IMUX_B6_25", - "PSS1_IMUX_B6_26", - "PSS1_IMUX_B6_27", - "PSS1_IMUX_B6_28", - "PSS1_IMUX_B6_29", - "PSS1_IMUX_B6_3", - "PSS1_IMUX_B6_30", - "PSS1_IMUX_B6_31", - "PSS1_IMUX_B6_32", - "PSS1_IMUX_B6_33", - "PSS1_IMUX_B6_34", - "PSS1_IMUX_B6_35", - "PSS1_IMUX_B6_36", - "PSS1_IMUX_B6_37", - "PSS1_IMUX_B6_38", - "PSS1_IMUX_B6_39", - "PSS1_IMUX_B6_4", - "PSS1_IMUX_B6_5", - "PSS1_IMUX_B6_6", - "PSS1_IMUX_B6_7", - "PSS1_IMUX_B6_8", - "PSS1_IMUX_B6_9", - "PSS1_IMUX_B7_0", - "PSS1_IMUX_B7_1", - "PSS1_IMUX_B7_10", - "PSS1_IMUX_B7_11", - "PSS1_IMUX_B7_12", - "PSS1_IMUX_B7_13", - "PSS1_IMUX_B7_14", - "PSS1_IMUX_B7_15", - "PSS1_IMUX_B7_16", - "PSS1_IMUX_B7_17", - "PSS1_IMUX_B7_18", - "PSS1_IMUX_B7_19", - "PSS1_IMUX_B7_2", - "PSS1_IMUX_B7_20", - "PSS1_IMUX_B7_21", - "PSS1_IMUX_B7_22", - "PSS1_IMUX_B7_23", - "PSS1_IMUX_B7_24", - "PSS1_IMUX_B7_25", - "PSS1_IMUX_B7_26", - "PSS1_IMUX_B7_27", - "PSS1_IMUX_B7_28", - "PSS1_IMUX_B7_29", - "PSS1_IMUX_B7_3", - "PSS1_IMUX_B7_30", - "PSS1_IMUX_B7_31", - "PSS1_IMUX_B7_32", - "PSS1_IMUX_B7_33", - "PSS1_IMUX_B7_34", - "PSS1_IMUX_B7_35", - "PSS1_IMUX_B7_36", - "PSS1_IMUX_B7_37", - "PSS1_IMUX_B7_38", - "PSS1_IMUX_B7_39", - "PSS1_IMUX_B7_4", - "PSS1_IMUX_B7_5", - "PSS1_IMUX_B7_6", - "PSS1_IMUX_B7_7", - "PSS1_IMUX_B7_8", - "PSS1_IMUX_B7_9", - "PSS1_IMUX_B8_0", - "PSS1_IMUX_B8_1", - "PSS1_IMUX_B8_10", - "PSS1_IMUX_B8_11", - "PSS1_IMUX_B8_12", - "PSS1_IMUX_B8_13", - "PSS1_IMUX_B8_14", - "PSS1_IMUX_B8_15", - "PSS1_IMUX_B8_16", - "PSS1_IMUX_B8_17", - "PSS1_IMUX_B8_18", - "PSS1_IMUX_B8_19", - "PSS1_IMUX_B8_2", - "PSS1_IMUX_B8_20", - "PSS1_IMUX_B8_21", - "PSS1_IMUX_B8_22", - "PSS1_IMUX_B8_23", - "PSS1_IMUX_B8_24", - "PSS1_IMUX_B8_25", - "PSS1_IMUX_B8_26", - "PSS1_IMUX_B8_27", - "PSS1_IMUX_B8_28", - "PSS1_IMUX_B8_29", - "PSS1_IMUX_B8_3", - "PSS1_IMUX_B8_30", - "PSS1_IMUX_B8_31", - "PSS1_IMUX_B8_32", - "PSS1_IMUX_B8_33", - "PSS1_IMUX_B8_34", - "PSS1_IMUX_B8_35", - "PSS1_IMUX_B8_36", - "PSS1_IMUX_B8_37", - "PSS1_IMUX_B8_38", - "PSS1_IMUX_B8_39", - "PSS1_IMUX_B8_4", - "PSS1_IMUX_B8_5", - "PSS1_IMUX_B8_6", - "PSS1_IMUX_B8_7", - "PSS1_IMUX_B8_8", - "PSS1_IMUX_B8_9", - "PSS1_IMUX_B9_0", - "PSS1_IMUX_B9_1", - "PSS1_IMUX_B9_10", - "PSS1_IMUX_B9_11", - "PSS1_IMUX_B9_12", - "PSS1_IMUX_B9_13", - "PSS1_IMUX_B9_14", - "PSS1_IMUX_B9_15", - "PSS1_IMUX_B9_16", - "PSS1_IMUX_B9_17", - "PSS1_IMUX_B9_18", - "PSS1_IMUX_B9_19", - "PSS1_IMUX_B9_2", - "PSS1_IMUX_B9_20", - "PSS1_IMUX_B9_21", - "PSS1_IMUX_B9_22", - "PSS1_IMUX_B9_23", - "PSS1_IMUX_B9_24", - "PSS1_IMUX_B9_25", - "PSS1_IMUX_B9_26", - "PSS1_IMUX_B9_27", - "PSS1_IMUX_B9_28", - "PSS1_IMUX_B9_29", - "PSS1_IMUX_B9_3", - "PSS1_IMUX_B9_30", - "PSS1_IMUX_B9_31", - "PSS1_IMUX_B9_32", - "PSS1_IMUX_B9_33", - "PSS1_IMUX_B9_34", - "PSS1_IMUX_B9_35", - "PSS1_IMUX_B9_36", - "PSS1_IMUX_B9_37", - "PSS1_IMUX_B9_38", - "PSS1_IMUX_B9_39", - "PSS1_IMUX_B9_4", - "PSS1_IMUX_B9_5", - "PSS1_IMUX_B9_6", - "PSS1_IMUX_B9_7", - "PSS1_IMUX_B9_8", - "PSS1_IMUX_B9_9", - "PSS1_LOGIC_OUTS0_0", - "PSS1_LOGIC_OUTS0_1", - "PSS1_LOGIC_OUTS0_10", - "PSS1_LOGIC_OUTS0_11", - "PSS1_LOGIC_OUTS0_12", - "PSS1_LOGIC_OUTS0_13", - "PSS1_LOGIC_OUTS0_14", - "PSS1_LOGIC_OUTS0_15", - "PSS1_LOGIC_OUTS0_16", - "PSS1_LOGIC_OUTS0_17", - "PSS1_LOGIC_OUTS0_18", - "PSS1_LOGIC_OUTS0_19", - "PSS1_LOGIC_OUTS0_2", - "PSS1_LOGIC_OUTS0_20", - "PSS1_LOGIC_OUTS0_21", - "PSS1_LOGIC_OUTS0_22", - "PSS1_LOGIC_OUTS0_23", - "PSS1_LOGIC_OUTS0_24", - "PSS1_LOGIC_OUTS0_25", - "PSS1_LOGIC_OUTS0_26", - "PSS1_LOGIC_OUTS0_27", - "PSS1_LOGIC_OUTS0_28", - "PSS1_LOGIC_OUTS0_29", - "PSS1_LOGIC_OUTS0_3", - "PSS1_LOGIC_OUTS0_30", - "PSS1_LOGIC_OUTS0_31", - "PSS1_LOGIC_OUTS0_32", - "PSS1_LOGIC_OUTS0_33", - "PSS1_LOGIC_OUTS0_34", - "PSS1_LOGIC_OUTS0_35", - "PSS1_LOGIC_OUTS0_36", - "PSS1_LOGIC_OUTS0_37", - "PSS1_LOGIC_OUTS0_38", - "PSS1_LOGIC_OUTS0_39", - "PSS1_LOGIC_OUTS0_4", - "PSS1_LOGIC_OUTS0_5", - "PSS1_LOGIC_OUTS0_6", - "PSS1_LOGIC_OUTS0_7", - "PSS1_LOGIC_OUTS0_8", - "PSS1_LOGIC_OUTS0_9", - "PSS1_LOGIC_OUTS10_0", - "PSS1_LOGIC_OUTS10_1", - "PSS1_LOGIC_OUTS10_10", - "PSS1_LOGIC_OUTS10_11", - "PSS1_LOGIC_OUTS10_12", - "PSS1_LOGIC_OUTS10_13", - "PSS1_LOGIC_OUTS10_14", - "PSS1_LOGIC_OUTS10_15", - "PSS1_LOGIC_OUTS10_16", - "PSS1_LOGIC_OUTS10_17", - "PSS1_LOGIC_OUTS10_18", - "PSS1_LOGIC_OUTS10_19", - "PSS1_LOGIC_OUTS10_2", - "PSS1_LOGIC_OUTS10_20", - "PSS1_LOGIC_OUTS10_21", - "PSS1_LOGIC_OUTS10_22", - "PSS1_LOGIC_OUTS10_23", - "PSS1_LOGIC_OUTS10_24", - "PSS1_LOGIC_OUTS10_25", - "PSS1_LOGIC_OUTS10_26", - "PSS1_LOGIC_OUTS10_27", - "PSS1_LOGIC_OUTS10_28", - "PSS1_LOGIC_OUTS10_29", - "PSS1_LOGIC_OUTS10_3", - "PSS1_LOGIC_OUTS10_30", - "PSS1_LOGIC_OUTS10_31", - "PSS1_LOGIC_OUTS10_32", - "PSS1_LOGIC_OUTS10_33", - "PSS1_LOGIC_OUTS10_34", - "PSS1_LOGIC_OUTS10_35", - "PSS1_LOGIC_OUTS10_36", - "PSS1_LOGIC_OUTS10_37", - "PSS1_LOGIC_OUTS10_38", - "PSS1_LOGIC_OUTS10_39", - "PSS1_LOGIC_OUTS10_4", - "PSS1_LOGIC_OUTS10_5", - "PSS1_LOGIC_OUTS10_6", - "PSS1_LOGIC_OUTS10_7", - "PSS1_LOGIC_OUTS10_8", - "PSS1_LOGIC_OUTS10_9", - "PSS1_LOGIC_OUTS11_0", - "PSS1_LOGIC_OUTS11_1", - "PSS1_LOGIC_OUTS11_10", - "PSS1_LOGIC_OUTS11_11", - "PSS1_LOGIC_OUTS11_12", - "PSS1_LOGIC_OUTS11_13", - "PSS1_LOGIC_OUTS11_14", - "PSS1_LOGIC_OUTS11_15", - "PSS1_LOGIC_OUTS11_16", - "PSS1_LOGIC_OUTS11_17", - "PSS1_LOGIC_OUTS11_18", - "PSS1_LOGIC_OUTS11_19", - "PSS1_LOGIC_OUTS11_2", - "PSS1_LOGIC_OUTS11_20", - "PSS1_LOGIC_OUTS11_21", - "PSS1_LOGIC_OUTS11_22", - "PSS1_LOGIC_OUTS11_23", - "PSS1_LOGIC_OUTS11_24", - "PSS1_LOGIC_OUTS11_25", - "PSS1_LOGIC_OUTS11_26", - "PSS1_LOGIC_OUTS11_27", - "PSS1_LOGIC_OUTS11_28", - "PSS1_LOGIC_OUTS11_29", - "PSS1_LOGIC_OUTS11_3", - "PSS1_LOGIC_OUTS11_30", - "PSS1_LOGIC_OUTS11_31", - "PSS1_LOGIC_OUTS11_32", - "PSS1_LOGIC_OUTS11_33", - "PSS1_LOGIC_OUTS11_34", - "PSS1_LOGIC_OUTS11_35", - "PSS1_LOGIC_OUTS11_36", - "PSS1_LOGIC_OUTS11_37", - "PSS1_LOGIC_OUTS11_38", - "PSS1_LOGIC_OUTS11_39", - "PSS1_LOGIC_OUTS11_4", - "PSS1_LOGIC_OUTS11_5", - "PSS1_LOGIC_OUTS11_6", - "PSS1_LOGIC_OUTS11_7", - "PSS1_LOGIC_OUTS11_8", - "PSS1_LOGIC_OUTS11_9", - "PSS1_LOGIC_OUTS12_0", - "PSS1_LOGIC_OUTS12_1", - "PSS1_LOGIC_OUTS12_10", - "PSS1_LOGIC_OUTS12_11", - "PSS1_LOGIC_OUTS12_12", - "PSS1_LOGIC_OUTS12_13", - "PSS1_LOGIC_OUTS12_14", - "PSS1_LOGIC_OUTS12_15", - "PSS1_LOGIC_OUTS12_16", - "PSS1_LOGIC_OUTS12_17", - "PSS1_LOGIC_OUTS12_18", - "PSS1_LOGIC_OUTS12_19", - "PSS1_LOGIC_OUTS12_2", - "PSS1_LOGIC_OUTS12_20", - "PSS1_LOGIC_OUTS12_21", - "PSS1_LOGIC_OUTS12_22", - "PSS1_LOGIC_OUTS12_23", - "PSS1_LOGIC_OUTS12_24", - "PSS1_LOGIC_OUTS12_25", - "PSS1_LOGIC_OUTS12_26", - "PSS1_LOGIC_OUTS12_27", - "PSS1_LOGIC_OUTS12_28", - "PSS1_LOGIC_OUTS12_29", - "PSS1_LOGIC_OUTS12_3", - "PSS1_LOGIC_OUTS12_30", - "PSS1_LOGIC_OUTS12_31", - "PSS1_LOGIC_OUTS12_32", - "PSS1_LOGIC_OUTS12_33", - "PSS1_LOGIC_OUTS12_34", - "PSS1_LOGIC_OUTS12_35", - "PSS1_LOGIC_OUTS12_36", - "PSS1_LOGIC_OUTS12_37", - "PSS1_LOGIC_OUTS12_38", - "PSS1_LOGIC_OUTS12_39", - "PSS1_LOGIC_OUTS12_4", - "PSS1_LOGIC_OUTS12_5", - "PSS1_LOGIC_OUTS12_6", - "PSS1_LOGIC_OUTS12_7", - "PSS1_LOGIC_OUTS12_8", - "PSS1_LOGIC_OUTS12_9", - "PSS1_LOGIC_OUTS13_0", - "PSS1_LOGIC_OUTS13_1", - "PSS1_LOGIC_OUTS13_10", - "PSS1_LOGIC_OUTS13_11", - "PSS1_LOGIC_OUTS13_12", - "PSS1_LOGIC_OUTS13_13", - "PSS1_LOGIC_OUTS13_14", - "PSS1_LOGIC_OUTS13_15", - "PSS1_LOGIC_OUTS13_16", - "PSS1_LOGIC_OUTS13_17", - "PSS1_LOGIC_OUTS13_18", - "PSS1_LOGIC_OUTS13_19", - "PSS1_LOGIC_OUTS13_2", - "PSS1_LOGIC_OUTS13_20", - "PSS1_LOGIC_OUTS13_21", - "PSS1_LOGIC_OUTS13_22", - "PSS1_LOGIC_OUTS13_23", - "PSS1_LOGIC_OUTS13_24", - "PSS1_LOGIC_OUTS13_25", - "PSS1_LOGIC_OUTS13_26", - "PSS1_LOGIC_OUTS13_27", - "PSS1_LOGIC_OUTS13_28", - "PSS1_LOGIC_OUTS13_29", - "PSS1_LOGIC_OUTS13_3", - "PSS1_LOGIC_OUTS13_30", - "PSS1_LOGIC_OUTS13_31", - "PSS1_LOGIC_OUTS13_32", - "PSS1_LOGIC_OUTS13_33", - "PSS1_LOGIC_OUTS13_34", - "PSS1_LOGIC_OUTS13_35", - "PSS1_LOGIC_OUTS13_36", - "PSS1_LOGIC_OUTS13_37", - "PSS1_LOGIC_OUTS13_38", - "PSS1_LOGIC_OUTS13_39", - "PSS1_LOGIC_OUTS13_4", - "PSS1_LOGIC_OUTS13_5", - "PSS1_LOGIC_OUTS13_6", - "PSS1_LOGIC_OUTS13_7", - "PSS1_LOGIC_OUTS13_8", - "PSS1_LOGIC_OUTS13_9", - "PSS1_LOGIC_OUTS14_0", - "PSS1_LOGIC_OUTS14_1", - "PSS1_LOGIC_OUTS14_10", - "PSS1_LOGIC_OUTS14_11", - "PSS1_LOGIC_OUTS14_12", - "PSS1_LOGIC_OUTS14_13", - "PSS1_LOGIC_OUTS14_14", - "PSS1_LOGIC_OUTS14_15", - "PSS1_LOGIC_OUTS14_16", - "PSS1_LOGIC_OUTS14_17", - "PSS1_LOGIC_OUTS14_18", - "PSS1_LOGIC_OUTS14_19", - "PSS1_LOGIC_OUTS14_2", - "PSS1_LOGIC_OUTS14_20", - "PSS1_LOGIC_OUTS14_21", - "PSS1_LOGIC_OUTS14_22", - "PSS1_LOGIC_OUTS14_23", - "PSS1_LOGIC_OUTS14_24", - "PSS1_LOGIC_OUTS14_25", - "PSS1_LOGIC_OUTS14_26", - "PSS1_LOGIC_OUTS14_27", - "PSS1_LOGIC_OUTS14_28", - "PSS1_LOGIC_OUTS14_29", - "PSS1_LOGIC_OUTS14_3", - "PSS1_LOGIC_OUTS14_30", - "PSS1_LOGIC_OUTS14_31", - "PSS1_LOGIC_OUTS14_32", - "PSS1_LOGIC_OUTS14_33", - "PSS1_LOGIC_OUTS14_34", - "PSS1_LOGIC_OUTS14_35", - "PSS1_LOGIC_OUTS14_36", - "PSS1_LOGIC_OUTS14_37", - "PSS1_LOGIC_OUTS14_38", - "PSS1_LOGIC_OUTS14_39", - "PSS1_LOGIC_OUTS14_4", - "PSS1_LOGIC_OUTS14_5", - "PSS1_LOGIC_OUTS14_6", - "PSS1_LOGIC_OUTS14_7", - "PSS1_LOGIC_OUTS14_8", - "PSS1_LOGIC_OUTS14_9", - "PSS1_LOGIC_OUTS15_0", - "PSS1_LOGIC_OUTS15_1", - "PSS1_LOGIC_OUTS15_10", - "PSS1_LOGIC_OUTS15_11", - "PSS1_LOGIC_OUTS15_12", - "PSS1_LOGIC_OUTS15_13", - "PSS1_LOGIC_OUTS15_14", - "PSS1_LOGIC_OUTS15_15", - "PSS1_LOGIC_OUTS15_16", - "PSS1_LOGIC_OUTS15_17", - "PSS1_LOGIC_OUTS15_18", - "PSS1_LOGIC_OUTS15_19", - "PSS1_LOGIC_OUTS15_2", - "PSS1_LOGIC_OUTS15_20", - "PSS1_LOGIC_OUTS15_21", - "PSS1_LOGIC_OUTS15_22", - "PSS1_LOGIC_OUTS15_23", - "PSS1_LOGIC_OUTS15_24", - "PSS1_LOGIC_OUTS15_25", - "PSS1_LOGIC_OUTS15_26", - "PSS1_LOGIC_OUTS15_27", - "PSS1_LOGIC_OUTS15_28", - "PSS1_LOGIC_OUTS15_29", - "PSS1_LOGIC_OUTS15_3", - "PSS1_LOGIC_OUTS15_30", - "PSS1_LOGIC_OUTS15_31", - "PSS1_LOGIC_OUTS15_32", - "PSS1_LOGIC_OUTS15_33", - "PSS1_LOGIC_OUTS15_34", - "PSS1_LOGIC_OUTS15_35", - "PSS1_LOGIC_OUTS15_36", - "PSS1_LOGIC_OUTS15_37", - "PSS1_LOGIC_OUTS15_38", - "PSS1_LOGIC_OUTS15_39", - "PSS1_LOGIC_OUTS15_4", - "PSS1_LOGIC_OUTS15_5", - "PSS1_LOGIC_OUTS15_6", - "PSS1_LOGIC_OUTS15_7", - "PSS1_LOGIC_OUTS15_8", - "PSS1_LOGIC_OUTS15_9", - "PSS1_LOGIC_OUTS16_0", - "PSS1_LOGIC_OUTS16_1", - "PSS1_LOGIC_OUTS16_10", - "PSS1_LOGIC_OUTS16_11", - "PSS1_LOGIC_OUTS16_12", - "PSS1_LOGIC_OUTS16_13", - "PSS1_LOGIC_OUTS16_14", - "PSS1_LOGIC_OUTS16_15", - "PSS1_LOGIC_OUTS16_16", - "PSS1_LOGIC_OUTS16_17", - "PSS1_LOGIC_OUTS16_18", - "PSS1_LOGIC_OUTS16_19", - "PSS1_LOGIC_OUTS16_2", - "PSS1_LOGIC_OUTS16_20", - "PSS1_LOGIC_OUTS16_21", - "PSS1_LOGIC_OUTS16_22", - "PSS1_LOGIC_OUTS16_23", - "PSS1_LOGIC_OUTS16_24", - "PSS1_LOGIC_OUTS16_25", - "PSS1_LOGIC_OUTS16_26", - "PSS1_LOGIC_OUTS16_27", - "PSS1_LOGIC_OUTS16_28", - "PSS1_LOGIC_OUTS16_29", - "PSS1_LOGIC_OUTS16_3", - "PSS1_LOGIC_OUTS16_30", - "PSS1_LOGIC_OUTS16_31", - "PSS1_LOGIC_OUTS16_32", - "PSS1_LOGIC_OUTS16_33", - "PSS1_LOGIC_OUTS16_34", - "PSS1_LOGIC_OUTS16_35", - "PSS1_LOGIC_OUTS16_36", - "PSS1_LOGIC_OUTS16_37", - "PSS1_LOGIC_OUTS16_38", - "PSS1_LOGIC_OUTS16_39", - "PSS1_LOGIC_OUTS16_4", - "PSS1_LOGIC_OUTS16_5", - "PSS1_LOGIC_OUTS16_6", - "PSS1_LOGIC_OUTS16_7", - "PSS1_LOGIC_OUTS16_8", - "PSS1_LOGIC_OUTS16_9", - "PSS1_LOGIC_OUTS17_0", - "PSS1_LOGIC_OUTS17_1", - "PSS1_LOGIC_OUTS17_10", - "PSS1_LOGIC_OUTS17_11", - "PSS1_LOGIC_OUTS17_12", - "PSS1_LOGIC_OUTS17_13", - "PSS1_LOGIC_OUTS17_14", - "PSS1_LOGIC_OUTS17_15", - "PSS1_LOGIC_OUTS17_16", - "PSS1_LOGIC_OUTS17_17", - "PSS1_LOGIC_OUTS17_18", - "PSS1_LOGIC_OUTS17_19", - "PSS1_LOGIC_OUTS17_2", - "PSS1_LOGIC_OUTS17_20", - "PSS1_LOGIC_OUTS17_21", - "PSS1_LOGIC_OUTS17_22", - "PSS1_LOGIC_OUTS17_23", - "PSS1_LOGIC_OUTS17_24", - "PSS1_LOGIC_OUTS17_25", - "PSS1_LOGIC_OUTS17_26", - "PSS1_LOGIC_OUTS17_27", - "PSS1_LOGIC_OUTS17_28", - "PSS1_LOGIC_OUTS17_29", - "PSS1_LOGIC_OUTS17_3", - "PSS1_LOGIC_OUTS17_30", - "PSS1_LOGIC_OUTS17_31", - "PSS1_LOGIC_OUTS17_32", - "PSS1_LOGIC_OUTS17_33", - "PSS1_LOGIC_OUTS17_34", - "PSS1_LOGIC_OUTS17_35", - "PSS1_LOGIC_OUTS17_36", - "PSS1_LOGIC_OUTS17_37", - "PSS1_LOGIC_OUTS17_38", - "PSS1_LOGIC_OUTS17_39", - "PSS1_LOGIC_OUTS17_4", - "PSS1_LOGIC_OUTS17_5", - "PSS1_LOGIC_OUTS17_6", - "PSS1_LOGIC_OUTS17_7", - "PSS1_LOGIC_OUTS17_8", - "PSS1_LOGIC_OUTS17_9", - "PSS1_LOGIC_OUTS18_0", - "PSS1_LOGIC_OUTS18_1", - "PSS1_LOGIC_OUTS18_10", - "PSS1_LOGIC_OUTS18_11", - "PSS1_LOGIC_OUTS18_12", - "PSS1_LOGIC_OUTS18_13", - "PSS1_LOGIC_OUTS18_14", - "PSS1_LOGIC_OUTS18_15", - "PSS1_LOGIC_OUTS18_16", - "PSS1_LOGIC_OUTS18_17", - "PSS1_LOGIC_OUTS18_18", - "PSS1_LOGIC_OUTS18_19", - "PSS1_LOGIC_OUTS18_2", - "PSS1_LOGIC_OUTS18_20", - "PSS1_LOGIC_OUTS18_21", - "PSS1_LOGIC_OUTS18_22", - "PSS1_LOGIC_OUTS18_23", - "PSS1_LOGIC_OUTS18_24", - "PSS1_LOGIC_OUTS18_25", - "PSS1_LOGIC_OUTS18_26", - "PSS1_LOGIC_OUTS18_27", - "PSS1_LOGIC_OUTS18_28", - "PSS1_LOGIC_OUTS18_29", - "PSS1_LOGIC_OUTS18_3", - "PSS1_LOGIC_OUTS18_30", - "PSS1_LOGIC_OUTS18_31", - "PSS1_LOGIC_OUTS18_32", - "PSS1_LOGIC_OUTS18_33", - "PSS1_LOGIC_OUTS18_34", - "PSS1_LOGIC_OUTS18_35", - "PSS1_LOGIC_OUTS18_36", - "PSS1_LOGIC_OUTS18_37", - "PSS1_LOGIC_OUTS18_38", - "PSS1_LOGIC_OUTS18_39", - "PSS1_LOGIC_OUTS18_4", - "PSS1_LOGIC_OUTS18_5", - "PSS1_LOGIC_OUTS18_6", - "PSS1_LOGIC_OUTS18_7", - "PSS1_LOGIC_OUTS18_8", - "PSS1_LOGIC_OUTS18_9", - "PSS1_LOGIC_OUTS19_0", - "PSS1_LOGIC_OUTS19_1", - "PSS1_LOGIC_OUTS19_10", - "PSS1_LOGIC_OUTS19_11", - "PSS1_LOGIC_OUTS19_12", - "PSS1_LOGIC_OUTS19_13", - "PSS1_LOGIC_OUTS19_14", - "PSS1_LOGIC_OUTS19_15", - "PSS1_LOGIC_OUTS19_16", - "PSS1_LOGIC_OUTS19_17", - "PSS1_LOGIC_OUTS19_18", - "PSS1_LOGIC_OUTS19_19", - "PSS1_LOGIC_OUTS19_2", - "PSS1_LOGIC_OUTS19_20", - "PSS1_LOGIC_OUTS19_21", - "PSS1_LOGIC_OUTS19_22", - "PSS1_LOGIC_OUTS19_23", - "PSS1_LOGIC_OUTS19_24", - "PSS1_LOGIC_OUTS19_25", - "PSS1_LOGIC_OUTS19_26", - "PSS1_LOGIC_OUTS19_27", - "PSS1_LOGIC_OUTS19_28", - "PSS1_LOGIC_OUTS19_29", - "PSS1_LOGIC_OUTS19_3", - "PSS1_LOGIC_OUTS19_30", - "PSS1_LOGIC_OUTS19_31", - "PSS1_LOGIC_OUTS19_32", - "PSS1_LOGIC_OUTS19_33", - "PSS1_LOGIC_OUTS19_34", - "PSS1_LOGIC_OUTS19_35", - "PSS1_LOGIC_OUTS19_36", - "PSS1_LOGIC_OUTS19_37", - "PSS1_LOGIC_OUTS19_38", - "PSS1_LOGIC_OUTS19_39", - "PSS1_LOGIC_OUTS19_4", - "PSS1_LOGIC_OUTS19_5", - "PSS1_LOGIC_OUTS19_6", - "PSS1_LOGIC_OUTS19_7", - "PSS1_LOGIC_OUTS19_8", - "PSS1_LOGIC_OUTS19_9", - "PSS1_LOGIC_OUTS1_0", - "PSS1_LOGIC_OUTS1_1", - "PSS1_LOGIC_OUTS1_10", - "PSS1_LOGIC_OUTS1_11", - "PSS1_LOGIC_OUTS1_12", - "PSS1_LOGIC_OUTS1_13", - "PSS1_LOGIC_OUTS1_14", - "PSS1_LOGIC_OUTS1_15", - "PSS1_LOGIC_OUTS1_16", - "PSS1_LOGIC_OUTS1_17", - "PSS1_LOGIC_OUTS1_18", - "PSS1_LOGIC_OUTS1_19", - "PSS1_LOGIC_OUTS1_2", - "PSS1_LOGIC_OUTS1_20", - "PSS1_LOGIC_OUTS1_21", - "PSS1_LOGIC_OUTS1_22", - "PSS1_LOGIC_OUTS1_23", - "PSS1_LOGIC_OUTS1_24", - "PSS1_LOGIC_OUTS1_25", - "PSS1_LOGIC_OUTS1_26", - "PSS1_LOGIC_OUTS1_27", - "PSS1_LOGIC_OUTS1_28", - "PSS1_LOGIC_OUTS1_29", - "PSS1_LOGIC_OUTS1_3", - "PSS1_LOGIC_OUTS1_30", - "PSS1_LOGIC_OUTS1_31", - "PSS1_LOGIC_OUTS1_32", - "PSS1_LOGIC_OUTS1_33", - "PSS1_LOGIC_OUTS1_34", - "PSS1_LOGIC_OUTS1_35", - "PSS1_LOGIC_OUTS1_36", - "PSS1_LOGIC_OUTS1_37", - "PSS1_LOGIC_OUTS1_38", - "PSS1_LOGIC_OUTS1_39", - "PSS1_LOGIC_OUTS1_4", - "PSS1_LOGIC_OUTS1_5", - "PSS1_LOGIC_OUTS1_6", - "PSS1_LOGIC_OUTS1_7", - "PSS1_LOGIC_OUTS1_8", - "PSS1_LOGIC_OUTS1_9", - "PSS1_LOGIC_OUTS20_0", - "PSS1_LOGIC_OUTS20_1", - "PSS1_LOGIC_OUTS20_10", - "PSS1_LOGIC_OUTS20_11", - "PSS1_LOGIC_OUTS20_12", - "PSS1_LOGIC_OUTS20_13", - "PSS1_LOGIC_OUTS20_14", - "PSS1_LOGIC_OUTS20_15", - "PSS1_LOGIC_OUTS20_16", - "PSS1_LOGIC_OUTS20_17", - "PSS1_LOGIC_OUTS20_18", - "PSS1_LOGIC_OUTS20_19", - "PSS1_LOGIC_OUTS20_2", - "PSS1_LOGIC_OUTS20_20", - "PSS1_LOGIC_OUTS20_21", - "PSS1_LOGIC_OUTS20_22", - "PSS1_LOGIC_OUTS20_23", - "PSS1_LOGIC_OUTS20_24", - "PSS1_LOGIC_OUTS20_25", - "PSS1_LOGIC_OUTS20_26", - "PSS1_LOGIC_OUTS20_27", - "PSS1_LOGIC_OUTS20_28", - "PSS1_LOGIC_OUTS20_29", - "PSS1_LOGIC_OUTS20_3", - "PSS1_LOGIC_OUTS20_30", - "PSS1_LOGIC_OUTS20_31", - "PSS1_LOGIC_OUTS20_32", - "PSS1_LOGIC_OUTS20_33", - "PSS1_LOGIC_OUTS20_34", - "PSS1_LOGIC_OUTS20_35", - "PSS1_LOGIC_OUTS20_36", - "PSS1_LOGIC_OUTS20_37", - "PSS1_LOGIC_OUTS20_38", - "PSS1_LOGIC_OUTS20_39", - "PSS1_LOGIC_OUTS20_4", - "PSS1_LOGIC_OUTS20_5", - "PSS1_LOGIC_OUTS20_6", - "PSS1_LOGIC_OUTS20_7", - "PSS1_LOGIC_OUTS20_8", - "PSS1_LOGIC_OUTS20_9", - "PSS1_LOGIC_OUTS21_0", - "PSS1_LOGIC_OUTS21_1", - "PSS1_LOGIC_OUTS21_10", - "PSS1_LOGIC_OUTS21_11", - "PSS1_LOGIC_OUTS21_12", - "PSS1_LOGIC_OUTS21_13", - "PSS1_LOGIC_OUTS21_14", - "PSS1_LOGIC_OUTS21_15", - "PSS1_LOGIC_OUTS21_16", - "PSS1_LOGIC_OUTS21_17", - "PSS1_LOGIC_OUTS21_18", - "PSS1_LOGIC_OUTS21_19", - "PSS1_LOGIC_OUTS21_2", - "PSS1_LOGIC_OUTS21_20", - "PSS1_LOGIC_OUTS21_21", - "PSS1_LOGIC_OUTS21_22", - "PSS1_LOGIC_OUTS21_23", - "PSS1_LOGIC_OUTS21_24", - "PSS1_LOGIC_OUTS21_25", - "PSS1_LOGIC_OUTS21_26", - "PSS1_LOGIC_OUTS21_27", - "PSS1_LOGIC_OUTS21_28", - "PSS1_LOGIC_OUTS21_29", - "PSS1_LOGIC_OUTS21_3", - "PSS1_LOGIC_OUTS21_30", - "PSS1_LOGIC_OUTS21_31", - "PSS1_LOGIC_OUTS21_32", - "PSS1_LOGIC_OUTS21_33", - "PSS1_LOGIC_OUTS21_34", - "PSS1_LOGIC_OUTS21_35", - "PSS1_LOGIC_OUTS21_36", - "PSS1_LOGIC_OUTS21_37", - "PSS1_LOGIC_OUTS21_38", - "PSS1_LOGIC_OUTS21_39", - "PSS1_LOGIC_OUTS21_4", - "PSS1_LOGIC_OUTS21_5", - "PSS1_LOGIC_OUTS21_6", - "PSS1_LOGIC_OUTS21_7", - "PSS1_LOGIC_OUTS21_8", - "PSS1_LOGIC_OUTS21_9", - "PSS1_LOGIC_OUTS22_0", - "PSS1_LOGIC_OUTS22_1", - "PSS1_LOGIC_OUTS22_10", - "PSS1_LOGIC_OUTS22_11", - "PSS1_LOGIC_OUTS22_12", - "PSS1_LOGIC_OUTS22_13", - "PSS1_LOGIC_OUTS22_14", - "PSS1_LOGIC_OUTS22_15", - "PSS1_LOGIC_OUTS22_16", - "PSS1_LOGIC_OUTS22_17", - "PSS1_LOGIC_OUTS22_18", - "PSS1_LOGIC_OUTS22_19", - "PSS1_LOGIC_OUTS22_2", - "PSS1_LOGIC_OUTS22_20", - "PSS1_LOGIC_OUTS22_21", - "PSS1_LOGIC_OUTS22_22", - "PSS1_LOGIC_OUTS22_23", - "PSS1_LOGIC_OUTS22_24", - "PSS1_LOGIC_OUTS22_25", - "PSS1_LOGIC_OUTS22_26", - "PSS1_LOGIC_OUTS22_27", - "PSS1_LOGIC_OUTS22_28", - "PSS1_LOGIC_OUTS22_29", - "PSS1_LOGIC_OUTS22_3", - "PSS1_LOGIC_OUTS22_30", - "PSS1_LOGIC_OUTS22_31", - "PSS1_LOGIC_OUTS22_32", - "PSS1_LOGIC_OUTS22_33", - "PSS1_LOGIC_OUTS22_34", - "PSS1_LOGIC_OUTS22_35", - "PSS1_LOGIC_OUTS22_36", - "PSS1_LOGIC_OUTS22_37", - "PSS1_LOGIC_OUTS22_38", - "PSS1_LOGIC_OUTS22_39", - "PSS1_LOGIC_OUTS22_4", - "PSS1_LOGIC_OUTS22_5", - "PSS1_LOGIC_OUTS22_6", - "PSS1_LOGIC_OUTS22_7", - "PSS1_LOGIC_OUTS22_8", - "PSS1_LOGIC_OUTS22_9", - "PSS1_LOGIC_OUTS23_0", - "PSS1_LOGIC_OUTS23_1", - "PSS1_LOGIC_OUTS23_10", - "PSS1_LOGIC_OUTS23_11", - "PSS1_LOGIC_OUTS23_12", - "PSS1_LOGIC_OUTS23_13", - "PSS1_LOGIC_OUTS23_14", - "PSS1_LOGIC_OUTS23_15", - "PSS1_LOGIC_OUTS23_16", - "PSS1_LOGIC_OUTS23_17", - "PSS1_LOGIC_OUTS23_18", - "PSS1_LOGIC_OUTS23_19", - "PSS1_LOGIC_OUTS23_2", - "PSS1_LOGIC_OUTS23_20", - "PSS1_LOGIC_OUTS23_21", - "PSS1_LOGIC_OUTS23_22", - "PSS1_LOGIC_OUTS23_23", - "PSS1_LOGIC_OUTS23_24", - "PSS1_LOGIC_OUTS23_25", - "PSS1_LOGIC_OUTS23_26", - "PSS1_LOGIC_OUTS23_27", - "PSS1_LOGIC_OUTS23_28", - "PSS1_LOGIC_OUTS23_29", - "PSS1_LOGIC_OUTS23_3", - "PSS1_LOGIC_OUTS23_30", - "PSS1_LOGIC_OUTS23_31", - "PSS1_LOGIC_OUTS23_32", - "PSS1_LOGIC_OUTS23_33", - "PSS1_LOGIC_OUTS23_34", - "PSS1_LOGIC_OUTS23_35", - "PSS1_LOGIC_OUTS23_36", - "PSS1_LOGIC_OUTS23_37", - "PSS1_LOGIC_OUTS23_38", - "PSS1_LOGIC_OUTS23_39", - "PSS1_LOGIC_OUTS23_4", - "PSS1_LOGIC_OUTS23_5", - "PSS1_LOGIC_OUTS23_6", - "PSS1_LOGIC_OUTS23_7", - "PSS1_LOGIC_OUTS23_8", - "PSS1_LOGIC_OUTS23_9", - "PSS1_LOGIC_OUTS2_0", - "PSS1_LOGIC_OUTS2_1", - "PSS1_LOGIC_OUTS2_10", - "PSS1_LOGIC_OUTS2_11", - "PSS1_LOGIC_OUTS2_12", - "PSS1_LOGIC_OUTS2_13", - "PSS1_LOGIC_OUTS2_14", - "PSS1_LOGIC_OUTS2_15", - "PSS1_LOGIC_OUTS2_16", - "PSS1_LOGIC_OUTS2_17", - "PSS1_LOGIC_OUTS2_18", - "PSS1_LOGIC_OUTS2_19", - "PSS1_LOGIC_OUTS2_2", - "PSS1_LOGIC_OUTS2_20", - "PSS1_LOGIC_OUTS2_21", - "PSS1_LOGIC_OUTS2_22", - "PSS1_LOGIC_OUTS2_23", - "PSS1_LOGIC_OUTS2_24", - "PSS1_LOGIC_OUTS2_25", - "PSS1_LOGIC_OUTS2_26", - "PSS1_LOGIC_OUTS2_27", - "PSS1_LOGIC_OUTS2_28", - "PSS1_LOGIC_OUTS2_29", - "PSS1_LOGIC_OUTS2_3", - "PSS1_LOGIC_OUTS2_30", - "PSS1_LOGIC_OUTS2_31", - "PSS1_LOGIC_OUTS2_32", - "PSS1_LOGIC_OUTS2_33", - "PSS1_LOGIC_OUTS2_34", - "PSS1_LOGIC_OUTS2_35", - "PSS1_LOGIC_OUTS2_36", - "PSS1_LOGIC_OUTS2_37", - "PSS1_LOGIC_OUTS2_38", - "PSS1_LOGIC_OUTS2_39", - "PSS1_LOGIC_OUTS2_4", - "PSS1_LOGIC_OUTS2_5", - "PSS1_LOGIC_OUTS2_6", - "PSS1_LOGIC_OUTS2_7", - "PSS1_LOGIC_OUTS2_8", - "PSS1_LOGIC_OUTS2_9", - "PSS1_LOGIC_OUTS3_0", - "PSS1_LOGIC_OUTS3_1", - "PSS1_LOGIC_OUTS3_10", - "PSS1_LOGIC_OUTS3_11", - "PSS1_LOGIC_OUTS3_12", - "PSS1_LOGIC_OUTS3_13", - "PSS1_LOGIC_OUTS3_14", - "PSS1_LOGIC_OUTS3_15", - "PSS1_LOGIC_OUTS3_16", - "PSS1_LOGIC_OUTS3_17", - "PSS1_LOGIC_OUTS3_18", - "PSS1_LOGIC_OUTS3_19", - "PSS1_LOGIC_OUTS3_2", - "PSS1_LOGIC_OUTS3_20", - "PSS1_LOGIC_OUTS3_21", - "PSS1_LOGIC_OUTS3_22", - "PSS1_LOGIC_OUTS3_23", - "PSS1_LOGIC_OUTS3_24", - "PSS1_LOGIC_OUTS3_25", - "PSS1_LOGIC_OUTS3_26", - "PSS1_LOGIC_OUTS3_27", - "PSS1_LOGIC_OUTS3_28", - "PSS1_LOGIC_OUTS3_29", - "PSS1_LOGIC_OUTS3_3", - "PSS1_LOGIC_OUTS3_30", - "PSS1_LOGIC_OUTS3_31", - "PSS1_LOGIC_OUTS3_32", - "PSS1_LOGIC_OUTS3_33", - "PSS1_LOGIC_OUTS3_34", - "PSS1_LOGIC_OUTS3_35", - "PSS1_LOGIC_OUTS3_36", - "PSS1_LOGIC_OUTS3_37", - "PSS1_LOGIC_OUTS3_38", - "PSS1_LOGIC_OUTS3_39", - "PSS1_LOGIC_OUTS3_4", - "PSS1_LOGIC_OUTS3_5", - "PSS1_LOGIC_OUTS3_6", - "PSS1_LOGIC_OUTS3_7", - "PSS1_LOGIC_OUTS3_8", - "PSS1_LOGIC_OUTS3_9", - "PSS1_LOGIC_OUTS4_0", - "PSS1_LOGIC_OUTS4_1", - "PSS1_LOGIC_OUTS4_10", - "PSS1_LOGIC_OUTS4_11", - "PSS1_LOGIC_OUTS4_12", - "PSS1_LOGIC_OUTS4_13", - "PSS1_LOGIC_OUTS4_14", - "PSS1_LOGIC_OUTS4_15", - "PSS1_LOGIC_OUTS4_16", - "PSS1_LOGIC_OUTS4_17", - "PSS1_LOGIC_OUTS4_18", - "PSS1_LOGIC_OUTS4_19", - "PSS1_LOGIC_OUTS4_2", - "PSS1_LOGIC_OUTS4_20", - "PSS1_LOGIC_OUTS4_21", - "PSS1_LOGIC_OUTS4_22", - "PSS1_LOGIC_OUTS4_23", - "PSS1_LOGIC_OUTS4_24", - "PSS1_LOGIC_OUTS4_25", - "PSS1_LOGIC_OUTS4_26", - "PSS1_LOGIC_OUTS4_27", - "PSS1_LOGIC_OUTS4_28", - "PSS1_LOGIC_OUTS4_29", - "PSS1_LOGIC_OUTS4_3", - "PSS1_LOGIC_OUTS4_30", - "PSS1_LOGIC_OUTS4_31", - "PSS1_LOGIC_OUTS4_32", - "PSS1_LOGIC_OUTS4_33", - "PSS1_LOGIC_OUTS4_34", - "PSS1_LOGIC_OUTS4_35", - "PSS1_LOGIC_OUTS4_36", - "PSS1_LOGIC_OUTS4_37", - "PSS1_LOGIC_OUTS4_38", - "PSS1_LOGIC_OUTS4_39", - "PSS1_LOGIC_OUTS4_4", - "PSS1_LOGIC_OUTS4_5", - "PSS1_LOGIC_OUTS4_6", - "PSS1_LOGIC_OUTS4_7", - "PSS1_LOGIC_OUTS4_8", - "PSS1_LOGIC_OUTS4_9", - "PSS1_LOGIC_OUTS5_0", - "PSS1_LOGIC_OUTS5_1", - "PSS1_LOGIC_OUTS5_10", - "PSS1_LOGIC_OUTS5_11", - "PSS1_LOGIC_OUTS5_12", - "PSS1_LOGIC_OUTS5_13", - "PSS1_LOGIC_OUTS5_14", - "PSS1_LOGIC_OUTS5_15", - "PSS1_LOGIC_OUTS5_16", - "PSS1_LOGIC_OUTS5_17", - "PSS1_LOGIC_OUTS5_18", - "PSS1_LOGIC_OUTS5_19", - "PSS1_LOGIC_OUTS5_2", - "PSS1_LOGIC_OUTS5_20", - "PSS1_LOGIC_OUTS5_21", - "PSS1_LOGIC_OUTS5_22", - "PSS1_LOGIC_OUTS5_23", - "PSS1_LOGIC_OUTS5_24", - "PSS1_LOGIC_OUTS5_25", - "PSS1_LOGIC_OUTS5_26", - "PSS1_LOGIC_OUTS5_27", - "PSS1_LOGIC_OUTS5_28", - "PSS1_LOGIC_OUTS5_29", - "PSS1_LOGIC_OUTS5_3", - "PSS1_LOGIC_OUTS5_30", - "PSS1_LOGIC_OUTS5_31", - "PSS1_LOGIC_OUTS5_32", - "PSS1_LOGIC_OUTS5_33", - "PSS1_LOGIC_OUTS5_34", - "PSS1_LOGIC_OUTS5_35", - "PSS1_LOGIC_OUTS5_36", - "PSS1_LOGIC_OUTS5_37", - "PSS1_LOGIC_OUTS5_38", - "PSS1_LOGIC_OUTS5_39", - "PSS1_LOGIC_OUTS5_4", - "PSS1_LOGIC_OUTS5_5", - "PSS1_LOGIC_OUTS5_6", - "PSS1_LOGIC_OUTS5_7", - "PSS1_LOGIC_OUTS5_8", - "PSS1_LOGIC_OUTS5_9", - "PSS1_LOGIC_OUTS6_0", - "PSS1_LOGIC_OUTS6_1", - "PSS1_LOGIC_OUTS6_10", - "PSS1_LOGIC_OUTS6_11", - "PSS1_LOGIC_OUTS6_12", - "PSS1_LOGIC_OUTS6_13", - "PSS1_LOGIC_OUTS6_14", - "PSS1_LOGIC_OUTS6_15", - "PSS1_LOGIC_OUTS6_16", - "PSS1_LOGIC_OUTS6_17", - "PSS1_LOGIC_OUTS6_18", - "PSS1_LOGIC_OUTS6_19", - "PSS1_LOGIC_OUTS6_2", - "PSS1_LOGIC_OUTS6_20", - "PSS1_LOGIC_OUTS6_21", - "PSS1_LOGIC_OUTS6_22", - "PSS1_LOGIC_OUTS6_23", - "PSS1_LOGIC_OUTS6_24", - "PSS1_LOGIC_OUTS6_25", - "PSS1_LOGIC_OUTS6_26", - "PSS1_LOGIC_OUTS6_27", - "PSS1_LOGIC_OUTS6_28", - "PSS1_LOGIC_OUTS6_29", - "PSS1_LOGIC_OUTS6_3", - "PSS1_LOGIC_OUTS6_30", - "PSS1_LOGIC_OUTS6_31", - "PSS1_LOGIC_OUTS6_32", - "PSS1_LOGIC_OUTS6_33", - "PSS1_LOGIC_OUTS6_34", - "PSS1_LOGIC_OUTS6_35", - "PSS1_LOGIC_OUTS6_36", - "PSS1_LOGIC_OUTS6_37", - "PSS1_LOGIC_OUTS6_38", - "PSS1_LOGIC_OUTS6_39", - "PSS1_LOGIC_OUTS6_4", - "PSS1_LOGIC_OUTS6_5", - "PSS1_LOGIC_OUTS6_6", - "PSS1_LOGIC_OUTS6_7", - "PSS1_LOGIC_OUTS6_8", - "PSS1_LOGIC_OUTS6_9", - "PSS1_LOGIC_OUTS7_0", - "PSS1_LOGIC_OUTS7_1", - "PSS1_LOGIC_OUTS7_10", - "PSS1_LOGIC_OUTS7_11", - "PSS1_LOGIC_OUTS7_12", - "PSS1_LOGIC_OUTS7_13", - "PSS1_LOGIC_OUTS7_14", - "PSS1_LOGIC_OUTS7_15", - "PSS1_LOGIC_OUTS7_16", - "PSS1_LOGIC_OUTS7_17", - "PSS1_LOGIC_OUTS7_18", - "PSS1_LOGIC_OUTS7_19", - "PSS1_LOGIC_OUTS7_2", - "PSS1_LOGIC_OUTS7_20", - "PSS1_LOGIC_OUTS7_21", - "PSS1_LOGIC_OUTS7_22", - "PSS1_LOGIC_OUTS7_23", - "PSS1_LOGIC_OUTS7_24", - "PSS1_LOGIC_OUTS7_25", - "PSS1_LOGIC_OUTS7_26", - "PSS1_LOGIC_OUTS7_27", - "PSS1_LOGIC_OUTS7_28", - "PSS1_LOGIC_OUTS7_29", - "PSS1_LOGIC_OUTS7_3", - "PSS1_LOGIC_OUTS7_30", - "PSS1_LOGIC_OUTS7_31", - "PSS1_LOGIC_OUTS7_32", - "PSS1_LOGIC_OUTS7_33", - "PSS1_LOGIC_OUTS7_34", - "PSS1_LOGIC_OUTS7_35", - "PSS1_LOGIC_OUTS7_36", - "PSS1_LOGIC_OUTS7_37", - "PSS1_LOGIC_OUTS7_38", - "PSS1_LOGIC_OUTS7_39", - "PSS1_LOGIC_OUTS7_4", - "PSS1_LOGIC_OUTS7_5", - "PSS1_LOGIC_OUTS7_6", - "PSS1_LOGIC_OUTS7_7", - "PSS1_LOGIC_OUTS7_8", - "PSS1_LOGIC_OUTS7_9", - "PSS1_LOGIC_OUTS8_0", - "PSS1_LOGIC_OUTS8_1", - "PSS1_LOGIC_OUTS8_10", - "PSS1_LOGIC_OUTS8_11", - "PSS1_LOGIC_OUTS8_12", - "PSS1_LOGIC_OUTS8_13", - "PSS1_LOGIC_OUTS8_14", - "PSS1_LOGIC_OUTS8_15", - "PSS1_LOGIC_OUTS8_16", - "PSS1_LOGIC_OUTS8_17", - "PSS1_LOGIC_OUTS8_18", - "PSS1_LOGIC_OUTS8_19", - "PSS1_LOGIC_OUTS8_2", - "PSS1_LOGIC_OUTS8_20", - "PSS1_LOGIC_OUTS8_21", - "PSS1_LOGIC_OUTS8_22", - "PSS1_LOGIC_OUTS8_23", - "PSS1_LOGIC_OUTS8_24", - "PSS1_LOGIC_OUTS8_25", - "PSS1_LOGIC_OUTS8_26", - "PSS1_LOGIC_OUTS8_27", - "PSS1_LOGIC_OUTS8_28", - "PSS1_LOGIC_OUTS8_29", - "PSS1_LOGIC_OUTS8_3", - "PSS1_LOGIC_OUTS8_30", - "PSS1_LOGIC_OUTS8_31", - "PSS1_LOGIC_OUTS8_32", - "PSS1_LOGIC_OUTS8_33", - "PSS1_LOGIC_OUTS8_34", - "PSS1_LOGIC_OUTS8_35", - "PSS1_LOGIC_OUTS8_36", - "PSS1_LOGIC_OUTS8_37", - "PSS1_LOGIC_OUTS8_38", - "PSS1_LOGIC_OUTS8_39", - "PSS1_LOGIC_OUTS8_4", - "PSS1_LOGIC_OUTS8_5", - "PSS1_LOGIC_OUTS8_6", - "PSS1_LOGIC_OUTS8_7", - "PSS1_LOGIC_OUTS8_8", - "PSS1_LOGIC_OUTS8_9", - "PSS1_LOGIC_OUTS9_0", - "PSS1_LOGIC_OUTS9_1", - "PSS1_LOGIC_OUTS9_10", - "PSS1_LOGIC_OUTS9_11", - "PSS1_LOGIC_OUTS9_12", - "PSS1_LOGIC_OUTS9_13", - "PSS1_LOGIC_OUTS9_14", - "PSS1_LOGIC_OUTS9_15", - "PSS1_LOGIC_OUTS9_16", - "PSS1_LOGIC_OUTS9_17", - "PSS1_LOGIC_OUTS9_18", - "PSS1_LOGIC_OUTS9_19", - "PSS1_LOGIC_OUTS9_2", - "PSS1_LOGIC_OUTS9_20", - "PSS1_LOGIC_OUTS9_21", - "PSS1_LOGIC_OUTS9_22", - "PSS1_LOGIC_OUTS9_23", - "PSS1_LOGIC_OUTS9_24", - "PSS1_LOGIC_OUTS9_25", - "PSS1_LOGIC_OUTS9_26", - "PSS1_LOGIC_OUTS9_27", - "PSS1_LOGIC_OUTS9_28", - "PSS1_LOGIC_OUTS9_29", - "PSS1_LOGIC_OUTS9_3", - "PSS1_LOGIC_OUTS9_30", - "PSS1_LOGIC_OUTS9_31", - "PSS1_LOGIC_OUTS9_32", - "PSS1_LOGIC_OUTS9_33", - "PSS1_LOGIC_OUTS9_34", - "PSS1_LOGIC_OUTS9_35", - "PSS1_LOGIC_OUTS9_36", - "PSS1_LOGIC_OUTS9_37", - "PSS1_LOGIC_OUTS9_38", - "PSS1_LOGIC_OUTS9_39", - "PSS1_LOGIC_OUTS9_4", - "PSS1_LOGIC_OUTS9_5", - "PSS1_LOGIC_OUTS9_6", - "PSS1_LOGIC_OUTS9_7", - "PSS1_LOGIC_OUTS9_8", - "PSS1_LOGIC_OUTS9_9", - "PSS_BYP_B0_0", - "PSS_BYP_B0_1", - "PSS_BYP_B0_10", - "PSS_BYP_B0_11", - "PSS_BYP_B0_12", - "PSS_BYP_B0_13", - "PSS_BYP_B0_14", - "PSS_BYP_B0_15", - "PSS_BYP_B0_16", - "PSS_BYP_B0_17", - "PSS_BYP_B0_18", - "PSS_BYP_B0_19", - "PSS_BYP_B0_2", - "PSS_BYP_B0_3", - "PSS_BYP_B0_4", - "PSS_BYP_B0_5", - "PSS_BYP_B0_6", - "PSS_BYP_B0_7", - "PSS_BYP_B0_8", - "PSS_BYP_B0_9", - "PSS_BYP_B1_0", - "PSS_BYP_B1_1", - "PSS_BYP_B1_10", - "PSS_BYP_B1_11", - "PSS_BYP_B1_12", - "PSS_BYP_B1_13", - "PSS_BYP_B1_14", - "PSS_BYP_B1_15", - "PSS_BYP_B1_16", - "PSS_BYP_B1_17", - "PSS_BYP_B1_18", - "PSS_BYP_B1_19", - "PSS_BYP_B1_2", - "PSS_BYP_B1_3", - "PSS_BYP_B1_4", - "PSS_BYP_B1_5", - "PSS_BYP_B1_6", - "PSS_BYP_B1_7", - "PSS_BYP_B1_8", - "PSS_BYP_B1_9", - "PSS_BYP_B2_0", - "PSS_BYP_B2_1", - "PSS_BYP_B2_10", - "PSS_BYP_B2_11", - "PSS_BYP_B2_12", - "PSS_BYP_B2_13", - "PSS_BYP_B2_14", - "PSS_BYP_B2_15", - "PSS_BYP_B2_16", - "PSS_BYP_B2_17", - "PSS_BYP_B2_18", - "PSS_BYP_B2_19", - "PSS_BYP_B2_2", - "PSS_BYP_B2_3", - "PSS_BYP_B2_4", - "PSS_BYP_B2_5", - "PSS_BYP_B2_6", - "PSS_BYP_B2_7", - "PSS_BYP_B2_8", - "PSS_BYP_B2_9", - "PSS_BYP_B3_0", - "PSS_BYP_B3_1", - "PSS_BYP_B3_10", - "PSS_BYP_B3_11", - "PSS_BYP_B3_12", - "PSS_BYP_B3_13", - "PSS_BYP_B3_14", - "PSS_BYP_B3_15", - "PSS_BYP_B3_16", - "PSS_BYP_B3_17", - "PSS_BYP_B3_18", - "PSS_BYP_B3_19", - "PSS_BYP_B3_2", - "PSS_BYP_B3_3", - "PSS_BYP_B3_4", - "PSS_BYP_B3_5", - "PSS_BYP_B3_6", - "PSS_BYP_B3_7", - "PSS_BYP_B3_8", - "PSS_BYP_B3_9", - "PSS_BYP_B4_0", - "PSS_BYP_B4_1", - "PSS_BYP_B4_10", - "PSS_BYP_B4_11", - "PSS_BYP_B4_12", - "PSS_BYP_B4_13", - "PSS_BYP_B4_14", - "PSS_BYP_B4_15", - "PSS_BYP_B4_16", - "PSS_BYP_B4_17", - "PSS_BYP_B4_18", - "PSS_BYP_B4_19", - "PSS_BYP_B4_2", - "PSS_BYP_B4_3", - "PSS_BYP_B4_4", - "PSS_BYP_B4_5", - "PSS_BYP_B4_6", - "PSS_BYP_B4_7", - "PSS_BYP_B4_8", - "PSS_BYP_B4_9", - "PSS_BYP_B5_0", - "PSS_BYP_B5_1", - "PSS_BYP_B5_10", - "PSS_BYP_B5_11", - "PSS_BYP_B5_12", - "PSS_BYP_B5_13", - "PSS_BYP_B5_14", - "PSS_BYP_B5_15", - "PSS_BYP_B5_16", - "PSS_BYP_B5_17", - "PSS_BYP_B5_18", - "PSS_BYP_B5_19", - "PSS_BYP_B5_2", - "PSS_BYP_B5_3", - "PSS_BYP_B5_4", - "PSS_BYP_B5_5", - "PSS_BYP_B5_6", - "PSS_BYP_B5_7", - "PSS_BYP_B5_8", - "PSS_BYP_B5_9", - "PSS_BYP_B6_0", - "PSS_BYP_B6_1", - "PSS_BYP_B6_10", - "PSS_BYP_B6_11", - "PSS_BYP_B6_12", - "PSS_BYP_B6_13", - "PSS_BYP_B6_14", - "PSS_BYP_B6_15", - "PSS_BYP_B6_16", - "PSS_BYP_B6_17", - "PSS_BYP_B6_18", - "PSS_BYP_B6_19", - "PSS_BYP_B6_2", - "PSS_BYP_B6_3", - "PSS_BYP_B6_4", - "PSS_BYP_B6_5", - "PSS_BYP_B6_6", - "PSS_BYP_B6_7", - "PSS_BYP_B6_8", - "PSS_BYP_B6_9", - "PSS_BYP_B7_0", - "PSS_BYP_B7_1", - "PSS_BYP_B7_10", - "PSS_BYP_B7_11", - "PSS_BYP_B7_12", - "PSS_BYP_B7_13", - "PSS_BYP_B7_14", - "PSS_BYP_B7_15", - "PSS_BYP_B7_16", - "PSS_BYP_B7_17", - "PSS_BYP_B7_18", - "PSS_BYP_B7_19", - "PSS_BYP_B7_2", - "PSS_BYP_B7_3", - "PSS_BYP_B7_4", - "PSS_BYP_B7_5", - "PSS_BYP_B7_6", - "PSS_BYP_B7_7", - "PSS_BYP_B7_8", - "PSS_BYP_B7_9", - "PSS_CLK_B0_0", - "PSS_CLK_B0_1", - "PSS_CLK_B0_10", - "PSS_CLK_B0_11", - "PSS_CLK_B0_12", - "PSS_CLK_B0_13", - "PSS_CLK_B0_14", - "PSS_CLK_B0_15", - "PSS_CLK_B0_16", - "PSS_CLK_B0_17", - "PSS_CLK_B0_18", - "PSS_CLK_B0_19", - "PSS_CLK_B0_2", - "PSS_CLK_B0_3", - "PSS_CLK_B0_4", - "PSS_CLK_B0_5", - "PSS_CLK_B0_6", - "PSS_CLK_B0_7", - "PSS_CLK_B0_8", - "PSS_CLK_B0_9", - "PSS_CLK_B1_0", - "PSS_CLK_B1_1", - "PSS_CLK_B1_10", - "PSS_CLK_B1_11", - "PSS_CLK_B1_12", - "PSS_CLK_B1_13", - "PSS_CLK_B1_14", - "PSS_CLK_B1_15", - "PSS_CLK_B1_16", - "PSS_CLK_B1_17", - "PSS_CLK_B1_18", - "PSS_CLK_B1_19", - "PSS_CLK_B1_2", - "PSS_CLK_B1_3", - "PSS_CLK_B1_4", - "PSS_CLK_B1_5", - "PSS_CLK_B1_6", - "PSS_CLK_B1_7", - "PSS_CLK_B1_8", - "PSS_CLK_B1_9", - "PSS_CTRL_B0_0", - "PSS_CTRL_B0_1", - "PSS_CTRL_B0_10", - "PSS_CTRL_B0_11", - "PSS_CTRL_B0_12", - "PSS_CTRL_B0_13", - "PSS_CTRL_B0_14", - "PSS_CTRL_B0_15", - "PSS_CTRL_B0_16", - "PSS_CTRL_B0_17", - "PSS_CTRL_B0_18", - "PSS_CTRL_B0_19", - "PSS_CTRL_B0_2", - "PSS_CTRL_B0_3", - "PSS_CTRL_B0_4", - "PSS_CTRL_B0_5", - "PSS_CTRL_B0_6", - "PSS_CTRL_B0_7", - "PSS_CTRL_B0_8", - "PSS_CTRL_B0_9", - "PSS_CTRL_B1_0", - "PSS_CTRL_B1_1", - "PSS_CTRL_B1_10", - "PSS_CTRL_B1_11", - "PSS_CTRL_B1_12", - "PSS_CTRL_B1_13", - "PSS_CTRL_B1_14", - "PSS_CTRL_B1_15", - "PSS_CTRL_B1_16", - "PSS_CTRL_B1_17", - "PSS_CTRL_B1_18", - "PSS_CTRL_B1_19", - "PSS_CTRL_B1_2", - "PSS_CTRL_B1_3", - "PSS_CTRL_B1_4", - "PSS_CTRL_B1_5", - "PSS_CTRL_B1_6", - "PSS_CTRL_B1_7", - "PSS_CTRL_B1_8", - "PSS_CTRL_B1_9", - "PSS_FAN_B0_0", - "PSS_FAN_B0_1", - "PSS_FAN_B0_10", - "PSS_FAN_B0_11", - "PSS_FAN_B0_12", - "PSS_FAN_B0_13", - "PSS_FAN_B0_14", - "PSS_FAN_B0_15", - "PSS_FAN_B0_16", - "PSS_FAN_B0_17", - "PSS_FAN_B0_18", - "PSS_FAN_B0_19", - "PSS_FAN_B0_2", - "PSS_FAN_B0_3", - "PSS_FAN_B0_4", - "PSS_FAN_B0_5", - "PSS_FAN_B0_6", - "PSS_FAN_B0_7", - "PSS_FAN_B0_8", - "PSS_FAN_B0_9", - "PSS_FAN_B1_0", - "PSS_FAN_B1_1", - "PSS_FAN_B1_10", - "PSS_FAN_B1_11", - "PSS_FAN_B1_12", - "PSS_FAN_B1_13", - "PSS_FAN_B1_14", - "PSS_FAN_B1_15", - "PSS_FAN_B1_16", - "PSS_FAN_B1_17", - "PSS_FAN_B1_18", - "PSS_FAN_B1_19", - "PSS_FAN_B1_2", - "PSS_FAN_B1_3", - "PSS_FAN_B1_4", - "PSS_FAN_B1_5", - "PSS_FAN_B1_6", - "PSS_FAN_B1_7", - "PSS_FAN_B1_8", - "PSS_FAN_B1_9", - "PSS_FAN_B2_0", - "PSS_FAN_B2_1", - "PSS_FAN_B2_10", - "PSS_FAN_B2_11", - "PSS_FAN_B2_12", - "PSS_FAN_B2_13", - "PSS_FAN_B2_14", - "PSS_FAN_B2_15", - "PSS_FAN_B2_16", - "PSS_FAN_B2_17", - "PSS_FAN_B2_18", - "PSS_FAN_B2_19", - "PSS_FAN_B2_2", - "PSS_FAN_B2_3", - "PSS_FAN_B2_4", - "PSS_FAN_B2_5", - "PSS_FAN_B2_6", - "PSS_FAN_B2_7", - "PSS_FAN_B2_8", - "PSS_FAN_B2_9", - "PSS_FAN_B3_0", - "PSS_FAN_B3_1", - "PSS_FAN_B3_10", - "PSS_FAN_B3_11", - "PSS_FAN_B3_12", - "PSS_FAN_B3_13", - "PSS_FAN_B3_14", - "PSS_FAN_B3_15", - "PSS_FAN_B3_16", - "PSS_FAN_B3_17", - "PSS_FAN_B3_18", - "PSS_FAN_B3_19", - "PSS_FAN_B3_2", - "PSS_FAN_B3_3", - "PSS_FAN_B3_4", - "PSS_FAN_B3_5", - "PSS_FAN_B3_6", - "PSS_FAN_B3_7", - "PSS_FAN_B3_8", - "PSS_FAN_B3_9", - "PSS_FAN_B4_0", - "PSS_FAN_B4_1", - "PSS_FAN_B4_10", - "PSS_FAN_B4_11", - "PSS_FAN_B4_12", - "PSS_FAN_B4_13", - "PSS_FAN_B4_14", - "PSS_FAN_B4_15", - "PSS_FAN_B4_16", - "PSS_FAN_B4_17", - "PSS_FAN_B4_18", - "PSS_FAN_B4_19", - "PSS_FAN_B4_2", - "PSS_FAN_B4_3", - "PSS_FAN_B4_4", - "PSS_FAN_B4_5", - "PSS_FAN_B4_6", - "PSS_FAN_B4_7", - "PSS_FAN_B4_8", - "PSS_FAN_B4_9", - "PSS_FAN_B5_0", - "PSS_FAN_B5_1", - "PSS_FAN_B5_10", - "PSS_FAN_B5_11", - "PSS_FAN_B5_12", - "PSS_FAN_B5_13", - "PSS_FAN_B5_14", - "PSS_FAN_B5_15", - "PSS_FAN_B5_16", - "PSS_FAN_B5_17", - "PSS_FAN_B5_18", - "PSS_FAN_B5_19", - "PSS_FAN_B5_2", - "PSS_FAN_B5_3", - "PSS_FAN_B5_4", - "PSS_FAN_B5_5", - "PSS_FAN_B5_6", - "PSS_FAN_B5_7", - "PSS_FAN_B5_8", - "PSS_FAN_B5_9", - "PSS_FAN_B6_0", - "PSS_FAN_B6_1", - "PSS_FAN_B6_10", - "PSS_FAN_B6_11", - "PSS_FAN_B6_12", - "PSS_FAN_B6_13", - "PSS_FAN_B6_14", - "PSS_FAN_B6_15", - "PSS_FAN_B6_16", - "PSS_FAN_B6_17", - "PSS_FAN_B6_18", - "PSS_FAN_B6_19", - "PSS_FAN_B6_2", - "PSS_FAN_B6_3", - "PSS_FAN_B6_4", - "PSS_FAN_B6_5", - "PSS_FAN_B6_6", - "PSS_FAN_B6_7", - "PSS_FAN_B6_8", - "PSS_FAN_B6_9", - "PSS_FAN_B7_0", - "PSS_FAN_B7_1", - "PSS_FAN_B7_10", - "PSS_FAN_B7_11", - "PSS_FAN_B7_12", - "PSS_FAN_B7_13", - "PSS_FAN_B7_14", - "PSS_FAN_B7_15", - "PSS_FAN_B7_16", - "PSS_FAN_B7_17", - "PSS_FAN_B7_18", - "PSS_FAN_B7_19", - "PSS_FAN_B7_2", - "PSS_FAN_B7_3", - "PSS_FAN_B7_4", - "PSS_FAN_B7_5", - "PSS_FAN_B7_6", - "PSS_FAN_B7_7", - "PSS_FAN_B7_8", - "PSS_FAN_B7_9", - "PSS_FCLKCLK0", - "PSS_FCLKCLK1", - "PSS_FCLKCLK2", - "PSS_FCLKCLK3", - "PSS_HCLK_CK_IN0", - "PSS_HCLK_CK_IN1", - "PSS_HCLK_CK_IN2", - "PSS_HCLK_CK_IN3", - "PSS_IMUX_B0_0", - "PSS_IMUX_B0_1", - "PSS_IMUX_B0_10", - "PSS_IMUX_B0_11", - "PSS_IMUX_B0_12", - "PSS_IMUX_B0_13", - "PSS_IMUX_B0_14", - "PSS_IMUX_B0_15", - "PSS_IMUX_B0_16", - "PSS_IMUX_B0_17", - "PSS_IMUX_B0_18", - "PSS_IMUX_B0_19", - "PSS_IMUX_B0_2", - "PSS_IMUX_B0_3", - "PSS_IMUX_B0_4", - "PSS_IMUX_B0_5", - "PSS_IMUX_B0_6", - "PSS_IMUX_B0_7", - "PSS_IMUX_B0_8", - "PSS_IMUX_B0_9", - "PSS_IMUX_B10_0", - "PSS_IMUX_B10_1", - "PSS_IMUX_B10_10", - "PSS_IMUX_B10_11", - "PSS_IMUX_B10_12", - "PSS_IMUX_B10_13", - "PSS_IMUX_B10_14", - "PSS_IMUX_B10_15", - "PSS_IMUX_B10_16", - "PSS_IMUX_B10_17", - "PSS_IMUX_B10_18", - "PSS_IMUX_B10_19", - "PSS_IMUX_B10_2", - "PSS_IMUX_B10_3", - "PSS_IMUX_B10_4", - "PSS_IMUX_B10_5", - "PSS_IMUX_B10_6", - "PSS_IMUX_B10_7", - "PSS_IMUX_B10_8", - "PSS_IMUX_B10_9", - "PSS_IMUX_B11_0", - "PSS_IMUX_B11_1", - "PSS_IMUX_B11_10", - "PSS_IMUX_B11_11", - "PSS_IMUX_B11_12", - "PSS_IMUX_B11_13", - "PSS_IMUX_B11_14", - "PSS_IMUX_B11_15", - "PSS_IMUX_B11_16", - "PSS_IMUX_B11_17", - "PSS_IMUX_B11_18", - "PSS_IMUX_B11_19", - "PSS_IMUX_B11_2", - "PSS_IMUX_B11_3", - "PSS_IMUX_B11_4", - "PSS_IMUX_B11_5", - "PSS_IMUX_B11_6", - "PSS_IMUX_B11_7", - "PSS_IMUX_B11_8", - "PSS_IMUX_B11_9", - "PSS_IMUX_B12_0", - "PSS_IMUX_B12_1", - "PSS_IMUX_B12_10", - "PSS_IMUX_B12_11", - "PSS_IMUX_B12_12", - "PSS_IMUX_B12_13", - "PSS_IMUX_B12_14", - "PSS_IMUX_B12_15", - "PSS_IMUX_B12_16", - "PSS_IMUX_B12_17", - "PSS_IMUX_B12_18", - "PSS_IMUX_B12_19", - "PSS_IMUX_B12_2", - "PSS_IMUX_B12_3", - "PSS_IMUX_B12_4", - "PSS_IMUX_B12_5", - "PSS_IMUX_B12_6", - "PSS_IMUX_B12_7", - "PSS_IMUX_B12_8", - "PSS_IMUX_B12_9", - "PSS_IMUX_B13_0", - "PSS_IMUX_B13_1", - "PSS_IMUX_B13_10", - "PSS_IMUX_B13_11", - "PSS_IMUX_B13_12", - "PSS_IMUX_B13_13", - "PSS_IMUX_B13_14", - "PSS_IMUX_B13_15", - "PSS_IMUX_B13_16", - "PSS_IMUX_B13_17", - "PSS_IMUX_B13_18", - "PSS_IMUX_B13_19", - "PSS_IMUX_B13_2", - "PSS_IMUX_B13_3", - "PSS_IMUX_B13_4", - "PSS_IMUX_B13_5", - "PSS_IMUX_B13_6", - "PSS_IMUX_B13_7", - "PSS_IMUX_B13_8", - "PSS_IMUX_B13_9", - "PSS_IMUX_B14_0", - "PSS_IMUX_B14_1", - "PSS_IMUX_B14_10", - "PSS_IMUX_B14_11", - "PSS_IMUX_B14_12", - "PSS_IMUX_B14_13", - "PSS_IMUX_B14_14", - "PSS_IMUX_B14_15", - "PSS_IMUX_B14_16", - "PSS_IMUX_B14_17", - "PSS_IMUX_B14_18", - "PSS_IMUX_B14_19", - "PSS_IMUX_B14_2", - "PSS_IMUX_B14_3", - "PSS_IMUX_B14_4", - "PSS_IMUX_B14_5", - "PSS_IMUX_B14_6", - "PSS_IMUX_B14_7", - "PSS_IMUX_B14_8", - "PSS_IMUX_B14_9", - "PSS_IMUX_B15_0", - "PSS_IMUX_B15_1", - "PSS_IMUX_B15_10", - "PSS_IMUX_B15_11", - "PSS_IMUX_B15_12", - "PSS_IMUX_B15_13", - "PSS_IMUX_B15_14", - "PSS_IMUX_B15_15", - "PSS_IMUX_B15_16", - "PSS_IMUX_B15_17", - "PSS_IMUX_B15_18", - "PSS_IMUX_B15_19", - "PSS_IMUX_B15_2", - "PSS_IMUX_B15_3", - "PSS_IMUX_B15_4", - "PSS_IMUX_B15_5", - "PSS_IMUX_B15_6", - "PSS_IMUX_B15_7", - "PSS_IMUX_B15_8", - "PSS_IMUX_B15_9", - "PSS_IMUX_B16_0", - "PSS_IMUX_B16_1", - "PSS_IMUX_B16_10", - "PSS_IMUX_B16_11", - "PSS_IMUX_B16_12", - "PSS_IMUX_B16_13", - "PSS_IMUX_B16_14", - "PSS_IMUX_B16_15", - "PSS_IMUX_B16_16", - "PSS_IMUX_B16_17", - "PSS_IMUX_B16_18", - "PSS_IMUX_B16_19", - "PSS_IMUX_B16_2", - "PSS_IMUX_B16_3", - "PSS_IMUX_B16_4", - "PSS_IMUX_B16_5", - "PSS_IMUX_B16_6", - "PSS_IMUX_B16_7", - "PSS_IMUX_B16_8", - "PSS_IMUX_B16_9", - "PSS_IMUX_B17_0", - "PSS_IMUX_B17_1", - "PSS_IMUX_B17_10", - "PSS_IMUX_B17_11", - "PSS_IMUX_B17_12", - "PSS_IMUX_B17_13", - "PSS_IMUX_B17_14", - "PSS_IMUX_B17_15", - "PSS_IMUX_B17_16", - "PSS_IMUX_B17_17", - "PSS_IMUX_B17_18", - "PSS_IMUX_B17_19", - "PSS_IMUX_B17_2", - "PSS_IMUX_B17_3", - "PSS_IMUX_B17_4", - "PSS_IMUX_B17_5", - "PSS_IMUX_B17_6", - "PSS_IMUX_B17_7", - "PSS_IMUX_B17_8", - "PSS_IMUX_B17_9", - "PSS_IMUX_B18_0", - "PSS_IMUX_B18_1", - "PSS_IMUX_B18_10", - "PSS_IMUX_B18_11", - "PSS_IMUX_B18_12", - "PSS_IMUX_B18_13", - "PSS_IMUX_B18_14", - "PSS_IMUX_B18_15", - "PSS_IMUX_B18_16", - "PSS_IMUX_B18_17", - "PSS_IMUX_B18_18", - "PSS_IMUX_B18_19", - "PSS_IMUX_B18_2", - "PSS_IMUX_B18_3", - "PSS_IMUX_B18_4", - "PSS_IMUX_B18_5", - "PSS_IMUX_B18_6", - "PSS_IMUX_B18_7", - "PSS_IMUX_B18_8", - "PSS_IMUX_B18_9", - "PSS_IMUX_B19_0", - "PSS_IMUX_B19_1", - "PSS_IMUX_B19_10", - "PSS_IMUX_B19_11", - "PSS_IMUX_B19_12", - "PSS_IMUX_B19_13", - "PSS_IMUX_B19_14", - "PSS_IMUX_B19_15", - "PSS_IMUX_B19_16", - "PSS_IMUX_B19_17", - "PSS_IMUX_B19_18", - "PSS_IMUX_B19_19", - "PSS_IMUX_B19_2", - "PSS_IMUX_B19_3", - "PSS_IMUX_B19_4", - "PSS_IMUX_B19_5", - "PSS_IMUX_B19_6", - "PSS_IMUX_B19_7", - "PSS_IMUX_B19_8", - "PSS_IMUX_B19_9", - "PSS_IMUX_B1_0", - "PSS_IMUX_B1_1", - "PSS_IMUX_B1_10", - "PSS_IMUX_B1_11", - "PSS_IMUX_B1_12", - "PSS_IMUX_B1_13", - "PSS_IMUX_B1_14", - "PSS_IMUX_B1_15", - "PSS_IMUX_B1_16", - "PSS_IMUX_B1_17", - "PSS_IMUX_B1_18", - "PSS_IMUX_B1_19", - "PSS_IMUX_B1_2", - "PSS_IMUX_B1_3", - "PSS_IMUX_B1_4", - "PSS_IMUX_B1_5", - "PSS_IMUX_B1_6", - "PSS_IMUX_B1_7", - "PSS_IMUX_B1_8", - "PSS_IMUX_B1_9", - "PSS_IMUX_B20_0", - "PSS_IMUX_B20_1", - "PSS_IMUX_B20_10", - "PSS_IMUX_B20_11", - "PSS_IMUX_B20_12", - "PSS_IMUX_B20_13", - "PSS_IMUX_B20_14", - "PSS_IMUX_B20_15", - "PSS_IMUX_B20_16", - "PSS_IMUX_B20_17", - "PSS_IMUX_B20_18", - "PSS_IMUX_B20_19", - "PSS_IMUX_B20_2", - "PSS_IMUX_B20_3", - "PSS_IMUX_B20_4", - "PSS_IMUX_B20_5", - "PSS_IMUX_B20_6", - "PSS_IMUX_B20_7", - "PSS_IMUX_B20_8", - "PSS_IMUX_B20_9", - "PSS_IMUX_B21_0", - "PSS_IMUX_B21_1", - "PSS_IMUX_B21_10", - "PSS_IMUX_B21_11", - "PSS_IMUX_B21_12", - "PSS_IMUX_B21_13", - "PSS_IMUX_B21_14", - "PSS_IMUX_B21_15", - "PSS_IMUX_B21_16", - "PSS_IMUX_B21_17", - "PSS_IMUX_B21_18", - "PSS_IMUX_B21_19", - "PSS_IMUX_B21_2", - "PSS_IMUX_B21_3", - "PSS_IMUX_B21_4", - "PSS_IMUX_B21_5", - "PSS_IMUX_B21_6", - "PSS_IMUX_B21_7", - "PSS_IMUX_B21_8", - "PSS_IMUX_B21_9", - "PSS_IMUX_B22_0", - "PSS_IMUX_B22_1", - "PSS_IMUX_B22_10", - "PSS_IMUX_B22_11", - "PSS_IMUX_B22_12", - "PSS_IMUX_B22_13", - "PSS_IMUX_B22_14", - "PSS_IMUX_B22_15", - "PSS_IMUX_B22_16", - "PSS_IMUX_B22_17", - "PSS_IMUX_B22_18", - "PSS_IMUX_B22_19", - "PSS_IMUX_B22_2", - "PSS_IMUX_B22_3", - "PSS_IMUX_B22_4", - "PSS_IMUX_B22_5", - "PSS_IMUX_B22_6", - "PSS_IMUX_B22_7", - "PSS_IMUX_B22_8", - "PSS_IMUX_B22_9", - "PSS_IMUX_B23_0", - "PSS_IMUX_B23_1", - "PSS_IMUX_B23_10", - "PSS_IMUX_B23_11", - "PSS_IMUX_B23_12", - "PSS_IMUX_B23_13", - "PSS_IMUX_B23_14", - "PSS_IMUX_B23_15", - "PSS_IMUX_B23_16", - "PSS_IMUX_B23_17", - "PSS_IMUX_B23_18", - "PSS_IMUX_B23_19", - "PSS_IMUX_B23_2", - "PSS_IMUX_B23_3", - "PSS_IMUX_B23_4", - "PSS_IMUX_B23_5", - "PSS_IMUX_B23_6", - "PSS_IMUX_B23_7", - "PSS_IMUX_B23_8", - "PSS_IMUX_B23_9", - "PSS_IMUX_B24_0", - "PSS_IMUX_B24_1", - "PSS_IMUX_B24_10", - "PSS_IMUX_B24_11", - "PSS_IMUX_B24_12", - "PSS_IMUX_B24_13", - "PSS_IMUX_B24_14", - "PSS_IMUX_B24_15", - "PSS_IMUX_B24_16", - "PSS_IMUX_B24_17", - "PSS_IMUX_B24_18", - "PSS_IMUX_B24_19", - "PSS_IMUX_B24_2", - "PSS_IMUX_B24_3", - "PSS_IMUX_B24_4", - "PSS_IMUX_B24_5", - "PSS_IMUX_B24_6", - "PSS_IMUX_B24_7", - "PSS_IMUX_B24_8", - "PSS_IMUX_B24_9", - "PSS_IMUX_B25_0", - "PSS_IMUX_B25_1", - "PSS_IMUX_B25_10", - "PSS_IMUX_B25_11", - "PSS_IMUX_B25_12", - "PSS_IMUX_B25_13", - "PSS_IMUX_B25_14", - "PSS_IMUX_B25_15", - "PSS_IMUX_B25_16", - "PSS_IMUX_B25_17", - "PSS_IMUX_B25_18", - "PSS_IMUX_B25_19", - "PSS_IMUX_B25_2", - "PSS_IMUX_B25_3", - "PSS_IMUX_B25_4", - "PSS_IMUX_B25_5", - "PSS_IMUX_B25_6", - "PSS_IMUX_B25_7", - "PSS_IMUX_B25_8", - "PSS_IMUX_B25_9", - "PSS_IMUX_B26_0", - "PSS_IMUX_B26_1", - "PSS_IMUX_B26_10", - "PSS_IMUX_B26_11", - "PSS_IMUX_B26_12", - "PSS_IMUX_B26_13", - "PSS_IMUX_B26_14", - "PSS_IMUX_B26_15", - "PSS_IMUX_B26_16", - "PSS_IMUX_B26_17", - "PSS_IMUX_B26_18", - "PSS_IMUX_B26_19", - "PSS_IMUX_B26_2", - "PSS_IMUX_B26_3", - "PSS_IMUX_B26_4", - "PSS_IMUX_B26_5", - "PSS_IMUX_B26_6", - "PSS_IMUX_B26_7", - "PSS_IMUX_B26_8", - "PSS_IMUX_B26_9", - "PSS_IMUX_B27_0", - "PSS_IMUX_B27_1", - "PSS_IMUX_B27_10", - "PSS_IMUX_B27_11", - "PSS_IMUX_B27_12", - "PSS_IMUX_B27_13", - "PSS_IMUX_B27_14", - "PSS_IMUX_B27_15", - "PSS_IMUX_B27_16", - "PSS_IMUX_B27_17", - "PSS_IMUX_B27_18", - "PSS_IMUX_B27_19", - "PSS_IMUX_B27_2", - "PSS_IMUX_B27_3", - "PSS_IMUX_B27_4", - "PSS_IMUX_B27_5", - "PSS_IMUX_B27_6", - "PSS_IMUX_B27_7", - "PSS_IMUX_B27_8", - "PSS_IMUX_B27_9", - "PSS_IMUX_B28_0", - "PSS_IMUX_B28_1", - "PSS_IMUX_B28_10", - "PSS_IMUX_B28_11", - "PSS_IMUX_B28_12", - "PSS_IMUX_B28_13", - "PSS_IMUX_B28_14", - "PSS_IMUX_B28_15", - "PSS_IMUX_B28_16", - "PSS_IMUX_B28_17", - "PSS_IMUX_B28_18", - "PSS_IMUX_B28_19", - "PSS_IMUX_B28_2", - "PSS_IMUX_B28_3", - "PSS_IMUX_B28_4", - "PSS_IMUX_B28_5", - "PSS_IMUX_B28_6", - "PSS_IMUX_B28_7", - "PSS_IMUX_B28_8", - "PSS_IMUX_B28_9", - "PSS_IMUX_B29_0", - "PSS_IMUX_B29_1", - "PSS_IMUX_B29_10", - "PSS_IMUX_B29_11", - "PSS_IMUX_B29_12", - "PSS_IMUX_B29_13", - "PSS_IMUX_B29_14", - "PSS_IMUX_B29_15", - "PSS_IMUX_B29_16", - "PSS_IMUX_B29_17", - "PSS_IMUX_B29_18", - "PSS_IMUX_B29_19", - "PSS_IMUX_B29_2", - "PSS_IMUX_B29_3", - "PSS_IMUX_B29_4", - "PSS_IMUX_B29_5", - "PSS_IMUX_B29_6", - "PSS_IMUX_B29_7", - "PSS_IMUX_B29_8", - "PSS_IMUX_B29_9", - "PSS_IMUX_B2_0", - "PSS_IMUX_B2_1", - "PSS_IMUX_B2_10", - "PSS_IMUX_B2_11", - "PSS_IMUX_B2_12", - "PSS_IMUX_B2_13", - "PSS_IMUX_B2_14", - "PSS_IMUX_B2_15", - "PSS_IMUX_B2_16", - "PSS_IMUX_B2_17", - "PSS_IMUX_B2_18", - "PSS_IMUX_B2_19", - "PSS_IMUX_B2_2", - "PSS_IMUX_B2_3", - "PSS_IMUX_B2_4", - "PSS_IMUX_B2_5", - "PSS_IMUX_B2_6", - "PSS_IMUX_B2_7", - "PSS_IMUX_B2_8", - "PSS_IMUX_B2_9", - "PSS_IMUX_B30_0", - "PSS_IMUX_B30_1", - "PSS_IMUX_B30_10", - "PSS_IMUX_B30_11", - "PSS_IMUX_B30_12", - "PSS_IMUX_B30_13", - "PSS_IMUX_B30_14", - "PSS_IMUX_B30_15", - "PSS_IMUX_B30_16", - "PSS_IMUX_B30_17", - "PSS_IMUX_B30_18", - "PSS_IMUX_B30_19", - "PSS_IMUX_B30_2", - "PSS_IMUX_B30_3", - "PSS_IMUX_B30_4", - "PSS_IMUX_B30_5", - "PSS_IMUX_B30_6", - "PSS_IMUX_B30_7", - "PSS_IMUX_B30_8", - "PSS_IMUX_B30_9", - "PSS_IMUX_B31_0", - "PSS_IMUX_B31_1", - "PSS_IMUX_B31_10", - "PSS_IMUX_B31_11", - "PSS_IMUX_B31_12", - "PSS_IMUX_B31_13", - "PSS_IMUX_B31_14", - "PSS_IMUX_B31_15", - "PSS_IMUX_B31_16", - "PSS_IMUX_B31_17", - "PSS_IMUX_B31_18", - "PSS_IMUX_B31_19", - "PSS_IMUX_B31_2", - "PSS_IMUX_B31_3", - "PSS_IMUX_B31_4", - "PSS_IMUX_B31_5", - "PSS_IMUX_B31_6", - "PSS_IMUX_B31_7", - "PSS_IMUX_B31_8", - "PSS_IMUX_B31_9", - "PSS_IMUX_B32_0", - "PSS_IMUX_B32_1", - "PSS_IMUX_B32_10", - "PSS_IMUX_B32_11", - "PSS_IMUX_B32_12", - "PSS_IMUX_B32_13", - "PSS_IMUX_B32_14", - "PSS_IMUX_B32_15", - "PSS_IMUX_B32_16", - "PSS_IMUX_B32_17", - "PSS_IMUX_B32_18", - "PSS_IMUX_B32_19", - "PSS_IMUX_B32_2", - "PSS_IMUX_B32_3", - "PSS_IMUX_B32_4", - "PSS_IMUX_B32_5", - "PSS_IMUX_B32_6", - "PSS_IMUX_B32_7", - "PSS_IMUX_B32_8", - "PSS_IMUX_B32_9", - "PSS_IMUX_B33_0", - "PSS_IMUX_B33_1", - "PSS_IMUX_B33_10", - "PSS_IMUX_B33_11", - "PSS_IMUX_B33_12", - "PSS_IMUX_B33_13", - "PSS_IMUX_B33_14", - "PSS_IMUX_B33_15", - "PSS_IMUX_B33_16", - "PSS_IMUX_B33_17", - "PSS_IMUX_B33_18", - "PSS_IMUX_B33_19", - "PSS_IMUX_B33_2", - "PSS_IMUX_B33_3", - "PSS_IMUX_B33_4", - "PSS_IMUX_B33_5", - "PSS_IMUX_B33_6", - "PSS_IMUX_B33_7", - "PSS_IMUX_B33_8", - "PSS_IMUX_B33_9", - "PSS_IMUX_B34_0", - "PSS_IMUX_B34_1", - "PSS_IMUX_B34_10", - "PSS_IMUX_B34_11", - "PSS_IMUX_B34_12", - "PSS_IMUX_B34_13", - "PSS_IMUX_B34_14", - "PSS_IMUX_B34_15", - "PSS_IMUX_B34_16", - "PSS_IMUX_B34_17", - "PSS_IMUX_B34_18", - "PSS_IMUX_B34_19", - "PSS_IMUX_B34_2", - "PSS_IMUX_B34_3", - "PSS_IMUX_B34_4", - "PSS_IMUX_B34_5", - "PSS_IMUX_B34_6", - "PSS_IMUX_B34_7", - "PSS_IMUX_B34_8", - "PSS_IMUX_B34_9", - "PSS_IMUX_B35_0", - "PSS_IMUX_B35_1", - "PSS_IMUX_B35_10", - "PSS_IMUX_B35_11", - "PSS_IMUX_B35_12", - "PSS_IMUX_B35_13", - "PSS_IMUX_B35_14", - "PSS_IMUX_B35_15", - "PSS_IMUX_B35_16", - "PSS_IMUX_B35_17", - "PSS_IMUX_B35_18", - "PSS_IMUX_B35_19", - "PSS_IMUX_B35_2", - "PSS_IMUX_B35_3", - "PSS_IMUX_B35_4", - "PSS_IMUX_B35_5", - "PSS_IMUX_B35_6", - "PSS_IMUX_B35_7", - "PSS_IMUX_B35_8", - "PSS_IMUX_B35_9", - "PSS_IMUX_B36_0", - "PSS_IMUX_B36_1", - "PSS_IMUX_B36_10", - "PSS_IMUX_B36_11", - "PSS_IMUX_B36_12", - "PSS_IMUX_B36_13", - "PSS_IMUX_B36_14", - "PSS_IMUX_B36_15", - "PSS_IMUX_B36_16", - "PSS_IMUX_B36_17", - "PSS_IMUX_B36_18", - "PSS_IMUX_B36_19", - "PSS_IMUX_B36_2", - "PSS_IMUX_B36_3", - "PSS_IMUX_B36_4", - "PSS_IMUX_B36_5", - "PSS_IMUX_B36_6", - "PSS_IMUX_B36_7", - "PSS_IMUX_B36_8", - "PSS_IMUX_B36_9", - "PSS_IMUX_B37_0", - "PSS_IMUX_B37_1", - "PSS_IMUX_B37_10", - "PSS_IMUX_B37_11", - "PSS_IMUX_B37_12", - "PSS_IMUX_B37_13", - "PSS_IMUX_B37_14", - "PSS_IMUX_B37_15", - "PSS_IMUX_B37_16", - "PSS_IMUX_B37_17", - "PSS_IMUX_B37_18", - "PSS_IMUX_B37_19", - "PSS_IMUX_B37_2", - "PSS_IMUX_B37_3", - "PSS_IMUX_B37_4", - "PSS_IMUX_B37_5", - "PSS_IMUX_B37_6", - "PSS_IMUX_B37_7", - "PSS_IMUX_B37_8", - "PSS_IMUX_B37_9", - "PSS_IMUX_B38_0", - "PSS_IMUX_B38_1", - "PSS_IMUX_B38_10", - "PSS_IMUX_B38_11", - "PSS_IMUX_B38_12", - "PSS_IMUX_B38_13", - "PSS_IMUX_B38_14", - "PSS_IMUX_B38_15", - "PSS_IMUX_B38_16", - "PSS_IMUX_B38_17", - "PSS_IMUX_B38_18", - "PSS_IMUX_B38_19", - "PSS_IMUX_B38_2", - "PSS_IMUX_B38_3", - "PSS_IMUX_B38_4", - "PSS_IMUX_B38_5", - "PSS_IMUX_B38_6", - "PSS_IMUX_B38_7", - "PSS_IMUX_B38_8", - "PSS_IMUX_B38_9", - "PSS_IMUX_B39_0", - "PSS_IMUX_B39_1", - "PSS_IMUX_B39_10", - "PSS_IMUX_B39_11", - "PSS_IMUX_B39_12", - "PSS_IMUX_B39_13", - "PSS_IMUX_B39_14", - "PSS_IMUX_B39_15", - "PSS_IMUX_B39_16", - "PSS_IMUX_B39_17", - "PSS_IMUX_B39_18", - "PSS_IMUX_B39_19", - "PSS_IMUX_B39_2", - "PSS_IMUX_B39_3", - "PSS_IMUX_B39_4", - "PSS_IMUX_B39_5", - "PSS_IMUX_B39_6", - "PSS_IMUX_B39_7", - "PSS_IMUX_B39_8", - "PSS_IMUX_B39_9", - "PSS_IMUX_B3_0", - "PSS_IMUX_B3_1", - "PSS_IMUX_B3_10", - "PSS_IMUX_B3_11", - "PSS_IMUX_B3_12", - "PSS_IMUX_B3_13", - "PSS_IMUX_B3_14", - "PSS_IMUX_B3_15", - "PSS_IMUX_B3_16", - "PSS_IMUX_B3_17", - "PSS_IMUX_B3_18", - "PSS_IMUX_B3_19", - "PSS_IMUX_B3_2", - "PSS_IMUX_B3_3", - "PSS_IMUX_B3_4", - "PSS_IMUX_B3_5", - "PSS_IMUX_B3_6", - "PSS_IMUX_B3_7", - "PSS_IMUX_B3_8", - "PSS_IMUX_B3_9", - "PSS_IMUX_B40_0", - "PSS_IMUX_B40_1", - "PSS_IMUX_B40_10", - "PSS_IMUX_B40_11", - "PSS_IMUX_B40_12", - "PSS_IMUX_B40_13", - "PSS_IMUX_B40_14", - "PSS_IMUX_B40_15", - "PSS_IMUX_B40_16", - "PSS_IMUX_B40_17", - "PSS_IMUX_B40_18", - "PSS_IMUX_B40_19", - "PSS_IMUX_B40_2", - "PSS_IMUX_B40_3", - "PSS_IMUX_B40_4", - "PSS_IMUX_B40_5", - "PSS_IMUX_B40_6", - "PSS_IMUX_B40_7", - "PSS_IMUX_B40_8", - "PSS_IMUX_B40_9", - "PSS_IMUX_B41_0", - "PSS_IMUX_B41_1", - "PSS_IMUX_B41_10", - "PSS_IMUX_B41_11", - "PSS_IMUX_B41_12", - "PSS_IMUX_B41_13", - "PSS_IMUX_B41_14", - "PSS_IMUX_B41_15", - "PSS_IMUX_B41_16", - "PSS_IMUX_B41_17", - "PSS_IMUX_B41_18", - "PSS_IMUX_B41_19", - "PSS_IMUX_B41_2", - "PSS_IMUX_B41_3", - "PSS_IMUX_B41_4", - "PSS_IMUX_B41_5", - "PSS_IMUX_B41_6", - "PSS_IMUX_B41_7", - "PSS_IMUX_B41_8", - "PSS_IMUX_B41_9", - "PSS_IMUX_B42_0", - "PSS_IMUX_B42_1", - "PSS_IMUX_B42_10", - "PSS_IMUX_B42_11", - "PSS_IMUX_B42_12", - "PSS_IMUX_B42_13", - "PSS_IMUX_B42_14", - "PSS_IMUX_B42_15", - "PSS_IMUX_B42_16", - "PSS_IMUX_B42_17", - "PSS_IMUX_B42_18", - "PSS_IMUX_B42_19", - "PSS_IMUX_B42_2", - "PSS_IMUX_B42_3", - "PSS_IMUX_B42_4", - "PSS_IMUX_B42_5", - "PSS_IMUX_B42_6", - "PSS_IMUX_B42_7", - "PSS_IMUX_B42_8", - "PSS_IMUX_B42_9", - "PSS_IMUX_B43_0", - "PSS_IMUX_B43_1", - "PSS_IMUX_B43_10", - "PSS_IMUX_B43_11", - "PSS_IMUX_B43_12", - "PSS_IMUX_B43_13", - "PSS_IMUX_B43_14", - "PSS_IMUX_B43_15", - "PSS_IMUX_B43_16", - "PSS_IMUX_B43_17", - "PSS_IMUX_B43_18", - "PSS_IMUX_B43_19", - "PSS_IMUX_B43_2", - "PSS_IMUX_B43_3", - "PSS_IMUX_B43_4", - "PSS_IMUX_B43_5", - "PSS_IMUX_B43_6", - "PSS_IMUX_B43_7", - "PSS_IMUX_B43_8", - "PSS_IMUX_B43_9", - "PSS_IMUX_B44_0", - "PSS_IMUX_B44_1", - "PSS_IMUX_B44_10", - "PSS_IMUX_B44_11", - "PSS_IMUX_B44_12", - "PSS_IMUX_B44_13", - "PSS_IMUX_B44_14", - "PSS_IMUX_B44_15", - "PSS_IMUX_B44_16", - "PSS_IMUX_B44_17", - "PSS_IMUX_B44_18", - "PSS_IMUX_B44_19", - "PSS_IMUX_B44_2", - "PSS_IMUX_B44_3", - "PSS_IMUX_B44_4", - "PSS_IMUX_B44_5", - "PSS_IMUX_B44_6", - "PSS_IMUX_B44_7", - "PSS_IMUX_B44_8", - "PSS_IMUX_B44_9", - "PSS_IMUX_B45_0", - "PSS_IMUX_B45_1", - "PSS_IMUX_B45_10", - "PSS_IMUX_B45_11", - "PSS_IMUX_B45_12", - "PSS_IMUX_B45_13", - "PSS_IMUX_B45_14", - "PSS_IMUX_B45_15", - "PSS_IMUX_B45_16", - "PSS_IMUX_B45_17", - "PSS_IMUX_B45_18", - "PSS_IMUX_B45_19", - "PSS_IMUX_B45_2", - "PSS_IMUX_B45_3", - "PSS_IMUX_B45_4", - "PSS_IMUX_B45_5", - "PSS_IMUX_B45_6", - "PSS_IMUX_B45_7", - "PSS_IMUX_B45_8", - "PSS_IMUX_B45_9", - "PSS_IMUX_B46_0", - "PSS_IMUX_B46_1", - "PSS_IMUX_B46_10", - "PSS_IMUX_B46_11", - "PSS_IMUX_B46_12", - "PSS_IMUX_B46_13", - "PSS_IMUX_B46_14", - "PSS_IMUX_B46_15", - "PSS_IMUX_B46_16", - "PSS_IMUX_B46_17", - "PSS_IMUX_B46_18", - "PSS_IMUX_B46_19", - "PSS_IMUX_B46_2", - "PSS_IMUX_B46_3", - "PSS_IMUX_B46_4", - "PSS_IMUX_B46_5", - "PSS_IMUX_B46_6", - "PSS_IMUX_B46_7", - "PSS_IMUX_B46_8", - "PSS_IMUX_B46_9", - "PSS_IMUX_B47_0", - "PSS_IMUX_B47_1", - "PSS_IMUX_B47_10", - "PSS_IMUX_B47_11", - "PSS_IMUX_B47_12", - "PSS_IMUX_B47_13", - "PSS_IMUX_B47_14", - "PSS_IMUX_B47_15", - "PSS_IMUX_B47_16", - "PSS_IMUX_B47_17", - "PSS_IMUX_B47_18", - "PSS_IMUX_B47_19", - "PSS_IMUX_B47_2", - "PSS_IMUX_B47_3", - "PSS_IMUX_B47_4", - "PSS_IMUX_B47_5", - "PSS_IMUX_B47_6", - "PSS_IMUX_B47_7", - "PSS_IMUX_B47_8", - "PSS_IMUX_B47_9", - "PSS_IMUX_B4_0", - "PSS_IMUX_B4_1", - "PSS_IMUX_B4_10", - "PSS_IMUX_B4_11", - "PSS_IMUX_B4_12", - "PSS_IMUX_B4_13", - "PSS_IMUX_B4_14", - "PSS_IMUX_B4_15", - "PSS_IMUX_B4_16", - "PSS_IMUX_B4_17", - "PSS_IMUX_B4_18", - "PSS_IMUX_B4_19", - "PSS_IMUX_B4_2", - "PSS_IMUX_B4_3", - "PSS_IMUX_B4_4", - "PSS_IMUX_B4_5", - "PSS_IMUX_B4_6", - "PSS_IMUX_B4_7", - "PSS_IMUX_B4_8", - "PSS_IMUX_B4_9", - "PSS_IMUX_B5_0", - "PSS_IMUX_B5_1", - "PSS_IMUX_B5_10", - "PSS_IMUX_B5_11", - "PSS_IMUX_B5_12", - "PSS_IMUX_B5_13", - "PSS_IMUX_B5_14", - "PSS_IMUX_B5_15", - "PSS_IMUX_B5_16", - "PSS_IMUX_B5_17", - "PSS_IMUX_B5_18", - "PSS_IMUX_B5_19", - "PSS_IMUX_B5_2", - "PSS_IMUX_B5_3", - "PSS_IMUX_B5_4", - "PSS_IMUX_B5_5", - "PSS_IMUX_B5_6", - "PSS_IMUX_B5_7", - "PSS_IMUX_B5_8", - "PSS_IMUX_B5_9", - "PSS_IMUX_B6_0", - "PSS_IMUX_B6_1", - "PSS_IMUX_B6_10", - "PSS_IMUX_B6_11", - "PSS_IMUX_B6_12", - "PSS_IMUX_B6_13", - "PSS_IMUX_B6_14", - "PSS_IMUX_B6_15", - "PSS_IMUX_B6_16", - "PSS_IMUX_B6_17", - "PSS_IMUX_B6_18", - "PSS_IMUX_B6_19", - "PSS_IMUX_B6_2", - "PSS_IMUX_B6_3", - "PSS_IMUX_B6_4", - "PSS_IMUX_B6_5", - "PSS_IMUX_B6_6", - "PSS_IMUX_B6_7", - "PSS_IMUX_B6_8", - "PSS_IMUX_B6_9", - "PSS_IMUX_B7_0", - "PSS_IMUX_B7_1", - "PSS_IMUX_B7_10", - "PSS_IMUX_B7_11", - "PSS_IMUX_B7_12", - "PSS_IMUX_B7_13", - "PSS_IMUX_B7_14", - "PSS_IMUX_B7_15", - "PSS_IMUX_B7_16", - "PSS_IMUX_B7_17", - "PSS_IMUX_B7_18", - "PSS_IMUX_B7_19", - "PSS_IMUX_B7_2", - "PSS_IMUX_B7_3", - "PSS_IMUX_B7_4", - "PSS_IMUX_B7_5", - "PSS_IMUX_B7_6", - "PSS_IMUX_B7_7", - "PSS_IMUX_B7_8", - "PSS_IMUX_B7_9", - "PSS_IMUX_B8_0", - "PSS_IMUX_B8_1", - "PSS_IMUX_B8_10", - "PSS_IMUX_B8_11", - "PSS_IMUX_B8_12", - "PSS_IMUX_B8_13", - "PSS_IMUX_B8_14", - "PSS_IMUX_B8_15", - "PSS_IMUX_B8_16", - "PSS_IMUX_B8_17", - "PSS_IMUX_B8_18", - "PSS_IMUX_B8_19", - "PSS_IMUX_B8_2", - "PSS_IMUX_B8_3", - "PSS_IMUX_B8_4", - "PSS_IMUX_B8_5", - "PSS_IMUX_B8_6", - "PSS_IMUX_B8_7", - "PSS_IMUX_B8_8", - "PSS_IMUX_B8_9", - "PSS_IMUX_B9_0", - "PSS_IMUX_B9_1", - "PSS_IMUX_B9_10", - "PSS_IMUX_B9_11", - "PSS_IMUX_B9_12", - "PSS_IMUX_B9_13", - "PSS_IMUX_B9_14", - "PSS_IMUX_B9_15", - "PSS_IMUX_B9_16", - "PSS_IMUX_B9_17", - "PSS_IMUX_B9_18", - "PSS_IMUX_B9_19", - "PSS_IMUX_B9_2", - "PSS_IMUX_B9_3", - "PSS_IMUX_B9_4", - "PSS_IMUX_B9_5", - "PSS_IMUX_B9_6", - "PSS_IMUX_B9_7", - "PSS_IMUX_B9_8", - "PSS_IMUX_B9_9", - "PSS_LOGIC_OUTS0_0", - "PSS_LOGIC_OUTS0_1", - "PSS_LOGIC_OUTS0_10", - "PSS_LOGIC_OUTS0_11", - "PSS_LOGIC_OUTS0_12", - "PSS_LOGIC_OUTS0_13", - "PSS_LOGIC_OUTS0_14", - "PSS_LOGIC_OUTS0_15", - "PSS_LOGIC_OUTS0_16", - "PSS_LOGIC_OUTS0_17", - "PSS_LOGIC_OUTS0_18", - "PSS_LOGIC_OUTS0_19", - "PSS_LOGIC_OUTS0_2", - "PSS_LOGIC_OUTS0_3", - "PSS_LOGIC_OUTS0_4", - "PSS_LOGIC_OUTS0_5", - "PSS_LOGIC_OUTS0_6", - "PSS_LOGIC_OUTS0_7", - "PSS_LOGIC_OUTS0_8", - "PSS_LOGIC_OUTS0_9", - "PSS_LOGIC_OUTS10_0", - "PSS_LOGIC_OUTS10_1", - "PSS_LOGIC_OUTS10_10", - "PSS_LOGIC_OUTS10_11", - "PSS_LOGIC_OUTS10_12", - "PSS_LOGIC_OUTS10_13", - "PSS_LOGIC_OUTS10_14", - "PSS_LOGIC_OUTS10_15", - "PSS_LOGIC_OUTS10_16", - "PSS_LOGIC_OUTS10_17", - "PSS_LOGIC_OUTS10_18", - "PSS_LOGIC_OUTS10_19", - "PSS_LOGIC_OUTS10_2", - "PSS_LOGIC_OUTS10_3", - "PSS_LOGIC_OUTS10_4", - "PSS_LOGIC_OUTS10_5", - "PSS_LOGIC_OUTS10_6", - "PSS_LOGIC_OUTS10_7", - "PSS_LOGIC_OUTS10_8", - "PSS_LOGIC_OUTS10_9", - "PSS_LOGIC_OUTS11_0", - "PSS_LOGIC_OUTS11_1", - "PSS_LOGIC_OUTS11_10", - "PSS_LOGIC_OUTS11_11", - "PSS_LOGIC_OUTS11_12", - "PSS_LOGIC_OUTS11_13", - "PSS_LOGIC_OUTS11_14", - "PSS_LOGIC_OUTS11_15", - "PSS_LOGIC_OUTS11_16", - "PSS_LOGIC_OUTS11_17", - "PSS_LOGIC_OUTS11_18", - "PSS_LOGIC_OUTS11_19", - "PSS_LOGIC_OUTS11_2", - "PSS_LOGIC_OUTS11_3", - "PSS_LOGIC_OUTS11_4", - "PSS_LOGIC_OUTS11_5", - "PSS_LOGIC_OUTS11_6", - "PSS_LOGIC_OUTS11_7", - "PSS_LOGIC_OUTS11_8", - "PSS_LOGIC_OUTS11_9", - "PSS_LOGIC_OUTS12_0", - "PSS_LOGIC_OUTS12_1", - "PSS_LOGIC_OUTS12_10", - "PSS_LOGIC_OUTS12_11", - "PSS_LOGIC_OUTS12_12", - "PSS_LOGIC_OUTS12_13", - "PSS_LOGIC_OUTS12_14", - "PSS_LOGIC_OUTS12_15", - "PSS_LOGIC_OUTS12_16", - "PSS_LOGIC_OUTS12_17", - "PSS_LOGIC_OUTS12_18", - "PSS_LOGIC_OUTS12_19", - "PSS_LOGIC_OUTS12_2", - "PSS_LOGIC_OUTS12_3", - "PSS_LOGIC_OUTS12_4", - "PSS_LOGIC_OUTS12_5", - "PSS_LOGIC_OUTS12_6", - "PSS_LOGIC_OUTS12_7", - "PSS_LOGIC_OUTS12_8", - "PSS_LOGIC_OUTS12_9", - "PSS_LOGIC_OUTS13_0", - "PSS_LOGIC_OUTS13_1", - "PSS_LOGIC_OUTS13_10", - "PSS_LOGIC_OUTS13_11", - "PSS_LOGIC_OUTS13_12", - "PSS_LOGIC_OUTS13_13", - "PSS_LOGIC_OUTS13_14", - "PSS_LOGIC_OUTS13_15", - "PSS_LOGIC_OUTS13_16", - "PSS_LOGIC_OUTS13_17", - "PSS_LOGIC_OUTS13_18", - "PSS_LOGIC_OUTS13_19", - "PSS_LOGIC_OUTS13_2", - "PSS_LOGIC_OUTS13_3", - "PSS_LOGIC_OUTS13_4", - "PSS_LOGIC_OUTS13_5", - "PSS_LOGIC_OUTS13_6", - "PSS_LOGIC_OUTS13_7", - "PSS_LOGIC_OUTS13_8", - "PSS_LOGIC_OUTS13_9", - "PSS_LOGIC_OUTS14_0", - "PSS_LOGIC_OUTS14_1", - "PSS_LOGIC_OUTS14_10", - "PSS_LOGIC_OUTS14_11", - "PSS_LOGIC_OUTS14_12", - "PSS_LOGIC_OUTS14_13", - "PSS_LOGIC_OUTS14_14", - "PSS_LOGIC_OUTS14_15", - "PSS_LOGIC_OUTS14_16", - "PSS_LOGIC_OUTS14_17", - "PSS_LOGIC_OUTS14_18", - "PSS_LOGIC_OUTS14_19", - "PSS_LOGIC_OUTS14_2", - "PSS_LOGIC_OUTS14_3", - "PSS_LOGIC_OUTS14_4", - "PSS_LOGIC_OUTS14_5", - "PSS_LOGIC_OUTS14_6", - "PSS_LOGIC_OUTS14_7", - "PSS_LOGIC_OUTS14_8", - "PSS_LOGIC_OUTS14_9", - "PSS_LOGIC_OUTS15_0", - "PSS_LOGIC_OUTS15_1", - "PSS_LOGIC_OUTS15_10", - "PSS_LOGIC_OUTS15_11", - "PSS_LOGIC_OUTS15_12", - "PSS_LOGIC_OUTS15_13", - "PSS_LOGIC_OUTS15_14", - "PSS_LOGIC_OUTS15_15", - "PSS_LOGIC_OUTS15_16", - "PSS_LOGIC_OUTS15_17", - "PSS_LOGIC_OUTS15_18", - "PSS_LOGIC_OUTS15_19", - "PSS_LOGIC_OUTS15_2", - "PSS_LOGIC_OUTS15_3", - "PSS_LOGIC_OUTS15_4", - "PSS_LOGIC_OUTS15_5", - "PSS_LOGIC_OUTS15_6", - "PSS_LOGIC_OUTS15_7", - "PSS_LOGIC_OUTS15_8", - "PSS_LOGIC_OUTS15_9", - "PSS_LOGIC_OUTS16_0", - "PSS_LOGIC_OUTS16_1", - "PSS_LOGIC_OUTS16_10", - "PSS_LOGIC_OUTS16_11", - "PSS_LOGIC_OUTS16_12", - "PSS_LOGIC_OUTS16_13", - "PSS_LOGIC_OUTS16_14", - "PSS_LOGIC_OUTS16_15", - "PSS_LOGIC_OUTS16_16", - "PSS_LOGIC_OUTS16_17", - "PSS_LOGIC_OUTS16_18", - "PSS_LOGIC_OUTS16_19", - "PSS_LOGIC_OUTS16_2", - "PSS_LOGIC_OUTS16_3", - "PSS_LOGIC_OUTS16_4", - "PSS_LOGIC_OUTS16_5", - "PSS_LOGIC_OUTS16_6", - "PSS_LOGIC_OUTS16_7", - "PSS_LOGIC_OUTS16_8", - "PSS_LOGIC_OUTS16_9", - "PSS_LOGIC_OUTS17_0", - "PSS_LOGIC_OUTS17_1", - "PSS_LOGIC_OUTS17_10", - "PSS_LOGIC_OUTS17_11", - "PSS_LOGIC_OUTS17_12", - "PSS_LOGIC_OUTS17_13", - "PSS_LOGIC_OUTS17_14", - "PSS_LOGIC_OUTS17_15", - "PSS_LOGIC_OUTS17_16", - "PSS_LOGIC_OUTS17_17", - "PSS_LOGIC_OUTS17_18", - "PSS_LOGIC_OUTS17_19", - "PSS_LOGIC_OUTS17_2", - "PSS_LOGIC_OUTS17_3", - "PSS_LOGIC_OUTS17_4", - "PSS_LOGIC_OUTS17_5", - "PSS_LOGIC_OUTS17_6", - "PSS_LOGIC_OUTS17_7", - "PSS_LOGIC_OUTS17_8", - "PSS_LOGIC_OUTS17_9", - "PSS_LOGIC_OUTS18_0", - "PSS_LOGIC_OUTS18_1", - "PSS_LOGIC_OUTS18_10", - "PSS_LOGIC_OUTS18_11", - "PSS_LOGIC_OUTS18_12", - "PSS_LOGIC_OUTS18_13", - "PSS_LOGIC_OUTS18_14", - "PSS_LOGIC_OUTS18_15", - "PSS_LOGIC_OUTS18_16", - "PSS_LOGIC_OUTS18_17", - "PSS_LOGIC_OUTS18_18", - "PSS_LOGIC_OUTS18_19", - "PSS_LOGIC_OUTS18_2", - "PSS_LOGIC_OUTS18_3", - "PSS_LOGIC_OUTS18_4", - "PSS_LOGIC_OUTS18_5", - "PSS_LOGIC_OUTS18_6", - "PSS_LOGIC_OUTS18_7", - "PSS_LOGIC_OUTS18_8", - "PSS_LOGIC_OUTS18_9", - "PSS_LOGIC_OUTS19_0", - "PSS_LOGIC_OUTS19_1", - "PSS_LOGIC_OUTS19_10", - "PSS_LOGIC_OUTS19_11", - "PSS_LOGIC_OUTS19_12", - "PSS_LOGIC_OUTS19_13", - "PSS_LOGIC_OUTS19_14", - "PSS_LOGIC_OUTS19_15", - "PSS_LOGIC_OUTS19_16", - "PSS_LOGIC_OUTS19_17", - "PSS_LOGIC_OUTS19_18", - "PSS_LOGIC_OUTS19_19", - "PSS_LOGIC_OUTS19_2", - "PSS_LOGIC_OUTS19_3", - "PSS_LOGIC_OUTS19_4", - "PSS_LOGIC_OUTS19_5", - "PSS_LOGIC_OUTS19_6", - "PSS_LOGIC_OUTS19_7", - "PSS_LOGIC_OUTS19_8", - "PSS_LOGIC_OUTS19_9", - "PSS_LOGIC_OUTS1_0", - "PSS_LOGIC_OUTS1_1", - "PSS_LOGIC_OUTS1_10", - "PSS_LOGIC_OUTS1_11", - "PSS_LOGIC_OUTS1_12", - "PSS_LOGIC_OUTS1_13", - "PSS_LOGIC_OUTS1_14", - "PSS_LOGIC_OUTS1_15", - "PSS_LOGIC_OUTS1_16", - "PSS_LOGIC_OUTS1_17", - "PSS_LOGIC_OUTS1_18", - "PSS_LOGIC_OUTS1_19", - "PSS_LOGIC_OUTS1_2", - "PSS_LOGIC_OUTS1_3", - "PSS_LOGIC_OUTS1_4", - "PSS_LOGIC_OUTS1_5", - "PSS_LOGIC_OUTS1_6", - "PSS_LOGIC_OUTS1_7", - "PSS_LOGIC_OUTS1_8", - "PSS_LOGIC_OUTS1_9", - "PSS_LOGIC_OUTS20_0", - "PSS_LOGIC_OUTS20_1", - "PSS_LOGIC_OUTS20_10", - "PSS_LOGIC_OUTS20_11", - "PSS_LOGIC_OUTS20_12", - "PSS_LOGIC_OUTS20_13", - "PSS_LOGIC_OUTS20_14", - "PSS_LOGIC_OUTS20_15", - "PSS_LOGIC_OUTS20_16", - "PSS_LOGIC_OUTS20_17", - "PSS_LOGIC_OUTS20_18", - "PSS_LOGIC_OUTS20_19", - "PSS_LOGIC_OUTS20_2", - "PSS_LOGIC_OUTS20_3", - "PSS_LOGIC_OUTS20_4", - "PSS_LOGIC_OUTS20_5", - "PSS_LOGIC_OUTS20_6", - "PSS_LOGIC_OUTS20_7", - "PSS_LOGIC_OUTS20_8", - "PSS_LOGIC_OUTS20_9", - "PSS_LOGIC_OUTS21_0", - "PSS_LOGIC_OUTS21_1", - "PSS_LOGIC_OUTS21_10", - "PSS_LOGIC_OUTS21_11", - "PSS_LOGIC_OUTS21_12", - "PSS_LOGIC_OUTS21_13", - "PSS_LOGIC_OUTS21_14", - "PSS_LOGIC_OUTS21_15", - "PSS_LOGIC_OUTS21_16", - "PSS_LOGIC_OUTS21_17", - "PSS_LOGIC_OUTS21_18", - "PSS_LOGIC_OUTS21_19", - "PSS_LOGIC_OUTS21_2", - "PSS_LOGIC_OUTS21_3", - "PSS_LOGIC_OUTS21_4", - "PSS_LOGIC_OUTS21_5", - "PSS_LOGIC_OUTS21_6", - "PSS_LOGIC_OUTS21_7", - "PSS_LOGIC_OUTS21_8", - "PSS_LOGIC_OUTS21_9", - "PSS_LOGIC_OUTS22_0", - "PSS_LOGIC_OUTS22_1", - "PSS_LOGIC_OUTS22_10", - "PSS_LOGIC_OUTS22_11", - "PSS_LOGIC_OUTS22_12", - "PSS_LOGIC_OUTS22_13", - "PSS_LOGIC_OUTS22_14", - "PSS_LOGIC_OUTS22_15", - "PSS_LOGIC_OUTS22_16", - "PSS_LOGIC_OUTS22_17", - "PSS_LOGIC_OUTS22_18", - "PSS_LOGIC_OUTS22_19", - "PSS_LOGIC_OUTS22_2", - "PSS_LOGIC_OUTS22_3", - "PSS_LOGIC_OUTS22_4", - "PSS_LOGIC_OUTS22_5", - "PSS_LOGIC_OUTS22_6", - "PSS_LOGIC_OUTS22_7", - "PSS_LOGIC_OUTS22_8", - "PSS_LOGIC_OUTS22_9", - "PSS_LOGIC_OUTS23_0", - "PSS_LOGIC_OUTS23_1", - "PSS_LOGIC_OUTS23_10", - "PSS_LOGIC_OUTS23_11", - "PSS_LOGIC_OUTS23_12", - "PSS_LOGIC_OUTS23_13", - "PSS_LOGIC_OUTS23_14", - "PSS_LOGIC_OUTS23_15", - "PSS_LOGIC_OUTS23_16", - "PSS_LOGIC_OUTS23_17", - "PSS_LOGIC_OUTS23_18", - "PSS_LOGIC_OUTS23_19", - "PSS_LOGIC_OUTS23_2", - "PSS_LOGIC_OUTS23_3", - "PSS_LOGIC_OUTS23_4", - "PSS_LOGIC_OUTS23_5", - "PSS_LOGIC_OUTS23_6", - "PSS_LOGIC_OUTS23_7", - "PSS_LOGIC_OUTS23_8", - "PSS_LOGIC_OUTS23_9", - "PSS_LOGIC_OUTS2_0", - "PSS_LOGIC_OUTS2_1", - "PSS_LOGIC_OUTS2_10", - "PSS_LOGIC_OUTS2_11", - "PSS_LOGIC_OUTS2_12", - "PSS_LOGIC_OUTS2_13", - "PSS_LOGIC_OUTS2_14", - "PSS_LOGIC_OUTS2_15", - "PSS_LOGIC_OUTS2_16", - "PSS_LOGIC_OUTS2_17", - "PSS_LOGIC_OUTS2_18", - "PSS_LOGIC_OUTS2_19", - "PSS_LOGIC_OUTS2_2", - "PSS_LOGIC_OUTS2_3", - "PSS_LOGIC_OUTS2_4", - "PSS_LOGIC_OUTS2_5", - "PSS_LOGIC_OUTS2_6", - "PSS_LOGIC_OUTS2_7", - "PSS_LOGIC_OUTS2_8", - "PSS_LOGIC_OUTS2_9", - "PSS_LOGIC_OUTS3_0", - "PSS_LOGIC_OUTS3_1", - "PSS_LOGIC_OUTS3_10", - "PSS_LOGIC_OUTS3_11", - "PSS_LOGIC_OUTS3_12", - "PSS_LOGIC_OUTS3_13", - "PSS_LOGIC_OUTS3_14", - "PSS_LOGIC_OUTS3_15", - "PSS_LOGIC_OUTS3_16", - "PSS_LOGIC_OUTS3_17", - "PSS_LOGIC_OUTS3_18", - "PSS_LOGIC_OUTS3_19", - "PSS_LOGIC_OUTS3_2", - "PSS_LOGIC_OUTS3_3", - "PSS_LOGIC_OUTS3_4", - "PSS_LOGIC_OUTS3_5", - "PSS_LOGIC_OUTS3_6", - "PSS_LOGIC_OUTS3_7", - "PSS_LOGIC_OUTS3_8", - "PSS_LOGIC_OUTS3_9", - "PSS_LOGIC_OUTS4_0", - "PSS_LOGIC_OUTS4_1", - "PSS_LOGIC_OUTS4_10", - "PSS_LOGIC_OUTS4_11", - "PSS_LOGIC_OUTS4_12", - "PSS_LOGIC_OUTS4_13", - "PSS_LOGIC_OUTS4_14", - "PSS_LOGIC_OUTS4_15", - "PSS_LOGIC_OUTS4_16", - "PSS_LOGIC_OUTS4_17", - "PSS_LOGIC_OUTS4_18", - "PSS_LOGIC_OUTS4_19", - "PSS_LOGIC_OUTS4_2", - "PSS_LOGIC_OUTS4_3", - "PSS_LOGIC_OUTS4_4", - "PSS_LOGIC_OUTS4_5", - "PSS_LOGIC_OUTS4_6", - "PSS_LOGIC_OUTS4_7", - "PSS_LOGIC_OUTS4_8", - "PSS_LOGIC_OUTS4_9", - "PSS_LOGIC_OUTS5_0", - "PSS_LOGIC_OUTS5_1", - "PSS_LOGIC_OUTS5_10", - "PSS_LOGIC_OUTS5_11", - "PSS_LOGIC_OUTS5_12", - "PSS_LOGIC_OUTS5_13", - "PSS_LOGIC_OUTS5_14", - "PSS_LOGIC_OUTS5_15", - "PSS_LOGIC_OUTS5_16", - "PSS_LOGIC_OUTS5_17", - "PSS_LOGIC_OUTS5_18", - "PSS_LOGIC_OUTS5_19", - "PSS_LOGIC_OUTS5_2", - "PSS_LOGIC_OUTS5_3", - "PSS_LOGIC_OUTS5_4", - "PSS_LOGIC_OUTS5_5", - "PSS_LOGIC_OUTS5_6", - "PSS_LOGIC_OUTS5_7", - "PSS_LOGIC_OUTS5_8", - "PSS_LOGIC_OUTS5_9", - "PSS_LOGIC_OUTS6_0", - "PSS_LOGIC_OUTS6_1", - "PSS_LOGIC_OUTS6_10", - "PSS_LOGIC_OUTS6_11", - "PSS_LOGIC_OUTS6_12", - "PSS_LOGIC_OUTS6_13", - "PSS_LOGIC_OUTS6_14", - "PSS_LOGIC_OUTS6_15", - "PSS_LOGIC_OUTS6_16", - "PSS_LOGIC_OUTS6_17", - "PSS_LOGIC_OUTS6_18", - "PSS_LOGIC_OUTS6_19", - "PSS_LOGIC_OUTS6_2", - "PSS_LOGIC_OUTS6_3", - "PSS_LOGIC_OUTS6_4", - "PSS_LOGIC_OUTS6_5", - "PSS_LOGIC_OUTS6_6", - "PSS_LOGIC_OUTS6_7", - "PSS_LOGIC_OUTS6_8", - "PSS_LOGIC_OUTS6_9", - "PSS_LOGIC_OUTS7_0", - "PSS_LOGIC_OUTS7_1", - "PSS_LOGIC_OUTS7_10", - "PSS_LOGIC_OUTS7_11", - "PSS_LOGIC_OUTS7_12", - "PSS_LOGIC_OUTS7_13", - "PSS_LOGIC_OUTS7_14", - "PSS_LOGIC_OUTS7_15", - "PSS_LOGIC_OUTS7_16", - "PSS_LOGIC_OUTS7_17", - "PSS_LOGIC_OUTS7_18", - "PSS_LOGIC_OUTS7_19", - "PSS_LOGIC_OUTS7_2", - "PSS_LOGIC_OUTS7_3", - "PSS_LOGIC_OUTS7_4", - "PSS_LOGIC_OUTS7_5", - "PSS_LOGIC_OUTS7_6", - "PSS_LOGIC_OUTS7_7", - "PSS_LOGIC_OUTS7_8", - "PSS_LOGIC_OUTS7_9", - "PSS_LOGIC_OUTS8_0", - "PSS_LOGIC_OUTS8_1", - "PSS_LOGIC_OUTS8_10", - "PSS_LOGIC_OUTS8_11", - "PSS_LOGIC_OUTS8_12", - "PSS_LOGIC_OUTS8_13", - "PSS_LOGIC_OUTS8_14", - "PSS_LOGIC_OUTS8_15", - "PSS_LOGIC_OUTS8_16", - "PSS_LOGIC_OUTS8_17", - "PSS_LOGIC_OUTS8_18", - "PSS_LOGIC_OUTS8_19", - "PSS_LOGIC_OUTS8_2", - "PSS_LOGIC_OUTS8_3", - "PSS_LOGIC_OUTS8_4", - "PSS_LOGIC_OUTS8_5", - "PSS_LOGIC_OUTS8_6", - "PSS_LOGIC_OUTS8_7", - "PSS_LOGIC_OUTS8_8", - "PSS_LOGIC_OUTS8_9", - "PSS_LOGIC_OUTS9_0", - "PSS_LOGIC_OUTS9_1", - "PSS_LOGIC_OUTS9_10", - "PSS_LOGIC_OUTS9_11", - "PSS_LOGIC_OUTS9_12", - "PSS_LOGIC_OUTS9_13", - "PSS_LOGIC_OUTS9_14", - "PSS_LOGIC_OUTS9_15", - "PSS_LOGIC_OUTS9_16", - "PSS_LOGIC_OUTS9_17", - "PSS_LOGIC_OUTS9_18", - "PSS_LOGIC_OUTS9_19", - "PSS_LOGIC_OUTS9_2", - "PSS_LOGIC_OUTS9_3", - "PSS_LOGIC_OUTS9_4", - "PSS_LOGIC_OUTS9_5", - "PSS_LOGIC_OUTS9_6", - "PSS_LOGIC_OUTS9_7", - "PSS_LOGIC_OUTS9_8", - "PSS_LOGIC_OUTS9_9" - ] + "wires": { + "PSS0_CLK_B0_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B10_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B11_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B11_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B11_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B11_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B11_12": { + "cap": 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"is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PS72_MIO9" }, "PSS2.PS72_PSCLK<<->>PS7_PSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PS7_PSCLK", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PS72_PSCLK" }, "PSS2.PS72_PSPORB<<->>PS7_PSPORB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PS7_PSPORB", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PS72_PSPORB" }, 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"is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA0DATYPE1" }, "PSS2.PS7_DMA0DAVALID->PSS1_LOGIC_OUTS2_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA0DAVALID" }, "PSS2.PS7_DMA0DRREADY->PSS_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA0DRREADY" }, "PSS2.PS7_DMA0RSTN->PSS1_LOGIC_OUTS0_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA0RSTN" }, "PSS2.PS7_DMA1DATYPE0->PSS1_LOGIC_OUTS0_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA1DATYPE0" }, "PSS2.PS7_DMA1DATYPE1->PSS1_LOGIC_OUTS1_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA1DATYPE1" }, "PSS2.PS7_DMA1DAVALID->PSS1_LOGIC_OUTS2_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA1DAVALID" }, "PSS2.PS7_DMA1DRREADY->PSS_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA1DRREADY" }, "PSS2.PS7_DMA1RSTN->PSS1_LOGIC_OUTS0_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA1RSTN" }, "PSS2.PS7_DMA2DATYPE0->PSS1_LOGIC_OUTS3_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA2DATYPE0" }, "PSS2.PS7_DMA2DATYPE1->PSS1_LOGIC_OUTS4_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA2DATYPE1" }, "PSS2.PS7_DMA2DAVALID->PSS1_LOGIC_OUTS5_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA2DAVALID" }, "PSS2.PS7_DMA2DRREADY->PSS_LOGIC_OUTS0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA2DRREADY" }, "PSS2.PS7_DMA2RSTN->PSS1_LOGIC_OUTS0_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA2RSTN" }, "PSS2.PS7_DMA3DATYPE0->PSS1_LOGIC_OUTS3_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA3DATYPE0" }, "PSS2.PS7_DMA3DATYPE1->PSS1_LOGIC_OUTS4_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA3DATYPE1" }, "PSS2.PS7_DMA3DAVALID->PSS1_LOGIC_OUTS5_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA3DAVALID" }, "PSS2.PS7_DMA3DRREADY->PSS_LOGIC_OUTS0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA3DRREADY" }, "PSS2.PS7_DMA3RSTN->PSS1_LOGIC_OUTS0_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_DMA3RSTN" }, "PSS2.PS7_EMIOCAN0PHYTX->PSS2_LOGIC_OUTS8_89": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_89", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOCAN0PHYTX" }, "PSS2.PS7_EMIOCAN1PHYTX->PSS2_LOGIC_OUTS7_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOCAN1PHYTX" }, "PSS2.PS7_EMIOENET0GMIITXD0->PSS2_LOGIC_OUTS0_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET0GMIITXD0" }, "PSS2.PS7_EMIOENET0GMIITXD1->PSS2_LOGIC_OUTS1_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET0GMIITXD1" }, "PSS2.PS7_EMIOENET0GMIITXD2->PSS2_LOGIC_OUTS2_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET0GMIITXD2" }, "PSS2.PS7_EMIOENET0GMIITXD3->PSS2_LOGIC_OUTS3_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET0GMIITXD3" }, "PSS2.PS7_EMIOENET0GMIITXD4->PSS2_LOGIC_OUTS0_68": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_68", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET0GMIITXD4" }, "PSS2.PS7_EMIOENET0GMIITXD5->PSS2_LOGIC_OUTS1_68": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_68", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET0GMIITXD5" }, "PSS2.PS7_EMIOENET0GMIITXD6->PSS2_LOGIC_OUTS2_68": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_68", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET0GMIITXD6" }, "PSS2.PS7_EMIOENET0GMIITXD7->PSS2_LOGIC_OUTS3_68": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_68", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET0GMIITXD7" }, "PSS2.PS7_EMIOENET0GMIITXEN->PSS2_LOGIC_OUTS4_68": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_68", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET0GMIITXEN" }, "PSS2.PS7_EMIOENET0GMIITXER->PSS2_LOGIC_OUTS4_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET0GMIITXER" }, "PSS2.PS7_EMIOENET0MDIOMDC->PSS2_LOGIC_OUTS5_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": 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"src_wire": "PS7_EMIOENET1GMIITXD0" }, "PSS2.PS7_EMIOENET1GMIITXD1->PSS2_LOGIC_OUTS1_71": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_71", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1GMIITXD1" }, "PSS2.PS7_EMIOENET1GMIITXD2->PSS2_LOGIC_OUTS2_71": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_71", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1GMIITXD2" }, "PSS2.PS7_EMIOENET1GMIITXD3->PSS2_LOGIC_OUTS3_71": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_71", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1GMIITXD3" }, "PSS2.PS7_EMIOENET1GMIITXD4->PSS2_LOGIC_OUTS0_72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1GMIITXD4" }, "PSS2.PS7_EMIOENET1GMIITXD5->PSS2_LOGIC_OUTS1_72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1GMIITXD5" }, "PSS2.PS7_EMIOENET1GMIITXD6->PSS2_LOGIC_OUTS2_72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1GMIITXD6" }, "PSS2.PS7_EMIOENET1GMIITXD7->PSS2_LOGIC_OUTS3_72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1GMIITXD7" }, "PSS2.PS7_EMIOENET1GMIITXEN->PSS2_LOGIC_OUTS4_72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1GMIITXEN" }, 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"delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1MDIOO" }, "PSS2.PS7_EMIOENET1MDIOTN->PSS2_LOGIC_OUTS1_70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_70", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1MDIOTN" }, "PSS2.PS7_EMIOENET1PTPDELAYREQRX->PSS2_LOGIC_OUTS4_69": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_69", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1PTPDELAYREQRX" }, "PSS2.PS7_EMIOENET1PTPDELAYREQTX->PSS2_LOGIC_OUTS3_70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": 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"is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1PTPSYNCFRAMERX" }, "PSS2.PS7_EMIOENET1PTPSYNCFRAMETX->PSS2_LOGIC_OUTS2_70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_70", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1PTPSYNCFRAMETX" }, "PSS2.PS7_EMIOENET1SOFRX->PSS2_LOGIC_OUTS5_70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_70", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1SOFRX" }, "PSS2.PS7_EMIOENET1SOFTX->PSS2_LOGIC_OUTS2_69": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_69", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOENET1SOFTX" }, "PSS2.PS7_EMIOGPIOO0->PSS2_LOGIC_OUTS0_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO0" }, "PSS2.PS7_EMIOGPIOO1->PSS2_LOGIC_OUTS1_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO1" }, "PSS2.PS7_EMIOGPIOO10->PSS2_LOGIC_OUTS2_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO10" }, "PSS2.PS7_EMIOGPIOO11->PSS2_LOGIC_OUTS3_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO11" }, "PSS2.PS7_EMIOGPIOO12->PSS2_LOGIC_OUTS0_76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO12" }, "PSS2.PS7_EMIOGPIOO13->PSS2_LOGIC_OUTS1_76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO13" }, "PSS2.PS7_EMIOGPIOO14->PSS2_LOGIC_OUTS2_76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO14" }, "PSS2.PS7_EMIOGPIOO15->PSS2_LOGIC_OUTS3_76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO15" }, "PSS2.PS7_EMIOGPIOO16->PSS2_LOGIC_OUTS0_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO16" }, "PSS2.PS7_EMIOGPIOO17->PSS2_LOGIC_OUTS1_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO17" }, "PSS2.PS7_EMIOGPIOO18->PSS2_LOGIC_OUTS2_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO18" }, "PSS2.PS7_EMIOGPIOO19->PSS2_LOGIC_OUTS3_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO19" }, "PSS2.PS7_EMIOGPIOO2->PSS2_LOGIC_OUTS2_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO2" }, "PSS2.PS7_EMIOGPIOO20->PSS2_LOGIC_OUTS0_78": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_78", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO20" }, "PSS2.PS7_EMIOGPIOO21->PSS2_LOGIC_OUTS1_78": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_78", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO21" }, "PSS2.PS7_EMIOGPIOO22->PSS2_LOGIC_OUTS2_78": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_78", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO22" }, "PSS2.PS7_EMIOGPIOO23->PSS2_LOGIC_OUTS3_78": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_78", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO23" }, "PSS2.PS7_EMIOGPIOO24->PSS2_LOGIC_OUTS0_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO24" }, "PSS2.PS7_EMIOGPIOO25->PSS2_LOGIC_OUTS1_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO25" }, "PSS2.PS7_EMIOGPIOO26->PSS2_LOGIC_OUTS2_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO26" }, "PSS2.PS7_EMIOGPIOO27->PSS2_LOGIC_OUTS3_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO27" }, "PSS2.PS7_EMIOGPIOO28->PSS2_LOGIC_OUTS0_80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO28" }, "PSS2.PS7_EMIOGPIOO29->PSS2_LOGIC_OUTS1_80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO29" }, "PSS2.PS7_EMIOGPIOO3->PSS2_LOGIC_OUTS3_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO3" }, "PSS2.PS7_EMIOGPIOO30->PSS2_LOGIC_OUTS2_80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO30" }, "PSS2.PS7_EMIOGPIOO31->PSS2_LOGIC_OUTS3_80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO31" }, "PSS2.PS7_EMIOGPIOO32->PSS2_LOGIC_OUTS0_81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO32" }, "PSS2.PS7_EMIOGPIOO33->PSS2_LOGIC_OUTS1_81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO33" }, "PSS2.PS7_EMIOGPIOO34->PSS2_LOGIC_OUTS2_81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO34" }, "PSS2.PS7_EMIOGPIOO35->PSS2_LOGIC_OUTS3_81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO35" }, "PSS2.PS7_EMIOGPIOO36->PSS2_LOGIC_OUTS0_82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO36" }, "PSS2.PS7_EMIOGPIOO37->PSS2_LOGIC_OUTS1_82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO37" }, "PSS2.PS7_EMIOGPIOO38->PSS2_LOGIC_OUTS2_82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO38" }, "PSS2.PS7_EMIOGPIOO39->PSS2_LOGIC_OUTS3_82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO39" }, "PSS2.PS7_EMIOGPIOO4->PSS2_LOGIC_OUTS0_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO4" }, "PSS2.PS7_EMIOGPIOO40->PSS2_LOGIC_OUTS0_83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO40" }, "PSS2.PS7_EMIOGPIOO41->PSS2_LOGIC_OUTS1_83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO41" }, "PSS2.PS7_EMIOGPIOO42->PSS2_LOGIC_OUTS2_83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO42" }, "PSS2.PS7_EMIOGPIOO43->PSS2_LOGIC_OUTS3_83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO43" }, "PSS2.PS7_EMIOGPIOO44->PSS2_LOGIC_OUTS0_84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO44" }, "PSS2.PS7_EMIOGPIOO45->PSS2_LOGIC_OUTS1_84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO45" }, "PSS2.PS7_EMIOGPIOO46->PSS2_LOGIC_OUTS2_84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO46" }, "PSS2.PS7_EMIOGPIOO47->PSS2_LOGIC_OUTS3_84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO47" }, "PSS2.PS7_EMIOGPIOO48->PSS2_LOGIC_OUTS0_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO48" }, "PSS2.PS7_EMIOGPIOO49->PSS2_LOGIC_OUTS1_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO49" }, "PSS2.PS7_EMIOGPIOO5->PSS2_LOGIC_OUTS1_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO5" }, "PSS2.PS7_EMIOGPIOO50->PSS2_LOGIC_OUTS2_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO50" }, "PSS2.PS7_EMIOGPIOO51->PSS2_LOGIC_OUTS3_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO51" }, "PSS2.PS7_EMIOGPIOO52->PSS2_LOGIC_OUTS0_86": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_86", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO52" }, "PSS2.PS7_EMIOGPIOO53->PSS2_LOGIC_OUTS1_86": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_86", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO53" }, "PSS2.PS7_EMIOGPIOO54->PSS2_LOGIC_OUTS2_86": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_86", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO54" }, "PSS2.PS7_EMIOGPIOO55->PSS2_LOGIC_OUTS3_86": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_86", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO55" }, "PSS2.PS7_EMIOGPIOO56->PSS2_LOGIC_OUTS0_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO56" }, "PSS2.PS7_EMIOGPIOO57->PSS2_LOGIC_OUTS1_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO57" }, "PSS2.PS7_EMIOGPIOO58->PSS2_LOGIC_OUTS2_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO58" }, "PSS2.PS7_EMIOGPIOO59->PSS2_LOGIC_OUTS3_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO59" }, "PSS2.PS7_EMIOGPIOO6->PSS2_LOGIC_OUTS2_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO6" }, "PSS2.PS7_EMIOGPIOO60->PSS2_LOGIC_OUTS0_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO60" }, "PSS2.PS7_EMIOGPIOO61->PSS2_LOGIC_OUTS1_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO61" }, "PSS2.PS7_EMIOGPIOO62->PSS2_LOGIC_OUTS2_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO62" }, "PSS2.PS7_EMIOGPIOO63->PSS2_LOGIC_OUTS3_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO63" }, "PSS2.PS7_EMIOGPIOO7->PSS2_LOGIC_OUTS3_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO7" }, "PSS2.PS7_EMIOGPIOO8->PSS2_LOGIC_OUTS0_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO8" }, "PSS2.PS7_EMIOGPIOO9->PSS2_LOGIC_OUTS1_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOO9" }, "PSS2.PS7_EMIOGPIOTN0->PSS2_LOGIC_OUTS4_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN0" }, "PSS2.PS7_EMIOGPIOTN1->PSS2_LOGIC_OUTS5_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN1" }, "PSS2.PS7_EMIOGPIOTN10->PSS2_LOGIC_OUTS6_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN10" }, "PSS2.PS7_EMIOGPIOTN11->PSS2_LOGIC_OUTS7_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN11" }, "PSS2.PS7_EMIOGPIOTN12->PSS2_LOGIC_OUTS4_76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN12" }, "PSS2.PS7_EMIOGPIOTN13->PSS2_LOGIC_OUTS5_76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN13" }, "PSS2.PS7_EMIOGPIOTN14->PSS2_LOGIC_OUTS6_76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN14" }, "PSS2.PS7_EMIOGPIOTN15->PSS2_LOGIC_OUTS7_76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN15" }, "PSS2.PS7_EMIOGPIOTN16->PSS2_LOGIC_OUTS4_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN16" }, "PSS2.PS7_EMIOGPIOTN17->PSS2_LOGIC_OUTS5_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN17" }, "PSS2.PS7_EMIOGPIOTN18->PSS2_LOGIC_OUTS6_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN18" }, "PSS2.PS7_EMIOGPIOTN19->PSS2_LOGIC_OUTS7_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN19" }, "PSS2.PS7_EMIOGPIOTN2->PSS2_LOGIC_OUTS6_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN2" }, "PSS2.PS7_EMIOGPIOTN20->PSS2_LOGIC_OUTS4_78": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_78", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN20" }, "PSS2.PS7_EMIOGPIOTN21->PSS2_LOGIC_OUTS5_78": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_78", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN21" }, "PSS2.PS7_EMIOGPIOTN22->PSS2_LOGIC_OUTS6_78": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_78", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN22" }, "PSS2.PS7_EMIOGPIOTN23->PSS2_LOGIC_OUTS7_78": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_78", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN23" }, "PSS2.PS7_EMIOGPIOTN24->PSS2_LOGIC_OUTS4_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN24" }, "PSS2.PS7_EMIOGPIOTN25->PSS2_LOGIC_OUTS5_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN25" }, "PSS2.PS7_EMIOGPIOTN26->PSS2_LOGIC_OUTS6_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN26" }, "PSS2.PS7_EMIOGPIOTN27->PSS2_LOGIC_OUTS7_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN27" }, "PSS2.PS7_EMIOGPIOTN28->PSS2_LOGIC_OUTS4_80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN28" }, "PSS2.PS7_EMIOGPIOTN29->PSS2_LOGIC_OUTS5_80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN29" }, "PSS2.PS7_EMIOGPIOTN3->PSS2_LOGIC_OUTS7_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN3" }, "PSS2.PS7_EMIOGPIOTN30->PSS2_LOGIC_OUTS6_80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN30" }, "PSS2.PS7_EMIOGPIOTN31->PSS2_LOGIC_OUTS7_80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN31" }, "PSS2.PS7_EMIOGPIOTN32->PSS2_LOGIC_OUTS4_81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN32" }, "PSS2.PS7_EMIOGPIOTN33->PSS2_LOGIC_OUTS5_81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN33" }, "PSS2.PS7_EMIOGPIOTN34->PSS2_LOGIC_OUTS6_81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_81", "is_directional": "1", + "is_pass_transistor": 1, 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"delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN4" }, "PSS2.PS7_EMIOGPIOTN40->PSS2_LOGIC_OUTS4_83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN40" }, "PSS2.PS7_EMIOGPIOTN41->PSS2_LOGIC_OUTS5_83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN41" }, 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null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN44" }, "PSS2.PS7_EMIOGPIOTN45->PSS2_LOGIC_OUTS5_84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN45" }, "PSS2.PS7_EMIOGPIOTN46->PSS2_LOGIC_OUTS6_84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN46" }, "PSS2.PS7_EMIOGPIOTN47->PSS2_LOGIC_OUTS7_84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN47" }, "PSS2.PS7_EMIOGPIOTN48->PSS2_LOGIC_OUTS4_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN48" }, "PSS2.PS7_EMIOGPIOTN49->PSS2_LOGIC_OUTS5_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN49" }, "PSS2.PS7_EMIOGPIOTN5->PSS2_LOGIC_OUTS5_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN5" }, "PSS2.PS7_EMIOGPIOTN50->PSS2_LOGIC_OUTS6_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN50" }, "PSS2.PS7_EMIOGPIOTN51->PSS2_LOGIC_OUTS7_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN51" }, "PSS2.PS7_EMIOGPIOTN52->PSS2_LOGIC_OUTS4_86": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_86", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN52" }, "PSS2.PS7_EMIOGPIOTN53->PSS2_LOGIC_OUTS5_86": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_86", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN53" }, "PSS2.PS7_EMIOGPIOTN54->PSS2_LOGIC_OUTS6_86": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_86", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN54" }, 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null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN57" }, "PSS2.PS7_EMIOGPIOTN58->PSS2_LOGIC_OUTS6_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN58" }, "PSS2.PS7_EMIOGPIOTN59->PSS2_LOGIC_OUTS7_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN59" }, "PSS2.PS7_EMIOGPIOTN6->PSS2_LOGIC_OUTS6_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN6" }, "PSS2.PS7_EMIOGPIOTN60->PSS2_LOGIC_OUTS4_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN60" }, "PSS2.PS7_EMIOGPIOTN61->PSS2_LOGIC_OUTS5_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN61" }, "PSS2.PS7_EMIOGPIOTN62->PSS2_LOGIC_OUTS6_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN62" }, "PSS2.PS7_EMIOGPIOTN63->PSS2_LOGIC_OUTS7_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN63" }, "PSS2.PS7_EMIOGPIOTN7->PSS2_LOGIC_OUTS7_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN7" }, "PSS2.PS7_EMIOGPIOTN8->PSS2_LOGIC_OUTS4_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN8" }, "PSS2.PS7_EMIOGPIOTN9->PSS2_LOGIC_OUTS5_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOGPIOTN9" }, "PSS2.PS7_EMIOI2C0SCLO->PSS2_LOGIC_OUTS4_89": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_89", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOI2C0SCLO" }, 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"in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOI2C0SDATN" }, "PSS2.PS7_EMIOI2C1SCLO->PSS2_LOGIC_OUTS3_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOI2C1SCLO" }, "PSS2.PS7_EMIOI2C1SCLTN->PSS2_LOGIC_OUTS4_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOI2C1SCLTN" }, "PSS2.PS7_EMIOI2C1SDAO->PSS2_LOGIC_OUTS5_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_90", "is_directional": "1", + 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"src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO0DATAO0" }, "PSS2.PS7_EMIOSDIO0DATAO1->PSS2_LOGIC_OUTS1_91": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_91", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO0DATAO1" }, "PSS2.PS7_EMIOSDIO0DATAO2->PSS2_LOGIC_OUTS2_91": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_91", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO0DATAO2" }, "PSS2.PS7_EMIOSDIO0DATAO3->PSS2_LOGIC_OUTS3_91": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": 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"PS7_EMIOSDIO0LED" }, "PSS2.PS7_EMIOSDIO1BUSPOW->PSS2_LOGIC_OUTS4_96": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_96", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO1BUSPOW" }, "PSS2.PS7_EMIOSDIO1BUSVOLT0->PSS2_LOGIC_OUTS4_95": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_95", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO1BUSVOLT0" }, "PSS2.PS7_EMIOSDIO1BUSVOLT1->PSS2_LOGIC_OUTS5_97": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_97", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO1BUSVOLT1" }, "PSS2.PS7_EMIOSDIO1BUSVOLT2->PSS2_LOGIC_OUTS9_98": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_98", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO1BUSVOLT2" }, "PSS2.PS7_EMIOSDIO1CLK->PSS2_LOGIC_OUTS4_98": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_98", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO1CLK" }, "PSS2.PS7_EMIOSDIO1CMDO->PSS2_LOGIC_OUTS5_98": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": 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"dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_95", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO1DATAO1" }, "PSS2.PS7_EMIOSDIO1DATAO2->PSS2_LOGIC_OUTS2_95": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_95", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO1DATAO2" }, "PSS2.PS7_EMIOSDIO1DATAO3->PSS2_LOGIC_OUTS3_95": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_95", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO1DATAO3" }, "PSS2.PS7_EMIOSDIO1DATATN0->PSS2_LOGIC_OUTS3_97": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_97", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO1DATATN0" }, "PSS2.PS7_EMIOSDIO1DATATN1->PSS2_LOGIC_OUTS4_97": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_97", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO1DATATN1" }, "PSS2.PS7_EMIOSDIO1DATATN2->PSS2_LOGIC_OUTS7_98": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_98", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO1DATATN2" }, "PSS2.PS7_EMIOSDIO1DATATN3->PSS2_LOGIC_OUTS8_98": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_98", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO1DATATN3" }, "PSS2.PS7_EMIOSDIO1LED->PSS2_LOGIC_OUTS3_96": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_96", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSDIO1LED" }, "PSS2.PS7_EMIOSPI0MO->PSS2_LOGIC_OUTS2_94": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_94", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI0MO" }, "PSS2.PS7_EMIOSPI0MOTN->PSS2_LOGIC_OUTS3_94": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_94", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI0MOTN" }, "PSS2.PS7_EMIOSPI0SCLKO->PSS2_LOGIC_OUTS0_94": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_94", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI0SCLKO" }, "PSS2.PS7_EMIOSPI0SCLKTN->PSS2_LOGIC_OUTS1_94": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_94", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI0SCLKTN" }, "PSS2.PS7_EMIOSPI0SO->PSS2_LOGIC_OUTS0_93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI0SO" }, "PSS2.PS7_EMIOSPI0SSNTN->PSS2_LOGIC_OUTS2_93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI0SSNTN" }, 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"in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI0SSON2" }, "PSS2.PS7_EMIOSPI0STN->PSS2_LOGIC_OUTS1_93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI0STN" }, "PSS2.PS7_EMIOSPI1MO->PSS2_LOGIC_OUTS2_98": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_98", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI1MO" }, "PSS2.PS7_EMIOSPI1MOTN->PSS2_LOGIC_OUTS3_98": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_98", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI1MOTN" }, "PSS2.PS7_EMIOSPI1SCLKO->PSS2_LOGIC_OUTS0_98": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_98", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI1SCLKO" }, "PSS2.PS7_EMIOSPI1SCLKTN->PSS2_LOGIC_OUTS1_98": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_98", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI1SCLKTN" }, "PSS2.PS7_EMIOSPI1SO->PSS2_LOGIC_OUTS0_97": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_97", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI1SO" }, "PSS2.PS7_EMIOSPI1SSNTN->PSS2_LOGIC_OUTS2_97": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_97", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI1SSNTN" }, "PSS2.PS7_EMIOSPI1SSON0->PSS2_LOGIC_OUTS0_96": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_96", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI1SSON0" }, "PSS2.PS7_EMIOSPI1SSON1->PSS2_LOGIC_OUTS1_96": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_96", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI1SSON1" }, "PSS2.PS7_EMIOSPI1SSON2->PSS2_LOGIC_OUTS2_96": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_96", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI1SSON2" }, "PSS2.PS7_EMIOSPI1STN->PSS2_LOGIC_OUTS1_97": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_97", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOSPI1STN" }, "PSS2.PS7_EMIOTRACECTL->PSS2_LOGIC_OUTS11_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACECTL" }, "PSS2.PS7_EMIOTRACEDATA0->PSS2_LOGIC_OUTS12_89": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_89", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA0" }, "PSS2.PS7_EMIOTRACEDATA1->PSS2_LOGIC_OUTS13_89": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_89", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA1" }, "PSS2.PS7_EMIOTRACEDATA10->PSS2_LOGIC_OUTS7_91": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_91", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA10" }, "PSS2.PS7_EMIOTRACEDATA11->PSS2_LOGIC_OUTS8_91": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_91", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA11" }, "PSS2.PS7_EMIOTRACEDATA12->PSS2_LOGIC_OUTS5_92": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_92", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA12" }, "PSS2.PS7_EMIOTRACEDATA13->PSS2_LOGIC_OUTS6_92": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_92", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA13" }, "PSS2.PS7_EMIOTRACEDATA14->PSS2_LOGIC_OUTS7_92": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_92", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA14" }, "PSS2.PS7_EMIOTRACEDATA15->PSS2_LOGIC_OUTS8_92": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_92", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA15" }, "PSS2.PS7_EMIOTRACEDATA16->PSS2_LOGIC_OUTS6_93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA16" }, "PSS2.PS7_EMIOTRACEDATA17->PSS2_LOGIC_OUTS7_93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA17" }, "PSS2.PS7_EMIOTRACEDATA18->PSS2_LOGIC_OUTS8_93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA18" }, "PSS2.PS7_EMIOTRACEDATA19->PSS2_LOGIC_OUTS9_93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA19" }, "PSS2.PS7_EMIOTRACEDATA2->PSS2_LOGIC_OUTS14_89": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_89", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA2" }, "PSS2.PS7_EMIOTRACEDATA20->PSS2_LOGIC_OUTS10_94": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_94", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA20" }, "PSS2.PS7_EMIOTRACEDATA21->PSS2_LOGIC_OUTS11_94": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_94", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA21" }, "PSS2.PS7_EMIOTRACEDATA22->PSS2_LOGIC_OUTS5_95": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_95", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA22" }, "PSS2.PS7_EMIOTRACEDATA23->PSS2_LOGIC_OUTS6_95": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_95", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA23" }, "PSS2.PS7_EMIOTRACEDATA24->PSS2_LOGIC_OUTS7_95": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_95", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA24" }, "PSS2.PS7_EMIOTRACEDATA25->PSS2_LOGIC_OUTS8_95": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_95", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA25" }, "PSS2.PS7_EMIOTRACEDATA26->PSS2_LOGIC_OUTS5_96": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_96", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA26" }, "PSS2.PS7_EMIOTRACEDATA27->PSS2_LOGIC_OUTS6_96": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_96", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA27" }, "PSS2.PS7_EMIOTRACEDATA28->PSS2_LOGIC_OUTS7_96": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_96", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA28" }, "PSS2.PS7_EMIOTRACEDATA29->PSS2_LOGIC_OUTS8_96": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_96", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA29" }, "PSS2.PS7_EMIOTRACEDATA3->PSS2_LOGIC_OUTS15_89": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS15_89", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA3" }, "PSS2.PS7_EMIOTRACEDATA30->PSS2_LOGIC_OUTS6_97": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_97", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA30" }, "PSS2.PS7_EMIOTRACEDATA31->PSS2_LOGIC_OUTS7_97": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_97", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA31" }, "PSS2.PS7_EMIOTRACEDATA4->PSS2_LOGIC_OUTS12_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA4" }, "PSS2.PS7_EMIOTRACEDATA5->PSS2_LOGIC_OUTS13_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA5" }, "PSS2.PS7_EMIOTRACEDATA6->PSS2_LOGIC_OUTS14_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA6" }, "PSS2.PS7_EMIOTRACEDATA7->PSS2_LOGIC_OUTS15_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS15_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA7" }, "PSS2.PS7_EMIOTRACEDATA8->PSS2_LOGIC_OUTS5_91": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_91", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA8" }, "PSS2.PS7_EMIOTRACEDATA9->PSS2_LOGIC_OUTS6_91": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_91", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTRACEDATA9" }, "PSS2.PS7_EMIOTTC0WAVEO0->PSS2_LOGIC_OUTS0_89": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_89", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTTC0WAVEO0" }, "PSS2.PS7_EMIOTTC0WAVEO1->PSS2_LOGIC_OUTS1_89": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_89", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTTC0WAVEO1" }, "PSS2.PS7_EMIOTTC0WAVEO2->PSS2_LOGIC_OUTS2_89": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_89", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTTC0WAVEO2" }, "PSS2.PS7_EMIOTTC1WAVEO0->PSS2_LOGIC_OUTS0_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTTC1WAVEO0" }, "PSS2.PS7_EMIOTTC1WAVEO1->PSS2_LOGIC_OUTS1_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTTC1WAVEO1" }, "PSS2.PS7_EMIOTTC1WAVEO2->PSS2_LOGIC_OUTS2_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOTTC1WAVEO2" }, "PSS2.PS7_EMIOUART0DTRN->PSS2_LOGIC_OUTS10_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOUART0DTRN" }, "PSS2.PS7_EMIOUART0RTSN->PSS2_LOGIC_OUTS9_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOUART0RTSN" }, "PSS2.PS7_EMIOUART0TX->PSS2_LOGIC_OUTS8_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOUART0TX" }, "PSS2.PS7_EMIOUART1DTRN->PSS2_LOGIC_OUTS11_89": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_89", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOUART1DTRN" }, "PSS2.PS7_EMIOUART1RTSN->PSS2_LOGIC_OUTS10_89": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_89", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOUART1RTSN" }, "PSS2.PS7_EMIOUART1TX->PSS2_LOGIC_OUTS9_89": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_89", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOUART1TX" }, "PSS2.PS7_EMIOUSB0PORTINDCTL0->PSS2_LOGIC_OUTS10_98": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_98", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOUSB0PORTINDCTL0" }, "PSS2.PS7_EMIOUSB0PORTINDCTL1->PSS2_LOGIC_OUTS11_98": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_98", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOUSB0PORTINDCTL1" }, "PSS2.PS7_EMIOUSB0VBUSPWRSELECT->PSS2_LOGIC_OUTS12_98": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_98", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOUSB0VBUSPWRSELECT" }, "PSS2.PS7_EMIOUSB1PORTINDCTL0->PSS2_LOGIC_OUTS10_93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOUSB1PORTINDCTL0" }, "PSS2.PS7_EMIOUSB1PORTINDCTL1->PSS2_LOGIC_OUTS9_95": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_95", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOUSB1PORTINDCTL1" }, "PSS2.PS7_EMIOUSB1VBUSPWRSELECT->PSS2_LOGIC_OUTS12_94": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_94", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOUSB1VBUSPWRSELECT" }, "PSS2.PS7_EMIOWDTRSTO->PSS2_LOGIC_OUTS3_89": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_89", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EMIOWDTRSTO" }, "PSS2.PS7_EVENTEVENTO->PSS2_LOGIC_OUTS0_64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EVENTEVENTO" }, "PSS2.PS7_EVENTSTANDBYWFE0->PSS2_LOGIC_OUTS1_64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EVENTSTANDBYWFE0" }, "PSS2.PS7_EVENTSTANDBYWFE1->PSS2_LOGIC_OUTS2_64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EVENTSTANDBYWFE1" }, "PSS2.PS7_EVENTSTANDBYWFI0->PSS2_LOGIC_OUTS0_63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EVENTSTANDBYWFI0" }, "PSS2.PS7_EVENTSTANDBYWFI1->PSS2_LOGIC_OUTS1_63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_EVENTSTANDBYWFI1" }, "PSS2.PS7_FCLKCLK0->PSS1_LOGIC_OUTS1_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FCLKCLK0" }, "PSS2.PS7_FCLKCLK0->PSS_FCLKCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_FCLKCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FCLKCLK0" }, "PSS2.PS7_FCLKCLK1->PSS1_LOGIC_OUTS2_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FCLKCLK1" }, "PSS2.PS7_FCLKCLK1->PSS_FCLKCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_FCLKCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FCLKCLK1" }, "PSS2.PS7_FCLKCLK2->PSS2_FCLKCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_FCLKCLK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FCLKCLK2" }, "PSS2.PS7_FCLKCLK2->PSS2_LOGIC_OUTS0_61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FCLKCLK2" }, "PSS2.PS7_FCLKCLK3->PSS2_FCLKCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_FCLKCLK3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FCLKCLK3" }, "PSS2.PS7_FCLKCLK3->PSS2_LOGIC_OUTS1_61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FCLKCLK3" }, "PSS2.PS7_FCLKRESETN0->PSS1_LOGIC_OUTS3_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FCLKRESETN0" }, "PSS2.PS7_FCLKRESETN1->PSS1_LOGIC_OUTS4_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FCLKRESETN1" }, "PSS2.PS7_FCLKRESETN2->PSS2_LOGIC_OUTS0_62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FCLKRESETN2" }, "PSS2.PS7_FCLKRESETN3->PSS2_LOGIC_OUTS1_62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FCLKRESETN3" }, "PSS2.PS7_FTMTF2PTRIGACK0->PSS2_LOGIC_OUTS2_61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTF2PTRIGACK0" }, "PSS2.PS7_FTMTF2PTRIGACK1->PSS2_LOGIC_OUTS2_63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTF2PTRIGACK1" }, "PSS2.PS7_FTMTF2PTRIGACK2->PSS2_LOGIC_OUTS7_65": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_65", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTF2PTRIGACK2" }, "PSS2.PS7_FTMTF2PTRIGACK3->PSS2_LOGIC_OUTS10_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTF2PTRIGACK3" }, "PSS2.PS7_FTMTP2FDEBUG0->PSS2_LOGIC_OUTS1_60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS1_60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG0" }, "PSS2.PS7_FTMTP2FDEBUG1->PSS2_LOGIC_OUTS2_60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG1" }, "PSS2.PS7_FTMTP2FDEBUG10->PSS2_LOGIC_OUTS5_62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG10" }, "PSS2.PS7_FTMTP2FDEBUG11->PSS2_LOGIC_OUTS6_62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG11" }, "PSS2.PS7_FTMTP2FDEBUG12->PSS2_LOGIC_OUTS3_63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG12" }, "PSS2.PS7_FTMTP2FDEBUG13->PSS2_LOGIC_OUTS4_63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG13" }, "PSS2.PS7_FTMTP2FDEBUG14->PSS2_LOGIC_OUTS5_63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG14" }, "PSS2.PS7_FTMTP2FDEBUG15->PSS2_LOGIC_OUTS6_63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG15" }, "PSS2.PS7_FTMTP2FDEBUG16->PSS2_LOGIC_OUTS4_64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG16" }, "PSS2.PS7_FTMTP2FDEBUG17->PSS2_LOGIC_OUTS5_64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG17" }, "PSS2.PS7_FTMTP2FDEBUG18->PSS2_LOGIC_OUTS6_64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG18" }, "PSS2.PS7_FTMTP2FDEBUG19->PSS2_LOGIC_OUTS7_64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG19" }, "PSS2.PS7_FTMTP2FDEBUG2->PSS2_LOGIC_OUTS3_60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG2" }, "PSS2.PS7_FTMTP2FDEBUG20->PSS2_LOGIC_OUTS8_65": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_65", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG20" }, "PSS2.PS7_FTMTP2FDEBUG21->PSS2_LOGIC_OUTS9_65": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_65", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG21" }, "PSS2.PS7_FTMTP2FDEBUG22->PSS2_LOGIC_OUTS10_65": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_65", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG22" }, "PSS2.PS7_FTMTP2FDEBUG23->PSS2_LOGIC_OUTS11_65": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_65", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG23" }, "PSS2.PS7_FTMTP2FDEBUG24->PSS2_LOGIC_OUTS11_66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG24" }, "PSS2.PS7_FTMTP2FDEBUG25->PSS2_LOGIC_OUTS12_66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG25" }, "PSS2.PS7_FTMTP2FDEBUG26->PSS2_LOGIC_OUTS13_66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG26" }, "PSS2.PS7_FTMTP2FDEBUG27->PSS2_LOGIC_OUTS14_66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG27" }, "PSS2.PS7_FTMTP2FDEBUG28->PSS2_LOGIC_OUTS11_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG28" }, "PSS2.PS7_FTMTP2FDEBUG29->PSS2_LOGIC_OUTS12_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG29" }, "PSS2.PS7_FTMTP2FDEBUG3->PSS2_LOGIC_OUTS4_60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG3" }, "PSS2.PS7_FTMTP2FDEBUG30->PSS2_LOGIC_OUTS13_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG30" }, "PSS2.PS7_FTMTP2FDEBUG31->PSS2_LOGIC_OUTS14_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG31" }, "PSS2.PS7_FTMTP2FDEBUG4->PSS2_LOGIC_OUTS3_61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG4" }, "PSS2.PS7_FTMTP2FDEBUG5->PSS2_LOGIC_OUTS4_61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG5" }, "PSS2.PS7_FTMTP2FDEBUG6->PSS2_LOGIC_OUTS5_61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG6" }, "PSS2.PS7_FTMTP2FDEBUG7->PSS2_LOGIC_OUTS6_61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG7" }, "PSS2.PS7_FTMTP2FDEBUG8->PSS2_LOGIC_OUTS3_62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG8" }, "PSS2.PS7_FTMTP2FDEBUG9->PSS2_LOGIC_OUTS4_62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS4_62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FDEBUG9" }, "PSS2.PS7_FTMTP2FTRIG0->PSS2_LOGIC_OUTS0_60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS0_60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FTRIG0" }, "PSS2.PS7_FTMTP2FTRIG1->PSS2_LOGIC_OUTS2_62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS2_62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FTRIG1" }, "PSS2.PS7_FTMTP2FTRIG2->PSS2_LOGIC_OUTS3_64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS3_64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FTRIG2" }, "PSS2.PS7_FTMTP2FTRIG3->PSS2_LOGIC_OUTS10_66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_FTMTP2FTRIG3" }, "PSS2.PS7_IRQP2F0->PSS2_LOGIC_OUTS6_65": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_65", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F0" }, "PSS2.PS7_IRQP2F1->PSS2_LOGIC_OUTS6_66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F1" }, "PSS2.PS7_IRQP2F10->PSS2_LOGIC_OUTS6_68": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_68", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F10" }, "PSS2.PS7_IRQP2F11->PSS2_LOGIC_OUTS7_68": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_68", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F11" }, "PSS2.PS7_IRQP2F12->PSS2_LOGIC_OUTS8_68": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_68", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F12" }, "PSS2.PS7_IRQP2F13->PSS2_LOGIC_OUTS6_69": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_69", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F13" }, "PSS2.PS7_IRQP2F14->PSS2_LOGIC_OUTS7_69": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_69", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F14" }, "PSS2.PS7_IRQP2F15->PSS2_LOGIC_OUTS8_69": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_69", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F15" }, "PSS2.PS7_IRQP2F16->PSS2_LOGIC_OUTS9_69": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_69", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F16" }, "PSS2.PS7_IRQP2F17->PSS2_LOGIC_OUTS6_70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_70", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F17" }, "PSS2.PS7_IRQP2F18->PSS2_LOGIC_OUTS7_70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_70", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F18" }, "PSS2.PS7_IRQP2F19->PSS2_LOGIC_OUTS8_70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_70", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F19" }, "PSS2.PS7_IRQP2F2->PSS2_LOGIC_OUTS7_66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F2" }, "PSS2.PS7_IRQP2F20->PSS2_LOGIC_OUTS9_70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_70", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F20" }, "PSS2.PS7_IRQP2F21->PSS2_LOGIC_OUTS6_71": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_71", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F21" }, "PSS2.PS7_IRQP2F22->PSS2_LOGIC_OUTS7_71": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_71", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F22" }, "PSS2.PS7_IRQP2F23->PSS2_LOGIC_OUTS8_71": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_71", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F23" }, "PSS2.PS7_IRQP2F24->PSS2_LOGIC_OUTS9_71": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_71", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F24" }, "PSS2.PS7_IRQP2F25->PSS2_LOGIC_OUTS5_72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F25" }, "PSS2.PS7_IRQP2F26->PSS2_LOGIC_OUTS6_72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F26" }, "PSS2.PS7_IRQP2F27->PSS2_LOGIC_OUTS7_72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F27" }, "PSS2.PS7_IRQP2F28->PSS2_LOGIC_OUTS8_72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F28" }, "PSS2.PS7_IRQP2F3->PSS2_LOGIC_OUTS8_66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F3" }, "PSS2.PS7_IRQP2F4->PSS2_LOGIC_OUTS9_66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F4" }, "PSS2.PS7_IRQP2F5->PSS2_LOGIC_OUTS6_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS6_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F5" }, "PSS2.PS7_IRQP2F6->PSS2_LOGIC_OUTS7_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS7_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F6" }, "PSS2.PS7_IRQP2F7->PSS2_LOGIC_OUTS8_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F7" }, "PSS2.PS7_IRQP2F8->PSS2_LOGIC_OUTS9_67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F8" }, "PSS2.PS7_IRQP2F9->PSS2_LOGIC_OUTS5_68": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS5_68", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_IRQP2F9" }, "PSS2.PS7_MAXIGP0ARADDR0->PSS_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR0" }, "PSS2.PS7_MAXIGP0ARADDR1->PSS_LOGIC_OUTS6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR1" }, "PSS2.PS7_MAXIGP0ARADDR10->PSS_LOGIC_OUTS14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR10" }, "PSS2.PS7_MAXIGP0ARADDR11->PSS_LOGIC_OUTS15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR11" }, "PSS2.PS7_MAXIGP0ARADDR12->PSS_LOGIC_OUTS15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR12" }, "PSS2.PS7_MAXIGP0ARADDR13->PSS_LOGIC_OUTS16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR13" }, "PSS2.PS7_MAXIGP0ARADDR14->PSS_LOGIC_OUTS17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR14" }, "PSS2.PS7_MAXIGP0ARADDR15->PSS_LOGIC_OUTS18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR15" }, "PSS2.PS7_MAXIGP0ARADDR16->PSS_LOGIC_OUTS14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR16" }, "PSS2.PS7_MAXIGP0ARADDR17->PSS_LOGIC_OUTS15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR17" }, "PSS2.PS7_MAXIGP0ARADDR18->PSS_LOGIC_OUTS16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR18" }, "PSS2.PS7_MAXIGP0ARADDR19->PSS_LOGIC_OUTS17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR19" }, "PSS2.PS7_MAXIGP0ARADDR2->PSS_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR2" }, "PSS2.PS7_MAXIGP0ARADDR20->PSS_LOGIC_OUTS14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR20" }, "PSS2.PS7_MAXIGP0ARADDR21->PSS_LOGIC_OUTS15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR21" }, "PSS2.PS7_MAXIGP0ARADDR22->PSS_LOGIC_OUTS16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR22" }, "PSS2.PS7_MAXIGP0ARADDR23->PSS_LOGIC_OUTS17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR23" }, "PSS2.PS7_MAXIGP0ARADDR24->PSS_LOGIC_OUTS11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR24" }, "PSS2.PS7_MAXIGP0ARADDR25->PSS_LOGIC_OUTS12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR25" }, "PSS2.PS7_MAXIGP0ARADDR26->PSS_LOGIC_OUTS13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR26" }, "PSS2.PS7_MAXIGP0ARADDR27->PSS_LOGIC_OUTS14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR27" }, "PSS2.PS7_MAXIGP0ARADDR28->PSS_LOGIC_OUTS17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR28" }, "PSS2.PS7_MAXIGP0ARADDR29->PSS_LOGIC_OUTS18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR29" }, "PSS2.PS7_MAXIGP0ARADDR3->PSS_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR3" }, "PSS2.PS7_MAXIGP0ARADDR30->PSS_LOGIC_OUTS17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR30" }, "PSS2.PS7_MAXIGP0ARADDR31->PSS_LOGIC_OUTS18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR31" }, "PSS2.PS7_MAXIGP0ARADDR4->PSS_LOGIC_OUTS6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR4" }, "PSS2.PS7_MAXIGP0ARADDR5->PSS_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR5" }, "PSS2.PS7_MAXIGP0ARADDR6->PSS_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR6" }, "PSS2.PS7_MAXIGP0ARADDR7->PSS_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR7" }, "PSS2.PS7_MAXIGP0ARADDR8->PSS_LOGIC_OUTS12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR8" }, "PSS2.PS7_MAXIGP0ARADDR9->PSS_LOGIC_OUTS13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARADDR9" }, "PSS2.PS7_MAXIGP0ARBURST0->PSS_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARBURST0" }, "PSS2.PS7_MAXIGP0ARBURST1->PSS_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARBURST1" }, "PSS2.PS7_MAXIGP0ARCACHE0->PSS_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARCACHE0" }, "PSS2.PS7_MAXIGP0ARCACHE1->PSS_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARCACHE1" }, "PSS2.PS7_MAXIGP0ARCACHE2->PSS_LOGIC_OUTS13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARCACHE2" }, "PSS2.PS7_MAXIGP0ARCACHE3->PSS_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARCACHE3" }, "PSS2.PS7_MAXIGP0ARESETN->PSS_LOGIC_OUTS0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARESETN" }, "PSS2.PS7_MAXIGP0ARID0->PSS_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARID0" }, "PSS2.PS7_MAXIGP0ARID1->PSS_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARID1" }, "PSS2.PS7_MAXIGP0ARID10->PSS_LOGIC_OUTS11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARID10" }, "PSS2.PS7_MAXIGP0ARID11->PSS_LOGIC_OUTS14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARID11" }, "PSS2.PS7_MAXIGP0ARID2->PSS_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARID2" }, "PSS2.PS7_MAXIGP0ARID3->PSS_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARID3" }, "PSS2.PS7_MAXIGP0ARID4->PSS_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARID4" }, "PSS2.PS7_MAXIGP0ARID5->PSS_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARID5" }, "PSS2.PS7_MAXIGP0ARID6->PSS_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARID6" }, "PSS2.PS7_MAXIGP0ARID7->PSS_LOGIC_OUTS8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARID7" }, "PSS2.PS7_MAXIGP0ARID8->PSS_LOGIC_OUTS9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARID8" }, "PSS2.PS7_MAXIGP0ARID9->PSS_LOGIC_OUTS10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARID9" }, "PSS2.PS7_MAXIGP0ARLEN0->PSS_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARLEN0" }, "PSS2.PS7_MAXIGP0ARLEN1->PSS_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARLEN1" }, "PSS2.PS7_MAXIGP0ARLEN2->PSS_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARLEN2" }, "PSS2.PS7_MAXIGP0ARLEN3->PSS_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARLEN3" }, "PSS2.PS7_MAXIGP0ARLOCK0->PSS_LOGIC_OUTS16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARLOCK0" }, "PSS2.PS7_MAXIGP0ARLOCK1->PSS_LOGIC_OUTS17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARLOCK1" }, "PSS2.PS7_MAXIGP0ARPROT0->PSS_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARPROT0" }, "PSS2.PS7_MAXIGP0ARPROT1->PSS_LOGIC_OUTS16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARPROT1" }, "PSS2.PS7_MAXIGP0ARPROT2->PSS_LOGIC_OUTS17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARPROT2" }, "PSS2.PS7_MAXIGP0ARQOS0->PSS_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARQOS0" }, "PSS2.PS7_MAXIGP0ARQOS1->PSS_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARQOS1" }, "PSS2.PS7_MAXIGP0ARQOS2->PSS_LOGIC_OUTS16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARQOS2" }, "PSS2.PS7_MAXIGP0ARQOS3->PSS_LOGIC_OUTS17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARQOS3" }, "PSS2.PS7_MAXIGP0ARSIZE0->PSS_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARSIZE0" }, "PSS2.PS7_MAXIGP0ARSIZE1->PSS_LOGIC_OUTS13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARSIZE1" }, "PSS2.PS7_MAXIGP0ARVALID->PSS_LOGIC_OUTS18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0ARVALID" }, "PSS2.PS7_MAXIGP0AWADDR0->PSS_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR0" }, "PSS2.PS7_MAXIGP0AWADDR1->PSS_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR1" }, "PSS2.PS7_MAXIGP0AWADDR10->PSS_LOGIC_OUTS3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR10" }, "PSS2.PS7_MAXIGP0AWADDR11->PSS_LOGIC_OUTS4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR11" }, "PSS2.PS7_MAXIGP0AWADDR12->PSS_LOGIC_OUTS0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR12" }, "PSS2.PS7_MAXIGP0AWADDR13->PSS_LOGIC_OUTS1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR13" }, "PSS2.PS7_MAXIGP0AWADDR14->PSS_LOGIC_OUTS2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR14" }, "PSS2.PS7_MAXIGP0AWADDR15->PSS_LOGIC_OUTS3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR15" }, "PSS2.PS7_MAXIGP0AWADDR16->PSS_LOGIC_OUTS1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR16" }, "PSS2.PS7_MAXIGP0AWADDR17->PSS_LOGIC_OUTS2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR17" }, "PSS2.PS7_MAXIGP0AWADDR18->PSS_LOGIC_OUTS3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR18" }, "PSS2.PS7_MAXIGP0AWADDR19->PSS_LOGIC_OUTS4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR19" }, "PSS2.PS7_MAXIGP0AWADDR2->PSS_LOGIC_OUTS1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR2" }, "PSS2.PS7_MAXIGP0AWADDR20->PSS_LOGIC_OUTS4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR20" }, "PSS2.PS7_MAXIGP0AWADDR21->PSS_LOGIC_OUTS5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR21" }, "PSS2.PS7_MAXIGP0AWADDR22->PSS_LOGIC_OUTS6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR22" }, "PSS2.PS7_MAXIGP0AWADDR23->PSS_LOGIC_OUTS7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR23" }, "PSS2.PS7_MAXIGP0AWADDR24->PSS_LOGIC_OUTS3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR24" }, "PSS2.PS7_MAXIGP0AWADDR25->PSS_LOGIC_OUTS4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR25" }, "PSS2.PS7_MAXIGP0AWADDR26->PSS_LOGIC_OUTS5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR26" }, "PSS2.PS7_MAXIGP0AWADDR27->PSS_LOGIC_OUTS6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR27" }, "PSS2.PS7_MAXIGP0AWADDR28->PSS_LOGIC_OUTS4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR28" }, "PSS2.PS7_MAXIGP0AWADDR29->PSS_LOGIC_OUTS5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR29" }, "PSS2.PS7_MAXIGP0AWADDR3->PSS_LOGIC_OUTS2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR3" }, "PSS2.PS7_MAXIGP0AWADDR30->PSS_LOGIC_OUTS6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR30" }, "PSS2.PS7_MAXIGP0AWADDR31->PSS_LOGIC_OUTS7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR31" }, "PSS2.PS7_MAXIGP0AWADDR4->PSS_LOGIC_OUTS1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR4" }, "PSS2.PS7_MAXIGP0AWADDR5->PSS_LOGIC_OUTS2_3": { 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"PS7_MAXIGP0AWADDR7" }, "PSS2.PS7_MAXIGP0AWADDR8->PSS_LOGIC_OUTS1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR8" }, "PSS2.PS7_MAXIGP0AWADDR9->PSS_LOGIC_OUTS2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWADDR9" }, "PSS2.PS7_MAXIGP0AWBURST0->PSS_LOGIC_OUTS10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWBURST0" }, "PSS2.PS7_MAXIGP0AWBURST1->PSS_LOGIC_OUTS11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWBURST1" }, "PSS2.PS7_MAXIGP0AWCACHE0->PSS_LOGIC_OUTS8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWCACHE0" }, "PSS2.PS7_MAXIGP0AWCACHE1->PSS_LOGIC_OUTS9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_3", "is_directional": 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"0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWID0" }, "PSS2.PS7_MAXIGP0AWID1->PSS_LOGIC_OUTS0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWID1" }, "PSS2.PS7_MAXIGP0AWID10->PSS_LOGIC_OUTS2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWID10" }, "PSS2.PS7_MAXIGP0AWID11->PSS_LOGIC_OUTS3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWID11" }, "PSS2.PS7_MAXIGP0AWID2->PSS_LOGIC_OUTS1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWID2" }, "PSS2.PS7_MAXIGP0AWID3->PSS_LOGIC_OUTS2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWID3" }, 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"res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWID6" }, "PSS2.PS7_MAXIGP0AWID7->PSS_LOGIC_OUTS2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWID7" }, "PSS2.PS7_MAXIGP0AWID8->PSS_LOGIC_OUTS0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWID8" }, "PSS2.PS7_MAXIGP0AWID9->PSS_LOGIC_OUTS1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWID9" }, "PSS2.PS7_MAXIGP0AWLEN0->PSS_LOGIC_OUTS3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWLEN0" }, "PSS2.PS7_MAXIGP0AWLEN1->PSS_LOGIC_OUTS5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWLEN1" }, "PSS2.PS7_MAXIGP0AWLEN2->PSS_LOGIC_OUTS6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_3", 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null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWLOCK1" }, "PSS2.PS7_MAXIGP0AWPROT0->PSS_LOGIC_OUTS7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWPROT0" }, "PSS2.PS7_MAXIGP0AWPROT1->PSS_LOGIC_OUTS8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWPROT1" }, "PSS2.PS7_MAXIGP0AWPROT2->PSS_LOGIC_OUTS4_5": { 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"PS7_MAXIGP0AWQOS1" }, "PSS2.PS7_MAXIGP0AWQOS2->PSS_LOGIC_OUTS17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWQOS2" }, "PSS2.PS7_MAXIGP0AWQOS3->PSS_LOGIC_OUTS18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWQOS3" }, "PSS2.PS7_MAXIGP0AWSIZE0->PSS_LOGIC_OUTS8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWSIZE0" }, "PSS2.PS7_MAXIGP0AWSIZE1->PSS_LOGIC_OUTS9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWSIZE1" }, "PSS2.PS7_MAXIGP0AWVALID->PSS_LOGIC_OUTS5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0AWVALID" }, "PSS2.PS7_MAXIGP0BREADY->PSS_LOGIC_OUTS13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_5", "is_directional": "1", + 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"dst_wire": "PSS_LOGIC_OUTS5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA1" }, "PSS2.PS7_MAXIGP0WDATA10->PSS_LOGIC_OUTS12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA10" }, "PSS2.PS7_MAXIGP0WDATA11->PSS_LOGIC_OUTS13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA11" }, "PSS2.PS7_MAXIGP0WDATA12->PSS_LOGIC_OUTS8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA12" }, "PSS2.PS7_MAXIGP0WDATA13->PSS_LOGIC_OUTS9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA13" }, "PSS2.PS7_MAXIGP0WDATA14->PSS_LOGIC_OUTS10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA14" }, "PSS2.PS7_MAXIGP0WDATA15->PSS_LOGIC_OUTS11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA15" }, "PSS2.PS7_MAXIGP0WDATA16->PSS_LOGIC_OUTS7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA16" }, "PSS2.PS7_MAXIGP0WDATA17->PSS_LOGIC_OUTS8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA17" }, "PSS2.PS7_MAXIGP0WDATA18->PSS_LOGIC_OUTS9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA18" }, "PSS2.PS7_MAXIGP0WDATA19->PSS_LOGIC_OUTS10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA19" }, "PSS2.PS7_MAXIGP0WDATA2->PSS_LOGIC_OUTS6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA2" }, "PSS2.PS7_MAXIGP0WDATA20->PSS_LOGIC_OUTS11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA20" }, "PSS2.PS7_MAXIGP0WDATA21->PSS_LOGIC_OUTS12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA21" }, "PSS2.PS7_MAXIGP0WDATA22->PSS_LOGIC_OUTS13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA22" }, "PSS2.PS7_MAXIGP0WDATA23->PSS_LOGIC_OUTS14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA23" }, "PSS2.PS7_MAXIGP0WDATA24->PSS_LOGIC_OUTS11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA24" }, "PSS2.PS7_MAXIGP0WDATA25->PSS_LOGIC_OUTS12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA25" }, "PSS2.PS7_MAXIGP0WDATA26->PSS_LOGIC_OUTS13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA26" }, "PSS2.PS7_MAXIGP0WDATA27->PSS_LOGIC_OUTS14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA27" }, "PSS2.PS7_MAXIGP0WDATA28->PSS_LOGIC_OUTS14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA28" }, "PSS2.PS7_MAXIGP0WDATA29->PSS_LOGIC_OUTS15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA29" }, "PSS2.PS7_MAXIGP0WDATA3->PSS_LOGIC_OUTS7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA3" }, "PSS2.PS7_MAXIGP0WDATA30->PSS_LOGIC_OUTS16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA30" }, "PSS2.PS7_MAXIGP0WDATA31->PSS_LOGIC_OUTS17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA31" }, "PSS2.PS7_MAXIGP0WDATA4->PSS_LOGIC_OUTS10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA4" }, "PSS2.PS7_MAXIGP0WDATA5->PSS_LOGIC_OUTS11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA5" }, "PSS2.PS7_MAXIGP0WDATA6->PSS_LOGIC_OUTS12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA6" }, "PSS2.PS7_MAXIGP0WDATA7->PSS_LOGIC_OUTS13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA7" }, "PSS2.PS7_MAXIGP0WDATA8->PSS_LOGIC_OUTS10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA8" }, "PSS2.PS7_MAXIGP0WDATA9->PSS_LOGIC_OUTS11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WDATA9" }, "PSS2.PS7_MAXIGP0WID0->PSS_LOGIC_OUTS9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WID0" }, "PSS2.PS7_MAXIGP0WID1->PSS_LOGIC_OUTS6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WID1" }, "PSS2.PS7_MAXIGP0WID10->PSS_LOGIC_OUTS9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WID10" }, "PSS2.PS7_MAXIGP0WID11->PSS_LOGIC_OUTS10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WID11" }, "PSS2.PS7_MAXIGP0WID2->PSS_LOGIC_OUTS7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WID2" }, "PSS2.PS7_MAXIGP0WID3->PSS_LOGIC_OUTS5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WID3" }, "PSS2.PS7_MAXIGP0WID4->PSS_LOGIC_OUTS6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WID4" }, "PSS2.PS7_MAXIGP0WID5->PSS_LOGIC_OUTS8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WID5" }, "PSS2.PS7_MAXIGP0WID6->PSS_LOGIC_OUTS9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WID6" }, "PSS2.PS7_MAXIGP0WID7->PSS_LOGIC_OUTS10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WID7" }, "PSS2.PS7_MAXIGP0WID8->PSS_LOGIC_OUTS7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WID8" }, "PSS2.PS7_MAXIGP0WID9->PSS_LOGIC_OUTS8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WID9" }, "PSS2.PS7_MAXIGP0WLAST->PSS_LOGIC_OUTS18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WLAST" }, "PSS2.PS7_MAXIGP0WSTRB0->PSS_LOGIC_OUTS15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WSTRB0" }, "PSS2.PS7_MAXIGP0WSTRB1->PSS_LOGIC_OUTS16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WSTRB1" }, "PSS2.PS7_MAXIGP0WSTRB2->PSS_LOGIC_OUTS15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WSTRB2" }, "PSS2.PS7_MAXIGP0WSTRB3->PSS_LOGIC_OUTS16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WSTRB3" }, "PSS2.PS7_MAXIGP0WVALID->PSS_LOGIC_OUTS12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP0WVALID" }, "PSS2.PS7_MAXIGP1ARADDR0->PSS_LOGIC_OUTS4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR0" }, "PSS2.PS7_MAXIGP1ARADDR1->PSS_LOGIC_OUTS5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR1" }, "PSS2.PS7_MAXIGP1ARADDR10->PSS_LOGIC_OUTS13_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR10" }, "PSS2.PS7_MAXIGP1ARADDR11->PSS_LOGIC_OUTS14_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR11" }, "PSS2.PS7_MAXIGP1ARADDR12->PSS_LOGIC_OUTS14_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR12" }, "PSS2.PS7_MAXIGP1ARADDR13->PSS_LOGIC_OUTS15_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR13" }, "PSS2.PS7_MAXIGP1ARADDR14->PSS_LOGIC_OUTS16_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR14" }, "PSS2.PS7_MAXIGP1ARADDR15->PSS_LOGIC_OUTS17_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR15" }, "PSS2.PS7_MAXIGP1ARADDR16->PSS_LOGIC_OUTS14_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR16" }, "PSS2.PS7_MAXIGP1ARADDR17->PSS_LOGIC_OUTS15_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR17" }, "PSS2.PS7_MAXIGP1ARADDR18->PSS_LOGIC_OUTS16_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR18" }, "PSS2.PS7_MAXIGP1ARADDR19->PSS_LOGIC_OUTS17_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR19" }, "PSS2.PS7_MAXIGP1ARADDR2->PSS_LOGIC_OUTS6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR2" }, "PSS2.PS7_MAXIGP1ARADDR20->PSS_LOGIC_OUTS14_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR20" }, "PSS2.PS7_MAXIGP1ARADDR21->PSS_LOGIC_OUTS15_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR21" }, "PSS2.PS7_MAXIGP1ARADDR22->PSS_LOGIC_OUTS16_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR22" }, "PSS2.PS7_MAXIGP1ARADDR23->PSS_LOGIC_OUTS17_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR23" }, "PSS2.PS7_MAXIGP1ARADDR24->PSS_LOGIC_OUTS11_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR24" }, "PSS2.PS7_MAXIGP1ARADDR25->PSS_LOGIC_OUTS12_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR25" }, "PSS2.PS7_MAXIGP1ARADDR26->PSS_LOGIC_OUTS13_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR26" }, "PSS2.PS7_MAXIGP1ARADDR27->PSS_LOGIC_OUTS14_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR27" }, "PSS2.PS7_MAXIGP1ARADDR28->PSS_LOGIC_OUTS17_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR28" }, "PSS2.PS7_MAXIGP1ARADDR29->PSS_LOGIC_OUTS18_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR29" }, "PSS2.PS7_MAXIGP1ARADDR3->PSS_LOGIC_OUTS7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR3" }, "PSS2.PS7_MAXIGP1ARADDR30->PSS_LOGIC_OUTS17_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR30" }, "PSS2.PS7_MAXIGP1ARADDR31->PSS_LOGIC_OUTS18_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR31" }, "PSS2.PS7_MAXIGP1ARADDR4->PSS_LOGIC_OUTS5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR4" }, "PSS2.PS7_MAXIGP1ARADDR5->PSS_LOGIC_OUTS6_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR5" }, "PSS2.PS7_MAXIGP1ARADDR6->PSS_LOGIC_OUTS7_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR6" }, "PSS2.PS7_MAXIGP1ARADDR7->PSS_LOGIC_OUTS8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR7" }, "PSS2.PS7_MAXIGP1ARADDR8->PSS_LOGIC_OUTS11_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR8" }, "PSS2.PS7_MAXIGP1ARADDR9->PSS_LOGIC_OUTS12_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARADDR9" }, "PSS2.PS7_MAXIGP1ARBURST0->PSS_LOGIC_OUTS13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARBURST0" }, "PSS2.PS7_MAXIGP1ARBURST1->PSS_LOGIC_OUTS14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARBURST1" }, "PSS2.PS7_MAXIGP1ARCACHE0->PSS_LOGIC_OUTS10_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARCACHE0" }, "PSS2.PS7_MAXIGP1ARCACHE1->PSS_LOGIC_OUTS11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARCACHE1" }, "PSS2.PS7_MAXIGP1ARCACHE2->PSS_LOGIC_OUTS12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARCACHE2" }, "PSS2.PS7_MAXIGP1ARCACHE3->PSS_LOGIC_OUTS13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARCACHE3" }, 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null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARID1" }, "PSS2.PS7_MAXIGP1ARID10->PSS_LOGIC_OUTS10_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARID10" }, "PSS2.PS7_MAXIGP1ARID11->PSS_LOGIC_OUTS13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARID11" }, "PSS2.PS7_MAXIGP1ARID2->PSS_LOGIC_OUTS2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_10", "is_directional": "1", + "is_pass_transistor": 1, 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null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARID8" }, "PSS2.PS7_MAXIGP1ARID9->PSS_LOGIC_OUTS9_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARID9" }, "PSS2.PS7_MAXIGP1ARLEN0->PSS_LOGIC_OUTS8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARLEN0" }, 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null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARLEN3" }, "PSS2.PS7_MAXIGP1ARLOCK0->PSS_LOGIC_OUTS15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARLOCK0" }, "PSS2.PS7_MAXIGP1ARLOCK1->PSS_LOGIC_OUTS16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1ARLOCK1" }, "PSS2.PS7_MAXIGP1ARPROT0->PSS_LOGIC_OUTS14_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_11", "is_directional": "1", + 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+ "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1AWADDR15" }, "PSS2.PS7_MAXIGP1AWADDR16->PSS_LOGIC_OUTS1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1AWADDR16" }, "PSS2.PS7_MAXIGP1AWADDR17->PSS_LOGIC_OUTS2_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1AWADDR17" }, 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"0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WDATA9" }, "PSS2.PS7_MAXIGP1WID0->PSS_LOGIC_OUTS9_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WID0" }, "PSS2.PS7_MAXIGP1WID1->PSS_LOGIC_OUTS6_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WID1" }, "PSS2.PS7_MAXIGP1WID10->PSS_LOGIC_OUTS9_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WID10" }, "PSS2.PS7_MAXIGP1WID11->PSS_LOGIC_OUTS10_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WID11" }, "PSS2.PS7_MAXIGP1WID2->PSS_LOGIC_OUTS7_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WID2" }, "PSS2.PS7_MAXIGP1WID3->PSS_LOGIC_OUTS5_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WID3" }, "PSS2.PS7_MAXIGP1WID4->PSS_LOGIC_OUTS6_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WID4" }, "PSS2.PS7_MAXIGP1WID5->PSS_LOGIC_OUTS8_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WID5" }, "PSS2.PS7_MAXIGP1WID6->PSS_LOGIC_OUTS9_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WID6" }, "PSS2.PS7_MAXIGP1WID7->PSS_LOGIC_OUTS10_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WID7" }, "PSS2.PS7_MAXIGP1WID8->PSS_LOGIC_OUTS7_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WID8" }, "PSS2.PS7_MAXIGP1WID9->PSS_LOGIC_OUTS8_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WID9" }, "PSS2.PS7_MAXIGP1WLAST->PSS_LOGIC_OUTS18_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WLAST" }, "PSS2.PS7_MAXIGP1WSTRB0->PSS_LOGIC_OUTS15_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WSTRB0" }, "PSS2.PS7_MAXIGP1WSTRB1->PSS_LOGIC_OUTS16_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WSTRB1" }, "PSS2.PS7_MAXIGP1WSTRB2->PSS_LOGIC_OUTS15_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WSTRB2" }, "PSS2.PS7_MAXIGP1WSTRB3->PSS_LOGIC_OUTS16_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WSTRB3" }, "PSS2.PS7_MAXIGP1WVALID->PSS_LOGIC_OUTS12_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_MAXIGP1WVALID" }, "PSS2.PS7_SAXIACPARESETN->PSS1_LOGIC_OUTS0_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPARESETN" }, "PSS2.PS7_SAXIACPARREADY->PSS1_LOGIC_OUTS2_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPARREADY" }, "PSS2.PS7_SAXIACPAWREADY->PSS1_LOGIC_OUTS1_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPAWREADY" }, "PSS2.PS7_SAXIACPBID0->PSS1_LOGIC_OUTS0_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPBID0" }, "PSS2.PS7_SAXIACPBID1->PSS1_LOGIC_OUTS1_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPBID1" }, "PSS2.PS7_SAXIACPBID2->PSS1_LOGIC_OUTS2_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPBID2" }, "PSS2.PS7_SAXIACPBRESP0->PSS1_LOGIC_OUTS1_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPBRESP0" }, "PSS2.PS7_SAXIACPBRESP1->PSS1_LOGIC_OUTS2_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPBRESP1" }, "PSS2.PS7_SAXIACPBVALID->PSS1_LOGIC_OUTS2_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPBVALID" }, "PSS2.PS7_SAXIACPRDATA0->PSS1_LOGIC_OUTS6_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA0" }, "PSS2.PS7_SAXIACPRDATA1->PSS1_LOGIC_OUTS7_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA1" }, "PSS2.PS7_SAXIACPRDATA10->PSS1_LOGIC_OUTS7_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA10" }, "PSS2.PS7_SAXIACPRDATA11->PSS1_LOGIC_OUTS8_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA11" }, "PSS2.PS7_SAXIACPRDATA12->PSS1_LOGIC_OUTS4_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA12" }, "PSS2.PS7_SAXIACPRDATA13->PSS1_LOGIC_OUTS5_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA13" }, "PSS2.PS7_SAXIACPRDATA14->PSS1_LOGIC_OUTS6_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA14" }, "PSS2.PS7_SAXIACPRDATA15->PSS1_LOGIC_OUTS7_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA15" }, "PSS2.PS7_SAXIACPRDATA16->PSS1_LOGIC_OUTS3_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA16" }, "PSS2.PS7_SAXIACPRDATA17->PSS1_LOGIC_OUTS4_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA17" }, "PSS2.PS7_SAXIACPRDATA18->PSS1_LOGIC_OUTS5_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA18" }, "PSS2.PS7_SAXIACPRDATA19->PSS1_LOGIC_OUTS6_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_36", "is_directional": "1", + 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"src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA59" }, "PSS2.PS7_SAXIACPRDATA6->PSS1_LOGIC_OUTS8_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA6" }, "PSS2.PS7_SAXIACPRDATA60->PSS1_LOGIC_OUTS9_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA60" }, "PSS2.PS7_SAXIACPRDATA61->PSS1_LOGIC_OUTS10_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA61" }, "PSS2.PS7_SAXIACPRDATA62->PSS1_LOGIC_OUTS11_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA62" }, "PSS2.PS7_SAXIACPRDATA63->PSS1_LOGIC_OUTS12_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA63" }, "PSS2.PS7_SAXIACPRDATA7->PSS1_LOGIC_OUTS9_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA7" }, "PSS2.PS7_SAXIACPRDATA8->PSS1_LOGIC_OUTS5_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA8" }, "PSS2.PS7_SAXIACPRDATA9->PSS1_LOGIC_OUTS6_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRDATA9" }, "PSS2.PS7_SAXIACPRID0->PSS1_LOGIC_OUTS3_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRID0" }, "PSS2.PS7_SAXIACPRID1->PSS1_LOGIC_OUTS4_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRID1" }, "PSS2.PS7_SAXIACPRID2->PSS1_LOGIC_OUTS3_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRID2" }, "PSS2.PS7_SAXIACPRLAST->PSS1_LOGIC_OUTS11_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRLAST" }, "PSS2.PS7_SAXIACPRRESP0->PSS1_LOGIC_OUTS9_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRRESP0" }, "PSS2.PS7_SAXIACPRRESP1->PSS1_LOGIC_OUTS10_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRRESP1" }, "PSS2.PS7_SAXIACPRVALID->PSS1_LOGIC_OUTS12_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPRVALID" }, "PSS2.PS7_SAXIACPWREADY->PSS1_LOGIC_OUTS1_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIACPWREADY" }, "PSS2.PS7_SAXIGP0ARESETN->PSS2_LOGIC_OUTS8_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0ARESETN" }, "PSS2.PS7_SAXIGP0ARREADY->PSS2_LOGIC_OUTS8_76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0ARREADY" }, "PSS2.PS7_SAXIGP0AWREADY->PSS2_LOGIC_OUTS9_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0AWREADY" }, "PSS2.PS7_SAXIGP0BID0->PSS2_LOGIC_OUTS8_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0BID0" }, "PSS2.PS7_SAXIGP0BID1->PSS2_LOGIC_OUTS9_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0BID1" }, "PSS2.PS7_SAXIGP0BID2->PSS2_LOGIC_OUTS8_80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0BID2" }, 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null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0BID5" }, "PSS2.PS7_SAXIGP0BRESP0->PSS2_LOGIC_OUTS10_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0BRESP0" }, "PSS2.PS7_SAXIGP0BRESP1->PSS2_LOGIC_OUTS11_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0BRESP1" }, "PSS2.PS7_SAXIGP0BVALID->PSS2_LOGIC_OUTS8_78": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_78", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0BVALID" }, "PSS2.PS7_SAXIGP0RDATA0->PSS2_LOGIC_OUTS12_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA0" }, "PSS2.PS7_SAXIGP0RDATA1->PSS2_LOGIC_OUTS13_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA1" }, "PSS2.PS7_SAXIGP0RDATA10->PSS2_LOGIC_OUTS10_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA10" }, "PSS2.PS7_SAXIGP0RDATA11->PSS2_LOGIC_OUTS11_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA11" }, "PSS2.PS7_SAXIGP0RDATA12->PSS2_LOGIC_OUTS9_76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA12" }, "PSS2.PS7_SAXIGP0RDATA13->PSS2_LOGIC_OUTS10_76": { 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"src_wire": "PS7_SAXIGP0RDATA15" }, "PSS2.PS7_SAXIGP0RDATA16->PSS2_LOGIC_OUTS11_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA16" }, "PSS2.PS7_SAXIGP0RDATA17->PSS2_LOGIC_OUTS12_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA17" }, "PSS2.PS7_SAXIGP0RDATA18->PSS2_LOGIC_OUTS13_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA18" }, "PSS2.PS7_SAXIGP0RDATA19->PSS2_LOGIC_OUTS14_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA19" }, "PSS2.PS7_SAXIGP0RDATA2->PSS2_LOGIC_OUTS14_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA2" }, "PSS2.PS7_SAXIGP0RDATA20->PSS2_LOGIC_OUTS9_78": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_78", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA20" }, "PSS2.PS7_SAXIGP0RDATA21->PSS2_LOGIC_OUTS10_78": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_78", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA21" }, "PSS2.PS7_SAXIGP0RDATA22->PSS2_LOGIC_OUTS11_78": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_78", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA22" }, "PSS2.PS7_SAXIGP0RDATA23->PSS2_LOGIC_OUTS12_78": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_78", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA23" }, "PSS2.PS7_SAXIGP0RDATA24->PSS2_LOGIC_OUTS12_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA24" }, "PSS2.PS7_SAXIGP0RDATA25->PSS2_LOGIC_OUTS13_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA25" }, "PSS2.PS7_SAXIGP0RDATA26->PSS2_LOGIC_OUTS14_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA26" }, "PSS2.PS7_SAXIGP0RDATA27->PSS2_LOGIC_OUTS15_79": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS15_79", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA27" }, "PSS2.PS7_SAXIGP0RDATA28->PSS2_LOGIC_OUTS12_80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA28" }, "PSS2.PS7_SAXIGP0RDATA29->PSS2_LOGIC_OUTS13_80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA29" }, "PSS2.PS7_SAXIGP0RDATA3->PSS2_LOGIC_OUTS15_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS15_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA3" }, "PSS2.PS7_SAXIGP0RDATA30->PSS2_LOGIC_OUTS14_80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA30" }, "PSS2.PS7_SAXIGP0RDATA31->PSS2_LOGIC_OUTS15_80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS15_80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA31" }, "PSS2.PS7_SAXIGP0RDATA4->PSS2_LOGIC_OUTS10_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA4" }, "PSS2.PS7_SAXIGP0RDATA5->PSS2_LOGIC_OUTS11_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA5" }, "PSS2.PS7_SAXIGP0RDATA6->PSS2_LOGIC_OUTS12_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA6" }, "PSS2.PS7_SAXIGP0RDATA7->PSS2_LOGIC_OUTS13_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA7" }, "PSS2.PS7_SAXIGP0RDATA8->PSS2_LOGIC_OUTS8_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA8" }, "PSS2.PS7_SAXIGP0RDATA9->PSS2_LOGIC_OUTS9_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RDATA9" }, "PSS2.PS7_SAXIGP0RID0->PSS2_LOGIC_OUTS8_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RID0" }, "PSS2.PS7_SAXIGP0RID1->PSS2_LOGIC_OUTS9_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RID1" }, "PSS2.PS7_SAXIGP0RID2->PSS2_LOGIC_OUTS10_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RID2" }, "PSS2.PS7_SAXIGP0RID3->PSS2_LOGIC_OUTS11_73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RID3" }, "PSS2.PS7_SAXIGP0RID4->PSS2_LOGIC_OUTS8_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RID4" }, "PSS2.PS7_SAXIGP0RID5->PSS2_LOGIC_OUTS9_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RID5" }, "PSS2.PS7_SAXIGP0RLAST->PSS2_LOGIC_OUTS14_74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RLAST" }, "PSS2.PS7_SAXIGP0RRESP0->PSS2_LOGIC_OUTS12_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RRESP0" }, "PSS2.PS7_SAXIGP0RRESP1->PSS2_LOGIC_OUTS13_75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RRESP1" }, "PSS2.PS7_SAXIGP0RVALID->PSS2_LOGIC_OUTS13_76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0RVALID" }, "PSS2.PS7_SAXIGP0WREADY->PSS2_LOGIC_OUTS10_77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP0WREADY" }, "PSS2.PS7_SAXIGP1ARESETN->PSS2_LOGIC_OUTS8_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1ARESETN" }, "PSS2.PS7_SAXIGP1ARREADY->PSS2_LOGIC_OUTS8_84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1ARREADY" }, "PSS2.PS7_SAXIGP1AWREADY->PSS2_LOGIC_OUTS9_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1AWREADY" }, "PSS2.PS7_SAXIGP1BID0->PSS2_LOGIC_OUTS8_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1BID0" }, "PSS2.PS7_SAXIGP1BID1->PSS2_LOGIC_OUTS9_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1BID1" }, "PSS2.PS7_SAXIGP1BID2->PSS2_LOGIC_OUTS8_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1BID2" }, "PSS2.PS7_SAXIGP1BID3->PSS2_LOGIC_OUTS9_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1BID3" }, "PSS2.PS7_SAXIGP1BID4->PSS2_LOGIC_OUTS10_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1BID4" }, "PSS2.PS7_SAXIGP1BID5->PSS2_LOGIC_OUTS11_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1BID5" }, "PSS2.PS7_SAXIGP1BRESP0->PSS2_LOGIC_OUTS10_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1BRESP0" }, "PSS2.PS7_SAXIGP1BRESP1->PSS2_LOGIC_OUTS11_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1BRESP1" }, "PSS2.PS7_SAXIGP1BVALID->PSS2_LOGIC_OUTS8_86": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_86", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1BVALID" }, "PSS2.PS7_SAXIGP1RDATA0->PSS2_LOGIC_OUTS12_81": { "can_invert": "0", + "dst_to_src": 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null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA13" }, "PSS2.PS7_SAXIGP1RDATA14->PSS2_LOGIC_OUTS11_84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA14" }, "PSS2.PS7_SAXIGP1RDATA15->PSS2_LOGIC_OUTS12_84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA15" }, "PSS2.PS7_SAXIGP1RDATA16->PSS2_LOGIC_OUTS11_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA16" }, "PSS2.PS7_SAXIGP1RDATA17->PSS2_LOGIC_OUTS12_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA17" }, "PSS2.PS7_SAXIGP1RDATA18->PSS2_LOGIC_OUTS13_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA18" }, "PSS2.PS7_SAXIGP1RDATA19->PSS2_LOGIC_OUTS14_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA19" }, "PSS2.PS7_SAXIGP1RDATA2->PSS2_LOGIC_OUTS14_81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA2" }, "PSS2.PS7_SAXIGP1RDATA20->PSS2_LOGIC_OUTS9_86": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_86", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA20" }, 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null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA23" }, "PSS2.PS7_SAXIGP1RDATA24->PSS2_LOGIC_OUTS12_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA24" }, "PSS2.PS7_SAXIGP1RDATA25->PSS2_LOGIC_OUTS13_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA25" }, "PSS2.PS7_SAXIGP1RDATA26->PSS2_LOGIC_OUTS14_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA26" }, "PSS2.PS7_SAXIGP1RDATA27->PSS2_LOGIC_OUTS15_87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS15_87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA27" }, "PSS2.PS7_SAXIGP1RDATA28->PSS2_LOGIC_OUTS12_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA28" }, "PSS2.PS7_SAXIGP1RDATA29->PSS2_LOGIC_OUTS13_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA29" }, "PSS2.PS7_SAXIGP1RDATA3->PSS2_LOGIC_OUTS15_81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS15_81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA3" }, "PSS2.PS7_SAXIGP1RDATA30->PSS2_LOGIC_OUTS14_88": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_88", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA30" }, 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+ "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA5" }, "PSS2.PS7_SAXIGP1RDATA6->PSS2_LOGIC_OUTS12_82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA6" }, "PSS2.PS7_SAXIGP1RDATA7->PSS2_LOGIC_OUTS13_82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA7" }, "PSS2.PS7_SAXIGP1RDATA8->PSS2_LOGIC_OUTS8_83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA8" }, "PSS2.PS7_SAXIGP1RDATA9->PSS2_LOGIC_OUTS9_83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RDATA9" }, "PSS2.PS7_SAXIGP1RID0->PSS2_LOGIC_OUTS8_81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RID0" }, "PSS2.PS7_SAXIGP1RID1->PSS2_LOGIC_OUTS9_81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RID1" }, "PSS2.PS7_SAXIGP1RID2->PSS2_LOGIC_OUTS10_81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RID2" }, "PSS2.PS7_SAXIGP1RID3->PSS2_LOGIC_OUTS11_81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS11_81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RID3" }, "PSS2.PS7_SAXIGP1RID4->PSS2_LOGIC_OUTS8_82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS8_82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RID4" }, "PSS2.PS7_SAXIGP1RID5->PSS2_LOGIC_OUTS9_82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS9_82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RID5" }, "PSS2.PS7_SAXIGP1RLAST->PSS2_LOGIC_OUTS14_82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS14_82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RLAST" }, "PSS2.PS7_SAXIGP1RRESP0->PSS2_LOGIC_OUTS12_83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS12_83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RRESP0" }, "PSS2.PS7_SAXIGP1RRESP1->PSS2_LOGIC_OUTS13_83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RRESP1" }, "PSS2.PS7_SAXIGP1RVALID->PSS2_LOGIC_OUTS13_84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS13_84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1RVALID" }, "PSS2.PS7_SAXIGP1WREADY->PSS2_LOGIC_OUTS10_85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS2_LOGIC_OUTS10_85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIGP1WREADY" }, "PSS2.PS7_SAXIHP0ARESETN->PSS1_LOGIC_OUTS0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0ARESETN" }, "PSS2.PS7_SAXIHP0ARREADY->PSS1_LOGIC_OUTS0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0ARREADY" }, "PSS2.PS7_SAXIHP0AWREADY->PSS1_LOGIC_OUTS0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0AWREADY" }, "PSS2.PS7_SAXIHP0BID0->PSS1_LOGIC_OUTS2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0BID0" }, "PSS2.PS7_SAXIHP0BID1->PSS1_LOGIC_OUTS3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0BID1" }, "PSS2.PS7_SAXIHP0BID2->PSS1_LOGIC_OUTS0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0BID2" }, "PSS2.PS7_SAXIHP0BID3->PSS1_LOGIC_OUTS1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0BID3" }, "PSS2.PS7_SAXIHP0BID4->PSS1_LOGIC_OUTS2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0BID4" }, "PSS2.PS7_SAXIHP0BID5->PSS1_LOGIC_OUTS3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0BID5" }, "PSS2.PS7_SAXIHP0BRESP0->PSS1_LOGIC_OUTS0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0BRESP0" }, "PSS2.PS7_SAXIHP0BRESP1->PSS1_LOGIC_OUTS1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0BRESP1" }, "PSS2.PS7_SAXIHP0BVALID->PSS1_LOGIC_OUTS4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0BVALID" }, "PSS2.PS7_SAXIHP0RACOUNT0->PSS1_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RACOUNT0" }, "PSS2.PS7_SAXIHP0RACOUNT1->PSS1_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RACOUNT1" }, "PSS2.PS7_SAXIHP0RACOUNT2->PSS1_LOGIC_OUTS13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RACOUNT2" }, "PSS2.PS7_SAXIHP0RCOUNT0->PSS1_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RCOUNT0" }, "PSS2.PS7_SAXIHP0RCOUNT1->PSS1_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RCOUNT1" }, "PSS2.PS7_SAXIHP0RCOUNT2->PSS1_LOGIC_OUTS13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RCOUNT2" }, "PSS2.PS7_SAXIHP0RCOUNT3->PSS1_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RCOUNT3" }, "PSS2.PS7_SAXIHP0RCOUNT4->PSS1_LOGIC_OUTS10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RCOUNT4" }, "PSS2.PS7_SAXIHP0RCOUNT5->PSS1_LOGIC_OUTS11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RCOUNT5" }, "PSS2.PS7_SAXIHP0RCOUNT6->PSS1_LOGIC_OUTS12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RCOUNT6" }, "PSS2.PS7_SAXIHP0RCOUNT7->PSS1_LOGIC_OUTS13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RCOUNT7" }, "PSS2.PS7_SAXIHP0RDATA0->PSS1_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA0" }, "PSS2.PS7_SAXIHP0RDATA1->PSS1_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA1" }, "PSS2.PS7_SAXIHP0RDATA10->PSS1_LOGIC_OUTS4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA10" }, "PSS2.PS7_SAXIHP0RDATA11->PSS1_LOGIC_OUTS5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA11" }, "PSS2.PS7_SAXIHP0RDATA12->PSS1_LOGIC_OUTS1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA12" }, "PSS2.PS7_SAXIHP0RDATA13->PSS1_LOGIC_OUTS2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA13" }, "PSS2.PS7_SAXIHP0RDATA14->PSS1_LOGIC_OUTS3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA14" }, "PSS2.PS7_SAXIHP0RDATA15->PSS1_LOGIC_OUTS4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA15" }, "PSS2.PS7_SAXIHP0RDATA16->PSS1_LOGIC_OUTS5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA16" }, "PSS2.PS7_SAXIHP0RDATA17->PSS1_LOGIC_OUTS6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA17" }, "PSS2.PS7_SAXIHP0RDATA18->PSS1_LOGIC_OUTS7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA18" }, "PSS2.PS7_SAXIHP0RDATA19->PSS1_LOGIC_OUTS8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA19" }, "PSS2.PS7_SAXIHP0RDATA2->PSS1_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA2" }, "PSS2.PS7_SAXIHP0RDATA20->PSS1_LOGIC_OUTS4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA20" }, "PSS2.PS7_SAXIHP0RDATA21->PSS1_LOGIC_OUTS5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA21" }, "PSS2.PS7_SAXIHP0RDATA22->PSS1_LOGIC_OUTS6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA22" }, "PSS2.PS7_SAXIHP0RDATA23->PSS1_LOGIC_OUTS7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA23" }, "PSS2.PS7_SAXIHP0RDATA24->PSS1_LOGIC_OUTS0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA24" }, "PSS2.PS7_SAXIHP0RDATA25->PSS1_LOGIC_OUTS1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA25" }, "PSS2.PS7_SAXIHP0RDATA26->PSS1_LOGIC_OUTS2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA26" }, "PSS2.PS7_SAXIHP0RDATA27->PSS1_LOGIC_OUTS3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA27" }, "PSS2.PS7_SAXIHP0RDATA28->PSS1_LOGIC_OUTS1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA28" }, "PSS2.PS7_SAXIHP0RDATA29->PSS1_LOGIC_OUTS2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA29" }, "PSS2.PS7_SAXIHP0RDATA3->PSS1_LOGIC_OUTS6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA3" }, "PSS2.PS7_SAXIHP0RDATA30->PSS1_LOGIC_OUTS3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA30" }, "PSS2.PS7_SAXIHP0RDATA31->PSS1_LOGIC_OUTS4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA31" }, "PSS2.PS7_SAXIHP0RDATA32->PSS1_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA32" }, "PSS2.PS7_SAXIHP0RDATA33->PSS1_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA33" }, "PSS2.PS7_SAXIHP0RDATA34->PSS1_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA34" }, "PSS2.PS7_SAXIHP0RDATA35->PSS1_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA35" }, "PSS2.PS7_SAXIHP0RDATA36->PSS1_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA36" }, "PSS2.PS7_SAXIHP0RDATA37->PSS1_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA37" }, "PSS2.PS7_SAXIHP0RDATA38->PSS1_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA38" }, "PSS2.PS7_SAXIHP0RDATA39->PSS1_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA39" }, "PSS2.PS7_SAXIHP0RDATA4->PSS1_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA4" }, "PSS2.PS7_SAXIHP0RDATA40->PSS1_LOGIC_OUTS6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA40" }, "PSS2.PS7_SAXIHP0RDATA41->PSS1_LOGIC_OUTS7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA41" }, "PSS2.PS7_SAXIHP0RDATA42->PSS1_LOGIC_OUTS8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA42" }, "PSS2.PS7_SAXIHP0RDATA43->PSS1_LOGIC_OUTS9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA43" }, "PSS2.PS7_SAXIHP0RDATA44->PSS1_LOGIC_OUTS5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA44" }, "PSS2.PS7_SAXIHP0RDATA45->PSS1_LOGIC_OUTS6_3": { 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"PS7_SAXIHP0RDATA47" }, "PSS2.PS7_SAXIHP0RDATA48->PSS1_LOGIC_OUTS9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA48" }, "PSS2.PS7_SAXIHP0RDATA49->PSS1_LOGIC_OUTS10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA49" }, "PSS2.PS7_SAXIHP0RDATA5->PSS1_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA5" }, "PSS2.PS7_SAXIHP0RDATA50->PSS1_LOGIC_OUTS11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA50" }, "PSS2.PS7_SAXIHP0RDATA51->PSS1_LOGIC_OUTS12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA51" }, "PSS2.PS7_SAXIHP0RDATA52->PSS1_LOGIC_OUTS8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA52" }, "PSS2.PS7_SAXIHP0RDATA53->PSS1_LOGIC_OUTS9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA53" }, "PSS2.PS7_SAXIHP0RDATA54->PSS1_LOGIC_OUTS10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA54" }, "PSS2.PS7_SAXIHP0RDATA55->PSS1_LOGIC_OUTS11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA55" }, "PSS2.PS7_SAXIHP0RDATA56->PSS1_LOGIC_OUTS4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA56" }, "PSS2.PS7_SAXIHP0RDATA57->PSS1_LOGIC_OUTS5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA57" }, "PSS2.PS7_SAXIHP0RDATA58->PSS1_LOGIC_OUTS6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA58" }, "PSS2.PS7_SAXIHP0RDATA59->PSS1_LOGIC_OUTS7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA59" }, "PSS2.PS7_SAXIHP0RDATA6->PSS1_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA6" }, "PSS2.PS7_SAXIHP0RDATA60->PSS1_LOGIC_OUTS5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA60" }, "PSS2.PS7_SAXIHP0RDATA61->PSS1_LOGIC_OUTS6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA61" }, "PSS2.PS7_SAXIHP0RDATA62->PSS1_LOGIC_OUTS7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA62" }, "PSS2.PS7_SAXIHP0RDATA63->PSS1_LOGIC_OUTS8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA63" }, "PSS2.PS7_SAXIHP0RDATA7->PSS1_LOGIC_OUTS6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA7" }, "PSS2.PS7_SAXIHP0RDATA8->PSS1_LOGIC_OUTS2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA8" }, "PSS2.PS7_SAXIHP0RDATA9->PSS1_LOGIC_OUTS3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RDATA9" }, "PSS2.PS7_SAXIHP0RID0->PSS1_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RID0" }, "PSS2.PS7_SAXIHP0RID1->PSS1_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RID1" }, "PSS2.PS7_SAXIHP0RID2->PSS1_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RID2" }, "PSS2.PS7_SAXIHP0RID3->PSS1_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RID3" }, "PSS2.PS7_SAXIHP0RID4->PSS1_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RID4" }, "PSS2.PS7_SAXIHP0RID5->PSS1_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RID5" }, "PSS2.PS7_SAXIHP0RLAST->PSS1_LOGIC_OUTS11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RLAST" }, "PSS2.PS7_SAXIHP0RRESP0->PSS1_LOGIC_OUTS9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RRESP0" }, "PSS2.PS7_SAXIHP0RRESP1->PSS1_LOGIC_OUTS10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RRESP1" }, "PSS2.PS7_SAXIHP0RVALID->PSS1_LOGIC_OUTS12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0RVALID" }, "PSS2.PS7_SAXIHP0WACOUNT0->PSS1_LOGIC_OUTS12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WACOUNT0" }, "PSS2.PS7_SAXIHP0WACOUNT1->PSS1_LOGIC_OUTS13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WACOUNT1" }, "PSS2.PS7_SAXIHP0WACOUNT2->PSS1_LOGIC_OUTS12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WACOUNT2" }, "PSS2.PS7_SAXIHP0WACOUNT3->PSS1_LOGIC_OUTS13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WACOUNT3" }, "PSS2.PS7_SAXIHP0WACOUNT4->PSS1_LOGIC_OUTS13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WACOUNT4" }, "PSS2.PS7_SAXIHP0WACOUNT5->PSS1_LOGIC_OUTS14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WACOUNT5" }, "PSS2.PS7_SAXIHP0WCOUNT0->PSS1_LOGIC_OUTS8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WCOUNT0" }, "PSS2.PS7_SAXIHP0WCOUNT1->PSS1_LOGIC_OUTS9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WCOUNT1" }, "PSS2.PS7_SAXIHP0WCOUNT2->PSS1_LOGIC_OUTS10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WCOUNT2" }, "PSS2.PS7_SAXIHP0WCOUNT3->PSS1_LOGIC_OUTS11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WCOUNT3" }, "PSS2.PS7_SAXIHP0WCOUNT4->PSS1_LOGIC_OUTS9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WCOUNT4" }, "PSS2.PS7_SAXIHP0WCOUNT5->PSS1_LOGIC_OUTS10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WCOUNT5" }, "PSS2.PS7_SAXIHP0WCOUNT6->PSS1_LOGIC_OUTS11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WCOUNT6" }, "PSS2.PS7_SAXIHP0WCOUNT7->PSS1_LOGIC_OUTS12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WCOUNT7" }, "PSS2.PS7_SAXIHP0WREADY->PSS1_LOGIC_OUTS1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP0WREADY" }, "PSS2.PS7_SAXIHP1ARESETN->PSS1_LOGIC_OUTS0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1ARESETN" }, "PSS2.PS7_SAXIHP1ARREADY->PSS1_LOGIC_OUTS0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1ARREADY" }, "PSS2.PS7_SAXIHP1AWREADY->PSS1_LOGIC_OUTS0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1AWREADY" }, "PSS2.PS7_SAXIHP1BID0->PSS1_LOGIC_OUTS2_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1BID0" }, "PSS2.PS7_SAXIHP1BID1->PSS1_LOGIC_OUTS3_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1BID1" }, "PSS2.PS7_SAXIHP1BID2->PSS1_LOGIC_OUTS0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1BID2" }, "PSS2.PS7_SAXIHP1BID3->PSS1_LOGIC_OUTS1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1BID3" }, "PSS2.PS7_SAXIHP1BID4->PSS1_LOGIC_OUTS2_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1BID4" }, "PSS2.PS7_SAXIHP1BID5->PSS1_LOGIC_OUTS3_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1BID5" }, "PSS2.PS7_SAXIHP1BRESP0->PSS1_LOGIC_OUTS0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1BRESP0" }, "PSS2.PS7_SAXIHP1BRESP1->PSS1_LOGIC_OUTS1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1BRESP1" }, "PSS2.PS7_SAXIHP1BVALID->PSS1_LOGIC_OUTS4_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1BVALID" }, "PSS2.PS7_SAXIHP1RACOUNT0->PSS1_LOGIC_OUTS11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RACOUNT0" }, "PSS2.PS7_SAXIHP1RACOUNT1->PSS1_LOGIC_OUTS12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RACOUNT1" }, "PSS2.PS7_SAXIHP1RACOUNT2->PSS1_LOGIC_OUTS13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RACOUNT2" }, "PSS2.PS7_SAXIHP1RCOUNT0->PSS1_LOGIC_OUTS11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RCOUNT0" }, "PSS2.PS7_SAXIHP1RCOUNT1->PSS1_LOGIC_OUTS12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RCOUNT1" }, "PSS2.PS7_SAXIHP1RCOUNT2->PSS1_LOGIC_OUTS13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RCOUNT2" }, "PSS2.PS7_SAXIHP1RCOUNT3->PSS1_LOGIC_OUTS14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RCOUNT3" }, "PSS2.PS7_SAXIHP1RCOUNT4->PSS1_LOGIC_OUTS10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RCOUNT4" }, "PSS2.PS7_SAXIHP1RCOUNT5->PSS1_LOGIC_OUTS11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RCOUNT5" }, "PSS2.PS7_SAXIHP1RCOUNT6->PSS1_LOGIC_OUTS12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RCOUNT6" }, "PSS2.PS7_SAXIHP1RCOUNT7->PSS1_LOGIC_OUTS13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RCOUNT7" }, "PSS2.PS7_SAXIHP1RDATA0->PSS1_LOGIC_OUTS3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_8", "is_directional": "1", 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"0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA11" }, "PSS2.PS7_SAXIHP1RDATA12->PSS1_LOGIC_OUTS1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA12" }, "PSS2.PS7_SAXIHP1RDATA13->PSS1_LOGIC_OUTS2_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA13" }, "PSS2.PS7_SAXIHP1RDATA14->PSS1_LOGIC_OUTS3_11": { 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"PS7_SAXIHP1RDATA16" }, "PSS2.PS7_SAXIHP1RDATA17->PSS1_LOGIC_OUTS6_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA17" }, "PSS2.PS7_SAXIHP1RDATA18->PSS1_LOGIC_OUTS7_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA18" }, "PSS2.PS7_SAXIHP1RDATA19->PSS1_LOGIC_OUTS8_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA19" }, "PSS2.PS7_SAXIHP1RDATA2->PSS1_LOGIC_OUTS5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA2" }, "PSS2.PS7_SAXIHP1RDATA20->PSS1_LOGIC_OUTS4_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA20" }, "PSS2.PS7_SAXIHP1RDATA21->PSS1_LOGIC_OUTS5_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA21" }, "PSS2.PS7_SAXIHP1RDATA22->PSS1_LOGIC_OUTS6_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA22" }, "PSS2.PS7_SAXIHP1RDATA23->PSS1_LOGIC_OUTS7_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA23" }, "PSS2.PS7_SAXIHP1RDATA24->PSS1_LOGIC_OUTS0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA24" }, "PSS2.PS7_SAXIHP1RDATA25->PSS1_LOGIC_OUTS1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA25" }, "PSS2.PS7_SAXIHP1RDATA26->PSS1_LOGIC_OUTS2_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA26" }, "PSS2.PS7_SAXIHP1RDATA27->PSS1_LOGIC_OUTS3_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA27" }, "PSS2.PS7_SAXIHP1RDATA28->PSS1_LOGIC_OUTS1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA28" }, "PSS2.PS7_SAXIHP1RDATA29->PSS1_LOGIC_OUTS2_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA29" }, "PSS2.PS7_SAXIHP1RDATA3->PSS1_LOGIC_OUTS6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA3" }, "PSS2.PS7_SAXIHP1RDATA30->PSS1_LOGIC_OUTS3_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA30" }, "PSS2.PS7_SAXIHP1RDATA31->PSS1_LOGIC_OUTS4_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA31" }, "PSS2.PS7_SAXIHP1RDATA32->PSS1_LOGIC_OUTS7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA32" }, "PSS2.PS7_SAXIHP1RDATA33->PSS1_LOGIC_OUTS8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA33" }, "PSS2.PS7_SAXIHP1RDATA34->PSS1_LOGIC_OUTS9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA34" }, "PSS2.PS7_SAXIHP1RDATA35->PSS1_LOGIC_OUTS10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA35" }, "PSS2.PS7_SAXIHP1RDATA36->PSS1_LOGIC_OUTS7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA36" }, "PSS2.PS7_SAXIHP1RDATA37->PSS1_LOGIC_OUTS8_9": { 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"in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA47" }, "PSS2.PS7_SAXIHP1RDATA48->PSS1_LOGIC_OUTS9_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA48" }, "PSS2.PS7_SAXIHP1RDATA49->PSS1_LOGIC_OUTS10_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA49" }, 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"in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA51" }, "PSS2.PS7_SAXIHP1RDATA52->PSS1_LOGIC_OUTS8_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA52" }, "PSS2.PS7_SAXIHP1RDATA53->PSS1_LOGIC_OUTS9_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA53" }, "PSS2.PS7_SAXIHP1RDATA54->PSS1_LOGIC_OUTS10_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA54" }, "PSS2.PS7_SAXIHP1RDATA55->PSS1_LOGIC_OUTS11_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA55" }, "PSS2.PS7_SAXIHP1RDATA56->PSS1_LOGIC_OUTS4_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA56" }, "PSS2.PS7_SAXIHP1RDATA57->PSS1_LOGIC_OUTS5_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA57" }, "PSS2.PS7_SAXIHP1RDATA58->PSS1_LOGIC_OUTS6_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA58" }, "PSS2.PS7_SAXIHP1RDATA59->PSS1_LOGIC_OUTS7_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA59" }, "PSS2.PS7_SAXIHP1RDATA6->PSS1_LOGIC_OUTS5_9": { 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"PS7_SAXIHP1RDATA61" }, "PSS2.PS7_SAXIHP1RDATA62->PSS1_LOGIC_OUTS7_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA62" }, "PSS2.PS7_SAXIHP1RDATA63->PSS1_LOGIC_OUTS8_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA63" }, "PSS2.PS7_SAXIHP1RDATA7->PSS1_LOGIC_OUTS6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA7" }, "PSS2.PS7_SAXIHP1RDATA8->PSS1_LOGIC_OUTS2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA8" }, "PSS2.PS7_SAXIHP1RDATA9->PSS1_LOGIC_OUTS3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RDATA9" }, "PSS2.PS7_SAXIHP1RID0->PSS1_LOGIC_OUTS0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RID0" }, "PSS2.PS7_SAXIHP1RID1->PSS1_LOGIC_OUTS1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RID1" }, "PSS2.PS7_SAXIHP1RID2->PSS1_LOGIC_OUTS2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RID2" }, "PSS2.PS7_SAXIHP1RID3->PSS1_LOGIC_OUTS0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RID3" }, "PSS2.PS7_SAXIHP1RID4->PSS1_LOGIC_OUTS1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RID4" }, "PSS2.PS7_SAXIHP1RID5->PSS1_LOGIC_OUTS2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RID5" }, "PSS2.PS7_SAXIHP1RLAST->PSS1_LOGIC_OUTS11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RLAST" }, "PSS2.PS7_SAXIHP1RRESP0->PSS1_LOGIC_OUTS9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RRESP0" }, "PSS2.PS7_SAXIHP1RRESP1->PSS1_LOGIC_OUTS10_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RRESP1" }, "PSS2.PS7_SAXIHP1RVALID->PSS1_LOGIC_OUTS12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1RVALID" }, "PSS2.PS7_SAXIHP1WACOUNT0->PSS1_LOGIC_OUTS12_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WACOUNT0" }, "PSS2.PS7_SAXIHP1WACOUNT1->PSS1_LOGIC_OUTS13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WACOUNT1" }, "PSS2.PS7_SAXIHP1WACOUNT2->PSS1_LOGIC_OUTS12_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WACOUNT2" }, "PSS2.PS7_SAXIHP1WACOUNT3->PSS1_LOGIC_OUTS13_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WACOUNT3" }, "PSS2.PS7_SAXIHP1WACOUNT4->PSS1_LOGIC_OUTS13_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WACOUNT4" }, "PSS2.PS7_SAXIHP1WACOUNT5->PSS1_LOGIC_OUTS14_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS14_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WACOUNT5" }, "PSS2.PS7_SAXIHP1WCOUNT0->PSS1_LOGIC_OUTS8_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WCOUNT0" }, "PSS2.PS7_SAXIHP1WCOUNT1->PSS1_LOGIC_OUTS9_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WCOUNT1" }, "PSS2.PS7_SAXIHP1WCOUNT2->PSS1_LOGIC_OUTS10_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WCOUNT2" }, "PSS2.PS7_SAXIHP1WCOUNT3->PSS1_LOGIC_OUTS11_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WCOUNT3" }, "PSS2.PS7_SAXIHP1WCOUNT4->PSS1_LOGIC_OUTS9_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WCOUNT4" }, "PSS2.PS7_SAXIHP1WCOUNT5->PSS1_LOGIC_OUTS10_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WCOUNT5" }, "PSS2.PS7_SAXIHP1WCOUNT6->PSS1_LOGIC_OUTS11_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WCOUNT6" }, "PSS2.PS7_SAXIHP1WCOUNT7->PSS1_LOGIC_OUTS12_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WCOUNT7" }, "PSS2.PS7_SAXIHP1WREADY->PSS1_LOGIC_OUTS1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP1WREADY" }, "PSS2.PS7_SAXIHP2ARESETN->PSS1_LOGIC_OUTS0_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2ARESETN" }, "PSS2.PS7_SAXIHP2ARREADY->PSS1_LOGIC_OUTS0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2ARREADY" }, "PSS2.PS7_SAXIHP2AWREADY->PSS1_LOGIC_OUTS0_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2AWREADY" }, "PSS2.PS7_SAXIHP2BID0->PSS1_LOGIC_OUTS2_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2BID0" }, "PSS2.PS7_SAXIHP2BID1->PSS1_LOGIC_OUTS3_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2BID1" }, "PSS2.PS7_SAXIHP2BID2->PSS1_LOGIC_OUTS0_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2BID2" }, "PSS2.PS7_SAXIHP2BID3->PSS1_LOGIC_OUTS1_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2BID3" }, "PSS2.PS7_SAXIHP2BID4->PSS1_LOGIC_OUTS2_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2BID4" }, "PSS2.PS7_SAXIHP2BID5->PSS1_LOGIC_OUTS3_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2BID5" }, "PSS2.PS7_SAXIHP2BRESP0->PSS1_LOGIC_OUTS0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2BRESP0" }, "PSS2.PS7_SAXIHP2BRESP1->PSS1_LOGIC_OUTS1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2BRESP1" }, "PSS2.PS7_SAXIHP2BVALID->PSS1_LOGIC_OUTS4_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2BVALID" }, "PSS2.PS7_SAXIHP2RACOUNT0->PSS1_LOGIC_OUTS11_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RACOUNT0" }, "PSS2.PS7_SAXIHP2RACOUNT1->PSS1_LOGIC_OUTS12_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RACOUNT1" }, "PSS2.PS7_SAXIHP2RACOUNT2->PSS1_LOGIC_OUTS13_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RACOUNT2" }, "PSS2.PS7_SAXIHP2RCOUNT0->PSS1_LOGIC_OUTS11_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RCOUNT0" }, "PSS2.PS7_SAXIHP2RCOUNT1->PSS1_LOGIC_OUTS12_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RCOUNT1" }, "PSS2.PS7_SAXIHP2RCOUNT2->PSS1_LOGIC_OUTS13_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RCOUNT2" }, "PSS2.PS7_SAXIHP2RCOUNT3->PSS1_LOGIC_OUTS14_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS14_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RCOUNT3" }, "PSS2.PS7_SAXIHP2RCOUNT4->PSS1_LOGIC_OUTS10_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RCOUNT4" }, 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null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RCOUNT7" }, "PSS2.PS7_SAXIHP2RDATA0->PSS1_LOGIC_OUTS3_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA0" }, "PSS2.PS7_SAXIHP2RDATA1->PSS1_LOGIC_OUTS4_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA1" }, "PSS2.PS7_SAXIHP2RDATA10->PSS1_LOGIC_OUTS4_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_18", "is_directional": "1", + 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"in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA26" }, "PSS2.PS7_SAXIHP2RDATA27->PSS1_LOGIC_OUTS3_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA27" }, "PSS2.PS7_SAXIHP2RDATA28->PSS1_LOGIC_OUTS1_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA28" }, "PSS2.PS7_SAXIHP2RDATA29->PSS1_LOGIC_OUTS2_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA29" }, "PSS2.PS7_SAXIHP2RDATA3->PSS1_LOGIC_OUTS6_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA3" }, "PSS2.PS7_SAXIHP2RDATA30->PSS1_LOGIC_OUTS3_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA30" }, "PSS2.PS7_SAXIHP2RDATA31->PSS1_LOGIC_OUTS4_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA31" }, "PSS2.PS7_SAXIHP2RDATA32->PSS1_LOGIC_OUTS7_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA32" }, "PSS2.PS7_SAXIHP2RDATA33->PSS1_LOGIC_OUTS8_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA33" }, "PSS2.PS7_SAXIHP2RDATA34->PSS1_LOGIC_OUTS9_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA34" }, "PSS2.PS7_SAXIHP2RDATA35->PSS1_LOGIC_OUTS10_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA35" }, "PSS2.PS7_SAXIHP2RDATA36->PSS1_LOGIC_OUTS7_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA36" }, "PSS2.PS7_SAXIHP2RDATA37->PSS1_LOGIC_OUTS8_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA37" }, "PSS2.PS7_SAXIHP2RDATA38->PSS1_LOGIC_OUTS9_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA38" }, "PSS2.PS7_SAXIHP2RDATA39->PSS1_LOGIC_OUTS10_17": { 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"PS7_SAXIHP2RDATA40" }, "PSS2.PS7_SAXIHP2RDATA41->PSS1_LOGIC_OUTS7_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA41" }, "PSS2.PS7_SAXIHP2RDATA42->PSS1_LOGIC_OUTS8_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA42" }, "PSS2.PS7_SAXIHP2RDATA43->PSS1_LOGIC_OUTS9_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA43" }, "PSS2.PS7_SAXIHP2RDATA44->PSS1_LOGIC_OUTS5_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA44" }, "PSS2.PS7_SAXIHP2RDATA45->PSS1_LOGIC_OUTS6_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA45" }, "PSS2.PS7_SAXIHP2RDATA46->PSS1_LOGIC_OUTS7_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": 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}, "PSS2.PS7_SAXIHP2RDATA51->PSS1_LOGIC_OUTS12_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA51" }, "PSS2.PS7_SAXIHP2RDATA52->PSS1_LOGIC_OUTS8_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA52" }, "PSS2.PS7_SAXIHP2RDATA53->PSS1_LOGIC_OUTS9_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA53" }, "PSS2.PS7_SAXIHP2RDATA54->PSS1_LOGIC_OUTS10_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA54" }, "PSS2.PS7_SAXIHP2RDATA55->PSS1_LOGIC_OUTS11_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA55" }, "PSS2.PS7_SAXIHP2RDATA56->PSS1_LOGIC_OUTS4_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA56" }, "PSS2.PS7_SAXIHP2RDATA57->PSS1_LOGIC_OUTS5_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA57" }, "PSS2.PS7_SAXIHP2RDATA58->PSS1_LOGIC_OUTS6_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA58" }, "PSS2.PS7_SAXIHP2RDATA59->PSS1_LOGIC_OUTS7_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA59" }, "PSS2.PS7_SAXIHP2RDATA6->PSS1_LOGIC_OUTS5_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA6" }, "PSS2.PS7_SAXIHP2RDATA60->PSS1_LOGIC_OUTS5_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA60" }, "PSS2.PS7_SAXIHP2RDATA61->PSS1_LOGIC_OUTS6_23": { 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"PS7_SAXIHP2RDATA63" }, "PSS2.PS7_SAXIHP2RDATA7->PSS1_LOGIC_OUTS6_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA7" }, "PSS2.PS7_SAXIHP2RDATA8->PSS1_LOGIC_OUTS2_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA8" }, "PSS2.PS7_SAXIHP2RDATA9->PSS1_LOGIC_OUTS3_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RDATA9" }, "PSS2.PS7_SAXIHP2RID0->PSS1_LOGIC_OUTS0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RID0" }, "PSS2.PS7_SAXIHP2RID1->PSS1_LOGIC_OUTS1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RID1" }, "PSS2.PS7_SAXIHP2RID2->PSS1_LOGIC_OUTS2_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RID2" }, "PSS2.PS7_SAXIHP2RID3->PSS1_LOGIC_OUTS0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RID3" }, "PSS2.PS7_SAXIHP2RID4->PSS1_LOGIC_OUTS1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RID4" }, "PSS2.PS7_SAXIHP2RID5->PSS1_LOGIC_OUTS2_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RID5" }, "PSS2.PS7_SAXIHP2RLAST->PSS1_LOGIC_OUTS11_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RLAST" }, "PSS2.PS7_SAXIHP2RRESP0->PSS1_LOGIC_OUTS9_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2RRESP0" }, "PSS2.PS7_SAXIHP2RRESP1->PSS1_LOGIC_OUTS10_19": { "can_invert": "0", + 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"PS7_SAXIHP2WACOUNT0" }, "PSS2.PS7_SAXIHP2WACOUNT1->PSS1_LOGIC_OUTS13_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WACOUNT1" }, "PSS2.PS7_SAXIHP2WACOUNT2->PSS1_LOGIC_OUTS12_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WACOUNT2" }, "PSS2.PS7_SAXIHP2WACOUNT3->PSS1_LOGIC_OUTS13_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WACOUNT3" }, "PSS2.PS7_SAXIHP2WACOUNT4->PSS1_LOGIC_OUTS13_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WACOUNT4" }, "PSS2.PS7_SAXIHP2WACOUNT5->PSS1_LOGIC_OUTS14_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS14_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WACOUNT5" }, "PSS2.PS7_SAXIHP2WCOUNT0->PSS1_LOGIC_OUTS8_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WCOUNT0" }, "PSS2.PS7_SAXIHP2WCOUNT1->PSS1_LOGIC_OUTS9_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WCOUNT1" }, "PSS2.PS7_SAXIHP2WCOUNT2->PSS1_LOGIC_OUTS10_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WCOUNT2" }, "PSS2.PS7_SAXIHP2WCOUNT3->PSS1_LOGIC_OUTS11_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WCOUNT3" }, "PSS2.PS7_SAXIHP2WCOUNT4->PSS1_LOGIC_OUTS9_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WCOUNT4" }, "PSS2.PS7_SAXIHP2WCOUNT5->PSS1_LOGIC_OUTS10_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WCOUNT5" }, "PSS2.PS7_SAXIHP2WCOUNT6->PSS1_LOGIC_OUTS11_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WCOUNT6" }, "PSS2.PS7_SAXIHP2WCOUNT7->PSS1_LOGIC_OUTS12_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WCOUNT7" }, "PSS2.PS7_SAXIHP2WREADY->PSS1_LOGIC_OUTS1_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP2WREADY" }, "PSS2.PS7_SAXIHP3ARESETN->PSS1_LOGIC_OUTS0_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3ARESETN" }, "PSS2.PS7_SAXIHP3ARREADY->PSS1_LOGIC_OUTS0_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3ARREADY" }, "PSS2.PS7_SAXIHP3AWREADY->PSS1_LOGIC_OUTS0_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3AWREADY" }, "PSS2.PS7_SAXIHP3BID0->PSS1_LOGIC_OUTS2_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3BID0" }, "PSS2.PS7_SAXIHP3BID1->PSS1_LOGIC_OUTS3_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3BID1" }, "PSS2.PS7_SAXIHP3BID2->PSS1_LOGIC_OUTS0_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3BID2" }, "PSS2.PS7_SAXIHP3BID3->PSS1_LOGIC_OUTS1_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3BID3" }, "PSS2.PS7_SAXIHP3BID4->PSS1_LOGIC_OUTS2_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3BID4" }, "PSS2.PS7_SAXIHP3BID5->PSS1_LOGIC_OUTS3_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3BID5" }, "PSS2.PS7_SAXIHP3BRESP0->PSS1_LOGIC_OUTS0_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3BRESP0" }, "PSS2.PS7_SAXIHP3BRESP1->PSS1_LOGIC_OUTS1_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3BRESP1" }, "PSS2.PS7_SAXIHP3BVALID->PSS1_LOGIC_OUTS4_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3BVALID" }, "PSS2.PS7_SAXIHP3RACOUNT0->PSS1_LOGIC_OUTS11_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RACOUNT0" }, "PSS2.PS7_SAXIHP3RACOUNT1->PSS1_LOGIC_OUTS12_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RACOUNT1" }, "PSS2.PS7_SAXIHP3RACOUNT2->PSS1_LOGIC_OUTS13_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RACOUNT2" }, "PSS2.PS7_SAXIHP3RCOUNT0->PSS1_LOGIC_OUTS11_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RCOUNT0" }, "PSS2.PS7_SAXIHP3RCOUNT1->PSS1_LOGIC_OUTS12_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RCOUNT1" }, "PSS2.PS7_SAXIHP3RCOUNT2->PSS1_LOGIC_OUTS13_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RCOUNT2" }, "PSS2.PS7_SAXIHP3RCOUNT3->PSS1_LOGIC_OUTS14_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS14_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RCOUNT3" }, "PSS2.PS7_SAXIHP3RCOUNT4->PSS1_LOGIC_OUTS10_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RCOUNT4" }, "PSS2.PS7_SAXIHP3RCOUNT5->PSS1_LOGIC_OUTS11_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RCOUNT5" }, "PSS2.PS7_SAXIHP3RCOUNT6->PSS1_LOGIC_OUTS12_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RCOUNT6" }, "PSS2.PS7_SAXIHP3RCOUNT7->PSS1_LOGIC_OUTS13_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RCOUNT7" }, "PSS2.PS7_SAXIHP3RDATA0->PSS1_LOGIC_OUTS3_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA0" }, "PSS2.PS7_SAXIHP3RDATA1->PSS1_LOGIC_OUTS4_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA1" }, "PSS2.PS7_SAXIHP3RDATA10->PSS1_LOGIC_OUTS4_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA10" }, "PSS2.PS7_SAXIHP3RDATA11->PSS1_LOGIC_OUTS5_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA11" }, "PSS2.PS7_SAXIHP3RDATA12->PSS1_LOGIC_OUTS1_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA12" }, "PSS2.PS7_SAXIHP3RDATA13->PSS1_LOGIC_OUTS2_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA13" }, "PSS2.PS7_SAXIHP3RDATA14->PSS1_LOGIC_OUTS3_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA14" }, "PSS2.PS7_SAXIHP3RDATA15->PSS1_LOGIC_OUTS4_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA15" }, "PSS2.PS7_SAXIHP3RDATA16->PSS1_LOGIC_OUTS5_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA16" }, "PSS2.PS7_SAXIHP3RDATA17->PSS1_LOGIC_OUTS6_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA17" }, "PSS2.PS7_SAXIHP3RDATA18->PSS1_LOGIC_OUTS7_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA18" }, "PSS2.PS7_SAXIHP3RDATA19->PSS1_LOGIC_OUTS8_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA19" }, "PSS2.PS7_SAXIHP3RDATA2->PSS1_LOGIC_OUTS5_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA2" }, "PSS2.PS7_SAXIHP3RDATA20->PSS1_LOGIC_OUTS4_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA20" }, "PSS2.PS7_SAXIHP3RDATA21->PSS1_LOGIC_OUTS5_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA21" }, "PSS2.PS7_SAXIHP3RDATA22->PSS1_LOGIC_OUTS6_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": 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"dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA25" }, "PSS2.PS7_SAXIHP3RDATA26->PSS1_LOGIC_OUTS2_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA26" }, "PSS2.PS7_SAXIHP3RDATA27->PSS1_LOGIC_OUTS3_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA27" }, "PSS2.PS7_SAXIHP3RDATA28->PSS1_LOGIC_OUTS1_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA28" }, "PSS2.PS7_SAXIHP3RDATA29->PSS1_LOGIC_OUTS2_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA29" }, "PSS2.PS7_SAXIHP3RDATA3->PSS1_LOGIC_OUTS6_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA3" }, "PSS2.PS7_SAXIHP3RDATA30->PSS1_LOGIC_OUTS3_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA30" }, "PSS2.PS7_SAXIHP3RDATA31->PSS1_LOGIC_OUTS4_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA31" }, "PSS2.PS7_SAXIHP3RDATA32->PSS1_LOGIC_OUTS7_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA32" }, "PSS2.PS7_SAXIHP3RDATA33->PSS1_LOGIC_OUTS8_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA33" }, "PSS2.PS7_SAXIHP3RDATA34->PSS1_LOGIC_OUTS9_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA34" }, "PSS2.PS7_SAXIHP3RDATA35->PSS1_LOGIC_OUTS10_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA35" }, "PSS2.PS7_SAXIHP3RDATA36->PSS1_LOGIC_OUTS7_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA36" }, "PSS2.PS7_SAXIHP3RDATA37->PSS1_LOGIC_OUTS8_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA37" }, "PSS2.PS7_SAXIHP3RDATA38->PSS1_LOGIC_OUTS9_25": { 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"PS7_SAXIHP3RDATA4" }, "PSS2.PS7_SAXIHP3RDATA40->PSS1_LOGIC_OUTS6_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA40" }, "PSS2.PS7_SAXIHP3RDATA41->PSS1_LOGIC_OUTS7_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA41" }, "PSS2.PS7_SAXIHP3RDATA42->PSS1_LOGIC_OUTS8_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA42" }, "PSS2.PS7_SAXIHP3RDATA43->PSS1_LOGIC_OUTS9_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA43" }, "PSS2.PS7_SAXIHP3RDATA44->PSS1_LOGIC_OUTS5_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA44" }, "PSS2.PS7_SAXIHP3RDATA45->PSS1_LOGIC_OUTS6_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA45" }, "PSS2.PS7_SAXIHP3RDATA46->PSS1_LOGIC_OUTS7_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA46" }, "PSS2.PS7_SAXIHP3RDATA47->PSS1_LOGIC_OUTS8_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA47" }, "PSS2.PS7_SAXIHP3RDATA48->PSS1_LOGIC_OUTS9_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA48" }, "PSS2.PS7_SAXIHP3RDATA49->PSS1_LOGIC_OUTS10_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA49" }, "PSS2.PS7_SAXIHP3RDATA5->PSS1_LOGIC_OUTS4_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA5" }, "PSS2.PS7_SAXIHP3RDATA50->PSS1_LOGIC_OUTS11_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA50" }, "PSS2.PS7_SAXIHP3RDATA51->PSS1_LOGIC_OUTS12_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA51" }, "PSS2.PS7_SAXIHP3RDATA52->PSS1_LOGIC_OUTS8_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA52" }, "PSS2.PS7_SAXIHP3RDATA53->PSS1_LOGIC_OUTS9_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA53" }, "PSS2.PS7_SAXIHP3RDATA54->PSS1_LOGIC_OUTS10_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA54" }, "PSS2.PS7_SAXIHP3RDATA55->PSS1_LOGIC_OUTS11_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA55" }, "PSS2.PS7_SAXIHP3RDATA56->PSS1_LOGIC_OUTS4_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS4_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA56" }, "PSS2.PS7_SAXIHP3RDATA57->PSS1_LOGIC_OUTS5_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA57" }, "PSS2.PS7_SAXIHP3RDATA58->PSS1_LOGIC_OUTS6_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA58" }, "PSS2.PS7_SAXIHP3RDATA59->PSS1_LOGIC_OUTS7_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA59" }, "PSS2.PS7_SAXIHP3RDATA6->PSS1_LOGIC_OUTS5_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA6" }, "PSS2.PS7_SAXIHP3RDATA60->PSS1_LOGIC_OUTS5_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS5_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA60" }, "PSS2.PS7_SAXIHP3RDATA61->PSS1_LOGIC_OUTS6_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA61" }, "PSS2.PS7_SAXIHP3RDATA62->PSS1_LOGIC_OUTS7_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS7_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA62" }, "PSS2.PS7_SAXIHP3RDATA63->PSS1_LOGIC_OUTS8_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA63" }, "PSS2.PS7_SAXIHP3RDATA7->PSS1_LOGIC_OUTS6_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS6_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA7" }, "PSS2.PS7_SAXIHP3RDATA8->PSS1_LOGIC_OUTS2_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA8" }, "PSS2.PS7_SAXIHP3RDATA9->PSS1_LOGIC_OUTS3_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS3_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RDATA9" }, "PSS2.PS7_SAXIHP3RID0->PSS1_LOGIC_OUTS0_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RID0" }, "PSS2.PS7_SAXIHP3RID1->PSS1_LOGIC_OUTS1_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RID1" }, "PSS2.PS7_SAXIHP3RID2->PSS1_LOGIC_OUTS2_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RID2" }, "PSS2.PS7_SAXIHP3RID3->PSS1_LOGIC_OUTS0_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS0_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RID3" }, "PSS2.PS7_SAXIHP3RID4->PSS1_LOGIC_OUTS1_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RID4" }, "PSS2.PS7_SAXIHP3RID5->PSS1_LOGIC_OUTS2_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS2_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RID5" }, "PSS2.PS7_SAXIHP3RLAST->PSS1_LOGIC_OUTS11_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RLAST" }, "PSS2.PS7_SAXIHP3RRESP0->PSS1_LOGIC_OUTS9_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RRESP0" }, "PSS2.PS7_SAXIHP3RRESP1->PSS1_LOGIC_OUTS10_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RRESP1" }, "PSS2.PS7_SAXIHP3RVALID->PSS1_LOGIC_OUTS12_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3RVALID" }, "PSS2.PS7_SAXIHP3WACOUNT0->PSS1_LOGIC_OUTS12_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WACOUNT0" }, "PSS2.PS7_SAXIHP3WACOUNT1->PSS1_LOGIC_OUTS13_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WACOUNT1" }, "PSS2.PS7_SAXIHP3WACOUNT2->PSS1_LOGIC_OUTS12_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WACOUNT2" }, "PSS2.PS7_SAXIHP3WACOUNT3->PSS1_LOGIC_OUTS13_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WACOUNT3" }, "PSS2.PS7_SAXIHP3WACOUNT4->PSS1_LOGIC_OUTS13_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS13_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WACOUNT4" }, "PSS2.PS7_SAXIHP3WACOUNT5->PSS1_LOGIC_OUTS14_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS14_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WACOUNT5" }, "PSS2.PS7_SAXIHP3WCOUNT0->PSS1_LOGIC_OUTS8_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS8_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WCOUNT0" }, "PSS2.PS7_SAXIHP3WCOUNT1->PSS1_LOGIC_OUTS9_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WCOUNT1" }, "PSS2.PS7_SAXIHP3WCOUNT2->PSS1_LOGIC_OUTS10_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WCOUNT2" }, "PSS2.PS7_SAXIHP3WCOUNT3->PSS1_LOGIC_OUTS11_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WCOUNT3" }, "PSS2.PS7_SAXIHP3WCOUNT4->PSS1_LOGIC_OUTS9_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS9_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WCOUNT4" }, "PSS2.PS7_SAXIHP3WCOUNT5->PSS1_LOGIC_OUTS10_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS10_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WCOUNT5" }, "PSS2.PS7_SAXIHP3WCOUNT6->PSS1_LOGIC_OUTS11_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS11_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WCOUNT6" }, "PSS2.PS7_SAXIHP3WCOUNT7->PSS1_LOGIC_OUTS12_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS12_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WCOUNT7" }, "PSS2.PS7_SAXIHP3WREADY->PSS1_LOGIC_OUTS1_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_LOGIC_OUTS1_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_SAXIHP3WREADY" }, "PSS2.PS7_TESTPLLCLKOUT0_PW->PS7_TESTPLLCLKOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_TESTPLLCLKOUT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_TESTPLLCLKOUT0_PW" }, "PSS2.PS7_TESTPLLCLKOUT1_PW->PS7_TESTPLLCLKOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_TESTPLLCLKOUT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_TESTPLLCLKOUT1_PW" }, "PSS2.PS7_TESTPLLCLKOUT2_PW->PS7_TESTPLLCLKOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_TESTPLLCLKOUT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_TESTPLLCLKOUT2_PW" }, "PSS2.PS7_TESTPLLNEWCLK0_PW->PS7_TESTPLLNEWCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_TESTPLLNEWCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_TESTPLLNEWCLK0_PW" }, "PSS2.PS7_TESTPLLNEWCLK1_PW->PS7_TESTPLLNEWCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_TESTPLLNEWCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_TESTPLLNEWCLK1_PW" }, "PSS2.PS7_TESTPLLNEWCLK2_PW->PS7_TESTPLLNEWCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_TESTPLLNEWCLK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PS7_TESTPLLNEWCLK2_PW" }, "PSS2.PSS1_CLK_B0_12->PS7_SAXIHP1ACLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ACLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_CLK_B0_12" }, "PSS2.PSS1_CLK_B0_20->PS7_SAXIHP2ACLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ACLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_CLK_B0_20" }, "PSS2.PSS1_CLK_B0_28->PS7_SAXIHP3ACLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ACLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_CLK_B0_28" }, "PSS2.PSS1_CLK_B0_35->PS7_SAXIACPACLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPACLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_CLK_B0_35" }, "PSS2.PSS1_CLK_B0_36->PS7_DMA0ACLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA0ACLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_CLK_B0_36" }, "PSS2.PSS1_CLK_B0_37->PS7_DMA1ACLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA1ACLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_CLK_B0_37" }, "PSS2.PSS1_CLK_B0_38->PS7_DMA2ACLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA2ACLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_CLK_B0_38" }, "PSS2.PSS1_CLK_B0_39->PS7_DMA3ACLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA3ACLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_CLK_B0_39" }, "PSS2.PSS1_CLK_B0_4->PS7_SAXIHP0ACLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ACLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_CLK_B0_4" }, "PSS2.PSS1_IMUX_B0_0->PS7_SAXIHP0AWADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_0" }, "PSS2.PSS1_IMUX_B0_1->PS7_SAXIHP0AWADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_1" }, "PSS2.PSS1_IMUX_B0_10->PS7_SAXIHP1AWADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_10" }, "PSS2.PSS1_IMUX_B0_11->PS7_SAXIHP1AWADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_11" }, "PSS2.PSS1_IMUX_B0_12->PS7_SAXIHP1AWADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_12" }, "PSS2.PSS1_IMUX_B0_13->PS7_SAXIHP1AWADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_13" }, "PSS2.PSS1_IMUX_B0_14->PS7_SAXIHP1AWID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_14" }, "PSS2.PSS1_IMUX_B0_15->PS7_SAXIHP1AWID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_15" }, "PSS2.PSS1_IMUX_B0_16->PS7_SAXIHP2AWADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_16" }, "PSS2.PSS1_IMUX_B0_17->PS7_SAXIHP2AWADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_17" }, "PSS2.PSS1_IMUX_B0_18->PS7_SAXIHP2AWADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_18" }, "PSS2.PSS1_IMUX_B0_19->PS7_SAXIHP2AWADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_19" }, "PSS2.PSS1_IMUX_B0_2->PS7_SAXIHP0AWADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_2" }, "PSS2.PSS1_IMUX_B0_20->PS7_SAXIHP2AWADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_20" }, "PSS2.PSS1_IMUX_B0_21->PS7_SAXIHP2AWADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_21" }, "PSS2.PSS1_IMUX_B0_22->PS7_SAXIHP2AWID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_22" }, "PSS2.PSS1_IMUX_B0_23->PS7_SAXIHP2AWID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_23" }, "PSS2.PSS1_IMUX_B0_24->PS7_SAXIHP3AWADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_24" }, "PSS2.PSS1_IMUX_B0_25->PS7_SAXIHP3AWADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_25" }, "PSS2.PSS1_IMUX_B0_26->PS7_SAXIHP3AWADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_26" }, "PSS2.PSS1_IMUX_B0_27->PS7_SAXIHP3AWADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_27" }, "PSS2.PSS1_IMUX_B0_28->PS7_SAXIHP3AWADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_28" }, "PSS2.PSS1_IMUX_B0_29->PS7_SAXIHP3AWADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_29" }, "PSS2.PSS1_IMUX_B0_3->PS7_SAXIHP0AWADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_3" }, "PSS2.PSS1_IMUX_B0_30->PS7_SAXIHP3AWID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_30" }, "PSS2.PSS1_IMUX_B0_31->PS7_SAXIHP3AWID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_31" }, "PSS2.PSS1_IMUX_B0_32->PS7_SAXIACPAWADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_32" }, "PSS2.PSS1_IMUX_B0_33->PS7_SAXIACPAWADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_33" }, "PSS2.PSS1_IMUX_B0_34->PS7_SAXIACPAWADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_34" }, "PSS2.PSS1_IMUX_B0_35->PS7_SAXIACPAWADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_35" }, "PSS2.PSS1_IMUX_B0_36->PS7_DMA0DAREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA0DAREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_36" }, "PSS2.PSS1_IMUX_B0_37->PS7_DMA1DAREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA1DAREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_37" }, "PSS2.PSS1_IMUX_B0_38->PS7_DMA2DAREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA2DAREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_38" }, "PSS2.PSS1_IMUX_B0_39->PS7_DMA3DAREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA3DAREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_39" }, "PSS2.PSS1_IMUX_B0_4->PS7_SAXIHP0AWADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_4" }, "PSS2.PSS1_IMUX_B0_5->PS7_SAXIHP0AWADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_5" }, "PSS2.PSS1_IMUX_B0_6->PS7_SAXIHP0AWID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_6" }, "PSS2.PSS1_IMUX_B0_7->PS7_SAXIHP0AWID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_7" }, "PSS2.PSS1_IMUX_B0_8->PS7_SAXIHP1AWADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_8" }, "PSS2.PSS1_IMUX_B0_9->PS7_SAXIHP1AWADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B0_9" }, "PSS2.PSS1_IMUX_B10_0->PS7_SAXIHP0WDATA34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_0" }, "PSS2.PSS1_IMUX_B10_1->PS7_SAXIHP0WDATA38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_1" }, "PSS2.PSS1_IMUX_B10_10->PS7_SAXIHP1WDATA42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_10" }, "PSS2.PSS1_IMUX_B10_11->PS7_SAXIHP1WDATA46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_11" }, "PSS2.PSS1_IMUX_B10_12->PS7_SAXIHP1WID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_12" }, "PSS2.PSS1_IMUX_B10_13->PS7_SAXIHP1WID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_13" }, "PSS2.PSS1_IMUX_B10_14->PS7_SAXIHP1AWBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_14" }, "PSS2.PSS1_IMUX_B10_15->PS7_SAXIHP1WDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_15" }, "PSS2.PSS1_IMUX_B10_16->PS7_SAXIHP2WDATA34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_16" }, "PSS2.PSS1_IMUX_B10_17->PS7_SAXIHP2WDATA38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_17" }, "PSS2.PSS1_IMUX_B10_18->PS7_SAXIHP2WDATA42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_18" }, "PSS2.PSS1_IMUX_B10_19->PS7_SAXIHP2WDATA46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_19" }, "PSS2.PSS1_IMUX_B10_2->PS7_SAXIHP0WDATA42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_2" }, "PSS2.PSS1_IMUX_B10_20->PS7_SAXIHP2WID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_20" }, "PSS2.PSS1_IMUX_B10_21->PS7_SAXIHP2WID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_21" }, "PSS2.PSS1_IMUX_B10_22->PS7_SAXIHP2AWBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_22" }, "PSS2.PSS1_IMUX_B10_23->PS7_SAXIHP2WDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_23" }, "PSS2.PSS1_IMUX_B10_24->PS7_SAXIHP3WDATA34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_24" }, "PSS2.PSS1_IMUX_B10_25->PS7_SAXIHP3WDATA38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_25" }, "PSS2.PSS1_IMUX_B10_26->PS7_SAXIHP3WDATA42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_26" }, "PSS2.PSS1_IMUX_B10_27->PS7_SAXIHP3WDATA46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_27" }, "PSS2.PSS1_IMUX_B10_28->PS7_SAXIHP3WID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_28" }, "PSS2.PSS1_IMUX_B10_29->PS7_SAXIHP3WID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_29" }, "PSS2.PSS1_IMUX_B10_3->PS7_SAXIHP0WDATA46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_3" }, "PSS2.PSS1_IMUX_B10_30->PS7_SAXIHP3AWBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_30" }, "PSS2.PSS1_IMUX_B10_31->PS7_SAXIHP3WDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_31" }, "PSS2.PSS1_IMUX_B10_32->PS7_SAXIACPWDATA34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_32" }, "PSS2.PSS1_IMUX_B10_33->PS7_SAXIACPWDATA38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_33" }, "PSS2.PSS1_IMUX_B10_34->PS7_SAXIACPWDATA42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_34" }, "PSS2.PSS1_IMUX_B10_35->PS7_SAXIACPWDATA45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_35" }, "PSS2.PSS1_IMUX_B10_36->PS7_SAXIACPAWUSER4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWUSER4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_36" }, "PSS2.PSS1_IMUX_B10_37->PS7_SAXIACPAWCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_37" }, "PSS2.PSS1_IMUX_B10_38->PS7_SAXIACPAWSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_38" }, "PSS2.PSS1_IMUX_B10_39->PS7_SAXIACPWDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_39" }, "PSS2.PSS1_IMUX_B10_4->PS7_SAXIHP0WID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_4" }, "PSS2.PSS1_IMUX_B10_5->PS7_SAXIHP0WID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_5" }, "PSS2.PSS1_IMUX_B10_6->PS7_SAXIHP0AWBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_6" }, "PSS2.PSS1_IMUX_B10_7->PS7_SAXIHP0WDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_7" }, "PSS2.PSS1_IMUX_B10_8->PS7_SAXIHP1WDATA34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_8" }, "PSS2.PSS1_IMUX_B10_9->PS7_SAXIHP1WDATA38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B10_9" }, "PSS2.PSS1_IMUX_B11_0->PS7_SAXIHP0WDATA35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_0" }, "PSS2.PSS1_IMUX_B11_1->PS7_SAXIHP0WDATA39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_1" }, "PSS2.PSS1_IMUX_B11_10->PS7_SAXIHP1WDATA43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_10" }, "PSS2.PSS1_IMUX_B11_11->PS7_SAXIHP1WDATA47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_11" }, "PSS2.PSS1_IMUX_B11_12->PS7_SAXIHP1WID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_12" }, "PSS2.PSS1_IMUX_B11_13->PS7_SAXIHP1WID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_13" }, "PSS2.PSS1_IMUX_B11_14->PS7_SAXIHP1WDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_14" }, "PSS2.PSS1_IMUX_B11_15->PS7_SAXIHP1WDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_15" }, "PSS2.PSS1_IMUX_B11_16->PS7_SAXIHP2WDATA35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_16" }, "PSS2.PSS1_IMUX_B11_17->PS7_SAXIHP2WDATA39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_17" }, "PSS2.PSS1_IMUX_B11_18->PS7_SAXIHP2WDATA43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_18" }, "PSS2.PSS1_IMUX_B11_19->PS7_SAXIHP2WDATA47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_19" }, "PSS2.PSS1_IMUX_B11_2->PS7_SAXIHP0WDATA43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_2" }, "PSS2.PSS1_IMUX_B11_20->PS7_SAXIHP2WID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_20" }, "PSS2.PSS1_IMUX_B11_21->PS7_SAXIHP2WID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_21" }, "PSS2.PSS1_IMUX_B11_22->PS7_SAXIHP2WDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_22" }, "PSS2.PSS1_IMUX_B11_23->PS7_SAXIHP2WDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_23" }, "PSS2.PSS1_IMUX_B11_24->PS7_SAXIHP3WDATA35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_24" }, "PSS2.PSS1_IMUX_B11_25->PS7_SAXIHP3WDATA39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_25" }, "PSS2.PSS1_IMUX_B11_26->PS7_SAXIHP3WDATA43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_26" }, "PSS2.PSS1_IMUX_B11_27->PS7_SAXIHP3WDATA47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_27" }, "PSS2.PSS1_IMUX_B11_28->PS7_SAXIHP3WID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_28" }, "PSS2.PSS1_IMUX_B11_29->PS7_SAXIHP3WID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_29" }, "PSS2.PSS1_IMUX_B11_3->PS7_SAXIHP0WDATA47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_3" }, "PSS2.PSS1_IMUX_B11_30->PS7_SAXIHP3WDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_30" }, "PSS2.PSS1_IMUX_B11_31->PS7_SAXIHP3WDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_31" }, "PSS2.PSS1_IMUX_B11_32->PS7_SAXIACPWDATA35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_32" }, "PSS2.PSS1_IMUX_B11_33->PS7_SAXIACPWDATA39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_33" }, "PSS2.PSS1_IMUX_B11_34->PS7_SAXIACPWDATA43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_34" }, "PSS2.PSS1_IMUX_B11_35->PS7_SAXIACPWDATA46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_35" }, "PSS2.PSS1_IMUX_B11_36->PS7_SAXIACPWID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_36" }, "PSS2.PSS1_IMUX_B11_37->PS7_SAXIACPAWCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_37" }, "PSS2.PSS1_IMUX_B11_38->PS7_SAXIACPAWSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_38" }, "PSS2.PSS1_IMUX_B11_39->PS7_SAXIACPWDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_39" }, "PSS2.PSS1_IMUX_B11_4->PS7_SAXIHP0WID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_4" }, "PSS2.PSS1_IMUX_B11_5->PS7_SAXIHP0WID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_5" }, "PSS2.PSS1_IMUX_B11_6->PS7_SAXIHP0WDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_6" }, "PSS2.PSS1_IMUX_B11_7->PS7_SAXIHP0WDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_7" }, "PSS2.PSS1_IMUX_B11_8->PS7_SAXIHP1WDATA35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_8" }, "PSS2.PSS1_IMUX_B11_9->PS7_SAXIHP1WDATA39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B11_9" }, "PSS2.PSS1_IMUX_B12_0->PS7_SAXIHP0ARID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_0" }, "PSS2.PSS1_IMUX_B12_1->PS7_SAXIHP0ARID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_1" }, "PSS2.PSS1_IMUX_B12_10->PS7_SAXIHP1WSTRB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WSTRB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_10" }, "PSS2.PSS1_IMUX_B12_11->PS7_SAXIHP1WSTRB4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WSTRB4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_11" }, "PSS2.PSS1_IMUX_B12_12->PS7_SAXIHP1WDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_12" }, "PSS2.PSS1_IMUX_B12_13->PS7_SAXIHP1WID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_13" }, "PSS2.PSS1_IMUX_B12_14->PS7_SAXIHP1WDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_14" }, "PSS2.PSS1_IMUX_B12_15->PS7_SAXIHP1WDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_15" }, "PSS2.PSS1_IMUX_B12_16->PS7_SAXIHP2ARID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_16" }, "PSS2.PSS1_IMUX_B12_17->PS7_SAXIHP2ARID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_17" }, "PSS2.PSS1_IMUX_B12_18->PS7_SAXIHP2WSTRB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WSTRB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_18" }, "PSS2.PSS1_IMUX_B12_19->PS7_SAXIHP2WSTRB4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WSTRB4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_19" }, "PSS2.PSS1_IMUX_B12_2->PS7_SAXIHP0WSTRB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WSTRB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_2" }, "PSS2.PSS1_IMUX_B12_20->PS7_SAXIHP2WDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_20" }, "PSS2.PSS1_IMUX_B12_21->PS7_SAXIHP2WID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_21" }, "PSS2.PSS1_IMUX_B12_22->PS7_SAXIHP2WDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_22" }, "PSS2.PSS1_IMUX_B12_23->PS7_SAXIHP2WDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_23" }, "PSS2.PSS1_IMUX_B12_24->PS7_SAXIHP3ARID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_24" }, "PSS2.PSS1_IMUX_B12_25->PS7_SAXIHP3ARID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_25" }, "PSS2.PSS1_IMUX_B12_26->PS7_SAXIHP3WSTRB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WSTRB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_26" }, "PSS2.PSS1_IMUX_B12_27->PS7_SAXIHP3WSTRB4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WSTRB4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_27" }, "PSS2.PSS1_IMUX_B12_28->PS7_SAXIHP3WDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_28" }, "PSS2.PSS1_IMUX_B12_29->PS7_SAXIHP3WID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_29" }, "PSS2.PSS1_IMUX_B12_3->PS7_SAXIHP0WSTRB4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WSTRB4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_3" }, "PSS2.PSS1_IMUX_B12_30->PS7_SAXIHP3WDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_30" }, "PSS2.PSS1_IMUX_B12_31->PS7_SAXIHP3WDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_31" }, "PSS2.PSS1_IMUX_B12_32->PS7_SAXIACPARADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_32" }, "PSS2.PSS1_IMUX_B12_33->PS7_SAXIACPARADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_33" }, "PSS2.PSS1_IMUX_B12_34->PS7_SAXIACPWSTRB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWSTRB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_34" }, "PSS2.PSS1_IMUX_B12_35->PS7_SAXIACPWDATA47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_35" }, "PSS2.PSS1_IMUX_B12_36->PS7_SAXIACPWID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_36" }, "PSS2.PSS1_IMUX_B12_37->PS7_SAXIACPAWPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_37" }, "PSS2.PSS1_IMUX_B12_38->PS7_SAXIACPAWBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_38" }, "PSS2.PSS1_IMUX_B12_39->PS7_SAXIACPWDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_39" }, "PSS2.PSS1_IMUX_B12_4->PS7_SAXIHP0WDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_4" }, "PSS2.PSS1_IMUX_B12_5->PS7_SAXIHP0WID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_5" }, "PSS2.PSS1_IMUX_B12_6->PS7_SAXIHP0WDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_6" }, "PSS2.PSS1_IMUX_B12_7->PS7_SAXIHP0WDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_7" }, "PSS2.PSS1_IMUX_B12_8->PS7_SAXIHP1ARID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_8" }, "PSS2.PSS1_IMUX_B12_9->PS7_SAXIHP1ARID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B12_9" }, "PSS2.PSS1_IMUX_B13_0->PS7_SAXIHP0ARID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_0" }, "PSS2.PSS1_IMUX_B13_1->PS7_SAXIHP0ARID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_1" }, "PSS2.PSS1_IMUX_B13_10->PS7_SAXIHP1WSTRB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WSTRB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_10" }, "PSS2.PSS1_IMUX_B13_11->PS7_SAXIHP1WSTRB5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WSTRB5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_11" }, "PSS2.PSS1_IMUX_B13_12->PS7_SAXIHP1WDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_12" }, "PSS2.PSS1_IMUX_B13_13->PS7_SAXIHP1WDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_13" }, "PSS2.PSS1_IMUX_B13_14->PS7_SAXIHP1WDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_14" }, "PSS2.PSS1_IMUX_B13_15->PS7_SAXIHP1WDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_15" }, "PSS2.PSS1_IMUX_B13_16->PS7_SAXIHP2ARID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_16" }, "PSS2.PSS1_IMUX_B13_17->PS7_SAXIHP2ARID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_17" }, "PSS2.PSS1_IMUX_B13_18->PS7_SAXIHP2WSTRB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WSTRB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_18" }, "PSS2.PSS1_IMUX_B13_19->PS7_SAXIHP2WSTRB5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WSTRB5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_19" }, "PSS2.PSS1_IMUX_B13_2->PS7_SAXIHP0WSTRB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WSTRB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_2" }, "PSS2.PSS1_IMUX_B13_20->PS7_SAXIHP2WDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_20" }, "PSS2.PSS1_IMUX_B13_21->PS7_SAXIHP2WDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_21" }, "PSS2.PSS1_IMUX_B13_22->PS7_SAXIHP2WDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_22" }, "PSS2.PSS1_IMUX_B13_23->PS7_SAXIHP2WDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_23" }, "PSS2.PSS1_IMUX_B13_24->PS7_SAXIHP3ARID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_24" }, "PSS2.PSS1_IMUX_B13_25->PS7_SAXIHP3ARID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_25" }, "PSS2.PSS1_IMUX_B13_26->PS7_SAXIHP3WSTRB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WSTRB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_26" }, "PSS2.PSS1_IMUX_B13_27->PS7_SAXIHP3WSTRB5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WSTRB5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_27" }, "PSS2.PSS1_IMUX_B13_28->PS7_SAXIHP3WDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_28" }, "PSS2.PSS1_IMUX_B13_29->PS7_SAXIHP3WDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_29" }, "PSS2.PSS1_IMUX_B13_3->PS7_SAXIHP0WSTRB5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WSTRB5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_3" }, "PSS2.PSS1_IMUX_B13_30->PS7_SAXIHP3WDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_30" }, "PSS2.PSS1_IMUX_B13_31->PS7_SAXIHP3WDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_31" }, "PSS2.PSS1_IMUX_B13_32->PS7_SAXIACPARADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_32" }, "PSS2.PSS1_IMUX_B13_33->PS7_SAXIACPARADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_33" }, "PSS2.PSS1_IMUX_B13_34->PS7_SAXIACPWSTRB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWSTRB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_34" }, "PSS2.PSS1_IMUX_B13_35->PS7_SAXIACPWSTRB4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWSTRB4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_35" }, "PSS2.PSS1_IMUX_B13_36->PS7_SAXIACPWID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_36" }, "PSS2.PSS1_IMUX_B13_37->PS7_SAXIACPAWPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_37" }, "PSS2.PSS1_IMUX_B13_38->PS7_SAXIACPAWBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_38" }, "PSS2.PSS1_IMUX_B13_39->PS7_SAXIACPWDATA60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_39" }, "PSS2.PSS1_IMUX_B13_4->PS7_SAXIHP0WDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_4" }, "PSS2.PSS1_IMUX_B13_5->PS7_SAXIHP0WDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_5" }, "PSS2.PSS1_IMUX_B13_6->PS7_SAXIHP0WDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_6" }, "PSS2.PSS1_IMUX_B13_7->PS7_SAXIHP0WDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_7" }, "PSS2.PSS1_IMUX_B13_8->PS7_SAXIHP1ARID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_8" }, "PSS2.PSS1_IMUX_B13_9->PS7_SAXIHP1ARID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B13_9" }, "PSS2.PSS1_IMUX_B14_0->PS7_SAXIHP0ARID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_0" }, "PSS2.PSS1_IMUX_B14_1->PS7_SAXIHP0ARADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_1" }, "PSS2.PSS1_IMUX_B14_10->PS7_SAXIHP1WSTRB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WSTRB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_10" }, "PSS2.PSS1_IMUX_B14_11->PS7_SAXIHP1WSTRB6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WSTRB6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_11" }, "PSS2.PSS1_IMUX_B14_12->PS7_SAXIHP1WDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_12" }, "PSS2.PSS1_IMUX_B14_13->PS7_SAXIHP1WDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_13" }, "PSS2.PSS1_IMUX_B14_14->PS7_SAXIHP1WDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_14" }, "PSS2.PSS1_IMUX_B14_15->PS7_SAXIHP1WDATA60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_15" }, "PSS2.PSS1_IMUX_B14_16->PS7_SAXIHP2ARID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_16" }, "PSS2.PSS1_IMUX_B14_17->PS7_SAXIHP2ARADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_17" }, "PSS2.PSS1_IMUX_B14_18->PS7_SAXIHP2WSTRB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WSTRB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_18" }, "PSS2.PSS1_IMUX_B14_19->PS7_SAXIHP2WSTRB6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WSTRB6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_19" }, "PSS2.PSS1_IMUX_B14_2->PS7_SAXIHP0WSTRB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WSTRB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_2" }, "PSS2.PSS1_IMUX_B14_20->PS7_SAXIHP2WDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_20" }, "PSS2.PSS1_IMUX_B14_21->PS7_SAXIHP2WDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_21" }, "PSS2.PSS1_IMUX_B14_22->PS7_SAXIHP2WDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_22" }, "PSS2.PSS1_IMUX_B14_23->PS7_SAXIHP2WDATA60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_23" }, "PSS2.PSS1_IMUX_B14_24->PS7_SAXIHP3ARID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_24" }, "PSS2.PSS1_IMUX_B14_25->PS7_SAXIHP3ARADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_25" }, "PSS2.PSS1_IMUX_B14_26->PS7_SAXIHP3WSTRB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WSTRB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_26" }, "PSS2.PSS1_IMUX_B14_27->PS7_SAXIHP3WSTRB6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WSTRB6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_27" }, "PSS2.PSS1_IMUX_B14_28->PS7_SAXIHP3WDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_28" }, "PSS2.PSS1_IMUX_B14_29->PS7_SAXIHP3WDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_29" }, "PSS2.PSS1_IMUX_B14_3->PS7_SAXIHP0WSTRB6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WSTRB6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_3" }, "PSS2.PSS1_IMUX_B14_30->PS7_SAXIHP3WDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_30" }, "PSS2.PSS1_IMUX_B14_31->PS7_SAXIHP3WDATA60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_31" }, "PSS2.PSS1_IMUX_B14_32->PS7_SAXIACPARADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_32" }, "PSS2.PSS1_IMUX_B14_33->PS7_SAXIACPARADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_33" }, "PSS2.PSS1_IMUX_B14_34->PS7_SAXIACPWSTRB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWSTRB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_34" }, "PSS2.PSS1_IMUX_B14_35->PS7_SAXIACPWSTRB5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWSTRB5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_35" }, "PSS2.PSS1_IMUX_B14_36->PS7_SAXIACPWDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_36" }, "PSS2.PSS1_IMUX_B14_37->PS7_SAXIACPAWPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_37" }, "PSS2.PSS1_IMUX_B14_38->PS7_SAXIACPWDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_38" }, "PSS2.PSS1_IMUX_B14_39->PS7_SAXIACPWDATA61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_39" }, "PSS2.PSS1_IMUX_B14_4->PS7_SAXIHP0WDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_4" }, "PSS2.PSS1_IMUX_B14_5->PS7_SAXIHP0WDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_5" }, "PSS2.PSS1_IMUX_B14_6->PS7_SAXIHP0WDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_6" }, "PSS2.PSS1_IMUX_B14_7->PS7_SAXIHP0WDATA60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_7" }, "PSS2.PSS1_IMUX_B14_8->PS7_SAXIHP1ARID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_8" }, "PSS2.PSS1_IMUX_B14_9->PS7_SAXIHP1ARADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B14_9" }, "PSS2.PSS1_IMUX_B15_0->PS7_SAXIHP0ARID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_0" }, "PSS2.PSS1_IMUX_B15_1->PS7_SAXIHP0ARADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_1" }, "PSS2.PSS1_IMUX_B15_10->PS7_SAXIHP1WSTRB3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WSTRB3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_10" }, "PSS2.PSS1_IMUX_B15_11->PS7_SAXIHP1WSTRB7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WSTRB7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_11" }, "PSS2.PSS1_IMUX_B15_12->PS7_SAXIHP1WDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_12" }, "PSS2.PSS1_IMUX_B15_13->PS7_SAXIHP1WDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_13" }, "PSS2.PSS1_IMUX_B15_14->PS7_SAXIHP1WDATA56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_14" }, "PSS2.PSS1_IMUX_B15_15->PS7_SAXIHP1WDATA61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_15" }, "PSS2.PSS1_IMUX_B15_16->PS7_SAXIHP2ARID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_16" }, "PSS2.PSS1_IMUX_B15_17->PS7_SAXIHP2ARADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_17" }, "PSS2.PSS1_IMUX_B15_18->PS7_SAXIHP2WSTRB3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WSTRB3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_18" }, "PSS2.PSS1_IMUX_B15_19->PS7_SAXIHP2WSTRB7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WSTRB7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_19" }, "PSS2.PSS1_IMUX_B15_2->PS7_SAXIHP0WSTRB3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WSTRB3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_2" }, "PSS2.PSS1_IMUX_B15_20->PS7_SAXIHP2WDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_20" }, "PSS2.PSS1_IMUX_B15_21->PS7_SAXIHP2WDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_21" }, "PSS2.PSS1_IMUX_B15_22->PS7_SAXIHP2WDATA56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_22" }, "PSS2.PSS1_IMUX_B15_23->PS7_SAXIHP2WDATA61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_23" }, "PSS2.PSS1_IMUX_B15_24->PS7_SAXIHP3ARID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_24" }, "PSS2.PSS1_IMUX_B15_25->PS7_SAXIHP3ARADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_25" }, "PSS2.PSS1_IMUX_B15_26->PS7_SAXIHP3WSTRB3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WSTRB3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_26" }, "PSS2.PSS1_IMUX_B15_27->PS7_SAXIHP3WSTRB7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WSTRB7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_27" }, "PSS2.PSS1_IMUX_B15_28->PS7_SAXIHP3WDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_28" }, "PSS2.PSS1_IMUX_B15_29->PS7_SAXIHP3WDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_29" }, "PSS2.PSS1_IMUX_B15_3->PS7_SAXIHP0WSTRB7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WSTRB7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_3" }, "PSS2.PSS1_IMUX_B15_30->PS7_SAXIHP3WDATA56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_30" }, "PSS2.PSS1_IMUX_B15_31->PS7_SAXIHP3WDATA61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_31" }, "PSS2.PSS1_IMUX_B15_32->PS7_SAXIACPARADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_32" }, "PSS2.PSS1_IMUX_B15_33->PS7_SAXIACPARADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_33" }, "PSS2.PSS1_IMUX_B15_34->PS7_SAXIACPWSTRB3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWSTRB3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_34" }, "PSS2.PSS1_IMUX_B15_35->PS7_SAXIACPWSTRB6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWSTRB6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_35" }, "PSS2.PSS1_IMUX_B15_36->PS7_SAXIACPWDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_36" }, "PSS2.PSS1_IMUX_B15_37->PS7_SAXIACPWDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_37" }, "PSS2.PSS1_IMUX_B15_38->PS7_SAXIACPWDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_38" }, "PSS2.PSS1_IMUX_B15_39->PS7_SAXIACPWDATA62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_39" }, "PSS2.PSS1_IMUX_B15_4->PS7_SAXIHP0WDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_4" }, "PSS2.PSS1_IMUX_B15_5->PS7_SAXIHP0WDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_5" }, "PSS2.PSS1_IMUX_B15_6->PS7_SAXIHP0WDATA56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_6" }, "PSS2.PSS1_IMUX_B15_7->PS7_SAXIHP0WDATA61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_7" }, "PSS2.PSS1_IMUX_B15_8->PS7_SAXIHP1ARID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_8" }, "PSS2.PSS1_IMUX_B15_9->PS7_SAXIHP1ARADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B15_9" }, "PSS2.PSS1_IMUX_B16_0->PS7_SAXIHP0ARADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_0" }, "PSS2.PSS1_IMUX_B16_1->PS7_SAXIHP0ARADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_1" }, "PSS2.PSS1_IMUX_B16_10->PS7_SAXIHP1WLAST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WLAST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_10" }, "PSS2.PSS1_IMUX_B16_11->PS7_SAXIHP1ARADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_11" }, "PSS2.PSS1_IMUX_B16_12->PS7_SAXIHP1WDATA48": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA48", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_12" }, "PSS2.PSS1_IMUX_B16_13->PS7_SAXIHP1WDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_13" }, "PSS2.PSS1_IMUX_B16_14->PS7_SAXIHP1WDATA57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_14" }, "PSS2.PSS1_IMUX_B16_15->PS7_SAXIHP1WDATA62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_15" }, "PSS2.PSS1_IMUX_B16_16->PS7_SAXIHP2ARADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_16" }, "PSS2.PSS1_IMUX_B16_17->PS7_SAXIHP2ARADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_17" }, "PSS2.PSS1_IMUX_B16_18->PS7_SAXIHP2WLAST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WLAST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_18" }, "PSS2.PSS1_IMUX_B16_19->PS7_SAXIHP2ARADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_19" }, "PSS2.PSS1_IMUX_B16_2->PS7_SAXIHP0WLAST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WLAST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_2" }, "PSS2.PSS1_IMUX_B16_20->PS7_SAXIHP2WDATA48": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA48", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_20" }, "PSS2.PSS1_IMUX_B16_21->PS7_SAXIHP2WDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_21" }, "PSS2.PSS1_IMUX_B16_22->PS7_SAXIHP2WDATA57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_22" }, "PSS2.PSS1_IMUX_B16_23->PS7_SAXIHP2WDATA62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_23" }, "PSS2.PSS1_IMUX_B16_24->PS7_SAXIHP3ARADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_24" }, "PSS2.PSS1_IMUX_B16_25->PS7_SAXIHP3ARADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_25" }, "PSS2.PSS1_IMUX_B16_26->PS7_SAXIHP3WLAST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WLAST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_26" }, "PSS2.PSS1_IMUX_B16_27->PS7_SAXIHP3ARADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_27" }, "PSS2.PSS1_IMUX_B16_28->PS7_SAXIHP3WDATA48": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA48", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_28" }, "PSS2.PSS1_IMUX_B16_29->PS7_SAXIHP3WDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_29" }, "PSS2.PSS1_IMUX_B16_3->PS7_SAXIHP0ARADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_3" }, "PSS2.PSS1_IMUX_B16_30->PS7_SAXIHP3WDATA57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_30" }, "PSS2.PSS1_IMUX_B16_31->PS7_SAXIHP3WDATA62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_31" }, "PSS2.PSS1_IMUX_B16_32->PS7_SAXIACPARLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_32" }, "PSS2.PSS1_IMUX_B16_33->PS7_SAXIACPARLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_33" }, "PSS2.PSS1_IMUX_B16_34->PS7_SAXIACPARID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_34" }, "PSS2.PSS1_IMUX_B16_35->PS7_SAXIACPWSTRB7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWSTRB7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_35" }, "PSS2.PSS1_IMUX_B16_36->PS7_SAXIACPWDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_36" }, "PSS2.PSS1_IMUX_B16_37->PS7_SAXIACPWDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_37" }, "PSS2.PSS1_IMUX_B16_38->PS7_SAXIACPWDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_38" }, "PSS2.PSS1_IMUX_B16_39->PS7_SAXIACPWDATA63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_39" }, "PSS2.PSS1_IMUX_B16_4->PS7_SAXIHP0WDATA48": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA48", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_4" }, "PSS2.PSS1_IMUX_B16_5->PS7_SAXIHP0WDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_5" }, "PSS2.PSS1_IMUX_B16_6->PS7_SAXIHP0WDATA57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_6" }, "PSS2.PSS1_IMUX_B16_7->PS7_SAXIHP0WDATA62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_7" }, "PSS2.PSS1_IMUX_B16_8->PS7_SAXIHP1ARADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_8" }, "PSS2.PSS1_IMUX_B16_9->PS7_SAXIHP1ARADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B16_9" }, "PSS2.PSS1_IMUX_B17_0->PS7_SAXIHP0ARADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_0" }, "PSS2.PSS1_IMUX_B17_1->PS7_SAXIHP0ARADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_1" }, "PSS2.PSS1_IMUX_B17_10->PS7_SAXIHP1ARADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_10" }, "PSS2.PSS1_IMUX_B17_11->PS7_SAXIHP1ARADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_11" }, "PSS2.PSS1_IMUX_B17_12->PS7_SAXIHP1WDATA49": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA49", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_12" }, "PSS2.PSS1_IMUX_B17_13->PS7_SAXIHP1WDATA52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_13" }, "PSS2.PSS1_IMUX_B17_14->PS7_SAXIHP1WDATA58": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA58", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_14" }, "PSS2.PSS1_IMUX_B17_15->PS7_SAXIHP1WDATA63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_15" }, "PSS2.PSS1_IMUX_B17_16->PS7_SAXIHP2ARADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_16" }, "PSS2.PSS1_IMUX_B17_17->PS7_SAXIHP2ARADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_17" }, "PSS2.PSS1_IMUX_B17_18->PS7_SAXIHP2ARADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_18" }, "PSS2.PSS1_IMUX_B17_19->PS7_SAXIHP2ARADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_19" }, "PSS2.PSS1_IMUX_B17_2->PS7_SAXIHP0ARADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_2" }, "PSS2.PSS1_IMUX_B17_20->PS7_SAXIHP2WDATA49": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA49", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_20" }, "PSS2.PSS1_IMUX_B17_21->PS7_SAXIHP2WDATA52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_21" }, "PSS2.PSS1_IMUX_B17_22->PS7_SAXIHP2WDATA58": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA58", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_22" }, "PSS2.PSS1_IMUX_B17_23->PS7_SAXIHP2WDATA63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_23" }, "PSS2.PSS1_IMUX_B17_24->PS7_SAXIHP3ARADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_24" }, "PSS2.PSS1_IMUX_B17_25->PS7_SAXIHP3ARADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_25" }, "PSS2.PSS1_IMUX_B17_26->PS7_SAXIHP3ARADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_26" }, "PSS2.PSS1_IMUX_B17_27->PS7_SAXIHP3ARADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_27" }, "PSS2.PSS1_IMUX_B17_28->PS7_SAXIHP3WDATA49": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA49", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_28" }, "PSS2.PSS1_IMUX_B17_29->PS7_SAXIHP3WDATA52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_29" }, "PSS2.PSS1_IMUX_B17_3->PS7_SAXIHP0ARADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_3" }, "PSS2.PSS1_IMUX_B17_30->PS7_SAXIHP3WDATA58": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA58", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_30" }, "PSS2.PSS1_IMUX_B17_31->PS7_SAXIHP3WDATA63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_31" }, "PSS2.PSS1_IMUX_B17_32->PS7_SAXIACPARLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_32" }, "PSS2.PSS1_IMUX_B17_33->PS7_SAXIACPARLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_33" }, "PSS2.PSS1_IMUX_B17_34->PS7_SAXIACPARID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_34" }, "PSS2.PSS1_IMUX_B17_35->PS7_SAXIACPWLAST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWLAST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_35" }, "PSS2.PSS1_IMUX_B17_36->PS7_SAXIACPWDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_36" }, "PSS2.PSS1_IMUX_B17_37->PS7_SAXIACPWDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_37" }, "PSS2.PSS1_IMUX_B17_38->PS7_SAXIACPWDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_38" }, "PSS2.PSS1_IMUX_B17_39->PS7_SAXIACPARADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_39" }, "PSS2.PSS1_IMUX_B17_4->PS7_SAXIHP0WDATA49": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA49", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_4" }, "PSS2.PSS1_IMUX_B17_5->PS7_SAXIHP0WDATA52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_5" }, "PSS2.PSS1_IMUX_B17_6->PS7_SAXIHP0WDATA58": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA58", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_6" }, "PSS2.PSS1_IMUX_B17_7->PS7_SAXIHP0WDATA63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_7" }, "PSS2.PSS1_IMUX_B17_8->PS7_SAXIHP1ARADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_8" }, "PSS2.PSS1_IMUX_B17_9->PS7_SAXIHP1ARADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B17_9" }, "PSS2.PSS1_IMUX_B18_0->PS7_SAXIHP0ARADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_0" }, "PSS2.PSS1_IMUX_B18_1->PS7_SAXIHP0ARLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_1" }, "PSS2.PSS1_IMUX_B18_10->PS7_SAXIHP1ARADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_10" }, "PSS2.PSS1_IMUX_B18_11->PS7_SAXIHP1ARADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_11" }, "PSS2.PSS1_IMUX_B18_12->PS7_SAXIHP1WDATA50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_12" }, "PSS2.PSS1_IMUX_B18_13->PS7_SAXIHP1WDATA53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_13" }, "PSS2.PSS1_IMUX_B18_14->PS7_SAXIHP1WDATA59": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA59", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_14" }, "PSS2.PSS1_IMUX_B18_15->PS7_SAXIHP1ARADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_15" }, "PSS2.PSS1_IMUX_B18_16->PS7_SAXIHP2ARADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_16" }, "PSS2.PSS1_IMUX_B18_17->PS7_SAXIHP2ARLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_17" }, "PSS2.PSS1_IMUX_B18_18->PS7_SAXIHP2ARADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_18" }, "PSS2.PSS1_IMUX_B18_19->PS7_SAXIHP2ARADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_19" }, "PSS2.PSS1_IMUX_B18_2->PS7_SAXIHP0ARADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_2" }, "PSS2.PSS1_IMUX_B18_20->PS7_SAXIHP2WDATA50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_20" }, "PSS2.PSS1_IMUX_B18_21->PS7_SAXIHP2WDATA53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_21" }, "PSS2.PSS1_IMUX_B18_22->PS7_SAXIHP2WDATA59": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA59", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_22" }, "PSS2.PSS1_IMUX_B18_23->PS7_SAXIHP2ARADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_23" }, "PSS2.PSS1_IMUX_B18_24->PS7_SAXIHP3ARADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_24" }, "PSS2.PSS1_IMUX_B18_25->PS7_SAXIHP3ARLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_25" }, "PSS2.PSS1_IMUX_B18_26->PS7_SAXIHP3ARADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_26" }, "PSS2.PSS1_IMUX_B18_27->PS7_SAXIHP3ARADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_27" }, "PSS2.PSS1_IMUX_B18_28->PS7_SAXIHP3WDATA50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_28" }, "PSS2.PSS1_IMUX_B18_29->PS7_SAXIHP3WDATA53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_29" }, "PSS2.PSS1_IMUX_B18_3->PS7_SAXIHP0ARADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_3" }, "PSS2.PSS1_IMUX_B18_30->PS7_SAXIHP3WDATA59": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA59", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_30" }, "PSS2.PSS1_IMUX_B18_31->PS7_SAXIHP3ARADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_31" }, "PSS2.PSS1_IMUX_B18_32->PS7_SAXIACPARBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_32" }, "PSS2.PSS1_IMUX_B18_33->PS7_SAXIACPARSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_33" }, "PSS2.PSS1_IMUX_B18_34->PS7_SAXIACPARADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_34" }, "PSS2.PSS1_IMUX_B18_35->PS7_SAXIACPWVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_35" }, "PSS2.PSS1_IMUX_B18_36->PS7_SAXIACPWDATA48": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA48", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_36" }, "PSS2.PSS1_IMUX_B18_37->PS7_SAXIACPWDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_37" }, "PSS2.PSS1_IMUX_B18_38->PS7_SAXIACPWDATA56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_38" }, "PSS2.PSS1_IMUX_B18_39->PS7_SAXIACPARADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_39" }, "PSS2.PSS1_IMUX_B18_4->PS7_SAXIHP0WDATA50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_4" }, "PSS2.PSS1_IMUX_B18_5->PS7_SAXIHP0WDATA53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_5" }, "PSS2.PSS1_IMUX_B18_6->PS7_SAXIHP0WDATA59": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA59", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_6" }, "PSS2.PSS1_IMUX_B18_7->PS7_SAXIHP0ARADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_7" }, "PSS2.PSS1_IMUX_B18_8->PS7_SAXIHP1ARADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_8" }, "PSS2.PSS1_IMUX_B18_9->PS7_SAXIHP1ARLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B18_9" }, "PSS2.PSS1_IMUX_B19_0->PS7_SAXIHP0ARADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_0" }, "PSS2.PSS1_IMUX_B19_1->PS7_SAXIHP0ARCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_1" }, "PSS2.PSS1_IMUX_B19_10->PS7_SAXIHP1ARADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_10" }, "PSS2.PSS1_IMUX_B19_11->PS7_SAXIHP1ARADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_11" }, "PSS2.PSS1_IMUX_B19_12->PS7_SAXIHP1WDATA51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_12" }, "PSS2.PSS1_IMUX_B19_13->PS7_SAXIHP1WDATA54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_13" }, "PSS2.PSS1_IMUX_B19_14->PS7_SAXIHP1ARADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_14" }, "PSS2.PSS1_IMUX_B19_15->PS7_SAXIHP1ARADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_15" }, "PSS2.PSS1_IMUX_B19_16->PS7_SAXIHP2ARADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_16" }, "PSS2.PSS1_IMUX_B19_17->PS7_SAXIHP2ARCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_17" }, "PSS2.PSS1_IMUX_B19_18->PS7_SAXIHP2ARADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_18" }, "PSS2.PSS1_IMUX_B19_19->PS7_SAXIHP2ARADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_19" }, "PSS2.PSS1_IMUX_B19_2->PS7_SAXIHP0ARADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_2" }, "PSS2.PSS1_IMUX_B19_20->PS7_SAXIHP2WDATA51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_20" }, "PSS2.PSS1_IMUX_B19_21->PS7_SAXIHP2WDATA54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_21" }, "PSS2.PSS1_IMUX_B19_22->PS7_SAXIHP2ARADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_22" }, "PSS2.PSS1_IMUX_B19_23->PS7_SAXIHP2ARADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_23" }, "PSS2.PSS1_IMUX_B19_24->PS7_SAXIHP3ARADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_24" }, "PSS2.PSS1_IMUX_B19_25->PS7_SAXIHP3ARCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_25" }, "PSS2.PSS1_IMUX_B19_26->PS7_SAXIHP3ARADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_26" }, "PSS2.PSS1_IMUX_B19_27->PS7_SAXIHP3ARADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_27" }, "PSS2.PSS1_IMUX_B19_28->PS7_SAXIHP3WDATA51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_28" }, "PSS2.PSS1_IMUX_B19_29->PS7_SAXIHP3WDATA54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_29" }, "PSS2.PSS1_IMUX_B19_3->PS7_SAXIHP0ARADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_3" }, "PSS2.PSS1_IMUX_B19_30->PS7_SAXIHP3ARADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_30" }, "PSS2.PSS1_IMUX_B19_31->PS7_SAXIHP3ARADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_31" }, "PSS2.PSS1_IMUX_B19_32->PS7_SAXIACPARBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_32" }, "PSS2.PSS1_IMUX_B19_33->PS7_SAXIACPARSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_33" }, "PSS2.PSS1_IMUX_B19_34->PS7_SAXIACPARADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_34" }, "PSS2.PSS1_IMUX_B19_35->PS7_SAXIACPARID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_35" }, "PSS2.PSS1_IMUX_B19_36->PS7_SAXIACPWDATA49": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA49", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_36" }, "PSS2.PSS1_IMUX_B19_37->PS7_SAXIACPWDATA52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_37" }, "PSS2.PSS1_IMUX_B19_38->PS7_SAXIACPWDATA57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_38" }, "PSS2.PSS1_IMUX_B19_39->PS7_SAXIACPARADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_39" }, "PSS2.PSS1_IMUX_B19_4->PS7_SAXIHP0WDATA51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_4" }, "PSS2.PSS1_IMUX_B19_5->PS7_SAXIHP0WDATA54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_5" }, "PSS2.PSS1_IMUX_B19_6->PS7_SAXIHP0ARADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_6" }, "PSS2.PSS1_IMUX_B19_7->PS7_SAXIHP0ARADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_7" }, "PSS2.PSS1_IMUX_B19_8->PS7_SAXIHP1ARADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_8" }, "PSS2.PSS1_IMUX_B19_9->PS7_SAXIHP1ARCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B19_9" }, "PSS2.PSS1_IMUX_B1_0->PS7_SAXIHP0AWADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_0" }, "PSS2.PSS1_IMUX_B1_1->PS7_SAXIHP0AWADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_1" }, "PSS2.PSS1_IMUX_B1_10->PS7_SAXIHP1AWADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_10" }, "PSS2.PSS1_IMUX_B1_11->PS7_SAXIHP1AWADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_11" }, "PSS2.PSS1_IMUX_B1_12->PS7_SAXIHP1AWADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_12" }, "PSS2.PSS1_IMUX_B1_13->PS7_SAXIHP1AWADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_13" }, "PSS2.PSS1_IMUX_B1_14->PS7_SAXIHP1AWID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_14" }, "PSS2.PSS1_IMUX_B1_15->PS7_SAXIHP1AWID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_15" }, "PSS2.PSS1_IMUX_B1_16->PS7_SAXIHP2AWADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_16" }, "PSS2.PSS1_IMUX_B1_17->PS7_SAXIHP2AWADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_17" }, "PSS2.PSS1_IMUX_B1_18->PS7_SAXIHP2AWADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_18" }, "PSS2.PSS1_IMUX_B1_19->PS7_SAXIHP2AWADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_19" }, "PSS2.PSS1_IMUX_B1_2->PS7_SAXIHP0AWADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_2" }, "PSS2.PSS1_IMUX_B1_20->PS7_SAXIHP2AWADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_20" }, "PSS2.PSS1_IMUX_B1_21->PS7_SAXIHP2AWADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_21" }, "PSS2.PSS1_IMUX_B1_22->PS7_SAXIHP2AWID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_22" }, "PSS2.PSS1_IMUX_B1_23->PS7_SAXIHP2AWID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_23" }, "PSS2.PSS1_IMUX_B1_24->PS7_SAXIHP3AWADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_24" }, "PSS2.PSS1_IMUX_B1_25->PS7_SAXIHP3AWADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_25" }, "PSS2.PSS1_IMUX_B1_26->PS7_SAXIHP3AWADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_26" }, "PSS2.PSS1_IMUX_B1_27->PS7_SAXIHP3AWADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_27" }, "PSS2.PSS1_IMUX_B1_28->PS7_SAXIHP3AWADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_28" }, "PSS2.PSS1_IMUX_B1_29->PS7_SAXIHP3AWADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_29" }, "PSS2.PSS1_IMUX_B1_3->PS7_SAXIHP0AWADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_3" }, "PSS2.PSS1_IMUX_B1_30->PS7_SAXIHP3AWID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_30" }, "PSS2.PSS1_IMUX_B1_31->PS7_SAXIHP3AWID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_31" }, "PSS2.PSS1_IMUX_B1_32->PS7_SAXIACPAWADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_32" }, "PSS2.PSS1_IMUX_B1_33->PS7_SAXIACPAWADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_33" }, "PSS2.PSS1_IMUX_B1_34->PS7_SAXIACPAWADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_34" }, "PSS2.PSS1_IMUX_B1_35->PS7_SAXIACPAWADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_35" }, "PSS2.PSS1_IMUX_B1_36->PS7_DMA0DRLAST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA0DRLAST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_36" }, "PSS2.PSS1_IMUX_B1_37->PS7_DMA1DRLAST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA1DRLAST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_37" }, "PSS2.PSS1_IMUX_B1_38->PS7_DMA2DRLAST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA2DRLAST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_38" }, "PSS2.PSS1_IMUX_B1_39->PS7_DMA3DRLAST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA3DRLAST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_39" }, "PSS2.PSS1_IMUX_B1_4->PS7_SAXIHP0AWADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_4" }, "PSS2.PSS1_IMUX_B1_5->PS7_SAXIHP0AWADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_5" }, "PSS2.PSS1_IMUX_B1_6->PS7_SAXIHP0AWID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_6" }, "PSS2.PSS1_IMUX_B1_7->PS7_SAXIHP0AWID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_7" }, "PSS2.PSS1_IMUX_B1_8->PS7_SAXIHP1AWADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_8" }, "PSS2.PSS1_IMUX_B1_9->PS7_SAXIHP1AWADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B1_9" }, "PSS2.PSS1_IMUX_B20_0->PS7_SAXIHP0ARSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_0" }, "PSS2.PSS1_IMUX_B20_1->PS7_SAXIHP0ARCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_1" }, "PSS2.PSS1_IMUX_B20_10->PS7_SAXIHP1ARADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_10" }, "PSS2.PSS1_IMUX_B20_11->PS7_SAXIHP1ARVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_11" }, "PSS2.PSS1_IMUX_B20_12->PS7_SAXIHP1WVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_12" }, "PSS2.PSS1_IMUX_B20_13->PS7_SAXIHP1WDATA55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_13" }, "PSS2.PSS1_IMUX_B20_14->PS7_SAXIHP1ARADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_14" }, "PSS2.PSS1_IMUX_B20_15->PS7_SAXIHP1ARADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_15" }, "PSS2.PSS1_IMUX_B20_16->PS7_SAXIHP2ARSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_16" }, "PSS2.PSS1_IMUX_B20_17->PS7_SAXIHP2ARCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_17" }, "PSS2.PSS1_IMUX_B20_18->PS7_SAXIHP2ARADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_18" }, "PSS2.PSS1_IMUX_B20_19->PS7_SAXIHP2ARVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_19" }, "PSS2.PSS1_IMUX_B20_2->PS7_SAXIHP0ARADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_2" }, "PSS2.PSS1_IMUX_B20_20->PS7_SAXIHP2WVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_20" }, "PSS2.PSS1_IMUX_B20_21->PS7_SAXIHP2WDATA55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_21" }, "PSS2.PSS1_IMUX_B20_22->PS7_SAXIHP2ARADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_22" }, "PSS2.PSS1_IMUX_B20_23->PS7_SAXIHP2ARADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_23" }, "PSS2.PSS1_IMUX_B20_24->PS7_SAXIHP3ARSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_24" }, "PSS2.PSS1_IMUX_B20_25->PS7_SAXIHP3ARCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_25" }, "PSS2.PSS1_IMUX_B20_26->PS7_SAXIHP3ARADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_26" }, "PSS2.PSS1_IMUX_B20_27->PS7_SAXIHP3ARVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_27" }, "PSS2.PSS1_IMUX_B20_28->PS7_SAXIHP3WVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_28" }, "PSS2.PSS1_IMUX_B20_29->PS7_SAXIHP3WDATA55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_29" }, "PSS2.PSS1_IMUX_B20_3->PS7_SAXIHP0ARVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_3" }, "PSS2.PSS1_IMUX_B20_30->PS7_SAXIHP3ARADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_30" }, "PSS2.PSS1_IMUX_B20_31->PS7_SAXIHP3ARADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_31" }, "PSS2.PSS1_IMUX_B20_32->PS7_SAXIACPARLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_32" }, "PSS2.PSS1_IMUX_B20_33->PS7_SAXIACPARCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_33" }, "PSS2.PSS1_IMUX_B20_34->PS7_SAXIACPARADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_34" }, "PSS2.PSS1_IMUX_B20_35->PS7_SAXIACPARADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_35" }, "PSS2.PSS1_IMUX_B20_36->PS7_SAXIACPWDATA50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_36" }, "PSS2.PSS1_IMUX_B20_37->PS7_SAXIACPWDATA53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_37" }, "PSS2.PSS1_IMUX_B20_38->PS7_SAXIACPWDATA58": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA58", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_38" }, "PSS2.PSS1_IMUX_B20_39->PS7_SAXIACPARADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_39" }, "PSS2.PSS1_IMUX_B20_4->PS7_SAXIHP0WVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_4" }, "PSS2.PSS1_IMUX_B20_5->PS7_SAXIHP0WDATA55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_5" }, "PSS2.PSS1_IMUX_B20_6->PS7_SAXIHP0ARADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_6" }, "PSS2.PSS1_IMUX_B20_7->PS7_SAXIHP0ARADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_7" }, "PSS2.PSS1_IMUX_B20_8->PS7_SAXIHP1ARSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_8" }, "PSS2.PSS1_IMUX_B20_9->PS7_SAXIHP1ARCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B20_9" }, "PSS2.PSS1_IMUX_B21_0->PS7_SAXIHP0ARSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_0" }, "PSS2.PSS1_IMUX_B21_1->PS7_SAXIHP0ARCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_1" }, "PSS2.PSS1_IMUX_B21_10->PS7_SAXIHP1ARLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_10" }, "PSS2.PSS1_IMUX_B21_11->PS7_SAXIHP1RREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1RREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_11" }, "PSS2.PSS1_IMUX_B21_12->PS7_SAXIHP1BREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1BREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_12" }, "PSS2.PSS1_IMUX_B21_13->PS7_SAXIHP1ARADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_13" }, "PSS2.PSS1_IMUX_B21_14->PS7_SAXIHP1ARADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_14" }, "PSS2.PSS1_IMUX_B21_15->PS7_SAXIHP1ARADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_15" }, "PSS2.PSS1_IMUX_B21_16->PS7_SAXIHP2ARSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_16" }, "PSS2.PSS1_IMUX_B21_17->PS7_SAXIHP2ARCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_17" }, "PSS2.PSS1_IMUX_B21_18->PS7_SAXIHP2ARLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_18" }, "PSS2.PSS1_IMUX_B21_19->PS7_SAXIHP2RREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2RREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_19" }, "PSS2.PSS1_IMUX_B21_2->PS7_SAXIHP0ARLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_2" }, "PSS2.PSS1_IMUX_B21_20->PS7_SAXIHP2BREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2BREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_20" }, "PSS2.PSS1_IMUX_B21_21->PS7_SAXIHP2ARADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_21" }, "PSS2.PSS1_IMUX_B21_22->PS7_SAXIHP2ARADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_22" }, "PSS2.PSS1_IMUX_B21_23->PS7_SAXIHP2ARADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_23" }, "PSS2.PSS1_IMUX_B21_24->PS7_SAXIHP3ARSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_24" }, "PSS2.PSS1_IMUX_B21_25->PS7_SAXIHP3ARCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_25" }, "PSS2.PSS1_IMUX_B21_26->PS7_SAXIHP3ARLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_26" }, "PSS2.PSS1_IMUX_B21_27->PS7_SAXIHP3RREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3RREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_27" }, "PSS2.PSS1_IMUX_B21_28->PS7_SAXIHP3BREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3BREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_28" }, "PSS2.PSS1_IMUX_B21_29->PS7_SAXIHP3ARADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_29" }, "PSS2.PSS1_IMUX_B21_3->PS7_SAXIHP0RREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0RREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_3" }, "PSS2.PSS1_IMUX_B21_30->PS7_SAXIHP3ARADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_30" }, "PSS2.PSS1_IMUX_B21_31->PS7_SAXIHP3ARADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_31" }, "PSS2.PSS1_IMUX_B21_32->PS7_SAXIACPARLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_32" }, "PSS2.PSS1_IMUX_B21_33->PS7_SAXIACPARCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_33" }, "PSS2.PSS1_IMUX_B21_34->PS7_SAXIACPARADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_34" }, "PSS2.PSS1_IMUX_B21_35->PS7_SAXIACPARADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_35" }, "PSS2.PSS1_IMUX_B21_36->PS7_SAXIACPWDATA51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_36" }, "PSS2.PSS1_IMUX_B21_37->PS7_SAXIACPWDATA54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_37" }, "PSS2.PSS1_IMUX_B21_38->PS7_SAXIACPWDATA59": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA59", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_38" }, "PSS2.PSS1_IMUX_B21_39->PS7_SAXIACPAWQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_39" }, "PSS2.PSS1_IMUX_B21_4->PS7_SAXIHP0BREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0BREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_4" }, "PSS2.PSS1_IMUX_B21_5->PS7_SAXIHP0ARADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_5" }, "PSS2.PSS1_IMUX_B21_6->PS7_SAXIHP0ARADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_6" }, "PSS2.PSS1_IMUX_B21_7->PS7_SAXIHP0ARADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_7" }, "PSS2.PSS1_IMUX_B21_8->PS7_SAXIHP1ARSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_8" }, "PSS2.PSS1_IMUX_B21_9->PS7_SAXIHP1ARCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B21_9" }, "PSS2.PSS1_IMUX_B22_0->PS7_SAXIHP0ARBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_0" }, "PSS2.PSS1_IMUX_B22_1->PS7_SAXIHP0ARCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_1" }, "PSS2.PSS1_IMUX_B22_10->PS7_SAXIHP1ARLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_10" }, "PSS2.PSS1_IMUX_B22_11->PS7_SAXIHP1ARQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_11" }, "PSS2.PSS1_IMUX_B22_12->PS7_SAXIHP1ARADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_12" }, "PSS2.PSS1_IMUX_B22_13->PS7_SAXIHP1ARADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_13" }, "PSS2.PSS1_IMUX_B22_14->PS7_SAXIHP1ARADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_14" }, "PSS2.PSS1_IMUX_B22_15->PS7_SAXIHP1WRISSUECAP1EN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WRISSUECAP1EN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_15" }, "PSS2.PSS1_IMUX_B22_16->PS7_SAXIHP2ARBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_16" }, "PSS2.PSS1_IMUX_B22_17->PS7_SAXIHP2ARCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_17" }, "PSS2.PSS1_IMUX_B22_18->PS7_SAXIHP2ARLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_18" }, "PSS2.PSS1_IMUX_B22_19->PS7_SAXIHP2ARQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_19" }, "PSS2.PSS1_IMUX_B22_2->PS7_SAXIHP0ARLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_2" }, "PSS2.PSS1_IMUX_B22_20->PS7_SAXIHP2ARADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_20" }, "PSS2.PSS1_IMUX_B22_21->PS7_SAXIHP2ARADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_21" }, "PSS2.PSS1_IMUX_B22_22->PS7_SAXIHP2ARADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_22" }, "PSS2.PSS1_IMUX_B22_23->PS7_SAXIHP2WRISSUECAP1EN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WRISSUECAP1EN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_23" }, "PSS2.PSS1_IMUX_B22_24->PS7_SAXIHP3ARBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_24" }, "PSS2.PSS1_IMUX_B22_25->PS7_SAXIHP3ARCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_25" }, "PSS2.PSS1_IMUX_B22_26->PS7_SAXIHP3ARLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_26" }, "PSS2.PSS1_IMUX_B22_27->PS7_SAXIHP3ARQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_27" }, "PSS2.PSS1_IMUX_B22_28->PS7_SAXIHP3ARADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_28" }, "PSS2.PSS1_IMUX_B22_29->PS7_SAXIHP3ARADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_29" }, "PSS2.PSS1_IMUX_B22_3->PS7_SAXIHP0ARQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_3" }, "PSS2.PSS1_IMUX_B22_30->PS7_SAXIHP3ARADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_30" }, "PSS2.PSS1_IMUX_B22_31->PS7_SAXIHP3WRISSUECAP1EN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WRISSUECAP1EN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_31" }, "PSS2.PSS1_IMUX_B22_32->PS7_SAXIACPARUSER0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARUSER0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_32" }, "PSS2.PSS1_IMUX_B22_33->PS7_SAXIACPARCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_33" }, "PSS2.PSS1_IMUX_B22_34->PS7_SAXIACPARQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_34" }, "PSS2.PSS1_IMUX_B22_35->PS7_SAXIACPARADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_35" }, "PSS2.PSS1_IMUX_B22_36->PS7_SAXIACPBREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPBREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_36" }, "PSS2.PSS1_IMUX_B22_37->PS7_SAXIACPWDATA55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_37" }, "PSS2.PSS1_IMUX_B22_38->PS7_SAXIACPARADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_38" }, "PSS2.PSS1_IMUX_B22_39->PS7_SAXIACPAWQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_39" }, "PSS2.PSS1_IMUX_B22_4->PS7_SAXIHP0ARADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_4" }, "PSS2.PSS1_IMUX_B22_5->PS7_SAXIHP0ARADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_5" }, "PSS2.PSS1_IMUX_B22_6->PS7_SAXIHP0ARADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_6" }, "PSS2.PSS1_IMUX_B22_7->PS7_SAXIHP0WRISSUECAP1EN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WRISSUECAP1EN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_7" }, "PSS2.PSS1_IMUX_B22_8->PS7_SAXIHP1ARBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_8" }, "PSS2.PSS1_IMUX_B22_9->PS7_SAXIHP1ARCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B22_9" }, "PSS2.PSS1_IMUX_B23_0->PS7_SAXIHP0ARBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_0" }, "PSS2.PSS1_IMUX_B23_1->PS7_SAXIHP0ARPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_1" }, "PSS2.PSS1_IMUX_B23_10->PS7_SAXIHP1ARLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_10" }, "PSS2.PSS1_IMUX_B23_11->PS7_SAXIHP1ARQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_11" }, "PSS2.PSS1_IMUX_B23_12->PS7_SAXIHP1ARADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_12" }, "PSS2.PSS1_IMUX_B23_13->PS7_SAXIHP1ARADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_13" }, "PSS2.PSS1_IMUX_B23_14->PS7_SAXIHP1AWQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_14" }, "PSS2.PSS1_IMUX_B23_15->PS7_SAXIHP1AWQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_15" }, "PSS2.PSS1_IMUX_B23_16->PS7_SAXIHP2ARBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_16" }, "PSS2.PSS1_IMUX_B23_17->PS7_SAXIHP2ARPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_17" }, "PSS2.PSS1_IMUX_B23_18->PS7_SAXIHP2ARLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_18" }, "PSS2.PSS1_IMUX_B23_19->PS7_SAXIHP2ARQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_19" }, "PSS2.PSS1_IMUX_B23_2->PS7_SAXIHP0ARLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_2" }, "PSS2.PSS1_IMUX_B23_20->PS7_SAXIHP2ARADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_20" }, "PSS2.PSS1_IMUX_B23_21->PS7_SAXIHP2ARADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_21" }, "PSS2.PSS1_IMUX_B23_22->PS7_SAXIHP2AWQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_22" }, "PSS2.PSS1_IMUX_B23_23->PS7_SAXIHP2AWQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_23" }, "PSS2.PSS1_IMUX_B23_24->PS7_SAXIHP3ARBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_24" }, "PSS2.PSS1_IMUX_B23_25->PS7_SAXIHP3ARPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_25" }, "PSS2.PSS1_IMUX_B23_26->PS7_SAXIHP3ARLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_26" }, "PSS2.PSS1_IMUX_B23_27->PS7_SAXIHP3ARQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_27" }, "PSS2.PSS1_IMUX_B23_28->PS7_SAXIHP3ARADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_28" }, "PSS2.PSS1_IMUX_B23_29->PS7_SAXIHP3ARADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_29" }, "PSS2.PSS1_IMUX_B23_3->PS7_SAXIHP0ARQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_3" }, "PSS2.PSS1_IMUX_B23_30->PS7_SAXIHP3AWQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_30" }, "PSS2.PSS1_IMUX_B23_31->PS7_SAXIHP3AWQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_31" }, "PSS2.PSS1_IMUX_B23_32->PS7_SAXIACPARUSER1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARUSER1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_32" }, "PSS2.PSS1_IMUX_B23_33->PS7_SAXIACPARCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_33" }, "PSS2.PSS1_IMUX_B23_34->PS7_SAXIACPARQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_34" }, "PSS2.PSS1_IMUX_B23_35->PS7_SAXIACPARADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_35" }, "PSS2.PSS1_IMUX_B23_36->PS7_SAXIACPARADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_36" }, "PSS2.PSS1_IMUX_B23_37->PS7_SAXIACPARADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_37" }, "PSS2.PSS1_IMUX_B23_38->PS7_SAXIACPARADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_38" }, "PSS2.PSS1_IMUX_B23_39->PS7_SAXIACPAWQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_39" }, "PSS2.PSS1_IMUX_B23_4->PS7_SAXIHP0ARADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_4" }, "PSS2.PSS1_IMUX_B23_5->PS7_SAXIHP0ARADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_5" }, "PSS2.PSS1_IMUX_B23_6->PS7_SAXIHP0AWQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_6" }, "PSS2.PSS1_IMUX_B23_7->PS7_SAXIHP0AWQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_7" }, "PSS2.PSS1_IMUX_B23_8->PS7_SAXIHP1ARBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_8" }, "PSS2.PSS1_IMUX_B23_9->PS7_SAXIHP1ARPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B23_9" }, "PSS2.PSS1_IMUX_B24_0->PS7_SAXIHP0ARLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_0" }, "PSS2.PSS1_IMUX_B24_1->PS7_SAXIHP0ARPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_1" }, "PSS2.PSS1_IMUX_B24_10->PS7_SAXIHP1ARLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_10" }, "PSS2.PSS1_IMUX_B24_11->PS7_SAXIHP1ARQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_11" }, "PSS2.PSS1_IMUX_B24_12->PS7_SAXIHP1ARADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_12" }, "PSS2.PSS1_IMUX_B24_13->PS7_SAXIHP1ARADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_13" }, "PSS2.PSS1_IMUX_B24_14->PS7_SAXIHP1AWQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_14" }, "PSS2.PSS1_IMUX_B24_15->PS7_SAXIHP1AWQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_15" }, "PSS2.PSS1_IMUX_B24_16->PS7_SAXIHP2ARLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_16" }, "PSS2.PSS1_IMUX_B24_17->PS7_SAXIHP2ARPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_17" }, "PSS2.PSS1_IMUX_B24_18->PS7_SAXIHP2ARLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_18" }, "PSS2.PSS1_IMUX_B24_19->PS7_SAXIHP2ARQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_19" }, "PSS2.PSS1_IMUX_B24_2->PS7_SAXIHP0ARLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_2" }, "PSS2.PSS1_IMUX_B24_20->PS7_SAXIHP2ARADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_20" }, "PSS2.PSS1_IMUX_B24_21->PS7_SAXIHP2ARADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_21" }, "PSS2.PSS1_IMUX_B24_22->PS7_SAXIHP2AWQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_22" }, "PSS2.PSS1_IMUX_B24_23->PS7_SAXIHP2AWQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_23" }, "PSS2.PSS1_IMUX_B24_24->PS7_SAXIHP3ARLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_24" }, "PSS2.PSS1_IMUX_B24_25->PS7_SAXIHP3ARPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_25" }, "PSS2.PSS1_IMUX_B24_26->PS7_SAXIHP3ARLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_26" }, "PSS2.PSS1_IMUX_B24_27->PS7_SAXIHP3ARQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_27" }, "PSS2.PSS1_IMUX_B24_28->PS7_SAXIHP3ARADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_28" }, "PSS2.PSS1_IMUX_B24_29->PS7_SAXIHP3ARADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_29" }, "PSS2.PSS1_IMUX_B24_3->PS7_SAXIHP0ARQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_3" }, "PSS2.PSS1_IMUX_B24_30->PS7_SAXIHP3AWQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_30" }, "PSS2.PSS1_IMUX_B24_31->PS7_SAXIHP3AWQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_31" }, "PSS2.PSS1_IMUX_B24_32->PS7_SAXIACPARUSER2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARUSER2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_32" }, "PSS2.PSS1_IMUX_B24_33->PS7_SAXIACPARPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_33" }, "PSS2.PSS1_IMUX_B24_34->PS7_SAXIACPARQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_34" }, "PSS2.PSS1_IMUX_B24_35->PS7_SAXIACPARPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_35" }, "PSS2.PSS1_IMUX_B24_36->PS7_SAXIACPARADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_36" }, "PSS2.PSS1_IMUX_B24_37->PS7_SAXIACPARADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_37" }, "PSS2.PSS1_IMUX_B24_38->PS7_SAXIACPARADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_38" }, "PSS2.PSS1_IMUX_B24_39->PS7_SAXIACPAWQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_39" }, "PSS2.PSS1_IMUX_B24_4->PS7_SAXIHP0ARADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_4" }, "PSS2.PSS1_IMUX_B24_5->PS7_SAXIHP0ARADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_5" }, "PSS2.PSS1_IMUX_B24_6->PS7_SAXIHP0AWQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_6" }, "PSS2.PSS1_IMUX_B24_7->PS7_SAXIHP0AWQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_7" }, "PSS2.PSS1_IMUX_B24_8->PS7_SAXIHP1ARLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_8" }, "PSS2.PSS1_IMUX_B24_9->PS7_SAXIHP1ARPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B24_9" }, "PSS2.PSS1_IMUX_B25_0->PS7_SAXIHP0RDISSUECAP1EN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0RDISSUECAP1EN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_0" }, "PSS2.PSS1_IMUX_B25_10->PS7_SAXIHP1ARPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_10" }, "PSS2.PSS1_IMUX_B25_11->PS7_SAXIHP1ARQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_11" }, "PSS2.PSS1_IMUX_B25_12->PS7_SAXIHP1ARADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1ARADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_12" }, "PSS2.PSS1_IMUX_B25_16->PS7_SAXIHP2RDISSUECAP1EN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2RDISSUECAP1EN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_16" }, "PSS2.PSS1_IMUX_B25_18->PS7_SAXIHP2ARPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_18" }, "PSS2.PSS1_IMUX_B25_19->PS7_SAXIHP2ARQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_19" }, "PSS2.PSS1_IMUX_B25_2->PS7_SAXIHP0ARPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_2" }, "PSS2.PSS1_IMUX_B25_20->PS7_SAXIHP2ARADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2ARADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_20" }, "PSS2.PSS1_IMUX_B25_24->PS7_SAXIHP3RDISSUECAP1EN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3RDISSUECAP1EN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_24" }, "PSS2.PSS1_IMUX_B25_26->PS7_SAXIHP3ARPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_26" }, "PSS2.PSS1_IMUX_B25_27->PS7_SAXIHP3ARQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_27" }, "PSS2.PSS1_IMUX_B25_28->PS7_SAXIHP3ARADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3ARADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_28" }, "PSS2.PSS1_IMUX_B25_3->PS7_SAXIHP0ARQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_3" }, "PSS2.PSS1_IMUX_B25_32->PS7_SAXIACPARUSER3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARUSER3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_32" }, "PSS2.PSS1_IMUX_B25_33->PS7_SAXIACPARPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_33" }, "PSS2.PSS1_IMUX_B25_34->PS7_SAXIACPARQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_34" }, "PSS2.PSS1_IMUX_B25_35->PS7_SAXIACPARVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_35" }, "PSS2.PSS1_IMUX_B25_36->PS7_SAXIACPARADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_36" }, "PSS2.PSS1_IMUX_B25_37->PS7_SAXIACPARADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_37" }, "PSS2.PSS1_IMUX_B25_38->PS7_SAXIACPARADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_38" }, "PSS2.PSS1_IMUX_B25_4->PS7_SAXIHP0ARADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0ARADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_4" }, "PSS2.PSS1_IMUX_B25_8->PS7_SAXIHP1RDISSUECAP1EN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1RDISSUECAP1EN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B25_8" }, "PSS2.PSS1_IMUX_B26_33->PS7_SAXIACPARUSER4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARUSER4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B26_33" }, "PSS2.PSS1_IMUX_B26_35->PS7_SAXIACPRREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPRREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B26_35" }, "PSS2.PSS1_IMUX_B26_36->PS7_SAXIACPARADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B26_36" }, "PSS2.PSS1_IMUX_B26_37->PS7_SAXIACPARADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPARADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B26_37" }, "PSS2.PSS1_IMUX_B2_0->PS7_SAXIHP0AWADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_0" }, "PSS2.PSS1_IMUX_B2_1->PS7_SAXIHP0AWADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_1" }, "PSS2.PSS1_IMUX_B2_10->PS7_SAXIHP1AWADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_10" }, "PSS2.PSS1_IMUX_B2_11->PS7_SAXIHP1AWADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_11" }, "PSS2.PSS1_IMUX_B2_12->PS7_SAXIHP1AWADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_12" }, "PSS2.PSS1_IMUX_B2_13->PS7_SAXIHP1AWADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_13" }, "PSS2.PSS1_IMUX_B2_14->PS7_SAXIHP1AWID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_14" }, "PSS2.PSS1_IMUX_B2_15->PS7_SAXIHP1AWADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_15" }, "PSS2.PSS1_IMUX_B2_16->PS7_SAXIHP2AWADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_16" }, "PSS2.PSS1_IMUX_B2_17->PS7_SAXIHP2AWADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_17" }, "PSS2.PSS1_IMUX_B2_18->PS7_SAXIHP2AWADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_18" }, "PSS2.PSS1_IMUX_B2_19->PS7_SAXIHP2AWADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_19" }, "PSS2.PSS1_IMUX_B2_2->PS7_SAXIHP0AWADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_2" }, "PSS2.PSS1_IMUX_B2_20->PS7_SAXIHP2AWADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_20" }, "PSS2.PSS1_IMUX_B2_21->PS7_SAXIHP2AWADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_21" }, "PSS2.PSS1_IMUX_B2_22->PS7_SAXIHP2AWID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_22" }, "PSS2.PSS1_IMUX_B2_23->PS7_SAXIHP2AWADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_23" }, "PSS2.PSS1_IMUX_B2_24->PS7_SAXIHP3AWADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_24" }, "PSS2.PSS1_IMUX_B2_25->PS7_SAXIHP3AWADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_25" }, "PSS2.PSS1_IMUX_B2_26->PS7_SAXIHP3AWADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_26" }, "PSS2.PSS1_IMUX_B2_27->PS7_SAXIHP3AWADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_27" }, "PSS2.PSS1_IMUX_B2_28->PS7_SAXIHP3AWADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_28" }, "PSS2.PSS1_IMUX_B2_29->PS7_SAXIHP3AWADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_29" }, "PSS2.PSS1_IMUX_B2_3->PS7_SAXIHP0AWADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_3" }, "PSS2.PSS1_IMUX_B2_30->PS7_SAXIHP3AWID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_30" }, "PSS2.PSS1_IMUX_B2_31->PS7_SAXIHP3AWADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_31" }, "PSS2.PSS1_IMUX_B2_32->PS7_SAXIACPAWADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_32" }, "PSS2.PSS1_IMUX_B2_33->PS7_SAXIACPAWADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_33" }, "PSS2.PSS1_IMUX_B2_34->PS7_SAXIACPAWADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_34" }, "PSS2.PSS1_IMUX_B2_35->PS7_SAXIACPAWADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_35" }, "PSS2.PSS1_IMUX_B2_36->PS7_SAXIACPAWADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_36" }, "PSS2.PSS1_IMUX_B2_37->PS7_SAXIACPAWADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_37" }, "PSS2.PSS1_IMUX_B2_38->PS7_SAXIACPAWADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_38" }, "PSS2.PSS1_IMUX_B2_39->PS7_SAXIACPAWID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_39" }, "PSS2.PSS1_IMUX_B2_4->PS7_SAXIHP0AWADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_4" }, "PSS2.PSS1_IMUX_B2_5->PS7_SAXIHP0AWADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_5" }, "PSS2.PSS1_IMUX_B2_6->PS7_SAXIHP0AWID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_6" }, "PSS2.PSS1_IMUX_B2_7->PS7_SAXIHP0AWADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_7" }, "PSS2.PSS1_IMUX_B2_8->PS7_SAXIHP1AWADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_8" }, "PSS2.PSS1_IMUX_B2_9->PS7_SAXIHP1AWADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B2_9" }, "PSS2.PSS1_IMUX_B3_0->PS7_SAXIHP0AWADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_0" }, "PSS2.PSS1_IMUX_B3_1->PS7_SAXIHP0AWADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_1" }, "PSS2.PSS1_IMUX_B3_10->PS7_SAXIHP1AWADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_10" }, "PSS2.PSS1_IMUX_B3_11->PS7_SAXIHP1AWADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_11" }, "PSS2.PSS1_IMUX_B3_12->PS7_SAXIHP1AWADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_12" }, "PSS2.PSS1_IMUX_B3_13->PS7_SAXIHP1AWADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_13" }, "PSS2.PSS1_IMUX_B3_14->PS7_SAXIHP1AWID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_14" }, "PSS2.PSS1_IMUX_B3_15->PS7_SAXIHP1AWADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_15" }, "PSS2.PSS1_IMUX_B3_16->PS7_SAXIHP2AWADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_16" }, "PSS2.PSS1_IMUX_B3_17->PS7_SAXIHP2AWADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_17" }, "PSS2.PSS1_IMUX_B3_18->PS7_SAXIHP2AWADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_18" }, "PSS2.PSS1_IMUX_B3_19->PS7_SAXIHP2AWADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_19" }, "PSS2.PSS1_IMUX_B3_2->PS7_SAXIHP0AWADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_2" }, "PSS2.PSS1_IMUX_B3_20->PS7_SAXIHP2AWADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_20" }, "PSS2.PSS1_IMUX_B3_21->PS7_SAXIHP2AWADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_21" }, "PSS2.PSS1_IMUX_B3_22->PS7_SAXIHP2AWID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_22" }, "PSS2.PSS1_IMUX_B3_23->PS7_SAXIHP2AWADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_23" }, "PSS2.PSS1_IMUX_B3_24->PS7_SAXIHP3AWADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_24" }, "PSS2.PSS1_IMUX_B3_25->PS7_SAXIHP3AWADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_25" }, "PSS2.PSS1_IMUX_B3_26->PS7_SAXIHP3AWADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_26" }, "PSS2.PSS1_IMUX_B3_27->PS7_SAXIHP3AWADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_27" }, "PSS2.PSS1_IMUX_B3_28->PS7_SAXIHP3AWADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_28" }, "PSS2.PSS1_IMUX_B3_29->PS7_SAXIHP3AWADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_29" }, "PSS2.PSS1_IMUX_B3_3->PS7_SAXIHP0AWADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_3" }, "PSS2.PSS1_IMUX_B3_30->PS7_SAXIHP3AWID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_30" }, "PSS2.PSS1_IMUX_B3_31->PS7_SAXIHP3AWADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_31" }, "PSS2.PSS1_IMUX_B3_32->PS7_SAXIACPAWADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_32" }, "PSS2.PSS1_IMUX_B3_33->PS7_SAXIACPAWADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_33" }, "PSS2.PSS1_IMUX_B3_34->PS7_SAXIACPAWADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_34" }, "PSS2.PSS1_IMUX_B3_35->PS7_SAXIACPAWADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_35" }, "PSS2.PSS1_IMUX_B3_36->PS7_SAXIACPAWADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_36" }, "PSS2.PSS1_IMUX_B3_37->PS7_SAXIACPAWADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_37" }, "PSS2.PSS1_IMUX_B3_38->PS7_SAXIACPAWADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_38" }, "PSS2.PSS1_IMUX_B3_39->PS7_SAXIACPAWID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_39" }, "PSS2.PSS1_IMUX_B3_4->PS7_SAXIHP0AWADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_4" }, "PSS2.PSS1_IMUX_B3_5->PS7_SAXIHP0AWADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_5" }, "PSS2.PSS1_IMUX_B3_6->PS7_SAXIHP0AWID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_6" }, "PSS2.PSS1_IMUX_B3_7->PS7_SAXIHP0AWADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_7" }, "PSS2.PSS1_IMUX_B3_8->PS7_SAXIHP1AWADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_8" }, "PSS2.PSS1_IMUX_B3_9->PS7_SAXIHP1AWADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B3_9" }, "PSS2.PSS1_IMUX_B4_0->PS7_SAXIHP0WDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_0" }, "PSS2.PSS1_IMUX_B4_1->PS7_SAXIHP0WDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_1" }, "PSS2.PSS1_IMUX_B4_10->PS7_SAXIHP1WDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_10" }, "PSS2.PSS1_IMUX_B4_11->PS7_SAXIHP1WDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_11" }, "PSS2.PSS1_IMUX_B4_12->PS7_SAXIHP1AWCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_12" }, "PSS2.PSS1_IMUX_B4_13->PS7_SAXIHP1AWBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_13" }, "PSS2.PSS1_IMUX_B4_14->PS7_SAXIHP1AWADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_14" }, "PSS2.PSS1_IMUX_B4_15->PS7_SAXIHP1AWADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_15" }, "PSS2.PSS1_IMUX_B4_16->PS7_SAXIHP2WDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_16" }, "PSS2.PSS1_IMUX_B4_17->PS7_SAXIHP2WDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_17" }, "PSS2.PSS1_IMUX_B4_18->PS7_SAXIHP2WDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_18" }, "PSS2.PSS1_IMUX_B4_19->PS7_SAXIHP2WDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_19" }, "PSS2.PSS1_IMUX_B4_2->PS7_SAXIHP0WDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_2" }, "PSS2.PSS1_IMUX_B4_20->PS7_SAXIHP2AWCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_20" }, "PSS2.PSS1_IMUX_B4_21->PS7_SAXIHP2AWBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_21" }, "PSS2.PSS1_IMUX_B4_22->PS7_SAXIHP2AWADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_22" }, "PSS2.PSS1_IMUX_B4_23->PS7_SAXIHP2AWADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_23" }, "PSS2.PSS1_IMUX_B4_24->PS7_SAXIHP3WDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_24" }, "PSS2.PSS1_IMUX_B4_25->PS7_SAXIHP3WDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_25" }, "PSS2.PSS1_IMUX_B4_26->PS7_SAXIHP3WDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_26" }, "PSS2.PSS1_IMUX_B4_27->PS7_SAXIHP3WDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_27" }, "PSS2.PSS1_IMUX_B4_28->PS7_SAXIHP3AWCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_28" }, "PSS2.PSS1_IMUX_B4_29->PS7_SAXIHP3AWBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_29" }, "PSS2.PSS1_IMUX_B4_3->PS7_SAXIHP0WDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_3" }, "PSS2.PSS1_IMUX_B4_30->PS7_SAXIHP3AWADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_30" }, "PSS2.PSS1_IMUX_B4_31->PS7_SAXIHP3AWADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_31" }, "PSS2.PSS1_IMUX_B4_32->PS7_SAXIACPWDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_32" }, "PSS2.PSS1_IMUX_B4_33->PS7_SAXIACPWDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_33" }, "PSS2.PSS1_IMUX_B4_34->PS7_SAXIACPWDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_34" }, "PSS2.PSS1_IMUX_B4_35->PS7_SAXIACPAWUSER0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWUSER0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_35" }, "PSS2.PSS1_IMUX_B4_36->PS7_SAXIACPAWADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_36" }, "PSS2.PSS1_IMUX_B4_37->PS7_SAXIACPAWADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_37" }, "PSS2.PSS1_IMUX_B4_38->PS7_SAXIACPAWADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_38" }, "PSS2.PSS1_IMUX_B4_39->PS7_SAXIACPAWID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_39" }, "PSS2.PSS1_IMUX_B4_4->PS7_SAXIHP0AWCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_4" }, "PSS2.PSS1_IMUX_B4_5->PS7_SAXIHP0AWBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_5" }, "PSS2.PSS1_IMUX_B4_6->PS7_SAXIHP0AWADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_6" }, "PSS2.PSS1_IMUX_B4_7->PS7_SAXIHP0AWADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_7" }, "PSS2.PSS1_IMUX_B4_8->PS7_SAXIHP1WDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_8" }, "PSS2.PSS1_IMUX_B4_9->PS7_SAXIHP1WDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B4_9" }, "PSS2.PSS1_IMUX_B5_0->PS7_SAXIHP0WDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_0" }, "PSS2.PSS1_IMUX_B5_1->PS7_SAXIHP0WDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_1" }, "PSS2.PSS1_IMUX_B5_10->PS7_SAXIHP1WDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_10" }, "PSS2.PSS1_IMUX_B5_11->PS7_SAXIHP1WDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_11" }, "PSS2.PSS1_IMUX_B5_12->PS7_SAXIHP1AWCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_12" }, "PSS2.PSS1_IMUX_B5_13->PS7_SAXIHP1AWLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_13" }, "PSS2.PSS1_IMUX_B5_14->PS7_SAXIHP1AWADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_14" }, "PSS2.PSS1_IMUX_B5_15->PS7_SAXIHP1AWADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_15" }, "PSS2.PSS1_IMUX_B5_16->PS7_SAXIHP2WDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_16" }, "PSS2.PSS1_IMUX_B5_17->PS7_SAXIHP2WDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_17" }, "PSS2.PSS1_IMUX_B5_18->PS7_SAXIHP2WDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_18" }, "PSS2.PSS1_IMUX_B5_19->PS7_SAXIHP2WDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_19" }, "PSS2.PSS1_IMUX_B5_2->PS7_SAXIHP0WDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_2" }, "PSS2.PSS1_IMUX_B5_20->PS7_SAXIHP2AWCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_20" }, "PSS2.PSS1_IMUX_B5_21->PS7_SAXIHP2AWLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_21" }, "PSS2.PSS1_IMUX_B5_22->PS7_SAXIHP2AWADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_22" }, "PSS2.PSS1_IMUX_B5_23->PS7_SAXIHP2AWADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_23" }, "PSS2.PSS1_IMUX_B5_24->PS7_SAXIHP3WDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_24" }, "PSS2.PSS1_IMUX_B5_25->PS7_SAXIHP3WDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_25" }, "PSS2.PSS1_IMUX_B5_26->PS7_SAXIHP3WDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_26" }, "PSS2.PSS1_IMUX_B5_27->PS7_SAXIHP3WDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_27" }, "PSS2.PSS1_IMUX_B5_28->PS7_SAXIHP3AWCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_28" }, "PSS2.PSS1_IMUX_B5_29->PS7_SAXIHP3AWLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_29" }, "PSS2.PSS1_IMUX_B5_3->PS7_SAXIHP0WDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_3" }, "PSS2.PSS1_IMUX_B5_30->PS7_SAXIHP3AWADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_30" }, "PSS2.PSS1_IMUX_B5_31->PS7_SAXIHP3AWADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_31" }, "PSS2.PSS1_IMUX_B5_32->PS7_SAXIACPWDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_32" }, "PSS2.PSS1_IMUX_B5_33->PS7_SAXIACPWDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_33" }, "PSS2.PSS1_IMUX_B5_34->PS7_SAXIACPWDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_34" }, "PSS2.PSS1_IMUX_B5_35->PS7_SAXIACPWDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_35" }, "PSS2.PSS1_IMUX_B5_36->PS7_SAXIACPAWADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_36" }, "PSS2.PSS1_IMUX_B5_37->PS7_SAXIACPAWADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_37" }, "PSS2.PSS1_IMUX_B5_38->PS7_SAXIACPAWADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_38" }, "PSS2.PSS1_IMUX_B5_39->PS7_SAXIACPAWADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_39" }, "PSS2.PSS1_IMUX_B5_4->PS7_SAXIHP0AWCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_4" }, "PSS2.PSS1_IMUX_B5_5->PS7_SAXIHP0AWLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_5" }, "PSS2.PSS1_IMUX_B5_6->PS7_SAXIHP0AWADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_6" }, "PSS2.PSS1_IMUX_B5_7->PS7_SAXIHP0AWADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_7" }, "PSS2.PSS1_IMUX_B5_8->PS7_SAXIHP1WDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_8" }, "PSS2.PSS1_IMUX_B5_9->PS7_SAXIHP1WDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B5_9" }, "PSS2.PSS1_IMUX_B6_0->PS7_SAXIHP0WDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_0" }, "PSS2.PSS1_IMUX_B6_1->PS7_SAXIHP0WDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_1" }, "PSS2.PSS1_IMUX_B6_10->PS7_SAXIHP1WDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_10" }, "PSS2.PSS1_IMUX_B6_11->PS7_SAXIHP1WDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_11" }, "PSS2.PSS1_IMUX_B6_12->PS7_SAXIHP1AWPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_12" }, "PSS2.PSS1_IMUX_B6_13->PS7_SAXIHP1AWLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_13" }, "PSS2.PSS1_IMUX_B6_14->PS7_SAXIHP1AWADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_14" }, "PSS2.PSS1_IMUX_B6_15->PS7_SAXIHP1AWLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_15" }, "PSS2.PSS1_IMUX_B6_16->PS7_SAXIHP2WDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_16" }, "PSS2.PSS1_IMUX_B6_17->PS7_SAXIHP2WDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_17" }, "PSS2.PSS1_IMUX_B6_18->PS7_SAXIHP2WDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_18" }, "PSS2.PSS1_IMUX_B6_19->PS7_SAXIHP2WDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_19" }, "PSS2.PSS1_IMUX_B6_2->PS7_SAXIHP0WDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_2" }, "PSS2.PSS1_IMUX_B6_20->PS7_SAXIHP2AWPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_20" }, "PSS2.PSS1_IMUX_B6_21->PS7_SAXIHP2AWLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_21" }, "PSS2.PSS1_IMUX_B6_22->PS7_SAXIHP2AWADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_22" }, "PSS2.PSS1_IMUX_B6_23->PS7_SAXIHP2AWLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_23" }, "PSS2.PSS1_IMUX_B6_24->PS7_SAXIHP3WDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_24" }, "PSS2.PSS1_IMUX_B6_25->PS7_SAXIHP3WDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_25" }, "PSS2.PSS1_IMUX_B6_26->PS7_SAXIHP3WDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_26" }, "PSS2.PSS1_IMUX_B6_27->PS7_SAXIHP3WDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_27" }, "PSS2.PSS1_IMUX_B6_28->PS7_SAXIHP3AWPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_28" }, "PSS2.PSS1_IMUX_B6_29->PS7_SAXIHP3AWLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_29" }, "PSS2.PSS1_IMUX_B6_3->PS7_SAXIHP0WDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_3" }, "PSS2.PSS1_IMUX_B6_30->PS7_SAXIHP3AWADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_30" }, "PSS2.PSS1_IMUX_B6_31->PS7_SAXIHP3AWLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_31" }, "PSS2.PSS1_IMUX_B6_32->PS7_SAXIACPWDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_32" }, "PSS2.PSS1_IMUX_B6_33->PS7_SAXIACPWDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_33" }, "PSS2.PSS1_IMUX_B6_34->PS7_SAXIACPWDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_34" }, "PSS2.PSS1_IMUX_B6_35->PS7_SAXIACPWDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_35" }, "PSS2.PSS1_IMUX_B6_36->PS7_SAXIACPAWVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_36" }, "PSS2.PSS1_IMUX_B6_37->PS7_SAXIACPAWLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_37" }, "PSS2.PSS1_IMUX_B6_38->PS7_SAXIACPAWLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_38" }, "PSS2.PSS1_IMUX_B6_39->PS7_SAXIACPAWADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_39" }, "PSS2.PSS1_IMUX_B6_4->PS7_SAXIHP0AWPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_4" }, "PSS2.PSS1_IMUX_B6_5->PS7_SAXIHP0AWLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_5" }, "PSS2.PSS1_IMUX_B6_6->PS7_SAXIHP0AWADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_6" }, "PSS2.PSS1_IMUX_B6_7->PS7_SAXIHP0AWLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_7" }, "PSS2.PSS1_IMUX_B6_8->PS7_SAXIHP1WDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_8" }, "PSS2.PSS1_IMUX_B6_9->PS7_SAXIHP1WDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B6_9" }, "PSS2.PSS1_IMUX_B7_0->PS7_SAXIHP0WDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_0" }, "PSS2.PSS1_IMUX_B7_1->PS7_SAXIHP0WDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_1" }, "PSS2.PSS1_IMUX_B7_10->PS7_SAXIHP1WDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_10" }, "PSS2.PSS1_IMUX_B7_11->PS7_SAXIHP1WDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_11" }, "PSS2.PSS1_IMUX_B7_12->PS7_SAXIHP1AWPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_12" }, "PSS2.PSS1_IMUX_B7_13->PS7_SAXIHP1AWCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_13" }, "PSS2.PSS1_IMUX_B7_14->PS7_SAXIHP1AWADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_14" }, "PSS2.PSS1_IMUX_B7_15->PS7_SAXIHP1AWLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_15" }, "PSS2.PSS1_IMUX_B7_16->PS7_SAXIHP2WDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_16" }, "PSS2.PSS1_IMUX_B7_17->PS7_SAXIHP2WDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_17" }, "PSS2.PSS1_IMUX_B7_18->PS7_SAXIHP2WDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_18" }, "PSS2.PSS1_IMUX_B7_19->PS7_SAXIHP2WDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_19" }, "PSS2.PSS1_IMUX_B7_2->PS7_SAXIHP0WDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_2" }, "PSS2.PSS1_IMUX_B7_20->PS7_SAXIHP2AWPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_20" }, "PSS2.PSS1_IMUX_B7_21->PS7_SAXIHP2AWCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_21" }, "PSS2.PSS1_IMUX_B7_22->PS7_SAXIHP2AWADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_22" }, "PSS2.PSS1_IMUX_B7_23->PS7_SAXIHP2AWLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_23" }, "PSS2.PSS1_IMUX_B7_24->PS7_SAXIHP3WDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_24" }, "PSS2.PSS1_IMUX_B7_25->PS7_SAXIHP3WDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_25" }, "PSS2.PSS1_IMUX_B7_26->PS7_SAXIHP3WDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_26" }, "PSS2.PSS1_IMUX_B7_27->PS7_SAXIHP3WDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_27" }, "PSS2.PSS1_IMUX_B7_28->PS7_SAXIHP3AWPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_28" }, "PSS2.PSS1_IMUX_B7_29->PS7_SAXIHP3AWCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_29" }, "PSS2.PSS1_IMUX_B7_3->PS7_SAXIHP0WDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_3" }, "PSS2.PSS1_IMUX_B7_30->PS7_SAXIHP3AWADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_30" }, "PSS2.PSS1_IMUX_B7_31->PS7_SAXIHP3AWLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_31" }, "PSS2.PSS1_IMUX_B7_32->PS7_SAXIACPWDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_32" }, "PSS2.PSS1_IMUX_B7_33->PS7_SAXIACPWDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_33" }, "PSS2.PSS1_IMUX_B7_34->PS7_SAXIACPWDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_34" }, "PSS2.PSS1_IMUX_B7_35->PS7_SAXIACPWDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_35" }, "PSS2.PSS1_IMUX_B7_36->PS7_SAXIACPAWUSER1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWUSER1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_36" }, "PSS2.PSS1_IMUX_B7_37->PS7_SAXIACPAWLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_37" }, "PSS2.PSS1_IMUX_B7_38->PS7_SAXIACPAWLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_38" }, "PSS2.PSS1_IMUX_B7_39->PS7_SAXIACPAWADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_39" }, "PSS2.PSS1_IMUX_B7_4->PS7_SAXIHP0AWPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_4" }, "PSS2.PSS1_IMUX_B7_5->PS7_SAXIHP0AWCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_5" }, "PSS2.PSS1_IMUX_B7_6->PS7_SAXIHP0AWADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_6" }, "PSS2.PSS1_IMUX_B7_7->PS7_SAXIHP0AWLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_7" }, "PSS2.PSS1_IMUX_B7_8->PS7_SAXIHP1WDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_8" }, "PSS2.PSS1_IMUX_B7_9->PS7_SAXIHP1WDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B7_9" }, "PSS2.PSS1_IMUX_B8_0->PS7_SAXIHP0WDATA32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_0" }, "PSS2.PSS1_IMUX_B8_1->PS7_SAXIHP0WDATA36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_1" }, "PSS2.PSS1_IMUX_B8_10->PS7_SAXIHP1WDATA40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_10" }, "PSS2.PSS1_IMUX_B8_11->PS7_SAXIHP1WDATA44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_11" }, "PSS2.PSS1_IMUX_B8_12->PS7_SAXIHP1AWPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_12" }, "PSS2.PSS1_IMUX_B8_13->PS7_SAXIHP1AWCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_13" }, "PSS2.PSS1_IMUX_B8_14->PS7_SAXIHP1AWSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_14" }, "PSS2.PSS1_IMUX_B8_15->PS7_SAXIHP1AWLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_15" }, "PSS2.PSS1_IMUX_B8_16->PS7_SAXIHP2WDATA32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_16" }, "PSS2.PSS1_IMUX_B8_17->PS7_SAXIHP2WDATA36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_17" }, "PSS2.PSS1_IMUX_B8_18->PS7_SAXIHP2WDATA40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_18" }, "PSS2.PSS1_IMUX_B8_19->PS7_SAXIHP2WDATA44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_19" }, "PSS2.PSS1_IMUX_B8_2->PS7_SAXIHP0WDATA40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_2" }, "PSS2.PSS1_IMUX_B8_20->PS7_SAXIHP2AWPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_20" }, "PSS2.PSS1_IMUX_B8_21->PS7_SAXIHP2AWCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_21" }, "PSS2.PSS1_IMUX_B8_22->PS7_SAXIHP2AWSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_22" }, "PSS2.PSS1_IMUX_B8_23->PS7_SAXIHP2AWLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_23" }, "PSS2.PSS1_IMUX_B8_24->PS7_SAXIHP3WDATA32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_24" }, "PSS2.PSS1_IMUX_B8_25->PS7_SAXIHP3WDATA36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_25" }, "PSS2.PSS1_IMUX_B8_26->PS7_SAXIHP3WDATA40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_26" }, "PSS2.PSS1_IMUX_B8_27->PS7_SAXIHP3WDATA44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_27" }, "PSS2.PSS1_IMUX_B8_28->PS7_SAXIHP3AWPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_28" }, "PSS2.PSS1_IMUX_B8_29->PS7_SAXIHP3AWCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_29" }, "PSS2.PSS1_IMUX_B8_3->PS7_SAXIHP0WDATA44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_3" }, "PSS2.PSS1_IMUX_B8_30->PS7_SAXIHP3AWSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_30" }, "PSS2.PSS1_IMUX_B8_31->PS7_SAXIHP3AWLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_31" }, "PSS2.PSS1_IMUX_B8_32->PS7_SAXIACPWDATA32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_32" }, "PSS2.PSS1_IMUX_B8_33->PS7_SAXIACPWDATA36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_33" }, "PSS2.PSS1_IMUX_B8_34->PS7_SAXIACPWDATA40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_34" }, "PSS2.PSS1_IMUX_B8_35->PS7_SAXIACPWDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_35" }, "PSS2.PSS1_IMUX_B8_36->PS7_SAXIACPAWUSER2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWUSER2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_36" }, "PSS2.PSS1_IMUX_B8_37->PS7_SAXIACPAWCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_37" }, "PSS2.PSS1_IMUX_B8_38->PS7_SAXIACPAWLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_38" }, "PSS2.PSS1_IMUX_B8_39->PS7_SAXIACPAWADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_39" }, "PSS2.PSS1_IMUX_B8_4->PS7_SAXIHP0AWPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_4" }, "PSS2.PSS1_IMUX_B8_5->PS7_SAXIHP0AWCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_5" }, "PSS2.PSS1_IMUX_B8_6->PS7_SAXIHP0AWSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_6" }, "PSS2.PSS1_IMUX_B8_7->PS7_SAXIHP0AWLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_7" }, "PSS2.PSS1_IMUX_B8_8->PS7_SAXIHP1WDATA32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_8" }, "PSS2.PSS1_IMUX_B8_9->PS7_SAXIHP1WDATA36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B8_9" }, "PSS2.PSS1_IMUX_B9_0->PS7_SAXIHP0WDATA33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_0" }, "PSS2.PSS1_IMUX_B9_1->PS7_SAXIHP0WDATA37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_1" }, "PSS2.PSS1_IMUX_B9_10->PS7_SAXIHP1WDATA41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_10" }, "PSS2.PSS1_IMUX_B9_11->PS7_SAXIHP1WDATA45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_11" }, "PSS2.PSS1_IMUX_B9_12->PS7_SAXIHP1AWVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_12" }, "PSS2.PSS1_IMUX_B9_13->PS7_SAXIHP1WID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_13" }, "PSS2.PSS1_IMUX_B9_14->PS7_SAXIHP1AWSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_14" }, "PSS2.PSS1_IMUX_B9_15->PS7_SAXIHP1AWLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1AWLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_15" }, "PSS2.PSS1_IMUX_B9_16->PS7_SAXIHP2WDATA33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_16" }, "PSS2.PSS1_IMUX_B9_17->PS7_SAXIHP2WDATA37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_17" }, "PSS2.PSS1_IMUX_B9_18->PS7_SAXIHP2WDATA41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_18" }, "PSS2.PSS1_IMUX_B9_19->PS7_SAXIHP2WDATA45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WDATA45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_19" }, "PSS2.PSS1_IMUX_B9_2->PS7_SAXIHP0WDATA41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_2" }, "PSS2.PSS1_IMUX_B9_20->PS7_SAXIHP2AWVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_20" }, "PSS2.PSS1_IMUX_B9_21->PS7_SAXIHP2WID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2WID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_21" }, "PSS2.PSS1_IMUX_B9_22->PS7_SAXIHP2AWSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_22" }, "PSS2.PSS1_IMUX_B9_23->PS7_SAXIHP2AWLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP2AWLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_23" }, "PSS2.PSS1_IMUX_B9_24->PS7_SAXIHP3WDATA33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_24" }, "PSS2.PSS1_IMUX_B9_25->PS7_SAXIHP3WDATA37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_25" }, "PSS2.PSS1_IMUX_B9_26->PS7_SAXIHP3WDATA41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_26" }, "PSS2.PSS1_IMUX_B9_27->PS7_SAXIHP3WDATA45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WDATA45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_27" }, "PSS2.PSS1_IMUX_B9_28->PS7_SAXIHP3AWVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_28" }, "PSS2.PSS1_IMUX_B9_29->PS7_SAXIHP3WID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3WID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_29" }, "PSS2.PSS1_IMUX_B9_3->PS7_SAXIHP0WDATA45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WDATA45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_3" }, "PSS2.PSS1_IMUX_B9_30->PS7_SAXIHP3AWSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_30" }, "PSS2.PSS1_IMUX_B9_31->PS7_SAXIHP3AWLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP3AWLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_31" }, "PSS2.PSS1_IMUX_B9_32->PS7_SAXIACPWDATA33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_32" }, "PSS2.PSS1_IMUX_B9_33->PS7_SAXIACPWDATA37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_33" }, "PSS2.PSS1_IMUX_B9_34->PS7_SAXIACPWDATA41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_34" }, "PSS2.PSS1_IMUX_B9_35->PS7_SAXIACPWDATA44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_35" }, "PSS2.PSS1_IMUX_B9_36->PS7_SAXIACPAWUSER3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWUSER3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_36" }, "PSS2.PSS1_IMUX_B9_37->PS7_SAXIACPAWCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_37" }, "PSS2.PSS1_IMUX_B9_38->PS7_SAXIACPAWLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPAWLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_38" }, "PSS2.PSS1_IMUX_B9_39->PS7_SAXIACPWDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIACPWDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_39" }, "PSS2.PSS1_IMUX_B9_4->PS7_SAXIHP0AWVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_4" }, "PSS2.PSS1_IMUX_B9_5->PS7_SAXIHP0WID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0WID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_5" }, "PSS2.PSS1_IMUX_B9_6->PS7_SAXIHP0AWSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_6" }, "PSS2.PSS1_IMUX_B9_7->PS7_SAXIHP0AWLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP0AWLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_7" }, "PSS2.PSS1_IMUX_B9_8->PS7_SAXIHP1WDATA33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_8" }, "PSS2.PSS1_IMUX_B9_9->PS7_SAXIHP1WDATA37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIHP1WDATA37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_IMUX_B9_9" }, "PSS2.PSS2_CLK_B0_60->PS7_FTMDTRACEINCLOCK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINCLOCK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_CLK_B0_60" }, "PSS2.PSS2_CLK_B0_67->PS7_EMIOENET0GMIITXCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIITXCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_CLK_B0_67" }, "PSS2.PSS2_CLK_B0_68->PS7_EMIOENET0GMIIRXCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIIRXCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_CLK_B0_68" }, "PSS2.PSS2_CLK_B0_71->PS7_EMIOENET1GMIITXCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIITXCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_CLK_B0_71" }, "PSS2.PSS2_CLK_B0_72->PS7_EMIOENET1GMIIRXCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIIRXCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_CLK_B0_72" }, "PSS2.PSS2_CLK_B0_77->PS7_SAXIGP0ACLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ACLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_CLK_B0_77" }, "PSS2.PSS2_CLK_B0_85->PS7_SAXIGP1ACLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ACLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_CLK_B0_85" }, "PSS2.PSS2_CLK_B0_89->PS7_EMIOTRACECLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOTRACECLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_CLK_B0_89" }, "PSS2.PSS2_CLK_B0_92->PS7_EMIOSDIO0CLKFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO0CLKFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_CLK_B0_92" }, "PSS2.PSS2_CLK_B0_96->PS7_EMIOSDIO1CLKFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO1CLKFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_CLK_B0_96" }, "PSS2.PSS2_CLK_B0_98->PS7_EMIOPJTAGTCK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOPJTAGTCK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_CLK_B0_98" }, "PSS2.PSS2_IMUX_B0_60->PS7_EMIOGPIOI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_60" }, "PSS2.PSS2_IMUX_B0_61->PS7_EMIOGPIOI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_61" }, "PSS2.PSS2_IMUX_B0_62->PS7_EMIOGPIOI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_62" }, "PSS2.PSS2_IMUX_B0_63->PS7_EMIOGPIOI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_63" }, "PSS2.PSS2_IMUX_B0_64->PS7_EMIOGPIOI16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_64" }, "PSS2.PSS2_IMUX_B0_65->PS7_EMIOGPIOI20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_65" }, "PSS2.PSS2_IMUX_B0_66->PS7_EMIOENET0MDIOI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0MDIOI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_66" }, "PSS2.PSS2_IMUX_B0_67->PS7_EMIOENET0GMIIRXD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIIRXD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_67" }, "PSS2.PSS2_IMUX_B0_68->PS7_EMIOENET0GMIICRS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIICRS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_68" }, "PSS2.PSS2_IMUX_B0_69->PS7_EMIOGPIOI36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_69" }, "PSS2.PSS2_IMUX_B0_70->PS7_EMIOENET1MDIOI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1MDIOI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_70" }, "PSS2.PSS2_IMUX_B0_71->PS7_EMIOENET1GMIIRXD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIIRXD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_71" }, "PSS2.PSS2_IMUX_B0_72->PS7_EMIOENET1GMIICRS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIICRS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_72" }, "PSS2.PSS2_IMUX_B0_73->PS7_SAXIGP0AWADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_73" }, "PSS2.PSS2_IMUX_B0_74->PS7_SAXIGP0AWADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_74" }, "PSS2.PSS2_IMUX_B0_75->PS7_SAXIGP0AWADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_75" }, "PSS2.PSS2_IMUX_B0_76->PS7_SAXIGP0AWADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_76" }, "PSS2.PSS2_IMUX_B0_77->PS7_SAXIGP0AWADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_77" }, "PSS2.PSS2_IMUX_B0_78->PS7_SAXIGP0AWADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_78" }, "PSS2.PSS2_IMUX_B0_79->PS7_SAXIGP0AWID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_79" }, "PSS2.PSS2_IMUX_B0_80->PS7_SAXIGP0AWID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_80" }, "PSS2.PSS2_IMUX_B0_81->PS7_SAXIGP1AWADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_81" }, "PSS2.PSS2_IMUX_B0_82->PS7_SAXIGP1AWADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_82" }, "PSS2.PSS2_IMUX_B0_83->PS7_SAXIGP1AWADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_83" }, "PSS2.PSS2_IMUX_B0_84->PS7_SAXIGP1AWADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_84" }, "PSS2.PSS2_IMUX_B0_85->PS7_SAXIGP1AWADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_85" }, "PSS2.PSS2_IMUX_B0_86->PS7_SAXIGP1AWADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_86" }, "PSS2.PSS2_IMUX_B0_87->PS7_SAXIGP1AWID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_87" }, "PSS2.PSS2_IMUX_B0_88->PS7_SAXIGP1AWID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_88" }, "PSS2.PSS2_IMUX_B0_89->PS7_EMIOTTC0CLKI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOTTC0CLKI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_89" }, "PSS2.PSS2_IMUX_B0_90->PS7_EMIOTTC1CLKI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOTTC1CLKI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_90" }, "PSS2.PSS2_IMUX_B0_93->PS7_EMIOSPI0SI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSPI0SI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_93" }, "PSS2.PSS2_IMUX_B0_94->PS7_EMIOSPI0SCLKI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSPI0SCLKI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_94" }, "PSS2.PSS2_IMUX_B0_96->PS7_EMIOPJTAGTMS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOPJTAGTMS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_96" }, "PSS2.PSS2_IMUX_B0_97->PS7_EMIOSPI1SI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSPI1SI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_97" }, "PSS2.PSS2_IMUX_B0_98->PS7_EMIOSPI1SCLKI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSPI1SCLKI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B0_98" }, "PSS2.PSS2_IMUX_B10_60->PS7_FTMDTRACEINATID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINATID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_60" }, "PSS2.PSS2_IMUX_B10_61->PS7_FTMTF2PDEBUG4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_61" }, "PSS2.PSS2_IMUX_B10_62->PS7_FTMTP2FTRIGACK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTP2FTRIGACK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_62" }, "PSS2.PSS2_IMUX_B10_63->PS7_FTMTF2PDEBUG13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_63" }, "PSS2.PSS2_IMUX_B10_64->PS7_FTMTF2PDEBUG16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_64" }, "PSS2.PSS2_IMUX_B10_65->PS7_FTMTF2PDEBUG21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_65" }, "PSS2.PSS2_IMUX_B10_66->PS7_FTMTF2PDEBUG27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_66" }, "PSS2.PSS2_IMUX_B10_67->PS7_FTMTF2PDEBUG29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_67" }, "PSS2.PSS2_IMUX_B10_68->PS7_EMIOGPIOI34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_68" }, "PSS2.PSS2_IMUX_B10_70->PS7_FTMDTRACEINDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_70" }, "PSS2.PSS2_IMUX_B10_71->PS7_EMIOGPIOI54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_71" }, "PSS2.PSS2_IMUX_B10_72->PS7_EMIOGPIOI58": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI58", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_72" }, "PSS2.PSS2_IMUX_B10_73->PS7_SAXIGP0ARADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_73" }, "PSS2.PSS2_IMUX_B10_74->PS7_SAXIGP0ARADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_74" }, "PSS2.PSS2_IMUX_B10_75->PS7_SAXIGP0ARID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_75" }, "PSS2.PSS2_IMUX_B10_76->PS7_SAXIGP0WDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_76" }, "PSS2.PSS2_IMUX_B10_77->PS7_SAXIGP0WID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_77" }, "PSS2.PSS2_IMUX_B10_78->PS7_SAXIGP0WDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_78" }, "PSS2.PSS2_IMUX_B10_79->PS7_SAXIGP0WDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_79" }, "PSS2.PSS2_IMUX_B10_80->PS7_SAXIGP0AWLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_80" }, "PSS2.PSS2_IMUX_B10_81->PS7_SAXIGP1ARADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_81" }, "PSS2.PSS2_IMUX_B10_82->PS7_SAXIGP1ARADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_82" }, "PSS2.PSS2_IMUX_B10_83->PS7_SAXIGP1ARID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_83" }, "PSS2.PSS2_IMUX_B10_84->PS7_SAXIGP1WDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_84" }, "PSS2.PSS2_IMUX_B10_85->PS7_SAXIGP1WID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_85" }, "PSS2.PSS2_IMUX_B10_86->PS7_SAXIGP1WDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_86" }, "PSS2.PSS2_IMUX_B10_87->PS7_SAXIGP1WDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_87" }, "PSS2.PSS2_IMUX_B10_88->PS7_SAXIGP1AWLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_88" }, "PSS2.PSS2_IMUX_B10_89->PS7_EMIOUART1DCDN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOUART1DCDN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_89" }, "PSS2.PSS2_IMUX_B10_90->PS7_EMIOUART0RIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOUART0RIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B10_90" }, "PSS2.PSS2_IMUX_B11_60->PS7_FTMDTRACEINATID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINATID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_60" }, "PSS2.PSS2_IMUX_B11_61->PS7_FTMTF2PDEBUG5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_61" }, "PSS2.PSS2_IMUX_B11_62->PS7_FTMTF2PDEBUG8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_62" }, "PSS2.PSS2_IMUX_B11_63->PS7_FTMTF2PDEBUG14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_63" }, "PSS2.PSS2_IMUX_B11_64->PS7_FTMTF2PDEBUG17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_64" }, "PSS2.PSS2_IMUX_B11_65->PS7_FTMTF2PDEBUG22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_65" }, "PSS2.PSS2_IMUX_B11_67->PS7_FTMTF2PDEBUG30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_67" }, "PSS2.PSS2_IMUX_B11_68->PS7_EMIOGPIOI35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_68" }, "PSS2.PSS2_IMUX_B11_70->PS7_FTMDTRACEINDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_70" }, "PSS2.PSS2_IMUX_B11_71->PS7_EMIOGPIOI55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_71" }, "PSS2.PSS2_IMUX_B11_72->PS7_EMIOGPIOI59": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI59", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_72" }, "PSS2.PSS2_IMUX_B11_73->PS7_SAXIGP0ARADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_73" }, "PSS2.PSS2_IMUX_B11_74->PS7_SAXIGP0ARADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_74" }, "PSS2.PSS2_IMUX_B11_75->PS7_SAXIGP0ARID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_75" }, "PSS2.PSS2_IMUX_B11_76->PS7_SAXIGP0WDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_76" }, "PSS2.PSS2_IMUX_B11_77->PS7_SAXIGP0WDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_77" }, "PSS2.PSS2_IMUX_B11_78->PS7_SAXIGP0WDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_78" }, "PSS2.PSS2_IMUX_B11_79->PS7_SAXIGP0WDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_79" }, "PSS2.PSS2_IMUX_B11_80->PS7_SAXIGP0AWLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_80" }, "PSS2.PSS2_IMUX_B11_81->PS7_SAXIGP1ARADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_81" }, "PSS2.PSS2_IMUX_B11_82->PS7_SAXIGP1ARADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_82" }, "PSS2.PSS2_IMUX_B11_83->PS7_SAXIGP1ARID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_83" }, "PSS2.PSS2_IMUX_B11_84->PS7_SAXIGP1WDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_84" }, "PSS2.PSS2_IMUX_B11_85->PS7_SAXIGP1WDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_85" }, "PSS2.PSS2_IMUX_B11_86->PS7_SAXIGP1WDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_86" }, "PSS2.PSS2_IMUX_B11_87->PS7_SAXIGP1WDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_87" }, "PSS2.PSS2_IMUX_B11_88->PS7_SAXIGP1AWLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_88" }, "PSS2.PSS2_IMUX_B11_89->PS7_EMIOUART1RIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOUART1RIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B11_89" }, "PSS2.PSS2_IMUX_B12_60->PS7_FTMTP2FTRIGACK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTP2FTRIGACK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_60" }, "PSS2.PSS2_IMUX_B12_61->PS7_FTMTF2PDEBUG6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_61" }, "PSS2.PSS2_IMUX_B12_62->PS7_FTMTF2PDEBUG9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_62" }, "PSS2.PSS2_IMUX_B12_63->PS7_FTMTF2PDEBUG15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_63" }, "PSS2.PSS2_IMUX_B12_64->PS7_FTMTF2PDEBUG18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_64" }, "PSS2.PSS2_IMUX_B12_65->PS7_FTMTF2PDEBUG23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_65" }, "PSS2.PSS2_IMUX_B12_67->PS7_FTMTF2PDEBUG31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_67" }, "PSS2.PSS2_IMUX_B12_70->PS7_FTMDTRACEINDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_70" }, "PSS2.PSS2_IMUX_B12_72->PS7_EMIOGPIOI60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_72" }, "PSS2.PSS2_IMUX_B12_73->PS7_SAXIGP0ARCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_73" }, "PSS2.PSS2_IMUX_B12_74->PS7_SAXIGP0ARADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_74" }, "PSS2.PSS2_IMUX_B12_75->PS7_SAXIGP0ARADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_75" }, "PSS2.PSS2_IMUX_B12_76->PS7_SAXIGP0WDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_76" }, "PSS2.PSS2_IMUX_B12_77->PS7_SAXIGP0WDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_77" }, "PSS2.PSS2_IMUX_B12_78->PS7_SAXIGP0WDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_78" }, "PSS2.PSS2_IMUX_B12_79->PS7_SAXIGP0WSTRB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WSTRB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_79" }, "PSS2.PSS2_IMUX_B12_80->PS7_SAXIGP0WDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_80" }, "PSS2.PSS2_IMUX_B12_81->PS7_SAXIGP1ARCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_81" }, "PSS2.PSS2_IMUX_B12_82->PS7_SAXIGP1ARADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_82" }, "PSS2.PSS2_IMUX_B12_83->PS7_SAXIGP1ARADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_83" }, "PSS2.PSS2_IMUX_B12_84->PS7_SAXIGP1WDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_84" }, "PSS2.PSS2_IMUX_B12_85->PS7_SAXIGP1WDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_85" }, "PSS2.PSS2_IMUX_B12_86->PS7_SAXIGP1WDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_86" }, "PSS2.PSS2_IMUX_B12_87->PS7_SAXIGP1WSTRB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WSTRB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_87" }, "PSS2.PSS2_IMUX_B12_88->PS7_SAXIGP1WDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_88" }, "PSS2.PSS2_IMUX_B12_89->PS7_EMIOSRAMINTIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSRAMINTIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B12_89" }, "PSS2.PSS2_IMUX_B13_60->PS7_FTMTF2PDEBUG0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_60" }, "PSS2.PSS2_IMUX_B13_61->PS7_FTMTF2PDEBUG7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_61" }, "PSS2.PSS2_IMUX_B13_62->PS7_FTMTF2PDEBUG10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_62" }, "PSS2.PSS2_IMUX_B13_64->PS7_FTMTF2PDEBUG19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_64" }, "PSS2.PSS2_IMUX_B13_70->PS7_FTMDTRACEINDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_70" }, "PSS2.PSS2_IMUX_B13_72->PS7_EMIOGPIOI61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_72" }, "PSS2.PSS2_IMUX_B13_73->PS7_SAXIGP0ARCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_73" }, "PSS2.PSS2_IMUX_B13_74->PS7_SAXIGP0ARBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_74" }, "PSS2.PSS2_IMUX_B13_75->PS7_SAXIGP0ARADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_75" }, "PSS2.PSS2_IMUX_B13_76->PS7_SAXIGP0ARID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_76" }, "PSS2.PSS2_IMUX_B13_77->PS7_SAXIGP0WDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_77" }, "PSS2.PSS2_IMUX_B13_78->PS7_SAXIGP0WDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_78" }, "PSS2.PSS2_IMUX_B13_79->PS7_SAXIGP0WSTRB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WSTRB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_79" }, "PSS2.PSS2_IMUX_B13_80->PS7_SAXIGP0WDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_80" }, "PSS2.PSS2_IMUX_B13_81->PS7_SAXIGP1ARCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_81" }, "PSS2.PSS2_IMUX_B13_82->PS7_SAXIGP1ARBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_82" }, "PSS2.PSS2_IMUX_B13_83->PS7_SAXIGP1ARADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_83" }, "PSS2.PSS2_IMUX_B13_84->PS7_SAXIGP1ARID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_84" }, "PSS2.PSS2_IMUX_B13_85->PS7_SAXIGP1WDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_85" }, "PSS2.PSS2_IMUX_B13_86->PS7_SAXIGP1WDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_86" }, "PSS2.PSS2_IMUX_B13_87->PS7_SAXIGP1WSTRB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WSTRB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_87" }, "PSS2.PSS2_IMUX_B13_88->PS7_SAXIGP1WDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B13_88" }, "PSS2.PSS2_IMUX_B14_60->PS7_FTMTF2PDEBUG1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_60" }, "PSS2.PSS2_IMUX_B14_62->PS7_FTMTF2PDEBUG11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_62" }, "PSS2.PSS2_IMUX_B14_64->PS7_FPGAIDLEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FPGAIDLEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_64" }, "PSS2.PSS2_IMUX_B14_72->PS7_EMIOGPIOI62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_72" }, "PSS2.PSS2_IMUX_B14_73->PS7_SAXIGP0ARCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_73" }, "PSS2.PSS2_IMUX_B14_74->PS7_SAXIGP0ARBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_74" }, "PSS2.PSS2_IMUX_B14_75->PS7_SAXIGP0ARADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_75" }, "PSS2.PSS2_IMUX_B14_76->PS7_SAXIGP0ARID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_76" }, "PSS2.PSS2_IMUX_B14_77->PS7_SAXIGP0WDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_77" }, "PSS2.PSS2_IMUX_B14_78->PS7_SAXIGP0BREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0BREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_78" }, "PSS2.PSS2_IMUX_B14_79->PS7_SAXIGP0WSTRB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WSTRB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_79" }, "PSS2.PSS2_IMUX_B14_80->PS7_SAXIGP0WDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_80" }, "PSS2.PSS2_IMUX_B14_81->PS7_SAXIGP1ARCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_81" }, "PSS2.PSS2_IMUX_B14_82->PS7_SAXIGP1ARBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_82" }, "PSS2.PSS2_IMUX_B14_83->PS7_SAXIGP1ARADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_83" }, "PSS2.PSS2_IMUX_B14_84->PS7_SAXIGP1ARID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_84" }, "PSS2.PSS2_IMUX_B14_85->PS7_SAXIGP1WDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_85" }, "PSS2.PSS2_IMUX_B14_86->PS7_SAXIGP1BREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1BREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_86" }, "PSS2.PSS2_IMUX_B14_87->PS7_SAXIGP1WSTRB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WSTRB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_87" }, "PSS2.PSS2_IMUX_B14_88->PS7_SAXIGP1WDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B14_88" }, "PSS2.PSS2_IMUX_B15_60->PS7_FTMTF2PDEBUG2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_60" }, "PSS2.PSS2_IMUX_B15_72->PS7_EMIOGPIOI63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_72" }, "PSS2.PSS2_IMUX_B15_73->PS7_SAXIGP0ARCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_73" }, "PSS2.PSS2_IMUX_B15_74->PS7_SAXIGP0ARLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_74" }, "PSS2.PSS2_IMUX_B15_75->PS7_SAXIGP0ARADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_75" }, "PSS2.PSS2_IMUX_B15_76->PS7_SAXIGP0ARADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_76" }, "PSS2.PSS2_IMUX_B15_77->PS7_SAXIGP0WVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_77" }, "PSS2.PSS2_IMUX_B15_78->PS7_SAXIGP0ARADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_78" }, "PSS2.PSS2_IMUX_B15_79->PS7_SAXIGP0WSTRB3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WSTRB3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_79" }, "PSS2.PSS2_IMUX_B15_80->PS7_SAXIGP0WDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_80" }, "PSS2.PSS2_IMUX_B15_81->PS7_SAXIGP1ARCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_81" }, "PSS2.PSS2_IMUX_B15_82->PS7_SAXIGP1ARLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_82" }, "PSS2.PSS2_IMUX_B15_83->PS7_SAXIGP1ARADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_83" }, "PSS2.PSS2_IMUX_B15_84->PS7_SAXIGP1ARADDR12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_84" }, "PSS2.PSS2_IMUX_B15_85->PS7_SAXIGP1WVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_85" }, "PSS2.PSS2_IMUX_B15_86->PS7_SAXIGP1ARADDR20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_86" }, "PSS2.PSS2_IMUX_B15_87->PS7_SAXIGP1WSTRB3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WSTRB3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_87" }, "PSS2.PSS2_IMUX_B15_88->PS7_SAXIGP1WDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B15_88" }, "PSS2.PSS2_IMUX_B16_60->PS7_FTMTF2PDEBUG3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_60" }, "PSS2.PSS2_IMUX_B16_73->PS7_SAXIGP0ARPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_73" }, "PSS2.PSS2_IMUX_B16_74->PS7_SAXIGP0ARLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_74" }, "PSS2.PSS2_IMUX_B16_75->PS7_SAXIGP0ARLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_75" }, "PSS2.PSS2_IMUX_B16_76->PS7_SAXIGP0ARADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_76" }, "PSS2.PSS2_IMUX_B16_77->PS7_SAXIGP0ARADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_77" }, "PSS2.PSS2_IMUX_B16_78->PS7_SAXIGP0ARADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_78" }, "PSS2.PSS2_IMUX_B16_79->PS7_SAXIGP0ARADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_79" }, "PSS2.PSS2_IMUX_B16_80->PS7_SAXIGP0ARADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_80" }, "PSS2.PSS2_IMUX_B16_81->PS7_SAXIGP1ARPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_81" }, "PSS2.PSS2_IMUX_B16_82->PS7_SAXIGP1ARLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_82" }, "PSS2.PSS2_IMUX_B16_83->PS7_SAXIGP1ARLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_83" }, "PSS2.PSS2_IMUX_B16_84->PS7_SAXIGP1ARADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_84" }, "PSS2.PSS2_IMUX_B16_85->PS7_SAXIGP1ARADDR16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_85" }, "PSS2.PSS2_IMUX_B16_86->PS7_SAXIGP1ARADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_86" }, "PSS2.PSS2_IMUX_B16_87->PS7_SAXIGP1ARADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_87" }, "PSS2.PSS2_IMUX_B16_88->PS7_SAXIGP1ARADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B16_88" }, "PSS2.PSS2_IMUX_B17_73->PS7_SAXIGP0ARPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_73" }, "PSS2.PSS2_IMUX_B17_74->PS7_SAXIGP0ARQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_74" }, "PSS2.PSS2_IMUX_B17_75->PS7_SAXIGP0ARLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_75" }, "PSS2.PSS2_IMUX_B17_76->PS7_SAXIGP0ARADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_76" }, "PSS2.PSS2_IMUX_B17_77->PS7_SAXIGP0ARADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_77" }, "PSS2.PSS2_IMUX_B17_78->PS7_SAXIGP0ARADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_78" }, "PSS2.PSS2_IMUX_B17_79->PS7_SAXIGP0ARADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_79" }, "PSS2.PSS2_IMUX_B17_80->PS7_SAXIGP0ARADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_80" }, "PSS2.PSS2_IMUX_B17_81->PS7_SAXIGP1ARPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_81" }, "PSS2.PSS2_IMUX_B17_82->PS7_SAXIGP1ARQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_82" }, "PSS2.PSS2_IMUX_B17_83->PS7_SAXIGP1ARLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_83" }, "PSS2.PSS2_IMUX_B17_84->PS7_SAXIGP1ARADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_84" }, "PSS2.PSS2_IMUX_B17_85->PS7_SAXIGP1ARADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_85" }, "PSS2.PSS2_IMUX_B17_86->PS7_SAXIGP1ARADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_86" }, "PSS2.PSS2_IMUX_B17_87->PS7_SAXIGP1ARADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_87" }, "PSS2.PSS2_IMUX_B17_88->PS7_SAXIGP1ARADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B17_88" }, "PSS2.PSS2_IMUX_B18_73->PS7_SAXIGP0ARPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_73" }, "PSS2.PSS2_IMUX_B18_74->PS7_SAXIGP0ARQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_74" }, "PSS2.PSS2_IMUX_B18_75->PS7_SAXIGP0ARLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_75" }, "PSS2.PSS2_IMUX_B18_76->PS7_SAXIGP0ARADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_76" }, "PSS2.PSS2_IMUX_B18_77->PS7_SAXIGP0ARADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_77" }, "PSS2.PSS2_IMUX_B18_78->PS7_SAXIGP0ARADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_78" }, "PSS2.PSS2_IMUX_B18_79->PS7_SAXIGP0ARADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_79" }, "PSS2.PSS2_IMUX_B18_80->PS7_SAXIGP0ARADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_80" }, "PSS2.PSS2_IMUX_B18_81->PS7_SAXIGP1ARPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_81" }, "PSS2.PSS2_IMUX_B18_82->PS7_SAXIGP1ARQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_82" }, "PSS2.PSS2_IMUX_B18_83->PS7_SAXIGP1ARLEN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARLEN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_83" }, "PSS2.PSS2_IMUX_B18_84->PS7_SAXIGP1ARADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_84" }, "PSS2.PSS2_IMUX_B18_85->PS7_SAXIGP1ARADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_85" }, "PSS2.PSS2_IMUX_B18_86->PS7_SAXIGP1ARADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_86" }, "PSS2.PSS2_IMUX_B18_87->PS7_SAXIGP1ARADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_87" }, "PSS2.PSS2_IMUX_B18_88->PS7_SAXIGP1ARADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B18_88" }, "PSS2.PSS2_IMUX_B19_74->PS7_SAXIGP0ARQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_74" }, "PSS2.PSS2_IMUX_B19_75->PS7_SAXIGP0ARLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_75" }, "PSS2.PSS2_IMUX_B19_76->PS7_SAXIGP0ARVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_76" }, "PSS2.PSS2_IMUX_B19_77->PS7_SAXIGP0ARADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_77" }, "PSS2.PSS2_IMUX_B19_78->PS7_SAXIGP0AWQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_78" }, "PSS2.PSS2_IMUX_B19_79->PS7_SAXIGP0ARADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_79" }, "PSS2.PSS2_IMUX_B19_80->PS7_SAXIGP0ARADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_80" }, "PSS2.PSS2_IMUX_B19_82->PS7_SAXIGP1ARQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_82" }, "PSS2.PSS2_IMUX_B19_83->PS7_SAXIGP1ARLEN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARLEN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_83" }, "PSS2.PSS2_IMUX_B19_84->PS7_SAXIGP1ARVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_84" }, "PSS2.PSS2_IMUX_B19_85->PS7_SAXIGP1ARADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_85" }, "PSS2.PSS2_IMUX_B19_86->PS7_SAXIGP1AWQOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWQOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_86" }, "PSS2.PSS2_IMUX_B19_87->PS7_SAXIGP1ARADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_87" }, "PSS2.PSS2_IMUX_B19_88->PS7_SAXIGP1ARADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B19_88" }, "PSS2.PSS2_IMUX_B1_60->PS7_EMIOGPIOI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_60" }, "PSS2.PSS2_IMUX_B1_61->PS7_EMIOGPIOI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_61" }, "PSS2.PSS2_IMUX_B1_62->PS7_EMIOGPIOI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_62" }, "PSS2.PSS2_IMUX_B1_63->PS7_EMIOGPIOI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_63" }, "PSS2.PSS2_IMUX_B1_64->PS7_EMIOGPIOI17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_64" }, "PSS2.PSS2_IMUX_B1_65->PS7_EMIOGPIOI21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_65" }, "PSS2.PSS2_IMUX_B1_66->PS7_EMIOENET0EXTINTIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0EXTINTIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_66" }, "PSS2.PSS2_IMUX_B1_67->PS7_EMIOENET0GMIIRXD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIIRXD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_67" }, "PSS2.PSS2_IMUX_B1_68->PS7_EMIOENET0GMIICOL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIICOL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_68" }, "PSS2.PSS2_IMUX_B1_69->PS7_EMIOGPIOI37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_69" }, "PSS2.PSS2_IMUX_B1_70->PS7_EMIOENET1EXTINTIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1EXTINTIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_70" }, "PSS2.PSS2_IMUX_B1_71->PS7_EMIOENET1GMIIRXD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIIRXD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_71" }, "PSS2.PSS2_IMUX_B1_72->PS7_EMIOENET1GMIICOL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIICOL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_72" }, "PSS2.PSS2_IMUX_B1_73->PS7_SAXIGP0AWADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_73" }, "PSS2.PSS2_IMUX_B1_74->PS7_SAXIGP0AWADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_74" }, "PSS2.PSS2_IMUX_B1_75->PS7_SAXIGP0AWADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_75" }, "PSS2.PSS2_IMUX_B1_76->PS7_SAXIGP0AWADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_76" }, "PSS2.PSS2_IMUX_B1_77->PS7_SAXIGP0AWADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_77" }, "PSS2.PSS2_IMUX_B1_78->PS7_SAXIGP0AWADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_78" }, "PSS2.PSS2_IMUX_B1_79->PS7_SAXIGP0AWID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_79" }, "PSS2.PSS2_IMUX_B1_80->PS7_SAXIGP0AWID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_80" }, "PSS2.PSS2_IMUX_B1_81->PS7_SAXIGP1AWADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_81" }, "PSS2.PSS2_IMUX_B1_82->PS7_SAXIGP1AWADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_82" }, "PSS2.PSS2_IMUX_B1_83->PS7_SAXIGP1AWADDR9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_83" }, "PSS2.PSS2_IMUX_B1_84->PS7_SAXIGP1AWADDR13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_84" }, "PSS2.PSS2_IMUX_B1_85->PS7_SAXIGP1AWADDR17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_85" }, "PSS2.PSS2_IMUX_B1_86->PS7_SAXIGP1AWADDR21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_86" }, "PSS2.PSS2_IMUX_B1_87->PS7_SAXIGP1AWID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_87" }, "PSS2.PSS2_IMUX_B1_88->PS7_SAXIGP1AWID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_88" }, "PSS2.PSS2_IMUX_B1_89->PS7_EMIOTTC0CLKI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOTTC0CLKI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_89" }, "PSS2.PSS2_IMUX_B1_90->PS7_EMIOTTC1CLKI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOTTC1CLKI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_90" }, "PSS2.PSS2_IMUX_B1_93->PS7_EMIOSPI0SSIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSPI0SSIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_93" }, "PSS2.PSS2_IMUX_B1_94->PS7_EMIOSPI0MI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSPI0MI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_94" }, "PSS2.PSS2_IMUX_B1_96->PS7_EMIOPJTAGTDI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOPJTAGTDI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_96" }, "PSS2.PSS2_IMUX_B1_97->PS7_EMIOSPI1SSIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSPI1SSIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_97" }, "PSS2.PSS2_IMUX_B1_98->PS7_EMIOSPI1MI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSPI1MI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B1_98" }, "PSS2.PSS2_IMUX_B20_74->PS7_SAXIGP0ARQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B20_74" }, "PSS2.PSS2_IMUX_B20_75->PS7_SAXIGP0ARSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B20_75" }, "PSS2.PSS2_IMUX_B20_76->PS7_SAXIGP0RREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0RREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B20_76" }, "PSS2.PSS2_IMUX_B20_78->PS7_SAXIGP0AWQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B20_78" }, "PSS2.PSS2_IMUX_B20_82->PS7_SAXIGP1ARQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B20_82" }, "PSS2.PSS2_IMUX_B20_83->PS7_SAXIGP1ARSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B20_83" }, "PSS2.PSS2_IMUX_B20_84->PS7_SAXIGP1RREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1RREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B20_84" }, "PSS2.PSS2_IMUX_B20_86->PS7_SAXIGP1AWQOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWQOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B20_86" }, "PSS2.PSS2_IMUX_B21_75->PS7_SAXIGP0ARSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B21_75" }, "PSS2.PSS2_IMUX_B21_78->PS7_SAXIGP0AWQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B21_78" }, "PSS2.PSS2_IMUX_B21_83->PS7_SAXIGP1ARSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B21_83" }, "PSS2.PSS2_IMUX_B21_86->PS7_SAXIGP1AWQOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWQOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B21_86" }, "PSS2.PSS2_IMUX_B22_78->PS7_SAXIGP0AWQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B22_78" }, "PSS2.PSS2_IMUX_B22_86->PS7_SAXIGP1AWQOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWQOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B22_86" }, "PSS2.PSS2_IMUX_B2_60->PS7_EMIOGPIOI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_60" }, "PSS2.PSS2_IMUX_B2_61->PS7_EMIOGPIOI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_61" }, "PSS2.PSS2_IMUX_B2_62->PS7_EMIOGPIOI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_62" }, "PSS2.PSS2_IMUX_B2_63->PS7_EMIOGPIOI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_63" }, "PSS2.PSS2_IMUX_B2_64->PS7_EMIOGPIOI18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_64" }, "PSS2.PSS2_IMUX_B2_65->PS7_EMIOGPIOI22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_65" }, "PSS2.PSS2_IMUX_B2_66->PS7_EMIOGPIOI24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_66" }, "PSS2.PSS2_IMUX_B2_67->PS7_EMIOENET0GMIIRXD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIIRXD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_67" }, "PSS2.PSS2_IMUX_B2_68->PS7_EMIOENET0GMIIRXD4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIIRXD4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_68" }, "PSS2.PSS2_IMUX_B2_69->PS7_EMIOGPIOI38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_69" }, "PSS2.PSS2_IMUX_B2_70->PS7_EMIOGPIOI40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_70" }, "PSS2.PSS2_IMUX_B2_71->PS7_EMIOENET1GMIIRXD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIIRXD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_71" }, "PSS2.PSS2_IMUX_B2_72->PS7_EMIOENET1GMIIRXD4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIIRXD4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_72" }, "PSS2.PSS2_IMUX_B2_73->PS7_SAXIGP0AWADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_73" }, "PSS2.PSS2_IMUX_B2_74->PS7_SAXIGP0AWADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_74" }, "PSS2.PSS2_IMUX_B2_75->PS7_SAXIGP0AWADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_75" }, "PSS2.PSS2_IMUX_B2_76->PS7_SAXIGP0AWADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_76" }, "PSS2.PSS2_IMUX_B2_77->PS7_SAXIGP0AWADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_77" }, "PSS2.PSS2_IMUX_B2_78->PS7_SAXIGP0AWADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_78" }, "PSS2.PSS2_IMUX_B2_79->PS7_SAXIGP0AWADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_79" }, "PSS2.PSS2_IMUX_B2_80->PS7_SAXIGP0AWID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_80" }, "PSS2.PSS2_IMUX_B2_81->PS7_SAXIGP1AWADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_81" }, "PSS2.PSS2_IMUX_B2_82->PS7_SAXIGP1AWADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_82" }, "PSS2.PSS2_IMUX_B2_83->PS7_SAXIGP1AWADDR10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_83" }, "PSS2.PSS2_IMUX_B2_84->PS7_SAXIGP1AWADDR14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_84" }, "PSS2.PSS2_IMUX_B2_85->PS7_SAXIGP1AWADDR18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_85" }, "PSS2.PSS2_IMUX_B2_86->PS7_SAXIGP1AWADDR22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_86" }, "PSS2.PSS2_IMUX_B2_87->PS7_SAXIGP1AWADDR24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_87" }, "PSS2.PSS2_IMUX_B2_88->PS7_SAXIGP1AWID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_88" }, "PSS2.PSS2_IMUX_B2_89->PS7_EMIOTTC0CLKI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOTTC0CLKI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_89" }, "PSS2.PSS2_IMUX_B2_90->PS7_EMIOTTC1CLKI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOTTC1CLKI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_90" }, "PSS2.PSS2_IMUX_B2_93->PS7_EMIOSDIO0DATAI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO0DATAI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_93" }, "PSS2.PSS2_IMUX_B2_94->PS7_EMIOSDIO0CMDI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO0CMDI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_94" }, "PSS2.PSS2_IMUX_B2_97->PS7_EMIOSDIO1DATAI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO1DATAI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_97" }, "PSS2.PSS2_IMUX_B2_98->PS7_EMIOSDIO1CMDI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO1CMDI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B2_98" }, "PSS2.PSS2_IMUX_B3_60->PS7_EMIOGPIOI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_60" }, "PSS2.PSS2_IMUX_B3_61->PS7_EMIOGPIOI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_61" }, "PSS2.PSS2_IMUX_B3_62->PS7_EMIOGPIOI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_62" }, "PSS2.PSS2_IMUX_B3_63->PS7_EMIOGPIOI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_63" }, "PSS2.PSS2_IMUX_B3_64->PS7_EMIOGPIOI19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_64" }, "PSS2.PSS2_IMUX_B3_65->PS7_EMIOGPIOI23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_65" }, "PSS2.PSS2_IMUX_B3_66->PS7_EMIOGPIOI25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_66" }, "PSS2.PSS2_IMUX_B3_67->PS7_EMIOENET0GMIIRXD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIIRXD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_67" }, "PSS2.PSS2_IMUX_B3_68->PS7_EMIOENET0GMIIRXD5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIIRXD5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_68" }, "PSS2.PSS2_IMUX_B3_69->PS7_EMIOGPIOI39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_69" }, "PSS2.PSS2_IMUX_B3_70->PS7_EMIOGPIOI41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_70" }, "PSS2.PSS2_IMUX_B3_71->PS7_EMIOENET1GMIIRXD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIIRXD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_71" }, "PSS2.PSS2_IMUX_B3_72->PS7_EMIOENET1GMIIRXD5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIIRXD5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_72" }, "PSS2.PSS2_IMUX_B3_73->PS7_SAXIGP0AWADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_73" }, "PSS2.PSS2_IMUX_B3_74->PS7_SAXIGP0AWADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_74" }, "PSS2.PSS2_IMUX_B3_75->PS7_SAXIGP0AWADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_75" }, "PSS2.PSS2_IMUX_B3_76->PS7_SAXIGP0AWADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_76" }, "PSS2.PSS2_IMUX_B3_77->PS7_SAXIGP0AWADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_77" }, "PSS2.PSS2_IMUX_B3_78->PS7_SAXIGP0AWADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_78" }, "PSS2.PSS2_IMUX_B3_79->PS7_SAXIGP0AWADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_79" }, "PSS2.PSS2_IMUX_B3_80->PS7_SAXIGP0AWID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_80" }, "PSS2.PSS2_IMUX_B3_81->PS7_SAXIGP1AWADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_81" }, "PSS2.PSS2_IMUX_B3_82->PS7_SAXIGP1AWADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_82" }, "PSS2.PSS2_IMUX_B3_83->PS7_SAXIGP1AWADDR11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_83" }, "PSS2.PSS2_IMUX_B3_84->PS7_SAXIGP1AWADDR15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_84" }, "PSS2.PSS2_IMUX_B3_85->PS7_SAXIGP1AWADDR19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_85" }, "PSS2.PSS2_IMUX_B3_86->PS7_SAXIGP1AWADDR23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_86" }, "PSS2.PSS2_IMUX_B3_87->PS7_SAXIGP1AWADDR25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_87" }, "PSS2.PSS2_IMUX_B3_88->PS7_SAXIGP1AWID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_88" }, "PSS2.PSS2_IMUX_B3_89->PS7_EMIOWDTCLKI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOWDTCLKI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_89" }, "PSS2.PSS2_IMUX_B3_90->PS7_EMIOI2C1SCLI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOI2C1SCLI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_90" }, "PSS2.PSS2_IMUX_B3_93->PS7_EMIOSDIO0DATAI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO0DATAI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_93" }, "PSS2.PSS2_IMUX_B3_94->PS7_EMIOSDIO0CDN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO0CDN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_94" }, "PSS2.PSS2_IMUX_B3_97->PS7_EMIOSDIO1DATAI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO1DATAI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_97" }, "PSS2.PSS2_IMUX_B3_98->PS7_EMIOSDIO1CDN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO1CDN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B3_98" }, "PSS2.PSS2_IMUX_B4_60->PS7_FTMDTRACEINDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_60" }, "PSS2.PSS2_IMUX_B4_61->PS7_FTMDTRACEINDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_61" }, "PSS2.PSS2_IMUX_B4_62->PS7_FCLKCLKTRIGN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FCLKCLKTRIGN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_62" }, "PSS2.PSS2_IMUX_B4_63->PS7_FTMDTRACEINDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_63" }, "PSS2.PSS2_IMUX_B4_64->PS7_EVENTEVENTI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EVENTEVENTI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_64" }, "PSS2.PSS2_IMUX_B4_65->PS7_FTMDTRACEINDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_65" }, "PSS2.PSS2_IMUX_B4_66->PS7_EMIOGPIOI26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_66" }, "PSS2.PSS2_IMUX_B4_67->PS7_EMIOGPIOI28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_67" }, "PSS2.PSS2_IMUX_B4_68->PS7_EMIOENET0GMIIRXD6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIIRXD6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_68" }, "PSS2.PSS2_IMUX_B4_69->PS7_FTMDTRACEINDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_69" }, "PSS2.PSS2_IMUX_B4_70->PS7_EMIOGPIOI42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_70" }, "PSS2.PSS2_IMUX_B4_71->PS7_EMIOGPIOI48": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI48", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_71" }, "PSS2.PSS2_IMUX_B4_72->PS7_EMIOENET1GMIIRXD6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIIRXD6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_72" }, "PSS2.PSS2_IMUX_B4_73->PS7_SAXIGP0WDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_73" }, "PSS2.PSS2_IMUX_B4_74->PS7_SAXIGP0WDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_74" }, "PSS2.PSS2_IMUX_B4_75->PS7_SAXIGP0WDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_75" }, "PSS2.PSS2_IMUX_B4_76->PS7_SAXIGP0AWPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_76" }, "PSS2.PSS2_IMUX_B4_77->PS7_SAXIGP0AWCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_77" }, "PSS2.PSS2_IMUX_B4_78->PS7_SAXIGP0AWBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_78" }, "PSS2.PSS2_IMUX_B4_79->PS7_SAXIGP0AWADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_79" }, "PSS2.PSS2_IMUX_B4_80->PS7_SAXIGP0AWADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_80" }, "PSS2.PSS2_IMUX_B4_81->PS7_SAXIGP1WDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_81" }, "PSS2.PSS2_IMUX_B4_82->PS7_SAXIGP1WDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_82" }, "PSS2.PSS2_IMUX_B4_83->PS7_SAXIGP1WDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_83" }, "PSS2.PSS2_IMUX_B4_84->PS7_SAXIGP1AWPROT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWPROT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_84" }, "PSS2.PSS2_IMUX_B4_85->PS7_SAXIGP1AWCACHE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWCACHE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_85" }, "PSS2.PSS2_IMUX_B4_86->PS7_SAXIGP1AWBURST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWBURST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_86" }, "PSS2.PSS2_IMUX_B4_87->PS7_SAXIGP1AWADDR26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_87" }, "PSS2.PSS2_IMUX_B4_88->PS7_SAXIGP1AWADDR28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_88" }, "PSS2.PSS2_IMUX_B4_89->PS7_EMIOI2C0SCLI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOI2C0SCLI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_89" }, "PSS2.PSS2_IMUX_B4_90->PS7_EMIOI2C1SDAI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOI2C1SDAI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_90" }, "PSS2.PSS2_IMUX_B4_93->PS7_EMIOSDIO0DATAI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO0DATAI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_93" }, "PSS2.PSS2_IMUX_B4_94->PS7_EMIOSDIO0WP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO0WP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_94" }, "PSS2.PSS2_IMUX_B4_97->PS7_EMIOSDIO1DATAI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO1DATAI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_97" }, "PSS2.PSS2_IMUX_B4_98->PS7_EMIOSDIO1WP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO1WP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B4_98" }, "PSS2.PSS2_IMUX_B5_60->PS7_FTMDTRACEINDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_60" }, "PSS2.PSS2_IMUX_B5_61->PS7_FTMDTRACEINDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_61" }, "PSS2.PSS2_IMUX_B5_62->PS7_FCLKCLKTRIGN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FCLKCLKTRIGN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_62" }, "PSS2.PSS2_IMUX_B5_63->PS7_FTMDTRACEINDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_63" }, "PSS2.PSS2_IMUX_B5_64->PS7_FTMDTRACEINDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_64" }, "PSS2.PSS2_IMUX_B5_65->PS7_FTMDTRACEINDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_65" }, "PSS2.PSS2_IMUX_B5_66->PS7_EMIOGPIOI27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_66" }, "PSS2.PSS2_IMUX_B5_67->PS7_EMIOGPIOI29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_67" }, "PSS2.PSS2_IMUX_B5_68->PS7_EMIOENET0GMIIRXD7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIIRXD7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_68" }, "PSS2.PSS2_IMUX_B5_69->PS7_FTMDTRACEINDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_69" }, "PSS2.PSS2_IMUX_B5_70->PS7_EMIOGPIOI43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_70" }, "PSS2.PSS2_IMUX_B5_71->PS7_EMIOGPIOI49": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI49", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_71" }, "PSS2.PSS2_IMUX_B5_72->PS7_EMIOENET1GMIIRXD7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIIRXD7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_72" }, "PSS2.PSS2_IMUX_B5_73->PS7_SAXIGP0WDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_73" }, "PSS2.PSS2_IMUX_B5_74->PS7_SAXIGP0WDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_74" }, "PSS2.PSS2_IMUX_B5_75->PS7_SAXIGP0WDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_75" }, "PSS2.PSS2_IMUX_B5_76->PS7_SAXIGP0AWPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_76" }, "PSS2.PSS2_IMUX_B5_77->PS7_SAXIGP0AWCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_77" }, "PSS2.PSS2_IMUX_B5_78->PS7_SAXIGP0AWBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_78" }, "PSS2.PSS2_IMUX_B5_79->PS7_SAXIGP0AWADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_79" }, "PSS2.PSS2_IMUX_B5_80->PS7_SAXIGP0AWADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_80" }, "PSS2.PSS2_IMUX_B5_81->PS7_SAXIGP1WDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_81" }, "PSS2.PSS2_IMUX_B5_82->PS7_SAXIGP1WDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_82" }, "PSS2.PSS2_IMUX_B5_83->PS7_SAXIGP1WDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_83" }, "PSS2.PSS2_IMUX_B5_84->PS7_SAXIGP1AWPROT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWPROT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_84" }, "PSS2.PSS2_IMUX_B5_85->PS7_SAXIGP1AWCACHE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWCACHE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_85" }, "PSS2.PSS2_IMUX_B5_86->PS7_SAXIGP1AWBURST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWBURST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_86" }, "PSS2.PSS2_IMUX_B5_87->PS7_SAXIGP1AWADDR27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_87" }, "PSS2.PSS2_IMUX_B5_88->PS7_SAXIGP1AWADDR29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_88" }, "PSS2.PSS2_IMUX_B5_89->PS7_EMIOI2C0SDAI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOI2C0SDAI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_89" }, "PSS2.PSS2_IMUX_B5_90->PS7_EMIOCAN1PHYRX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOCAN1PHYRX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_90" }, "PSS2.PSS2_IMUX_B5_93->PS7_EMIOSDIO0DATAI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO0DATAI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_93" }, "PSS2.PSS2_IMUX_B5_94->PS7_EMIOUSB1VBUSPWRFAULT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOUSB1VBUSPWRFAULT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_94" }, "PSS2.PSS2_IMUX_B5_97->PS7_EMIOSDIO1DATAI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOSDIO1DATAI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_97" }, "PSS2.PSS2_IMUX_B5_98->PS7_EMIOUSB0VBUSPWRFAULT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOUSB0VBUSPWRFAULT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B5_98" }, "PSS2.PSS2_IMUX_B6_60->PS7_FTMDTRACEINDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_60" }, "PSS2.PSS2_IMUX_B6_61->PS7_FTMDTRACEINDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_61" }, "PSS2.PSS2_IMUX_B6_62->PS7_FTMDTRACEINDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_62" }, "PSS2.PSS2_IMUX_B6_63->PS7_FTMDTRACEINDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_63" }, "PSS2.PSS2_IMUX_B6_64->PS7_FTMDTRACEINDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_64" }, "PSS2.PSS2_IMUX_B6_65->PS7_FTMDTRACEINDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_65" }, "PSS2.PSS2_IMUX_B6_66->PS7_FTMTP2FTRIGACK3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTP2FTRIGACK3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_66" }, "PSS2.PSS2_IMUX_B6_67->PS7_EMIOGPIOI30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_67" }, "PSS2.PSS2_IMUX_B6_68->PS7_EMIOENET0GMIIRXER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIIRXER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_68" }, "PSS2.PSS2_IMUX_B6_69->PS7_FTMDTRACEINDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_69" }, "PSS2.PSS2_IMUX_B6_70->PS7_EMIOGPIOI44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_70" }, "PSS2.PSS2_IMUX_B6_71->PS7_EMIOGPIOI50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_71" }, "PSS2.PSS2_IMUX_B6_72->PS7_EMIOENET1GMIIRXER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIIRXER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_72" }, "PSS2.PSS2_IMUX_B6_73->PS7_SAXIGP0WDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_73" }, "PSS2.PSS2_IMUX_B6_74->PS7_SAXIGP0WDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_74" }, "PSS2.PSS2_IMUX_B6_75->PS7_SAXIGP0WDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_75" }, "PSS2.PSS2_IMUX_B6_76->PS7_SAXIGP0AWPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_76" }, "PSS2.PSS2_IMUX_B6_77->PS7_SAXIGP0AWVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_77" }, "PSS2.PSS2_IMUX_B6_78->PS7_SAXIGP0AWLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_78" }, "PSS2.PSS2_IMUX_B6_79->PS7_SAXIGP0AWSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_79" }, "PSS2.PSS2_IMUX_B6_80->PS7_SAXIGP0AWADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_80" }, "PSS2.PSS2_IMUX_B6_81->PS7_SAXIGP1WDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_81" }, "PSS2.PSS2_IMUX_B6_82->PS7_SAXIGP1WDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_82" }, "PSS2.PSS2_IMUX_B6_83->PS7_SAXIGP1WDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_83" }, "PSS2.PSS2_IMUX_B6_84->PS7_SAXIGP1AWPROT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWPROT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_84" }, "PSS2.PSS2_IMUX_B6_85->PS7_SAXIGP1AWVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_85" }, "PSS2.PSS2_IMUX_B6_86->PS7_SAXIGP1AWLOCK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWLOCK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_86" }, "PSS2.PSS2_IMUX_B6_87->PS7_SAXIGP1AWSIZE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWSIZE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_87" }, "PSS2.PSS2_IMUX_B6_88->PS7_SAXIGP1AWADDR30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_88" }, "PSS2.PSS2_IMUX_B6_89->PS7_EMIOCAN0PHYRX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOCAN0PHYRX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_89" }, "PSS2.PSS2_IMUX_B6_90->PS7_EMIOUART0RX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOUART0RX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B6_90" }, "PSS2.PSS2_IMUX_B7_60->PS7_FTMDTRACEINDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_60" }, "PSS2.PSS2_IMUX_B7_61->PS7_FTMDTRACEINDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_61" }, "PSS2.PSS2_IMUX_B7_62->PS7_FTMDTRACEINDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_62" }, "PSS2.PSS2_IMUX_B7_63->PS7_FTMDTRACEINDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_63" }, "PSS2.PSS2_IMUX_B7_64->PS7_FTMDTRACEINDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_64" }, "PSS2.PSS2_IMUX_B7_65->PS7_FTMDTRACEINDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_65" }, "PSS2.PSS2_IMUX_B7_66->PS7_FTMTF2PDEBUG24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_66" }, "PSS2.PSS2_IMUX_B7_67->PS7_EMIOGPIOI31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_67" }, "PSS2.PSS2_IMUX_B7_68->PS7_EMIOENET0GMIIRXDV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET0GMIIRXDV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_68" }, "PSS2.PSS2_IMUX_B7_69->PS7_FTMDTRACEINDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_69" }, "PSS2.PSS2_IMUX_B7_70->PS7_EMIOGPIOI45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_70" }, "PSS2.PSS2_IMUX_B7_71->PS7_EMIOGPIOI51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_71" }, "PSS2.PSS2_IMUX_B7_72->PS7_EMIOENET1GMIIRXDV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOENET1GMIIRXDV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_72" }, "PSS2.PSS2_IMUX_B7_73->PS7_SAXIGP0WDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_73" }, "PSS2.PSS2_IMUX_B7_74->PS7_SAXIGP0WDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_74" }, "PSS2.PSS2_IMUX_B7_75->PS7_SAXIGP0WDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_75" }, "PSS2.PSS2_IMUX_B7_76->PS7_SAXIGP0WID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_76" }, "PSS2.PSS2_IMUX_B7_77->PS7_SAXIGP0WID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_77" }, "PSS2.PSS2_IMUX_B7_78->PS7_SAXIGP0AWLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_78" }, "PSS2.PSS2_IMUX_B7_79->PS7_SAXIGP0AWSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_79" }, "PSS2.PSS2_IMUX_B7_80->PS7_SAXIGP0AWADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_80" }, "PSS2.PSS2_IMUX_B7_81->PS7_SAXIGP1WDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_81" }, "PSS2.PSS2_IMUX_B7_82->PS7_SAXIGP1WDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_82" }, "PSS2.PSS2_IMUX_B7_83->PS7_SAXIGP1WDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_83" }, "PSS2.PSS2_IMUX_B7_84->PS7_SAXIGP1WID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_84" }, "PSS2.PSS2_IMUX_B7_85->PS7_SAXIGP1WID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_85" }, "PSS2.PSS2_IMUX_B7_86->PS7_SAXIGP1AWLOCK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWLOCK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_86" }, "PSS2.PSS2_IMUX_B7_87->PS7_SAXIGP1AWSIZE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWSIZE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_87" }, "PSS2.PSS2_IMUX_B7_88->PS7_SAXIGP1AWADDR31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWADDR31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_88" }, "PSS2.PSS2_IMUX_B7_89->PS7_EMIOUART1RX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOUART1RX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_89" }, "PSS2.PSS2_IMUX_B7_90->PS7_EMIOUART0CTSN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOUART0CTSN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B7_90" }, "PSS2.PSS2_IMUX_B8_60->PS7_FTMDTRACEINATID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINATID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_60" }, "PSS2.PSS2_IMUX_B8_61->PS7_FTMDTRACEINVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_61" }, "PSS2.PSS2_IMUX_B8_62->PS7_FTMDTRACEINDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_62" }, "PSS2.PSS2_IMUX_B8_63->PS7_FTMTF2PTRIG1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PTRIG1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_63" }, "PSS2.PSS2_IMUX_B8_64->PS7_FTMDTRACEINDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_64" }, "PSS2.PSS2_IMUX_B8_65->PS7_FTMTF2PTRIG2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PTRIG2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_65" }, "PSS2.PSS2_IMUX_B8_66->PS7_FTMTF2PDEBUG25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_66" }, "PSS2.PSS2_IMUX_B8_67->PS7_FTMTF2PTRIG3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PTRIG3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_67" }, "PSS2.PSS2_IMUX_B8_68->PS7_EMIOGPIOI32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_68" }, "PSS2.PSS2_IMUX_B8_70->PS7_EMIOGPIOI46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_70" }, "PSS2.PSS2_IMUX_B8_71->PS7_EMIOGPIOI52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_71" }, "PSS2.PSS2_IMUX_B8_72->PS7_EMIOGPIOI56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_72" }, "PSS2.PSS2_IMUX_B8_73->PS7_SAXIGP0ARADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_73" }, "PSS2.PSS2_IMUX_B8_74->PS7_SAXIGP0WLAST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WLAST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_74" }, "PSS2.PSS2_IMUX_B8_75->PS7_SAXIGP0ARID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_75" }, "PSS2.PSS2_IMUX_B8_76->PS7_SAXIGP0WID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_76" }, "PSS2.PSS2_IMUX_B8_77->PS7_SAXIGP0WID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_77" }, "PSS2.PSS2_IMUX_B8_78->PS7_SAXIGP0AWCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_78" }, "PSS2.PSS2_IMUX_B8_79->PS7_SAXIGP0WDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_79" }, "PSS2.PSS2_IMUX_B8_80->PS7_SAXIGP0AWLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_80" }, "PSS2.PSS2_IMUX_B8_81->PS7_SAXIGP1ARADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_81" }, "PSS2.PSS2_IMUX_B8_82->PS7_SAXIGP1WLAST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WLAST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_82" }, "PSS2.PSS2_IMUX_B8_83->PS7_SAXIGP1ARID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_83" }, "PSS2.PSS2_IMUX_B8_84->PS7_SAXIGP1WID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_84" }, "PSS2.PSS2_IMUX_B8_85->PS7_SAXIGP1WID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_85" }, "PSS2.PSS2_IMUX_B8_86->PS7_SAXIGP1AWCACHE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWCACHE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_86" }, "PSS2.PSS2_IMUX_B8_87->PS7_SAXIGP1WDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_87" }, "PSS2.PSS2_IMUX_B8_88->PS7_SAXIGP1AWLEN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWLEN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_88" }, "PSS2.PSS2_IMUX_B8_89->PS7_EMIOUART1CTSN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOUART1CTSN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_89" }, "PSS2.PSS2_IMUX_B8_90->PS7_EMIOUART0DSRN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOUART0DSRN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B8_90" }, "PSS2.PSS2_IMUX_B9_60->PS7_FTMDTRACEINATID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINATID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_60" }, "PSS2.PSS2_IMUX_B9_61->PS7_FTMTF2PTRIG0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PTRIG0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_61" }, "PSS2.PSS2_IMUX_B9_62->PS7_FTMDTRACEINDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMDTRACEINDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_62" }, "PSS2.PSS2_IMUX_B9_63->PS7_FTMTF2PDEBUG12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_63" }, "PSS2.PSS2_IMUX_B9_64->PS7_FTMTP2FTRIGACK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTP2FTRIGACK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_64" }, "PSS2.PSS2_IMUX_B9_65->PS7_FTMTF2PDEBUG20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_65" }, "PSS2.PSS2_IMUX_B9_66->PS7_FTMTF2PDEBUG26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_66" }, "PSS2.PSS2_IMUX_B9_67->PS7_FTMTF2PDEBUG28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FTMTF2PDEBUG28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_67" }, "PSS2.PSS2_IMUX_B9_68->PS7_EMIOGPIOI33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_68" }, "PSS2.PSS2_IMUX_B9_70->PS7_EMIOGPIOI47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_70" }, "PSS2.PSS2_IMUX_B9_71->PS7_EMIOGPIOI53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_71" }, "PSS2.PSS2_IMUX_B9_72->PS7_EMIOGPIOI57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOGPIOI57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_72" }, "PSS2.PSS2_IMUX_B9_73->PS7_SAXIGP0ARADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_73" }, "PSS2.PSS2_IMUX_B9_74->PS7_SAXIGP0ARADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_74" }, "PSS2.PSS2_IMUX_B9_75->PS7_SAXIGP0ARID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0ARID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_75" }, "PSS2.PSS2_IMUX_B9_76->PS7_SAXIGP0WDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_76" }, "PSS2.PSS2_IMUX_B9_77->PS7_SAXIGP0WID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_77" }, "PSS2.PSS2_IMUX_B9_78->PS7_SAXIGP0AWCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_78" }, "PSS2.PSS2_IMUX_B9_79->PS7_SAXIGP0WDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0WDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_79" }, "PSS2.PSS2_IMUX_B9_80->PS7_SAXIGP0AWLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP0AWLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_80" }, "PSS2.PSS2_IMUX_B9_81->PS7_SAXIGP1ARADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_81" }, "PSS2.PSS2_IMUX_B9_82->PS7_SAXIGP1ARADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_82" }, "PSS2.PSS2_IMUX_B9_83->PS7_SAXIGP1ARID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1ARID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_83" }, "PSS2.PSS2_IMUX_B9_84->PS7_SAXIGP1WDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_84" }, "PSS2.PSS2_IMUX_B9_85->PS7_SAXIGP1WID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_85" }, "PSS2.PSS2_IMUX_B9_86->PS7_SAXIGP1AWCACHE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWCACHE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_86" }, "PSS2.PSS2_IMUX_B9_87->PS7_SAXIGP1WDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1WDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_87" }, "PSS2.PSS2_IMUX_B9_88->PS7_SAXIGP1AWLEN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_SAXIGP1AWLEN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_88" }, "PSS2.PSS2_IMUX_B9_89->PS7_EMIOUART1DSRN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOUART1DSRN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_89" }, "PSS2.PSS2_IMUX_B9_90->PS7_EMIOUART0DCDN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_EMIOUART0DCDN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS2_IMUX_B9_90" }, "PSS2.PSS_CLK_B0_15->PS7_MAXIGP1ACLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1ACLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_15" }, "PSS2.PSS_CLK_B0_5->PS7_MAXIGP0ACLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0ACLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_5" }, "PSS2.PSS_IMUX_B0_0->PS7_DMA0DRTYPE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA0DRTYPE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_0" }, "PSS2.PSS_IMUX_B0_1->PS7_DMA1DRTYPE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA1DRTYPE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_1" }, "PSS2.PSS_IMUX_B0_10->PS7_IRQF2P10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_10" }, "PSS2.PSS_IMUX_B0_11->PS7_IRQF2P12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_11" }, "PSS2.PSS_IMUX_B0_12->PS7_IRQF2P14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_12" }, "PSS2.PSS_IMUX_B0_13->PS7_IRQF2P16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_13" }, "PSS2.PSS_IMUX_B0_14->PS7_IRQF2P18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_14" }, "PSS2.PSS_IMUX_B0_15->PS7_MAXIGP1AWREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1AWREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_15" }, "PSS2.PSS_IMUX_B0_16->PS7_MAXIGP1BVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_16" }, "PSS2.PSS_IMUX_B0_17->PS7_MAXIGP1BID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_17" }, "PSS2.PSS_IMUX_B0_18->PS7_MAXIGP1BID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_18" }, "PSS2.PSS_IMUX_B0_19->PS7_MAXIGP1BID8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BID8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_19" }, "PSS2.PSS_IMUX_B0_2->PS7_DMA2DRTYPE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA2DRTYPE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_2" }, "PSS2.PSS_IMUX_B0_3->PS7_DMA3DRTYPE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA3DRTYPE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_3" }, "PSS2.PSS_IMUX_B0_4->PS7_MAXIGP0RID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_4" }, "PSS2.PSS_IMUX_B0_5->PS7_IRQF2P0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_5" }, "PSS2.PSS_IMUX_B0_6->PS7_IRQF2P2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_6" }, "PSS2.PSS_IMUX_B0_7->PS7_IRQF2P4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_7" }, "PSS2.PSS_IMUX_B0_8->PS7_IRQF2P6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_8" }, "PSS2.PSS_IMUX_B0_9->PS7_IRQF2P8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_9" }, "PSS2.PSS_IMUX_B10_14->PS7_MAXIGP1RVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_14" }, "PSS2.PSS_IMUX_B10_7->PS7_MAXIGP0RDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_7" }, "PSS2.PSS_IMUX_B10_8->PS7_MAXIGP0RID9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RID9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_8" }, "PSS2.PSS_IMUX_B11_7->PS7_MAXIGP0RDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_7" }, "PSS2.PSS_IMUX_B1_0->PS7_DMA0DRTYPE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA0DRTYPE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_0" }, "PSS2.PSS_IMUX_B1_1->PS7_DMA1DRTYPE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA1DRTYPE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_1" }, "PSS2.PSS_IMUX_B1_10->PS7_IRQF2P11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_10" }, "PSS2.PSS_IMUX_B1_11->PS7_IRQF2P13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_11" }, "PSS2.PSS_IMUX_B1_12->PS7_IRQF2P15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_12" }, "PSS2.PSS_IMUX_B1_13->PS7_IRQF2P17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_13" }, "PSS2.PSS_IMUX_B1_14->PS7_IRQF2P19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_14" }, "PSS2.PSS_IMUX_B1_15->PS7_MAXIGP1WREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1WREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_15" }, "PSS2.PSS_IMUX_B1_16->PS7_MAXIGP1RID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_16" }, "PSS2.PSS_IMUX_B1_17->PS7_MAXIGP1BID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_17" }, "PSS2.PSS_IMUX_B1_18->PS7_MAXIGP1BID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_18" }, "PSS2.PSS_IMUX_B1_19->PS7_MAXIGP1BID9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BID9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_19" }, "PSS2.PSS_IMUX_B1_2->PS7_DMA2DRTYPE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA2DRTYPE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_2" }, "PSS2.PSS_IMUX_B1_3->PS7_DMA3DRTYPE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA3DRTYPE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_3" }, "PSS2.PSS_IMUX_B1_4->PS7_MAXIGP0RID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_4" }, "PSS2.PSS_IMUX_B1_5->PS7_IRQF2P1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_5" }, "PSS2.PSS_IMUX_B1_6->PS7_IRQF2P3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_6" }, "PSS2.PSS_IMUX_B1_7->PS7_IRQF2P5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_7" }, "PSS2.PSS_IMUX_B1_8->PS7_IRQF2P7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_8" }, "PSS2.PSS_IMUX_B1_9->PS7_IRQF2P9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_IRQF2P9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_9" }, "PSS2.PSS_IMUX_B2_0->PS7_DMA0DRVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA0DRVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_0" }, "PSS2.PSS_IMUX_B2_1->PS7_DMA1DRVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA1DRVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_1" }, "PSS2.PSS_IMUX_B2_10->PS7_DDRARB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DDRARB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_10" }, "PSS2.PSS_IMUX_B2_11->PS7_MAXIGP1RDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_11" }, "PSS2.PSS_IMUX_B2_12->PS7_MAXIGP1RDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_12" }, "PSS2.PSS_IMUX_B2_13->PS7_MAXIGP1RDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_13" }, "PSS2.PSS_IMUX_B2_14->PS7_MAXIGP1RID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_14" }, "PSS2.PSS_IMUX_B2_15->PS7_MAXIGP1ARREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1ARREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_15" }, "PSS2.PSS_IMUX_B2_16->PS7_MAXIGP1RID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_16" }, "PSS2.PSS_IMUX_B2_17->PS7_MAXIGP1BID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_17" }, "PSS2.PSS_IMUX_B2_18->PS7_MAXIGP1BID6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BID6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_18" }, "PSS2.PSS_IMUX_B2_19->PS7_MAXIGP1BID10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BID10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_19" }, "PSS2.PSS_IMUX_B2_2->PS7_DMA2DRVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA2DRVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_2" }, "PSS2.PSS_IMUX_B2_3->PS7_DMA3DRVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DMA3DRVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_3" }, "PSS2.PSS_IMUX_B2_4->PS7_MAXIGP0RDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_4" }, "PSS2.PSS_IMUX_B2_5->PS7_MAXIGP0AWREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0AWREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_5" }, "PSS2.PSS_IMUX_B2_6->PS7_MAXIGP0BVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_6" }, "PSS2.PSS_IMUX_B2_7->PS7_MAXIGP0BID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_7" }, "PSS2.PSS_IMUX_B2_8->PS7_MAXIGP0BID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_8" }, "PSS2.PSS_IMUX_B2_9->PS7_MAXIGP0BID8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BID8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_9" }, "PSS2.PSS_IMUX_B3_0->PS7_FCLKCLKTRIGN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FCLKCLKTRIGN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_0" }, "PSS2.PSS_IMUX_B3_1->PS7_MAXIGP0RDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_1" }, "PSS2.PSS_IMUX_B3_10->PS7_DDRARB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DDRARB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_10" }, "PSS2.PSS_IMUX_B3_11->PS7_MAXIGP1RDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_11" }, "PSS2.PSS_IMUX_B3_12->PS7_MAXIGP1RDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_12" }, "PSS2.PSS_IMUX_B3_13->PS7_MAXIGP1RDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_13" }, "PSS2.PSS_IMUX_B3_14->PS7_MAXIGP1RID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_14" }, "PSS2.PSS_IMUX_B3_15->PS7_MAXIGP1RDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_15" }, "PSS2.PSS_IMUX_B3_16->PS7_MAXIGP1RDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_16" }, "PSS2.PSS_IMUX_B3_17->PS7_MAXIGP1BID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_17" }, "PSS2.PSS_IMUX_B3_18->PS7_MAXIGP1BID7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BID7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_18" }, "PSS2.PSS_IMUX_B3_19->PS7_MAXIGP1BID11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BID11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_19" }, "PSS2.PSS_IMUX_B3_2->PS7_MAXIGP0RDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_2" }, "PSS2.PSS_IMUX_B3_3->PS7_MAXIGP0RDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_3" }, "PSS2.PSS_IMUX_B3_4->PS7_MAXIGP0RDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_4" }, "PSS2.PSS_IMUX_B3_5->PS7_MAXIGP0WREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0WREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_5" }, "PSS2.PSS_IMUX_B3_6->PS7_MAXIGP0RID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_6" }, "PSS2.PSS_IMUX_B3_7->PS7_MAXIGP0BID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_7" }, "PSS2.PSS_IMUX_B3_8->PS7_MAXIGP0BID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_8" }, "PSS2.PSS_IMUX_B3_9->PS7_MAXIGP0BID9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BID9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_9" }, "PSS2.PSS_IMUX_B4_0->PS7_FCLKCLKTRIGN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_FCLKCLKTRIGN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_0" }, "PSS2.PSS_IMUX_B4_1->PS7_MAXIGP0RDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_1" }, "PSS2.PSS_IMUX_B4_10->PS7_DDRARB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DDRARB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_10" }, "PSS2.PSS_IMUX_B4_11->PS7_MAXIGP1RDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_11" }, "PSS2.PSS_IMUX_B4_12->PS7_MAXIGP1RDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_12" }, "PSS2.PSS_IMUX_B4_13->PS7_MAXIGP1RDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_13" }, "PSS2.PSS_IMUX_B4_14->PS7_MAXIGP1RDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_14" }, "PSS2.PSS_IMUX_B4_15->PS7_MAXIGP1RDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_15" }, "PSS2.PSS_IMUX_B4_16->PS7_MAXIGP1RDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_16" }, "PSS2.PSS_IMUX_B4_17->PS7_MAXIGP1RID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_17" }, "PSS2.PSS_IMUX_B4_18->PS7_MAXIGP1BRESP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BRESP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_18" }, "PSS2.PSS_IMUX_B4_19->PS7_MAXIGP1BRESP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1BRESP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_19" }, "PSS2.PSS_IMUX_B4_2->PS7_MAXIGP0RDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_2" }, "PSS2.PSS_IMUX_B4_3->PS7_MAXIGP0RDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_3" }, "PSS2.PSS_IMUX_B4_4->PS7_MAXIGP0RDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_4" }, "PSS2.PSS_IMUX_B4_5->PS7_MAXIGP0ARREADY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0ARREADY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_5" }, "PSS2.PSS_IMUX_B4_6->PS7_MAXIGP0RID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_6" }, "PSS2.PSS_IMUX_B4_7->PS7_MAXIGP0BID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_7" }, "PSS2.PSS_IMUX_B4_8->PS7_MAXIGP0BID6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BID6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_8" }, "PSS2.PSS_IMUX_B4_9->PS7_MAXIGP0BID10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BID10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_9" }, "PSS2.PSS_IMUX_B5_0->PS7_MAXIGP0RDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_0" }, "PSS2.PSS_IMUX_B5_1->PS7_MAXIGP0RDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_1" }, "PSS2.PSS_IMUX_B5_10->PS7_DDRARB3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_DDRARB3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_10" }, "PSS2.PSS_IMUX_B5_11->PS7_MAXIGP1RDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_11" }, "PSS2.PSS_IMUX_B5_12->PS7_MAXIGP1RDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_12" }, "PSS2.PSS_IMUX_B5_13->PS7_MAXIGP1RDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_13" }, "PSS2.PSS_IMUX_B5_14->PS7_MAXIGP1RDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_14" }, "PSS2.PSS_IMUX_B5_15->PS7_MAXIGP1RDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_15" }, "PSS2.PSS_IMUX_B5_16->PS7_MAXIGP1RDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_16" }, "PSS2.PSS_IMUX_B5_17->PS7_MAXIGP1RID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_17" }, "PSS2.PSS_IMUX_B5_18->PS7_MAXIGP1RID6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RID6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_18" }, "PSS2.PSS_IMUX_B5_19->PS7_MAXIGP1RID10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RID10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_19" }, "PSS2.PSS_IMUX_B5_2->PS7_MAXIGP0RDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_2" }, "PSS2.PSS_IMUX_B5_3->PS7_MAXIGP0RDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_3" }, "PSS2.PSS_IMUX_B5_4->PS7_MAXIGP0RDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_4" }, "PSS2.PSS_IMUX_B5_5->PS7_MAXIGP0RDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_5" }, "PSS2.PSS_IMUX_B5_6->PS7_MAXIGP0RDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_6" }, "PSS2.PSS_IMUX_B5_7->PS7_MAXIGP0BID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_7" }, "PSS2.PSS_IMUX_B5_8->PS7_MAXIGP0BID7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BID7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_8" }, "PSS2.PSS_IMUX_B5_9->PS7_MAXIGP0BID11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BID11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_9" }, "PSS2.PSS_IMUX_B6_0->PS7_MAXIGP0RDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_0" }, "PSS2.PSS_IMUX_B6_1->PS7_MAXIGP0RDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_1" }, "PSS2.PSS_IMUX_B6_10->PS7_MAXIGP1RDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_10" }, "PSS2.PSS_IMUX_B6_13->PS7_MAXIGP1RLAST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RLAST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_13" }, "PSS2.PSS_IMUX_B6_14->PS7_MAXIGP1RDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_14" }, "PSS2.PSS_IMUX_B6_15->PS7_MAXIGP1RDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_15" }, "PSS2.PSS_IMUX_B6_16->PS7_MAXIGP1RDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_16" }, "PSS2.PSS_IMUX_B6_17->PS7_MAXIGP1RDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_17" }, "PSS2.PSS_IMUX_B6_18->PS7_MAXIGP1RID7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RID7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_18" }, "PSS2.PSS_IMUX_B6_19->PS7_MAXIGP1RID11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RID11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_19" }, "PSS2.PSS_IMUX_B6_2->PS7_MAXIGP0RDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_2" }, "PSS2.PSS_IMUX_B6_3->PS7_MAXIGP0RDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_3" }, "PSS2.PSS_IMUX_B6_4->PS7_MAXIGP0RRESP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RRESP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_4" }, "PSS2.PSS_IMUX_B6_5->PS7_MAXIGP0RDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_5" }, "PSS2.PSS_IMUX_B6_6->PS7_MAXIGP0RDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_6" }, "PSS2.PSS_IMUX_B6_7->PS7_MAXIGP0RID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_7" }, "PSS2.PSS_IMUX_B6_8->PS7_MAXIGP0BRESP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BRESP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_8" }, "PSS2.PSS_IMUX_B6_9->PS7_MAXIGP0BRESP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0BRESP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_9" }, "PSS2.PSS_IMUX_B7_0->PS7_MAXIGP0RDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_0" }, "PSS2.PSS_IMUX_B7_10->PS7_MAXIGP1RDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_10" }, "PSS2.PSS_IMUX_B7_14->PS7_MAXIGP1RDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_14" }, "PSS2.PSS_IMUX_B7_17->PS7_MAXIGP1RDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_17" }, "PSS2.PSS_IMUX_B7_18->PS7_MAXIGP1RID8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RID8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_18" }, "PSS2.PSS_IMUX_B7_3->PS7_MAXIGP0RLAST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RLAST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_3" }, "PSS2.PSS_IMUX_B7_4->PS7_MAXIGP0RRESP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RRESP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_4" }, "PSS2.PSS_IMUX_B7_5->PS7_MAXIGP0RDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_5" }, "PSS2.PSS_IMUX_B7_6->PS7_MAXIGP0RDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_6" }, "PSS2.PSS_IMUX_B7_7->PS7_MAXIGP0RID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_7" }, "PSS2.PSS_IMUX_B7_8->PS7_MAXIGP0RID6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RID6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_8" }, "PSS2.PSS_IMUX_B7_9->PS7_MAXIGP0RID10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RID10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_9" }, "PSS2.PSS_IMUX_B8_0->PS7_MAXIGP0RDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_0" }, "PSS2.PSS_IMUX_B8_10->PS7_MAXIGP1RDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_10" }, "PSS2.PSS_IMUX_B8_14->PS7_MAXIGP1RRESP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RRESP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_14" }, "PSS2.PSS_IMUX_B8_17->PS7_MAXIGP1RDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_17" }, "PSS2.PSS_IMUX_B8_18->PS7_MAXIGP1RID9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RID9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_18" }, "PSS2.PSS_IMUX_B8_4->PS7_MAXIGP0RVALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RVALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_4" }, "PSS2.PSS_IMUX_B8_5->PS7_MAXIGP0RDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_5" }, "PSS2.PSS_IMUX_B8_6->PS7_MAXIGP0RDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_6" }, "PSS2.PSS_IMUX_B8_7->PS7_MAXIGP0RDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_7" }, "PSS2.PSS_IMUX_B8_8->PS7_MAXIGP0RID7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RID7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_8" }, "PSS2.PSS_IMUX_B8_9->PS7_MAXIGP0RID11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RID11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_9" }, "PSS2.PSS_IMUX_B9_10->PS7_MAXIGP1RDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_10" }, "PSS2.PSS_IMUX_B9_14->PS7_MAXIGP1RRESP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RRESP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_14" }, "PSS2.PSS_IMUX_B9_17->PS7_MAXIGP1RDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP1RDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_17" }, "PSS2.PSS_IMUX_B9_7->PS7_MAXIGP0RDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_7" }, "PSS2.PSS_IMUX_B9_8->PS7_MAXIGP0RID8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PS7_MAXIGP0RID8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_8" } }, @@ -23211,7 +60976,16 @@ "name": "X0Y0", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRWEB" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRWEB" + } }, "type": "IOPAD", "x_coord": 0, @@ -23221,7 +60995,16 @@ "name": "X0Y1", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRVRN" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRVRN" + } }, "type": "IOPAD", "x_coord": 0, @@ -23231,7 +61014,16 @@ "name": "X0Y2", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRVRP" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRVRP" + } }, "type": "IOPAD", "x_coord": 0, @@ -23241,7 +61033,16 @@ "name": "X0Y3", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA0" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA0" + } }, "type": "IOPAD", "x_coord": 0, @@ -23251,7 +61052,16 @@ "name": "X0Y4", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA1" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA1" + } }, "type": "IOPAD", "x_coord": 0, @@ -23261,7 +61071,16 @@ "name": "X0Y5", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA2" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA2" + } }, "type": "IOPAD", "x_coord": 0, @@ -23271,7 +61090,16 @@ "name": "X0Y6", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA3" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA3" + } }, "type": "IOPAD", "x_coord": 0, @@ -23281,7 +61109,16 @@ "name": "X0Y7", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA4" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA4" + } }, "type": "IOPAD", "x_coord": 0, @@ -23291,7 +61128,16 @@ "name": "X0Y8", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA5" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA5" + } }, "type": "IOPAD", "x_coord": 0, @@ -23301,7 +61147,16 @@ "name": "X0Y9", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA6" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA6" + } }, "type": "IOPAD", "x_coord": 0, @@ -23311,7 +61166,16 @@ "name": "X0Y10", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA7" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA7" + } }, "type": "IOPAD", "x_coord": 0, @@ -23321,7 +61185,16 @@ "name": "X0Y11", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA8" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA8" + } }, "type": "IOPAD", "x_coord": 0, @@ -23331,7 +61204,16 @@ "name": "X0Y12", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA9" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA9" + } }, "type": "IOPAD", "x_coord": 0, @@ -23341,7 +61223,16 @@ "name": "X0Y13", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA10" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA10" + } }, "type": "IOPAD", "x_coord": 0, @@ -23351,7 +61242,16 @@ "name": "X0Y14", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA11" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA11" + } }, "type": "IOPAD", "x_coord": 0, @@ -23361,7 +61261,16 @@ "name": "X0Y15", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA12" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA12" + } }, "type": "IOPAD", "x_coord": 0, @@ -23371,7 +61280,16 @@ "name": "X0Y16", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA14" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA14" + } }, "type": "IOPAD", "x_coord": 0, @@ -23381,7 +61299,16 @@ "name": "X0Y17", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRA13" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRA13" + } }, "type": "IOPAD", "x_coord": 0, @@ -23391,7 +61318,16 @@ "name": "X0Y18", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRBA0" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRBA0" + } }, "type": "IOPAD", "x_coord": 0, @@ -23401,7 +61337,16 @@ "name": "X0Y19", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRBA1" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRBA1" + } }, "type": "IOPAD", "x_coord": 0, @@ -23411,7 +61356,16 @@ "name": "X0Y20", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRBA2" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRBA2" + } }, "type": "IOPAD", "x_coord": 0, @@ -23421,7 +61375,16 @@ "name": "X0Y21", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRCASB" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRCASB" + } }, "type": "IOPAD", "x_coord": 0, @@ -23431,7 +61394,16 @@ "name": "X0Y22", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRCKE" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRCKE" + } }, "type": "IOPAD", "x_coord": 0, @@ -23441,7 +61413,16 @@ "name": "X0Y23", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRCKN" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRCKN" + } }, "type": "IOPAD", "x_coord": 0, @@ -23451,7 +61432,16 @@ "name": "X0Y24", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRCKP" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRCKP" + } }, "type": "IOPAD", "x_coord": 0, @@ -23461,7 +61451,16 @@ "name": "X0Y25", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_PSCLK" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_PSCLK" + } }, "type": "IOPAD", "x_coord": 0, @@ -23471,7 +61470,16 @@ "name": "X0Y26", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRCSB" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRCSB" + } }, "type": "IOPAD", "x_coord": 0, @@ -23481,7 +61489,16 @@ "name": "X0Y27", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDM0" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDM0" + } }, "type": "IOPAD", "x_coord": 0, @@ -23491,7 +61508,16 @@ "name": "X0Y28", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDM1" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDM1" + } }, "type": "IOPAD", "x_coord": 0, @@ -23501,7 +61527,16 @@ "name": "X0Y29", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDM2" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDM2" + } }, "type": "IOPAD", "x_coord": 0, @@ -23511,7 +61546,16 @@ "name": "X0Y30", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDM3" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDM3" + } }, "type": "IOPAD", "x_coord": 0, @@ -23521,7 +61565,16 @@ "name": "X0Y31", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ0" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ0" + } }, "type": "IOPAD", "x_coord": 0, @@ -23531,7 +61584,16 @@ "name": "X0Y32", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ1" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ1" + } }, "type": "IOPAD", "x_coord": 0, @@ -23541,7 +61603,16 @@ "name": "X0Y33", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ2" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ2" + } }, "type": "IOPAD", "x_coord": 0, @@ -23551,7 +61622,16 @@ "name": "X0Y34", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ3" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ3" + } }, "type": "IOPAD", "x_coord": 0, @@ -23561,7 +61641,16 @@ "name": "X0Y35", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ4" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ4" + } }, "type": "IOPAD", "x_coord": 0, @@ -23571,7 +61660,16 @@ "name": "X0Y36", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ5" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ5" + } }, "type": "IOPAD", "x_coord": 0, @@ -23581,7 +61679,16 @@ "name": "X0Y37", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ6" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ6" + } }, "type": "IOPAD", "x_coord": 0, @@ -23591,7 +61698,16 @@ "name": "X0Y38", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ7" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ7" + } }, "type": "IOPAD", "x_coord": 0, @@ -23601,7 +61717,16 @@ "name": "X0Y39", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ8" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ8" + } }, "type": "IOPAD", "x_coord": 0, @@ -23611,7 +61736,16 @@ "name": "X0Y40", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ9" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ9" + } }, "type": "IOPAD", "x_coord": 0, @@ -23621,7 +61755,16 @@ "name": "X0Y41", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ10" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ10" + } }, "type": "IOPAD", "x_coord": 0, @@ -23631,7 +61774,16 @@ "name": "X0Y42", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ11" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ11" + } }, "type": "IOPAD", "x_coord": 0, @@ -23641,7 +61793,16 @@ "name": "X0Y43", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ12" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ12" + } }, "type": "IOPAD", "x_coord": 0, @@ -23651,7 +61812,16 @@ "name": "X0Y44", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ13" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ13" + } }, "type": "IOPAD", "x_coord": 0, @@ -23661,7 +61831,16 @@ "name": "X0Y45", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ14" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ14" + } }, "type": "IOPAD", "x_coord": 0, @@ -23671,7 +61850,16 @@ "name": "X0Y46", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ15" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ15" + } }, "type": "IOPAD", "x_coord": 0, @@ -23681,7 +61869,16 @@ "name": "X0Y47", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ16" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ16" + } }, "type": "IOPAD", "x_coord": 0, @@ -23691,7 +61888,16 @@ "name": "X0Y48", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ17" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ17" + } }, "type": "IOPAD", "x_coord": 0, @@ -23701,7 +61907,16 @@ "name": "X0Y49", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ18" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ18" + } }, "type": "IOPAD", "x_coord": 0, @@ -23711,7 +61926,16 @@ "name": "X0Y50", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ19" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ19" + } }, "type": "IOPAD", "x_coord": 0, @@ -23721,7 +61945,16 @@ "name": "X0Y51", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ20" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ20" + } }, "type": "IOPAD", "x_coord": 0, @@ -23731,7 +61964,16 @@ "name": "X0Y52", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ21" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ21" + } }, "type": "IOPAD", "x_coord": 0, @@ -23741,7 +61983,16 @@ "name": "X0Y53", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ22" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ22" + } }, "type": "IOPAD", "x_coord": 0, @@ -23751,7 +62002,16 @@ "name": "X0Y54", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ23" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ23" + } }, "type": "IOPAD", "x_coord": 0, @@ -23761,7 +62021,16 @@ "name": "X0Y55", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ24" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ24" + } }, "type": "IOPAD", "x_coord": 0, @@ -23771,7 +62040,16 @@ "name": "X0Y56", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ25" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ25" + } }, "type": "IOPAD", "x_coord": 0, @@ -23781,7 +62059,16 @@ "name": "X0Y57", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ26" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ26" + } }, "type": "IOPAD", "x_coord": 0, @@ -23791,7 +62078,16 @@ "name": "X0Y58", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ27" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ27" + } }, "type": "IOPAD", "x_coord": 0, @@ -23801,7 +62097,16 @@ "name": "X0Y59", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ28" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ28" + } }, "type": "IOPAD", "x_coord": 0, @@ -23811,7 +62116,16 @@ "name": "X0Y60", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ29" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ29" + } }, "type": "IOPAD", "x_coord": 0, @@ -23821,7 +62135,16 @@ "name": "X0Y61", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ30" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ30" + } }, "type": "IOPAD", "x_coord": 0, @@ -23831,7 +62154,16 @@ "name": "X0Y62", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQ31" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQ31" + } }, "type": "IOPAD", "x_coord": 0, @@ -23841,7 +62173,16 @@ "name": "X0Y63", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQSN0" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQSN0" + } }, "type": "IOPAD", "x_coord": 0, @@ -23851,7 +62192,16 @@ "name": "X0Y64", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQSN1" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQSN1" + } }, "type": "IOPAD", "x_coord": 0, @@ -23861,7 +62211,16 @@ "name": "X0Y65", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQSN2" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQSN2" + } }, "type": "IOPAD", "x_coord": 0, @@ -23871,7 +62230,16 @@ "name": "X0Y66", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQSN3" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQSN3" + } }, "type": "IOPAD", "x_coord": 0, @@ -23881,7 +62249,16 @@ "name": "X0Y67", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQSP0" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQSP0" + } }, "type": "IOPAD", "x_coord": 0, @@ -23891,7 +62268,16 @@ "name": "X0Y68", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQSP1" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQSP1" + } }, "type": "IOPAD", "x_coord": 0, @@ -23901,7 +62287,16 @@ "name": "X0Y69", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQSP2" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQSP2" + } }, "type": "IOPAD", "x_coord": 0, @@ -23911,7 +62306,16 @@ "name": "X0Y70", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDQSP3" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDQSP3" + } }, "type": "IOPAD", "x_coord": 0, @@ -23921,7 +62325,16 @@ "name": "X0Y71", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRDRSTB" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRDRSTB" + } }, "type": "IOPAD", "x_coord": 0, @@ -23931,7 +62344,16 @@ "name": "X0Y76", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO0" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO0" + } }, "type": "IOPAD", "x_coord": 0, @@ -23941,7 +62363,16 @@ "name": "X0Y77", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO1" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO1" + } }, "type": "IOPAD", "x_coord": 0, @@ -23951,7 +62382,16 @@ "name": "X0Y78", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO2" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO2" + } }, "type": "IOPAD", "x_coord": 0, @@ -23961,7 +62401,16 @@ "name": "X0Y79", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO3" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO3" + } }, "type": "IOPAD", "x_coord": 0, @@ -23971,7 +62420,16 @@ "name": "X0Y80", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO4" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO4" + } }, "type": "IOPAD", "x_coord": 0, @@ -23981,7 +62439,16 @@ "name": "X0Y81", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO5" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO5" + } }, "type": "IOPAD", "x_coord": 0, @@ -23991,7 +62458,16 @@ "name": "X0Y82", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO6" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO6" + } }, "type": "IOPAD", "x_coord": 0, @@ -24001,7 +62477,16 @@ "name": "X0Y83", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO7" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO7" + } }, "type": "IOPAD", "x_coord": 0, @@ -24011,7 +62496,16 @@ "name": "X0Y84", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO8" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO8" + } }, "type": "IOPAD", "x_coord": 0, @@ -24021,7 +62515,16 @@ "name": "X0Y85", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO9" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO9" + } }, "type": "IOPAD", "x_coord": 0, @@ -24031,7 +62534,16 @@ "name": "X0Y86", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO10" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO10" + } }, "type": "IOPAD", "x_coord": 0, @@ -24041,7 +62553,16 @@ "name": "X0Y87", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO11" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO11" + } }, "type": "IOPAD", "x_coord": 0, @@ -24051,7 +62572,16 @@ "name": "X0Y88", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO12" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO12" + } }, "type": "IOPAD", "x_coord": 0, @@ -24061,7 +62591,16 @@ "name": "X0Y89", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO13" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO13" + } }, "type": "IOPAD", "x_coord": 0, @@ -24071,7 +62610,16 @@ "name": "X0Y90", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO14" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO14" + } }, "type": "IOPAD", "x_coord": 0, @@ -24081,7 +62629,16 @@ "name": "X0Y91", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO15" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO15" + } }, "type": "IOPAD", "x_coord": 0, @@ -24091,7 +62648,16 @@ "name": "X0Y92", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO16" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO16" + } }, "type": "IOPAD", "x_coord": 0, @@ -24101,7 +62667,16 @@ "name": "X0Y93", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO17" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO17" + } }, "type": "IOPAD", "x_coord": 0, @@ -24111,7 +62686,16 @@ "name": "X0Y94", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO18" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO18" + } }, "type": "IOPAD", "x_coord": 0, @@ -24121,7 +62705,16 @@ "name": "X0Y95", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO19" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO19" + } }, "type": "IOPAD", "x_coord": 0, @@ -24131,7 +62724,16 @@ "name": "X0Y96", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO20" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO20" + } }, "type": "IOPAD", "x_coord": 0, @@ -24141,7 +62743,16 @@ "name": "X0Y97", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO21" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO21" + } }, "type": "IOPAD", "x_coord": 0, @@ -24151,7 +62762,16 @@ "name": "X0Y98", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO22" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO22" + } }, "type": "IOPAD", "x_coord": 0, @@ -24161,7 +62781,16 @@ "name": "X0Y99", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO23" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO23" + } }, "type": "IOPAD", "x_coord": 0, @@ -24171,7 +62800,16 @@ "name": "X0Y100", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO24" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO24" + } }, "type": "IOPAD", "x_coord": 0, @@ -24181,7 +62819,16 @@ "name": "X0Y101", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO25" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO25" + } }, "type": "IOPAD", "x_coord": 0, @@ -24191,7 +62838,16 @@ "name": "X0Y102", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO26" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO26" + } }, "type": "IOPAD", "x_coord": 0, @@ -24201,7 +62857,16 @@ "name": "X0Y103", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO27" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO27" + } }, "type": "IOPAD", "x_coord": 0, @@ -24211,7 +62876,16 @@ "name": "X0Y104", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO28" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO28" + } }, "type": "IOPAD", "x_coord": 0, @@ -24221,7 +62895,16 @@ "name": "X0Y105", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO29" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO29" + } }, "type": "IOPAD", "x_coord": 0, @@ -24231,7 +62914,16 @@ "name": "X0Y106", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO30" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO30" + } }, "type": "IOPAD", "x_coord": 0, @@ -24241,7 +62933,16 @@ "name": "X0Y107", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO31" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO31" + } }, "type": "IOPAD", "x_coord": 0, @@ -24251,7 +62952,16 @@ "name": "X0Y108", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO32" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO32" + } }, "type": "IOPAD", "x_coord": 0, @@ -24261,7 +62971,16 @@ "name": "X0Y109", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO33" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO33" + } }, "type": "IOPAD", "x_coord": 0, @@ -24271,7 +62990,16 @@ "name": "X0Y110", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO34" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO34" + } }, "type": "IOPAD", "x_coord": 0, @@ -24281,7 +63009,16 @@ "name": "X0Y111", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO35" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO35" + } }, "type": "IOPAD", "x_coord": 0, @@ -24291,7 +63028,16 @@ "name": "X0Y112", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO36" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO36" + } }, "type": "IOPAD", "x_coord": 0, @@ -24301,7 +63047,16 @@ "name": "X0Y113", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO37" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO37" + } }, "type": "IOPAD", "x_coord": 0, @@ -24311,7 +63066,16 @@ "name": "X0Y114", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO38" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO38" + } }, "type": "IOPAD", "x_coord": 0, @@ -24321,7 +63085,16 @@ "name": "X0Y115", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO39" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO39" + } }, "type": "IOPAD", "x_coord": 0, @@ -24331,7 +63104,16 @@ "name": "X0Y116", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO40" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO40" + } }, "type": "IOPAD", "x_coord": 0, @@ -24341,7 +63123,16 @@ "name": "X0Y117", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO41" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO41" + } }, "type": "IOPAD", "x_coord": 0, @@ -24351,7 +63142,16 @@ "name": "X0Y118", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO42" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO42" + } }, "type": "IOPAD", "x_coord": 0, @@ -24361,7 +63161,16 @@ "name": "X0Y119", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO43" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO43" + } }, "type": "IOPAD", "x_coord": 0, @@ -24371,7 +63180,16 @@ "name": "X0Y120", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO44" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO44" + } }, "type": "IOPAD", "x_coord": 0, @@ -24381,7 +63199,16 @@ "name": "X0Y121", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO45" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO45" + } }, "type": "IOPAD", "x_coord": 0, @@ -24391,7 +63218,16 @@ "name": "X0Y122", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO46" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO46" + } }, "type": "IOPAD", "x_coord": 0, @@ -24401,7 +63237,16 @@ "name": "X0Y123", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO47" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO47" + } }, "type": "IOPAD", "x_coord": 0, @@ -24411,7 +63256,16 @@ "name": "X0Y124", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO48" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO48" + } }, "type": "IOPAD", "x_coord": 0, @@ -24421,7 +63275,16 @@ "name": "X0Y125", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO49" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO49" + } }, "type": "IOPAD", "x_coord": 0, @@ -24431,7 +63294,16 @@ "name": "X0Y126", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO50" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO50" + } }, "type": "IOPAD", "x_coord": 0, @@ -24441,7 +63313,16 @@ "name": "X0Y127", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO51" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO51" + } }, "type": "IOPAD", "x_coord": 0, @@ -24451,7 +63332,16 @@ "name": "X0Y128", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO52" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO52" + } }, "type": "IOPAD", "x_coord": 0, @@ -24461,7 +63351,16 @@ "name": "X0Y129", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_MIO53" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_MIO53" + } }, "type": "IOPAD", "x_coord": 0, @@ -24471,7 +63370,16 @@ "name": "X0Y130", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRODT" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRODT" + } }, "type": "IOPAD", "x_coord": 0, @@ -24481,7 +63389,16 @@ "name": "X0Y131", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_PSPORB" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_PSPORB" + } }, "type": "IOPAD", "x_coord": 0, @@ -24491,7 +63408,16 @@ "name": "X0Y132", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_DDRRASB" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_DDRRASB" + } }, "type": "IOPAD", "x_coord": 0, @@ -24501,7 +63427,16 @@ "name": "X0Y133", "prefix": "IOPAD", "site_pins": { - "IO": "PS72_PSSRSTB" + "IO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "PS72_PSSRSTB" + } }, "type": "IOPAD", "x_coord": 0, @@ -24511,3714 +63446,37086 @@ "name": "X0Y0", "prefix": "PS7", "site_pins": { - "DDRA0": "PS7_DDRA0", - "DDRA1": "PS7_DDRA1", - "DDRA10": "PS7_DDRA10", - "DDRA11": "PS7_DDRA11", - "DDRA12": "PS7_DDRA12", - "DDRA13": "PS7_DDRA13", - "DDRA14": "PS7_DDRA14", - "DDRA2": "PS7_DDRA2", - "DDRA3": "PS7_DDRA3", - "DDRA4": "PS7_DDRA4", - "DDRA5": "PS7_DDRA5", - "DDRA6": "PS7_DDRA6", - "DDRA7": "PS7_DDRA7", - "DDRA8": "PS7_DDRA8", - "DDRA9": "PS7_DDRA9", - "DDRARB0": "PS7_DDRARB0", - "DDRARB1": "PS7_DDRARB1", - "DDRARB2": "PS7_DDRARB2", - "DDRARB3": "PS7_DDRARB3", - "DDRBA0": "PS7_DDRBA0", - "DDRBA1": "PS7_DDRBA1", - "DDRBA2": "PS7_DDRBA2", - "DDRCASB": "PS7_DDRCASB", - "DDRCKE": "PS7_DDRCKE", - "DDRCKN": "PS7_DDRCKN", - "DDRCKP": "PS7_DDRCKP", - "DDRCSB": "PS7_DDRCSB", - "DDRDM0": "PS7_DDRDM0", - "DDRDM1": "PS7_DDRDM1", - "DDRDM2": "PS7_DDRDM2", - "DDRDM3": "PS7_DDRDM3", - "DDRDQ0": "PS7_DDRDQ0", - "DDRDQ1": "PS7_DDRDQ1", - "DDRDQ10": "PS7_DDRDQ10", - "DDRDQ11": "PS7_DDRDQ11", - "DDRDQ12": "PS7_DDRDQ12", - "DDRDQ13": "PS7_DDRDQ13", - "DDRDQ14": "PS7_DDRDQ14", - "DDRDQ15": "PS7_DDRDQ15", - "DDRDQ16": "PS7_DDRDQ16", - "DDRDQ17": "PS7_DDRDQ17", - "DDRDQ18": "PS7_DDRDQ18", - "DDRDQ19": "PS7_DDRDQ19", - "DDRDQ2": "PS7_DDRDQ2", - "DDRDQ20": "PS7_DDRDQ20", - "DDRDQ21": "PS7_DDRDQ21", - "DDRDQ22": "PS7_DDRDQ22", - "DDRDQ23": "PS7_DDRDQ23", - "DDRDQ24": "PS7_DDRDQ24", - "DDRDQ25": "PS7_DDRDQ25", - "DDRDQ26": "PS7_DDRDQ26", - "DDRDQ27": "PS7_DDRDQ27", - "DDRDQ28": "PS7_DDRDQ28", - "DDRDQ29": "PS7_DDRDQ29", - "DDRDQ3": "PS7_DDRDQ3", - "DDRDQ30": "PS7_DDRDQ30", - "DDRDQ31": "PS7_DDRDQ31", - "DDRDQ4": "PS7_DDRDQ4", - "DDRDQ5": "PS7_DDRDQ5", - "DDRDQ6": "PS7_DDRDQ6", - "DDRDQ7": "PS7_DDRDQ7", - "DDRDQ8": "PS7_DDRDQ8", - "DDRDQ9": "PS7_DDRDQ9", - "DDRDQSN0": "PS7_DDRDQSN0", - "DDRDQSN1": "PS7_DDRDQSN1", - "DDRDQSN2": "PS7_DDRDQSN2", - "DDRDQSN3": "PS7_DDRDQSN3", - "DDRDQSP0": "PS7_DDRDQSP0", - "DDRDQSP1": "PS7_DDRDQSP1", - "DDRDQSP2": "PS7_DDRDQSP2", - "DDRDQSP3": "PS7_DDRDQSP3", - "DDRDRSTB": "PS7_DDRDRSTB", - "DDRODT": "PS7_DDRODT", - "DDRRASB": "PS7_DDRRASB", - "DDRVRN": "PS7_DDRVRN", - "DDRVRP": "PS7_DDRVRP", - "DDRWEB": "PS7_DDRWEB", - "DEBUGDATA0": "PS7_DEBUGDATA0", - "DEBUGDATA1": "PS7_DEBUGDATA1", - "DEBUGDATA10": "PS7_DEBUGDATA10", - "DEBUGDATA100": "PS7_DEBUGDATA100", - "DEBUGDATA101": "PS7_DEBUGDATA101", - "DEBUGDATA102": "PS7_DEBUGDATA102", - "DEBUGDATA103": "PS7_DEBUGDATA103", - "DEBUGDATA104": "PS7_DEBUGDATA104", - "DEBUGDATA105": "PS7_DEBUGDATA105", - "DEBUGDATA106": "PS7_DEBUGDATA106", - "DEBUGDATA107": "PS7_DEBUGDATA107", - "DEBUGDATA108": "PS7_DEBUGDATA108", - "DEBUGDATA109": "PS7_DEBUGDATA109", - "DEBUGDATA11": "PS7_DEBUGDATA11", - "DEBUGDATA110": "PS7_DEBUGDATA110", - "DEBUGDATA111": "PS7_DEBUGDATA111", - "DEBUGDATA112": "PS7_DEBUGDATA112", - "DEBUGDATA113": "PS7_DEBUGDATA113", - "DEBUGDATA114": "PS7_DEBUGDATA114", - "DEBUGDATA115": "PS7_DEBUGDATA115", - "DEBUGDATA116": "PS7_DEBUGDATA116", - "DEBUGDATA117": "PS7_DEBUGDATA117", - "DEBUGDATA118": "PS7_DEBUGDATA118", - "DEBUGDATA119": "PS7_DEBUGDATA119", - "DEBUGDATA12": "PS7_DEBUGDATA12", - "DEBUGDATA120": "PS7_DEBUGDATA120", - "DEBUGDATA121": "PS7_DEBUGDATA121", - "DEBUGDATA122": "PS7_DEBUGDATA122", - "DEBUGDATA123": "PS7_DEBUGDATA123", - "DEBUGDATA124": "PS7_DEBUGDATA124", - "DEBUGDATA125": "PS7_DEBUGDATA125", - "DEBUGDATA126": "PS7_DEBUGDATA126", - "DEBUGDATA127": "PS7_DEBUGDATA127", - "DEBUGDATA128": "PS7_DEBUGDATA128", - "DEBUGDATA129": "PS7_DEBUGDATA129", - "DEBUGDATA13": "PS7_DEBUGDATA13", - "DEBUGDATA130": "PS7_DEBUGDATA130", - "DEBUGDATA131": "PS7_DEBUGDATA131", - "DEBUGDATA132": "PS7_DEBUGDATA132", - "DEBUGDATA133": "PS7_DEBUGDATA133", - "DEBUGDATA134": "PS7_DEBUGDATA134", - "DEBUGDATA135": "PS7_DEBUGDATA135", - "DEBUGDATA136": "PS7_DEBUGDATA136", - "DEBUGDATA137": "PS7_DEBUGDATA137", - "DEBUGDATA138": "PS7_DEBUGDATA138", - "DEBUGDATA139": "PS7_DEBUGDATA139", - "DEBUGDATA14": "PS7_DEBUGDATA14", - "DEBUGDATA140": "PS7_DEBUGDATA140", - "DEBUGDATA141": "PS7_DEBUGDATA141", - "DEBUGDATA142": "PS7_DEBUGDATA142", - "DEBUGDATA143": "PS7_DEBUGDATA143", - "DEBUGDATA144": "PS7_DEBUGDATA144", - "DEBUGDATA145": "PS7_DEBUGDATA145", - "DEBUGDATA146": "PS7_DEBUGDATA146", - "DEBUGDATA147": "PS7_DEBUGDATA147", - "DEBUGDATA148": "PS7_DEBUGDATA148", - "DEBUGDATA149": "PS7_DEBUGDATA149", - "DEBUGDATA15": "PS7_DEBUGDATA15", - "DEBUGDATA150": "PS7_DEBUGDATA150", - "DEBUGDATA151": "PS7_DEBUGDATA151", - "DEBUGDATA152": "PS7_DEBUGDATA152", - "DEBUGDATA153": "PS7_DEBUGDATA153", - "DEBUGDATA154": "PS7_DEBUGDATA154", - "DEBUGDATA155": "PS7_DEBUGDATA155", - "DEBUGDATA156": "PS7_DEBUGDATA156", - "DEBUGDATA157": "PS7_DEBUGDATA157", - "DEBUGDATA158": "PS7_DEBUGDATA158", - "DEBUGDATA159": "PS7_DEBUGDATA159", - "DEBUGDATA16": "PS7_DEBUGDATA16", - "DEBUGDATA160": "PS7_DEBUGDATA160", - "DEBUGDATA161": "PS7_DEBUGDATA161", - "DEBUGDATA162": "PS7_DEBUGDATA162", - "DEBUGDATA163": "PS7_DEBUGDATA163", - "DEBUGDATA164": "PS7_DEBUGDATA164", - "DEBUGDATA165": "PS7_DEBUGDATA165", - "DEBUGDATA166": "PS7_DEBUGDATA166", - "DEBUGDATA167": "PS7_DEBUGDATA167", - "DEBUGDATA168": "PS7_DEBUGDATA168", - "DEBUGDATA169": "PS7_DEBUGDATA169", - "DEBUGDATA17": "PS7_DEBUGDATA17", - "DEBUGDATA170": "PS7_DEBUGDATA170", - "DEBUGDATA171": "PS7_DEBUGDATA171", - "DEBUGDATA172": "PS7_DEBUGDATA172", - "DEBUGDATA173": "PS7_DEBUGDATA173", - "DEBUGDATA174": "PS7_DEBUGDATA174", - "DEBUGDATA175": "PS7_DEBUGDATA175", - "DEBUGDATA176": "PS7_DEBUGDATA176", - "DEBUGDATA177": "PS7_DEBUGDATA177", - "DEBUGDATA178": "PS7_DEBUGDATA178", - "DEBUGDATA179": "PS7_DEBUGDATA179", - "DEBUGDATA18": "PS7_DEBUGDATA18", - "DEBUGDATA180": "PS7_DEBUGDATA180", - "DEBUGDATA181": "PS7_DEBUGDATA181", - "DEBUGDATA182": "PS7_DEBUGDATA182", - "DEBUGDATA183": "PS7_DEBUGDATA183", - "DEBUGDATA184": "PS7_DEBUGDATA184", - "DEBUGDATA185": "PS7_DEBUGDATA185", - "DEBUGDATA186": "PS7_DEBUGDATA186", - "DEBUGDATA187": "PS7_DEBUGDATA187", - "DEBUGDATA188": "PS7_DEBUGDATA188", - "DEBUGDATA189": "PS7_DEBUGDATA189", - "DEBUGDATA19": "PS7_DEBUGDATA19", - "DEBUGDATA190": "PS7_DEBUGDATA190", - "DEBUGDATA191": "PS7_DEBUGDATA191", - "DEBUGDATA192": "PS7_DEBUGDATA192", - "DEBUGDATA193": "PS7_DEBUGDATA193", - "DEBUGDATA194": "PS7_DEBUGDATA194", - "DEBUGDATA195": "PS7_DEBUGDATA195", - "DEBUGDATA196": "PS7_DEBUGDATA196", - "DEBUGDATA197": "PS7_DEBUGDATA197", - "DEBUGDATA198": "PS7_DEBUGDATA198", - "DEBUGDATA199": "PS7_DEBUGDATA199", - "DEBUGDATA2": "PS7_DEBUGDATA2", - "DEBUGDATA20": "PS7_DEBUGDATA20", - "DEBUGDATA21": "PS7_DEBUGDATA21", - "DEBUGDATA22": "PS7_DEBUGDATA22", - "DEBUGDATA23": "PS7_DEBUGDATA23", - "DEBUGDATA24": "PS7_DEBUGDATA24", - "DEBUGDATA25": "PS7_DEBUGDATA25", - "DEBUGDATA26": "PS7_DEBUGDATA26", - "DEBUGDATA27": "PS7_DEBUGDATA27", - "DEBUGDATA28": "PS7_DEBUGDATA28", - "DEBUGDATA29": "PS7_DEBUGDATA29", - "DEBUGDATA3": "PS7_DEBUGDATA3", - "DEBUGDATA30": "PS7_DEBUGDATA30", - "DEBUGDATA31": "PS7_DEBUGDATA31", - "DEBUGDATA32": "PS7_DEBUGDATA32", - "DEBUGDATA33": "PS7_DEBUGDATA33", - "DEBUGDATA34": "PS7_DEBUGDATA34", - "DEBUGDATA35": "PS7_DEBUGDATA35", - "DEBUGDATA36": "PS7_DEBUGDATA36", - "DEBUGDATA37": "PS7_DEBUGDATA37", - "DEBUGDATA38": "PS7_DEBUGDATA38", - "DEBUGDATA39": "PS7_DEBUGDATA39", - "DEBUGDATA4": "PS7_DEBUGDATA4", - "DEBUGDATA40": "PS7_DEBUGDATA40", - "DEBUGDATA41": "PS7_DEBUGDATA41", - "DEBUGDATA42": "PS7_DEBUGDATA42", - "DEBUGDATA43": "PS7_DEBUGDATA43", - "DEBUGDATA44": "PS7_DEBUGDATA44", - "DEBUGDATA45": "PS7_DEBUGDATA45", - "DEBUGDATA46": "PS7_DEBUGDATA46", - "DEBUGDATA47": "PS7_DEBUGDATA47", - "DEBUGDATA48": "PS7_DEBUGDATA48", - "DEBUGDATA49": "PS7_DEBUGDATA49", - "DEBUGDATA5": "PS7_DEBUGDATA5", - "DEBUGDATA50": "PS7_DEBUGDATA50", - "DEBUGDATA51": "PS7_DEBUGDATA51", - "DEBUGDATA52": "PS7_DEBUGDATA52", - "DEBUGDATA53": "PS7_DEBUGDATA53", - "DEBUGDATA54": "PS7_DEBUGDATA54", - "DEBUGDATA55": "PS7_DEBUGDATA55", - "DEBUGDATA56": "PS7_DEBUGDATA56", - "DEBUGDATA57": "PS7_DEBUGDATA57", - "DEBUGDATA58": "PS7_DEBUGDATA58", - "DEBUGDATA59": "PS7_DEBUGDATA59", - "DEBUGDATA6": "PS7_DEBUGDATA6", - "DEBUGDATA60": "PS7_DEBUGDATA60", - "DEBUGDATA61": "PS7_DEBUGDATA61", - "DEBUGDATA62": "PS7_DEBUGDATA62", - "DEBUGDATA63": "PS7_DEBUGDATA63", - "DEBUGDATA64": "PS7_DEBUGDATA64", - "DEBUGDATA65": "PS7_DEBUGDATA65", - "DEBUGDATA66": "PS7_DEBUGDATA66", - "DEBUGDATA67": "PS7_DEBUGDATA67", - "DEBUGDATA68": "PS7_DEBUGDATA68", - "DEBUGDATA69": "PS7_DEBUGDATA69", - "DEBUGDATA7": "PS7_DEBUGDATA7", - "DEBUGDATA70": "PS7_DEBUGDATA70", - "DEBUGDATA71": "PS7_DEBUGDATA71", - "DEBUGDATA72": "PS7_DEBUGDATA72", - "DEBUGDATA73": "PS7_DEBUGDATA73", - "DEBUGDATA74": "PS7_DEBUGDATA74", - "DEBUGDATA75": "PS7_DEBUGDATA75", - "DEBUGDATA76": "PS7_DEBUGDATA76", - "DEBUGDATA77": "PS7_DEBUGDATA77", - "DEBUGDATA78": "PS7_DEBUGDATA78", - "DEBUGDATA79": "PS7_DEBUGDATA79", - "DEBUGDATA8": "PS7_DEBUGDATA8", - "DEBUGDATA80": "PS7_DEBUGDATA80", - "DEBUGDATA81": "PS7_DEBUGDATA81", - "DEBUGDATA82": "PS7_DEBUGDATA82", - "DEBUGDATA83": "PS7_DEBUGDATA83", - "DEBUGDATA84": "PS7_DEBUGDATA84", - "DEBUGDATA85": "PS7_DEBUGDATA85", - "DEBUGDATA86": "PS7_DEBUGDATA86", - "DEBUGDATA87": "PS7_DEBUGDATA87", - "DEBUGDATA88": "PS7_DEBUGDATA88", - "DEBUGDATA89": "PS7_DEBUGDATA89", - "DEBUGDATA9": "PS7_DEBUGDATA9", - "DEBUGDATA90": "PS7_DEBUGDATA90", - "DEBUGDATA91": "PS7_DEBUGDATA91", - "DEBUGDATA92": "PS7_DEBUGDATA92", - "DEBUGDATA93": "PS7_DEBUGDATA93", - "DEBUGDATA94": "PS7_DEBUGDATA94", - "DEBUGDATA95": "PS7_DEBUGDATA95", - "DEBUGDATA96": "PS7_DEBUGDATA96", - "DEBUGDATA97": "PS7_DEBUGDATA97", - "DEBUGDATA98": "PS7_DEBUGDATA98", - "DEBUGDATA99": "PS7_DEBUGDATA99", - "DEBUGSELECT0": "PS7_DEBUGSELECT0", - "DEBUGSELECT1": "PS7_DEBUGSELECT1", - "DEBUGSELECT10": "PS7_DEBUGSELECT10", - "DEBUGSELECT11": "PS7_DEBUGSELECT11", - "DEBUGSELECT12": "PS7_DEBUGSELECT12", - "DEBUGSELECT13": "PS7_DEBUGSELECT13", - "DEBUGSELECT14": "PS7_DEBUGSELECT14", - "DEBUGSELECT15": "PS7_DEBUGSELECT15", - "DEBUGSELECT2": "PS7_DEBUGSELECT2", - "DEBUGSELECT3": "PS7_DEBUGSELECT3", - "DEBUGSELECT4": "PS7_DEBUGSELECT4", - "DEBUGSELECT5": "PS7_DEBUGSELECT5", - "DEBUGSELECT6": "PS7_DEBUGSELECT6", - "DEBUGSELECT7": "PS7_DEBUGSELECT7", - "DEBUGSELECT8": "PS7_DEBUGSELECT8", - "DEBUGSELECT9": "PS7_DEBUGSELECT9", - "DMA0ACLK": "PS7_DMA0ACLK", - "DMA0DAREADY": "PS7_DMA0DAREADY", - "DMA0DATYPE0": "PS7_DMA0DATYPE0", - "DMA0DATYPE1": "PS7_DMA0DATYPE1", - "DMA0DAVALID": "PS7_DMA0DAVALID", - "DMA0DRLAST": "PS7_DMA0DRLAST", - "DMA0DRREADY": "PS7_DMA0DRREADY", - "DMA0DRTYPE0": "PS7_DMA0DRTYPE0", - "DMA0DRTYPE1": "PS7_DMA0DRTYPE1", - "DMA0DRVALID": "PS7_DMA0DRVALID", - "DMA0RSTN": "PS7_DMA0RSTN", - "DMA1ACLK": "PS7_DMA1ACLK", - "DMA1DAREADY": "PS7_DMA1DAREADY", - "DMA1DATYPE0": "PS7_DMA1DATYPE0", - "DMA1DATYPE1": "PS7_DMA1DATYPE1", - "DMA1DAVALID": "PS7_DMA1DAVALID", - "DMA1DRLAST": "PS7_DMA1DRLAST", - "DMA1DRREADY": "PS7_DMA1DRREADY", - "DMA1DRTYPE0": "PS7_DMA1DRTYPE0", - "DMA1DRTYPE1": "PS7_DMA1DRTYPE1", - "DMA1DRVALID": "PS7_DMA1DRVALID", - "DMA1RSTN": "PS7_DMA1RSTN", - "DMA2ACLK": "PS7_DMA2ACLK", - "DMA2DAREADY": "PS7_DMA2DAREADY", - "DMA2DATYPE0": "PS7_DMA2DATYPE0", - "DMA2DATYPE1": "PS7_DMA2DATYPE1", - "DMA2DAVALID": "PS7_DMA2DAVALID", - "DMA2DRLAST": "PS7_DMA2DRLAST", - "DMA2DRREADY": "PS7_DMA2DRREADY", - "DMA2DRTYPE0": "PS7_DMA2DRTYPE0", - "DMA2DRTYPE1": "PS7_DMA2DRTYPE1", - "DMA2DRVALID": "PS7_DMA2DRVALID", - "DMA2RSTN": "PS7_DMA2RSTN", - "DMA3ACLK": "PS7_DMA3ACLK", - "DMA3DAREADY": "PS7_DMA3DAREADY", - "DMA3DATYPE0": "PS7_DMA3DATYPE0", - "DMA3DATYPE1": "PS7_DMA3DATYPE1", - "DMA3DAVALID": "PS7_DMA3DAVALID", - "DMA3DRLAST": "PS7_DMA3DRLAST", - "DMA3DRREADY": "PS7_DMA3DRREADY", - "DMA3DRTYPE0": "PS7_DMA3DRTYPE0", - "DMA3DRTYPE1": "PS7_DMA3DRTYPE1", - "DMA3DRVALID": "PS7_DMA3DRVALID", - "DMA3RSTN": "PS7_DMA3RSTN", - "EMIOCAN0PHYRX": "PS7_EMIOCAN0PHYRX", - "EMIOCAN0PHYTX": "PS7_EMIOCAN0PHYTX", - "EMIOCAN1PHYRX": "PS7_EMIOCAN1PHYRX", - "EMIOCAN1PHYTX": "PS7_EMIOCAN1PHYTX", - "EMIOENET0EXTINTIN": "PS7_EMIOENET0EXTINTIN", - "EMIOENET0GMIICOL": "PS7_EMIOENET0GMIICOL", - "EMIOENET0GMIICRS": "PS7_EMIOENET0GMIICRS", - "EMIOENET0GMIIRXCLK": "PS7_EMIOENET0GMIIRXCLK", - "EMIOENET0GMIIRXD0": "PS7_EMIOENET0GMIIRXD0", - "EMIOENET0GMIIRXD1": "PS7_EMIOENET0GMIIRXD1", - "EMIOENET0GMIIRXD2": "PS7_EMIOENET0GMIIRXD2", - "EMIOENET0GMIIRXD3": "PS7_EMIOENET0GMIIRXD3", - "EMIOENET0GMIIRXD4": "PS7_EMIOENET0GMIIRXD4", - "EMIOENET0GMIIRXD5": "PS7_EMIOENET0GMIIRXD5", - "EMIOENET0GMIIRXD6": "PS7_EMIOENET0GMIIRXD6", - "EMIOENET0GMIIRXD7": "PS7_EMIOENET0GMIIRXD7", - "EMIOENET0GMIIRXDV": "PS7_EMIOENET0GMIIRXDV", - "EMIOENET0GMIIRXER": "PS7_EMIOENET0GMIIRXER", - "EMIOENET0GMIITXCLK": "PS7_EMIOENET0GMIITXCLK", - "EMIOENET0GMIITXD0": "PS7_EMIOENET0GMIITXD0", - "EMIOENET0GMIITXD1": "PS7_EMIOENET0GMIITXD1", - "EMIOENET0GMIITXD2": "PS7_EMIOENET0GMIITXD2", - "EMIOENET0GMIITXD3": "PS7_EMIOENET0GMIITXD3", - "EMIOENET0GMIITXD4": "PS7_EMIOENET0GMIITXD4", - "EMIOENET0GMIITXD5": "PS7_EMIOENET0GMIITXD5", - "EMIOENET0GMIITXD6": "PS7_EMIOENET0GMIITXD6", - "EMIOENET0GMIITXD7": "PS7_EMIOENET0GMIITXD7", - "EMIOENET0GMIITXEN": "PS7_EMIOENET0GMIITXEN", - "EMIOENET0GMIITXER": "PS7_EMIOENET0GMIITXER", - "EMIOENET0MDIOI": "PS7_EMIOENET0MDIOI", - "EMIOENET0MDIOMDC": "PS7_EMIOENET0MDIOMDC", - "EMIOENET0MDIOO": "PS7_EMIOENET0MDIOO", - "EMIOENET0MDIOTN": "PS7_EMIOENET0MDIOTN", - "EMIOENET0PTPDELAYREQRX": "PS7_EMIOENET0PTPDELAYREQRX", - "EMIOENET0PTPDELAYREQTX": "PS7_EMIOENET0PTPDELAYREQTX", - "EMIOENET0PTPPDELAYREQRX": "PS7_EMIOENET0PTPPDELAYREQRX", - "EMIOENET0PTPPDELAYREQTX": "PS7_EMIOENET0PTPPDELAYREQTX", - "EMIOENET0PTPPDELAYRESPRX": "PS7_EMIOENET0PTPPDELAYRESPRX", - "EMIOENET0PTPPDELAYRESPTX": "PS7_EMIOENET0PTPPDELAYRESPTX", - "EMIOENET0PTPSYNCFRAMERX": "PS7_EMIOENET0PTPSYNCFRAMERX", - "EMIOENET0PTPSYNCFRAMETX": "PS7_EMIOENET0PTPSYNCFRAMETX", - "EMIOENET0SOFRX": "PS7_EMIOENET0SOFRX", - "EMIOENET0SOFTX": "PS7_EMIOENET0SOFTX", - "EMIOENET1EXTINTIN": "PS7_EMIOENET1EXTINTIN", - "EMIOENET1GMIICOL": "PS7_EMIOENET1GMIICOL", - "EMIOENET1GMIICRS": "PS7_EMIOENET1GMIICRS", - "EMIOENET1GMIIRXCLK": "PS7_EMIOENET1GMIIRXCLK", - "EMIOENET1GMIIRXD0": "PS7_EMIOENET1GMIIRXD0", - "EMIOENET1GMIIRXD1": "PS7_EMIOENET1GMIIRXD1", - "EMIOENET1GMIIRXD2": "PS7_EMIOENET1GMIIRXD2", - "EMIOENET1GMIIRXD3": "PS7_EMIOENET1GMIIRXD3", - "EMIOENET1GMIIRXD4": "PS7_EMIOENET1GMIIRXD4", - "EMIOENET1GMIIRXD5": "PS7_EMIOENET1GMIIRXD5", - "EMIOENET1GMIIRXD6": "PS7_EMIOENET1GMIIRXD6", - "EMIOENET1GMIIRXD7": "PS7_EMIOENET1GMIIRXD7", - "EMIOENET1GMIIRXDV": "PS7_EMIOENET1GMIIRXDV", - "EMIOENET1GMIIRXER": "PS7_EMIOENET1GMIIRXER", - "EMIOENET1GMIITXCLK": "PS7_EMIOENET1GMIITXCLK", - "EMIOENET1GMIITXD0": "PS7_EMIOENET1GMIITXD0", - "EMIOENET1GMIITXD1": "PS7_EMIOENET1GMIITXD1", - "EMIOENET1GMIITXD2": "PS7_EMIOENET1GMIITXD2", - "EMIOENET1GMIITXD3": "PS7_EMIOENET1GMIITXD3", - "EMIOENET1GMIITXD4": "PS7_EMIOENET1GMIITXD4", - "EMIOENET1GMIITXD5": "PS7_EMIOENET1GMIITXD5", - "EMIOENET1GMIITXD6": "PS7_EMIOENET1GMIITXD6", - "EMIOENET1GMIITXD7": "PS7_EMIOENET1GMIITXD7", - "EMIOENET1GMIITXEN": "PS7_EMIOENET1GMIITXEN", - "EMIOENET1GMIITXER": "PS7_EMIOENET1GMIITXER", - "EMIOENET1MDIOI": "PS7_EMIOENET1MDIOI", - "EMIOENET1MDIOMDC": "PS7_EMIOENET1MDIOMDC", - "EMIOENET1MDIOO": "PS7_EMIOENET1MDIOO", - "EMIOENET1MDIOTN": "PS7_EMIOENET1MDIOTN", - "EMIOENET1PTPDELAYREQRX": "PS7_EMIOENET1PTPDELAYREQRX", - "EMIOENET1PTPDELAYREQTX": "PS7_EMIOENET1PTPDELAYREQTX", - "EMIOENET1PTPPDELAYREQRX": "PS7_EMIOENET1PTPPDELAYREQRX", - "EMIOENET1PTPPDELAYREQTX": "PS7_EMIOENET1PTPPDELAYREQTX", - "EMIOENET1PTPPDELAYRESPRX": "PS7_EMIOENET1PTPPDELAYRESPRX", - "EMIOENET1PTPPDELAYRESPTX": "PS7_EMIOENET1PTPPDELAYRESPTX", - "EMIOENET1PTPSYNCFRAMERX": "PS7_EMIOENET1PTPSYNCFRAMERX", - "EMIOENET1PTPSYNCFRAMETX": "PS7_EMIOENET1PTPSYNCFRAMETX", - "EMIOENET1SOFRX": "PS7_EMIOENET1SOFRX", - "EMIOENET1SOFTX": "PS7_EMIOENET1SOFTX", - "EMIOGPIOI0": "PS7_EMIOGPIOI0", - "EMIOGPIOI1": "PS7_EMIOGPIOI1", - "EMIOGPIOI10": "PS7_EMIOGPIOI10", - "EMIOGPIOI11": "PS7_EMIOGPIOI11", - "EMIOGPIOI12": "PS7_EMIOGPIOI12", - "EMIOGPIOI13": "PS7_EMIOGPIOI13", - "EMIOGPIOI14": "PS7_EMIOGPIOI14", - "EMIOGPIOI15": "PS7_EMIOGPIOI15", - "EMIOGPIOI16": "PS7_EMIOGPIOI16", - "EMIOGPIOI17": "PS7_EMIOGPIOI17", - "EMIOGPIOI18": "PS7_EMIOGPIOI18", - "EMIOGPIOI19": "PS7_EMIOGPIOI19", - "EMIOGPIOI2": "PS7_EMIOGPIOI2", - "EMIOGPIOI20": "PS7_EMIOGPIOI20", - "EMIOGPIOI21": "PS7_EMIOGPIOI21", - "EMIOGPIOI22": "PS7_EMIOGPIOI22", - "EMIOGPIOI23": "PS7_EMIOGPIOI23", - "EMIOGPIOI24": "PS7_EMIOGPIOI24", - "EMIOGPIOI25": "PS7_EMIOGPIOI25", - "EMIOGPIOI26": "PS7_EMIOGPIOI26", - "EMIOGPIOI27": "PS7_EMIOGPIOI27", - "EMIOGPIOI28": "PS7_EMIOGPIOI28", - "EMIOGPIOI29": "PS7_EMIOGPIOI29", - "EMIOGPIOI3": "PS7_EMIOGPIOI3", - "EMIOGPIOI30": "PS7_EMIOGPIOI30", - "EMIOGPIOI31": "PS7_EMIOGPIOI31", - "EMIOGPIOI32": "PS7_EMIOGPIOI32", - "EMIOGPIOI33": "PS7_EMIOGPIOI33", - "EMIOGPIOI34": "PS7_EMIOGPIOI34", - "EMIOGPIOI35": "PS7_EMIOGPIOI35", - "EMIOGPIOI36": "PS7_EMIOGPIOI36", - "EMIOGPIOI37": "PS7_EMIOGPIOI37", - "EMIOGPIOI38": "PS7_EMIOGPIOI38", - "EMIOGPIOI39": "PS7_EMIOGPIOI39", - "EMIOGPIOI4": "PS7_EMIOGPIOI4", - "EMIOGPIOI40": "PS7_EMIOGPIOI40", - "EMIOGPIOI41": "PS7_EMIOGPIOI41", - "EMIOGPIOI42": "PS7_EMIOGPIOI42", - "EMIOGPIOI43": "PS7_EMIOGPIOI43", - "EMIOGPIOI44": "PS7_EMIOGPIOI44", - "EMIOGPIOI45": "PS7_EMIOGPIOI45", - "EMIOGPIOI46": "PS7_EMIOGPIOI46", - "EMIOGPIOI47": "PS7_EMIOGPIOI47", - "EMIOGPIOI48": "PS7_EMIOGPIOI48", - "EMIOGPIOI49": "PS7_EMIOGPIOI49", - "EMIOGPIOI5": "PS7_EMIOGPIOI5", - "EMIOGPIOI50": "PS7_EMIOGPIOI50", - "EMIOGPIOI51": "PS7_EMIOGPIOI51", - "EMIOGPIOI52": "PS7_EMIOGPIOI52", - "EMIOGPIOI53": "PS7_EMIOGPIOI53", - "EMIOGPIOI54": "PS7_EMIOGPIOI54", - "EMIOGPIOI55": "PS7_EMIOGPIOI55", - "EMIOGPIOI56": "PS7_EMIOGPIOI56", - "EMIOGPIOI57": "PS7_EMIOGPIOI57", - "EMIOGPIOI58": "PS7_EMIOGPIOI58", - "EMIOGPIOI59": "PS7_EMIOGPIOI59", - "EMIOGPIOI6": "PS7_EMIOGPIOI6", - "EMIOGPIOI60": "PS7_EMIOGPIOI60", - "EMIOGPIOI61": "PS7_EMIOGPIOI61", - "EMIOGPIOI62": "PS7_EMIOGPIOI62", - "EMIOGPIOI63": "PS7_EMIOGPIOI63", - "EMIOGPIOI7": "PS7_EMIOGPIOI7", - "EMIOGPIOI8": "PS7_EMIOGPIOI8", - "EMIOGPIOI9": "PS7_EMIOGPIOI9", - "EMIOGPIOO0": "PS7_EMIOGPIOO0", - "EMIOGPIOO1": "PS7_EMIOGPIOO1", - "EMIOGPIOO10": "PS7_EMIOGPIOO10", - "EMIOGPIOO11": "PS7_EMIOGPIOO11", - "EMIOGPIOO12": "PS7_EMIOGPIOO12", - "EMIOGPIOO13": "PS7_EMIOGPIOO13", - "EMIOGPIOO14": "PS7_EMIOGPIOO14", - "EMIOGPIOO15": "PS7_EMIOGPIOO15", - "EMIOGPIOO16": "PS7_EMIOGPIOO16", - "EMIOGPIOO17": "PS7_EMIOGPIOO17", - "EMIOGPIOO18": "PS7_EMIOGPIOO18", - "EMIOGPIOO19": "PS7_EMIOGPIOO19", - "EMIOGPIOO2": "PS7_EMIOGPIOO2", - "EMIOGPIOO20": "PS7_EMIOGPIOO20", - "EMIOGPIOO21": "PS7_EMIOGPIOO21", - "EMIOGPIOO22": "PS7_EMIOGPIOO22", - "EMIOGPIOO23": "PS7_EMIOGPIOO23", - "EMIOGPIOO24": "PS7_EMIOGPIOO24", - "EMIOGPIOO25": "PS7_EMIOGPIOO25", - "EMIOGPIOO26": "PS7_EMIOGPIOO26", - "EMIOGPIOO27": "PS7_EMIOGPIOO27", - "EMIOGPIOO28": "PS7_EMIOGPIOO28", - "EMIOGPIOO29": "PS7_EMIOGPIOO29", - "EMIOGPIOO3": "PS7_EMIOGPIOO3", - "EMIOGPIOO30": "PS7_EMIOGPIOO30", - "EMIOGPIOO31": "PS7_EMIOGPIOO31", - "EMIOGPIOO32": "PS7_EMIOGPIOO32", - "EMIOGPIOO33": "PS7_EMIOGPIOO33", - "EMIOGPIOO34": "PS7_EMIOGPIOO34", - "EMIOGPIOO35": "PS7_EMIOGPIOO35", - "EMIOGPIOO36": "PS7_EMIOGPIOO36", - "EMIOGPIOO37": "PS7_EMIOGPIOO37", - "EMIOGPIOO38": "PS7_EMIOGPIOO38", - "EMIOGPIOO39": "PS7_EMIOGPIOO39", - "EMIOGPIOO4": "PS7_EMIOGPIOO4", - "EMIOGPIOO40": "PS7_EMIOGPIOO40", - "EMIOGPIOO41": "PS7_EMIOGPIOO41", - "EMIOGPIOO42": "PS7_EMIOGPIOO42", - "EMIOGPIOO43": "PS7_EMIOGPIOO43", - "EMIOGPIOO44": "PS7_EMIOGPIOO44", - "EMIOGPIOO45": "PS7_EMIOGPIOO45", - "EMIOGPIOO46": "PS7_EMIOGPIOO46", - "EMIOGPIOO47": "PS7_EMIOGPIOO47", - "EMIOGPIOO48": "PS7_EMIOGPIOO48", - "EMIOGPIOO49": "PS7_EMIOGPIOO49", - "EMIOGPIOO5": "PS7_EMIOGPIOO5", - "EMIOGPIOO50": "PS7_EMIOGPIOO50", - "EMIOGPIOO51": "PS7_EMIOGPIOO51", - "EMIOGPIOO52": "PS7_EMIOGPIOO52", - "EMIOGPIOO53": "PS7_EMIOGPIOO53", - "EMIOGPIOO54": "PS7_EMIOGPIOO54", - "EMIOGPIOO55": "PS7_EMIOGPIOO55", - "EMIOGPIOO56": "PS7_EMIOGPIOO56", - "EMIOGPIOO57": "PS7_EMIOGPIOO57", - "EMIOGPIOO58": "PS7_EMIOGPIOO58", - "EMIOGPIOO59": "PS7_EMIOGPIOO59", - "EMIOGPIOO6": "PS7_EMIOGPIOO6", - "EMIOGPIOO60": "PS7_EMIOGPIOO60", - "EMIOGPIOO61": "PS7_EMIOGPIOO61", - "EMIOGPIOO62": "PS7_EMIOGPIOO62", - "EMIOGPIOO63": "PS7_EMIOGPIOO63", - "EMIOGPIOO7": "PS7_EMIOGPIOO7", - "EMIOGPIOO8": "PS7_EMIOGPIOO8", - "EMIOGPIOO9": "PS7_EMIOGPIOO9", - "EMIOGPIOTN0": "PS7_EMIOGPIOTN0", - "EMIOGPIOTN1": "PS7_EMIOGPIOTN1", - "EMIOGPIOTN10": "PS7_EMIOGPIOTN10", - "EMIOGPIOTN11": "PS7_EMIOGPIOTN11", - "EMIOGPIOTN12": "PS7_EMIOGPIOTN12", - "EMIOGPIOTN13": "PS7_EMIOGPIOTN13", - "EMIOGPIOTN14": "PS7_EMIOGPIOTN14", - "EMIOGPIOTN15": "PS7_EMIOGPIOTN15", - "EMIOGPIOTN16": "PS7_EMIOGPIOTN16", - "EMIOGPIOTN17": "PS7_EMIOGPIOTN17", - "EMIOGPIOTN18": "PS7_EMIOGPIOTN18", - "EMIOGPIOTN19": "PS7_EMIOGPIOTN19", - "EMIOGPIOTN2": "PS7_EMIOGPIOTN2", - "EMIOGPIOTN20": "PS7_EMIOGPIOTN20", - "EMIOGPIOTN21": "PS7_EMIOGPIOTN21", - "EMIOGPIOTN22": "PS7_EMIOGPIOTN22", - "EMIOGPIOTN23": "PS7_EMIOGPIOTN23", - "EMIOGPIOTN24": "PS7_EMIOGPIOTN24", - "EMIOGPIOTN25": "PS7_EMIOGPIOTN25", - "EMIOGPIOTN26": "PS7_EMIOGPIOTN26", - "EMIOGPIOTN27": "PS7_EMIOGPIOTN27", - "EMIOGPIOTN28": "PS7_EMIOGPIOTN28", - "EMIOGPIOTN29": "PS7_EMIOGPIOTN29", - "EMIOGPIOTN3": "PS7_EMIOGPIOTN3", - "EMIOGPIOTN30": "PS7_EMIOGPIOTN30", - "EMIOGPIOTN31": "PS7_EMIOGPIOTN31", - "EMIOGPIOTN32": "PS7_EMIOGPIOTN32", - "EMIOGPIOTN33": "PS7_EMIOGPIOTN33", - "EMIOGPIOTN34": "PS7_EMIOGPIOTN34", - "EMIOGPIOTN35": "PS7_EMIOGPIOTN35", - "EMIOGPIOTN36": "PS7_EMIOGPIOTN36", - "EMIOGPIOTN37": "PS7_EMIOGPIOTN37", - "EMIOGPIOTN38": "PS7_EMIOGPIOTN38", - "EMIOGPIOTN39": "PS7_EMIOGPIOTN39", - "EMIOGPIOTN4": "PS7_EMIOGPIOTN4", - "EMIOGPIOTN40": "PS7_EMIOGPIOTN40", - "EMIOGPIOTN41": "PS7_EMIOGPIOTN41", - "EMIOGPIOTN42": "PS7_EMIOGPIOTN42", - "EMIOGPIOTN43": "PS7_EMIOGPIOTN43", - "EMIOGPIOTN44": "PS7_EMIOGPIOTN44", - "EMIOGPIOTN45": "PS7_EMIOGPIOTN45", - "EMIOGPIOTN46": "PS7_EMIOGPIOTN46", - "EMIOGPIOTN47": "PS7_EMIOGPIOTN47", - "EMIOGPIOTN48": "PS7_EMIOGPIOTN48", - "EMIOGPIOTN49": "PS7_EMIOGPIOTN49", - "EMIOGPIOTN5": "PS7_EMIOGPIOTN5", - "EMIOGPIOTN50": "PS7_EMIOGPIOTN50", - "EMIOGPIOTN51": "PS7_EMIOGPIOTN51", - "EMIOGPIOTN52": "PS7_EMIOGPIOTN52", - "EMIOGPIOTN53": "PS7_EMIOGPIOTN53", - "EMIOGPIOTN54": "PS7_EMIOGPIOTN54", - "EMIOGPIOTN55": "PS7_EMIOGPIOTN55", - "EMIOGPIOTN56": "PS7_EMIOGPIOTN56", - "EMIOGPIOTN57": "PS7_EMIOGPIOTN57", - "EMIOGPIOTN58": "PS7_EMIOGPIOTN58", - "EMIOGPIOTN59": "PS7_EMIOGPIOTN59", - "EMIOGPIOTN6": "PS7_EMIOGPIOTN6", - "EMIOGPIOTN60": "PS7_EMIOGPIOTN60", - "EMIOGPIOTN61": "PS7_EMIOGPIOTN61", - "EMIOGPIOTN62": "PS7_EMIOGPIOTN62", - "EMIOGPIOTN63": "PS7_EMIOGPIOTN63", - "EMIOGPIOTN7": "PS7_EMIOGPIOTN7", - "EMIOGPIOTN8": "PS7_EMIOGPIOTN8", - "EMIOGPIOTN9": "PS7_EMIOGPIOTN9", - "EMIOI2C0SCLI": "PS7_EMIOI2C0SCLI", - "EMIOI2C0SCLO": "PS7_EMIOI2C0SCLO", - "EMIOI2C0SCLTN": "PS7_EMIOI2C0SCLTN", - "EMIOI2C0SDAI": "PS7_EMIOI2C0SDAI", - "EMIOI2C0SDAO": "PS7_EMIOI2C0SDAO", - "EMIOI2C0SDATN": "PS7_EMIOI2C0SDATN", - "EMIOI2C1SCLI": "PS7_EMIOI2C1SCLI", - "EMIOI2C1SCLO": "PS7_EMIOI2C1SCLO", - "EMIOI2C1SCLTN": "PS7_EMIOI2C1SCLTN", - "EMIOI2C1SDAI": "PS7_EMIOI2C1SDAI", - "EMIOI2C1SDAO": "PS7_EMIOI2C1SDAO", - "EMIOI2C1SDATN": "PS7_EMIOI2C1SDATN", - "EMIOPJTAGTCK": "PS7_EMIOPJTAGTCK", - "EMIOPJTAGTDI": "PS7_EMIOPJTAGTDI", - "EMIOPJTAGTDO": "PS7_EMIOPJTAGTDO", - "EMIOPJTAGTDTN": "PS7_EMIOPJTAGTDTN", - "EMIOPJTAGTMS": "PS7_EMIOPJTAGTMS", - "EMIOSDIO0BUSPOW": "PS7_EMIOSDIO0BUSPOW", - "EMIOSDIO0BUSVOLT0": "PS7_EMIOSDIO0BUSVOLT0", - "EMIOSDIO0BUSVOLT1": "PS7_EMIOSDIO0BUSVOLT1", - "EMIOSDIO0BUSVOLT2": "PS7_EMIOSDIO0BUSVOLT2", - "EMIOSDIO0CDN": "PS7_EMIOSDIO0CDN", - "EMIOSDIO0CLK": "PS7_EMIOSDIO0CLK", - "EMIOSDIO0CLKFB": "PS7_EMIOSDIO0CLKFB", - "EMIOSDIO0CMDI": "PS7_EMIOSDIO0CMDI", - "EMIOSDIO0CMDO": "PS7_EMIOSDIO0CMDO", - "EMIOSDIO0CMDTN": "PS7_EMIOSDIO0CMDTN", - "EMIOSDIO0DATAI0": "PS7_EMIOSDIO0DATAI0", - "EMIOSDIO0DATAI1": "PS7_EMIOSDIO0DATAI1", - "EMIOSDIO0DATAI2": "PS7_EMIOSDIO0DATAI2", - "EMIOSDIO0DATAI3": "PS7_EMIOSDIO0DATAI3", - "EMIOSDIO0DATAO0": "PS7_EMIOSDIO0DATAO0", - "EMIOSDIO0DATAO1": "PS7_EMIOSDIO0DATAO1", - "EMIOSDIO0DATAO2": "PS7_EMIOSDIO0DATAO2", - "EMIOSDIO0DATAO3": "PS7_EMIOSDIO0DATAO3", - "EMIOSDIO0DATATN0": "PS7_EMIOSDIO0DATATN0", - "EMIOSDIO0DATATN1": "PS7_EMIOSDIO0DATATN1", - "EMIOSDIO0DATATN2": "PS7_EMIOSDIO0DATATN2", - "EMIOSDIO0DATATN3": "PS7_EMIOSDIO0DATATN3", - "EMIOSDIO0LED": "PS7_EMIOSDIO0LED", - "EMIOSDIO0WP": "PS7_EMIOSDIO0WP", - "EMIOSDIO1BUSPOW": "PS7_EMIOSDIO1BUSPOW", - "EMIOSDIO1BUSVOLT0": "PS7_EMIOSDIO1BUSVOLT0", - "EMIOSDIO1BUSVOLT1": "PS7_EMIOSDIO1BUSVOLT1", - "EMIOSDIO1BUSVOLT2": "PS7_EMIOSDIO1BUSVOLT2", - "EMIOSDIO1CDN": "PS7_EMIOSDIO1CDN", - "EMIOSDIO1CLK": "PS7_EMIOSDIO1CLK", - "EMIOSDIO1CLKFB": "PS7_EMIOSDIO1CLKFB", - "EMIOSDIO1CMDI": "PS7_EMIOSDIO1CMDI", - "EMIOSDIO1CMDO": "PS7_EMIOSDIO1CMDO", - "EMIOSDIO1CMDTN": "PS7_EMIOSDIO1CMDTN", - "EMIOSDIO1DATAI0": "PS7_EMIOSDIO1DATAI0", - "EMIOSDIO1DATAI1": "PS7_EMIOSDIO1DATAI1", - "EMIOSDIO1DATAI2": "PS7_EMIOSDIO1DATAI2", - "EMIOSDIO1DATAI3": "PS7_EMIOSDIO1DATAI3", - "EMIOSDIO1DATAO0": "PS7_EMIOSDIO1DATAO0", - "EMIOSDIO1DATAO1": "PS7_EMIOSDIO1DATAO1", - "EMIOSDIO1DATAO2": "PS7_EMIOSDIO1DATAO2", - "EMIOSDIO1DATAO3": "PS7_EMIOSDIO1DATAO3", - "EMIOSDIO1DATATN0": "PS7_EMIOSDIO1DATATN0", - "EMIOSDIO1DATATN1": "PS7_EMIOSDIO1DATATN1", - "EMIOSDIO1DATATN2": "PS7_EMIOSDIO1DATATN2", - "EMIOSDIO1DATATN3": "PS7_EMIOSDIO1DATATN3", - "EMIOSDIO1LED": "PS7_EMIOSDIO1LED", - "EMIOSDIO1WP": "PS7_EMIOSDIO1WP", - "EMIOSPI0MI": "PS7_EMIOSPI0MI", - "EMIOSPI0MO": "PS7_EMIOSPI0MO", - "EMIOSPI0MOTN": "PS7_EMIOSPI0MOTN", - "EMIOSPI0SCLKI": "PS7_EMIOSPI0SCLKI", - "EMIOSPI0SCLKO": "PS7_EMIOSPI0SCLKO", - "EMIOSPI0SCLKTN": "PS7_EMIOSPI0SCLKTN", - "EMIOSPI0SI": "PS7_EMIOSPI0SI", - "EMIOSPI0SO": "PS7_EMIOSPI0SO", - "EMIOSPI0SSIN": "PS7_EMIOSPI0SSIN", - "EMIOSPI0SSNTN": "PS7_EMIOSPI0SSNTN", - "EMIOSPI0SSON0": "PS7_EMIOSPI0SSON0", - "EMIOSPI0SSON1": "PS7_EMIOSPI0SSON1", - "EMIOSPI0SSON2": "PS7_EMIOSPI0SSON2", - "EMIOSPI0STN": "PS7_EMIOSPI0STN", - "EMIOSPI1MI": "PS7_EMIOSPI1MI", - "EMIOSPI1MO": "PS7_EMIOSPI1MO", - "EMIOSPI1MOTN": "PS7_EMIOSPI1MOTN", - "EMIOSPI1SCLKI": "PS7_EMIOSPI1SCLKI", - "EMIOSPI1SCLKO": "PS7_EMIOSPI1SCLKO", - "EMIOSPI1SCLKTN": "PS7_EMIOSPI1SCLKTN", - "EMIOSPI1SI": "PS7_EMIOSPI1SI", - "EMIOSPI1SO": "PS7_EMIOSPI1SO", - "EMIOSPI1SSIN": "PS7_EMIOSPI1SSIN", - "EMIOSPI1SSNTN": "PS7_EMIOSPI1SSNTN", - "EMIOSPI1SSON0": "PS7_EMIOSPI1SSON0", - "EMIOSPI1SSON1": "PS7_EMIOSPI1SSON1", - "EMIOSPI1SSON2": "PS7_EMIOSPI1SSON2", - "EMIOSPI1STN": "PS7_EMIOSPI1STN", - "EMIOSRAMINTIN": "PS7_EMIOSRAMINTIN", - "EMIOTRACECLK": "PS7_EMIOTRACECLK", - "EMIOTRACECTL": "PS7_EMIOTRACECTL", - "EMIOTRACEDATA0": "PS7_EMIOTRACEDATA0", - "EMIOTRACEDATA1": "PS7_EMIOTRACEDATA1", - "EMIOTRACEDATA10": "PS7_EMIOTRACEDATA10", - "EMIOTRACEDATA11": "PS7_EMIOTRACEDATA11", - "EMIOTRACEDATA12": "PS7_EMIOTRACEDATA12", - "EMIOTRACEDATA13": "PS7_EMIOTRACEDATA13", - "EMIOTRACEDATA14": "PS7_EMIOTRACEDATA14", - "EMIOTRACEDATA15": "PS7_EMIOTRACEDATA15", - "EMIOTRACEDATA16": "PS7_EMIOTRACEDATA16", - "EMIOTRACEDATA17": "PS7_EMIOTRACEDATA17", - "EMIOTRACEDATA18": "PS7_EMIOTRACEDATA18", - "EMIOTRACEDATA19": "PS7_EMIOTRACEDATA19", - "EMIOTRACEDATA2": "PS7_EMIOTRACEDATA2", - "EMIOTRACEDATA20": "PS7_EMIOTRACEDATA20", - "EMIOTRACEDATA21": "PS7_EMIOTRACEDATA21", - "EMIOTRACEDATA22": "PS7_EMIOTRACEDATA22", - "EMIOTRACEDATA23": "PS7_EMIOTRACEDATA23", - "EMIOTRACEDATA24": "PS7_EMIOTRACEDATA24", - "EMIOTRACEDATA25": "PS7_EMIOTRACEDATA25", - "EMIOTRACEDATA26": "PS7_EMIOTRACEDATA26", - "EMIOTRACEDATA27": "PS7_EMIOTRACEDATA27", - "EMIOTRACEDATA28": "PS7_EMIOTRACEDATA28", - "EMIOTRACEDATA29": "PS7_EMIOTRACEDATA29", - "EMIOTRACEDATA3": "PS7_EMIOTRACEDATA3", - "EMIOTRACEDATA30": "PS7_EMIOTRACEDATA30", - "EMIOTRACEDATA31": "PS7_EMIOTRACEDATA31", - "EMIOTRACEDATA4": "PS7_EMIOTRACEDATA4", - "EMIOTRACEDATA5": "PS7_EMIOTRACEDATA5", - "EMIOTRACEDATA6": "PS7_EMIOTRACEDATA6", - "EMIOTRACEDATA7": "PS7_EMIOTRACEDATA7", - "EMIOTRACEDATA8": "PS7_EMIOTRACEDATA8", - "EMIOTRACEDATA9": "PS7_EMIOTRACEDATA9", - "EMIOTTC0CLKI0": "PS7_EMIOTTC0CLKI0", - "EMIOTTC0CLKI1": "PS7_EMIOTTC0CLKI1", - "EMIOTTC0CLKI2": "PS7_EMIOTTC0CLKI2", - "EMIOTTC0WAVEO0": "PS7_EMIOTTC0WAVEO0", - "EMIOTTC0WAVEO1": "PS7_EMIOTTC0WAVEO1", - "EMIOTTC0WAVEO2": "PS7_EMIOTTC0WAVEO2", - "EMIOTTC1CLKI0": "PS7_EMIOTTC1CLKI0", - "EMIOTTC1CLKI1": "PS7_EMIOTTC1CLKI1", - "EMIOTTC1CLKI2": "PS7_EMIOTTC1CLKI2", - "EMIOTTC1WAVEO0": "PS7_EMIOTTC1WAVEO0", - "EMIOTTC1WAVEO1": "PS7_EMIOTTC1WAVEO1", - "EMIOTTC1WAVEO2": "PS7_EMIOTTC1WAVEO2", - "EMIOUART0CTSN": "PS7_EMIOUART0CTSN", - "EMIOUART0DCDN": "PS7_EMIOUART0DCDN", - "EMIOUART0DSRN": "PS7_EMIOUART0DSRN", - "EMIOUART0DTRN": "PS7_EMIOUART0DTRN", - "EMIOUART0RIN": "PS7_EMIOUART0RIN", - "EMIOUART0RTSN": "PS7_EMIOUART0RTSN", - "EMIOUART0RX": "PS7_EMIOUART0RX", - "EMIOUART0TX": "PS7_EMIOUART0TX", - "EMIOUART1CTSN": "PS7_EMIOUART1CTSN", - "EMIOUART1DCDN": "PS7_EMIOUART1DCDN", - "EMIOUART1DSRN": "PS7_EMIOUART1DSRN", - "EMIOUART1DTRN": "PS7_EMIOUART1DTRN", - "EMIOUART1RIN": "PS7_EMIOUART1RIN", - "EMIOUART1RTSN": "PS7_EMIOUART1RTSN", - "EMIOUART1RX": "PS7_EMIOUART1RX", - "EMIOUART1TX": "PS7_EMIOUART1TX", - "EMIOUSB0PORTINDCTL0": "PS7_EMIOUSB0PORTINDCTL0", - "EMIOUSB0PORTINDCTL1": "PS7_EMIOUSB0PORTINDCTL1", - "EMIOUSB0VBUSPWRFAULT": "PS7_EMIOUSB0VBUSPWRFAULT", - "EMIOUSB0VBUSPWRSELECT": "PS7_EMIOUSB0VBUSPWRSELECT", - "EMIOUSB1PORTINDCTL0": "PS7_EMIOUSB1PORTINDCTL0", - "EMIOUSB1PORTINDCTL1": "PS7_EMIOUSB1PORTINDCTL1", - "EMIOUSB1VBUSPWRFAULT": "PS7_EMIOUSB1VBUSPWRFAULT", - "EMIOUSB1VBUSPWRSELECT": "PS7_EMIOUSB1VBUSPWRSELECT", - "EMIOWDTCLKI": "PS7_EMIOWDTCLKI", - "EMIOWDTRSTO": "PS7_EMIOWDTRSTO", - "EVENTEVENTI": "PS7_EVENTEVENTI", - "EVENTEVENTO": "PS7_EVENTEVENTO", - "EVENTSTANDBYWFE0": "PS7_EVENTSTANDBYWFE0", - "EVENTSTANDBYWFE1": "PS7_EVENTSTANDBYWFE1", - "EVENTSTANDBYWFI0": "PS7_EVENTSTANDBYWFI0", - "EVENTSTANDBYWFI1": "PS7_EVENTSTANDBYWFI1", - "FCLKCLK0": "PS7_FCLKCLK0", - "FCLKCLK1": "PS7_FCLKCLK1", - "FCLKCLK2": "PS7_FCLKCLK2", - "FCLKCLK3": "PS7_FCLKCLK3", - "FCLKCLKTRIGN0": "PS7_FCLKCLKTRIGN0", - "FCLKCLKTRIGN1": "PS7_FCLKCLKTRIGN1", - "FCLKCLKTRIGN2": "PS7_FCLKCLKTRIGN2", - "FCLKCLKTRIGN3": "PS7_FCLKCLKTRIGN3", - "FCLKRESETN0": "PS7_FCLKRESETN0", - "FCLKRESETN1": "PS7_FCLKRESETN1", - "FCLKRESETN2": "PS7_FCLKRESETN2", - "FCLKRESETN3": "PS7_FCLKRESETN3", - "FPGAIDLEN": "PS7_FPGAIDLEN", - "FTMDTRACEINATID0": "PS7_FTMDTRACEINATID0", - "FTMDTRACEINATID1": "PS7_FTMDTRACEINATID1", - "FTMDTRACEINATID2": "PS7_FTMDTRACEINATID2", - "FTMDTRACEINATID3": "PS7_FTMDTRACEINATID3", - "FTMDTRACEINCLOCK": "PS7_FTMDTRACEINCLOCK", - "FTMDTRACEINDATA0": "PS7_FTMDTRACEINDATA0", - "FTMDTRACEINDATA1": "PS7_FTMDTRACEINDATA1", - "FTMDTRACEINDATA10": "PS7_FTMDTRACEINDATA10", - "FTMDTRACEINDATA11": "PS7_FTMDTRACEINDATA11", - "FTMDTRACEINDATA12": "PS7_FTMDTRACEINDATA12", - "FTMDTRACEINDATA13": "PS7_FTMDTRACEINDATA13", - "FTMDTRACEINDATA14": "PS7_FTMDTRACEINDATA14", - "FTMDTRACEINDATA15": "PS7_FTMDTRACEINDATA15", - "FTMDTRACEINDATA16": "PS7_FTMDTRACEINDATA16", - "FTMDTRACEINDATA17": "PS7_FTMDTRACEINDATA17", - "FTMDTRACEINDATA18": "PS7_FTMDTRACEINDATA18", - "FTMDTRACEINDATA19": "PS7_FTMDTRACEINDATA19", - "FTMDTRACEINDATA2": "PS7_FTMDTRACEINDATA2", - "FTMDTRACEINDATA20": "PS7_FTMDTRACEINDATA20", - "FTMDTRACEINDATA21": "PS7_FTMDTRACEINDATA21", - "FTMDTRACEINDATA22": "PS7_FTMDTRACEINDATA22", - "FTMDTRACEINDATA23": "PS7_FTMDTRACEINDATA23", - "FTMDTRACEINDATA24": "PS7_FTMDTRACEINDATA24", - "FTMDTRACEINDATA25": "PS7_FTMDTRACEINDATA25", - "FTMDTRACEINDATA26": "PS7_FTMDTRACEINDATA26", - "FTMDTRACEINDATA27": "PS7_FTMDTRACEINDATA27", - "FTMDTRACEINDATA28": "PS7_FTMDTRACEINDATA28", - "FTMDTRACEINDATA29": "PS7_FTMDTRACEINDATA29", - "FTMDTRACEINDATA3": "PS7_FTMDTRACEINDATA3", - "FTMDTRACEINDATA30": "PS7_FTMDTRACEINDATA30", - "FTMDTRACEINDATA31": "PS7_FTMDTRACEINDATA31", - "FTMDTRACEINDATA4": "PS7_FTMDTRACEINDATA4", - "FTMDTRACEINDATA5": "PS7_FTMDTRACEINDATA5", - "FTMDTRACEINDATA6": "PS7_FTMDTRACEINDATA6", - "FTMDTRACEINDATA7": "PS7_FTMDTRACEINDATA7", - "FTMDTRACEINDATA8": "PS7_FTMDTRACEINDATA8", - "FTMDTRACEINDATA9": "PS7_FTMDTRACEINDATA9", - "FTMDTRACEINVALID": "PS7_FTMDTRACEINVALID", - "FTMTF2PDEBUG0": "PS7_FTMTF2PDEBUG0", - "FTMTF2PDEBUG1": "PS7_FTMTF2PDEBUG1", - "FTMTF2PDEBUG10": "PS7_FTMTF2PDEBUG10", - "FTMTF2PDEBUG11": "PS7_FTMTF2PDEBUG11", - "FTMTF2PDEBUG12": "PS7_FTMTF2PDEBUG12", - "FTMTF2PDEBUG13": "PS7_FTMTF2PDEBUG13", - "FTMTF2PDEBUG14": "PS7_FTMTF2PDEBUG14", - "FTMTF2PDEBUG15": "PS7_FTMTF2PDEBUG15", - "FTMTF2PDEBUG16": "PS7_FTMTF2PDEBUG16", - "FTMTF2PDEBUG17": "PS7_FTMTF2PDEBUG17", - "FTMTF2PDEBUG18": "PS7_FTMTF2PDEBUG18", - "FTMTF2PDEBUG19": "PS7_FTMTF2PDEBUG19", - "FTMTF2PDEBUG2": "PS7_FTMTF2PDEBUG2", - "FTMTF2PDEBUG20": "PS7_FTMTF2PDEBUG20", - "FTMTF2PDEBUG21": "PS7_FTMTF2PDEBUG21", - "FTMTF2PDEBUG22": "PS7_FTMTF2PDEBUG22", - "FTMTF2PDEBUG23": "PS7_FTMTF2PDEBUG23", - "FTMTF2PDEBUG24": "PS7_FTMTF2PDEBUG24", - "FTMTF2PDEBUG25": "PS7_FTMTF2PDEBUG25", - "FTMTF2PDEBUG26": "PS7_FTMTF2PDEBUG26", - "FTMTF2PDEBUG27": "PS7_FTMTF2PDEBUG27", - "FTMTF2PDEBUG28": "PS7_FTMTF2PDEBUG28", - "FTMTF2PDEBUG29": "PS7_FTMTF2PDEBUG29", - "FTMTF2PDEBUG3": "PS7_FTMTF2PDEBUG3", - "FTMTF2PDEBUG30": "PS7_FTMTF2PDEBUG30", - "FTMTF2PDEBUG31": "PS7_FTMTF2PDEBUG31", - "FTMTF2PDEBUG4": "PS7_FTMTF2PDEBUG4", - "FTMTF2PDEBUG5": "PS7_FTMTF2PDEBUG5", - "FTMTF2PDEBUG6": "PS7_FTMTF2PDEBUG6", - "FTMTF2PDEBUG7": "PS7_FTMTF2PDEBUG7", - "FTMTF2PDEBUG8": "PS7_FTMTF2PDEBUG8", - "FTMTF2PDEBUG9": "PS7_FTMTF2PDEBUG9", - "FTMTF2PTRIG0": "PS7_FTMTF2PTRIG0", - "FTMTF2PTRIG1": "PS7_FTMTF2PTRIG1", - "FTMTF2PTRIG2": "PS7_FTMTF2PTRIG2", - "FTMTF2PTRIG3": "PS7_FTMTF2PTRIG3", - "FTMTF2PTRIGACK0": "PS7_FTMTF2PTRIGACK0", - "FTMTF2PTRIGACK1": "PS7_FTMTF2PTRIGACK1", - "FTMTF2PTRIGACK2": "PS7_FTMTF2PTRIGACK2", - "FTMTF2PTRIGACK3": "PS7_FTMTF2PTRIGACK3", - "FTMTP2FDEBUG0": "PS7_FTMTP2FDEBUG0", - "FTMTP2FDEBUG1": "PS7_FTMTP2FDEBUG1", - "FTMTP2FDEBUG10": "PS7_FTMTP2FDEBUG10", - "FTMTP2FDEBUG11": "PS7_FTMTP2FDEBUG11", - "FTMTP2FDEBUG12": "PS7_FTMTP2FDEBUG12", - "FTMTP2FDEBUG13": "PS7_FTMTP2FDEBUG13", - "FTMTP2FDEBUG14": "PS7_FTMTP2FDEBUG14", - "FTMTP2FDEBUG15": "PS7_FTMTP2FDEBUG15", - "FTMTP2FDEBUG16": "PS7_FTMTP2FDEBUG16", - "FTMTP2FDEBUG17": "PS7_FTMTP2FDEBUG17", - "FTMTP2FDEBUG18": "PS7_FTMTP2FDEBUG18", - "FTMTP2FDEBUG19": "PS7_FTMTP2FDEBUG19", - "FTMTP2FDEBUG2": "PS7_FTMTP2FDEBUG2", - "FTMTP2FDEBUG20": "PS7_FTMTP2FDEBUG20", - "FTMTP2FDEBUG21": "PS7_FTMTP2FDEBUG21", - "FTMTP2FDEBUG22": "PS7_FTMTP2FDEBUG22", - "FTMTP2FDEBUG23": "PS7_FTMTP2FDEBUG23", - "FTMTP2FDEBUG24": "PS7_FTMTP2FDEBUG24", - "FTMTP2FDEBUG25": "PS7_FTMTP2FDEBUG25", - "FTMTP2FDEBUG26": "PS7_FTMTP2FDEBUG26", - "FTMTP2FDEBUG27": "PS7_FTMTP2FDEBUG27", - "FTMTP2FDEBUG28": "PS7_FTMTP2FDEBUG28", - "FTMTP2FDEBUG29": "PS7_FTMTP2FDEBUG29", - "FTMTP2FDEBUG3": "PS7_FTMTP2FDEBUG3", - "FTMTP2FDEBUG30": "PS7_FTMTP2FDEBUG30", - "FTMTP2FDEBUG31": "PS7_FTMTP2FDEBUG31", - "FTMTP2FDEBUG4": "PS7_FTMTP2FDEBUG4", - "FTMTP2FDEBUG5": "PS7_FTMTP2FDEBUG5", - "FTMTP2FDEBUG6": "PS7_FTMTP2FDEBUG6", - "FTMTP2FDEBUG7": "PS7_FTMTP2FDEBUG7", - "FTMTP2FDEBUG8": "PS7_FTMTP2FDEBUG8", - "FTMTP2FDEBUG9": "PS7_FTMTP2FDEBUG9", - "FTMTP2FTRIG0": "PS7_FTMTP2FTRIG0", - "FTMTP2FTRIG1": "PS7_FTMTP2FTRIG1", - "FTMTP2FTRIG2": "PS7_FTMTP2FTRIG2", - "FTMTP2FTRIG3": "PS7_FTMTP2FTRIG3", - "FTMTP2FTRIGACK0": "PS7_FTMTP2FTRIGACK0", - "FTMTP2FTRIGACK1": "PS7_FTMTP2FTRIGACK1", - "FTMTP2FTRIGACK2": "PS7_FTMTP2FTRIGACK2", - "FTMTP2FTRIGACK3": "PS7_FTMTP2FTRIGACK3", - "IRQF2P0": "PS7_IRQF2P0", - "IRQF2P1": "PS7_IRQF2P1", - "IRQF2P10": "PS7_IRQF2P10", - "IRQF2P11": "PS7_IRQF2P11", - "IRQF2P12": "PS7_IRQF2P12", - "IRQF2P13": "PS7_IRQF2P13", - "IRQF2P14": "PS7_IRQF2P14", - "IRQF2P15": "PS7_IRQF2P15", - "IRQF2P16": "PS7_IRQF2P16", - "IRQF2P17": "PS7_IRQF2P17", - "IRQF2P18": "PS7_IRQF2P18", - "IRQF2P19": "PS7_IRQF2P19", - "IRQF2P2": "PS7_IRQF2P2", - "IRQF2P3": "PS7_IRQF2P3", - "IRQF2P4": "PS7_IRQF2P4", - "IRQF2P5": "PS7_IRQF2P5", - "IRQF2P6": "PS7_IRQF2P6", - "IRQF2P7": "PS7_IRQF2P7", - "IRQF2P8": "PS7_IRQF2P8", - "IRQF2P9": "PS7_IRQF2P9", - "IRQP2F0": "PS7_IRQP2F0", - "IRQP2F1": "PS7_IRQP2F1", - "IRQP2F10": "PS7_IRQP2F10", - "IRQP2F11": "PS7_IRQP2F11", - "IRQP2F12": "PS7_IRQP2F12", - "IRQP2F13": "PS7_IRQP2F13", - "IRQP2F14": "PS7_IRQP2F14", - "IRQP2F15": "PS7_IRQP2F15", - "IRQP2F16": "PS7_IRQP2F16", - "IRQP2F17": "PS7_IRQP2F17", - "IRQP2F18": "PS7_IRQP2F18", - "IRQP2F19": "PS7_IRQP2F19", - "IRQP2F2": "PS7_IRQP2F2", - "IRQP2F20": "PS7_IRQP2F20", - "IRQP2F21": "PS7_IRQP2F21", - "IRQP2F22": "PS7_IRQP2F22", - "IRQP2F23": "PS7_IRQP2F23", - "IRQP2F24": "PS7_IRQP2F24", - "IRQP2F25": "PS7_IRQP2F25", - "IRQP2F26": "PS7_IRQP2F26", - "IRQP2F27": "PS7_IRQP2F27", - "IRQP2F28": "PS7_IRQP2F28", - "IRQP2F3": "PS7_IRQP2F3", - "IRQP2F4": "PS7_IRQP2F4", - "IRQP2F5": "PS7_IRQP2F5", - "IRQP2F6": "PS7_IRQP2F6", - "IRQP2F7": "PS7_IRQP2F7", - "IRQP2F8": "PS7_IRQP2F8", - "IRQP2F9": "PS7_IRQP2F9", - "MAXIGP0ACLK": "PS7_MAXIGP0ACLK", - "MAXIGP0ARADDR0": "PS7_MAXIGP0ARADDR0", - "MAXIGP0ARADDR1": "PS7_MAXIGP0ARADDR1", - "MAXIGP0ARADDR10": "PS7_MAXIGP0ARADDR10", - "MAXIGP0ARADDR11": "PS7_MAXIGP0ARADDR11", - "MAXIGP0ARADDR12": "PS7_MAXIGP0ARADDR12", - "MAXIGP0ARADDR13": "PS7_MAXIGP0ARADDR13", - "MAXIGP0ARADDR14": "PS7_MAXIGP0ARADDR14", - "MAXIGP0ARADDR15": "PS7_MAXIGP0ARADDR15", - "MAXIGP0ARADDR16": "PS7_MAXIGP0ARADDR16", - "MAXIGP0ARADDR17": "PS7_MAXIGP0ARADDR17", - "MAXIGP0ARADDR18": "PS7_MAXIGP0ARADDR18", - "MAXIGP0ARADDR19": "PS7_MAXIGP0ARADDR19", - "MAXIGP0ARADDR2": "PS7_MAXIGP0ARADDR2", - "MAXIGP0ARADDR20": "PS7_MAXIGP0ARADDR20", - "MAXIGP0ARADDR21": "PS7_MAXIGP0ARADDR21", - "MAXIGP0ARADDR22": "PS7_MAXIGP0ARADDR22", - "MAXIGP0ARADDR23": "PS7_MAXIGP0ARADDR23", - "MAXIGP0ARADDR24": "PS7_MAXIGP0ARADDR24", - "MAXIGP0ARADDR25": "PS7_MAXIGP0ARADDR25", - "MAXIGP0ARADDR26": "PS7_MAXIGP0ARADDR26", - "MAXIGP0ARADDR27": "PS7_MAXIGP0ARADDR27", - "MAXIGP0ARADDR28": "PS7_MAXIGP0ARADDR28", - "MAXIGP0ARADDR29": "PS7_MAXIGP0ARADDR29", - "MAXIGP0ARADDR3": "PS7_MAXIGP0ARADDR3", - "MAXIGP0ARADDR30": "PS7_MAXIGP0ARADDR30", - "MAXIGP0ARADDR31": "PS7_MAXIGP0ARADDR31", - "MAXIGP0ARADDR4": "PS7_MAXIGP0ARADDR4", - "MAXIGP0ARADDR5": "PS7_MAXIGP0ARADDR5", - "MAXIGP0ARADDR6": "PS7_MAXIGP0ARADDR6", - "MAXIGP0ARADDR7": "PS7_MAXIGP0ARADDR7", - "MAXIGP0ARADDR8": "PS7_MAXIGP0ARADDR8", - "MAXIGP0ARADDR9": "PS7_MAXIGP0ARADDR9", - "MAXIGP0ARBURST0": "PS7_MAXIGP0ARBURST0", - "MAXIGP0ARBURST1": "PS7_MAXIGP0ARBURST1", - "MAXIGP0ARCACHE0": "PS7_MAXIGP0ARCACHE0", - "MAXIGP0ARCACHE1": "PS7_MAXIGP0ARCACHE1", - "MAXIGP0ARCACHE2": "PS7_MAXIGP0ARCACHE2", - "MAXIGP0ARCACHE3": "PS7_MAXIGP0ARCACHE3", - "MAXIGP0ARESETN": "PS7_MAXIGP0ARESETN", - "MAXIGP0ARID0": "PS7_MAXIGP0ARID0", - "MAXIGP0ARID1": "PS7_MAXIGP0ARID1", - "MAXIGP0ARID10": "PS7_MAXIGP0ARID10", - "MAXIGP0ARID11": "PS7_MAXIGP0ARID11", - "MAXIGP0ARID2": "PS7_MAXIGP0ARID2", - "MAXIGP0ARID3": "PS7_MAXIGP0ARID3", - "MAXIGP0ARID4": "PS7_MAXIGP0ARID4", - "MAXIGP0ARID5": "PS7_MAXIGP0ARID5", - "MAXIGP0ARID6": "PS7_MAXIGP0ARID6", - "MAXIGP0ARID7": "PS7_MAXIGP0ARID7", - "MAXIGP0ARID8": "PS7_MAXIGP0ARID8", - "MAXIGP0ARID9": "PS7_MAXIGP0ARID9", - "MAXIGP0ARLEN0": "PS7_MAXIGP0ARLEN0", - "MAXIGP0ARLEN1": "PS7_MAXIGP0ARLEN1", - "MAXIGP0ARLEN2": "PS7_MAXIGP0ARLEN2", - "MAXIGP0ARLEN3": "PS7_MAXIGP0ARLEN3", - "MAXIGP0ARLOCK0": "PS7_MAXIGP0ARLOCK0", - "MAXIGP0ARLOCK1": "PS7_MAXIGP0ARLOCK1", - "MAXIGP0ARPROT0": "PS7_MAXIGP0ARPROT0", - "MAXIGP0ARPROT1": "PS7_MAXIGP0ARPROT1", - "MAXIGP0ARPROT2": "PS7_MAXIGP0ARPROT2", - "MAXIGP0ARQOS0": "PS7_MAXIGP0ARQOS0", - "MAXIGP0ARQOS1": "PS7_MAXIGP0ARQOS1", - "MAXIGP0ARQOS2": "PS7_MAXIGP0ARQOS2", - "MAXIGP0ARQOS3": "PS7_MAXIGP0ARQOS3", - "MAXIGP0ARREADY": "PS7_MAXIGP0ARREADY", - "MAXIGP0ARSIZE0": "PS7_MAXIGP0ARSIZE0", - "MAXIGP0ARSIZE1": "PS7_MAXIGP0ARSIZE1", - "MAXIGP0ARVALID": "PS7_MAXIGP0ARVALID", - "MAXIGP0AWADDR0": "PS7_MAXIGP0AWADDR0", - "MAXIGP0AWADDR1": "PS7_MAXIGP0AWADDR1", - "MAXIGP0AWADDR10": "PS7_MAXIGP0AWADDR10", - "MAXIGP0AWADDR11": "PS7_MAXIGP0AWADDR11", - "MAXIGP0AWADDR12": "PS7_MAXIGP0AWADDR12", - "MAXIGP0AWADDR13": "PS7_MAXIGP0AWADDR13", - "MAXIGP0AWADDR14": "PS7_MAXIGP0AWADDR14", - "MAXIGP0AWADDR15": "PS7_MAXIGP0AWADDR15", - "MAXIGP0AWADDR16": "PS7_MAXIGP0AWADDR16", - "MAXIGP0AWADDR17": "PS7_MAXIGP0AWADDR17", - "MAXIGP0AWADDR18": "PS7_MAXIGP0AWADDR18", - "MAXIGP0AWADDR19": "PS7_MAXIGP0AWADDR19", - "MAXIGP0AWADDR2": "PS7_MAXIGP0AWADDR2", - "MAXIGP0AWADDR20": "PS7_MAXIGP0AWADDR20", - "MAXIGP0AWADDR21": "PS7_MAXIGP0AWADDR21", - "MAXIGP0AWADDR22": "PS7_MAXIGP0AWADDR22", - "MAXIGP0AWADDR23": "PS7_MAXIGP0AWADDR23", - "MAXIGP0AWADDR24": "PS7_MAXIGP0AWADDR24", - "MAXIGP0AWADDR25": "PS7_MAXIGP0AWADDR25", - "MAXIGP0AWADDR26": "PS7_MAXIGP0AWADDR26", - "MAXIGP0AWADDR27": "PS7_MAXIGP0AWADDR27", - "MAXIGP0AWADDR28": "PS7_MAXIGP0AWADDR28", - "MAXIGP0AWADDR29": "PS7_MAXIGP0AWADDR29", - "MAXIGP0AWADDR3": "PS7_MAXIGP0AWADDR3", - "MAXIGP0AWADDR30": "PS7_MAXIGP0AWADDR30", - "MAXIGP0AWADDR31": "PS7_MAXIGP0AWADDR31", - "MAXIGP0AWADDR4": "PS7_MAXIGP0AWADDR4", - "MAXIGP0AWADDR5": "PS7_MAXIGP0AWADDR5", - "MAXIGP0AWADDR6": "PS7_MAXIGP0AWADDR6", - "MAXIGP0AWADDR7": "PS7_MAXIGP0AWADDR7", - "MAXIGP0AWADDR8": "PS7_MAXIGP0AWADDR8", - "MAXIGP0AWADDR9": "PS7_MAXIGP0AWADDR9", - "MAXIGP0AWBURST0": "PS7_MAXIGP0AWBURST0", - "MAXIGP0AWBURST1": "PS7_MAXIGP0AWBURST1", - "MAXIGP0AWCACHE0": "PS7_MAXIGP0AWCACHE0", - "MAXIGP0AWCACHE1": "PS7_MAXIGP0AWCACHE1", - "MAXIGP0AWCACHE2": "PS7_MAXIGP0AWCACHE2", - "MAXIGP0AWCACHE3": "PS7_MAXIGP0AWCACHE3", - "MAXIGP0AWID0": "PS7_MAXIGP0AWID0", - "MAXIGP0AWID1": "PS7_MAXIGP0AWID1", - "MAXIGP0AWID10": "PS7_MAXIGP0AWID10", - "MAXIGP0AWID11": "PS7_MAXIGP0AWID11", - "MAXIGP0AWID2": "PS7_MAXIGP0AWID2", - "MAXIGP0AWID3": "PS7_MAXIGP0AWID3", - "MAXIGP0AWID4": "PS7_MAXIGP0AWID4", - "MAXIGP0AWID5": "PS7_MAXIGP0AWID5", - "MAXIGP0AWID6": "PS7_MAXIGP0AWID6", - "MAXIGP0AWID7": "PS7_MAXIGP0AWID7", - "MAXIGP0AWID8": "PS7_MAXIGP0AWID8", - "MAXIGP0AWID9": "PS7_MAXIGP0AWID9", - "MAXIGP0AWLEN0": "PS7_MAXIGP0AWLEN0", - "MAXIGP0AWLEN1": "PS7_MAXIGP0AWLEN1", - "MAXIGP0AWLEN2": "PS7_MAXIGP0AWLEN2", - "MAXIGP0AWLEN3": "PS7_MAXIGP0AWLEN3", - "MAXIGP0AWLOCK0": "PS7_MAXIGP0AWLOCK0", - "MAXIGP0AWLOCK1": "PS7_MAXIGP0AWLOCK1", - "MAXIGP0AWPROT0": "PS7_MAXIGP0AWPROT0", - "MAXIGP0AWPROT1": "PS7_MAXIGP0AWPROT1", - "MAXIGP0AWPROT2": "PS7_MAXIGP0AWPROT2", - "MAXIGP0AWQOS0": "PS7_MAXIGP0AWQOS0", - "MAXIGP0AWQOS1": "PS7_MAXIGP0AWQOS1", - "MAXIGP0AWQOS2": "PS7_MAXIGP0AWQOS2", - "MAXIGP0AWQOS3": "PS7_MAXIGP0AWQOS3", - "MAXIGP0AWREADY": "PS7_MAXIGP0AWREADY", - "MAXIGP0AWSIZE0": "PS7_MAXIGP0AWSIZE0", - "MAXIGP0AWSIZE1": "PS7_MAXIGP0AWSIZE1", - "MAXIGP0AWVALID": "PS7_MAXIGP0AWVALID", - "MAXIGP0BID0": "PS7_MAXIGP0BID0", - "MAXIGP0BID1": "PS7_MAXIGP0BID1", - "MAXIGP0BID10": "PS7_MAXIGP0BID10", - "MAXIGP0BID11": "PS7_MAXIGP0BID11", - "MAXIGP0BID2": "PS7_MAXIGP0BID2", - "MAXIGP0BID3": "PS7_MAXIGP0BID3", - "MAXIGP0BID4": "PS7_MAXIGP0BID4", - "MAXIGP0BID5": "PS7_MAXIGP0BID5", - "MAXIGP0BID6": "PS7_MAXIGP0BID6", - "MAXIGP0BID7": "PS7_MAXIGP0BID7", - "MAXIGP0BID8": "PS7_MAXIGP0BID8", - "MAXIGP0BID9": "PS7_MAXIGP0BID9", - "MAXIGP0BREADY": "PS7_MAXIGP0BREADY", - "MAXIGP0BRESP0": "PS7_MAXIGP0BRESP0", - "MAXIGP0BRESP1": "PS7_MAXIGP0BRESP1", - "MAXIGP0BVALID": "PS7_MAXIGP0BVALID", - "MAXIGP0RDATA0": "PS7_MAXIGP0RDATA0", - "MAXIGP0RDATA1": "PS7_MAXIGP0RDATA1", - "MAXIGP0RDATA10": "PS7_MAXIGP0RDATA10", - "MAXIGP0RDATA11": "PS7_MAXIGP0RDATA11", - "MAXIGP0RDATA12": "PS7_MAXIGP0RDATA12", - "MAXIGP0RDATA13": "PS7_MAXIGP0RDATA13", - "MAXIGP0RDATA14": "PS7_MAXIGP0RDATA14", - "MAXIGP0RDATA15": "PS7_MAXIGP0RDATA15", - "MAXIGP0RDATA16": "PS7_MAXIGP0RDATA16", - "MAXIGP0RDATA17": "PS7_MAXIGP0RDATA17", - "MAXIGP0RDATA18": "PS7_MAXIGP0RDATA18", - "MAXIGP0RDATA19": "PS7_MAXIGP0RDATA19", - "MAXIGP0RDATA2": "PS7_MAXIGP0RDATA2", - "MAXIGP0RDATA20": "PS7_MAXIGP0RDATA20", - "MAXIGP0RDATA21": "PS7_MAXIGP0RDATA21", - "MAXIGP0RDATA22": "PS7_MAXIGP0RDATA22", - "MAXIGP0RDATA23": "PS7_MAXIGP0RDATA23", - "MAXIGP0RDATA24": "PS7_MAXIGP0RDATA24", - "MAXIGP0RDATA25": "PS7_MAXIGP0RDATA25", - "MAXIGP0RDATA26": "PS7_MAXIGP0RDATA26", - "MAXIGP0RDATA27": "PS7_MAXIGP0RDATA27", - "MAXIGP0RDATA28": "PS7_MAXIGP0RDATA28", - "MAXIGP0RDATA29": "PS7_MAXIGP0RDATA29", - "MAXIGP0RDATA3": "PS7_MAXIGP0RDATA3", - "MAXIGP0RDATA30": "PS7_MAXIGP0RDATA30", - "MAXIGP0RDATA31": "PS7_MAXIGP0RDATA31", - "MAXIGP0RDATA4": "PS7_MAXIGP0RDATA4", - "MAXIGP0RDATA5": "PS7_MAXIGP0RDATA5", - "MAXIGP0RDATA6": "PS7_MAXIGP0RDATA6", - "MAXIGP0RDATA7": "PS7_MAXIGP0RDATA7", - "MAXIGP0RDATA8": "PS7_MAXIGP0RDATA8", - "MAXIGP0RDATA9": "PS7_MAXIGP0RDATA9", - "MAXIGP0RID0": "PS7_MAXIGP0RID0", - "MAXIGP0RID1": "PS7_MAXIGP0RID1", - "MAXIGP0RID10": "PS7_MAXIGP0RID10", - "MAXIGP0RID11": "PS7_MAXIGP0RID11", - "MAXIGP0RID2": "PS7_MAXIGP0RID2", - "MAXIGP0RID3": "PS7_MAXIGP0RID3", - "MAXIGP0RID4": "PS7_MAXIGP0RID4", - "MAXIGP0RID5": "PS7_MAXIGP0RID5", - "MAXIGP0RID6": "PS7_MAXIGP0RID6", - "MAXIGP0RID7": "PS7_MAXIGP0RID7", - "MAXIGP0RID8": "PS7_MAXIGP0RID8", - "MAXIGP0RID9": "PS7_MAXIGP0RID9", - "MAXIGP0RLAST": "PS7_MAXIGP0RLAST", - "MAXIGP0RREADY": "PS7_MAXIGP0RREADY", - "MAXIGP0RRESP0": "PS7_MAXIGP0RRESP0", - "MAXIGP0RRESP1": "PS7_MAXIGP0RRESP1", - "MAXIGP0RVALID": "PS7_MAXIGP0RVALID", - "MAXIGP0WDATA0": "PS7_MAXIGP0WDATA0", - "MAXIGP0WDATA1": "PS7_MAXIGP0WDATA1", - "MAXIGP0WDATA10": "PS7_MAXIGP0WDATA10", - "MAXIGP0WDATA11": "PS7_MAXIGP0WDATA11", - "MAXIGP0WDATA12": "PS7_MAXIGP0WDATA12", - "MAXIGP0WDATA13": "PS7_MAXIGP0WDATA13", - "MAXIGP0WDATA14": "PS7_MAXIGP0WDATA14", - "MAXIGP0WDATA15": "PS7_MAXIGP0WDATA15", - "MAXIGP0WDATA16": "PS7_MAXIGP0WDATA16", - "MAXIGP0WDATA17": "PS7_MAXIGP0WDATA17", - "MAXIGP0WDATA18": "PS7_MAXIGP0WDATA18", - "MAXIGP0WDATA19": "PS7_MAXIGP0WDATA19", - "MAXIGP0WDATA2": "PS7_MAXIGP0WDATA2", - "MAXIGP0WDATA20": "PS7_MAXIGP0WDATA20", - "MAXIGP0WDATA21": "PS7_MAXIGP0WDATA21", - "MAXIGP0WDATA22": "PS7_MAXIGP0WDATA22", - "MAXIGP0WDATA23": "PS7_MAXIGP0WDATA23", - "MAXIGP0WDATA24": "PS7_MAXIGP0WDATA24", - "MAXIGP0WDATA25": "PS7_MAXIGP0WDATA25", - "MAXIGP0WDATA26": "PS7_MAXIGP0WDATA26", - "MAXIGP0WDATA27": "PS7_MAXIGP0WDATA27", - "MAXIGP0WDATA28": "PS7_MAXIGP0WDATA28", - "MAXIGP0WDATA29": "PS7_MAXIGP0WDATA29", - "MAXIGP0WDATA3": "PS7_MAXIGP0WDATA3", - "MAXIGP0WDATA30": "PS7_MAXIGP0WDATA30", - "MAXIGP0WDATA31": "PS7_MAXIGP0WDATA31", - "MAXIGP0WDATA4": "PS7_MAXIGP0WDATA4", - "MAXIGP0WDATA5": "PS7_MAXIGP0WDATA5", - "MAXIGP0WDATA6": "PS7_MAXIGP0WDATA6", - "MAXIGP0WDATA7": "PS7_MAXIGP0WDATA7", - "MAXIGP0WDATA8": "PS7_MAXIGP0WDATA8", - "MAXIGP0WDATA9": "PS7_MAXIGP0WDATA9", - "MAXIGP0WID0": "PS7_MAXIGP0WID0", - "MAXIGP0WID1": "PS7_MAXIGP0WID1", - "MAXIGP0WID10": "PS7_MAXIGP0WID10", - "MAXIGP0WID11": "PS7_MAXIGP0WID11", - "MAXIGP0WID2": "PS7_MAXIGP0WID2", - "MAXIGP0WID3": "PS7_MAXIGP0WID3", - "MAXIGP0WID4": "PS7_MAXIGP0WID4", - "MAXIGP0WID5": "PS7_MAXIGP0WID5", - "MAXIGP0WID6": "PS7_MAXIGP0WID6", - "MAXIGP0WID7": "PS7_MAXIGP0WID7", - "MAXIGP0WID8": "PS7_MAXIGP0WID8", - "MAXIGP0WID9": "PS7_MAXIGP0WID9", - "MAXIGP0WLAST": "PS7_MAXIGP0WLAST", - "MAXIGP0WREADY": "PS7_MAXIGP0WREADY", - "MAXIGP0WSTRB0": "PS7_MAXIGP0WSTRB0", - "MAXIGP0WSTRB1": "PS7_MAXIGP0WSTRB1", - "MAXIGP0WSTRB2": "PS7_MAXIGP0WSTRB2", - "MAXIGP0WSTRB3": "PS7_MAXIGP0WSTRB3", - "MAXIGP0WVALID": "PS7_MAXIGP0WVALID", - "MAXIGP1ACLK": "PS7_MAXIGP1ACLK", - "MAXIGP1ARADDR0": "PS7_MAXIGP1ARADDR0", - "MAXIGP1ARADDR1": "PS7_MAXIGP1ARADDR1", - "MAXIGP1ARADDR10": "PS7_MAXIGP1ARADDR10", - "MAXIGP1ARADDR11": "PS7_MAXIGP1ARADDR11", - "MAXIGP1ARADDR12": "PS7_MAXIGP1ARADDR12", - "MAXIGP1ARADDR13": "PS7_MAXIGP1ARADDR13", - "MAXIGP1ARADDR14": "PS7_MAXIGP1ARADDR14", - "MAXIGP1ARADDR15": "PS7_MAXIGP1ARADDR15", - "MAXIGP1ARADDR16": "PS7_MAXIGP1ARADDR16", - "MAXIGP1ARADDR17": "PS7_MAXIGP1ARADDR17", - "MAXIGP1ARADDR18": "PS7_MAXIGP1ARADDR18", - "MAXIGP1ARADDR19": "PS7_MAXIGP1ARADDR19", - "MAXIGP1ARADDR2": "PS7_MAXIGP1ARADDR2", - "MAXIGP1ARADDR20": "PS7_MAXIGP1ARADDR20", - "MAXIGP1ARADDR21": "PS7_MAXIGP1ARADDR21", - "MAXIGP1ARADDR22": "PS7_MAXIGP1ARADDR22", - "MAXIGP1ARADDR23": "PS7_MAXIGP1ARADDR23", - "MAXIGP1ARADDR24": "PS7_MAXIGP1ARADDR24", - "MAXIGP1ARADDR25": "PS7_MAXIGP1ARADDR25", - "MAXIGP1ARADDR26": "PS7_MAXIGP1ARADDR26", - "MAXIGP1ARADDR27": "PS7_MAXIGP1ARADDR27", - "MAXIGP1ARADDR28": "PS7_MAXIGP1ARADDR28", - "MAXIGP1ARADDR29": "PS7_MAXIGP1ARADDR29", - "MAXIGP1ARADDR3": "PS7_MAXIGP1ARADDR3", - "MAXIGP1ARADDR30": "PS7_MAXIGP1ARADDR30", - "MAXIGP1ARADDR31": "PS7_MAXIGP1ARADDR31", - "MAXIGP1ARADDR4": "PS7_MAXIGP1ARADDR4", - "MAXIGP1ARADDR5": "PS7_MAXIGP1ARADDR5", - "MAXIGP1ARADDR6": "PS7_MAXIGP1ARADDR6", - "MAXIGP1ARADDR7": "PS7_MAXIGP1ARADDR7", - "MAXIGP1ARADDR8": "PS7_MAXIGP1ARADDR8", - "MAXIGP1ARADDR9": "PS7_MAXIGP1ARADDR9", - "MAXIGP1ARBURST0": "PS7_MAXIGP1ARBURST0", - "MAXIGP1ARBURST1": "PS7_MAXIGP1ARBURST1", - "MAXIGP1ARCACHE0": "PS7_MAXIGP1ARCACHE0", - "MAXIGP1ARCACHE1": "PS7_MAXIGP1ARCACHE1", - "MAXIGP1ARCACHE2": "PS7_MAXIGP1ARCACHE2", - "MAXIGP1ARCACHE3": "PS7_MAXIGP1ARCACHE3", - "MAXIGP1ARESETN": "PS7_MAXIGP1ARESETN", - "MAXIGP1ARID0": "PS7_MAXIGP1ARID0", - "MAXIGP1ARID1": "PS7_MAXIGP1ARID1", - "MAXIGP1ARID10": "PS7_MAXIGP1ARID10", - "MAXIGP1ARID11": "PS7_MAXIGP1ARID11", - "MAXIGP1ARID2": "PS7_MAXIGP1ARID2", - "MAXIGP1ARID3": "PS7_MAXIGP1ARID3", - "MAXIGP1ARID4": "PS7_MAXIGP1ARID4", - "MAXIGP1ARID5": "PS7_MAXIGP1ARID5", - "MAXIGP1ARID6": "PS7_MAXIGP1ARID6", - "MAXIGP1ARID7": "PS7_MAXIGP1ARID7", - "MAXIGP1ARID8": "PS7_MAXIGP1ARID8", - "MAXIGP1ARID9": "PS7_MAXIGP1ARID9", - "MAXIGP1ARLEN0": "PS7_MAXIGP1ARLEN0", - "MAXIGP1ARLEN1": "PS7_MAXIGP1ARLEN1", - "MAXIGP1ARLEN2": "PS7_MAXIGP1ARLEN2", - "MAXIGP1ARLEN3": "PS7_MAXIGP1ARLEN3", - "MAXIGP1ARLOCK0": "PS7_MAXIGP1ARLOCK0", - "MAXIGP1ARLOCK1": "PS7_MAXIGP1ARLOCK1", - "MAXIGP1ARPROT0": "PS7_MAXIGP1ARPROT0", - "MAXIGP1ARPROT1": "PS7_MAXIGP1ARPROT1", - "MAXIGP1ARPROT2": "PS7_MAXIGP1ARPROT2", - "MAXIGP1ARQOS0": "PS7_MAXIGP1ARQOS0", - "MAXIGP1ARQOS1": "PS7_MAXIGP1ARQOS1", - "MAXIGP1ARQOS2": "PS7_MAXIGP1ARQOS2", - "MAXIGP1ARQOS3": "PS7_MAXIGP1ARQOS3", - "MAXIGP1ARREADY": "PS7_MAXIGP1ARREADY", - "MAXIGP1ARSIZE0": "PS7_MAXIGP1ARSIZE0", - "MAXIGP1ARSIZE1": "PS7_MAXIGP1ARSIZE1", - "MAXIGP1ARVALID": "PS7_MAXIGP1ARVALID", - "MAXIGP1AWADDR0": "PS7_MAXIGP1AWADDR0", - "MAXIGP1AWADDR1": "PS7_MAXIGP1AWADDR1", - "MAXIGP1AWADDR10": "PS7_MAXIGP1AWADDR10", - "MAXIGP1AWADDR11": "PS7_MAXIGP1AWADDR11", - "MAXIGP1AWADDR12": "PS7_MAXIGP1AWADDR12", - "MAXIGP1AWADDR13": "PS7_MAXIGP1AWADDR13", - "MAXIGP1AWADDR14": "PS7_MAXIGP1AWADDR14", - "MAXIGP1AWADDR15": "PS7_MAXIGP1AWADDR15", - "MAXIGP1AWADDR16": "PS7_MAXIGP1AWADDR16", - "MAXIGP1AWADDR17": "PS7_MAXIGP1AWADDR17", - "MAXIGP1AWADDR18": "PS7_MAXIGP1AWADDR18", - "MAXIGP1AWADDR19": "PS7_MAXIGP1AWADDR19", - "MAXIGP1AWADDR2": "PS7_MAXIGP1AWADDR2", - "MAXIGP1AWADDR20": "PS7_MAXIGP1AWADDR20", - "MAXIGP1AWADDR21": "PS7_MAXIGP1AWADDR21", - "MAXIGP1AWADDR22": "PS7_MAXIGP1AWADDR22", - "MAXIGP1AWADDR23": "PS7_MAXIGP1AWADDR23", - "MAXIGP1AWADDR24": "PS7_MAXIGP1AWADDR24", - "MAXIGP1AWADDR25": "PS7_MAXIGP1AWADDR25", - "MAXIGP1AWADDR26": "PS7_MAXIGP1AWADDR26", - "MAXIGP1AWADDR27": "PS7_MAXIGP1AWADDR27", - "MAXIGP1AWADDR28": "PS7_MAXIGP1AWADDR28", - "MAXIGP1AWADDR29": "PS7_MAXIGP1AWADDR29", - "MAXIGP1AWADDR3": "PS7_MAXIGP1AWADDR3", - "MAXIGP1AWADDR30": "PS7_MAXIGP1AWADDR30", - "MAXIGP1AWADDR31": "PS7_MAXIGP1AWADDR31", - "MAXIGP1AWADDR4": "PS7_MAXIGP1AWADDR4", - "MAXIGP1AWADDR5": "PS7_MAXIGP1AWADDR5", - "MAXIGP1AWADDR6": "PS7_MAXIGP1AWADDR6", - "MAXIGP1AWADDR7": "PS7_MAXIGP1AWADDR7", - "MAXIGP1AWADDR8": "PS7_MAXIGP1AWADDR8", - "MAXIGP1AWADDR9": "PS7_MAXIGP1AWADDR9", - "MAXIGP1AWBURST0": "PS7_MAXIGP1AWBURST0", - "MAXIGP1AWBURST1": "PS7_MAXIGP1AWBURST1", - "MAXIGP1AWCACHE0": "PS7_MAXIGP1AWCACHE0", - "MAXIGP1AWCACHE1": "PS7_MAXIGP1AWCACHE1", - "MAXIGP1AWCACHE2": "PS7_MAXIGP1AWCACHE2", - "MAXIGP1AWCACHE3": "PS7_MAXIGP1AWCACHE3", - "MAXIGP1AWID0": "PS7_MAXIGP1AWID0", - "MAXIGP1AWID1": "PS7_MAXIGP1AWID1", - "MAXIGP1AWID10": "PS7_MAXIGP1AWID10", - "MAXIGP1AWID11": "PS7_MAXIGP1AWID11", - "MAXIGP1AWID2": "PS7_MAXIGP1AWID2", - "MAXIGP1AWID3": "PS7_MAXIGP1AWID3", - "MAXIGP1AWID4": "PS7_MAXIGP1AWID4", - "MAXIGP1AWID5": "PS7_MAXIGP1AWID5", - "MAXIGP1AWID6": "PS7_MAXIGP1AWID6", - "MAXIGP1AWID7": "PS7_MAXIGP1AWID7", - "MAXIGP1AWID8": "PS7_MAXIGP1AWID8", - "MAXIGP1AWID9": "PS7_MAXIGP1AWID9", - "MAXIGP1AWLEN0": "PS7_MAXIGP1AWLEN0", - "MAXIGP1AWLEN1": "PS7_MAXIGP1AWLEN1", - "MAXIGP1AWLEN2": "PS7_MAXIGP1AWLEN2", - "MAXIGP1AWLEN3": "PS7_MAXIGP1AWLEN3", - "MAXIGP1AWLOCK0": "PS7_MAXIGP1AWLOCK0", - "MAXIGP1AWLOCK1": "PS7_MAXIGP1AWLOCK1", - "MAXIGP1AWPROT0": "PS7_MAXIGP1AWPROT0", - "MAXIGP1AWPROT1": "PS7_MAXIGP1AWPROT1", - "MAXIGP1AWPROT2": "PS7_MAXIGP1AWPROT2", - "MAXIGP1AWQOS0": "PS7_MAXIGP1AWQOS0", - "MAXIGP1AWQOS1": "PS7_MAXIGP1AWQOS1", - "MAXIGP1AWQOS2": "PS7_MAXIGP1AWQOS2", - "MAXIGP1AWQOS3": "PS7_MAXIGP1AWQOS3", - "MAXIGP1AWREADY": "PS7_MAXIGP1AWREADY", - "MAXIGP1AWSIZE0": "PS7_MAXIGP1AWSIZE0", - "MAXIGP1AWSIZE1": "PS7_MAXIGP1AWSIZE1", - "MAXIGP1AWVALID": "PS7_MAXIGP1AWVALID", - "MAXIGP1BID0": "PS7_MAXIGP1BID0", - "MAXIGP1BID1": "PS7_MAXIGP1BID1", - "MAXIGP1BID10": "PS7_MAXIGP1BID10", - "MAXIGP1BID11": "PS7_MAXIGP1BID11", - "MAXIGP1BID2": "PS7_MAXIGP1BID2", - "MAXIGP1BID3": "PS7_MAXIGP1BID3", - "MAXIGP1BID4": "PS7_MAXIGP1BID4", - "MAXIGP1BID5": "PS7_MAXIGP1BID5", - "MAXIGP1BID6": "PS7_MAXIGP1BID6", - "MAXIGP1BID7": "PS7_MAXIGP1BID7", - "MAXIGP1BID8": "PS7_MAXIGP1BID8", - "MAXIGP1BID9": "PS7_MAXIGP1BID9", - "MAXIGP1BREADY": "PS7_MAXIGP1BREADY", - "MAXIGP1BRESP0": "PS7_MAXIGP1BRESP0", - "MAXIGP1BRESP1": "PS7_MAXIGP1BRESP1", - "MAXIGP1BVALID": "PS7_MAXIGP1BVALID", - "MAXIGP1RDATA0": "PS7_MAXIGP1RDATA0", - "MAXIGP1RDATA1": "PS7_MAXIGP1RDATA1", - "MAXIGP1RDATA10": "PS7_MAXIGP1RDATA10", - "MAXIGP1RDATA11": "PS7_MAXIGP1RDATA11", - "MAXIGP1RDATA12": "PS7_MAXIGP1RDATA12", - "MAXIGP1RDATA13": "PS7_MAXIGP1RDATA13", - "MAXIGP1RDATA14": "PS7_MAXIGP1RDATA14", - "MAXIGP1RDATA15": "PS7_MAXIGP1RDATA15", - "MAXIGP1RDATA16": "PS7_MAXIGP1RDATA16", - "MAXIGP1RDATA17": "PS7_MAXIGP1RDATA17", - "MAXIGP1RDATA18": "PS7_MAXIGP1RDATA18", - "MAXIGP1RDATA19": "PS7_MAXIGP1RDATA19", - "MAXIGP1RDATA2": "PS7_MAXIGP1RDATA2", - "MAXIGP1RDATA20": "PS7_MAXIGP1RDATA20", - "MAXIGP1RDATA21": "PS7_MAXIGP1RDATA21", - "MAXIGP1RDATA22": "PS7_MAXIGP1RDATA22", - "MAXIGP1RDATA23": "PS7_MAXIGP1RDATA23", - "MAXIGP1RDATA24": "PS7_MAXIGP1RDATA24", - "MAXIGP1RDATA25": "PS7_MAXIGP1RDATA25", - "MAXIGP1RDATA26": "PS7_MAXIGP1RDATA26", - "MAXIGP1RDATA27": "PS7_MAXIGP1RDATA27", - "MAXIGP1RDATA28": "PS7_MAXIGP1RDATA28", - "MAXIGP1RDATA29": "PS7_MAXIGP1RDATA29", - "MAXIGP1RDATA3": "PS7_MAXIGP1RDATA3", - "MAXIGP1RDATA30": "PS7_MAXIGP1RDATA30", - "MAXIGP1RDATA31": "PS7_MAXIGP1RDATA31", - "MAXIGP1RDATA4": "PS7_MAXIGP1RDATA4", - "MAXIGP1RDATA5": "PS7_MAXIGP1RDATA5", - "MAXIGP1RDATA6": "PS7_MAXIGP1RDATA6", - "MAXIGP1RDATA7": "PS7_MAXIGP1RDATA7", - "MAXIGP1RDATA8": "PS7_MAXIGP1RDATA8", - "MAXIGP1RDATA9": "PS7_MAXIGP1RDATA9", - "MAXIGP1RID0": "PS7_MAXIGP1RID0", - "MAXIGP1RID1": "PS7_MAXIGP1RID1", - "MAXIGP1RID10": "PS7_MAXIGP1RID10", - "MAXIGP1RID11": "PS7_MAXIGP1RID11", - "MAXIGP1RID2": "PS7_MAXIGP1RID2", - "MAXIGP1RID3": "PS7_MAXIGP1RID3", - "MAXIGP1RID4": "PS7_MAXIGP1RID4", - "MAXIGP1RID5": "PS7_MAXIGP1RID5", - "MAXIGP1RID6": "PS7_MAXIGP1RID6", - "MAXIGP1RID7": "PS7_MAXIGP1RID7", - "MAXIGP1RID8": "PS7_MAXIGP1RID8", - "MAXIGP1RID9": "PS7_MAXIGP1RID9", - "MAXIGP1RLAST": "PS7_MAXIGP1RLAST", - "MAXIGP1RREADY": "PS7_MAXIGP1RREADY", - "MAXIGP1RRESP0": "PS7_MAXIGP1RRESP0", - "MAXIGP1RRESP1": "PS7_MAXIGP1RRESP1", - "MAXIGP1RVALID": "PS7_MAXIGP1RVALID", - "MAXIGP1WDATA0": "PS7_MAXIGP1WDATA0", - "MAXIGP1WDATA1": "PS7_MAXIGP1WDATA1", - "MAXIGP1WDATA10": "PS7_MAXIGP1WDATA10", - "MAXIGP1WDATA11": "PS7_MAXIGP1WDATA11", - "MAXIGP1WDATA12": "PS7_MAXIGP1WDATA12", - "MAXIGP1WDATA13": "PS7_MAXIGP1WDATA13", - "MAXIGP1WDATA14": "PS7_MAXIGP1WDATA14", - "MAXIGP1WDATA15": "PS7_MAXIGP1WDATA15", - "MAXIGP1WDATA16": "PS7_MAXIGP1WDATA16", - "MAXIGP1WDATA17": "PS7_MAXIGP1WDATA17", - "MAXIGP1WDATA18": "PS7_MAXIGP1WDATA18", - "MAXIGP1WDATA19": "PS7_MAXIGP1WDATA19", - "MAXIGP1WDATA2": "PS7_MAXIGP1WDATA2", - "MAXIGP1WDATA20": "PS7_MAXIGP1WDATA20", - "MAXIGP1WDATA21": "PS7_MAXIGP1WDATA21", - "MAXIGP1WDATA22": "PS7_MAXIGP1WDATA22", - "MAXIGP1WDATA23": "PS7_MAXIGP1WDATA23", - "MAXIGP1WDATA24": "PS7_MAXIGP1WDATA24", - "MAXIGP1WDATA25": "PS7_MAXIGP1WDATA25", - "MAXIGP1WDATA26": "PS7_MAXIGP1WDATA26", - "MAXIGP1WDATA27": "PS7_MAXIGP1WDATA27", - "MAXIGP1WDATA28": "PS7_MAXIGP1WDATA28", - "MAXIGP1WDATA29": "PS7_MAXIGP1WDATA29", - "MAXIGP1WDATA3": "PS7_MAXIGP1WDATA3", - "MAXIGP1WDATA30": "PS7_MAXIGP1WDATA30", - "MAXIGP1WDATA31": "PS7_MAXIGP1WDATA31", - "MAXIGP1WDATA4": "PS7_MAXIGP1WDATA4", - "MAXIGP1WDATA5": "PS7_MAXIGP1WDATA5", - "MAXIGP1WDATA6": "PS7_MAXIGP1WDATA6", - "MAXIGP1WDATA7": "PS7_MAXIGP1WDATA7", - "MAXIGP1WDATA8": "PS7_MAXIGP1WDATA8", - "MAXIGP1WDATA9": "PS7_MAXIGP1WDATA9", - "MAXIGP1WID0": "PS7_MAXIGP1WID0", - "MAXIGP1WID1": "PS7_MAXIGP1WID1", - "MAXIGP1WID10": "PS7_MAXIGP1WID10", - "MAXIGP1WID11": "PS7_MAXIGP1WID11", - "MAXIGP1WID2": "PS7_MAXIGP1WID2", - "MAXIGP1WID3": "PS7_MAXIGP1WID3", - "MAXIGP1WID4": "PS7_MAXIGP1WID4", - "MAXIGP1WID5": "PS7_MAXIGP1WID5", - "MAXIGP1WID6": "PS7_MAXIGP1WID6", - "MAXIGP1WID7": "PS7_MAXIGP1WID7", - "MAXIGP1WID8": "PS7_MAXIGP1WID8", - "MAXIGP1WID9": "PS7_MAXIGP1WID9", - "MAXIGP1WLAST": "PS7_MAXIGP1WLAST", - "MAXIGP1WREADY": "PS7_MAXIGP1WREADY", - "MAXIGP1WSTRB0": "PS7_MAXIGP1WSTRB0", - "MAXIGP1WSTRB1": "PS7_MAXIGP1WSTRB1", - "MAXIGP1WSTRB2": "PS7_MAXIGP1WSTRB2", - "MAXIGP1WSTRB3": "PS7_MAXIGP1WSTRB3", - "MAXIGP1WVALID": "PS7_MAXIGP1WVALID", - "MIO0": "PS7_MIO0", - "MIO1": "PS7_MIO1", - "MIO10": "PS7_MIO10", - "MIO11": "PS7_MIO11", - "MIO12": "PS7_MIO12", - "MIO13": "PS7_MIO13", - "MIO14": "PS7_MIO14", - "MIO15": "PS7_MIO15", - "MIO16": "PS7_MIO16", - "MIO17": "PS7_MIO17", - "MIO18": "PS7_MIO18", - "MIO19": "PS7_MIO19", - "MIO2": "PS7_MIO2", - "MIO20": "PS7_MIO20", - "MIO21": "PS7_MIO21", - "MIO22": "PS7_MIO22", - "MIO23": "PS7_MIO23", - "MIO24": "PS7_MIO24", - "MIO25": "PS7_MIO25", - "MIO26": "PS7_MIO26", - "MIO27": "PS7_MIO27", - "MIO28": "PS7_MIO28", - "MIO29": "PS7_MIO29", - "MIO3": "PS7_MIO3", - "MIO30": "PS7_MIO30", - "MIO31": "PS7_MIO31", - "MIO32": "PS7_MIO32", - "MIO33": "PS7_MIO33", - "MIO34": "PS7_MIO34", - "MIO35": "PS7_MIO35", - "MIO36": "PS7_MIO36", - "MIO37": "PS7_MIO37", - "MIO38": "PS7_MIO38", - "MIO39": "PS7_MIO39", - "MIO4": "PS7_MIO4", - "MIO40": "PS7_MIO40", - "MIO41": "PS7_MIO41", - "MIO42": "PS7_MIO42", - "MIO43": "PS7_MIO43", - "MIO44": "PS7_MIO44", - "MIO45": "PS7_MIO45", - "MIO46": "PS7_MIO46", - "MIO47": "PS7_MIO47", - "MIO48": "PS7_MIO48", - "MIO49": "PS7_MIO49", - "MIO5": "PS7_MIO5", - "MIO50": "PS7_MIO50", - "MIO51": "PS7_MIO51", - "MIO52": "PS7_MIO52", - "MIO53": "PS7_MIO53", - "MIO6": "PS7_MIO6", - "MIO7": "PS7_MIO7", - "MIO8": "PS7_MIO8", - "MIO9": "PS7_MIO9", - "PSCLK": "PS7_PSCLK", - "PSPORB": "PS7_PSPORB", - "PSSRSTB": "PS7_PSSRSTB", - "SAXIACPACLK": "PS7_SAXIACPACLK", - "SAXIACPARADDR0": "PS7_SAXIACPARADDR0", - "SAXIACPARADDR1": "PS7_SAXIACPARADDR1", - "SAXIACPARADDR10": "PS7_SAXIACPARADDR10", - "SAXIACPARADDR11": "PS7_SAXIACPARADDR11", - "SAXIACPARADDR12": "PS7_SAXIACPARADDR12", - "SAXIACPARADDR13": "PS7_SAXIACPARADDR13", - "SAXIACPARADDR14": "PS7_SAXIACPARADDR14", - "SAXIACPARADDR15": "PS7_SAXIACPARADDR15", - "SAXIACPARADDR16": "PS7_SAXIACPARADDR16", - "SAXIACPARADDR17": "PS7_SAXIACPARADDR17", - "SAXIACPARADDR18": "PS7_SAXIACPARADDR18", - "SAXIACPARADDR19": "PS7_SAXIACPARADDR19", - "SAXIACPARADDR2": "PS7_SAXIACPARADDR2", - "SAXIACPARADDR20": "PS7_SAXIACPARADDR20", - "SAXIACPARADDR21": "PS7_SAXIACPARADDR21", - "SAXIACPARADDR22": "PS7_SAXIACPARADDR22", - "SAXIACPARADDR23": "PS7_SAXIACPARADDR23", - "SAXIACPARADDR24": "PS7_SAXIACPARADDR24", - "SAXIACPARADDR25": "PS7_SAXIACPARADDR25", - "SAXIACPARADDR26": "PS7_SAXIACPARADDR26", - "SAXIACPARADDR27": "PS7_SAXIACPARADDR27", - "SAXIACPARADDR28": "PS7_SAXIACPARADDR28", - "SAXIACPARADDR29": "PS7_SAXIACPARADDR29", - "SAXIACPARADDR3": "PS7_SAXIACPARADDR3", - "SAXIACPARADDR30": "PS7_SAXIACPARADDR30", - "SAXIACPARADDR31": "PS7_SAXIACPARADDR31", - "SAXIACPARADDR4": "PS7_SAXIACPARADDR4", - "SAXIACPARADDR5": "PS7_SAXIACPARADDR5", - "SAXIACPARADDR6": "PS7_SAXIACPARADDR6", - "SAXIACPARADDR7": "PS7_SAXIACPARADDR7", - "SAXIACPARADDR8": "PS7_SAXIACPARADDR8", - "SAXIACPARADDR9": "PS7_SAXIACPARADDR9", - "SAXIACPARBURST0": "PS7_SAXIACPARBURST0", - "SAXIACPARBURST1": "PS7_SAXIACPARBURST1", - "SAXIACPARCACHE0": "PS7_SAXIACPARCACHE0", - "SAXIACPARCACHE1": "PS7_SAXIACPARCACHE1", - "SAXIACPARCACHE2": "PS7_SAXIACPARCACHE2", - "SAXIACPARCACHE3": "PS7_SAXIACPARCACHE3", - "SAXIACPARESETN": "PS7_SAXIACPARESETN", - "SAXIACPARID0": "PS7_SAXIACPARID0", - "SAXIACPARID1": "PS7_SAXIACPARID1", - "SAXIACPARID2": "PS7_SAXIACPARID2", - "SAXIACPARLEN0": "PS7_SAXIACPARLEN0", - "SAXIACPARLEN1": "PS7_SAXIACPARLEN1", - "SAXIACPARLEN2": "PS7_SAXIACPARLEN2", - "SAXIACPARLEN3": "PS7_SAXIACPARLEN3", - "SAXIACPARLOCK0": "PS7_SAXIACPARLOCK0", - "SAXIACPARLOCK1": "PS7_SAXIACPARLOCK1", - "SAXIACPARPROT0": "PS7_SAXIACPARPROT0", - "SAXIACPARPROT1": "PS7_SAXIACPARPROT1", - "SAXIACPARPROT2": "PS7_SAXIACPARPROT2", - "SAXIACPARQOS0": "PS7_SAXIACPARQOS0", - "SAXIACPARQOS1": "PS7_SAXIACPARQOS1", - "SAXIACPARQOS2": "PS7_SAXIACPARQOS2", - "SAXIACPARQOS3": "PS7_SAXIACPARQOS3", - "SAXIACPARREADY": "PS7_SAXIACPARREADY", - "SAXIACPARSIZE0": "PS7_SAXIACPARSIZE0", - "SAXIACPARSIZE1": "PS7_SAXIACPARSIZE1", - "SAXIACPARUSER0": "PS7_SAXIACPARUSER0", - "SAXIACPARUSER1": "PS7_SAXIACPARUSER1", - "SAXIACPARUSER2": "PS7_SAXIACPARUSER2", - "SAXIACPARUSER3": "PS7_SAXIACPARUSER3", - "SAXIACPARUSER4": "PS7_SAXIACPARUSER4", - "SAXIACPARVALID": "PS7_SAXIACPARVALID", - "SAXIACPAWADDR0": "PS7_SAXIACPAWADDR0", - "SAXIACPAWADDR1": "PS7_SAXIACPAWADDR1", - "SAXIACPAWADDR10": "PS7_SAXIACPAWADDR10", - "SAXIACPAWADDR11": "PS7_SAXIACPAWADDR11", - "SAXIACPAWADDR12": "PS7_SAXIACPAWADDR12", - "SAXIACPAWADDR13": "PS7_SAXIACPAWADDR13", - "SAXIACPAWADDR14": "PS7_SAXIACPAWADDR14", - "SAXIACPAWADDR15": "PS7_SAXIACPAWADDR15", - "SAXIACPAWADDR16": "PS7_SAXIACPAWADDR16", - "SAXIACPAWADDR17": "PS7_SAXIACPAWADDR17", - "SAXIACPAWADDR18": "PS7_SAXIACPAWADDR18", - "SAXIACPAWADDR19": "PS7_SAXIACPAWADDR19", - "SAXIACPAWADDR2": "PS7_SAXIACPAWADDR2", - "SAXIACPAWADDR20": "PS7_SAXIACPAWADDR20", - "SAXIACPAWADDR21": "PS7_SAXIACPAWADDR21", - "SAXIACPAWADDR22": "PS7_SAXIACPAWADDR22", - "SAXIACPAWADDR23": "PS7_SAXIACPAWADDR23", - "SAXIACPAWADDR24": "PS7_SAXIACPAWADDR24", - "SAXIACPAWADDR25": "PS7_SAXIACPAWADDR25", - "SAXIACPAWADDR26": "PS7_SAXIACPAWADDR26", - "SAXIACPAWADDR27": "PS7_SAXIACPAWADDR27", - "SAXIACPAWADDR28": "PS7_SAXIACPAWADDR28", - "SAXIACPAWADDR29": "PS7_SAXIACPAWADDR29", - "SAXIACPAWADDR3": "PS7_SAXIACPAWADDR3", - "SAXIACPAWADDR30": "PS7_SAXIACPAWADDR30", - "SAXIACPAWADDR31": "PS7_SAXIACPAWADDR31", - "SAXIACPAWADDR4": "PS7_SAXIACPAWADDR4", - "SAXIACPAWADDR5": "PS7_SAXIACPAWADDR5", - "SAXIACPAWADDR6": "PS7_SAXIACPAWADDR6", - "SAXIACPAWADDR7": "PS7_SAXIACPAWADDR7", - "SAXIACPAWADDR8": "PS7_SAXIACPAWADDR8", - "SAXIACPAWADDR9": "PS7_SAXIACPAWADDR9", - "SAXIACPAWBURST0": "PS7_SAXIACPAWBURST0", - "SAXIACPAWBURST1": "PS7_SAXIACPAWBURST1", - "SAXIACPAWCACHE0": "PS7_SAXIACPAWCACHE0", - "SAXIACPAWCACHE1": "PS7_SAXIACPAWCACHE1", - "SAXIACPAWCACHE2": "PS7_SAXIACPAWCACHE2", - "SAXIACPAWCACHE3": "PS7_SAXIACPAWCACHE3", - "SAXIACPAWID0": "PS7_SAXIACPAWID0", - "SAXIACPAWID1": "PS7_SAXIACPAWID1", - "SAXIACPAWID2": "PS7_SAXIACPAWID2", - "SAXIACPAWLEN0": "PS7_SAXIACPAWLEN0", - "SAXIACPAWLEN1": "PS7_SAXIACPAWLEN1", - "SAXIACPAWLEN2": "PS7_SAXIACPAWLEN2", - "SAXIACPAWLEN3": "PS7_SAXIACPAWLEN3", - "SAXIACPAWLOCK0": "PS7_SAXIACPAWLOCK0", - "SAXIACPAWLOCK1": "PS7_SAXIACPAWLOCK1", - "SAXIACPAWPROT0": "PS7_SAXIACPAWPROT0", - "SAXIACPAWPROT1": "PS7_SAXIACPAWPROT1", - "SAXIACPAWPROT2": "PS7_SAXIACPAWPROT2", - "SAXIACPAWQOS0": "PS7_SAXIACPAWQOS0", - "SAXIACPAWQOS1": "PS7_SAXIACPAWQOS1", - "SAXIACPAWQOS2": "PS7_SAXIACPAWQOS2", - "SAXIACPAWQOS3": "PS7_SAXIACPAWQOS3", - "SAXIACPAWREADY": "PS7_SAXIACPAWREADY", - "SAXIACPAWSIZE0": "PS7_SAXIACPAWSIZE0", - "SAXIACPAWSIZE1": "PS7_SAXIACPAWSIZE1", - "SAXIACPAWUSER0": "PS7_SAXIACPAWUSER0", - "SAXIACPAWUSER1": "PS7_SAXIACPAWUSER1", - "SAXIACPAWUSER2": "PS7_SAXIACPAWUSER2", - "SAXIACPAWUSER3": "PS7_SAXIACPAWUSER3", - "SAXIACPAWUSER4": "PS7_SAXIACPAWUSER4", - "SAXIACPAWVALID": "PS7_SAXIACPAWVALID", - "SAXIACPBID0": "PS7_SAXIACPBID0", - "SAXIACPBID1": "PS7_SAXIACPBID1", - "SAXIACPBID2": "PS7_SAXIACPBID2", - "SAXIACPBREADY": "PS7_SAXIACPBREADY", - "SAXIACPBRESP0": "PS7_SAXIACPBRESP0", - "SAXIACPBRESP1": "PS7_SAXIACPBRESP1", - "SAXIACPBVALID": "PS7_SAXIACPBVALID", - "SAXIACPRDATA0": "PS7_SAXIACPRDATA0", - "SAXIACPRDATA1": "PS7_SAXIACPRDATA1", - "SAXIACPRDATA10": "PS7_SAXIACPRDATA10", - "SAXIACPRDATA11": "PS7_SAXIACPRDATA11", - "SAXIACPRDATA12": "PS7_SAXIACPRDATA12", - "SAXIACPRDATA13": "PS7_SAXIACPRDATA13", - "SAXIACPRDATA14": "PS7_SAXIACPRDATA14", - "SAXIACPRDATA15": "PS7_SAXIACPRDATA15", - "SAXIACPRDATA16": "PS7_SAXIACPRDATA16", - "SAXIACPRDATA17": "PS7_SAXIACPRDATA17", - "SAXIACPRDATA18": "PS7_SAXIACPRDATA18", - "SAXIACPRDATA19": "PS7_SAXIACPRDATA19", - "SAXIACPRDATA2": "PS7_SAXIACPRDATA2", - "SAXIACPRDATA20": "PS7_SAXIACPRDATA20", - "SAXIACPRDATA21": "PS7_SAXIACPRDATA21", - "SAXIACPRDATA22": "PS7_SAXIACPRDATA22", - "SAXIACPRDATA23": "PS7_SAXIACPRDATA23", - "SAXIACPRDATA24": "PS7_SAXIACPRDATA24", - "SAXIACPRDATA25": "PS7_SAXIACPRDATA25", - "SAXIACPRDATA26": "PS7_SAXIACPRDATA26", - "SAXIACPRDATA27": "PS7_SAXIACPRDATA27", - "SAXIACPRDATA28": "PS7_SAXIACPRDATA28", - "SAXIACPRDATA29": "PS7_SAXIACPRDATA29", - "SAXIACPRDATA3": "PS7_SAXIACPRDATA3", - "SAXIACPRDATA30": "PS7_SAXIACPRDATA30", - "SAXIACPRDATA31": "PS7_SAXIACPRDATA31", - "SAXIACPRDATA32": "PS7_SAXIACPRDATA32", - "SAXIACPRDATA33": "PS7_SAXIACPRDATA33", - "SAXIACPRDATA34": "PS7_SAXIACPRDATA34", - "SAXIACPRDATA35": "PS7_SAXIACPRDATA35", - "SAXIACPRDATA36": "PS7_SAXIACPRDATA36", - "SAXIACPRDATA37": "PS7_SAXIACPRDATA37", - "SAXIACPRDATA38": "PS7_SAXIACPRDATA38", - "SAXIACPRDATA39": "PS7_SAXIACPRDATA39", - "SAXIACPRDATA4": "PS7_SAXIACPRDATA4", - "SAXIACPRDATA40": "PS7_SAXIACPRDATA40", - "SAXIACPRDATA41": "PS7_SAXIACPRDATA41", - "SAXIACPRDATA42": "PS7_SAXIACPRDATA42", - "SAXIACPRDATA43": "PS7_SAXIACPRDATA43", - "SAXIACPRDATA44": "PS7_SAXIACPRDATA44", - "SAXIACPRDATA45": "PS7_SAXIACPRDATA45", - "SAXIACPRDATA46": "PS7_SAXIACPRDATA46", - "SAXIACPRDATA47": "PS7_SAXIACPRDATA47", - "SAXIACPRDATA48": "PS7_SAXIACPRDATA48", - "SAXIACPRDATA49": "PS7_SAXIACPRDATA49", - "SAXIACPRDATA5": "PS7_SAXIACPRDATA5", - "SAXIACPRDATA50": "PS7_SAXIACPRDATA50", - "SAXIACPRDATA51": "PS7_SAXIACPRDATA51", - "SAXIACPRDATA52": "PS7_SAXIACPRDATA52", - "SAXIACPRDATA53": "PS7_SAXIACPRDATA53", - "SAXIACPRDATA54": "PS7_SAXIACPRDATA54", - "SAXIACPRDATA55": "PS7_SAXIACPRDATA55", - "SAXIACPRDATA56": "PS7_SAXIACPRDATA56", - "SAXIACPRDATA57": "PS7_SAXIACPRDATA57", - "SAXIACPRDATA58": "PS7_SAXIACPRDATA58", - "SAXIACPRDATA59": "PS7_SAXIACPRDATA59", - "SAXIACPRDATA6": "PS7_SAXIACPRDATA6", - "SAXIACPRDATA60": "PS7_SAXIACPRDATA60", - "SAXIACPRDATA61": "PS7_SAXIACPRDATA61", - "SAXIACPRDATA62": "PS7_SAXIACPRDATA62", - "SAXIACPRDATA63": "PS7_SAXIACPRDATA63", - "SAXIACPRDATA7": "PS7_SAXIACPRDATA7", - "SAXIACPRDATA8": "PS7_SAXIACPRDATA8", - "SAXIACPRDATA9": "PS7_SAXIACPRDATA9", - "SAXIACPRID0": "PS7_SAXIACPRID0", - "SAXIACPRID1": "PS7_SAXIACPRID1", - "SAXIACPRID2": "PS7_SAXIACPRID2", - "SAXIACPRLAST": "PS7_SAXIACPRLAST", - "SAXIACPRREADY": "PS7_SAXIACPRREADY", - "SAXIACPRRESP0": "PS7_SAXIACPRRESP0", - "SAXIACPRRESP1": "PS7_SAXIACPRRESP1", - "SAXIACPRVALID": "PS7_SAXIACPRVALID", - "SAXIACPWDATA0": "PS7_SAXIACPWDATA0", - "SAXIACPWDATA1": "PS7_SAXIACPWDATA1", - "SAXIACPWDATA10": "PS7_SAXIACPWDATA10", - "SAXIACPWDATA11": "PS7_SAXIACPWDATA11", - "SAXIACPWDATA12": "PS7_SAXIACPWDATA12", - "SAXIACPWDATA13": "PS7_SAXIACPWDATA13", - "SAXIACPWDATA14": "PS7_SAXIACPWDATA14", - "SAXIACPWDATA15": "PS7_SAXIACPWDATA15", - "SAXIACPWDATA16": "PS7_SAXIACPWDATA16", - "SAXIACPWDATA17": "PS7_SAXIACPWDATA17", - "SAXIACPWDATA18": "PS7_SAXIACPWDATA18", - "SAXIACPWDATA19": "PS7_SAXIACPWDATA19", - "SAXIACPWDATA2": "PS7_SAXIACPWDATA2", - "SAXIACPWDATA20": "PS7_SAXIACPWDATA20", - "SAXIACPWDATA21": "PS7_SAXIACPWDATA21", - "SAXIACPWDATA22": "PS7_SAXIACPWDATA22", - "SAXIACPWDATA23": "PS7_SAXIACPWDATA23", - "SAXIACPWDATA24": "PS7_SAXIACPWDATA24", - "SAXIACPWDATA25": "PS7_SAXIACPWDATA25", - "SAXIACPWDATA26": "PS7_SAXIACPWDATA26", - "SAXIACPWDATA27": "PS7_SAXIACPWDATA27", - "SAXIACPWDATA28": "PS7_SAXIACPWDATA28", - "SAXIACPWDATA29": "PS7_SAXIACPWDATA29", - "SAXIACPWDATA3": "PS7_SAXIACPWDATA3", - "SAXIACPWDATA30": "PS7_SAXIACPWDATA30", - "SAXIACPWDATA31": "PS7_SAXIACPWDATA31", - "SAXIACPWDATA32": "PS7_SAXIACPWDATA32", - "SAXIACPWDATA33": "PS7_SAXIACPWDATA33", - "SAXIACPWDATA34": "PS7_SAXIACPWDATA34", - "SAXIACPWDATA35": "PS7_SAXIACPWDATA35", - "SAXIACPWDATA36": "PS7_SAXIACPWDATA36", - "SAXIACPWDATA37": "PS7_SAXIACPWDATA37", - "SAXIACPWDATA38": "PS7_SAXIACPWDATA38", - "SAXIACPWDATA39": "PS7_SAXIACPWDATA39", - "SAXIACPWDATA4": "PS7_SAXIACPWDATA4", - "SAXIACPWDATA40": "PS7_SAXIACPWDATA40", - "SAXIACPWDATA41": "PS7_SAXIACPWDATA41", - "SAXIACPWDATA42": "PS7_SAXIACPWDATA42", - "SAXIACPWDATA43": "PS7_SAXIACPWDATA43", - "SAXIACPWDATA44": "PS7_SAXIACPWDATA44", - "SAXIACPWDATA45": "PS7_SAXIACPWDATA45", - "SAXIACPWDATA46": "PS7_SAXIACPWDATA46", - "SAXIACPWDATA47": "PS7_SAXIACPWDATA47", - "SAXIACPWDATA48": "PS7_SAXIACPWDATA48", - "SAXIACPWDATA49": "PS7_SAXIACPWDATA49", - "SAXIACPWDATA5": "PS7_SAXIACPWDATA5", - "SAXIACPWDATA50": "PS7_SAXIACPWDATA50", - "SAXIACPWDATA51": "PS7_SAXIACPWDATA51", - "SAXIACPWDATA52": "PS7_SAXIACPWDATA52", - "SAXIACPWDATA53": "PS7_SAXIACPWDATA53", - "SAXIACPWDATA54": "PS7_SAXIACPWDATA54", - "SAXIACPWDATA55": "PS7_SAXIACPWDATA55", - "SAXIACPWDATA56": "PS7_SAXIACPWDATA56", - "SAXIACPWDATA57": "PS7_SAXIACPWDATA57", - "SAXIACPWDATA58": "PS7_SAXIACPWDATA58", - "SAXIACPWDATA59": "PS7_SAXIACPWDATA59", - "SAXIACPWDATA6": "PS7_SAXIACPWDATA6", - "SAXIACPWDATA60": "PS7_SAXIACPWDATA60", - "SAXIACPWDATA61": "PS7_SAXIACPWDATA61", - "SAXIACPWDATA62": "PS7_SAXIACPWDATA62", - "SAXIACPWDATA63": "PS7_SAXIACPWDATA63", - "SAXIACPWDATA7": "PS7_SAXIACPWDATA7", - "SAXIACPWDATA8": "PS7_SAXIACPWDATA8", - "SAXIACPWDATA9": "PS7_SAXIACPWDATA9", - "SAXIACPWID0": "PS7_SAXIACPWID0", - "SAXIACPWID1": "PS7_SAXIACPWID1", - "SAXIACPWID2": "PS7_SAXIACPWID2", - "SAXIACPWLAST": "PS7_SAXIACPWLAST", - "SAXIACPWREADY": "PS7_SAXIACPWREADY", - "SAXIACPWSTRB0": "PS7_SAXIACPWSTRB0", - "SAXIACPWSTRB1": "PS7_SAXIACPWSTRB1", - "SAXIACPWSTRB2": "PS7_SAXIACPWSTRB2", - "SAXIACPWSTRB3": "PS7_SAXIACPWSTRB3", - "SAXIACPWSTRB4": "PS7_SAXIACPWSTRB4", - "SAXIACPWSTRB5": "PS7_SAXIACPWSTRB5", - "SAXIACPWSTRB6": "PS7_SAXIACPWSTRB6", - "SAXIACPWSTRB7": "PS7_SAXIACPWSTRB7", - "SAXIACPWVALID": "PS7_SAXIACPWVALID", - "SAXIGP0ACLK": "PS7_SAXIGP0ACLK", - "SAXIGP0ARADDR0": "PS7_SAXIGP0ARADDR0", - "SAXIGP0ARADDR1": "PS7_SAXIGP0ARADDR1", - "SAXIGP0ARADDR10": "PS7_SAXIGP0ARADDR10", - "SAXIGP0ARADDR11": "PS7_SAXIGP0ARADDR11", - "SAXIGP0ARADDR12": "PS7_SAXIGP0ARADDR12", - "SAXIGP0ARADDR13": "PS7_SAXIGP0ARADDR13", - "SAXIGP0ARADDR14": "PS7_SAXIGP0ARADDR14", - "SAXIGP0ARADDR15": "PS7_SAXIGP0ARADDR15", - "SAXIGP0ARADDR16": "PS7_SAXIGP0ARADDR16", - "SAXIGP0ARADDR17": "PS7_SAXIGP0ARADDR17", - "SAXIGP0ARADDR18": "PS7_SAXIGP0ARADDR18", - "SAXIGP0ARADDR19": "PS7_SAXIGP0ARADDR19", - "SAXIGP0ARADDR2": "PS7_SAXIGP0ARADDR2", - "SAXIGP0ARADDR20": "PS7_SAXIGP0ARADDR20", - "SAXIGP0ARADDR21": "PS7_SAXIGP0ARADDR21", - "SAXIGP0ARADDR22": "PS7_SAXIGP0ARADDR22", - "SAXIGP0ARADDR23": "PS7_SAXIGP0ARADDR23", - "SAXIGP0ARADDR24": "PS7_SAXIGP0ARADDR24", - "SAXIGP0ARADDR25": "PS7_SAXIGP0ARADDR25", - "SAXIGP0ARADDR26": "PS7_SAXIGP0ARADDR26", - "SAXIGP0ARADDR27": "PS7_SAXIGP0ARADDR27", - "SAXIGP0ARADDR28": "PS7_SAXIGP0ARADDR28", - "SAXIGP0ARADDR29": "PS7_SAXIGP0ARADDR29", - "SAXIGP0ARADDR3": "PS7_SAXIGP0ARADDR3", - "SAXIGP0ARADDR30": "PS7_SAXIGP0ARADDR30", - "SAXIGP0ARADDR31": "PS7_SAXIGP0ARADDR31", - "SAXIGP0ARADDR4": "PS7_SAXIGP0ARADDR4", - "SAXIGP0ARADDR5": "PS7_SAXIGP0ARADDR5", - "SAXIGP0ARADDR6": "PS7_SAXIGP0ARADDR6", - "SAXIGP0ARADDR7": "PS7_SAXIGP0ARADDR7", - "SAXIGP0ARADDR8": "PS7_SAXIGP0ARADDR8", - "SAXIGP0ARADDR9": "PS7_SAXIGP0ARADDR9", - "SAXIGP0ARBURST0": "PS7_SAXIGP0ARBURST0", - "SAXIGP0ARBURST1": "PS7_SAXIGP0ARBURST1", - "SAXIGP0ARCACHE0": "PS7_SAXIGP0ARCACHE0", - "SAXIGP0ARCACHE1": "PS7_SAXIGP0ARCACHE1", - "SAXIGP0ARCACHE2": "PS7_SAXIGP0ARCACHE2", - "SAXIGP0ARCACHE3": "PS7_SAXIGP0ARCACHE3", - "SAXIGP0ARESETN": "PS7_SAXIGP0ARESETN", - "SAXIGP0ARID0": "PS7_SAXIGP0ARID0", - "SAXIGP0ARID1": "PS7_SAXIGP0ARID1", - "SAXIGP0ARID2": "PS7_SAXIGP0ARID2", - "SAXIGP0ARID3": "PS7_SAXIGP0ARID3", - "SAXIGP0ARID4": "PS7_SAXIGP0ARID4", - "SAXIGP0ARID5": "PS7_SAXIGP0ARID5", - "SAXIGP0ARLEN0": "PS7_SAXIGP0ARLEN0", - "SAXIGP0ARLEN1": "PS7_SAXIGP0ARLEN1", - "SAXIGP0ARLEN2": "PS7_SAXIGP0ARLEN2", - "SAXIGP0ARLEN3": "PS7_SAXIGP0ARLEN3", - "SAXIGP0ARLOCK0": "PS7_SAXIGP0ARLOCK0", - "SAXIGP0ARLOCK1": "PS7_SAXIGP0ARLOCK1", - "SAXIGP0ARPROT0": "PS7_SAXIGP0ARPROT0", - "SAXIGP0ARPROT1": "PS7_SAXIGP0ARPROT1", - "SAXIGP0ARPROT2": "PS7_SAXIGP0ARPROT2", - "SAXIGP0ARQOS0": "PS7_SAXIGP0ARQOS0", - "SAXIGP0ARQOS1": "PS7_SAXIGP0ARQOS1", - "SAXIGP0ARQOS2": "PS7_SAXIGP0ARQOS2", - "SAXIGP0ARQOS3": "PS7_SAXIGP0ARQOS3", - "SAXIGP0ARREADY": "PS7_SAXIGP0ARREADY", - "SAXIGP0ARSIZE0": "PS7_SAXIGP0ARSIZE0", - "SAXIGP0ARSIZE1": "PS7_SAXIGP0ARSIZE1", - "SAXIGP0ARVALID": "PS7_SAXIGP0ARVALID", - "SAXIGP0AWADDR0": "PS7_SAXIGP0AWADDR0", - "SAXIGP0AWADDR1": "PS7_SAXIGP0AWADDR1", - "SAXIGP0AWADDR10": "PS7_SAXIGP0AWADDR10", - "SAXIGP0AWADDR11": "PS7_SAXIGP0AWADDR11", - "SAXIGP0AWADDR12": "PS7_SAXIGP0AWADDR12", - "SAXIGP0AWADDR13": "PS7_SAXIGP0AWADDR13", - "SAXIGP0AWADDR14": "PS7_SAXIGP0AWADDR14", - "SAXIGP0AWADDR15": "PS7_SAXIGP0AWADDR15", - "SAXIGP0AWADDR16": "PS7_SAXIGP0AWADDR16", - "SAXIGP0AWADDR17": "PS7_SAXIGP0AWADDR17", - "SAXIGP0AWADDR18": "PS7_SAXIGP0AWADDR18", - "SAXIGP0AWADDR19": "PS7_SAXIGP0AWADDR19", - "SAXIGP0AWADDR2": "PS7_SAXIGP0AWADDR2", - "SAXIGP0AWADDR20": "PS7_SAXIGP0AWADDR20", - "SAXIGP0AWADDR21": "PS7_SAXIGP0AWADDR21", - "SAXIGP0AWADDR22": "PS7_SAXIGP0AWADDR22", - "SAXIGP0AWADDR23": "PS7_SAXIGP0AWADDR23", - "SAXIGP0AWADDR24": "PS7_SAXIGP0AWADDR24", - "SAXIGP0AWADDR25": "PS7_SAXIGP0AWADDR25", - "SAXIGP0AWADDR26": "PS7_SAXIGP0AWADDR26", - "SAXIGP0AWADDR27": "PS7_SAXIGP0AWADDR27", - "SAXIGP0AWADDR28": "PS7_SAXIGP0AWADDR28", - "SAXIGP0AWADDR29": "PS7_SAXIGP0AWADDR29", - "SAXIGP0AWADDR3": "PS7_SAXIGP0AWADDR3", - "SAXIGP0AWADDR30": "PS7_SAXIGP0AWADDR30", - "SAXIGP0AWADDR31": "PS7_SAXIGP0AWADDR31", - "SAXIGP0AWADDR4": "PS7_SAXIGP0AWADDR4", - "SAXIGP0AWADDR5": "PS7_SAXIGP0AWADDR5", - "SAXIGP0AWADDR6": "PS7_SAXIGP0AWADDR6", - "SAXIGP0AWADDR7": "PS7_SAXIGP0AWADDR7", - "SAXIGP0AWADDR8": "PS7_SAXIGP0AWADDR8", - "SAXIGP0AWADDR9": "PS7_SAXIGP0AWADDR9", - "SAXIGP0AWBURST0": "PS7_SAXIGP0AWBURST0", - "SAXIGP0AWBURST1": "PS7_SAXIGP0AWBURST1", - "SAXIGP0AWCACHE0": "PS7_SAXIGP0AWCACHE0", - "SAXIGP0AWCACHE1": "PS7_SAXIGP0AWCACHE1", - "SAXIGP0AWCACHE2": "PS7_SAXIGP0AWCACHE2", - "SAXIGP0AWCACHE3": "PS7_SAXIGP0AWCACHE3", - "SAXIGP0AWID0": "PS7_SAXIGP0AWID0", - "SAXIGP0AWID1": "PS7_SAXIGP0AWID1", - "SAXIGP0AWID2": "PS7_SAXIGP0AWID2", - "SAXIGP0AWID3": "PS7_SAXIGP0AWID3", - "SAXIGP0AWID4": "PS7_SAXIGP0AWID4", - "SAXIGP0AWID5": "PS7_SAXIGP0AWID5", - "SAXIGP0AWLEN0": "PS7_SAXIGP0AWLEN0", - "SAXIGP0AWLEN1": "PS7_SAXIGP0AWLEN1", - "SAXIGP0AWLEN2": "PS7_SAXIGP0AWLEN2", - "SAXIGP0AWLEN3": "PS7_SAXIGP0AWLEN3", - "SAXIGP0AWLOCK0": "PS7_SAXIGP0AWLOCK0", - "SAXIGP0AWLOCK1": "PS7_SAXIGP0AWLOCK1", - "SAXIGP0AWPROT0": "PS7_SAXIGP0AWPROT0", - "SAXIGP0AWPROT1": "PS7_SAXIGP0AWPROT1", - "SAXIGP0AWPROT2": "PS7_SAXIGP0AWPROT2", - "SAXIGP0AWQOS0": "PS7_SAXIGP0AWQOS0", - "SAXIGP0AWQOS1": "PS7_SAXIGP0AWQOS1", - "SAXIGP0AWQOS2": "PS7_SAXIGP0AWQOS2", - "SAXIGP0AWQOS3": "PS7_SAXIGP0AWQOS3", - "SAXIGP0AWREADY": "PS7_SAXIGP0AWREADY", - "SAXIGP0AWSIZE0": "PS7_SAXIGP0AWSIZE0", - "SAXIGP0AWSIZE1": "PS7_SAXIGP0AWSIZE1", - "SAXIGP0AWVALID": "PS7_SAXIGP0AWVALID", - "SAXIGP0BID0": "PS7_SAXIGP0BID0", - "SAXIGP0BID1": "PS7_SAXIGP0BID1", - "SAXIGP0BID2": "PS7_SAXIGP0BID2", - "SAXIGP0BID3": "PS7_SAXIGP0BID3", - "SAXIGP0BID4": "PS7_SAXIGP0BID4", - "SAXIGP0BID5": "PS7_SAXIGP0BID5", - "SAXIGP0BREADY": "PS7_SAXIGP0BREADY", - "SAXIGP0BRESP0": "PS7_SAXIGP0BRESP0", - "SAXIGP0BRESP1": "PS7_SAXIGP0BRESP1", - "SAXIGP0BVALID": "PS7_SAXIGP0BVALID", - "SAXIGP0RDATA0": "PS7_SAXIGP0RDATA0", - "SAXIGP0RDATA1": "PS7_SAXIGP0RDATA1", - "SAXIGP0RDATA10": "PS7_SAXIGP0RDATA10", - "SAXIGP0RDATA11": "PS7_SAXIGP0RDATA11", - "SAXIGP0RDATA12": "PS7_SAXIGP0RDATA12", - "SAXIGP0RDATA13": "PS7_SAXIGP0RDATA13", - "SAXIGP0RDATA14": "PS7_SAXIGP0RDATA14", - "SAXIGP0RDATA15": "PS7_SAXIGP0RDATA15", - "SAXIGP0RDATA16": "PS7_SAXIGP0RDATA16", - "SAXIGP0RDATA17": "PS7_SAXIGP0RDATA17", - "SAXIGP0RDATA18": "PS7_SAXIGP0RDATA18", - "SAXIGP0RDATA19": "PS7_SAXIGP0RDATA19", - "SAXIGP0RDATA2": "PS7_SAXIGP0RDATA2", - "SAXIGP0RDATA20": "PS7_SAXIGP0RDATA20", - "SAXIGP0RDATA21": "PS7_SAXIGP0RDATA21", - "SAXIGP0RDATA22": "PS7_SAXIGP0RDATA22", - "SAXIGP0RDATA23": "PS7_SAXIGP0RDATA23", - "SAXIGP0RDATA24": "PS7_SAXIGP0RDATA24", - "SAXIGP0RDATA25": "PS7_SAXIGP0RDATA25", - "SAXIGP0RDATA26": "PS7_SAXIGP0RDATA26", - "SAXIGP0RDATA27": "PS7_SAXIGP0RDATA27", - "SAXIGP0RDATA28": "PS7_SAXIGP0RDATA28", - "SAXIGP0RDATA29": "PS7_SAXIGP0RDATA29", - "SAXIGP0RDATA3": "PS7_SAXIGP0RDATA3", - "SAXIGP0RDATA30": "PS7_SAXIGP0RDATA30", - "SAXIGP0RDATA31": "PS7_SAXIGP0RDATA31", - "SAXIGP0RDATA4": "PS7_SAXIGP0RDATA4", - "SAXIGP0RDATA5": "PS7_SAXIGP0RDATA5", - "SAXIGP0RDATA6": "PS7_SAXIGP0RDATA6", - "SAXIGP0RDATA7": "PS7_SAXIGP0RDATA7", - "SAXIGP0RDATA8": "PS7_SAXIGP0RDATA8", - "SAXIGP0RDATA9": "PS7_SAXIGP0RDATA9", - "SAXIGP0RID0": "PS7_SAXIGP0RID0", - "SAXIGP0RID1": "PS7_SAXIGP0RID1", - "SAXIGP0RID2": "PS7_SAXIGP0RID2", - "SAXIGP0RID3": "PS7_SAXIGP0RID3", - "SAXIGP0RID4": "PS7_SAXIGP0RID4", - "SAXIGP0RID5": "PS7_SAXIGP0RID5", - "SAXIGP0RLAST": "PS7_SAXIGP0RLAST", - "SAXIGP0RREADY": "PS7_SAXIGP0RREADY", - "SAXIGP0RRESP0": "PS7_SAXIGP0RRESP0", - "SAXIGP0RRESP1": "PS7_SAXIGP0RRESP1", - "SAXIGP0RVALID": "PS7_SAXIGP0RVALID", - "SAXIGP0WDATA0": "PS7_SAXIGP0WDATA0", - "SAXIGP0WDATA1": "PS7_SAXIGP0WDATA1", - "SAXIGP0WDATA10": "PS7_SAXIGP0WDATA10", - "SAXIGP0WDATA11": "PS7_SAXIGP0WDATA11", - "SAXIGP0WDATA12": "PS7_SAXIGP0WDATA12", - "SAXIGP0WDATA13": "PS7_SAXIGP0WDATA13", - "SAXIGP0WDATA14": "PS7_SAXIGP0WDATA14", - "SAXIGP0WDATA15": "PS7_SAXIGP0WDATA15", - "SAXIGP0WDATA16": "PS7_SAXIGP0WDATA16", - "SAXIGP0WDATA17": "PS7_SAXIGP0WDATA17", - "SAXIGP0WDATA18": "PS7_SAXIGP0WDATA18", - "SAXIGP0WDATA19": "PS7_SAXIGP0WDATA19", - "SAXIGP0WDATA2": "PS7_SAXIGP0WDATA2", - "SAXIGP0WDATA20": "PS7_SAXIGP0WDATA20", - "SAXIGP0WDATA21": "PS7_SAXIGP0WDATA21", - "SAXIGP0WDATA22": "PS7_SAXIGP0WDATA22", - "SAXIGP0WDATA23": "PS7_SAXIGP0WDATA23", - "SAXIGP0WDATA24": "PS7_SAXIGP0WDATA24", - "SAXIGP0WDATA25": "PS7_SAXIGP0WDATA25", - "SAXIGP0WDATA26": "PS7_SAXIGP0WDATA26", - "SAXIGP0WDATA27": "PS7_SAXIGP0WDATA27", - "SAXIGP0WDATA28": "PS7_SAXIGP0WDATA28", - "SAXIGP0WDATA29": "PS7_SAXIGP0WDATA29", - "SAXIGP0WDATA3": "PS7_SAXIGP0WDATA3", - "SAXIGP0WDATA30": "PS7_SAXIGP0WDATA30", - "SAXIGP0WDATA31": "PS7_SAXIGP0WDATA31", - "SAXIGP0WDATA4": "PS7_SAXIGP0WDATA4", - "SAXIGP0WDATA5": "PS7_SAXIGP0WDATA5", - "SAXIGP0WDATA6": "PS7_SAXIGP0WDATA6", - "SAXIGP0WDATA7": "PS7_SAXIGP0WDATA7", - "SAXIGP0WDATA8": "PS7_SAXIGP0WDATA8", - "SAXIGP0WDATA9": "PS7_SAXIGP0WDATA9", - "SAXIGP0WID0": "PS7_SAXIGP0WID0", - "SAXIGP0WID1": "PS7_SAXIGP0WID1", - "SAXIGP0WID2": "PS7_SAXIGP0WID2", - "SAXIGP0WID3": "PS7_SAXIGP0WID3", - "SAXIGP0WID4": "PS7_SAXIGP0WID4", - "SAXIGP0WID5": "PS7_SAXIGP0WID5", - "SAXIGP0WLAST": "PS7_SAXIGP0WLAST", - "SAXIGP0WREADY": "PS7_SAXIGP0WREADY", - "SAXIGP0WSTRB0": "PS7_SAXIGP0WSTRB0", - "SAXIGP0WSTRB1": "PS7_SAXIGP0WSTRB1", - "SAXIGP0WSTRB2": "PS7_SAXIGP0WSTRB2", - "SAXIGP0WSTRB3": "PS7_SAXIGP0WSTRB3", - "SAXIGP0WVALID": "PS7_SAXIGP0WVALID", - "SAXIGP1ACLK": "PS7_SAXIGP1ACLK", - "SAXIGP1ARADDR0": "PS7_SAXIGP1ARADDR0", - "SAXIGP1ARADDR1": "PS7_SAXIGP1ARADDR1", - "SAXIGP1ARADDR10": "PS7_SAXIGP1ARADDR10", - "SAXIGP1ARADDR11": "PS7_SAXIGP1ARADDR11", - "SAXIGP1ARADDR12": "PS7_SAXIGP1ARADDR12", - "SAXIGP1ARADDR13": "PS7_SAXIGP1ARADDR13", - "SAXIGP1ARADDR14": "PS7_SAXIGP1ARADDR14", - "SAXIGP1ARADDR15": "PS7_SAXIGP1ARADDR15", - "SAXIGP1ARADDR16": "PS7_SAXIGP1ARADDR16", - "SAXIGP1ARADDR17": "PS7_SAXIGP1ARADDR17", - "SAXIGP1ARADDR18": "PS7_SAXIGP1ARADDR18", - "SAXIGP1ARADDR19": "PS7_SAXIGP1ARADDR19", - "SAXIGP1ARADDR2": "PS7_SAXIGP1ARADDR2", - "SAXIGP1ARADDR20": "PS7_SAXIGP1ARADDR20", - "SAXIGP1ARADDR21": "PS7_SAXIGP1ARADDR21", - "SAXIGP1ARADDR22": "PS7_SAXIGP1ARADDR22", - "SAXIGP1ARADDR23": "PS7_SAXIGP1ARADDR23", - "SAXIGP1ARADDR24": "PS7_SAXIGP1ARADDR24", - "SAXIGP1ARADDR25": "PS7_SAXIGP1ARADDR25", - "SAXIGP1ARADDR26": "PS7_SAXIGP1ARADDR26", - "SAXIGP1ARADDR27": "PS7_SAXIGP1ARADDR27", - "SAXIGP1ARADDR28": "PS7_SAXIGP1ARADDR28", - "SAXIGP1ARADDR29": "PS7_SAXIGP1ARADDR29", - "SAXIGP1ARADDR3": "PS7_SAXIGP1ARADDR3", - "SAXIGP1ARADDR30": "PS7_SAXIGP1ARADDR30", - "SAXIGP1ARADDR31": "PS7_SAXIGP1ARADDR31", - "SAXIGP1ARADDR4": "PS7_SAXIGP1ARADDR4", - "SAXIGP1ARADDR5": "PS7_SAXIGP1ARADDR5", - "SAXIGP1ARADDR6": "PS7_SAXIGP1ARADDR6", - "SAXIGP1ARADDR7": "PS7_SAXIGP1ARADDR7", - "SAXIGP1ARADDR8": "PS7_SAXIGP1ARADDR8", - "SAXIGP1ARADDR9": "PS7_SAXIGP1ARADDR9", - "SAXIGP1ARBURST0": "PS7_SAXIGP1ARBURST0", - "SAXIGP1ARBURST1": "PS7_SAXIGP1ARBURST1", - "SAXIGP1ARCACHE0": "PS7_SAXIGP1ARCACHE0", - "SAXIGP1ARCACHE1": "PS7_SAXIGP1ARCACHE1", - "SAXIGP1ARCACHE2": "PS7_SAXIGP1ARCACHE2", - "SAXIGP1ARCACHE3": "PS7_SAXIGP1ARCACHE3", - "SAXIGP1ARESETN": "PS7_SAXIGP1ARESETN", - "SAXIGP1ARID0": "PS7_SAXIGP1ARID0", - "SAXIGP1ARID1": "PS7_SAXIGP1ARID1", - "SAXIGP1ARID2": "PS7_SAXIGP1ARID2", - "SAXIGP1ARID3": "PS7_SAXIGP1ARID3", - "SAXIGP1ARID4": "PS7_SAXIGP1ARID4", - "SAXIGP1ARID5": "PS7_SAXIGP1ARID5", - "SAXIGP1ARLEN0": "PS7_SAXIGP1ARLEN0", - "SAXIGP1ARLEN1": "PS7_SAXIGP1ARLEN1", - "SAXIGP1ARLEN2": "PS7_SAXIGP1ARLEN2", - "SAXIGP1ARLEN3": "PS7_SAXIGP1ARLEN3", - "SAXIGP1ARLOCK0": "PS7_SAXIGP1ARLOCK0", - "SAXIGP1ARLOCK1": "PS7_SAXIGP1ARLOCK1", - "SAXIGP1ARPROT0": "PS7_SAXIGP1ARPROT0", - "SAXIGP1ARPROT1": "PS7_SAXIGP1ARPROT1", - "SAXIGP1ARPROT2": "PS7_SAXIGP1ARPROT2", - "SAXIGP1ARQOS0": "PS7_SAXIGP1ARQOS0", - "SAXIGP1ARQOS1": "PS7_SAXIGP1ARQOS1", - "SAXIGP1ARQOS2": "PS7_SAXIGP1ARQOS2", - "SAXIGP1ARQOS3": "PS7_SAXIGP1ARQOS3", - "SAXIGP1ARREADY": "PS7_SAXIGP1ARREADY", - "SAXIGP1ARSIZE0": "PS7_SAXIGP1ARSIZE0", - "SAXIGP1ARSIZE1": "PS7_SAXIGP1ARSIZE1", - "SAXIGP1ARVALID": "PS7_SAXIGP1ARVALID", - "SAXIGP1AWADDR0": "PS7_SAXIGP1AWADDR0", - "SAXIGP1AWADDR1": "PS7_SAXIGP1AWADDR1", - "SAXIGP1AWADDR10": "PS7_SAXIGP1AWADDR10", - "SAXIGP1AWADDR11": "PS7_SAXIGP1AWADDR11", - "SAXIGP1AWADDR12": "PS7_SAXIGP1AWADDR12", - "SAXIGP1AWADDR13": "PS7_SAXIGP1AWADDR13", - "SAXIGP1AWADDR14": "PS7_SAXIGP1AWADDR14", - "SAXIGP1AWADDR15": "PS7_SAXIGP1AWADDR15", - "SAXIGP1AWADDR16": "PS7_SAXIGP1AWADDR16", - "SAXIGP1AWADDR17": "PS7_SAXIGP1AWADDR17", - "SAXIGP1AWADDR18": "PS7_SAXIGP1AWADDR18", - "SAXIGP1AWADDR19": "PS7_SAXIGP1AWADDR19", - "SAXIGP1AWADDR2": "PS7_SAXIGP1AWADDR2", - "SAXIGP1AWADDR20": "PS7_SAXIGP1AWADDR20", - "SAXIGP1AWADDR21": "PS7_SAXIGP1AWADDR21", - "SAXIGP1AWADDR22": "PS7_SAXIGP1AWADDR22", - "SAXIGP1AWADDR23": "PS7_SAXIGP1AWADDR23", - "SAXIGP1AWADDR24": "PS7_SAXIGP1AWADDR24", - "SAXIGP1AWADDR25": "PS7_SAXIGP1AWADDR25", - "SAXIGP1AWADDR26": "PS7_SAXIGP1AWADDR26", - "SAXIGP1AWADDR27": "PS7_SAXIGP1AWADDR27", - "SAXIGP1AWADDR28": "PS7_SAXIGP1AWADDR28", - "SAXIGP1AWADDR29": "PS7_SAXIGP1AWADDR29", - "SAXIGP1AWADDR3": "PS7_SAXIGP1AWADDR3", - "SAXIGP1AWADDR30": "PS7_SAXIGP1AWADDR30", - "SAXIGP1AWADDR31": "PS7_SAXIGP1AWADDR31", - "SAXIGP1AWADDR4": "PS7_SAXIGP1AWADDR4", - "SAXIGP1AWADDR5": "PS7_SAXIGP1AWADDR5", - "SAXIGP1AWADDR6": "PS7_SAXIGP1AWADDR6", - "SAXIGP1AWADDR7": "PS7_SAXIGP1AWADDR7", - "SAXIGP1AWADDR8": "PS7_SAXIGP1AWADDR8", - "SAXIGP1AWADDR9": "PS7_SAXIGP1AWADDR9", - "SAXIGP1AWBURST0": "PS7_SAXIGP1AWBURST0", - "SAXIGP1AWBURST1": "PS7_SAXIGP1AWBURST1", - "SAXIGP1AWCACHE0": "PS7_SAXIGP1AWCACHE0", - "SAXIGP1AWCACHE1": "PS7_SAXIGP1AWCACHE1", - "SAXIGP1AWCACHE2": "PS7_SAXIGP1AWCACHE2", - "SAXIGP1AWCACHE3": "PS7_SAXIGP1AWCACHE3", - "SAXIGP1AWID0": "PS7_SAXIGP1AWID0", - "SAXIGP1AWID1": "PS7_SAXIGP1AWID1", - "SAXIGP1AWID2": "PS7_SAXIGP1AWID2", - "SAXIGP1AWID3": "PS7_SAXIGP1AWID3", - "SAXIGP1AWID4": "PS7_SAXIGP1AWID4", - "SAXIGP1AWID5": "PS7_SAXIGP1AWID5", - "SAXIGP1AWLEN0": "PS7_SAXIGP1AWLEN0", - "SAXIGP1AWLEN1": "PS7_SAXIGP1AWLEN1", - "SAXIGP1AWLEN2": "PS7_SAXIGP1AWLEN2", - "SAXIGP1AWLEN3": "PS7_SAXIGP1AWLEN3", - "SAXIGP1AWLOCK0": "PS7_SAXIGP1AWLOCK0", - "SAXIGP1AWLOCK1": "PS7_SAXIGP1AWLOCK1", - "SAXIGP1AWPROT0": "PS7_SAXIGP1AWPROT0", - "SAXIGP1AWPROT1": "PS7_SAXIGP1AWPROT1", - "SAXIGP1AWPROT2": "PS7_SAXIGP1AWPROT2", - "SAXIGP1AWQOS0": "PS7_SAXIGP1AWQOS0", - "SAXIGP1AWQOS1": "PS7_SAXIGP1AWQOS1", - "SAXIGP1AWQOS2": "PS7_SAXIGP1AWQOS2", - "SAXIGP1AWQOS3": "PS7_SAXIGP1AWQOS3", - "SAXIGP1AWREADY": "PS7_SAXIGP1AWREADY", - "SAXIGP1AWSIZE0": "PS7_SAXIGP1AWSIZE0", - "SAXIGP1AWSIZE1": "PS7_SAXIGP1AWSIZE1", - "SAXIGP1AWVALID": "PS7_SAXIGP1AWVALID", - "SAXIGP1BID0": "PS7_SAXIGP1BID0", - "SAXIGP1BID1": "PS7_SAXIGP1BID1", - "SAXIGP1BID2": "PS7_SAXIGP1BID2", - "SAXIGP1BID3": "PS7_SAXIGP1BID3", - "SAXIGP1BID4": "PS7_SAXIGP1BID4", - "SAXIGP1BID5": "PS7_SAXIGP1BID5", - "SAXIGP1BREADY": "PS7_SAXIGP1BREADY", - "SAXIGP1BRESP0": "PS7_SAXIGP1BRESP0", - "SAXIGP1BRESP1": "PS7_SAXIGP1BRESP1", - "SAXIGP1BVALID": "PS7_SAXIGP1BVALID", - "SAXIGP1RDATA0": "PS7_SAXIGP1RDATA0", - "SAXIGP1RDATA1": "PS7_SAXIGP1RDATA1", - "SAXIGP1RDATA10": "PS7_SAXIGP1RDATA10", - "SAXIGP1RDATA11": "PS7_SAXIGP1RDATA11", - "SAXIGP1RDATA12": "PS7_SAXIGP1RDATA12", - "SAXIGP1RDATA13": "PS7_SAXIGP1RDATA13", - "SAXIGP1RDATA14": "PS7_SAXIGP1RDATA14", - "SAXIGP1RDATA15": "PS7_SAXIGP1RDATA15", - "SAXIGP1RDATA16": "PS7_SAXIGP1RDATA16", - "SAXIGP1RDATA17": "PS7_SAXIGP1RDATA17", - "SAXIGP1RDATA18": "PS7_SAXIGP1RDATA18", - "SAXIGP1RDATA19": "PS7_SAXIGP1RDATA19", - "SAXIGP1RDATA2": "PS7_SAXIGP1RDATA2", - "SAXIGP1RDATA20": "PS7_SAXIGP1RDATA20", - "SAXIGP1RDATA21": "PS7_SAXIGP1RDATA21", - "SAXIGP1RDATA22": "PS7_SAXIGP1RDATA22", - "SAXIGP1RDATA23": "PS7_SAXIGP1RDATA23", - "SAXIGP1RDATA24": "PS7_SAXIGP1RDATA24", - "SAXIGP1RDATA25": "PS7_SAXIGP1RDATA25", - "SAXIGP1RDATA26": "PS7_SAXIGP1RDATA26", - "SAXIGP1RDATA27": "PS7_SAXIGP1RDATA27", - "SAXIGP1RDATA28": "PS7_SAXIGP1RDATA28", - "SAXIGP1RDATA29": "PS7_SAXIGP1RDATA29", - "SAXIGP1RDATA3": "PS7_SAXIGP1RDATA3", - "SAXIGP1RDATA30": "PS7_SAXIGP1RDATA30", - "SAXIGP1RDATA31": "PS7_SAXIGP1RDATA31", - "SAXIGP1RDATA4": "PS7_SAXIGP1RDATA4", - "SAXIGP1RDATA5": "PS7_SAXIGP1RDATA5", - "SAXIGP1RDATA6": "PS7_SAXIGP1RDATA6", - "SAXIGP1RDATA7": "PS7_SAXIGP1RDATA7", - "SAXIGP1RDATA8": "PS7_SAXIGP1RDATA8", - "SAXIGP1RDATA9": "PS7_SAXIGP1RDATA9", - "SAXIGP1RID0": "PS7_SAXIGP1RID0", - "SAXIGP1RID1": "PS7_SAXIGP1RID1", - "SAXIGP1RID2": "PS7_SAXIGP1RID2", - "SAXIGP1RID3": "PS7_SAXIGP1RID3", - "SAXIGP1RID4": "PS7_SAXIGP1RID4", - "SAXIGP1RID5": "PS7_SAXIGP1RID5", - "SAXIGP1RLAST": "PS7_SAXIGP1RLAST", - "SAXIGP1RREADY": "PS7_SAXIGP1RREADY", - "SAXIGP1RRESP0": "PS7_SAXIGP1RRESP0", - "SAXIGP1RRESP1": "PS7_SAXIGP1RRESP1", - "SAXIGP1RVALID": "PS7_SAXIGP1RVALID", - "SAXIGP1WDATA0": "PS7_SAXIGP1WDATA0", - "SAXIGP1WDATA1": "PS7_SAXIGP1WDATA1", - "SAXIGP1WDATA10": "PS7_SAXIGP1WDATA10", - "SAXIGP1WDATA11": "PS7_SAXIGP1WDATA11", - "SAXIGP1WDATA12": "PS7_SAXIGP1WDATA12", - "SAXIGP1WDATA13": "PS7_SAXIGP1WDATA13", - "SAXIGP1WDATA14": "PS7_SAXIGP1WDATA14", - "SAXIGP1WDATA15": "PS7_SAXIGP1WDATA15", - "SAXIGP1WDATA16": "PS7_SAXIGP1WDATA16", - "SAXIGP1WDATA17": "PS7_SAXIGP1WDATA17", - "SAXIGP1WDATA18": "PS7_SAXIGP1WDATA18", - "SAXIGP1WDATA19": "PS7_SAXIGP1WDATA19", - "SAXIGP1WDATA2": "PS7_SAXIGP1WDATA2", - "SAXIGP1WDATA20": "PS7_SAXIGP1WDATA20", - "SAXIGP1WDATA21": "PS7_SAXIGP1WDATA21", - "SAXIGP1WDATA22": "PS7_SAXIGP1WDATA22", - "SAXIGP1WDATA23": "PS7_SAXIGP1WDATA23", - "SAXIGP1WDATA24": "PS7_SAXIGP1WDATA24", - "SAXIGP1WDATA25": "PS7_SAXIGP1WDATA25", - "SAXIGP1WDATA26": "PS7_SAXIGP1WDATA26", - "SAXIGP1WDATA27": "PS7_SAXIGP1WDATA27", - "SAXIGP1WDATA28": "PS7_SAXIGP1WDATA28", - "SAXIGP1WDATA29": "PS7_SAXIGP1WDATA29", - "SAXIGP1WDATA3": "PS7_SAXIGP1WDATA3", - "SAXIGP1WDATA30": "PS7_SAXIGP1WDATA30", - "SAXIGP1WDATA31": "PS7_SAXIGP1WDATA31", - "SAXIGP1WDATA4": "PS7_SAXIGP1WDATA4", - "SAXIGP1WDATA5": "PS7_SAXIGP1WDATA5", - "SAXIGP1WDATA6": "PS7_SAXIGP1WDATA6", - "SAXIGP1WDATA7": "PS7_SAXIGP1WDATA7", - "SAXIGP1WDATA8": "PS7_SAXIGP1WDATA8", - "SAXIGP1WDATA9": "PS7_SAXIGP1WDATA9", - "SAXIGP1WID0": "PS7_SAXIGP1WID0", - "SAXIGP1WID1": "PS7_SAXIGP1WID1", - "SAXIGP1WID2": "PS7_SAXIGP1WID2", - "SAXIGP1WID3": "PS7_SAXIGP1WID3", - "SAXIGP1WID4": "PS7_SAXIGP1WID4", - "SAXIGP1WID5": "PS7_SAXIGP1WID5", - "SAXIGP1WLAST": "PS7_SAXIGP1WLAST", - "SAXIGP1WREADY": "PS7_SAXIGP1WREADY", - "SAXIGP1WSTRB0": "PS7_SAXIGP1WSTRB0", - "SAXIGP1WSTRB1": "PS7_SAXIGP1WSTRB1", - "SAXIGP1WSTRB2": "PS7_SAXIGP1WSTRB2", - "SAXIGP1WSTRB3": "PS7_SAXIGP1WSTRB3", - "SAXIGP1WVALID": "PS7_SAXIGP1WVALID", - "SAXIHP0ACLK": "PS7_SAXIHP0ACLK", - "SAXIHP0ARADDR0": "PS7_SAXIHP0ARADDR0", - "SAXIHP0ARADDR1": "PS7_SAXIHP0ARADDR1", - "SAXIHP0ARADDR10": "PS7_SAXIHP0ARADDR10", - "SAXIHP0ARADDR11": "PS7_SAXIHP0ARADDR11", - "SAXIHP0ARADDR12": "PS7_SAXIHP0ARADDR12", - "SAXIHP0ARADDR13": "PS7_SAXIHP0ARADDR13", - "SAXIHP0ARADDR14": "PS7_SAXIHP0ARADDR14", - "SAXIHP0ARADDR15": "PS7_SAXIHP0ARADDR15", - "SAXIHP0ARADDR16": "PS7_SAXIHP0ARADDR16", - "SAXIHP0ARADDR17": "PS7_SAXIHP0ARADDR17", - "SAXIHP0ARADDR18": "PS7_SAXIHP0ARADDR18", - "SAXIHP0ARADDR19": "PS7_SAXIHP0ARADDR19", - "SAXIHP0ARADDR2": "PS7_SAXIHP0ARADDR2", - "SAXIHP0ARADDR20": "PS7_SAXIHP0ARADDR20", - "SAXIHP0ARADDR21": "PS7_SAXIHP0ARADDR21", - "SAXIHP0ARADDR22": "PS7_SAXIHP0ARADDR22", - "SAXIHP0ARADDR23": "PS7_SAXIHP0ARADDR23", - "SAXIHP0ARADDR24": "PS7_SAXIHP0ARADDR24", - "SAXIHP0ARADDR25": "PS7_SAXIHP0ARADDR25", - "SAXIHP0ARADDR26": "PS7_SAXIHP0ARADDR26", - "SAXIHP0ARADDR27": "PS7_SAXIHP0ARADDR27", - "SAXIHP0ARADDR28": "PS7_SAXIHP0ARADDR28", - "SAXIHP0ARADDR29": "PS7_SAXIHP0ARADDR29", - "SAXIHP0ARADDR3": "PS7_SAXIHP0ARADDR3", - "SAXIHP0ARADDR30": "PS7_SAXIHP0ARADDR30", - "SAXIHP0ARADDR31": "PS7_SAXIHP0ARADDR31", - "SAXIHP0ARADDR4": "PS7_SAXIHP0ARADDR4", - "SAXIHP0ARADDR5": "PS7_SAXIHP0ARADDR5", - "SAXIHP0ARADDR6": "PS7_SAXIHP0ARADDR6", - "SAXIHP0ARADDR7": "PS7_SAXIHP0ARADDR7", - "SAXIHP0ARADDR8": "PS7_SAXIHP0ARADDR8", - "SAXIHP0ARADDR9": "PS7_SAXIHP0ARADDR9", - "SAXIHP0ARBURST0": "PS7_SAXIHP0ARBURST0", - "SAXIHP0ARBURST1": "PS7_SAXIHP0ARBURST1", - "SAXIHP0ARCACHE0": "PS7_SAXIHP0ARCACHE0", - "SAXIHP0ARCACHE1": "PS7_SAXIHP0ARCACHE1", - "SAXIHP0ARCACHE2": "PS7_SAXIHP0ARCACHE2", - "SAXIHP0ARCACHE3": "PS7_SAXIHP0ARCACHE3", - "SAXIHP0ARESETN": "PS7_SAXIHP0ARESETN", - "SAXIHP0ARID0": "PS7_SAXIHP0ARID0", - "SAXIHP0ARID1": "PS7_SAXIHP0ARID1", - "SAXIHP0ARID2": "PS7_SAXIHP0ARID2", - "SAXIHP0ARID3": "PS7_SAXIHP0ARID3", - "SAXIHP0ARID4": "PS7_SAXIHP0ARID4", - "SAXIHP0ARID5": "PS7_SAXIHP0ARID5", - "SAXIHP0ARLEN0": "PS7_SAXIHP0ARLEN0", - "SAXIHP0ARLEN1": "PS7_SAXIHP0ARLEN1", - "SAXIHP0ARLEN2": "PS7_SAXIHP0ARLEN2", - "SAXIHP0ARLEN3": "PS7_SAXIHP0ARLEN3", - "SAXIHP0ARLOCK0": "PS7_SAXIHP0ARLOCK0", - "SAXIHP0ARLOCK1": "PS7_SAXIHP0ARLOCK1", - "SAXIHP0ARPROT0": "PS7_SAXIHP0ARPROT0", - "SAXIHP0ARPROT1": "PS7_SAXIHP0ARPROT1", - "SAXIHP0ARPROT2": "PS7_SAXIHP0ARPROT2", - "SAXIHP0ARQOS0": "PS7_SAXIHP0ARQOS0", - "SAXIHP0ARQOS1": "PS7_SAXIHP0ARQOS1", - "SAXIHP0ARQOS2": "PS7_SAXIHP0ARQOS2", - "SAXIHP0ARQOS3": "PS7_SAXIHP0ARQOS3", - "SAXIHP0ARREADY": "PS7_SAXIHP0ARREADY", - "SAXIHP0ARSIZE0": "PS7_SAXIHP0ARSIZE0", - "SAXIHP0ARSIZE1": "PS7_SAXIHP0ARSIZE1", - "SAXIHP0ARVALID": "PS7_SAXIHP0ARVALID", - "SAXIHP0AWADDR0": "PS7_SAXIHP0AWADDR0", - "SAXIHP0AWADDR1": "PS7_SAXIHP0AWADDR1", - "SAXIHP0AWADDR10": "PS7_SAXIHP0AWADDR10", - "SAXIHP0AWADDR11": "PS7_SAXIHP0AWADDR11", - "SAXIHP0AWADDR12": "PS7_SAXIHP0AWADDR12", - "SAXIHP0AWADDR13": "PS7_SAXIHP0AWADDR13", - "SAXIHP0AWADDR14": "PS7_SAXIHP0AWADDR14", - "SAXIHP0AWADDR15": "PS7_SAXIHP0AWADDR15", - "SAXIHP0AWADDR16": "PS7_SAXIHP0AWADDR16", - "SAXIHP0AWADDR17": "PS7_SAXIHP0AWADDR17", - "SAXIHP0AWADDR18": "PS7_SAXIHP0AWADDR18", - "SAXIHP0AWADDR19": "PS7_SAXIHP0AWADDR19", - "SAXIHP0AWADDR2": "PS7_SAXIHP0AWADDR2", - "SAXIHP0AWADDR20": "PS7_SAXIHP0AWADDR20", - "SAXIHP0AWADDR21": "PS7_SAXIHP0AWADDR21", - "SAXIHP0AWADDR22": "PS7_SAXIHP0AWADDR22", - "SAXIHP0AWADDR23": "PS7_SAXIHP0AWADDR23", - "SAXIHP0AWADDR24": "PS7_SAXIHP0AWADDR24", - "SAXIHP0AWADDR25": "PS7_SAXIHP0AWADDR25", - "SAXIHP0AWADDR26": "PS7_SAXIHP0AWADDR26", - "SAXIHP0AWADDR27": "PS7_SAXIHP0AWADDR27", - "SAXIHP0AWADDR28": "PS7_SAXIHP0AWADDR28", - "SAXIHP0AWADDR29": "PS7_SAXIHP0AWADDR29", - "SAXIHP0AWADDR3": "PS7_SAXIHP0AWADDR3", - "SAXIHP0AWADDR30": "PS7_SAXIHP0AWADDR30", - "SAXIHP0AWADDR31": "PS7_SAXIHP0AWADDR31", - "SAXIHP0AWADDR4": "PS7_SAXIHP0AWADDR4", - "SAXIHP0AWADDR5": "PS7_SAXIHP0AWADDR5", - "SAXIHP0AWADDR6": "PS7_SAXIHP0AWADDR6", - "SAXIHP0AWADDR7": "PS7_SAXIHP0AWADDR7", - "SAXIHP0AWADDR8": "PS7_SAXIHP0AWADDR8", - "SAXIHP0AWADDR9": "PS7_SAXIHP0AWADDR9", - "SAXIHP0AWBURST0": "PS7_SAXIHP0AWBURST0", - "SAXIHP0AWBURST1": "PS7_SAXIHP0AWBURST1", - "SAXIHP0AWCACHE0": "PS7_SAXIHP0AWCACHE0", - "SAXIHP0AWCACHE1": "PS7_SAXIHP0AWCACHE1", - "SAXIHP0AWCACHE2": "PS7_SAXIHP0AWCACHE2", - "SAXIHP0AWCACHE3": "PS7_SAXIHP0AWCACHE3", - "SAXIHP0AWID0": "PS7_SAXIHP0AWID0", - "SAXIHP0AWID1": "PS7_SAXIHP0AWID1", - "SAXIHP0AWID2": "PS7_SAXIHP0AWID2", - "SAXIHP0AWID3": "PS7_SAXIHP0AWID3", - "SAXIHP0AWID4": "PS7_SAXIHP0AWID4", - "SAXIHP0AWID5": "PS7_SAXIHP0AWID5", - "SAXIHP0AWLEN0": "PS7_SAXIHP0AWLEN0", - "SAXIHP0AWLEN1": "PS7_SAXIHP0AWLEN1", - "SAXIHP0AWLEN2": "PS7_SAXIHP0AWLEN2", - "SAXIHP0AWLEN3": "PS7_SAXIHP0AWLEN3", - "SAXIHP0AWLOCK0": "PS7_SAXIHP0AWLOCK0", - "SAXIHP0AWLOCK1": "PS7_SAXIHP0AWLOCK1", - "SAXIHP0AWPROT0": "PS7_SAXIHP0AWPROT0", - "SAXIHP0AWPROT1": "PS7_SAXIHP0AWPROT1", - "SAXIHP0AWPROT2": "PS7_SAXIHP0AWPROT2", - "SAXIHP0AWQOS0": "PS7_SAXIHP0AWQOS0", - "SAXIHP0AWQOS1": "PS7_SAXIHP0AWQOS1", - "SAXIHP0AWQOS2": "PS7_SAXIHP0AWQOS2", - "SAXIHP0AWQOS3": "PS7_SAXIHP0AWQOS3", - "SAXIHP0AWREADY": "PS7_SAXIHP0AWREADY", - "SAXIHP0AWSIZE0": "PS7_SAXIHP0AWSIZE0", - "SAXIHP0AWSIZE1": "PS7_SAXIHP0AWSIZE1", - "SAXIHP0AWVALID": "PS7_SAXIHP0AWVALID", - "SAXIHP0BID0": "PS7_SAXIHP0BID0", - "SAXIHP0BID1": "PS7_SAXIHP0BID1", - "SAXIHP0BID2": "PS7_SAXIHP0BID2", - "SAXIHP0BID3": "PS7_SAXIHP0BID3", - "SAXIHP0BID4": "PS7_SAXIHP0BID4", - "SAXIHP0BID5": "PS7_SAXIHP0BID5", - "SAXIHP0BREADY": "PS7_SAXIHP0BREADY", - "SAXIHP0BRESP0": "PS7_SAXIHP0BRESP0", - "SAXIHP0BRESP1": "PS7_SAXIHP0BRESP1", - "SAXIHP0BVALID": "PS7_SAXIHP0BVALID", - "SAXIHP0RACOUNT0": "PS7_SAXIHP0RACOUNT0", - "SAXIHP0RACOUNT1": "PS7_SAXIHP0RACOUNT1", - "SAXIHP0RACOUNT2": "PS7_SAXIHP0RACOUNT2", - "SAXIHP0RCOUNT0": "PS7_SAXIHP0RCOUNT0", - "SAXIHP0RCOUNT1": "PS7_SAXIHP0RCOUNT1", - "SAXIHP0RCOUNT2": "PS7_SAXIHP0RCOUNT2", - "SAXIHP0RCOUNT3": "PS7_SAXIHP0RCOUNT3", - "SAXIHP0RCOUNT4": "PS7_SAXIHP0RCOUNT4", - "SAXIHP0RCOUNT5": "PS7_SAXIHP0RCOUNT5", - "SAXIHP0RCOUNT6": "PS7_SAXIHP0RCOUNT6", - "SAXIHP0RCOUNT7": "PS7_SAXIHP0RCOUNT7", - "SAXIHP0RDATA0": "PS7_SAXIHP0RDATA0", - "SAXIHP0RDATA1": "PS7_SAXIHP0RDATA1", - "SAXIHP0RDATA10": "PS7_SAXIHP0RDATA10", - "SAXIHP0RDATA11": "PS7_SAXIHP0RDATA11", - "SAXIHP0RDATA12": "PS7_SAXIHP0RDATA12", - "SAXIHP0RDATA13": "PS7_SAXIHP0RDATA13", - "SAXIHP0RDATA14": "PS7_SAXIHP0RDATA14", - "SAXIHP0RDATA15": "PS7_SAXIHP0RDATA15", - "SAXIHP0RDATA16": "PS7_SAXIHP0RDATA16", - "SAXIHP0RDATA17": "PS7_SAXIHP0RDATA17", - "SAXIHP0RDATA18": "PS7_SAXIHP0RDATA18", - "SAXIHP0RDATA19": "PS7_SAXIHP0RDATA19", - "SAXIHP0RDATA2": "PS7_SAXIHP0RDATA2", - "SAXIHP0RDATA20": "PS7_SAXIHP0RDATA20", - "SAXIHP0RDATA21": "PS7_SAXIHP0RDATA21", - "SAXIHP0RDATA22": "PS7_SAXIHP0RDATA22", - "SAXIHP0RDATA23": "PS7_SAXIHP0RDATA23", - "SAXIHP0RDATA24": "PS7_SAXIHP0RDATA24", - "SAXIHP0RDATA25": "PS7_SAXIHP0RDATA25", - "SAXIHP0RDATA26": "PS7_SAXIHP0RDATA26", - "SAXIHP0RDATA27": "PS7_SAXIHP0RDATA27", - "SAXIHP0RDATA28": "PS7_SAXIHP0RDATA28", - "SAXIHP0RDATA29": "PS7_SAXIHP0RDATA29", - "SAXIHP0RDATA3": "PS7_SAXIHP0RDATA3", - "SAXIHP0RDATA30": "PS7_SAXIHP0RDATA30", - "SAXIHP0RDATA31": "PS7_SAXIHP0RDATA31", - "SAXIHP0RDATA32": "PS7_SAXIHP0RDATA32", - "SAXIHP0RDATA33": "PS7_SAXIHP0RDATA33", - "SAXIHP0RDATA34": "PS7_SAXIHP0RDATA34", - "SAXIHP0RDATA35": "PS7_SAXIHP0RDATA35", - "SAXIHP0RDATA36": "PS7_SAXIHP0RDATA36", - "SAXIHP0RDATA37": "PS7_SAXIHP0RDATA37", - "SAXIHP0RDATA38": "PS7_SAXIHP0RDATA38", - "SAXIHP0RDATA39": "PS7_SAXIHP0RDATA39", - "SAXIHP0RDATA4": "PS7_SAXIHP0RDATA4", - "SAXIHP0RDATA40": "PS7_SAXIHP0RDATA40", - "SAXIHP0RDATA41": "PS7_SAXIHP0RDATA41", - "SAXIHP0RDATA42": "PS7_SAXIHP0RDATA42", - "SAXIHP0RDATA43": "PS7_SAXIHP0RDATA43", - "SAXIHP0RDATA44": "PS7_SAXIHP0RDATA44", - "SAXIHP0RDATA45": "PS7_SAXIHP0RDATA45", - "SAXIHP0RDATA46": "PS7_SAXIHP0RDATA46", - "SAXIHP0RDATA47": "PS7_SAXIHP0RDATA47", - "SAXIHP0RDATA48": "PS7_SAXIHP0RDATA48", - "SAXIHP0RDATA49": "PS7_SAXIHP0RDATA49", - "SAXIHP0RDATA5": "PS7_SAXIHP0RDATA5", - "SAXIHP0RDATA50": "PS7_SAXIHP0RDATA50", - "SAXIHP0RDATA51": "PS7_SAXIHP0RDATA51", - "SAXIHP0RDATA52": "PS7_SAXIHP0RDATA52", - "SAXIHP0RDATA53": "PS7_SAXIHP0RDATA53", - "SAXIHP0RDATA54": "PS7_SAXIHP0RDATA54", - "SAXIHP0RDATA55": "PS7_SAXIHP0RDATA55", - "SAXIHP0RDATA56": "PS7_SAXIHP0RDATA56", - "SAXIHP0RDATA57": "PS7_SAXIHP0RDATA57", - "SAXIHP0RDATA58": "PS7_SAXIHP0RDATA58", - "SAXIHP0RDATA59": "PS7_SAXIHP0RDATA59", - "SAXIHP0RDATA6": "PS7_SAXIHP0RDATA6", - "SAXIHP0RDATA60": "PS7_SAXIHP0RDATA60", - "SAXIHP0RDATA61": "PS7_SAXIHP0RDATA61", - "SAXIHP0RDATA62": "PS7_SAXIHP0RDATA62", - "SAXIHP0RDATA63": "PS7_SAXIHP0RDATA63", - "SAXIHP0RDATA7": "PS7_SAXIHP0RDATA7", - "SAXIHP0RDATA8": "PS7_SAXIHP0RDATA8", - "SAXIHP0RDATA9": "PS7_SAXIHP0RDATA9", - "SAXIHP0RDISSUECAP1EN": "PS7_SAXIHP0RDISSUECAP1EN", - "SAXIHP0RID0": "PS7_SAXIHP0RID0", - "SAXIHP0RID1": "PS7_SAXIHP0RID1", - "SAXIHP0RID2": "PS7_SAXIHP0RID2", - "SAXIHP0RID3": "PS7_SAXIHP0RID3", - "SAXIHP0RID4": "PS7_SAXIHP0RID4", - "SAXIHP0RID5": "PS7_SAXIHP0RID5", - "SAXIHP0RLAST": "PS7_SAXIHP0RLAST", - "SAXIHP0RREADY": "PS7_SAXIHP0RREADY", - "SAXIHP0RRESP0": "PS7_SAXIHP0RRESP0", - "SAXIHP0RRESP1": "PS7_SAXIHP0RRESP1", - "SAXIHP0RVALID": "PS7_SAXIHP0RVALID", - "SAXIHP0WACOUNT0": "PS7_SAXIHP0WACOUNT0", - "SAXIHP0WACOUNT1": "PS7_SAXIHP0WACOUNT1", - "SAXIHP0WACOUNT2": "PS7_SAXIHP0WACOUNT2", - "SAXIHP0WACOUNT3": "PS7_SAXIHP0WACOUNT3", - "SAXIHP0WACOUNT4": "PS7_SAXIHP0WACOUNT4", - "SAXIHP0WACOUNT5": "PS7_SAXIHP0WACOUNT5", - "SAXIHP0WCOUNT0": "PS7_SAXIHP0WCOUNT0", - "SAXIHP0WCOUNT1": "PS7_SAXIHP0WCOUNT1", - "SAXIHP0WCOUNT2": "PS7_SAXIHP0WCOUNT2", - "SAXIHP0WCOUNT3": "PS7_SAXIHP0WCOUNT3", - "SAXIHP0WCOUNT4": "PS7_SAXIHP0WCOUNT4", - "SAXIHP0WCOUNT5": "PS7_SAXIHP0WCOUNT5", - "SAXIHP0WCOUNT6": "PS7_SAXIHP0WCOUNT6", - "SAXIHP0WCOUNT7": "PS7_SAXIHP0WCOUNT7", - "SAXIHP0WDATA0": "PS7_SAXIHP0WDATA0", - "SAXIHP0WDATA1": "PS7_SAXIHP0WDATA1", - "SAXIHP0WDATA10": "PS7_SAXIHP0WDATA10", - "SAXIHP0WDATA11": "PS7_SAXIHP0WDATA11", - "SAXIHP0WDATA12": "PS7_SAXIHP0WDATA12", - "SAXIHP0WDATA13": "PS7_SAXIHP0WDATA13", - "SAXIHP0WDATA14": "PS7_SAXIHP0WDATA14", - "SAXIHP0WDATA15": "PS7_SAXIHP0WDATA15", - "SAXIHP0WDATA16": "PS7_SAXIHP0WDATA16", - "SAXIHP0WDATA17": "PS7_SAXIHP0WDATA17", - "SAXIHP0WDATA18": "PS7_SAXIHP0WDATA18", - "SAXIHP0WDATA19": "PS7_SAXIHP0WDATA19", - "SAXIHP0WDATA2": "PS7_SAXIHP0WDATA2", - "SAXIHP0WDATA20": "PS7_SAXIHP0WDATA20", - "SAXIHP0WDATA21": "PS7_SAXIHP0WDATA21", - "SAXIHP0WDATA22": "PS7_SAXIHP0WDATA22", - "SAXIHP0WDATA23": "PS7_SAXIHP0WDATA23", - "SAXIHP0WDATA24": "PS7_SAXIHP0WDATA24", - "SAXIHP0WDATA25": "PS7_SAXIHP0WDATA25", - "SAXIHP0WDATA26": "PS7_SAXIHP0WDATA26", - "SAXIHP0WDATA27": "PS7_SAXIHP0WDATA27", - "SAXIHP0WDATA28": "PS7_SAXIHP0WDATA28", - "SAXIHP0WDATA29": "PS7_SAXIHP0WDATA29", - "SAXIHP0WDATA3": "PS7_SAXIHP0WDATA3", - "SAXIHP0WDATA30": "PS7_SAXIHP0WDATA30", - "SAXIHP0WDATA31": "PS7_SAXIHP0WDATA31", - "SAXIHP0WDATA32": "PS7_SAXIHP0WDATA32", - "SAXIHP0WDATA33": "PS7_SAXIHP0WDATA33", - "SAXIHP0WDATA34": "PS7_SAXIHP0WDATA34", - "SAXIHP0WDATA35": "PS7_SAXIHP0WDATA35", - "SAXIHP0WDATA36": "PS7_SAXIHP0WDATA36", - "SAXIHP0WDATA37": "PS7_SAXIHP0WDATA37", - "SAXIHP0WDATA38": "PS7_SAXIHP0WDATA38", - "SAXIHP0WDATA39": "PS7_SAXIHP0WDATA39", - "SAXIHP0WDATA4": "PS7_SAXIHP0WDATA4", - "SAXIHP0WDATA40": "PS7_SAXIHP0WDATA40", - "SAXIHP0WDATA41": "PS7_SAXIHP0WDATA41", - "SAXIHP0WDATA42": "PS7_SAXIHP0WDATA42", - "SAXIHP0WDATA43": "PS7_SAXIHP0WDATA43", - "SAXIHP0WDATA44": "PS7_SAXIHP0WDATA44", - "SAXIHP0WDATA45": "PS7_SAXIHP0WDATA45", - "SAXIHP0WDATA46": "PS7_SAXIHP0WDATA46", - "SAXIHP0WDATA47": "PS7_SAXIHP0WDATA47", - "SAXIHP0WDATA48": "PS7_SAXIHP0WDATA48", - "SAXIHP0WDATA49": "PS7_SAXIHP0WDATA49", - "SAXIHP0WDATA5": "PS7_SAXIHP0WDATA5", - "SAXIHP0WDATA50": "PS7_SAXIHP0WDATA50", - "SAXIHP0WDATA51": "PS7_SAXIHP0WDATA51", - "SAXIHP0WDATA52": "PS7_SAXIHP0WDATA52", - "SAXIHP0WDATA53": "PS7_SAXIHP0WDATA53", - "SAXIHP0WDATA54": "PS7_SAXIHP0WDATA54", - "SAXIHP0WDATA55": "PS7_SAXIHP0WDATA55", - "SAXIHP0WDATA56": "PS7_SAXIHP0WDATA56", - "SAXIHP0WDATA57": "PS7_SAXIHP0WDATA57", - "SAXIHP0WDATA58": "PS7_SAXIHP0WDATA58", - "SAXIHP0WDATA59": "PS7_SAXIHP0WDATA59", - "SAXIHP0WDATA6": "PS7_SAXIHP0WDATA6", - "SAXIHP0WDATA60": "PS7_SAXIHP0WDATA60", - "SAXIHP0WDATA61": "PS7_SAXIHP0WDATA61", - "SAXIHP0WDATA62": "PS7_SAXIHP0WDATA62", - "SAXIHP0WDATA63": "PS7_SAXIHP0WDATA63", - "SAXIHP0WDATA7": "PS7_SAXIHP0WDATA7", - "SAXIHP0WDATA8": "PS7_SAXIHP0WDATA8", - "SAXIHP0WDATA9": "PS7_SAXIHP0WDATA9", - "SAXIHP0WID0": "PS7_SAXIHP0WID0", - "SAXIHP0WID1": "PS7_SAXIHP0WID1", - "SAXIHP0WID2": "PS7_SAXIHP0WID2", - "SAXIHP0WID3": "PS7_SAXIHP0WID3", - "SAXIHP0WID4": "PS7_SAXIHP0WID4", - "SAXIHP0WID5": "PS7_SAXIHP0WID5", - "SAXIHP0WLAST": "PS7_SAXIHP0WLAST", - "SAXIHP0WREADY": "PS7_SAXIHP0WREADY", - "SAXIHP0WRISSUECAP1EN": "PS7_SAXIHP0WRISSUECAP1EN", - "SAXIHP0WSTRB0": "PS7_SAXIHP0WSTRB0", - "SAXIHP0WSTRB1": "PS7_SAXIHP0WSTRB1", - "SAXIHP0WSTRB2": "PS7_SAXIHP0WSTRB2", - "SAXIHP0WSTRB3": "PS7_SAXIHP0WSTRB3", - "SAXIHP0WSTRB4": "PS7_SAXIHP0WSTRB4", - "SAXIHP0WSTRB5": "PS7_SAXIHP0WSTRB5", - "SAXIHP0WSTRB6": "PS7_SAXIHP0WSTRB6", - "SAXIHP0WSTRB7": "PS7_SAXIHP0WSTRB7", - "SAXIHP0WVALID": "PS7_SAXIHP0WVALID", - "SAXIHP1ACLK": "PS7_SAXIHP1ACLK", - "SAXIHP1ARADDR0": "PS7_SAXIHP1ARADDR0", - "SAXIHP1ARADDR1": "PS7_SAXIHP1ARADDR1", - "SAXIHP1ARADDR10": "PS7_SAXIHP1ARADDR10", - "SAXIHP1ARADDR11": "PS7_SAXIHP1ARADDR11", - "SAXIHP1ARADDR12": "PS7_SAXIHP1ARADDR12", - "SAXIHP1ARADDR13": "PS7_SAXIHP1ARADDR13", - "SAXIHP1ARADDR14": "PS7_SAXIHP1ARADDR14", - "SAXIHP1ARADDR15": "PS7_SAXIHP1ARADDR15", - "SAXIHP1ARADDR16": "PS7_SAXIHP1ARADDR16", - "SAXIHP1ARADDR17": "PS7_SAXIHP1ARADDR17", - "SAXIHP1ARADDR18": "PS7_SAXIHP1ARADDR18", - "SAXIHP1ARADDR19": "PS7_SAXIHP1ARADDR19", - "SAXIHP1ARADDR2": "PS7_SAXIHP1ARADDR2", - "SAXIHP1ARADDR20": "PS7_SAXIHP1ARADDR20", - "SAXIHP1ARADDR21": "PS7_SAXIHP1ARADDR21", - "SAXIHP1ARADDR22": "PS7_SAXIHP1ARADDR22", - "SAXIHP1ARADDR23": "PS7_SAXIHP1ARADDR23", - "SAXIHP1ARADDR24": "PS7_SAXIHP1ARADDR24", - "SAXIHP1ARADDR25": "PS7_SAXIHP1ARADDR25", - "SAXIHP1ARADDR26": "PS7_SAXIHP1ARADDR26", - "SAXIHP1ARADDR27": "PS7_SAXIHP1ARADDR27", - "SAXIHP1ARADDR28": "PS7_SAXIHP1ARADDR28", - "SAXIHP1ARADDR29": "PS7_SAXIHP1ARADDR29", - "SAXIHP1ARADDR3": "PS7_SAXIHP1ARADDR3", - "SAXIHP1ARADDR30": "PS7_SAXIHP1ARADDR30", - "SAXIHP1ARADDR31": "PS7_SAXIHP1ARADDR31", - "SAXIHP1ARADDR4": "PS7_SAXIHP1ARADDR4", - "SAXIHP1ARADDR5": "PS7_SAXIHP1ARADDR5", - "SAXIHP1ARADDR6": "PS7_SAXIHP1ARADDR6", - "SAXIHP1ARADDR7": "PS7_SAXIHP1ARADDR7", - "SAXIHP1ARADDR8": "PS7_SAXIHP1ARADDR8", - "SAXIHP1ARADDR9": "PS7_SAXIHP1ARADDR9", - "SAXIHP1ARBURST0": "PS7_SAXIHP1ARBURST0", - "SAXIHP1ARBURST1": "PS7_SAXIHP1ARBURST1", - "SAXIHP1ARCACHE0": "PS7_SAXIHP1ARCACHE0", - "SAXIHP1ARCACHE1": "PS7_SAXIHP1ARCACHE1", - "SAXIHP1ARCACHE2": "PS7_SAXIHP1ARCACHE2", - "SAXIHP1ARCACHE3": "PS7_SAXIHP1ARCACHE3", - "SAXIHP1ARESETN": "PS7_SAXIHP1ARESETN", - "SAXIHP1ARID0": "PS7_SAXIHP1ARID0", - "SAXIHP1ARID1": "PS7_SAXIHP1ARID1", - "SAXIHP1ARID2": "PS7_SAXIHP1ARID2", - "SAXIHP1ARID3": "PS7_SAXIHP1ARID3", - "SAXIHP1ARID4": "PS7_SAXIHP1ARID4", - "SAXIHP1ARID5": "PS7_SAXIHP1ARID5", - "SAXIHP1ARLEN0": "PS7_SAXIHP1ARLEN0", - "SAXIHP1ARLEN1": "PS7_SAXIHP1ARLEN1", - "SAXIHP1ARLEN2": "PS7_SAXIHP1ARLEN2", - "SAXIHP1ARLEN3": "PS7_SAXIHP1ARLEN3", - "SAXIHP1ARLOCK0": "PS7_SAXIHP1ARLOCK0", - "SAXIHP1ARLOCK1": "PS7_SAXIHP1ARLOCK1", - "SAXIHP1ARPROT0": "PS7_SAXIHP1ARPROT0", - "SAXIHP1ARPROT1": "PS7_SAXIHP1ARPROT1", - "SAXIHP1ARPROT2": "PS7_SAXIHP1ARPROT2", - "SAXIHP1ARQOS0": "PS7_SAXIHP1ARQOS0", - "SAXIHP1ARQOS1": "PS7_SAXIHP1ARQOS1", - "SAXIHP1ARQOS2": "PS7_SAXIHP1ARQOS2", - "SAXIHP1ARQOS3": "PS7_SAXIHP1ARQOS3", - "SAXIHP1ARREADY": "PS7_SAXIHP1ARREADY", - "SAXIHP1ARSIZE0": "PS7_SAXIHP1ARSIZE0", - "SAXIHP1ARSIZE1": "PS7_SAXIHP1ARSIZE1", - "SAXIHP1ARVALID": "PS7_SAXIHP1ARVALID", - "SAXIHP1AWADDR0": "PS7_SAXIHP1AWADDR0", - "SAXIHP1AWADDR1": "PS7_SAXIHP1AWADDR1", - "SAXIHP1AWADDR10": "PS7_SAXIHP1AWADDR10", - "SAXIHP1AWADDR11": "PS7_SAXIHP1AWADDR11", - "SAXIHP1AWADDR12": "PS7_SAXIHP1AWADDR12", - "SAXIHP1AWADDR13": "PS7_SAXIHP1AWADDR13", - "SAXIHP1AWADDR14": "PS7_SAXIHP1AWADDR14", - "SAXIHP1AWADDR15": "PS7_SAXIHP1AWADDR15", - "SAXIHP1AWADDR16": "PS7_SAXIHP1AWADDR16", - "SAXIHP1AWADDR17": "PS7_SAXIHP1AWADDR17", - "SAXIHP1AWADDR18": "PS7_SAXIHP1AWADDR18", - "SAXIHP1AWADDR19": "PS7_SAXIHP1AWADDR19", - "SAXIHP1AWADDR2": "PS7_SAXIHP1AWADDR2", - "SAXIHP1AWADDR20": "PS7_SAXIHP1AWADDR20", - "SAXIHP1AWADDR21": "PS7_SAXIHP1AWADDR21", - "SAXIHP1AWADDR22": "PS7_SAXIHP1AWADDR22", - "SAXIHP1AWADDR23": "PS7_SAXIHP1AWADDR23", - "SAXIHP1AWADDR24": "PS7_SAXIHP1AWADDR24", - "SAXIHP1AWADDR25": "PS7_SAXIHP1AWADDR25", - "SAXIHP1AWADDR26": "PS7_SAXIHP1AWADDR26", - "SAXIHP1AWADDR27": "PS7_SAXIHP1AWADDR27", - "SAXIHP1AWADDR28": "PS7_SAXIHP1AWADDR28", - "SAXIHP1AWADDR29": "PS7_SAXIHP1AWADDR29", - "SAXIHP1AWADDR3": "PS7_SAXIHP1AWADDR3", - "SAXIHP1AWADDR30": "PS7_SAXIHP1AWADDR30", - "SAXIHP1AWADDR31": "PS7_SAXIHP1AWADDR31", - "SAXIHP1AWADDR4": "PS7_SAXIHP1AWADDR4", - "SAXIHP1AWADDR5": "PS7_SAXIHP1AWADDR5", - "SAXIHP1AWADDR6": "PS7_SAXIHP1AWADDR6", - "SAXIHP1AWADDR7": "PS7_SAXIHP1AWADDR7", - "SAXIHP1AWADDR8": "PS7_SAXIHP1AWADDR8", - "SAXIHP1AWADDR9": "PS7_SAXIHP1AWADDR9", - "SAXIHP1AWBURST0": "PS7_SAXIHP1AWBURST0", - "SAXIHP1AWBURST1": "PS7_SAXIHP1AWBURST1", - "SAXIHP1AWCACHE0": "PS7_SAXIHP1AWCACHE0", - "SAXIHP1AWCACHE1": "PS7_SAXIHP1AWCACHE1", - "SAXIHP1AWCACHE2": "PS7_SAXIHP1AWCACHE2", - "SAXIHP1AWCACHE3": "PS7_SAXIHP1AWCACHE3", - "SAXIHP1AWID0": "PS7_SAXIHP1AWID0", - "SAXIHP1AWID1": "PS7_SAXIHP1AWID1", - "SAXIHP1AWID2": "PS7_SAXIHP1AWID2", - "SAXIHP1AWID3": "PS7_SAXIHP1AWID3", - "SAXIHP1AWID4": "PS7_SAXIHP1AWID4", - "SAXIHP1AWID5": "PS7_SAXIHP1AWID5", - "SAXIHP1AWLEN0": "PS7_SAXIHP1AWLEN0", - "SAXIHP1AWLEN1": "PS7_SAXIHP1AWLEN1", - "SAXIHP1AWLEN2": "PS7_SAXIHP1AWLEN2", - "SAXIHP1AWLEN3": "PS7_SAXIHP1AWLEN3", - "SAXIHP1AWLOCK0": "PS7_SAXIHP1AWLOCK0", - "SAXIHP1AWLOCK1": "PS7_SAXIHP1AWLOCK1", - "SAXIHP1AWPROT0": "PS7_SAXIHP1AWPROT0", - "SAXIHP1AWPROT1": "PS7_SAXIHP1AWPROT1", - "SAXIHP1AWPROT2": "PS7_SAXIHP1AWPROT2", - "SAXIHP1AWQOS0": "PS7_SAXIHP1AWQOS0", - "SAXIHP1AWQOS1": "PS7_SAXIHP1AWQOS1", - "SAXIHP1AWQOS2": "PS7_SAXIHP1AWQOS2", - "SAXIHP1AWQOS3": "PS7_SAXIHP1AWQOS3", - "SAXIHP1AWREADY": "PS7_SAXIHP1AWREADY", - "SAXIHP1AWSIZE0": "PS7_SAXIHP1AWSIZE0", - "SAXIHP1AWSIZE1": "PS7_SAXIHP1AWSIZE1", - "SAXIHP1AWVALID": "PS7_SAXIHP1AWVALID", - "SAXIHP1BID0": "PS7_SAXIHP1BID0", - "SAXIHP1BID1": "PS7_SAXIHP1BID1", - "SAXIHP1BID2": "PS7_SAXIHP1BID2", - "SAXIHP1BID3": "PS7_SAXIHP1BID3", - "SAXIHP1BID4": "PS7_SAXIHP1BID4", - "SAXIHP1BID5": "PS7_SAXIHP1BID5", - "SAXIHP1BREADY": "PS7_SAXIHP1BREADY", - "SAXIHP1BRESP0": "PS7_SAXIHP1BRESP0", - "SAXIHP1BRESP1": "PS7_SAXIHP1BRESP1", - "SAXIHP1BVALID": "PS7_SAXIHP1BVALID", - "SAXIHP1RACOUNT0": "PS7_SAXIHP1RACOUNT0", - "SAXIHP1RACOUNT1": "PS7_SAXIHP1RACOUNT1", - "SAXIHP1RACOUNT2": "PS7_SAXIHP1RACOUNT2", - "SAXIHP1RCOUNT0": "PS7_SAXIHP1RCOUNT0", - "SAXIHP1RCOUNT1": "PS7_SAXIHP1RCOUNT1", - "SAXIHP1RCOUNT2": "PS7_SAXIHP1RCOUNT2", - "SAXIHP1RCOUNT3": "PS7_SAXIHP1RCOUNT3", - "SAXIHP1RCOUNT4": "PS7_SAXIHP1RCOUNT4", - "SAXIHP1RCOUNT5": "PS7_SAXIHP1RCOUNT5", - "SAXIHP1RCOUNT6": "PS7_SAXIHP1RCOUNT6", - "SAXIHP1RCOUNT7": "PS7_SAXIHP1RCOUNT7", - "SAXIHP1RDATA0": "PS7_SAXIHP1RDATA0", - "SAXIHP1RDATA1": "PS7_SAXIHP1RDATA1", - "SAXIHP1RDATA10": "PS7_SAXIHP1RDATA10", - "SAXIHP1RDATA11": "PS7_SAXIHP1RDATA11", - "SAXIHP1RDATA12": "PS7_SAXIHP1RDATA12", - "SAXIHP1RDATA13": "PS7_SAXIHP1RDATA13", - "SAXIHP1RDATA14": "PS7_SAXIHP1RDATA14", - "SAXIHP1RDATA15": "PS7_SAXIHP1RDATA15", - "SAXIHP1RDATA16": "PS7_SAXIHP1RDATA16", - "SAXIHP1RDATA17": "PS7_SAXIHP1RDATA17", - "SAXIHP1RDATA18": "PS7_SAXIHP1RDATA18", - "SAXIHP1RDATA19": "PS7_SAXIHP1RDATA19", - "SAXIHP1RDATA2": "PS7_SAXIHP1RDATA2", - "SAXIHP1RDATA20": "PS7_SAXIHP1RDATA20", - "SAXIHP1RDATA21": "PS7_SAXIHP1RDATA21", - "SAXIHP1RDATA22": "PS7_SAXIHP1RDATA22", - "SAXIHP1RDATA23": "PS7_SAXIHP1RDATA23", - "SAXIHP1RDATA24": "PS7_SAXIHP1RDATA24", - "SAXIHP1RDATA25": "PS7_SAXIHP1RDATA25", - "SAXIHP1RDATA26": "PS7_SAXIHP1RDATA26", - "SAXIHP1RDATA27": "PS7_SAXIHP1RDATA27", - "SAXIHP1RDATA28": "PS7_SAXIHP1RDATA28", - "SAXIHP1RDATA29": "PS7_SAXIHP1RDATA29", - "SAXIHP1RDATA3": "PS7_SAXIHP1RDATA3", - "SAXIHP1RDATA30": "PS7_SAXIHP1RDATA30", - "SAXIHP1RDATA31": "PS7_SAXIHP1RDATA31", - "SAXIHP1RDATA32": "PS7_SAXIHP1RDATA32", - "SAXIHP1RDATA33": "PS7_SAXIHP1RDATA33", - "SAXIHP1RDATA34": "PS7_SAXIHP1RDATA34", - "SAXIHP1RDATA35": "PS7_SAXIHP1RDATA35", - "SAXIHP1RDATA36": "PS7_SAXIHP1RDATA36", - "SAXIHP1RDATA37": "PS7_SAXIHP1RDATA37", - "SAXIHP1RDATA38": "PS7_SAXIHP1RDATA38", - "SAXIHP1RDATA39": "PS7_SAXIHP1RDATA39", - "SAXIHP1RDATA4": "PS7_SAXIHP1RDATA4", - "SAXIHP1RDATA40": "PS7_SAXIHP1RDATA40", - "SAXIHP1RDATA41": "PS7_SAXIHP1RDATA41", - "SAXIHP1RDATA42": "PS7_SAXIHP1RDATA42", - "SAXIHP1RDATA43": "PS7_SAXIHP1RDATA43", - "SAXIHP1RDATA44": "PS7_SAXIHP1RDATA44", - "SAXIHP1RDATA45": "PS7_SAXIHP1RDATA45", - "SAXIHP1RDATA46": "PS7_SAXIHP1RDATA46", - "SAXIHP1RDATA47": "PS7_SAXIHP1RDATA47", - "SAXIHP1RDATA48": "PS7_SAXIHP1RDATA48", - "SAXIHP1RDATA49": "PS7_SAXIHP1RDATA49", - "SAXIHP1RDATA5": "PS7_SAXIHP1RDATA5", - "SAXIHP1RDATA50": "PS7_SAXIHP1RDATA50", - "SAXIHP1RDATA51": "PS7_SAXIHP1RDATA51", - "SAXIHP1RDATA52": "PS7_SAXIHP1RDATA52", - "SAXIHP1RDATA53": "PS7_SAXIHP1RDATA53", - "SAXIHP1RDATA54": "PS7_SAXIHP1RDATA54", - "SAXIHP1RDATA55": "PS7_SAXIHP1RDATA55", - "SAXIHP1RDATA56": "PS7_SAXIHP1RDATA56", - "SAXIHP1RDATA57": "PS7_SAXIHP1RDATA57", - "SAXIHP1RDATA58": "PS7_SAXIHP1RDATA58", - "SAXIHP1RDATA59": "PS7_SAXIHP1RDATA59", - "SAXIHP1RDATA6": "PS7_SAXIHP1RDATA6", - "SAXIHP1RDATA60": "PS7_SAXIHP1RDATA60", - "SAXIHP1RDATA61": "PS7_SAXIHP1RDATA61", - "SAXIHP1RDATA62": "PS7_SAXIHP1RDATA62", - "SAXIHP1RDATA63": "PS7_SAXIHP1RDATA63", - "SAXIHP1RDATA7": "PS7_SAXIHP1RDATA7", - "SAXIHP1RDATA8": "PS7_SAXIHP1RDATA8", - "SAXIHP1RDATA9": "PS7_SAXIHP1RDATA9", - "SAXIHP1RDISSUECAP1EN": "PS7_SAXIHP1RDISSUECAP1EN", - "SAXIHP1RID0": "PS7_SAXIHP1RID0", - "SAXIHP1RID1": "PS7_SAXIHP1RID1", - "SAXIHP1RID2": "PS7_SAXIHP1RID2", - "SAXIHP1RID3": "PS7_SAXIHP1RID3", - "SAXIHP1RID4": "PS7_SAXIHP1RID4", - "SAXIHP1RID5": "PS7_SAXIHP1RID5", - "SAXIHP1RLAST": "PS7_SAXIHP1RLAST", - "SAXIHP1RREADY": "PS7_SAXIHP1RREADY", - "SAXIHP1RRESP0": "PS7_SAXIHP1RRESP0", - "SAXIHP1RRESP1": "PS7_SAXIHP1RRESP1", - "SAXIHP1RVALID": "PS7_SAXIHP1RVALID", - "SAXIHP1WACOUNT0": "PS7_SAXIHP1WACOUNT0", - "SAXIHP1WACOUNT1": "PS7_SAXIHP1WACOUNT1", - "SAXIHP1WACOUNT2": "PS7_SAXIHP1WACOUNT2", - "SAXIHP1WACOUNT3": "PS7_SAXIHP1WACOUNT3", - "SAXIHP1WACOUNT4": "PS7_SAXIHP1WACOUNT4", - "SAXIHP1WACOUNT5": "PS7_SAXIHP1WACOUNT5", - "SAXIHP1WCOUNT0": "PS7_SAXIHP1WCOUNT0", - "SAXIHP1WCOUNT1": "PS7_SAXIHP1WCOUNT1", - "SAXIHP1WCOUNT2": "PS7_SAXIHP1WCOUNT2", - "SAXIHP1WCOUNT3": "PS7_SAXIHP1WCOUNT3", - "SAXIHP1WCOUNT4": "PS7_SAXIHP1WCOUNT4", - "SAXIHP1WCOUNT5": "PS7_SAXIHP1WCOUNT5", - "SAXIHP1WCOUNT6": "PS7_SAXIHP1WCOUNT6", - "SAXIHP1WCOUNT7": "PS7_SAXIHP1WCOUNT7", - "SAXIHP1WDATA0": "PS7_SAXIHP1WDATA0", - "SAXIHP1WDATA1": "PS7_SAXIHP1WDATA1", - "SAXIHP1WDATA10": "PS7_SAXIHP1WDATA10", - "SAXIHP1WDATA11": "PS7_SAXIHP1WDATA11", - "SAXIHP1WDATA12": "PS7_SAXIHP1WDATA12", - "SAXIHP1WDATA13": "PS7_SAXIHP1WDATA13", - "SAXIHP1WDATA14": "PS7_SAXIHP1WDATA14", - "SAXIHP1WDATA15": "PS7_SAXIHP1WDATA15", - "SAXIHP1WDATA16": "PS7_SAXIHP1WDATA16", - "SAXIHP1WDATA17": "PS7_SAXIHP1WDATA17", - "SAXIHP1WDATA18": "PS7_SAXIHP1WDATA18", - "SAXIHP1WDATA19": "PS7_SAXIHP1WDATA19", - "SAXIHP1WDATA2": "PS7_SAXIHP1WDATA2", - "SAXIHP1WDATA20": "PS7_SAXIHP1WDATA20", - "SAXIHP1WDATA21": "PS7_SAXIHP1WDATA21", - "SAXIHP1WDATA22": "PS7_SAXIHP1WDATA22", - "SAXIHP1WDATA23": "PS7_SAXIHP1WDATA23", - "SAXIHP1WDATA24": "PS7_SAXIHP1WDATA24", - "SAXIHP1WDATA25": "PS7_SAXIHP1WDATA25", - "SAXIHP1WDATA26": "PS7_SAXIHP1WDATA26", - "SAXIHP1WDATA27": "PS7_SAXIHP1WDATA27", - "SAXIHP1WDATA28": "PS7_SAXIHP1WDATA28", - "SAXIHP1WDATA29": "PS7_SAXIHP1WDATA29", - "SAXIHP1WDATA3": "PS7_SAXIHP1WDATA3", - "SAXIHP1WDATA30": "PS7_SAXIHP1WDATA30", - "SAXIHP1WDATA31": "PS7_SAXIHP1WDATA31", - "SAXIHP1WDATA32": "PS7_SAXIHP1WDATA32", - "SAXIHP1WDATA33": "PS7_SAXIHP1WDATA33", - "SAXIHP1WDATA34": "PS7_SAXIHP1WDATA34", - "SAXIHP1WDATA35": "PS7_SAXIHP1WDATA35", - "SAXIHP1WDATA36": "PS7_SAXIHP1WDATA36", - "SAXIHP1WDATA37": "PS7_SAXIHP1WDATA37", - "SAXIHP1WDATA38": "PS7_SAXIHP1WDATA38", - "SAXIHP1WDATA39": "PS7_SAXIHP1WDATA39", - "SAXIHP1WDATA4": "PS7_SAXIHP1WDATA4", - "SAXIHP1WDATA40": "PS7_SAXIHP1WDATA40", - "SAXIHP1WDATA41": "PS7_SAXIHP1WDATA41", - "SAXIHP1WDATA42": "PS7_SAXIHP1WDATA42", - "SAXIHP1WDATA43": "PS7_SAXIHP1WDATA43", - "SAXIHP1WDATA44": "PS7_SAXIHP1WDATA44", - "SAXIHP1WDATA45": "PS7_SAXIHP1WDATA45", - "SAXIHP1WDATA46": "PS7_SAXIHP1WDATA46", - "SAXIHP1WDATA47": "PS7_SAXIHP1WDATA47", - "SAXIHP1WDATA48": "PS7_SAXIHP1WDATA48", - "SAXIHP1WDATA49": "PS7_SAXIHP1WDATA49", - "SAXIHP1WDATA5": "PS7_SAXIHP1WDATA5", - "SAXIHP1WDATA50": "PS7_SAXIHP1WDATA50", - "SAXIHP1WDATA51": "PS7_SAXIHP1WDATA51", - "SAXIHP1WDATA52": "PS7_SAXIHP1WDATA52", - "SAXIHP1WDATA53": "PS7_SAXIHP1WDATA53", - "SAXIHP1WDATA54": "PS7_SAXIHP1WDATA54", - "SAXIHP1WDATA55": "PS7_SAXIHP1WDATA55", - "SAXIHP1WDATA56": "PS7_SAXIHP1WDATA56", - "SAXIHP1WDATA57": "PS7_SAXIHP1WDATA57", - "SAXIHP1WDATA58": "PS7_SAXIHP1WDATA58", - "SAXIHP1WDATA59": "PS7_SAXIHP1WDATA59", - "SAXIHP1WDATA6": "PS7_SAXIHP1WDATA6", - "SAXIHP1WDATA60": "PS7_SAXIHP1WDATA60", - "SAXIHP1WDATA61": "PS7_SAXIHP1WDATA61", - "SAXIHP1WDATA62": "PS7_SAXIHP1WDATA62", - "SAXIHP1WDATA63": "PS7_SAXIHP1WDATA63", - "SAXIHP1WDATA7": "PS7_SAXIHP1WDATA7", - "SAXIHP1WDATA8": "PS7_SAXIHP1WDATA8", - "SAXIHP1WDATA9": "PS7_SAXIHP1WDATA9", - "SAXIHP1WID0": "PS7_SAXIHP1WID0", - "SAXIHP1WID1": "PS7_SAXIHP1WID1", - "SAXIHP1WID2": "PS7_SAXIHP1WID2", - "SAXIHP1WID3": "PS7_SAXIHP1WID3", - "SAXIHP1WID4": "PS7_SAXIHP1WID4", - "SAXIHP1WID5": "PS7_SAXIHP1WID5", - "SAXIHP1WLAST": "PS7_SAXIHP1WLAST", - "SAXIHP1WREADY": "PS7_SAXIHP1WREADY", - "SAXIHP1WRISSUECAP1EN": "PS7_SAXIHP1WRISSUECAP1EN", - "SAXIHP1WSTRB0": "PS7_SAXIHP1WSTRB0", - "SAXIHP1WSTRB1": "PS7_SAXIHP1WSTRB1", - "SAXIHP1WSTRB2": "PS7_SAXIHP1WSTRB2", - "SAXIHP1WSTRB3": "PS7_SAXIHP1WSTRB3", - "SAXIHP1WSTRB4": "PS7_SAXIHP1WSTRB4", - "SAXIHP1WSTRB5": "PS7_SAXIHP1WSTRB5", - "SAXIHP1WSTRB6": "PS7_SAXIHP1WSTRB6", - "SAXIHP1WSTRB7": "PS7_SAXIHP1WSTRB7", - "SAXIHP1WVALID": "PS7_SAXIHP1WVALID", - "SAXIHP2ACLK": "PS7_SAXIHP2ACLK", - "SAXIHP2ARADDR0": "PS7_SAXIHP2ARADDR0", - "SAXIHP2ARADDR1": "PS7_SAXIHP2ARADDR1", - "SAXIHP2ARADDR10": "PS7_SAXIHP2ARADDR10", - "SAXIHP2ARADDR11": "PS7_SAXIHP2ARADDR11", - "SAXIHP2ARADDR12": "PS7_SAXIHP2ARADDR12", - "SAXIHP2ARADDR13": "PS7_SAXIHP2ARADDR13", - "SAXIHP2ARADDR14": "PS7_SAXIHP2ARADDR14", - "SAXIHP2ARADDR15": "PS7_SAXIHP2ARADDR15", - "SAXIHP2ARADDR16": "PS7_SAXIHP2ARADDR16", - "SAXIHP2ARADDR17": "PS7_SAXIHP2ARADDR17", - "SAXIHP2ARADDR18": "PS7_SAXIHP2ARADDR18", - "SAXIHP2ARADDR19": "PS7_SAXIHP2ARADDR19", - "SAXIHP2ARADDR2": "PS7_SAXIHP2ARADDR2", - "SAXIHP2ARADDR20": "PS7_SAXIHP2ARADDR20", - "SAXIHP2ARADDR21": "PS7_SAXIHP2ARADDR21", - "SAXIHP2ARADDR22": "PS7_SAXIHP2ARADDR22", - "SAXIHP2ARADDR23": "PS7_SAXIHP2ARADDR23", - "SAXIHP2ARADDR24": "PS7_SAXIHP2ARADDR24", - "SAXIHP2ARADDR25": "PS7_SAXIHP2ARADDR25", - "SAXIHP2ARADDR26": "PS7_SAXIHP2ARADDR26", - "SAXIHP2ARADDR27": "PS7_SAXIHP2ARADDR27", - "SAXIHP2ARADDR28": "PS7_SAXIHP2ARADDR28", - "SAXIHP2ARADDR29": "PS7_SAXIHP2ARADDR29", - "SAXIHP2ARADDR3": "PS7_SAXIHP2ARADDR3", - "SAXIHP2ARADDR30": "PS7_SAXIHP2ARADDR30", - "SAXIHP2ARADDR31": "PS7_SAXIHP2ARADDR31", - "SAXIHP2ARADDR4": "PS7_SAXIHP2ARADDR4", - "SAXIHP2ARADDR5": "PS7_SAXIHP2ARADDR5", - "SAXIHP2ARADDR6": "PS7_SAXIHP2ARADDR6", - "SAXIHP2ARADDR7": "PS7_SAXIHP2ARADDR7", - "SAXIHP2ARADDR8": "PS7_SAXIHP2ARADDR8", - "SAXIHP2ARADDR9": "PS7_SAXIHP2ARADDR9", - "SAXIHP2ARBURST0": "PS7_SAXIHP2ARBURST0", - "SAXIHP2ARBURST1": "PS7_SAXIHP2ARBURST1", - "SAXIHP2ARCACHE0": "PS7_SAXIHP2ARCACHE0", - "SAXIHP2ARCACHE1": "PS7_SAXIHP2ARCACHE1", - "SAXIHP2ARCACHE2": "PS7_SAXIHP2ARCACHE2", - "SAXIHP2ARCACHE3": "PS7_SAXIHP2ARCACHE3", - "SAXIHP2ARESETN": "PS7_SAXIHP2ARESETN", - "SAXIHP2ARID0": "PS7_SAXIHP2ARID0", - "SAXIHP2ARID1": "PS7_SAXIHP2ARID1", - "SAXIHP2ARID2": "PS7_SAXIHP2ARID2", - "SAXIHP2ARID3": "PS7_SAXIHP2ARID3", - "SAXIHP2ARID4": "PS7_SAXIHP2ARID4", - "SAXIHP2ARID5": "PS7_SAXIHP2ARID5", - "SAXIHP2ARLEN0": "PS7_SAXIHP2ARLEN0", - "SAXIHP2ARLEN1": "PS7_SAXIHP2ARLEN1", - "SAXIHP2ARLEN2": "PS7_SAXIHP2ARLEN2", - "SAXIHP2ARLEN3": "PS7_SAXIHP2ARLEN3", - "SAXIHP2ARLOCK0": "PS7_SAXIHP2ARLOCK0", - "SAXIHP2ARLOCK1": "PS7_SAXIHP2ARLOCK1", - "SAXIHP2ARPROT0": "PS7_SAXIHP2ARPROT0", - "SAXIHP2ARPROT1": "PS7_SAXIHP2ARPROT1", - "SAXIHP2ARPROT2": "PS7_SAXIHP2ARPROT2", - "SAXIHP2ARQOS0": "PS7_SAXIHP2ARQOS0", - "SAXIHP2ARQOS1": "PS7_SAXIHP2ARQOS1", - "SAXIHP2ARQOS2": "PS7_SAXIHP2ARQOS2", - "SAXIHP2ARQOS3": "PS7_SAXIHP2ARQOS3", - "SAXIHP2ARREADY": "PS7_SAXIHP2ARREADY", - "SAXIHP2ARSIZE0": "PS7_SAXIHP2ARSIZE0", - "SAXIHP2ARSIZE1": "PS7_SAXIHP2ARSIZE1", - "SAXIHP2ARVALID": "PS7_SAXIHP2ARVALID", - "SAXIHP2AWADDR0": "PS7_SAXIHP2AWADDR0", - "SAXIHP2AWADDR1": "PS7_SAXIHP2AWADDR1", - "SAXIHP2AWADDR10": "PS7_SAXIHP2AWADDR10", - "SAXIHP2AWADDR11": "PS7_SAXIHP2AWADDR11", - "SAXIHP2AWADDR12": "PS7_SAXIHP2AWADDR12", - "SAXIHP2AWADDR13": "PS7_SAXIHP2AWADDR13", - "SAXIHP2AWADDR14": "PS7_SAXIHP2AWADDR14", - "SAXIHP2AWADDR15": "PS7_SAXIHP2AWADDR15", - "SAXIHP2AWADDR16": "PS7_SAXIHP2AWADDR16", - "SAXIHP2AWADDR17": "PS7_SAXIHP2AWADDR17", - "SAXIHP2AWADDR18": "PS7_SAXIHP2AWADDR18", - "SAXIHP2AWADDR19": "PS7_SAXIHP2AWADDR19", - "SAXIHP2AWADDR2": "PS7_SAXIHP2AWADDR2", - "SAXIHP2AWADDR20": "PS7_SAXIHP2AWADDR20", - "SAXIHP2AWADDR21": "PS7_SAXIHP2AWADDR21", - "SAXIHP2AWADDR22": "PS7_SAXIHP2AWADDR22", - "SAXIHP2AWADDR23": "PS7_SAXIHP2AWADDR23", - "SAXIHP2AWADDR24": "PS7_SAXIHP2AWADDR24", - "SAXIHP2AWADDR25": "PS7_SAXIHP2AWADDR25", - "SAXIHP2AWADDR26": "PS7_SAXIHP2AWADDR26", - "SAXIHP2AWADDR27": "PS7_SAXIHP2AWADDR27", - "SAXIHP2AWADDR28": "PS7_SAXIHP2AWADDR28", - "SAXIHP2AWADDR29": "PS7_SAXIHP2AWADDR29", - "SAXIHP2AWADDR3": "PS7_SAXIHP2AWADDR3", - "SAXIHP2AWADDR30": "PS7_SAXIHP2AWADDR30", - "SAXIHP2AWADDR31": "PS7_SAXIHP2AWADDR31", - "SAXIHP2AWADDR4": "PS7_SAXIHP2AWADDR4", - "SAXIHP2AWADDR5": "PS7_SAXIHP2AWADDR5", - "SAXIHP2AWADDR6": "PS7_SAXIHP2AWADDR6", - "SAXIHP2AWADDR7": "PS7_SAXIHP2AWADDR7", - "SAXIHP2AWADDR8": "PS7_SAXIHP2AWADDR8", - "SAXIHP2AWADDR9": "PS7_SAXIHP2AWADDR9", - "SAXIHP2AWBURST0": "PS7_SAXIHP2AWBURST0", - "SAXIHP2AWBURST1": "PS7_SAXIHP2AWBURST1", - "SAXIHP2AWCACHE0": "PS7_SAXIHP2AWCACHE0", - "SAXIHP2AWCACHE1": "PS7_SAXIHP2AWCACHE1", - "SAXIHP2AWCACHE2": "PS7_SAXIHP2AWCACHE2", - "SAXIHP2AWCACHE3": "PS7_SAXIHP2AWCACHE3", - "SAXIHP2AWID0": "PS7_SAXIHP2AWID0", - "SAXIHP2AWID1": "PS7_SAXIHP2AWID1", - "SAXIHP2AWID2": "PS7_SAXIHP2AWID2", - "SAXIHP2AWID3": "PS7_SAXIHP2AWID3", - "SAXIHP2AWID4": "PS7_SAXIHP2AWID4", - "SAXIHP2AWID5": "PS7_SAXIHP2AWID5", - "SAXIHP2AWLEN0": "PS7_SAXIHP2AWLEN0", - "SAXIHP2AWLEN1": "PS7_SAXIHP2AWLEN1", - "SAXIHP2AWLEN2": "PS7_SAXIHP2AWLEN2", - "SAXIHP2AWLEN3": "PS7_SAXIHP2AWLEN3", - "SAXIHP2AWLOCK0": "PS7_SAXIHP2AWLOCK0", - "SAXIHP2AWLOCK1": "PS7_SAXIHP2AWLOCK1", - "SAXIHP2AWPROT0": "PS7_SAXIHP2AWPROT0", - "SAXIHP2AWPROT1": "PS7_SAXIHP2AWPROT1", - "SAXIHP2AWPROT2": "PS7_SAXIHP2AWPROT2", - "SAXIHP2AWQOS0": "PS7_SAXIHP2AWQOS0", - "SAXIHP2AWQOS1": "PS7_SAXIHP2AWQOS1", - "SAXIHP2AWQOS2": "PS7_SAXIHP2AWQOS2", - "SAXIHP2AWQOS3": "PS7_SAXIHP2AWQOS3", - "SAXIHP2AWREADY": "PS7_SAXIHP2AWREADY", - "SAXIHP2AWSIZE0": "PS7_SAXIHP2AWSIZE0", - "SAXIHP2AWSIZE1": "PS7_SAXIHP2AWSIZE1", - "SAXIHP2AWVALID": "PS7_SAXIHP2AWVALID", - "SAXIHP2BID0": "PS7_SAXIHP2BID0", - "SAXIHP2BID1": "PS7_SAXIHP2BID1", - "SAXIHP2BID2": "PS7_SAXIHP2BID2", - "SAXIHP2BID3": "PS7_SAXIHP2BID3", - "SAXIHP2BID4": "PS7_SAXIHP2BID4", - "SAXIHP2BID5": "PS7_SAXIHP2BID5", - "SAXIHP2BREADY": "PS7_SAXIHP2BREADY", - "SAXIHP2BRESP0": "PS7_SAXIHP2BRESP0", - "SAXIHP2BRESP1": "PS7_SAXIHP2BRESP1", - "SAXIHP2BVALID": "PS7_SAXIHP2BVALID", - "SAXIHP2RACOUNT0": "PS7_SAXIHP2RACOUNT0", - "SAXIHP2RACOUNT1": "PS7_SAXIHP2RACOUNT1", - "SAXIHP2RACOUNT2": "PS7_SAXIHP2RACOUNT2", - "SAXIHP2RCOUNT0": "PS7_SAXIHP2RCOUNT0", - "SAXIHP2RCOUNT1": "PS7_SAXIHP2RCOUNT1", - "SAXIHP2RCOUNT2": "PS7_SAXIHP2RCOUNT2", - "SAXIHP2RCOUNT3": "PS7_SAXIHP2RCOUNT3", - "SAXIHP2RCOUNT4": "PS7_SAXIHP2RCOUNT4", - "SAXIHP2RCOUNT5": "PS7_SAXIHP2RCOUNT5", - "SAXIHP2RCOUNT6": "PS7_SAXIHP2RCOUNT6", - "SAXIHP2RCOUNT7": "PS7_SAXIHP2RCOUNT7", - "SAXIHP2RDATA0": "PS7_SAXIHP2RDATA0", - "SAXIHP2RDATA1": "PS7_SAXIHP2RDATA1", - "SAXIHP2RDATA10": "PS7_SAXIHP2RDATA10", - "SAXIHP2RDATA11": "PS7_SAXIHP2RDATA11", - "SAXIHP2RDATA12": "PS7_SAXIHP2RDATA12", - "SAXIHP2RDATA13": "PS7_SAXIHP2RDATA13", - "SAXIHP2RDATA14": "PS7_SAXIHP2RDATA14", - "SAXIHP2RDATA15": "PS7_SAXIHP2RDATA15", - "SAXIHP2RDATA16": "PS7_SAXIHP2RDATA16", - "SAXIHP2RDATA17": "PS7_SAXIHP2RDATA17", - "SAXIHP2RDATA18": "PS7_SAXIHP2RDATA18", - "SAXIHP2RDATA19": "PS7_SAXIHP2RDATA19", - "SAXIHP2RDATA2": "PS7_SAXIHP2RDATA2", - "SAXIHP2RDATA20": "PS7_SAXIHP2RDATA20", - "SAXIHP2RDATA21": "PS7_SAXIHP2RDATA21", - "SAXIHP2RDATA22": "PS7_SAXIHP2RDATA22", - "SAXIHP2RDATA23": "PS7_SAXIHP2RDATA23", - "SAXIHP2RDATA24": "PS7_SAXIHP2RDATA24", - "SAXIHP2RDATA25": "PS7_SAXIHP2RDATA25", - "SAXIHP2RDATA26": "PS7_SAXIHP2RDATA26", - "SAXIHP2RDATA27": "PS7_SAXIHP2RDATA27", - "SAXIHP2RDATA28": "PS7_SAXIHP2RDATA28", - "SAXIHP2RDATA29": "PS7_SAXIHP2RDATA29", - "SAXIHP2RDATA3": "PS7_SAXIHP2RDATA3", - "SAXIHP2RDATA30": "PS7_SAXIHP2RDATA30", - "SAXIHP2RDATA31": "PS7_SAXIHP2RDATA31", - "SAXIHP2RDATA32": "PS7_SAXIHP2RDATA32", - "SAXIHP2RDATA33": "PS7_SAXIHP2RDATA33", - "SAXIHP2RDATA34": "PS7_SAXIHP2RDATA34", - "SAXIHP2RDATA35": "PS7_SAXIHP2RDATA35", - "SAXIHP2RDATA36": "PS7_SAXIHP2RDATA36", - "SAXIHP2RDATA37": "PS7_SAXIHP2RDATA37", - "SAXIHP2RDATA38": "PS7_SAXIHP2RDATA38", - "SAXIHP2RDATA39": "PS7_SAXIHP2RDATA39", - "SAXIHP2RDATA4": "PS7_SAXIHP2RDATA4", - "SAXIHP2RDATA40": "PS7_SAXIHP2RDATA40", - "SAXIHP2RDATA41": "PS7_SAXIHP2RDATA41", - "SAXIHP2RDATA42": "PS7_SAXIHP2RDATA42", - "SAXIHP2RDATA43": "PS7_SAXIHP2RDATA43", - "SAXIHP2RDATA44": "PS7_SAXIHP2RDATA44", - "SAXIHP2RDATA45": "PS7_SAXIHP2RDATA45", - "SAXIHP2RDATA46": "PS7_SAXIHP2RDATA46", - "SAXIHP2RDATA47": "PS7_SAXIHP2RDATA47", - "SAXIHP2RDATA48": "PS7_SAXIHP2RDATA48", - "SAXIHP2RDATA49": "PS7_SAXIHP2RDATA49", - "SAXIHP2RDATA5": "PS7_SAXIHP2RDATA5", - "SAXIHP2RDATA50": "PS7_SAXIHP2RDATA50", - "SAXIHP2RDATA51": "PS7_SAXIHP2RDATA51", - "SAXIHP2RDATA52": "PS7_SAXIHP2RDATA52", - "SAXIHP2RDATA53": "PS7_SAXIHP2RDATA53", - "SAXIHP2RDATA54": "PS7_SAXIHP2RDATA54", - "SAXIHP2RDATA55": "PS7_SAXIHP2RDATA55", - "SAXIHP2RDATA56": "PS7_SAXIHP2RDATA56", - "SAXIHP2RDATA57": "PS7_SAXIHP2RDATA57", - "SAXIHP2RDATA58": "PS7_SAXIHP2RDATA58", - "SAXIHP2RDATA59": "PS7_SAXIHP2RDATA59", - "SAXIHP2RDATA6": "PS7_SAXIHP2RDATA6", - "SAXIHP2RDATA60": "PS7_SAXIHP2RDATA60", - "SAXIHP2RDATA61": "PS7_SAXIHP2RDATA61", - "SAXIHP2RDATA62": "PS7_SAXIHP2RDATA62", - "SAXIHP2RDATA63": "PS7_SAXIHP2RDATA63", - "SAXIHP2RDATA7": "PS7_SAXIHP2RDATA7", - "SAXIHP2RDATA8": "PS7_SAXIHP2RDATA8", - "SAXIHP2RDATA9": "PS7_SAXIHP2RDATA9", - "SAXIHP2RDISSUECAP1EN": "PS7_SAXIHP2RDISSUECAP1EN", - "SAXIHP2RID0": "PS7_SAXIHP2RID0", - "SAXIHP2RID1": "PS7_SAXIHP2RID1", - "SAXIHP2RID2": "PS7_SAXIHP2RID2", - "SAXIHP2RID3": "PS7_SAXIHP2RID3", - "SAXIHP2RID4": "PS7_SAXIHP2RID4", - "SAXIHP2RID5": "PS7_SAXIHP2RID5", - "SAXIHP2RLAST": "PS7_SAXIHP2RLAST", - "SAXIHP2RREADY": "PS7_SAXIHP2RREADY", - "SAXIHP2RRESP0": "PS7_SAXIHP2RRESP0", - "SAXIHP2RRESP1": "PS7_SAXIHP2RRESP1", - "SAXIHP2RVALID": "PS7_SAXIHP2RVALID", - "SAXIHP2WACOUNT0": "PS7_SAXIHP2WACOUNT0", - "SAXIHP2WACOUNT1": "PS7_SAXIHP2WACOUNT1", - "SAXIHP2WACOUNT2": "PS7_SAXIHP2WACOUNT2", - "SAXIHP2WACOUNT3": "PS7_SAXIHP2WACOUNT3", - "SAXIHP2WACOUNT4": "PS7_SAXIHP2WACOUNT4", - "SAXIHP2WACOUNT5": "PS7_SAXIHP2WACOUNT5", - "SAXIHP2WCOUNT0": "PS7_SAXIHP2WCOUNT0", - "SAXIHP2WCOUNT1": "PS7_SAXIHP2WCOUNT1", - "SAXIHP2WCOUNT2": "PS7_SAXIHP2WCOUNT2", - "SAXIHP2WCOUNT3": "PS7_SAXIHP2WCOUNT3", - "SAXIHP2WCOUNT4": "PS7_SAXIHP2WCOUNT4", - "SAXIHP2WCOUNT5": "PS7_SAXIHP2WCOUNT5", - "SAXIHP2WCOUNT6": "PS7_SAXIHP2WCOUNT6", - "SAXIHP2WCOUNT7": "PS7_SAXIHP2WCOUNT7", - "SAXIHP2WDATA0": "PS7_SAXIHP2WDATA0", - "SAXIHP2WDATA1": "PS7_SAXIHP2WDATA1", - "SAXIHP2WDATA10": "PS7_SAXIHP2WDATA10", - "SAXIHP2WDATA11": "PS7_SAXIHP2WDATA11", - "SAXIHP2WDATA12": "PS7_SAXIHP2WDATA12", - "SAXIHP2WDATA13": "PS7_SAXIHP2WDATA13", - "SAXIHP2WDATA14": "PS7_SAXIHP2WDATA14", - "SAXIHP2WDATA15": "PS7_SAXIHP2WDATA15", - "SAXIHP2WDATA16": "PS7_SAXIHP2WDATA16", - "SAXIHP2WDATA17": "PS7_SAXIHP2WDATA17", - "SAXIHP2WDATA18": "PS7_SAXIHP2WDATA18", - "SAXIHP2WDATA19": "PS7_SAXIHP2WDATA19", - "SAXIHP2WDATA2": "PS7_SAXIHP2WDATA2", - "SAXIHP2WDATA20": "PS7_SAXIHP2WDATA20", - "SAXIHP2WDATA21": "PS7_SAXIHP2WDATA21", - "SAXIHP2WDATA22": "PS7_SAXIHP2WDATA22", - "SAXIHP2WDATA23": "PS7_SAXIHP2WDATA23", - "SAXIHP2WDATA24": "PS7_SAXIHP2WDATA24", - "SAXIHP2WDATA25": "PS7_SAXIHP2WDATA25", - "SAXIHP2WDATA26": "PS7_SAXIHP2WDATA26", - "SAXIHP2WDATA27": "PS7_SAXIHP2WDATA27", - "SAXIHP2WDATA28": "PS7_SAXIHP2WDATA28", - "SAXIHP2WDATA29": "PS7_SAXIHP2WDATA29", - "SAXIHP2WDATA3": "PS7_SAXIHP2WDATA3", - "SAXIHP2WDATA30": "PS7_SAXIHP2WDATA30", - "SAXIHP2WDATA31": "PS7_SAXIHP2WDATA31", - "SAXIHP2WDATA32": "PS7_SAXIHP2WDATA32", - "SAXIHP2WDATA33": "PS7_SAXIHP2WDATA33", - "SAXIHP2WDATA34": "PS7_SAXIHP2WDATA34", - "SAXIHP2WDATA35": "PS7_SAXIHP2WDATA35", - "SAXIHP2WDATA36": "PS7_SAXIHP2WDATA36", - "SAXIHP2WDATA37": "PS7_SAXIHP2WDATA37", - "SAXIHP2WDATA38": "PS7_SAXIHP2WDATA38", - "SAXIHP2WDATA39": "PS7_SAXIHP2WDATA39", - "SAXIHP2WDATA4": "PS7_SAXIHP2WDATA4", - "SAXIHP2WDATA40": "PS7_SAXIHP2WDATA40", - "SAXIHP2WDATA41": "PS7_SAXIHP2WDATA41", - "SAXIHP2WDATA42": "PS7_SAXIHP2WDATA42", - "SAXIHP2WDATA43": "PS7_SAXIHP2WDATA43", - "SAXIHP2WDATA44": "PS7_SAXIHP2WDATA44", - "SAXIHP2WDATA45": "PS7_SAXIHP2WDATA45", - "SAXIHP2WDATA46": "PS7_SAXIHP2WDATA46", - "SAXIHP2WDATA47": "PS7_SAXIHP2WDATA47", - "SAXIHP2WDATA48": "PS7_SAXIHP2WDATA48", - "SAXIHP2WDATA49": "PS7_SAXIHP2WDATA49", - "SAXIHP2WDATA5": "PS7_SAXIHP2WDATA5", - "SAXIHP2WDATA50": "PS7_SAXIHP2WDATA50", - "SAXIHP2WDATA51": "PS7_SAXIHP2WDATA51", - "SAXIHP2WDATA52": "PS7_SAXIHP2WDATA52", - "SAXIHP2WDATA53": "PS7_SAXIHP2WDATA53", - "SAXIHP2WDATA54": "PS7_SAXIHP2WDATA54", - "SAXIHP2WDATA55": "PS7_SAXIHP2WDATA55", - "SAXIHP2WDATA56": "PS7_SAXIHP2WDATA56", - "SAXIHP2WDATA57": "PS7_SAXIHP2WDATA57", - "SAXIHP2WDATA58": "PS7_SAXIHP2WDATA58", - "SAXIHP2WDATA59": "PS7_SAXIHP2WDATA59", - "SAXIHP2WDATA6": "PS7_SAXIHP2WDATA6", - "SAXIHP2WDATA60": "PS7_SAXIHP2WDATA60", - "SAXIHP2WDATA61": "PS7_SAXIHP2WDATA61", - "SAXIHP2WDATA62": "PS7_SAXIHP2WDATA62", - "SAXIHP2WDATA63": "PS7_SAXIHP2WDATA63", - "SAXIHP2WDATA7": "PS7_SAXIHP2WDATA7", - "SAXIHP2WDATA8": "PS7_SAXIHP2WDATA8", - "SAXIHP2WDATA9": "PS7_SAXIHP2WDATA9", - "SAXIHP2WID0": "PS7_SAXIHP2WID0", - "SAXIHP2WID1": "PS7_SAXIHP2WID1", - "SAXIHP2WID2": "PS7_SAXIHP2WID2", - "SAXIHP2WID3": "PS7_SAXIHP2WID3", - "SAXIHP2WID4": "PS7_SAXIHP2WID4", - "SAXIHP2WID5": "PS7_SAXIHP2WID5", - "SAXIHP2WLAST": "PS7_SAXIHP2WLAST", - "SAXIHP2WREADY": "PS7_SAXIHP2WREADY", - "SAXIHP2WRISSUECAP1EN": "PS7_SAXIHP2WRISSUECAP1EN", - "SAXIHP2WSTRB0": "PS7_SAXIHP2WSTRB0", - "SAXIHP2WSTRB1": "PS7_SAXIHP2WSTRB1", - "SAXIHP2WSTRB2": "PS7_SAXIHP2WSTRB2", - "SAXIHP2WSTRB3": "PS7_SAXIHP2WSTRB3", - "SAXIHP2WSTRB4": "PS7_SAXIHP2WSTRB4", - "SAXIHP2WSTRB5": "PS7_SAXIHP2WSTRB5", - "SAXIHP2WSTRB6": "PS7_SAXIHP2WSTRB6", - "SAXIHP2WSTRB7": "PS7_SAXIHP2WSTRB7", - "SAXIHP2WVALID": "PS7_SAXIHP2WVALID", - "SAXIHP3ACLK": "PS7_SAXIHP3ACLK", - "SAXIHP3ARADDR0": "PS7_SAXIHP3ARADDR0", - "SAXIHP3ARADDR1": "PS7_SAXIHP3ARADDR1", - "SAXIHP3ARADDR10": "PS7_SAXIHP3ARADDR10", - "SAXIHP3ARADDR11": "PS7_SAXIHP3ARADDR11", - "SAXIHP3ARADDR12": "PS7_SAXIHP3ARADDR12", - "SAXIHP3ARADDR13": "PS7_SAXIHP3ARADDR13", - "SAXIHP3ARADDR14": "PS7_SAXIHP3ARADDR14", - "SAXIHP3ARADDR15": "PS7_SAXIHP3ARADDR15", - "SAXIHP3ARADDR16": "PS7_SAXIHP3ARADDR16", - "SAXIHP3ARADDR17": "PS7_SAXIHP3ARADDR17", - "SAXIHP3ARADDR18": "PS7_SAXIHP3ARADDR18", - "SAXIHP3ARADDR19": "PS7_SAXIHP3ARADDR19", - "SAXIHP3ARADDR2": "PS7_SAXIHP3ARADDR2", - "SAXIHP3ARADDR20": "PS7_SAXIHP3ARADDR20", - "SAXIHP3ARADDR21": "PS7_SAXIHP3ARADDR21", - "SAXIHP3ARADDR22": "PS7_SAXIHP3ARADDR22", - "SAXIHP3ARADDR23": "PS7_SAXIHP3ARADDR23", - "SAXIHP3ARADDR24": "PS7_SAXIHP3ARADDR24", - "SAXIHP3ARADDR25": "PS7_SAXIHP3ARADDR25", - "SAXIHP3ARADDR26": "PS7_SAXIHP3ARADDR26", - "SAXIHP3ARADDR27": "PS7_SAXIHP3ARADDR27", - "SAXIHP3ARADDR28": "PS7_SAXIHP3ARADDR28", - "SAXIHP3ARADDR29": "PS7_SAXIHP3ARADDR29", - "SAXIHP3ARADDR3": "PS7_SAXIHP3ARADDR3", - "SAXIHP3ARADDR30": "PS7_SAXIHP3ARADDR30", - "SAXIHP3ARADDR31": "PS7_SAXIHP3ARADDR31", - "SAXIHP3ARADDR4": "PS7_SAXIHP3ARADDR4", - "SAXIHP3ARADDR5": "PS7_SAXIHP3ARADDR5", - "SAXIHP3ARADDR6": "PS7_SAXIHP3ARADDR6", - "SAXIHP3ARADDR7": "PS7_SAXIHP3ARADDR7", - "SAXIHP3ARADDR8": "PS7_SAXIHP3ARADDR8", - "SAXIHP3ARADDR9": "PS7_SAXIHP3ARADDR9", - "SAXIHP3ARBURST0": "PS7_SAXIHP3ARBURST0", - "SAXIHP3ARBURST1": "PS7_SAXIHP3ARBURST1", - "SAXIHP3ARCACHE0": "PS7_SAXIHP3ARCACHE0", - "SAXIHP3ARCACHE1": "PS7_SAXIHP3ARCACHE1", - "SAXIHP3ARCACHE2": "PS7_SAXIHP3ARCACHE2", - "SAXIHP3ARCACHE3": "PS7_SAXIHP3ARCACHE3", - "SAXIHP3ARESETN": "PS7_SAXIHP3ARESETN", - "SAXIHP3ARID0": "PS7_SAXIHP3ARID0", - "SAXIHP3ARID1": "PS7_SAXIHP3ARID1", - "SAXIHP3ARID2": "PS7_SAXIHP3ARID2", - "SAXIHP3ARID3": "PS7_SAXIHP3ARID3", - "SAXIHP3ARID4": "PS7_SAXIHP3ARID4", - "SAXIHP3ARID5": "PS7_SAXIHP3ARID5", - "SAXIHP3ARLEN0": "PS7_SAXIHP3ARLEN0", - "SAXIHP3ARLEN1": "PS7_SAXIHP3ARLEN1", - "SAXIHP3ARLEN2": "PS7_SAXIHP3ARLEN2", - "SAXIHP3ARLEN3": "PS7_SAXIHP3ARLEN3", - "SAXIHP3ARLOCK0": "PS7_SAXIHP3ARLOCK0", - "SAXIHP3ARLOCK1": "PS7_SAXIHP3ARLOCK1", - "SAXIHP3ARPROT0": "PS7_SAXIHP3ARPROT0", - "SAXIHP3ARPROT1": "PS7_SAXIHP3ARPROT1", - "SAXIHP3ARPROT2": "PS7_SAXIHP3ARPROT2", - "SAXIHP3ARQOS0": "PS7_SAXIHP3ARQOS0", - "SAXIHP3ARQOS1": "PS7_SAXIHP3ARQOS1", - "SAXIHP3ARQOS2": "PS7_SAXIHP3ARQOS2", - "SAXIHP3ARQOS3": "PS7_SAXIHP3ARQOS3", - "SAXIHP3ARREADY": "PS7_SAXIHP3ARREADY", - "SAXIHP3ARSIZE0": "PS7_SAXIHP3ARSIZE0", - "SAXIHP3ARSIZE1": "PS7_SAXIHP3ARSIZE1", - "SAXIHP3ARVALID": "PS7_SAXIHP3ARVALID", - "SAXIHP3AWADDR0": "PS7_SAXIHP3AWADDR0", - "SAXIHP3AWADDR1": "PS7_SAXIHP3AWADDR1", - "SAXIHP3AWADDR10": "PS7_SAXIHP3AWADDR10", - "SAXIHP3AWADDR11": "PS7_SAXIHP3AWADDR11", - "SAXIHP3AWADDR12": "PS7_SAXIHP3AWADDR12", - "SAXIHP3AWADDR13": "PS7_SAXIHP3AWADDR13", - "SAXIHP3AWADDR14": "PS7_SAXIHP3AWADDR14", - "SAXIHP3AWADDR15": "PS7_SAXIHP3AWADDR15", - "SAXIHP3AWADDR16": "PS7_SAXIHP3AWADDR16", - "SAXIHP3AWADDR17": "PS7_SAXIHP3AWADDR17", - "SAXIHP3AWADDR18": "PS7_SAXIHP3AWADDR18", - "SAXIHP3AWADDR19": "PS7_SAXIHP3AWADDR19", - "SAXIHP3AWADDR2": "PS7_SAXIHP3AWADDR2", - "SAXIHP3AWADDR20": "PS7_SAXIHP3AWADDR20", - "SAXIHP3AWADDR21": "PS7_SAXIHP3AWADDR21", - "SAXIHP3AWADDR22": "PS7_SAXIHP3AWADDR22", - "SAXIHP3AWADDR23": "PS7_SAXIHP3AWADDR23", - "SAXIHP3AWADDR24": "PS7_SAXIHP3AWADDR24", - "SAXIHP3AWADDR25": "PS7_SAXIHP3AWADDR25", - "SAXIHP3AWADDR26": "PS7_SAXIHP3AWADDR26", - "SAXIHP3AWADDR27": "PS7_SAXIHP3AWADDR27", - "SAXIHP3AWADDR28": "PS7_SAXIHP3AWADDR28", - "SAXIHP3AWADDR29": "PS7_SAXIHP3AWADDR29", - "SAXIHP3AWADDR3": "PS7_SAXIHP3AWADDR3", - "SAXIHP3AWADDR30": "PS7_SAXIHP3AWADDR30", - "SAXIHP3AWADDR31": "PS7_SAXIHP3AWADDR31", - "SAXIHP3AWADDR4": "PS7_SAXIHP3AWADDR4", - "SAXIHP3AWADDR5": "PS7_SAXIHP3AWADDR5", - "SAXIHP3AWADDR6": "PS7_SAXIHP3AWADDR6", - "SAXIHP3AWADDR7": "PS7_SAXIHP3AWADDR7", - "SAXIHP3AWADDR8": "PS7_SAXIHP3AWADDR8", - "SAXIHP3AWADDR9": "PS7_SAXIHP3AWADDR9", - "SAXIHP3AWBURST0": "PS7_SAXIHP3AWBURST0", - "SAXIHP3AWBURST1": "PS7_SAXIHP3AWBURST1", - "SAXIHP3AWCACHE0": "PS7_SAXIHP3AWCACHE0", - "SAXIHP3AWCACHE1": "PS7_SAXIHP3AWCACHE1", - "SAXIHP3AWCACHE2": "PS7_SAXIHP3AWCACHE2", - "SAXIHP3AWCACHE3": "PS7_SAXIHP3AWCACHE3", - "SAXIHP3AWID0": "PS7_SAXIHP3AWID0", - "SAXIHP3AWID1": "PS7_SAXIHP3AWID1", - "SAXIHP3AWID2": "PS7_SAXIHP3AWID2", - "SAXIHP3AWID3": "PS7_SAXIHP3AWID3", - "SAXIHP3AWID4": "PS7_SAXIHP3AWID4", - "SAXIHP3AWID5": "PS7_SAXIHP3AWID5", - "SAXIHP3AWLEN0": "PS7_SAXIHP3AWLEN0", - "SAXIHP3AWLEN1": "PS7_SAXIHP3AWLEN1", - "SAXIHP3AWLEN2": "PS7_SAXIHP3AWLEN2", - "SAXIHP3AWLEN3": "PS7_SAXIHP3AWLEN3", - "SAXIHP3AWLOCK0": "PS7_SAXIHP3AWLOCK0", - "SAXIHP3AWLOCK1": "PS7_SAXIHP3AWLOCK1", - "SAXIHP3AWPROT0": "PS7_SAXIHP3AWPROT0", - "SAXIHP3AWPROT1": "PS7_SAXIHP3AWPROT1", - "SAXIHP3AWPROT2": "PS7_SAXIHP3AWPROT2", - "SAXIHP3AWQOS0": "PS7_SAXIHP3AWQOS0", - "SAXIHP3AWQOS1": "PS7_SAXIHP3AWQOS1", - "SAXIHP3AWQOS2": "PS7_SAXIHP3AWQOS2", - "SAXIHP3AWQOS3": "PS7_SAXIHP3AWQOS3", - "SAXIHP3AWREADY": "PS7_SAXIHP3AWREADY", - "SAXIHP3AWSIZE0": "PS7_SAXIHP3AWSIZE0", - "SAXIHP3AWSIZE1": "PS7_SAXIHP3AWSIZE1", - "SAXIHP3AWVALID": "PS7_SAXIHP3AWVALID", - "SAXIHP3BID0": "PS7_SAXIHP3BID0", - "SAXIHP3BID1": "PS7_SAXIHP3BID1", - "SAXIHP3BID2": "PS7_SAXIHP3BID2", - "SAXIHP3BID3": "PS7_SAXIHP3BID3", - "SAXIHP3BID4": "PS7_SAXIHP3BID4", - "SAXIHP3BID5": "PS7_SAXIHP3BID5", - "SAXIHP3BREADY": "PS7_SAXIHP3BREADY", - "SAXIHP3BRESP0": "PS7_SAXIHP3BRESP0", - "SAXIHP3BRESP1": "PS7_SAXIHP3BRESP1", - "SAXIHP3BVALID": "PS7_SAXIHP3BVALID", - "SAXIHP3RACOUNT0": "PS7_SAXIHP3RACOUNT0", - "SAXIHP3RACOUNT1": "PS7_SAXIHP3RACOUNT1", - "SAXIHP3RACOUNT2": "PS7_SAXIHP3RACOUNT2", - "SAXIHP3RCOUNT0": "PS7_SAXIHP3RCOUNT0", - "SAXIHP3RCOUNT1": "PS7_SAXIHP3RCOUNT1", - "SAXIHP3RCOUNT2": "PS7_SAXIHP3RCOUNT2", - "SAXIHP3RCOUNT3": "PS7_SAXIHP3RCOUNT3", - "SAXIHP3RCOUNT4": "PS7_SAXIHP3RCOUNT4", - "SAXIHP3RCOUNT5": "PS7_SAXIHP3RCOUNT5", - "SAXIHP3RCOUNT6": "PS7_SAXIHP3RCOUNT6", - "SAXIHP3RCOUNT7": "PS7_SAXIHP3RCOUNT7", - "SAXIHP3RDATA0": "PS7_SAXIHP3RDATA0", - "SAXIHP3RDATA1": "PS7_SAXIHP3RDATA1", - "SAXIHP3RDATA10": "PS7_SAXIHP3RDATA10", - "SAXIHP3RDATA11": "PS7_SAXIHP3RDATA11", - "SAXIHP3RDATA12": "PS7_SAXIHP3RDATA12", - "SAXIHP3RDATA13": "PS7_SAXIHP3RDATA13", - "SAXIHP3RDATA14": "PS7_SAXIHP3RDATA14", - "SAXIHP3RDATA15": "PS7_SAXIHP3RDATA15", - "SAXIHP3RDATA16": "PS7_SAXIHP3RDATA16", - "SAXIHP3RDATA17": "PS7_SAXIHP3RDATA17", - "SAXIHP3RDATA18": "PS7_SAXIHP3RDATA18", - "SAXIHP3RDATA19": "PS7_SAXIHP3RDATA19", - "SAXIHP3RDATA2": "PS7_SAXIHP3RDATA2", - "SAXIHP3RDATA20": "PS7_SAXIHP3RDATA20", - "SAXIHP3RDATA21": "PS7_SAXIHP3RDATA21", - "SAXIHP3RDATA22": "PS7_SAXIHP3RDATA22", - "SAXIHP3RDATA23": "PS7_SAXIHP3RDATA23", - "SAXIHP3RDATA24": "PS7_SAXIHP3RDATA24", - "SAXIHP3RDATA25": "PS7_SAXIHP3RDATA25", - "SAXIHP3RDATA26": "PS7_SAXIHP3RDATA26", - "SAXIHP3RDATA27": "PS7_SAXIHP3RDATA27", - "SAXIHP3RDATA28": "PS7_SAXIHP3RDATA28", - "SAXIHP3RDATA29": "PS7_SAXIHP3RDATA29", - "SAXIHP3RDATA3": "PS7_SAXIHP3RDATA3", - "SAXIHP3RDATA30": "PS7_SAXIHP3RDATA30", - "SAXIHP3RDATA31": "PS7_SAXIHP3RDATA31", - "SAXIHP3RDATA32": "PS7_SAXIHP3RDATA32", - "SAXIHP3RDATA33": "PS7_SAXIHP3RDATA33", - "SAXIHP3RDATA34": "PS7_SAXIHP3RDATA34", - "SAXIHP3RDATA35": "PS7_SAXIHP3RDATA35", - "SAXIHP3RDATA36": "PS7_SAXIHP3RDATA36", - "SAXIHP3RDATA37": "PS7_SAXIHP3RDATA37", - "SAXIHP3RDATA38": "PS7_SAXIHP3RDATA38", - "SAXIHP3RDATA39": "PS7_SAXIHP3RDATA39", - "SAXIHP3RDATA4": "PS7_SAXIHP3RDATA4", - "SAXIHP3RDATA40": "PS7_SAXIHP3RDATA40", - "SAXIHP3RDATA41": "PS7_SAXIHP3RDATA41", - "SAXIHP3RDATA42": "PS7_SAXIHP3RDATA42", - "SAXIHP3RDATA43": "PS7_SAXIHP3RDATA43", - "SAXIHP3RDATA44": "PS7_SAXIHP3RDATA44", - "SAXIHP3RDATA45": "PS7_SAXIHP3RDATA45", - "SAXIHP3RDATA46": "PS7_SAXIHP3RDATA46", - "SAXIHP3RDATA47": "PS7_SAXIHP3RDATA47", - "SAXIHP3RDATA48": "PS7_SAXIHP3RDATA48", - "SAXIHP3RDATA49": "PS7_SAXIHP3RDATA49", - "SAXIHP3RDATA5": "PS7_SAXIHP3RDATA5", - "SAXIHP3RDATA50": "PS7_SAXIHP3RDATA50", - "SAXIHP3RDATA51": "PS7_SAXIHP3RDATA51", - "SAXIHP3RDATA52": "PS7_SAXIHP3RDATA52", - "SAXIHP3RDATA53": "PS7_SAXIHP3RDATA53", - "SAXIHP3RDATA54": "PS7_SAXIHP3RDATA54", - "SAXIHP3RDATA55": "PS7_SAXIHP3RDATA55", - "SAXIHP3RDATA56": "PS7_SAXIHP3RDATA56", - "SAXIHP3RDATA57": "PS7_SAXIHP3RDATA57", - "SAXIHP3RDATA58": "PS7_SAXIHP3RDATA58", - "SAXIHP3RDATA59": "PS7_SAXIHP3RDATA59", - "SAXIHP3RDATA6": "PS7_SAXIHP3RDATA6", - "SAXIHP3RDATA60": "PS7_SAXIHP3RDATA60", - "SAXIHP3RDATA61": "PS7_SAXIHP3RDATA61", - "SAXIHP3RDATA62": "PS7_SAXIHP3RDATA62", - "SAXIHP3RDATA63": "PS7_SAXIHP3RDATA63", - "SAXIHP3RDATA7": "PS7_SAXIHP3RDATA7", - "SAXIHP3RDATA8": "PS7_SAXIHP3RDATA8", - "SAXIHP3RDATA9": "PS7_SAXIHP3RDATA9", - "SAXIHP3RDISSUECAP1EN": "PS7_SAXIHP3RDISSUECAP1EN", - "SAXIHP3RID0": "PS7_SAXIHP3RID0", - "SAXIHP3RID1": "PS7_SAXIHP3RID1", - "SAXIHP3RID2": "PS7_SAXIHP3RID2", - "SAXIHP3RID3": "PS7_SAXIHP3RID3", - "SAXIHP3RID4": "PS7_SAXIHP3RID4", - "SAXIHP3RID5": "PS7_SAXIHP3RID5", - "SAXIHP3RLAST": "PS7_SAXIHP3RLAST", - "SAXIHP3RREADY": "PS7_SAXIHP3RREADY", - "SAXIHP3RRESP0": "PS7_SAXIHP3RRESP0", - "SAXIHP3RRESP1": "PS7_SAXIHP3RRESP1", - "SAXIHP3RVALID": "PS7_SAXIHP3RVALID", - "SAXIHP3WACOUNT0": "PS7_SAXIHP3WACOUNT0", - "SAXIHP3WACOUNT1": "PS7_SAXIHP3WACOUNT1", - "SAXIHP3WACOUNT2": "PS7_SAXIHP3WACOUNT2", - "SAXIHP3WACOUNT3": "PS7_SAXIHP3WACOUNT3", - "SAXIHP3WACOUNT4": "PS7_SAXIHP3WACOUNT4", - "SAXIHP3WACOUNT5": "PS7_SAXIHP3WACOUNT5", - "SAXIHP3WCOUNT0": "PS7_SAXIHP3WCOUNT0", - "SAXIHP3WCOUNT1": "PS7_SAXIHP3WCOUNT1", - "SAXIHP3WCOUNT2": "PS7_SAXIHP3WCOUNT2", - "SAXIHP3WCOUNT3": "PS7_SAXIHP3WCOUNT3", - "SAXIHP3WCOUNT4": "PS7_SAXIHP3WCOUNT4", - "SAXIHP3WCOUNT5": "PS7_SAXIHP3WCOUNT5", - "SAXIHP3WCOUNT6": "PS7_SAXIHP3WCOUNT6", - "SAXIHP3WCOUNT7": "PS7_SAXIHP3WCOUNT7", - "SAXIHP3WDATA0": "PS7_SAXIHP3WDATA0", - "SAXIHP3WDATA1": "PS7_SAXIHP3WDATA1", - "SAXIHP3WDATA10": "PS7_SAXIHP3WDATA10", - "SAXIHP3WDATA11": "PS7_SAXIHP3WDATA11", - "SAXIHP3WDATA12": "PS7_SAXIHP3WDATA12", - "SAXIHP3WDATA13": "PS7_SAXIHP3WDATA13", - "SAXIHP3WDATA14": "PS7_SAXIHP3WDATA14", - "SAXIHP3WDATA15": "PS7_SAXIHP3WDATA15", - "SAXIHP3WDATA16": "PS7_SAXIHP3WDATA16", - "SAXIHP3WDATA17": "PS7_SAXIHP3WDATA17", - "SAXIHP3WDATA18": "PS7_SAXIHP3WDATA18", - "SAXIHP3WDATA19": "PS7_SAXIHP3WDATA19", - "SAXIHP3WDATA2": "PS7_SAXIHP3WDATA2", - "SAXIHP3WDATA20": "PS7_SAXIHP3WDATA20", - "SAXIHP3WDATA21": "PS7_SAXIHP3WDATA21", - "SAXIHP3WDATA22": "PS7_SAXIHP3WDATA22", - "SAXIHP3WDATA23": "PS7_SAXIHP3WDATA23", - "SAXIHP3WDATA24": "PS7_SAXIHP3WDATA24", - "SAXIHP3WDATA25": "PS7_SAXIHP3WDATA25", - "SAXIHP3WDATA26": "PS7_SAXIHP3WDATA26", - "SAXIHP3WDATA27": "PS7_SAXIHP3WDATA27", - "SAXIHP3WDATA28": "PS7_SAXIHP3WDATA28", - "SAXIHP3WDATA29": "PS7_SAXIHP3WDATA29", - "SAXIHP3WDATA3": "PS7_SAXIHP3WDATA3", - "SAXIHP3WDATA30": "PS7_SAXIHP3WDATA30", - "SAXIHP3WDATA31": "PS7_SAXIHP3WDATA31", - "SAXIHP3WDATA32": "PS7_SAXIHP3WDATA32", - "SAXIHP3WDATA33": "PS7_SAXIHP3WDATA33", - "SAXIHP3WDATA34": "PS7_SAXIHP3WDATA34", - "SAXIHP3WDATA35": "PS7_SAXIHP3WDATA35", - "SAXIHP3WDATA36": "PS7_SAXIHP3WDATA36", - "SAXIHP3WDATA37": "PS7_SAXIHP3WDATA37", - "SAXIHP3WDATA38": "PS7_SAXIHP3WDATA38", - "SAXIHP3WDATA39": "PS7_SAXIHP3WDATA39", - "SAXIHP3WDATA4": "PS7_SAXIHP3WDATA4", - "SAXIHP3WDATA40": "PS7_SAXIHP3WDATA40", - "SAXIHP3WDATA41": "PS7_SAXIHP3WDATA41", - "SAXIHP3WDATA42": "PS7_SAXIHP3WDATA42", - "SAXIHP3WDATA43": "PS7_SAXIHP3WDATA43", - "SAXIHP3WDATA44": "PS7_SAXIHP3WDATA44", - "SAXIHP3WDATA45": "PS7_SAXIHP3WDATA45", - "SAXIHP3WDATA46": "PS7_SAXIHP3WDATA46", - "SAXIHP3WDATA47": "PS7_SAXIHP3WDATA47", - "SAXIHP3WDATA48": "PS7_SAXIHP3WDATA48", - "SAXIHP3WDATA49": "PS7_SAXIHP3WDATA49", - "SAXIHP3WDATA5": "PS7_SAXIHP3WDATA5", - "SAXIHP3WDATA50": "PS7_SAXIHP3WDATA50", - "SAXIHP3WDATA51": "PS7_SAXIHP3WDATA51", - "SAXIHP3WDATA52": "PS7_SAXIHP3WDATA52", - "SAXIHP3WDATA53": "PS7_SAXIHP3WDATA53", - "SAXIHP3WDATA54": "PS7_SAXIHP3WDATA54", - "SAXIHP3WDATA55": "PS7_SAXIHP3WDATA55", - "SAXIHP3WDATA56": "PS7_SAXIHP3WDATA56", - "SAXIHP3WDATA57": "PS7_SAXIHP3WDATA57", - "SAXIHP3WDATA58": "PS7_SAXIHP3WDATA58", - "SAXIHP3WDATA59": "PS7_SAXIHP3WDATA59", - "SAXIHP3WDATA6": "PS7_SAXIHP3WDATA6", - "SAXIHP3WDATA60": "PS7_SAXIHP3WDATA60", - "SAXIHP3WDATA61": "PS7_SAXIHP3WDATA61", - "SAXIHP3WDATA62": "PS7_SAXIHP3WDATA62", - "SAXIHP3WDATA63": "PS7_SAXIHP3WDATA63", - "SAXIHP3WDATA7": "PS7_SAXIHP3WDATA7", - "SAXIHP3WDATA8": "PS7_SAXIHP3WDATA8", - "SAXIHP3WDATA9": "PS7_SAXIHP3WDATA9", - "SAXIHP3WID0": "PS7_SAXIHP3WID0", - "SAXIHP3WID1": "PS7_SAXIHP3WID1", - "SAXIHP3WID2": "PS7_SAXIHP3WID2", - "SAXIHP3WID3": "PS7_SAXIHP3WID3", - "SAXIHP3WID4": "PS7_SAXIHP3WID4", - "SAXIHP3WID5": "PS7_SAXIHP3WID5", - "SAXIHP3WLAST": "PS7_SAXIHP3WLAST", - "SAXIHP3WREADY": "PS7_SAXIHP3WREADY", - "SAXIHP3WRISSUECAP1EN": "PS7_SAXIHP3WRISSUECAP1EN", - "SAXIHP3WSTRB0": "PS7_SAXIHP3WSTRB0", - "SAXIHP3WSTRB1": "PS7_SAXIHP3WSTRB1", - "SAXIHP3WSTRB2": "PS7_SAXIHP3WSTRB2", - "SAXIHP3WSTRB3": "PS7_SAXIHP3WSTRB3", - "SAXIHP3WSTRB4": "PS7_SAXIHP3WSTRB4", - "SAXIHP3WSTRB5": "PS7_SAXIHP3WSTRB5", - "SAXIHP3WSTRB6": "PS7_SAXIHP3WSTRB6", - "SAXIHP3WSTRB7": "PS7_SAXIHP3WSTRB7", - "SAXIHP3WVALID": "PS7_SAXIHP3WVALID", - "TESTA9MBISTDATAIN": "PS7_TESTA9MBISTDATAIN", - "TESTA9MBISTDSHIFT": "PS7_TESTA9MBISTDSHIFT", - "TESTA9MBISTENABLEN": "PS7_TESTA9MBISTENABLEN", - "TESTA9MBISTRESET": "PS7_TESTA9MBISTRESET", - "TESTA9MBISTRESULT0": "PS7_TESTA9MBISTRESULT0", - "TESTA9MBISTRESULT1": "PS7_TESTA9MBISTRESULT1", - "TESTA9MBISTRESULT2": "PS7_TESTA9MBISTRESULT2", - "TESTA9MBISTRESULT3": "PS7_TESTA9MBISTRESULT3", - "TESTA9MBISTRESULT4": "PS7_TESTA9MBISTRESULT4", - "TESTA9MBISTRESULT5": "PS7_TESTA9MBISTRESULT5", - "TESTA9MBISTRUN": "PS7_TESTA9MBISTRUN", - "TESTA9MBISTSHIFT": "PS7_TESTA9MBISTSHIFT", - "TESTAMUXENABLEB": "PS7_TESTAMUXENABLEB", - "TESTBGAMUXSEL0": "PS7_TESTBGAMUXSEL0", - "TESTBGAMUXSEL1": "PS7_TESTBGAMUXSEL1", - "TESTBGAMUXSEL2": "PS7_TESTBGAMUXSEL2", - "TESTBGAMUXSEL3": "PS7_TESTBGAMUXSEL3", - "TESTBGAMUXSEL4": "PS7_TESTBGAMUXSEL4", - "TESTBGPOWERDOWN": "PS7_TESTBGPOWERDOWN", - "TESTBSCENN": "PS7_TESTBSCENN", - "TESTDFTRAMBYPN": "PS7_TESTDFTRAMBYPN", - "TESTDIVCLKOUT0": "PS7_TESTDIVCLKOUT0", - "TESTDIVCLKOUT1": "PS7_TESTDIVCLKOUT1", - "TESTDIVCLKOUT10": "PS7_TESTDIVCLKOUT10", - "TESTDIVCLKOUT11": "PS7_TESTDIVCLKOUT11", - "TESTDIVCLKOUT12": "PS7_TESTDIVCLKOUT12", - "TESTDIVCLKOUT13": "PS7_TESTDIVCLKOUT13", - "TESTDIVCLKOUT14": "PS7_TESTDIVCLKOUT14", - "TESTDIVCLKOUT15": "PS7_TESTDIVCLKOUT15", - "TESTDIVCLKOUT16": "PS7_TESTDIVCLKOUT16", - "TESTDIVCLKOUT17": "PS7_TESTDIVCLKOUT17", - "TESTDIVCLKOUT18": "PS7_TESTDIVCLKOUT18", - "TESTDIVCLKOUT19": "PS7_TESTDIVCLKOUT19", - "TESTDIVCLKOUT2": "PS7_TESTDIVCLKOUT2", - "TESTDIVCLKOUT20": "PS7_TESTDIVCLKOUT20", - "TESTDIVCLKOUT3": "PS7_TESTDIVCLKOUT3", - "TESTDIVCLKOUT4": "PS7_TESTDIVCLKOUT4", - "TESTDIVCLKOUT5": "PS7_TESTDIVCLKOUT5", - "TESTDIVCLKOUT6": "PS7_TESTDIVCLKOUT6", - "TESTDIVCLKOUT7": "PS7_TESTDIVCLKOUT7", - "TESTDIVCLKOUT8": "PS7_TESTDIVCLKOUT8", - "TESTDIVCLKOUT9": "PS7_TESTDIVCLKOUT9", - "TESTDIVCLKOUTPREOPCGENABLEN": "PS7_TESTDIVCLKOUTPREOPCGENABLEN", - "TESTDIVIDERRESETN": "PS7_TESTDIVIDERRESETN", - "TESTDIVIDERUPDATETOG": "PS7_TESTDIVIDERUPDATETOG", - "TESTEDTBYPASS": "PS7_TESTEDTBYPASS", - "TESTEDTCHANNELSIN0": "PS7_TESTEDTCHANNELSIN0", - "TESTEDTCHANNELSIN1": "PS7_TESTEDTCHANNELSIN1", - "TESTEDTCHANNELSIN2": "PS7_TESTEDTCHANNELSIN2", - "TESTEDTCHANNELSIN3": "PS7_TESTEDTCHANNELSIN3", - "TESTEDTCHANNELSIN4": "PS7_TESTEDTCHANNELSIN4", - "TESTEDTCHANNELSIN5": "PS7_TESTEDTCHANNELSIN5", - "TESTEDTCHANNELSIN6": "PS7_TESTEDTCHANNELSIN6", - "TESTEDTCHANNELSOUT0": "PS7_TESTEDTCHANNELSOUT0", - "TESTEDTCHANNELSOUT1": "PS7_TESTEDTCHANNELSOUT1", - "TESTEDTCHANNELSOUT2": "PS7_TESTEDTCHANNELSOUT2", - "TESTEDTCHANNELSOUT3": "PS7_TESTEDTCHANNELSOUT3", - "TESTEDTCHANNELSOUT4": "PS7_TESTEDTCHANNELSOUT4", - "TESTEDTCHANNELSOUT5": "PS7_TESTEDTCHANNELSOUT5", - "TESTEDTCHANNELSOUT6": "PS7_TESTEDTCHANNELSOUT6", - "TESTEDTCLOCK": "PS7_TESTEDTCLOCK", - "TESTEDTUPDATE": "PS7_TESTEDTUPDATE", - "TESTMBISTCOMPSTAT": "PS7_TESTMBISTCOMPSTAT", - "TESTMBISTMODEN": "PS7_TESTMBISTMODEN", - "TESTMBISTTAPTCK": "PS7_TESTMBISTTAPTCK", - "TESTMBISTTAPTDI": "PS7_TESTMBISTTAPTDI", - "TESTMBISTTAPTDO": "PS7_TESTMBISTTAPTDO", - "TESTMBISTTAPTDOENABLE": "PS7_TESTMBISTTAPTDOENABLE", - "TESTMBISTTAPTMS": "PS7_TESTMBISTTAPTMS", - "TESTMBISTTAPTRST": "PS7_TESTMBISTTAPTRST", - "TESTPLLCLKOUT0": "PS7_TESTPLLCLKOUT0_PW", - "TESTPLLCLKOUT1": "PS7_TESTPLLCLKOUT1_PW", - "TESTPLLCLKOUT2": "PS7_TESTPLLCLKOUT2_PW", - "TESTPLLCONFIGREADY0": "PS7_TESTPLLCONFIGREADY0", - "TESTPLLCONFIGREADY1": "PS7_TESTPLLCONFIGREADY1", - "TESTPLLCONFIGREADY2": "PS7_TESTPLLCONFIGREADY2", - "TESTPLLCONFIGUPDATE0": "PS7_TESTPLLCONFIGUPDATE0", - "TESTPLLCONFIGUPDATE1": "PS7_TESTPLLCONFIGUPDATE1", - "TESTPLLCONFIGUPDATE2": "PS7_TESTPLLCONFIGUPDATE2", - "TESTPLLFBTESTN0": "PS7_TESTPLLFBTESTN0", - "TESTPLLFBTESTN1": "PS7_TESTPLLFBTESTN1", - "TESTPLLFBTESTN2": "PS7_TESTPLLFBTESTN2", - "TESTPLLFEEDBACKDIV0": "PS7_TESTPLLFEEDBACKDIV0", - "TESTPLLFEEDBACKDIV1": "PS7_TESTPLLFEEDBACKDIV1", - "TESTPLLFEEDBACKDIV2": "PS7_TESTPLLFEEDBACKDIV2", - "TESTPLLLOCK0": "PS7_TESTPLLLOCK0", - "TESTPLLLOCK1": "PS7_TESTPLLLOCK1", - "TESTPLLLOCK2": "PS7_TESTPLLLOCK2", - "TESTPLLNEWCLK0": "PS7_TESTPLLNEWCLK0_PW", - "TESTPLLNEWCLK1": "PS7_TESTPLLNEWCLK1_PW", - "TESTPLLNEWCLK2": "PS7_TESTPLLNEWCLK2_PW", - "TESTPLLPOWERDOWNN": "PS7_TESTPLLPOWERDOWNN", - "TESTPLLREFCLKCPU": "PS7_TESTPLLREFCLKCPU", - "TESTPLLREFCLKDDR": "PS7_TESTPLLREFCLKDDR", - "TESTPLLREFCLKENN0": "PS7_TESTPLLREFCLKENN0", - "TESTPLLREFCLKENN1": "PS7_TESTPLLREFCLKENN1", - "TESTPLLREFCLKENN2": "PS7_TESTPLLREFCLKENN2", - "TESTPLLREFCLKIOU": "PS7_TESTPLLREFCLKIOU", - "TESTPLLRESET": "PS7_TESTPLLRESET", - "TESTPSSCLOCKDR": "PS7_TESTPSSCLOCKDR", - "TESTPSSEXTEST": "PS7_TESTPSSEXTEST", - "TESTPSSEXTESTSMPL": "PS7_TESTPSSEXTESTSMPL", - "TESTPSSINTEST": "PS7_TESTPSSINTEST", - "TESTPSSRESETTAPB": "PS7_TESTPSSRESETTAPB", - "TESTPSSSHIFTDR": "PS7_TESTPSSSHIFTDR", - "TESTPSSTDI": "PS7_TESTPSSTDI", - "TESTPSSTDO": "PS7_TESTPSSTDO", - "TESTPSSUPDATEDR": "PS7_TESTPSSUPDATEDR", - "TESTRESETMUXN": "PS7_TESTRESETMUXN", - "TESTSCANCLOCKCLOCKGEN": "PS7_TESTSCANCLOCKCLOCKGEN", - "TESTSCANCLOCKOPCG0": "PS7_TESTSCANCLOCKOPCG0", - "TESTSCANCLOCKOPCG1": "PS7_TESTSCANCLOCKOPCG1", - "TESTSCANCLOCKOPCG10": "PS7_TESTSCANCLOCKOPCG10", - "TESTSCANCLOCKOPCG11": "PS7_TESTSCANCLOCKOPCG11", - "TESTSCANCLOCKOPCG12": "PS7_TESTSCANCLOCKOPCG12", - "TESTSCANCLOCKOPCG13": "PS7_TESTSCANCLOCKOPCG13", - "TESTSCANCLOCKOPCG14": "PS7_TESTSCANCLOCKOPCG14", - "TESTSCANCLOCKOPCG15": "PS7_TESTSCANCLOCKOPCG15", - "TESTSCANCLOCKOPCG16": "PS7_TESTSCANCLOCKOPCG16", - "TESTSCANCLOCKOPCG17": "PS7_TESTSCANCLOCKOPCG17", - "TESTSCANCLOCKOPCG18": "PS7_TESTSCANCLOCKOPCG18", - "TESTSCANCLOCKOPCG19": "PS7_TESTSCANCLOCKOPCG19", - "TESTSCANCLOCKOPCG2": "PS7_TESTSCANCLOCKOPCG2", - "TESTSCANCLOCKOPCG20": "PS7_TESTSCANCLOCKOPCG20", - "TESTSCANCLOCKOPCG21": "PS7_TESTSCANCLOCKOPCG21", - "TESTSCANCLOCKOPCG22": "PS7_TESTSCANCLOCKOPCG22", - "TESTSCANCLOCKOPCG23": "PS7_TESTSCANCLOCKOPCG23", - "TESTSCANCLOCKOPCG3": "PS7_TESTSCANCLOCKOPCG3", - "TESTSCANCLOCKOPCG4": "PS7_TESTSCANCLOCKOPCG4", - "TESTSCANCLOCKOPCG5": "PS7_TESTSCANCLOCKOPCG5", - "TESTSCANCLOCKOPCG6": "PS7_TESTSCANCLOCKOPCG6", - "TESTSCANCLOCKOPCG7": "PS7_TESTSCANCLOCKOPCG7", - "TESTSCANCLOCKOPCG8": "PS7_TESTSCANCLOCKOPCG8", - "TESTSCANCLOCKOPCG9": "PS7_TESTSCANCLOCKOPCG9", - "TESTSCANCLOCKPAD0": "PS7_TESTSCANCLOCKPAD0", - "TESTSCANCLOCKPAD1": "PS7_TESTSCANCLOCKPAD1", - "TESTSCANCLOCKPAD2": "PS7_TESTSCANCLOCKPAD2", - "TESTSCANCLOCKPAD3": "PS7_TESTSCANCLOCKPAD3", - "TESTSCANCLOCKPAD4": "PS7_TESTSCANCLOCKPAD4", - "TESTSCANENABLEATSPEEDNONSCANFLOPSN": "PS7_TESTSCANENABLEATSPEEDNONSCANFLOPSN", - "TESTSCANENABLEN": "PS7_TESTSCANENABLEN", - "TESTSCANMODEATSPEEDN": "PS7_TESTSCANMODEATSPEEDN", - "TESTSCANMODEATSPEEDOPCGN0": "PS7_TESTSCANMODEATSPEEDOPCGN0", - "TESTSCANMODEATSPEEDOPCGN1": "PS7_TESTSCANMODEATSPEEDOPCGN1", - "TESTSCANMODEATSPEEDOPCGN10": "PS7_TESTSCANMODEATSPEEDOPCGN10", - "TESTSCANMODEATSPEEDOPCGN11": "PS7_TESTSCANMODEATSPEEDOPCGN11", - "TESTSCANMODEATSPEEDOPCGN12": "PS7_TESTSCANMODEATSPEEDOPCGN12", - "TESTSCANMODEATSPEEDOPCGN13": "PS7_TESTSCANMODEATSPEEDOPCGN13", - "TESTSCANMODEATSPEEDOPCGN14": "PS7_TESTSCANMODEATSPEEDOPCGN14", - "TESTSCANMODEATSPEEDOPCGN15": "PS7_TESTSCANMODEATSPEEDOPCGN15", - "TESTSCANMODEATSPEEDOPCGN16": "PS7_TESTSCANMODEATSPEEDOPCGN16", - "TESTSCANMODEATSPEEDOPCGN17": "PS7_TESTSCANMODEATSPEEDOPCGN17", - "TESTSCANMODEATSPEEDOPCGN18": "PS7_TESTSCANMODEATSPEEDOPCGN18", - "TESTSCANMODEATSPEEDOPCGN19": "PS7_TESTSCANMODEATSPEEDOPCGN19", - "TESTSCANMODEATSPEEDOPCGN2": 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@@ } ], "tile_type": "PSS2", - "wires": [ - "PS72_DDRA0", - "PS72_DDRA1", - "PS72_DDRA10", - "PS72_DDRA11", - "PS72_DDRA12", - "PS72_DDRA13", - "PS72_DDRA14", - "PS72_DDRA2", - "PS72_DDRA3", - "PS72_DDRA4", - "PS72_DDRA5", - "PS72_DDRA6", - "PS72_DDRA7", - "PS72_DDRA8", - "PS72_DDRA9", - "PS72_DDRBA0", - "PS72_DDRBA1", - "PS72_DDRBA2", - "PS72_DDRCASB", - "PS72_DDRCKE", - "PS72_DDRCKN", - "PS72_DDRCKP", - "PS72_DDRCSB", - "PS72_DDRDM0", - "PS72_DDRDM1", - "PS72_DDRDM2", - "PS72_DDRDM3", - "PS72_DDRDQ0", - "PS72_DDRDQ1", - "PS72_DDRDQ10", - "PS72_DDRDQ11", - "PS72_DDRDQ12", - "PS72_DDRDQ13", - "PS72_DDRDQ14", - "PS72_DDRDQ15", - "PS72_DDRDQ16", - "PS72_DDRDQ17", - "PS72_DDRDQ18", - "PS72_DDRDQ19", - "PS72_DDRDQ2", - "PS72_DDRDQ20", - "PS72_DDRDQ21", - "PS72_DDRDQ22", - "PS72_DDRDQ23", - "PS72_DDRDQ24", - "PS72_DDRDQ25", - "PS72_DDRDQ26", - "PS72_DDRDQ27", - "PS72_DDRDQ28", - "PS72_DDRDQ29", - "PS72_DDRDQ3", - "PS72_DDRDQ30", - "PS72_DDRDQ31", - "PS72_DDRDQ4", - "PS72_DDRDQ5", - "PS72_DDRDQ6", - "PS72_DDRDQ7", - "PS72_DDRDQ8", - "PS72_DDRDQ9", - "PS72_DDRDQSN0", - "PS72_DDRDQSN1", - "PS72_DDRDQSN2", - "PS72_DDRDQSN3", - "PS72_DDRDQSP0", - "PS72_DDRDQSP1", - "PS72_DDRDQSP2", - "PS72_DDRDQSP3", - "PS72_DDRDRSTB", - "PS72_DDRODT", - "PS72_DDRRASB", - "PS72_DDRVRN", - "PS72_DDRVRP", - "PS72_DDRWEB", - "PS72_MIO0", - "PS72_MIO1", - "PS72_MIO10", - "PS72_MIO11", - "PS72_MIO12", - "PS72_MIO13", - "PS72_MIO14", - "PS72_MIO15", - "PS72_MIO16", - "PS72_MIO17", - "PS72_MIO18", - "PS72_MIO19", - "PS72_MIO2", - "PS72_MIO20", - "PS72_MIO21", - "PS72_MIO22", - "PS72_MIO23", - "PS72_MIO24", - "PS72_MIO25", - "PS72_MIO26", - "PS72_MIO27", - "PS72_MIO28", - "PS72_MIO29", - "PS72_MIO3", - "PS72_MIO30", - "PS72_MIO31", - "PS72_MIO32", - "PS72_MIO33", - "PS72_MIO34", - "PS72_MIO35", - "PS72_MIO36", - "PS72_MIO37", - "PS72_MIO38", - "PS72_MIO39", - "PS72_MIO4", - "PS72_MIO40", - "PS72_MIO41", - "PS72_MIO42", - "PS72_MIO43", - "PS72_MIO44", - "PS72_MIO45", - "PS72_MIO46", - "PS72_MIO47", - "PS72_MIO48", - "PS72_MIO49", - "PS72_MIO5", - "PS72_MIO50", - "PS72_MIO51", - "PS72_MIO52", - "PS72_MIO53", - "PS72_MIO6", - "PS72_MIO7", - "PS72_MIO8", - "PS72_MIO9", - "PS72_PSCLK", - "PS72_PSPORB", - "PS72_PSSRSTB", - "PS7_DDRA0", - "PS7_DDRA1", - "PS7_DDRA10", - "PS7_DDRA11", - "PS7_DDRA12", - "PS7_DDRA13", - "PS7_DDRA14", - "PS7_DDRA2", - "PS7_DDRA3", - "PS7_DDRA4", - "PS7_DDRA5", - "PS7_DDRA6", - "PS7_DDRA7", - "PS7_DDRA8", - "PS7_DDRA9", - "PS7_DDRARB0", - "PS7_DDRARB1", - "PS7_DDRARB2", - "PS7_DDRARB3", - "PS7_DDRBA0", - "PS7_DDRBA1", - "PS7_DDRBA2", - "PS7_DDRCASB", - "PS7_DDRCKE", - "PS7_DDRCKN", - "PS7_DDRCKP", - "PS7_DDRCSB", - "PS7_DDRDM0", - "PS7_DDRDM1", - "PS7_DDRDM2", - "PS7_DDRDM3", - "PS7_DDRDQ0", - "PS7_DDRDQ1", - "PS7_DDRDQ10", - "PS7_DDRDQ11", - "PS7_DDRDQ12", - "PS7_DDRDQ13", - "PS7_DDRDQ14", - "PS7_DDRDQ15", - "PS7_DDRDQ16", - "PS7_DDRDQ17", - "PS7_DDRDQ18", - "PS7_DDRDQ19", - "PS7_DDRDQ2", - "PS7_DDRDQ20", - "PS7_DDRDQ21", - "PS7_DDRDQ22", - "PS7_DDRDQ23", - "PS7_DDRDQ24", - "PS7_DDRDQ25", - "PS7_DDRDQ26", - "PS7_DDRDQ27", - "PS7_DDRDQ28", - "PS7_DDRDQ29", - "PS7_DDRDQ3", - "PS7_DDRDQ30", - "PS7_DDRDQ31", - "PS7_DDRDQ4", - "PS7_DDRDQ5", - "PS7_DDRDQ6", - "PS7_DDRDQ7", - "PS7_DDRDQ8", - "PS7_DDRDQ9", - "PS7_DDRDQSN0", - "PS7_DDRDQSN1", - "PS7_DDRDQSN2", - "PS7_DDRDQSN3", - "PS7_DDRDQSP0", - "PS7_DDRDQSP1", - "PS7_DDRDQSP2", - "PS7_DDRDQSP3", - "PS7_DDRDRSTB", - "PS7_DDRODT", - "PS7_DDRRASB", - "PS7_DDRVRN", - "PS7_DDRVRP", - "PS7_DDRWEB", - "PS7_DEBUGDATA0", - "PS7_DEBUGDATA1", - "PS7_DEBUGDATA10", - "PS7_DEBUGDATA100", - "PS7_DEBUGDATA101", - "PS7_DEBUGDATA102", - "PS7_DEBUGDATA103", - "PS7_DEBUGDATA104", - "PS7_DEBUGDATA105", - "PS7_DEBUGDATA106", - "PS7_DEBUGDATA107", - "PS7_DEBUGDATA108", - "PS7_DEBUGDATA109", - "PS7_DEBUGDATA11", - "PS7_DEBUGDATA110", - "PS7_DEBUGDATA111", - "PS7_DEBUGDATA112", - "PS7_DEBUGDATA113", - "PS7_DEBUGDATA114", - "PS7_DEBUGDATA115", - "PS7_DEBUGDATA116", - "PS7_DEBUGDATA117", - "PS7_DEBUGDATA118", - "PS7_DEBUGDATA119", - "PS7_DEBUGDATA12", - "PS7_DEBUGDATA120", - "PS7_DEBUGDATA121", - "PS7_DEBUGDATA122", - "PS7_DEBUGDATA123", - "PS7_DEBUGDATA124", - "PS7_DEBUGDATA125", - "PS7_DEBUGDATA126", - "PS7_DEBUGDATA127", - "PS7_DEBUGDATA128", - "PS7_DEBUGDATA129", - "PS7_DEBUGDATA13", - "PS7_DEBUGDATA130", - "PS7_DEBUGDATA131", - "PS7_DEBUGDATA132", - "PS7_DEBUGDATA133", - "PS7_DEBUGDATA134", - "PS7_DEBUGDATA135", - "PS7_DEBUGDATA136", - "PS7_DEBUGDATA137", - "PS7_DEBUGDATA138", - "PS7_DEBUGDATA139", - "PS7_DEBUGDATA14", - "PS7_DEBUGDATA140", - "PS7_DEBUGDATA141", - "PS7_DEBUGDATA142", - "PS7_DEBUGDATA143", - "PS7_DEBUGDATA144", - "PS7_DEBUGDATA145", - "PS7_DEBUGDATA146", - "PS7_DEBUGDATA147", - "PS7_DEBUGDATA148", - "PS7_DEBUGDATA149", - "PS7_DEBUGDATA15", - "PS7_DEBUGDATA150", - "PS7_DEBUGDATA151", - "PS7_DEBUGDATA152", - "PS7_DEBUGDATA153", - "PS7_DEBUGDATA154", - "PS7_DEBUGDATA155", - "PS7_DEBUGDATA156", - "PS7_DEBUGDATA157", - "PS7_DEBUGDATA158", - "PS7_DEBUGDATA159", - "PS7_DEBUGDATA16", - "PS7_DEBUGDATA160", - "PS7_DEBUGDATA161", - "PS7_DEBUGDATA162", - "PS7_DEBUGDATA163", - "PS7_DEBUGDATA164", - "PS7_DEBUGDATA165", - "PS7_DEBUGDATA166", - "PS7_DEBUGDATA167", - "PS7_DEBUGDATA168", - "PS7_DEBUGDATA169", - "PS7_DEBUGDATA17", - "PS7_DEBUGDATA170", - "PS7_DEBUGDATA171", - "PS7_DEBUGDATA172", - "PS7_DEBUGDATA173", - "PS7_DEBUGDATA174", - "PS7_DEBUGDATA175", - "PS7_DEBUGDATA176", - "PS7_DEBUGDATA177", - "PS7_DEBUGDATA178", - "PS7_DEBUGDATA179", - "PS7_DEBUGDATA18", - "PS7_DEBUGDATA180", - "PS7_DEBUGDATA181", - "PS7_DEBUGDATA182", - "PS7_DEBUGDATA183", - "PS7_DEBUGDATA184", - "PS7_DEBUGDATA185", - "PS7_DEBUGDATA186", - "PS7_DEBUGDATA187", - "PS7_DEBUGDATA188", - "PS7_DEBUGDATA189", - "PS7_DEBUGDATA19", - "PS7_DEBUGDATA190", - "PS7_DEBUGDATA191", - "PS7_DEBUGDATA192", - "PS7_DEBUGDATA193", - "PS7_DEBUGDATA194", - "PS7_DEBUGDATA195", - "PS7_DEBUGDATA196", - "PS7_DEBUGDATA197", - "PS7_DEBUGDATA198", - "PS7_DEBUGDATA199", - "PS7_DEBUGDATA2", - "PS7_DEBUGDATA20", - "PS7_DEBUGDATA21", - "PS7_DEBUGDATA22", - "PS7_DEBUGDATA23", - "PS7_DEBUGDATA24", - "PS7_DEBUGDATA25", - "PS7_DEBUGDATA26", - "PS7_DEBUGDATA27", - "PS7_DEBUGDATA28", - "PS7_DEBUGDATA29", - "PS7_DEBUGDATA3", - "PS7_DEBUGDATA30", - "PS7_DEBUGDATA31", - "PS7_DEBUGDATA32", - "PS7_DEBUGDATA33", - "PS7_DEBUGDATA34", - "PS7_DEBUGDATA35", - "PS7_DEBUGDATA36", - "PS7_DEBUGDATA37", - "PS7_DEBUGDATA38", - "PS7_DEBUGDATA39", - "PS7_DEBUGDATA4", - "PS7_DEBUGDATA40", - "PS7_DEBUGDATA41", - "PS7_DEBUGDATA42", - "PS7_DEBUGDATA43", - "PS7_DEBUGDATA44", - "PS7_DEBUGDATA45", - "PS7_DEBUGDATA46", - "PS7_DEBUGDATA47", - "PS7_DEBUGDATA48", - "PS7_DEBUGDATA49", - "PS7_DEBUGDATA5", - "PS7_DEBUGDATA50", - "PS7_DEBUGDATA51", - "PS7_DEBUGDATA52", - "PS7_DEBUGDATA53", - "PS7_DEBUGDATA54", - "PS7_DEBUGDATA55", - "PS7_DEBUGDATA56", - "PS7_DEBUGDATA57", - "PS7_DEBUGDATA58", - "PS7_DEBUGDATA59", - "PS7_DEBUGDATA6", - "PS7_DEBUGDATA60", - "PS7_DEBUGDATA61", - "PS7_DEBUGDATA62", - "PS7_DEBUGDATA63", - "PS7_DEBUGDATA64", - "PS7_DEBUGDATA65", - "PS7_DEBUGDATA66", - "PS7_DEBUGDATA67", - "PS7_DEBUGDATA68", - "PS7_DEBUGDATA69", - "PS7_DEBUGDATA7", - "PS7_DEBUGDATA70", - "PS7_DEBUGDATA71", - "PS7_DEBUGDATA72", - "PS7_DEBUGDATA73", - "PS7_DEBUGDATA74", - "PS7_DEBUGDATA75", - "PS7_DEBUGDATA76", - "PS7_DEBUGDATA77", - "PS7_DEBUGDATA78", - "PS7_DEBUGDATA79", - "PS7_DEBUGDATA8", - "PS7_DEBUGDATA80", - "PS7_DEBUGDATA81", - "PS7_DEBUGDATA82", - "PS7_DEBUGDATA83", - "PS7_DEBUGDATA84", - "PS7_DEBUGDATA85", - "PS7_DEBUGDATA86", - "PS7_DEBUGDATA87", - "PS7_DEBUGDATA88", - "PS7_DEBUGDATA89", - "PS7_DEBUGDATA9", - "PS7_DEBUGDATA90", - "PS7_DEBUGDATA91", - "PS7_DEBUGDATA92", - "PS7_DEBUGDATA93", - "PS7_DEBUGDATA94", - "PS7_DEBUGDATA95", - "PS7_DEBUGDATA96", - "PS7_DEBUGDATA97", - "PS7_DEBUGDATA98", - "PS7_DEBUGDATA99", - "PS7_DEBUGSELECT0", - "PS7_DEBUGSELECT1", - "PS7_DEBUGSELECT10", - "PS7_DEBUGSELECT11", - "PS7_DEBUGSELECT12", - "PS7_DEBUGSELECT13", - "PS7_DEBUGSELECT14", - "PS7_DEBUGSELECT15", - "PS7_DEBUGSELECT2", - "PS7_DEBUGSELECT3", - "PS7_DEBUGSELECT4", - "PS7_DEBUGSELECT5", - "PS7_DEBUGSELECT6", - "PS7_DEBUGSELECT7", - "PS7_DEBUGSELECT8", - "PS7_DEBUGSELECT9", - "PS7_DMA0ACLK", - "PS7_DMA0DAREADY", - "PS7_DMA0DATYPE0", - "PS7_DMA0DATYPE1", - "PS7_DMA0DAVALID", - "PS7_DMA0DRLAST", - "PS7_DMA0DRREADY", - "PS7_DMA0DRTYPE0", - "PS7_DMA0DRTYPE1", - "PS7_DMA0DRVALID", - "PS7_DMA0RSTN", - "PS7_DMA1ACLK", - "PS7_DMA1DAREADY", - "PS7_DMA1DATYPE0", - "PS7_DMA1DATYPE1", - "PS7_DMA1DAVALID", - "PS7_DMA1DRLAST", - "PS7_DMA1DRREADY", - "PS7_DMA1DRTYPE0", - "PS7_DMA1DRTYPE1", - "PS7_DMA1DRVALID", - "PS7_DMA1RSTN", - "PS7_DMA2ACLK", - "PS7_DMA2DAREADY", - "PS7_DMA2DATYPE0", - "PS7_DMA2DATYPE1", - "PS7_DMA2DAVALID", - "PS7_DMA2DRLAST", - "PS7_DMA2DRREADY", - "PS7_DMA2DRTYPE0", - "PS7_DMA2DRTYPE1", - "PS7_DMA2DRVALID", - "PS7_DMA2RSTN", - "PS7_DMA3ACLK", - "PS7_DMA3DAREADY", - "PS7_DMA3DATYPE0", - "PS7_DMA3DATYPE1", - "PS7_DMA3DAVALID", - "PS7_DMA3DRLAST", - "PS7_DMA3DRREADY", - "PS7_DMA3DRTYPE0", - "PS7_DMA3DRTYPE1", - "PS7_DMA3DRVALID", - "PS7_DMA3RSTN", - "PS7_EMIOCAN0PHYRX", - "PS7_EMIOCAN0PHYTX", - "PS7_EMIOCAN1PHYRX", - "PS7_EMIOCAN1PHYTX", - "PS7_EMIOENET0EXTINTIN", - "PS7_EMIOENET0GMIICOL", - "PS7_EMIOENET0GMIICRS", - "PS7_EMIOENET0GMIIRXCLK", - "PS7_EMIOENET0GMIIRXD0", - "PS7_EMIOENET0GMIIRXD1", - "PS7_EMIOENET0GMIIRXD2", - "PS7_EMIOENET0GMIIRXD3", - "PS7_EMIOENET0GMIIRXD4", - "PS7_EMIOENET0GMIIRXD5", - "PS7_EMIOENET0GMIIRXD6", - "PS7_EMIOENET0GMIIRXD7", - "PS7_EMIOENET0GMIIRXDV", - "PS7_EMIOENET0GMIIRXER", - "PS7_EMIOENET0GMIITXCLK", - "PS7_EMIOENET0GMIITXD0", - "PS7_EMIOENET0GMIITXD1", - "PS7_EMIOENET0GMIITXD2", - "PS7_EMIOENET0GMIITXD3", - "PS7_EMIOENET0GMIITXD4", - "PS7_EMIOENET0GMIITXD5", - "PS7_EMIOENET0GMIITXD6", - "PS7_EMIOENET0GMIITXD7", - "PS7_EMIOENET0GMIITXEN", - "PS7_EMIOENET0GMIITXER", - "PS7_EMIOENET0MDIOI", - "PS7_EMIOENET0MDIOMDC", - "PS7_EMIOENET0MDIOO", - "PS7_EMIOENET0MDIOTN", - "PS7_EMIOENET0PTPDELAYREQRX", - "PS7_EMIOENET0PTPDELAYREQTX", - "PS7_EMIOENET0PTPPDELAYREQRX", - "PS7_EMIOENET0PTPPDELAYREQTX", - "PS7_EMIOENET0PTPPDELAYRESPRX", - "PS7_EMIOENET0PTPPDELAYRESPTX", - "PS7_EMIOENET0PTPSYNCFRAMERX", - "PS7_EMIOENET0PTPSYNCFRAMETX", - "PS7_EMIOENET0SOFRX", - "PS7_EMIOENET0SOFTX", - "PS7_EMIOENET1EXTINTIN", - "PS7_EMIOENET1GMIICOL", - "PS7_EMIOENET1GMIICRS", - "PS7_EMIOENET1GMIIRXCLK", - "PS7_EMIOENET1GMIIRXD0", - "PS7_EMIOENET1GMIIRXD1", - "PS7_EMIOENET1GMIIRXD2", - "PS7_EMIOENET1GMIIRXD3", - "PS7_EMIOENET1GMIIRXD4", - "PS7_EMIOENET1GMIIRXD5", - "PS7_EMIOENET1GMIIRXD6", - "PS7_EMIOENET1GMIIRXD7", - "PS7_EMIOENET1GMIIRXDV", - "PS7_EMIOENET1GMIIRXER", - "PS7_EMIOENET1GMIITXCLK", - "PS7_EMIOENET1GMIITXD0", - "PS7_EMIOENET1GMIITXD1", - "PS7_EMIOENET1GMIITXD2", - "PS7_EMIOENET1GMIITXD3", - "PS7_EMIOENET1GMIITXD4", - "PS7_EMIOENET1GMIITXD5", - "PS7_EMIOENET1GMIITXD6", - "PS7_EMIOENET1GMIITXD7", - "PS7_EMIOENET1GMIITXEN", - "PS7_EMIOENET1GMIITXER", - "PS7_EMIOENET1MDIOI", - "PS7_EMIOENET1MDIOMDC", - "PS7_EMIOENET1MDIOO", - "PS7_EMIOENET1MDIOTN", - "PS7_EMIOENET1PTPDELAYREQRX", - "PS7_EMIOENET1PTPDELAYREQTX", - "PS7_EMIOENET1PTPPDELAYREQRX", - "PS7_EMIOENET1PTPPDELAYREQTX", - "PS7_EMIOENET1PTPPDELAYRESPRX", - "PS7_EMIOENET1PTPPDELAYRESPTX", - "PS7_EMIOENET1PTPSYNCFRAMERX", - "PS7_EMIOENET1PTPSYNCFRAMETX", - "PS7_EMIOENET1SOFRX", - "PS7_EMIOENET1SOFTX", - "PS7_EMIOGPIOI0", - "PS7_EMIOGPIOI1", - "PS7_EMIOGPIOI10", - "PS7_EMIOGPIOI11", - "PS7_EMIOGPIOI12", - "PS7_EMIOGPIOI13", - "PS7_EMIOGPIOI14", - "PS7_EMIOGPIOI15", - "PS7_EMIOGPIOI16", - "PS7_EMIOGPIOI17", - "PS7_EMIOGPIOI18", - "PS7_EMIOGPIOI19", - "PS7_EMIOGPIOI2", - "PS7_EMIOGPIOI20", - "PS7_EMIOGPIOI21", - "PS7_EMIOGPIOI22", - "PS7_EMIOGPIOI23", - "PS7_EMIOGPIOI24", - "PS7_EMIOGPIOI25", - "PS7_EMIOGPIOI26", - "PS7_EMIOGPIOI27", - "PS7_EMIOGPIOI28", - "PS7_EMIOGPIOI29", - "PS7_EMIOGPIOI3", - "PS7_EMIOGPIOI30", - "PS7_EMIOGPIOI31", - "PS7_EMIOGPIOI32", - "PS7_EMIOGPIOI33", - "PS7_EMIOGPIOI34", - "PS7_EMIOGPIOI35", - "PS7_EMIOGPIOI36", - "PS7_EMIOGPIOI37", - "PS7_EMIOGPIOI38", - "PS7_EMIOGPIOI39", - "PS7_EMIOGPIOI4", - "PS7_EMIOGPIOI40", - "PS7_EMIOGPIOI41", - "PS7_EMIOGPIOI42", - "PS7_EMIOGPIOI43", - "PS7_EMIOGPIOI44", - "PS7_EMIOGPIOI45", - "PS7_EMIOGPIOI46", - "PS7_EMIOGPIOI47", - "PS7_EMIOGPIOI48", - "PS7_EMIOGPIOI49", - "PS7_EMIOGPIOI5", - "PS7_EMIOGPIOI50", - "PS7_EMIOGPIOI51", - "PS7_EMIOGPIOI52", - "PS7_EMIOGPIOI53", - "PS7_EMIOGPIOI54", - "PS7_EMIOGPIOI55", - "PS7_EMIOGPIOI56", - "PS7_EMIOGPIOI57", - "PS7_EMIOGPIOI58", - "PS7_EMIOGPIOI59", - "PS7_EMIOGPIOI6", - "PS7_EMIOGPIOI60", - "PS7_EMIOGPIOI61", - "PS7_EMIOGPIOI62", - "PS7_EMIOGPIOI63", - "PS7_EMIOGPIOI7", - "PS7_EMIOGPIOI8", - "PS7_EMIOGPIOI9", - "PS7_EMIOGPIOO0", - "PS7_EMIOGPIOO1", - "PS7_EMIOGPIOO10", - "PS7_EMIOGPIOO11", - "PS7_EMIOGPIOO12", - "PS7_EMIOGPIOO13", - "PS7_EMIOGPIOO14", - "PS7_EMIOGPIOO15", - "PS7_EMIOGPIOO16", - "PS7_EMIOGPIOO17", - "PS7_EMIOGPIOO18", - "PS7_EMIOGPIOO19", - "PS7_EMIOGPIOO2", - "PS7_EMIOGPIOO20", - "PS7_EMIOGPIOO21", - "PS7_EMIOGPIOO22", - "PS7_EMIOGPIOO23", - "PS7_EMIOGPIOO24", - "PS7_EMIOGPIOO25", - "PS7_EMIOGPIOO26", - "PS7_EMIOGPIOO27", - "PS7_EMIOGPIOO28", - "PS7_EMIOGPIOO29", - "PS7_EMIOGPIOO3", - "PS7_EMIOGPIOO30", - "PS7_EMIOGPIOO31", - "PS7_EMIOGPIOO32", - "PS7_EMIOGPIOO33", - "PS7_EMIOGPIOO34", - "PS7_EMIOGPIOO35", - "PS7_EMIOGPIOO36", - "PS7_EMIOGPIOO37", - "PS7_EMIOGPIOO38", - "PS7_EMIOGPIOO39", - "PS7_EMIOGPIOO4", - "PS7_EMIOGPIOO40", - "PS7_EMIOGPIOO41", - "PS7_EMIOGPIOO42", - "PS7_EMIOGPIOO43", - "PS7_EMIOGPIOO44", - "PS7_EMIOGPIOO45", - "PS7_EMIOGPIOO46", - "PS7_EMIOGPIOO47", - "PS7_EMIOGPIOO48", - "PS7_EMIOGPIOO49", - "PS7_EMIOGPIOO5", - "PS7_EMIOGPIOO50", - "PS7_EMIOGPIOO51", - "PS7_EMIOGPIOO52", - "PS7_EMIOGPIOO53", - "PS7_EMIOGPIOO54", - "PS7_EMIOGPIOO55", - "PS7_EMIOGPIOO56", - "PS7_EMIOGPIOO57", - "PS7_EMIOGPIOO58", - "PS7_EMIOGPIOO59", - "PS7_EMIOGPIOO6", - "PS7_EMIOGPIOO60", - "PS7_EMIOGPIOO61", - "PS7_EMIOGPIOO62", - "PS7_EMIOGPIOO63", - "PS7_EMIOGPIOO7", - "PS7_EMIOGPIOO8", - "PS7_EMIOGPIOO9", - "PS7_EMIOGPIOTN0", - "PS7_EMIOGPIOTN1", - "PS7_EMIOGPIOTN10", - "PS7_EMIOGPIOTN11", - "PS7_EMIOGPIOTN12", - "PS7_EMIOGPIOTN13", - "PS7_EMIOGPIOTN14", - "PS7_EMIOGPIOTN15", - "PS7_EMIOGPIOTN16", - "PS7_EMIOGPIOTN17", - "PS7_EMIOGPIOTN18", - "PS7_EMIOGPIOTN19", - "PS7_EMIOGPIOTN2", - "PS7_EMIOGPIOTN20", - "PS7_EMIOGPIOTN21", - "PS7_EMIOGPIOTN22", - "PS7_EMIOGPIOTN23", - "PS7_EMIOGPIOTN24", - "PS7_EMIOGPIOTN25", - "PS7_EMIOGPIOTN26", - "PS7_EMIOGPIOTN27", - "PS7_EMIOGPIOTN28", - "PS7_EMIOGPIOTN29", - "PS7_EMIOGPIOTN3", - "PS7_EMIOGPIOTN30", - "PS7_EMIOGPIOTN31", - "PS7_EMIOGPIOTN32", - "PS7_EMIOGPIOTN33", - "PS7_EMIOGPIOTN34", - "PS7_EMIOGPIOTN35", - "PS7_EMIOGPIOTN36", - "PS7_EMIOGPIOTN37", - "PS7_EMIOGPIOTN38", - "PS7_EMIOGPIOTN39", - "PS7_EMIOGPIOTN4", - "PS7_EMIOGPIOTN40", - "PS7_EMIOGPIOTN41", - "PS7_EMIOGPIOTN42", - "PS7_EMIOGPIOTN43", - "PS7_EMIOGPIOTN44", - "PS7_EMIOGPIOTN45", - "PS7_EMIOGPIOTN46", - "PS7_EMIOGPIOTN47", - "PS7_EMIOGPIOTN48", - "PS7_EMIOGPIOTN49", - "PS7_EMIOGPIOTN5", - "PS7_EMIOGPIOTN50", - "PS7_EMIOGPIOTN51", - "PS7_EMIOGPIOTN52", - "PS7_EMIOGPIOTN53", - "PS7_EMIOGPIOTN54", - "PS7_EMIOGPIOTN55", - "PS7_EMIOGPIOTN56", - "PS7_EMIOGPIOTN57", - "PS7_EMIOGPIOTN58", - "PS7_EMIOGPIOTN59", - "PS7_EMIOGPIOTN6", - "PS7_EMIOGPIOTN60", - "PS7_EMIOGPIOTN61", - "PS7_EMIOGPIOTN62", - "PS7_EMIOGPIOTN63", - "PS7_EMIOGPIOTN7", - "PS7_EMIOGPIOTN8", - "PS7_EMIOGPIOTN9", - "PS7_EMIOI2C0SCLI", - "PS7_EMIOI2C0SCLO", - "PS7_EMIOI2C0SCLTN", - "PS7_EMIOI2C0SDAI", - "PS7_EMIOI2C0SDAO", - "PS7_EMIOI2C0SDATN", - "PS7_EMIOI2C1SCLI", - "PS7_EMIOI2C1SCLO", - "PS7_EMIOI2C1SCLTN", - "PS7_EMIOI2C1SDAI", - "PS7_EMIOI2C1SDAO", - "PS7_EMIOI2C1SDATN", - "PS7_EMIOPJTAGTCK", - "PS7_EMIOPJTAGTDI", - "PS7_EMIOPJTAGTDO", - "PS7_EMIOPJTAGTDTN", - "PS7_EMIOPJTAGTMS", - "PS7_EMIOSDIO0BUSPOW", - "PS7_EMIOSDIO0BUSVOLT0", - "PS7_EMIOSDIO0BUSVOLT1", - "PS7_EMIOSDIO0BUSVOLT2", - "PS7_EMIOSDIO0CDN", - "PS7_EMIOSDIO0CLK", - "PS7_EMIOSDIO0CLKFB", - "PS7_EMIOSDIO0CMDI", - "PS7_EMIOSDIO0CMDO", - "PS7_EMIOSDIO0CMDTN", - "PS7_EMIOSDIO0DATAI0", - "PS7_EMIOSDIO0DATAI1", - "PS7_EMIOSDIO0DATAI2", - "PS7_EMIOSDIO0DATAI3", - "PS7_EMIOSDIO0DATAO0", - "PS7_EMIOSDIO0DATAO1", - "PS7_EMIOSDIO0DATAO2", - "PS7_EMIOSDIO0DATAO3", - "PS7_EMIOSDIO0DATATN0", - "PS7_EMIOSDIO0DATATN1", - "PS7_EMIOSDIO0DATATN2", - "PS7_EMIOSDIO0DATATN3", - "PS7_EMIOSDIO0LED", - "PS7_EMIOSDIO0WP", - "PS7_EMIOSDIO1BUSPOW", - "PS7_EMIOSDIO1BUSVOLT0", - "PS7_EMIOSDIO1BUSVOLT1", - "PS7_EMIOSDIO1BUSVOLT2", - "PS7_EMIOSDIO1CDN", - "PS7_EMIOSDIO1CLK", - "PS7_EMIOSDIO1CLKFB", - "PS7_EMIOSDIO1CMDI", - "PS7_EMIOSDIO1CMDO", - "PS7_EMIOSDIO1CMDTN", - "PS7_EMIOSDIO1DATAI0", - "PS7_EMIOSDIO1DATAI1", - "PS7_EMIOSDIO1DATAI2", - "PS7_EMIOSDIO1DATAI3", - "PS7_EMIOSDIO1DATAO0", - "PS7_EMIOSDIO1DATAO1", - "PS7_EMIOSDIO1DATAO2", - "PS7_EMIOSDIO1DATAO3", - "PS7_EMIOSDIO1DATATN0", - "PS7_EMIOSDIO1DATATN1", - "PS7_EMIOSDIO1DATATN2", - "PS7_EMIOSDIO1DATATN3", - "PS7_EMIOSDIO1LED", - "PS7_EMIOSDIO1WP", - "PS7_EMIOSPI0MI", - "PS7_EMIOSPI0MO", - "PS7_EMIOSPI0MOTN", - "PS7_EMIOSPI0SCLKI", - "PS7_EMIOSPI0SCLKO", - "PS7_EMIOSPI0SCLKTN", - "PS7_EMIOSPI0SI", - "PS7_EMIOSPI0SO", - "PS7_EMIOSPI0SSIN", - "PS7_EMIOSPI0SSNTN", - "PS7_EMIOSPI0SSON0", - "PS7_EMIOSPI0SSON1", - "PS7_EMIOSPI0SSON2", - "PS7_EMIOSPI0STN", - "PS7_EMIOSPI1MI", - "PS7_EMIOSPI1MO", - "PS7_EMIOSPI1MOTN", - "PS7_EMIOSPI1SCLKI", - "PS7_EMIOSPI1SCLKO", - "PS7_EMIOSPI1SCLKTN", - "PS7_EMIOSPI1SI", - "PS7_EMIOSPI1SO", - "PS7_EMIOSPI1SSIN", - "PS7_EMIOSPI1SSNTN", - "PS7_EMIOSPI1SSON0", - "PS7_EMIOSPI1SSON1", - "PS7_EMIOSPI1SSON2", - "PS7_EMIOSPI1STN", - "PS7_EMIOSRAMINTIN", - "PS7_EMIOTRACECLK", - "PS7_EMIOTRACECTL", - "PS7_EMIOTRACEDATA0", - "PS7_EMIOTRACEDATA1", - "PS7_EMIOTRACEDATA10", - "PS7_EMIOTRACEDATA11", - "PS7_EMIOTRACEDATA12", - "PS7_EMIOTRACEDATA13", - "PS7_EMIOTRACEDATA14", - "PS7_EMIOTRACEDATA15", - "PS7_EMIOTRACEDATA16", - "PS7_EMIOTRACEDATA17", - "PS7_EMIOTRACEDATA18", - "PS7_EMIOTRACEDATA19", - "PS7_EMIOTRACEDATA2", - "PS7_EMIOTRACEDATA20", - "PS7_EMIOTRACEDATA21", - "PS7_EMIOTRACEDATA22", - "PS7_EMIOTRACEDATA23", - "PS7_EMIOTRACEDATA24", - "PS7_EMIOTRACEDATA25", - "PS7_EMIOTRACEDATA26", - "PS7_EMIOTRACEDATA27", - "PS7_EMIOTRACEDATA28", - "PS7_EMIOTRACEDATA29", - "PS7_EMIOTRACEDATA3", - "PS7_EMIOTRACEDATA30", - "PS7_EMIOTRACEDATA31", - "PS7_EMIOTRACEDATA4", - "PS7_EMIOTRACEDATA5", - "PS7_EMIOTRACEDATA6", - "PS7_EMIOTRACEDATA7", - "PS7_EMIOTRACEDATA8", - "PS7_EMIOTRACEDATA9", - "PS7_EMIOTTC0CLKI0", - "PS7_EMIOTTC0CLKI1", - "PS7_EMIOTTC0CLKI2", - "PS7_EMIOTTC0WAVEO0", - "PS7_EMIOTTC0WAVEO1", - "PS7_EMIOTTC0WAVEO2", - "PS7_EMIOTTC1CLKI0", - "PS7_EMIOTTC1CLKI1", - "PS7_EMIOTTC1CLKI2", - "PS7_EMIOTTC1WAVEO0", - "PS7_EMIOTTC1WAVEO1", - "PS7_EMIOTTC1WAVEO2", - "PS7_EMIOUART0CTSN", - "PS7_EMIOUART0DCDN", - "PS7_EMIOUART0DSRN", - "PS7_EMIOUART0DTRN", - "PS7_EMIOUART0RIN", - "PS7_EMIOUART0RTSN", - "PS7_EMIOUART0RX", - "PS7_EMIOUART0TX", - "PS7_EMIOUART1CTSN", - "PS7_EMIOUART1DCDN", - "PS7_EMIOUART1DSRN", - "PS7_EMIOUART1DTRN", - "PS7_EMIOUART1RIN", - "PS7_EMIOUART1RTSN", - "PS7_EMIOUART1RX", - "PS7_EMIOUART1TX", - "PS7_EMIOUSB0PORTINDCTL0", - "PS7_EMIOUSB0PORTINDCTL1", - "PS7_EMIOUSB0VBUSPWRFAULT", - "PS7_EMIOUSB0VBUSPWRSELECT", - "PS7_EMIOUSB1PORTINDCTL0", - "PS7_EMIOUSB1PORTINDCTL1", - "PS7_EMIOUSB1VBUSPWRFAULT", - "PS7_EMIOUSB1VBUSPWRSELECT", - "PS7_EMIOWDTCLKI", - "PS7_EMIOWDTRSTO", - "PS7_EVENTEVENTI", - "PS7_EVENTEVENTO", - "PS7_EVENTSTANDBYWFE0", - "PS7_EVENTSTANDBYWFE1", - "PS7_EVENTSTANDBYWFI0", - "PS7_EVENTSTANDBYWFI1", - "PS7_FCLKCLK0", - "PS7_FCLKCLK1", - "PS7_FCLKCLK2", - "PS7_FCLKCLK3", - "PS7_FCLKCLKTRIGN0", - "PS7_FCLKCLKTRIGN1", - "PS7_FCLKCLKTRIGN2", - "PS7_FCLKCLKTRIGN3", - "PS7_FCLKRESETN0", - "PS7_FCLKRESETN1", - "PS7_FCLKRESETN2", - "PS7_FCLKRESETN3", - "PS7_FPGAIDLEN", - "PS7_FTMDTRACEINATID0", - "PS7_FTMDTRACEINATID1", - "PS7_FTMDTRACEINATID2", - "PS7_FTMDTRACEINATID3", - "PS7_FTMDTRACEINCLOCK", - "PS7_FTMDTRACEINDATA0", - "PS7_FTMDTRACEINDATA1", - "PS7_FTMDTRACEINDATA10", - "PS7_FTMDTRACEINDATA11", - "PS7_FTMDTRACEINDATA12", - "PS7_FTMDTRACEINDATA13", - "PS7_FTMDTRACEINDATA14", - "PS7_FTMDTRACEINDATA15", - "PS7_FTMDTRACEINDATA16", - "PS7_FTMDTRACEINDATA17", - "PS7_FTMDTRACEINDATA18", - "PS7_FTMDTRACEINDATA19", - "PS7_FTMDTRACEINDATA2", - "PS7_FTMDTRACEINDATA20", - "PS7_FTMDTRACEINDATA21", - "PS7_FTMDTRACEINDATA22", - "PS7_FTMDTRACEINDATA23", - "PS7_FTMDTRACEINDATA24", - "PS7_FTMDTRACEINDATA25", - "PS7_FTMDTRACEINDATA26", - "PS7_FTMDTRACEINDATA27", - "PS7_FTMDTRACEINDATA28", - "PS7_FTMDTRACEINDATA29", - "PS7_FTMDTRACEINDATA3", - "PS7_FTMDTRACEINDATA30", - "PS7_FTMDTRACEINDATA31", - "PS7_FTMDTRACEINDATA4", - "PS7_FTMDTRACEINDATA5", - "PS7_FTMDTRACEINDATA6", - "PS7_FTMDTRACEINDATA7", - "PS7_FTMDTRACEINDATA8", - "PS7_FTMDTRACEINDATA9", - "PS7_FTMDTRACEINVALID", - "PS7_FTMTF2PDEBUG0", - "PS7_FTMTF2PDEBUG1", - "PS7_FTMTF2PDEBUG10", - "PS7_FTMTF2PDEBUG11", - "PS7_FTMTF2PDEBUG12", - "PS7_FTMTF2PDEBUG13", - "PS7_FTMTF2PDEBUG14", - "PS7_FTMTF2PDEBUG15", - "PS7_FTMTF2PDEBUG16", - "PS7_FTMTF2PDEBUG17", - "PS7_FTMTF2PDEBUG18", - "PS7_FTMTF2PDEBUG19", - "PS7_FTMTF2PDEBUG2", - "PS7_FTMTF2PDEBUG20", - "PS7_FTMTF2PDEBUG21", - "PS7_FTMTF2PDEBUG22", - "PS7_FTMTF2PDEBUG23", - "PS7_FTMTF2PDEBUG24", - "PS7_FTMTF2PDEBUG25", - "PS7_FTMTF2PDEBUG26", - "PS7_FTMTF2PDEBUG27", - "PS7_FTMTF2PDEBUG28", - "PS7_FTMTF2PDEBUG29", - "PS7_FTMTF2PDEBUG3", - "PS7_FTMTF2PDEBUG30", - "PS7_FTMTF2PDEBUG31", - "PS7_FTMTF2PDEBUG4", - "PS7_FTMTF2PDEBUG5", - "PS7_FTMTF2PDEBUG6", - "PS7_FTMTF2PDEBUG7", - "PS7_FTMTF2PDEBUG8", - "PS7_FTMTF2PDEBUG9", - "PS7_FTMTF2PTRIG0", - "PS7_FTMTF2PTRIG1", - "PS7_FTMTF2PTRIG2", - "PS7_FTMTF2PTRIG3", - "PS7_FTMTF2PTRIGACK0", - "PS7_FTMTF2PTRIGACK1", - "PS7_FTMTF2PTRIGACK2", - "PS7_FTMTF2PTRIGACK3", - "PS7_FTMTP2FDEBUG0", - "PS7_FTMTP2FDEBUG1", - "PS7_FTMTP2FDEBUG10", - "PS7_FTMTP2FDEBUG11", - "PS7_FTMTP2FDEBUG12", - "PS7_FTMTP2FDEBUG13", - "PS7_FTMTP2FDEBUG14", - "PS7_FTMTP2FDEBUG15", - "PS7_FTMTP2FDEBUG16", - "PS7_FTMTP2FDEBUG17", - "PS7_FTMTP2FDEBUG18", - "PS7_FTMTP2FDEBUG19", - "PS7_FTMTP2FDEBUG2", - "PS7_FTMTP2FDEBUG20", - "PS7_FTMTP2FDEBUG21", - "PS7_FTMTP2FDEBUG22", - "PS7_FTMTP2FDEBUG23", - "PS7_FTMTP2FDEBUG24", - "PS7_FTMTP2FDEBUG25", - "PS7_FTMTP2FDEBUG26", - "PS7_FTMTP2FDEBUG27", - "PS7_FTMTP2FDEBUG28", - "PS7_FTMTP2FDEBUG29", - "PS7_FTMTP2FDEBUG3", - "PS7_FTMTP2FDEBUG30", - "PS7_FTMTP2FDEBUG31", - "PS7_FTMTP2FDEBUG4", - "PS7_FTMTP2FDEBUG5", - "PS7_FTMTP2FDEBUG6", - "PS7_FTMTP2FDEBUG7", - "PS7_FTMTP2FDEBUG8", - "PS7_FTMTP2FDEBUG9", - "PS7_FTMTP2FTRIG0", - "PS7_FTMTP2FTRIG1", - "PS7_FTMTP2FTRIG2", - "PS7_FTMTP2FTRIG3", - "PS7_FTMTP2FTRIGACK0", - "PS7_FTMTP2FTRIGACK1", - "PS7_FTMTP2FTRIGACK2", - "PS7_FTMTP2FTRIGACK3", - "PS7_IRQF2P0", - "PS7_IRQF2P1", - "PS7_IRQF2P10", - "PS7_IRQF2P11", - "PS7_IRQF2P12", - "PS7_IRQF2P13", - "PS7_IRQF2P14", - "PS7_IRQF2P15", - "PS7_IRQF2P16", - "PS7_IRQF2P17", - "PS7_IRQF2P18", - "PS7_IRQF2P19", - "PS7_IRQF2P2", - "PS7_IRQF2P3", - "PS7_IRQF2P4", - "PS7_IRQF2P5", - "PS7_IRQF2P6", - "PS7_IRQF2P7", - "PS7_IRQF2P8", - "PS7_IRQF2P9", - "PS7_IRQP2F0", - "PS7_IRQP2F1", - "PS7_IRQP2F10", - "PS7_IRQP2F11", - "PS7_IRQP2F12", - "PS7_IRQP2F13", - "PS7_IRQP2F14", - "PS7_IRQP2F15", - "PS7_IRQP2F16", - "PS7_IRQP2F17", - "PS7_IRQP2F18", - "PS7_IRQP2F19", - "PS7_IRQP2F2", - "PS7_IRQP2F20", - "PS7_IRQP2F21", - "PS7_IRQP2F22", - "PS7_IRQP2F23", - "PS7_IRQP2F24", - "PS7_IRQP2F25", - "PS7_IRQP2F26", - "PS7_IRQP2F27", - "PS7_IRQP2F28", - "PS7_IRQP2F3", - "PS7_IRQP2F4", - "PS7_IRQP2F5", - "PS7_IRQP2F6", - "PS7_IRQP2F7", - "PS7_IRQP2F8", - "PS7_IRQP2F9", - "PS7_MAXIGP0ACLK", - "PS7_MAXIGP0ARADDR0", - "PS7_MAXIGP0ARADDR1", - "PS7_MAXIGP0ARADDR10", - "PS7_MAXIGP0ARADDR11", - "PS7_MAXIGP0ARADDR12", - "PS7_MAXIGP0ARADDR13", - "PS7_MAXIGP0ARADDR14", - "PS7_MAXIGP0ARADDR15", - "PS7_MAXIGP0ARADDR16", - "PS7_MAXIGP0ARADDR17", - "PS7_MAXIGP0ARADDR18", - "PS7_MAXIGP0ARADDR19", - "PS7_MAXIGP0ARADDR2", - "PS7_MAXIGP0ARADDR20", - "PS7_MAXIGP0ARADDR21", - "PS7_MAXIGP0ARADDR22", - "PS7_MAXIGP0ARADDR23", - "PS7_MAXIGP0ARADDR24", - "PS7_MAXIGP0ARADDR25", - "PS7_MAXIGP0ARADDR26", - "PS7_MAXIGP0ARADDR27", - "PS7_MAXIGP0ARADDR28", - "PS7_MAXIGP0ARADDR29", - "PS7_MAXIGP0ARADDR3", - "PS7_MAXIGP0ARADDR30", - "PS7_MAXIGP0ARADDR31", - "PS7_MAXIGP0ARADDR4", - "PS7_MAXIGP0ARADDR5", - "PS7_MAXIGP0ARADDR6", - "PS7_MAXIGP0ARADDR7", - "PS7_MAXIGP0ARADDR8", - "PS7_MAXIGP0ARADDR9", - "PS7_MAXIGP0ARBURST0", - "PS7_MAXIGP0ARBURST1", - "PS7_MAXIGP0ARCACHE0", - "PS7_MAXIGP0ARCACHE1", - "PS7_MAXIGP0ARCACHE2", - "PS7_MAXIGP0ARCACHE3", - "PS7_MAXIGP0ARESETN", - "PS7_MAXIGP0ARID0", - "PS7_MAXIGP0ARID1", - "PS7_MAXIGP0ARID10", - "PS7_MAXIGP0ARID11", - "PS7_MAXIGP0ARID2", - "PS7_MAXIGP0ARID3", - "PS7_MAXIGP0ARID4", - "PS7_MAXIGP0ARID5", - "PS7_MAXIGP0ARID6", - "PS7_MAXIGP0ARID7", - "PS7_MAXIGP0ARID8", - "PS7_MAXIGP0ARID9", - "PS7_MAXIGP0ARLEN0", - "PS7_MAXIGP0ARLEN1", - "PS7_MAXIGP0ARLEN2", - "PS7_MAXIGP0ARLEN3", - "PS7_MAXIGP0ARLOCK0", - "PS7_MAXIGP0ARLOCK1", - "PS7_MAXIGP0ARPROT0", - "PS7_MAXIGP0ARPROT1", - "PS7_MAXIGP0ARPROT2", - "PS7_MAXIGP0ARQOS0", - "PS7_MAXIGP0ARQOS1", - "PS7_MAXIGP0ARQOS2", - "PS7_MAXIGP0ARQOS3", - "PS7_MAXIGP0ARREADY", - "PS7_MAXIGP0ARSIZE0", - "PS7_MAXIGP0ARSIZE1", - "PS7_MAXIGP0ARVALID", - "PS7_MAXIGP0AWADDR0", - "PS7_MAXIGP0AWADDR1", - "PS7_MAXIGP0AWADDR10", - "PS7_MAXIGP0AWADDR11", - "PS7_MAXIGP0AWADDR12", - "PS7_MAXIGP0AWADDR13", - "PS7_MAXIGP0AWADDR14", - "PS7_MAXIGP0AWADDR15", - "PS7_MAXIGP0AWADDR16", - "PS7_MAXIGP0AWADDR17", - "PS7_MAXIGP0AWADDR18", - "PS7_MAXIGP0AWADDR19", - "PS7_MAXIGP0AWADDR2", - "PS7_MAXIGP0AWADDR20", - "PS7_MAXIGP0AWADDR21", - "PS7_MAXIGP0AWADDR22", - "PS7_MAXIGP0AWADDR23", - "PS7_MAXIGP0AWADDR24", - "PS7_MAXIGP0AWADDR25", - "PS7_MAXIGP0AWADDR26", - "PS7_MAXIGP0AWADDR27", - "PS7_MAXIGP0AWADDR28", - "PS7_MAXIGP0AWADDR29", - "PS7_MAXIGP0AWADDR3", - "PS7_MAXIGP0AWADDR30", - "PS7_MAXIGP0AWADDR31", - "PS7_MAXIGP0AWADDR4", - "PS7_MAXIGP0AWADDR5", - "PS7_MAXIGP0AWADDR6", - "PS7_MAXIGP0AWADDR7", - "PS7_MAXIGP0AWADDR8", - "PS7_MAXIGP0AWADDR9", - "PS7_MAXIGP0AWBURST0", - "PS7_MAXIGP0AWBURST1", - "PS7_MAXIGP0AWCACHE0", - "PS7_MAXIGP0AWCACHE1", - "PS7_MAXIGP0AWCACHE2", - "PS7_MAXIGP0AWCACHE3", - "PS7_MAXIGP0AWID0", - "PS7_MAXIGP0AWID1", - "PS7_MAXIGP0AWID10", - "PS7_MAXIGP0AWID11", - "PS7_MAXIGP0AWID2", - "PS7_MAXIGP0AWID3", - "PS7_MAXIGP0AWID4", - "PS7_MAXIGP0AWID5", - "PS7_MAXIGP0AWID6", - "PS7_MAXIGP0AWID7", - "PS7_MAXIGP0AWID8", - "PS7_MAXIGP0AWID9", - "PS7_MAXIGP0AWLEN0", - "PS7_MAXIGP0AWLEN1", - "PS7_MAXIGP0AWLEN2", - "PS7_MAXIGP0AWLEN3", - "PS7_MAXIGP0AWLOCK0", - "PS7_MAXIGP0AWLOCK1", - "PS7_MAXIGP0AWPROT0", - "PS7_MAXIGP0AWPROT1", - "PS7_MAXIGP0AWPROT2", - "PS7_MAXIGP0AWQOS0", - "PS7_MAXIGP0AWQOS1", - "PS7_MAXIGP0AWQOS2", - "PS7_MAXIGP0AWQOS3", - "PS7_MAXIGP0AWREADY", - "PS7_MAXIGP0AWSIZE0", - "PS7_MAXIGP0AWSIZE1", - "PS7_MAXIGP0AWVALID", - "PS7_MAXIGP0BID0", - "PS7_MAXIGP0BID1", - "PS7_MAXIGP0BID10", - "PS7_MAXIGP0BID11", - "PS7_MAXIGP0BID2", - "PS7_MAXIGP0BID3", - "PS7_MAXIGP0BID4", - "PS7_MAXIGP0BID5", - "PS7_MAXIGP0BID6", - "PS7_MAXIGP0BID7", - "PS7_MAXIGP0BID8", - "PS7_MAXIGP0BID9", - "PS7_MAXIGP0BREADY", - "PS7_MAXIGP0BRESP0", - "PS7_MAXIGP0BRESP1", - "PS7_MAXIGP0BVALID", - "PS7_MAXIGP0RDATA0", - "PS7_MAXIGP0RDATA1", - "PS7_MAXIGP0RDATA10", - "PS7_MAXIGP0RDATA11", - "PS7_MAXIGP0RDATA12", - "PS7_MAXIGP0RDATA13", - "PS7_MAXIGP0RDATA14", - "PS7_MAXIGP0RDATA15", - "PS7_MAXIGP0RDATA16", - "PS7_MAXIGP0RDATA17", - "PS7_MAXIGP0RDATA18", - "PS7_MAXIGP0RDATA19", - "PS7_MAXIGP0RDATA2", - "PS7_MAXIGP0RDATA20", - "PS7_MAXIGP0RDATA21", - "PS7_MAXIGP0RDATA22", - "PS7_MAXIGP0RDATA23", - "PS7_MAXIGP0RDATA24", - "PS7_MAXIGP0RDATA25", - "PS7_MAXIGP0RDATA26", - "PS7_MAXIGP0RDATA27", - "PS7_MAXIGP0RDATA28", - "PS7_MAXIGP0RDATA29", - "PS7_MAXIGP0RDATA3", - "PS7_MAXIGP0RDATA30", - "PS7_MAXIGP0RDATA31", - "PS7_MAXIGP0RDATA4", - "PS7_MAXIGP0RDATA5", - "PS7_MAXIGP0RDATA6", - "PS7_MAXIGP0RDATA7", - "PS7_MAXIGP0RDATA8", - "PS7_MAXIGP0RDATA9", - "PS7_MAXIGP0RID0", - "PS7_MAXIGP0RID1", - "PS7_MAXIGP0RID10", - "PS7_MAXIGP0RID11", - "PS7_MAXIGP0RID2", - "PS7_MAXIGP0RID3", - "PS7_MAXIGP0RID4", - "PS7_MAXIGP0RID5", - "PS7_MAXIGP0RID6", - "PS7_MAXIGP0RID7", - "PS7_MAXIGP0RID8", - "PS7_MAXIGP0RID9", - "PS7_MAXIGP0RLAST", - "PS7_MAXIGP0RREADY", - "PS7_MAXIGP0RRESP0", - "PS7_MAXIGP0RRESP1", - "PS7_MAXIGP0RVALID", - "PS7_MAXIGP0WDATA0", - "PS7_MAXIGP0WDATA1", - "PS7_MAXIGP0WDATA10", - "PS7_MAXIGP0WDATA11", - "PS7_MAXIGP0WDATA12", - "PS7_MAXIGP0WDATA13", - "PS7_MAXIGP0WDATA14", - "PS7_MAXIGP0WDATA15", - "PS7_MAXIGP0WDATA16", - "PS7_MAXIGP0WDATA17", - "PS7_MAXIGP0WDATA18", - "PS7_MAXIGP0WDATA19", - "PS7_MAXIGP0WDATA2", - "PS7_MAXIGP0WDATA20", - "PS7_MAXIGP0WDATA21", - "PS7_MAXIGP0WDATA22", - "PS7_MAXIGP0WDATA23", - "PS7_MAXIGP0WDATA24", - "PS7_MAXIGP0WDATA25", - "PS7_MAXIGP0WDATA26", - "PS7_MAXIGP0WDATA27", - "PS7_MAXIGP0WDATA28", - "PS7_MAXIGP0WDATA29", - "PS7_MAXIGP0WDATA3", - "PS7_MAXIGP0WDATA30", - "PS7_MAXIGP0WDATA31", - "PS7_MAXIGP0WDATA4", - "PS7_MAXIGP0WDATA5", - "PS7_MAXIGP0WDATA6", - "PS7_MAXIGP0WDATA7", - "PS7_MAXIGP0WDATA8", - "PS7_MAXIGP0WDATA9", - "PS7_MAXIGP0WID0", - "PS7_MAXIGP0WID1", - "PS7_MAXIGP0WID10", - "PS7_MAXIGP0WID11", - "PS7_MAXIGP0WID2", - "PS7_MAXIGP0WID3", - "PS7_MAXIGP0WID4", - "PS7_MAXIGP0WID5", - "PS7_MAXIGP0WID6", - "PS7_MAXIGP0WID7", - "PS7_MAXIGP0WID8", - "PS7_MAXIGP0WID9", - "PS7_MAXIGP0WLAST", - "PS7_MAXIGP0WREADY", - "PS7_MAXIGP0WSTRB0", - "PS7_MAXIGP0WSTRB1", - "PS7_MAXIGP0WSTRB2", - "PS7_MAXIGP0WSTRB3", - "PS7_MAXIGP0WVALID", - "PS7_MAXIGP1ACLK", - "PS7_MAXIGP1ARADDR0", - "PS7_MAXIGP1ARADDR1", - "PS7_MAXIGP1ARADDR10", - "PS7_MAXIGP1ARADDR11", - "PS7_MAXIGP1ARADDR12", - "PS7_MAXIGP1ARADDR13", - "PS7_MAXIGP1ARADDR14", - "PS7_MAXIGP1ARADDR15", - "PS7_MAXIGP1ARADDR16", - "PS7_MAXIGP1ARADDR17", - "PS7_MAXIGP1ARADDR18", - "PS7_MAXIGP1ARADDR19", - "PS7_MAXIGP1ARADDR2", - "PS7_MAXIGP1ARADDR20", - "PS7_MAXIGP1ARADDR21", - "PS7_MAXIGP1ARADDR22", - "PS7_MAXIGP1ARADDR23", - "PS7_MAXIGP1ARADDR24", - "PS7_MAXIGP1ARADDR25", - "PS7_MAXIGP1ARADDR26", - "PS7_MAXIGP1ARADDR27", - "PS7_MAXIGP1ARADDR28", - "PS7_MAXIGP1ARADDR29", - "PS7_MAXIGP1ARADDR3", - "PS7_MAXIGP1ARADDR30", - "PS7_MAXIGP1ARADDR31", - "PS7_MAXIGP1ARADDR4", - "PS7_MAXIGP1ARADDR5", - "PS7_MAXIGP1ARADDR6", - "PS7_MAXIGP1ARADDR7", - "PS7_MAXIGP1ARADDR8", - "PS7_MAXIGP1ARADDR9", - "PS7_MAXIGP1ARBURST0", - "PS7_MAXIGP1ARBURST1", - "PS7_MAXIGP1ARCACHE0", - "PS7_MAXIGP1ARCACHE1", - "PS7_MAXIGP1ARCACHE2", - "PS7_MAXIGP1ARCACHE3", - "PS7_MAXIGP1ARESETN", - "PS7_MAXIGP1ARID0", - "PS7_MAXIGP1ARID1", - "PS7_MAXIGP1ARID10", - "PS7_MAXIGP1ARID11", - "PS7_MAXIGP1ARID2", - "PS7_MAXIGP1ARID3", - "PS7_MAXIGP1ARID4", - "PS7_MAXIGP1ARID5", - "PS7_MAXIGP1ARID6", - "PS7_MAXIGP1ARID7", - "PS7_MAXIGP1ARID8", - "PS7_MAXIGP1ARID9", - "PS7_MAXIGP1ARLEN0", - "PS7_MAXIGP1ARLEN1", - "PS7_MAXIGP1ARLEN2", - "PS7_MAXIGP1ARLEN3", - "PS7_MAXIGP1ARLOCK0", - "PS7_MAXIGP1ARLOCK1", - "PS7_MAXIGP1ARPROT0", - "PS7_MAXIGP1ARPROT1", - "PS7_MAXIGP1ARPROT2", - "PS7_MAXIGP1ARQOS0", - "PS7_MAXIGP1ARQOS1", - "PS7_MAXIGP1ARQOS2", - "PS7_MAXIGP1ARQOS3", - "PS7_MAXIGP1ARREADY", - "PS7_MAXIGP1ARSIZE0", - "PS7_MAXIGP1ARSIZE1", - "PS7_MAXIGP1ARVALID", - "PS7_MAXIGP1AWADDR0", - "PS7_MAXIGP1AWADDR1", - "PS7_MAXIGP1AWADDR10", - "PS7_MAXIGP1AWADDR11", - "PS7_MAXIGP1AWADDR12", - "PS7_MAXIGP1AWADDR13", - "PS7_MAXIGP1AWADDR14", - "PS7_MAXIGP1AWADDR15", - "PS7_MAXIGP1AWADDR16", - "PS7_MAXIGP1AWADDR17", - "PS7_MAXIGP1AWADDR18", - "PS7_MAXIGP1AWADDR19", - "PS7_MAXIGP1AWADDR2", - "PS7_MAXIGP1AWADDR20", - "PS7_MAXIGP1AWADDR21", - "PS7_MAXIGP1AWADDR22", - "PS7_MAXIGP1AWADDR23", - "PS7_MAXIGP1AWADDR24", - "PS7_MAXIGP1AWADDR25", - "PS7_MAXIGP1AWADDR26", - "PS7_MAXIGP1AWADDR27", - "PS7_MAXIGP1AWADDR28", - "PS7_MAXIGP1AWADDR29", - "PS7_MAXIGP1AWADDR3", - "PS7_MAXIGP1AWADDR30", - "PS7_MAXIGP1AWADDR31", - "PS7_MAXIGP1AWADDR4", - "PS7_MAXIGP1AWADDR5", - "PS7_MAXIGP1AWADDR6", - "PS7_MAXIGP1AWADDR7", - "PS7_MAXIGP1AWADDR8", - "PS7_MAXIGP1AWADDR9", - "PS7_MAXIGP1AWBURST0", - "PS7_MAXIGP1AWBURST1", - "PS7_MAXIGP1AWCACHE0", - "PS7_MAXIGP1AWCACHE1", - "PS7_MAXIGP1AWCACHE2", - "PS7_MAXIGP1AWCACHE3", - "PS7_MAXIGP1AWID0", - "PS7_MAXIGP1AWID1", - "PS7_MAXIGP1AWID10", - "PS7_MAXIGP1AWID11", - "PS7_MAXIGP1AWID2", - "PS7_MAXIGP1AWID3", - "PS7_MAXIGP1AWID4", - "PS7_MAXIGP1AWID5", - "PS7_MAXIGP1AWID6", - "PS7_MAXIGP1AWID7", - "PS7_MAXIGP1AWID8", - "PS7_MAXIGP1AWID9", - "PS7_MAXIGP1AWLEN0", - "PS7_MAXIGP1AWLEN1", - "PS7_MAXIGP1AWLEN2", - "PS7_MAXIGP1AWLEN3", - "PS7_MAXIGP1AWLOCK0", - "PS7_MAXIGP1AWLOCK1", - "PS7_MAXIGP1AWPROT0", - "PS7_MAXIGP1AWPROT1", - "PS7_MAXIGP1AWPROT2", - "PS7_MAXIGP1AWQOS0", - "PS7_MAXIGP1AWQOS1", - "PS7_MAXIGP1AWQOS2", - "PS7_MAXIGP1AWQOS3", - "PS7_MAXIGP1AWREADY", - "PS7_MAXIGP1AWSIZE0", - "PS7_MAXIGP1AWSIZE1", - "PS7_MAXIGP1AWVALID", - "PS7_MAXIGP1BID0", - "PS7_MAXIGP1BID1", - "PS7_MAXIGP1BID10", - "PS7_MAXIGP1BID11", - "PS7_MAXIGP1BID2", - "PS7_MAXIGP1BID3", - "PS7_MAXIGP1BID4", - "PS7_MAXIGP1BID5", - "PS7_MAXIGP1BID6", - "PS7_MAXIGP1BID7", - "PS7_MAXIGP1BID8", - "PS7_MAXIGP1BID9", - "PS7_MAXIGP1BREADY", - "PS7_MAXIGP1BRESP0", - "PS7_MAXIGP1BRESP1", - "PS7_MAXIGP1BVALID", - "PS7_MAXIGP1RDATA0", - "PS7_MAXIGP1RDATA1", - "PS7_MAXIGP1RDATA10", - "PS7_MAXIGP1RDATA11", - "PS7_MAXIGP1RDATA12", - "PS7_MAXIGP1RDATA13", - "PS7_MAXIGP1RDATA14", - "PS7_MAXIGP1RDATA15", - "PS7_MAXIGP1RDATA16", - "PS7_MAXIGP1RDATA17", - "PS7_MAXIGP1RDATA18", - "PS7_MAXIGP1RDATA19", - "PS7_MAXIGP1RDATA2", - "PS7_MAXIGP1RDATA20", - "PS7_MAXIGP1RDATA21", - "PS7_MAXIGP1RDATA22", - "PS7_MAXIGP1RDATA23", - "PS7_MAXIGP1RDATA24", - "PS7_MAXIGP1RDATA25", - "PS7_MAXIGP1RDATA26", - "PS7_MAXIGP1RDATA27", - "PS7_MAXIGP1RDATA28", - "PS7_MAXIGP1RDATA29", - "PS7_MAXIGP1RDATA3", - "PS7_MAXIGP1RDATA30", - "PS7_MAXIGP1RDATA31", - "PS7_MAXIGP1RDATA4", - "PS7_MAXIGP1RDATA5", - "PS7_MAXIGP1RDATA6", - "PS7_MAXIGP1RDATA7", - "PS7_MAXIGP1RDATA8", - "PS7_MAXIGP1RDATA9", - "PS7_MAXIGP1RID0", - "PS7_MAXIGP1RID1", - "PS7_MAXIGP1RID10", - "PS7_MAXIGP1RID11", - "PS7_MAXIGP1RID2", - "PS7_MAXIGP1RID3", - "PS7_MAXIGP1RID4", - "PS7_MAXIGP1RID5", - "PS7_MAXIGP1RID6", - "PS7_MAXIGP1RID7", - "PS7_MAXIGP1RID8", - "PS7_MAXIGP1RID9", - "PS7_MAXIGP1RLAST", - "PS7_MAXIGP1RREADY", - "PS7_MAXIGP1RRESP0", - "PS7_MAXIGP1RRESP1", - "PS7_MAXIGP1RVALID", - "PS7_MAXIGP1WDATA0", - "PS7_MAXIGP1WDATA1", - "PS7_MAXIGP1WDATA10", - "PS7_MAXIGP1WDATA11", - "PS7_MAXIGP1WDATA12", - "PS7_MAXIGP1WDATA13", - "PS7_MAXIGP1WDATA14", - "PS7_MAXIGP1WDATA15", - "PS7_MAXIGP1WDATA16", - "PS7_MAXIGP1WDATA17", - "PS7_MAXIGP1WDATA18", - "PS7_MAXIGP1WDATA19", - "PS7_MAXIGP1WDATA2", - "PS7_MAXIGP1WDATA20", - "PS7_MAXIGP1WDATA21", - "PS7_MAXIGP1WDATA22", - "PS7_MAXIGP1WDATA23", - "PS7_MAXIGP1WDATA24", - "PS7_MAXIGP1WDATA25", - "PS7_MAXIGP1WDATA26", - "PS7_MAXIGP1WDATA27", - "PS7_MAXIGP1WDATA28", - "PS7_MAXIGP1WDATA29", - "PS7_MAXIGP1WDATA3", - "PS7_MAXIGP1WDATA30", - "PS7_MAXIGP1WDATA31", - "PS7_MAXIGP1WDATA4", - "PS7_MAXIGP1WDATA5", - "PS7_MAXIGP1WDATA6", - "PS7_MAXIGP1WDATA7", - "PS7_MAXIGP1WDATA8", - "PS7_MAXIGP1WDATA9", - "PS7_MAXIGP1WID0", - "PS7_MAXIGP1WID1", - "PS7_MAXIGP1WID10", - "PS7_MAXIGP1WID11", - "PS7_MAXIGP1WID2", - "PS7_MAXIGP1WID3", - "PS7_MAXIGP1WID4", - "PS7_MAXIGP1WID5", - "PS7_MAXIGP1WID6", - "PS7_MAXIGP1WID7", - "PS7_MAXIGP1WID8", - "PS7_MAXIGP1WID9", - "PS7_MAXIGP1WLAST", - "PS7_MAXIGP1WREADY", - "PS7_MAXIGP1WSTRB0", - "PS7_MAXIGP1WSTRB1", - "PS7_MAXIGP1WSTRB2", - "PS7_MAXIGP1WSTRB3", - "PS7_MAXIGP1WVALID", - "PS7_MIO0", - "PS7_MIO1", - "PS7_MIO10", - "PS7_MIO11", - "PS7_MIO12", - "PS7_MIO13", - "PS7_MIO14", - "PS7_MIO15", - "PS7_MIO16", - "PS7_MIO17", - "PS7_MIO18", - "PS7_MIO19", - "PS7_MIO2", - "PS7_MIO20", - "PS7_MIO21", - "PS7_MIO22", - "PS7_MIO23", - "PS7_MIO24", - "PS7_MIO25", - "PS7_MIO26", - "PS7_MIO27", - "PS7_MIO28", - "PS7_MIO29", - "PS7_MIO3", - "PS7_MIO30", - "PS7_MIO31", - "PS7_MIO32", - "PS7_MIO33", - "PS7_MIO34", - "PS7_MIO35", - "PS7_MIO36", - "PS7_MIO37", - "PS7_MIO38", - "PS7_MIO39", - "PS7_MIO4", - "PS7_MIO40", - "PS7_MIO41", - "PS7_MIO42", - "PS7_MIO43", - "PS7_MIO44", - "PS7_MIO45", - "PS7_MIO46", - "PS7_MIO47", - "PS7_MIO48", - "PS7_MIO49", - "PS7_MIO5", - "PS7_MIO50", - "PS7_MIO51", - "PS7_MIO52", - "PS7_MIO53", - "PS7_MIO6", - "PS7_MIO7", - "PS7_MIO8", - "PS7_MIO9", - "PS7_PSCLK", - "PS7_PSPORB", - "PS7_PSSRSTB", - "PS7_SAXIACPACLK", - "PS7_SAXIACPARADDR0", - "PS7_SAXIACPARADDR1", - "PS7_SAXIACPARADDR10", - "PS7_SAXIACPARADDR11", - "PS7_SAXIACPARADDR12", - "PS7_SAXIACPARADDR13", - "PS7_SAXIACPARADDR14", - "PS7_SAXIACPARADDR15", - "PS7_SAXIACPARADDR16", - "PS7_SAXIACPARADDR17", - "PS7_SAXIACPARADDR18", - "PS7_SAXIACPARADDR19", - "PS7_SAXIACPARADDR2", - "PS7_SAXIACPARADDR20", - "PS7_SAXIACPARADDR21", - "PS7_SAXIACPARADDR22", - "PS7_SAXIACPARADDR23", - "PS7_SAXIACPARADDR24", - "PS7_SAXIACPARADDR25", - "PS7_SAXIACPARADDR26", - "PS7_SAXIACPARADDR27", - "PS7_SAXIACPARADDR28", - "PS7_SAXIACPARADDR29", - "PS7_SAXIACPARADDR3", - "PS7_SAXIACPARADDR30", - "PS7_SAXIACPARADDR31", - "PS7_SAXIACPARADDR4", - "PS7_SAXIACPARADDR5", - "PS7_SAXIACPARADDR6", - "PS7_SAXIACPARADDR7", - "PS7_SAXIACPARADDR8", - "PS7_SAXIACPARADDR9", - "PS7_SAXIACPARBURST0", - "PS7_SAXIACPARBURST1", - "PS7_SAXIACPARCACHE0", - "PS7_SAXIACPARCACHE1", - "PS7_SAXIACPARCACHE2", - "PS7_SAXIACPARCACHE3", - "PS7_SAXIACPARESETN", - "PS7_SAXIACPARID0", - "PS7_SAXIACPARID1", - "PS7_SAXIACPARID2", - "PS7_SAXIACPARLEN0", - "PS7_SAXIACPARLEN1", - "PS7_SAXIACPARLEN2", - "PS7_SAXIACPARLEN3", - "PS7_SAXIACPARLOCK0", - "PS7_SAXIACPARLOCK1", - "PS7_SAXIACPARPROT0", - "PS7_SAXIACPARPROT1", - "PS7_SAXIACPARPROT2", - "PS7_SAXIACPARQOS0", - "PS7_SAXIACPARQOS1", - "PS7_SAXIACPARQOS2", - "PS7_SAXIACPARQOS3", - "PS7_SAXIACPARREADY", - "PS7_SAXIACPARSIZE0", - "PS7_SAXIACPARSIZE1", - "PS7_SAXIACPARUSER0", - "PS7_SAXIACPARUSER1", - "PS7_SAXIACPARUSER2", - "PS7_SAXIACPARUSER3", - "PS7_SAXIACPARUSER4", - "PS7_SAXIACPARVALID", - "PS7_SAXIACPAWADDR0", - "PS7_SAXIACPAWADDR1", - "PS7_SAXIACPAWADDR10", - "PS7_SAXIACPAWADDR11", - "PS7_SAXIACPAWADDR12", - "PS7_SAXIACPAWADDR13", - "PS7_SAXIACPAWADDR14", - "PS7_SAXIACPAWADDR15", - "PS7_SAXIACPAWADDR16", - "PS7_SAXIACPAWADDR17", - "PS7_SAXIACPAWADDR18", - "PS7_SAXIACPAWADDR19", - "PS7_SAXIACPAWADDR2", - "PS7_SAXIACPAWADDR20", - "PS7_SAXIACPAWADDR21", - "PS7_SAXIACPAWADDR22", - "PS7_SAXIACPAWADDR23", - "PS7_SAXIACPAWADDR24", - "PS7_SAXIACPAWADDR25", - "PS7_SAXIACPAWADDR26", - "PS7_SAXIACPAWADDR27", - "PS7_SAXIACPAWADDR28", - "PS7_SAXIACPAWADDR29", - "PS7_SAXIACPAWADDR3", - "PS7_SAXIACPAWADDR30", - "PS7_SAXIACPAWADDR31", - "PS7_SAXIACPAWADDR4", - "PS7_SAXIACPAWADDR5", - "PS7_SAXIACPAWADDR6", - "PS7_SAXIACPAWADDR7", - "PS7_SAXIACPAWADDR8", - "PS7_SAXIACPAWADDR9", - "PS7_SAXIACPAWBURST0", - "PS7_SAXIACPAWBURST1", - "PS7_SAXIACPAWCACHE0", - "PS7_SAXIACPAWCACHE1", - "PS7_SAXIACPAWCACHE2", - "PS7_SAXIACPAWCACHE3", - "PS7_SAXIACPAWID0", - "PS7_SAXIACPAWID1", - "PS7_SAXIACPAWID2", - "PS7_SAXIACPAWLEN0", - "PS7_SAXIACPAWLEN1", - "PS7_SAXIACPAWLEN2", - "PS7_SAXIACPAWLEN3", - "PS7_SAXIACPAWLOCK0", - "PS7_SAXIACPAWLOCK1", - "PS7_SAXIACPAWPROT0", - "PS7_SAXIACPAWPROT1", - "PS7_SAXIACPAWPROT2", - "PS7_SAXIACPAWQOS0", - "PS7_SAXIACPAWQOS1", - "PS7_SAXIACPAWQOS2", - "PS7_SAXIACPAWQOS3", - "PS7_SAXIACPAWREADY", - "PS7_SAXIACPAWSIZE0", - "PS7_SAXIACPAWSIZE1", - "PS7_SAXIACPAWUSER0", - "PS7_SAXIACPAWUSER1", - "PS7_SAXIACPAWUSER2", - "PS7_SAXIACPAWUSER3", - "PS7_SAXIACPAWUSER4", - "PS7_SAXIACPAWVALID", - "PS7_SAXIACPBID0", - "PS7_SAXIACPBID1", - "PS7_SAXIACPBID2", - "PS7_SAXIACPBREADY", - "PS7_SAXIACPBRESP0", - "PS7_SAXIACPBRESP1", - "PS7_SAXIACPBVALID", - "PS7_SAXIACPRDATA0", - "PS7_SAXIACPRDATA1", - "PS7_SAXIACPRDATA10", - "PS7_SAXIACPRDATA11", - "PS7_SAXIACPRDATA12", - "PS7_SAXIACPRDATA13", - "PS7_SAXIACPRDATA14", - "PS7_SAXIACPRDATA15", - "PS7_SAXIACPRDATA16", - "PS7_SAXIACPRDATA17", - "PS7_SAXIACPRDATA18", - "PS7_SAXIACPRDATA19", - "PS7_SAXIACPRDATA2", - "PS7_SAXIACPRDATA20", - "PS7_SAXIACPRDATA21", - "PS7_SAXIACPRDATA22", - "PS7_SAXIACPRDATA23", - "PS7_SAXIACPRDATA24", - "PS7_SAXIACPRDATA25", - "PS7_SAXIACPRDATA26", - "PS7_SAXIACPRDATA27", - "PS7_SAXIACPRDATA28", - "PS7_SAXIACPRDATA29", - "PS7_SAXIACPRDATA3", - "PS7_SAXIACPRDATA30", - "PS7_SAXIACPRDATA31", - "PS7_SAXIACPRDATA32", - "PS7_SAXIACPRDATA33", - "PS7_SAXIACPRDATA34", - "PS7_SAXIACPRDATA35", - "PS7_SAXIACPRDATA36", - "PS7_SAXIACPRDATA37", - "PS7_SAXIACPRDATA38", - "PS7_SAXIACPRDATA39", - "PS7_SAXIACPRDATA4", - "PS7_SAXIACPRDATA40", - "PS7_SAXIACPRDATA41", - "PS7_SAXIACPRDATA42", - "PS7_SAXIACPRDATA43", - "PS7_SAXIACPRDATA44", - "PS7_SAXIACPRDATA45", - "PS7_SAXIACPRDATA46", - "PS7_SAXIACPRDATA47", - "PS7_SAXIACPRDATA48", - "PS7_SAXIACPRDATA49", - "PS7_SAXIACPRDATA5", - "PS7_SAXIACPRDATA50", - "PS7_SAXIACPRDATA51", - "PS7_SAXIACPRDATA52", - "PS7_SAXIACPRDATA53", - "PS7_SAXIACPRDATA54", - "PS7_SAXIACPRDATA55", - "PS7_SAXIACPRDATA56", - "PS7_SAXIACPRDATA57", - "PS7_SAXIACPRDATA58", - "PS7_SAXIACPRDATA59", - "PS7_SAXIACPRDATA6", - "PS7_SAXIACPRDATA60", - "PS7_SAXIACPRDATA61", - "PS7_SAXIACPRDATA62", - "PS7_SAXIACPRDATA63", - "PS7_SAXIACPRDATA7", - "PS7_SAXIACPRDATA8", - "PS7_SAXIACPRDATA9", - "PS7_SAXIACPRID0", - "PS7_SAXIACPRID1", - "PS7_SAXIACPRID2", - "PS7_SAXIACPRLAST", - "PS7_SAXIACPRREADY", - "PS7_SAXIACPRRESP0", - "PS7_SAXIACPRRESP1", - "PS7_SAXIACPRVALID", - "PS7_SAXIACPWDATA0", - "PS7_SAXIACPWDATA1", - "PS7_SAXIACPWDATA10", - "PS7_SAXIACPWDATA11", - "PS7_SAXIACPWDATA12", - "PS7_SAXIACPWDATA13", - "PS7_SAXIACPWDATA14", - "PS7_SAXIACPWDATA15", - "PS7_SAXIACPWDATA16", - "PS7_SAXIACPWDATA17", - "PS7_SAXIACPWDATA18", - "PS7_SAXIACPWDATA19", - "PS7_SAXIACPWDATA2", - "PS7_SAXIACPWDATA20", - "PS7_SAXIACPWDATA21", - "PS7_SAXIACPWDATA22", - "PS7_SAXIACPWDATA23", - "PS7_SAXIACPWDATA24", - "PS7_SAXIACPWDATA25", - "PS7_SAXIACPWDATA26", - "PS7_SAXIACPWDATA27", - "PS7_SAXIACPWDATA28", - "PS7_SAXIACPWDATA29", - "PS7_SAXIACPWDATA3", - "PS7_SAXIACPWDATA30", - "PS7_SAXIACPWDATA31", - "PS7_SAXIACPWDATA32", - "PS7_SAXIACPWDATA33", - "PS7_SAXIACPWDATA34", - "PS7_SAXIACPWDATA35", - "PS7_SAXIACPWDATA36", - "PS7_SAXIACPWDATA37", - "PS7_SAXIACPWDATA38", - "PS7_SAXIACPWDATA39", - "PS7_SAXIACPWDATA4", - "PS7_SAXIACPWDATA40", - "PS7_SAXIACPWDATA41", - "PS7_SAXIACPWDATA42", - "PS7_SAXIACPWDATA43", - "PS7_SAXIACPWDATA44", - "PS7_SAXIACPWDATA45", - "PS7_SAXIACPWDATA46", - "PS7_SAXIACPWDATA47", - "PS7_SAXIACPWDATA48", - "PS7_SAXIACPWDATA49", - "PS7_SAXIACPWDATA5", - "PS7_SAXIACPWDATA50", - "PS7_SAXIACPWDATA51", - "PS7_SAXIACPWDATA52", - "PS7_SAXIACPWDATA53", - "PS7_SAXIACPWDATA54", - "PS7_SAXIACPWDATA55", - "PS7_SAXIACPWDATA56", - "PS7_SAXIACPWDATA57", - "PS7_SAXIACPWDATA58", - "PS7_SAXIACPWDATA59", - "PS7_SAXIACPWDATA6", - "PS7_SAXIACPWDATA60", - "PS7_SAXIACPWDATA61", - "PS7_SAXIACPWDATA62", - "PS7_SAXIACPWDATA63", - "PS7_SAXIACPWDATA7", - "PS7_SAXIACPWDATA8", - "PS7_SAXIACPWDATA9", - "PS7_SAXIACPWID0", - "PS7_SAXIACPWID1", - "PS7_SAXIACPWID2", - "PS7_SAXIACPWLAST", - "PS7_SAXIACPWREADY", - "PS7_SAXIACPWSTRB0", - "PS7_SAXIACPWSTRB1", - "PS7_SAXIACPWSTRB2", - "PS7_SAXIACPWSTRB3", - "PS7_SAXIACPWSTRB4", - "PS7_SAXIACPWSTRB5", - "PS7_SAXIACPWSTRB6", - "PS7_SAXIACPWSTRB7", - "PS7_SAXIACPWVALID", - "PS7_SAXIGP0ACLK", - "PS7_SAXIGP0ARADDR0", - "PS7_SAXIGP0ARADDR1", - "PS7_SAXIGP0ARADDR10", - "PS7_SAXIGP0ARADDR11", - "PS7_SAXIGP0ARADDR12", - "PS7_SAXIGP0ARADDR13", - "PS7_SAXIGP0ARADDR14", - "PS7_SAXIGP0ARADDR15", - "PS7_SAXIGP0ARADDR16", - "PS7_SAXIGP0ARADDR17", - "PS7_SAXIGP0ARADDR18", - "PS7_SAXIGP0ARADDR19", - "PS7_SAXIGP0ARADDR2", - "PS7_SAXIGP0ARADDR20", - "PS7_SAXIGP0ARADDR21", - "PS7_SAXIGP0ARADDR22", - "PS7_SAXIGP0ARADDR23", - "PS7_SAXIGP0ARADDR24", - "PS7_SAXIGP0ARADDR25", - "PS7_SAXIGP0ARADDR26", - "PS7_SAXIGP0ARADDR27", - "PS7_SAXIGP0ARADDR28", - "PS7_SAXIGP0ARADDR29", - "PS7_SAXIGP0ARADDR3", - "PS7_SAXIGP0ARADDR30", - "PS7_SAXIGP0ARADDR31", - "PS7_SAXIGP0ARADDR4", - "PS7_SAXIGP0ARADDR5", - "PS7_SAXIGP0ARADDR6", - "PS7_SAXIGP0ARADDR7", - "PS7_SAXIGP0ARADDR8", - "PS7_SAXIGP0ARADDR9", - "PS7_SAXIGP0ARBURST0", - "PS7_SAXIGP0ARBURST1", - "PS7_SAXIGP0ARCACHE0", - "PS7_SAXIGP0ARCACHE1", - "PS7_SAXIGP0ARCACHE2", - "PS7_SAXIGP0ARCACHE3", - "PS7_SAXIGP0ARESETN", - "PS7_SAXIGP0ARID0", - "PS7_SAXIGP0ARID1", - "PS7_SAXIGP0ARID2", - "PS7_SAXIGP0ARID3", - "PS7_SAXIGP0ARID4", - "PS7_SAXIGP0ARID5", - "PS7_SAXIGP0ARLEN0", - "PS7_SAXIGP0ARLEN1", - "PS7_SAXIGP0ARLEN2", - "PS7_SAXIGP0ARLEN3", - "PS7_SAXIGP0ARLOCK0", - "PS7_SAXIGP0ARLOCK1", - "PS7_SAXIGP0ARPROT0", - "PS7_SAXIGP0ARPROT1", - "PS7_SAXIGP0ARPROT2", - "PS7_SAXIGP0ARQOS0", - "PS7_SAXIGP0ARQOS1", - "PS7_SAXIGP0ARQOS2", - "PS7_SAXIGP0ARQOS3", - "PS7_SAXIGP0ARREADY", - "PS7_SAXIGP0ARSIZE0", - "PS7_SAXIGP0ARSIZE1", - "PS7_SAXIGP0ARVALID", - "PS7_SAXIGP0AWADDR0", - "PS7_SAXIGP0AWADDR1", - "PS7_SAXIGP0AWADDR10", - "PS7_SAXIGP0AWADDR11", - "PS7_SAXIGP0AWADDR12", - "PS7_SAXIGP0AWADDR13", - "PS7_SAXIGP0AWADDR14", - "PS7_SAXIGP0AWADDR15", - "PS7_SAXIGP0AWADDR16", - "PS7_SAXIGP0AWADDR17", - "PS7_SAXIGP0AWADDR18", - "PS7_SAXIGP0AWADDR19", - "PS7_SAXIGP0AWADDR2", - "PS7_SAXIGP0AWADDR20", - "PS7_SAXIGP0AWADDR21", - "PS7_SAXIGP0AWADDR22", - "PS7_SAXIGP0AWADDR23", - "PS7_SAXIGP0AWADDR24", - "PS7_SAXIGP0AWADDR25", - "PS7_SAXIGP0AWADDR26", - "PS7_SAXIGP0AWADDR27", - "PS7_SAXIGP0AWADDR28", - "PS7_SAXIGP0AWADDR29", - "PS7_SAXIGP0AWADDR3", - "PS7_SAXIGP0AWADDR30", - "PS7_SAXIGP0AWADDR31", - "PS7_SAXIGP0AWADDR4", - "PS7_SAXIGP0AWADDR5", - "PS7_SAXIGP0AWADDR6", - "PS7_SAXIGP0AWADDR7", - "PS7_SAXIGP0AWADDR8", - "PS7_SAXIGP0AWADDR9", - "PS7_SAXIGP0AWBURST0", - "PS7_SAXIGP0AWBURST1", - "PS7_SAXIGP0AWCACHE0", - "PS7_SAXIGP0AWCACHE1", - "PS7_SAXIGP0AWCACHE2", - "PS7_SAXIGP0AWCACHE3", - "PS7_SAXIGP0AWID0", - "PS7_SAXIGP0AWID1", - "PS7_SAXIGP0AWID2", - "PS7_SAXIGP0AWID3", - "PS7_SAXIGP0AWID4", - "PS7_SAXIGP0AWID5", - "PS7_SAXIGP0AWLEN0", - "PS7_SAXIGP0AWLEN1", - "PS7_SAXIGP0AWLEN2", - "PS7_SAXIGP0AWLEN3", - "PS7_SAXIGP0AWLOCK0", - "PS7_SAXIGP0AWLOCK1", - "PS7_SAXIGP0AWPROT0", - "PS7_SAXIGP0AWPROT1", - "PS7_SAXIGP0AWPROT2", - "PS7_SAXIGP0AWQOS0", - "PS7_SAXIGP0AWQOS1", - "PS7_SAXIGP0AWQOS2", - "PS7_SAXIGP0AWQOS3", - "PS7_SAXIGP0AWREADY", - "PS7_SAXIGP0AWSIZE0", - "PS7_SAXIGP0AWSIZE1", - "PS7_SAXIGP0AWVALID", - "PS7_SAXIGP0BID0", - "PS7_SAXIGP0BID1", - "PS7_SAXIGP0BID2", - "PS7_SAXIGP0BID3", - "PS7_SAXIGP0BID4", - "PS7_SAXIGP0BID5", - "PS7_SAXIGP0BREADY", - "PS7_SAXIGP0BRESP0", - "PS7_SAXIGP0BRESP1", - "PS7_SAXIGP0BVALID", - "PS7_SAXIGP0RDATA0", - "PS7_SAXIGP0RDATA1", - "PS7_SAXIGP0RDATA10", - "PS7_SAXIGP0RDATA11", - "PS7_SAXIGP0RDATA12", - "PS7_SAXIGP0RDATA13", - "PS7_SAXIGP0RDATA14", - "PS7_SAXIGP0RDATA15", - "PS7_SAXIGP0RDATA16", - "PS7_SAXIGP0RDATA17", - "PS7_SAXIGP0RDATA18", - "PS7_SAXIGP0RDATA19", - "PS7_SAXIGP0RDATA2", - "PS7_SAXIGP0RDATA20", - "PS7_SAXIGP0RDATA21", - "PS7_SAXIGP0RDATA22", - "PS7_SAXIGP0RDATA23", - "PS7_SAXIGP0RDATA24", - "PS7_SAXIGP0RDATA25", - "PS7_SAXIGP0RDATA26", - "PS7_SAXIGP0RDATA27", - "PS7_SAXIGP0RDATA28", - "PS7_SAXIGP0RDATA29", - "PS7_SAXIGP0RDATA3", - "PS7_SAXIGP0RDATA30", - "PS7_SAXIGP0RDATA31", - "PS7_SAXIGP0RDATA4", - "PS7_SAXIGP0RDATA5", - "PS7_SAXIGP0RDATA6", - "PS7_SAXIGP0RDATA7", - "PS7_SAXIGP0RDATA8", - "PS7_SAXIGP0RDATA9", - "PS7_SAXIGP0RID0", - "PS7_SAXIGP0RID1", - "PS7_SAXIGP0RID2", - "PS7_SAXIGP0RID3", - "PS7_SAXIGP0RID4", - "PS7_SAXIGP0RID5", - "PS7_SAXIGP0RLAST", - "PS7_SAXIGP0RREADY", - "PS7_SAXIGP0RRESP0", - "PS7_SAXIGP0RRESP1", - "PS7_SAXIGP0RVALID", - "PS7_SAXIGP0WDATA0", - "PS7_SAXIGP0WDATA1", - "PS7_SAXIGP0WDATA10", - "PS7_SAXIGP0WDATA11", - "PS7_SAXIGP0WDATA12", - "PS7_SAXIGP0WDATA13", - "PS7_SAXIGP0WDATA14", - "PS7_SAXIGP0WDATA15", - "PS7_SAXIGP0WDATA16", - "PS7_SAXIGP0WDATA17", - "PS7_SAXIGP0WDATA18", - "PS7_SAXIGP0WDATA19", - "PS7_SAXIGP0WDATA2", - "PS7_SAXIGP0WDATA20", - "PS7_SAXIGP0WDATA21", - "PS7_SAXIGP0WDATA22", - "PS7_SAXIGP0WDATA23", - "PS7_SAXIGP0WDATA24", - "PS7_SAXIGP0WDATA25", - "PS7_SAXIGP0WDATA26", - "PS7_SAXIGP0WDATA27", - "PS7_SAXIGP0WDATA28", - "PS7_SAXIGP0WDATA29", - "PS7_SAXIGP0WDATA3", - "PS7_SAXIGP0WDATA30", - "PS7_SAXIGP0WDATA31", - "PS7_SAXIGP0WDATA4", - "PS7_SAXIGP0WDATA5", - "PS7_SAXIGP0WDATA6", - "PS7_SAXIGP0WDATA7", - "PS7_SAXIGP0WDATA8", - "PS7_SAXIGP0WDATA9", - "PS7_SAXIGP0WID0", - "PS7_SAXIGP0WID1", - "PS7_SAXIGP0WID2", - "PS7_SAXIGP0WID3", - "PS7_SAXIGP0WID4", - "PS7_SAXIGP0WID5", - "PS7_SAXIGP0WLAST", - "PS7_SAXIGP0WREADY", - "PS7_SAXIGP0WSTRB0", - "PS7_SAXIGP0WSTRB1", - "PS7_SAXIGP0WSTRB2", - "PS7_SAXIGP0WSTRB3", - "PS7_SAXIGP0WVALID", - "PS7_SAXIGP1ACLK", - "PS7_SAXIGP1ARADDR0", - "PS7_SAXIGP1ARADDR1", - "PS7_SAXIGP1ARADDR10", - "PS7_SAXIGP1ARADDR11", - "PS7_SAXIGP1ARADDR12", - "PS7_SAXIGP1ARADDR13", - "PS7_SAXIGP1ARADDR14", - "PS7_SAXIGP1ARADDR15", - "PS7_SAXIGP1ARADDR16", - "PS7_SAXIGP1ARADDR17", - "PS7_SAXIGP1ARADDR18", - "PS7_SAXIGP1ARADDR19", - "PS7_SAXIGP1ARADDR2", - "PS7_SAXIGP1ARADDR20", - "PS7_SAXIGP1ARADDR21", - "PS7_SAXIGP1ARADDR22", - "PS7_SAXIGP1ARADDR23", - "PS7_SAXIGP1ARADDR24", - "PS7_SAXIGP1ARADDR25", - "PS7_SAXIGP1ARADDR26", - "PS7_SAXIGP1ARADDR27", - "PS7_SAXIGP1ARADDR28", - "PS7_SAXIGP1ARADDR29", - "PS7_SAXIGP1ARADDR3", - "PS7_SAXIGP1ARADDR30", - "PS7_SAXIGP1ARADDR31", - "PS7_SAXIGP1ARADDR4", - "PS7_SAXIGP1ARADDR5", - "PS7_SAXIGP1ARADDR6", - "PS7_SAXIGP1ARADDR7", - "PS7_SAXIGP1ARADDR8", - "PS7_SAXIGP1ARADDR9", - "PS7_SAXIGP1ARBURST0", - "PS7_SAXIGP1ARBURST1", - "PS7_SAXIGP1ARCACHE0", - "PS7_SAXIGP1ARCACHE1", - "PS7_SAXIGP1ARCACHE2", - "PS7_SAXIGP1ARCACHE3", - "PS7_SAXIGP1ARESETN", - "PS7_SAXIGP1ARID0", - "PS7_SAXIGP1ARID1", - "PS7_SAXIGP1ARID2", - "PS7_SAXIGP1ARID3", - "PS7_SAXIGP1ARID4", - "PS7_SAXIGP1ARID5", - "PS7_SAXIGP1ARLEN0", - "PS7_SAXIGP1ARLEN1", - "PS7_SAXIGP1ARLEN2", - "PS7_SAXIGP1ARLEN3", - "PS7_SAXIGP1ARLOCK0", - "PS7_SAXIGP1ARLOCK1", - "PS7_SAXIGP1ARPROT0", - "PS7_SAXIGP1ARPROT1", - "PS7_SAXIGP1ARPROT2", - "PS7_SAXIGP1ARQOS0", - "PS7_SAXIGP1ARQOS1", - "PS7_SAXIGP1ARQOS2", - "PS7_SAXIGP1ARQOS3", - "PS7_SAXIGP1ARREADY", - "PS7_SAXIGP1ARSIZE0", - "PS7_SAXIGP1ARSIZE1", - "PS7_SAXIGP1ARVALID", - "PS7_SAXIGP1AWADDR0", - "PS7_SAXIGP1AWADDR1", - "PS7_SAXIGP1AWADDR10", - "PS7_SAXIGP1AWADDR11", - "PS7_SAXIGP1AWADDR12", - "PS7_SAXIGP1AWADDR13", - "PS7_SAXIGP1AWADDR14", - "PS7_SAXIGP1AWADDR15", - "PS7_SAXIGP1AWADDR16", - "PS7_SAXIGP1AWADDR17", - "PS7_SAXIGP1AWADDR18", - "PS7_SAXIGP1AWADDR19", - "PS7_SAXIGP1AWADDR2", - "PS7_SAXIGP1AWADDR20", - "PS7_SAXIGP1AWADDR21", - "PS7_SAXIGP1AWADDR22", - "PS7_SAXIGP1AWADDR23", - "PS7_SAXIGP1AWADDR24", - "PS7_SAXIGP1AWADDR25", - "PS7_SAXIGP1AWADDR26", - "PS7_SAXIGP1AWADDR27", - "PS7_SAXIGP1AWADDR28", - "PS7_SAXIGP1AWADDR29", - "PS7_SAXIGP1AWADDR3", - "PS7_SAXIGP1AWADDR30", - "PS7_SAXIGP1AWADDR31", - "PS7_SAXIGP1AWADDR4", - "PS7_SAXIGP1AWADDR5", - "PS7_SAXIGP1AWADDR6", - "PS7_SAXIGP1AWADDR7", - "PS7_SAXIGP1AWADDR8", - "PS7_SAXIGP1AWADDR9", - "PS7_SAXIGP1AWBURST0", - "PS7_SAXIGP1AWBURST1", - "PS7_SAXIGP1AWCACHE0", - "PS7_SAXIGP1AWCACHE1", - "PS7_SAXIGP1AWCACHE2", - "PS7_SAXIGP1AWCACHE3", - "PS7_SAXIGP1AWID0", - "PS7_SAXIGP1AWID1", - "PS7_SAXIGP1AWID2", - "PS7_SAXIGP1AWID3", - "PS7_SAXIGP1AWID4", - "PS7_SAXIGP1AWID5", - "PS7_SAXIGP1AWLEN0", - "PS7_SAXIGP1AWLEN1", - "PS7_SAXIGP1AWLEN2", - "PS7_SAXIGP1AWLEN3", - "PS7_SAXIGP1AWLOCK0", - "PS7_SAXIGP1AWLOCK1", - "PS7_SAXIGP1AWPROT0", - "PS7_SAXIGP1AWPROT1", - "PS7_SAXIGP1AWPROT2", - "PS7_SAXIGP1AWQOS0", - "PS7_SAXIGP1AWQOS1", - "PS7_SAXIGP1AWQOS2", - "PS7_SAXIGP1AWQOS3", - "PS7_SAXIGP1AWREADY", - "PS7_SAXIGP1AWSIZE0", - "PS7_SAXIGP1AWSIZE1", - "PS7_SAXIGP1AWVALID", - "PS7_SAXIGP1BID0", - "PS7_SAXIGP1BID1", - "PS7_SAXIGP1BID2", - "PS7_SAXIGP1BID3", - "PS7_SAXIGP1BID4", - "PS7_SAXIGP1BID5", - "PS7_SAXIGP1BREADY", - "PS7_SAXIGP1BRESP0", - "PS7_SAXIGP1BRESP1", - "PS7_SAXIGP1BVALID", - "PS7_SAXIGP1RDATA0", - "PS7_SAXIGP1RDATA1", - "PS7_SAXIGP1RDATA10", - "PS7_SAXIGP1RDATA11", - "PS7_SAXIGP1RDATA12", - "PS7_SAXIGP1RDATA13", - "PS7_SAXIGP1RDATA14", - "PS7_SAXIGP1RDATA15", - "PS7_SAXIGP1RDATA16", - "PS7_SAXIGP1RDATA17", - "PS7_SAXIGP1RDATA18", - "PS7_SAXIGP1RDATA19", - "PS7_SAXIGP1RDATA2", - "PS7_SAXIGP1RDATA20", - "PS7_SAXIGP1RDATA21", - "PS7_SAXIGP1RDATA22", - "PS7_SAXIGP1RDATA23", - "PS7_SAXIGP1RDATA24", - "PS7_SAXIGP1RDATA25", - "PS7_SAXIGP1RDATA26", - "PS7_SAXIGP1RDATA27", - "PS7_SAXIGP1RDATA28", - "PS7_SAXIGP1RDATA29", - "PS7_SAXIGP1RDATA3", - "PS7_SAXIGP1RDATA30", - "PS7_SAXIGP1RDATA31", - "PS7_SAXIGP1RDATA4", - "PS7_SAXIGP1RDATA5", - "PS7_SAXIGP1RDATA6", - "PS7_SAXIGP1RDATA7", - "PS7_SAXIGP1RDATA8", - "PS7_SAXIGP1RDATA9", - "PS7_SAXIGP1RID0", - "PS7_SAXIGP1RID1", - "PS7_SAXIGP1RID2", - "PS7_SAXIGP1RID3", - "PS7_SAXIGP1RID4", - "PS7_SAXIGP1RID5", - "PS7_SAXIGP1RLAST", - "PS7_SAXIGP1RREADY", - "PS7_SAXIGP1RRESP0", - "PS7_SAXIGP1RRESP1", - "PS7_SAXIGP1RVALID", - "PS7_SAXIGP1WDATA0", - "PS7_SAXIGP1WDATA1", - "PS7_SAXIGP1WDATA10", - "PS7_SAXIGP1WDATA11", - "PS7_SAXIGP1WDATA12", - "PS7_SAXIGP1WDATA13", - "PS7_SAXIGP1WDATA14", - "PS7_SAXIGP1WDATA15", - "PS7_SAXIGP1WDATA16", - "PS7_SAXIGP1WDATA17", - "PS7_SAXIGP1WDATA18", - "PS7_SAXIGP1WDATA19", - "PS7_SAXIGP1WDATA2", - "PS7_SAXIGP1WDATA20", - "PS7_SAXIGP1WDATA21", - "PS7_SAXIGP1WDATA22", - "PS7_SAXIGP1WDATA23", - "PS7_SAXIGP1WDATA24", - "PS7_SAXIGP1WDATA25", - "PS7_SAXIGP1WDATA26", - "PS7_SAXIGP1WDATA27", - "PS7_SAXIGP1WDATA28", - "PS7_SAXIGP1WDATA29", - "PS7_SAXIGP1WDATA3", - "PS7_SAXIGP1WDATA30", - "PS7_SAXIGP1WDATA31", - "PS7_SAXIGP1WDATA4", - "PS7_SAXIGP1WDATA5", - "PS7_SAXIGP1WDATA6", - "PS7_SAXIGP1WDATA7", - "PS7_SAXIGP1WDATA8", - "PS7_SAXIGP1WDATA9", - "PS7_SAXIGP1WID0", - "PS7_SAXIGP1WID1", - "PS7_SAXIGP1WID2", - "PS7_SAXIGP1WID3", - "PS7_SAXIGP1WID4", - "PS7_SAXIGP1WID5", - "PS7_SAXIGP1WLAST", - "PS7_SAXIGP1WREADY", - "PS7_SAXIGP1WSTRB0", - "PS7_SAXIGP1WSTRB1", - "PS7_SAXIGP1WSTRB2", - "PS7_SAXIGP1WSTRB3", - "PS7_SAXIGP1WVALID", - "PS7_SAXIHP0ACLK", - "PS7_SAXIHP0ARADDR0", - "PS7_SAXIHP0ARADDR1", - "PS7_SAXIHP0ARADDR10", - "PS7_SAXIHP0ARADDR11", - "PS7_SAXIHP0ARADDR12", - "PS7_SAXIHP0ARADDR13", - "PS7_SAXIHP0ARADDR14", - "PS7_SAXIHP0ARADDR15", - "PS7_SAXIHP0ARADDR16", - "PS7_SAXIHP0ARADDR17", - "PS7_SAXIHP0ARADDR18", - "PS7_SAXIHP0ARADDR19", - "PS7_SAXIHP0ARADDR2", - "PS7_SAXIHP0ARADDR20", - "PS7_SAXIHP0ARADDR21", - "PS7_SAXIHP0ARADDR22", - "PS7_SAXIHP0ARADDR23", - "PS7_SAXIHP0ARADDR24", - "PS7_SAXIHP0ARADDR25", - "PS7_SAXIHP0ARADDR26", - "PS7_SAXIHP0ARADDR27", - "PS7_SAXIHP0ARADDR28", - "PS7_SAXIHP0ARADDR29", - "PS7_SAXIHP0ARADDR3", - "PS7_SAXIHP0ARADDR30", - "PS7_SAXIHP0ARADDR31", - "PS7_SAXIHP0ARADDR4", - "PS7_SAXIHP0ARADDR5", - "PS7_SAXIHP0ARADDR6", - "PS7_SAXIHP0ARADDR7", - "PS7_SAXIHP0ARADDR8", - "PS7_SAXIHP0ARADDR9", - "PS7_SAXIHP0ARBURST0", - "PS7_SAXIHP0ARBURST1", - "PS7_SAXIHP0ARCACHE0", - "PS7_SAXIHP0ARCACHE1", - "PS7_SAXIHP0ARCACHE2", - "PS7_SAXIHP0ARCACHE3", - "PS7_SAXIHP0ARESETN", - "PS7_SAXIHP0ARID0", - "PS7_SAXIHP0ARID1", - "PS7_SAXIHP0ARID2", - "PS7_SAXIHP0ARID3", - "PS7_SAXIHP0ARID4", - "PS7_SAXIHP0ARID5", - "PS7_SAXIHP0ARLEN0", - "PS7_SAXIHP0ARLEN1", - "PS7_SAXIHP0ARLEN2", - "PS7_SAXIHP0ARLEN3", - "PS7_SAXIHP0ARLOCK0", - "PS7_SAXIHP0ARLOCK1", - "PS7_SAXIHP0ARPROT0", - "PS7_SAXIHP0ARPROT1", - "PS7_SAXIHP0ARPROT2", - "PS7_SAXIHP0ARQOS0", - "PS7_SAXIHP0ARQOS1", - "PS7_SAXIHP0ARQOS2", - "PS7_SAXIHP0ARQOS3", - "PS7_SAXIHP0ARREADY", - "PS7_SAXIHP0ARSIZE0", - "PS7_SAXIHP0ARSIZE1", - "PS7_SAXIHP0ARVALID", - "PS7_SAXIHP0AWADDR0", - "PS7_SAXIHP0AWADDR1", - "PS7_SAXIHP0AWADDR10", - "PS7_SAXIHP0AWADDR11", - "PS7_SAXIHP0AWADDR12", - "PS7_SAXIHP0AWADDR13", - "PS7_SAXIHP0AWADDR14", - "PS7_SAXIHP0AWADDR15", - "PS7_SAXIHP0AWADDR16", - "PS7_SAXIHP0AWADDR17", - "PS7_SAXIHP0AWADDR18", - "PS7_SAXIHP0AWADDR19", - "PS7_SAXIHP0AWADDR2", - "PS7_SAXIHP0AWADDR20", - "PS7_SAXIHP0AWADDR21", - "PS7_SAXIHP0AWADDR22", - "PS7_SAXIHP0AWADDR23", - "PS7_SAXIHP0AWADDR24", - "PS7_SAXIHP0AWADDR25", - "PS7_SAXIHP0AWADDR26", - "PS7_SAXIHP0AWADDR27", - "PS7_SAXIHP0AWADDR28", - "PS7_SAXIHP0AWADDR29", - "PS7_SAXIHP0AWADDR3", - "PS7_SAXIHP0AWADDR30", - "PS7_SAXIHP0AWADDR31", - "PS7_SAXIHP0AWADDR4", - "PS7_SAXIHP0AWADDR5", - "PS7_SAXIHP0AWADDR6", - "PS7_SAXIHP0AWADDR7", - "PS7_SAXIHP0AWADDR8", - "PS7_SAXIHP0AWADDR9", - "PS7_SAXIHP0AWBURST0", - "PS7_SAXIHP0AWBURST1", - "PS7_SAXIHP0AWCACHE0", - "PS7_SAXIHP0AWCACHE1", - "PS7_SAXIHP0AWCACHE2", - "PS7_SAXIHP0AWCACHE3", - "PS7_SAXIHP0AWID0", - "PS7_SAXIHP0AWID1", - "PS7_SAXIHP0AWID2", - "PS7_SAXIHP0AWID3", - "PS7_SAXIHP0AWID4", - "PS7_SAXIHP0AWID5", - "PS7_SAXIHP0AWLEN0", - "PS7_SAXIHP0AWLEN1", - "PS7_SAXIHP0AWLEN2", - "PS7_SAXIHP0AWLEN3", - "PS7_SAXIHP0AWLOCK0", - "PS7_SAXIHP0AWLOCK1", - "PS7_SAXIHP0AWPROT0", - "PS7_SAXIHP0AWPROT1", - "PS7_SAXIHP0AWPROT2", - "PS7_SAXIHP0AWQOS0", - "PS7_SAXIHP0AWQOS1", - "PS7_SAXIHP0AWQOS2", - "PS7_SAXIHP0AWQOS3", - "PS7_SAXIHP0AWREADY", - "PS7_SAXIHP0AWSIZE0", - "PS7_SAXIHP0AWSIZE1", - "PS7_SAXIHP0AWVALID", - "PS7_SAXIHP0BID0", - "PS7_SAXIHP0BID1", - "PS7_SAXIHP0BID2", - "PS7_SAXIHP0BID3", - "PS7_SAXIHP0BID4", - "PS7_SAXIHP0BID5", - "PS7_SAXIHP0BREADY", - "PS7_SAXIHP0BRESP0", - "PS7_SAXIHP0BRESP1", - "PS7_SAXIHP0BVALID", - "PS7_SAXIHP0RACOUNT0", - "PS7_SAXIHP0RACOUNT1", - "PS7_SAXIHP0RACOUNT2", - "PS7_SAXIHP0RCOUNT0", - "PS7_SAXIHP0RCOUNT1", - "PS7_SAXIHP0RCOUNT2", - "PS7_SAXIHP0RCOUNT3", - "PS7_SAXIHP0RCOUNT4", - "PS7_SAXIHP0RCOUNT5", - "PS7_SAXIHP0RCOUNT6", - "PS7_SAXIHP0RCOUNT7", - "PS7_SAXIHP0RDATA0", - "PS7_SAXIHP0RDATA1", - "PS7_SAXIHP0RDATA10", - "PS7_SAXIHP0RDATA11", - "PS7_SAXIHP0RDATA12", - "PS7_SAXIHP0RDATA13", - "PS7_SAXIHP0RDATA14", - "PS7_SAXIHP0RDATA15", - "PS7_SAXIHP0RDATA16", - "PS7_SAXIHP0RDATA17", - "PS7_SAXIHP0RDATA18", - "PS7_SAXIHP0RDATA19", - "PS7_SAXIHP0RDATA2", - "PS7_SAXIHP0RDATA20", - "PS7_SAXIHP0RDATA21", - "PS7_SAXIHP0RDATA22", - "PS7_SAXIHP0RDATA23", - "PS7_SAXIHP0RDATA24", - "PS7_SAXIHP0RDATA25", - "PS7_SAXIHP0RDATA26", - "PS7_SAXIHP0RDATA27", - "PS7_SAXIHP0RDATA28", - "PS7_SAXIHP0RDATA29", - "PS7_SAXIHP0RDATA3", - "PS7_SAXIHP0RDATA30", - "PS7_SAXIHP0RDATA31", - "PS7_SAXIHP0RDATA32", - "PS7_SAXIHP0RDATA33", - "PS7_SAXIHP0RDATA34", - "PS7_SAXIHP0RDATA35", - "PS7_SAXIHP0RDATA36", - "PS7_SAXIHP0RDATA37", - "PS7_SAXIHP0RDATA38", - "PS7_SAXIHP0RDATA39", - "PS7_SAXIHP0RDATA4", - "PS7_SAXIHP0RDATA40", - "PS7_SAXIHP0RDATA41", - "PS7_SAXIHP0RDATA42", - "PS7_SAXIHP0RDATA43", - "PS7_SAXIHP0RDATA44", - "PS7_SAXIHP0RDATA45", - "PS7_SAXIHP0RDATA46", - "PS7_SAXIHP0RDATA47", - "PS7_SAXIHP0RDATA48", - "PS7_SAXIHP0RDATA49", - "PS7_SAXIHP0RDATA5", - "PS7_SAXIHP0RDATA50", - "PS7_SAXIHP0RDATA51", - "PS7_SAXIHP0RDATA52", - "PS7_SAXIHP0RDATA53", - "PS7_SAXIHP0RDATA54", - "PS7_SAXIHP0RDATA55", - "PS7_SAXIHP0RDATA56", - "PS7_SAXIHP0RDATA57", - "PS7_SAXIHP0RDATA58", - "PS7_SAXIHP0RDATA59", - "PS7_SAXIHP0RDATA6", - "PS7_SAXIHP0RDATA60", - "PS7_SAXIHP0RDATA61", - "PS7_SAXIHP0RDATA62", - "PS7_SAXIHP0RDATA63", - "PS7_SAXIHP0RDATA7", - "PS7_SAXIHP0RDATA8", - "PS7_SAXIHP0RDATA9", - "PS7_SAXIHP0RDISSUECAP1EN", - "PS7_SAXIHP0RID0", - "PS7_SAXIHP0RID1", - "PS7_SAXIHP0RID2", - "PS7_SAXIHP0RID3", - "PS7_SAXIHP0RID4", - "PS7_SAXIHP0RID5", - "PS7_SAXIHP0RLAST", - "PS7_SAXIHP0RREADY", - "PS7_SAXIHP0RRESP0", - "PS7_SAXIHP0RRESP1", - "PS7_SAXIHP0RVALID", - "PS7_SAXIHP0WACOUNT0", - "PS7_SAXIHP0WACOUNT1", - "PS7_SAXIHP0WACOUNT2", - "PS7_SAXIHP0WACOUNT3", - "PS7_SAXIHP0WACOUNT4", - "PS7_SAXIHP0WACOUNT5", - "PS7_SAXIHP0WCOUNT0", - "PS7_SAXIHP0WCOUNT1", - "PS7_SAXIHP0WCOUNT2", - "PS7_SAXIHP0WCOUNT3", - "PS7_SAXIHP0WCOUNT4", - "PS7_SAXIHP0WCOUNT5", - "PS7_SAXIHP0WCOUNT6", - "PS7_SAXIHP0WCOUNT7", - "PS7_SAXIHP0WDATA0", - "PS7_SAXIHP0WDATA1", - "PS7_SAXIHP0WDATA10", - "PS7_SAXIHP0WDATA11", - "PS7_SAXIHP0WDATA12", - "PS7_SAXIHP0WDATA13", - "PS7_SAXIHP0WDATA14", - "PS7_SAXIHP0WDATA15", - "PS7_SAXIHP0WDATA16", - "PS7_SAXIHP0WDATA17", - "PS7_SAXIHP0WDATA18", - "PS7_SAXIHP0WDATA19", - "PS7_SAXIHP0WDATA2", - "PS7_SAXIHP0WDATA20", - "PS7_SAXIHP0WDATA21", - "PS7_SAXIHP0WDATA22", - "PS7_SAXIHP0WDATA23", - "PS7_SAXIHP0WDATA24", - "PS7_SAXIHP0WDATA25", - "PS7_SAXIHP0WDATA26", - "PS7_SAXIHP0WDATA27", - "PS7_SAXIHP0WDATA28", - "PS7_SAXIHP0WDATA29", - "PS7_SAXIHP0WDATA3", - "PS7_SAXIHP0WDATA30", - "PS7_SAXIHP0WDATA31", - "PS7_SAXIHP0WDATA32", - "PS7_SAXIHP0WDATA33", - "PS7_SAXIHP0WDATA34", - "PS7_SAXIHP0WDATA35", - "PS7_SAXIHP0WDATA36", - "PS7_SAXIHP0WDATA37", - "PS7_SAXIHP0WDATA38", - "PS7_SAXIHP0WDATA39", - "PS7_SAXIHP0WDATA4", - "PS7_SAXIHP0WDATA40", - "PS7_SAXIHP0WDATA41", - "PS7_SAXIHP0WDATA42", - "PS7_SAXIHP0WDATA43", - "PS7_SAXIHP0WDATA44", - "PS7_SAXIHP0WDATA45", - "PS7_SAXIHP0WDATA46", - "PS7_SAXIHP0WDATA47", - "PS7_SAXIHP0WDATA48", - "PS7_SAXIHP0WDATA49", - "PS7_SAXIHP0WDATA5", - "PS7_SAXIHP0WDATA50", - "PS7_SAXIHP0WDATA51", - "PS7_SAXIHP0WDATA52", - "PS7_SAXIHP0WDATA53", - "PS7_SAXIHP0WDATA54", - "PS7_SAXIHP0WDATA55", - "PS7_SAXIHP0WDATA56", - "PS7_SAXIHP0WDATA57", - "PS7_SAXIHP0WDATA58", - "PS7_SAXIHP0WDATA59", - "PS7_SAXIHP0WDATA6", - "PS7_SAXIHP0WDATA60", - "PS7_SAXIHP0WDATA61", - "PS7_SAXIHP0WDATA62", - "PS7_SAXIHP0WDATA63", - "PS7_SAXIHP0WDATA7", - "PS7_SAXIHP0WDATA8", - "PS7_SAXIHP0WDATA9", - "PS7_SAXIHP0WID0", - "PS7_SAXIHP0WID1", - "PS7_SAXIHP0WID2", - "PS7_SAXIHP0WID3", - "PS7_SAXIHP0WID4", - "PS7_SAXIHP0WID5", - "PS7_SAXIHP0WLAST", - "PS7_SAXIHP0WREADY", - "PS7_SAXIHP0WRISSUECAP1EN", - "PS7_SAXIHP0WSTRB0", - "PS7_SAXIHP0WSTRB1", - "PS7_SAXIHP0WSTRB2", - "PS7_SAXIHP0WSTRB3", - "PS7_SAXIHP0WSTRB4", - "PS7_SAXIHP0WSTRB5", - "PS7_SAXIHP0WSTRB6", - "PS7_SAXIHP0WSTRB7", - "PS7_SAXIHP0WVALID", - "PS7_SAXIHP1ACLK", - "PS7_SAXIHP1ARADDR0", - "PS7_SAXIHP1ARADDR1", - "PS7_SAXIHP1ARADDR10", - "PS7_SAXIHP1ARADDR11", - "PS7_SAXIHP1ARADDR12", - "PS7_SAXIHP1ARADDR13", - "PS7_SAXIHP1ARADDR14", - "PS7_SAXIHP1ARADDR15", - "PS7_SAXIHP1ARADDR16", - "PS7_SAXIHP1ARADDR17", - "PS7_SAXIHP1ARADDR18", - "PS7_SAXIHP1ARADDR19", - "PS7_SAXIHP1ARADDR2", - "PS7_SAXIHP1ARADDR20", - "PS7_SAXIHP1ARADDR21", - "PS7_SAXIHP1ARADDR22", - "PS7_SAXIHP1ARADDR23", - "PS7_SAXIHP1ARADDR24", - "PS7_SAXIHP1ARADDR25", - "PS7_SAXIHP1ARADDR26", - "PS7_SAXIHP1ARADDR27", - "PS7_SAXIHP1ARADDR28", - "PS7_SAXIHP1ARADDR29", - "PS7_SAXIHP1ARADDR3", - "PS7_SAXIHP1ARADDR30", - "PS7_SAXIHP1ARADDR31", - "PS7_SAXIHP1ARADDR4", - "PS7_SAXIHP1ARADDR5", - "PS7_SAXIHP1ARADDR6", - "PS7_SAXIHP1ARADDR7", - "PS7_SAXIHP1ARADDR8", - "PS7_SAXIHP1ARADDR9", - "PS7_SAXIHP1ARBURST0", - "PS7_SAXIHP1ARBURST1", - "PS7_SAXIHP1ARCACHE0", - "PS7_SAXIHP1ARCACHE1", - "PS7_SAXIHP1ARCACHE2", - "PS7_SAXIHP1ARCACHE3", - "PS7_SAXIHP1ARESETN", - "PS7_SAXIHP1ARID0", - "PS7_SAXIHP1ARID1", - "PS7_SAXIHP1ARID2", - "PS7_SAXIHP1ARID3", - "PS7_SAXIHP1ARID4", - "PS7_SAXIHP1ARID5", - "PS7_SAXIHP1ARLEN0", - "PS7_SAXIHP1ARLEN1", - "PS7_SAXIHP1ARLEN2", - "PS7_SAXIHP1ARLEN3", - "PS7_SAXIHP1ARLOCK0", - "PS7_SAXIHP1ARLOCK1", - "PS7_SAXIHP1ARPROT0", - "PS7_SAXIHP1ARPROT1", - "PS7_SAXIHP1ARPROT2", - "PS7_SAXIHP1ARQOS0", - "PS7_SAXIHP1ARQOS1", - "PS7_SAXIHP1ARQOS2", - "PS7_SAXIHP1ARQOS3", - "PS7_SAXIHP1ARREADY", - "PS7_SAXIHP1ARSIZE0", - "PS7_SAXIHP1ARSIZE1", - "PS7_SAXIHP1ARVALID", - "PS7_SAXIHP1AWADDR0", - "PS7_SAXIHP1AWADDR1", - "PS7_SAXIHP1AWADDR10", - "PS7_SAXIHP1AWADDR11", - "PS7_SAXIHP1AWADDR12", - "PS7_SAXIHP1AWADDR13", - "PS7_SAXIHP1AWADDR14", - "PS7_SAXIHP1AWADDR15", - "PS7_SAXIHP1AWADDR16", - "PS7_SAXIHP1AWADDR17", - "PS7_SAXIHP1AWADDR18", - "PS7_SAXIHP1AWADDR19", - "PS7_SAXIHP1AWADDR2", - "PS7_SAXIHP1AWADDR20", - "PS7_SAXIHP1AWADDR21", - "PS7_SAXIHP1AWADDR22", - "PS7_SAXIHP1AWADDR23", - "PS7_SAXIHP1AWADDR24", - "PS7_SAXIHP1AWADDR25", - "PS7_SAXIHP1AWADDR26", - "PS7_SAXIHP1AWADDR27", - "PS7_SAXIHP1AWADDR28", - "PS7_SAXIHP1AWADDR29", - "PS7_SAXIHP1AWADDR3", - "PS7_SAXIHP1AWADDR30", - "PS7_SAXIHP1AWADDR31", - "PS7_SAXIHP1AWADDR4", - "PS7_SAXIHP1AWADDR5", - "PS7_SAXIHP1AWADDR6", - "PS7_SAXIHP1AWADDR7", - "PS7_SAXIHP1AWADDR8", - "PS7_SAXIHP1AWADDR9", - "PS7_SAXIHP1AWBURST0", - "PS7_SAXIHP1AWBURST1", - "PS7_SAXIHP1AWCACHE0", - "PS7_SAXIHP1AWCACHE1", - "PS7_SAXIHP1AWCACHE2", - "PS7_SAXIHP1AWCACHE3", - "PS7_SAXIHP1AWID0", - "PS7_SAXIHP1AWID1", - "PS7_SAXIHP1AWID2", - "PS7_SAXIHP1AWID3", - "PS7_SAXIHP1AWID4", - "PS7_SAXIHP1AWID5", - "PS7_SAXIHP1AWLEN0", - "PS7_SAXIHP1AWLEN1", - "PS7_SAXIHP1AWLEN2", - "PS7_SAXIHP1AWLEN3", - "PS7_SAXIHP1AWLOCK0", - "PS7_SAXIHP1AWLOCK1", - "PS7_SAXIHP1AWPROT0", - "PS7_SAXIHP1AWPROT1", - "PS7_SAXIHP1AWPROT2", - "PS7_SAXIHP1AWQOS0", - "PS7_SAXIHP1AWQOS1", - "PS7_SAXIHP1AWQOS2", - "PS7_SAXIHP1AWQOS3", - "PS7_SAXIHP1AWREADY", - "PS7_SAXIHP1AWSIZE0", - "PS7_SAXIHP1AWSIZE1", - "PS7_SAXIHP1AWVALID", - "PS7_SAXIHP1BID0", - "PS7_SAXIHP1BID1", - "PS7_SAXIHP1BID2", - "PS7_SAXIHP1BID3", - "PS7_SAXIHP1BID4", - "PS7_SAXIHP1BID5", - "PS7_SAXIHP1BREADY", - "PS7_SAXIHP1BRESP0", - "PS7_SAXIHP1BRESP1", - "PS7_SAXIHP1BVALID", - "PS7_SAXIHP1RACOUNT0", - "PS7_SAXIHP1RACOUNT1", - "PS7_SAXIHP1RACOUNT2", - "PS7_SAXIHP1RCOUNT0", - "PS7_SAXIHP1RCOUNT1", - "PS7_SAXIHP1RCOUNT2", - "PS7_SAXIHP1RCOUNT3", - "PS7_SAXIHP1RCOUNT4", - "PS7_SAXIHP1RCOUNT5", - "PS7_SAXIHP1RCOUNT6", - "PS7_SAXIHP1RCOUNT7", - "PS7_SAXIHP1RDATA0", - "PS7_SAXIHP1RDATA1", - "PS7_SAXIHP1RDATA10", - "PS7_SAXIHP1RDATA11", - "PS7_SAXIHP1RDATA12", - "PS7_SAXIHP1RDATA13", - "PS7_SAXIHP1RDATA14", - "PS7_SAXIHP1RDATA15", - "PS7_SAXIHP1RDATA16", - "PS7_SAXIHP1RDATA17", - "PS7_SAXIHP1RDATA18", - "PS7_SAXIHP1RDATA19", - "PS7_SAXIHP1RDATA2", - "PS7_SAXIHP1RDATA20", - "PS7_SAXIHP1RDATA21", - "PS7_SAXIHP1RDATA22", - "PS7_SAXIHP1RDATA23", - "PS7_SAXIHP1RDATA24", - "PS7_SAXIHP1RDATA25", - "PS7_SAXIHP1RDATA26", - "PS7_SAXIHP1RDATA27", - "PS7_SAXIHP1RDATA28", - "PS7_SAXIHP1RDATA29", - "PS7_SAXIHP1RDATA3", - "PS7_SAXIHP1RDATA30", - "PS7_SAXIHP1RDATA31", - "PS7_SAXIHP1RDATA32", - "PS7_SAXIHP1RDATA33", - "PS7_SAXIHP1RDATA34", - "PS7_SAXIHP1RDATA35", - "PS7_SAXIHP1RDATA36", - "PS7_SAXIHP1RDATA37", - "PS7_SAXIHP1RDATA38", - "PS7_SAXIHP1RDATA39", - "PS7_SAXIHP1RDATA4", - "PS7_SAXIHP1RDATA40", - "PS7_SAXIHP1RDATA41", - "PS7_SAXIHP1RDATA42", - "PS7_SAXIHP1RDATA43", - "PS7_SAXIHP1RDATA44", - "PS7_SAXIHP1RDATA45", - "PS7_SAXIHP1RDATA46", - "PS7_SAXIHP1RDATA47", - "PS7_SAXIHP1RDATA48", - "PS7_SAXIHP1RDATA49", - "PS7_SAXIHP1RDATA5", - "PS7_SAXIHP1RDATA50", - "PS7_SAXIHP1RDATA51", - "PS7_SAXIHP1RDATA52", - "PS7_SAXIHP1RDATA53", - "PS7_SAXIHP1RDATA54", - "PS7_SAXIHP1RDATA55", - "PS7_SAXIHP1RDATA56", - "PS7_SAXIHP1RDATA57", - "PS7_SAXIHP1RDATA58", - "PS7_SAXIHP1RDATA59", - "PS7_SAXIHP1RDATA6", - "PS7_SAXIHP1RDATA60", - "PS7_SAXIHP1RDATA61", - "PS7_SAXIHP1RDATA62", - "PS7_SAXIHP1RDATA63", - "PS7_SAXIHP1RDATA7", - "PS7_SAXIHP1RDATA8", - "PS7_SAXIHP1RDATA9", - "PS7_SAXIHP1RDISSUECAP1EN", - "PS7_SAXIHP1RID0", - "PS7_SAXIHP1RID1", - "PS7_SAXIHP1RID2", - "PS7_SAXIHP1RID3", - "PS7_SAXIHP1RID4", - "PS7_SAXIHP1RID5", - "PS7_SAXIHP1RLAST", - "PS7_SAXIHP1RREADY", - "PS7_SAXIHP1RRESP0", - "PS7_SAXIHP1RRESP1", - "PS7_SAXIHP1RVALID", - "PS7_SAXIHP1WACOUNT0", - "PS7_SAXIHP1WACOUNT1", - "PS7_SAXIHP1WACOUNT2", - "PS7_SAXIHP1WACOUNT3", - "PS7_SAXIHP1WACOUNT4", - "PS7_SAXIHP1WACOUNT5", - "PS7_SAXIHP1WCOUNT0", - "PS7_SAXIHP1WCOUNT1", - "PS7_SAXIHP1WCOUNT2", - "PS7_SAXIHP1WCOUNT3", - "PS7_SAXIHP1WCOUNT4", - "PS7_SAXIHP1WCOUNT5", - "PS7_SAXIHP1WCOUNT6", - "PS7_SAXIHP1WCOUNT7", - "PS7_SAXIHP1WDATA0", - "PS7_SAXIHP1WDATA1", - "PS7_SAXIHP1WDATA10", - "PS7_SAXIHP1WDATA11", - "PS7_SAXIHP1WDATA12", - "PS7_SAXIHP1WDATA13", - "PS7_SAXIHP1WDATA14", - "PS7_SAXIHP1WDATA15", - "PS7_SAXIHP1WDATA16", - "PS7_SAXIHP1WDATA17", - "PS7_SAXIHP1WDATA18", - "PS7_SAXIHP1WDATA19", - "PS7_SAXIHP1WDATA2", - "PS7_SAXIHP1WDATA20", - "PS7_SAXIHP1WDATA21", - "PS7_SAXIHP1WDATA22", - "PS7_SAXIHP1WDATA23", - "PS7_SAXIHP1WDATA24", - "PS7_SAXIHP1WDATA25", - "PS7_SAXIHP1WDATA26", - "PS7_SAXIHP1WDATA27", - "PS7_SAXIHP1WDATA28", - "PS7_SAXIHP1WDATA29", - "PS7_SAXIHP1WDATA3", - "PS7_SAXIHP1WDATA30", - "PS7_SAXIHP1WDATA31", - "PS7_SAXIHP1WDATA32", - "PS7_SAXIHP1WDATA33", - "PS7_SAXIHP1WDATA34", - "PS7_SAXIHP1WDATA35", - "PS7_SAXIHP1WDATA36", - "PS7_SAXIHP1WDATA37", - "PS7_SAXIHP1WDATA38", - "PS7_SAXIHP1WDATA39", - "PS7_SAXIHP1WDATA4", - "PS7_SAXIHP1WDATA40", - "PS7_SAXIHP1WDATA41", - "PS7_SAXIHP1WDATA42", - "PS7_SAXIHP1WDATA43", - "PS7_SAXIHP1WDATA44", - "PS7_SAXIHP1WDATA45", - "PS7_SAXIHP1WDATA46", - "PS7_SAXIHP1WDATA47", - "PS7_SAXIHP1WDATA48", - "PS7_SAXIHP1WDATA49", - "PS7_SAXIHP1WDATA5", - "PS7_SAXIHP1WDATA50", - "PS7_SAXIHP1WDATA51", - "PS7_SAXIHP1WDATA52", - "PS7_SAXIHP1WDATA53", - "PS7_SAXIHP1WDATA54", - "PS7_SAXIHP1WDATA55", - "PS7_SAXIHP1WDATA56", - "PS7_SAXIHP1WDATA57", - "PS7_SAXIHP1WDATA58", - "PS7_SAXIHP1WDATA59", - "PS7_SAXIHP1WDATA6", - "PS7_SAXIHP1WDATA60", - "PS7_SAXIHP1WDATA61", - "PS7_SAXIHP1WDATA62", - "PS7_SAXIHP1WDATA63", - "PS7_SAXIHP1WDATA7", - "PS7_SAXIHP1WDATA8", - "PS7_SAXIHP1WDATA9", - "PS7_SAXIHP1WID0", - "PS7_SAXIHP1WID1", - "PS7_SAXIHP1WID2", - "PS7_SAXIHP1WID3", - "PS7_SAXIHP1WID4", - "PS7_SAXIHP1WID5", - "PS7_SAXIHP1WLAST", - "PS7_SAXIHP1WREADY", - "PS7_SAXIHP1WRISSUECAP1EN", - "PS7_SAXIHP1WSTRB0", - "PS7_SAXIHP1WSTRB1", - "PS7_SAXIHP1WSTRB2", - "PS7_SAXIHP1WSTRB3", - "PS7_SAXIHP1WSTRB4", - "PS7_SAXIHP1WSTRB5", - "PS7_SAXIHP1WSTRB6", - "PS7_SAXIHP1WSTRB7", - "PS7_SAXIHP1WVALID", - "PS7_SAXIHP2ACLK", - "PS7_SAXIHP2ARADDR0", - "PS7_SAXIHP2ARADDR1", - "PS7_SAXIHP2ARADDR10", - "PS7_SAXIHP2ARADDR11", - "PS7_SAXIHP2ARADDR12", - "PS7_SAXIHP2ARADDR13", - "PS7_SAXIHP2ARADDR14", - "PS7_SAXIHP2ARADDR15", - "PS7_SAXIHP2ARADDR16", - "PS7_SAXIHP2ARADDR17", - "PS7_SAXIHP2ARADDR18", - "PS7_SAXIHP2ARADDR19", - "PS7_SAXIHP2ARADDR2", - "PS7_SAXIHP2ARADDR20", - "PS7_SAXIHP2ARADDR21", - "PS7_SAXIHP2ARADDR22", - "PS7_SAXIHP2ARADDR23", - "PS7_SAXIHP2ARADDR24", - "PS7_SAXIHP2ARADDR25", - "PS7_SAXIHP2ARADDR26", - "PS7_SAXIHP2ARADDR27", - "PS7_SAXIHP2ARADDR28", - "PS7_SAXIHP2ARADDR29", - "PS7_SAXIHP2ARADDR3", - "PS7_SAXIHP2ARADDR30", - "PS7_SAXIHP2ARADDR31", - "PS7_SAXIHP2ARADDR4", - "PS7_SAXIHP2ARADDR5", - "PS7_SAXIHP2ARADDR6", - "PS7_SAXIHP2ARADDR7", - "PS7_SAXIHP2ARADDR8", - "PS7_SAXIHP2ARADDR9", - "PS7_SAXIHP2ARBURST0", - "PS7_SAXIHP2ARBURST1", - "PS7_SAXIHP2ARCACHE0", - "PS7_SAXIHP2ARCACHE1", - "PS7_SAXIHP2ARCACHE2", - "PS7_SAXIHP2ARCACHE3", - "PS7_SAXIHP2ARESETN", - "PS7_SAXIHP2ARID0", - "PS7_SAXIHP2ARID1", - "PS7_SAXIHP2ARID2", - "PS7_SAXIHP2ARID3", - "PS7_SAXIHP2ARID4", - "PS7_SAXIHP2ARID5", - "PS7_SAXIHP2ARLEN0", - "PS7_SAXIHP2ARLEN1", - "PS7_SAXIHP2ARLEN2", - "PS7_SAXIHP2ARLEN3", - "PS7_SAXIHP2ARLOCK0", - "PS7_SAXIHP2ARLOCK1", - "PS7_SAXIHP2ARPROT0", - "PS7_SAXIHP2ARPROT1", - "PS7_SAXIHP2ARPROT2", - "PS7_SAXIHP2ARQOS0", - "PS7_SAXIHP2ARQOS1", - "PS7_SAXIHP2ARQOS2", - "PS7_SAXIHP2ARQOS3", - "PS7_SAXIHP2ARREADY", - "PS7_SAXIHP2ARSIZE0", - "PS7_SAXIHP2ARSIZE1", - "PS7_SAXIHP2ARVALID", - "PS7_SAXIHP2AWADDR0", - "PS7_SAXIHP2AWADDR1", - "PS7_SAXIHP2AWADDR10", - "PS7_SAXIHP2AWADDR11", - "PS7_SAXIHP2AWADDR12", - "PS7_SAXIHP2AWADDR13", - "PS7_SAXIHP2AWADDR14", - "PS7_SAXIHP2AWADDR15", - "PS7_SAXIHP2AWADDR16", - "PS7_SAXIHP2AWADDR17", - "PS7_SAXIHP2AWADDR18", - "PS7_SAXIHP2AWADDR19", - "PS7_SAXIHP2AWADDR2", - "PS7_SAXIHP2AWADDR20", - "PS7_SAXIHP2AWADDR21", - "PS7_SAXIHP2AWADDR22", - "PS7_SAXIHP2AWADDR23", - "PS7_SAXIHP2AWADDR24", - "PS7_SAXIHP2AWADDR25", - "PS7_SAXIHP2AWADDR26", - "PS7_SAXIHP2AWADDR27", - "PS7_SAXIHP2AWADDR28", - "PS7_SAXIHP2AWADDR29", - "PS7_SAXIHP2AWADDR3", - "PS7_SAXIHP2AWADDR30", - "PS7_SAXIHP2AWADDR31", - "PS7_SAXIHP2AWADDR4", - "PS7_SAXIHP2AWADDR5", - "PS7_SAXIHP2AWADDR6", - "PS7_SAXIHP2AWADDR7", - "PS7_SAXIHP2AWADDR8", - "PS7_SAXIHP2AWADDR9", - "PS7_SAXIHP2AWBURST0", - "PS7_SAXIHP2AWBURST1", - "PS7_SAXIHP2AWCACHE0", - "PS7_SAXIHP2AWCACHE1", - "PS7_SAXIHP2AWCACHE2", - "PS7_SAXIHP2AWCACHE3", - "PS7_SAXIHP2AWID0", - "PS7_SAXIHP2AWID1", - "PS7_SAXIHP2AWID2", - "PS7_SAXIHP2AWID3", - "PS7_SAXIHP2AWID4", - "PS7_SAXIHP2AWID5", - "PS7_SAXIHP2AWLEN0", - "PS7_SAXIHP2AWLEN1", - "PS7_SAXIHP2AWLEN2", - "PS7_SAXIHP2AWLEN3", - "PS7_SAXIHP2AWLOCK0", - "PS7_SAXIHP2AWLOCK1", - "PS7_SAXIHP2AWPROT0", - "PS7_SAXIHP2AWPROT1", - "PS7_SAXIHP2AWPROT2", - "PS7_SAXIHP2AWQOS0", - "PS7_SAXIHP2AWQOS1", - "PS7_SAXIHP2AWQOS2", - "PS7_SAXIHP2AWQOS3", - "PS7_SAXIHP2AWREADY", - "PS7_SAXIHP2AWSIZE0", - "PS7_SAXIHP2AWSIZE1", - "PS7_SAXIHP2AWVALID", - "PS7_SAXIHP2BID0", - "PS7_SAXIHP2BID1", - "PS7_SAXIHP2BID2", - "PS7_SAXIHP2BID3", - "PS7_SAXIHP2BID4", - "PS7_SAXIHP2BID5", - "PS7_SAXIHP2BREADY", - "PS7_SAXIHP2BRESP0", - "PS7_SAXIHP2BRESP1", - "PS7_SAXIHP2BVALID", - "PS7_SAXIHP2RACOUNT0", - "PS7_SAXIHP2RACOUNT1", - "PS7_SAXIHP2RACOUNT2", - "PS7_SAXIHP2RCOUNT0", - "PS7_SAXIHP2RCOUNT1", - "PS7_SAXIHP2RCOUNT2", - "PS7_SAXIHP2RCOUNT3", - "PS7_SAXIHP2RCOUNT4", - "PS7_SAXIHP2RCOUNT5", - "PS7_SAXIHP2RCOUNT6", - "PS7_SAXIHP2RCOUNT7", - "PS7_SAXIHP2RDATA0", - "PS7_SAXIHP2RDATA1", - "PS7_SAXIHP2RDATA10", - "PS7_SAXIHP2RDATA11", - "PS7_SAXIHP2RDATA12", - "PS7_SAXIHP2RDATA13", - "PS7_SAXIHP2RDATA14", - "PS7_SAXIHP2RDATA15", - "PS7_SAXIHP2RDATA16", - "PS7_SAXIHP2RDATA17", - "PS7_SAXIHP2RDATA18", - "PS7_SAXIHP2RDATA19", - "PS7_SAXIHP2RDATA2", - "PS7_SAXIHP2RDATA20", - "PS7_SAXIHP2RDATA21", - "PS7_SAXIHP2RDATA22", - "PS7_SAXIHP2RDATA23", - "PS7_SAXIHP2RDATA24", - "PS7_SAXIHP2RDATA25", - "PS7_SAXIHP2RDATA26", - "PS7_SAXIHP2RDATA27", - "PS7_SAXIHP2RDATA28", - "PS7_SAXIHP2RDATA29", - "PS7_SAXIHP2RDATA3", - "PS7_SAXIHP2RDATA30", - "PS7_SAXIHP2RDATA31", - "PS7_SAXIHP2RDATA32", - "PS7_SAXIHP2RDATA33", - "PS7_SAXIHP2RDATA34", - "PS7_SAXIHP2RDATA35", - "PS7_SAXIHP2RDATA36", - "PS7_SAXIHP2RDATA37", - "PS7_SAXIHP2RDATA38", - "PS7_SAXIHP2RDATA39", - "PS7_SAXIHP2RDATA4", - "PS7_SAXIHP2RDATA40", - "PS7_SAXIHP2RDATA41", - "PS7_SAXIHP2RDATA42", - "PS7_SAXIHP2RDATA43", - "PS7_SAXIHP2RDATA44", - "PS7_SAXIHP2RDATA45", - "PS7_SAXIHP2RDATA46", - "PS7_SAXIHP2RDATA47", - "PS7_SAXIHP2RDATA48", - "PS7_SAXIHP2RDATA49", - "PS7_SAXIHP2RDATA5", - "PS7_SAXIHP2RDATA50", - "PS7_SAXIHP2RDATA51", - "PS7_SAXIHP2RDATA52", - "PS7_SAXIHP2RDATA53", - "PS7_SAXIHP2RDATA54", - "PS7_SAXIHP2RDATA55", - "PS7_SAXIHP2RDATA56", - "PS7_SAXIHP2RDATA57", - "PS7_SAXIHP2RDATA58", - "PS7_SAXIHP2RDATA59", - "PS7_SAXIHP2RDATA6", - "PS7_SAXIHP2RDATA60", - "PS7_SAXIHP2RDATA61", - "PS7_SAXIHP2RDATA62", - "PS7_SAXIHP2RDATA63", - "PS7_SAXIHP2RDATA7", - "PS7_SAXIHP2RDATA8", - "PS7_SAXIHP2RDATA9", - "PS7_SAXIHP2RDISSUECAP1EN", - "PS7_SAXIHP2RID0", - "PS7_SAXIHP2RID1", - "PS7_SAXIHP2RID2", - "PS7_SAXIHP2RID3", - "PS7_SAXIHP2RID4", - "PS7_SAXIHP2RID5", - "PS7_SAXIHP2RLAST", - "PS7_SAXIHP2RREADY", - "PS7_SAXIHP2RRESP0", - "PS7_SAXIHP2RRESP1", - "PS7_SAXIHP2RVALID", - "PS7_SAXIHP2WACOUNT0", - "PS7_SAXIHP2WACOUNT1", - "PS7_SAXIHP2WACOUNT2", - "PS7_SAXIHP2WACOUNT3", - "PS7_SAXIHP2WACOUNT4", - "PS7_SAXIHP2WACOUNT5", - "PS7_SAXIHP2WCOUNT0", - "PS7_SAXIHP2WCOUNT1", - "PS7_SAXIHP2WCOUNT2", - "PS7_SAXIHP2WCOUNT3", - "PS7_SAXIHP2WCOUNT4", - "PS7_SAXIHP2WCOUNT5", - "PS7_SAXIHP2WCOUNT6", - "PS7_SAXIHP2WCOUNT7", - "PS7_SAXIHP2WDATA0", - "PS7_SAXIHP2WDATA1", - "PS7_SAXIHP2WDATA10", - "PS7_SAXIHP2WDATA11", - "PS7_SAXIHP2WDATA12", - "PS7_SAXIHP2WDATA13", - "PS7_SAXIHP2WDATA14", - "PS7_SAXIHP2WDATA15", - "PS7_SAXIHP2WDATA16", - "PS7_SAXIHP2WDATA17", - "PS7_SAXIHP2WDATA18", - "PS7_SAXIHP2WDATA19", - "PS7_SAXIHP2WDATA2", - "PS7_SAXIHP2WDATA20", - "PS7_SAXIHP2WDATA21", - "PS7_SAXIHP2WDATA22", - "PS7_SAXIHP2WDATA23", - "PS7_SAXIHP2WDATA24", - "PS7_SAXIHP2WDATA25", - "PS7_SAXIHP2WDATA26", - "PS7_SAXIHP2WDATA27", - "PS7_SAXIHP2WDATA28", - "PS7_SAXIHP2WDATA29", - "PS7_SAXIHP2WDATA3", - "PS7_SAXIHP2WDATA30", - "PS7_SAXIHP2WDATA31", - "PS7_SAXIHP2WDATA32", - "PS7_SAXIHP2WDATA33", - "PS7_SAXIHP2WDATA34", - "PS7_SAXIHP2WDATA35", - "PS7_SAXIHP2WDATA36", - "PS7_SAXIHP2WDATA37", - "PS7_SAXIHP2WDATA38", - "PS7_SAXIHP2WDATA39", - "PS7_SAXIHP2WDATA4", - "PS7_SAXIHP2WDATA40", - "PS7_SAXIHP2WDATA41", - "PS7_SAXIHP2WDATA42", - "PS7_SAXIHP2WDATA43", - "PS7_SAXIHP2WDATA44", - "PS7_SAXIHP2WDATA45", - "PS7_SAXIHP2WDATA46", - "PS7_SAXIHP2WDATA47", - "PS7_SAXIHP2WDATA48", - "PS7_SAXIHP2WDATA49", - "PS7_SAXIHP2WDATA5", - "PS7_SAXIHP2WDATA50", - "PS7_SAXIHP2WDATA51", - "PS7_SAXIHP2WDATA52", - "PS7_SAXIHP2WDATA53", - "PS7_SAXIHP2WDATA54", - "PS7_SAXIHP2WDATA55", - "PS7_SAXIHP2WDATA56", - "PS7_SAXIHP2WDATA57", - "PS7_SAXIHP2WDATA58", - "PS7_SAXIHP2WDATA59", - "PS7_SAXIHP2WDATA6", - "PS7_SAXIHP2WDATA60", - "PS7_SAXIHP2WDATA61", - "PS7_SAXIHP2WDATA62", - "PS7_SAXIHP2WDATA63", - "PS7_SAXIHP2WDATA7", - "PS7_SAXIHP2WDATA8", - "PS7_SAXIHP2WDATA9", - "PS7_SAXIHP2WID0", - "PS7_SAXIHP2WID1", - "PS7_SAXIHP2WID2", - "PS7_SAXIHP2WID3", - "PS7_SAXIHP2WID4", - "PS7_SAXIHP2WID5", - "PS7_SAXIHP2WLAST", - "PS7_SAXIHP2WREADY", - "PS7_SAXIHP2WRISSUECAP1EN", - "PS7_SAXIHP2WSTRB0", - "PS7_SAXIHP2WSTRB1", - "PS7_SAXIHP2WSTRB2", - "PS7_SAXIHP2WSTRB3", - "PS7_SAXIHP2WSTRB4", - "PS7_SAXIHP2WSTRB5", - "PS7_SAXIHP2WSTRB6", - "PS7_SAXIHP2WSTRB7", - "PS7_SAXIHP2WVALID", - "PS7_SAXIHP3ACLK", - "PS7_SAXIHP3ARADDR0", - "PS7_SAXIHP3ARADDR1", - "PS7_SAXIHP3ARADDR10", - "PS7_SAXIHP3ARADDR11", - "PS7_SAXIHP3ARADDR12", - "PS7_SAXIHP3ARADDR13", - "PS7_SAXIHP3ARADDR14", - "PS7_SAXIHP3ARADDR15", - "PS7_SAXIHP3ARADDR16", - "PS7_SAXIHP3ARADDR17", - "PS7_SAXIHP3ARADDR18", - "PS7_SAXIHP3ARADDR19", - "PS7_SAXIHP3ARADDR2", - "PS7_SAXIHP3ARADDR20", - "PS7_SAXIHP3ARADDR21", - "PS7_SAXIHP3ARADDR22", - "PS7_SAXIHP3ARADDR23", - "PS7_SAXIHP3ARADDR24", - "PS7_SAXIHP3ARADDR25", - "PS7_SAXIHP3ARADDR26", - "PS7_SAXIHP3ARADDR27", - "PS7_SAXIHP3ARADDR28", - "PS7_SAXIHP3ARADDR29", - "PS7_SAXIHP3ARADDR3", - "PS7_SAXIHP3ARADDR30", - "PS7_SAXIHP3ARADDR31", - "PS7_SAXIHP3ARADDR4", - "PS7_SAXIHP3ARADDR5", - "PS7_SAXIHP3ARADDR6", - "PS7_SAXIHP3ARADDR7", - "PS7_SAXIHP3ARADDR8", - "PS7_SAXIHP3ARADDR9", - "PS7_SAXIHP3ARBURST0", - "PS7_SAXIHP3ARBURST1", - "PS7_SAXIHP3ARCACHE0", - "PS7_SAXIHP3ARCACHE1", - "PS7_SAXIHP3ARCACHE2", - "PS7_SAXIHP3ARCACHE3", - "PS7_SAXIHP3ARESETN", - "PS7_SAXIHP3ARID0", - "PS7_SAXIHP3ARID1", - "PS7_SAXIHP3ARID2", - "PS7_SAXIHP3ARID3", - "PS7_SAXIHP3ARID4", - "PS7_SAXIHP3ARID5", - "PS7_SAXIHP3ARLEN0", - "PS7_SAXIHP3ARLEN1", - "PS7_SAXIHP3ARLEN2", - "PS7_SAXIHP3ARLEN3", - "PS7_SAXIHP3ARLOCK0", - "PS7_SAXIHP3ARLOCK1", - "PS7_SAXIHP3ARPROT0", - "PS7_SAXIHP3ARPROT1", - "PS7_SAXIHP3ARPROT2", - "PS7_SAXIHP3ARQOS0", - "PS7_SAXIHP3ARQOS1", - "PS7_SAXIHP3ARQOS2", - "PS7_SAXIHP3ARQOS3", - "PS7_SAXIHP3ARREADY", - "PS7_SAXIHP3ARSIZE0", - "PS7_SAXIHP3ARSIZE1", - "PS7_SAXIHP3ARVALID", - "PS7_SAXIHP3AWADDR0", - "PS7_SAXIHP3AWADDR1", - "PS7_SAXIHP3AWADDR10", - "PS7_SAXIHP3AWADDR11", - "PS7_SAXIHP3AWADDR12", - "PS7_SAXIHP3AWADDR13", - "PS7_SAXIHP3AWADDR14", - "PS7_SAXIHP3AWADDR15", - "PS7_SAXIHP3AWADDR16", - "PS7_SAXIHP3AWADDR17", - "PS7_SAXIHP3AWADDR18", - "PS7_SAXIHP3AWADDR19", - "PS7_SAXIHP3AWADDR2", - "PS7_SAXIHP3AWADDR20", - "PS7_SAXIHP3AWADDR21", - "PS7_SAXIHP3AWADDR22", - "PS7_SAXIHP3AWADDR23", - "PS7_SAXIHP3AWADDR24", - "PS7_SAXIHP3AWADDR25", - "PS7_SAXIHP3AWADDR26", - "PS7_SAXIHP3AWADDR27", - "PS7_SAXIHP3AWADDR28", - "PS7_SAXIHP3AWADDR29", - "PS7_SAXIHP3AWADDR3", - "PS7_SAXIHP3AWADDR30", - "PS7_SAXIHP3AWADDR31", - "PS7_SAXIHP3AWADDR4", - "PS7_SAXIHP3AWADDR5", - "PS7_SAXIHP3AWADDR6", - "PS7_SAXIHP3AWADDR7", - "PS7_SAXIHP3AWADDR8", - "PS7_SAXIHP3AWADDR9", - "PS7_SAXIHP3AWBURST0", - "PS7_SAXIHP3AWBURST1", - "PS7_SAXIHP3AWCACHE0", - "PS7_SAXIHP3AWCACHE1", - "PS7_SAXIHP3AWCACHE2", - "PS7_SAXIHP3AWCACHE3", - "PS7_SAXIHP3AWID0", - "PS7_SAXIHP3AWID1", - "PS7_SAXIHP3AWID2", - "PS7_SAXIHP3AWID3", - "PS7_SAXIHP3AWID4", - "PS7_SAXIHP3AWID5", - "PS7_SAXIHP3AWLEN0", - "PS7_SAXIHP3AWLEN1", - "PS7_SAXIHP3AWLEN2", - "PS7_SAXIHP3AWLEN3", - "PS7_SAXIHP3AWLOCK0", - "PS7_SAXIHP3AWLOCK1", - "PS7_SAXIHP3AWPROT0", - "PS7_SAXIHP3AWPROT1", - "PS7_SAXIHP3AWPROT2", - "PS7_SAXIHP3AWQOS0", - "PS7_SAXIHP3AWQOS1", - "PS7_SAXIHP3AWQOS2", - "PS7_SAXIHP3AWQOS3", - "PS7_SAXIHP3AWREADY", - "PS7_SAXIHP3AWSIZE0", - "PS7_SAXIHP3AWSIZE1", - "PS7_SAXIHP3AWVALID", - "PS7_SAXIHP3BID0", - "PS7_SAXIHP3BID1", - "PS7_SAXIHP3BID2", - "PS7_SAXIHP3BID3", - "PS7_SAXIHP3BID4", - "PS7_SAXIHP3BID5", - "PS7_SAXIHP3BREADY", - "PS7_SAXIHP3BRESP0", - "PS7_SAXIHP3BRESP1", - "PS7_SAXIHP3BVALID", - "PS7_SAXIHP3RACOUNT0", - "PS7_SAXIHP3RACOUNT1", - "PS7_SAXIHP3RACOUNT2", - "PS7_SAXIHP3RCOUNT0", - "PS7_SAXIHP3RCOUNT1", - "PS7_SAXIHP3RCOUNT2", - "PS7_SAXIHP3RCOUNT3", - "PS7_SAXIHP3RCOUNT4", - "PS7_SAXIHP3RCOUNT5", - "PS7_SAXIHP3RCOUNT6", - "PS7_SAXIHP3RCOUNT7", - "PS7_SAXIHP3RDATA0", - "PS7_SAXIHP3RDATA1", - "PS7_SAXIHP3RDATA10", - "PS7_SAXIHP3RDATA11", - "PS7_SAXIHP3RDATA12", - "PS7_SAXIHP3RDATA13", - "PS7_SAXIHP3RDATA14", - "PS7_SAXIHP3RDATA15", - "PS7_SAXIHP3RDATA16", - "PS7_SAXIHP3RDATA17", - "PS7_SAXIHP3RDATA18", - "PS7_SAXIHP3RDATA19", - "PS7_SAXIHP3RDATA2", - "PS7_SAXIHP3RDATA20", - "PS7_SAXIHP3RDATA21", - "PS7_SAXIHP3RDATA22", - "PS7_SAXIHP3RDATA23", - "PS7_SAXIHP3RDATA24", - "PS7_SAXIHP3RDATA25", - "PS7_SAXIHP3RDATA26", - "PS7_SAXIHP3RDATA27", - "PS7_SAXIHP3RDATA28", - "PS7_SAXIHP3RDATA29", - "PS7_SAXIHP3RDATA3", - "PS7_SAXIHP3RDATA30", - "PS7_SAXIHP3RDATA31", - "PS7_SAXIHP3RDATA32", - "PS7_SAXIHP3RDATA33", - "PS7_SAXIHP3RDATA34", - "PS7_SAXIHP3RDATA35", - "PS7_SAXIHP3RDATA36", - "PS7_SAXIHP3RDATA37", - "PS7_SAXIHP3RDATA38", - "PS7_SAXIHP3RDATA39", - "PS7_SAXIHP3RDATA4", - "PS7_SAXIHP3RDATA40", - "PS7_SAXIHP3RDATA41", - "PS7_SAXIHP3RDATA42", - "PS7_SAXIHP3RDATA43", - "PS7_SAXIHP3RDATA44", - "PS7_SAXIHP3RDATA45", - "PS7_SAXIHP3RDATA46", - "PS7_SAXIHP3RDATA47", - "PS7_SAXIHP3RDATA48", - "PS7_SAXIHP3RDATA49", - "PS7_SAXIHP3RDATA5", - "PS7_SAXIHP3RDATA50", - "PS7_SAXIHP3RDATA51", - "PS7_SAXIHP3RDATA52", - "PS7_SAXIHP3RDATA53", - "PS7_SAXIHP3RDATA54", - "PS7_SAXIHP3RDATA55", - "PS7_SAXIHP3RDATA56", - "PS7_SAXIHP3RDATA57", - "PS7_SAXIHP3RDATA58", - "PS7_SAXIHP3RDATA59", - "PS7_SAXIHP3RDATA6", - "PS7_SAXIHP3RDATA60", - "PS7_SAXIHP3RDATA61", - "PS7_SAXIHP3RDATA62", - "PS7_SAXIHP3RDATA63", - "PS7_SAXIHP3RDATA7", - "PS7_SAXIHP3RDATA8", - "PS7_SAXIHP3RDATA9", - "PS7_SAXIHP3RDISSUECAP1EN", - "PS7_SAXIHP3RID0", - "PS7_SAXIHP3RID1", - "PS7_SAXIHP3RID2", - "PS7_SAXIHP3RID3", - "PS7_SAXIHP3RID4", - "PS7_SAXIHP3RID5", - "PS7_SAXIHP3RLAST", - "PS7_SAXIHP3RREADY", - "PS7_SAXIHP3RRESP0", - "PS7_SAXIHP3RRESP1", - "PS7_SAXIHP3RVALID", - "PS7_SAXIHP3WACOUNT0", - "PS7_SAXIHP3WACOUNT1", - "PS7_SAXIHP3WACOUNT2", - "PS7_SAXIHP3WACOUNT3", - "PS7_SAXIHP3WACOUNT4", - "PS7_SAXIHP3WACOUNT5", - "PS7_SAXIHP3WCOUNT0", - "PS7_SAXIHP3WCOUNT1", - "PS7_SAXIHP3WCOUNT2", - "PS7_SAXIHP3WCOUNT3", - "PS7_SAXIHP3WCOUNT4", - "PS7_SAXIHP3WCOUNT5", - "PS7_SAXIHP3WCOUNT6", - "PS7_SAXIHP3WCOUNT7", - "PS7_SAXIHP3WDATA0", - "PS7_SAXIHP3WDATA1", - "PS7_SAXIHP3WDATA10", - "PS7_SAXIHP3WDATA11", - "PS7_SAXIHP3WDATA12", - "PS7_SAXIHP3WDATA13", - "PS7_SAXIHP3WDATA14", - "PS7_SAXIHP3WDATA15", - "PS7_SAXIHP3WDATA16", - "PS7_SAXIHP3WDATA17", - "PS7_SAXIHP3WDATA18", - "PS7_SAXIHP3WDATA19", - "PS7_SAXIHP3WDATA2", - "PS7_SAXIHP3WDATA20", - "PS7_SAXIHP3WDATA21", - "PS7_SAXIHP3WDATA22", - "PS7_SAXIHP3WDATA23", - "PS7_SAXIHP3WDATA24", - "PS7_SAXIHP3WDATA25", - "PS7_SAXIHP3WDATA26", - "PS7_SAXIHP3WDATA27", - "PS7_SAXIHP3WDATA28", - "PS7_SAXIHP3WDATA29", - "PS7_SAXIHP3WDATA3", - "PS7_SAXIHP3WDATA30", - "PS7_SAXIHP3WDATA31", - "PS7_SAXIHP3WDATA32", - "PS7_SAXIHP3WDATA33", - "PS7_SAXIHP3WDATA34", - "PS7_SAXIHP3WDATA35", - "PS7_SAXIHP3WDATA36", - "PS7_SAXIHP3WDATA37", - "PS7_SAXIHP3WDATA38", - "PS7_SAXIHP3WDATA39", - "PS7_SAXIHP3WDATA4", - "PS7_SAXIHP3WDATA40", - "PS7_SAXIHP3WDATA41", - "PS7_SAXIHP3WDATA42", - "PS7_SAXIHP3WDATA43", - "PS7_SAXIHP3WDATA44", - "PS7_SAXIHP3WDATA45", - "PS7_SAXIHP3WDATA46", - "PS7_SAXIHP3WDATA47", - "PS7_SAXIHP3WDATA48", - "PS7_SAXIHP3WDATA49", - "PS7_SAXIHP3WDATA5", - "PS7_SAXIHP3WDATA50", - "PS7_SAXIHP3WDATA51", - "PS7_SAXIHP3WDATA52", - "PS7_SAXIHP3WDATA53", - "PS7_SAXIHP3WDATA54", - "PS7_SAXIHP3WDATA55", - "PS7_SAXIHP3WDATA56", - "PS7_SAXIHP3WDATA57", - "PS7_SAXIHP3WDATA58", - "PS7_SAXIHP3WDATA59", - "PS7_SAXIHP3WDATA6", - "PS7_SAXIHP3WDATA60", - "PS7_SAXIHP3WDATA61", - "PS7_SAXIHP3WDATA62", - "PS7_SAXIHP3WDATA63", - "PS7_SAXIHP3WDATA7", - "PS7_SAXIHP3WDATA8", - "PS7_SAXIHP3WDATA9", - "PS7_SAXIHP3WID0", - "PS7_SAXIHP3WID1", - "PS7_SAXIHP3WID2", - "PS7_SAXIHP3WID3", - "PS7_SAXIHP3WID4", - "PS7_SAXIHP3WID5", - "PS7_SAXIHP3WLAST", - "PS7_SAXIHP3WREADY", - "PS7_SAXIHP3WRISSUECAP1EN", - "PS7_SAXIHP3WSTRB0", - "PS7_SAXIHP3WSTRB1", - "PS7_SAXIHP3WSTRB2", - "PS7_SAXIHP3WSTRB3", - "PS7_SAXIHP3WSTRB4", - "PS7_SAXIHP3WSTRB5", - "PS7_SAXIHP3WSTRB6", - "PS7_SAXIHP3WSTRB7", - "PS7_SAXIHP3WVALID", - "PS7_TESTA9MBISTDATAIN", - "PS7_TESTA9MBISTDSHIFT", - "PS7_TESTA9MBISTENABLEN", - "PS7_TESTA9MBISTRESET", - "PS7_TESTA9MBISTRESULT0", - "PS7_TESTA9MBISTRESULT1", - "PS7_TESTA9MBISTRESULT2", - "PS7_TESTA9MBISTRESULT3", - "PS7_TESTA9MBISTRESULT4", - "PS7_TESTA9MBISTRESULT5", - "PS7_TESTA9MBISTRUN", - "PS7_TESTA9MBISTSHIFT", - "PS7_TESTAMUXENABLEB", - "PS7_TESTBGAMUXSEL0", - "PS7_TESTBGAMUXSEL1", - "PS7_TESTBGAMUXSEL2", - "PS7_TESTBGAMUXSEL3", - "PS7_TESTBGAMUXSEL4", - "PS7_TESTBGPOWERDOWN", - "PS7_TESTBSCENN", - "PS7_TESTDFTRAMBYPN", - "PS7_TESTDIVCLKOUT0", - "PS7_TESTDIVCLKOUT1", - "PS7_TESTDIVCLKOUT10", - "PS7_TESTDIVCLKOUT11", - "PS7_TESTDIVCLKOUT12", - "PS7_TESTDIVCLKOUT13", - "PS7_TESTDIVCLKOUT14", - "PS7_TESTDIVCLKOUT15", - "PS7_TESTDIVCLKOUT16", - "PS7_TESTDIVCLKOUT17", - "PS7_TESTDIVCLKOUT18", - "PS7_TESTDIVCLKOUT19", - "PS7_TESTDIVCLKOUT2", - "PS7_TESTDIVCLKOUT20", - "PS7_TESTDIVCLKOUT3", - "PS7_TESTDIVCLKOUT4", - "PS7_TESTDIVCLKOUT5", - "PS7_TESTDIVCLKOUT6", - "PS7_TESTDIVCLKOUT7", - "PS7_TESTDIVCLKOUT8", - "PS7_TESTDIVCLKOUT9", - "PS7_TESTDIVCLKOUTPREOPCGENABLEN", - "PS7_TESTDIVIDERRESETN", - "PS7_TESTDIVIDERUPDATETOG", - "PS7_TESTEDTBYPASS", - "PS7_TESTEDTCHANNELSIN0", - "PS7_TESTEDTCHANNELSIN1", - "PS7_TESTEDTCHANNELSIN2", - "PS7_TESTEDTCHANNELSIN3", - "PS7_TESTEDTCHANNELSIN4", - "PS7_TESTEDTCHANNELSIN5", - "PS7_TESTEDTCHANNELSIN6", - "PS7_TESTEDTCHANNELSOUT0", - "PS7_TESTEDTCHANNELSOUT1", - "PS7_TESTEDTCHANNELSOUT2", - "PS7_TESTEDTCHANNELSOUT3", - "PS7_TESTEDTCHANNELSOUT4", - "PS7_TESTEDTCHANNELSOUT5", - "PS7_TESTEDTCHANNELSOUT6", - "PS7_TESTEDTCLOCK", - "PS7_TESTEDTUPDATE", - "PS7_TESTMBISTCOMPSTAT", - "PS7_TESTMBISTMODEN", - "PS7_TESTMBISTTAPTCK", - "PS7_TESTMBISTTAPTDI", - "PS7_TESTMBISTTAPTDO", - "PS7_TESTMBISTTAPTDOENABLE", - "PS7_TESTMBISTTAPTMS", - "PS7_TESTMBISTTAPTRST", - "PS7_TESTPLLCLKOUT0", - "PS7_TESTPLLCLKOUT0_PW", - "PS7_TESTPLLCLKOUT1", - "PS7_TESTPLLCLKOUT1_PW", - "PS7_TESTPLLCLKOUT2", - "PS7_TESTPLLCLKOUT2_PW", - "PS7_TESTPLLCONFIGREADY0", - "PS7_TESTPLLCONFIGREADY1", - "PS7_TESTPLLCONFIGREADY2", - "PS7_TESTPLLCONFIGUPDATE0", - "PS7_TESTPLLCONFIGUPDATE1", - "PS7_TESTPLLCONFIGUPDATE2", - "PS7_TESTPLLFBTESTN0", - "PS7_TESTPLLFBTESTN1", - "PS7_TESTPLLFBTESTN2", - "PS7_TESTPLLFEEDBACKDIV0", - "PS7_TESTPLLFEEDBACKDIV1", - "PS7_TESTPLLFEEDBACKDIV2", - "PS7_TESTPLLLOCK0", - "PS7_TESTPLLLOCK1", - "PS7_TESTPLLLOCK2", - "PS7_TESTPLLNEWCLK0", - "PS7_TESTPLLNEWCLK0_PW", - "PS7_TESTPLLNEWCLK1", - "PS7_TESTPLLNEWCLK1_PW", - "PS7_TESTPLLNEWCLK2", - "PS7_TESTPLLNEWCLK2_PW", - "PS7_TESTPLLPOWERDOWNN", - "PS7_TESTPLLREFCLKCPU", - "PS7_TESTPLLREFCLKDDR", - "PS7_TESTPLLREFCLKENN0", - "PS7_TESTPLLREFCLKENN1", - "PS7_TESTPLLREFCLKENN2", - "PS7_TESTPLLREFCLKIOU", - "PS7_TESTPLLRESET", - "PS7_TESTPSSCLOCKDR", - "PS7_TESTPSSEXTEST", - "PS7_TESTPSSEXTESTSMPL", - "PS7_TESTPSSINTEST", - "PS7_TESTPSSRESETTAPB", - "PS7_TESTPSSSHIFTDR", - "PS7_TESTPSSTDI", - "PS7_TESTPSSTDO", - "PS7_TESTPSSUPDATEDR", - "PS7_TESTRESETMUXN", - "PS7_TESTSCANCLOCKCLOCKGEN", - "PS7_TESTSCANCLOCKOPCG0", - "PS7_TESTSCANCLOCKOPCG1", - "PS7_TESTSCANCLOCKOPCG10", - "PS7_TESTSCANCLOCKOPCG11", - "PS7_TESTSCANCLOCKOPCG12", - "PS7_TESTSCANCLOCKOPCG13", - "PS7_TESTSCANCLOCKOPCG14", - "PS7_TESTSCANCLOCKOPCG15", - "PS7_TESTSCANCLOCKOPCG16", - "PS7_TESTSCANCLOCKOPCG17", - "PS7_TESTSCANCLOCKOPCG18", - "PS7_TESTSCANCLOCKOPCG19", - "PS7_TESTSCANCLOCKOPCG2", - "PS7_TESTSCANCLOCKOPCG20", - "PS7_TESTSCANCLOCKOPCG21", - "PS7_TESTSCANCLOCKOPCG22", - "PS7_TESTSCANCLOCKOPCG23", - "PS7_TESTSCANCLOCKOPCG3", - "PS7_TESTSCANCLOCKOPCG4", - "PS7_TESTSCANCLOCKOPCG5", - "PS7_TESTSCANCLOCKOPCG6", - "PS7_TESTSCANCLOCKOPCG7", - "PS7_TESTSCANCLOCKOPCG8", - "PS7_TESTSCANCLOCKOPCG9", - "PS7_TESTSCANCLOCKPAD0", - "PS7_TESTSCANCLOCKPAD1", - "PS7_TESTSCANCLOCKPAD2", - "PS7_TESTSCANCLOCKPAD3", - "PS7_TESTSCANCLOCKPAD4", - "PS7_TESTSCANENABLEATSPEEDNONSCANFLOPSN", - "PS7_TESTSCANENABLEN", - "PS7_TESTSCANMODEATSPEEDN", - "PS7_TESTSCANMODEATSPEEDOPCGN0", - "PS7_TESTSCANMODEATSPEEDOPCGN1", - "PS7_TESTSCANMODEATSPEEDOPCGN10", - "PS7_TESTSCANMODEATSPEEDOPCGN11", - "PS7_TESTSCANMODEATSPEEDOPCGN12", - "PS7_TESTSCANMODEATSPEEDOPCGN13", - "PS7_TESTSCANMODEATSPEEDOPCGN14", - "PS7_TESTSCANMODEATSPEEDOPCGN15", - "PS7_TESTSCANMODEATSPEEDOPCGN16", - "PS7_TESTSCANMODEATSPEEDOPCGN17", - "PS7_TESTSCANMODEATSPEEDOPCGN18", - "PS7_TESTSCANMODEATSPEEDOPCGN19", - "PS7_TESTSCANMODEATSPEEDOPCGN2", - "PS7_TESTSCANMODEATSPEEDOPCGN20", - "PS7_TESTSCANMODEATSPEEDOPCGN21", - "PS7_TESTSCANMODEATSPEEDOPCGN22", - "PS7_TESTSCANMODEATSPEEDOPCGN23", - "PS7_TESTSCANMODEATSPEEDOPCGN3", - "PS7_TESTSCANMODEATSPEEDOPCGN4", - "PS7_TESTSCANMODEATSPEEDOPCGN5", - "PS7_TESTSCANMODEATSPEEDOPCGN6", - "PS7_TESTSCANMODEATSPEEDOPCGN7", - "PS7_TESTSCANMODEATSPEEDOPCGN8", - "PS7_TESTSCANMODEATSPEEDOPCGN9", - "PS7_TESTSCANMODEN", - "PS7_TESTSCANRESETN", - "PS7_TESTSLCRCONFIGCLOCK", - "PS7_TESTSLCRCONFIGIN", - "PS7_TESTSLCRCONFIGOUT", - "PS7_TESTSLCRCONFIGRESETN", - "PS7_TESTSPAREIN0", - "PS7_TESTSPAREIN1", - "PS7_TESTSPAREIN2", - "PS7_TESTSPAREIN3", - "PS7_TESTSPAREIN4", - "PS7_TESTSPAREIN5", - "PS7_TESTSPAREIN6", - "PS7_TESTSPAREOUT0", - "PS7_TESTSPAREOUT1", - "PS7_TESTSPAREOUT2", - "PS7_TESTSPAREOUT3", - "PS7_TESTSPAREOUT4", - "PS7_TESTSPAREOUT5", - "PS7_TESTSPAREOUT6", - "PS7_TESTTRIGGEROPCGN", - "PSS1_CLK_B0_0", - "PSS1_CLK_B0_1", - "PSS1_CLK_B0_10", - "PSS1_CLK_B0_11", - "PSS1_CLK_B0_12", - "PSS1_CLK_B0_13", - "PSS1_CLK_B0_14", - "PSS1_CLK_B0_15", - "PSS1_CLK_B0_16", - "PSS1_CLK_B0_17", - "PSS1_CLK_B0_18", - "PSS1_CLK_B0_19", - "PSS1_CLK_B0_2", - "PSS1_CLK_B0_20", - "PSS1_CLK_B0_21", - "PSS1_CLK_B0_22", - "PSS1_CLK_B0_23", - "PSS1_CLK_B0_24", - "PSS1_CLK_B0_25", - "PSS1_CLK_B0_26", - "PSS1_CLK_B0_27", - "PSS1_CLK_B0_28", - "PSS1_CLK_B0_29", - "PSS1_CLK_B0_3", - "PSS1_CLK_B0_30", - "PSS1_CLK_B0_31", - "PSS1_CLK_B0_32", - "PSS1_CLK_B0_33", - "PSS1_CLK_B0_34", - "PSS1_CLK_B0_35", - "PSS1_CLK_B0_36", - "PSS1_CLK_B0_37", - "PSS1_CLK_B0_38", - "PSS1_CLK_B0_39", - "PSS1_CLK_B0_4", - "PSS1_CLK_B0_5", - "PSS1_CLK_B0_6", - "PSS1_CLK_B0_7", - "PSS1_CLK_B0_8", - "PSS1_CLK_B0_9", - "PSS1_CLK_B1_0", - "PSS1_CLK_B1_1", - "PSS1_CLK_B1_10", - "PSS1_CLK_B1_11", - "PSS1_CLK_B1_12", - "PSS1_CLK_B1_13", - "PSS1_CLK_B1_14", - "PSS1_CLK_B1_15", - "PSS1_CLK_B1_16", - "PSS1_CLK_B1_17", - "PSS1_CLK_B1_18", - "PSS1_CLK_B1_19", - "PSS1_CLK_B1_2", - "PSS1_CLK_B1_20", - "PSS1_CLK_B1_21", - "PSS1_CLK_B1_22", - "PSS1_CLK_B1_23", - "PSS1_CLK_B1_24", - "PSS1_CLK_B1_25", - "PSS1_CLK_B1_26", - "PSS1_CLK_B1_27", - "PSS1_CLK_B1_28", - "PSS1_CLK_B1_29", - "PSS1_CLK_B1_3", - "PSS1_CLK_B1_30", - "PSS1_CLK_B1_31", - "PSS1_CLK_B1_32", - "PSS1_CLK_B1_33", - "PSS1_CLK_B1_34", - "PSS1_CLK_B1_35", - "PSS1_CLK_B1_36", - "PSS1_CLK_B1_37", - "PSS1_CLK_B1_38", - "PSS1_CLK_B1_39", - "PSS1_CLK_B1_4", - "PSS1_CLK_B1_5", - "PSS1_CLK_B1_6", - "PSS1_CLK_B1_7", - "PSS1_CLK_B1_8", - "PSS1_CLK_B1_9", - "PSS1_IMUX_B0_0", - "PSS1_IMUX_B0_1", - "PSS1_IMUX_B0_10", - "PSS1_IMUX_B0_11", - "PSS1_IMUX_B0_12", - "PSS1_IMUX_B0_13", - "PSS1_IMUX_B0_14", - "PSS1_IMUX_B0_15", - "PSS1_IMUX_B0_16", - "PSS1_IMUX_B0_17", - "PSS1_IMUX_B0_18", - "PSS1_IMUX_B0_19", - "PSS1_IMUX_B0_2", - "PSS1_IMUX_B0_20", - "PSS1_IMUX_B0_21", - "PSS1_IMUX_B0_22", - "PSS1_IMUX_B0_23", - "PSS1_IMUX_B0_24", - "PSS1_IMUX_B0_25", - "PSS1_IMUX_B0_26", - "PSS1_IMUX_B0_27", - "PSS1_IMUX_B0_28", - "PSS1_IMUX_B0_29", - "PSS1_IMUX_B0_3", - "PSS1_IMUX_B0_30", - "PSS1_IMUX_B0_31", - "PSS1_IMUX_B0_32", - "PSS1_IMUX_B0_33", - "PSS1_IMUX_B0_34", - "PSS1_IMUX_B0_35", - "PSS1_IMUX_B0_36", - "PSS1_IMUX_B0_37", - "PSS1_IMUX_B0_38", - "PSS1_IMUX_B0_39", - "PSS1_IMUX_B0_4", - "PSS1_IMUX_B0_5", - "PSS1_IMUX_B0_6", - "PSS1_IMUX_B0_7", - "PSS1_IMUX_B0_8", - "PSS1_IMUX_B0_9", - "PSS1_IMUX_B10_0", - "PSS1_IMUX_B10_1", - "PSS1_IMUX_B10_10", - "PSS1_IMUX_B10_11", - "PSS1_IMUX_B10_12", - "PSS1_IMUX_B10_13", - "PSS1_IMUX_B10_14", - "PSS1_IMUX_B10_15", - "PSS1_IMUX_B10_16", - "PSS1_IMUX_B10_17", - "PSS1_IMUX_B10_18", - "PSS1_IMUX_B10_19", - "PSS1_IMUX_B10_2", - "PSS1_IMUX_B10_20", - "PSS1_IMUX_B10_21", - "PSS1_IMUX_B10_22", - "PSS1_IMUX_B10_23", - "PSS1_IMUX_B10_24", - "PSS1_IMUX_B10_25", - "PSS1_IMUX_B10_26", - "PSS1_IMUX_B10_27", - "PSS1_IMUX_B10_28", - "PSS1_IMUX_B10_29", - "PSS1_IMUX_B10_3", - "PSS1_IMUX_B10_30", - "PSS1_IMUX_B10_31", - "PSS1_IMUX_B10_32", - "PSS1_IMUX_B10_33", - "PSS1_IMUX_B10_34", - "PSS1_IMUX_B10_35", - "PSS1_IMUX_B10_36", - "PSS1_IMUX_B10_37", - "PSS1_IMUX_B10_38", - "PSS1_IMUX_B10_39", - "PSS1_IMUX_B10_4", - "PSS1_IMUX_B10_5", - "PSS1_IMUX_B10_6", - "PSS1_IMUX_B10_7", - "PSS1_IMUX_B10_8", - "PSS1_IMUX_B10_9", - "PSS1_IMUX_B11_0", - "PSS1_IMUX_B11_1", - "PSS1_IMUX_B11_10", - "PSS1_IMUX_B11_11", - "PSS1_IMUX_B11_12", - "PSS1_IMUX_B11_13", - "PSS1_IMUX_B11_14", - "PSS1_IMUX_B11_15", - "PSS1_IMUX_B11_16", - "PSS1_IMUX_B11_17", - "PSS1_IMUX_B11_18", - "PSS1_IMUX_B11_19", - "PSS1_IMUX_B11_2", - "PSS1_IMUX_B11_20", - "PSS1_IMUX_B11_21", - "PSS1_IMUX_B11_22", - "PSS1_IMUX_B11_23", - "PSS1_IMUX_B11_24", - "PSS1_IMUX_B11_25", - "PSS1_IMUX_B11_26", - "PSS1_IMUX_B11_27", - "PSS1_IMUX_B11_28", - "PSS1_IMUX_B11_29", - "PSS1_IMUX_B11_3", - "PSS1_IMUX_B11_30", - "PSS1_IMUX_B11_31", - "PSS1_IMUX_B11_32", - "PSS1_IMUX_B11_33", - "PSS1_IMUX_B11_34", - "PSS1_IMUX_B11_35", - "PSS1_IMUX_B11_36", - "PSS1_IMUX_B11_37", - "PSS1_IMUX_B11_38", - "PSS1_IMUX_B11_39", - "PSS1_IMUX_B11_4", - "PSS1_IMUX_B11_5", - "PSS1_IMUX_B11_6", - "PSS1_IMUX_B11_7", - "PSS1_IMUX_B11_8", - "PSS1_IMUX_B11_9", - "PSS1_IMUX_B12_0", - "PSS1_IMUX_B12_1", - "PSS1_IMUX_B12_10", - "PSS1_IMUX_B12_11", - "PSS1_IMUX_B12_12", - "PSS1_IMUX_B12_13", - "PSS1_IMUX_B12_14", - "PSS1_IMUX_B12_15", - "PSS1_IMUX_B12_16", - "PSS1_IMUX_B12_17", - "PSS1_IMUX_B12_18", - "PSS1_IMUX_B12_19", - "PSS1_IMUX_B12_2", - "PSS1_IMUX_B12_20", - "PSS1_IMUX_B12_21", - "PSS1_IMUX_B12_22", - "PSS1_IMUX_B12_23", - "PSS1_IMUX_B12_24", - "PSS1_IMUX_B12_25", - "PSS1_IMUX_B12_26", - "PSS1_IMUX_B12_27", - "PSS1_IMUX_B12_28", - "PSS1_IMUX_B12_29", - "PSS1_IMUX_B12_3", - "PSS1_IMUX_B12_30", - "PSS1_IMUX_B12_31", - "PSS1_IMUX_B12_32", - "PSS1_IMUX_B12_33", - "PSS1_IMUX_B12_34", - "PSS1_IMUX_B12_35", - "PSS1_IMUX_B12_36", - "PSS1_IMUX_B12_37", - "PSS1_IMUX_B12_38", - "PSS1_IMUX_B12_39", - "PSS1_IMUX_B12_4", - "PSS1_IMUX_B12_5", - "PSS1_IMUX_B12_6", - "PSS1_IMUX_B12_7", - "PSS1_IMUX_B12_8", - "PSS1_IMUX_B12_9", - "PSS1_IMUX_B13_0", - "PSS1_IMUX_B13_1", - "PSS1_IMUX_B13_10", - "PSS1_IMUX_B13_11", - "PSS1_IMUX_B13_12", - "PSS1_IMUX_B13_13", - "PSS1_IMUX_B13_14", - "PSS1_IMUX_B13_15", - "PSS1_IMUX_B13_16", - "PSS1_IMUX_B13_17", - "PSS1_IMUX_B13_18", - "PSS1_IMUX_B13_19", - "PSS1_IMUX_B13_2", - "PSS1_IMUX_B13_20", - "PSS1_IMUX_B13_21", - "PSS1_IMUX_B13_22", - "PSS1_IMUX_B13_23", - "PSS1_IMUX_B13_24", - "PSS1_IMUX_B13_25", - "PSS1_IMUX_B13_26", - "PSS1_IMUX_B13_27", - "PSS1_IMUX_B13_28", - "PSS1_IMUX_B13_29", - "PSS1_IMUX_B13_3", - "PSS1_IMUX_B13_30", - "PSS1_IMUX_B13_31", - "PSS1_IMUX_B13_32", - "PSS1_IMUX_B13_33", - "PSS1_IMUX_B13_34", - "PSS1_IMUX_B13_35", - "PSS1_IMUX_B13_36", - "PSS1_IMUX_B13_37", - "PSS1_IMUX_B13_38", - "PSS1_IMUX_B13_39", - "PSS1_IMUX_B13_4", - "PSS1_IMUX_B13_5", - "PSS1_IMUX_B13_6", - "PSS1_IMUX_B13_7", - "PSS1_IMUX_B13_8", - "PSS1_IMUX_B13_9", - "PSS1_IMUX_B14_0", - "PSS1_IMUX_B14_1", - "PSS1_IMUX_B14_10", - "PSS1_IMUX_B14_11", - "PSS1_IMUX_B14_12", - "PSS1_IMUX_B14_13", - "PSS1_IMUX_B14_14", - "PSS1_IMUX_B14_15", - "PSS1_IMUX_B14_16", - "PSS1_IMUX_B14_17", - "PSS1_IMUX_B14_18", - "PSS1_IMUX_B14_19", - "PSS1_IMUX_B14_2", - "PSS1_IMUX_B14_20", - "PSS1_IMUX_B14_21", - "PSS1_IMUX_B14_22", - "PSS1_IMUX_B14_23", - "PSS1_IMUX_B14_24", - "PSS1_IMUX_B14_25", - "PSS1_IMUX_B14_26", - "PSS1_IMUX_B14_27", - "PSS1_IMUX_B14_28", - "PSS1_IMUX_B14_29", - "PSS1_IMUX_B14_3", - "PSS1_IMUX_B14_30", - "PSS1_IMUX_B14_31", - "PSS1_IMUX_B14_32", - "PSS1_IMUX_B14_33", - "PSS1_IMUX_B14_34", - "PSS1_IMUX_B14_35", - "PSS1_IMUX_B14_36", - "PSS1_IMUX_B14_37", - "PSS1_IMUX_B14_38", - "PSS1_IMUX_B14_39", - "PSS1_IMUX_B14_4", - "PSS1_IMUX_B14_5", - "PSS1_IMUX_B14_6", - "PSS1_IMUX_B14_7", - "PSS1_IMUX_B14_8", - "PSS1_IMUX_B14_9", - "PSS1_IMUX_B15_0", - "PSS1_IMUX_B15_1", - "PSS1_IMUX_B15_10", - "PSS1_IMUX_B15_11", - "PSS1_IMUX_B15_12", - "PSS1_IMUX_B15_13", - "PSS1_IMUX_B15_14", - "PSS1_IMUX_B15_15", - "PSS1_IMUX_B15_16", - "PSS1_IMUX_B15_17", - "PSS1_IMUX_B15_18", - "PSS1_IMUX_B15_19", - "PSS1_IMUX_B15_2", - "PSS1_IMUX_B15_20", - "PSS1_IMUX_B15_21", - "PSS1_IMUX_B15_22", - "PSS1_IMUX_B15_23", - "PSS1_IMUX_B15_24", - "PSS1_IMUX_B15_25", - "PSS1_IMUX_B15_26", - "PSS1_IMUX_B15_27", - "PSS1_IMUX_B15_28", - "PSS1_IMUX_B15_29", - "PSS1_IMUX_B15_3", - "PSS1_IMUX_B15_30", - "PSS1_IMUX_B15_31", - "PSS1_IMUX_B15_32", - "PSS1_IMUX_B15_33", - "PSS1_IMUX_B15_34", - "PSS1_IMUX_B15_35", - "PSS1_IMUX_B15_36", - "PSS1_IMUX_B15_37", - "PSS1_IMUX_B15_38", - "PSS1_IMUX_B15_39", - "PSS1_IMUX_B15_4", - "PSS1_IMUX_B15_5", - "PSS1_IMUX_B15_6", - "PSS1_IMUX_B15_7", - "PSS1_IMUX_B15_8", - "PSS1_IMUX_B15_9", - "PSS1_IMUX_B16_0", - "PSS1_IMUX_B16_1", - "PSS1_IMUX_B16_10", - "PSS1_IMUX_B16_11", - "PSS1_IMUX_B16_12", - "PSS1_IMUX_B16_13", - "PSS1_IMUX_B16_14", - "PSS1_IMUX_B16_15", - "PSS1_IMUX_B16_16", - "PSS1_IMUX_B16_17", - "PSS1_IMUX_B16_18", - "PSS1_IMUX_B16_19", - "PSS1_IMUX_B16_2", - "PSS1_IMUX_B16_20", - "PSS1_IMUX_B16_21", - "PSS1_IMUX_B16_22", - "PSS1_IMUX_B16_23", - "PSS1_IMUX_B16_24", - "PSS1_IMUX_B16_25", - "PSS1_IMUX_B16_26", - "PSS1_IMUX_B16_27", - "PSS1_IMUX_B16_28", - "PSS1_IMUX_B16_29", - "PSS1_IMUX_B16_3", - "PSS1_IMUX_B16_30", - "PSS1_IMUX_B16_31", - "PSS1_IMUX_B16_32", - "PSS1_IMUX_B16_33", - "PSS1_IMUX_B16_34", - "PSS1_IMUX_B16_35", - "PSS1_IMUX_B16_36", - "PSS1_IMUX_B16_37", - "PSS1_IMUX_B16_38", - "PSS1_IMUX_B16_39", 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"PSS1_IMUX_B18_0", - "PSS1_IMUX_B18_1", - "PSS1_IMUX_B18_10", - "PSS1_IMUX_B18_11", - "PSS1_IMUX_B18_12", - "PSS1_IMUX_B18_13", - "PSS1_IMUX_B18_14", - "PSS1_IMUX_B18_15", - "PSS1_IMUX_B18_16", - "PSS1_IMUX_B18_17", - "PSS1_IMUX_B18_18", - "PSS1_IMUX_B18_19", - "PSS1_IMUX_B18_2", - "PSS1_IMUX_B18_20", - "PSS1_IMUX_B18_21", - "PSS1_IMUX_B18_22", - "PSS1_IMUX_B18_23", - "PSS1_IMUX_B18_24", - "PSS1_IMUX_B18_25", - "PSS1_IMUX_B18_26", - "PSS1_IMUX_B18_27", - "PSS1_IMUX_B18_28", - "PSS1_IMUX_B18_29", - "PSS1_IMUX_B18_3", - "PSS1_IMUX_B18_30", - "PSS1_IMUX_B18_31", - "PSS1_IMUX_B18_32", - "PSS1_IMUX_B18_33", - "PSS1_IMUX_B18_34", - "PSS1_IMUX_B18_35", - "PSS1_IMUX_B18_36", - "PSS1_IMUX_B18_37", - "PSS1_IMUX_B18_38", - "PSS1_IMUX_B18_39", - "PSS1_IMUX_B18_4", - "PSS1_IMUX_B18_5", - "PSS1_IMUX_B18_6", - "PSS1_IMUX_B18_7", - "PSS1_IMUX_B18_8", - "PSS1_IMUX_B18_9", - "PSS1_IMUX_B19_0", - "PSS1_IMUX_B19_1", - "PSS1_IMUX_B19_10", - "PSS1_IMUX_B19_11", - "PSS1_IMUX_B19_12", - "PSS1_IMUX_B19_13", - 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"PSS1_IMUX_B1_2", - "PSS1_IMUX_B1_20", - "PSS1_IMUX_B1_21", - "PSS1_IMUX_B1_22", - "PSS1_IMUX_B1_23", - "PSS1_IMUX_B1_24", - "PSS1_IMUX_B1_25", - "PSS1_IMUX_B1_26", - "PSS1_IMUX_B1_27", - "PSS1_IMUX_B1_28", - "PSS1_IMUX_B1_29", - "PSS1_IMUX_B1_3", - "PSS1_IMUX_B1_30", - "PSS1_IMUX_B1_31", - "PSS1_IMUX_B1_32", - "PSS1_IMUX_B1_33", - "PSS1_IMUX_B1_34", - "PSS1_IMUX_B1_35", - "PSS1_IMUX_B1_36", - "PSS1_IMUX_B1_37", - "PSS1_IMUX_B1_38", - "PSS1_IMUX_B1_39", - "PSS1_IMUX_B1_4", - "PSS1_IMUX_B1_5", - "PSS1_IMUX_B1_6", - "PSS1_IMUX_B1_7", - "PSS1_IMUX_B1_8", - "PSS1_IMUX_B1_9", - "PSS1_IMUX_B20_0", - "PSS1_IMUX_B20_1", - "PSS1_IMUX_B20_10", - "PSS1_IMUX_B20_11", - "PSS1_IMUX_B20_12", - "PSS1_IMUX_B20_13", - "PSS1_IMUX_B20_14", - "PSS1_IMUX_B20_15", - "PSS1_IMUX_B20_16", - "PSS1_IMUX_B20_17", - "PSS1_IMUX_B20_18", - "PSS1_IMUX_B20_19", - "PSS1_IMUX_B20_2", - "PSS1_IMUX_B20_20", - "PSS1_IMUX_B20_21", - "PSS1_IMUX_B20_22", - "PSS1_IMUX_B20_23", - "PSS1_IMUX_B20_24", - "PSS1_IMUX_B20_25", - "PSS1_IMUX_B20_26", - "PSS1_IMUX_B20_27", - "PSS1_IMUX_B20_28", - "PSS1_IMUX_B20_29", - "PSS1_IMUX_B20_3", - "PSS1_IMUX_B20_30", - "PSS1_IMUX_B20_31", - "PSS1_IMUX_B20_32", - "PSS1_IMUX_B20_33", - "PSS1_IMUX_B20_34", - "PSS1_IMUX_B20_35", - "PSS1_IMUX_B20_36", - "PSS1_IMUX_B20_37", - "PSS1_IMUX_B20_38", - "PSS1_IMUX_B20_39", - "PSS1_IMUX_B20_4", - "PSS1_IMUX_B20_5", - "PSS1_IMUX_B20_6", - "PSS1_IMUX_B20_7", - "PSS1_IMUX_B20_8", - "PSS1_IMUX_B20_9", - "PSS1_IMUX_B21_0", - "PSS1_IMUX_B21_1", - "PSS1_IMUX_B21_10", - "PSS1_IMUX_B21_11", - "PSS1_IMUX_B21_12", - "PSS1_IMUX_B21_13", - "PSS1_IMUX_B21_14", - "PSS1_IMUX_B21_15", - "PSS1_IMUX_B21_16", - "PSS1_IMUX_B21_17", - "PSS1_IMUX_B21_18", - "PSS1_IMUX_B21_19", - "PSS1_IMUX_B21_2", - "PSS1_IMUX_B21_20", - "PSS1_IMUX_B21_21", - "PSS1_IMUX_B21_22", - "PSS1_IMUX_B21_23", - "PSS1_IMUX_B21_24", - "PSS1_IMUX_B21_25", - "PSS1_IMUX_B21_26", - "PSS1_IMUX_B21_27", - "PSS1_IMUX_B21_28", - "PSS1_IMUX_B21_29", - "PSS1_IMUX_B21_3", - "PSS1_IMUX_B21_30", - "PSS1_IMUX_B21_31", - "PSS1_IMUX_B21_32", - "PSS1_IMUX_B21_33", - "PSS1_IMUX_B21_34", - "PSS1_IMUX_B21_35", - "PSS1_IMUX_B21_36", - "PSS1_IMUX_B21_37", - "PSS1_IMUX_B21_38", - "PSS1_IMUX_B21_39", - "PSS1_IMUX_B21_4", - "PSS1_IMUX_B21_5", - "PSS1_IMUX_B21_6", - "PSS1_IMUX_B21_7", - "PSS1_IMUX_B21_8", - "PSS1_IMUX_B21_9", - "PSS1_IMUX_B22_0", - "PSS1_IMUX_B22_1", - "PSS1_IMUX_B22_10", - "PSS1_IMUX_B22_11", - "PSS1_IMUX_B22_12", - "PSS1_IMUX_B22_13", - "PSS1_IMUX_B22_14", - "PSS1_IMUX_B22_15", - "PSS1_IMUX_B22_16", - "PSS1_IMUX_B22_17", - "PSS1_IMUX_B22_18", - "PSS1_IMUX_B22_19", - "PSS1_IMUX_B22_2", - "PSS1_IMUX_B22_20", - "PSS1_IMUX_B22_21", - "PSS1_IMUX_B22_22", - "PSS1_IMUX_B22_23", - "PSS1_IMUX_B22_24", - "PSS1_IMUX_B22_25", - "PSS1_IMUX_B22_26", - "PSS1_IMUX_B22_27", - "PSS1_IMUX_B22_28", - "PSS1_IMUX_B22_29", - "PSS1_IMUX_B22_3", - "PSS1_IMUX_B22_30", - "PSS1_IMUX_B22_31", - "PSS1_IMUX_B22_32", - "PSS1_IMUX_B22_33", - "PSS1_IMUX_B22_34", - "PSS1_IMUX_B22_35", - "PSS1_IMUX_B22_36", - "PSS1_IMUX_B22_37", - "PSS1_IMUX_B22_38", - "PSS1_IMUX_B22_39", - "PSS1_IMUX_B22_4", - "PSS1_IMUX_B22_5", - "PSS1_IMUX_B22_6", - "PSS1_IMUX_B22_7", - "PSS1_IMUX_B22_8", - "PSS1_IMUX_B22_9", - "PSS1_IMUX_B23_0", - "PSS1_IMUX_B23_1", - "PSS1_IMUX_B23_10", - "PSS1_IMUX_B23_11", - "PSS1_IMUX_B23_12", - "PSS1_IMUX_B23_13", - "PSS1_IMUX_B23_14", - "PSS1_IMUX_B23_15", - "PSS1_IMUX_B23_16", - "PSS1_IMUX_B23_17", - "PSS1_IMUX_B23_18", - "PSS1_IMUX_B23_19", - "PSS1_IMUX_B23_2", - "PSS1_IMUX_B23_20", - "PSS1_IMUX_B23_21", - "PSS1_IMUX_B23_22", - "PSS1_IMUX_B23_23", - "PSS1_IMUX_B23_24", - "PSS1_IMUX_B23_25", - "PSS1_IMUX_B23_26", - "PSS1_IMUX_B23_27", - "PSS1_IMUX_B23_28", - "PSS1_IMUX_B23_29", - "PSS1_IMUX_B23_3", - "PSS1_IMUX_B23_30", - "PSS1_IMUX_B23_31", - "PSS1_IMUX_B23_32", - "PSS1_IMUX_B23_33", - "PSS1_IMUX_B23_34", - "PSS1_IMUX_B23_35", - "PSS1_IMUX_B23_36", - "PSS1_IMUX_B23_37", - "PSS1_IMUX_B23_38", - "PSS1_IMUX_B23_39", - "PSS1_IMUX_B23_4", - "PSS1_IMUX_B23_5", - "PSS1_IMUX_B23_6", - "PSS1_IMUX_B23_7", - "PSS1_IMUX_B23_8", - "PSS1_IMUX_B23_9", - "PSS1_IMUX_B24_0", - "PSS1_IMUX_B24_1", - "PSS1_IMUX_B24_10", - "PSS1_IMUX_B24_11", - "PSS1_IMUX_B24_12", - "PSS1_IMUX_B24_13", - "PSS1_IMUX_B24_14", - "PSS1_IMUX_B24_15", - "PSS1_IMUX_B24_16", - "PSS1_IMUX_B24_17", - "PSS1_IMUX_B24_18", - "PSS1_IMUX_B24_19", - "PSS1_IMUX_B24_2", - "PSS1_IMUX_B24_20", - "PSS1_IMUX_B24_21", - "PSS1_IMUX_B24_22", - "PSS1_IMUX_B24_23", - "PSS1_IMUX_B24_24", - "PSS1_IMUX_B24_25", - "PSS1_IMUX_B24_26", - "PSS1_IMUX_B24_27", - "PSS1_IMUX_B24_28", - "PSS1_IMUX_B24_29", - "PSS1_IMUX_B24_3", - "PSS1_IMUX_B24_30", - "PSS1_IMUX_B24_31", - "PSS1_IMUX_B24_32", - "PSS1_IMUX_B24_33", - "PSS1_IMUX_B24_34", - "PSS1_IMUX_B24_35", - "PSS1_IMUX_B24_36", - "PSS1_IMUX_B24_37", - "PSS1_IMUX_B24_38", - "PSS1_IMUX_B24_39", - "PSS1_IMUX_B24_4", - "PSS1_IMUX_B24_5", - "PSS1_IMUX_B24_6", - "PSS1_IMUX_B24_7", - "PSS1_IMUX_B24_8", - "PSS1_IMUX_B24_9", - "PSS1_IMUX_B25_0", - "PSS1_IMUX_B25_1", - "PSS1_IMUX_B25_10", - "PSS1_IMUX_B25_11", - "PSS1_IMUX_B25_12", - "PSS1_IMUX_B25_13", - "PSS1_IMUX_B25_14", - "PSS1_IMUX_B25_15", - "PSS1_IMUX_B25_16", - "PSS1_IMUX_B25_17", - "PSS1_IMUX_B25_18", - "PSS1_IMUX_B25_19", - "PSS1_IMUX_B25_2", - "PSS1_IMUX_B25_20", - "PSS1_IMUX_B25_21", - "PSS1_IMUX_B25_22", - "PSS1_IMUX_B25_23", - "PSS1_IMUX_B25_24", - "PSS1_IMUX_B25_25", - "PSS1_IMUX_B25_26", - "PSS1_IMUX_B25_27", - "PSS1_IMUX_B25_28", - "PSS1_IMUX_B25_29", - "PSS1_IMUX_B25_3", - "PSS1_IMUX_B25_30", - "PSS1_IMUX_B25_31", - "PSS1_IMUX_B25_32", - "PSS1_IMUX_B25_33", - "PSS1_IMUX_B25_34", - "PSS1_IMUX_B25_35", - "PSS1_IMUX_B25_36", - "PSS1_IMUX_B25_37", - "PSS1_IMUX_B25_38", - "PSS1_IMUX_B25_39", - "PSS1_IMUX_B25_4", - "PSS1_IMUX_B25_5", - "PSS1_IMUX_B25_6", - "PSS1_IMUX_B25_7", - "PSS1_IMUX_B25_8", - "PSS1_IMUX_B25_9", - "PSS1_IMUX_B26_0", - "PSS1_IMUX_B26_1", - "PSS1_IMUX_B26_10", - "PSS1_IMUX_B26_11", - "PSS1_IMUX_B26_12", - "PSS1_IMUX_B26_13", - "PSS1_IMUX_B26_14", - "PSS1_IMUX_B26_15", - "PSS1_IMUX_B26_16", - "PSS1_IMUX_B26_17", - "PSS1_IMUX_B26_18", - "PSS1_IMUX_B26_19", - "PSS1_IMUX_B26_2", - "PSS1_IMUX_B26_20", - "PSS1_IMUX_B26_21", - "PSS1_IMUX_B26_22", - "PSS1_IMUX_B26_23", - "PSS1_IMUX_B26_24", - "PSS1_IMUX_B26_25", - "PSS1_IMUX_B26_26", - "PSS1_IMUX_B26_27", - "PSS1_IMUX_B26_28", - "PSS1_IMUX_B26_29", - "PSS1_IMUX_B26_3", - "PSS1_IMUX_B26_30", - "PSS1_IMUX_B26_31", - "PSS1_IMUX_B26_32", - "PSS1_IMUX_B26_33", - "PSS1_IMUX_B26_34", - "PSS1_IMUX_B26_35", - "PSS1_IMUX_B26_36", - "PSS1_IMUX_B26_37", - "PSS1_IMUX_B26_38", - "PSS1_IMUX_B26_39", - "PSS1_IMUX_B26_4", - "PSS1_IMUX_B26_5", - "PSS1_IMUX_B26_6", - "PSS1_IMUX_B26_7", - "PSS1_IMUX_B26_8", - "PSS1_IMUX_B26_9", - "PSS1_IMUX_B27_0", - "PSS1_IMUX_B27_1", - "PSS1_IMUX_B27_10", - "PSS1_IMUX_B27_11", - "PSS1_IMUX_B27_12", - "PSS1_IMUX_B27_13", - "PSS1_IMUX_B27_14", - "PSS1_IMUX_B27_15", - "PSS1_IMUX_B27_16", - "PSS1_IMUX_B27_17", - "PSS1_IMUX_B27_18", - "PSS1_IMUX_B27_19", - "PSS1_IMUX_B27_2", - "PSS1_IMUX_B27_20", - "PSS1_IMUX_B27_21", - "PSS1_IMUX_B27_22", - "PSS1_IMUX_B27_23", - "PSS1_IMUX_B27_24", - "PSS1_IMUX_B27_25", - "PSS1_IMUX_B27_26", - "PSS1_IMUX_B27_27", - "PSS1_IMUX_B27_28", - "PSS1_IMUX_B27_29", - "PSS1_IMUX_B27_3", - "PSS1_IMUX_B27_30", - "PSS1_IMUX_B27_31", - "PSS1_IMUX_B27_32", - "PSS1_IMUX_B27_33", - "PSS1_IMUX_B27_34", - "PSS1_IMUX_B27_35", - "PSS1_IMUX_B27_36", - "PSS1_IMUX_B27_37", - "PSS1_IMUX_B27_38", - "PSS1_IMUX_B27_39", - "PSS1_IMUX_B27_4", - "PSS1_IMUX_B27_5", - "PSS1_IMUX_B27_6", - "PSS1_IMUX_B27_7", - "PSS1_IMUX_B27_8", - "PSS1_IMUX_B27_9", - "PSS1_IMUX_B28_0", - "PSS1_IMUX_B28_1", - "PSS1_IMUX_B28_10", - "PSS1_IMUX_B28_11", - "PSS1_IMUX_B28_12", - "PSS1_IMUX_B28_13", - "PSS1_IMUX_B28_14", - "PSS1_IMUX_B28_15", - "PSS1_IMUX_B28_16", - "PSS1_IMUX_B28_17", - "PSS1_IMUX_B28_18", - "PSS1_IMUX_B28_19", - "PSS1_IMUX_B28_2", - "PSS1_IMUX_B28_20", - "PSS1_IMUX_B28_21", - "PSS1_IMUX_B28_22", - "PSS1_IMUX_B28_23", - "PSS1_IMUX_B28_24", - "PSS1_IMUX_B28_25", - "PSS1_IMUX_B28_26", - "PSS1_IMUX_B28_27", - "PSS1_IMUX_B28_28", - "PSS1_IMUX_B28_29", - "PSS1_IMUX_B28_3", - "PSS1_IMUX_B28_30", - "PSS1_IMUX_B28_31", - "PSS1_IMUX_B28_32", - "PSS1_IMUX_B28_33", - "PSS1_IMUX_B28_34", - "PSS1_IMUX_B28_35", - "PSS1_IMUX_B28_36", - "PSS1_IMUX_B28_37", - "PSS1_IMUX_B28_38", - "PSS1_IMUX_B28_39", - "PSS1_IMUX_B28_4", - "PSS1_IMUX_B28_5", - "PSS1_IMUX_B28_6", - "PSS1_IMUX_B28_7", - "PSS1_IMUX_B28_8", - "PSS1_IMUX_B28_9", - "PSS1_IMUX_B29_0", - "PSS1_IMUX_B29_1", - "PSS1_IMUX_B29_10", - "PSS1_IMUX_B29_11", - "PSS1_IMUX_B29_12", - "PSS1_IMUX_B29_13", - "PSS1_IMUX_B29_14", - "PSS1_IMUX_B29_15", - "PSS1_IMUX_B29_16", - "PSS1_IMUX_B29_17", - "PSS1_IMUX_B29_18", - "PSS1_IMUX_B29_19", - "PSS1_IMUX_B29_2", - "PSS1_IMUX_B29_20", - "PSS1_IMUX_B29_21", - "PSS1_IMUX_B29_22", - "PSS1_IMUX_B29_23", - "PSS1_IMUX_B29_24", - "PSS1_IMUX_B29_25", - "PSS1_IMUX_B29_26", - "PSS1_IMUX_B29_27", - "PSS1_IMUX_B29_28", - "PSS1_IMUX_B29_29", - "PSS1_IMUX_B29_3", - "PSS1_IMUX_B29_30", - "PSS1_IMUX_B29_31", - "PSS1_IMUX_B29_32", - "PSS1_IMUX_B29_33", - "PSS1_IMUX_B29_34", - "PSS1_IMUX_B29_35", - "PSS1_IMUX_B29_36", - "PSS1_IMUX_B29_37", - "PSS1_IMUX_B29_38", - "PSS1_IMUX_B29_39", - "PSS1_IMUX_B29_4", - "PSS1_IMUX_B29_5", - "PSS1_IMUX_B29_6", - "PSS1_IMUX_B29_7", - "PSS1_IMUX_B29_8", - "PSS1_IMUX_B29_9", - "PSS1_IMUX_B2_0", - "PSS1_IMUX_B2_1", - "PSS1_IMUX_B2_10", - "PSS1_IMUX_B2_11", - "PSS1_IMUX_B2_12", - "PSS1_IMUX_B2_13", - "PSS1_IMUX_B2_14", - "PSS1_IMUX_B2_15", - "PSS1_IMUX_B2_16", - "PSS1_IMUX_B2_17", - "PSS1_IMUX_B2_18", - "PSS1_IMUX_B2_19", - "PSS1_IMUX_B2_2", - "PSS1_IMUX_B2_20", - "PSS1_IMUX_B2_21", - "PSS1_IMUX_B2_22", - "PSS1_IMUX_B2_23", - "PSS1_IMUX_B2_24", - "PSS1_IMUX_B2_25", - "PSS1_IMUX_B2_26", - "PSS1_IMUX_B2_27", - "PSS1_IMUX_B2_28", - "PSS1_IMUX_B2_29", - "PSS1_IMUX_B2_3", - "PSS1_IMUX_B2_30", - "PSS1_IMUX_B2_31", - "PSS1_IMUX_B2_32", - "PSS1_IMUX_B2_33", - "PSS1_IMUX_B2_34", - "PSS1_IMUX_B2_35", - "PSS1_IMUX_B2_36", - "PSS1_IMUX_B2_37", - "PSS1_IMUX_B2_38", - "PSS1_IMUX_B2_39", - "PSS1_IMUX_B2_4", - "PSS1_IMUX_B2_5", - "PSS1_IMUX_B2_6", - "PSS1_IMUX_B2_7", - "PSS1_IMUX_B2_8", - "PSS1_IMUX_B2_9", - "PSS1_IMUX_B30_0", - "PSS1_IMUX_B30_1", - "PSS1_IMUX_B30_10", - "PSS1_IMUX_B30_11", - "PSS1_IMUX_B30_12", - "PSS1_IMUX_B30_13", - "PSS1_IMUX_B30_14", - "PSS1_IMUX_B30_15", - "PSS1_IMUX_B30_16", - "PSS1_IMUX_B30_17", - "PSS1_IMUX_B30_18", - "PSS1_IMUX_B30_19", - "PSS1_IMUX_B30_2", - "PSS1_IMUX_B30_20", - "PSS1_IMUX_B30_21", - "PSS1_IMUX_B30_22", - "PSS1_IMUX_B30_23", - "PSS1_IMUX_B30_24", - "PSS1_IMUX_B30_25", - "PSS1_IMUX_B30_26", - "PSS1_IMUX_B30_27", - "PSS1_IMUX_B30_28", - "PSS1_IMUX_B30_29", - "PSS1_IMUX_B30_3", - "PSS1_IMUX_B30_30", - "PSS1_IMUX_B30_31", - "PSS1_IMUX_B30_32", - "PSS1_IMUX_B30_33", - "PSS1_IMUX_B30_34", - "PSS1_IMUX_B30_35", - "PSS1_IMUX_B30_36", - "PSS1_IMUX_B30_37", - "PSS1_IMUX_B30_38", - "PSS1_IMUX_B30_39", - "PSS1_IMUX_B30_4", - "PSS1_IMUX_B30_5", - "PSS1_IMUX_B30_6", - "PSS1_IMUX_B30_7", - "PSS1_IMUX_B30_8", - "PSS1_IMUX_B30_9", - "PSS1_IMUX_B31_0", - "PSS1_IMUX_B31_1", - "PSS1_IMUX_B31_10", - "PSS1_IMUX_B31_11", - "PSS1_IMUX_B31_12", - "PSS1_IMUX_B31_13", - "PSS1_IMUX_B31_14", - "PSS1_IMUX_B31_15", - "PSS1_IMUX_B31_16", - "PSS1_IMUX_B31_17", - "PSS1_IMUX_B31_18", - "PSS1_IMUX_B31_19", - "PSS1_IMUX_B31_2", - "PSS1_IMUX_B31_20", - "PSS1_IMUX_B31_21", - "PSS1_IMUX_B31_22", - "PSS1_IMUX_B31_23", - "PSS1_IMUX_B31_24", - "PSS1_IMUX_B31_25", - "PSS1_IMUX_B31_26", - "PSS1_IMUX_B31_27", - "PSS1_IMUX_B31_28", - "PSS1_IMUX_B31_29", - "PSS1_IMUX_B31_3", - "PSS1_IMUX_B31_30", - "PSS1_IMUX_B31_31", - "PSS1_IMUX_B31_32", - "PSS1_IMUX_B31_33", - "PSS1_IMUX_B31_34", - "PSS1_IMUX_B31_35", - "PSS1_IMUX_B31_36", - "PSS1_IMUX_B31_37", - "PSS1_IMUX_B31_38", - "PSS1_IMUX_B31_39", - "PSS1_IMUX_B31_4", - "PSS1_IMUX_B31_5", - "PSS1_IMUX_B31_6", - "PSS1_IMUX_B31_7", - "PSS1_IMUX_B31_8", - "PSS1_IMUX_B31_9", - "PSS1_IMUX_B32_0", - "PSS1_IMUX_B32_1", - "PSS1_IMUX_B32_10", - "PSS1_IMUX_B32_11", - "PSS1_IMUX_B32_12", - "PSS1_IMUX_B32_13", - "PSS1_IMUX_B32_14", - "PSS1_IMUX_B32_15", - "PSS1_IMUX_B32_16", - "PSS1_IMUX_B32_17", - "PSS1_IMUX_B32_18", - "PSS1_IMUX_B32_19", - "PSS1_IMUX_B32_2", - "PSS1_IMUX_B32_20", - "PSS1_IMUX_B32_21", - "PSS1_IMUX_B32_22", - "PSS1_IMUX_B32_23", - "PSS1_IMUX_B32_24", - "PSS1_IMUX_B32_25", - "PSS1_IMUX_B32_26", - "PSS1_IMUX_B32_27", - "PSS1_IMUX_B32_28", - "PSS1_IMUX_B32_29", - "PSS1_IMUX_B32_3", - "PSS1_IMUX_B32_30", - "PSS1_IMUX_B32_31", - "PSS1_IMUX_B32_32", - "PSS1_IMUX_B32_33", - "PSS1_IMUX_B32_34", - "PSS1_IMUX_B32_35", - "PSS1_IMUX_B32_36", - "PSS1_IMUX_B32_37", - "PSS1_IMUX_B32_38", - "PSS1_IMUX_B32_39", - "PSS1_IMUX_B32_4", - "PSS1_IMUX_B32_5", - "PSS1_IMUX_B32_6", - "PSS1_IMUX_B32_7", - "PSS1_IMUX_B32_8", - "PSS1_IMUX_B32_9", - "PSS1_IMUX_B33_0", - "PSS1_IMUX_B33_1", - "PSS1_IMUX_B33_10", - "PSS1_IMUX_B33_11", - "PSS1_IMUX_B33_12", - "PSS1_IMUX_B33_13", - "PSS1_IMUX_B33_14", - "PSS1_IMUX_B33_15", - "PSS1_IMUX_B33_16", - "PSS1_IMUX_B33_17", - "PSS1_IMUX_B33_18", - "PSS1_IMUX_B33_19", - "PSS1_IMUX_B33_2", - "PSS1_IMUX_B33_20", - "PSS1_IMUX_B33_21", - "PSS1_IMUX_B33_22", - "PSS1_IMUX_B33_23", - "PSS1_IMUX_B33_24", - "PSS1_IMUX_B33_25", - "PSS1_IMUX_B33_26", - "PSS1_IMUX_B33_27", - "PSS1_IMUX_B33_28", - "PSS1_IMUX_B33_29", - "PSS1_IMUX_B33_3", - "PSS1_IMUX_B33_30", - "PSS1_IMUX_B33_31", - "PSS1_IMUX_B33_32", - "PSS1_IMUX_B33_33", - "PSS1_IMUX_B33_34", - "PSS1_IMUX_B33_35", - "PSS1_IMUX_B33_36", - "PSS1_IMUX_B33_37", - "PSS1_IMUX_B33_38", - "PSS1_IMUX_B33_39", - "PSS1_IMUX_B33_4", - "PSS1_IMUX_B33_5", - "PSS1_IMUX_B33_6", - "PSS1_IMUX_B33_7", - "PSS1_IMUX_B33_8", - "PSS1_IMUX_B33_9", - "PSS1_IMUX_B34_0", - "PSS1_IMUX_B34_1", - "PSS1_IMUX_B34_10", - "PSS1_IMUX_B34_11", - "PSS1_IMUX_B34_12", - "PSS1_IMUX_B34_13", - "PSS1_IMUX_B34_14", - "PSS1_IMUX_B34_15", - "PSS1_IMUX_B34_16", - "PSS1_IMUX_B34_17", - "PSS1_IMUX_B34_18", - "PSS1_IMUX_B34_19", - "PSS1_IMUX_B34_2", - "PSS1_IMUX_B34_20", - "PSS1_IMUX_B34_21", - "PSS1_IMUX_B34_22", - "PSS1_IMUX_B34_23", - "PSS1_IMUX_B34_24", - "PSS1_IMUX_B34_25", - "PSS1_IMUX_B34_26", - "PSS1_IMUX_B34_27", - "PSS1_IMUX_B34_28", - "PSS1_IMUX_B34_29", - "PSS1_IMUX_B34_3", - "PSS1_IMUX_B34_30", - "PSS1_IMUX_B34_31", - "PSS1_IMUX_B34_32", - "PSS1_IMUX_B34_33", - "PSS1_IMUX_B34_34", - "PSS1_IMUX_B34_35", - "PSS1_IMUX_B34_36", - "PSS1_IMUX_B34_37", - "PSS1_IMUX_B34_38", - "PSS1_IMUX_B34_39", - "PSS1_IMUX_B34_4", - "PSS1_IMUX_B34_5", - "PSS1_IMUX_B34_6", - "PSS1_IMUX_B34_7", - "PSS1_IMUX_B34_8", - "PSS1_IMUX_B34_9", - "PSS1_IMUX_B35_0", - "PSS1_IMUX_B35_1", - "PSS1_IMUX_B35_10", - "PSS1_IMUX_B35_11", - "PSS1_IMUX_B35_12", - "PSS1_IMUX_B35_13", - "PSS1_IMUX_B35_14", - "PSS1_IMUX_B35_15", - "PSS1_IMUX_B35_16", - "PSS1_IMUX_B35_17", - "PSS1_IMUX_B35_18", - "PSS1_IMUX_B35_19", - "PSS1_IMUX_B35_2", - "PSS1_IMUX_B35_20", - "PSS1_IMUX_B35_21", - "PSS1_IMUX_B35_22", - "PSS1_IMUX_B35_23", - "PSS1_IMUX_B35_24", - "PSS1_IMUX_B35_25", - "PSS1_IMUX_B35_26", - "PSS1_IMUX_B35_27", - "PSS1_IMUX_B35_28", - "PSS1_IMUX_B35_29", - "PSS1_IMUX_B35_3", - "PSS1_IMUX_B35_30", - "PSS1_IMUX_B35_31", - "PSS1_IMUX_B35_32", - "PSS1_IMUX_B35_33", - "PSS1_IMUX_B35_34", - "PSS1_IMUX_B35_35", - "PSS1_IMUX_B35_36", - "PSS1_IMUX_B35_37", - "PSS1_IMUX_B35_38", - "PSS1_IMUX_B35_39", - "PSS1_IMUX_B35_4", - "PSS1_IMUX_B35_5", - "PSS1_IMUX_B35_6", - "PSS1_IMUX_B35_7", - "PSS1_IMUX_B35_8", - "PSS1_IMUX_B35_9", - "PSS1_IMUX_B36_0", - "PSS1_IMUX_B36_1", - "PSS1_IMUX_B36_10", - "PSS1_IMUX_B36_11", - "PSS1_IMUX_B36_12", - "PSS1_IMUX_B36_13", - "PSS1_IMUX_B36_14", - "PSS1_IMUX_B36_15", - "PSS1_IMUX_B36_16", - "PSS1_IMUX_B36_17", - "PSS1_IMUX_B36_18", - "PSS1_IMUX_B36_19", - "PSS1_IMUX_B36_2", - "PSS1_IMUX_B36_20", - "PSS1_IMUX_B36_21", - "PSS1_IMUX_B36_22", - "PSS1_IMUX_B36_23", - "PSS1_IMUX_B36_24", - "PSS1_IMUX_B36_25", - "PSS1_IMUX_B36_26", - "PSS1_IMUX_B36_27", - "PSS1_IMUX_B36_28", - "PSS1_IMUX_B36_29", - "PSS1_IMUX_B36_3", - "PSS1_IMUX_B36_30", - "PSS1_IMUX_B36_31", - "PSS1_IMUX_B36_32", - "PSS1_IMUX_B36_33", - "PSS1_IMUX_B36_34", - "PSS1_IMUX_B36_35", - "PSS1_IMUX_B36_36", - "PSS1_IMUX_B36_37", - "PSS1_IMUX_B36_38", - "PSS1_IMUX_B36_39", - "PSS1_IMUX_B36_4", - "PSS1_IMUX_B36_5", - "PSS1_IMUX_B36_6", - "PSS1_IMUX_B36_7", - "PSS1_IMUX_B36_8", - "PSS1_IMUX_B36_9", - "PSS1_IMUX_B37_0", - "PSS1_IMUX_B37_1", - "PSS1_IMUX_B37_10", - "PSS1_IMUX_B37_11", - "PSS1_IMUX_B37_12", - "PSS1_IMUX_B37_13", - "PSS1_IMUX_B37_14", - "PSS1_IMUX_B37_15", - "PSS1_IMUX_B37_16", - "PSS1_IMUX_B37_17", - "PSS1_IMUX_B37_18", - "PSS1_IMUX_B37_19", - "PSS1_IMUX_B37_2", - "PSS1_IMUX_B37_20", - "PSS1_IMUX_B37_21", - "PSS1_IMUX_B37_22", - "PSS1_IMUX_B37_23", - "PSS1_IMUX_B37_24", - "PSS1_IMUX_B37_25", - "PSS1_IMUX_B37_26", - "PSS1_IMUX_B37_27", - "PSS1_IMUX_B37_28", - "PSS1_IMUX_B37_29", - "PSS1_IMUX_B37_3", - "PSS1_IMUX_B37_30", - "PSS1_IMUX_B37_31", - "PSS1_IMUX_B37_32", - "PSS1_IMUX_B37_33", - "PSS1_IMUX_B37_34", - "PSS1_IMUX_B37_35", - "PSS1_IMUX_B37_36", - "PSS1_IMUX_B37_37", - "PSS1_IMUX_B37_38", - "PSS1_IMUX_B37_39", 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"PSS1_IMUX_B39_0", - "PSS1_IMUX_B39_1", - "PSS1_IMUX_B39_10", - "PSS1_IMUX_B39_11", - "PSS1_IMUX_B39_12", - "PSS1_IMUX_B39_13", - "PSS1_IMUX_B39_14", - "PSS1_IMUX_B39_15", - "PSS1_IMUX_B39_16", - "PSS1_IMUX_B39_17", - "PSS1_IMUX_B39_18", - "PSS1_IMUX_B39_19", - "PSS1_IMUX_B39_2", - "PSS1_IMUX_B39_20", - "PSS1_IMUX_B39_21", - "PSS1_IMUX_B39_22", - "PSS1_IMUX_B39_23", - "PSS1_IMUX_B39_24", - "PSS1_IMUX_B39_25", - "PSS1_IMUX_B39_26", - "PSS1_IMUX_B39_27", - "PSS1_IMUX_B39_28", - "PSS1_IMUX_B39_29", - "PSS1_IMUX_B39_3", - "PSS1_IMUX_B39_30", - "PSS1_IMUX_B39_31", - "PSS1_IMUX_B39_32", - "PSS1_IMUX_B39_33", - "PSS1_IMUX_B39_34", - "PSS1_IMUX_B39_35", - "PSS1_IMUX_B39_36", - "PSS1_IMUX_B39_37", - "PSS1_IMUX_B39_38", - "PSS1_IMUX_B39_39", - "PSS1_IMUX_B39_4", - "PSS1_IMUX_B39_5", - "PSS1_IMUX_B39_6", - "PSS1_IMUX_B39_7", - "PSS1_IMUX_B39_8", - "PSS1_IMUX_B39_9", - "PSS1_IMUX_B3_0", - "PSS1_IMUX_B3_1", - "PSS1_IMUX_B3_10", - "PSS1_IMUX_B3_11", - "PSS1_IMUX_B3_12", - "PSS1_IMUX_B3_13", - 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"PSS1_IMUX_B40_20", - "PSS1_IMUX_B40_21", - "PSS1_IMUX_B40_22", - "PSS1_IMUX_B40_23", - "PSS1_IMUX_B40_24", - "PSS1_IMUX_B40_25", - "PSS1_IMUX_B40_26", - "PSS1_IMUX_B40_27", - "PSS1_IMUX_B40_28", - "PSS1_IMUX_B40_29", - "PSS1_IMUX_B40_3", - "PSS1_IMUX_B40_30", - "PSS1_IMUX_B40_31", - "PSS1_IMUX_B40_32", - "PSS1_IMUX_B40_33", - "PSS1_IMUX_B40_34", - "PSS1_IMUX_B40_35", - "PSS1_IMUX_B40_36", - "PSS1_IMUX_B40_37", - "PSS1_IMUX_B40_38", - "PSS1_IMUX_B40_39", - "PSS1_IMUX_B40_4", - "PSS1_IMUX_B40_5", - "PSS1_IMUX_B40_6", - "PSS1_IMUX_B40_7", - "PSS1_IMUX_B40_8", - "PSS1_IMUX_B40_9", - "PSS1_IMUX_B41_0", - "PSS1_IMUX_B41_1", - "PSS1_IMUX_B41_10", - "PSS1_IMUX_B41_11", - "PSS1_IMUX_B41_12", - "PSS1_IMUX_B41_13", - "PSS1_IMUX_B41_14", - "PSS1_IMUX_B41_15", - "PSS1_IMUX_B41_16", - "PSS1_IMUX_B41_17", - "PSS1_IMUX_B41_18", - "PSS1_IMUX_B41_19", - "PSS1_IMUX_B41_2", - "PSS1_IMUX_B41_20", - "PSS1_IMUX_B41_21", - "PSS1_IMUX_B41_22", - "PSS1_IMUX_B41_23", - "PSS1_IMUX_B41_24", - "PSS1_IMUX_B41_25", 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"PSS1_IMUX_B44_6", - "PSS1_IMUX_B44_7", - "PSS1_IMUX_B44_8", - "PSS1_IMUX_B44_9", - "PSS1_IMUX_B45_0", - "PSS1_IMUX_B45_1", - "PSS1_IMUX_B45_10", - "PSS1_IMUX_B45_11", - "PSS1_IMUX_B45_12", - "PSS1_IMUX_B45_13", - "PSS1_IMUX_B45_14", - "PSS1_IMUX_B45_15", - "PSS1_IMUX_B45_16", - "PSS1_IMUX_B45_17", - "PSS1_IMUX_B45_18", - "PSS1_IMUX_B45_19", - "PSS1_IMUX_B45_2", - "PSS1_IMUX_B45_20", - "PSS1_IMUX_B45_21", - "PSS1_IMUX_B45_22", - "PSS1_IMUX_B45_23", - "PSS1_IMUX_B45_24", - "PSS1_IMUX_B45_25", - "PSS1_IMUX_B45_26", - "PSS1_IMUX_B45_27", - "PSS1_IMUX_B45_28", - "PSS1_IMUX_B45_29", - "PSS1_IMUX_B45_3", - "PSS1_IMUX_B45_30", - "PSS1_IMUX_B45_31", - "PSS1_IMUX_B45_32", - "PSS1_IMUX_B45_33", - "PSS1_IMUX_B45_34", - "PSS1_IMUX_B45_35", - "PSS1_IMUX_B45_36", - "PSS1_IMUX_B45_37", - "PSS1_IMUX_B45_38", - "PSS1_IMUX_B45_39", - "PSS1_IMUX_B45_4", - "PSS1_IMUX_B45_5", - "PSS1_IMUX_B45_6", - "PSS1_IMUX_B45_7", - "PSS1_IMUX_B45_8", - "PSS1_IMUX_B45_9", - "PSS1_IMUX_B46_0", - "PSS1_IMUX_B46_1", - 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"PSS1_IMUX_B4_21", - "PSS1_IMUX_B4_22", - "PSS1_IMUX_B4_23", - "PSS1_IMUX_B4_24", - "PSS1_IMUX_B4_25", - "PSS1_IMUX_B4_26", - "PSS1_IMUX_B4_27", - "PSS1_IMUX_B4_28", - "PSS1_IMUX_B4_29", - "PSS1_IMUX_B4_3", - "PSS1_IMUX_B4_30", - "PSS1_IMUX_B4_31", - "PSS1_IMUX_B4_32", - "PSS1_IMUX_B4_33", - "PSS1_IMUX_B4_34", - "PSS1_IMUX_B4_35", - "PSS1_IMUX_B4_36", - "PSS1_IMUX_B4_37", - "PSS1_IMUX_B4_38", - "PSS1_IMUX_B4_39", - "PSS1_IMUX_B4_4", - "PSS1_IMUX_B4_5", - "PSS1_IMUX_B4_6", - "PSS1_IMUX_B4_7", - "PSS1_IMUX_B4_8", - "PSS1_IMUX_B4_9", - "PSS1_IMUX_B5_0", - "PSS1_IMUX_B5_1", - "PSS1_IMUX_B5_10", - "PSS1_IMUX_B5_11", - "PSS1_IMUX_B5_12", - "PSS1_IMUX_B5_13", - "PSS1_IMUX_B5_14", - "PSS1_IMUX_B5_15", - "PSS1_IMUX_B5_16", - "PSS1_IMUX_B5_17", - "PSS1_IMUX_B5_18", - "PSS1_IMUX_B5_19", - "PSS1_IMUX_B5_2", - "PSS1_IMUX_B5_20", - "PSS1_IMUX_B5_21", - "PSS1_IMUX_B5_22", - "PSS1_IMUX_B5_23", - "PSS1_IMUX_B5_24", - "PSS1_IMUX_B5_25", - "PSS1_IMUX_B5_26", - "PSS1_IMUX_B5_27", - "PSS1_IMUX_B5_28", - "PSS1_IMUX_B5_29", - "PSS1_IMUX_B5_3", - "PSS1_IMUX_B5_30", - "PSS1_IMUX_B5_31", - "PSS1_IMUX_B5_32", - "PSS1_IMUX_B5_33", - "PSS1_IMUX_B5_34", - "PSS1_IMUX_B5_35", - "PSS1_IMUX_B5_36", - "PSS1_IMUX_B5_37", - "PSS1_IMUX_B5_38", - "PSS1_IMUX_B5_39", - "PSS1_IMUX_B5_4", - "PSS1_IMUX_B5_5", - "PSS1_IMUX_B5_6", - "PSS1_IMUX_B5_7", - "PSS1_IMUX_B5_8", - "PSS1_IMUX_B5_9", - "PSS1_IMUX_B6_0", - "PSS1_IMUX_B6_1", - "PSS1_IMUX_B6_10", - "PSS1_IMUX_B6_11", - "PSS1_IMUX_B6_12", - "PSS1_IMUX_B6_13", - "PSS1_IMUX_B6_14", - "PSS1_IMUX_B6_15", - "PSS1_IMUX_B6_16", - "PSS1_IMUX_B6_17", - "PSS1_IMUX_B6_18", - "PSS1_IMUX_B6_19", - "PSS1_IMUX_B6_2", - "PSS1_IMUX_B6_20", - "PSS1_IMUX_B6_21", - "PSS1_IMUX_B6_22", - "PSS1_IMUX_B6_23", - "PSS1_IMUX_B6_24", - "PSS1_IMUX_B6_25", - "PSS1_IMUX_B6_26", - "PSS1_IMUX_B6_27", - "PSS1_IMUX_B6_28", - "PSS1_IMUX_B6_29", - "PSS1_IMUX_B6_3", - "PSS1_IMUX_B6_30", - "PSS1_IMUX_B6_31", - "PSS1_IMUX_B6_32", - "PSS1_IMUX_B6_33", - "PSS1_IMUX_B6_34", - "PSS1_IMUX_B6_35", - "PSS1_IMUX_B6_36", - "PSS1_IMUX_B6_37", - "PSS1_IMUX_B6_38", - "PSS1_IMUX_B6_39", - "PSS1_IMUX_B6_4", - "PSS1_IMUX_B6_5", - "PSS1_IMUX_B6_6", - "PSS1_IMUX_B6_7", - "PSS1_IMUX_B6_8", - "PSS1_IMUX_B6_9", - "PSS1_IMUX_B7_0", - "PSS1_IMUX_B7_1", - "PSS1_IMUX_B7_10", - "PSS1_IMUX_B7_11", - "PSS1_IMUX_B7_12", - "PSS1_IMUX_B7_13", - "PSS1_IMUX_B7_14", - "PSS1_IMUX_B7_15", - "PSS1_IMUX_B7_16", - "PSS1_IMUX_B7_17", - "PSS1_IMUX_B7_18", - "PSS1_IMUX_B7_19", - "PSS1_IMUX_B7_2", - "PSS1_IMUX_B7_20", - "PSS1_IMUX_B7_21", - "PSS1_IMUX_B7_22", - "PSS1_IMUX_B7_23", - "PSS1_IMUX_B7_24", - "PSS1_IMUX_B7_25", - "PSS1_IMUX_B7_26", - "PSS1_IMUX_B7_27", - "PSS1_IMUX_B7_28", - "PSS1_IMUX_B7_29", - "PSS1_IMUX_B7_3", - "PSS1_IMUX_B7_30", - "PSS1_IMUX_B7_31", - "PSS1_IMUX_B7_32", - "PSS1_IMUX_B7_33", - "PSS1_IMUX_B7_34", - "PSS1_IMUX_B7_35", - "PSS1_IMUX_B7_36", - "PSS1_IMUX_B7_37", - "PSS1_IMUX_B7_38", - "PSS1_IMUX_B7_39", - "PSS1_IMUX_B7_4", - "PSS1_IMUX_B7_5", - "PSS1_IMUX_B7_6", - "PSS1_IMUX_B7_7", - "PSS1_IMUX_B7_8", - "PSS1_IMUX_B7_9", - "PSS1_IMUX_B8_0", - "PSS1_IMUX_B8_1", - "PSS1_IMUX_B8_10", - "PSS1_IMUX_B8_11", - "PSS1_IMUX_B8_12", - "PSS1_IMUX_B8_13", - "PSS1_IMUX_B8_14", - "PSS1_IMUX_B8_15", - "PSS1_IMUX_B8_16", - "PSS1_IMUX_B8_17", - "PSS1_IMUX_B8_18", - "PSS1_IMUX_B8_19", - "PSS1_IMUX_B8_2", - "PSS1_IMUX_B8_20", - "PSS1_IMUX_B8_21", - "PSS1_IMUX_B8_22", - "PSS1_IMUX_B8_23", - "PSS1_IMUX_B8_24", - "PSS1_IMUX_B8_25", - "PSS1_IMUX_B8_26", - "PSS1_IMUX_B8_27", - "PSS1_IMUX_B8_28", - "PSS1_IMUX_B8_29", - "PSS1_IMUX_B8_3", - "PSS1_IMUX_B8_30", - "PSS1_IMUX_B8_31", - "PSS1_IMUX_B8_32", - "PSS1_IMUX_B8_33", - "PSS1_IMUX_B8_34", - "PSS1_IMUX_B8_35", - "PSS1_IMUX_B8_36", - "PSS1_IMUX_B8_37", - "PSS1_IMUX_B8_38", - "PSS1_IMUX_B8_39", - "PSS1_IMUX_B8_4", - "PSS1_IMUX_B8_5", - "PSS1_IMUX_B8_6", - "PSS1_IMUX_B8_7", - "PSS1_IMUX_B8_8", - "PSS1_IMUX_B8_9", - "PSS1_IMUX_B9_0", - "PSS1_IMUX_B9_1", - "PSS1_IMUX_B9_10", - "PSS1_IMUX_B9_11", - "PSS1_IMUX_B9_12", - "PSS1_IMUX_B9_13", - "PSS1_IMUX_B9_14", - "PSS1_IMUX_B9_15", - "PSS1_IMUX_B9_16", - "PSS1_IMUX_B9_17", - "PSS1_IMUX_B9_18", - "PSS1_IMUX_B9_19", - "PSS1_IMUX_B9_2", - "PSS1_IMUX_B9_20", - "PSS1_IMUX_B9_21", - "PSS1_IMUX_B9_22", - "PSS1_IMUX_B9_23", - "PSS1_IMUX_B9_24", - "PSS1_IMUX_B9_25", - "PSS1_IMUX_B9_26", - "PSS1_IMUX_B9_27", - "PSS1_IMUX_B9_28", - "PSS1_IMUX_B9_29", - "PSS1_IMUX_B9_3", - "PSS1_IMUX_B9_30", - "PSS1_IMUX_B9_31", - "PSS1_IMUX_B9_32", - "PSS1_IMUX_B9_33", - "PSS1_IMUX_B9_34", - "PSS1_IMUX_B9_35", - "PSS1_IMUX_B9_36", - "PSS1_IMUX_B9_37", - "PSS1_IMUX_B9_38", - "PSS1_IMUX_B9_39", - "PSS1_IMUX_B9_4", - "PSS1_IMUX_B9_5", - "PSS1_IMUX_B9_6", - "PSS1_IMUX_B9_7", - "PSS1_IMUX_B9_8", - "PSS1_IMUX_B9_9", - "PSS1_LOGIC_OUTS0_0", - "PSS1_LOGIC_OUTS0_1", - "PSS1_LOGIC_OUTS0_10", - "PSS1_LOGIC_OUTS0_11", - "PSS1_LOGIC_OUTS0_12", - "PSS1_LOGIC_OUTS0_13", - "PSS1_LOGIC_OUTS0_14", - "PSS1_LOGIC_OUTS0_15", - "PSS1_LOGIC_OUTS0_16", - "PSS1_LOGIC_OUTS0_17", - "PSS1_LOGIC_OUTS0_18", - "PSS1_LOGIC_OUTS0_19", - "PSS1_LOGIC_OUTS0_2", - "PSS1_LOGIC_OUTS0_20", - "PSS1_LOGIC_OUTS0_21", - "PSS1_LOGIC_OUTS0_22", - "PSS1_LOGIC_OUTS0_23", - "PSS1_LOGIC_OUTS0_24", - "PSS1_LOGIC_OUTS0_25", - "PSS1_LOGIC_OUTS0_26", - "PSS1_LOGIC_OUTS0_27", - "PSS1_LOGIC_OUTS0_28", - "PSS1_LOGIC_OUTS0_29", - "PSS1_LOGIC_OUTS0_3", - "PSS1_LOGIC_OUTS0_30", - "PSS1_LOGIC_OUTS0_31", - "PSS1_LOGIC_OUTS0_32", - "PSS1_LOGIC_OUTS0_33", - "PSS1_LOGIC_OUTS0_34", - "PSS1_LOGIC_OUTS0_35", - "PSS1_LOGIC_OUTS0_36", - "PSS1_LOGIC_OUTS0_37", - "PSS1_LOGIC_OUTS0_38", - "PSS1_LOGIC_OUTS0_39", - "PSS1_LOGIC_OUTS0_4", - "PSS1_LOGIC_OUTS0_5", - "PSS1_LOGIC_OUTS0_6", - "PSS1_LOGIC_OUTS0_7", - "PSS1_LOGIC_OUTS0_8", - "PSS1_LOGIC_OUTS0_9", - "PSS1_LOGIC_OUTS10_0", - "PSS1_LOGIC_OUTS10_1", - "PSS1_LOGIC_OUTS10_10", - "PSS1_LOGIC_OUTS10_11", - "PSS1_LOGIC_OUTS10_12", - "PSS1_LOGIC_OUTS10_13", - "PSS1_LOGIC_OUTS10_14", - "PSS1_LOGIC_OUTS10_15", - "PSS1_LOGIC_OUTS10_16", - "PSS1_LOGIC_OUTS10_17", - "PSS1_LOGIC_OUTS10_18", - "PSS1_LOGIC_OUTS10_19", - "PSS1_LOGIC_OUTS10_2", - "PSS1_LOGIC_OUTS10_20", - "PSS1_LOGIC_OUTS10_21", - "PSS1_LOGIC_OUTS10_22", - "PSS1_LOGIC_OUTS10_23", - "PSS1_LOGIC_OUTS10_24", - "PSS1_LOGIC_OUTS10_25", - "PSS1_LOGIC_OUTS10_26", - "PSS1_LOGIC_OUTS10_27", - "PSS1_LOGIC_OUTS10_28", - "PSS1_LOGIC_OUTS10_29", - "PSS1_LOGIC_OUTS10_3", - "PSS1_LOGIC_OUTS10_30", - "PSS1_LOGIC_OUTS10_31", - "PSS1_LOGIC_OUTS10_32", - "PSS1_LOGIC_OUTS10_33", - "PSS1_LOGIC_OUTS10_34", - "PSS1_LOGIC_OUTS10_35", - "PSS1_LOGIC_OUTS10_36", - "PSS1_LOGIC_OUTS10_37", - "PSS1_LOGIC_OUTS10_38", - "PSS1_LOGIC_OUTS10_39", - "PSS1_LOGIC_OUTS10_4", - "PSS1_LOGIC_OUTS10_5", - "PSS1_LOGIC_OUTS10_6", - "PSS1_LOGIC_OUTS10_7", - "PSS1_LOGIC_OUTS10_8", - "PSS1_LOGIC_OUTS10_9", - "PSS1_LOGIC_OUTS11_0", - "PSS1_LOGIC_OUTS11_1", - "PSS1_LOGIC_OUTS11_10", - "PSS1_LOGIC_OUTS11_11", - "PSS1_LOGIC_OUTS11_12", - "PSS1_LOGIC_OUTS11_13", - "PSS1_LOGIC_OUTS11_14", - "PSS1_LOGIC_OUTS11_15", - "PSS1_LOGIC_OUTS11_16", - "PSS1_LOGIC_OUTS11_17", - "PSS1_LOGIC_OUTS11_18", - "PSS1_LOGIC_OUTS11_19", - "PSS1_LOGIC_OUTS11_2", - "PSS1_LOGIC_OUTS11_20", - "PSS1_LOGIC_OUTS11_21", - "PSS1_LOGIC_OUTS11_22", - "PSS1_LOGIC_OUTS11_23", - "PSS1_LOGIC_OUTS11_24", - "PSS1_LOGIC_OUTS11_25", - "PSS1_LOGIC_OUTS11_26", - "PSS1_LOGIC_OUTS11_27", - "PSS1_LOGIC_OUTS11_28", - "PSS1_LOGIC_OUTS11_29", - "PSS1_LOGIC_OUTS11_3", - "PSS1_LOGIC_OUTS11_30", - "PSS1_LOGIC_OUTS11_31", - "PSS1_LOGIC_OUTS11_32", - "PSS1_LOGIC_OUTS11_33", - "PSS1_LOGIC_OUTS11_34", - "PSS1_LOGIC_OUTS11_35", - "PSS1_LOGIC_OUTS11_36", - "PSS1_LOGIC_OUTS11_37", - "PSS1_LOGIC_OUTS11_38", - "PSS1_LOGIC_OUTS11_39", - "PSS1_LOGIC_OUTS11_4", - "PSS1_LOGIC_OUTS11_5", - "PSS1_LOGIC_OUTS11_6", - "PSS1_LOGIC_OUTS11_7", - "PSS1_LOGIC_OUTS11_8", - "PSS1_LOGIC_OUTS11_9", - "PSS1_LOGIC_OUTS12_0", - "PSS1_LOGIC_OUTS12_1", - "PSS1_LOGIC_OUTS12_10", - "PSS1_LOGIC_OUTS12_11", - "PSS1_LOGIC_OUTS12_12", - "PSS1_LOGIC_OUTS12_13", - "PSS1_LOGIC_OUTS12_14", - "PSS1_LOGIC_OUTS12_15", - "PSS1_LOGIC_OUTS12_16", - "PSS1_LOGIC_OUTS12_17", - "PSS1_LOGIC_OUTS12_18", - "PSS1_LOGIC_OUTS12_19", - "PSS1_LOGIC_OUTS12_2", - "PSS1_LOGIC_OUTS12_20", - "PSS1_LOGIC_OUTS12_21", - "PSS1_LOGIC_OUTS12_22", - "PSS1_LOGIC_OUTS12_23", - "PSS1_LOGIC_OUTS12_24", - "PSS1_LOGIC_OUTS12_25", - "PSS1_LOGIC_OUTS12_26", - "PSS1_LOGIC_OUTS12_27", - "PSS1_LOGIC_OUTS12_28", - "PSS1_LOGIC_OUTS12_29", - "PSS1_LOGIC_OUTS12_3", - "PSS1_LOGIC_OUTS12_30", - "PSS1_LOGIC_OUTS12_31", - "PSS1_LOGIC_OUTS12_32", - "PSS1_LOGIC_OUTS12_33", - "PSS1_LOGIC_OUTS12_34", - "PSS1_LOGIC_OUTS12_35", - "PSS1_LOGIC_OUTS12_36", - "PSS1_LOGIC_OUTS12_37", - "PSS1_LOGIC_OUTS12_38", - "PSS1_LOGIC_OUTS12_39", - "PSS1_LOGIC_OUTS12_4", - "PSS1_LOGIC_OUTS12_5", - "PSS1_LOGIC_OUTS12_6", - "PSS1_LOGIC_OUTS12_7", - "PSS1_LOGIC_OUTS12_8", - "PSS1_LOGIC_OUTS12_9", - "PSS1_LOGIC_OUTS13_0", - "PSS1_LOGIC_OUTS13_1", - "PSS1_LOGIC_OUTS13_10", - "PSS1_LOGIC_OUTS13_11", - "PSS1_LOGIC_OUTS13_12", - "PSS1_LOGIC_OUTS13_13", - "PSS1_LOGIC_OUTS13_14", - "PSS1_LOGIC_OUTS13_15", - "PSS1_LOGIC_OUTS13_16", - "PSS1_LOGIC_OUTS13_17", - "PSS1_LOGIC_OUTS13_18", - "PSS1_LOGIC_OUTS13_19", - "PSS1_LOGIC_OUTS13_2", - "PSS1_LOGIC_OUTS13_20", - "PSS1_LOGIC_OUTS13_21", - "PSS1_LOGIC_OUTS13_22", - "PSS1_LOGIC_OUTS13_23", - "PSS1_LOGIC_OUTS13_24", - "PSS1_LOGIC_OUTS13_25", - "PSS1_LOGIC_OUTS13_26", - "PSS1_LOGIC_OUTS13_27", - "PSS1_LOGIC_OUTS13_28", - "PSS1_LOGIC_OUTS13_29", - "PSS1_LOGIC_OUTS13_3", - "PSS1_LOGIC_OUTS13_30", - "PSS1_LOGIC_OUTS13_31", - "PSS1_LOGIC_OUTS13_32", - "PSS1_LOGIC_OUTS13_33", - "PSS1_LOGIC_OUTS13_34", - "PSS1_LOGIC_OUTS13_35", - "PSS1_LOGIC_OUTS13_36", - "PSS1_LOGIC_OUTS13_37", - "PSS1_LOGIC_OUTS13_38", - "PSS1_LOGIC_OUTS13_39", - "PSS1_LOGIC_OUTS13_4", - "PSS1_LOGIC_OUTS13_5", - "PSS1_LOGIC_OUTS13_6", - "PSS1_LOGIC_OUTS13_7", - "PSS1_LOGIC_OUTS13_8", - "PSS1_LOGIC_OUTS13_9", - "PSS1_LOGIC_OUTS14_0", - "PSS1_LOGIC_OUTS14_1", - "PSS1_LOGIC_OUTS14_10", - "PSS1_LOGIC_OUTS14_11", - "PSS1_LOGIC_OUTS14_12", - "PSS1_LOGIC_OUTS14_13", - "PSS1_LOGIC_OUTS14_14", - "PSS1_LOGIC_OUTS14_15", - "PSS1_LOGIC_OUTS14_16", - "PSS1_LOGIC_OUTS14_17", - "PSS1_LOGIC_OUTS14_18", - "PSS1_LOGIC_OUTS14_19", - "PSS1_LOGIC_OUTS14_2", - "PSS1_LOGIC_OUTS14_20", - "PSS1_LOGIC_OUTS14_21", - "PSS1_LOGIC_OUTS14_22", - "PSS1_LOGIC_OUTS14_23", - "PSS1_LOGIC_OUTS14_24", - "PSS1_LOGIC_OUTS14_25", - "PSS1_LOGIC_OUTS14_26", - "PSS1_LOGIC_OUTS14_27", - "PSS1_LOGIC_OUTS14_28", - "PSS1_LOGIC_OUTS14_29", - "PSS1_LOGIC_OUTS14_3", - "PSS1_LOGIC_OUTS14_30", - "PSS1_LOGIC_OUTS14_31", - "PSS1_LOGIC_OUTS14_32", - "PSS1_LOGIC_OUTS14_33", - "PSS1_LOGIC_OUTS14_34", - "PSS1_LOGIC_OUTS14_35", - "PSS1_LOGIC_OUTS14_36", - "PSS1_LOGIC_OUTS14_37", - "PSS1_LOGIC_OUTS14_38", - "PSS1_LOGIC_OUTS14_39", - "PSS1_LOGIC_OUTS14_4", - "PSS1_LOGIC_OUTS14_5", - "PSS1_LOGIC_OUTS14_6", - "PSS1_LOGIC_OUTS14_7", - "PSS1_LOGIC_OUTS14_8", - "PSS1_LOGIC_OUTS14_9", - "PSS1_LOGIC_OUTS15_0", - "PSS1_LOGIC_OUTS15_1", - "PSS1_LOGIC_OUTS15_10", - "PSS1_LOGIC_OUTS15_11", - "PSS1_LOGIC_OUTS15_12", - "PSS1_LOGIC_OUTS15_13", - "PSS1_LOGIC_OUTS15_14", - "PSS1_LOGIC_OUTS15_15", - "PSS1_LOGIC_OUTS15_16", - "PSS1_LOGIC_OUTS15_17", - "PSS1_LOGIC_OUTS15_18", - "PSS1_LOGIC_OUTS15_19", - "PSS1_LOGIC_OUTS15_2", - "PSS1_LOGIC_OUTS15_20", - "PSS1_LOGIC_OUTS15_21", - "PSS1_LOGIC_OUTS15_22", - "PSS1_LOGIC_OUTS15_23", - "PSS1_LOGIC_OUTS15_24", - "PSS1_LOGIC_OUTS15_25", - "PSS1_LOGIC_OUTS15_26", - "PSS1_LOGIC_OUTS15_27", - "PSS1_LOGIC_OUTS15_28", - "PSS1_LOGIC_OUTS15_29", - "PSS1_LOGIC_OUTS15_3", - "PSS1_LOGIC_OUTS15_30", - "PSS1_LOGIC_OUTS15_31", - "PSS1_LOGIC_OUTS15_32", - "PSS1_LOGIC_OUTS15_33", - "PSS1_LOGIC_OUTS15_34", - "PSS1_LOGIC_OUTS15_35", - "PSS1_LOGIC_OUTS15_36", - "PSS1_LOGIC_OUTS15_37", - "PSS1_LOGIC_OUTS15_38", - "PSS1_LOGIC_OUTS15_39", - "PSS1_LOGIC_OUTS15_4", - "PSS1_LOGIC_OUTS15_5", - "PSS1_LOGIC_OUTS15_6", - "PSS1_LOGIC_OUTS15_7", - "PSS1_LOGIC_OUTS15_8", - "PSS1_LOGIC_OUTS15_9", - "PSS1_LOGIC_OUTS16_0", - "PSS1_LOGIC_OUTS16_1", - "PSS1_LOGIC_OUTS16_10", - "PSS1_LOGIC_OUTS16_11", - "PSS1_LOGIC_OUTS16_12", - "PSS1_LOGIC_OUTS16_13", - "PSS1_LOGIC_OUTS16_14", - "PSS1_LOGIC_OUTS16_15", - "PSS1_LOGIC_OUTS16_16", - "PSS1_LOGIC_OUTS16_17", - "PSS1_LOGIC_OUTS16_18", - "PSS1_LOGIC_OUTS16_19", - "PSS1_LOGIC_OUTS16_2", - "PSS1_LOGIC_OUTS16_20", - "PSS1_LOGIC_OUTS16_21", - "PSS1_LOGIC_OUTS16_22", - "PSS1_LOGIC_OUTS16_23", - "PSS1_LOGIC_OUTS16_24", - "PSS1_LOGIC_OUTS16_25", - "PSS1_LOGIC_OUTS16_26", - "PSS1_LOGIC_OUTS16_27", - "PSS1_LOGIC_OUTS16_28", - "PSS1_LOGIC_OUTS16_29", - "PSS1_LOGIC_OUTS16_3", - "PSS1_LOGIC_OUTS16_30", - "PSS1_LOGIC_OUTS16_31", - "PSS1_LOGIC_OUTS16_32", - "PSS1_LOGIC_OUTS16_33", - "PSS1_LOGIC_OUTS16_34", - "PSS1_LOGIC_OUTS16_35", - "PSS1_LOGIC_OUTS16_36", - "PSS1_LOGIC_OUTS16_37", - "PSS1_LOGIC_OUTS16_38", - "PSS1_LOGIC_OUTS16_39", - "PSS1_LOGIC_OUTS16_4", - "PSS1_LOGIC_OUTS16_5", - "PSS1_LOGIC_OUTS16_6", - "PSS1_LOGIC_OUTS16_7", - "PSS1_LOGIC_OUTS16_8", - "PSS1_LOGIC_OUTS16_9", - "PSS1_LOGIC_OUTS17_0", - "PSS1_LOGIC_OUTS17_1", - "PSS1_LOGIC_OUTS17_10", - "PSS1_LOGIC_OUTS17_11", - "PSS1_LOGIC_OUTS17_12", - "PSS1_LOGIC_OUTS17_13", - "PSS1_LOGIC_OUTS17_14", - "PSS1_LOGIC_OUTS17_15", - "PSS1_LOGIC_OUTS17_16", - "PSS1_LOGIC_OUTS17_17", - "PSS1_LOGIC_OUTS17_18", - "PSS1_LOGIC_OUTS17_19", - "PSS1_LOGIC_OUTS17_2", - "PSS1_LOGIC_OUTS17_20", - "PSS1_LOGIC_OUTS17_21", - "PSS1_LOGIC_OUTS17_22", - "PSS1_LOGIC_OUTS17_23", - "PSS1_LOGIC_OUTS17_24", - "PSS1_LOGIC_OUTS17_25", - "PSS1_LOGIC_OUTS17_26", - "PSS1_LOGIC_OUTS17_27", - "PSS1_LOGIC_OUTS17_28", - "PSS1_LOGIC_OUTS17_29", - "PSS1_LOGIC_OUTS17_3", - "PSS1_LOGIC_OUTS17_30", - "PSS1_LOGIC_OUTS17_31", - "PSS1_LOGIC_OUTS17_32", - "PSS1_LOGIC_OUTS17_33", - "PSS1_LOGIC_OUTS17_34", - "PSS1_LOGIC_OUTS17_35", - "PSS1_LOGIC_OUTS17_36", - "PSS1_LOGIC_OUTS17_37", - "PSS1_LOGIC_OUTS17_38", - "PSS1_LOGIC_OUTS17_39", - "PSS1_LOGIC_OUTS17_4", - "PSS1_LOGIC_OUTS17_5", - "PSS1_LOGIC_OUTS17_6", - "PSS1_LOGIC_OUTS17_7", - "PSS1_LOGIC_OUTS17_8", - "PSS1_LOGIC_OUTS17_9", - "PSS1_LOGIC_OUTS18_0", - "PSS1_LOGIC_OUTS18_1", - "PSS1_LOGIC_OUTS18_10", - "PSS1_LOGIC_OUTS18_11", - "PSS1_LOGIC_OUTS18_12", - "PSS1_LOGIC_OUTS18_13", - "PSS1_LOGIC_OUTS18_14", - "PSS1_LOGIC_OUTS18_15", - "PSS1_LOGIC_OUTS18_16", - "PSS1_LOGIC_OUTS18_17", - "PSS1_LOGIC_OUTS18_18", - "PSS1_LOGIC_OUTS18_19", - "PSS1_LOGIC_OUTS18_2", - "PSS1_LOGIC_OUTS18_20", - "PSS1_LOGIC_OUTS18_21", - "PSS1_LOGIC_OUTS18_22", - "PSS1_LOGIC_OUTS18_23", - "PSS1_LOGIC_OUTS18_24", - "PSS1_LOGIC_OUTS18_25", - "PSS1_LOGIC_OUTS18_26", - "PSS1_LOGIC_OUTS18_27", - "PSS1_LOGIC_OUTS18_28", - "PSS1_LOGIC_OUTS18_29", - "PSS1_LOGIC_OUTS18_3", - "PSS1_LOGIC_OUTS18_30", - "PSS1_LOGIC_OUTS18_31", - "PSS1_LOGIC_OUTS18_32", - "PSS1_LOGIC_OUTS18_33", - "PSS1_LOGIC_OUTS18_34", - "PSS1_LOGIC_OUTS18_35", - "PSS1_LOGIC_OUTS18_36", - "PSS1_LOGIC_OUTS18_37", - "PSS1_LOGIC_OUTS18_38", - "PSS1_LOGIC_OUTS18_39", - "PSS1_LOGIC_OUTS18_4", - "PSS1_LOGIC_OUTS18_5", - "PSS1_LOGIC_OUTS18_6", - "PSS1_LOGIC_OUTS18_7", - "PSS1_LOGIC_OUTS18_8", - "PSS1_LOGIC_OUTS18_9", - "PSS1_LOGIC_OUTS19_0", - "PSS1_LOGIC_OUTS19_1", - "PSS1_LOGIC_OUTS19_10", - "PSS1_LOGIC_OUTS19_11", - "PSS1_LOGIC_OUTS19_12", - "PSS1_LOGIC_OUTS19_13", - "PSS1_LOGIC_OUTS19_14", - "PSS1_LOGIC_OUTS19_15", - "PSS1_LOGIC_OUTS19_16", - "PSS1_LOGIC_OUTS19_17", - "PSS1_LOGIC_OUTS19_18", - "PSS1_LOGIC_OUTS19_19", - "PSS1_LOGIC_OUTS19_2", - "PSS1_LOGIC_OUTS19_20", - "PSS1_LOGIC_OUTS19_21", - "PSS1_LOGIC_OUTS19_22", - "PSS1_LOGIC_OUTS19_23", - "PSS1_LOGIC_OUTS19_24", - "PSS1_LOGIC_OUTS19_25", - "PSS1_LOGIC_OUTS19_26", - "PSS1_LOGIC_OUTS19_27", - "PSS1_LOGIC_OUTS19_28", - "PSS1_LOGIC_OUTS19_29", - "PSS1_LOGIC_OUTS19_3", - "PSS1_LOGIC_OUTS19_30", - "PSS1_LOGIC_OUTS19_31", - "PSS1_LOGIC_OUTS19_32", - "PSS1_LOGIC_OUTS19_33", - "PSS1_LOGIC_OUTS19_34", - "PSS1_LOGIC_OUTS19_35", - "PSS1_LOGIC_OUTS19_36", - "PSS1_LOGIC_OUTS19_37", - "PSS1_LOGIC_OUTS19_38", - "PSS1_LOGIC_OUTS19_39", - "PSS1_LOGIC_OUTS19_4", - "PSS1_LOGIC_OUTS19_5", - "PSS1_LOGIC_OUTS19_6", - "PSS1_LOGIC_OUTS19_7", - "PSS1_LOGIC_OUTS19_8", - "PSS1_LOGIC_OUTS19_9", - "PSS1_LOGIC_OUTS1_0", - "PSS1_LOGIC_OUTS1_1", - "PSS1_LOGIC_OUTS1_10", - "PSS1_LOGIC_OUTS1_11", - "PSS1_LOGIC_OUTS1_12", - "PSS1_LOGIC_OUTS1_13", - "PSS1_LOGIC_OUTS1_14", - "PSS1_LOGIC_OUTS1_15", - "PSS1_LOGIC_OUTS1_16", - "PSS1_LOGIC_OUTS1_17", - "PSS1_LOGIC_OUTS1_18", - "PSS1_LOGIC_OUTS1_19", - "PSS1_LOGIC_OUTS1_2", - "PSS1_LOGIC_OUTS1_20", - "PSS1_LOGIC_OUTS1_21", - "PSS1_LOGIC_OUTS1_22", - "PSS1_LOGIC_OUTS1_23", - "PSS1_LOGIC_OUTS1_24", - "PSS1_LOGIC_OUTS1_25", - "PSS1_LOGIC_OUTS1_26", - "PSS1_LOGIC_OUTS1_27", - "PSS1_LOGIC_OUTS1_28", - "PSS1_LOGIC_OUTS1_29", - "PSS1_LOGIC_OUTS1_3", - "PSS1_LOGIC_OUTS1_30", - "PSS1_LOGIC_OUTS1_31", - "PSS1_LOGIC_OUTS1_32", - "PSS1_LOGIC_OUTS1_33", - "PSS1_LOGIC_OUTS1_34", - "PSS1_LOGIC_OUTS1_35", - "PSS1_LOGIC_OUTS1_36", - "PSS1_LOGIC_OUTS1_37", - "PSS1_LOGIC_OUTS1_38", - "PSS1_LOGIC_OUTS1_39", - "PSS1_LOGIC_OUTS1_4", - "PSS1_LOGIC_OUTS1_5", - "PSS1_LOGIC_OUTS1_6", - "PSS1_LOGIC_OUTS1_7", - "PSS1_LOGIC_OUTS1_8", - "PSS1_LOGIC_OUTS1_9", - "PSS1_LOGIC_OUTS20_0", - "PSS1_LOGIC_OUTS20_1", - "PSS1_LOGIC_OUTS20_10", - "PSS1_LOGIC_OUTS20_11", - "PSS1_LOGIC_OUTS20_12", - "PSS1_LOGIC_OUTS20_13", - "PSS1_LOGIC_OUTS20_14", - "PSS1_LOGIC_OUTS20_15", - "PSS1_LOGIC_OUTS20_16", - "PSS1_LOGIC_OUTS20_17", - "PSS1_LOGIC_OUTS20_18", - "PSS1_LOGIC_OUTS20_19", - "PSS1_LOGIC_OUTS20_2", - "PSS1_LOGIC_OUTS20_20", - "PSS1_LOGIC_OUTS20_21", - "PSS1_LOGIC_OUTS20_22", - "PSS1_LOGIC_OUTS20_23", - "PSS1_LOGIC_OUTS20_24", - "PSS1_LOGIC_OUTS20_25", - "PSS1_LOGIC_OUTS20_26", - "PSS1_LOGIC_OUTS20_27", - "PSS1_LOGIC_OUTS20_28", - "PSS1_LOGIC_OUTS20_29", - "PSS1_LOGIC_OUTS20_3", - "PSS1_LOGIC_OUTS20_30", - "PSS1_LOGIC_OUTS20_31", - "PSS1_LOGIC_OUTS20_32", - "PSS1_LOGIC_OUTS20_33", - "PSS1_LOGIC_OUTS20_34", - "PSS1_LOGIC_OUTS20_35", - "PSS1_LOGIC_OUTS20_36", - "PSS1_LOGIC_OUTS20_37", - "PSS1_LOGIC_OUTS20_38", - "PSS1_LOGIC_OUTS20_39", - "PSS1_LOGIC_OUTS20_4", - "PSS1_LOGIC_OUTS20_5", - "PSS1_LOGIC_OUTS20_6", - "PSS1_LOGIC_OUTS20_7", - "PSS1_LOGIC_OUTS20_8", - "PSS1_LOGIC_OUTS20_9", - "PSS1_LOGIC_OUTS21_0", - "PSS1_LOGIC_OUTS21_1", - "PSS1_LOGIC_OUTS21_10", - "PSS1_LOGIC_OUTS21_11", - "PSS1_LOGIC_OUTS21_12", - "PSS1_LOGIC_OUTS21_13", - "PSS1_LOGIC_OUTS21_14", - "PSS1_LOGIC_OUTS21_15", - "PSS1_LOGIC_OUTS21_16", - "PSS1_LOGIC_OUTS21_17", - "PSS1_LOGIC_OUTS21_18", - "PSS1_LOGIC_OUTS21_19", - "PSS1_LOGIC_OUTS21_2", - "PSS1_LOGIC_OUTS21_20", - "PSS1_LOGIC_OUTS21_21", - "PSS1_LOGIC_OUTS21_22", - "PSS1_LOGIC_OUTS21_23", - "PSS1_LOGIC_OUTS21_24", - "PSS1_LOGIC_OUTS21_25", - "PSS1_LOGIC_OUTS21_26", - "PSS1_LOGIC_OUTS21_27", - "PSS1_LOGIC_OUTS21_28", - "PSS1_LOGIC_OUTS21_29", - "PSS1_LOGIC_OUTS21_3", - "PSS1_LOGIC_OUTS21_30", - "PSS1_LOGIC_OUTS21_31", - "PSS1_LOGIC_OUTS21_32", - "PSS1_LOGIC_OUTS21_33", - "PSS1_LOGIC_OUTS21_34", - "PSS1_LOGIC_OUTS21_35", - "PSS1_LOGIC_OUTS21_36", - "PSS1_LOGIC_OUTS21_37", - "PSS1_LOGIC_OUTS21_38", - "PSS1_LOGIC_OUTS21_39", - "PSS1_LOGIC_OUTS21_4", - "PSS1_LOGIC_OUTS21_5", - "PSS1_LOGIC_OUTS21_6", - "PSS1_LOGIC_OUTS21_7", - "PSS1_LOGIC_OUTS21_8", - "PSS1_LOGIC_OUTS21_9", - "PSS1_LOGIC_OUTS22_0", - "PSS1_LOGIC_OUTS22_1", - "PSS1_LOGIC_OUTS22_10", - "PSS1_LOGIC_OUTS22_11", - "PSS1_LOGIC_OUTS22_12", - "PSS1_LOGIC_OUTS22_13", - "PSS1_LOGIC_OUTS22_14", - "PSS1_LOGIC_OUTS22_15", - "PSS1_LOGIC_OUTS22_16", - "PSS1_LOGIC_OUTS22_17", - "PSS1_LOGIC_OUTS22_18", - "PSS1_LOGIC_OUTS22_19", - "PSS1_LOGIC_OUTS22_2", - "PSS1_LOGIC_OUTS22_20", - "PSS1_LOGIC_OUTS22_21", - "PSS1_LOGIC_OUTS22_22", - "PSS1_LOGIC_OUTS22_23", - "PSS1_LOGIC_OUTS22_24", - "PSS1_LOGIC_OUTS22_25", - "PSS1_LOGIC_OUTS22_26", - "PSS1_LOGIC_OUTS22_27", - "PSS1_LOGIC_OUTS22_28", - "PSS1_LOGIC_OUTS22_29", - "PSS1_LOGIC_OUTS22_3", - "PSS1_LOGIC_OUTS22_30", - "PSS1_LOGIC_OUTS22_31", - "PSS1_LOGIC_OUTS22_32", - "PSS1_LOGIC_OUTS22_33", - "PSS1_LOGIC_OUTS22_34", - "PSS1_LOGIC_OUTS22_35", - "PSS1_LOGIC_OUTS22_36", - "PSS1_LOGIC_OUTS22_37", - "PSS1_LOGIC_OUTS22_38", - "PSS1_LOGIC_OUTS22_39", - "PSS1_LOGIC_OUTS22_4", - "PSS1_LOGIC_OUTS22_5", - "PSS1_LOGIC_OUTS22_6", - "PSS1_LOGIC_OUTS22_7", - "PSS1_LOGIC_OUTS22_8", - "PSS1_LOGIC_OUTS22_9", - "PSS1_LOGIC_OUTS23_0", - "PSS1_LOGIC_OUTS23_1", - "PSS1_LOGIC_OUTS23_10", - "PSS1_LOGIC_OUTS23_11", - "PSS1_LOGIC_OUTS23_12", - "PSS1_LOGIC_OUTS23_13", - "PSS1_LOGIC_OUTS23_14", - "PSS1_LOGIC_OUTS23_15", - "PSS1_LOGIC_OUTS23_16", - "PSS1_LOGIC_OUTS23_17", - "PSS1_LOGIC_OUTS23_18", - "PSS1_LOGIC_OUTS23_19", - "PSS1_LOGIC_OUTS23_2", - "PSS1_LOGIC_OUTS23_20", - "PSS1_LOGIC_OUTS23_21", - "PSS1_LOGIC_OUTS23_22", - "PSS1_LOGIC_OUTS23_23", - "PSS1_LOGIC_OUTS23_24", - "PSS1_LOGIC_OUTS23_25", - "PSS1_LOGIC_OUTS23_26", - "PSS1_LOGIC_OUTS23_27", - "PSS1_LOGIC_OUTS23_28", - "PSS1_LOGIC_OUTS23_29", - "PSS1_LOGIC_OUTS23_3", - "PSS1_LOGIC_OUTS23_30", - "PSS1_LOGIC_OUTS23_31", - "PSS1_LOGIC_OUTS23_32", - "PSS1_LOGIC_OUTS23_33", - "PSS1_LOGIC_OUTS23_34", - "PSS1_LOGIC_OUTS23_35", - "PSS1_LOGIC_OUTS23_36", - "PSS1_LOGIC_OUTS23_37", - "PSS1_LOGIC_OUTS23_38", - "PSS1_LOGIC_OUTS23_39", - "PSS1_LOGIC_OUTS23_4", - "PSS1_LOGIC_OUTS23_5", - "PSS1_LOGIC_OUTS23_6", - "PSS1_LOGIC_OUTS23_7", - "PSS1_LOGIC_OUTS23_8", - "PSS1_LOGIC_OUTS23_9", - "PSS1_LOGIC_OUTS2_0", - "PSS1_LOGIC_OUTS2_1", - "PSS1_LOGIC_OUTS2_10", - "PSS1_LOGIC_OUTS2_11", - "PSS1_LOGIC_OUTS2_12", - "PSS1_LOGIC_OUTS2_13", - "PSS1_LOGIC_OUTS2_14", - "PSS1_LOGIC_OUTS2_15", - "PSS1_LOGIC_OUTS2_16", - "PSS1_LOGIC_OUTS2_17", - "PSS1_LOGIC_OUTS2_18", - "PSS1_LOGIC_OUTS2_19", - "PSS1_LOGIC_OUTS2_2", - "PSS1_LOGIC_OUTS2_20", - "PSS1_LOGIC_OUTS2_21", - "PSS1_LOGIC_OUTS2_22", - "PSS1_LOGIC_OUTS2_23", - "PSS1_LOGIC_OUTS2_24", - "PSS1_LOGIC_OUTS2_25", - "PSS1_LOGIC_OUTS2_26", - "PSS1_LOGIC_OUTS2_27", - "PSS1_LOGIC_OUTS2_28", - "PSS1_LOGIC_OUTS2_29", - "PSS1_LOGIC_OUTS2_3", - "PSS1_LOGIC_OUTS2_30", - "PSS1_LOGIC_OUTS2_31", - "PSS1_LOGIC_OUTS2_32", - "PSS1_LOGIC_OUTS2_33", - "PSS1_LOGIC_OUTS2_34", - "PSS1_LOGIC_OUTS2_35", - "PSS1_LOGIC_OUTS2_36", - "PSS1_LOGIC_OUTS2_37", - "PSS1_LOGIC_OUTS2_38", - "PSS1_LOGIC_OUTS2_39", - "PSS1_LOGIC_OUTS2_4", - "PSS1_LOGIC_OUTS2_5", - "PSS1_LOGIC_OUTS2_6", - "PSS1_LOGIC_OUTS2_7", - "PSS1_LOGIC_OUTS2_8", - "PSS1_LOGIC_OUTS2_9", - "PSS1_LOGIC_OUTS3_0", - "PSS1_LOGIC_OUTS3_1", - "PSS1_LOGIC_OUTS3_10", - "PSS1_LOGIC_OUTS3_11", - "PSS1_LOGIC_OUTS3_12", - "PSS1_LOGIC_OUTS3_13", - "PSS1_LOGIC_OUTS3_14", - "PSS1_LOGIC_OUTS3_15", - "PSS1_LOGIC_OUTS3_16", - "PSS1_LOGIC_OUTS3_17", - "PSS1_LOGIC_OUTS3_18", - "PSS1_LOGIC_OUTS3_19", - "PSS1_LOGIC_OUTS3_2", - "PSS1_LOGIC_OUTS3_20", - "PSS1_LOGIC_OUTS3_21", - "PSS1_LOGIC_OUTS3_22", - "PSS1_LOGIC_OUTS3_23", - "PSS1_LOGIC_OUTS3_24", - "PSS1_LOGIC_OUTS3_25", - "PSS1_LOGIC_OUTS3_26", - "PSS1_LOGIC_OUTS3_27", - "PSS1_LOGIC_OUTS3_28", - "PSS1_LOGIC_OUTS3_29", - "PSS1_LOGIC_OUTS3_3", - "PSS1_LOGIC_OUTS3_30", - "PSS1_LOGIC_OUTS3_31", - "PSS1_LOGIC_OUTS3_32", - "PSS1_LOGIC_OUTS3_33", - "PSS1_LOGIC_OUTS3_34", - "PSS1_LOGIC_OUTS3_35", - "PSS1_LOGIC_OUTS3_36", - "PSS1_LOGIC_OUTS3_37", - "PSS1_LOGIC_OUTS3_38", - "PSS1_LOGIC_OUTS3_39", - "PSS1_LOGIC_OUTS3_4", - "PSS1_LOGIC_OUTS3_5", - "PSS1_LOGIC_OUTS3_6", - "PSS1_LOGIC_OUTS3_7", - "PSS1_LOGIC_OUTS3_8", - "PSS1_LOGIC_OUTS3_9", - "PSS1_LOGIC_OUTS4_0", - "PSS1_LOGIC_OUTS4_1", - "PSS1_LOGIC_OUTS4_10", - "PSS1_LOGIC_OUTS4_11", - "PSS1_LOGIC_OUTS4_12", - "PSS1_LOGIC_OUTS4_13", - "PSS1_LOGIC_OUTS4_14", - "PSS1_LOGIC_OUTS4_15", - "PSS1_LOGIC_OUTS4_16", - "PSS1_LOGIC_OUTS4_17", - "PSS1_LOGIC_OUTS4_18", - "PSS1_LOGIC_OUTS4_19", - "PSS1_LOGIC_OUTS4_2", - "PSS1_LOGIC_OUTS4_20", - "PSS1_LOGIC_OUTS4_21", - "PSS1_LOGIC_OUTS4_22", - "PSS1_LOGIC_OUTS4_23", - "PSS1_LOGIC_OUTS4_24", - "PSS1_LOGIC_OUTS4_25", - "PSS1_LOGIC_OUTS4_26", - "PSS1_LOGIC_OUTS4_27", - "PSS1_LOGIC_OUTS4_28", - "PSS1_LOGIC_OUTS4_29", - "PSS1_LOGIC_OUTS4_3", - "PSS1_LOGIC_OUTS4_30", - "PSS1_LOGIC_OUTS4_31", - "PSS1_LOGIC_OUTS4_32", - "PSS1_LOGIC_OUTS4_33", - "PSS1_LOGIC_OUTS4_34", - "PSS1_LOGIC_OUTS4_35", - "PSS1_LOGIC_OUTS4_36", - "PSS1_LOGIC_OUTS4_37", - "PSS1_LOGIC_OUTS4_38", - "PSS1_LOGIC_OUTS4_39", - "PSS1_LOGIC_OUTS4_4", - "PSS1_LOGIC_OUTS4_5", - "PSS1_LOGIC_OUTS4_6", - "PSS1_LOGIC_OUTS4_7", - "PSS1_LOGIC_OUTS4_8", - "PSS1_LOGIC_OUTS4_9", - "PSS1_LOGIC_OUTS5_0", - "PSS1_LOGIC_OUTS5_1", - "PSS1_LOGIC_OUTS5_10", - "PSS1_LOGIC_OUTS5_11", - "PSS1_LOGIC_OUTS5_12", - "PSS1_LOGIC_OUTS5_13", - "PSS1_LOGIC_OUTS5_14", - "PSS1_LOGIC_OUTS5_15", - "PSS1_LOGIC_OUTS5_16", - "PSS1_LOGIC_OUTS5_17", - "PSS1_LOGIC_OUTS5_18", - "PSS1_LOGIC_OUTS5_19", - "PSS1_LOGIC_OUTS5_2", - "PSS1_LOGIC_OUTS5_20", - "PSS1_LOGIC_OUTS5_21", - "PSS1_LOGIC_OUTS5_22", - "PSS1_LOGIC_OUTS5_23", - "PSS1_LOGIC_OUTS5_24", - "PSS1_LOGIC_OUTS5_25", - "PSS1_LOGIC_OUTS5_26", - "PSS1_LOGIC_OUTS5_27", - "PSS1_LOGIC_OUTS5_28", - "PSS1_LOGIC_OUTS5_29", - "PSS1_LOGIC_OUTS5_3", - "PSS1_LOGIC_OUTS5_30", - "PSS1_LOGIC_OUTS5_31", - "PSS1_LOGIC_OUTS5_32", - "PSS1_LOGIC_OUTS5_33", - "PSS1_LOGIC_OUTS5_34", - "PSS1_LOGIC_OUTS5_35", - "PSS1_LOGIC_OUTS5_36", - "PSS1_LOGIC_OUTS5_37", - "PSS1_LOGIC_OUTS5_38", - "PSS1_LOGIC_OUTS5_39", - "PSS1_LOGIC_OUTS5_4", - "PSS1_LOGIC_OUTS5_5", - "PSS1_LOGIC_OUTS5_6", - "PSS1_LOGIC_OUTS5_7", - "PSS1_LOGIC_OUTS5_8", - "PSS1_LOGIC_OUTS5_9", - "PSS1_LOGIC_OUTS6_0", - "PSS1_LOGIC_OUTS6_1", - "PSS1_LOGIC_OUTS6_10", - "PSS1_LOGIC_OUTS6_11", - "PSS1_LOGIC_OUTS6_12", - "PSS1_LOGIC_OUTS6_13", - "PSS1_LOGIC_OUTS6_14", - "PSS1_LOGIC_OUTS6_15", - "PSS1_LOGIC_OUTS6_16", - "PSS1_LOGIC_OUTS6_17", - "PSS1_LOGIC_OUTS6_18", - "PSS1_LOGIC_OUTS6_19", - "PSS1_LOGIC_OUTS6_2", - "PSS1_LOGIC_OUTS6_20", - "PSS1_LOGIC_OUTS6_21", - "PSS1_LOGIC_OUTS6_22", - "PSS1_LOGIC_OUTS6_23", - "PSS1_LOGIC_OUTS6_24", - "PSS1_LOGIC_OUTS6_25", - "PSS1_LOGIC_OUTS6_26", - "PSS1_LOGIC_OUTS6_27", - "PSS1_LOGIC_OUTS6_28", - "PSS1_LOGIC_OUTS6_29", - "PSS1_LOGIC_OUTS6_3", - "PSS1_LOGIC_OUTS6_30", - "PSS1_LOGIC_OUTS6_31", - "PSS1_LOGIC_OUTS6_32", - "PSS1_LOGIC_OUTS6_33", - "PSS1_LOGIC_OUTS6_34", - "PSS1_LOGIC_OUTS6_35", - "PSS1_LOGIC_OUTS6_36", - "PSS1_LOGIC_OUTS6_37", - "PSS1_LOGIC_OUTS6_38", - "PSS1_LOGIC_OUTS6_39", - "PSS1_LOGIC_OUTS6_4", - "PSS1_LOGIC_OUTS6_5", - "PSS1_LOGIC_OUTS6_6", - "PSS1_LOGIC_OUTS6_7", - "PSS1_LOGIC_OUTS6_8", - "PSS1_LOGIC_OUTS6_9", - "PSS1_LOGIC_OUTS7_0", - "PSS1_LOGIC_OUTS7_1", - "PSS1_LOGIC_OUTS7_10", - "PSS1_LOGIC_OUTS7_11", - "PSS1_LOGIC_OUTS7_12", - "PSS1_LOGIC_OUTS7_13", - "PSS1_LOGIC_OUTS7_14", - "PSS1_LOGIC_OUTS7_15", - "PSS1_LOGIC_OUTS7_16", - "PSS1_LOGIC_OUTS7_17", - "PSS1_LOGIC_OUTS7_18", - "PSS1_LOGIC_OUTS7_19", - "PSS1_LOGIC_OUTS7_2", - "PSS1_LOGIC_OUTS7_20", - "PSS1_LOGIC_OUTS7_21", - "PSS1_LOGIC_OUTS7_22", - "PSS1_LOGIC_OUTS7_23", - "PSS1_LOGIC_OUTS7_24", - "PSS1_LOGIC_OUTS7_25", - "PSS1_LOGIC_OUTS7_26", - "PSS1_LOGIC_OUTS7_27", - "PSS1_LOGIC_OUTS7_28", - "PSS1_LOGIC_OUTS7_29", - "PSS1_LOGIC_OUTS7_3", - "PSS1_LOGIC_OUTS7_30", - "PSS1_LOGIC_OUTS7_31", - "PSS1_LOGIC_OUTS7_32", - "PSS1_LOGIC_OUTS7_33", - "PSS1_LOGIC_OUTS7_34", - "PSS1_LOGIC_OUTS7_35", - "PSS1_LOGIC_OUTS7_36", - "PSS1_LOGIC_OUTS7_37", - "PSS1_LOGIC_OUTS7_38", - "PSS1_LOGIC_OUTS7_39", - "PSS1_LOGIC_OUTS7_4", - "PSS1_LOGIC_OUTS7_5", - "PSS1_LOGIC_OUTS7_6", - "PSS1_LOGIC_OUTS7_7", - "PSS1_LOGIC_OUTS7_8", - "PSS1_LOGIC_OUTS7_9", - "PSS1_LOGIC_OUTS8_0", - "PSS1_LOGIC_OUTS8_1", - "PSS1_LOGIC_OUTS8_10", - "PSS1_LOGIC_OUTS8_11", - "PSS1_LOGIC_OUTS8_12", - "PSS1_LOGIC_OUTS8_13", - "PSS1_LOGIC_OUTS8_14", - "PSS1_LOGIC_OUTS8_15", - "PSS1_LOGIC_OUTS8_16", - "PSS1_LOGIC_OUTS8_17", - "PSS1_LOGIC_OUTS8_18", - "PSS1_LOGIC_OUTS8_19", - "PSS1_LOGIC_OUTS8_2", - "PSS1_LOGIC_OUTS8_20", - "PSS1_LOGIC_OUTS8_21", - "PSS1_LOGIC_OUTS8_22", - "PSS1_LOGIC_OUTS8_23", - "PSS1_LOGIC_OUTS8_24", - "PSS1_LOGIC_OUTS8_25", - "PSS1_LOGIC_OUTS8_26", - "PSS1_LOGIC_OUTS8_27", - "PSS1_LOGIC_OUTS8_28", - "PSS1_LOGIC_OUTS8_29", - "PSS1_LOGIC_OUTS8_3", - "PSS1_LOGIC_OUTS8_30", - "PSS1_LOGIC_OUTS8_31", - "PSS1_LOGIC_OUTS8_32", - "PSS1_LOGIC_OUTS8_33", - "PSS1_LOGIC_OUTS8_34", - "PSS1_LOGIC_OUTS8_35", - "PSS1_LOGIC_OUTS8_36", - "PSS1_LOGIC_OUTS8_37", - "PSS1_LOGIC_OUTS8_38", - "PSS1_LOGIC_OUTS8_39", - "PSS1_LOGIC_OUTS8_4", - "PSS1_LOGIC_OUTS8_5", - "PSS1_LOGIC_OUTS8_6", - "PSS1_LOGIC_OUTS8_7", - "PSS1_LOGIC_OUTS8_8", - "PSS1_LOGIC_OUTS8_9", - "PSS1_LOGIC_OUTS9_0", - "PSS1_LOGIC_OUTS9_1", - "PSS1_LOGIC_OUTS9_10", - "PSS1_LOGIC_OUTS9_11", - "PSS1_LOGIC_OUTS9_12", - "PSS1_LOGIC_OUTS9_13", - "PSS1_LOGIC_OUTS9_14", - "PSS1_LOGIC_OUTS9_15", - "PSS1_LOGIC_OUTS9_16", - "PSS1_LOGIC_OUTS9_17", - "PSS1_LOGIC_OUTS9_18", - "PSS1_LOGIC_OUTS9_19", - "PSS1_LOGIC_OUTS9_2", - "PSS1_LOGIC_OUTS9_20", - "PSS1_LOGIC_OUTS9_21", - "PSS1_LOGIC_OUTS9_22", - "PSS1_LOGIC_OUTS9_23", - "PSS1_LOGIC_OUTS9_24", - "PSS1_LOGIC_OUTS9_25", - "PSS1_LOGIC_OUTS9_26", - "PSS1_LOGIC_OUTS9_27", - "PSS1_LOGIC_OUTS9_28", - "PSS1_LOGIC_OUTS9_29", - "PSS1_LOGIC_OUTS9_3", - "PSS1_LOGIC_OUTS9_30", - "PSS1_LOGIC_OUTS9_31", - "PSS1_LOGIC_OUTS9_32", - "PSS1_LOGIC_OUTS9_33", - "PSS1_LOGIC_OUTS9_34", - "PSS1_LOGIC_OUTS9_35", - "PSS1_LOGIC_OUTS9_36", - "PSS1_LOGIC_OUTS9_37", - "PSS1_LOGIC_OUTS9_38", - "PSS1_LOGIC_OUTS9_39", - "PSS1_LOGIC_OUTS9_4", - "PSS1_LOGIC_OUTS9_5", - "PSS1_LOGIC_OUTS9_6", - "PSS1_LOGIC_OUTS9_7", - "PSS1_LOGIC_OUTS9_8", - "PSS1_LOGIC_OUTS9_9", - "PSS2_CLK_B0_60", - "PSS2_CLK_B0_61", - "PSS2_CLK_B0_62", - "PSS2_CLK_B0_63", - "PSS2_CLK_B0_64", - "PSS2_CLK_B0_65", - "PSS2_CLK_B0_66", - "PSS2_CLK_B0_67", - "PSS2_CLK_B0_68", - "PSS2_CLK_B0_69", - "PSS2_CLK_B0_70", - "PSS2_CLK_B0_71", - "PSS2_CLK_B0_72", - "PSS2_CLK_B0_73", - "PSS2_CLK_B0_74", - "PSS2_CLK_B0_75", - "PSS2_CLK_B0_76", - "PSS2_CLK_B0_77", - "PSS2_CLK_B0_78", - "PSS2_CLK_B0_79", - "PSS2_CLK_B0_80", - "PSS2_CLK_B0_81", - "PSS2_CLK_B0_82", - "PSS2_CLK_B0_83", - "PSS2_CLK_B0_84", - "PSS2_CLK_B0_85", - "PSS2_CLK_B0_86", - "PSS2_CLK_B0_87", - "PSS2_CLK_B0_88", - "PSS2_CLK_B0_89", - "PSS2_CLK_B0_90", - "PSS2_CLK_B0_91", - "PSS2_CLK_B0_92", - "PSS2_CLK_B0_93", - "PSS2_CLK_B0_94", - "PSS2_CLK_B0_95", - "PSS2_CLK_B0_96", - "PSS2_CLK_B0_97", - "PSS2_CLK_B0_98", - "PSS2_CLK_B0_99", - "PSS2_CLK_B1_60", - "PSS2_CLK_B1_61", - "PSS2_CLK_B1_62", - "PSS2_CLK_B1_63", - "PSS2_CLK_B1_64", - "PSS2_CLK_B1_65", - "PSS2_CLK_B1_66", - "PSS2_CLK_B1_67", - "PSS2_CLK_B1_68", - "PSS2_CLK_B1_69", - "PSS2_CLK_B1_70", - "PSS2_CLK_B1_71", - "PSS2_CLK_B1_72", - "PSS2_CLK_B1_73", - "PSS2_CLK_B1_74", - "PSS2_CLK_B1_75", - "PSS2_CLK_B1_76", - "PSS2_CLK_B1_77", - "PSS2_CLK_B1_78", - "PSS2_CLK_B1_79", - "PSS2_CLK_B1_80", - "PSS2_CLK_B1_81", - "PSS2_CLK_B1_82", - "PSS2_CLK_B1_83", - "PSS2_CLK_B1_84", - "PSS2_CLK_B1_85", - "PSS2_CLK_B1_86", - "PSS2_CLK_B1_87", - "PSS2_CLK_B1_88", - "PSS2_CLK_B1_89", - "PSS2_CLK_B1_90", - "PSS2_CLK_B1_91", - "PSS2_CLK_B1_92", - "PSS2_CLK_B1_93", - "PSS2_CLK_B1_94", - "PSS2_CLK_B1_95", - "PSS2_CLK_B1_96", - "PSS2_CLK_B1_97", - "PSS2_CLK_B1_98", - "PSS2_CLK_B1_99", - "PSS2_FCLKCLK2", - "PSS2_FCLKCLK3", - "PSS2_IMUX_B0_60", - "PSS2_IMUX_B0_61", - "PSS2_IMUX_B0_62", - "PSS2_IMUX_B0_63", - "PSS2_IMUX_B0_64", - "PSS2_IMUX_B0_65", - "PSS2_IMUX_B0_66", - "PSS2_IMUX_B0_67", - "PSS2_IMUX_B0_68", - "PSS2_IMUX_B0_69", - "PSS2_IMUX_B0_70", - "PSS2_IMUX_B0_71", - "PSS2_IMUX_B0_72", - "PSS2_IMUX_B0_73", - "PSS2_IMUX_B0_74", - "PSS2_IMUX_B0_75", - "PSS2_IMUX_B0_76", - "PSS2_IMUX_B0_77", - "PSS2_IMUX_B0_78", - "PSS2_IMUX_B0_79", - "PSS2_IMUX_B0_80", - "PSS2_IMUX_B0_81", - "PSS2_IMUX_B0_82", - "PSS2_IMUX_B0_83", - "PSS2_IMUX_B0_84", - "PSS2_IMUX_B0_85", - "PSS2_IMUX_B0_86", - "PSS2_IMUX_B0_87", - "PSS2_IMUX_B0_88", - "PSS2_IMUX_B0_89", - "PSS2_IMUX_B0_90", - "PSS2_IMUX_B0_91", - "PSS2_IMUX_B0_92", - "PSS2_IMUX_B0_93", - "PSS2_IMUX_B0_94", - "PSS2_IMUX_B0_95", - "PSS2_IMUX_B0_96", - "PSS2_IMUX_B0_97", - "PSS2_IMUX_B0_98", - "PSS2_IMUX_B0_99", - "PSS2_IMUX_B10_60", - "PSS2_IMUX_B10_61", - "PSS2_IMUX_B10_62", - "PSS2_IMUX_B10_63", - "PSS2_IMUX_B10_64", - "PSS2_IMUX_B10_65", - "PSS2_IMUX_B10_66", - "PSS2_IMUX_B10_67", - "PSS2_IMUX_B10_68", - "PSS2_IMUX_B10_69", - "PSS2_IMUX_B10_70", - "PSS2_IMUX_B10_71", - "PSS2_IMUX_B10_72", - "PSS2_IMUX_B10_73", - "PSS2_IMUX_B10_74", - "PSS2_IMUX_B10_75", - "PSS2_IMUX_B10_76", - "PSS2_IMUX_B10_77", - "PSS2_IMUX_B10_78", - "PSS2_IMUX_B10_79", - "PSS2_IMUX_B10_80", - "PSS2_IMUX_B10_81", - "PSS2_IMUX_B10_82", - "PSS2_IMUX_B10_83", - "PSS2_IMUX_B10_84", - "PSS2_IMUX_B10_85", - "PSS2_IMUX_B10_86", - "PSS2_IMUX_B10_87", - "PSS2_IMUX_B10_88", - "PSS2_IMUX_B10_89", - "PSS2_IMUX_B10_90", - "PSS2_IMUX_B10_91", - "PSS2_IMUX_B10_92", - "PSS2_IMUX_B10_93", - "PSS2_IMUX_B10_94", - "PSS2_IMUX_B10_95", - "PSS2_IMUX_B10_96", - "PSS2_IMUX_B10_97", - "PSS2_IMUX_B10_98", - "PSS2_IMUX_B10_99", - "PSS2_IMUX_B11_60", - "PSS2_IMUX_B11_61", - "PSS2_IMUX_B11_62", - "PSS2_IMUX_B11_63", - "PSS2_IMUX_B11_64", - "PSS2_IMUX_B11_65", - "PSS2_IMUX_B11_66", - "PSS2_IMUX_B11_67", - "PSS2_IMUX_B11_68", - "PSS2_IMUX_B11_69", - "PSS2_IMUX_B11_70", - "PSS2_IMUX_B11_71", - "PSS2_IMUX_B11_72", - "PSS2_IMUX_B11_73", - "PSS2_IMUX_B11_74", - "PSS2_IMUX_B11_75", - "PSS2_IMUX_B11_76", - "PSS2_IMUX_B11_77", - "PSS2_IMUX_B11_78", - "PSS2_IMUX_B11_79", - "PSS2_IMUX_B11_80", - "PSS2_IMUX_B11_81", - "PSS2_IMUX_B11_82", - "PSS2_IMUX_B11_83", - "PSS2_IMUX_B11_84", - "PSS2_IMUX_B11_85", - "PSS2_IMUX_B11_86", - "PSS2_IMUX_B11_87", - "PSS2_IMUX_B11_88", - "PSS2_IMUX_B11_89", - "PSS2_IMUX_B11_90", - "PSS2_IMUX_B11_91", - "PSS2_IMUX_B11_92", - "PSS2_IMUX_B11_93", - "PSS2_IMUX_B11_94", - "PSS2_IMUX_B11_95", - "PSS2_IMUX_B11_96", - "PSS2_IMUX_B11_97", - "PSS2_IMUX_B11_98", - "PSS2_IMUX_B11_99", - "PSS2_IMUX_B12_60", - "PSS2_IMUX_B12_61", - "PSS2_IMUX_B12_62", - "PSS2_IMUX_B12_63", - "PSS2_IMUX_B12_64", - "PSS2_IMUX_B12_65", - "PSS2_IMUX_B12_66", - "PSS2_IMUX_B12_67", - "PSS2_IMUX_B12_68", - "PSS2_IMUX_B12_69", - "PSS2_IMUX_B12_70", - "PSS2_IMUX_B12_71", - "PSS2_IMUX_B12_72", - "PSS2_IMUX_B12_73", - "PSS2_IMUX_B12_74", - "PSS2_IMUX_B12_75", - "PSS2_IMUX_B12_76", - "PSS2_IMUX_B12_77", - "PSS2_IMUX_B12_78", - "PSS2_IMUX_B12_79", - "PSS2_IMUX_B12_80", - "PSS2_IMUX_B12_81", - "PSS2_IMUX_B12_82", - "PSS2_IMUX_B12_83", - "PSS2_IMUX_B12_84", - "PSS2_IMUX_B12_85", - "PSS2_IMUX_B12_86", - "PSS2_IMUX_B12_87", - "PSS2_IMUX_B12_88", - "PSS2_IMUX_B12_89", - "PSS2_IMUX_B12_90", - "PSS2_IMUX_B12_91", - "PSS2_IMUX_B12_92", - "PSS2_IMUX_B12_93", - "PSS2_IMUX_B12_94", - "PSS2_IMUX_B12_95", - "PSS2_IMUX_B12_96", - "PSS2_IMUX_B12_97", - "PSS2_IMUX_B12_98", - "PSS2_IMUX_B12_99", - "PSS2_IMUX_B13_60", - "PSS2_IMUX_B13_61", - "PSS2_IMUX_B13_62", - "PSS2_IMUX_B13_63", - "PSS2_IMUX_B13_64", - "PSS2_IMUX_B13_65", - "PSS2_IMUX_B13_66", - "PSS2_IMUX_B13_67", - "PSS2_IMUX_B13_68", - "PSS2_IMUX_B13_69", - "PSS2_IMUX_B13_70", - "PSS2_IMUX_B13_71", - "PSS2_IMUX_B13_72", - "PSS2_IMUX_B13_73", - "PSS2_IMUX_B13_74", - "PSS2_IMUX_B13_75", - "PSS2_IMUX_B13_76", - "PSS2_IMUX_B13_77", - "PSS2_IMUX_B13_78", - "PSS2_IMUX_B13_79", - "PSS2_IMUX_B13_80", - "PSS2_IMUX_B13_81", - "PSS2_IMUX_B13_82", - "PSS2_IMUX_B13_83", - "PSS2_IMUX_B13_84", - "PSS2_IMUX_B13_85", - "PSS2_IMUX_B13_86", - "PSS2_IMUX_B13_87", - "PSS2_IMUX_B13_88", - "PSS2_IMUX_B13_89", - "PSS2_IMUX_B13_90", - "PSS2_IMUX_B13_91", - "PSS2_IMUX_B13_92", - "PSS2_IMUX_B13_93", - "PSS2_IMUX_B13_94", - "PSS2_IMUX_B13_95", - "PSS2_IMUX_B13_96", - "PSS2_IMUX_B13_97", - "PSS2_IMUX_B13_98", - "PSS2_IMUX_B13_99", - "PSS2_IMUX_B14_60", - "PSS2_IMUX_B14_61", - "PSS2_IMUX_B14_62", - "PSS2_IMUX_B14_63", - "PSS2_IMUX_B14_64", - "PSS2_IMUX_B14_65", - "PSS2_IMUX_B14_66", - "PSS2_IMUX_B14_67", - "PSS2_IMUX_B14_68", - "PSS2_IMUX_B14_69", - "PSS2_IMUX_B14_70", - "PSS2_IMUX_B14_71", - "PSS2_IMUX_B14_72", - "PSS2_IMUX_B14_73", - "PSS2_IMUX_B14_74", - "PSS2_IMUX_B14_75", - "PSS2_IMUX_B14_76", - "PSS2_IMUX_B14_77", - "PSS2_IMUX_B14_78", - "PSS2_IMUX_B14_79", - "PSS2_IMUX_B14_80", - "PSS2_IMUX_B14_81", - "PSS2_IMUX_B14_82", - "PSS2_IMUX_B14_83", - "PSS2_IMUX_B14_84", - "PSS2_IMUX_B14_85", - "PSS2_IMUX_B14_86", - "PSS2_IMUX_B14_87", - "PSS2_IMUX_B14_88", - "PSS2_IMUX_B14_89", - "PSS2_IMUX_B14_90", - "PSS2_IMUX_B14_91", - "PSS2_IMUX_B14_92", - "PSS2_IMUX_B14_93", - "PSS2_IMUX_B14_94", - "PSS2_IMUX_B14_95", - "PSS2_IMUX_B14_96", - "PSS2_IMUX_B14_97", - "PSS2_IMUX_B14_98", - "PSS2_IMUX_B14_99", - "PSS2_IMUX_B15_60", - "PSS2_IMUX_B15_61", - "PSS2_IMUX_B15_62", - "PSS2_IMUX_B15_63", - "PSS2_IMUX_B15_64", - "PSS2_IMUX_B15_65", - "PSS2_IMUX_B15_66", - "PSS2_IMUX_B15_67", - "PSS2_IMUX_B15_68", - "PSS2_IMUX_B15_69", - "PSS2_IMUX_B15_70", - "PSS2_IMUX_B15_71", - "PSS2_IMUX_B15_72", - "PSS2_IMUX_B15_73", - "PSS2_IMUX_B15_74", - "PSS2_IMUX_B15_75", - "PSS2_IMUX_B15_76", - "PSS2_IMUX_B15_77", - "PSS2_IMUX_B15_78", - "PSS2_IMUX_B15_79", - "PSS2_IMUX_B15_80", - "PSS2_IMUX_B15_81", - "PSS2_IMUX_B15_82", - "PSS2_IMUX_B15_83", - "PSS2_IMUX_B15_84", - "PSS2_IMUX_B15_85", - "PSS2_IMUX_B15_86", - "PSS2_IMUX_B15_87", - "PSS2_IMUX_B15_88", - "PSS2_IMUX_B15_89", - "PSS2_IMUX_B15_90", - "PSS2_IMUX_B15_91", - "PSS2_IMUX_B15_92", - "PSS2_IMUX_B15_93", - "PSS2_IMUX_B15_94", - "PSS2_IMUX_B15_95", - "PSS2_IMUX_B15_96", - "PSS2_IMUX_B15_97", - "PSS2_IMUX_B15_98", - "PSS2_IMUX_B15_99", - "PSS2_IMUX_B16_60", - "PSS2_IMUX_B16_61", - "PSS2_IMUX_B16_62", - "PSS2_IMUX_B16_63", - "PSS2_IMUX_B16_64", - "PSS2_IMUX_B16_65", - "PSS2_IMUX_B16_66", - "PSS2_IMUX_B16_67", - "PSS2_IMUX_B16_68", - "PSS2_IMUX_B16_69", - "PSS2_IMUX_B16_70", - "PSS2_IMUX_B16_71", - "PSS2_IMUX_B16_72", - "PSS2_IMUX_B16_73", - "PSS2_IMUX_B16_74", - "PSS2_IMUX_B16_75", - "PSS2_IMUX_B16_76", - "PSS2_IMUX_B16_77", - "PSS2_IMUX_B16_78", - "PSS2_IMUX_B16_79", - "PSS2_IMUX_B16_80", - "PSS2_IMUX_B16_81", - "PSS2_IMUX_B16_82", - "PSS2_IMUX_B16_83", - "PSS2_IMUX_B16_84", - "PSS2_IMUX_B16_85", - "PSS2_IMUX_B16_86", - "PSS2_IMUX_B16_87", - "PSS2_IMUX_B16_88", - "PSS2_IMUX_B16_89", - "PSS2_IMUX_B16_90", - "PSS2_IMUX_B16_91", - "PSS2_IMUX_B16_92", - "PSS2_IMUX_B16_93", - "PSS2_IMUX_B16_94", - "PSS2_IMUX_B16_95", - "PSS2_IMUX_B16_96", - "PSS2_IMUX_B16_97", - "PSS2_IMUX_B16_98", - "PSS2_IMUX_B16_99", - "PSS2_IMUX_B17_60", - "PSS2_IMUX_B17_61", - "PSS2_IMUX_B17_62", - "PSS2_IMUX_B17_63", - "PSS2_IMUX_B17_64", - "PSS2_IMUX_B17_65", - "PSS2_IMUX_B17_66", - "PSS2_IMUX_B17_67", - "PSS2_IMUX_B17_68", - "PSS2_IMUX_B17_69", - "PSS2_IMUX_B17_70", - "PSS2_IMUX_B17_71", - "PSS2_IMUX_B17_72", - "PSS2_IMUX_B17_73", - "PSS2_IMUX_B17_74", - "PSS2_IMUX_B17_75", - "PSS2_IMUX_B17_76", - "PSS2_IMUX_B17_77", - "PSS2_IMUX_B17_78", - "PSS2_IMUX_B17_79", - "PSS2_IMUX_B17_80", - "PSS2_IMUX_B17_81", - "PSS2_IMUX_B17_82", - "PSS2_IMUX_B17_83", - "PSS2_IMUX_B17_84", - "PSS2_IMUX_B17_85", - "PSS2_IMUX_B17_86", - "PSS2_IMUX_B17_87", - "PSS2_IMUX_B17_88", - "PSS2_IMUX_B17_89", - "PSS2_IMUX_B17_90", - "PSS2_IMUX_B17_91", - "PSS2_IMUX_B17_92", - "PSS2_IMUX_B17_93", - "PSS2_IMUX_B17_94", - "PSS2_IMUX_B17_95", - "PSS2_IMUX_B17_96", - "PSS2_IMUX_B17_97", - "PSS2_IMUX_B17_98", - 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"PSS2_IMUX_B19_64", - "PSS2_IMUX_B19_65", - "PSS2_IMUX_B19_66", - "PSS2_IMUX_B19_67", - "PSS2_IMUX_B19_68", - "PSS2_IMUX_B19_69", - "PSS2_IMUX_B19_70", - "PSS2_IMUX_B19_71", - "PSS2_IMUX_B19_72", - "PSS2_IMUX_B19_73", - "PSS2_IMUX_B19_74", - "PSS2_IMUX_B19_75", - "PSS2_IMUX_B19_76", - "PSS2_IMUX_B19_77", - "PSS2_IMUX_B19_78", - "PSS2_IMUX_B19_79", - "PSS2_IMUX_B19_80", - "PSS2_IMUX_B19_81", - "PSS2_IMUX_B19_82", - "PSS2_IMUX_B19_83", - "PSS2_IMUX_B19_84", - "PSS2_IMUX_B19_85", - "PSS2_IMUX_B19_86", - "PSS2_IMUX_B19_87", - "PSS2_IMUX_B19_88", - "PSS2_IMUX_B19_89", - "PSS2_IMUX_B19_90", - "PSS2_IMUX_B19_91", - "PSS2_IMUX_B19_92", - "PSS2_IMUX_B19_93", - "PSS2_IMUX_B19_94", - "PSS2_IMUX_B19_95", - "PSS2_IMUX_B19_96", - "PSS2_IMUX_B19_97", - "PSS2_IMUX_B19_98", - "PSS2_IMUX_B19_99", - "PSS2_IMUX_B1_60", - "PSS2_IMUX_B1_61", - "PSS2_IMUX_B1_62", - "PSS2_IMUX_B1_63", - "PSS2_IMUX_B1_64", - "PSS2_IMUX_B1_65", - "PSS2_IMUX_B1_66", - "PSS2_IMUX_B1_67", - "PSS2_IMUX_B1_68", - "PSS2_IMUX_B1_69", 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"PSS2_IMUX_B26_61", - "PSS2_IMUX_B26_62", - "PSS2_IMUX_B26_63", - "PSS2_IMUX_B26_64", - "PSS2_IMUX_B26_65", - "PSS2_IMUX_B26_66", - "PSS2_IMUX_B26_67", - "PSS2_IMUX_B26_68", - "PSS2_IMUX_B26_69", - "PSS2_IMUX_B26_70", - "PSS2_IMUX_B26_71", - "PSS2_IMUX_B26_72", - "PSS2_IMUX_B26_73", - "PSS2_IMUX_B26_74", - "PSS2_IMUX_B26_75", - "PSS2_IMUX_B26_76", - "PSS2_IMUX_B26_77", - "PSS2_IMUX_B26_78", - "PSS2_IMUX_B26_79", - "PSS2_IMUX_B26_80", - "PSS2_IMUX_B26_81", - "PSS2_IMUX_B26_82", - "PSS2_IMUX_B26_83", - "PSS2_IMUX_B26_84", - "PSS2_IMUX_B26_85", - "PSS2_IMUX_B26_86", - "PSS2_IMUX_B26_87", - "PSS2_IMUX_B26_88", - "PSS2_IMUX_B26_89", - "PSS2_IMUX_B26_90", - "PSS2_IMUX_B26_91", - "PSS2_IMUX_B26_92", - "PSS2_IMUX_B26_93", - "PSS2_IMUX_B26_94", - "PSS2_IMUX_B26_95", - "PSS2_IMUX_B26_96", - "PSS2_IMUX_B26_97", - "PSS2_IMUX_B26_98", - "PSS2_IMUX_B26_99", - "PSS2_IMUX_B27_60", - "PSS2_IMUX_B27_61", - "PSS2_IMUX_B27_62", - "PSS2_IMUX_B27_63", - "PSS2_IMUX_B27_64", - "PSS2_IMUX_B27_65", - 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"PSS2_IMUX_B8_78", - "PSS2_IMUX_B8_79", - "PSS2_IMUX_B8_80", - "PSS2_IMUX_B8_81", - "PSS2_IMUX_B8_82", - "PSS2_IMUX_B8_83", - "PSS2_IMUX_B8_84", - "PSS2_IMUX_B8_85", - "PSS2_IMUX_B8_86", - "PSS2_IMUX_B8_87", - "PSS2_IMUX_B8_88", - "PSS2_IMUX_B8_89", - "PSS2_IMUX_B8_90", - "PSS2_IMUX_B8_91", - "PSS2_IMUX_B8_92", - "PSS2_IMUX_B8_93", - "PSS2_IMUX_B8_94", - "PSS2_IMUX_B8_95", - "PSS2_IMUX_B8_96", - "PSS2_IMUX_B8_97", - "PSS2_IMUX_B8_98", - "PSS2_IMUX_B8_99", - "PSS2_IMUX_B9_60", - "PSS2_IMUX_B9_61", - "PSS2_IMUX_B9_62", - "PSS2_IMUX_B9_63", - "PSS2_IMUX_B9_64", - "PSS2_IMUX_B9_65", - "PSS2_IMUX_B9_66", - "PSS2_IMUX_B9_67", - "PSS2_IMUX_B9_68", - "PSS2_IMUX_B9_69", - "PSS2_IMUX_B9_70", - "PSS2_IMUX_B9_71", - "PSS2_IMUX_B9_72", - "PSS2_IMUX_B9_73", - "PSS2_IMUX_B9_74", - "PSS2_IMUX_B9_75", - "PSS2_IMUX_B9_76", - "PSS2_IMUX_B9_77", - "PSS2_IMUX_B9_78", - "PSS2_IMUX_B9_79", - "PSS2_IMUX_B9_80", - "PSS2_IMUX_B9_81", - "PSS2_IMUX_B9_82", - "PSS2_IMUX_B9_83", - "PSS2_IMUX_B9_84", - "PSS2_IMUX_B9_85", - "PSS2_IMUX_B9_86", - "PSS2_IMUX_B9_87", - "PSS2_IMUX_B9_88", - "PSS2_IMUX_B9_89", - "PSS2_IMUX_B9_90", - "PSS2_IMUX_B9_91", - "PSS2_IMUX_B9_92", - "PSS2_IMUX_B9_93", - "PSS2_IMUX_B9_94", - "PSS2_IMUX_B9_95", - "PSS2_IMUX_B9_96", - "PSS2_IMUX_B9_97", - "PSS2_IMUX_B9_98", - "PSS2_IMUX_B9_99", - "PSS2_LOGIC_OUTS0_60", - "PSS2_LOGIC_OUTS0_61", - "PSS2_LOGIC_OUTS0_62", - "PSS2_LOGIC_OUTS0_63", - "PSS2_LOGIC_OUTS0_64", - "PSS2_LOGIC_OUTS0_65", - "PSS2_LOGIC_OUTS0_66", - "PSS2_LOGIC_OUTS0_67", - "PSS2_LOGIC_OUTS0_68", - "PSS2_LOGIC_OUTS0_69", - "PSS2_LOGIC_OUTS0_70", - "PSS2_LOGIC_OUTS0_71", - "PSS2_LOGIC_OUTS0_72", - "PSS2_LOGIC_OUTS0_73", - "PSS2_LOGIC_OUTS0_74", - "PSS2_LOGIC_OUTS0_75", - "PSS2_LOGIC_OUTS0_76", - "PSS2_LOGIC_OUTS0_77", - "PSS2_LOGIC_OUTS0_78", - "PSS2_LOGIC_OUTS0_79", - "PSS2_LOGIC_OUTS0_80", - "PSS2_LOGIC_OUTS0_81", - "PSS2_LOGIC_OUTS0_82", - "PSS2_LOGIC_OUTS0_83", - "PSS2_LOGIC_OUTS0_84", - "PSS2_LOGIC_OUTS0_85", - "PSS2_LOGIC_OUTS0_86", - "PSS2_LOGIC_OUTS0_87", - "PSS2_LOGIC_OUTS0_88", - "PSS2_LOGIC_OUTS0_89", - "PSS2_LOGIC_OUTS0_90", - "PSS2_LOGIC_OUTS0_91", - "PSS2_LOGIC_OUTS0_92", - "PSS2_LOGIC_OUTS0_93", - "PSS2_LOGIC_OUTS0_94", - "PSS2_LOGIC_OUTS0_95", - "PSS2_LOGIC_OUTS0_96", - "PSS2_LOGIC_OUTS0_97", - "PSS2_LOGIC_OUTS0_98", - "PSS2_LOGIC_OUTS0_99", - "PSS2_LOGIC_OUTS10_60", - "PSS2_LOGIC_OUTS10_61", - "PSS2_LOGIC_OUTS10_62", - "PSS2_LOGIC_OUTS10_63", - "PSS2_LOGIC_OUTS10_64", - "PSS2_LOGIC_OUTS10_65", - "PSS2_LOGIC_OUTS10_66", - "PSS2_LOGIC_OUTS10_67", - "PSS2_LOGIC_OUTS10_68", - "PSS2_LOGIC_OUTS10_69", - "PSS2_LOGIC_OUTS10_70", - "PSS2_LOGIC_OUTS10_71", - "PSS2_LOGIC_OUTS10_72", - "PSS2_LOGIC_OUTS10_73", - "PSS2_LOGIC_OUTS10_74", - "PSS2_LOGIC_OUTS10_75", - "PSS2_LOGIC_OUTS10_76", - "PSS2_LOGIC_OUTS10_77", - "PSS2_LOGIC_OUTS10_78", - "PSS2_LOGIC_OUTS10_79", - "PSS2_LOGIC_OUTS10_80", - "PSS2_LOGIC_OUTS10_81", - "PSS2_LOGIC_OUTS10_82", - "PSS2_LOGIC_OUTS10_83", - "PSS2_LOGIC_OUTS10_84", - "PSS2_LOGIC_OUTS10_85", - "PSS2_LOGIC_OUTS10_86", - "PSS2_LOGIC_OUTS10_87", - "PSS2_LOGIC_OUTS10_88", - "PSS2_LOGIC_OUTS10_89", - "PSS2_LOGIC_OUTS10_90", - "PSS2_LOGIC_OUTS10_91", - "PSS2_LOGIC_OUTS10_92", - "PSS2_LOGIC_OUTS10_93", - "PSS2_LOGIC_OUTS10_94", - "PSS2_LOGIC_OUTS10_95", - "PSS2_LOGIC_OUTS10_96", - "PSS2_LOGIC_OUTS10_97", - "PSS2_LOGIC_OUTS10_98", - "PSS2_LOGIC_OUTS10_99", - "PSS2_LOGIC_OUTS11_60", - "PSS2_LOGIC_OUTS11_61", - "PSS2_LOGIC_OUTS11_62", - "PSS2_LOGIC_OUTS11_63", - "PSS2_LOGIC_OUTS11_64", - "PSS2_LOGIC_OUTS11_65", - "PSS2_LOGIC_OUTS11_66", - "PSS2_LOGIC_OUTS11_67", - "PSS2_LOGIC_OUTS11_68", - "PSS2_LOGIC_OUTS11_69", - "PSS2_LOGIC_OUTS11_70", - "PSS2_LOGIC_OUTS11_71", - "PSS2_LOGIC_OUTS11_72", - "PSS2_LOGIC_OUTS11_73", - "PSS2_LOGIC_OUTS11_74", - "PSS2_LOGIC_OUTS11_75", - "PSS2_LOGIC_OUTS11_76", - "PSS2_LOGIC_OUTS11_77", - "PSS2_LOGIC_OUTS11_78", - "PSS2_LOGIC_OUTS11_79", - "PSS2_LOGIC_OUTS11_80", - "PSS2_LOGIC_OUTS11_81", - "PSS2_LOGIC_OUTS11_82", - "PSS2_LOGIC_OUTS11_83", - "PSS2_LOGIC_OUTS11_84", - "PSS2_LOGIC_OUTS11_85", - "PSS2_LOGIC_OUTS11_86", - "PSS2_LOGIC_OUTS11_87", - "PSS2_LOGIC_OUTS11_88", - "PSS2_LOGIC_OUTS11_89", - "PSS2_LOGIC_OUTS11_90", - "PSS2_LOGIC_OUTS11_91", - "PSS2_LOGIC_OUTS11_92", - "PSS2_LOGIC_OUTS11_93", - "PSS2_LOGIC_OUTS11_94", - "PSS2_LOGIC_OUTS11_95", - "PSS2_LOGIC_OUTS11_96", - "PSS2_LOGIC_OUTS11_97", - "PSS2_LOGIC_OUTS11_98", - "PSS2_LOGIC_OUTS11_99", - "PSS2_LOGIC_OUTS12_60", - "PSS2_LOGIC_OUTS12_61", - "PSS2_LOGIC_OUTS12_62", - "PSS2_LOGIC_OUTS12_63", - "PSS2_LOGIC_OUTS12_64", - "PSS2_LOGIC_OUTS12_65", - "PSS2_LOGIC_OUTS12_66", - "PSS2_LOGIC_OUTS12_67", - "PSS2_LOGIC_OUTS12_68", - "PSS2_LOGIC_OUTS12_69", - "PSS2_LOGIC_OUTS12_70", - "PSS2_LOGIC_OUTS12_71", - "PSS2_LOGIC_OUTS12_72", - "PSS2_LOGIC_OUTS12_73", - "PSS2_LOGIC_OUTS12_74", - "PSS2_LOGIC_OUTS12_75", - "PSS2_LOGIC_OUTS12_76", - "PSS2_LOGIC_OUTS12_77", - "PSS2_LOGIC_OUTS12_78", - "PSS2_LOGIC_OUTS12_79", - "PSS2_LOGIC_OUTS12_80", - "PSS2_LOGIC_OUTS12_81", - "PSS2_LOGIC_OUTS12_82", - "PSS2_LOGIC_OUTS12_83", - "PSS2_LOGIC_OUTS12_84", - "PSS2_LOGIC_OUTS12_85", - "PSS2_LOGIC_OUTS12_86", - "PSS2_LOGIC_OUTS12_87", - "PSS2_LOGIC_OUTS12_88", - "PSS2_LOGIC_OUTS12_89", - "PSS2_LOGIC_OUTS12_90", - "PSS2_LOGIC_OUTS12_91", - "PSS2_LOGIC_OUTS12_92", - "PSS2_LOGIC_OUTS12_93", - "PSS2_LOGIC_OUTS12_94", - "PSS2_LOGIC_OUTS12_95", - "PSS2_LOGIC_OUTS12_96", - "PSS2_LOGIC_OUTS12_97", - "PSS2_LOGIC_OUTS12_98", - "PSS2_LOGIC_OUTS12_99", - "PSS2_LOGIC_OUTS13_60", - "PSS2_LOGIC_OUTS13_61", - "PSS2_LOGIC_OUTS13_62", - "PSS2_LOGIC_OUTS13_63", - "PSS2_LOGIC_OUTS13_64", - "PSS2_LOGIC_OUTS13_65", - "PSS2_LOGIC_OUTS13_66", - "PSS2_LOGIC_OUTS13_67", - "PSS2_LOGIC_OUTS13_68", - "PSS2_LOGIC_OUTS13_69", - "PSS2_LOGIC_OUTS13_70", - "PSS2_LOGIC_OUTS13_71", - "PSS2_LOGIC_OUTS13_72", - "PSS2_LOGIC_OUTS13_73", - "PSS2_LOGIC_OUTS13_74", - "PSS2_LOGIC_OUTS13_75", - "PSS2_LOGIC_OUTS13_76", - "PSS2_LOGIC_OUTS13_77", - "PSS2_LOGIC_OUTS13_78", - "PSS2_LOGIC_OUTS13_79", - "PSS2_LOGIC_OUTS13_80", - "PSS2_LOGIC_OUTS13_81", - "PSS2_LOGIC_OUTS13_82", - "PSS2_LOGIC_OUTS13_83", - "PSS2_LOGIC_OUTS13_84", - "PSS2_LOGIC_OUTS13_85", - "PSS2_LOGIC_OUTS13_86", - "PSS2_LOGIC_OUTS13_87", - "PSS2_LOGIC_OUTS13_88", - "PSS2_LOGIC_OUTS13_89", - "PSS2_LOGIC_OUTS13_90", - "PSS2_LOGIC_OUTS13_91", - "PSS2_LOGIC_OUTS13_92", - "PSS2_LOGIC_OUTS13_93", - "PSS2_LOGIC_OUTS13_94", - "PSS2_LOGIC_OUTS13_95", - "PSS2_LOGIC_OUTS13_96", - "PSS2_LOGIC_OUTS13_97", - "PSS2_LOGIC_OUTS13_98", - "PSS2_LOGIC_OUTS13_99", - "PSS2_LOGIC_OUTS14_60", - "PSS2_LOGIC_OUTS14_61", - "PSS2_LOGIC_OUTS14_62", - "PSS2_LOGIC_OUTS14_63", - "PSS2_LOGIC_OUTS14_64", - "PSS2_LOGIC_OUTS14_65", - "PSS2_LOGIC_OUTS14_66", - "PSS2_LOGIC_OUTS14_67", - "PSS2_LOGIC_OUTS14_68", - "PSS2_LOGIC_OUTS14_69", - "PSS2_LOGIC_OUTS14_70", - "PSS2_LOGIC_OUTS14_71", - "PSS2_LOGIC_OUTS14_72", - "PSS2_LOGIC_OUTS14_73", - "PSS2_LOGIC_OUTS14_74", - "PSS2_LOGIC_OUTS14_75", - "PSS2_LOGIC_OUTS14_76", - "PSS2_LOGIC_OUTS14_77", - "PSS2_LOGIC_OUTS14_78", - "PSS2_LOGIC_OUTS14_79", - "PSS2_LOGIC_OUTS14_80", - "PSS2_LOGIC_OUTS14_81", - "PSS2_LOGIC_OUTS14_82", - "PSS2_LOGIC_OUTS14_83", - "PSS2_LOGIC_OUTS14_84", - "PSS2_LOGIC_OUTS14_85", - "PSS2_LOGIC_OUTS14_86", - "PSS2_LOGIC_OUTS14_87", - "PSS2_LOGIC_OUTS14_88", - "PSS2_LOGIC_OUTS14_89", - "PSS2_LOGIC_OUTS14_90", - "PSS2_LOGIC_OUTS14_91", - "PSS2_LOGIC_OUTS14_92", - "PSS2_LOGIC_OUTS14_93", - "PSS2_LOGIC_OUTS14_94", - "PSS2_LOGIC_OUTS14_95", - "PSS2_LOGIC_OUTS14_96", - "PSS2_LOGIC_OUTS14_97", - "PSS2_LOGIC_OUTS14_98", - "PSS2_LOGIC_OUTS14_99", - "PSS2_LOGIC_OUTS15_60", - "PSS2_LOGIC_OUTS15_61", - "PSS2_LOGIC_OUTS15_62", - "PSS2_LOGIC_OUTS15_63", - "PSS2_LOGIC_OUTS15_64", - "PSS2_LOGIC_OUTS15_65", - "PSS2_LOGIC_OUTS15_66", - "PSS2_LOGIC_OUTS15_67", - "PSS2_LOGIC_OUTS15_68", - "PSS2_LOGIC_OUTS15_69", - "PSS2_LOGIC_OUTS15_70", - "PSS2_LOGIC_OUTS15_71", - "PSS2_LOGIC_OUTS15_72", - "PSS2_LOGIC_OUTS15_73", - "PSS2_LOGIC_OUTS15_74", - "PSS2_LOGIC_OUTS15_75", - "PSS2_LOGIC_OUTS15_76", - "PSS2_LOGIC_OUTS15_77", - "PSS2_LOGIC_OUTS15_78", - "PSS2_LOGIC_OUTS15_79", - "PSS2_LOGIC_OUTS15_80", - "PSS2_LOGIC_OUTS15_81", - "PSS2_LOGIC_OUTS15_82", - "PSS2_LOGIC_OUTS15_83", - "PSS2_LOGIC_OUTS15_84", - "PSS2_LOGIC_OUTS15_85", - "PSS2_LOGIC_OUTS15_86", - "PSS2_LOGIC_OUTS15_87", - "PSS2_LOGIC_OUTS15_88", - "PSS2_LOGIC_OUTS15_89", - "PSS2_LOGIC_OUTS15_90", - "PSS2_LOGIC_OUTS15_91", - "PSS2_LOGIC_OUTS15_92", - "PSS2_LOGIC_OUTS15_93", - "PSS2_LOGIC_OUTS15_94", - "PSS2_LOGIC_OUTS15_95", - "PSS2_LOGIC_OUTS15_96", - "PSS2_LOGIC_OUTS15_97", - "PSS2_LOGIC_OUTS15_98", - "PSS2_LOGIC_OUTS15_99", - "PSS2_LOGIC_OUTS16_60", - "PSS2_LOGIC_OUTS16_61", - "PSS2_LOGIC_OUTS16_62", - "PSS2_LOGIC_OUTS16_63", - "PSS2_LOGIC_OUTS16_64", - "PSS2_LOGIC_OUTS16_65", - "PSS2_LOGIC_OUTS16_66", - "PSS2_LOGIC_OUTS16_67", - "PSS2_LOGIC_OUTS16_68", - "PSS2_LOGIC_OUTS16_69", - "PSS2_LOGIC_OUTS16_70", - "PSS2_LOGIC_OUTS16_71", - "PSS2_LOGIC_OUTS16_72", - "PSS2_LOGIC_OUTS16_73", - "PSS2_LOGIC_OUTS16_74", - "PSS2_LOGIC_OUTS16_75", - "PSS2_LOGIC_OUTS16_76", - "PSS2_LOGIC_OUTS16_77", - "PSS2_LOGIC_OUTS16_78", - "PSS2_LOGIC_OUTS16_79", - "PSS2_LOGIC_OUTS16_80", - "PSS2_LOGIC_OUTS16_81", - "PSS2_LOGIC_OUTS16_82", - "PSS2_LOGIC_OUTS16_83", - "PSS2_LOGIC_OUTS16_84", - "PSS2_LOGIC_OUTS16_85", - "PSS2_LOGIC_OUTS16_86", - "PSS2_LOGIC_OUTS16_87", - "PSS2_LOGIC_OUTS16_88", - "PSS2_LOGIC_OUTS16_89", - "PSS2_LOGIC_OUTS16_90", - "PSS2_LOGIC_OUTS16_91", - "PSS2_LOGIC_OUTS16_92", - "PSS2_LOGIC_OUTS16_93", - "PSS2_LOGIC_OUTS16_94", - "PSS2_LOGIC_OUTS16_95", - "PSS2_LOGIC_OUTS16_96", - "PSS2_LOGIC_OUTS16_97", - "PSS2_LOGIC_OUTS16_98", - "PSS2_LOGIC_OUTS16_99", - "PSS2_LOGIC_OUTS17_60", - "PSS2_LOGIC_OUTS17_61", - "PSS2_LOGIC_OUTS17_62", - "PSS2_LOGIC_OUTS17_63", - "PSS2_LOGIC_OUTS17_64", - "PSS2_LOGIC_OUTS17_65", - "PSS2_LOGIC_OUTS17_66", - "PSS2_LOGIC_OUTS17_67", - "PSS2_LOGIC_OUTS17_68", - "PSS2_LOGIC_OUTS17_69", - "PSS2_LOGIC_OUTS17_70", - "PSS2_LOGIC_OUTS17_71", - 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- "PSS2_LOGIC_OUTS5_97", - "PSS2_LOGIC_OUTS5_98", - "PSS2_LOGIC_OUTS5_99", - "PSS2_LOGIC_OUTS6_60", - "PSS2_LOGIC_OUTS6_61", - "PSS2_LOGIC_OUTS6_62", - "PSS2_LOGIC_OUTS6_63", - "PSS2_LOGIC_OUTS6_64", - "PSS2_LOGIC_OUTS6_65", - "PSS2_LOGIC_OUTS6_66", - "PSS2_LOGIC_OUTS6_67", - "PSS2_LOGIC_OUTS6_68", - "PSS2_LOGIC_OUTS6_69", - "PSS2_LOGIC_OUTS6_70", - "PSS2_LOGIC_OUTS6_71", - "PSS2_LOGIC_OUTS6_72", - "PSS2_LOGIC_OUTS6_73", - "PSS2_LOGIC_OUTS6_74", - "PSS2_LOGIC_OUTS6_75", - "PSS2_LOGIC_OUTS6_76", - "PSS2_LOGIC_OUTS6_77", - "PSS2_LOGIC_OUTS6_78", - "PSS2_LOGIC_OUTS6_79", - "PSS2_LOGIC_OUTS6_80", - "PSS2_LOGIC_OUTS6_81", - "PSS2_LOGIC_OUTS6_82", - "PSS2_LOGIC_OUTS6_83", - "PSS2_LOGIC_OUTS6_84", - "PSS2_LOGIC_OUTS6_85", - "PSS2_LOGIC_OUTS6_86", - "PSS2_LOGIC_OUTS6_87", - "PSS2_LOGIC_OUTS6_88", - "PSS2_LOGIC_OUTS6_89", - "PSS2_LOGIC_OUTS6_90", - "PSS2_LOGIC_OUTS6_91", - "PSS2_LOGIC_OUTS6_92", - "PSS2_LOGIC_OUTS6_93", - "PSS2_LOGIC_OUTS6_94", - "PSS2_LOGIC_OUTS6_95", - "PSS2_LOGIC_OUTS6_96", - "PSS2_LOGIC_OUTS6_97", - "PSS2_LOGIC_OUTS6_98", - "PSS2_LOGIC_OUTS6_99", - "PSS2_LOGIC_OUTS7_60", - "PSS2_LOGIC_OUTS7_61", - "PSS2_LOGIC_OUTS7_62", - "PSS2_LOGIC_OUTS7_63", - "PSS2_LOGIC_OUTS7_64", - "PSS2_LOGIC_OUTS7_65", - "PSS2_LOGIC_OUTS7_66", - "PSS2_LOGIC_OUTS7_67", - "PSS2_LOGIC_OUTS7_68", - "PSS2_LOGIC_OUTS7_69", - "PSS2_LOGIC_OUTS7_70", - "PSS2_LOGIC_OUTS7_71", - "PSS2_LOGIC_OUTS7_72", - "PSS2_LOGIC_OUTS7_73", - "PSS2_LOGIC_OUTS7_74", - "PSS2_LOGIC_OUTS7_75", - "PSS2_LOGIC_OUTS7_76", - "PSS2_LOGIC_OUTS7_77", - "PSS2_LOGIC_OUTS7_78", - "PSS2_LOGIC_OUTS7_79", - "PSS2_LOGIC_OUTS7_80", - "PSS2_LOGIC_OUTS7_81", - "PSS2_LOGIC_OUTS7_82", - "PSS2_LOGIC_OUTS7_83", - "PSS2_LOGIC_OUTS7_84", - "PSS2_LOGIC_OUTS7_85", - "PSS2_LOGIC_OUTS7_86", - "PSS2_LOGIC_OUTS7_87", - "PSS2_LOGIC_OUTS7_88", - "PSS2_LOGIC_OUTS7_89", - "PSS2_LOGIC_OUTS7_90", - "PSS2_LOGIC_OUTS7_91", - "PSS2_LOGIC_OUTS7_92", - "PSS2_LOGIC_OUTS7_93", - "PSS2_LOGIC_OUTS7_94", - "PSS2_LOGIC_OUTS7_95", - "PSS2_LOGIC_OUTS7_96", - "PSS2_LOGIC_OUTS7_97", - "PSS2_LOGIC_OUTS7_98", - "PSS2_LOGIC_OUTS7_99", - "PSS2_LOGIC_OUTS8_60", - "PSS2_LOGIC_OUTS8_61", - "PSS2_LOGIC_OUTS8_62", - "PSS2_LOGIC_OUTS8_63", - "PSS2_LOGIC_OUTS8_64", - "PSS2_LOGIC_OUTS8_65", - "PSS2_LOGIC_OUTS8_66", - "PSS2_LOGIC_OUTS8_67", - "PSS2_LOGIC_OUTS8_68", - "PSS2_LOGIC_OUTS8_69", - "PSS2_LOGIC_OUTS8_70", - "PSS2_LOGIC_OUTS8_71", - "PSS2_LOGIC_OUTS8_72", - "PSS2_LOGIC_OUTS8_73", - "PSS2_LOGIC_OUTS8_74", - "PSS2_LOGIC_OUTS8_75", - "PSS2_LOGIC_OUTS8_76", - "PSS2_LOGIC_OUTS8_77", - "PSS2_LOGIC_OUTS8_78", - "PSS2_LOGIC_OUTS8_79", - "PSS2_LOGIC_OUTS8_80", - "PSS2_LOGIC_OUTS8_81", - "PSS2_LOGIC_OUTS8_82", - "PSS2_LOGIC_OUTS8_83", - "PSS2_LOGIC_OUTS8_84", - "PSS2_LOGIC_OUTS8_85", - "PSS2_LOGIC_OUTS8_86", - "PSS2_LOGIC_OUTS8_87", - "PSS2_LOGIC_OUTS8_88", - "PSS2_LOGIC_OUTS8_89", - "PSS2_LOGIC_OUTS8_90", - "PSS2_LOGIC_OUTS8_91", - "PSS2_LOGIC_OUTS8_92", - "PSS2_LOGIC_OUTS8_93", - "PSS2_LOGIC_OUTS8_94", - "PSS2_LOGIC_OUTS8_95", - "PSS2_LOGIC_OUTS8_96", - "PSS2_LOGIC_OUTS8_97", - "PSS2_LOGIC_OUTS8_98", - "PSS2_LOGIC_OUTS8_99", - "PSS2_LOGIC_OUTS9_60", - "PSS2_LOGIC_OUTS9_61", - "PSS2_LOGIC_OUTS9_62", - "PSS2_LOGIC_OUTS9_63", - "PSS2_LOGIC_OUTS9_64", - "PSS2_LOGIC_OUTS9_65", - "PSS2_LOGIC_OUTS9_66", - "PSS2_LOGIC_OUTS9_67", - "PSS2_LOGIC_OUTS9_68", - "PSS2_LOGIC_OUTS9_69", - "PSS2_LOGIC_OUTS9_70", - "PSS2_LOGIC_OUTS9_71", - "PSS2_LOGIC_OUTS9_72", - "PSS2_LOGIC_OUTS9_73", - "PSS2_LOGIC_OUTS9_74", - "PSS2_LOGIC_OUTS9_75", - "PSS2_LOGIC_OUTS9_76", - "PSS2_LOGIC_OUTS9_77", - "PSS2_LOGIC_OUTS9_78", - "PSS2_LOGIC_OUTS9_79", - "PSS2_LOGIC_OUTS9_80", - "PSS2_LOGIC_OUTS9_81", - "PSS2_LOGIC_OUTS9_82", - "PSS2_LOGIC_OUTS9_83", - "PSS2_LOGIC_OUTS9_84", - "PSS2_LOGIC_OUTS9_85", - "PSS2_LOGIC_OUTS9_86", - "PSS2_LOGIC_OUTS9_87", - "PSS2_LOGIC_OUTS9_88", - "PSS2_LOGIC_OUTS9_89", - "PSS2_LOGIC_OUTS9_90", - "PSS2_LOGIC_OUTS9_91", - "PSS2_LOGIC_OUTS9_92", - "PSS2_LOGIC_OUTS9_93", - "PSS2_LOGIC_OUTS9_94", - "PSS2_LOGIC_OUTS9_95", - "PSS2_LOGIC_OUTS9_96", - "PSS2_LOGIC_OUTS9_97", - "PSS2_LOGIC_OUTS9_98", - "PSS2_LOGIC_OUTS9_99", - "PSS_BYP_B0_0", - "PSS_BYP_B0_1", - "PSS_BYP_B0_10", - "PSS_BYP_B0_11", - "PSS_BYP_B0_12", - "PSS_BYP_B0_13", - "PSS_BYP_B0_14", - "PSS_BYP_B0_15", - "PSS_BYP_B0_16", - "PSS_BYP_B0_17", - "PSS_BYP_B0_18", - "PSS_BYP_B0_19", - "PSS_BYP_B0_2", - "PSS_BYP_B0_3", - "PSS_BYP_B0_4", - "PSS_BYP_B0_5", - "PSS_BYP_B0_6", - "PSS_BYP_B0_7", - "PSS_BYP_B0_8", - "PSS_BYP_B0_9", - "PSS_BYP_B1_0", - "PSS_BYP_B1_1", - "PSS_BYP_B1_10", - "PSS_BYP_B1_11", - "PSS_BYP_B1_12", - "PSS_BYP_B1_13", - "PSS_BYP_B1_14", - "PSS_BYP_B1_15", - "PSS_BYP_B1_16", - "PSS_BYP_B1_17", - "PSS_BYP_B1_18", - "PSS_BYP_B1_19", - "PSS_BYP_B1_2", - "PSS_BYP_B1_3", - "PSS_BYP_B1_4", - "PSS_BYP_B1_5", - "PSS_BYP_B1_6", - "PSS_BYP_B1_7", - "PSS_BYP_B1_8", - "PSS_BYP_B1_9", - "PSS_BYP_B2_0", - "PSS_BYP_B2_1", - "PSS_BYP_B2_10", - "PSS_BYP_B2_11", - "PSS_BYP_B2_12", - "PSS_BYP_B2_13", - "PSS_BYP_B2_14", - "PSS_BYP_B2_15", - "PSS_BYP_B2_16", - "PSS_BYP_B2_17", - "PSS_BYP_B2_18", - "PSS_BYP_B2_19", - "PSS_BYP_B2_2", - "PSS_BYP_B2_3", - "PSS_BYP_B2_4", - "PSS_BYP_B2_5", - "PSS_BYP_B2_6", - "PSS_BYP_B2_7", - "PSS_BYP_B2_8", - "PSS_BYP_B2_9", - "PSS_BYP_B3_0", - "PSS_BYP_B3_1", - "PSS_BYP_B3_10", - "PSS_BYP_B3_11", - "PSS_BYP_B3_12", - "PSS_BYP_B3_13", - "PSS_BYP_B3_14", - "PSS_BYP_B3_15", - "PSS_BYP_B3_16", - "PSS_BYP_B3_17", - "PSS_BYP_B3_18", - "PSS_BYP_B3_19", - "PSS_BYP_B3_2", - "PSS_BYP_B3_3", - "PSS_BYP_B3_4", - "PSS_BYP_B3_5", - "PSS_BYP_B3_6", - "PSS_BYP_B3_7", - "PSS_BYP_B3_8", - "PSS_BYP_B3_9", - "PSS_BYP_B4_0", - "PSS_BYP_B4_1", - "PSS_BYP_B4_10", - "PSS_BYP_B4_11", - "PSS_BYP_B4_12", - "PSS_BYP_B4_13", - "PSS_BYP_B4_14", - "PSS_BYP_B4_15", - "PSS_BYP_B4_16", - "PSS_BYP_B4_17", - "PSS_BYP_B4_18", - "PSS_BYP_B4_19", - "PSS_BYP_B4_2", - "PSS_BYP_B4_3", - "PSS_BYP_B4_4", - "PSS_BYP_B4_5", - "PSS_BYP_B4_6", - "PSS_BYP_B4_7", - "PSS_BYP_B4_8", - "PSS_BYP_B4_9", - "PSS_BYP_B5_0", - "PSS_BYP_B5_1", - "PSS_BYP_B5_10", - "PSS_BYP_B5_11", - "PSS_BYP_B5_12", - "PSS_BYP_B5_13", - "PSS_BYP_B5_14", - "PSS_BYP_B5_15", - "PSS_BYP_B5_16", - "PSS_BYP_B5_17", - "PSS_BYP_B5_18", - "PSS_BYP_B5_19", - "PSS_BYP_B5_2", - "PSS_BYP_B5_3", - "PSS_BYP_B5_4", - "PSS_BYP_B5_5", - "PSS_BYP_B5_6", - "PSS_BYP_B5_7", - "PSS_BYP_B5_8", - "PSS_BYP_B5_9", - "PSS_BYP_B6_0", - "PSS_BYP_B6_1", - "PSS_BYP_B6_10", - "PSS_BYP_B6_11", - "PSS_BYP_B6_12", - "PSS_BYP_B6_13", - "PSS_BYP_B6_14", - "PSS_BYP_B6_15", - "PSS_BYP_B6_16", - "PSS_BYP_B6_17", - "PSS_BYP_B6_18", - "PSS_BYP_B6_19", - "PSS_BYP_B6_2", - "PSS_BYP_B6_3", - "PSS_BYP_B6_4", - "PSS_BYP_B6_5", - "PSS_BYP_B6_6", - "PSS_BYP_B6_7", - "PSS_BYP_B6_8", - "PSS_BYP_B6_9", - "PSS_BYP_B7_0", - "PSS_BYP_B7_1", - "PSS_BYP_B7_10", - "PSS_BYP_B7_11", - "PSS_BYP_B7_12", - "PSS_BYP_B7_13", - "PSS_BYP_B7_14", - "PSS_BYP_B7_15", - "PSS_BYP_B7_16", - "PSS_BYP_B7_17", - "PSS_BYP_B7_18", - "PSS_BYP_B7_19", - "PSS_BYP_B7_2", - "PSS_BYP_B7_3", - "PSS_BYP_B7_4", - "PSS_BYP_B7_5", - "PSS_BYP_B7_6", - "PSS_BYP_B7_7", - "PSS_BYP_B7_8", - "PSS_BYP_B7_9", - "PSS_CLK_B0_0", - "PSS_CLK_B0_1", - "PSS_CLK_B0_10", - "PSS_CLK_B0_11", - "PSS_CLK_B0_12", - "PSS_CLK_B0_13", - "PSS_CLK_B0_14", - "PSS_CLK_B0_15", - "PSS_CLK_B0_16", - "PSS_CLK_B0_17", - "PSS_CLK_B0_18", - "PSS_CLK_B0_19", - "PSS_CLK_B0_2", - "PSS_CLK_B0_3", - "PSS_CLK_B0_4", - "PSS_CLK_B0_5", - "PSS_CLK_B0_6", - "PSS_CLK_B0_7", - "PSS_CLK_B0_8", - "PSS_CLK_B0_9", - "PSS_CLK_B1_0", - "PSS_CLK_B1_1", - "PSS_CLK_B1_10", - "PSS_CLK_B1_11", - "PSS_CLK_B1_12", - "PSS_CLK_B1_13", - "PSS_CLK_B1_14", - "PSS_CLK_B1_15", - "PSS_CLK_B1_16", - "PSS_CLK_B1_17", - "PSS_CLK_B1_18", - "PSS_CLK_B1_19", - "PSS_CLK_B1_2", - "PSS_CLK_B1_3", - "PSS_CLK_B1_4", - "PSS_CLK_B1_5", - "PSS_CLK_B1_6", - "PSS_CLK_B1_7", - "PSS_CLK_B1_8", - "PSS_CLK_B1_9", - "PSS_CTRL_B0_0", - "PSS_CTRL_B0_1", - "PSS_CTRL_B0_10", - "PSS_CTRL_B0_11", - "PSS_CTRL_B0_12", - "PSS_CTRL_B0_13", - "PSS_CTRL_B0_14", - "PSS_CTRL_B0_15", - "PSS_CTRL_B0_16", - "PSS_CTRL_B0_17", - "PSS_CTRL_B0_18", - "PSS_CTRL_B0_19", - "PSS_CTRL_B0_2", - "PSS_CTRL_B0_3", - "PSS_CTRL_B0_4", - "PSS_CTRL_B0_5", - "PSS_CTRL_B0_6", - "PSS_CTRL_B0_7", - "PSS_CTRL_B0_8", - "PSS_CTRL_B0_9", - "PSS_CTRL_B1_0", - "PSS_CTRL_B1_1", - "PSS_CTRL_B1_10", - "PSS_CTRL_B1_11", - "PSS_CTRL_B1_12", - "PSS_CTRL_B1_13", - "PSS_CTRL_B1_14", - "PSS_CTRL_B1_15", - "PSS_CTRL_B1_16", - "PSS_CTRL_B1_17", - "PSS_CTRL_B1_18", - "PSS_CTRL_B1_19", - "PSS_CTRL_B1_2", - "PSS_CTRL_B1_3", - "PSS_CTRL_B1_4", - "PSS_CTRL_B1_5", - "PSS_CTRL_B1_6", - "PSS_CTRL_B1_7", - "PSS_CTRL_B1_8", - "PSS_CTRL_B1_9", - "PSS_FAN_B0_0", - "PSS_FAN_B0_1", - "PSS_FAN_B0_10", - "PSS_FAN_B0_11", - "PSS_FAN_B0_12", - "PSS_FAN_B0_13", - "PSS_FAN_B0_14", - "PSS_FAN_B0_15", - "PSS_FAN_B0_16", - "PSS_FAN_B0_17", - "PSS_FAN_B0_18", - "PSS_FAN_B0_19", - "PSS_FAN_B0_2", - "PSS_FAN_B0_3", - "PSS_FAN_B0_4", - "PSS_FAN_B0_5", - "PSS_FAN_B0_6", - "PSS_FAN_B0_7", - "PSS_FAN_B0_8", - "PSS_FAN_B0_9", - "PSS_FAN_B1_0", - "PSS_FAN_B1_1", - "PSS_FAN_B1_10", - "PSS_FAN_B1_11", - "PSS_FAN_B1_12", - "PSS_FAN_B1_13", - "PSS_FAN_B1_14", - "PSS_FAN_B1_15", - "PSS_FAN_B1_16", - "PSS_FAN_B1_17", - "PSS_FAN_B1_18", - "PSS_FAN_B1_19", - "PSS_FAN_B1_2", - "PSS_FAN_B1_3", - "PSS_FAN_B1_4", - "PSS_FAN_B1_5", - "PSS_FAN_B1_6", - "PSS_FAN_B1_7", - "PSS_FAN_B1_8", - "PSS_FAN_B1_9", - "PSS_FAN_B2_0", - "PSS_FAN_B2_1", - "PSS_FAN_B2_10", - "PSS_FAN_B2_11", - "PSS_FAN_B2_12", - "PSS_FAN_B2_13", - "PSS_FAN_B2_14", - "PSS_FAN_B2_15", - "PSS_FAN_B2_16", - "PSS_FAN_B2_17", - "PSS_FAN_B2_18", - "PSS_FAN_B2_19", - "PSS_FAN_B2_2", - "PSS_FAN_B2_3", - "PSS_FAN_B2_4", - "PSS_FAN_B2_5", - "PSS_FAN_B2_6", - "PSS_FAN_B2_7", - "PSS_FAN_B2_8", - "PSS_FAN_B2_9", - "PSS_FAN_B3_0", - "PSS_FAN_B3_1", - "PSS_FAN_B3_10", - "PSS_FAN_B3_11", - "PSS_FAN_B3_12", - "PSS_FAN_B3_13", - "PSS_FAN_B3_14", - "PSS_FAN_B3_15", - "PSS_FAN_B3_16", - "PSS_FAN_B3_17", - "PSS_FAN_B3_18", - "PSS_FAN_B3_19", - "PSS_FAN_B3_2", - "PSS_FAN_B3_3", - "PSS_FAN_B3_4", - "PSS_FAN_B3_5", - "PSS_FAN_B3_6", - "PSS_FAN_B3_7", - "PSS_FAN_B3_8", - "PSS_FAN_B3_9", - "PSS_FAN_B4_0", - "PSS_FAN_B4_1", - "PSS_FAN_B4_10", - "PSS_FAN_B4_11", - "PSS_FAN_B4_12", - "PSS_FAN_B4_13", - "PSS_FAN_B4_14", - "PSS_FAN_B4_15", - "PSS_FAN_B4_16", - "PSS_FAN_B4_17", - "PSS_FAN_B4_18", - "PSS_FAN_B4_19", - "PSS_FAN_B4_2", - "PSS_FAN_B4_3", - "PSS_FAN_B4_4", - "PSS_FAN_B4_5", - "PSS_FAN_B4_6", - "PSS_FAN_B4_7", - "PSS_FAN_B4_8", - "PSS_FAN_B4_9", - "PSS_FAN_B5_0", - "PSS_FAN_B5_1", - "PSS_FAN_B5_10", - "PSS_FAN_B5_11", - "PSS_FAN_B5_12", - "PSS_FAN_B5_13", - "PSS_FAN_B5_14", - "PSS_FAN_B5_15", - "PSS_FAN_B5_16", - "PSS_FAN_B5_17", - "PSS_FAN_B5_18", - "PSS_FAN_B5_19", - "PSS_FAN_B5_2", - "PSS_FAN_B5_3", - "PSS_FAN_B5_4", - "PSS_FAN_B5_5", - "PSS_FAN_B5_6", - "PSS_FAN_B5_7", - "PSS_FAN_B5_8", - "PSS_FAN_B5_9", - "PSS_FAN_B6_0", - "PSS_FAN_B6_1", - "PSS_FAN_B6_10", - "PSS_FAN_B6_11", - "PSS_FAN_B6_12", - "PSS_FAN_B6_13", - "PSS_FAN_B6_14", - "PSS_FAN_B6_15", - "PSS_FAN_B6_16", - "PSS_FAN_B6_17", - "PSS_FAN_B6_18", - "PSS_FAN_B6_19", - "PSS_FAN_B6_2", - "PSS_FAN_B6_3", - "PSS_FAN_B6_4", - "PSS_FAN_B6_5", - "PSS_FAN_B6_6", - "PSS_FAN_B6_7", - "PSS_FAN_B6_8", - "PSS_FAN_B6_9", - "PSS_FAN_B7_0", - "PSS_FAN_B7_1", - "PSS_FAN_B7_10", - "PSS_FAN_B7_11", - "PSS_FAN_B7_12", - "PSS_FAN_B7_13", - "PSS_FAN_B7_14", - "PSS_FAN_B7_15", - "PSS_FAN_B7_16", - "PSS_FAN_B7_17", - "PSS_FAN_B7_18", - "PSS_FAN_B7_19", - "PSS_FAN_B7_2", - "PSS_FAN_B7_3", - "PSS_FAN_B7_4", - "PSS_FAN_B7_5", - "PSS_FAN_B7_6", - "PSS_FAN_B7_7", - "PSS_FAN_B7_8", - "PSS_FAN_B7_9", - "PSS_FCLKCLK0", - "PSS_FCLKCLK1", - "PSS_IMUX_B0_0", - "PSS_IMUX_B0_1", - "PSS_IMUX_B0_10", - "PSS_IMUX_B0_11", - "PSS_IMUX_B0_12", - "PSS_IMUX_B0_13", - "PSS_IMUX_B0_14", - "PSS_IMUX_B0_15", - "PSS_IMUX_B0_16", - "PSS_IMUX_B0_17", - "PSS_IMUX_B0_18", - "PSS_IMUX_B0_19", - "PSS_IMUX_B0_2", - "PSS_IMUX_B0_3", - "PSS_IMUX_B0_4", - "PSS_IMUX_B0_5", - "PSS_IMUX_B0_6", - "PSS_IMUX_B0_7", - "PSS_IMUX_B0_8", - "PSS_IMUX_B0_9", - "PSS_IMUX_B10_0", - "PSS_IMUX_B10_1", - "PSS_IMUX_B10_10", - "PSS_IMUX_B10_11", - "PSS_IMUX_B10_12", - "PSS_IMUX_B10_13", - "PSS_IMUX_B10_14", - "PSS_IMUX_B10_15", - "PSS_IMUX_B10_16", - "PSS_IMUX_B10_17", - "PSS_IMUX_B10_18", - "PSS_IMUX_B10_19", - "PSS_IMUX_B10_2", - "PSS_IMUX_B10_3", - "PSS_IMUX_B10_4", - "PSS_IMUX_B10_5", - "PSS_IMUX_B10_6", - "PSS_IMUX_B10_7", - "PSS_IMUX_B10_8", - "PSS_IMUX_B10_9", - "PSS_IMUX_B11_0", - "PSS_IMUX_B11_1", - "PSS_IMUX_B11_10", - "PSS_IMUX_B11_11", - "PSS_IMUX_B11_12", - "PSS_IMUX_B11_13", - "PSS_IMUX_B11_14", - "PSS_IMUX_B11_15", - "PSS_IMUX_B11_16", - "PSS_IMUX_B11_17", - "PSS_IMUX_B11_18", - "PSS_IMUX_B11_19", - "PSS_IMUX_B11_2", - "PSS_IMUX_B11_3", - "PSS_IMUX_B11_4", - "PSS_IMUX_B11_5", - "PSS_IMUX_B11_6", - "PSS_IMUX_B11_7", - "PSS_IMUX_B11_8", - "PSS_IMUX_B11_9", - "PSS_IMUX_B12_0", - "PSS_IMUX_B12_1", - "PSS_IMUX_B12_10", - "PSS_IMUX_B12_11", - "PSS_IMUX_B12_12", - "PSS_IMUX_B12_13", - "PSS_IMUX_B12_14", - "PSS_IMUX_B12_15", - "PSS_IMUX_B12_16", - "PSS_IMUX_B12_17", - "PSS_IMUX_B12_18", - "PSS_IMUX_B12_19", - "PSS_IMUX_B12_2", - "PSS_IMUX_B12_3", - "PSS_IMUX_B12_4", - "PSS_IMUX_B12_5", - "PSS_IMUX_B12_6", - "PSS_IMUX_B12_7", - "PSS_IMUX_B12_8", - "PSS_IMUX_B12_9", - "PSS_IMUX_B13_0", - "PSS_IMUX_B13_1", - "PSS_IMUX_B13_10", - "PSS_IMUX_B13_11", - "PSS_IMUX_B13_12", - "PSS_IMUX_B13_13", - "PSS_IMUX_B13_14", - "PSS_IMUX_B13_15", - "PSS_IMUX_B13_16", - "PSS_IMUX_B13_17", - "PSS_IMUX_B13_18", - "PSS_IMUX_B13_19", - "PSS_IMUX_B13_2", - "PSS_IMUX_B13_3", - "PSS_IMUX_B13_4", - "PSS_IMUX_B13_5", - "PSS_IMUX_B13_6", - "PSS_IMUX_B13_7", - "PSS_IMUX_B13_8", - "PSS_IMUX_B13_9", - "PSS_IMUX_B14_0", - "PSS_IMUX_B14_1", - "PSS_IMUX_B14_10", - "PSS_IMUX_B14_11", - "PSS_IMUX_B14_12", - "PSS_IMUX_B14_13", - "PSS_IMUX_B14_14", - "PSS_IMUX_B14_15", - "PSS_IMUX_B14_16", - "PSS_IMUX_B14_17", - "PSS_IMUX_B14_18", - "PSS_IMUX_B14_19", - "PSS_IMUX_B14_2", - "PSS_IMUX_B14_3", - "PSS_IMUX_B14_4", - "PSS_IMUX_B14_5", - "PSS_IMUX_B14_6", - "PSS_IMUX_B14_7", - "PSS_IMUX_B14_8", - "PSS_IMUX_B14_9", - "PSS_IMUX_B15_0", - "PSS_IMUX_B15_1", - "PSS_IMUX_B15_10", - "PSS_IMUX_B15_11", - "PSS_IMUX_B15_12", - "PSS_IMUX_B15_13", - "PSS_IMUX_B15_14", - "PSS_IMUX_B15_15", - "PSS_IMUX_B15_16", - "PSS_IMUX_B15_17", - "PSS_IMUX_B15_18", - "PSS_IMUX_B15_19", - "PSS_IMUX_B15_2", - "PSS_IMUX_B15_3", - "PSS_IMUX_B15_4", - "PSS_IMUX_B15_5", - "PSS_IMUX_B15_6", - "PSS_IMUX_B15_7", - "PSS_IMUX_B15_8", - "PSS_IMUX_B15_9", - "PSS_IMUX_B16_0", - "PSS_IMUX_B16_1", - "PSS_IMUX_B16_10", - "PSS_IMUX_B16_11", - "PSS_IMUX_B16_12", - "PSS_IMUX_B16_13", - "PSS_IMUX_B16_14", - "PSS_IMUX_B16_15", - "PSS_IMUX_B16_16", - "PSS_IMUX_B16_17", - "PSS_IMUX_B16_18", - "PSS_IMUX_B16_19", - "PSS_IMUX_B16_2", - "PSS_IMUX_B16_3", - "PSS_IMUX_B16_4", - "PSS_IMUX_B16_5", - "PSS_IMUX_B16_6", - "PSS_IMUX_B16_7", - "PSS_IMUX_B16_8", - "PSS_IMUX_B16_9", - "PSS_IMUX_B17_0", - "PSS_IMUX_B17_1", - "PSS_IMUX_B17_10", - "PSS_IMUX_B17_11", - "PSS_IMUX_B17_12", - "PSS_IMUX_B17_13", - "PSS_IMUX_B17_14", - "PSS_IMUX_B17_15", - "PSS_IMUX_B17_16", - "PSS_IMUX_B17_17", - "PSS_IMUX_B17_18", - "PSS_IMUX_B17_19", - "PSS_IMUX_B17_2", - "PSS_IMUX_B17_3", - "PSS_IMUX_B17_4", - "PSS_IMUX_B17_5", - "PSS_IMUX_B17_6", - "PSS_IMUX_B17_7", - "PSS_IMUX_B17_8", - "PSS_IMUX_B17_9", - "PSS_IMUX_B18_0", - "PSS_IMUX_B18_1", - "PSS_IMUX_B18_10", - "PSS_IMUX_B18_11", - "PSS_IMUX_B18_12", - "PSS_IMUX_B18_13", - "PSS_IMUX_B18_14", - "PSS_IMUX_B18_15", - "PSS_IMUX_B18_16", - "PSS_IMUX_B18_17", - "PSS_IMUX_B18_18", - "PSS_IMUX_B18_19", - "PSS_IMUX_B18_2", - "PSS_IMUX_B18_3", - "PSS_IMUX_B18_4", - "PSS_IMUX_B18_5", - "PSS_IMUX_B18_6", - "PSS_IMUX_B18_7", - "PSS_IMUX_B18_8", - "PSS_IMUX_B18_9", - "PSS_IMUX_B19_0", - "PSS_IMUX_B19_1", - "PSS_IMUX_B19_10", - "PSS_IMUX_B19_11", - "PSS_IMUX_B19_12", - "PSS_IMUX_B19_13", - "PSS_IMUX_B19_14", - "PSS_IMUX_B19_15", - "PSS_IMUX_B19_16", - "PSS_IMUX_B19_17", - "PSS_IMUX_B19_18", - "PSS_IMUX_B19_19", - "PSS_IMUX_B19_2", - "PSS_IMUX_B19_3", - "PSS_IMUX_B19_4", - "PSS_IMUX_B19_5", - "PSS_IMUX_B19_6", - "PSS_IMUX_B19_7", - "PSS_IMUX_B19_8", - "PSS_IMUX_B19_9", - "PSS_IMUX_B1_0", - "PSS_IMUX_B1_1", - "PSS_IMUX_B1_10", - "PSS_IMUX_B1_11", - "PSS_IMUX_B1_12", - "PSS_IMUX_B1_13", - "PSS_IMUX_B1_14", - "PSS_IMUX_B1_15", - "PSS_IMUX_B1_16", - "PSS_IMUX_B1_17", - "PSS_IMUX_B1_18", - "PSS_IMUX_B1_19", - "PSS_IMUX_B1_2", - "PSS_IMUX_B1_3", - "PSS_IMUX_B1_4", - "PSS_IMUX_B1_5", - "PSS_IMUX_B1_6", - "PSS_IMUX_B1_7", - "PSS_IMUX_B1_8", - "PSS_IMUX_B1_9", - "PSS_IMUX_B20_0", - "PSS_IMUX_B20_1", - "PSS_IMUX_B20_10", - "PSS_IMUX_B20_11", - "PSS_IMUX_B20_12", - "PSS_IMUX_B20_13", - "PSS_IMUX_B20_14", - "PSS_IMUX_B20_15", - "PSS_IMUX_B20_16", - "PSS_IMUX_B20_17", - "PSS_IMUX_B20_18", - "PSS_IMUX_B20_19", - "PSS_IMUX_B20_2", - "PSS_IMUX_B20_3", - "PSS_IMUX_B20_4", - "PSS_IMUX_B20_5", - "PSS_IMUX_B20_6", - "PSS_IMUX_B20_7", - "PSS_IMUX_B20_8", - "PSS_IMUX_B20_9", - "PSS_IMUX_B21_0", - "PSS_IMUX_B21_1", - "PSS_IMUX_B21_10", - "PSS_IMUX_B21_11", - "PSS_IMUX_B21_12", - "PSS_IMUX_B21_13", - "PSS_IMUX_B21_14", - "PSS_IMUX_B21_15", - "PSS_IMUX_B21_16", - "PSS_IMUX_B21_17", - "PSS_IMUX_B21_18", - "PSS_IMUX_B21_19", - "PSS_IMUX_B21_2", - "PSS_IMUX_B21_3", - "PSS_IMUX_B21_4", - "PSS_IMUX_B21_5", - "PSS_IMUX_B21_6", - "PSS_IMUX_B21_7", - "PSS_IMUX_B21_8", - "PSS_IMUX_B21_9", - "PSS_IMUX_B22_0", - "PSS_IMUX_B22_1", - "PSS_IMUX_B22_10", - "PSS_IMUX_B22_11", - "PSS_IMUX_B22_12", - "PSS_IMUX_B22_13", - "PSS_IMUX_B22_14", - "PSS_IMUX_B22_15", - "PSS_IMUX_B22_16", - "PSS_IMUX_B22_17", - "PSS_IMUX_B22_18", - "PSS_IMUX_B22_19", - "PSS_IMUX_B22_2", - "PSS_IMUX_B22_3", - "PSS_IMUX_B22_4", - "PSS_IMUX_B22_5", - "PSS_IMUX_B22_6", - "PSS_IMUX_B22_7", - "PSS_IMUX_B22_8", - "PSS_IMUX_B22_9", - "PSS_IMUX_B23_0", - "PSS_IMUX_B23_1", - "PSS_IMUX_B23_10", - "PSS_IMUX_B23_11", - "PSS_IMUX_B23_12", - "PSS_IMUX_B23_13", - "PSS_IMUX_B23_14", - "PSS_IMUX_B23_15", - "PSS_IMUX_B23_16", - "PSS_IMUX_B23_17", - "PSS_IMUX_B23_18", - "PSS_IMUX_B23_19", - "PSS_IMUX_B23_2", - "PSS_IMUX_B23_3", - "PSS_IMUX_B23_4", - "PSS_IMUX_B23_5", - "PSS_IMUX_B23_6", - "PSS_IMUX_B23_7", - "PSS_IMUX_B23_8", - "PSS_IMUX_B23_9", - "PSS_IMUX_B24_0", - "PSS_IMUX_B24_1", - "PSS_IMUX_B24_10", - "PSS_IMUX_B24_11", - "PSS_IMUX_B24_12", - "PSS_IMUX_B24_13", - "PSS_IMUX_B24_14", - "PSS_IMUX_B24_15", - "PSS_IMUX_B24_16", - "PSS_IMUX_B24_17", - "PSS_IMUX_B24_18", - "PSS_IMUX_B24_19", - "PSS_IMUX_B24_2", - "PSS_IMUX_B24_3", - "PSS_IMUX_B24_4", - "PSS_IMUX_B24_5", - "PSS_IMUX_B24_6", - "PSS_IMUX_B24_7", - "PSS_IMUX_B24_8", - "PSS_IMUX_B24_9", - "PSS_IMUX_B25_0", - "PSS_IMUX_B25_1", - "PSS_IMUX_B25_10", - "PSS_IMUX_B25_11", - "PSS_IMUX_B25_12", - "PSS_IMUX_B25_13", - "PSS_IMUX_B25_14", - "PSS_IMUX_B25_15", - "PSS_IMUX_B25_16", - "PSS_IMUX_B25_17", - "PSS_IMUX_B25_18", - "PSS_IMUX_B25_19", - "PSS_IMUX_B25_2", - "PSS_IMUX_B25_3", - "PSS_IMUX_B25_4", - "PSS_IMUX_B25_5", - "PSS_IMUX_B25_6", - "PSS_IMUX_B25_7", - "PSS_IMUX_B25_8", - "PSS_IMUX_B25_9", - "PSS_IMUX_B26_0", - "PSS_IMUX_B26_1", - "PSS_IMUX_B26_10", - "PSS_IMUX_B26_11", - "PSS_IMUX_B26_12", - "PSS_IMUX_B26_13", - "PSS_IMUX_B26_14", - "PSS_IMUX_B26_15", - "PSS_IMUX_B26_16", - "PSS_IMUX_B26_17", - "PSS_IMUX_B26_18", - "PSS_IMUX_B26_19", - "PSS_IMUX_B26_2", - "PSS_IMUX_B26_3", - "PSS_IMUX_B26_4", - "PSS_IMUX_B26_5", - "PSS_IMUX_B26_6", - "PSS_IMUX_B26_7", - "PSS_IMUX_B26_8", - "PSS_IMUX_B26_9", - "PSS_IMUX_B27_0", - "PSS_IMUX_B27_1", - "PSS_IMUX_B27_10", - "PSS_IMUX_B27_11", - "PSS_IMUX_B27_12", - "PSS_IMUX_B27_13", - "PSS_IMUX_B27_14", - "PSS_IMUX_B27_15", - "PSS_IMUX_B27_16", - "PSS_IMUX_B27_17", - "PSS_IMUX_B27_18", - "PSS_IMUX_B27_19", - "PSS_IMUX_B27_2", - "PSS_IMUX_B27_3", - "PSS_IMUX_B27_4", - "PSS_IMUX_B27_5", - "PSS_IMUX_B27_6", - "PSS_IMUX_B27_7", - "PSS_IMUX_B27_8", - "PSS_IMUX_B27_9", - "PSS_IMUX_B28_0", - "PSS_IMUX_B28_1", - "PSS_IMUX_B28_10", - "PSS_IMUX_B28_11", - "PSS_IMUX_B28_12", - "PSS_IMUX_B28_13", - "PSS_IMUX_B28_14", - "PSS_IMUX_B28_15", - "PSS_IMUX_B28_16", - "PSS_IMUX_B28_17", - "PSS_IMUX_B28_18", - "PSS_IMUX_B28_19", - "PSS_IMUX_B28_2", - "PSS_IMUX_B28_3", - "PSS_IMUX_B28_4", - "PSS_IMUX_B28_5", - "PSS_IMUX_B28_6", - "PSS_IMUX_B28_7", - "PSS_IMUX_B28_8", - "PSS_IMUX_B28_9", - "PSS_IMUX_B29_0", - "PSS_IMUX_B29_1", - "PSS_IMUX_B29_10", - "PSS_IMUX_B29_11", - "PSS_IMUX_B29_12", - "PSS_IMUX_B29_13", - "PSS_IMUX_B29_14", - "PSS_IMUX_B29_15", - "PSS_IMUX_B29_16", - "PSS_IMUX_B29_17", - "PSS_IMUX_B29_18", - "PSS_IMUX_B29_19", - "PSS_IMUX_B29_2", - "PSS_IMUX_B29_3", - "PSS_IMUX_B29_4", - "PSS_IMUX_B29_5", - "PSS_IMUX_B29_6", - "PSS_IMUX_B29_7", - "PSS_IMUX_B29_8", - "PSS_IMUX_B29_9", - "PSS_IMUX_B2_0", - "PSS_IMUX_B2_1", - "PSS_IMUX_B2_10", - "PSS_IMUX_B2_11", - "PSS_IMUX_B2_12", - "PSS_IMUX_B2_13", - "PSS_IMUX_B2_14", - "PSS_IMUX_B2_15", - "PSS_IMUX_B2_16", - "PSS_IMUX_B2_17", - "PSS_IMUX_B2_18", - "PSS_IMUX_B2_19", - "PSS_IMUX_B2_2", - "PSS_IMUX_B2_3", - "PSS_IMUX_B2_4", - "PSS_IMUX_B2_5", - "PSS_IMUX_B2_6", - "PSS_IMUX_B2_7", - "PSS_IMUX_B2_8", - "PSS_IMUX_B2_9", - "PSS_IMUX_B30_0", - "PSS_IMUX_B30_1", - "PSS_IMUX_B30_10", - "PSS_IMUX_B30_11", - "PSS_IMUX_B30_12", - "PSS_IMUX_B30_13", - "PSS_IMUX_B30_14", - "PSS_IMUX_B30_15", - "PSS_IMUX_B30_16", - "PSS_IMUX_B30_17", - "PSS_IMUX_B30_18", - "PSS_IMUX_B30_19", - "PSS_IMUX_B30_2", - "PSS_IMUX_B30_3", - "PSS_IMUX_B30_4", - "PSS_IMUX_B30_5", - "PSS_IMUX_B30_6", - "PSS_IMUX_B30_7", - "PSS_IMUX_B30_8", - "PSS_IMUX_B30_9", - "PSS_IMUX_B31_0", - "PSS_IMUX_B31_1", - "PSS_IMUX_B31_10", - "PSS_IMUX_B31_11", - "PSS_IMUX_B31_12", - "PSS_IMUX_B31_13", - "PSS_IMUX_B31_14", - "PSS_IMUX_B31_15", - "PSS_IMUX_B31_16", - "PSS_IMUX_B31_17", - "PSS_IMUX_B31_18", - "PSS_IMUX_B31_19", - "PSS_IMUX_B31_2", - "PSS_IMUX_B31_3", - "PSS_IMUX_B31_4", - "PSS_IMUX_B31_5", - "PSS_IMUX_B31_6", - "PSS_IMUX_B31_7", - "PSS_IMUX_B31_8", - "PSS_IMUX_B31_9", - "PSS_IMUX_B32_0", - "PSS_IMUX_B32_1", - "PSS_IMUX_B32_10", - "PSS_IMUX_B32_11", - "PSS_IMUX_B32_12", - "PSS_IMUX_B32_13", - "PSS_IMUX_B32_14", - "PSS_IMUX_B32_15", - "PSS_IMUX_B32_16", - "PSS_IMUX_B32_17", - "PSS_IMUX_B32_18", - "PSS_IMUX_B32_19", - "PSS_IMUX_B32_2", - "PSS_IMUX_B32_3", - "PSS_IMUX_B32_4", - "PSS_IMUX_B32_5", - "PSS_IMUX_B32_6", - "PSS_IMUX_B32_7", - "PSS_IMUX_B32_8", - "PSS_IMUX_B32_9", - "PSS_IMUX_B33_0", - "PSS_IMUX_B33_1", - "PSS_IMUX_B33_10", - "PSS_IMUX_B33_11", - "PSS_IMUX_B33_12", - "PSS_IMUX_B33_13", - "PSS_IMUX_B33_14", - "PSS_IMUX_B33_15", - "PSS_IMUX_B33_16", - "PSS_IMUX_B33_17", - "PSS_IMUX_B33_18", - "PSS_IMUX_B33_19", - "PSS_IMUX_B33_2", - "PSS_IMUX_B33_3", - "PSS_IMUX_B33_4", - "PSS_IMUX_B33_5", - "PSS_IMUX_B33_6", - "PSS_IMUX_B33_7", - "PSS_IMUX_B33_8", - "PSS_IMUX_B33_9", - "PSS_IMUX_B34_0", - "PSS_IMUX_B34_1", - "PSS_IMUX_B34_10", - "PSS_IMUX_B34_11", - "PSS_IMUX_B34_12", - "PSS_IMUX_B34_13", - "PSS_IMUX_B34_14", - "PSS_IMUX_B34_15", - "PSS_IMUX_B34_16", - "PSS_IMUX_B34_17", - "PSS_IMUX_B34_18", - "PSS_IMUX_B34_19", - "PSS_IMUX_B34_2", - "PSS_IMUX_B34_3", - "PSS_IMUX_B34_4", - "PSS_IMUX_B34_5", - "PSS_IMUX_B34_6", - "PSS_IMUX_B34_7", - "PSS_IMUX_B34_8", - "PSS_IMUX_B34_9", - "PSS_IMUX_B35_0", - "PSS_IMUX_B35_1", - "PSS_IMUX_B35_10", - "PSS_IMUX_B35_11", - "PSS_IMUX_B35_12", - "PSS_IMUX_B35_13", - "PSS_IMUX_B35_14", - "PSS_IMUX_B35_15", - "PSS_IMUX_B35_16", - "PSS_IMUX_B35_17", - "PSS_IMUX_B35_18", - "PSS_IMUX_B35_19", - "PSS_IMUX_B35_2", - "PSS_IMUX_B35_3", - "PSS_IMUX_B35_4", - "PSS_IMUX_B35_5", - "PSS_IMUX_B35_6", - "PSS_IMUX_B35_7", - "PSS_IMUX_B35_8", - "PSS_IMUX_B35_9", - "PSS_IMUX_B36_0", - "PSS_IMUX_B36_1", - "PSS_IMUX_B36_10", - "PSS_IMUX_B36_11", - "PSS_IMUX_B36_12", - "PSS_IMUX_B36_13", - "PSS_IMUX_B36_14", - "PSS_IMUX_B36_15", - "PSS_IMUX_B36_16", - "PSS_IMUX_B36_17", - "PSS_IMUX_B36_18", - "PSS_IMUX_B36_19", - "PSS_IMUX_B36_2", - "PSS_IMUX_B36_3", - "PSS_IMUX_B36_4", - "PSS_IMUX_B36_5", - "PSS_IMUX_B36_6", - "PSS_IMUX_B36_7", - "PSS_IMUX_B36_8", - "PSS_IMUX_B36_9", - "PSS_IMUX_B37_0", - "PSS_IMUX_B37_1", - "PSS_IMUX_B37_10", - "PSS_IMUX_B37_11", - "PSS_IMUX_B37_12", - "PSS_IMUX_B37_13", - "PSS_IMUX_B37_14", - "PSS_IMUX_B37_15", - "PSS_IMUX_B37_16", - "PSS_IMUX_B37_17", - "PSS_IMUX_B37_18", - "PSS_IMUX_B37_19", - "PSS_IMUX_B37_2", - "PSS_IMUX_B37_3", - "PSS_IMUX_B37_4", - "PSS_IMUX_B37_5", - "PSS_IMUX_B37_6", - "PSS_IMUX_B37_7", - "PSS_IMUX_B37_8", - "PSS_IMUX_B37_9", - "PSS_IMUX_B38_0", - "PSS_IMUX_B38_1", - "PSS_IMUX_B38_10", - "PSS_IMUX_B38_11", - "PSS_IMUX_B38_12", - "PSS_IMUX_B38_13", - "PSS_IMUX_B38_14", - "PSS_IMUX_B38_15", - "PSS_IMUX_B38_16", - "PSS_IMUX_B38_17", - "PSS_IMUX_B38_18", - "PSS_IMUX_B38_19", - "PSS_IMUX_B38_2", - "PSS_IMUX_B38_3", - "PSS_IMUX_B38_4", - "PSS_IMUX_B38_5", - "PSS_IMUX_B38_6", - "PSS_IMUX_B38_7", - "PSS_IMUX_B38_8", - "PSS_IMUX_B38_9", - "PSS_IMUX_B39_0", - "PSS_IMUX_B39_1", - "PSS_IMUX_B39_10", - "PSS_IMUX_B39_11", - "PSS_IMUX_B39_12", - "PSS_IMUX_B39_13", - "PSS_IMUX_B39_14", - "PSS_IMUX_B39_15", - "PSS_IMUX_B39_16", - "PSS_IMUX_B39_17", - "PSS_IMUX_B39_18", - "PSS_IMUX_B39_19", - "PSS_IMUX_B39_2", - "PSS_IMUX_B39_3", - "PSS_IMUX_B39_4", - "PSS_IMUX_B39_5", - "PSS_IMUX_B39_6", - "PSS_IMUX_B39_7", - "PSS_IMUX_B39_8", - "PSS_IMUX_B39_9", - "PSS_IMUX_B3_0", - "PSS_IMUX_B3_1", - "PSS_IMUX_B3_10", - "PSS_IMUX_B3_11", - "PSS_IMUX_B3_12", - "PSS_IMUX_B3_13", - "PSS_IMUX_B3_14", - "PSS_IMUX_B3_15", - "PSS_IMUX_B3_16", - "PSS_IMUX_B3_17", - "PSS_IMUX_B3_18", - "PSS_IMUX_B3_19", - "PSS_IMUX_B3_2", - "PSS_IMUX_B3_3", - "PSS_IMUX_B3_4", - "PSS_IMUX_B3_5", - "PSS_IMUX_B3_6", - "PSS_IMUX_B3_7", - "PSS_IMUX_B3_8", - "PSS_IMUX_B3_9", - "PSS_IMUX_B40_0", - "PSS_IMUX_B40_1", - "PSS_IMUX_B40_10", - "PSS_IMUX_B40_11", - "PSS_IMUX_B40_12", - "PSS_IMUX_B40_13", - "PSS_IMUX_B40_14", - "PSS_IMUX_B40_15", - "PSS_IMUX_B40_16", - "PSS_IMUX_B40_17", - "PSS_IMUX_B40_18", - "PSS_IMUX_B40_19", - "PSS_IMUX_B40_2", - "PSS_IMUX_B40_3", - "PSS_IMUX_B40_4", - "PSS_IMUX_B40_5", - "PSS_IMUX_B40_6", - "PSS_IMUX_B40_7", - "PSS_IMUX_B40_8", - "PSS_IMUX_B40_9", - "PSS_IMUX_B41_0", - "PSS_IMUX_B41_1", - "PSS_IMUX_B41_10", - "PSS_IMUX_B41_11", - "PSS_IMUX_B41_12", - "PSS_IMUX_B41_13", - "PSS_IMUX_B41_14", - "PSS_IMUX_B41_15", - "PSS_IMUX_B41_16", - "PSS_IMUX_B41_17", - "PSS_IMUX_B41_18", - "PSS_IMUX_B41_19", - "PSS_IMUX_B41_2", - "PSS_IMUX_B41_3", - "PSS_IMUX_B41_4", - "PSS_IMUX_B41_5", - "PSS_IMUX_B41_6", - "PSS_IMUX_B41_7", - "PSS_IMUX_B41_8", - "PSS_IMUX_B41_9", - "PSS_IMUX_B42_0", - "PSS_IMUX_B42_1", - "PSS_IMUX_B42_10", - "PSS_IMUX_B42_11", - "PSS_IMUX_B42_12", - "PSS_IMUX_B42_13", - "PSS_IMUX_B42_14", - "PSS_IMUX_B42_15", - "PSS_IMUX_B42_16", - "PSS_IMUX_B42_17", - "PSS_IMUX_B42_18", - "PSS_IMUX_B42_19", - "PSS_IMUX_B42_2", - "PSS_IMUX_B42_3", - "PSS_IMUX_B42_4", - "PSS_IMUX_B42_5", - "PSS_IMUX_B42_6", - "PSS_IMUX_B42_7", - "PSS_IMUX_B42_8", - "PSS_IMUX_B42_9", - "PSS_IMUX_B43_0", - "PSS_IMUX_B43_1", - "PSS_IMUX_B43_10", - "PSS_IMUX_B43_11", - "PSS_IMUX_B43_12", - "PSS_IMUX_B43_13", - "PSS_IMUX_B43_14", - "PSS_IMUX_B43_15", - "PSS_IMUX_B43_16", - "PSS_IMUX_B43_17", - "PSS_IMUX_B43_18", - "PSS_IMUX_B43_19", - "PSS_IMUX_B43_2", - "PSS_IMUX_B43_3", - "PSS_IMUX_B43_4", - "PSS_IMUX_B43_5", - "PSS_IMUX_B43_6", - "PSS_IMUX_B43_7", - "PSS_IMUX_B43_8", - "PSS_IMUX_B43_9", - "PSS_IMUX_B44_0", - "PSS_IMUX_B44_1", - "PSS_IMUX_B44_10", - "PSS_IMUX_B44_11", - "PSS_IMUX_B44_12", - "PSS_IMUX_B44_13", - "PSS_IMUX_B44_14", - "PSS_IMUX_B44_15", - "PSS_IMUX_B44_16", - "PSS_IMUX_B44_17", - "PSS_IMUX_B44_18", - "PSS_IMUX_B44_19", - "PSS_IMUX_B44_2", - "PSS_IMUX_B44_3", - "PSS_IMUX_B44_4", - "PSS_IMUX_B44_5", - "PSS_IMUX_B44_6", - "PSS_IMUX_B44_7", - "PSS_IMUX_B44_8", - "PSS_IMUX_B44_9", - "PSS_IMUX_B45_0", - "PSS_IMUX_B45_1", - "PSS_IMUX_B45_10", - "PSS_IMUX_B45_11", - "PSS_IMUX_B45_12", - "PSS_IMUX_B45_13", - "PSS_IMUX_B45_14", - "PSS_IMUX_B45_15", - "PSS_IMUX_B45_16", - "PSS_IMUX_B45_17", - "PSS_IMUX_B45_18", - "PSS_IMUX_B45_19", - "PSS_IMUX_B45_2", - "PSS_IMUX_B45_3", - "PSS_IMUX_B45_4", - "PSS_IMUX_B45_5", - "PSS_IMUX_B45_6", - "PSS_IMUX_B45_7", - "PSS_IMUX_B45_8", - "PSS_IMUX_B45_9", - "PSS_IMUX_B46_0", - "PSS_IMUX_B46_1", - "PSS_IMUX_B46_10", - "PSS_IMUX_B46_11", - "PSS_IMUX_B46_12", - "PSS_IMUX_B46_13", - "PSS_IMUX_B46_14", - "PSS_IMUX_B46_15", - "PSS_IMUX_B46_16", - "PSS_IMUX_B46_17", - "PSS_IMUX_B46_18", - "PSS_IMUX_B46_19", - "PSS_IMUX_B46_2", - "PSS_IMUX_B46_3", - "PSS_IMUX_B46_4", - "PSS_IMUX_B46_5", - "PSS_IMUX_B46_6", - "PSS_IMUX_B46_7", - "PSS_IMUX_B46_8", - "PSS_IMUX_B46_9", - "PSS_IMUX_B47_0", - "PSS_IMUX_B47_1", - "PSS_IMUX_B47_10", - "PSS_IMUX_B47_11", - "PSS_IMUX_B47_12", - "PSS_IMUX_B47_13", - "PSS_IMUX_B47_14", - "PSS_IMUX_B47_15", - "PSS_IMUX_B47_16", - "PSS_IMUX_B47_17", - "PSS_IMUX_B47_18", - "PSS_IMUX_B47_19", - "PSS_IMUX_B47_2", - "PSS_IMUX_B47_3", - "PSS_IMUX_B47_4", - "PSS_IMUX_B47_5", - "PSS_IMUX_B47_6", - "PSS_IMUX_B47_7", - "PSS_IMUX_B47_8", - "PSS_IMUX_B47_9", - "PSS_IMUX_B4_0", - "PSS_IMUX_B4_1", - "PSS_IMUX_B4_10", - "PSS_IMUX_B4_11", - "PSS_IMUX_B4_12", - "PSS_IMUX_B4_13", - "PSS_IMUX_B4_14", - "PSS_IMUX_B4_15", - "PSS_IMUX_B4_16", - "PSS_IMUX_B4_17", - "PSS_IMUX_B4_18", - "PSS_IMUX_B4_19", - "PSS_IMUX_B4_2", - "PSS_IMUX_B4_3", - "PSS_IMUX_B4_4", - "PSS_IMUX_B4_5", - "PSS_IMUX_B4_6", - "PSS_IMUX_B4_7", - "PSS_IMUX_B4_8", - "PSS_IMUX_B4_9", - "PSS_IMUX_B5_0", - "PSS_IMUX_B5_1", - "PSS_IMUX_B5_10", - "PSS_IMUX_B5_11", - "PSS_IMUX_B5_12", - "PSS_IMUX_B5_13", - "PSS_IMUX_B5_14", - "PSS_IMUX_B5_15", - "PSS_IMUX_B5_16", - "PSS_IMUX_B5_17", - "PSS_IMUX_B5_18", - "PSS_IMUX_B5_19", - "PSS_IMUX_B5_2", - "PSS_IMUX_B5_3", - "PSS_IMUX_B5_4", - "PSS_IMUX_B5_5", - "PSS_IMUX_B5_6", - "PSS_IMUX_B5_7", - "PSS_IMUX_B5_8", - "PSS_IMUX_B5_9", - "PSS_IMUX_B6_0", - "PSS_IMUX_B6_1", - "PSS_IMUX_B6_10", - "PSS_IMUX_B6_11", - "PSS_IMUX_B6_12", - "PSS_IMUX_B6_13", - "PSS_IMUX_B6_14", - "PSS_IMUX_B6_15", - "PSS_IMUX_B6_16", - "PSS_IMUX_B6_17", - "PSS_IMUX_B6_18", - "PSS_IMUX_B6_19", - "PSS_IMUX_B6_2", - "PSS_IMUX_B6_3", - "PSS_IMUX_B6_4", - "PSS_IMUX_B6_5", - "PSS_IMUX_B6_6", - "PSS_IMUX_B6_7", - "PSS_IMUX_B6_8", - "PSS_IMUX_B6_9", - "PSS_IMUX_B7_0", - "PSS_IMUX_B7_1", - "PSS_IMUX_B7_10", - "PSS_IMUX_B7_11", - "PSS_IMUX_B7_12", - "PSS_IMUX_B7_13", - "PSS_IMUX_B7_14", - "PSS_IMUX_B7_15", - "PSS_IMUX_B7_16", - "PSS_IMUX_B7_17", - "PSS_IMUX_B7_18", - "PSS_IMUX_B7_19", - "PSS_IMUX_B7_2", - "PSS_IMUX_B7_3", - "PSS_IMUX_B7_4", - "PSS_IMUX_B7_5", - "PSS_IMUX_B7_6", - "PSS_IMUX_B7_7", - "PSS_IMUX_B7_8", - "PSS_IMUX_B7_9", - "PSS_IMUX_B8_0", - "PSS_IMUX_B8_1", - "PSS_IMUX_B8_10", - "PSS_IMUX_B8_11", - "PSS_IMUX_B8_12", - "PSS_IMUX_B8_13", - "PSS_IMUX_B8_14", - "PSS_IMUX_B8_15", - "PSS_IMUX_B8_16", - "PSS_IMUX_B8_17", - "PSS_IMUX_B8_18", - "PSS_IMUX_B8_19", - "PSS_IMUX_B8_2", - "PSS_IMUX_B8_3", - "PSS_IMUX_B8_4", - "PSS_IMUX_B8_5", - "PSS_IMUX_B8_6", - "PSS_IMUX_B8_7", - "PSS_IMUX_B8_8", - "PSS_IMUX_B8_9", - "PSS_IMUX_B9_0", - "PSS_IMUX_B9_1", - "PSS_IMUX_B9_10", - "PSS_IMUX_B9_11", - "PSS_IMUX_B9_12", - "PSS_IMUX_B9_13", - "PSS_IMUX_B9_14", - "PSS_IMUX_B9_15", - "PSS_IMUX_B9_16", - "PSS_IMUX_B9_17", - "PSS_IMUX_B9_18", - "PSS_IMUX_B9_19", - "PSS_IMUX_B9_2", - "PSS_IMUX_B9_3", - "PSS_IMUX_B9_4", - "PSS_IMUX_B9_5", - "PSS_IMUX_B9_6", - "PSS_IMUX_B9_7", - "PSS_IMUX_B9_8", - "PSS_IMUX_B9_9", - "PSS_LOGIC_OUTS0_0", - "PSS_LOGIC_OUTS0_1", - "PSS_LOGIC_OUTS0_10", - "PSS_LOGIC_OUTS0_11", - "PSS_LOGIC_OUTS0_12", - "PSS_LOGIC_OUTS0_13", - "PSS_LOGIC_OUTS0_14", - "PSS_LOGIC_OUTS0_15", - "PSS_LOGIC_OUTS0_16", - "PSS_LOGIC_OUTS0_17", - "PSS_LOGIC_OUTS0_18", - "PSS_LOGIC_OUTS0_19", - "PSS_LOGIC_OUTS0_2", - "PSS_LOGIC_OUTS0_3", - "PSS_LOGIC_OUTS0_4", - "PSS_LOGIC_OUTS0_5", - "PSS_LOGIC_OUTS0_6", - "PSS_LOGIC_OUTS0_7", - "PSS_LOGIC_OUTS0_8", - "PSS_LOGIC_OUTS0_9", - "PSS_LOGIC_OUTS10_0", - "PSS_LOGIC_OUTS10_1", - "PSS_LOGIC_OUTS10_10", - "PSS_LOGIC_OUTS10_11", - "PSS_LOGIC_OUTS10_12", - "PSS_LOGIC_OUTS10_13", - "PSS_LOGIC_OUTS10_14", - "PSS_LOGIC_OUTS10_15", - "PSS_LOGIC_OUTS10_16", - "PSS_LOGIC_OUTS10_17", - "PSS_LOGIC_OUTS10_18", - "PSS_LOGIC_OUTS10_19", - "PSS_LOGIC_OUTS10_2", - "PSS_LOGIC_OUTS10_3", - "PSS_LOGIC_OUTS10_4", - "PSS_LOGIC_OUTS10_5", - "PSS_LOGIC_OUTS10_6", - "PSS_LOGIC_OUTS10_7", - "PSS_LOGIC_OUTS10_8", - "PSS_LOGIC_OUTS10_9", - "PSS_LOGIC_OUTS11_0", - "PSS_LOGIC_OUTS11_1", - "PSS_LOGIC_OUTS11_10", - "PSS_LOGIC_OUTS11_11", - "PSS_LOGIC_OUTS11_12", - "PSS_LOGIC_OUTS11_13", - "PSS_LOGIC_OUTS11_14", - "PSS_LOGIC_OUTS11_15", - "PSS_LOGIC_OUTS11_16", - "PSS_LOGIC_OUTS11_17", - "PSS_LOGIC_OUTS11_18", - "PSS_LOGIC_OUTS11_19", - "PSS_LOGIC_OUTS11_2", - "PSS_LOGIC_OUTS11_3", - "PSS_LOGIC_OUTS11_4", - "PSS_LOGIC_OUTS11_5", - "PSS_LOGIC_OUTS11_6", - "PSS_LOGIC_OUTS11_7", - "PSS_LOGIC_OUTS11_8", - "PSS_LOGIC_OUTS11_9", - "PSS_LOGIC_OUTS12_0", - "PSS_LOGIC_OUTS12_1", - "PSS_LOGIC_OUTS12_10", - "PSS_LOGIC_OUTS12_11", - "PSS_LOGIC_OUTS12_12", - "PSS_LOGIC_OUTS12_13", - "PSS_LOGIC_OUTS12_14", - "PSS_LOGIC_OUTS12_15", - "PSS_LOGIC_OUTS12_16", - "PSS_LOGIC_OUTS12_17", - "PSS_LOGIC_OUTS12_18", - "PSS_LOGIC_OUTS12_19", - "PSS_LOGIC_OUTS12_2", - "PSS_LOGIC_OUTS12_3", - "PSS_LOGIC_OUTS12_4", - "PSS_LOGIC_OUTS12_5", - "PSS_LOGIC_OUTS12_6", - "PSS_LOGIC_OUTS12_7", - "PSS_LOGIC_OUTS12_8", - "PSS_LOGIC_OUTS12_9", - "PSS_LOGIC_OUTS13_0", - "PSS_LOGIC_OUTS13_1", - "PSS_LOGIC_OUTS13_10", - "PSS_LOGIC_OUTS13_11", - "PSS_LOGIC_OUTS13_12", - "PSS_LOGIC_OUTS13_13", - "PSS_LOGIC_OUTS13_14", - "PSS_LOGIC_OUTS13_15", - "PSS_LOGIC_OUTS13_16", - "PSS_LOGIC_OUTS13_17", - "PSS_LOGIC_OUTS13_18", - "PSS_LOGIC_OUTS13_19", - "PSS_LOGIC_OUTS13_2", - "PSS_LOGIC_OUTS13_3", - "PSS_LOGIC_OUTS13_4", - "PSS_LOGIC_OUTS13_5", - "PSS_LOGIC_OUTS13_6", - "PSS_LOGIC_OUTS13_7", - "PSS_LOGIC_OUTS13_8", - "PSS_LOGIC_OUTS13_9", - "PSS_LOGIC_OUTS14_0", - "PSS_LOGIC_OUTS14_1", - "PSS_LOGIC_OUTS14_10", - "PSS_LOGIC_OUTS14_11", - "PSS_LOGIC_OUTS14_12", - "PSS_LOGIC_OUTS14_13", - "PSS_LOGIC_OUTS14_14", - "PSS_LOGIC_OUTS14_15", - "PSS_LOGIC_OUTS14_16", - "PSS_LOGIC_OUTS14_17", - "PSS_LOGIC_OUTS14_18", - "PSS_LOGIC_OUTS14_19", - "PSS_LOGIC_OUTS14_2", - "PSS_LOGIC_OUTS14_3", - "PSS_LOGIC_OUTS14_4", - "PSS_LOGIC_OUTS14_5", - "PSS_LOGIC_OUTS14_6", - "PSS_LOGIC_OUTS14_7", - "PSS_LOGIC_OUTS14_8", - "PSS_LOGIC_OUTS14_9", - "PSS_LOGIC_OUTS15_0", - "PSS_LOGIC_OUTS15_1", - "PSS_LOGIC_OUTS15_10", - "PSS_LOGIC_OUTS15_11", - "PSS_LOGIC_OUTS15_12", - "PSS_LOGIC_OUTS15_13", - "PSS_LOGIC_OUTS15_14", - "PSS_LOGIC_OUTS15_15", - "PSS_LOGIC_OUTS15_16", - "PSS_LOGIC_OUTS15_17", - "PSS_LOGIC_OUTS15_18", - "PSS_LOGIC_OUTS15_19", - "PSS_LOGIC_OUTS15_2", - "PSS_LOGIC_OUTS15_3", - "PSS_LOGIC_OUTS15_4", - "PSS_LOGIC_OUTS15_5", - "PSS_LOGIC_OUTS15_6", - "PSS_LOGIC_OUTS15_7", - "PSS_LOGIC_OUTS15_8", - "PSS_LOGIC_OUTS15_9", - "PSS_LOGIC_OUTS16_0", - "PSS_LOGIC_OUTS16_1", - "PSS_LOGIC_OUTS16_10", - "PSS_LOGIC_OUTS16_11", - "PSS_LOGIC_OUTS16_12", - "PSS_LOGIC_OUTS16_13", - "PSS_LOGIC_OUTS16_14", - "PSS_LOGIC_OUTS16_15", - "PSS_LOGIC_OUTS16_16", - "PSS_LOGIC_OUTS16_17", - "PSS_LOGIC_OUTS16_18", - "PSS_LOGIC_OUTS16_19", - "PSS_LOGIC_OUTS16_2", - "PSS_LOGIC_OUTS16_3", - "PSS_LOGIC_OUTS16_4", - "PSS_LOGIC_OUTS16_5", - "PSS_LOGIC_OUTS16_6", - "PSS_LOGIC_OUTS16_7", - "PSS_LOGIC_OUTS16_8", - "PSS_LOGIC_OUTS16_9", - "PSS_LOGIC_OUTS17_0", - "PSS_LOGIC_OUTS17_1", - "PSS_LOGIC_OUTS17_10", - "PSS_LOGIC_OUTS17_11", - "PSS_LOGIC_OUTS17_12", - "PSS_LOGIC_OUTS17_13", - "PSS_LOGIC_OUTS17_14", - "PSS_LOGIC_OUTS17_15", - "PSS_LOGIC_OUTS17_16", - "PSS_LOGIC_OUTS17_17", - "PSS_LOGIC_OUTS17_18", - "PSS_LOGIC_OUTS17_19", - "PSS_LOGIC_OUTS17_2", - "PSS_LOGIC_OUTS17_3", - "PSS_LOGIC_OUTS17_4", - "PSS_LOGIC_OUTS17_5", - "PSS_LOGIC_OUTS17_6", - "PSS_LOGIC_OUTS17_7", - "PSS_LOGIC_OUTS17_8", - "PSS_LOGIC_OUTS17_9", - "PSS_LOGIC_OUTS18_0", - "PSS_LOGIC_OUTS18_1", - "PSS_LOGIC_OUTS18_10", - "PSS_LOGIC_OUTS18_11", - "PSS_LOGIC_OUTS18_12", - "PSS_LOGIC_OUTS18_13", - "PSS_LOGIC_OUTS18_14", - "PSS_LOGIC_OUTS18_15", - "PSS_LOGIC_OUTS18_16", - "PSS_LOGIC_OUTS18_17", - "PSS_LOGIC_OUTS18_18", - "PSS_LOGIC_OUTS18_19", - "PSS_LOGIC_OUTS18_2", - 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"PS7_FTMTP2FDEBUG0": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG1": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG10": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG11": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG12": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG13": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG14": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG15": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG16": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG17": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG18": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG19": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG2": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG20": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG21": { + "cap": "10.823", + "res": "0.000" + }, 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+ "PS7_FTMTP2FDEBUG8": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FDEBUG9": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FTRIG0": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FTRIG1": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FTRIG2": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FTRIG3": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FTRIGACK0": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FTRIGACK1": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FTRIGACK2": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_FTMTP2FTRIGACK3": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P0": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P1": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P10": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P11": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P12": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P13": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P14": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P15": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P16": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P17": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P18": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P19": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P2": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P3": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P4": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P5": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P6": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P7": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P8": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQF2P9": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F0": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F1": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F10": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F11": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F12": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F13": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F14": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F15": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F16": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F17": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F18": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F19": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F2": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F20": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F21": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F22": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F23": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F24": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F25": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F26": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F27": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F28": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F3": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F4": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F5": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F6": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F7": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F8": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_IRQP2F9": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_MAXIGP0ACLK": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_MAXIGP0ARADDR0": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_MAXIGP0ARADDR1": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_MAXIGP0ARADDR10": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_MAXIGP0ARADDR11": { + "cap": "10.823", + "res": "0.000" + }, + "PS7_MAXIGP0ARADDR12": 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"res": "0.000" + }, + "PSS_LOGIC_OUTS8_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_9": { + "cap": "10.823", + "res": "0.000" + } + } } diff --git a/zynq7/tile_type_PSS3.json b/zynq7/tile_type_PSS3.json index c4d3b1c..a5ca45f 100644 --- a/zynq7/tile_type_PSS3.json +++ b/zynq7/tile_type_PSS3.json @@ -2,27061 +2,78545 @@ "pips": { "PSS3.PSS0_CLK_B0_0->PSS1_CLK_B0_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_0" }, "PSS3.PSS0_CLK_B0_1->PSS1_CLK_B0_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_1" }, "PSS3.PSS0_CLK_B0_10->PSS1_CLK_B0_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_10" }, "PSS3.PSS0_CLK_B0_11->PSS1_CLK_B0_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_11" }, "PSS3.PSS0_CLK_B0_12->PSS1_CLK_B0_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_12" }, "PSS3.PSS0_CLK_B0_13->PSS1_CLK_B0_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_13" }, "PSS3.PSS0_CLK_B0_14->PSS1_CLK_B0_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_14" }, "PSS3.PSS0_CLK_B0_15->PSS1_CLK_B0_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_15" }, "PSS3.PSS0_CLK_B0_16->PSS1_CLK_B0_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_16" }, "PSS3.PSS0_CLK_B0_17->PSS1_CLK_B0_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_17" }, "PSS3.PSS0_CLK_B0_18->PSS1_CLK_B0_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_18" }, "PSS3.PSS0_CLK_B0_19->PSS1_CLK_B0_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_19" }, "PSS3.PSS0_CLK_B0_2->PSS1_CLK_B0_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_2" }, "PSS3.PSS0_CLK_B0_3->PSS1_CLK_B0_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_3" }, "PSS3.PSS0_CLK_B0_4->PSS1_CLK_B0_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_4" }, "PSS3.PSS0_CLK_B0_5->PSS1_CLK_B0_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_5" }, "PSS3.PSS0_CLK_B0_6->PSS1_CLK_B0_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_6" }, "PSS3.PSS0_CLK_B0_7->PSS1_CLK_B0_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_7" }, "PSS3.PSS0_CLK_B0_8->PSS1_CLK_B0_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_8" }, "PSS3.PSS0_CLK_B0_9->PSS1_CLK_B0_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B0_9" }, "PSS3.PSS0_CLK_B1_0->PSS1_CLK_B1_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_0" }, "PSS3.PSS0_CLK_B1_1->PSS1_CLK_B1_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_1" }, "PSS3.PSS0_CLK_B1_10->PSS1_CLK_B1_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_10" }, "PSS3.PSS0_CLK_B1_11->PSS1_CLK_B1_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_11" }, "PSS3.PSS0_CLK_B1_12->PSS1_CLK_B1_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_12" }, "PSS3.PSS0_CLK_B1_13->PSS1_CLK_B1_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_13" }, "PSS3.PSS0_CLK_B1_14->PSS1_CLK_B1_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_14" }, "PSS3.PSS0_CLK_B1_15->PSS1_CLK_B1_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_15" }, "PSS3.PSS0_CLK_B1_16->PSS1_CLK_B1_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_16" }, "PSS3.PSS0_CLK_B1_17->PSS1_CLK_B1_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_17" }, "PSS3.PSS0_CLK_B1_18->PSS1_CLK_B1_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_18" }, "PSS3.PSS0_CLK_B1_19->PSS1_CLK_B1_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_19" }, "PSS3.PSS0_CLK_B1_2->PSS1_CLK_B1_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_2" }, "PSS3.PSS0_CLK_B1_3->PSS1_CLK_B1_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_3" }, "PSS3.PSS0_CLK_B1_4->PSS1_CLK_B1_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_4" }, "PSS3.PSS0_CLK_B1_5->PSS1_CLK_B1_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_5" }, "PSS3.PSS0_CLK_B1_6->PSS1_CLK_B1_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_6" }, "PSS3.PSS0_CLK_B1_7->PSS1_CLK_B1_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_7" }, "PSS3.PSS0_CLK_B1_8->PSS1_CLK_B1_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_8" }, "PSS3.PSS0_CLK_B1_9->PSS1_CLK_B1_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_CLK_B1_9" }, "PSS3.PSS0_IMUX_B0_0->PSS1_IMUX_B0_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_0" }, "PSS3.PSS0_IMUX_B0_1->PSS1_IMUX_B0_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_1" }, "PSS3.PSS0_IMUX_B0_10->PSS1_IMUX_B0_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_10" }, "PSS3.PSS0_IMUX_B0_11->PSS1_IMUX_B0_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_11" }, "PSS3.PSS0_IMUX_B0_12->PSS1_IMUX_B0_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_12" }, "PSS3.PSS0_IMUX_B0_13->PSS1_IMUX_B0_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_13" }, "PSS3.PSS0_IMUX_B0_14->PSS1_IMUX_B0_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_14" }, "PSS3.PSS0_IMUX_B0_15->PSS1_IMUX_B0_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_15" }, "PSS3.PSS0_IMUX_B0_16->PSS1_IMUX_B0_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_16" }, "PSS3.PSS0_IMUX_B0_17->PSS1_IMUX_B0_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_17" }, "PSS3.PSS0_IMUX_B0_18->PSS1_IMUX_B0_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_18" }, "PSS3.PSS0_IMUX_B0_19->PSS1_IMUX_B0_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_19" }, "PSS3.PSS0_IMUX_B0_2->PSS1_IMUX_B0_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_2" }, "PSS3.PSS0_IMUX_B0_3->PSS1_IMUX_B0_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_3" }, "PSS3.PSS0_IMUX_B0_4->PSS1_IMUX_B0_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_4" }, "PSS3.PSS0_IMUX_B0_5->PSS1_IMUX_B0_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_5" }, "PSS3.PSS0_IMUX_B0_6->PSS1_IMUX_B0_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_6" }, "PSS3.PSS0_IMUX_B0_7->PSS1_IMUX_B0_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_7" }, "PSS3.PSS0_IMUX_B0_8->PSS1_IMUX_B0_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_8" }, "PSS3.PSS0_IMUX_B0_9->PSS1_IMUX_B0_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B0_9" }, "PSS3.PSS0_IMUX_B10_0->PSS1_IMUX_B10_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_0" }, "PSS3.PSS0_IMUX_B10_1->PSS1_IMUX_B10_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_1" }, "PSS3.PSS0_IMUX_B10_10->PSS1_IMUX_B10_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_10" }, "PSS3.PSS0_IMUX_B10_11->PSS1_IMUX_B10_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_11" }, "PSS3.PSS0_IMUX_B10_12->PSS1_IMUX_B10_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_12" }, "PSS3.PSS0_IMUX_B10_13->PSS1_IMUX_B10_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_13" }, "PSS3.PSS0_IMUX_B10_14->PSS1_IMUX_B10_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_14" }, "PSS3.PSS0_IMUX_B10_15->PSS1_IMUX_B10_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_15" }, "PSS3.PSS0_IMUX_B10_16->PSS1_IMUX_B10_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_16" }, "PSS3.PSS0_IMUX_B10_17->PSS1_IMUX_B10_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_17" }, "PSS3.PSS0_IMUX_B10_18->PSS1_IMUX_B10_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_18" }, "PSS3.PSS0_IMUX_B10_19->PSS1_IMUX_B10_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_19" }, "PSS3.PSS0_IMUX_B10_2->PSS1_IMUX_B10_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_2" }, "PSS3.PSS0_IMUX_B10_3->PSS1_IMUX_B10_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_3" }, "PSS3.PSS0_IMUX_B10_4->PSS1_IMUX_B10_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_4" }, "PSS3.PSS0_IMUX_B10_5->PSS1_IMUX_B10_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_5" }, "PSS3.PSS0_IMUX_B10_6->PSS1_IMUX_B10_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_6" }, "PSS3.PSS0_IMUX_B10_7->PSS1_IMUX_B10_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_7" }, "PSS3.PSS0_IMUX_B10_8->PSS1_IMUX_B10_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_8" }, "PSS3.PSS0_IMUX_B10_9->PSS1_IMUX_B10_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B10_9" }, "PSS3.PSS0_IMUX_B11_0->PSS1_IMUX_B11_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_0" }, "PSS3.PSS0_IMUX_B11_1->PSS1_IMUX_B11_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_1" }, "PSS3.PSS0_IMUX_B11_10->PSS1_IMUX_B11_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_10" }, "PSS3.PSS0_IMUX_B11_11->PSS1_IMUX_B11_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_11" }, "PSS3.PSS0_IMUX_B11_12->PSS1_IMUX_B11_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_12" }, "PSS3.PSS0_IMUX_B11_13->PSS1_IMUX_B11_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_13" }, "PSS3.PSS0_IMUX_B11_14->PSS1_IMUX_B11_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_14" }, "PSS3.PSS0_IMUX_B11_15->PSS1_IMUX_B11_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_15" }, "PSS3.PSS0_IMUX_B11_16->PSS1_IMUX_B11_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_16" }, "PSS3.PSS0_IMUX_B11_17->PSS1_IMUX_B11_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_17" }, "PSS3.PSS0_IMUX_B11_18->PSS1_IMUX_B11_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_18" }, "PSS3.PSS0_IMUX_B11_19->PSS1_IMUX_B11_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_19" }, "PSS3.PSS0_IMUX_B11_2->PSS1_IMUX_B11_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_2" }, "PSS3.PSS0_IMUX_B11_3->PSS1_IMUX_B11_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_3" }, "PSS3.PSS0_IMUX_B11_4->PSS1_IMUX_B11_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_4" }, "PSS3.PSS0_IMUX_B11_5->PSS1_IMUX_B11_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_5" }, "PSS3.PSS0_IMUX_B11_6->PSS1_IMUX_B11_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_6" }, "PSS3.PSS0_IMUX_B11_7->PSS1_IMUX_B11_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_7" }, "PSS3.PSS0_IMUX_B11_8->PSS1_IMUX_B11_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_8" }, "PSS3.PSS0_IMUX_B11_9->PSS1_IMUX_B11_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B11_9" }, "PSS3.PSS0_IMUX_B12_0->PSS1_IMUX_B12_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_0" }, "PSS3.PSS0_IMUX_B12_1->PSS1_IMUX_B12_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_1" }, "PSS3.PSS0_IMUX_B12_10->PSS1_IMUX_B12_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_10" }, "PSS3.PSS0_IMUX_B12_11->PSS1_IMUX_B12_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_11" }, "PSS3.PSS0_IMUX_B12_12->PSS1_IMUX_B12_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_12" }, "PSS3.PSS0_IMUX_B12_13->PSS1_IMUX_B12_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_13" }, "PSS3.PSS0_IMUX_B12_14->PSS1_IMUX_B12_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_14" }, "PSS3.PSS0_IMUX_B12_15->PSS1_IMUX_B12_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_15" }, "PSS3.PSS0_IMUX_B12_16->PSS1_IMUX_B12_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_16" }, "PSS3.PSS0_IMUX_B12_17->PSS1_IMUX_B12_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_17" }, "PSS3.PSS0_IMUX_B12_18->PSS1_IMUX_B12_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_18" }, "PSS3.PSS0_IMUX_B12_19->PSS1_IMUX_B12_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_19" }, "PSS3.PSS0_IMUX_B12_2->PSS1_IMUX_B12_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_2" }, "PSS3.PSS0_IMUX_B12_3->PSS1_IMUX_B12_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_3" }, "PSS3.PSS0_IMUX_B12_4->PSS1_IMUX_B12_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_4" }, "PSS3.PSS0_IMUX_B12_5->PSS1_IMUX_B12_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_5" }, "PSS3.PSS0_IMUX_B12_6->PSS1_IMUX_B12_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_6" }, "PSS3.PSS0_IMUX_B12_7->PSS1_IMUX_B12_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_7" }, "PSS3.PSS0_IMUX_B12_8->PSS1_IMUX_B12_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_8" }, "PSS3.PSS0_IMUX_B12_9->PSS1_IMUX_B12_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B12_9" }, "PSS3.PSS0_IMUX_B13_0->PSS1_IMUX_B13_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_0" }, "PSS3.PSS0_IMUX_B13_1->PSS1_IMUX_B13_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_1" }, "PSS3.PSS0_IMUX_B13_10->PSS1_IMUX_B13_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_10" }, "PSS3.PSS0_IMUX_B13_11->PSS1_IMUX_B13_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_11" }, "PSS3.PSS0_IMUX_B13_12->PSS1_IMUX_B13_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_12" }, "PSS3.PSS0_IMUX_B13_13->PSS1_IMUX_B13_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_13" }, "PSS3.PSS0_IMUX_B13_14->PSS1_IMUX_B13_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_14" }, "PSS3.PSS0_IMUX_B13_15->PSS1_IMUX_B13_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_15" }, "PSS3.PSS0_IMUX_B13_16->PSS1_IMUX_B13_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_16" }, "PSS3.PSS0_IMUX_B13_17->PSS1_IMUX_B13_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_17" }, "PSS3.PSS0_IMUX_B13_18->PSS1_IMUX_B13_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_18" }, "PSS3.PSS0_IMUX_B13_19->PSS1_IMUX_B13_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_19" }, "PSS3.PSS0_IMUX_B13_2->PSS1_IMUX_B13_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_2" }, "PSS3.PSS0_IMUX_B13_3->PSS1_IMUX_B13_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_3" }, "PSS3.PSS0_IMUX_B13_4->PSS1_IMUX_B13_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_4" }, "PSS3.PSS0_IMUX_B13_5->PSS1_IMUX_B13_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_5" }, "PSS3.PSS0_IMUX_B13_6->PSS1_IMUX_B13_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_6" }, "PSS3.PSS0_IMUX_B13_7->PSS1_IMUX_B13_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_7" }, "PSS3.PSS0_IMUX_B13_8->PSS1_IMUX_B13_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_8" }, "PSS3.PSS0_IMUX_B13_9->PSS1_IMUX_B13_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B13_9" }, "PSS3.PSS0_IMUX_B14_0->PSS1_IMUX_B14_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_0" }, "PSS3.PSS0_IMUX_B14_1->PSS1_IMUX_B14_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_1" }, "PSS3.PSS0_IMUX_B14_10->PSS1_IMUX_B14_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_10" }, "PSS3.PSS0_IMUX_B14_11->PSS1_IMUX_B14_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_11" }, "PSS3.PSS0_IMUX_B14_12->PSS1_IMUX_B14_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_12" }, "PSS3.PSS0_IMUX_B14_13->PSS1_IMUX_B14_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_13" }, "PSS3.PSS0_IMUX_B14_14->PSS1_IMUX_B14_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_14" }, "PSS3.PSS0_IMUX_B14_15->PSS1_IMUX_B14_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_15" }, "PSS3.PSS0_IMUX_B14_16->PSS1_IMUX_B14_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_16" }, "PSS3.PSS0_IMUX_B14_17->PSS1_IMUX_B14_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_17" }, "PSS3.PSS0_IMUX_B14_18->PSS1_IMUX_B14_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_18" }, "PSS3.PSS0_IMUX_B14_19->PSS1_IMUX_B14_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_19" }, "PSS3.PSS0_IMUX_B14_2->PSS1_IMUX_B14_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_2" }, "PSS3.PSS0_IMUX_B14_3->PSS1_IMUX_B14_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_3" }, "PSS3.PSS0_IMUX_B14_4->PSS1_IMUX_B14_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_4" }, "PSS3.PSS0_IMUX_B14_5->PSS1_IMUX_B14_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_5" }, "PSS3.PSS0_IMUX_B14_6->PSS1_IMUX_B14_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_6" }, "PSS3.PSS0_IMUX_B14_7->PSS1_IMUX_B14_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_7" }, "PSS3.PSS0_IMUX_B14_8->PSS1_IMUX_B14_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_8" }, "PSS3.PSS0_IMUX_B14_9->PSS1_IMUX_B14_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B14_9" }, "PSS3.PSS0_IMUX_B15_0->PSS1_IMUX_B15_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_0" }, "PSS3.PSS0_IMUX_B15_1->PSS1_IMUX_B15_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_1" }, "PSS3.PSS0_IMUX_B15_10->PSS1_IMUX_B15_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_10" }, "PSS3.PSS0_IMUX_B15_11->PSS1_IMUX_B15_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_11" }, "PSS3.PSS0_IMUX_B15_12->PSS1_IMUX_B15_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_12" }, "PSS3.PSS0_IMUX_B15_13->PSS1_IMUX_B15_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_13" }, "PSS3.PSS0_IMUX_B15_14->PSS1_IMUX_B15_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_14" }, "PSS3.PSS0_IMUX_B15_15->PSS1_IMUX_B15_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_15" }, "PSS3.PSS0_IMUX_B15_16->PSS1_IMUX_B15_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_16" }, "PSS3.PSS0_IMUX_B15_17->PSS1_IMUX_B15_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_17" }, "PSS3.PSS0_IMUX_B15_18->PSS1_IMUX_B15_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_18" }, "PSS3.PSS0_IMUX_B15_19->PSS1_IMUX_B15_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_19" }, "PSS3.PSS0_IMUX_B15_2->PSS1_IMUX_B15_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_2" }, "PSS3.PSS0_IMUX_B15_3->PSS1_IMUX_B15_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_3" }, "PSS3.PSS0_IMUX_B15_4->PSS1_IMUX_B15_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_4" }, "PSS3.PSS0_IMUX_B15_5->PSS1_IMUX_B15_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_5" }, "PSS3.PSS0_IMUX_B15_6->PSS1_IMUX_B15_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_6" }, "PSS3.PSS0_IMUX_B15_7->PSS1_IMUX_B15_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_7" }, "PSS3.PSS0_IMUX_B15_8->PSS1_IMUX_B15_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_8" }, "PSS3.PSS0_IMUX_B15_9->PSS1_IMUX_B15_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B15_9" }, "PSS3.PSS0_IMUX_B16_0->PSS1_IMUX_B16_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_0" }, "PSS3.PSS0_IMUX_B16_1->PSS1_IMUX_B16_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_1" }, "PSS3.PSS0_IMUX_B16_10->PSS1_IMUX_B16_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_10" }, "PSS3.PSS0_IMUX_B16_11->PSS1_IMUX_B16_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_11" }, "PSS3.PSS0_IMUX_B16_12->PSS1_IMUX_B16_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_12" }, "PSS3.PSS0_IMUX_B16_13->PSS1_IMUX_B16_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_13" }, "PSS3.PSS0_IMUX_B16_14->PSS1_IMUX_B16_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_14" }, "PSS3.PSS0_IMUX_B16_15->PSS1_IMUX_B16_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_15" }, "PSS3.PSS0_IMUX_B16_16->PSS1_IMUX_B16_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_16" }, "PSS3.PSS0_IMUX_B16_17->PSS1_IMUX_B16_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_17" }, "PSS3.PSS0_IMUX_B16_18->PSS1_IMUX_B16_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_18" }, "PSS3.PSS0_IMUX_B16_19->PSS1_IMUX_B16_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_19" }, "PSS3.PSS0_IMUX_B16_2->PSS1_IMUX_B16_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_2" }, "PSS3.PSS0_IMUX_B16_3->PSS1_IMUX_B16_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_3" }, "PSS3.PSS0_IMUX_B16_4->PSS1_IMUX_B16_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_4" }, "PSS3.PSS0_IMUX_B16_5->PSS1_IMUX_B16_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_5" }, "PSS3.PSS0_IMUX_B16_6->PSS1_IMUX_B16_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_6" }, "PSS3.PSS0_IMUX_B16_7->PSS1_IMUX_B16_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_7" }, "PSS3.PSS0_IMUX_B16_8->PSS1_IMUX_B16_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_8" }, "PSS3.PSS0_IMUX_B16_9->PSS1_IMUX_B16_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B16_9" }, "PSS3.PSS0_IMUX_B17_0->PSS1_IMUX_B17_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_0" }, "PSS3.PSS0_IMUX_B17_1->PSS1_IMUX_B17_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_1" }, "PSS3.PSS0_IMUX_B17_10->PSS1_IMUX_B17_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_10" }, "PSS3.PSS0_IMUX_B17_11->PSS1_IMUX_B17_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_11" }, "PSS3.PSS0_IMUX_B17_12->PSS1_IMUX_B17_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_12" }, "PSS3.PSS0_IMUX_B17_13->PSS1_IMUX_B17_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_13" }, "PSS3.PSS0_IMUX_B17_14->PSS1_IMUX_B17_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_14" }, "PSS3.PSS0_IMUX_B17_15->PSS1_IMUX_B17_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_15" }, "PSS3.PSS0_IMUX_B17_16->PSS1_IMUX_B17_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_16" }, "PSS3.PSS0_IMUX_B17_17->PSS1_IMUX_B17_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_17" }, "PSS3.PSS0_IMUX_B17_18->PSS1_IMUX_B17_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_18" }, "PSS3.PSS0_IMUX_B17_19->PSS1_IMUX_B17_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_19" }, "PSS3.PSS0_IMUX_B17_2->PSS1_IMUX_B17_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_2" }, "PSS3.PSS0_IMUX_B17_3->PSS1_IMUX_B17_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_3" }, "PSS3.PSS0_IMUX_B17_4->PSS1_IMUX_B17_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_4" }, "PSS3.PSS0_IMUX_B17_5->PSS1_IMUX_B17_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_5" }, "PSS3.PSS0_IMUX_B17_6->PSS1_IMUX_B17_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_6" }, "PSS3.PSS0_IMUX_B17_7->PSS1_IMUX_B17_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_7" }, "PSS3.PSS0_IMUX_B17_8->PSS1_IMUX_B17_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_8" }, "PSS3.PSS0_IMUX_B17_9->PSS1_IMUX_B17_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B17_9" }, "PSS3.PSS0_IMUX_B18_0->PSS1_IMUX_B18_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_0" }, "PSS3.PSS0_IMUX_B18_1->PSS1_IMUX_B18_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_1" }, "PSS3.PSS0_IMUX_B18_10->PSS1_IMUX_B18_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_10" }, "PSS3.PSS0_IMUX_B18_11->PSS1_IMUX_B18_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_11" }, "PSS3.PSS0_IMUX_B18_12->PSS1_IMUX_B18_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_12" }, "PSS3.PSS0_IMUX_B18_13->PSS1_IMUX_B18_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_13" }, "PSS3.PSS0_IMUX_B18_14->PSS1_IMUX_B18_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_14" }, "PSS3.PSS0_IMUX_B18_15->PSS1_IMUX_B18_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_15" }, "PSS3.PSS0_IMUX_B18_16->PSS1_IMUX_B18_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_16" }, "PSS3.PSS0_IMUX_B18_17->PSS1_IMUX_B18_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_17" }, "PSS3.PSS0_IMUX_B18_18->PSS1_IMUX_B18_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_18" }, "PSS3.PSS0_IMUX_B18_19->PSS1_IMUX_B18_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_19" }, "PSS3.PSS0_IMUX_B18_2->PSS1_IMUX_B18_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_2" }, "PSS3.PSS0_IMUX_B18_3->PSS1_IMUX_B18_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_3" }, "PSS3.PSS0_IMUX_B18_4->PSS1_IMUX_B18_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_4" }, "PSS3.PSS0_IMUX_B18_5->PSS1_IMUX_B18_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_5" }, "PSS3.PSS0_IMUX_B18_6->PSS1_IMUX_B18_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_6" }, "PSS3.PSS0_IMUX_B18_7->PSS1_IMUX_B18_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_7" }, "PSS3.PSS0_IMUX_B18_8->PSS1_IMUX_B18_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_8" }, "PSS3.PSS0_IMUX_B18_9->PSS1_IMUX_B18_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B18_9" }, "PSS3.PSS0_IMUX_B19_0->PSS1_IMUX_B19_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_0" }, "PSS3.PSS0_IMUX_B19_1->PSS1_IMUX_B19_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_1" }, "PSS3.PSS0_IMUX_B19_10->PSS1_IMUX_B19_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_10" }, "PSS3.PSS0_IMUX_B19_11->PSS1_IMUX_B19_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_11" }, "PSS3.PSS0_IMUX_B19_12->PSS1_IMUX_B19_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_12" }, "PSS3.PSS0_IMUX_B19_13->PSS1_IMUX_B19_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_13" }, "PSS3.PSS0_IMUX_B19_14->PSS1_IMUX_B19_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_14" }, "PSS3.PSS0_IMUX_B19_15->PSS1_IMUX_B19_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_15" }, "PSS3.PSS0_IMUX_B19_16->PSS1_IMUX_B19_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_16" }, "PSS3.PSS0_IMUX_B19_17->PSS1_IMUX_B19_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_17" }, "PSS3.PSS0_IMUX_B19_18->PSS1_IMUX_B19_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_18" }, "PSS3.PSS0_IMUX_B19_19->PSS1_IMUX_B19_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_19" }, "PSS3.PSS0_IMUX_B19_2->PSS1_IMUX_B19_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_2" }, "PSS3.PSS0_IMUX_B19_3->PSS1_IMUX_B19_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_3" }, "PSS3.PSS0_IMUX_B19_4->PSS1_IMUX_B19_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_4" }, "PSS3.PSS0_IMUX_B19_5->PSS1_IMUX_B19_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_5" }, "PSS3.PSS0_IMUX_B19_6->PSS1_IMUX_B19_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_6" }, "PSS3.PSS0_IMUX_B19_7->PSS1_IMUX_B19_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_7" }, "PSS3.PSS0_IMUX_B19_8->PSS1_IMUX_B19_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_8" }, "PSS3.PSS0_IMUX_B19_9->PSS1_IMUX_B19_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B19_9" }, "PSS3.PSS0_IMUX_B1_0->PSS1_IMUX_B1_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_0" }, "PSS3.PSS0_IMUX_B1_1->PSS1_IMUX_B1_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_1" }, "PSS3.PSS0_IMUX_B1_10->PSS1_IMUX_B1_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_10" }, "PSS3.PSS0_IMUX_B1_11->PSS1_IMUX_B1_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_11" }, "PSS3.PSS0_IMUX_B1_12->PSS1_IMUX_B1_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_12" }, "PSS3.PSS0_IMUX_B1_13->PSS1_IMUX_B1_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_13" }, "PSS3.PSS0_IMUX_B1_14->PSS1_IMUX_B1_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_14" }, "PSS3.PSS0_IMUX_B1_15->PSS1_IMUX_B1_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_15" }, "PSS3.PSS0_IMUX_B1_16->PSS1_IMUX_B1_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_16" }, "PSS3.PSS0_IMUX_B1_17->PSS1_IMUX_B1_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_17" }, "PSS3.PSS0_IMUX_B1_18->PSS1_IMUX_B1_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_18" }, "PSS3.PSS0_IMUX_B1_19->PSS1_IMUX_B1_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_19" }, "PSS3.PSS0_IMUX_B1_2->PSS1_IMUX_B1_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_2" }, "PSS3.PSS0_IMUX_B1_3->PSS1_IMUX_B1_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_3" }, "PSS3.PSS0_IMUX_B1_4->PSS1_IMUX_B1_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_4" }, "PSS3.PSS0_IMUX_B1_5->PSS1_IMUX_B1_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_5" }, "PSS3.PSS0_IMUX_B1_6->PSS1_IMUX_B1_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_6" }, "PSS3.PSS0_IMUX_B1_7->PSS1_IMUX_B1_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_7" }, "PSS3.PSS0_IMUX_B1_8->PSS1_IMUX_B1_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_8" }, "PSS3.PSS0_IMUX_B1_9->PSS1_IMUX_B1_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B1_9" }, "PSS3.PSS0_IMUX_B20_0->PSS1_IMUX_B20_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_0" }, "PSS3.PSS0_IMUX_B20_1->PSS1_IMUX_B20_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_1" }, "PSS3.PSS0_IMUX_B20_10->PSS1_IMUX_B20_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_10" }, "PSS3.PSS0_IMUX_B20_11->PSS1_IMUX_B20_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_11" }, "PSS3.PSS0_IMUX_B20_12->PSS1_IMUX_B20_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_12" }, "PSS3.PSS0_IMUX_B20_13->PSS1_IMUX_B20_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_13" }, "PSS3.PSS0_IMUX_B20_14->PSS1_IMUX_B20_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_14" }, "PSS3.PSS0_IMUX_B20_15->PSS1_IMUX_B20_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_15" }, "PSS3.PSS0_IMUX_B20_16->PSS1_IMUX_B20_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_16" }, "PSS3.PSS0_IMUX_B20_17->PSS1_IMUX_B20_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_17" }, "PSS3.PSS0_IMUX_B20_18->PSS1_IMUX_B20_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_18" }, "PSS3.PSS0_IMUX_B20_19->PSS1_IMUX_B20_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_19" }, "PSS3.PSS0_IMUX_B20_2->PSS1_IMUX_B20_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_2" }, "PSS3.PSS0_IMUX_B20_3->PSS1_IMUX_B20_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_3" }, "PSS3.PSS0_IMUX_B20_4->PSS1_IMUX_B20_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_4" }, "PSS3.PSS0_IMUX_B20_5->PSS1_IMUX_B20_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_5" }, "PSS3.PSS0_IMUX_B20_6->PSS1_IMUX_B20_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_6" }, "PSS3.PSS0_IMUX_B20_7->PSS1_IMUX_B20_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_7" }, "PSS3.PSS0_IMUX_B20_8->PSS1_IMUX_B20_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_8" }, "PSS3.PSS0_IMUX_B20_9->PSS1_IMUX_B20_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B20_9" }, "PSS3.PSS0_IMUX_B21_0->PSS1_IMUX_B21_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_0" }, "PSS3.PSS0_IMUX_B21_1->PSS1_IMUX_B21_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_1" }, "PSS3.PSS0_IMUX_B21_10->PSS1_IMUX_B21_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_10" }, "PSS3.PSS0_IMUX_B21_11->PSS1_IMUX_B21_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_11" }, "PSS3.PSS0_IMUX_B21_12->PSS1_IMUX_B21_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_12" }, "PSS3.PSS0_IMUX_B21_13->PSS1_IMUX_B21_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_13" }, "PSS3.PSS0_IMUX_B21_14->PSS1_IMUX_B21_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_14" }, "PSS3.PSS0_IMUX_B21_15->PSS1_IMUX_B21_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_15" }, "PSS3.PSS0_IMUX_B21_16->PSS1_IMUX_B21_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_16" }, "PSS3.PSS0_IMUX_B21_17->PSS1_IMUX_B21_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_17" }, "PSS3.PSS0_IMUX_B21_18->PSS1_IMUX_B21_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_18" }, "PSS3.PSS0_IMUX_B21_19->PSS1_IMUX_B21_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_19" }, "PSS3.PSS0_IMUX_B21_2->PSS1_IMUX_B21_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_2" }, "PSS3.PSS0_IMUX_B21_3->PSS1_IMUX_B21_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_3" }, "PSS3.PSS0_IMUX_B21_4->PSS1_IMUX_B21_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_4" }, "PSS3.PSS0_IMUX_B21_5->PSS1_IMUX_B21_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_5" }, "PSS3.PSS0_IMUX_B21_6->PSS1_IMUX_B21_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_6" }, "PSS3.PSS0_IMUX_B21_7->PSS1_IMUX_B21_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_7" }, "PSS3.PSS0_IMUX_B21_8->PSS1_IMUX_B21_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_8" }, "PSS3.PSS0_IMUX_B21_9->PSS1_IMUX_B21_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B21_9" }, "PSS3.PSS0_IMUX_B22_0->PSS1_IMUX_B22_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_0" }, "PSS3.PSS0_IMUX_B22_1->PSS1_IMUX_B22_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_1" }, "PSS3.PSS0_IMUX_B22_10->PSS1_IMUX_B22_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_10" }, "PSS3.PSS0_IMUX_B22_11->PSS1_IMUX_B22_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_11" }, "PSS3.PSS0_IMUX_B22_12->PSS1_IMUX_B22_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_12" }, "PSS3.PSS0_IMUX_B22_13->PSS1_IMUX_B22_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_13" }, "PSS3.PSS0_IMUX_B22_14->PSS1_IMUX_B22_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_14" }, "PSS3.PSS0_IMUX_B22_15->PSS1_IMUX_B22_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_15" }, "PSS3.PSS0_IMUX_B22_16->PSS1_IMUX_B22_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_16" }, "PSS3.PSS0_IMUX_B22_17->PSS1_IMUX_B22_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_17" }, "PSS3.PSS0_IMUX_B22_18->PSS1_IMUX_B22_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_18" }, "PSS3.PSS0_IMUX_B22_19->PSS1_IMUX_B22_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_19" }, "PSS3.PSS0_IMUX_B22_2->PSS1_IMUX_B22_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_2" }, "PSS3.PSS0_IMUX_B22_3->PSS1_IMUX_B22_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_3" }, "PSS3.PSS0_IMUX_B22_4->PSS1_IMUX_B22_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_4" }, "PSS3.PSS0_IMUX_B22_5->PSS1_IMUX_B22_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_5" }, "PSS3.PSS0_IMUX_B22_6->PSS1_IMUX_B22_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_6" }, "PSS3.PSS0_IMUX_B22_7->PSS1_IMUX_B22_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_7" }, "PSS3.PSS0_IMUX_B22_8->PSS1_IMUX_B22_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_8" }, "PSS3.PSS0_IMUX_B22_9->PSS1_IMUX_B22_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B22_9" }, "PSS3.PSS0_IMUX_B23_0->PSS1_IMUX_B23_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_0" }, "PSS3.PSS0_IMUX_B23_1->PSS1_IMUX_B23_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_1" }, "PSS3.PSS0_IMUX_B23_10->PSS1_IMUX_B23_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_10" }, "PSS3.PSS0_IMUX_B23_11->PSS1_IMUX_B23_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_11" }, "PSS3.PSS0_IMUX_B23_12->PSS1_IMUX_B23_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_12" }, "PSS3.PSS0_IMUX_B23_13->PSS1_IMUX_B23_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_13" }, "PSS3.PSS0_IMUX_B23_14->PSS1_IMUX_B23_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_14" }, "PSS3.PSS0_IMUX_B23_15->PSS1_IMUX_B23_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_15" }, "PSS3.PSS0_IMUX_B23_16->PSS1_IMUX_B23_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_16" }, "PSS3.PSS0_IMUX_B23_17->PSS1_IMUX_B23_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_17" }, "PSS3.PSS0_IMUX_B23_18->PSS1_IMUX_B23_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_18" }, "PSS3.PSS0_IMUX_B23_19->PSS1_IMUX_B23_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_19" }, "PSS3.PSS0_IMUX_B23_2->PSS1_IMUX_B23_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_2" }, "PSS3.PSS0_IMUX_B23_3->PSS1_IMUX_B23_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_3" }, "PSS3.PSS0_IMUX_B23_4->PSS1_IMUX_B23_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_4" }, "PSS3.PSS0_IMUX_B23_5->PSS1_IMUX_B23_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_5" }, "PSS3.PSS0_IMUX_B23_6->PSS1_IMUX_B23_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_6" }, "PSS3.PSS0_IMUX_B23_7->PSS1_IMUX_B23_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_7" }, "PSS3.PSS0_IMUX_B23_8->PSS1_IMUX_B23_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_8" }, "PSS3.PSS0_IMUX_B23_9->PSS1_IMUX_B23_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B23_9" }, "PSS3.PSS0_IMUX_B24_0->PSS1_IMUX_B24_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_0" }, "PSS3.PSS0_IMUX_B24_1->PSS1_IMUX_B24_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_1" }, "PSS3.PSS0_IMUX_B24_10->PSS1_IMUX_B24_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_10" }, "PSS3.PSS0_IMUX_B24_11->PSS1_IMUX_B24_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_11" }, "PSS3.PSS0_IMUX_B24_12->PSS1_IMUX_B24_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_12" }, "PSS3.PSS0_IMUX_B24_13->PSS1_IMUX_B24_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_13" }, "PSS3.PSS0_IMUX_B24_14->PSS1_IMUX_B24_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_14" }, "PSS3.PSS0_IMUX_B24_15->PSS1_IMUX_B24_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_15" }, "PSS3.PSS0_IMUX_B24_16->PSS1_IMUX_B24_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_16" }, "PSS3.PSS0_IMUX_B24_17->PSS1_IMUX_B24_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_17" }, "PSS3.PSS0_IMUX_B24_18->PSS1_IMUX_B24_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_18" }, "PSS3.PSS0_IMUX_B24_19->PSS1_IMUX_B24_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_19" }, "PSS3.PSS0_IMUX_B24_2->PSS1_IMUX_B24_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_2" }, "PSS3.PSS0_IMUX_B24_3->PSS1_IMUX_B24_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_3" }, "PSS3.PSS0_IMUX_B24_4->PSS1_IMUX_B24_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_4" }, "PSS3.PSS0_IMUX_B24_5->PSS1_IMUX_B24_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_5" }, "PSS3.PSS0_IMUX_B24_6->PSS1_IMUX_B24_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_6" }, "PSS3.PSS0_IMUX_B24_7->PSS1_IMUX_B24_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_7" }, "PSS3.PSS0_IMUX_B24_8->PSS1_IMUX_B24_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_8" }, "PSS3.PSS0_IMUX_B24_9->PSS1_IMUX_B24_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B24_9" }, "PSS3.PSS0_IMUX_B25_0->PSS1_IMUX_B25_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_0" }, "PSS3.PSS0_IMUX_B25_1->PSS1_IMUX_B25_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_1" }, "PSS3.PSS0_IMUX_B25_10->PSS1_IMUX_B25_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_10" }, "PSS3.PSS0_IMUX_B25_11->PSS1_IMUX_B25_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_11" }, "PSS3.PSS0_IMUX_B25_12->PSS1_IMUX_B25_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_12" }, "PSS3.PSS0_IMUX_B25_13->PSS1_IMUX_B25_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_13" }, "PSS3.PSS0_IMUX_B25_14->PSS1_IMUX_B25_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_14" }, "PSS3.PSS0_IMUX_B25_15->PSS1_IMUX_B25_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_15" }, "PSS3.PSS0_IMUX_B25_16->PSS1_IMUX_B25_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_16" }, "PSS3.PSS0_IMUX_B25_17->PSS1_IMUX_B25_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_17" }, "PSS3.PSS0_IMUX_B25_18->PSS1_IMUX_B25_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_18" }, "PSS3.PSS0_IMUX_B25_19->PSS1_IMUX_B25_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_19" }, "PSS3.PSS0_IMUX_B25_2->PSS1_IMUX_B25_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_2" }, "PSS3.PSS0_IMUX_B25_3->PSS1_IMUX_B25_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_3" }, "PSS3.PSS0_IMUX_B25_4->PSS1_IMUX_B25_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_4" }, "PSS3.PSS0_IMUX_B25_5->PSS1_IMUX_B25_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_5" }, "PSS3.PSS0_IMUX_B25_6->PSS1_IMUX_B25_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_6" }, "PSS3.PSS0_IMUX_B25_7->PSS1_IMUX_B25_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_7" }, "PSS3.PSS0_IMUX_B25_8->PSS1_IMUX_B25_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_8" }, "PSS3.PSS0_IMUX_B25_9->PSS1_IMUX_B25_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B25_9" }, "PSS3.PSS0_IMUX_B26_0->PSS1_IMUX_B26_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_0" }, "PSS3.PSS0_IMUX_B26_1->PSS1_IMUX_B26_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_1" }, "PSS3.PSS0_IMUX_B26_10->PSS1_IMUX_B26_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_10" }, "PSS3.PSS0_IMUX_B26_11->PSS1_IMUX_B26_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_11" }, "PSS3.PSS0_IMUX_B26_12->PSS1_IMUX_B26_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_12" }, "PSS3.PSS0_IMUX_B26_13->PSS1_IMUX_B26_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_13" }, "PSS3.PSS0_IMUX_B26_14->PSS1_IMUX_B26_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_14" }, "PSS3.PSS0_IMUX_B26_15->PSS1_IMUX_B26_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_15" }, "PSS3.PSS0_IMUX_B26_16->PSS1_IMUX_B26_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_16" }, "PSS3.PSS0_IMUX_B26_17->PSS1_IMUX_B26_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_17" }, "PSS3.PSS0_IMUX_B26_18->PSS1_IMUX_B26_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_18" }, "PSS3.PSS0_IMUX_B26_19->PSS1_IMUX_B26_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_19" }, "PSS3.PSS0_IMUX_B26_2->PSS1_IMUX_B26_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_2" }, "PSS3.PSS0_IMUX_B26_3->PSS1_IMUX_B26_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_3" }, "PSS3.PSS0_IMUX_B26_4->PSS1_IMUX_B26_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_4" }, "PSS3.PSS0_IMUX_B26_5->PSS1_IMUX_B26_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_5" }, "PSS3.PSS0_IMUX_B26_6->PSS1_IMUX_B26_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_6" }, "PSS3.PSS0_IMUX_B26_7->PSS1_IMUX_B26_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_7" }, "PSS3.PSS0_IMUX_B26_8->PSS1_IMUX_B26_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_8" }, "PSS3.PSS0_IMUX_B26_9->PSS1_IMUX_B26_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B26_9" }, "PSS3.PSS0_IMUX_B27_0->PSS1_IMUX_B27_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_0" }, "PSS3.PSS0_IMUX_B27_1->PSS1_IMUX_B27_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_1" }, "PSS3.PSS0_IMUX_B27_10->PSS1_IMUX_B27_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_10" }, "PSS3.PSS0_IMUX_B27_11->PSS1_IMUX_B27_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_11" }, "PSS3.PSS0_IMUX_B27_12->PSS1_IMUX_B27_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_12" }, "PSS3.PSS0_IMUX_B27_13->PSS1_IMUX_B27_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_13" }, "PSS3.PSS0_IMUX_B27_14->PSS1_IMUX_B27_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_14" }, "PSS3.PSS0_IMUX_B27_15->PSS1_IMUX_B27_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_15" }, "PSS3.PSS0_IMUX_B27_16->PSS1_IMUX_B27_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_16" }, "PSS3.PSS0_IMUX_B27_17->PSS1_IMUX_B27_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_17" }, "PSS3.PSS0_IMUX_B27_18->PSS1_IMUX_B27_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_18" }, "PSS3.PSS0_IMUX_B27_19->PSS1_IMUX_B27_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_19" }, "PSS3.PSS0_IMUX_B27_2->PSS1_IMUX_B27_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_2" }, "PSS3.PSS0_IMUX_B27_3->PSS1_IMUX_B27_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_3" }, "PSS3.PSS0_IMUX_B27_4->PSS1_IMUX_B27_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_4" }, "PSS3.PSS0_IMUX_B27_5->PSS1_IMUX_B27_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_5" }, "PSS3.PSS0_IMUX_B27_6->PSS1_IMUX_B27_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_6" }, "PSS3.PSS0_IMUX_B27_7->PSS1_IMUX_B27_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_7" }, "PSS3.PSS0_IMUX_B27_8->PSS1_IMUX_B27_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_8" }, "PSS3.PSS0_IMUX_B27_9->PSS1_IMUX_B27_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B27_9" }, "PSS3.PSS0_IMUX_B28_0->PSS1_IMUX_B28_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_0" }, "PSS3.PSS0_IMUX_B28_1->PSS1_IMUX_B28_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_1" }, "PSS3.PSS0_IMUX_B28_10->PSS1_IMUX_B28_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_10" }, "PSS3.PSS0_IMUX_B28_11->PSS1_IMUX_B28_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_11" }, "PSS3.PSS0_IMUX_B28_12->PSS1_IMUX_B28_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_12" }, "PSS3.PSS0_IMUX_B28_13->PSS1_IMUX_B28_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_13" }, "PSS3.PSS0_IMUX_B28_14->PSS1_IMUX_B28_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_14" }, "PSS3.PSS0_IMUX_B28_15->PSS1_IMUX_B28_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_15" }, "PSS3.PSS0_IMUX_B28_16->PSS1_IMUX_B28_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_16" }, "PSS3.PSS0_IMUX_B28_17->PSS1_IMUX_B28_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_17" }, "PSS3.PSS0_IMUX_B28_18->PSS1_IMUX_B28_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_18" }, "PSS3.PSS0_IMUX_B28_19->PSS1_IMUX_B28_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_19" }, "PSS3.PSS0_IMUX_B28_2->PSS1_IMUX_B28_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_2" }, "PSS3.PSS0_IMUX_B28_3->PSS1_IMUX_B28_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_3" }, "PSS3.PSS0_IMUX_B28_4->PSS1_IMUX_B28_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_4" }, "PSS3.PSS0_IMUX_B28_5->PSS1_IMUX_B28_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_5" }, "PSS3.PSS0_IMUX_B28_6->PSS1_IMUX_B28_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_6" }, "PSS3.PSS0_IMUX_B28_7->PSS1_IMUX_B28_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_7" }, "PSS3.PSS0_IMUX_B28_8->PSS1_IMUX_B28_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_8" }, "PSS3.PSS0_IMUX_B28_9->PSS1_IMUX_B28_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B28_9" }, "PSS3.PSS0_IMUX_B29_0->PSS1_IMUX_B29_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_0" }, "PSS3.PSS0_IMUX_B29_1->PSS1_IMUX_B29_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_1" }, "PSS3.PSS0_IMUX_B29_10->PSS1_IMUX_B29_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_10" }, "PSS3.PSS0_IMUX_B29_11->PSS1_IMUX_B29_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_11" }, "PSS3.PSS0_IMUX_B29_12->PSS1_IMUX_B29_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_12" }, "PSS3.PSS0_IMUX_B29_13->PSS1_IMUX_B29_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_13" }, "PSS3.PSS0_IMUX_B29_14->PSS1_IMUX_B29_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_14" }, "PSS3.PSS0_IMUX_B29_15->PSS1_IMUX_B29_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_15" }, "PSS3.PSS0_IMUX_B29_16->PSS1_IMUX_B29_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_16" }, "PSS3.PSS0_IMUX_B29_17->PSS1_IMUX_B29_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_17" }, "PSS3.PSS0_IMUX_B29_18->PSS1_IMUX_B29_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_18" }, "PSS3.PSS0_IMUX_B29_19->PSS1_IMUX_B29_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_19" }, "PSS3.PSS0_IMUX_B29_2->PSS1_IMUX_B29_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_2" }, "PSS3.PSS0_IMUX_B29_3->PSS1_IMUX_B29_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_3" }, "PSS3.PSS0_IMUX_B29_4->PSS1_IMUX_B29_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_4" }, "PSS3.PSS0_IMUX_B29_5->PSS1_IMUX_B29_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_5" }, "PSS3.PSS0_IMUX_B29_6->PSS1_IMUX_B29_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_6" }, "PSS3.PSS0_IMUX_B29_7->PSS1_IMUX_B29_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_7" }, "PSS3.PSS0_IMUX_B29_8->PSS1_IMUX_B29_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_8" }, "PSS3.PSS0_IMUX_B29_9->PSS1_IMUX_B29_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B29_9" }, "PSS3.PSS0_IMUX_B2_0->PSS1_IMUX_B2_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_0" }, "PSS3.PSS0_IMUX_B2_1->PSS1_IMUX_B2_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_1" }, "PSS3.PSS0_IMUX_B2_10->PSS1_IMUX_B2_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_10" }, "PSS3.PSS0_IMUX_B2_11->PSS1_IMUX_B2_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_11" }, "PSS3.PSS0_IMUX_B2_12->PSS1_IMUX_B2_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_12" }, "PSS3.PSS0_IMUX_B2_13->PSS1_IMUX_B2_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_13" }, "PSS3.PSS0_IMUX_B2_14->PSS1_IMUX_B2_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_14" }, "PSS3.PSS0_IMUX_B2_15->PSS1_IMUX_B2_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_15" }, "PSS3.PSS0_IMUX_B2_16->PSS1_IMUX_B2_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_16" }, "PSS3.PSS0_IMUX_B2_17->PSS1_IMUX_B2_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_17" }, "PSS3.PSS0_IMUX_B2_18->PSS1_IMUX_B2_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_18" }, "PSS3.PSS0_IMUX_B2_19->PSS1_IMUX_B2_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_19" }, "PSS3.PSS0_IMUX_B2_2->PSS1_IMUX_B2_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_2" }, "PSS3.PSS0_IMUX_B2_3->PSS1_IMUX_B2_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_3" }, "PSS3.PSS0_IMUX_B2_4->PSS1_IMUX_B2_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_4" }, "PSS3.PSS0_IMUX_B2_5->PSS1_IMUX_B2_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_5" }, "PSS3.PSS0_IMUX_B2_6->PSS1_IMUX_B2_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_6" }, "PSS3.PSS0_IMUX_B2_7->PSS1_IMUX_B2_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_7" }, "PSS3.PSS0_IMUX_B2_8->PSS1_IMUX_B2_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_8" }, "PSS3.PSS0_IMUX_B2_9->PSS1_IMUX_B2_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B2_9" }, "PSS3.PSS0_IMUX_B30_0->PSS1_IMUX_B30_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_0" }, "PSS3.PSS0_IMUX_B30_1->PSS1_IMUX_B30_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_1" }, "PSS3.PSS0_IMUX_B30_10->PSS1_IMUX_B30_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_10" }, "PSS3.PSS0_IMUX_B30_11->PSS1_IMUX_B30_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_11" }, "PSS3.PSS0_IMUX_B30_12->PSS1_IMUX_B30_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_12" }, "PSS3.PSS0_IMUX_B30_13->PSS1_IMUX_B30_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_13" }, "PSS3.PSS0_IMUX_B30_14->PSS1_IMUX_B30_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_14" }, "PSS3.PSS0_IMUX_B30_15->PSS1_IMUX_B30_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_15" }, "PSS3.PSS0_IMUX_B30_16->PSS1_IMUX_B30_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_16" }, "PSS3.PSS0_IMUX_B30_17->PSS1_IMUX_B30_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_17" }, "PSS3.PSS0_IMUX_B30_18->PSS1_IMUX_B30_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_18" }, "PSS3.PSS0_IMUX_B30_19->PSS1_IMUX_B30_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_19" }, "PSS3.PSS0_IMUX_B30_2->PSS1_IMUX_B30_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_2" }, "PSS3.PSS0_IMUX_B30_3->PSS1_IMUX_B30_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_3" }, "PSS3.PSS0_IMUX_B30_4->PSS1_IMUX_B30_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_4" }, "PSS3.PSS0_IMUX_B30_5->PSS1_IMUX_B30_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_5" }, "PSS3.PSS0_IMUX_B30_6->PSS1_IMUX_B30_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_6" }, "PSS3.PSS0_IMUX_B30_7->PSS1_IMUX_B30_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_7" }, "PSS3.PSS0_IMUX_B30_8->PSS1_IMUX_B30_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_8" }, "PSS3.PSS0_IMUX_B30_9->PSS1_IMUX_B30_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B30_9" }, "PSS3.PSS0_IMUX_B31_0->PSS1_IMUX_B31_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_0" }, "PSS3.PSS0_IMUX_B31_1->PSS1_IMUX_B31_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_1" }, "PSS3.PSS0_IMUX_B31_10->PSS1_IMUX_B31_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_10" }, "PSS3.PSS0_IMUX_B31_11->PSS1_IMUX_B31_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_11" }, "PSS3.PSS0_IMUX_B31_12->PSS1_IMUX_B31_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_12" }, "PSS3.PSS0_IMUX_B31_13->PSS1_IMUX_B31_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_13" }, "PSS3.PSS0_IMUX_B31_14->PSS1_IMUX_B31_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_14" }, "PSS3.PSS0_IMUX_B31_15->PSS1_IMUX_B31_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_15" }, "PSS3.PSS0_IMUX_B31_16->PSS1_IMUX_B31_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_16" }, "PSS3.PSS0_IMUX_B31_17->PSS1_IMUX_B31_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_17" }, "PSS3.PSS0_IMUX_B31_18->PSS1_IMUX_B31_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_18" }, "PSS3.PSS0_IMUX_B31_19->PSS1_IMUX_B31_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_19" }, "PSS3.PSS0_IMUX_B31_2->PSS1_IMUX_B31_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_2" }, "PSS3.PSS0_IMUX_B31_3->PSS1_IMUX_B31_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_3" }, "PSS3.PSS0_IMUX_B31_4->PSS1_IMUX_B31_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_4" }, "PSS3.PSS0_IMUX_B31_5->PSS1_IMUX_B31_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_5" }, "PSS3.PSS0_IMUX_B31_6->PSS1_IMUX_B31_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_6" }, "PSS3.PSS0_IMUX_B31_7->PSS1_IMUX_B31_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_7" }, "PSS3.PSS0_IMUX_B31_8->PSS1_IMUX_B31_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_8" }, "PSS3.PSS0_IMUX_B31_9->PSS1_IMUX_B31_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B31_9" }, "PSS3.PSS0_IMUX_B32_0->PSS1_IMUX_B32_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_0" }, "PSS3.PSS0_IMUX_B32_1->PSS1_IMUX_B32_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_1" }, "PSS3.PSS0_IMUX_B32_10->PSS1_IMUX_B32_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_10" }, "PSS3.PSS0_IMUX_B32_11->PSS1_IMUX_B32_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_11" }, "PSS3.PSS0_IMUX_B32_12->PSS1_IMUX_B32_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_12" }, "PSS3.PSS0_IMUX_B32_13->PSS1_IMUX_B32_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_13" }, "PSS3.PSS0_IMUX_B32_14->PSS1_IMUX_B32_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_14" }, "PSS3.PSS0_IMUX_B32_15->PSS1_IMUX_B32_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_15" }, "PSS3.PSS0_IMUX_B32_16->PSS1_IMUX_B32_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_16" }, "PSS3.PSS0_IMUX_B32_17->PSS1_IMUX_B32_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_17" }, "PSS3.PSS0_IMUX_B32_18->PSS1_IMUX_B32_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_18" }, "PSS3.PSS0_IMUX_B32_19->PSS1_IMUX_B32_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_19" }, "PSS3.PSS0_IMUX_B32_2->PSS1_IMUX_B32_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_2" }, "PSS3.PSS0_IMUX_B32_3->PSS1_IMUX_B32_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_3" }, "PSS3.PSS0_IMUX_B32_4->PSS1_IMUX_B32_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_4" }, "PSS3.PSS0_IMUX_B32_5->PSS1_IMUX_B32_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_5" }, "PSS3.PSS0_IMUX_B32_6->PSS1_IMUX_B32_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_6" }, "PSS3.PSS0_IMUX_B32_7->PSS1_IMUX_B32_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_7" }, "PSS3.PSS0_IMUX_B32_8->PSS1_IMUX_B32_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_8" }, "PSS3.PSS0_IMUX_B32_9->PSS1_IMUX_B32_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B32_9" }, "PSS3.PSS0_IMUX_B33_0->PSS1_IMUX_B33_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_0" }, "PSS3.PSS0_IMUX_B33_1->PSS1_IMUX_B33_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_1" }, "PSS3.PSS0_IMUX_B33_10->PSS1_IMUX_B33_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_10" }, "PSS3.PSS0_IMUX_B33_11->PSS1_IMUX_B33_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_11" }, "PSS3.PSS0_IMUX_B33_12->PSS1_IMUX_B33_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_12" }, "PSS3.PSS0_IMUX_B33_13->PSS1_IMUX_B33_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_13" }, "PSS3.PSS0_IMUX_B33_14->PSS1_IMUX_B33_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_14" }, "PSS3.PSS0_IMUX_B33_15->PSS1_IMUX_B33_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_15" }, "PSS3.PSS0_IMUX_B33_16->PSS1_IMUX_B33_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_16" }, "PSS3.PSS0_IMUX_B33_17->PSS1_IMUX_B33_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_17" }, "PSS3.PSS0_IMUX_B33_18->PSS1_IMUX_B33_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_18" }, "PSS3.PSS0_IMUX_B33_19->PSS1_IMUX_B33_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_19" }, "PSS3.PSS0_IMUX_B33_2->PSS1_IMUX_B33_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_2" }, "PSS3.PSS0_IMUX_B33_3->PSS1_IMUX_B33_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_3" }, "PSS3.PSS0_IMUX_B33_4->PSS1_IMUX_B33_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_4" }, "PSS3.PSS0_IMUX_B33_5->PSS1_IMUX_B33_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_5" }, "PSS3.PSS0_IMUX_B33_6->PSS1_IMUX_B33_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_6" }, "PSS3.PSS0_IMUX_B33_7->PSS1_IMUX_B33_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_7" }, "PSS3.PSS0_IMUX_B33_8->PSS1_IMUX_B33_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_8" }, "PSS3.PSS0_IMUX_B33_9->PSS1_IMUX_B33_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B33_9" }, "PSS3.PSS0_IMUX_B34_0->PSS1_IMUX_B34_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_0" }, "PSS3.PSS0_IMUX_B34_1->PSS1_IMUX_B34_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_1" }, "PSS3.PSS0_IMUX_B34_10->PSS1_IMUX_B34_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_10" }, "PSS3.PSS0_IMUX_B34_11->PSS1_IMUX_B34_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_11" }, "PSS3.PSS0_IMUX_B34_12->PSS1_IMUX_B34_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_12" }, "PSS3.PSS0_IMUX_B34_13->PSS1_IMUX_B34_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_13" }, "PSS3.PSS0_IMUX_B34_14->PSS1_IMUX_B34_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_14" }, "PSS3.PSS0_IMUX_B34_15->PSS1_IMUX_B34_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_15" }, "PSS3.PSS0_IMUX_B34_16->PSS1_IMUX_B34_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_16" }, "PSS3.PSS0_IMUX_B34_17->PSS1_IMUX_B34_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_17" }, "PSS3.PSS0_IMUX_B34_18->PSS1_IMUX_B34_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_18" }, "PSS3.PSS0_IMUX_B34_19->PSS1_IMUX_B34_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_19" }, "PSS3.PSS0_IMUX_B34_2->PSS1_IMUX_B34_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_2" }, "PSS3.PSS0_IMUX_B34_3->PSS1_IMUX_B34_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_3" }, "PSS3.PSS0_IMUX_B34_4->PSS1_IMUX_B34_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_4" }, "PSS3.PSS0_IMUX_B34_5->PSS1_IMUX_B34_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_5" }, "PSS3.PSS0_IMUX_B34_6->PSS1_IMUX_B34_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_6" }, "PSS3.PSS0_IMUX_B34_7->PSS1_IMUX_B34_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_7" }, "PSS3.PSS0_IMUX_B34_8->PSS1_IMUX_B34_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_8" }, "PSS3.PSS0_IMUX_B34_9->PSS1_IMUX_B34_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B34_9" }, "PSS3.PSS0_IMUX_B35_0->PSS1_IMUX_B35_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_0" }, "PSS3.PSS0_IMUX_B35_1->PSS1_IMUX_B35_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_1" }, "PSS3.PSS0_IMUX_B35_10->PSS1_IMUX_B35_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_10" }, "PSS3.PSS0_IMUX_B35_11->PSS1_IMUX_B35_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_11" }, "PSS3.PSS0_IMUX_B35_12->PSS1_IMUX_B35_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_12" }, "PSS3.PSS0_IMUX_B35_13->PSS1_IMUX_B35_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_13" }, "PSS3.PSS0_IMUX_B35_14->PSS1_IMUX_B35_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_14" }, "PSS3.PSS0_IMUX_B35_15->PSS1_IMUX_B35_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_15" }, "PSS3.PSS0_IMUX_B35_16->PSS1_IMUX_B35_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_16" }, "PSS3.PSS0_IMUX_B35_17->PSS1_IMUX_B35_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_17" }, "PSS3.PSS0_IMUX_B35_18->PSS1_IMUX_B35_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_18" }, "PSS3.PSS0_IMUX_B35_19->PSS1_IMUX_B35_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_19" }, "PSS3.PSS0_IMUX_B35_2->PSS1_IMUX_B35_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_2" }, "PSS3.PSS0_IMUX_B35_3->PSS1_IMUX_B35_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_3" }, "PSS3.PSS0_IMUX_B35_4->PSS1_IMUX_B35_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_4" }, "PSS3.PSS0_IMUX_B35_5->PSS1_IMUX_B35_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_5" }, "PSS3.PSS0_IMUX_B35_6->PSS1_IMUX_B35_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_6" }, "PSS3.PSS0_IMUX_B35_7->PSS1_IMUX_B35_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_7" }, "PSS3.PSS0_IMUX_B35_8->PSS1_IMUX_B35_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_8" }, "PSS3.PSS0_IMUX_B35_9->PSS1_IMUX_B35_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B35_9" }, "PSS3.PSS0_IMUX_B36_0->PSS1_IMUX_B36_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_0" }, "PSS3.PSS0_IMUX_B36_1->PSS1_IMUX_B36_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_1" }, "PSS3.PSS0_IMUX_B36_10->PSS1_IMUX_B36_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_10" }, "PSS3.PSS0_IMUX_B36_11->PSS1_IMUX_B36_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_11" }, "PSS3.PSS0_IMUX_B36_12->PSS1_IMUX_B36_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_12" }, "PSS3.PSS0_IMUX_B36_13->PSS1_IMUX_B36_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_13" }, "PSS3.PSS0_IMUX_B36_14->PSS1_IMUX_B36_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_14" }, "PSS3.PSS0_IMUX_B36_15->PSS1_IMUX_B36_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_15" }, "PSS3.PSS0_IMUX_B36_16->PSS1_IMUX_B36_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_16" }, "PSS3.PSS0_IMUX_B36_17->PSS1_IMUX_B36_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_17" }, "PSS3.PSS0_IMUX_B36_18->PSS1_IMUX_B36_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_18" }, "PSS3.PSS0_IMUX_B36_19->PSS1_IMUX_B36_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_19" }, "PSS3.PSS0_IMUX_B36_2->PSS1_IMUX_B36_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_2" }, "PSS3.PSS0_IMUX_B36_3->PSS1_IMUX_B36_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_3" }, "PSS3.PSS0_IMUX_B36_4->PSS1_IMUX_B36_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_4" }, "PSS3.PSS0_IMUX_B36_5->PSS1_IMUX_B36_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_5" }, "PSS3.PSS0_IMUX_B36_6->PSS1_IMUX_B36_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_6" }, "PSS3.PSS0_IMUX_B36_7->PSS1_IMUX_B36_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_7" }, "PSS3.PSS0_IMUX_B36_8->PSS1_IMUX_B36_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_8" }, "PSS3.PSS0_IMUX_B36_9->PSS1_IMUX_B36_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B36_9" }, "PSS3.PSS0_IMUX_B37_0->PSS1_IMUX_B37_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_0" }, "PSS3.PSS0_IMUX_B37_1->PSS1_IMUX_B37_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_1" }, "PSS3.PSS0_IMUX_B37_10->PSS1_IMUX_B37_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_10" }, "PSS3.PSS0_IMUX_B37_11->PSS1_IMUX_B37_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_11" }, "PSS3.PSS0_IMUX_B37_12->PSS1_IMUX_B37_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_12" }, "PSS3.PSS0_IMUX_B37_13->PSS1_IMUX_B37_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_13" }, "PSS3.PSS0_IMUX_B37_14->PSS1_IMUX_B37_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_14" }, "PSS3.PSS0_IMUX_B37_15->PSS1_IMUX_B37_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_15" }, "PSS3.PSS0_IMUX_B37_16->PSS1_IMUX_B37_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_16" }, "PSS3.PSS0_IMUX_B37_17->PSS1_IMUX_B37_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_17" }, "PSS3.PSS0_IMUX_B37_18->PSS1_IMUX_B37_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_18" }, "PSS3.PSS0_IMUX_B37_19->PSS1_IMUX_B37_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_19" }, "PSS3.PSS0_IMUX_B37_2->PSS1_IMUX_B37_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_2" }, "PSS3.PSS0_IMUX_B37_3->PSS1_IMUX_B37_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_3" }, "PSS3.PSS0_IMUX_B37_4->PSS1_IMUX_B37_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_4" }, "PSS3.PSS0_IMUX_B37_5->PSS1_IMUX_B37_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_5" }, "PSS3.PSS0_IMUX_B37_6->PSS1_IMUX_B37_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_6" }, "PSS3.PSS0_IMUX_B37_7->PSS1_IMUX_B37_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_7" }, "PSS3.PSS0_IMUX_B37_8->PSS1_IMUX_B37_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_8" }, "PSS3.PSS0_IMUX_B37_9->PSS1_IMUX_B37_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B37_9" }, "PSS3.PSS0_IMUX_B38_0->PSS1_IMUX_B38_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_0" }, "PSS3.PSS0_IMUX_B38_1->PSS1_IMUX_B38_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_1" }, "PSS3.PSS0_IMUX_B38_10->PSS1_IMUX_B38_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_10" }, "PSS3.PSS0_IMUX_B38_11->PSS1_IMUX_B38_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_11" }, "PSS3.PSS0_IMUX_B38_12->PSS1_IMUX_B38_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_12" }, "PSS3.PSS0_IMUX_B38_13->PSS1_IMUX_B38_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_13" }, "PSS3.PSS0_IMUX_B38_14->PSS1_IMUX_B38_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_14" }, "PSS3.PSS0_IMUX_B38_15->PSS1_IMUX_B38_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_15" }, "PSS3.PSS0_IMUX_B38_16->PSS1_IMUX_B38_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_16" }, "PSS3.PSS0_IMUX_B38_17->PSS1_IMUX_B38_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_17" }, "PSS3.PSS0_IMUX_B38_18->PSS1_IMUX_B38_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_18" }, "PSS3.PSS0_IMUX_B38_19->PSS1_IMUX_B38_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_19" }, "PSS3.PSS0_IMUX_B38_2->PSS1_IMUX_B38_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_2" }, "PSS3.PSS0_IMUX_B38_3->PSS1_IMUX_B38_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_3" }, "PSS3.PSS0_IMUX_B38_4->PSS1_IMUX_B38_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_4" }, "PSS3.PSS0_IMUX_B38_5->PSS1_IMUX_B38_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_5" }, "PSS3.PSS0_IMUX_B38_6->PSS1_IMUX_B38_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_6" }, "PSS3.PSS0_IMUX_B38_7->PSS1_IMUX_B38_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_7" }, "PSS3.PSS0_IMUX_B38_8->PSS1_IMUX_B38_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_8" }, "PSS3.PSS0_IMUX_B38_9->PSS1_IMUX_B38_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B38_9" }, "PSS3.PSS0_IMUX_B39_0->PSS1_IMUX_B39_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_0" }, "PSS3.PSS0_IMUX_B39_1->PSS1_IMUX_B39_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_1" }, "PSS3.PSS0_IMUX_B39_10->PSS1_IMUX_B39_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_10" }, "PSS3.PSS0_IMUX_B39_11->PSS1_IMUX_B39_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_11" }, "PSS3.PSS0_IMUX_B39_12->PSS1_IMUX_B39_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_12" }, "PSS3.PSS0_IMUX_B39_13->PSS1_IMUX_B39_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_13" }, "PSS3.PSS0_IMUX_B39_14->PSS1_IMUX_B39_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_14" }, "PSS3.PSS0_IMUX_B39_15->PSS1_IMUX_B39_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_15" }, "PSS3.PSS0_IMUX_B39_16->PSS1_IMUX_B39_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_16" }, "PSS3.PSS0_IMUX_B39_17->PSS1_IMUX_B39_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_17" }, "PSS3.PSS0_IMUX_B39_18->PSS1_IMUX_B39_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_18" }, "PSS3.PSS0_IMUX_B39_19->PSS1_IMUX_B39_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_19" }, "PSS3.PSS0_IMUX_B39_2->PSS1_IMUX_B39_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_2" }, "PSS3.PSS0_IMUX_B39_3->PSS1_IMUX_B39_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_3" }, "PSS3.PSS0_IMUX_B39_4->PSS1_IMUX_B39_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_4" }, "PSS3.PSS0_IMUX_B39_5->PSS1_IMUX_B39_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_5" }, "PSS3.PSS0_IMUX_B39_6->PSS1_IMUX_B39_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_6" }, "PSS3.PSS0_IMUX_B39_7->PSS1_IMUX_B39_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_7" }, "PSS3.PSS0_IMUX_B39_8->PSS1_IMUX_B39_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_8" }, "PSS3.PSS0_IMUX_B39_9->PSS1_IMUX_B39_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B39_9" }, "PSS3.PSS0_IMUX_B3_0->PSS1_IMUX_B3_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_0" }, "PSS3.PSS0_IMUX_B3_1->PSS1_IMUX_B3_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_1" }, "PSS3.PSS0_IMUX_B3_10->PSS1_IMUX_B3_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_10" }, "PSS3.PSS0_IMUX_B3_11->PSS1_IMUX_B3_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_11" }, "PSS3.PSS0_IMUX_B3_12->PSS1_IMUX_B3_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_12" }, "PSS3.PSS0_IMUX_B3_13->PSS1_IMUX_B3_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_13" }, "PSS3.PSS0_IMUX_B3_14->PSS1_IMUX_B3_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_14" }, "PSS3.PSS0_IMUX_B3_15->PSS1_IMUX_B3_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_15" }, "PSS3.PSS0_IMUX_B3_16->PSS1_IMUX_B3_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_16" }, "PSS3.PSS0_IMUX_B3_17->PSS1_IMUX_B3_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_17" }, "PSS3.PSS0_IMUX_B3_18->PSS1_IMUX_B3_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_18" }, "PSS3.PSS0_IMUX_B3_19->PSS1_IMUX_B3_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_19" }, "PSS3.PSS0_IMUX_B3_2->PSS1_IMUX_B3_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_2" }, "PSS3.PSS0_IMUX_B3_3->PSS1_IMUX_B3_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_3" }, "PSS3.PSS0_IMUX_B3_4->PSS1_IMUX_B3_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_4" }, "PSS3.PSS0_IMUX_B3_5->PSS1_IMUX_B3_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_5" }, "PSS3.PSS0_IMUX_B3_6->PSS1_IMUX_B3_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_6" }, "PSS3.PSS0_IMUX_B3_7->PSS1_IMUX_B3_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_7" }, "PSS3.PSS0_IMUX_B3_8->PSS1_IMUX_B3_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_8" }, "PSS3.PSS0_IMUX_B3_9->PSS1_IMUX_B3_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B3_9" }, "PSS3.PSS0_IMUX_B40_0->PSS1_IMUX_B40_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_0" }, "PSS3.PSS0_IMUX_B40_1->PSS1_IMUX_B40_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_1" }, "PSS3.PSS0_IMUX_B40_10->PSS1_IMUX_B40_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_10" }, "PSS3.PSS0_IMUX_B40_11->PSS1_IMUX_B40_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_11" }, "PSS3.PSS0_IMUX_B40_12->PSS1_IMUX_B40_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_12" }, "PSS3.PSS0_IMUX_B40_13->PSS1_IMUX_B40_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_13" }, "PSS3.PSS0_IMUX_B40_14->PSS1_IMUX_B40_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_14" }, "PSS3.PSS0_IMUX_B40_15->PSS1_IMUX_B40_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_15" }, "PSS3.PSS0_IMUX_B40_16->PSS1_IMUX_B40_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_16" }, "PSS3.PSS0_IMUX_B40_17->PSS1_IMUX_B40_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_17" }, "PSS3.PSS0_IMUX_B40_18->PSS1_IMUX_B40_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_18" }, "PSS3.PSS0_IMUX_B40_19->PSS1_IMUX_B40_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_19" }, "PSS3.PSS0_IMUX_B40_2->PSS1_IMUX_B40_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_2" }, "PSS3.PSS0_IMUX_B40_3->PSS1_IMUX_B40_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_3" }, "PSS3.PSS0_IMUX_B40_4->PSS1_IMUX_B40_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_4" }, "PSS3.PSS0_IMUX_B40_5->PSS1_IMUX_B40_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_5" }, "PSS3.PSS0_IMUX_B40_6->PSS1_IMUX_B40_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_6" }, "PSS3.PSS0_IMUX_B40_7->PSS1_IMUX_B40_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_7" }, "PSS3.PSS0_IMUX_B40_8->PSS1_IMUX_B40_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_8" }, "PSS3.PSS0_IMUX_B40_9->PSS1_IMUX_B40_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B40_9" }, "PSS3.PSS0_IMUX_B41_0->PSS1_IMUX_B41_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_0" }, "PSS3.PSS0_IMUX_B41_1->PSS1_IMUX_B41_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_1" }, "PSS3.PSS0_IMUX_B41_10->PSS1_IMUX_B41_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_10" }, "PSS3.PSS0_IMUX_B41_11->PSS1_IMUX_B41_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_11" }, "PSS3.PSS0_IMUX_B41_12->PSS1_IMUX_B41_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_12" }, "PSS3.PSS0_IMUX_B41_13->PSS1_IMUX_B41_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_13" }, "PSS3.PSS0_IMUX_B41_14->PSS1_IMUX_B41_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_14" }, "PSS3.PSS0_IMUX_B41_15->PSS1_IMUX_B41_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_15" }, "PSS3.PSS0_IMUX_B41_16->PSS1_IMUX_B41_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_16" }, "PSS3.PSS0_IMUX_B41_17->PSS1_IMUX_B41_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_17" }, "PSS3.PSS0_IMUX_B41_18->PSS1_IMUX_B41_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_18" }, "PSS3.PSS0_IMUX_B41_19->PSS1_IMUX_B41_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_19" }, "PSS3.PSS0_IMUX_B41_2->PSS1_IMUX_B41_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_2" }, "PSS3.PSS0_IMUX_B41_3->PSS1_IMUX_B41_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_3" }, "PSS3.PSS0_IMUX_B41_4->PSS1_IMUX_B41_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_4" }, "PSS3.PSS0_IMUX_B41_5->PSS1_IMUX_B41_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_5" }, "PSS3.PSS0_IMUX_B41_6->PSS1_IMUX_B41_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_6" }, "PSS3.PSS0_IMUX_B41_7->PSS1_IMUX_B41_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_7" }, "PSS3.PSS0_IMUX_B41_8->PSS1_IMUX_B41_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_8" }, "PSS3.PSS0_IMUX_B41_9->PSS1_IMUX_B41_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B41_9" }, "PSS3.PSS0_IMUX_B42_0->PSS1_IMUX_B42_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_0" }, "PSS3.PSS0_IMUX_B42_1->PSS1_IMUX_B42_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_1" }, "PSS3.PSS0_IMUX_B42_10->PSS1_IMUX_B42_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_10" }, "PSS3.PSS0_IMUX_B42_11->PSS1_IMUX_B42_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_11" }, "PSS3.PSS0_IMUX_B42_12->PSS1_IMUX_B42_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_12" }, "PSS3.PSS0_IMUX_B42_13->PSS1_IMUX_B42_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_13" }, "PSS3.PSS0_IMUX_B42_14->PSS1_IMUX_B42_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_14" }, "PSS3.PSS0_IMUX_B42_15->PSS1_IMUX_B42_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_15" }, "PSS3.PSS0_IMUX_B42_16->PSS1_IMUX_B42_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_16" }, "PSS3.PSS0_IMUX_B42_17->PSS1_IMUX_B42_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_17" }, "PSS3.PSS0_IMUX_B42_18->PSS1_IMUX_B42_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_18" }, "PSS3.PSS0_IMUX_B42_19->PSS1_IMUX_B42_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_19" }, "PSS3.PSS0_IMUX_B42_2->PSS1_IMUX_B42_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_2" }, "PSS3.PSS0_IMUX_B42_3->PSS1_IMUX_B42_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_3" }, "PSS3.PSS0_IMUX_B42_4->PSS1_IMUX_B42_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_4" }, "PSS3.PSS0_IMUX_B42_5->PSS1_IMUX_B42_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_5" }, "PSS3.PSS0_IMUX_B42_6->PSS1_IMUX_B42_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_6" }, "PSS3.PSS0_IMUX_B42_7->PSS1_IMUX_B42_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_7" }, "PSS3.PSS0_IMUX_B42_8->PSS1_IMUX_B42_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_8" }, "PSS3.PSS0_IMUX_B42_9->PSS1_IMUX_B42_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B42_9" }, "PSS3.PSS0_IMUX_B43_0->PSS1_IMUX_B43_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_0" }, "PSS3.PSS0_IMUX_B43_1->PSS1_IMUX_B43_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_1" }, "PSS3.PSS0_IMUX_B43_10->PSS1_IMUX_B43_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_10" }, "PSS3.PSS0_IMUX_B43_11->PSS1_IMUX_B43_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_11" }, "PSS3.PSS0_IMUX_B43_12->PSS1_IMUX_B43_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_12" }, "PSS3.PSS0_IMUX_B43_13->PSS1_IMUX_B43_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_13" }, "PSS3.PSS0_IMUX_B43_14->PSS1_IMUX_B43_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_14" }, "PSS3.PSS0_IMUX_B43_15->PSS1_IMUX_B43_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_15" }, "PSS3.PSS0_IMUX_B43_16->PSS1_IMUX_B43_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_16" }, "PSS3.PSS0_IMUX_B43_17->PSS1_IMUX_B43_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_17" }, "PSS3.PSS0_IMUX_B43_18->PSS1_IMUX_B43_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_18" }, "PSS3.PSS0_IMUX_B43_19->PSS1_IMUX_B43_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_19" }, "PSS3.PSS0_IMUX_B43_2->PSS1_IMUX_B43_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_2" }, "PSS3.PSS0_IMUX_B43_3->PSS1_IMUX_B43_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_3" }, "PSS3.PSS0_IMUX_B43_4->PSS1_IMUX_B43_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_4" }, "PSS3.PSS0_IMUX_B43_5->PSS1_IMUX_B43_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_5" }, "PSS3.PSS0_IMUX_B43_6->PSS1_IMUX_B43_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_6" }, "PSS3.PSS0_IMUX_B43_7->PSS1_IMUX_B43_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_7" }, "PSS3.PSS0_IMUX_B43_8->PSS1_IMUX_B43_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_8" }, "PSS3.PSS0_IMUX_B43_9->PSS1_IMUX_B43_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B43_9" }, "PSS3.PSS0_IMUX_B44_0->PSS1_IMUX_B44_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_0" }, "PSS3.PSS0_IMUX_B44_1->PSS1_IMUX_B44_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_1" }, "PSS3.PSS0_IMUX_B44_10->PSS1_IMUX_B44_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_10" }, "PSS3.PSS0_IMUX_B44_11->PSS1_IMUX_B44_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_11" }, "PSS3.PSS0_IMUX_B44_12->PSS1_IMUX_B44_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_12" }, "PSS3.PSS0_IMUX_B44_13->PSS1_IMUX_B44_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_13" }, "PSS3.PSS0_IMUX_B44_14->PSS1_IMUX_B44_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_14" }, "PSS3.PSS0_IMUX_B44_15->PSS1_IMUX_B44_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_15" }, "PSS3.PSS0_IMUX_B44_16->PSS1_IMUX_B44_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_16" }, "PSS3.PSS0_IMUX_B44_17->PSS1_IMUX_B44_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_17" }, "PSS3.PSS0_IMUX_B44_18->PSS1_IMUX_B44_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_18" }, "PSS3.PSS0_IMUX_B44_19->PSS1_IMUX_B44_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_19" }, "PSS3.PSS0_IMUX_B44_2->PSS1_IMUX_B44_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_2" }, "PSS3.PSS0_IMUX_B44_3->PSS1_IMUX_B44_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_3" }, "PSS3.PSS0_IMUX_B44_4->PSS1_IMUX_B44_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_4" }, "PSS3.PSS0_IMUX_B44_5->PSS1_IMUX_B44_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_5" }, "PSS3.PSS0_IMUX_B44_6->PSS1_IMUX_B44_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_6" }, "PSS3.PSS0_IMUX_B44_7->PSS1_IMUX_B44_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_7" }, "PSS3.PSS0_IMUX_B44_8->PSS1_IMUX_B44_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_8" }, "PSS3.PSS0_IMUX_B44_9->PSS1_IMUX_B44_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B44_9" }, "PSS3.PSS0_IMUX_B45_0->PSS1_IMUX_B45_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_0" }, "PSS3.PSS0_IMUX_B45_1->PSS1_IMUX_B45_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_1" }, "PSS3.PSS0_IMUX_B45_10->PSS1_IMUX_B45_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_10" }, "PSS3.PSS0_IMUX_B45_11->PSS1_IMUX_B45_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_11" }, "PSS3.PSS0_IMUX_B45_12->PSS1_IMUX_B45_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_12" }, "PSS3.PSS0_IMUX_B45_13->PSS1_IMUX_B45_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_13" }, "PSS3.PSS0_IMUX_B45_14->PSS1_IMUX_B45_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_14" }, "PSS3.PSS0_IMUX_B45_15->PSS1_IMUX_B45_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_15" }, "PSS3.PSS0_IMUX_B45_16->PSS1_IMUX_B45_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_16" }, "PSS3.PSS0_IMUX_B45_17->PSS1_IMUX_B45_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_17" }, "PSS3.PSS0_IMUX_B45_18->PSS1_IMUX_B45_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_18" }, "PSS3.PSS0_IMUX_B45_19->PSS1_IMUX_B45_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_19" }, "PSS3.PSS0_IMUX_B45_2->PSS1_IMUX_B45_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_2" }, "PSS3.PSS0_IMUX_B45_3->PSS1_IMUX_B45_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_3" }, "PSS3.PSS0_IMUX_B45_4->PSS1_IMUX_B45_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_4" }, "PSS3.PSS0_IMUX_B45_5->PSS1_IMUX_B45_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_5" }, "PSS3.PSS0_IMUX_B45_6->PSS1_IMUX_B45_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_6" }, "PSS3.PSS0_IMUX_B45_7->PSS1_IMUX_B45_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_7" }, "PSS3.PSS0_IMUX_B45_8->PSS1_IMUX_B45_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_8" }, "PSS3.PSS0_IMUX_B45_9->PSS1_IMUX_B45_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B45_9" }, "PSS3.PSS0_IMUX_B46_0->PSS1_IMUX_B46_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_0" }, "PSS3.PSS0_IMUX_B46_1->PSS1_IMUX_B46_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_1" }, "PSS3.PSS0_IMUX_B46_10->PSS1_IMUX_B46_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_10" }, "PSS3.PSS0_IMUX_B46_11->PSS1_IMUX_B46_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_11" }, "PSS3.PSS0_IMUX_B46_12->PSS1_IMUX_B46_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_12" }, "PSS3.PSS0_IMUX_B46_13->PSS1_IMUX_B46_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_13" }, "PSS3.PSS0_IMUX_B46_14->PSS1_IMUX_B46_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_14" }, "PSS3.PSS0_IMUX_B46_15->PSS1_IMUX_B46_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_15" }, "PSS3.PSS0_IMUX_B46_16->PSS1_IMUX_B46_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_16" }, "PSS3.PSS0_IMUX_B46_17->PSS1_IMUX_B46_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_17" }, "PSS3.PSS0_IMUX_B46_18->PSS1_IMUX_B46_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_18" }, "PSS3.PSS0_IMUX_B46_19->PSS1_IMUX_B46_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_19" }, "PSS3.PSS0_IMUX_B46_2->PSS1_IMUX_B46_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_2" }, "PSS3.PSS0_IMUX_B46_3->PSS1_IMUX_B46_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_3" }, "PSS3.PSS0_IMUX_B46_4->PSS1_IMUX_B46_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_4" }, "PSS3.PSS0_IMUX_B46_5->PSS1_IMUX_B46_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_5" }, "PSS3.PSS0_IMUX_B46_6->PSS1_IMUX_B46_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_6" }, "PSS3.PSS0_IMUX_B46_7->PSS1_IMUX_B46_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_7" }, "PSS3.PSS0_IMUX_B46_8->PSS1_IMUX_B46_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_8" }, "PSS3.PSS0_IMUX_B46_9->PSS1_IMUX_B46_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B46_9" }, "PSS3.PSS0_IMUX_B47_0->PSS1_IMUX_B47_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_0" }, "PSS3.PSS0_IMUX_B47_1->PSS1_IMUX_B47_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_1" }, "PSS3.PSS0_IMUX_B47_10->PSS1_IMUX_B47_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_10" }, "PSS3.PSS0_IMUX_B47_11->PSS1_IMUX_B47_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_11" }, "PSS3.PSS0_IMUX_B47_12->PSS1_IMUX_B47_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_12" }, "PSS3.PSS0_IMUX_B47_13->PSS1_IMUX_B47_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_13" }, "PSS3.PSS0_IMUX_B47_14->PSS1_IMUX_B47_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_14" }, "PSS3.PSS0_IMUX_B47_15->PSS1_IMUX_B47_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_15" }, "PSS3.PSS0_IMUX_B47_16->PSS1_IMUX_B47_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_16" }, "PSS3.PSS0_IMUX_B47_17->PSS1_IMUX_B47_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_17" }, "PSS3.PSS0_IMUX_B47_18->PSS1_IMUX_B47_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_18" }, "PSS3.PSS0_IMUX_B47_19->PSS1_IMUX_B47_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_19" }, "PSS3.PSS0_IMUX_B47_2->PSS1_IMUX_B47_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_2" }, "PSS3.PSS0_IMUX_B47_3->PSS1_IMUX_B47_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_3" }, "PSS3.PSS0_IMUX_B47_4->PSS1_IMUX_B47_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_4" }, "PSS3.PSS0_IMUX_B47_5->PSS1_IMUX_B47_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_5" }, "PSS3.PSS0_IMUX_B47_6->PSS1_IMUX_B47_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_6" }, "PSS3.PSS0_IMUX_B47_7->PSS1_IMUX_B47_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_7" }, "PSS3.PSS0_IMUX_B47_8->PSS1_IMUX_B47_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_8" }, "PSS3.PSS0_IMUX_B47_9->PSS1_IMUX_B47_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B47_9" }, "PSS3.PSS0_IMUX_B4_0->PSS1_IMUX_B4_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_0" }, "PSS3.PSS0_IMUX_B4_1->PSS1_IMUX_B4_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_1" }, "PSS3.PSS0_IMUX_B4_10->PSS1_IMUX_B4_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_10" }, "PSS3.PSS0_IMUX_B4_11->PSS1_IMUX_B4_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_11" }, "PSS3.PSS0_IMUX_B4_12->PSS1_IMUX_B4_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_12" }, "PSS3.PSS0_IMUX_B4_13->PSS1_IMUX_B4_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_13" }, "PSS3.PSS0_IMUX_B4_14->PSS1_IMUX_B4_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_14" }, "PSS3.PSS0_IMUX_B4_15->PSS1_IMUX_B4_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_15" }, "PSS3.PSS0_IMUX_B4_16->PSS1_IMUX_B4_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_16" }, "PSS3.PSS0_IMUX_B4_17->PSS1_IMUX_B4_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_17" }, "PSS3.PSS0_IMUX_B4_18->PSS1_IMUX_B4_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_18" }, "PSS3.PSS0_IMUX_B4_19->PSS1_IMUX_B4_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_19" }, "PSS3.PSS0_IMUX_B4_2->PSS1_IMUX_B4_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_2" }, "PSS3.PSS0_IMUX_B4_3->PSS1_IMUX_B4_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_3" }, "PSS3.PSS0_IMUX_B4_4->PSS1_IMUX_B4_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_4" }, "PSS3.PSS0_IMUX_B4_5->PSS1_IMUX_B4_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_5" }, "PSS3.PSS0_IMUX_B4_6->PSS1_IMUX_B4_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_6" }, "PSS3.PSS0_IMUX_B4_7->PSS1_IMUX_B4_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_7" }, "PSS3.PSS0_IMUX_B4_8->PSS1_IMUX_B4_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_8" }, "PSS3.PSS0_IMUX_B4_9->PSS1_IMUX_B4_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B4_9" }, "PSS3.PSS0_IMUX_B5_0->PSS1_IMUX_B5_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_0" }, "PSS3.PSS0_IMUX_B5_1->PSS1_IMUX_B5_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_1" }, "PSS3.PSS0_IMUX_B5_10->PSS1_IMUX_B5_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_10" }, "PSS3.PSS0_IMUX_B5_11->PSS1_IMUX_B5_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_11" }, "PSS3.PSS0_IMUX_B5_12->PSS1_IMUX_B5_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_12" }, "PSS3.PSS0_IMUX_B5_13->PSS1_IMUX_B5_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_13" }, "PSS3.PSS0_IMUX_B5_14->PSS1_IMUX_B5_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_14" }, "PSS3.PSS0_IMUX_B5_15->PSS1_IMUX_B5_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_15" }, "PSS3.PSS0_IMUX_B5_16->PSS1_IMUX_B5_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_16" }, "PSS3.PSS0_IMUX_B5_17->PSS1_IMUX_B5_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_17" }, "PSS3.PSS0_IMUX_B5_18->PSS1_IMUX_B5_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_18" }, "PSS3.PSS0_IMUX_B5_19->PSS1_IMUX_B5_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_19" }, "PSS3.PSS0_IMUX_B5_2->PSS1_IMUX_B5_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_2" }, "PSS3.PSS0_IMUX_B5_3->PSS1_IMUX_B5_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_3" }, "PSS3.PSS0_IMUX_B5_4->PSS1_IMUX_B5_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_4" }, "PSS3.PSS0_IMUX_B5_5->PSS1_IMUX_B5_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_5" }, "PSS3.PSS0_IMUX_B5_6->PSS1_IMUX_B5_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_6" }, "PSS3.PSS0_IMUX_B5_7->PSS1_IMUX_B5_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_7" }, "PSS3.PSS0_IMUX_B5_8->PSS1_IMUX_B5_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_8" }, "PSS3.PSS0_IMUX_B5_9->PSS1_IMUX_B5_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B5_9" }, "PSS3.PSS0_IMUX_B6_0->PSS1_IMUX_B6_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_0" }, "PSS3.PSS0_IMUX_B6_1->PSS1_IMUX_B6_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_1" }, "PSS3.PSS0_IMUX_B6_10->PSS1_IMUX_B6_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_10" }, "PSS3.PSS0_IMUX_B6_11->PSS1_IMUX_B6_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_11" }, "PSS3.PSS0_IMUX_B6_12->PSS1_IMUX_B6_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_12" }, "PSS3.PSS0_IMUX_B6_13->PSS1_IMUX_B6_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_13" }, "PSS3.PSS0_IMUX_B6_14->PSS1_IMUX_B6_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_14" }, "PSS3.PSS0_IMUX_B6_15->PSS1_IMUX_B6_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_15" }, "PSS3.PSS0_IMUX_B6_16->PSS1_IMUX_B6_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_16" }, "PSS3.PSS0_IMUX_B6_17->PSS1_IMUX_B6_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_17" }, "PSS3.PSS0_IMUX_B6_18->PSS1_IMUX_B6_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_18" }, "PSS3.PSS0_IMUX_B6_19->PSS1_IMUX_B6_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_19" }, "PSS3.PSS0_IMUX_B6_2->PSS1_IMUX_B6_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_2" }, "PSS3.PSS0_IMUX_B6_3->PSS1_IMUX_B6_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_3" }, "PSS3.PSS0_IMUX_B6_4->PSS1_IMUX_B6_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_4" }, "PSS3.PSS0_IMUX_B6_5->PSS1_IMUX_B6_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_5" }, "PSS3.PSS0_IMUX_B6_6->PSS1_IMUX_B6_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_6" }, "PSS3.PSS0_IMUX_B6_7->PSS1_IMUX_B6_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_7" }, "PSS3.PSS0_IMUX_B6_8->PSS1_IMUX_B6_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_8" }, "PSS3.PSS0_IMUX_B6_9->PSS1_IMUX_B6_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B6_9" }, "PSS3.PSS0_IMUX_B7_0->PSS1_IMUX_B7_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_0" }, "PSS3.PSS0_IMUX_B7_1->PSS1_IMUX_B7_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_1" }, "PSS3.PSS0_IMUX_B7_10->PSS1_IMUX_B7_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_10" }, "PSS3.PSS0_IMUX_B7_11->PSS1_IMUX_B7_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_11" }, "PSS3.PSS0_IMUX_B7_12->PSS1_IMUX_B7_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_12" }, "PSS3.PSS0_IMUX_B7_13->PSS1_IMUX_B7_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_13" }, "PSS3.PSS0_IMUX_B7_14->PSS1_IMUX_B7_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_14" }, "PSS3.PSS0_IMUX_B7_15->PSS1_IMUX_B7_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_15" }, "PSS3.PSS0_IMUX_B7_16->PSS1_IMUX_B7_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_16" }, "PSS3.PSS0_IMUX_B7_17->PSS1_IMUX_B7_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_17" }, "PSS3.PSS0_IMUX_B7_18->PSS1_IMUX_B7_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_18" }, "PSS3.PSS0_IMUX_B7_19->PSS1_IMUX_B7_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_19" }, "PSS3.PSS0_IMUX_B7_2->PSS1_IMUX_B7_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_2" }, "PSS3.PSS0_IMUX_B7_3->PSS1_IMUX_B7_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_3" }, "PSS3.PSS0_IMUX_B7_4->PSS1_IMUX_B7_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_4" }, "PSS3.PSS0_IMUX_B7_5->PSS1_IMUX_B7_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_5" }, "PSS3.PSS0_IMUX_B7_6->PSS1_IMUX_B7_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_6" }, "PSS3.PSS0_IMUX_B7_7->PSS1_IMUX_B7_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_7" }, "PSS3.PSS0_IMUX_B7_8->PSS1_IMUX_B7_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_8" }, "PSS3.PSS0_IMUX_B7_9->PSS1_IMUX_B7_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B7_9" }, "PSS3.PSS0_IMUX_B8_0->PSS1_IMUX_B8_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_0" }, "PSS3.PSS0_IMUX_B8_1->PSS1_IMUX_B8_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_1" }, "PSS3.PSS0_IMUX_B8_10->PSS1_IMUX_B8_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_10" }, "PSS3.PSS0_IMUX_B8_11->PSS1_IMUX_B8_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_11" }, "PSS3.PSS0_IMUX_B8_12->PSS1_IMUX_B8_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_12" }, "PSS3.PSS0_IMUX_B8_13->PSS1_IMUX_B8_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_13" }, "PSS3.PSS0_IMUX_B8_14->PSS1_IMUX_B8_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_14" }, "PSS3.PSS0_IMUX_B8_15->PSS1_IMUX_B8_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_15" }, "PSS3.PSS0_IMUX_B8_16->PSS1_IMUX_B8_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_16" }, "PSS3.PSS0_IMUX_B8_17->PSS1_IMUX_B8_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_17" }, "PSS3.PSS0_IMUX_B8_18->PSS1_IMUX_B8_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_18" }, "PSS3.PSS0_IMUX_B8_19->PSS1_IMUX_B8_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_19" }, "PSS3.PSS0_IMUX_B8_2->PSS1_IMUX_B8_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_2" }, "PSS3.PSS0_IMUX_B8_3->PSS1_IMUX_B8_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_3" }, "PSS3.PSS0_IMUX_B8_4->PSS1_IMUX_B8_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_4" }, "PSS3.PSS0_IMUX_B8_5->PSS1_IMUX_B8_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_5" }, "PSS3.PSS0_IMUX_B8_6->PSS1_IMUX_B8_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_6" }, "PSS3.PSS0_IMUX_B8_7->PSS1_IMUX_B8_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_7" }, "PSS3.PSS0_IMUX_B8_8->PSS1_IMUX_B8_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_8" }, "PSS3.PSS0_IMUX_B8_9->PSS1_IMUX_B8_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B8_9" }, "PSS3.PSS0_IMUX_B9_0->PSS1_IMUX_B9_20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_0" }, "PSS3.PSS0_IMUX_B9_1->PSS1_IMUX_B9_21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_1" }, "PSS3.PSS0_IMUX_B9_10->PSS1_IMUX_B9_30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_10" }, "PSS3.PSS0_IMUX_B9_11->PSS1_IMUX_B9_31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_11" }, "PSS3.PSS0_IMUX_B9_12->PSS1_IMUX_B9_32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_12" }, "PSS3.PSS0_IMUX_B9_13->PSS1_IMUX_B9_33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_13" }, "PSS3.PSS0_IMUX_B9_14->PSS1_IMUX_B9_34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_14" }, "PSS3.PSS0_IMUX_B9_15->PSS1_IMUX_B9_35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_15" }, "PSS3.PSS0_IMUX_B9_16->PSS1_IMUX_B9_36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_16" }, "PSS3.PSS0_IMUX_B9_17->PSS1_IMUX_B9_37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_17" }, "PSS3.PSS0_IMUX_B9_18->PSS1_IMUX_B9_38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_18" }, "PSS3.PSS0_IMUX_B9_19->PSS1_IMUX_B9_39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_19" }, "PSS3.PSS0_IMUX_B9_2->PSS1_IMUX_B9_22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_2" }, "PSS3.PSS0_IMUX_B9_3->PSS1_IMUX_B9_23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_3" }, "PSS3.PSS0_IMUX_B9_4->PSS1_IMUX_B9_24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_4" }, "PSS3.PSS0_IMUX_B9_5->PSS1_IMUX_B9_25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_5" }, "PSS3.PSS0_IMUX_B9_6->PSS1_IMUX_B9_26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_6" }, "PSS3.PSS0_IMUX_B9_7->PSS1_IMUX_B9_27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_7" }, "PSS3.PSS0_IMUX_B9_8->PSS1_IMUX_B9_28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_8" }, "PSS3.PSS0_IMUX_B9_9->PSS1_IMUX_B9_29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_IMUX_B9_9" }, "PSS3.PSS1_LOGIC_OUTS0_0->PSS_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_0" }, "PSS3.PSS1_LOGIC_OUTS0_1->PSS_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_1" }, "PSS3.PSS1_LOGIC_OUTS0_10->PSS_LOGIC_OUTS0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_10" }, "PSS3.PSS1_LOGIC_OUTS0_11->PSS_LOGIC_OUTS0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_11" }, "PSS3.PSS1_LOGIC_OUTS0_12->PSS_LOGIC_OUTS0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_12" }, "PSS3.PSS1_LOGIC_OUTS0_13->PSS_LOGIC_OUTS0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_13" }, "PSS3.PSS1_LOGIC_OUTS0_14->PSS_LOGIC_OUTS0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_14" }, "PSS3.PSS1_LOGIC_OUTS0_15->PSS_LOGIC_OUTS0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_15" }, "PSS3.PSS1_LOGIC_OUTS0_16->PSS_LOGIC_OUTS0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_16" }, "PSS3.PSS1_LOGIC_OUTS0_17->PSS_LOGIC_OUTS0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_17" }, "PSS3.PSS1_LOGIC_OUTS0_18->PSS_LOGIC_OUTS0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_18" }, "PSS3.PSS1_LOGIC_OUTS0_19->PSS_LOGIC_OUTS0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_19" }, "PSS3.PSS1_LOGIC_OUTS0_2->PSS_LOGIC_OUTS0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_2" }, "PSS3.PSS1_LOGIC_OUTS0_20->PSS0_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_20" }, "PSS3.PSS1_LOGIC_OUTS0_21->PSS0_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_21" }, "PSS3.PSS1_LOGIC_OUTS0_22->PSS0_LOGIC_OUTS0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_22" }, "PSS3.PSS1_LOGIC_OUTS0_23->PSS0_LOGIC_OUTS0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_23" }, "PSS3.PSS1_LOGIC_OUTS0_24->PSS0_LOGIC_OUTS0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_24" }, "PSS3.PSS1_LOGIC_OUTS0_25->PSS0_LOGIC_OUTS0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_25" }, "PSS3.PSS1_LOGIC_OUTS0_26->PSS0_LOGIC_OUTS0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_26" }, "PSS3.PSS1_LOGIC_OUTS0_27->PSS0_LOGIC_OUTS0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_27" }, "PSS3.PSS1_LOGIC_OUTS0_28->PSS0_LOGIC_OUTS0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_28" }, "PSS3.PSS1_LOGIC_OUTS0_29->PSS0_LOGIC_OUTS0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_29" }, "PSS3.PSS1_LOGIC_OUTS0_3->PSS_LOGIC_OUTS0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_3" }, "PSS3.PSS1_LOGIC_OUTS0_30->PSS0_LOGIC_OUTS0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_30" }, "PSS3.PSS1_LOGIC_OUTS0_31->PSS0_LOGIC_OUTS0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_31" }, "PSS3.PSS1_LOGIC_OUTS0_32->PSS0_LOGIC_OUTS0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_32" }, "PSS3.PSS1_LOGIC_OUTS0_33->PSS0_LOGIC_OUTS0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_33" }, "PSS3.PSS1_LOGIC_OUTS0_34->PSS0_LOGIC_OUTS0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_34" }, "PSS3.PSS1_LOGIC_OUTS0_35->PSS0_LOGIC_OUTS0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_35" }, "PSS3.PSS1_LOGIC_OUTS0_36->PSS0_LOGIC_OUTS0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_36" }, "PSS3.PSS1_LOGIC_OUTS0_37->PSS0_LOGIC_OUTS0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_37" }, "PSS3.PSS1_LOGIC_OUTS0_38->PSS0_LOGIC_OUTS0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_38" }, "PSS3.PSS1_LOGIC_OUTS0_39->PSS0_LOGIC_OUTS0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_39" }, "PSS3.PSS1_LOGIC_OUTS0_4->PSS_LOGIC_OUTS0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_4" }, "PSS3.PSS1_LOGIC_OUTS0_5->PSS_LOGIC_OUTS0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_5" }, "PSS3.PSS1_LOGIC_OUTS0_6->PSS_LOGIC_OUTS0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_6" }, "PSS3.PSS1_LOGIC_OUTS0_7->PSS_LOGIC_OUTS0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_7" }, "PSS3.PSS1_LOGIC_OUTS0_8->PSS_LOGIC_OUTS0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_8" }, "PSS3.PSS1_LOGIC_OUTS0_9->PSS_LOGIC_OUTS0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS0_9" }, "PSS3.PSS1_LOGIC_OUTS10_0->PSS_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_0" }, "PSS3.PSS1_LOGIC_OUTS10_1->PSS_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_1" }, "PSS3.PSS1_LOGIC_OUTS10_10->PSS_LOGIC_OUTS10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_10" }, "PSS3.PSS1_LOGIC_OUTS10_11->PSS_LOGIC_OUTS10_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_11" }, "PSS3.PSS1_LOGIC_OUTS10_12->PSS_LOGIC_OUTS10_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_12" }, "PSS3.PSS1_LOGIC_OUTS10_13->PSS_LOGIC_OUTS10_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_13" }, "PSS3.PSS1_LOGIC_OUTS10_14->PSS_LOGIC_OUTS10_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_14" }, "PSS3.PSS1_LOGIC_OUTS10_15->PSS_LOGIC_OUTS10_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_15" }, "PSS3.PSS1_LOGIC_OUTS10_16->PSS_LOGIC_OUTS10_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_16" }, "PSS3.PSS1_LOGIC_OUTS10_17->PSS_LOGIC_OUTS10_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_17" }, "PSS3.PSS1_LOGIC_OUTS10_18->PSS_LOGIC_OUTS10_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_18" }, "PSS3.PSS1_LOGIC_OUTS10_19->PSS_LOGIC_OUTS10_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_19" }, "PSS3.PSS1_LOGIC_OUTS10_2->PSS_LOGIC_OUTS10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_2" }, "PSS3.PSS1_LOGIC_OUTS10_20->PSS0_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_20" }, "PSS3.PSS1_LOGIC_OUTS10_21->PSS0_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_21" }, "PSS3.PSS1_LOGIC_OUTS10_22->PSS0_LOGIC_OUTS10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_22" }, "PSS3.PSS1_LOGIC_OUTS10_23->PSS0_LOGIC_OUTS10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_23" }, "PSS3.PSS1_LOGIC_OUTS10_24->PSS0_LOGIC_OUTS10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_24" }, "PSS3.PSS1_LOGIC_OUTS10_25->PSS0_LOGIC_OUTS10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_25" }, "PSS3.PSS1_LOGIC_OUTS10_26->PSS0_LOGIC_OUTS10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_26" }, "PSS3.PSS1_LOGIC_OUTS10_27->PSS0_LOGIC_OUTS10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_27" }, "PSS3.PSS1_LOGIC_OUTS10_28->PSS0_LOGIC_OUTS10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_28" }, "PSS3.PSS1_LOGIC_OUTS10_29->PSS0_LOGIC_OUTS10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_29" }, "PSS3.PSS1_LOGIC_OUTS10_3->PSS_LOGIC_OUTS10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_3" }, "PSS3.PSS1_LOGIC_OUTS10_30->PSS0_LOGIC_OUTS10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_30" }, "PSS3.PSS1_LOGIC_OUTS10_31->PSS0_LOGIC_OUTS10_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_31" }, "PSS3.PSS1_LOGIC_OUTS10_32->PSS0_LOGIC_OUTS10_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_32" }, "PSS3.PSS1_LOGIC_OUTS10_33->PSS0_LOGIC_OUTS10_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_33" }, "PSS3.PSS1_LOGIC_OUTS10_34->PSS0_LOGIC_OUTS10_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_34" }, "PSS3.PSS1_LOGIC_OUTS10_35->PSS0_LOGIC_OUTS10_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_35" }, "PSS3.PSS1_LOGIC_OUTS10_36->PSS0_LOGIC_OUTS10_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_36" }, "PSS3.PSS1_LOGIC_OUTS10_37->PSS0_LOGIC_OUTS10_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_37" }, "PSS3.PSS1_LOGIC_OUTS10_38->PSS0_LOGIC_OUTS10_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_38" }, "PSS3.PSS1_LOGIC_OUTS10_39->PSS0_LOGIC_OUTS10_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS10_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_39" }, "PSS3.PSS1_LOGIC_OUTS10_4->PSS_LOGIC_OUTS10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_4" }, "PSS3.PSS1_LOGIC_OUTS10_5->PSS_LOGIC_OUTS10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_5" }, "PSS3.PSS1_LOGIC_OUTS10_6->PSS_LOGIC_OUTS10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_6" }, "PSS3.PSS1_LOGIC_OUTS10_7->PSS_LOGIC_OUTS10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_7" }, "PSS3.PSS1_LOGIC_OUTS10_8->PSS_LOGIC_OUTS10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_8" }, "PSS3.PSS1_LOGIC_OUTS10_9->PSS_LOGIC_OUTS10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS10_9" }, "PSS3.PSS1_LOGIC_OUTS11_0->PSS_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_0" }, "PSS3.PSS1_LOGIC_OUTS11_1->PSS_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_1" }, "PSS3.PSS1_LOGIC_OUTS11_10->PSS_LOGIC_OUTS11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_10" }, "PSS3.PSS1_LOGIC_OUTS11_11->PSS_LOGIC_OUTS11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_11" }, "PSS3.PSS1_LOGIC_OUTS11_12->PSS_LOGIC_OUTS11_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_12" }, "PSS3.PSS1_LOGIC_OUTS11_13->PSS_LOGIC_OUTS11_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_13" }, "PSS3.PSS1_LOGIC_OUTS11_14->PSS_LOGIC_OUTS11_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_14" }, "PSS3.PSS1_LOGIC_OUTS11_15->PSS_LOGIC_OUTS11_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_15" }, "PSS3.PSS1_LOGIC_OUTS11_16->PSS_LOGIC_OUTS11_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_16" }, "PSS3.PSS1_LOGIC_OUTS11_17->PSS_LOGIC_OUTS11_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_17" }, "PSS3.PSS1_LOGIC_OUTS11_18->PSS_LOGIC_OUTS11_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_18" }, "PSS3.PSS1_LOGIC_OUTS11_19->PSS_LOGIC_OUTS11_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_19" }, "PSS3.PSS1_LOGIC_OUTS11_2->PSS_LOGIC_OUTS11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_2" }, "PSS3.PSS1_LOGIC_OUTS11_20->PSS0_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_20" }, "PSS3.PSS1_LOGIC_OUTS11_21->PSS0_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_21" }, "PSS3.PSS1_LOGIC_OUTS11_22->PSS0_LOGIC_OUTS11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_22" }, "PSS3.PSS1_LOGIC_OUTS11_23->PSS0_LOGIC_OUTS11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_23" }, "PSS3.PSS1_LOGIC_OUTS11_24->PSS0_LOGIC_OUTS11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_24" }, "PSS3.PSS1_LOGIC_OUTS11_25->PSS0_LOGIC_OUTS11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_25" }, "PSS3.PSS1_LOGIC_OUTS11_26->PSS0_LOGIC_OUTS11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_26" }, "PSS3.PSS1_LOGIC_OUTS11_27->PSS0_LOGIC_OUTS11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_27" }, "PSS3.PSS1_LOGIC_OUTS11_28->PSS0_LOGIC_OUTS11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_28" }, "PSS3.PSS1_LOGIC_OUTS11_29->PSS0_LOGIC_OUTS11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_29" }, "PSS3.PSS1_LOGIC_OUTS11_3->PSS_LOGIC_OUTS11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_3" }, "PSS3.PSS1_LOGIC_OUTS11_30->PSS0_LOGIC_OUTS11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_30" }, "PSS3.PSS1_LOGIC_OUTS11_31->PSS0_LOGIC_OUTS11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_31" }, "PSS3.PSS1_LOGIC_OUTS11_32->PSS0_LOGIC_OUTS11_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_32" }, "PSS3.PSS1_LOGIC_OUTS11_33->PSS0_LOGIC_OUTS11_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_33" }, "PSS3.PSS1_LOGIC_OUTS11_34->PSS0_LOGIC_OUTS11_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_34" }, "PSS3.PSS1_LOGIC_OUTS11_35->PSS0_LOGIC_OUTS11_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_35" }, "PSS3.PSS1_LOGIC_OUTS11_36->PSS0_LOGIC_OUTS11_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_36" }, "PSS3.PSS1_LOGIC_OUTS11_37->PSS0_LOGIC_OUTS11_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_37" }, "PSS3.PSS1_LOGIC_OUTS11_38->PSS0_LOGIC_OUTS11_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_38" }, "PSS3.PSS1_LOGIC_OUTS11_39->PSS0_LOGIC_OUTS11_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS11_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_39" }, "PSS3.PSS1_LOGIC_OUTS11_4->PSS_LOGIC_OUTS11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_4" }, "PSS3.PSS1_LOGIC_OUTS11_5->PSS_LOGIC_OUTS11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_5" }, "PSS3.PSS1_LOGIC_OUTS11_6->PSS_LOGIC_OUTS11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_6" }, "PSS3.PSS1_LOGIC_OUTS11_7->PSS_LOGIC_OUTS11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_7" }, "PSS3.PSS1_LOGIC_OUTS11_8->PSS_LOGIC_OUTS11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_8" }, "PSS3.PSS1_LOGIC_OUTS11_9->PSS_LOGIC_OUTS11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS11_9" }, "PSS3.PSS1_LOGIC_OUTS12_0->PSS_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_0" }, "PSS3.PSS1_LOGIC_OUTS12_1->PSS_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_1" }, "PSS3.PSS1_LOGIC_OUTS12_10->PSS_LOGIC_OUTS12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_10" }, "PSS3.PSS1_LOGIC_OUTS12_11->PSS_LOGIC_OUTS12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_11" }, "PSS3.PSS1_LOGIC_OUTS12_12->PSS_LOGIC_OUTS12_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_12" }, "PSS3.PSS1_LOGIC_OUTS12_13->PSS_LOGIC_OUTS12_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_13" }, "PSS3.PSS1_LOGIC_OUTS12_14->PSS_LOGIC_OUTS12_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_14" }, "PSS3.PSS1_LOGIC_OUTS12_15->PSS_LOGIC_OUTS12_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_15" }, "PSS3.PSS1_LOGIC_OUTS12_16->PSS_LOGIC_OUTS12_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_16" }, "PSS3.PSS1_LOGIC_OUTS12_17->PSS_LOGIC_OUTS12_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_17" }, "PSS3.PSS1_LOGIC_OUTS12_18->PSS_LOGIC_OUTS12_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_18" }, "PSS3.PSS1_LOGIC_OUTS12_19->PSS_LOGIC_OUTS12_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_19" }, "PSS3.PSS1_LOGIC_OUTS12_2->PSS_LOGIC_OUTS12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_2" }, "PSS3.PSS1_LOGIC_OUTS12_20->PSS0_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_20" }, "PSS3.PSS1_LOGIC_OUTS12_21->PSS0_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_21" }, "PSS3.PSS1_LOGIC_OUTS12_22->PSS0_LOGIC_OUTS12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_22" }, "PSS3.PSS1_LOGIC_OUTS12_23->PSS0_LOGIC_OUTS12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_23" }, "PSS3.PSS1_LOGIC_OUTS12_24->PSS0_LOGIC_OUTS12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_24" }, "PSS3.PSS1_LOGIC_OUTS12_25->PSS0_LOGIC_OUTS12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_25" }, "PSS3.PSS1_LOGIC_OUTS12_26->PSS0_LOGIC_OUTS12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_26" }, "PSS3.PSS1_LOGIC_OUTS12_27->PSS0_LOGIC_OUTS12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_27" }, "PSS3.PSS1_LOGIC_OUTS12_28->PSS0_LOGIC_OUTS12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_28" }, "PSS3.PSS1_LOGIC_OUTS12_29->PSS0_LOGIC_OUTS12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_29" }, "PSS3.PSS1_LOGIC_OUTS12_3->PSS_LOGIC_OUTS12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_3" }, "PSS3.PSS1_LOGIC_OUTS12_30->PSS0_LOGIC_OUTS12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_30" }, "PSS3.PSS1_LOGIC_OUTS12_31->PSS0_LOGIC_OUTS12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_31" }, "PSS3.PSS1_LOGIC_OUTS12_32->PSS0_LOGIC_OUTS12_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_32" }, "PSS3.PSS1_LOGIC_OUTS12_33->PSS0_LOGIC_OUTS12_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_33" }, "PSS3.PSS1_LOGIC_OUTS12_34->PSS0_LOGIC_OUTS12_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_34" }, "PSS3.PSS1_LOGIC_OUTS12_35->PSS0_LOGIC_OUTS12_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_35" }, "PSS3.PSS1_LOGIC_OUTS12_36->PSS0_LOGIC_OUTS12_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_36" }, "PSS3.PSS1_LOGIC_OUTS12_37->PSS0_LOGIC_OUTS12_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_37" }, "PSS3.PSS1_LOGIC_OUTS12_38->PSS0_LOGIC_OUTS12_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_38" }, "PSS3.PSS1_LOGIC_OUTS12_39->PSS0_LOGIC_OUTS12_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS12_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_39" }, "PSS3.PSS1_LOGIC_OUTS12_4->PSS_LOGIC_OUTS12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_4" }, "PSS3.PSS1_LOGIC_OUTS12_5->PSS_LOGIC_OUTS12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_5" }, "PSS3.PSS1_LOGIC_OUTS12_6->PSS_LOGIC_OUTS12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_6" }, "PSS3.PSS1_LOGIC_OUTS12_7->PSS_LOGIC_OUTS12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_7" }, "PSS3.PSS1_LOGIC_OUTS12_8->PSS_LOGIC_OUTS12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_8" }, "PSS3.PSS1_LOGIC_OUTS12_9->PSS_LOGIC_OUTS12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS12_9" }, "PSS3.PSS1_LOGIC_OUTS13_0->PSS_LOGIC_OUTS13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_0" }, "PSS3.PSS1_LOGIC_OUTS13_1->PSS_LOGIC_OUTS13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_1" }, "PSS3.PSS1_LOGIC_OUTS13_10->PSS_LOGIC_OUTS13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_10" }, "PSS3.PSS1_LOGIC_OUTS13_11->PSS_LOGIC_OUTS13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_11" }, "PSS3.PSS1_LOGIC_OUTS13_12->PSS_LOGIC_OUTS13_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_12" }, "PSS3.PSS1_LOGIC_OUTS13_13->PSS_LOGIC_OUTS13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_13" }, "PSS3.PSS1_LOGIC_OUTS13_14->PSS_LOGIC_OUTS13_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_14" }, "PSS3.PSS1_LOGIC_OUTS13_15->PSS_LOGIC_OUTS13_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_15" }, "PSS3.PSS1_LOGIC_OUTS13_16->PSS_LOGIC_OUTS13_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_16" }, "PSS3.PSS1_LOGIC_OUTS13_17->PSS_LOGIC_OUTS13_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_17" }, "PSS3.PSS1_LOGIC_OUTS13_18->PSS_LOGIC_OUTS13_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_18" }, "PSS3.PSS1_LOGIC_OUTS13_19->PSS_LOGIC_OUTS13_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_19" }, "PSS3.PSS1_LOGIC_OUTS13_2->PSS_LOGIC_OUTS13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_2" }, "PSS3.PSS1_LOGIC_OUTS13_20->PSS0_LOGIC_OUTS13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_20" }, "PSS3.PSS1_LOGIC_OUTS13_21->PSS0_LOGIC_OUTS13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_21" }, "PSS3.PSS1_LOGIC_OUTS13_22->PSS0_LOGIC_OUTS13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_22" }, "PSS3.PSS1_LOGIC_OUTS13_23->PSS0_LOGIC_OUTS13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_23" }, "PSS3.PSS1_LOGIC_OUTS13_24->PSS0_LOGIC_OUTS13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_24" }, "PSS3.PSS1_LOGIC_OUTS13_25->PSS0_LOGIC_OUTS13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_25" }, "PSS3.PSS1_LOGIC_OUTS13_26->PSS0_LOGIC_OUTS13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_26" }, "PSS3.PSS1_LOGIC_OUTS13_27->PSS0_LOGIC_OUTS13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_27" }, "PSS3.PSS1_LOGIC_OUTS13_28->PSS0_LOGIC_OUTS13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_28" }, "PSS3.PSS1_LOGIC_OUTS13_29->PSS0_LOGIC_OUTS13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_29" }, "PSS3.PSS1_LOGIC_OUTS13_3->PSS_LOGIC_OUTS13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_3" }, "PSS3.PSS1_LOGIC_OUTS13_30->PSS0_LOGIC_OUTS13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_30" }, "PSS3.PSS1_LOGIC_OUTS13_31->PSS0_LOGIC_OUTS13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_31" }, "PSS3.PSS1_LOGIC_OUTS13_32->PSS0_LOGIC_OUTS13_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_32" }, "PSS3.PSS1_LOGIC_OUTS13_33->PSS0_LOGIC_OUTS13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_33" }, "PSS3.PSS1_LOGIC_OUTS13_34->PSS0_LOGIC_OUTS13_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_34" }, "PSS3.PSS1_LOGIC_OUTS13_35->PSS0_LOGIC_OUTS13_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_35" }, "PSS3.PSS1_LOGIC_OUTS13_36->PSS0_LOGIC_OUTS13_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_36" }, "PSS3.PSS1_LOGIC_OUTS13_37->PSS0_LOGIC_OUTS13_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_37" }, "PSS3.PSS1_LOGIC_OUTS13_38->PSS0_LOGIC_OUTS13_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_38" }, "PSS3.PSS1_LOGIC_OUTS13_39->PSS0_LOGIC_OUTS13_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS13_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_39" }, "PSS3.PSS1_LOGIC_OUTS13_4->PSS_LOGIC_OUTS13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_4" }, "PSS3.PSS1_LOGIC_OUTS13_5->PSS_LOGIC_OUTS13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_5" }, "PSS3.PSS1_LOGIC_OUTS13_6->PSS_LOGIC_OUTS13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_6" }, "PSS3.PSS1_LOGIC_OUTS13_7->PSS_LOGIC_OUTS13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_7" }, "PSS3.PSS1_LOGIC_OUTS13_8->PSS_LOGIC_OUTS13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_8" }, "PSS3.PSS1_LOGIC_OUTS13_9->PSS_LOGIC_OUTS13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS13_9" }, "PSS3.PSS1_LOGIC_OUTS14_0->PSS_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_0" }, "PSS3.PSS1_LOGIC_OUTS14_1->PSS_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_1" }, "PSS3.PSS1_LOGIC_OUTS14_10->PSS_LOGIC_OUTS14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_10" }, "PSS3.PSS1_LOGIC_OUTS14_11->PSS_LOGIC_OUTS14_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_11" }, "PSS3.PSS1_LOGIC_OUTS14_12->PSS_LOGIC_OUTS14_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_12" }, "PSS3.PSS1_LOGIC_OUTS14_13->PSS_LOGIC_OUTS14_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_13" }, "PSS3.PSS1_LOGIC_OUTS14_14->PSS_LOGIC_OUTS14_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_14" }, "PSS3.PSS1_LOGIC_OUTS14_15->PSS_LOGIC_OUTS14_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_15" }, "PSS3.PSS1_LOGIC_OUTS14_16->PSS_LOGIC_OUTS14_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_16" }, "PSS3.PSS1_LOGIC_OUTS14_17->PSS_LOGIC_OUTS14_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_17" }, "PSS3.PSS1_LOGIC_OUTS14_18->PSS_LOGIC_OUTS14_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_18" }, "PSS3.PSS1_LOGIC_OUTS14_19->PSS_LOGIC_OUTS14_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_19" }, "PSS3.PSS1_LOGIC_OUTS14_2->PSS_LOGIC_OUTS14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_2" }, "PSS3.PSS1_LOGIC_OUTS14_20->PSS0_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_20" }, "PSS3.PSS1_LOGIC_OUTS14_21->PSS0_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_21" }, "PSS3.PSS1_LOGIC_OUTS14_22->PSS0_LOGIC_OUTS14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_22" }, "PSS3.PSS1_LOGIC_OUTS14_23->PSS0_LOGIC_OUTS14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_23" }, "PSS3.PSS1_LOGIC_OUTS14_24->PSS0_LOGIC_OUTS14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_24" }, "PSS3.PSS1_LOGIC_OUTS14_25->PSS0_LOGIC_OUTS14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_25" }, "PSS3.PSS1_LOGIC_OUTS14_26->PSS0_LOGIC_OUTS14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_26" }, "PSS3.PSS1_LOGIC_OUTS14_27->PSS0_LOGIC_OUTS14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_27" }, "PSS3.PSS1_LOGIC_OUTS14_28->PSS0_LOGIC_OUTS14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_28" }, "PSS3.PSS1_LOGIC_OUTS14_29->PSS0_LOGIC_OUTS14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_29" }, "PSS3.PSS1_LOGIC_OUTS14_3->PSS_LOGIC_OUTS14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_3" }, "PSS3.PSS1_LOGIC_OUTS14_30->PSS0_LOGIC_OUTS14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_30" }, "PSS3.PSS1_LOGIC_OUTS14_31->PSS0_LOGIC_OUTS14_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_31" }, "PSS3.PSS1_LOGIC_OUTS14_32->PSS0_LOGIC_OUTS14_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_32" }, "PSS3.PSS1_LOGIC_OUTS14_33->PSS0_LOGIC_OUTS14_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_33" }, "PSS3.PSS1_LOGIC_OUTS14_34->PSS0_LOGIC_OUTS14_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_34" }, "PSS3.PSS1_LOGIC_OUTS14_35->PSS0_LOGIC_OUTS14_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_35" }, "PSS3.PSS1_LOGIC_OUTS14_36->PSS0_LOGIC_OUTS14_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_36" }, "PSS3.PSS1_LOGIC_OUTS14_37->PSS0_LOGIC_OUTS14_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_37" }, "PSS3.PSS1_LOGIC_OUTS14_38->PSS0_LOGIC_OUTS14_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_38" }, "PSS3.PSS1_LOGIC_OUTS14_39->PSS0_LOGIC_OUTS14_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS14_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_39" }, "PSS3.PSS1_LOGIC_OUTS14_4->PSS_LOGIC_OUTS14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_4" }, "PSS3.PSS1_LOGIC_OUTS14_5->PSS_LOGIC_OUTS14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_5" }, "PSS3.PSS1_LOGIC_OUTS14_6->PSS_LOGIC_OUTS14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_6" }, "PSS3.PSS1_LOGIC_OUTS14_7->PSS_LOGIC_OUTS14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_7" }, "PSS3.PSS1_LOGIC_OUTS14_8->PSS_LOGIC_OUTS14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_8" }, "PSS3.PSS1_LOGIC_OUTS14_9->PSS_LOGIC_OUTS14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS14_9" }, "PSS3.PSS1_LOGIC_OUTS15_0->PSS_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_0" }, "PSS3.PSS1_LOGIC_OUTS15_1->PSS_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_1" }, "PSS3.PSS1_LOGIC_OUTS15_10->PSS_LOGIC_OUTS15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_10" }, "PSS3.PSS1_LOGIC_OUTS15_11->PSS_LOGIC_OUTS15_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_11" }, "PSS3.PSS1_LOGIC_OUTS15_12->PSS_LOGIC_OUTS15_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_12" }, "PSS3.PSS1_LOGIC_OUTS15_13->PSS_LOGIC_OUTS15_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_13" }, "PSS3.PSS1_LOGIC_OUTS15_14->PSS_LOGIC_OUTS15_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_14" }, "PSS3.PSS1_LOGIC_OUTS15_15->PSS_LOGIC_OUTS15_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_15" }, "PSS3.PSS1_LOGIC_OUTS15_16->PSS_LOGIC_OUTS15_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_16" }, "PSS3.PSS1_LOGIC_OUTS15_17->PSS_LOGIC_OUTS15_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_17" }, "PSS3.PSS1_LOGIC_OUTS15_18->PSS_LOGIC_OUTS15_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_18" }, "PSS3.PSS1_LOGIC_OUTS15_19->PSS_LOGIC_OUTS15_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_19" }, "PSS3.PSS1_LOGIC_OUTS15_2->PSS_LOGIC_OUTS15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_2" }, "PSS3.PSS1_LOGIC_OUTS15_20->PSS0_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_20" }, "PSS3.PSS1_LOGIC_OUTS15_21->PSS0_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_21" }, "PSS3.PSS1_LOGIC_OUTS15_22->PSS0_LOGIC_OUTS15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_22" }, "PSS3.PSS1_LOGIC_OUTS15_23->PSS0_LOGIC_OUTS15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_23" }, "PSS3.PSS1_LOGIC_OUTS15_24->PSS0_LOGIC_OUTS15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_24" }, "PSS3.PSS1_LOGIC_OUTS15_25->PSS0_LOGIC_OUTS15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_25" }, "PSS3.PSS1_LOGIC_OUTS15_26->PSS0_LOGIC_OUTS15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_26" }, "PSS3.PSS1_LOGIC_OUTS15_27->PSS0_LOGIC_OUTS15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_27" }, "PSS3.PSS1_LOGIC_OUTS15_28->PSS0_LOGIC_OUTS15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_28" }, "PSS3.PSS1_LOGIC_OUTS15_29->PSS0_LOGIC_OUTS15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_29" }, "PSS3.PSS1_LOGIC_OUTS15_3->PSS_LOGIC_OUTS15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_3" }, "PSS3.PSS1_LOGIC_OUTS15_30->PSS0_LOGIC_OUTS15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_30" }, "PSS3.PSS1_LOGIC_OUTS15_31->PSS0_LOGIC_OUTS15_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_31" }, "PSS3.PSS1_LOGIC_OUTS15_32->PSS0_LOGIC_OUTS15_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_32" }, "PSS3.PSS1_LOGIC_OUTS15_33->PSS0_LOGIC_OUTS15_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_33" }, "PSS3.PSS1_LOGIC_OUTS15_34->PSS0_LOGIC_OUTS15_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_34" }, "PSS3.PSS1_LOGIC_OUTS15_35->PSS0_LOGIC_OUTS15_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_35" }, "PSS3.PSS1_LOGIC_OUTS15_36->PSS0_LOGIC_OUTS15_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_36" }, "PSS3.PSS1_LOGIC_OUTS15_37->PSS0_LOGIC_OUTS15_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_37" }, "PSS3.PSS1_LOGIC_OUTS15_38->PSS0_LOGIC_OUTS15_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_38" }, "PSS3.PSS1_LOGIC_OUTS15_39->PSS0_LOGIC_OUTS15_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS15_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_39" }, "PSS3.PSS1_LOGIC_OUTS15_4->PSS_LOGIC_OUTS15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_4" }, "PSS3.PSS1_LOGIC_OUTS15_5->PSS_LOGIC_OUTS15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_5" }, "PSS3.PSS1_LOGIC_OUTS15_6->PSS_LOGIC_OUTS15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_6" }, "PSS3.PSS1_LOGIC_OUTS15_7->PSS_LOGIC_OUTS15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_7" }, "PSS3.PSS1_LOGIC_OUTS15_8->PSS_LOGIC_OUTS15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_8" }, "PSS3.PSS1_LOGIC_OUTS15_9->PSS_LOGIC_OUTS15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS15_9" }, "PSS3.PSS1_LOGIC_OUTS16_0->PSS_LOGIC_OUTS16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_0" }, "PSS3.PSS1_LOGIC_OUTS16_1->PSS_LOGIC_OUTS16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_1" }, "PSS3.PSS1_LOGIC_OUTS16_10->PSS_LOGIC_OUTS16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_10" }, "PSS3.PSS1_LOGIC_OUTS16_11->PSS_LOGIC_OUTS16_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_11" }, "PSS3.PSS1_LOGIC_OUTS16_12->PSS_LOGIC_OUTS16_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_12" }, "PSS3.PSS1_LOGIC_OUTS16_13->PSS_LOGIC_OUTS16_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_13" }, "PSS3.PSS1_LOGIC_OUTS16_14->PSS_LOGIC_OUTS16_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_14" }, "PSS3.PSS1_LOGIC_OUTS16_15->PSS_LOGIC_OUTS16_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_15" }, "PSS3.PSS1_LOGIC_OUTS16_16->PSS_LOGIC_OUTS16_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_16" }, "PSS3.PSS1_LOGIC_OUTS16_17->PSS_LOGIC_OUTS16_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_17" }, "PSS3.PSS1_LOGIC_OUTS16_18->PSS_LOGIC_OUTS16_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_18" }, "PSS3.PSS1_LOGIC_OUTS16_19->PSS_LOGIC_OUTS16_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_19" }, "PSS3.PSS1_LOGIC_OUTS16_2->PSS_LOGIC_OUTS16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_2" }, "PSS3.PSS1_LOGIC_OUTS16_20->PSS0_LOGIC_OUTS16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_20" }, "PSS3.PSS1_LOGIC_OUTS16_21->PSS0_LOGIC_OUTS16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_21" }, "PSS3.PSS1_LOGIC_OUTS16_22->PSS0_LOGIC_OUTS16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_22" }, "PSS3.PSS1_LOGIC_OUTS16_23->PSS0_LOGIC_OUTS16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_23" }, "PSS3.PSS1_LOGIC_OUTS16_24->PSS0_LOGIC_OUTS16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_24" }, "PSS3.PSS1_LOGIC_OUTS16_25->PSS0_LOGIC_OUTS16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_25" }, "PSS3.PSS1_LOGIC_OUTS16_26->PSS0_LOGIC_OUTS16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_26" }, "PSS3.PSS1_LOGIC_OUTS16_27->PSS0_LOGIC_OUTS16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_27" }, "PSS3.PSS1_LOGIC_OUTS16_28->PSS0_LOGIC_OUTS16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_28" }, "PSS3.PSS1_LOGIC_OUTS16_29->PSS0_LOGIC_OUTS16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_29" }, "PSS3.PSS1_LOGIC_OUTS16_3->PSS_LOGIC_OUTS16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_3" }, "PSS3.PSS1_LOGIC_OUTS16_30->PSS0_LOGIC_OUTS16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_30" }, "PSS3.PSS1_LOGIC_OUTS16_31->PSS0_LOGIC_OUTS16_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_31" }, "PSS3.PSS1_LOGIC_OUTS16_32->PSS0_LOGIC_OUTS16_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_32" }, "PSS3.PSS1_LOGIC_OUTS16_33->PSS0_LOGIC_OUTS16_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_33" }, "PSS3.PSS1_LOGIC_OUTS16_34->PSS0_LOGIC_OUTS16_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_34" }, "PSS3.PSS1_LOGIC_OUTS16_35->PSS0_LOGIC_OUTS16_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_35" }, "PSS3.PSS1_LOGIC_OUTS16_36->PSS0_LOGIC_OUTS16_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_36" }, "PSS3.PSS1_LOGIC_OUTS16_37->PSS0_LOGIC_OUTS16_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_37" }, "PSS3.PSS1_LOGIC_OUTS16_38->PSS0_LOGIC_OUTS16_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_38" }, "PSS3.PSS1_LOGIC_OUTS16_39->PSS0_LOGIC_OUTS16_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS16_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_39" }, "PSS3.PSS1_LOGIC_OUTS16_4->PSS_LOGIC_OUTS16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_4" }, "PSS3.PSS1_LOGIC_OUTS16_5->PSS_LOGIC_OUTS16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_5" }, "PSS3.PSS1_LOGIC_OUTS16_6->PSS_LOGIC_OUTS16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_6" }, "PSS3.PSS1_LOGIC_OUTS16_7->PSS_LOGIC_OUTS16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_7" }, "PSS3.PSS1_LOGIC_OUTS16_8->PSS_LOGIC_OUTS16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_8" }, "PSS3.PSS1_LOGIC_OUTS16_9->PSS_LOGIC_OUTS16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS16_9" }, "PSS3.PSS1_LOGIC_OUTS17_0->PSS_LOGIC_OUTS17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_0" }, "PSS3.PSS1_LOGIC_OUTS17_1->PSS_LOGIC_OUTS17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_1" }, "PSS3.PSS1_LOGIC_OUTS17_10->PSS_LOGIC_OUTS17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_10" }, "PSS3.PSS1_LOGIC_OUTS17_11->PSS_LOGIC_OUTS17_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_11" }, "PSS3.PSS1_LOGIC_OUTS17_12->PSS_LOGIC_OUTS17_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_12" }, "PSS3.PSS1_LOGIC_OUTS17_13->PSS_LOGIC_OUTS17_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_13" }, "PSS3.PSS1_LOGIC_OUTS17_14->PSS_LOGIC_OUTS17_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_14" }, "PSS3.PSS1_LOGIC_OUTS17_15->PSS_LOGIC_OUTS17_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_15" }, "PSS3.PSS1_LOGIC_OUTS17_16->PSS_LOGIC_OUTS17_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_16" }, "PSS3.PSS1_LOGIC_OUTS17_17->PSS_LOGIC_OUTS17_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_17" }, "PSS3.PSS1_LOGIC_OUTS17_18->PSS_LOGIC_OUTS17_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_18" }, "PSS3.PSS1_LOGIC_OUTS17_19->PSS_LOGIC_OUTS17_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_19" }, "PSS3.PSS1_LOGIC_OUTS17_2->PSS_LOGIC_OUTS17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_2" }, "PSS3.PSS1_LOGIC_OUTS17_20->PSS0_LOGIC_OUTS17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_20" }, "PSS3.PSS1_LOGIC_OUTS17_21->PSS0_LOGIC_OUTS17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_21" }, "PSS3.PSS1_LOGIC_OUTS17_22->PSS0_LOGIC_OUTS17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_22" }, "PSS3.PSS1_LOGIC_OUTS17_23->PSS0_LOGIC_OUTS17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_23" }, "PSS3.PSS1_LOGIC_OUTS17_24->PSS0_LOGIC_OUTS17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_24" }, "PSS3.PSS1_LOGIC_OUTS17_25->PSS0_LOGIC_OUTS17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_25" }, "PSS3.PSS1_LOGIC_OUTS17_26->PSS0_LOGIC_OUTS17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_26" }, "PSS3.PSS1_LOGIC_OUTS17_27->PSS0_LOGIC_OUTS17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_27" }, "PSS3.PSS1_LOGIC_OUTS17_28->PSS0_LOGIC_OUTS17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_28" }, "PSS3.PSS1_LOGIC_OUTS17_29->PSS0_LOGIC_OUTS17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_29" }, "PSS3.PSS1_LOGIC_OUTS17_3->PSS_LOGIC_OUTS17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_3" }, "PSS3.PSS1_LOGIC_OUTS17_30->PSS0_LOGIC_OUTS17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_30" }, "PSS3.PSS1_LOGIC_OUTS17_31->PSS0_LOGIC_OUTS17_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_31" }, "PSS3.PSS1_LOGIC_OUTS17_32->PSS0_LOGIC_OUTS17_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_32" }, "PSS3.PSS1_LOGIC_OUTS17_33->PSS0_LOGIC_OUTS17_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_33" }, "PSS3.PSS1_LOGIC_OUTS17_34->PSS0_LOGIC_OUTS17_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_34" }, "PSS3.PSS1_LOGIC_OUTS17_35->PSS0_LOGIC_OUTS17_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_35" }, "PSS3.PSS1_LOGIC_OUTS17_36->PSS0_LOGIC_OUTS17_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_36" }, "PSS3.PSS1_LOGIC_OUTS17_37->PSS0_LOGIC_OUTS17_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_37" }, "PSS3.PSS1_LOGIC_OUTS17_38->PSS0_LOGIC_OUTS17_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_38" }, "PSS3.PSS1_LOGIC_OUTS17_39->PSS0_LOGIC_OUTS17_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS17_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_39" }, "PSS3.PSS1_LOGIC_OUTS17_4->PSS_LOGIC_OUTS17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_4" }, "PSS3.PSS1_LOGIC_OUTS17_5->PSS_LOGIC_OUTS17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_5" }, "PSS3.PSS1_LOGIC_OUTS17_6->PSS_LOGIC_OUTS17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_6" }, "PSS3.PSS1_LOGIC_OUTS17_7->PSS_LOGIC_OUTS17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_7" }, "PSS3.PSS1_LOGIC_OUTS17_8->PSS_LOGIC_OUTS17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_8" }, "PSS3.PSS1_LOGIC_OUTS17_9->PSS_LOGIC_OUTS17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS17_9" }, "PSS3.PSS1_LOGIC_OUTS18_0->PSS_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_0" }, "PSS3.PSS1_LOGIC_OUTS18_1->PSS_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_1" }, "PSS3.PSS1_LOGIC_OUTS18_10->PSS_LOGIC_OUTS18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_10" }, "PSS3.PSS1_LOGIC_OUTS18_11->PSS_LOGIC_OUTS18_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_11" }, "PSS3.PSS1_LOGIC_OUTS18_12->PSS_LOGIC_OUTS18_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_12" }, "PSS3.PSS1_LOGIC_OUTS18_13->PSS_LOGIC_OUTS18_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_13" }, "PSS3.PSS1_LOGIC_OUTS18_14->PSS_LOGIC_OUTS18_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_14" }, "PSS3.PSS1_LOGIC_OUTS18_15->PSS_LOGIC_OUTS18_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_15" }, "PSS3.PSS1_LOGIC_OUTS18_16->PSS_LOGIC_OUTS18_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_16" }, "PSS3.PSS1_LOGIC_OUTS18_17->PSS_LOGIC_OUTS18_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_17" }, "PSS3.PSS1_LOGIC_OUTS18_18->PSS_LOGIC_OUTS18_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_18" }, "PSS3.PSS1_LOGIC_OUTS18_19->PSS_LOGIC_OUTS18_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_19" }, "PSS3.PSS1_LOGIC_OUTS18_2->PSS_LOGIC_OUTS18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_2" }, "PSS3.PSS1_LOGIC_OUTS18_20->PSS0_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_20" }, "PSS3.PSS1_LOGIC_OUTS18_21->PSS0_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_21" }, "PSS3.PSS1_LOGIC_OUTS18_22->PSS0_LOGIC_OUTS18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_22" }, "PSS3.PSS1_LOGIC_OUTS18_23->PSS0_LOGIC_OUTS18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_23" }, "PSS3.PSS1_LOGIC_OUTS18_24->PSS0_LOGIC_OUTS18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_24" }, "PSS3.PSS1_LOGIC_OUTS18_25->PSS0_LOGIC_OUTS18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_25" }, "PSS3.PSS1_LOGIC_OUTS18_26->PSS0_LOGIC_OUTS18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_26" }, "PSS3.PSS1_LOGIC_OUTS18_27->PSS0_LOGIC_OUTS18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_27" }, "PSS3.PSS1_LOGIC_OUTS18_28->PSS0_LOGIC_OUTS18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_28" }, "PSS3.PSS1_LOGIC_OUTS18_29->PSS0_LOGIC_OUTS18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_29" }, "PSS3.PSS1_LOGIC_OUTS18_3->PSS_LOGIC_OUTS18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_3" }, "PSS3.PSS1_LOGIC_OUTS18_30->PSS0_LOGIC_OUTS18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_30" }, "PSS3.PSS1_LOGIC_OUTS18_31->PSS0_LOGIC_OUTS18_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_31" }, "PSS3.PSS1_LOGIC_OUTS18_32->PSS0_LOGIC_OUTS18_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_32" }, "PSS3.PSS1_LOGIC_OUTS18_33->PSS0_LOGIC_OUTS18_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_33" }, "PSS3.PSS1_LOGIC_OUTS18_34->PSS0_LOGIC_OUTS18_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_34" }, "PSS3.PSS1_LOGIC_OUTS18_35->PSS0_LOGIC_OUTS18_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_35" }, "PSS3.PSS1_LOGIC_OUTS18_36->PSS0_LOGIC_OUTS18_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_36" }, "PSS3.PSS1_LOGIC_OUTS18_37->PSS0_LOGIC_OUTS18_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_37" }, "PSS3.PSS1_LOGIC_OUTS18_38->PSS0_LOGIC_OUTS18_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_38" }, "PSS3.PSS1_LOGIC_OUTS18_39->PSS0_LOGIC_OUTS18_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS18_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_39" }, "PSS3.PSS1_LOGIC_OUTS18_4->PSS_LOGIC_OUTS18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_4" }, "PSS3.PSS1_LOGIC_OUTS18_5->PSS_LOGIC_OUTS18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_5" }, "PSS3.PSS1_LOGIC_OUTS18_6->PSS_LOGIC_OUTS18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_6" }, "PSS3.PSS1_LOGIC_OUTS18_7->PSS_LOGIC_OUTS18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_7" }, "PSS3.PSS1_LOGIC_OUTS18_8->PSS_LOGIC_OUTS18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_8" }, "PSS3.PSS1_LOGIC_OUTS18_9->PSS_LOGIC_OUTS18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS18_9" }, "PSS3.PSS1_LOGIC_OUTS19_0->PSS_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_0" }, "PSS3.PSS1_LOGIC_OUTS19_1->PSS_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_1" }, "PSS3.PSS1_LOGIC_OUTS19_10->PSS_LOGIC_OUTS19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_10" }, "PSS3.PSS1_LOGIC_OUTS19_11->PSS_LOGIC_OUTS19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_11" }, "PSS3.PSS1_LOGIC_OUTS19_12->PSS_LOGIC_OUTS19_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_12" }, "PSS3.PSS1_LOGIC_OUTS19_13->PSS_LOGIC_OUTS19_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_13" }, "PSS3.PSS1_LOGIC_OUTS19_14->PSS_LOGIC_OUTS19_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_14" }, "PSS3.PSS1_LOGIC_OUTS19_15->PSS_LOGIC_OUTS19_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_15" }, "PSS3.PSS1_LOGIC_OUTS19_16->PSS_LOGIC_OUTS19_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_16" }, "PSS3.PSS1_LOGIC_OUTS19_17->PSS_LOGIC_OUTS19_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_17" }, "PSS3.PSS1_LOGIC_OUTS19_18->PSS_LOGIC_OUTS19_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_18" }, "PSS3.PSS1_LOGIC_OUTS19_19->PSS_LOGIC_OUTS19_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_19" }, "PSS3.PSS1_LOGIC_OUTS19_2->PSS_LOGIC_OUTS19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_2" }, "PSS3.PSS1_LOGIC_OUTS19_20->PSS0_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_20" }, "PSS3.PSS1_LOGIC_OUTS19_21->PSS0_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_21" }, "PSS3.PSS1_LOGIC_OUTS19_22->PSS0_LOGIC_OUTS19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_22" }, "PSS3.PSS1_LOGIC_OUTS19_23->PSS0_LOGIC_OUTS19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_23" }, "PSS3.PSS1_LOGIC_OUTS19_24->PSS0_LOGIC_OUTS19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_24" }, "PSS3.PSS1_LOGIC_OUTS19_25->PSS0_LOGIC_OUTS19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_25" }, "PSS3.PSS1_LOGIC_OUTS19_26->PSS0_LOGIC_OUTS19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_26" }, "PSS3.PSS1_LOGIC_OUTS19_27->PSS0_LOGIC_OUTS19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_27" }, "PSS3.PSS1_LOGIC_OUTS19_28->PSS0_LOGIC_OUTS19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_28" }, "PSS3.PSS1_LOGIC_OUTS19_29->PSS0_LOGIC_OUTS19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_29" }, "PSS3.PSS1_LOGIC_OUTS19_3->PSS_LOGIC_OUTS19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_3" }, "PSS3.PSS1_LOGIC_OUTS19_30->PSS0_LOGIC_OUTS19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_30" }, "PSS3.PSS1_LOGIC_OUTS19_31->PSS0_LOGIC_OUTS19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_31" }, "PSS3.PSS1_LOGIC_OUTS19_32->PSS0_LOGIC_OUTS19_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_32" }, "PSS3.PSS1_LOGIC_OUTS19_33->PSS0_LOGIC_OUTS19_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_33" }, "PSS3.PSS1_LOGIC_OUTS19_34->PSS0_LOGIC_OUTS19_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_34" }, "PSS3.PSS1_LOGIC_OUTS19_35->PSS0_LOGIC_OUTS19_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_35" }, "PSS3.PSS1_LOGIC_OUTS19_36->PSS0_LOGIC_OUTS19_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_36" }, "PSS3.PSS1_LOGIC_OUTS19_37->PSS0_LOGIC_OUTS19_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_37" }, "PSS3.PSS1_LOGIC_OUTS19_38->PSS0_LOGIC_OUTS19_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_38" }, "PSS3.PSS1_LOGIC_OUTS19_39->PSS0_LOGIC_OUTS19_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS19_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_39" }, "PSS3.PSS1_LOGIC_OUTS19_4->PSS_LOGIC_OUTS19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_4" }, "PSS3.PSS1_LOGIC_OUTS19_5->PSS_LOGIC_OUTS19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_5" }, "PSS3.PSS1_LOGIC_OUTS19_6->PSS_LOGIC_OUTS19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_6" }, "PSS3.PSS1_LOGIC_OUTS19_7->PSS_LOGIC_OUTS19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_7" }, "PSS3.PSS1_LOGIC_OUTS19_8->PSS_LOGIC_OUTS19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_8" }, "PSS3.PSS1_LOGIC_OUTS19_9->PSS_LOGIC_OUTS19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS19_9" }, "PSS3.PSS1_LOGIC_OUTS1_0->PSS_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_0" }, "PSS3.PSS1_LOGIC_OUTS1_1->PSS_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_1" }, "PSS3.PSS1_LOGIC_OUTS1_10->PSS_LOGIC_OUTS1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_10" }, "PSS3.PSS1_LOGIC_OUTS1_11->PSS_LOGIC_OUTS1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_11" }, "PSS3.PSS1_LOGIC_OUTS1_12->PSS_LOGIC_OUTS1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_12" }, "PSS3.PSS1_LOGIC_OUTS1_13->PSS_LOGIC_OUTS1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_13" }, "PSS3.PSS1_LOGIC_OUTS1_14->PSS_LOGIC_OUTS1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_14" }, "PSS3.PSS1_LOGIC_OUTS1_15->PSS_LOGIC_OUTS1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_15" }, "PSS3.PSS1_LOGIC_OUTS1_16->PSS_LOGIC_OUTS1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_16" }, "PSS3.PSS1_LOGIC_OUTS1_17->PSS_LOGIC_OUTS1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_17" }, "PSS3.PSS1_LOGIC_OUTS1_18->PSS_LOGIC_OUTS1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_18" }, "PSS3.PSS1_LOGIC_OUTS1_19->PSS_LOGIC_OUTS1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_19" }, "PSS3.PSS1_LOGIC_OUTS1_2->PSS_LOGIC_OUTS1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_2" }, "PSS3.PSS1_LOGIC_OUTS1_20->PSS0_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_20" }, "PSS3.PSS1_LOGIC_OUTS1_21->PSS0_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_21" }, "PSS3.PSS1_LOGIC_OUTS1_22->PSS0_LOGIC_OUTS1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_22" }, "PSS3.PSS1_LOGIC_OUTS1_23->PSS0_LOGIC_OUTS1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_23" }, "PSS3.PSS1_LOGIC_OUTS1_24->PSS0_LOGIC_OUTS1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_24" }, "PSS3.PSS1_LOGIC_OUTS1_25->PSS0_LOGIC_OUTS1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_25" }, "PSS3.PSS1_LOGIC_OUTS1_26->PSS0_LOGIC_OUTS1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_26" }, "PSS3.PSS1_LOGIC_OUTS1_27->PSS0_LOGIC_OUTS1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_27" }, "PSS3.PSS1_LOGIC_OUTS1_28->PSS0_LOGIC_OUTS1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_28" }, "PSS3.PSS1_LOGIC_OUTS1_29->PSS0_LOGIC_OUTS1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_29" }, "PSS3.PSS1_LOGIC_OUTS1_3->PSS_LOGIC_OUTS1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_3" }, "PSS3.PSS1_LOGIC_OUTS1_30->PSS0_LOGIC_OUTS1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_30" }, "PSS3.PSS1_LOGIC_OUTS1_31->PSS0_LOGIC_OUTS1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_31" }, "PSS3.PSS1_LOGIC_OUTS1_32->PSS0_LOGIC_OUTS1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_32" }, "PSS3.PSS1_LOGIC_OUTS1_33->PSS0_LOGIC_OUTS1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_33" }, "PSS3.PSS1_LOGIC_OUTS1_34->PSS0_LOGIC_OUTS1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_34" }, "PSS3.PSS1_LOGIC_OUTS1_35->PSS0_LOGIC_OUTS1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_35" }, "PSS3.PSS1_LOGIC_OUTS1_36->PSS0_LOGIC_OUTS1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_36" }, "PSS3.PSS1_LOGIC_OUTS1_37->PSS0_LOGIC_OUTS1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_37" }, "PSS3.PSS1_LOGIC_OUTS1_38->PSS0_LOGIC_OUTS1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_38" }, "PSS3.PSS1_LOGIC_OUTS1_39->PSS0_LOGIC_OUTS1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_39" }, "PSS3.PSS1_LOGIC_OUTS1_4->PSS_LOGIC_OUTS1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_4" }, "PSS3.PSS1_LOGIC_OUTS1_5->PSS_LOGIC_OUTS1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_5" }, "PSS3.PSS1_LOGIC_OUTS1_6->PSS_LOGIC_OUTS1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_6" }, "PSS3.PSS1_LOGIC_OUTS1_7->PSS_LOGIC_OUTS1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_7" }, "PSS3.PSS1_LOGIC_OUTS1_8->PSS_LOGIC_OUTS1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_8" }, "PSS3.PSS1_LOGIC_OUTS1_9->PSS_LOGIC_OUTS1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS1_9" }, "PSS3.PSS1_LOGIC_OUTS20_0->PSS_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_0" }, "PSS3.PSS1_LOGIC_OUTS20_1->PSS_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_1" }, "PSS3.PSS1_LOGIC_OUTS20_10->PSS_LOGIC_OUTS20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_10" }, "PSS3.PSS1_LOGIC_OUTS20_11->PSS_LOGIC_OUTS20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_11" }, "PSS3.PSS1_LOGIC_OUTS20_12->PSS_LOGIC_OUTS20_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_12" }, "PSS3.PSS1_LOGIC_OUTS20_13->PSS_LOGIC_OUTS20_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_13" }, "PSS3.PSS1_LOGIC_OUTS20_14->PSS_LOGIC_OUTS20_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_14" }, "PSS3.PSS1_LOGIC_OUTS20_15->PSS_LOGIC_OUTS20_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_15" }, "PSS3.PSS1_LOGIC_OUTS20_16->PSS_LOGIC_OUTS20_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_16" }, "PSS3.PSS1_LOGIC_OUTS20_17->PSS_LOGIC_OUTS20_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_17" }, "PSS3.PSS1_LOGIC_OUTS20_18->PSS_LOGIC_OUTS20_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_18" }, "PSS3.PSS1_LOGIC_OUTS20_19->PSS_LOGIC_OUTS20_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_19" }, "PSS3.PSS1_LOGIC_OUTS20_2->PSS_LOGIC_OUTS20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_2" }, "PSS3.PSS1_LOGIC_OUTS20_20->PSS0_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_20" }, "PSS3.PSS1_LOGIC_OUTS20_21->PSS0_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_21" }, "PSS3.PSS1_LOGIC_OUTS20_22->PSS0_LOGIC_OUTS20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_22" }, "PSS3.PSS1_LOGIC_OUTS20_23->PSS0_LOGIC_OUTS20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_23" }, "PSS3.PSS1_LOGIC_OUTS20_24->PSS0_LOGIC_OUTS20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_24" }, "PSS3.PSS1_LOGIC_OUTS20_25->PSS0_LOGIC_OUTS20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_25" }, "PSS3.PSS1_LOGIC_OUTS20_26->PSS0_LOGIC_OUTS20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_26" }, "PSS3.PSS1_LOGIC_OUTS20_27->PSS0_LOGIC_OUTS20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_27" }, "PSS3.PSS1_LOGIC_OUTS20_28->PSS0_LOGIC_OUTS20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_28" }, "PSS3.PSS1_LOGIC_OUTS20_29->PSS0_LOGIC_OUTS20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_29" }, "PSS3.PSS1_LOGIC_OUTS20_3->PSS_LOGIC_OUTS20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_3" }, "PSS3.PSS1_LOGIC_OUTS20_30->PSS0_LOGIC_OUTS20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_30" }, "PSS3.PSS1_LOGIC_OUTS20_31->PSS0_LOGIC_OUTS20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_31" }, "PSS3.PSS1_LOGIC_OUTS20_32->PSS0_LOGIC_OUTS20_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_32" }, "PSS3.PSS1_LOGIC_OUTS20_33->PSS0_LOGIC_OUTS20_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_33" }, "PSS3.PSS1_LOGIC_OUTS20_34->PSS0_LOGIC_OUTS20_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_34" }, "PSS3.PSS1_LOGIC_OUTS20_35->PSS0_LOGIC_OUTS20_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_35" }, "PSS3.PSS1_LOGIC_OUTS20_36->PSS0_LOGIC_OUTS20_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_36" }, "PSS3.PSS1_LOGIC_OUTS20_37->PSS0_LOGIC_OUTS20_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_37" }, "PSS3.PSS1_LOGIC_OUTS20_38->PSS0_LOGIC_OUTS20_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_38" }, "PSS3.PSS1_LOGIC_OUTS20_39->PSS0_LOGIC_OUTS20_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS20_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_39" }, "PSS3.PSS1_LOGIC_OUTS20_4->PSS_LOGIC_OUTS20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_4" }, "PSS3.PSS1_LOGIC_OUTS20_5->PSS_LOGIC_OUTS20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_5" }, "PSS3.PSS1_LOGIC_OUTS20_6->PSS_LOGIC_OUTS20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_6" }, "PSS3.PSS1_LOGIC_OUTS20_7->PSS_LOGIC_OUTS20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_7" }, "PSS3.PSS1_LOGIC_OUTS20_8->PSS_LOGIC_OUTS20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_8" }, "PSS3.PSS1_LOGIC_OUTS20_9->PSS_LOGIC_OUTS20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS20_9" }, "PSS3.PSS1_LOGIC_OUTS21_0->PSS_LOGIC_OUTS21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_0" }, "PSS3.PSS1_LOGIC_OUTS21_1->PSS_LOGIC_OUTS21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_1" }, "PSS3.PSS1_LOGIC_OUTS21_10->PSS_LOGIC_OUTS21_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_10" }, "PSS3.PSS1_LOGIC_OUTS21_11->PSS_LOGIC_OUTS21_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_11" }, "PSS3.PSS1_LOGIC_OUTS21_12->PSS_LOGIC_OUTS21_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_12" }, "PSS3.PSS1_LOGIC_OUTS21_13->PSS_LOGIC_OUTS21_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_13" }, "PSS3.PSS1_LOGIC_OUTS21_14->PSS_LOGIC_OUTS21_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_14" }, "PSS3.PSS1_LOGIC_OUTS21_15->PSS_LOGIC_OUTS21_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_15" }, "PSS3.PSS1_LOGIC_OUTS21_16->PSS_LOGIC_OUTS21_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_16" }, "PSS3.PSS1_LOGIC_OUTS21_17->PSS_LOGIC_OUTS21_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_17" }, "PSS3.PSS1_LOGIC_OUTS21_18->PSS_LOGIC_OUTS21_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_18" }, "PSS3.PSS1_LOGIC_OUTS21_19->PSS_LOGIC_OUTS21_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_19" }, "PSS3.PSS1_LOGIC_OUTS21_2->PSS_LOGIC_OUTS21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_2" }, "PSS3.PSS1_LOGIC_OUTS21_20->PSS0_LOGIC_OUTS21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_20" }, "PSS3.PSS1_LOGIC_OUTS21_21->PSS0_LOGIC_OUTS21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_21" }, "PSS3.PSS1_LOGIC_OUTS21_22->PSS0_LOGIC_OUTS21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_22" }, "PSS3.PSS1_LOGIC_OUTS21_23->PSS0_LOGIC_OUTS21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_23" }, "PSS3.PSS1_LOGIC_OUTS21_24->PSS0_LOGIC_OUTS21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_24" }, "PSS3.PSS1_LOGIC_OUTS21_25->PSS0_LOGIC_OUTS21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_25" }, "PSS3.PSS1_LOGIC_OUTS21_26->PSS0_LOGIC_OUTS21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_26" }, "PSS3.PSS1_LOGIC_OUTS21_27->PSS0_LOGIC_OUTS21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_27" }, "PSS3.PSS1_LOGIC_OUTS21_28->PSS0_LOGIC_OUTS21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_28" }, "PSS3.PSS1_LOGIC_OUTS21_29->PSS0_LOGIC_OUTS21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_29" }, "PSS3.PSS1_LOGIC_OUTS21_3->PSS_LOGIC_OUTS21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_3" }, "PSS3.PSS1_LOGIC_OUTS21_30->PSS0_LOGIC_OUTS21_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_30" }, "PSS3.PSS1_LOGIC_OUTS21_31->PSS0_LOGIC_OUTS21_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_31" }, "PSS3.PSS1_LOGIC_OUTS21_32->PSS0_LOGIC_OUTS21_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_32" }, "PSS3.PSS1_LOGIC_OUTS21_33->PSS0_LOGIC_OUTS21_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_33" }, "PSS3.PSS1_LOGIC_OUTS21_34->PSS0_LOGIC_OUTS21_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_34" }, "PSS3.PSS1_LOGIC_OUTS21_35->PSS0_LOGIC_OUTS21_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_35" }, "PSS3.PSS1_LOGIC_OUTS21_36->PSS0_LOGIC_OUTS21_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_36" }, "PSS3.PSS1_LOGIC_OUTS21_37->PSS0_LOGIC_OUTS21_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_37" }, "PSS3.PSS1_LOGIC_OUTS21_38->PSS0_LOGIC_OUTS21_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_38" }, "PSS3.PSS1_LOGIC_OUTS21_39->PSS0_LOGIC_OUTS21_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS21_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_39" }, "PSS3.PSS1_LOGIC_OUTS21_4->PSS_LOGIC_OUTS21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_4" }, "PSS3.PSS1_LOGIC_OUTS21_5->PSS_LOGIC_OUTS21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_5" }, "PSS3.PSS1_LOGIC_OUTS21_6->PSS_LOGIC_OUTS21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_6" }, "PSS3.PSS1_LOGIC_OUTS21_7->PSS_LOGIC_OUTS21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_7" }, "PSS3.PSS1_LOGIC_OUTS21_8->PSS_LOGIC_OUTS21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_8" }, "PSS3.PSS1_LOGIC_OUTS21_9->PSS_LOGIC_OUTS21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS21_9" }, "PSS3.PSS1_LOGIC_OUTS22_0->PSS_LOGIC_OUTS22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_0" }, "PSS3.PSS1_LOGIC_OUTS22_1->PSS_LOGIC_OUTS22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_1" }, "PSS3.PSS1_LOGIC_OUTS22_10->PSS_LOGIC_OUTS22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_10" }, "PSS3.PSS1_LOGIC_OUTS22_11->PSS_LOGIC_OUTS22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_11" }, "PSS3.PSS1_LOGIC_OUTS22_12->PSS_LOGIC_OUTS22_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_12" }, "PSS3.PSS1_LOGIC_OUTS22_13->PSS_LOGIC_OUTS22_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_13" }, "PSS3.PSS1_LOGIC_OUTS22_14->PSS_LOGIC_OUTS22_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_14" }, "PSS3.PSS1_LOGIC_OUTS22_15->PSS_LOGIC_OUTS22_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_15" }, "PSS3.PSS1_LOGIC_OUTS22_16->PSS_LOGIC_OUTS22_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_16" }, "PSS3.PSS1_LOGIC_OUTS22_17->PSS_LOGIC_OUTS22_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_17" }, "PSS3.PSS1_LOGIC_OUTS22_18->PSS_LOGIC_OUTS22_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_18" }, "PSS3.PSS1_LOGIC_OUTS22_19->PSS_LOGIC_OUTS22_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_19" }, "PSS3.PSS1_LOGIC_OUTS22_2->PSS_LOGIC_OUTS22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_2" }, "PSS3.PSS1_LOGIC_OUTS22_20->PSS0_LOGIC_OUTS22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_20" }, "PSS3.PSS1_LOGIC_OUTS22_21->PSS0_LOGIC_OUTS22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_21" }, "PSS3.PSS1_LOGIC_OUTS22_22->PSS0_LOGIC_OUTS22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_22" }, "PSS3.PSS1_LOGIC_OUTS22_23->PSS0_LOGIC_OUTS22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_23" }, "PSS3.PSS1_LOGIC_OUTS22_24->PSS0_LOGIC_OUTS22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_24" }, "PSS3.PSS1_LOGIC_OUTS22_25->PSS0_LOGIC_OUTS22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_25" }, "PSS3.PSS1_LOGIC_OUTS22_26->PSS0_LOGIC_OUTS22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_26" }, "PSS3.PSS1_LOGIC_OUTS22_27->PSS0_LOGIC_OUTS22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_27" }, "PSS3.PSS1_LOGIC_OUTS22_28->PSS0_LOGIC_OUTS22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_28" }, "PSS3.PSS1_LOGIC_OUTS22_29->PSS0_LOGIC_OUTS22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_29" }, "PSS3.PSS1_LOGIC_OUTS22_3->PSS_LOGIC_OUTS22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_3" }, "PSS3.PSS1_LOGIC_OUTS22_30->PSS0_LOGIC_OUTS22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_30" }, "PSS3.PSS1_LOGIC_OUTS22_31->PSS0_LOGIC_OUTS22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_31" }, "PSS3.PSS1_LOGIC_OUTS22_32->PSS0_LOGIC_OUTS22_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_32" }, "PSS3.PSS1_LOGIC_OUTS22_33->PSS0_LOGIC_OUTS22_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_33" }, "PSS3.PSS1_LOGIC_OUTS22_34->PSS0_LOGIC_OUTS22_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_34" }, "PSS3.PSS1_LOGIC_OUTS22_35->PSS0_LOGIC_OUTS22_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_35" }, "PSS3.PSS1_LOGIC_OUTS22_36->PSS0_LOGIC_OUTS22_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_36" }, "PSS3.PSS1_LOGIC_OUTS22_37->PSS0_LOGIC_OUTS22_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_37" }, "PSS3.PSS1_LOGIC_OUTS22_38->PSS0_LOGIC_OUTS22_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_38" }, "PSS3.PSS1_LOGIC_OUTS22_39->PSS0_LOGIC_OUTS22_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS22_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_39" }, "PSS3.PSS1_LOGIC_OUTS22_4->PSS_LOGIC_OUTS22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_4" }, "PSS3.PSS1_LOGIC_OUTS22_5->PSS_LOGIC_OUTS22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_5" }, "PSS3.PSS1_LOGIC_OUTS22_6->PSS_LOGIC_OUTS22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_6" }, "PSS3.PSS1_LOGIC_OUTS22_7->PSS_LOGIC_OUTS22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_7" }, "PSS3.PSS1_LOGIC_OUTS22_8->PSS_LOGIC_OUTS22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_8" }, "PSS3.PSS1_LOGIC_OUTS22_9->PSS_LOGIC_OUTS22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS22_9" }, "PSS3.PSS1_LOGIC_OUTS23_0->PSS_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_0" }, "PSS3.PSS1_LOGIC_OUTS23_1->PSS_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_1" }, "PSS3.PSS1_LOGIC_OUTS23_10->PSS_LOGIC_OUTS23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_10" }, "PSS3.PSS1_LOGIC_OUTS23_11->PSS_LOGIC_OUTS23_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_11" }, "PSS3.PSS1_LOGIC_OUTS23_12->PSS_LOGIC_OUTS23_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_12" }, "PSS3.PSS1_LOGIC_OUTS23_13->PSS_LOGIC_OUTS23_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_13" }, "PSS3.PSS1_LOGIC_OUTS23_14->PSS_LOGIC_OUTS23_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_14" }, "PSS3.PSS1_LOGIC_OUTS23_15->PSS_LOGIC_OUTS23_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_15" }, "PSS3.PSS1_LOGIC_OUTS23_16->PSS_LOGIC_OUTS23_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_16" }, "PSS3.PSS1_LOGIC_OUTS23_17->PSS_LOGIC_OUTS23_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_17" }, "PSS3.PSS1_LOGIC_OUTS23_18->PSS_LOGIC_OUTS23_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_18" }, "PSS3.PSS1_LOGIC_OUTS23_19->PSS_LOGIC_OUTS23_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_19" }, "PSS3.PSS1_LOGIC_OUTS23_2->PSS_LOGIC_OUTS23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_2" }, "PSS3.PSS1_LOGIC_OUTS23_20->PSS0_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_20" }, "PSS3.PSS1_LOGIC_OUTS23_21->PSS0_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_21" }, "PSS3.PSS1_LOGIC_OUTS23_22->PSS0_LOGIC_OUTS23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_22" }, "PSS3.PSS1_LOGIC_OUTS23_23->PSS0_LOGIC_OUTS23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_23" }, "PSS3.PSS1_LOGIC_OUTS23_24->PSS0_LOGIC_OUTS23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_24" }, "PSS3.PSS1_LOGIC_OUTS23_25->PSS0_LOGIC_OUTS23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_25" }, "PSS3.PSS1_LOGIC_OUTS23_26->PSS0_LOGIC_OUTS23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_26" }, "PSS3.PSS1_LOGIC_OUTS23_27->PSS0_LOGIC_OUTS23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_27" }, "PSS3.PSS1_LOGIC_OUTS23_28->PSS0_LOGIC_OUTS23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_28" }, "PSS3.PSS1_LOGIC_OUTS23_29->PSS0_LOGIC_OUTS23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_29" }, "PSS3.PSS1_LOGIC_OUTS23_3->PSS_LOGIC_OUTS23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_3" }, "PSS3.PSS1_LOGIC_OUTS23_30->PSS0_LOGIC_OUTS23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_30" }, "PSS3.PSS1_LOGIC_OUTS23_31->PSS0_LOGIC_OUTS23_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_31" }, "PSS3.PSS1_LOGIC_OUTS23_32->PSS0_LOGIC_OUTS23_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_32" }, "PSS3.PSS1_LOGIC_OUTS23_33->PSS0_LOGIC_OUTS23_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_33" }, "PSS3.PSS1_LOGIC_OUTS23_34->PSS0_LOGIC_OUTS23_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_34" }, "PSS3.PSS1_LOGIC_OUTS23_35->PSS0_LOGIC_OUTS23_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_35" }, "PSS3.PSS1_LOGIC_OUTS23_36->PSS0_LOGIC_OUTS23_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_36" }, "PSS3.PSS1_LOGIC_OUTS23_37->PSS0_LOGIC_OUTS23_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_37" }, "PSS3.PSS1_LOGIC_OUTS23_38->PSS0_LOGIC_OUTS23_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_38" }, "PSS3.PSS1_LOGIC_OUTS23_39->PSS0_LOGIC_OUTS23_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS23_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_39" }, "PSS3.PSS1_LOGIC_OUTS23_4->PSS_LOGIC_OUTS23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_4" }, "PSS3.PSS1_LOGIC_OUTS23_5->PSS_LOGIC_OUTS23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_5" }, "PSS3.PSS1_LOGIC_OUTS23_6->PSS_LOGIC_OUTS23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_6" }, "PSS3.PSS1_LOGIC_OUTS23_7->PSS_LOGIC_OUTS23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_7" }, "PSS3.PSS1_LOGIC_OUTS23_8->PSS_LOGIC_OUTS23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_8" }, "PSS3.PSS1_LOGIC_OUTS23_9->PSS_LOGIC_OUTS23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS23_9" }, "PSS3.PSS1_LOGIC_OUTS2_0->PSS_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_0" }, "PSS3.PSS1_LOGIC_OUTS2_1->PSS_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_1" }, "PSS3.PSS1_LOGIC_OUTS2_10->PSS_LOGIC_OUTS2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_10" }, "PSS3.PSS1_LOGIC_OUTS2_11->PSS_LOGIC_OUTS2_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_11" }, "PSS3.PSS1_LOGIC_OUTS2_12->PSS_LOGIC_OUTS2_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_12" }, "PSS3.PSS1_LOGIC_OUTS2_13->PSS_LOGIC_OUTS2_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_13" }, "PSS3.PSS1_LOGIC_OUTS2_14->PSS_LOGIC_OUTS2_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_14" }, "PSS3.PSS1_LOGIC_OUTS2_15->PSS_LOGIC_OUTS2_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_15" }, "PSS3.PSS1_LOGIC_OUTS2_16->PSS_LOGIC_OUTS2_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_16" }, "PSS3.PSS1_LOGIC_OUTS2_17->PSS_LOGIC_OUTS2_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_17" }, "PSS3.PSS1_LOGIC_OUTS2_18->PSS_LOGIC_OUTS2_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_18" }, "PSS3.PSS1_LOGIC_OUTS2_19->PSS_LOGIC_OUTS2_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_19" }, "PSS3.PSS1_LOGIC_OUTS2_2->PSS_LOGIC_OUTS2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_2" }, "PSS3.PSS1_LOGIC_OUTS2_20->PSS0_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_20" }, "PSS3.PSS1_LOGIC_OUTS2_21->PSS0_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_21" }, "PSS3.PSS1_LOGIC_OUTS2_22->PSS0_LOGIC_OUTS2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_22" }, "PSS3.PSS1_LOGIC_OUTS2_23->PSS0_LOGIC_OUTS2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_23" }, "PSS3.PSS1_LOGIC_OUTS2_24->PSS0_LOGIC_OUTS2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_24" }, "PSS3.PSS1_LOGIC_OUTS2_25->PSS0_LOGIC_OUTS2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_25" }, "PSS3.PSS1_LOGIC_OUTS2_26->PSS0_LOGIC_OUTS2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_26" }, "PSS3.PSS1_LOGIC_OUTS2_27->PSS0_LOGIC_OUTS2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_27" }, "PSS3.PSS1_LOGIC_OUTS2_28->PSS0_LOGIC_OUTS2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_28" }, "PSS3.PSS1_LOGIC_OUTS2_29->PSS0_LOGIC_OUTS2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_29" }, "PSS3.PSS1_LOGIC_OUTS2_3->PSS_LOGIC_OUTS2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_3" }, "PSS3.PSS1_LOGIC_OUTS2_30->PSS0_LOGIC_OUTS2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_30" }, "PSS3.PSS1_LOGIC_OUTS2_31->PSS0_LOGIC_OUTS2_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_31" }, "PSS3.PSS1_LOGIC_OUTS2_32->PSS0_LOGIC_OUTS2_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_32" }, "PSS3.PSS1_LOGIC_OUTS2_33->PSS0_LOGIC_OUTS2_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_33" }, "PSS3.PSS1_LOGIC_OUTS2_34->PSS0_LOGIC_OUTS2_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_34" }, "PSS3.PSS1_LOGIC_OUTS2_35->PSS0_LOGIC_OUTS2_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_35" }, "PSS3.PSS1_LOGIC_OUTS2_36->PSS0_LOGIC_OUTS2_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_36" }, "PSS3.PSS1_LOGIC_OUTS2_37->PSS0_LOGIC_OUTS2_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_37" }, "PSS3.PSS1_LOGIC_OUTS2_38->PSS0_LOGIC_OUTS2_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_38" }, "PSS3.PSS1_LOGIC_OUTS2_39->PSS0_LOGIC_OUTS2_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS2_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_39" }, "PSS3.PSS1_LOGIC_OUTS2_4->PSS_LOGIC_OUTS2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_4" }, "PSS3.PSS1_LOGIC_OUTS2_5->PSS_LOGIC_OUTS2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_5" }, "PSS3.PSS1_LOGIC_OUTS2_6->PSS_LOGIC_OUTS2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_6" }, "PSS3.PSS1_LOGIC_OUTS2_7->PSS_LOGIC_OUTS2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_7" }, "PSS3.PSS1_LOGIC_OUTS2_8->PSS_LOGIC_OUTS2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_8" }, "PSS3.PSS1_LOGIC_OUTS2_9->PSS_LOGIC_OUTS2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS2_9" }, "PSS3.PSS1_LOGIC_OUTS3_0->PSS_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_0" }, "PSS3.PSS1_LOGIC_OUTS3_1->PSS_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_1" }, "PSS3.PSS1_LOGIC_OUTS3_10->PSS_LOGIC_OUTS3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_10" }, "PSS3.PSS1_LOGIC_OUTS3_11->PSS_LOGIC_OUTS3_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_11" }, "PSS3.PSS1_LOGIC_OUTS3_12->PSS_LOGIC_OUTS3_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_12" }, "PSS3.PSS1_LOGIC_OUTS3_13->PSS_LOGIC_OUTS3_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_13" }, "PSS3.PSS1_LOGIC_OUTS3_14->PSS_LOGIC_OUTS3_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_14" }, "PSS3.PSS1_LOGIC_OUTS3_15->PSS_LOGIC_OUTS3_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_15" }, "PSS3.PSS1_LOGIC_OUTS3_16->PSS_LOGIC_OUTS3_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_16" }, "PSS3.PSS1_LOGIC_OUTS3_17->PSS_LOGIC_OUTS3_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_17" }, "PSS3.PSS1_LOGIC_OUTS3_18->PSS_LOGIC_OUTS3_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_18" }, "PSS3.PSS1_LOGIC_OUTS3_19->PSS_LOGIC_OUTS3_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_19" }, "PSS3.PSS1_LOGIC_OUTS3_2->PSS_LOGIC_OUTS3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_2" }, "PSS3.PSS1_LOGIC_OUTS3_20->PSS0_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_20" }, "PSS3.PSS1_LOGIC_OUTS3_21->PSS0_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_21" }, "PSS3.PSS1_LOGIC_OUTS3_22->PSS0_LOGIC_OUTS3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_22" }, "PSS3.PSS1_LOGIC_OUTS3_23->PSS0_LOGIC_OUTS3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_23" }, "PSS3.PSS1_LOGIC_OUTS3_24->PSS0_LOGIC_OUTS3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_24" }, "PSS3.PSS1_LOGIC_OUTS3_25->PSS0_LOGIC_OUTS3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_25" }, "PSS3.PSS1_LOGIC_OUTS3_26->PSS0_LOGIC_OUTS3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_26" }, "PSS3.PSS1_LOGIC_OUTS3_27->PSS0_LOGIC_OUTS3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_27" }, "PSS3.PSS1_LOGIC_OUTS3_28->PSS0_LOGIC_OUTS3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_28" }, "PSS3.PSS1_LOGIC_OUTS3_29->PSS0_LOGIC_OUTS3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_29" }, "PSS3.PSS1_LOGIC_OUTS3_3->PSS_LOGIC_OUTS3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_3" }, "PSS3.PSS1_LOGIC_OUTS3_30->PSS0_LOGIC_OUTS3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_30" }, "PSS3.PSS1_LOGIC_OUTS3_31->PSS0_LOGIC_OUTS3_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_31" }, "PSS3.PSS1_LOGIC_OUTS3_32->PSS0_LOGIC_OUTS3_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_32" }, "PSS3.PSS1_LOGIC_OUTS3_33->PSS0_LOGIC_OUTS3_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_33" }, "PSS3.PSS1_LOGIC_OUTS3_34->PSS0_LOGIC_OUTS3_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_34" }, "PSS3.PSS1_LOGIC_OUTS3_35->PSS0_LOGIC_OUTS3_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_35" }, "PSS3.PSS1_LOGIC_OUTS3_36->PSS0_LOGIC_OUTS3_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_36" }, "PSS3.PSS1_LOGIC_OUTS3_37->PSS0_LOGIC_OUTS3_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_37" }, "PSS3.PSS1_LOGIC_OUTS3_38->PSS0_LOGIC_OUTS3_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_38" }, "PSS3.PSS1_LOGIC_OUTS3_39->PSS0_LOGIC_OUTS3_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS3_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_39" }, "PSS3.PSS1_LOGIC_OUTS3_4->PSS_LOGIC_OUTS3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_4" }, "PSS3.PSS1_LOGIC_OUTS3_5->PSS_LOGIC_OUTS3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_5" }, "PSS3.PSS1_LOGIC_OUTS3_6->PSS_LOGIC_OUTS3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_6" }, "PSS3.PSS1_LOGIC_OUTS3_7->PSS_LOGIC_OUTS3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_7" }, "PSS3.PSS1_LOGIC_OUTS3_8->PSS_LOGIC_OUTS3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_8" }, "PSS3.PSS1_LOGIC_OUTS3_9->PSS_LOGIC_OUTS3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS3_9" }, "PSS3.PSS1_LOGIC_OUTS4_0->PSS_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_0" }, "PSS3.PSS1_LOGIC_OUTS4_1->PSS_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_1" }, "PSS3.PSS1_LOGIC_OUTS4_10->PSS_LOGIC_OUTS4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_10" }, "PSS3.PSS1_LOGIC_OUTS4_11->PSS_LOGIC_OUTS4_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_11" }, "PSS3.PSS1_LOGIC_OUTS4_12->PSS_LOGIC_OUTS4_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_12" }, "PSS3.PSS1_LOGIC_OUTS4_13->PSS_LOGIC_OUTS4_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_13" }, "PSS3.PSS1_LOGIC_OUTS4_14->PSS_LOGIC_OUTS4_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_14" }, "PSS3.PSS1_LOGIC_OUTS4_15->PSS_LOGIC_OUTS4_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_15" }, "PSS3.PSS1_LOGIC_OUTS4_16->PSS_LOGIC_OUTS4_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_16" }, "PSS3.PSS1_LOGIC_OUTS4_17->PSS_LOGIC_OUTS4_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_17" }, "PSS3.PSS1_LOGIC_OUTS4_18->PSS_LOGIC_OUTS4_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_18" }, "PSS3.PSS1_LOGIC_OUTS4_19->PSS_LOGIC_OUTS4_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_19" }, "PSS3.PSS1_LOGIC_OUTS4_2->PSS_LOGIC_OUTS4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_2" }, "PSS3.PSS1_LOGIC_OUTS4_20->PSS0_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_20" }, "PSS3.PSS1_LOGIC_OUTS4_21->PSS0_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_21" }, "PSS3.PSS1_LOGIC_OUTS4_22->PSS0_LOGIC_OUTS4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_22" }, "PSS3.PSS1_LOGIC_OUTS4_23->PSS0_LOGIC_OUTS4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_23" }, "PSS3.PSS1_LOGIC_OUTS4_24->PSS0_LOGIC_OUTS4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_24" }, "PSS3.PSS1_LOGIC_OUTS4_25->PSS0_LOGIC_OUTS4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_25" }, "PSS3.PSS1_LOGIC_OUTS4_26->PSS0_LOGIC_OUTS4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_26" }, "PSS3.PSS1_LOGIC_OUTS4_27->PSS0_LOGIC_OUTS4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_27" }, "PSS3.PSS1_LOGIC_OUTS4_28->PSS0_LOGIC_OUTS4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_28" }, "PSS3.PSS1_LOGIC_OUTS4_29->PSS0_LOGIC_OUTS4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_29" }, "PSS3.PSS1_LOGIC_OUTS4_3->PSS_LOGIC_OUTS4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_3" }, "PSS3.PSS1_LOGIC_OUTS4_30->PSS0_LOGIC_OUTS4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_30" }, "PSS3.PSS1_LOGIC_OUTS4_31->PSS0_LOGIC_OUTS4_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_31" }, "PSS3.PSS1_LOGIC_OUTS4_32->PSS0_LOGIC_OUTS4_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_32" }, "PSS3.PSS1_LOGIC_OUTS4_33->PSS0_LOGIC_OUTS4_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_33" }, "PSS3.PSS1_LOGIC_OUTS4_34->PSS0_LOGIC_OUTS4_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_34" }, "PSS3.PSS1_LOGIC_OUTS4_35->PSS0_LOGIC_OUTS4_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_35" }, "PSS3.PSS1_LOGIC_OUTS4_36->PSS0_LOGIC_OUTS4_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_36" }, "PSS3.PSS1_LOGIC_OUTS4_37->PSS0_LOGIC_OUTS4_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_37" }, "PSS3.PSS1_LOGIC_OUTS4_38->PSS0_LOGIC_OUTS4_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_38" }, "PSS3.PSS1_LOGIC_OUTS4_39->PSS0_LOGIC_OUTS4_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS4_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_39" }, "PSS3.PSS1_LOGIC_OUTS4_4->PSS_LOGIC_OUTS4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_4" }, "PSS3.PSS1_LOGIC_OUTS4_5->PSS_LOGIC_OUTS4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_5" }, "PSS3.PSS1_LOGIC_OUTS4_6->PSS_LOGIC_OUTS4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_6" }, "PSS3.PSS1_LOGIC_OUTS4_7->PSS_LOGIC_OUTS4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_7" }, "PSS3.PSS1_LOGIC_OUTS4_8->PSS_LOGIC_OUTS4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_8" }, "PSS3.PSS1_LOGIC_OUTS4_9->PSS_LOGIC_OUTS4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS4_9" }, "PSS3.PSS1_LOGIC_OUTS5_0->PSS_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_0" }, "PSS3.PSS1_LOGIC_OUTS5_1->PSS_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_1" }, "PSS3.PSS1_LOGIC_OUTS5_10->PSS_LOGIC_OUTS5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_10" }, "PSS3.PSS1_LOGIC_OUTS5_11->PSS_LOGIC_OUTS5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_11" }, "PSS3.PSS1_LOGIC_OUTS5_12->PSS_LOGIC_OUTS5_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_12" }, "PSS3.PSS1_LOGIC_OUTS5_13->PSS_LOGIC_OUTS5_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_13" }, "PSS3.PSS1_LOGIC_OUTS5_14->PSS_LOGIC_OUTS5_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_14" }, "PSS3.PSS1_LOGIC_OUTS5_15->PSS_LOGIC_OUTS5_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_15" }, "PSS3.PSS1_LOGIC_OUTS5_16->PSS_LOGIC_OUTS5_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_16" }, "PSS3.PSS1_LOGIC_OUTS5_17->PSS_LOGIC_OUTS5_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_17" }, "PSS3.PSS1_LOGIC_OUTS5_18->PSS_LOGIC_OUTS5_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_18" }, "PSS3.PSS1_LOGIC_OUTS5_19->PSS_LOGIC_OUTS5_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_19" }, "PSS3.PSS1_LOGIC_OUTS5_2->PSS_LOGIC_OUTS5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_2" }, "PSS3.PSS1_LOGIC_OUTS5_20->PSS0_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_20" }, "PSS3.PSS1_LOGIC_OUTS5_21->PSS0_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_21" }, "PSS3.PSS1_LOGIC_OUTS5_22->PSS0_LOGIC_OUTS5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_22" }, "PSS3.PSS1_LOGIC_OUTS5_23->PSS0_LOGIC_OUTS5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_23" }, "PSS3.PSS1_LOGIC_OUTS5_24->PSS0_LOGIC_OUTS5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_24" }, "PSS3.PSS1_LOGIC_OUTS5_25->PSS0_LOGIC_OUTS5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_25" }, "PSS3.PSS1_LOGIC_OUTS5_26->PSS0_LOGIC_OUTS5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_26" }, "PSS3.PSS1_LOGIC_OUTS5_27->PSS0_LOGIC_OUTS5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_27" }, "PSS3.PSS1_LOGIC_OUTS5_28->PSS0_LOGIC_OUTS5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_28" }, "PSS3.PSS1_LOGIC_OUTS5_29->PSS0_LOGIC_OUTS5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_29" }, "PSS3.PSS1_LOGIC_OUTS5_3->PSS_LOGIC_OUTS5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_3" }, "PSS3.PSS1_LOGIC_OUTS5_30->PSS0_LOGIC_OUTS5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_30" }, "PSS3.PSS1_LOGIC_OUTS5_31->PSS0_LOGIC_OUTS5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_31" }, "PSS3.PSS1_LOGIC_OUTS5_32->PSS0_LOGIC_OUTS5_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_32" }, "PSS3.PSS1_LOGIC_OUTS5_33->PSS0_LOGIC_OUTS5_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_33" }, "PSS3.PSS1_LOGIC_OUTS5_34->PSS0_LOGIC_OUTS5_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_34" }, "PSS3.PSS1_LOGIC_OUTS5_35->PSS0_LOGIC_OUTS5_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_35" }, "PSS3.PSS1_LOGIC_OUTS5_36->PSS0_LOGIC_OUTS5_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_36" }, "PSS3.PSS1_LOGIC_OUTS5_37->PSS0_LOGIC_OUTS5_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_37" }, "PSS3.PSS1_LOGIC_OUTS5_38->PSS0_LOGIC_OUTS5_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_38" }, "PSS3.PSS1_LOGIC_OUTS5_39->PSS0_LOGIC_OUTS5_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS5_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_39" }, "PSS3.PSS1_LOGIC_OUTS5_4->PSS_LOGIC_OUTS5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_4" }, "PSS3.PSS1_LOGIC_OUTS5_5->PSS_LOGIC_OUTS5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_5" }, "PSS3.PSS1_LOGIC_OUTS5_6->PSS_LOGIC_OUTS5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_6" }, "PSS3.PSS1_LOGIC_OUTS5_7->PSS_LOGIC_OUTS5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_7" }, "PSS3.PSS1_LOGIC_OUTS5_8->PSS_LOGIC_OUTS5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_8" }, "PSS3.PSS1_LOGIC_OUTS5_9->PSS_LOGIC_OUTS5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS5_9" }, "PSS3.PSS1_LOGIC_OUTS6_0->PSS_LOGIC_OUTS6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_0" }, "PSS3.PSS1_LOGIC_OUTS6_1->PSS_LOGIC_OUTS6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_1" }, "PSS3.PSS1_LOGIC_OUTS6_10->PSS_LOGIC_OUTS6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_10" }, "PSS3.PSS1_LOGIC_OUTS6_11->PSS_LOGIC_OUTS6_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_11" }, "PSS3.PSS1_LOGIC_OUTS6_12->PSS_LOGIC_OUTS6_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_12" }, "PSS3.PSS1_LOGIC_OUTS6_13->PSS_LOGIC_OUTS6_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_13" }, "PSS3.PSS1_LOGIC_OUTS6_14->PSS_LOGIC_OUTS6_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_14" }, "PSS3.PSS1_LOGIC_OUTS6_15->PSS_LOGIC_OUTS6_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_15" }, "PSS3.PSS1_LOGIC_OUTS6_16->PSS_LOGIC_OUTS6_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_16" }, "PSS3.PSS1_LOGIC_OUTS6_17->PSS_LOGIC_OUTS6_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_17" }, "PSS3.PSS1_LOGIC_OUTS6_18->PSS_LOGIC_OUTS6_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_18" }, "PSS3.PSS1_LOGIC_OUTS6_19->PSS_LOGIC_OUTS6_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_19" }, "PSS3.PSS1_LOGIC_OUTS6_2->PSS_LOGIC_OUTS6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_2" }, "PSS3.PSS1_LOGIC_OUTS6_20->PSS0_LOGIC_OUTS6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_20" }, "PSS3.PSS1_LOGIC_OUTS6_21->PSS0_LOGIC_OUTS6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_21" }, "PSS3.PSS1_LOGIC_OUTS6_22->PSS0_LOGIC_OUTS6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_22" }, "PSS3.PSS1_LOGIC_OUTS6_23->PSS0_LOGIC_OUTS6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_23" }, "PSS3.PSS1_LOGIC_OUTS6_24->PSS0_LOGIC_OUTS6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_24" }, "PSS3.PSS1_LOGIC_OUTS6_25->PSS0_LOGIC_OUTS6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_25" }, "PSS3.PSS1_LOGIC_OUTS6_26->PSS0_LOGIC_OUTS6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_26" }, "PSS3.PSS1_LOGIC_OUTS6_27->PSS0_LOGIC_OUTS6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_27" }, "PSS3.PSS1_LOGIC_OUTS6_28->PSS0_LOGIC_OUTS6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_28" }, "PSS3.PSS1_LOGIC_OUTS6_29->PSS0_LOGIC_OUTS6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_29" }, "PSS3.PSS1_LOGIC_OUTS6_3->PSS_LOGIC_OUTS6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_3" }, "PSS3.PSS1_LOGIC_OUTS6_30->PSS0_LOGIC_OUTS6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_30" }, "PSS3.PSS1_LOGIC_OUTS6_31->PSS0_LOGIC_OUTS6_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_31" }, "PSS3.PSS1_LOGIC_OUTS6_32->PSS0_LOGIC_OUTS6_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_32" }, "PSS3.PSS1_LOGIC_OUTS6_33->PSS0_LOGIC_OUTS6_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_33" }, "PSS3.PSS1_LOGIC_OUTS6_34->PSS0_LOGIC_OUTS6_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_34" }, "PSS3.PSS1_LOGIC_OUTS6_35->PSS0_LOGIC_OUTS6_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_35" }, "PSS3.PSS1_LOGIC_OUTS6_36->PSS0_LOGIC_OUTS6_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_36" }, "PSS3.PSS1_LOGIC_OUTS6_37->PSS0_LOGIC_OUTS6_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_37" }, "PSS3.PSS1_LOGIC_OUTS6_38->PSS0_LOGIC_OUTS6_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_38" }, "PSS3.PSS1_LOGIC_OUTS6_39->PSS0_LOGIC_OUTS6_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS6_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_39" }, "PSS3.PSS1_LOGIC_OUTS6_4->PSS_LOGIC_OUTS6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_4" }, "PSS3.PSS1_LOGIC_OUTS6_5->PSS_LOGIC_OUTS6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_5" }, "PSS3.PSS1_LOGIC_OUTS6_6->PSS_LOGIC_OUTS6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_6" }, "PSS3.PSS1_LOGIC_OUTS6_7->PSS_LOGIC_OUTS6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_7" }, "PSS3.PSS1_LOGIC_OUTS6_8->PSS_LOGIC_OUTS6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_8" }, "PSS3.PSS1_LOGIC_OUTS6_9->PSS_LOGIC_OUTS6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS6_9" }, "PSS3.PSS1_LOGIC_OUTS7_0->PSS_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_0" }, "PSS3.PSS1_LOGIC_OUTS7_1->PSS_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_1" }, "PSS3.PSS1_LOGIC_OUTS7_10->PSS_LOGIC_OUTS7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_10" }, "PSS3.PSS1_LOGIC_OUTS7_11->PSS_LOGIC_OUTS7_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_11" }, "PSS3.PSS1_LOGIC_OUTS7_12->PSS_LOGIC_OUTS7_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_12" }, "PSS3.PSS1_LOGIC_OUTS7_13->PSS_LOGIC_OUTS7_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_13" }, "PSS3.PSS1_LOGIC_OUTS7_14->PSS_LOGIC_OUTS7_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_14" }, "PSS3.PSS1_LOGIC_OUTS7_15->PSS_LOGIC_OUTS7_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_15" }, "PSS3.PSS1_LOGIC_OUTS7_16->PSS_LOGIC_OUTS7_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_16" }, "PSS3.PSS1_LOGIC_OUTS7_17->PSS_LOGIC_OUTS7_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_17" }, "PSS3.PSS1_LOGIC_OUTS7_18->PSS_LOGIC_OUTS7_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_18" }, "PSS3.PSS1_LOGIC_OUTS7_19->PSS_LOGIC_OUTS7_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_19" }, "PSS3.PSS1_LOGIC_OUTS7_2->PSS_LOGIC_OUTS7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_2" }, "PSS3.PSS1_LOGIC_OUTS7_20->PSS0_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_20" }, "PSS3.PSS1_LOGIC_OUTS7_21->PSS0_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_21" }, "PSS3.PSS1_LOGIC_OUTS7_22->PSS0_LOGIC_OUTS7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_22" }, "PSS3.PSS1_LOGIC_OUTS7_23->PSS0_LOGIC_OUTS7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_23" }, "PSS3.PSS1_LOGIC_OUTS7_24->PSS0_LOGIC_OUTS7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_24" }, "PSS3.PSS1_LOGIC_OUTS7_25->PSS0_LOGIC_OUTS7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_25" }, "PSS3.PSS1_LOGIC_OUTS7_26->PSS0_LOGIC_OUTS7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_26" }, "PSS3.PSS1_LOGIC_OUTS7_27->PSS0_LOGIC_OUTS7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_27" }, "PSS3.PSS1_LOGIC_OUTS7_28->PSS0_LOGIC_OUTS7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_28" }, "PSS3.PSS1_LOGIC_OUTS7_29->PSS0_LOGIC_OUTS7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_29" }, "PSS3.PSS1_LOGIC_OUTS7_3->PSS_LOGIC_OUTS7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_3" }, "PSS3.PSS1_LOGIC_OUTS7_30->PSS0_LOGIC_OUTS7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_30" }, "PSS3.PSS1_LOGIC_OUTS7_31->PSS0_LOGIC_OUTS7_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_31" }, "PSS3.PSS1_LOGIC_OUTS7_32->PSS0_LOGIC_OUTS7_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_32" }, "PSS3.PSS1_LOGIC_OUTS7_33->PSS0_LOGIC_OUTS7_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_33" }, "PSS3.PSS1_LOGIC_OUTS7_34->PSS0_LOGIC_OUTS7_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_34" }, "PSS3.PSS1_LOGIC_OUTS7_35->PSS0_LOGIC_OUTS7_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_35" }, "PSS3.PSS1_LOGIC_OUTS7_36->PSS0_LOGIC_OUTS7_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_36" }, "PSS3.PSS1_LOGIC_OUTS7_37->PSS0_LOGIC_OUTS7_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_37" }, "PSS3.PSS1_LOGIC_OUTS7_38->PSS0_LOGIC_OUTS7_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_38" }, "PSS3.PSS1_LOGIC_OUTS7_39->PSS0_LOGIC_OUTS7_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS7_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_39" }, "PSS3.PSS1_LOGIC_OUTS7_4->PSS_LOGIC_OUTS7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_4" }, "PSS3.PSS1_LOGIC_OUTS7_5->PSS_LOGIC_OUTS7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_5" }, "PSS3.PSS1_LOGIC_OUTS7_6->PSS_LOGIC_OUTS7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_6" }, "PSS3.PSS1_LOGIC_OUTS7_7->PSS_LOGIC_OUTS7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_7" }, "PSS3.PSS1_LOGIC_OUTS7_8->PSS_LOGIC_OUTS7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_8" }, "PSS3.PSS1_LOGIC_OUTS7_9->PSS_LOGIC_OUTS7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS7_9" }, "PSS3.PSS1_LOGIC_OUTS8_0->PSS_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_0" }, "PSS3.PSS1_LOGIC_OUTS8_1->PSS_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_1" }, "PSS3.PSS1_LOGIC_OUTS8_10->PSS_LOGIC_OUTS8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_10" }, "PSS3.PSS1_LOGIC_OUTS8_11->PSS_LOGIC_OUTS8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_11" }, "PSS3.PSS1_LOGIC_OUTS8_12->PSS_LOGIC_OUTS8_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_12" }, "PSS3.PSS1_LOGIC_OUTS8_13->PSS_LOGIC_OUTS8_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_13" }, "PSS3.PSS1_LOGIC_OUTS8_14->PSS_LOGIC_OUTS8_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_14" }, "PSS3.PSS1_LOGIC_OUTS8_15->PSS_LOGIC_OUTS8_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_15" }, "PSS3.PSS1_LOGIC_OUTS8_16->PSS_LOGIC_OUTS8_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_16" }, "PSS3.PSS1_LOGIC_OUTS8_17->PSS_LOGIC_OUTS8_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_17" }, "PSS3.PSS1_LOGIC_OUTS8_18->PSS_LOGIC_OUTS8_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_18" }, "PSS3.PSS1_LOGIC_OUTS8_19->PSS_LOGIC_OUTS8_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_19" }, "PSS3.PSS1_LOGIC_OUTS8_2->PSS_LOGIC_OUTS8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_2" }, "PSS3.PSS1_LOGIC_OUTS8_20->PSS0_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_20" }, "PSS3.PSS1_LOGIC_OUTS8_21->PSS0_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_21" }, "PSS3.PSS1_LOGIC_OUTS8_22->PSS0_LOGIC_OUTS8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_22" }, "PSS3.PSS1_LOGIC_OUTS8_23->PSS0_LOGIC_OUTS8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_23" }, "PSS3.PSS1_LOGIC_OUTS8_24->PSS0_LOGIC_OUTS8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_24" }, "PSS3.PSS1_LOGIC_OUTS8_25->PSS0_LOGIC_OUTS8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_25" }, "PSS3.PSS1_LOGIC_OUTS8_26->PSS0_LOGIC_OUTS8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_26" }, "PSS3.PSS1_LOGIC_OUTS8_27->PSS0_LOGIC_OUTS8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_27" }, "PSS3.PSS1_LOGIC_OUTS8_28->PSS0_LOGIC_OUTS8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_28" }, "PSS3.PSS1_LOGIC_OUTS8_29->PSS0_LOGIC_OUTS8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_29" }, "PSS3.PSS1_LOGIC_OUTS8_3->PSS_LOGIC_OUTS8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_3" }, "PSS3.PSS1_LOGIC_OUTS8_30->PSS0_LOGIC_OUTS8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_30" }, "PSS3.PSS1_LOGIC_OUTS8_31->PSS0_LOGIC_OUTS8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_31" }, "PSS3.PSS1_LOGIC_OUTS8_32->PSS0_LOGIC_OUTS8_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_32" }, "PSS3.PSS1_LOGIC_OUTS8_33->PSS0_LOGIC_OUTS8_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_33" }, "PSS3.PSS1_LOGIC_OUTS8_34->PSS0_LOGIC_OUTS8_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_34" }, "PSS3.PSS1_LOGIC_OUTS8_35->PSS0_LOGIC_OUTS8_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_35" }, "PSS3.PSS1_LOGIC_OUTS8_36->PSS0_LOGIC_OUTS8_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_36" }, "PSS3.PSS1_LOGIC_OUTS8_37->PSS0_LOGIC_OUTS8_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_37" }, "PSS3.PSS1_LOGIC_OUTS8_38->PSS0_LOGIC_OUTS8_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_38" }, "PSS3.PSS1_LOGIC_OUTS8_39->PSS0_LOGIC_OUTS8_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS8_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_39" }, "PSS3.PSS1_LOGIC_OUTS8_4->PSS_LOGIC_OUTS8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_4" }, "PSS3.PSS1_LOGIC_OUTS8_5->PSS_LOGIC_OUTS8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_5" }, "PSS3.PSS1_LOGIC_OUTS8_6->PSS_LOGIC_OUTS8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_6" }, "PSS3.PSS1_LOGIC_OUTS8_7->PSS_LOGIC_OUTS8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_7" }, "PSS3.PSS1_LOGIC_OUTS8_8->PSS_LOGIC_OUTS8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_8" }, "PSS3.PSS1_LOGIC_OUTS8_9->PSS_LOGIC_OUTS8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS8_9" }, "PSS3.PSS1_LOGIC_OUTS9_0->PSS_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_0" }, "PSS3.PSS1_LOGIC_OUTS9_1->PSS_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_1" }, "PSS3.PSS1_LOGIC_OUTS9_10->PSS_LOGIC_OUTS9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_10" }, "PSS3.PSS1_LOGIC_OUTS9_11->PSS_LOGIC_OUTS9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_11" }, "PSS3.PSS1_LOGIC_OUTS9_12->PSS_LOGIC_OUTS9_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_12" }, "PSS3.PSS1_LOGIC_OUTS9_13->PSS_LOGIC_OUTS9_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_13" }, "PSS3.PSS1_LOGIC_OUTS9_14->PSS_LOGIC_OUTS9_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_14" }, "PSS3.PSS1_LOGIC_OUTS9_15->PSS_LOGIC_OUTS9_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_15" }, "PSS3.PSS1_LOGIC_OUTS9_16->PSS_LOGIC_OUTS9_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_16" }, "PSS3.PSS1_LOGIC_OUTS9_17->PSS_LOGIC_OUTS9_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_17" }, "PSS3.PSS1_LOGIC_OUTS9_18->PSS_LOGIC_OUTS9_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_18" }, "PSS3.PSS1_LOGIC_OUTS9_19->PSS_LOGIC_OUTS9_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_19" }, "PSS3.PSS1_LOGIC_OUTS9_2->PSS_LOGIC_OUTS9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_2" }, "PSS3.PSS1_LOGIC_OUTS9_20->PSS0_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_20" }, "PSS3.PSS1_LOGIC_OUTS9_21->PSS0_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_21" }, "PSS3.PSS1_LOGIC_OUTS9_22->PSS0_LOGIC_OUTS9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_22" }, "PSS3.PSS1_LOGIC_OUTS9_23->PSS0_LOGIC_OUTS9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_23" }, "PSS3.PSS1_LOGIC_OUTS9_24->PSS0_LOGIC_OUTS9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_24" }, "PSS3.PSS1_LOGIC_OUTS9_25->PSS0_LOGIC_OUTS9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_25" }, "PSS3.PSS1_LOGIC_OUTS9_26->PSS0_LOGIC_OUTS9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_26" }, "PSS3.PSS1_LOGIC_OUTS9_27->PSS0_LOGIC_OUTS9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_27" }, "PSS3.PSS1_LOGIC_OUTS9_28->PSS0_LOGIC_OUTS9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_28" }, "PSS3.PSS1_LOGIC_OUTS9_29->PSS0_LOGIC_OUTS9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_29" }, "PSS3.PSS1_LOGIC_OUTS9_3->PSS_LOGIC_OUTS9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_3" }, "PSS3.PSS1_LOGIC_OUTS9_30->PSS0_LOGIC_OUTS9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_30" }, "PSS3.PSS1_LOGIC_OUTS9_31->PSS0_LOGIC_OUTS9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_31" }, "PSS3.PSS1_LOGIC_OUTS9_32->PSS0_LOGIC_OUTS9_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_32" }, "PSS3.PSS1_LOGIC_OUTS9_33->PSS0_LOGIC_OUTS9_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_33" }, "PSS3.PSS1_LOGIC_OUTS9_34->PSS0_LOGIC_OUTS9_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_34" }, "PSS3.PSS1_LOGIC_OUTS9_35->PSS0_LOGIC_OUTS9_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_35" }, "PSS3.PSS1_LOGIC_OUTS9_36->PSS0_LOGIC_OUTS9_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_36" }, "PSS3.PSS1_LOGIC_OUTS9_37->PSS0_LOGIC_OUTS9_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_37" }, "PSS3.PSS1_LOGIC_OUTS9_38->PSS0_LOGIC_OUTS9_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_38" }, "PSS3.PSS1_LOGIC_OUTS9_39->PSS0_LOGIC_OUTS9_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_LOGIC_OUTS9_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_39" }, "PSS3.PSS1_LOGIC_OUTS9_4->PSS_LOGIC_OUTS9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_4" }, "PSS3.PSS1_LOGIC_OUTS9_5->PSS_LOGIC_OUTS9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_5" }, "PSS3.PSS1_LOGIC_OUTS9_6->PSS_LOGIC_OUTS9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_6" }, "PSS3.PSS1_LOGIC_OUTS9_7->PSS_LOGIC_OUTS9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_7" }, "PSS3.PSS1_LOGIC_OUTS9_8->PSS_LOGIC_OUTS9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_8" }, "PSS3.PSS1_LOGIC_OUTS9_9->PSS_LOGIC_OUTS9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS1_LOGIC_OUTS9_9" }, "PSS3.PSS3_TESTPLLCLKOUT0_IN->PSS3_TESTPLLCLKOUT0_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS3_TESTPLLCLKOUT0_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS3_TESTPLLCLKOUT0_IN" }, "PSS3.PSS3_TESTPLLCLKOUT1_IN->PSS3_TESTPLLCLKOUT1_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS3_TESTPLLCLKOUT1_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS3_TESTPLLCLKOUT1_IN" }, "PSS3.PSS3_TESTPLLCLKOUT2_IN->PSS3_TESTPLLCLKOUT2_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS3_TESTPLLCLKOUT2_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS3_TESTPLLCLKOUT2_IN" }, "PSS3.PSS3_TESTPLLNEWCLK0_IN->PSS3_TESTPLLNEWCLK0_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS3_TESTPLLNEWCLK0_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS3_TESTPLLNEWCLK0_IN" }, "PSS3.PSS3_TESTPLLNEWCLK1_IN->PSS3_TESTPLLNEWCLK1_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS3_TESTPLLNEWCLK1_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS3_TESTPLLNEWCLK1_IN" }, "PSS3.PSS3_TESTPLLNEWCLK2_IN->PSS3_TESTPLLNEWCLK2_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS3_TESTPLLNEWCLK2_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS3_TESTPLLNEWCLK2_IN" }, "PSS3.PSS_CLK_B0_0->PSS1_CLK_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_0" }, "PSS3.PSS_CLK_B0_1->PSS1_CLK_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_1" }, "PSS3.PSS_CLK_B0_10->PSS1_CLK_B0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_10" }, "PSS3.PSS_CLK_B0_11->PSS1_CLK_B0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_11" }, "PSS3.PSS_CLK_B0_12->PSS1_CLK_B0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_12" }, "PSS3.PSS_CLK_B0_13->PSS1_CLK_B0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_13" }, "PSS3.PSS_CLK_B0_14->PSS1_CLK_B0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_14" }, "PSS3.PSS_CLK_B0_15->PSS1_CLK_B0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_15" }, "PSS3.PSS_CLK_B0_16->PSS1_CLK_B0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_16" }, "PSS3.PSS_CLK_B0_17->PSS1_CLK_B0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_17" }, "PSS3.PSS_CLK_B0_18->PSS1_CLK_B0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_18" }, "PSS3.PSS_CLK_B0_19->PSS1_CLK_B0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_19" }, "PSS3.PSS_CLK_B0_2->PSS1_CLK_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_2" }, "PSS3.PSS_CLK_B0_3->PSS1_CLK_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_3" }, "PSS3.PSS_CLK_B0_4->PSS1_CLK_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_4" }, "PSS3.PSS_CLK_B0_5->PSS1_CLK_B0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_5" }, "PSS3.PSS_CLK_B0_6->PSS1_CLK_B0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_6" }, "PSS3.PSS_CLK_B0_7->PSS1_CLK_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_7" }, "PSS3.PSS_CLK_B0_8->PSS1_CLK_B0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_8" }, "PSS3.PSS_CLK_B0_9->PSS1_CLK_B0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_9" }, "PSS3.PSS_CLK_B1_0->PSS1_CLK_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_0" }, "PSS3.PSS_CLK_B1_1->PSS1_CLK_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_1" }, "PSS3.PSS_CLK_B1_10->PSS1_CLK_B1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_10" }, "PSS3.PSS_CLK_B1_11->PSS1_CLK_B1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_11" }, "PSS3.PSS_CLK_B1_12->PSS1_CLK_B1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_12" }, "PSS3.PSS_CLK_B1_13->PSS1_CLK_B1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_13" }, "PSS3.PSS_CLK_B1_14->PSS1_CLK_B1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_14" }, "PSS3.PSS_CLK_B1_15->PSS1_CLK_B1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_15" }, "PSS3.PSS_CLK_B1_16->PSS1_CLK_B1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_16" }, "PSS3.PSS_CLK_B1_17->PSS1_CLK_B1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_17" }, "PSS3.PSS_CLK_B1_18->PSS1_CLK_B1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_18" }, "PSS3.PSS_CLK_B1_19->PSS1_CLK_B1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_19" }, "PSS3.PSS_CLK_B1_2->PSS1_CLK_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_2" }, "PSS3.PSS_CLK_B1_3->PSS1_CLK_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_3" }, "PSS3.PSS_CLK_B1_4->PSS1_CLK_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_4" }, "PSS3.PSS_CLK_B1_5->PSS1_CLK_B1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_5" }, "PSS3.PSS_CLK_B1_6->PSS1_CLK_B1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_6" }, "PSS3.PSS_CLK_B1_7->PSS1_CLK_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_7" }, "PSS3.PSS_CLK_B1_8->PSS1_CLK_B1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_8" }, "PSS3.PSS_CLK_B1_9->PSS1_CLK_B1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_CLK_B1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_9" }, "PSS3.PSS_IMUX_B0_0->PSS1_IMUX_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_0" }, "PSS3.PSS_IMUX_B0_1->PSS1_IMUX_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_1" }, "PSS3.PSS_IMUX_B0_10->PSS1_IMUX_B0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_10" }, "PSS3.PSS_IMUX_B0_11->PSS1_IMUX_B0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_11" }, "PSS3.PSS_IMUX_B0_12->PSS1_IMUX_B0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_12" }, "PSS3.PSS_IMUX_B0_13->PSS1_IMUX_B0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_13" }, "PSS3.PSS_IMUX_B0_14->PSS1_IMUX_B0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_14" }, "PSS3.PSS_IMUX_B0_15->PSS1_IMUX_B0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_15" }, "PSS3.PSS_IMUX_B0_16->PSS1_IMUX_B0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_16" }, "PSS3.PSS_IMUX_B0_17->PSS1_IMUX_B0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_17" }, "PSS3.PSS_IMUX_B0_18->PSS1_IMUX_B0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_18" }, "PSS3.PSS_IMUX_B0_19->PSS1_IMUX_B0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_19" }, "PSS3.PSS_IMUX_B0_2->PSS1_IMUX_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_2" }, "PSS3.PSS_IMUX_B0_3->PSS1_IMUX_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_3" }, "PSS3.PSS_IMUX_B0_4->PSS1_IMUX_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_4" }, "PSS3.PSS_IMUX_B0_5->PSS1_IMUX_B0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_5" }, "PSS3.PSS_IMUX_B0_6->PSS1_IMUX_B0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_6" }, "PSS3.PSS_IMUX_B0_7->PSS1_IMUX_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_7" }, "PSS3.PSS_IMUX_B0_8->PSS1_IMUX_B0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_8" }, "PSS3.PSS_IMUX_B0_9->PSS1_IMUX_B0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_9" }, "PSS3.PSS_IMUX_B10_0->PSS1_IMUX_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_0" }, "PSS3.PSS_IMUX_B10_1->PSS1_IMUX_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_1" }, "PSS3.PSS_IMUX_B10_10->PSS1_IMUX_B10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_10" }, "PSS3.PSS_IMUX_B10_11->PSS1_IMUX_B10_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_11" }, "PSS3.PSS_IMUX_B10_12->PSS1_IMUX_B10_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_12" }, "PSS3.PSS_IMUX_B10_13->PSS1_IMUX_B10_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_13" }, "PSS3.PSS_IMUX_B10_14->PSS1_IMUX_B10_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_14" }, "PSS3.PSS_IMUX_B10_15->PSS1_IMUX_B10_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_15" }, "PSS3.PSS_IMUX_B10_16->PSS1_IMUX_B10_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_16" }, "PSS3.PSS_IMUX_B10_17->PSS1_IMUX_B10_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_17" }, "PSS3.PSS_IMUX_B10_18->PSS1_IMUX_B10_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_18" }, "PSS3.PSS_IMUX_B10_19->PSS1_IMUX_B10_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_19" }, "PSS3.PSS_IMUX_B10_2->PSS1_IMUX_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_2" }, "PSS3.PSS_IMUX_B10_3->PSS1_IMUX_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_3" }, "PSS3.PSS_IMUX_B10_4->PSS1_IMUX_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_4" }, "PSS3.PSS_IMUX_B10_5->PSS1_IMUX_B10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_5" }, "PSS3.PSS_IMUX_B10_6->PSS1_IMUX_B10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_6" }, "PSS3.PSS_IMUX_B10_7->PSS1_IMUX_B10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_7" }, "PSS3.PSS_IMUX_B10_8->PSS1_IMUX_B10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_8" }, "PSS3.PSS_IMUX_B10_9->PSS1_IMUX_B10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_9" }, "PSS3.PSS_IMUX_B11_0->PSS1_IMUX_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_0" }, "PSS3.PSS_IMUX_B11_1->PSS1_IMUX_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_1" }, "PSS3.PSS_IMUX_B11_10->PSS1_IMUX_B11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_10" }, "PSS3.PSS_IMUX_B11_11->PSS1_IMUX_B11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_11" }, "PSS3.PSS_IMUX_B11_12->PSS1_IMUX_B11_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_12" }, "PSS3.PSS_IMUX_B11_13->PSS1_IMUX_B11_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_13" }, "PSS3.PSS_IMUX_B11_14->PSS1_IMUX_B11_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_14" }, "PSS3.PSS_IMUX_B11_15->PSS1_IMUX_B11_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_15" }, "PSS3.PSS_IMUX_B11_16->PSS1_IMUX_B11_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_16" }, "PSS3.PSS_IMUX_B11_17->PSS1_IMUX_B11_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_17" }, "PSS3.PSS_IMUX_B11_18->PSS1_IMUX_B11_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_18" }, "PSS3.PSS_IMUX_B11_19->PSS1_IMUX_B11_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_19" }, "PSS3.PSS_IMUX_B11_2->PSS1_IMUX_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_2" }, "PSS3.PSS_IMUX_B11_3->PSS1_IMUX_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_3" }, "PSS3.PSS_IMUX_B11_4->PSS1_IMUX_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_4" }, "PSS3.PSS_IMUX_B11_5->PSS1_IMUX_B11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_5" }, "PSS3.PSS_IMUX_B11_6->PSS1_IMUX_B11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_6" }, "PSS3.PSS_IMUX_B11_7->PSS1_IMUX_B11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_7" }, "PSS3.PSS_IMUX_B11_8->PSS1_IMUX_B11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_8" }, "PSS3.PSS_IMUX_B11_9->PSS1_IMUX_B11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_9" }, "PSS3.PSS_IMUX_B12_0->PSS1_IMUX_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_0" }, "PSS3.PSS_IMUX_B12_1->PSS1_IMUX_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_1" }, "PSS3.PSS_IMUX_B12_10->PSS1_IMUX_B12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_10" }, "PSS3.PSS_IMUX_B12_11->PSS1_IMUX_B12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_11" }, "PSS3.PSS_IMUX_B12_12->PSS1_IMUX_B12_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_12" }, "PSS3.PSS_IMUX_B12_13->PSS1_IMUX_B12_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_13" }, "PSS3.PSS_IMUX_B12_14->PSS1_IMUX_B12_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_14" }, "PSS3.PSS_IMUX_B12_15->PSS1_IMUX_B12_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_15" }, "PSS3.PSS_IMUX_B12_16->PSS1_IMUX_B12_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_16" }, "PSS3.PSS_IMUX_B12_17->PSS1_IMUX_B12_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_17" }, "PSS3.PSS_IMUX_B12_18->PSS1_IMUX_B12_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_18" }, "PSS3.PSS_IMUX_B12_19->PSS1_IMUX_B12_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_19" }, "PSS3.PSS_IMUX_B12_2->PSS1_IMUX_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_2" }, "PSS3.PSS_IMUX_B12_3->PSS1_IMUX_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_3" }, "PSS3.PSS_IMUX_B12_4->PSS1_IMUX_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_4" }, "PSS3.PSS_IMUX_B12_5->PSS1_IMUX_B12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_5" }, "PSS3.PSS_IMUX_B12_6->PSS1_IMUX_B12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_6" }, "PSS3.PSS_IMUX_B12_7->PSS1_IMUX_B12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_7" }, "PSS3.PSS_IMUX_B12_8->PSS1_IMUX_B12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_8" }, "PSS3.PSS_IMUX_B12_9->PSS1_IMUX_B12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_9" }, "PSS3.PSS_IMUX_B13_0->PSS1_IMUX_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_0" }, "PSS3.PSS_IMUX_B13_1->PSS1_IMUX_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_1" }, "PSS3.PSS_IMUX_B13_10->PSS1_IMUX_B13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_10" }, "PSS3.PSS_IMUX_B13_11->PSS1_IMUX_B13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_11" }, "PSS3.PSS_IMUX_B13_12->PSS1_IMUX_B13_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_12" }, "PSS3.PSS_IMUX_B13_13->PSS1_IMUX_B13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_13" }, "PSS3.PSS_IMUX_B13_14->PSS1_IMUX_B13_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_14" }, "PSS3.PSS_IMUX_B13_15->PSS1_IMUX_B13_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_15" }, "PSS3.PSS_IMUX_B13_16->PSS1_IMUX_B13_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_16" }, "PSS3.PSS_IMUX_B13_17->PSS1_IMUX_B13_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_17" }, "PSS3.PSS_IMUX_B13_18->PSS1_IMUX_B13_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_18" }, "PSS3.PSS_IMUX_B13_19->PSS1_IMUX_B13_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_19" }, "PSS3.PSS_IMUX_B13_2->PSS1_IMUX_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_2" }, "PSS3.PSS_IMUX_B13_3->PSS1_IMUX_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_3" }, "PSS3.PSS_IMUX_B13_4->PSS1_IMUX_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_4" }, "PSS3.PSS_IMUX_B13_5->PSS1_IMUX_B13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_5" }, "PSS3.PSS_IMUX_B13_6->PSS1_IMUX_B13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_6" }, "PSS3.PSS_IMUX_B13_7->PSS1_IMUX_B13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_7" }, "PSS3.PSS_IMUX_B13_8->PSS1_IMUX_B13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_8" }, "PSS3.PSS_IMUX_B13_9->PSS1_IMUX_B13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_9" }, "PSS3.PSS_IMUX_B14_0->PSS1_IMUX_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_0" }, "PSS3.PSS_IMUX_B14_1->PSS1_IMUX_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_1" }, "PSS3.PSS_IMUX_B14_10->PSS1_IMUX_B14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_10" }, "PSS3.PSS_IMUX_B14_11->PSS1_IMUX_B14_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_11" }, "PSS3.PSS_IMUX_B14_12->PSS1_IMUX_B14_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_12" }, "PSS3.PSS_IMUX_B14_13->PSS1_IMUX_B14_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_13" }, "PSS3.PSS_IMUX_B14_14->PSS1_IMUX_B14_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_14" }, "PSS3.PSS_IMUX_B14_15->PSS1_IMUX_B14_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_15" }, "PSS3.PSS_IMUX_B14_16->PSS1_IMUX_B14_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_16" }, "PSS3.PSS_IMUX_B14_17->PSS1_IMUX_B14_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_17" }, "PSS3.PSS_IMUX_B14_18->PSS1_IMUX_B14_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_18" }, "PSS3.PSS_IMUX_B14_19->PSS1_IMUX_B14_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_19" }, "PSS3.PSS_IMUX_B14_2->PSS1_IMUX_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_2" }, "PSS3.PSS_IMUX_B14_3->PSS1_IMUX_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_3" }, "PSS3.PSS_IMUX_B14_4->PSS1_IMUX_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_4" }, "PSS3.PSS_IMUX_B14_5->PSS1_IMUX_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_5" }, "PSS3.PSS_IMUX_B14_6->PSS1_IMUX_B14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_6" }, "PSS3.PSS_IMUX_B14_7->PSS1_IMUX_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_7" }, "PSS3.PSS_IMUX_B14_8->PSS1_IMUX_B14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_8" }, "PSS3.PSS_IMUX_B14_9->PSS1_IMUX_B14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_9" }, "PSS3.PSS_IMUX_B15_0->PSS1_IMUX_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_0" }, "PSS3.PSS_IMUX_B15_1->PSS1_IMUX_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_1" }, "PSS3.PSS_IMUX_B15_10->PSS1_IMUX_B15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_10" }, "PSS3.PSS_IMUX_B15_11->PSS1_IMUX_B15_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_11" }, "PSS3.PSS_IMUX_B15_12->PSS1_IMUX_B15_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_12" }, "PSS3.PSS_IMUX_B15_13->PSS1_IMUX_B15_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_13" }, "PSS3.PSS_IMUX_B15_14->PSS1_IMUX_B15_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_14" }, "PSS3.PSS_IMUX_B15_15->PSS1_IMUX_B15_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_15" }, "PSS3.PSS_IMUX_B15_16->PSS1_IMUX_B15_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_16" }, "PSS3.PSS_IMUX_B15_17->PSS1_IMUX_B15_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_17" }, "PSS3.PSS_IMUX_B15_18->PSS1_IMUX_B15_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_18" }, "PSS3.PSS_IMUX_B15_19->PSS1_IMUX_B15_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_19" }, "PSS3.PSS_IMUX_B15_2->PSS1_IMUX_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_2" }, "PSS3.PSS_IMUX_B15_3->PSS1_IMUX_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_3" }, "PSS3.PSS_IMUX_B15_4->PSS1_IMUX_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_4" }, "PSS3.PSS_IMUX_B15_5->PSS1_IMUX_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_5" }, "PSS3.PSS_IMUX_B15_6->PSS1_IMUX_B15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_6" }, "PSS3.PSS_IMUX_B15_7->PSS1_IMUX_B15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_7" }, "PSS3.PSS_IMUX_B15_8->PSS1_IMUX_B15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_8" }, "PSS3.PSS_IMUX_B15_9->PSS1_IMUX_B15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_9" }, "PSS3.PSS_IMUX_B16_0->PSS1_IMUX_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_0" }, "PSS3.PSS_IMUX_B16_1->PSS1_IMUX_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_1" }, "PSS3.PSS_IMUX_B16_10->PSS1_IMUX_B16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_10" }, "PSS3.PSS_IMUX_B16_11->PSS1_IMUX_B16_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_11" }, "PSS3.PSS_IMUX_B16_12->PSS1_IMUX_B16_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_12" }, "PSS3.PSS_IMUX_B16_13->PSS1_IMUX_B16_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_13" }, "PSS3.PSS_IMUX_B16_14->PSS1_IMUX_B16_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_14" }, "PSS3.PSS_IMUX_B16_15->PSS1_IMUX_B16_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_15" }, "PSS3.PSS_IMUX_B16_16->PSS1_IMUX_B16_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_16" }, "PSS3.PSS_IMUX_B16_17->PSS1_IMUX_B16_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_17" }, "PSS3.PSS_IMUX_B16_18->PSS1_IMUX_B16_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_18" }, "PSS3.PSS_IMUX_B16_19->PSS1_IMUX_B16_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_19" }, "PSS3.PSS_IMUX_B16_2->PSS1_IMUX_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_2" }, "PSS3.PSS_IMUX_B16_3->PSS1_IMUX_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_3" }, "PSS3.PSS_IMUX_B16_4->PSS1_IMUX_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_4" }, "PSS3.PSS_IMUX_B16_5->PSS1_IMUX_B16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_5" }, "PSS3.PSS_IMUX_B16_6->PSS1_IMUX_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_6" }, "PSS3.PSS_IMUX_B16_7->PSS1_IMUX_B16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_7" }, "PSS3.PSS_IMUX_B16_8->PSS1_IMUX_B16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_8" }, "PSS3.PSS_IMUX_B16_9->PSS1_IMUX_B16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_9" }, "PSS3.PSS_IMUX_B17_0->PSS1_IMUX_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_0" }, "PSS3.PSS_IMUX_B17_1->PSS1_IMUX_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_1" }, "PSS3.PSS_IMUX_B17_10->PSS1_IMUX_B17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_10" }, "PSS3.PSS_IMUX_B17_11->PSS1_IMUX_B17_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_11" }, "PSS3.PSS_IMUX_B17_12->PSS1_IMUX_B17_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_12" }, "PSS3.PSS_IMUX_B17_13->PSS1_IMUX_B17_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_13" }, "PSS3.PSS_IMUX_B17_14->PSS1_IMUX_B17_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_14" }, "PSS3.PSS_IMUX_B17_15->PSS1_IMUX_B17_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_15" }, "PSS3.PSS_IMUX_B17_16->PSS1_IMUX_B17_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_16" }, "PSS3.PSS_IMUX_B17_17->PSS1_IMUX_B17_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_17" }, "PSS3.PSS_IMUX_B17_18->PSS1_IMUX_B17_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_18" }, "PSS3.PSS_IMUX_B17_19->PSS1_IMUX_B17_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_19" }, "PSS3.PSS_IMUX_B17_2->PSS1_IMUX_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_2" }, "PSS3.PSS_IMUX_B17_3->PSS1_IMUX_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_3" }, "PSS3.PSS_IMUX_B17_4->PSS1_IMUX_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_4" }, "PSS3.PSS_IMUX_B17_5->PSS1_IMUX_B17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_5" }, "PSS3.PSS_IMUX_B17_6->PSS1_IMUX_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_6" }, "PSS3.PSS_IMUX_B17_7->PSS1_IMUX_B17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_7" }, "PSS3.PSS_IMUX_B17_8->PSS1_IMUX_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_8" }, "PSS3.PSS_IMUX_B17_9->PSS1_IMUX_B17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_9" }, "PSS3.PSS_IMUX_B18_0->PSS1_IMUX_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_0" }, "PSS3.PSS_IMUX_B18_1->PSS1_IMUX_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_1" }, "PSS3.PSS_IMUX_B18_10->PSS1_IMUX_B18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_10" }, "PSS3.PSS_IMUX_B18_11->PSS1_IMUX_B18_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_11" }, "PSS3.PSS_IMUX_B18_12->PSS1_IMUX_B18_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_12" }, "PSS3.PSS_IMUX_B18_13->PSS1_IMUX_B18_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_13" }, "PSS3.PSS_IMUX_B18_14->PSS1_IMUX_B18_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_14" }, "PSS3.PSS_IMUX_B18_15->PSS1_IMUX_B18_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_15" }, "PSS3.PSS_IMUX_B18_16->PSS1_IMUX_B18_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_16" }, "PSS3.PSS_IMUX_B18_17->PSS1_IMUX_B18_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_17" }, "PSS3.PSS_IMUX_B18_18->PSS1_IMUX_B18_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_18" }, "PSS3.PSS_IMUX_B18_19->PSS1_IMUX_B18_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_19" }, "PSS3.PSS_IMUX_B18_2->PSS1_IMUX_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_2" }, "PSS3.PSS_IMUX_B18_3->PSS1_IMUX_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_3" }, "PSS3.PSS_IMUX_B18_4->PSS1_IMUX_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_4" }, "PSS3.PSS_IMUX_B18_5->PSS1_IMUX_B18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_5" }, "PSS3.PSS_IMUX_B18_6->PSS1_IMUX_B18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_6" }, "PSS3.PSS_IMUX_B18_7->PSS1_IMUX_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_7" }, "PSS3.PSS_IMUX_B18_8->PSS1_IMUX_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_8" }, "PSS3.PSS_IMUX_B18_9->PSS1_IMUX_B18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_9" }, "PSS3.PSS_IMUX_B19_0->PSS1_IMUX_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_0" }, "PSS3.PSS_IMUX_B19_1->PSS1_IMUX_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_1" }, "PSS3.PSS_IMUX_B19_10->PSS1_IMUX_B19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_10" }, "PSS3.PSS_IMUX_B19_11->PSS1_IMUX_B19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_11" }, "PSS3.PSS_IMUX_B19_12->PSS1_IMUX_B19_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_12" }, "PSS3.PSS_IMUX_B19_13->PSS1_IMUX_B19_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_13" }, "PSS3.PSS_IMUX_B19_14->PSS1_IMUX_B19_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_14" }, "PSS3.PSS_IMUX_B19_15->PSS1_IMUX_B19_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_15" }, "PSS3.PSS_IMUX_B19_16->PSS1_IMUX_B19_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_16" }, "PSS3.PSS_IMUX_B19_17->PSS1_IMUX_B19_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_17" }, "PSS3.PSS_IMUX_B19_18->PSS1_IMUX_B19_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_18" }, "PSS3.PSS_IMUX_B19_19->PSS1_IMUX_B19_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_19" }, "PSS3.PSS_IMUX_B19_2->PSS1_IMUX_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_2" }, "PSS3.PSS_IMUX_B19_3->PSS1_IMUX_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_3" }, "PSS3.PSS_IMUX_B19_4->PSS1_IMUX_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_4" }, "PSS3.PSS_IMUX_B19_5->PSS1_IMUX_B19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_5" }, "PSS3.PSS_IMUX_B19_6->PSS1_IMUX_B19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_6" }, "PSS3.PSS_IMUX_B19_7->PSS1_IMUX_B19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_7" }, "PSS3.PSS_IMUX_B19_8->PSS1_IMUX_B19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_8" }, "PSS3.PSS_IMUX_B19_9->PSS1_IMUX_B19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_9" }, "PSS3.PSS_IMUX_B1_0->PSS1_IMUX_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_0" }, "PSS3.PSS_IMUX_B1_1->PSS1_IMUX_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_1" }, "PSS3.PSS_IMUX_B1_10->PSS1_IMUX_B1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_10" }, "PSS3.PSS_IMUX_B1_11->PSS1_IMUX_B1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_11" }, "PSS3.PSS_IMUX_B1_12->PSS1_IMUX_B1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_12" }, "PSS3.PSS_IMUX_B1_13->PSS1_IMUX_B1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_13" }, "PSS3.PSS_IMUX_B1_14->PSS1_IMUX_B1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_14" }, "PSS3.PSS_IMUX_B1_15->PSS1_IMUX_B1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_15" }, "PSS3.PSS_IMUX_B1_16->PSS1_IMUX_B1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_16" }, "PSS3.PSS_IMUX_B1_17->PSS1_IMUX_B1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_17" }, "PSS3.PSS_IMUX_B1_18->PSS1_IMUX_B1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_18" }, "PSS3.PSS_IMUX_B1_19->PSS1_IMUX_B1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_19" }, "PSS3.PSS_IMUX_B1_2->PSS1_IMUX_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_2" }, "PSS3.PSS_IMUX_B1_3->PSS1_IMUX_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_3" }, "PSS3.PSS_IMUX_B1_4->PSS1_IMUX_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_4" }, "PSS3.PSS_IMUX_B1_5->PSS1_IMUX_B1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_5" }, "PSS3.PSS_IMUX_B1_6->PSS1_IMUX_B1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_6" }, "PSS3.PSS_IMUX_B1_7->PSS1_IMUX_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_7" }, "PSS3.PSS_IMUX_B1_8->PSS1_IMUX_B1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_8" }, "PSS3.PSS_IMUX_B1_9->PSS1_IMUX_B1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_9" }, "PSS3.PSS_IMUX_B20_0->PSS1_IMUX_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_0" }, "PSS3.PSS_IMUX_B20_1->PSS1_IMUX_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_1" }, "PSS3.PSS_IMUX_B20_10->PSS1_IMUX_B20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_10" }, "PSS3.PSS_IMUX_B20_11->PSS1_IMUX_B20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_11" }, "PSS3.PSS_IMUX_B20_12->PSS1_IMUX_B20_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_12" }, "PSS3.PSS_IMUX_B20_13->PSS1_IMUX_B20_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_13" }, "PSS3.PSS_IMUX_B20_14->PSS1_IMUX_B20_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_14" }, "PSS3.PSS_IMUX_B20_15->PSS1_IMUX_B20_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_15" }, "PSS3.PSS_IMUX_B20_16->PSS1_IMUX_B20_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_16" }, "PSS3.PSS_IMUX_B20_17->PSS1_IMUX_B20_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_17" }, "PSS3.PSS_IMUX_B20_18->PSS1_IMUX_B20_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_18" }, "PSS3.PSS_IMUX_B20_19->PSS1_IMUX_B20_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_19" }, "PSS3.PSS_IMUX_B20_2->PSS1_IMUX_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_2" }, "PSS3.PSS_IMUX_B20_3->PSS1_IMUX_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_3" }, "PSS3.PSS_IMUX_B20_4->PSS1_IMUX_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_4" }, "PSS3.PSS_IMUX_B20_5->PSS1_IMUX_B20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_5" }, "PSS3.PSS_IMUX_B20_6->PSS1_IMUX_B20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_6" }, "PSS3.PSS_IMUX_B20_7->PSS1_IMUX_B20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_7" }, "PSS3.PSS_IMUX_B20_8->PSS1_IMUX_B20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_8" }, "PSS3.PSS_IMUX_B20_9->PSS1_IMUX_B20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_9" }, "PSS3.PSS_IMUX_B21_0->PSS1_IMUX_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_0" }, "PSS3.PSS_IMUX_B21_1->PSS1_IMUX_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_1" }, "PSS3.PSS_IMUX_B21_10->PSS1_IMUX_B21_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_10" }, "PSS3.PSS_IMUX_B21_11->PSS1_IMUX_B21_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_11" }, "PSS3.PSS_IMUX_B21_12->PSS1_IMUX_B21_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_12" }, "PSS3.PSS_IMUX_B21_13->PSS1_IMUX_B21_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_13" }, "PSS3.PSS_IMUX_B21_14->PSS1_IMUX_B21_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_14" }, "PSS3.PSS_IMUX_B21_15->PSS1_IMUX_B21_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_15" }, "PSS3.PSS_IMUX_B21_16->PSS1_IMUX_B21_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_16" }, "PSS3.PSS_IMUX_B21_17->PSS1_IMUX_B21_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_17" }, "PSS3.PSS_IMUX_B21_18->PSS1_IMUX_B21_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_18" }, "PSS3.PSS_IMUX_B21_19->PSS1_IMUX_B21_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_19" }, "PSS3.PSS_IMUX_B21_2->PSS1_IMUX_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_2" }, "PSS3.PSS_IMUX_B21_3->PSS1_IMUX_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_3" }, "PSS3.PSS_IMUX_B21_4->PSS1_IMUX_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_4" }, "PSS3.PSS_IMUX_B21_5->PSS1_IMUX_B21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_5" }, "PSS3.PSS_IMUX_B21_6->PSS1_IMUX_B21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_6" }, "PSS3.PSS_IMUX_B21_7->PSS1_IMUX_B21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_7" }, "PSS3.PSS_IMUX_B21_8->PSS1_IMUX_B21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_8" }, "PSS3.PSS_IMUX_B21_9->PSS1_IMUX_B21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_9" }, "PSS3.PSS_IMUX_B22_0->PSS1_IMUX_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_0" }, "PSS3.PSS_IMUX_B22_1->PSS1_IMUX_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_1" }, "PSS3.PSS_IMUX_B22_10->PSS1_IMUX_B22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_10" }, "PSS3.PSS_IMUX_B22_11->PSS1_IMUX_B22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_11" }, "PSS3.PSS_IMUX_B22_12->PSS1_IMUX_B22_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_12" }, "PSS3.PSS_IMUX_B22_13->PSS1_IMUX_B22_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_13" }, "PSS3.PSS_IMUX_B22_14->PSS1_IMUX_B22_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_14" }, "PSS3.PSS_IMUX_B22_15->PSS1_IMUX_B22_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_15" }, "PSS3.PSS_IMUX_B22_16->PSS1_IMUX_B22_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_16" }, "PSS3.PSS_IMUX_B22_17->PSS1_IMUX_B22_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_17" }, "PSS3.PSS_IMUX_B22_18->PSS1_IMUX_B22_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_18" }, "PSS3.PSS_IMUX_B22_19->PSS1_IMUX_B22_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_19" }, "PSS3.PSS_IMUX_B22_2->PSS1_IMUX_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_2" }, "PSS3.PSS_IMUX_B22_3->PSS1_IMUX_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_3" }, "PSS3.PSS_IMUX_B22_4->PSS1_IMUX_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_4" }, "PSS3.PSS_IMUX_B22_5->PSS1_IMUX_B22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_5" }, "PSS3.PSS_IMUX_B22_6->PSS1_IMUX_B22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_6" }, "PSS3.PSS_IMUX_B22_7->PSS1_IMUX_B22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_7" }, "PSS3.PSS_IMUX_B22_8->PSS1_IMUX_B22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_8" }, "PSS3.PSS_IMUX_B22_9->PSS1_IMUX_B22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_9" }, "PSS3.PSS_IMUX_B23_0->PSS1_IMUX_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_0" }, "PSS3.PSS_IMUX_B23_1->PSS1_IMUX_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_1" }, "PSS3.PSS_IMUX_B23_10->PSS1_IMUX_B23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_10" }, "PSS3.PSS_IMUX_B23_11->PSS1_IMUX_B23_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_11" }, "PSS3.PSS_IMUX_B23_12->PSS1_IMUX_B23_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_12" }, "PSS3.PSS_IMUX_B23_13->PSS1_IMUX_B23_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_13" }, "PSS3.PSS_IMUX_B23_14->PSS1_IMUX_B23_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_14" }, "PSS3.PSS_IMUX_B23_15->PSS1_IMUX_B23_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_15" }, "PSS3.PSS_IMUX_B23_16->PSS1_IMUX_B23_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_16" }, "PSS3.PSS_IMUX_B23_17->PSS1_IMUX_B23_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_17" }, "PSS3.PSS_IMUX_B23_18->PSS1_IMUX_B23_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_18" }, "PSS3.PSS_IMUX_B23_19->PSS1_IMUX_B23_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_19" }, "PSS3.PSS_IMUX_B23_2->PSS1_IMUX_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_2" }, "PSS3.PSS_IMUX_B23_3->PSS1_IMUX_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_3" }, "PSS3.PSS_IMUX_B23_4->PSS1_IMUX_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_4" }, "PSS3.PSS_IMUX_B23_5->PSS1_IMUX_B23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_5" }, "PSS3.PSS_IMUX_B23_6->PSS1_IMUX_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_6" }, "PSS3.PSS_IMUX_B23_7->PSS1_IMUX_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_7" }, "PSS3.PSS_IMUX_B23_8->PSS1_IMUX_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_8" }, "PSS3.PSS_IMUX_B23_9->PSS1_IMUX_B23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_9" }, "PSS3.PSS_IMUX_B24_0->PSS1_IMUX_B24_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_0" }, "PSS3.PSS_IMUX_B24_1->PSS1_IMUX_B24_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_1" }, "PSS3.PSS_IMUX_B24_10->PSS1_IMUX_B24_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_10" }, "PSS3.PSS_IMUX_B24_11->PSS1_IMUX_B24_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_11" }, "PSS3.PSS_IMUX_B24_12->PSS1_IMUX_B24_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_12" }, "PSS3.PSS_IMUX_B24_13->PSS1_IMUX_B24_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_13" }, "PSS3.PSS_IMUX_B24_14->PSS1_IMUX_B24_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_14" }, "PSS3.PSS_IMUX_B24_15->PSS1_IMUX_B24_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_15" }, "PSS3.PSS_IMUX_B24_16->PSS1_IMUX_B24_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_16" }, "PSS3.PSS_IMUX_B24_17->PSS1_IMUX_B24_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_17" }, "PSS3.PSS_IMUX_B24_18->PSS1_IMUX_B24_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_18" }, "PSS3.PSS_IMUX_B24_19->PSS1_IMUX_B24_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_19" }, "PSS3.PSS_IMUX_B24_2->PSS1_IMUX_B24_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_2" }, "PSS3.PSS_IMUX_B24_3->PSS1_IMUX_B24_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_3" }, "PSS3.PSS_IMUX_B24_4->PSS1_IMUX_B24_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_4" }, "PSS3.PSS_IMUX_B24_5->PSS1_IMUX_B24_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_5" }, "PSS3.PSS_IMUX_B24_6->PSS1_IMUX_B24_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_6" }, "PSS3.PSS_IMUX_B24_7->PSS1_IMUX_B24_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_7" }, "PSS3.PSS_IMUX_B24_8->PSS1_IMUX_B24_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_8" }, "PSS3.PSS_IMUX_B24_9->PSS1_IMUX_B24_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B24_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_9" }, "PSS3.PSS_IMUX_B25_0->PSS1_IMUX_B25_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_0" }, "PSS3.PSS_IMUX_B25_1->PSS1_IMUX_B25_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_1" }, "PSS3.PSS_IMUX_B25_10->PSS1_IMUX_B25_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_10" }, "PSS3.PSS_IMUX_B25_11->PSS1_IMUX_B25_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_11" }, "PSS3.PSS_IMUX_B25_12->PSS1_IMUX_B25_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_12" }, "PSS3.PSS_IMUX_B25_13->PSS1_IMUX_B25_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_13" }, "PSS3.PSS_IMUX_B25_14->PSS1_IMUX_B25_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_14" }, "PSS3.PSS_IMUX_B25_15->PSS1_IMUX_B25_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_15" }, "PSS3.PSS_IMUX_B25_16->PSS1_IMUX_B25_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_16" }, "PSS3.PSS_IMUX_B25_17->PSS1_IMUX_B25_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_17" }, "PSS3.PSS_IMUX_B25_18->PSS1_IMUX_B25_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_18" }, "PSS3.PSS_IMUX_B25_19->PSS1_IMUX_B25_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_19" }, "PSS3.PSS_IMUX_B25_2->PSS1_IMUX_B25_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_2" }, "PSS3.PSS_IMUX_B25_3->PSS1_IMUX_B25_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_3" }, "PSS3.PSS_IMUX_B25_4->PSS1_IMUX_B25_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_4" }, "PSS3.PSS_IMUX_B25_5->PSS1_IMUX_B25_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_5" }, "PSS3.PSS_IMUX_B25_6->PSS1_IMUX_B25_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_6" }, "PSS3.PSS_IMUX_B25_7->PSS1_IMUX_B25_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_7" }, "PSS3.PSS_IMUX_B25_8->PSS1_IMUX_B25_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_8" }, "PSS3.PSS_IMUX_B25_9->PSS1_IMUX_B25_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B25_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_9" }, "PSS3.PSS_IMUX_B26_0->PSS1_IMUX_B26_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_0" }, "PSS3.PSS_IMUX_B26_1->PSS1_IMUX_B26_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_1" }, "PSS3.PSS_IMUX_B26_10->PSS1_IMUX_B26_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_10" }, "PSS3.PSS_IMUX_B26_11->PSS1_IMUX_B26_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_11" }, "PSS3.PSS_IMUX_B26_12->PSS1_IMUX_B26_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_12" }, "PSS3.PSS_IMUX_B26_13->PSS1_IMUX_B26_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_13" }, "PSS3.PSS_IMUX_B26_14->PSS1_IMUX_B26_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_14" }, "PSS3.PSS_IMUX_B26_15->PSS1_IMUX_B26_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_15" }, "PSS3.PSS_IMUX_B26_16->PSS1_IMUX_B26_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_16" }, "PSS3.PSS_IMUX_B26_17->PSS1_IMUX_B26_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_17" }, "PSS3.PSS_IMUX_B26_18->PSS1_IMUX_B26_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_18" }, "PSS3.PSS_IMUX_B26_19->PSS1_IMUX_B26_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_19" }, "PSS3.PSS_IMUX_B26_2->PSS1_IMUX_B26_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_2" }, "PSS3.PSS_IMUX_B26_3->PSS1_IMUX_B26_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_3" }, "PSS3.PSS_IMUX_B26_4->PSS1_IMUX_B26_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_4" }, "PSS3.PSS_IMUX_B26_5->PSS1_IMUX_B26_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_5" }, "PSS3.PSS_IMUX_B26_6->PSS1_IMUX_B26_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_6" }, "PSS3.PSS_IMUX_B26_7->PSS1_IMUX_B26_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_7" }, "PSS3.PSS_IMUX_B26_8->PSS1_IMUX_B26_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_8" }, "PSS3.PSS_IMUX_B26_9->PSS1_IMUX_B26_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B26_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_9" }, "PSS3.PSS_IMUX_B27_0->PSS1_IMUX_B27_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_0" }, "PSS3.PSS_IMUX_B27_1->PSS1_IMUX_B27_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_1" }, "PSS3.PSS_IMUX_B27_10->PSS1_IMUX_B27_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_10" }, "PSS3.PSS_IMUX_B27_11->PSS1_IMUX_B27_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_11" }, "PSS3.PSS_IMUX_B27_12->PSS1_IMUX_B27_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_12" }, "PSS3.PSS_IMUX_B27_13->PSS1_IMUX_B27_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_13" }, "PSS3.PSS_IMUX_B27_14->PSS1_IMUX_B27_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_14" }, "PSS3.PSS_IMUX_B27_15->PSS1_IMUX_B27_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_15" }, "PSS3.PSS_IMUX_B27_16->PSS1_IMUX_B27_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_16" }, "PSS3.PSS_IMUX_B27_17->PSS1_IMUX_B27_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_17" }, "PSS3.PSS_IMUX_B27_18->PSS1_IMUX_B27_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_18" }, "PSS3.PSS_IMUX_B27_19->PSS1_IMUX_B27_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_19" }, "PSS3.PSS_IMUX_B27_2->PSS1_IMUX_B27_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_2" }, "PSS3.PSS_IMUX_B27_3->PSS1_IMUX_B27_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_3" }, "PSS3.PSS_IMUX_B27_4->PSS1_IMUX_B27_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_4" }, "PSS3.PSS_IMUX_B27_5->PSS1_IMUX_B27_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_5" }, "PSS3.PSS_IMUX_B27_6->PSS1_IMUX_B27_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_6" }, "PSS3.PSS_IMUX_B27_7->PSS1_IMUX_B27_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_7" }, "PSS3.PSS_IMUX_B27_8->PSS1_IMUX_B27_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_8" }, "PSS3.PSS_IMUX_B27_9->PSS1_IMUX_B27_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B27_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_9" }, "PSS3.PSS_IMUX_B28_0->PSS1_IMUX_B28_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_0" }, "PSS3.PSS_IMUX_B28_1->PSS1_IMUX_B28_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_1" }, "PSS3.PSS_IMUX_B28_10->PSS1_IMUX_B28_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_10" }, "PSS3.PSS_IMUX_B28_11->PSS1_IMUX_B28_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_11" }, "PSS3.PSS_IMUX_B28_12->PSS1_IMUX_B28_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_12" }, "PSS3.PSS_IMUX_B28_13->PSS1_IMUX_B28_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_13" }, "PSS3.PSS_IMUX_B28_14->PSS1_IMUX_B28_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_14" }, "PSS3.PSS_IMUX_B28_15->PSS1_IMUX_B28_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_15" }, "PSS3.PSS_IMUX_B28_16->PSS1_IMUX_B28_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_16" }, "PSS3.PSS_IMUX_B28_17->PSS1_IMUX_B28_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_17" }, "PSS3.PSS_IMUX_B28_18->PSS1_IMUX_B28_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_18" }, "PSS3.PSS_IMUX_B28_19->PSS1_IMUX_B28_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_19" }, "PSS3.PSS_IMUX_B28_2->PSS1_IMUX_B28_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_2" }, "PSS3.PSS_IMUX_B28_3->PSS1_IMUX_B28_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_3" }, "PSS3.PSS_IMUX_B28_4->PSS1_IMUX_B28_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_4" }, "PSS3.PSS_IMUX_B28_5->PSS1_IMUX_B28_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_5" }, "PSS3.PSS_IMUX_B28_6->PSS1_IMUX_B28_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_6" }, "PSS3.PSS_IMUX_B28_7->PSS1_IMUX_B28_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_7" }, "PSS3.PSS_IMUX_B28_8->PSS1_IMUX_B28_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_8" }, "PSS3.PSS_IMUX_B28_9->PSS1_IMUX_B28_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B28_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_9" }, "PSS3.PSS_IMUX_B29_0->PSS1_IMUX_B29_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_0" }, "PSS3.PSS_IMUX_B29_1->PSS1_IMUX_B29_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_1" }, "PSS3.PSS_IMUX_B29_10->PSS1_IMUX_B29_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_10" }, "PSS3.PSS_IMUX_B29_11->PSS1_IMUX_B29_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_11" }, "PSS3.PSS_IMUX_B29_12->PSS1_IMUX_B29_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_12" }, "PSS3.PSS_IMUX_B29_13->PSS1_IMUX_B29_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_13" }, "PSS3.PSS_IMUX_B29_14->PSS1_IMUX_B29_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_14" }, "PSS3.PSS_IMUX_B29_15->PSS1_IMUX_B29_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_15" }, "PSS3.PSS_IMUX_B29_16->PSS1_IMUX_B29_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_16" }, "PSS3.PSS_IMUX_B29_17->PSS1_IMUX_B29_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_17" }, "PSS3.PSS_IMUX_B29_18->PSS1_IMUX_B29_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_18" }, "PSS3.PSS_IMUX_B29_19->PSS1_IMUX_B29_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_19" }, "PSS3.PSS_IMUX_B29_2->PSS1_IMUX_B29_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_2" }, "PSS3.PSS_IMUX_B29_3->PSS1_IMUX_B29_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_3" }, "PSS3.PSS_IMUX_B29_4->PSS1_IMUX_B29_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_4" }, "PSS3.PSS_IMUX_B29_5->PSS1_IMUX_B29_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_5" }, "PSS3.PSS_IMUX_B29_6->PSS1_IMUX_B29_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_6" }, "PSS3.PSS_IMUX_B29_7->PSS1_IMUX_B29_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_7" }, "PSS3.PSS_IMUX_B29_8->PSS1_IMUX_B29_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_8" }, "PSS3.PSS_IMUX_B29_9->PSS1_IMUX_B29_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B29_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_9" }, "PSS3.PSS_IMUX_B2_0->PSS1_IMUX_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_0" }, "PSS3.PSS_IMUX_B2_1->PSS1_IMUX_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_1" }, "PSS3.PSS_IMUX_B2_10->PSS1_IMUX_B2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_10" }, "PSS3.PSS_IMUX_B2_11->PSS1_IMUX_B2_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_11" }, "PSS3.PSS_IMUX_B2_12->PSS1_IMUX_B2_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_12" }, "PSS3.PSS_IMUX_B2_13->PSS1_IMUX_B2_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_13" }, "PSS3.PSS_IMUX_B2_14->PSS1_IMUX_B2_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_14" }, "PSS3.PSS_IMUX_B2_15->PSS1_IMUX_B2_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_15" }, "PSS3.PSS_IMUX_B2_16->PSS1_IMUX_B2_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_16" }, "PSS3.PSS_IMUX_B2_17->PSS1_IMUX_B2_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_17" }, "PSS3.PSS_IMUX_B2_18->PSS1_IMUX_B2_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_18" }, "PSS3.PSS_IMUX_B2_19->PSS1_IMUX_B2_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_19" }, "PSS3.PSS_IMUX_B2_2->PSS1_IMUX_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_2" }, "PSS3.PSS_IMUX_B2_3->PSS1_IMUX_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_3" }, "PSS3.PSS_IMUX_B2_4->PSS1_IMUX_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_4" }, "PSS3.PSS_IMUX_B2_5->PSS1_IMUX_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_5" }, "PSS3.PSS_IMUX_B2_6->PSS1_IMUX_B2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_6" }, "PSS3.PSS_IMUX_B2_7->PSS1_IMUX_B2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_7" }, "PSS3.PSS_IMUX_B2_8->PSS1_IMUX_B2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_8" }, "PSS3.PSS_IMUX_B2_9->PSS1_IMUX_B2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_9" }, "PSS3.PSS_IMUX_B30_0->PSS1_IMUX_B30_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_0" }, "PSS3.PSS_IMUX_B30_1->PSS1_IMUX_B30_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_1" }, "PSS3.PSS_IMUX_B30_10->PSS1_IMUX_B30_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_10" }, "PSS3.PSS_IMUX_B30_11->PSS1_IMUX_B30_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_11" }, "PSS3.PSS_IMUX_B30_12->PSS1_IMUX_B30_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_12" }, "PSS3.PSS_IMUX_B30_13->PSS1_IMUX_B30_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_13" }, "PSS3.PSS_IMUX_B30_14->PSS1_IMUX_B30_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_14" }, "PSS3.PSS_IMUX_B30_15->PSS1_IMUX_B30_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_15" }, "PSS3.PSS_IMUX_B30_16->PSS1_IMUX_B30_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_16" }, "PSS3.PSS_IMUX_B30_17->PSS1_IMUX_B30_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_17" }, "PSS3.PSS_IMUX_B30_18->PSS1_IMUX_B30_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_18" }, "PSS3.PSS_IMUX_B30_19->PSS1_IMUX_B30_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_19" }, "PSS3.PSS_IMUX_B30_2->PSS1_IMUX_B30_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_2" }, "PSS3.PSS_IMUX_B30_3->PSS1_IMUX_B30_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_3" }, "PSS3.PSS_IMUX_B30_4->PSS1_IMUX_B30_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_4" }, "PSS3.PSS_IMUX_B30_5->PSS1_IMUX_B30_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_5" }, "PSS3.PSS_IMUX_B30_6->PSS1_IMUX_B30_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_6" }, "PSS3.PSS_IMUX_B30_7->PSS1_IMUX_B30_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_7" }, "PSS3.PSS_IMUX_B30_8->PSS1_IMUX_B30_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_8" }, "PSS3.PSS_IMUX_B30_9->PSS1_IMUX_B30_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B30_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_9" }, "PSS3.PSS_IMUX_B31_0->PSS1_IMUX_B31_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_0" }, "PSS3.PSS_IMUX_B31_1->PSS1_IMUX_B31_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_1" }, "PSS3.PSS_IMUX_B31_10->PSS1_IMUX_B31_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_10" }, "PSS3.PSS_IMUX_B31_11->PSS1_IMUX_B31_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_11" }, "PSS3.PSS_IMUX_B31_12->PSS1_IMUX_B31_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_12" }, "PSS3.PSS_IMUX_B31_13->PSS1_IMUX_B31_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_13" }, "PSS3.PSS_IMUX_B31_14->PSS1_IMUX_B31_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_14" }, "PSS3.PSS_IMUX_B31_15->PSS1_IMUX_B31_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_15" }, "PSS3.PSS_IMUX_B31_16->PSS1_IMUX_B31_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_16" }, "PSS3.PSS_IMUX_B31_17->PSS1_IMUX_B31_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_17" }, "PSS3.PSS_IMUX_B31_18->PSS1_IMUX_B31_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_18" }, "PSS3.PSS_IMUX_B31_19->PSS1_IMUX_B31_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_19" }, "PSS3.PSS_IMUX_B31_2->PSS1_IMUX_B31_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_2" }, "PSS3.PSS_IMUX_B31_3->PSS1_IMUX_B31_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_3" }, "PSS3.PSS_IMUX_B31_4->PSS1_IMUX_B31_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_4" }, "PSS3.PSS_IMUX_B31_5->PSS1_IMUX_B31_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_5" }, "PSS3.PSS_IMUX_B31_6->PSS1_IMUX_B31_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_6" }, "PSS3.PSS_IMUX_B31_7->PSS1_IMUX_B31_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_7" }, "PSS3.PSS_IMUX_B31_8->PSS1_IMUX_B31_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_8" }, "PSS3.PSS_IMUX_B31_9->PSS1_IMUX_B31_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B31_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_9" }, "PSS3.PSS_IMUX_B32_0->PSS1_IMUX_B32_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_0" }, "PSS3.PSS_IMUX_B32_1->PSS1_IMUX_B32_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_1" }, "PSS3.PSS_IMUX_B32_10->PSS1_IMUX_B32_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_10" }, "PSS3.PSS_IMUX_B32_11->PSS1_IMUX_B32_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_11" }, "PSS3.PSS_IMUX_B32_12->PSS1_IMUX_B32_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_12" }, "PSS3.PSS_IMUX_B32_13->PSS1_IMUX_B32_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_13" }, "PSS3.PSS_IMUX_B32_14->PSS1_IMUX_B32_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_14" }, "PSS3.PSS_IMUX_B32_15->PSS1_IMUX_B32_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_15" }, "PSS3.PSS_IMUX_B32_16->PSS1_IMUX_B32_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_16" }, "PSS3.PSS_IMUX_B32_17->PSS1_IMUX_B32_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_17" }, "PSS3.PSS_IMUX_B32_18->PSS1_IMUX_B32_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_18" }, "PSS3.PSS_IMUX_B32_19->PSS1_IMUX_B32_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_19" }, "PSS3.PSS_IMUX_B32_2->PSS1_IMUX_B32_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_2" }, "PSS3.PSS_IMUX_B32_3->PSS1_IMUX_B32_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_3" }, "PSS3.PSS_IMUX_B32_4->PSS1_IMUX_B32_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_4" }, "PSS3.PSS_IMUX_B32_5->PSS1_IMUX_B32_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_5" }, "PSS3.PSS_IMUX_B32_6->PSS1_IMUX_B32_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_6" }, "PSS3.PSS_IMUX_B32_7->PSS1_IMUX_B32_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_7" }, "PSS3.PSS_IMUX_B32_8->PSS1_IMUX_B32_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_8" }, "PSS3.PSS_IMUX_B32_9->PSS1_IMUX_B32_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B32_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_9" }, "PSS3.PSS_IMUX_B33_0->PSS1_IMUX_B33_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_0" }, "PSS3.PSS_IMUX_B33_1->PSS1_IMUX_B33_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_1" }, "PSS3.PSS_IMUX_B33_10->PSS1_IMUX_B33_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_10" }, "PSS3.PSS_IMUX_B33_11->PSS1_IMUX_B33_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_11" }, "PSS3.PSS_IMUX_B33_12->PSS1_IMUX_B33_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_12" }, "PSS3.PSS_IMUX_B33_13->PSS1_IMUX_B33_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_13" }, "PSS3.PSS_IMUX_B33_14->PSS1_IMUX_B33_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_14" }, "PSS3.PSS_IMUX_B33_15->PSS1_IMUX_B33_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_15" }, "PSS3.PSS_IMUX_B33_16->PSS1_IMUX_B33_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_16" }, "PSS3.PSS_IMUX_B33_17->PSS1_IMUX_B33_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_17" }, "PSS3.PSS_IMUX_B33_18->PSS1_IMUX_B33_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_18" }, "PSS3.PSS_IMUX_B33_19->PSS1_IMUX_B33_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_19" }, "PSS3.PSS_IMUX_B33_2->PSS1_IMUX_B33_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_2" }, "PSS3.PSS_IMUX_B33_3->PSS1_IMUX_B33_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_3" }, "PSS3.PSS_IMUX_B33_4->PSS1_IMUX_B33_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_4" }, "PSS3.PSS_IMUX_B33_5->PSS1_IMUX_B33_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_5" }, "PSS3.PSS_IMUX_B33_6->PSS1_IMUX_B33_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_6" }, "PSS3.PSS_IMUX_B33_7->PSS1_IMUX_B33_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_7" }, "PSS3.PSS_IMUX_B33_8->PSS1_IMUX_B33_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_8" }, "PSS3.PSS_IMUX_B33_9->PSS1_IMUX_B33_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B33_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_9" }, "PSS3.PSS_IMUX_B34_0->PSS1_IMUX_B34_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_0" }, "PSS3.PSS_IMUX_B34_1->PSS1_IMUX_B34_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_1" }, "PSS3.PSS_IMUX_B34_10->PSS1_IMUX_B34_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_10" }, "PSS3.PSS_IMUX_B34_11->PSS1_IMUX_B34_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_11" }, "PSS3.PSS_IMUX_B34_12->PSS1_IMUX_B34_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_12" }, "PSS3.PSS_IMUX_B34_13->PSS1_IMUX_B34_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_13" }, "PSS3.PSS_IMUX_B34_14->PSS1_IMUX_B34_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_14" }, "PSS3.PSS_IMUX_B34_15->PSS1_IMUX_B34_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_15" }, "PSS3.PSS_IMUX_B34_16->PSS1_IMUX_B34_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_16" }, "PSS3.PSS_IMUX_B34_17->PSS1_IMUX_B34_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_17" }, "PSS3.PSS_IMUX_B34_18->PSS1_IMUX_B34_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_18" }, "PSS3.PSS_IMUX_B34_19->PSS1_IMUX_B34_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_19" }, "PSS3.PSS_IMUX_B34_2->PSS1_IMUX_B34_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_2" }, "PSS3.PSS_IMUX_B34_3->PSS1_IMUX_B34_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_3" }, "PSS3.PSS_IMUX_B34_4->PSS1_IMUX_B34_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_4" }, "PSS3.PSS_IMUX_B34_5->PSS1_IMUX_B34_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_5" }, "PSS3.PSS_IMUX_B34_6->PSS1_IMUX_B34_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_6" }, "PSS3.PSS_IMUX_B34_7->PSS1_IMUX_B34_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_7" }, "PSS3.PSS_IMUX_B34_8->PSS1_IMUX_B34_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_8" }, "PSS3.PSS_IMUX_B34_9->PSS1_IMUX_B34_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B34_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_9" }, "PSS3.PSS_IMUX_B35_0->PSS1_IMUX_B35_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_0" }, "PSS3.PSS_IMUX_B35_1->PSS1_IMUX_B35_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_1" }, "PSS3.PSS_IMUX_B35_10->PSS1_IMUX_B35_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_10" }, "PSS3.PSS_IMUX_B35_11->PSS1_IMUX_B35_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_11" }, "PSS3.PSS_IMUX_B35_12->PSS1_IMUX_B35_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_12" }, "PSS3.PSS_IMUX_B35_13->PSS1_IMUX_B35_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_13" }, "PSS3.PSS_IMUX_B35_14->PSS1_IMUX_B35_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_14" }, "PSS3.PSS_IMUX_B35_15->PSS1_IMUX_B35_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_15" }, "PSS3.PSS_IMUX_B35_16->PSS1_IMUX_B35_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_16" }, "PSS3.PSS_IMUX_B35_17->PSS1_IMUX_B35_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_17" }, "PSS3.PSS_IMUX_B35_18->PSS1_IMUX_B35_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_18" }, "PSS3.PSS_IMUX_B35_19->PSS1_IMUX_B35_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_19" }, "PSS3.PSS_IMUX_B35_2->PSS1_IMUX_B35_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_2" }, "PSS3.PSS_IMUX_B35_3->PSS1_IMUX_B35_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_3" }, "PSS3.PSS_IMUX_B35_4->PSS1_IMUX_B35_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_4" }, "PSS3.PSS_IMUX_B35_5->PSS1_IMUX_B35_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_5" }, "PSS3.PSS_IMUX_B35_6->PSS1_IMUX_B35_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_6" }, "PSS3.PSS_IMUX_B35_7->PSS1_IMUX_B35_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_7" }, "PSS3.PSS_IMUX_B35_8->PSS1_IMUX_B35_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_8" }, "PSS3.PSS_IMUX_B35_9->PSS1_IMUX_B35_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B35_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_9" }, "PSS3.PSS_IMUX_B36_0->PSS1_IMUX_B36_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_0" }, "PSS3.PSS_IMUX_B36_1->PSS1_IMUX_B36_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_1" }, "PSS3.PSS_IMUX_B36_10->PSS1_IMUX_B36_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_10" }, "PSS3.PSS_IMUX_B36_11->PSS1_IMUX_B36_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_11" }, "PSS3.PSS_IMUX_B36_12->PSS1_IMUX_B36_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_12" }, "PSS3.PSS_IMUX_B36_13->PSS1_IMUX_B36_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_13" }, "PSS3.PSS_IMUX_B36_14->PSS1_IMUX_B36_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_14" }, "PSS3.PSS_IMUX_B36_15->PSS1_IMUX_B36_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_15" }, "PSS3.PSS_IMUX_B36_16->PSS1_IMUX_B36_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_16" }, "PSS3.PSS_IMUX_B36_17->PSS1_IMUX_B36_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_17" }, "PSS3.PSS_IMUX_B36_18->PSS1_IMUX_B36_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_18" }, "PSS3.PSS_IMUX_B36_19->PSS1_IMUX_B36_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_19" }, "PSS3.PSS_IMUX_B36_2->PSS1_IMUX_B36_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_2" }, "PSS3.PSS_IMUX_B36_3->PSS1_IMUX_B36_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_3" }, "PSS3.PSS_IMUX_B36_4->PSS1_IMUX_B36_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_4" }, "PSS3.PSS_IMUX_B36_5->PSS1_IMUX_B36_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_5" }, "PSS3.PSS_IMUX_B36_6->PSS1_IMUX_B36_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_6" }, "PSS3.PSS_IMUX_B36_7->PSS1_IMUX_B36_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_7" }, "PSS3.PSS_IMUX_B36_8->PSS1_IMUX_B36_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_8" }, "PSS3.PSS_IMUX_B36_9->PSS1_IMUX_B36_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B36_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_9" }, "PSS3.PSS_IMUX_B37_0->PSS1_IMUX_B37_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_0" }, "PSS3.PSS_IMUX_B37_1->PSS1_IMUX_B37_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_1" }, "PSS3.PSS_IMUX_B37_10->PSS1_IMUX_B37_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_10" }, "PSS3.PSS_IMUX_B37_11->PSS1_IMUX_B37_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_11" }, "PSS3.PSS_IMUX_B37_12->PSS1_IMUX_B37_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_12" }, "PSS3.PSS_IMUX_B37_13->PSS1_IMUX_B37_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_13" }, "PSS3.PSS_IMUX_B37_14->PSS1_IMUX_B37_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_14" }, "PSS3.PSS_IMUX_B37_15->PSS1_IMUX_B37_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_15" }, "PSS3.PSS_IMUX_B37_16->PSS1_IMUX_B37_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_16" }, "PSS3.PSS_IMUX_B37_17->PSS1_IMUX_B37_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_17" }, "PSS3.PSS_IMUX_B37_18->PSS1_IMUX_B37_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_18" }, "PSS3.PSS_IMUX_B37_19->PSS1_IMUX_B37_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_19" }, "PSS3.PSS_IMUX_B37_2->PSS1_IMUX_B37_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_2" }, "PSS3.PSS_IMUX_B37_3->PSS1_IMUX_B37_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_3" }, "PSS3.PSS_IMUX_B37_4->PSS1_IMUX_B37_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_4" }, "PSS3.PSS_IMUX_B37_5->PSS1_IMUX_B37_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_5" }, "PSS3.PSS_IMUX_B37_6->PSS1_IMUX_B37_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_6" }, "PSS3.PSS_IMUX_B37_7->PSS1_IMUX_B37_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_7" }, "PSS3.PSS_IMUX_B37_8->PSS1_IMUX_B37_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_8" }, "PSS3.PSS_IMUX_B37_9->PSS1_IMUX_B37_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B37_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_9" }, "PSS3.PSS_IMUX_B38_0->PSS1_IMUX_B38_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_0" }, "PSS3.PSS_IMUX_B38_1->PSS1_IMUX_B38_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_1" }, "PSS3.PSS_IMUX_B38_10->PSS1_IMUX_B38_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_10" }, "PSS3.PSS_IMUX_B38_11->PSS1_IMUX_B38_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_11" }, "PSS3.PSS_IMUX_B38_12->PSS1_IMUX_B38_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_12" }, "PSS3.PSS_IMUX_B38_13->PSS1_IMUX_B38_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_13" }, "PSS3.PSS_IMUX_B38_14->PSS1_IMUX_B38_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_14" }, "PSS3.PSS_IMUX_B38_15->PSS1_IMUX_B38_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_15" }, "PSS3.PSS_IMUX_B38_16->PSS1_IMUX_B38_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_16" }, "PSS3.PSS_IMUX_B38_17->PSS1_IMUX_B38_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_17" }, "PSS3.PSS_IMUX_B38_18->PSS1_IMUX_B38_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_18" }, "PSS3.PSS_IMUX_B38_19->PSS1_IMUX_B38_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_19" }, "PSS3.PSS_IMUX_B38_2->PSS1_IMUX_B38_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_2" }, "PSS3.PSS_IMUX_B38_3->PSS1_IMUX_B38_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_3" }, "PSS3.PSS_IMUX_B38_4->PSS1_IMUX_B38_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_4" }, "PSS3.PSS_IMUX_B38_5->PSS1_IMUX_B38_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_5" }, "PSS3.PSS_IMUX_B38_6->PSS1_IMUX_B38_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_6" }, "PSS3.PSS_IMUX_B38_7->PSS1_IMUX_B38_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_7" }, "PSS3.PSS_IMUX_B38_8->PSS1_IMUX_B38_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_8" }, "PSS3.PSS_IMUX_B38_9->PSS1_IMUX_B38_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B38_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_9" }, "PSS3.PSS_IMUX_B39_0->PSS1_IMUX_B39_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_0" }, "PSS3.PSS_IMUX_B39_1->PSS1_IMUX_B39_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_1" }, "PSS3.PSS_IMUX_B39_10->PSS1_IMUX_B39_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_10" }, "PSS3.PSS_IMUX_B39_11->PSS1_IMUX_B39_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_11" }, "PSS3.PSS_IMUX_B39_12->PSS1_IMUX_B39_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_12" }, "PSS3.PSS_IMUX_B39_13->PSS1_IMUX_B39_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_13" }, "PSS3.PSS_IMUX_B39_14->PSS1_IMUX_B39_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_14" }, "PSS3.PSS_IMUX_B39_15->PSS1_IMUX_B39_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_15" }, "PSS3.PSS_IMUX_B39_16->PSS1_IMUX_B39_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_16" }, "PSS3.PSS_IMUX_B39_17->PSS1_IMUX_B39_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_17" }, "PSS3.PSS_IMUX_B39_18->PSS1_IMUX_B39_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_18" }, "PSS3.PSS_IMUX_B39_19->PSS1_IMUX_B39_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_19" }, "PSS3.PSS_IMUX_B39_2->PSS1_IMUX_B39_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_2" }, "PSS3.PSS_IMUX_B39_3->PSS1_IMUX_B39_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_3" }, "PSS3.PSS_IMUX_B39_4->PSS1_IMUX_B39_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_4" }, "PSS3.PSS_IMUX_B39_5->PSS1_IMUX_B39_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_5" }, "PSS3.PSS_IMUX_B39_6->PSS1_IMUX_B39_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_6" }, "PSS3.PSS_IMUX_B39_7->PSS1_IMUX_B39_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_7" }, "PSS3.PSS_IMUX_B39_8->PSS1_IMUX_B39_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_8" }, "PSS3.PSS_IMUX_B39_9->PSS1_IMUX_B39_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B39_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_9" }, "PSS3.PSS_IMUX_B3_0->PSS1_IMUX_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_0" }, "PSS3.PSS_IMUX_B3_1->PSS1_IMUX_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_1" }, "PSS3.PSS_IMUX_B3_10->PSS1_IMUX_B3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_10" }, "PSS3.PSS_IMUX_B3_11->PSS1_IMUX_B3_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_11" }, "PSS3.PSS_IMUX_B3_12->PSS1_IMUX_B3_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_12" }, "PSS3.PSS_IMUX_B3_13->PSS1_IMUX_B3_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_13" }, "PSS3.PSS_IMUX_B3_14->PSS1_IMUX_B3_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_14" }, "PSS3.PSS_IMUX_B3_15->PSS1_IMUX_B3_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_15" }, "PSS3.PSS_IMUX_B3_16->PSS1_IMUX_B3_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_16" }, "PSS3.PSS_IMUX_B3_17->PSS1_IMUX_B3_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_17" }, "PSS3.PSS_IMUX_B3_18->PSS1_IMUX_B3_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_18" }, "PSS3.PSS_IMUX_B3_19->PSS1_IMUX_B3_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_19" }, "PSS3.PSS_IMUX_B3_2->PSS1_IMUX_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_2" }, "PSS3.PSS_IMUX_B3_3->PSS1_IMUX_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_3" }, "PSS3.PSS_IMUX_B3_4->PSS1_IMUX_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_4" }, "PSS3.PSS_IMUX_B3_5->PSS1_IMUX_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_5" }, "PSS3.PSS_IMUX_B3_6->PSS1_IMUX_B3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_6" }, "PSS3.PSS_IMUX_B3_7->PSS1_IMUX_B3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_7" }, "PSS3.PSS_IMUX_B3_8->PSS1_IMUX_B3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_8" }, "PSS3.PSS_IMUX_B3_9->PSS1_IMUX_B3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_9" }, "PSS3.PSS_IMUX_B40_0->PSS1_IMUX_B40_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_0" }, "PSS3.PSS_IMUX_B40_1->PSS1_IMUX_B40_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_1" }, "PSS3.PSS_IMUX_B40_10->PSS1_IMUX_B40_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_10" }, "PSS3.PSS_IMUX_B40_11->PSS1_IMUX_B40_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_11" }, "PSS3.PSS_IMUX_B40_12->PSS1_IMUX_B40_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_12" }, "PSS3.PSS_IMUX_B40_13->PSS1_IMUX_B40_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_13" }, "PSS3.PSS_IMUX_B40_14->PSS1_IMUX_B40_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_14" }, "PSS3.PSS_IMUX_B40_15->PSS1_IMUX_B40_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_15" }, "PSS3.PSS_IMUX_B40_16->PSS1_IMUX_B40_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_16" }, "PSS3.PSS_IMUX_B40_17->PSS1_IMUX_B40_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_17" }, "PSS3.PSS_IMUX_B40_18->PSS1_IMUX_B40_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_18" }, "PSS3.PSS_IMUX_B40_19->PSS1_IMUX_B40_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_19" }, "PSS3.PSS_IMUX_B40_2->PSS1_IMUX_B40_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_2" }, "PSS3.PSS_IMUX_B40_3->PSS1_IMUX_B40_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_3" }, "PSS3.PSS_IMUX_B40_4->PSS1_IMUX_B40_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_4" }, "PSS3.PSS_IMUX_B40_5->PSS1_IMUX_B40_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_5" }, "PSS3.PSS_IMUX_B40_6->PSS1_IMUX_B40_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_6" }, "PSS3.PSS_IMUX_B40_7->PSS1_IMUX_B40_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_7" }, "PSS3.PSS_IMUX_B40_8->PSS1_IMUX_B40_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_8" }, "PSS3.PSS_IMUX_B40_9->PSS1_IMUX_B40_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B40_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_9" }, "PSS3.PSS_IMUX_B41_0->PSS1_IMUX_B41_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_0" }, "PSS3.PSS_IMUX_B41_1->PSS1_IMUX_B41_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_1" }, "PSS3.PSS_IMUX_B41_10->PSS1_IMUX_B41_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_10" }, "PSS3.PSS_IMUX_B41_11->PSS1_IMUX_B41_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_11" }, "PSS3.PSS_IMUX_B41_12->PSS1_IMUX_B41_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_12" }, "PSS3.PSS_IMUX_B41_13->PSS1_IMUX_B41_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_13" }, "PSS3.PSS_IMUX_B41_14->PSS1_IMUX_B41_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_14" }, "PSS3.PSS_IMUX_B41_15->PSS1_IMUX_B41_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_15" }, "PSS3.PSS_IMUX_B41_16->PSS1_IMUX_B41_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_16" }, "PSS3.PSS_IMUX_B41_17->PSS1_IMUX_B41_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_17" }, "PSS3.PSS_IMUX_B41_18->PSS1_IMUX_B41_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_18" }, "PSS3.PSS_IMUX_B41_19->PSS1_IMUX_B41_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_19" }, "PSS3.PSS_IMUX_B41_2->PSS1_IMUX_B41_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_2" }, "PSS3.PSS_IMUX_B41_3->PSS1_IMUX_B41_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_3" }, "PSS3.PSS_IMUX_B41_4->PSS1_IMUX_B41_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_4" }, "PSS3.PSS_IMUX_B41_5->PSS1_IMUX_B41_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_5" }, "PSS3.PSS_IMUX_B41_6->PSS1_IMUX_B41_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_6" }, "PSS3.PSS_IMUX_B41_7->PSS1_IMUX_B41_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_7" }, "PSS3.PSS_IMUX_B41_8->PSS1_IMUX_B41_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_8" }, "PSS3.PSS_IMUX_B41_9->PSS1_IMUX_B41_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B41_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_9" }, "PSS3.PSS_IMUX_B42_0->PSS1_IMUX_B42_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_0" }, "PSS3.PSS_IMUX_B42_1->PSS1_IMUX_B42_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_1" }, "PSS3.PSS_IMUX_B42_10->PSS1_IMUX_B42_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_10" }, "PSS3.PSS_IMUX_B42_11->PSS1_IMUX_B42_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_11" }, "PSS3.PSS_IMUX_B42_12->PSS1_IMUX_B42_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_12" }, "PSS3.PSS_IMUX_B42_13->PSS1_IMUX_B42_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_13" }, "PSS3.PSS_IMUX_B42_14->PSS1_IMUX_B42_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_14" }, "PSS3.PSS_IMUX_B42_15->PSS1_IMUX_B42_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_15" }, "PSS3.PSS_IMUX_B42_16->PSS1_IMUX_B42_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_16" }, "PSS3.PSS_IMUX_B42_17->PSS1_IMUX_B42_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_17" }, "PSS3.PSS_IMUX_B42_18->PSS1_IMUX_B42_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_18" }, "PSS3.PSS_IMUX_B42_19->PSS1_IMUX_B42_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_19" }, "PSS3.PSS_IMUX_B42_2->PSS1_IMUX_B42_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_2" }, "PSS3.PSS_IMUX_B42_3->PSS1_IMUX_B42_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_3" }, "PSS3.PSS_IMUX_B42_4->PSS1_IMUX_B42_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_4" }, "PSS3.PSS_IMUX_B42_5->PSS1_IMUX_B42_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_5" }, "PSS3.PSS_IMUX_B42_6->PSS1_IMUX_B42_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_6" }, "PSS3.PSS_IMUX_B42_7->PSS1_IMUX_B42_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_7" }, "PSS3.PSS_IMUX_B42_8->PSS1_IMUX_B42_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_8" }, "PSS3.PSS_IMUX_B42_9->PSS1_IMUX_B42_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B42_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_9" }, "PSS3.PSS_IMUX_B43_0->PSS1_IMUX_B43_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_0" }, "PSS3.PSS_IMUX_B43_1->PSS1_IMUX_B43_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_1" }, "PSS3.PSS_IMUX_B43_10->PSS1_IMUX_B43_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_10" }, "PSS3.PSS_IMUX_B43_11->PSS1_IMUX_B43_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_11" }, "PSS3.PSS_IMUX_B43_12->PSS1_IMUX_B43_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_12" }, "PSS3.PSS_IMUX_B43_13->PSS1_IMUX_B43_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_13" }, "PSS3.PSS_IMUX_B43_14->PSS1_IMUX_B43_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_14" }, "PSS3.PSS_IMUX_B43_15->PSS1_IMUX_B43_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_15" }, "PSS3.PSS_IMUX_B43_16->PSS1_IMUX_B43_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_16" }, "PSS3.PSS_IMUX_B43_17->PSS1_IMUX_B43_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_17" }, "PSS3.PSS_IMUX_B43_18->PSS1_IMUX_B43_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_18" }, "PSS3.PSS_IMUX_B43_19->PSS1_IMUX_B43_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_19" }, "PSS3.PSS_IMUX_B43_2->PSS1_IMUX_B43_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_2" }, "PSS3.PSS_IMUX_B43_3->PSS1_IMUX_B43_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_3" }, "PSS3.PSS_IMUX_B43_4->PSS1_IMUX_B43_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_4" }, "PSS3.PSS_IMUX_B43_5->PSS1_IMUX_B43_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_5" }, "PSS3.PSS_IMUX_B43_6->PSS1_IMUX_B43_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_6" }, "PSS3.PSS_IMUX_B43_7->PSS1_IMUX_B43_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_7" }, "PSS3.PSS_IMUX_B43_8->PSS1_IMUX_B43_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_8" }, "PSS3.PSS_IMUX_B43_9->PSS1_IMUX_B43_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B43_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_9" }, "PSS3.PSS_IMUX_B44_0->PSS1_IMUX_B44_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_0" }, "PSS3.PSS_IMUX_B44_1->PSS1_IMUX_B44_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_1" }, "PSS3.PSS_IMUX_B44_10->PSS1_IMUX_B44_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_10" }, "PSS3.PSS_IMUX_B44_11->PSS1_IMUX_B44_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_11" }, "PSS3.PSS_IMUX_B44_12->PSS1_IMUX_B44_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_12" }, "PSS3.PSS_IMUX_B44_13->PSS1_IMUX_B44_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_13" }, "PSS3.PSS_IMUX_B44_14->PSS1_IMUX_B44_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_14" }, "PSS3.PSS_IMUX_B44_15->PSS1_IMUX_B44_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_15" }, "PSS3.PSS_IMUX_B44_16->PSS1_IMUX_B44_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_16" }, "PSS3.PSS_IMUX_B44_17->PSS1_IMUX_B44_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_17" }, "PSS3.PSS_IMUX_B44_18->PSS1_IMUX_B44_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_18" }, "PSS3.PSS_IMUX_B44_19->PSS1_IMUX_B44_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_19" }, "PSS3.PSS_IMUX_B44_2->PSS1_IMUX_B44_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_2" }, "PSS3.PSS_IMUX_B44_3->PSS1_IMUX_B44_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_3" }, "PSS3.PSS_IMUX_B44_4->PSS1_IMUX_B44_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_4" }, "PSS3.PSS_IMUX_B44_5->PSS1_IMUX_B44_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_5" }, "PSS3.PSS_IMUX_B44_6->PSS1_IMUX_B44_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_6" }, "PSS3.PSS_IMUX_B44_7->PSS1_IMUX_B44_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_7" }, "PSS3.PSS_IMUX_B44_8->PSS1_IMUX_B44_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_8" }, "PSS3.PSS_IMUX_B44_9->PSS1_IMUX_B44_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B44_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_9" }, "PSS3.PSS_IMUX_B45_0->PSS1_IMUX_B45_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_0" }, "PSS3.PSS_IMUX_B45_1->PSS1_IMUX_B45_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_1" }, "PSS3.PSS_IMUX_B45_10->PSS1_IMUX_B45_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_10" }, "PSS3.PSS_IMUX_B45_11->PSS1_IMUX_B45_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_11" }, "PSS3.PSS_IMUX_B45_12->PSS1_IMUX_B45_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_12" }, "PSS3.PSS_IMUX_B45_13->PSS1_IMUX_B45_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_13" }, "PSS3.PSS_IMUX_B45_14->PSS1_IMUX_B45_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_14" }, "PSS3.PSS_IMUX_B45_15->PSS1_IMUX_B45_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_15" }, "PSS3.PSS_IMUX_B45_16->PSS1_IMUX_B45_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_16" }, "PSS3.PSS_IMUX_B45_17->PSS1_IMUX_B45_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_17" }, "PSS3.PSS_IMUX_B45_18->PSS1_IMUX_B45_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_18" }, "PSS3.PSS_IMUX_B45_19->PSS1_IMUX_B45_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_19" }, "PSS3.PSS_IMUX_B45_2->PSS1_IMUX_B45_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_2" }, "PSS3.PSS_IMUX_B45_3->PSS1_IMUX_B45_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_3" }, "PSS3.PSS_IMUX_B45_4->PSS1_IMUX_B45_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_4" }, "PSS3.PSS_IMUX_B45_5->PSS1_IMUX_B45_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_5" }, "PSS3.PSS_IMUX_B45_6->PSS1_IMUX_B45_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_6" }, "PSS3.PSS_IMUX_B45_7->PSS1_IMUX_B45_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_7" }, "PSS3.PSS_IMUX_B45_8->PSS1_IMUX_B45_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_8" }, "PSS3.PSS_IMUX_B45_9->PSS1_IMUX_B45_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B45_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_9" }, "PSS3.PSS_IMUX_B46_0->PSS1_IMUX_B46_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_0" }, "PSS3.PSS_IMUX_B46_1->PSS1_IMUX_B46_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_1" }, "PSS3.PSS_IMUX_B46_10->PSS1_IMUX_B46_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_10" }, "PSS3.PSS_IMUX_B46_11->PSS1_IMUX_B46_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_11" }, "PSS3.PSS_IMUX_B46_12->PSS1_IMUX_B46_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_12" }, "PSS3.PSS_IMUX_B46_13->PSS1_IMUX_B46_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_13" }, "PSS3.PSS_IMUX_B46_14->PSS1_IMUX_B46_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_14" }, "PSS3.PSS_IMUX_B46_15->PSS1_IMUX_B46_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_15" }, "PSS3.PSS_IMUX_B46_16->PSS1_IMUX_B46_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_16" }, "PSS3.PSS_IMUX_B46_17->PSS1_IMUX_B46_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_17" }, "PSS3.PSS_IMUX_B46_18->PSS1_IMUX_B46_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_18" }, "PSS3.PSS_IMUX_B46_19->PSS1_IMUX_B46_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_19" }, "PSS3.PSS_IMUX_B46_2->PSS1_IMUX_B46_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_2" }, "PSS3.PSS_IMUX_B46_3->PSS1_IMUX_B46_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_3" }, "PSS3.PSS_IMUX_B46_4->PSS1_IMUX_B46_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_4" }, "PSS3.PSS_IMUX_B46_5->PSS1_IMUX_B46_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_5" }, "PSS3.PSS_IMUX_B46_6->PSS1_IMUX_B46_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_6" }, "PSS3.PSS_IMUX_B46_7->PSS1_IMUX_B46_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_7" }, "PSS3.PSS_IMUX_B46_8->PSS1_IMUX_B46_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_8" }, "PSS3.PSS_IMUX_B46_9->PSS1_IMUX_B46_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B46_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_9" }, "PSS3.PSS_IMUX_B47_0->PSS1_IMUX_B47_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_0" }, "PSS3.PSS_IMUX_B47_1->PSS1_IMUX_B47_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_1" }, "PSS3.PSS_IMUX_B47_10->PSS1_IMUX_B47_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_10" }, "PSS3.PSS_IMUX_B47_11->PSS1_IMUX_B47_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_11" }, "PSS3.PSS_IMUX_B47_12->PSS1_IMUX_B47_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_12" }, "PSS3.PSS_IMUX_B47_13->PSS1_IMUX_B47_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_13" }, "PSS3.PSS_IMUX_B47_14->PSS1_IMUX_B47_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_14" }, "PSS3.PSS_IMUX_B47_15->PSS1_IMUX_B47_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_15" }, "PSS3.PSS_IMUX_B47_16->PSS1_IMUX_B47_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_16" }, "PSS3.PSS_IMUX_B47_17->PSS1_IMUX_B47_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_17" }, "PSS3.PSS_IMUX_B47_18->PSS1_IMUX_B47_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_18" }, "PSS3.PSS_IMUX_B47_19->PSS1_IMUX_B47_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_19" }, "PSS3.PSS_IMUX_B47_2->PSS1_IMUX_B47_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_2" }, "PSS3.PSS_IMUX_B47_3->PSS1_IMUX_B47_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_3" }, "PSS3.PSS_IMUX_B47_4->PSS1_IMUX_B47_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_4" }, "PSS3.PSS_IMUX_B47_5->PSS1_IMUX_B47_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_5" }, "PSS3.PSS_IMUX_B47_6->PSS1_IMUX_B47_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_6" }, "PSS3.PSS_IMUX_B47_7->PSS1_IMUX_B47_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_7" }, "PSS3.PSS_IMUX_B47_8->PSS1_IMUX_B47_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_8" }, "PSS3.PSS_IMUX_B47_9->PSS1_IMUX_B47_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B47_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_9" }, "PSS3.PSS_IMUX_B4_0->PSS1_IMUX_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_0" }, "PSS3.PSS_IMUX_B4_1->PSS1_IMUX_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_1" }, "PSS3.PSS_IMUX_B4_10->PSS1_IMUX_B4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_10" }, "PSS3.PSS_IMUX_B4_11->PSS1_IMUX_B4_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_11" }, "PSS3.PSS_IMUX_B4_12->PSS1_IMUX_B4_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_12" }, "PSS3.PSS_IMUX_B4_13->PSS1_IMUX_B4_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_13" }, "PSS3.PSS_IMUX_B4_14->PSS1_IMUX_B4_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_14" }, "PSS3.PSS_IMUX_B4_15->PSS1_IMUX_B4_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_15" }, "PSS3.PSS_IMUX_B4_16->PSS1_IMUX_B4_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_16" }, "PSS3.PSS_IMUX_B4_17->PSS1_IMUX_B4_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_17" }, "PSS3.PSS_IMUX_B4_18->PSS1_IMUX_B4_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_18" }, "PSS3.PSS_IMUX_B4_19->PSS1_IMUX_B4_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_19" }, "PSS3.PSS_IMUX_B4_2->PSS1_IMUX_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_2" }, "PSS3.PSS_IMUX_B4_3->PSS1_IMUX_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_3" }, "PSS3.PSS_IMUX_B4_4->PSS1_IMUX_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_4" }, "PSS3.PSS_IMUX_B4_5->PSS1_IMUX_B4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_5" }, "PSS3.PSS_IMUX_B4_6->PSS1_IMUX_B4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_6" }, "PSS3.PSS_IMUX_B4_7->PSS1_IMUX_B4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_7" }, "PSS3.PSS_IMUX_B4_8->PSS1_IMUX_B4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_8" }, "PSS3.PSS_IMUX_B4_9->PSS1_IMUX_B4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_9" }, "PSS3.PSS_IMUX_B5_0->PSS1_IMUX_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_0" }, "PSS3.PSS_IMUX_B5_1->PSS1_IMUX_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_1" }, "PSS3.PSS_IMUX_B5_10->PSS1_IMUX_B5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_10" }, "PSS3.PSS_IMUX_B5_11->PSS1_IMUX_B5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_11" }, "PSS3.PSS_IMUX_B5_12->PSS1_IMUX_B5_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_12" }, "PSS3.PSS_IMUX_B5_13->PSS1_IMUX_B5_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_13" }, "PSS3.PSS_IMUX_B5_14->PSS1_IMUX_B5_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_14" }, "PSS3.PSS_IMUX_B5_15->PSS1_IMUX_B5_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_15" }, "PSS3.PSS_IMUX_B5_16->PSS1_IMUX_B5_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_16" }, "PSS3.PSS_IMUX_B5_17->PSS1_IMUX_B5_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_17" }, "PSS3.PSS_IMUX_B5_18->PSS1_IMUX_B5_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_18" }, "PSS3.PSS_IMUX_B5_19->PSS1_IMUX_B5_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_19" }, "PSS3.PSS_IMUX_B5_2->PSS1_IMUX_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_2" }, "PSS3.PSS_IMUX_B5_3->PSS1_IMUX_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_3" }, "PSS3.PSS_IMUX_B5_4->PSS1_IMUX_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_4" }, "PSS3.PSS_IMUX_B5_5->PSS1_IMUX_B5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_5" }, "PSS3.PSS_IMUX_B5_6->PSS1_IMUX_B5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_6" }, "PSS3.PSS_IMUX_B5_7->PSS1_IMUX_B5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_7" }, "PSS3.PSS_IMUX_B5_8->PSS1_IMUX_B5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_8" }, "PSS3.PSS_IMUX_B5_9->PSS1_IMUX_B5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_9" }, "PSS3.PSS_IMUX_B6_0->PSS1_IMUX_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_0" }, "PSS3.PSS_IMUX_B6_1->PSS1_IMUX_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_1" }, "PSS3.PSS_IMUX_B6_10->PSS1_IMUX_B6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_10" }, "PSS3.PSS_IMUX_B6_11->PSS1_IMUX_B6_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_11" }, "PSS3.PSS_IMUX_B6_12->PSS1_IMUX_B6_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_12" }, "PSS3.PSS_IMUX_B6_13->PSS1_IMUX_B6_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_13" }, "PSS3.PSS_IMUX_B6_14->PSS1_IMUX_B6_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_14" }, "PSS3.PSS_IMUX_B6_15->PSS1_IMUX_B6_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_15" }, "PSS3.PSS_IMUX_B6_16->PSS1_IMUX_B6_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_16" }, "PSS3.PSS_IMUX_B6_17->PSS1_IMUX_B6_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_17" }, "PSS3.PSS_IMUX_B6_18->PSS1_IMUX_B6_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_18" }, "PSS3.PSS_IMUX_B6_19->PSS1_IMUX_B6_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_19" }, "PSS3.PSS_IMUX_B6_2->PSS1_IMUX_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_2" }, "PSS3.PSS_IMUX_B6_3->PSS1_IMUX_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_3" }, "PSS3.PSS_IMUX_B6_4->PSS1_IMUX_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_4" }, "PSS3.PSS_IMUX_B6_5->PSS1_IMUX_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_5" }, "PSS3.PSS_IMUX_B6_6->PSS1_IMUX_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_6" }, "PSS3.PSS_IMUX_B6_7->PSS1_IMUX_B6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_7" }, "PSS3.PSS_IMUX_B6_8->PSS1_IMUX_B6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_8" }, "PSS3.PSS_IMUX_B6_9->PSS1_IMUX_B6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_9" }, "PSS3.PSS_IMUX_B7_0->PSS1_IMUX_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_0" }, "PSS3.PSS_IMUX_B7_1->PSS1_IMUX_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_1" }, "PSS3.PSS_IMUX_B7_10->PSS1_IMUX_B7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_10" }, "PSS3.PSS_IMUX_B7_11->PSS1_IMUX_B7_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_11" }, "PSS3.PSS_IMUX_B7_12->PSS1_IMUX_B7_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_12" }, "PSS3.PSS_IMUX_B7_13->PSS1_IMUX_B7_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_13" }, "PSS3.PSS_IMUX_B7_14->PSS1_IMUX_B7_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_14" }, "PSS3.PSS_IMUX_B7_15->PSS1_IMUX_B7_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_15" }, "PSS3.PSS_IMUX_B7_16->PSS1_IMUX_B7_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_16" }, "PSS3.PSS_IMUX_B7_17->PSS1_IMUX_B7_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_17" }, "PSS3.PSS_IMUX_B7_18->PSS1_IMUX_B7_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_18" }, "PSS3.PSS_IMUX_B7_19->PSS1_IMUX_B7_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_19" }, "PSS3.PSS_IMUX_B7_2->PSS1_IMUX_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_2" }, "PSS3.PSS_IMUX_B7_3->PSS1_IMUX_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_3" }, "PSS3.PSS_IMUX_B7_4->PSS1_IMUX_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_4" }, "PSS3.PSS_IMUX_B7_5->PSS1_IMUX_B7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_5" }, "PSS3.PSS_IMUX_B7_6->PSS1_IMUX_B7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_6" }, "PSS3.PSS_IMUX_B7_7->PSS1_IMUX_B7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_7" }, "PSS3.PSS_IMUX_B7_8->PSS1_IMUX_B7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_8" }, "PSS3.PSS_IMUX_B7_9->PSS1_IMUX_B7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_9" }, "PSS3.PSS_IMUX_B8_0->PSS1_IMUX_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_0" }, "PSS3.PSS_IMUX_B8_1->PSS1_IMUX_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_1" }, "PSS3.PSS_IMUX_B8_10->PSS1_IMUX_B8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_10" }, "PSS3.PSS_IMUX_B8_11->PSS1_IMUX_B8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_11" }, "PSS3.PSS_IMUX_B8_12->PSS1_IMUX_B8_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_12" }, "PSS3.PSS_IMUX_B8_13->PSS1_IMUX_B8_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_13" }, "PSS3.PSS_IMUX_B8_14->PSS1_IMUX_B8_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_14" }, "PSS3.PSS_IMUX_B8_15->PSS1_IMUX_B8_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_15" }, "PSS3.PSS_IMUX_B8_16->PSS1_IMUX_B8_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_16" }, "PSS3.PSS_IMUX_B8_17->PSS1_IMUX_B8_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_17" }, "PSS3.PSS_IMUX_B8_18->PSS1_IMUX_B8_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_18" }, "PSS3.PSS_IMUX_B8_19->PSS1_IMUX_B8_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_19" }, "PSS3.PSS_IMUX_B8_2->PSS1_IMUX_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_2" }, "PSS3.PSS_IMUX_B8_3->PSS1_IMUX_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_3" }, "PSS3.PSS_IMUX_B8_4->PSS1_IMUX_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_4" }, "PSS3.PSS_IMUX_B8_5->PSS1_IMUX_B8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_5" }, "PSS3.PSS_IMUX_B8_6->PSS1_IMUX_B8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_6" }, "PSS3.PSS_IMUX_B8_7->PSS1_IMUX_B8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_7" }, "PSS3.PSS_IMUX_B8_8->PSS1_IMUX_B8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_8" }, "PSS3.PSS_IMUX_B8_9->PSS1_IMUX_B8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_9" }, "PSS3.PSS_IMUX_B9_0->PSS1_IMUX_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_0" }, "PSS3.PSS_IMUX_B9_1->PSS1_IMUX_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_1" }, "PSS3.PSS_IMUX_B9_10->PSS1_IMUX_B9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_10" }, "PSS3.PSS_IMUX_B9_11->PSS1_IMUX_B9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_11" }, "PSS3.PSS_IMUX_B9_12->PSS1_IMUX_B9_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_12" }, "PSS3.PSS_IMUX_B9_13->PSS1_IMUX_B9_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_13" }, "PSS3.PSS_IMUX_B9_14->PSS1_IMUX_B9_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_14" }, "PSS3.PSS_IMUX_B9_15->PSS1_IMUX_B9_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_15" }, "PSS3.PSS_IMUX_B9_16->PSS1_IMUX_B9_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_16" }, "PSS3.PSS_IMUX_B9_17->PSS1_IMUX_B9_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_17" }, "PSS3.PSS_IMUX_B9_18->PSS1_IMUX_B9_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_18" }, "PSS3.PSS_IMUX_B9_19->PSS1_IMUX_B9_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_19" }, "PSS3.PSS_IMUX_B9_2->PSS1_IMUX_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_2" }, "PSS3.PSS_IMUX_B9_3->PSS1_IMUX_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_3" }, "PSS3.PSS_IMUX_B9_4->PSS1_IMUX_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_4" }, "PSS3.PSS_IMUX_B9_5->PSS1_IMUX_B9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_5" }, "PSS3.PSS_IMUX_B9_6->PSS1_IMUX_B9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_6" }, "PSS3.PSS_IMUX_B9_7->PSS1_IMUX_B9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_7" }, "PSS3.PSS_IMUX_B9_8->PSS1_IMUX_B9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_8" }, "PSS3.PSS_IMUX_B9_9->PSS1_IMUX_B9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS1_IMUX_B9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_9" } }, "sites": [], "tile_type": "PSS3", - "wires": [ - "PSS0_CLK_B0_0", - "PSS0_CLK_B0_1", - "PSS0_CLK_B0_10", - "PSS0_CLK_B0_11", - "PSS0_CLK_B0_12", - "PSS0_CLK_B0_13", - "PSS0_CLK_B0_14", - "PSS0_CLK_B0_15", - "PSS0_CLK_B0_16", - "PSS0_CLK_B0_17", - "PSS0_CLK_B0_18", - "PSS0_CLK_B0_19", - "PSS0_CLK_B0_2", - "PSS0_CLK_B0_3", - "PSS0_CLK_B0_4", - "PSS0_CLK_B0_5", - "PSS0_CLK_B0_6", - "PSS0_CLK_B0_7", - "PSS0_CLK_B0_8", - "PSS0_CLK_B0_9", - "PSS0_CLK_B1_0", - "PSS0_CLK_B1_1", - "PSS0_CLK_B1_10", - "PSS0_CLK_B1_11", - "PSS0_CLK_B1_12", - "PSS0_CLK_B1_13", - "PSS0_CLK_B1_14", - "PSS0_CLK_B1_15", - "PSS0_CLK_B1_16", - "PSS0_CLK_B1_17", - "PSS0_CLK_B1_18", - "PSS0_CLK_B1_19", - "PSS0_CLK_B1_2", - "PSS0_CLK_B1_3", - "PSS0_CLK_B1_4", - "PSS0_CLK_B1_5", - "PSS0_CLK_B1_6", - "PSS0_CLK_B1_7", - "PSS0_CLK_B1_8", - "PSS0_CLK_B1_9", - "PSS0_IMUX_B0_0", - "PSS0_IMUX_B0_1", - "PSS0_IMUX_B0_10", - "PSS0_IMUX_B0_11", - "PSS0_IMUX_B0_12", - "PSS0_IMUX_B0_13", - "PSS0_IMUX_B0_14", - "PSS0_IMUX_B0_15", - "PSS0_IMUX_B0_16", - "PSS0_IMUX_B0_17", - "PSS0_IMUX_B0_18", - "PSS0_IMUX_B0_19", - "PSS0_IMUX_B0_2", - "PSS0_IMUX_B0_3", - "PSS0_IMUX_B0_4", - "PSS0_IMUX_B0_5", - "PSS0_IMUX_B0_6", - "PSS0_IMUX_B0_7", - "PSS0_IMUX_B0_8", - "PSS0_IMUX_B0_9", - "PSS0_IMUX_B10_0", - "PSS0_IMUX_B10_1", - "PSS0_IMUX_B10_10", - "PSS0_IMUX_B10_11", - "PSS0_IMUX_B10_12", - "PSS0_IMUX_B10_13", - "PSS0_IMUX_B10_14", - "PSS0_IMUX_B10_15", - "PSS0_IMUX_B10_16", - "PSS0_IMUX_B10_17", - "PSS0_IMUX_B10_18", - "PSS0_IMUX_B10_19", - "PSS0_IMUX_B10_2", - "PSS0_IMUX_B10_3", - "PSS0_IMUX_B10_4", - "PSS0_IMUX_B10_5", - "PSS0_IMUX_B10_6", - "PSS0_IMUX_B10_7", - "PSS0_IMUX_B10_8", - "PSS0_IMUX_B10_9", - "PSS0_IMUX_B11_0", - "PSS0_IMUX_B11_1", - "PSS0_IMUX_B11_10", - "PSS0_IMUX_B11_11", - "PSS0_IMUX_B11_12", - "PSS0_IMUX_B11_13", - "PSS0_IMUX_B11_14", - "PSS0_IMUX_B11_15", - "PSS0_IMUX_B11_16", - "PSS0_IMUX_B11_17", - "PSS0_IMUX_B11_18", - "PSS0_IMUX_B11_19", - "PSS0_IMUX_B11_2", - "PSS0_IMUX_B11_3", - "PSS0_IMUX_B11_4", - "PSS0_IMUX_B11_5", - "PSS0_IMUX_B11_6", - "PSS0_IMUX_B11_7", - "PSS0_IMUX_B11_8", - "PSS0_IMUX_B11_9", - "PSS0_IMUX_B12_0", - "PSS0_IMUX_B12_1", - "PSS0_IMUX_B12_10", - "PSS0_IMUX_B12_11", - "PSS0_IMUX_B12_12", - "PSS0_IMUX_B12_13", - "PSS0_IMUX_B12_14", - "PSS0_IMUX_B12_15", - "PSS0_IMUX_B12_16", - "PSS0_IMUX_B12_17", - "PSS0_IMUX_B12_18", - "PSS0_IMUX_B12_19", - "PSS0_IMUX_B12_2", - "PSS0_IMUX_B12_3", - "PSS0_IMUX_B12_4", - "PSS0_IMUX_B12_5", - "PSS0_IMUX_B12_6", - "PSS0_IMUX_B12_7", - "PSS0_IMUX_B12_8", - "PSS0_IMUX_B12_9", - "PSS0_IMUX_B13_0", - "PSS0_IMUX_B13_1", - "PSS0_IMUX_B13_10", - "PSS0_IMUX_B13_11", - "PSS0_IMUX_B13_12", - "PSS0_IMUX_B13_13", - "PSS0_IMUX_B13_14", - "PSS0_IMUX_B13_15", - "PSS0_IMUX_B13_16", - "PSS0_IMUX_B13_17", - "PSS0_IMUX_B13_18", - "PSS0_IMUX_B13_19", - "PSS0_IMUX_B13_2", - "PSS0_IMUX_B13_3", - "PSS0_IMUX_B13_4", - "PSS0_IMUX_B13_5", - "PSS0_IMUX_B13_6", - "PSS0_IMUX_B13_7", - "PSS0_IMUX_B13_8", - "PSS0_IMUX_B13_9", - "PSS0_IMUX_B14_0", - "PSS0_IMUX_B14_1", - "PSS0_IMUX_B14_10", - "PSS0_IMUX_B14_11", - "PSS0_IMUX_B14_12", - "PSS0_IMUX_B14_13", - "PSS0_IMUX_B14_14", - "PSS0_IMUX_B14_15", - "PSS0_IMUX_B14_16", - "PSS0_IMUX_B14_17", - "PSS0_IMUX_B14_18", - "PSS0_IMUX_B14_19", - "PSS0_IMUX_B14_2", - "PSS0_IMUX_B14_3", - "PSS0_IMUX_B14_4", - "PSS0_IMUX_B14_5", - "PSS0_IMUX_B14_6", - "PSS0_IMUX_B14_7", - "PSS0_IMUX_B14_8", - "PSS0_IMUX_B14_9", - "PSS0_IMUX_B15_0", - "PSS0_IMUX_B15_1", - "PSS0_IMUX_B15_10", - "PSS0_IMUX_B15_11", - "PSS0_IMUX_B15_12", - "PSS0_IMUX_B15_13", - "PSS0_IMUX_B15_14", - "PSS0_IMUX_B15_15", - "PSS0_IMUX_B15_16", - "PSS0_IMUX_B15_17", - "PSS0_IMUX_B15_18", - "PSS0_IMUX_B15_19", - "PSS0_IMUX_B15_2", - "PSS0_IMUX_B15_3", - "PSS0_IMUX_B15_4", - "PSS0_IMUX_B15_5", - "PSS0_IMUX_B15_6", - "PSS0_IMUX_B15_7", - "PSS0_IMUX_B15_8", - "PSS0_IMUX_B15_9", - "PSS0_IMUX_B16_0", - "PSS0_IMUX_B16_1", - "PSS0_IMUX_B16_10", - "PSS0_IMUX_B16_11", - "PSS0_IMUX_B16_12", - "PSS0_IMUX_B16_13", - "PSS0_IMUX_B16_14", - "PSS0_IMUX_B16_15", - "PSS0_IMUX_B16_16", - "PSS0_IMUX_B16_17", - "PSS0_IMUX_B16_18", - "PSS0_IMUX_B16_19", - "PSS0_IMUX_B16_2", - "PSS0_IMUX_B16_3", - "PSS0_IMUX_B16_4", - "PSS0_IMUX_B16_5", - "PSS0_IMUX_B16_6", - "PSS0_IMUX_B16_7", - "PSS0_IMUX_B16_8", - "PSS0_IMUX_B16_9", - "PSS0_IMUX_B17_0", - "PSS0_IMUX_B17_1", - "PSS0_IMUX_B17_10", - "PSS0_IMUX_B17_11", - "PSS0_IMUX_B17_12", - "PSS0_IMUX_B17_13", - "PSS0_IMUX_B17_14", - "PSS0_IMUX_B17_15", - "PSS0_IMUX_B17_16", - "PSS0_IMUX_B17_17", - "PSS0_IMUX_B17_18", - "PSS0_IMUX_B17_19", - "PSS0_IMUX_B17_2", - "PSS0_IMUX_B17_3", - "PSS0_IMUX_B17_4", - "PSS0_IMUX_B17_5", - "PSS0_IMUX_B17_6", - "PSS0_IMUX_B17_7", - "PSS0_IMUX_B17_8", - "PSS0_IMUX_B17_9", - "PSS0_IMUX_B18_0", - "PSS0_IMUX_B18_1", - "PSS0_IMUX_B18_10", - "PSS0_IMUX_B18_11", - "PSS0_IMUX_B18_12", - "PSS0_IMUX_B18_13", - "PSS0_IMUX_B18_14", - "PSS0_IMUX_B18_15", - "PSS0_IMUX_B18_16", - "PSS0_IMUX_B18_17", - "PSS0_IMUX_B18_18", - "PSS0_IMUX_B18_19", - "PSS0_IMUX_B18_2", - "PSS0_IMUX_B18_3", - "PSS0_IMUX_B18_4", - "PSS0_IMUX_B18_5", - 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"PSS0_IMUX_B43_19", - "PSS0_IMUX_B43_2", - "PSS0_IMUX_B43_3", - "PSS0_IMUX_B43_4", - "PSS0_IMUX_B43_5", - "PSS0_IMUX_B43_6", - "PSS0_IMUX_B43_7", - "PSS0_IMUX_B43_8", - "PSS0_IMUX_B43_9", - "PSS0_IMUX_B44_0", - "PSS0_IMUX_B44_1", - "PSS0_IMUX_B44_10", - "PSS0_IMUX_B44_11", - "PSS0_IMUX_B44_12", - "PSS0_IMUX_B44_13", - "PSS0_IMUX_B44_14", - "PSS0_IMUX_B44_15", - "PSS0_IMUX_B44_16", - "PSS0_IMUX_B44_17", - "PSS0_IMUX_B44_18", - "PSS0_IMUX_B44_19", - "PSS0_IMUX_B44_2", - "PSS0_IMUX_B44_3", - "PSS0_IMUX_B44_4", - "PSS0_IMUX_B44_5", - "PSS0_IMUX_B44_6", - "PSS0_IMUX_B44_7", - "PSS0_IMUX_B44_8", - "PSS0_IMUX_B44_9", - "PSS0_IMUX_B45_0", - "PSS0_IMUX_B45_1", - "PSS0_IMUX_B45_10", - "PSS0_IMUX_B45_11", - "PSS0_IMUX_B45_12", - "PSS0_IMUX_B45_13", - "PSS0_IMUX_B45_14", - "PSS0_IMUX_B45_15", - "PSS0_IMUX_B45_16", - "PSS0_IMUX_B45_17", - "PSS0_IMUX_B45_18", - "PSS0_IMUX_B45_19", - "PSS0_IMUX_B45_2", - "PSS0_IMUX_B45_3", - "PSS0_IMUX_B45_4", - "PSS0_IMUX_B45_5", - "PSS0_IMUX_B45_6", - "PSS0_IMUX_B45_7", - "PSS0_IMUX_B45_8", - "PSS0_IMUX_B45_9", - "PSS0_IMUX_B46_0", - "PSS0_IMUX_B46_1", - "PSS0_IMUX_B46_10", - "PSS0_IMUX_B46_11", - "PSS0_IMUX_B46_12", - "PSS0_IMUX_B46_13", - "PSS0_IMUX_B46_14", - "PSS0_IMUX_B46_15", - "PSS0_IMUX_B46_16", - "PSS0_IMUX_B46_17", - "PSS0_IMUX_B46_18", - "PSS0_IMUX_B46_19", - "PSS0_IMUX_B46_2", - "PSS0_IMUX_B46_3", - "PSS0_IMUX_B46_4", - "PSS0_IMUX_B46_5", - "PSS0_IMUX_B46_6", - "PSS0_IMUX_B46_7", - "PSS0_IMUX_B46_8", - "PSS0_IMUX_B46_9", - "PSS0_IMUX_B47_0", - "PSS0_IMUX_B47_1", - "PSS0_IMUX_B47_10", - "PSS0_IMUX_B47_11", - "PSS0_IMUX_B47_12", - "PSS0_IMUX_B47_13", - "PSS0_IMUX_B47_14", - "PSS0_IMUX_B47_15", - "PSS0_IMUX_B47_16", - "PSS0_IMUX_B47_17", - "PSS0_IMUX_B47_18", - "PSS0_IMUX_B47_19", - "PSS0_IMUX_B47_2", - "PSS0_IMUX_B47_3", - "PSS0_IMUX_B47_4", - "PSS0_IMUX_B47_5", - "PSS0_IMUX_B47_6", - "PSS0_IMUX_B47_7", - "PSS0_IMUX_B47_8", - "PSS0_IMUX_B47_9", - "PSS0_IMUX_B4_0", - "PSS0_IMUX_B4_1", - "PSS0_IMUX_B4_10", - "PSS0_IMUX_B4_11", - "PSS0_IMUX_B4_12", - "PSS0_IMUX_B4_13", - "PSS0_IMUX_B4_14", - "PSS0_IMUX_B4_15", - "PSS0_IMUX_B4_16", - "PSS0_IMUX_B4_17", - "PSS0_IMUX_B4_18", - "PSS0_IMUX_B4_19", - "PSS0_IMUX_B4_2", - "PSS0_IMUX_B4_3", - "PSS0_IMUX_B4_4", - "PSS0_IMUX_B4_5", - "PSS0_IMUX_B4_6", - "PSS0_IMUX_B4_7", - "PSS0_IMUX_B4_8", - "PSS0_IMUX_B4_9", - "PSS0_IMUX_B5_0", - "PSS0_IMUX_B5_1", - "PSS0_IMUX_B5_10", - "PSS0_IMUX_B5_11", - "PSS0_IMUX_B5_12", - "PSS0_IMUX_B5_13", - "PSS0_IMUX_B5_14", - "PSS0_IMUX_B5_15", - "PSS0_IMUX_B5_16", - "PSS0_IMUX_B5_17", - "PSS0_IMUX_B5_18", - "PSS0_IMUX_B5_19", - "PSS0_IMUX_B5_2", - "PSS0_IMUX_B5_3", - "PSS0_IMUX_B5_4", - "PSS0_IMUX_B5_5", - "PSS0_IMUX_B5_6", - "PSS0_IMUX_B5_7", - "PSS0_IMUX_B5_8", - "PSS0_IMUX_B5_9", - "PSS0_IMUX_B6_0", - "PSS0_IMUX_B6_1", - "PSS0_IMUX_B6_10", - "PSS0_IMUX_B6_11", - "PSS0_IMUX_B6_12", - "PSS0_IMUX_B6_13", - "PSS0_IMUX_B6_14", - "PSS0_IMUX_B6_15", - "PSS0_IMUX_B6_16", - "PSS0_IMUX_B6_17", - "PSS0_IMUX_B6_18", - "PSS0_IMUX_B6_19", - "PSS0_IMUX_B6_2", - "PSS0_IMUX_B6_3", - "PSS0_IMUX_B6_4", - "PSS0_IMUX_B6_5", - "PSS0_IMUX_B6_6", - "PSS0_IMUX_B6_7", - "PSS0_IMUX_B6_8", - "PSS0_IMUX_B6_9", - "PSS0_IMUX_B7_0", - "PSS0_IMUX_B7_1", - "PSS0_IMUX_B7_10", - "PSS0_IMUX_B7_11", - "PSS0_IMUX_B7_12", - "PSS0_IMUX_B7_13", - "PSS0_IMUX_B7_14", - "PSS0_IMUX_B7_15", - "PSS0_IMUX_B7_16", - "PSS0_IMUX_B7_17", - "PSS0_IMUX_B7_18", - "PSS0_IMUX_B7_19", - "PSS0_IMUX_B7_2", - "PSS0_IMUX_B7_3", - "PSS0_IMUX_B7_4", - "PSS0_IMUX_B7_5", - "PSS0_IMUX_B7_6", - "PSS0_IMUX_B7_7", - "PSS0_IMUX_B7_8", - "PSS0_IMUX_B7_9", - "PSS0_IMUX_B8_0", - "PSS0_IMUX_B8_1", - "PSS0_IMUX_B8_10", - "PSS0_IMUX_B8_11", - "PSS0_IMUX_B8_12", - "PSS0_IMUX_B8_13", - "PSS0_IMUX_B8_14", - "PSS0_IMUX_B8_15", - "PSS0_IMUX_B8_16", - "PSS0_IMUX_B8_17", - "PSS0_IMUX_B8_18", - "PSS0_IMUX_B8_19", - "PSS0_IMUX_B8_2", - "PSS0_IMUX_B8_3", - "PSS0_IMUX_B8_4", - "PSS0_IMUX_B8_5", - "PSS0_IMUX_B8_6", - "PSS0_IMUX_B8_7", - "PSS0_IMUX_B8_8", - "PSS0_IMUX_B8_9", - "PSS0_IMUX_B9_0", - "PSS0_IMUX_B9_1", - "PSS0_IMUX_B9_10", - "PSS0_IMUX_B9_11", - "PSS0_IMUX_B9_12", - "PSS0_IMUX_B9_13", - "PSS0_IMUX_B9_14", - "PSS0_IMUX_B9_15", - "PSS0_IMUX_B9_16", - "PSS0_IMUX_B9_17", - "PSS0_IMUX_B9_18", - "PSS0_IMUX_B9_19", - "PSS0_IMUX_B9_2", - "PSS0_IMUX_B9_3", - "PSS0_IMUX_B9_4", - "PSS0_IMUX_B9_5", - "PSS0_IMUX_B9_6", - "PSS0_IMUX_B9_7", - "PSS0_IMUX_B9_8", - "PSS0_IMUX_B9_9", - "PSS0_LOGIC_OUTS0_0", - "PSS0_LOGIC_OUTS0_1", - "PSS0_LOGIC_OUTS0_10", - "PSS0_LOGIC_OUTS0_11", - "PSS0_LOGIC_OUTS0_12", - "PSS0_LOGIC_OUTS0_13", - "PSS0_LOGIC_OUTS0_14", - "PSS0_LOGIC_OUTS0_15", - "PSS0_LOGIC_OUTS0_16", - "PSS0_LOGIC_OUTS0_17", - "PSS0_LOGIC_OUTS0_18", - "PSS0_LOGIC_OUTS0_19", - "PSS0_LOGIC_OUTS0_2", - "PSS0_LOGIC_OUTS0_3", - "PSS0_LOGIC_OUTS0_4", - "PSS0_LOGIC_OUTS0_5", - "PSS0_LOGIC_OUTS0_6", - "PSS0_LOGIC_OUTS0_7", - "PSS0_LOGIC_OUTS0_8", - "PSS0_LOGIC_OUTS0_9", - "PSS0_LOGIC_OUTS10_0", - "PSS0_LOGIC_OUTS10_1", - "PSS0_LOGIC_OUTS10_10", - "PSS0_LOGIC_OUTS10_11", - "PSS0_LOGIC_OUTS10_12", - "PSS0_LOGIC_OUTS10_13", - "PSS0_LOGIC_OUTS10_14", - "PSS0_LOGIC_OUTS10_15", - "PSS0_LOGIC_OUTS10_16", - "PSS0_LOGIC_OUTS10_17", - "PSS0_LOGIC_OUTS10_18", - "PSS0_LOGIC_OUTS10_19", - "PSS0_LOGIC_OUTS10_2", - "PSS0_LOGIC_OUTS10_3", - "PSS0_LOGIC_OUTS10_4", - "PSS0_LOGIC_OUTS10_5", - "PSS0_LOGIC_OUTS10_6", - "PSS0_LOGIC_OUTS10_7", - "PSS0_LOGIC_OUTS10_8", - "PSS0_LOGIC_OUTS10_9", - "PSS0_LOGIC_OUTS11_0", - "PSS0_LOGIC_OUTS11_1", - "PSS0_LOGIC_OUTS11_10", - "PSS0_LOGIC_OUTS11_11", - "PSS0_LOGIC_OUTS11_12", - "PSS0_LOGIC_OUTS11_13", - "PSS0_LOGIC_OUTS11_14", - "PSS0_LOGIC_OUTS11_15", - "PSS0_LOGIC_OUTS11_16", - "PSS0_LOGIC_OUTS11_17", - "PSS0_LOGIC_OUTS11_18", - "PSS0_LOGIC_OUTS11_19", - "PSS0_LOGIC_OUTS11_2", - "PSS0_LOGIC_OUTS11_3", - "PSS0_LOGIC_OUTS11_4", - "PSS0_LOGIC_OUTS11_5", - "PSS0_LOGIC_OUTS11_6", - "PSS0_LOGIC_OUTS11_7", - "PSS0_LOGIC_OUTS11_8", - "PSS0_LOGIC_OUTS11_9", - "PSS0_LOGIC_OUTS12_0", - "PSS0_LOGIC_OUTS12_1", - "PSS0_LOGIC_OUTS12_10", - "PSS0_LOGIC_OUTS12_11", - "PSS0_LOGIC_OUTS12_12", - "PSS0_LOGIC_OUTS12_13", - "PSS0_LOGIC_OUTS12_14", - "PSS0_LOGIC_OUTS12_15", - "PSS0_LOGIC_OUTS12_16", - "PSS0_LOGIC_OUTS12_17", - "PSS0_LOGIC_OUTS12_18", - "PSS0_LOGIC_OUTS12_19", - "PSS0_LOGIC_OUTS12_2", - "PSS0_LOGIC_OUTS12_3", - "PSS0_LOGIC_OUTS12_4", - "PSS0_LOGIC_OUTS12_5", - "PSS0_LOGIC_OUTS12_6", - "PSS0_LOGIC_OUTS12_7", - "PSS0_LOGIC_OUTS12_8", - "PSS0_LOGIC_OUTS12_9", - "PSS0_LOGIC_OUTS13_0", - "PSS0_LOGIC_OUTS13_1", - "PSS0_LOGIC_OUTS13_10", - "PSS0_LOGIC_OUTS13_11", - "PSS0_LOGIC_OUTS13_12", - "PSS0_LOGIC_OUTS13_13", - "PSS0_LOGIC_OUTS13_14", - "PSS0_LOGIC_OUTS13_15", - "PSS0_LOGIC_OUTS13_16", - "PSS0_LOGIC_OUTS13_17", - "PSS0_LOGIC_OUTS13_18", - "PSS0_LOGIC_OUTS13_19", - "PSS0_LOGIC_OUTS13_2", - "PSS0_LOGIC_OUTS13_3", - "PSS0_LOGIC_OUTS13_4", - "PSS0_LOGIC_OUTS13_5", - "PSS0_LOGIC_OUTS13_6", - "PSS0_LOGIC_OUTS13_7", - "PSS0_LOGIC_OUTS13_8", - "PSS0_LOGIC_OUTS13_9", - "PSS0_LOGIC_OUTS14_0", - "PSS0_LOGIC_OUTS14_1", - "PSS0_LOGIC_OUTS14_10", - "PSS0_LOGIC_OUTS14_11", - "PSS0_LOGIC_OUTS14_12", - "PSS0_LOGIC_OUTS14_13", - "PSS0_LOGIC_OUTS14_14", - "PSS0_LOGIC_OUTS14_15", - "PSS0_LOGIC_OUTS14_16", - "PSS0_LOGIC_OUTS14_17", - "PSS0_LOGIC_OUTS14_18", - "PSS0_LOGIC_OUTS14_19", - "PSS0_LOGIC_OUTS14_2", - "PSS0_LOGIC_OUTS14_3", - "PSS0_LOGIC_OUTS14_4", - "PSS0_LOGIC_OUTS14_5", - "PSS0_LOGIC_OUTS14_6", - "PSS0_LOGIC_OUTS14_7", - "PSS0_LOGIC_OUTS14_8", - "PSS0_LOGIC_OUTS14_9", - "PSS0_LOGIC_OUTS15_0", - "PSS0_LOGIC_OUTS15_1", - "PSS0_LOGIC_OUTS15_10", - "PSS0_LOGIC_OUTS15_11", - "PSS0_LOGIC_OUTS15_12", - "PSS0_LOGIC_OUTS15_13", - "PSS0_LOGIC_OUTS15_14", - "PSS0_LOGIC_OUTS15_15", - "PSS0_LOGIC_OUTS15_16", - "PSS0_LOGIC_OUTS15_17", - "PSS0_LOGIC_OUTS15_18", - "PSS0_LOGIC_OUTS15_19", - "PSS0_LOGIC_OUTS15_2", - "PSS0_LOGIC_OUTS15_3", - "PSS0_LOGIC_OUTS15_4", - "PSS0_LOGIC_OUTS15_5", - "PSS0_LOGIC_OUTS15_6", - "PSS0_LOGIC_OUTS15_7", - "PSS0_LOGIC_OUTS15_8", - "PSS0_LOGIC_OUTS15_9", - "PSS0_LOGIC_OUTS16_0", - "PSS0_LOGIC_OUTS16_1", - "PSS0_LOGIC_OUTS16_10", - "PSS0_LOGIC_OUTS16_11", - "PSS0_LOGIC_OUTS16_12", - "PSS0_LOGIC_OUTS16_13", - "PSS0_LOGIC_OUTS16_14", - "PSS0_LOGIC_OUTS16_15", - "PSS0_LOGIC_OUTS16_16", - "PSS0_LOGIC_OUTS16_17", - "PSS0_LOGIC_OUTS16_18", - "PSS0_LOGIC_OUTS16_19", - "PSS0_LOGIC_OUTS16_2", - "PSS0_LOGIC_OUTS16_3", - "PSS0_LOGIC_OUTS16_4", - "PSS0_LOGIC_OUTS16_5", - "PSS0_LOGIC_OUTS16_6", - "PSS0_LOGIC_OUTS16_7", - "PSS0_LOGIC_OUTS16_8", - "PSS0_LOGIC_OUTS16_9", - "PSS0_LOGIC_OUTS17_0", - "PSS0_LOGIC_OUTS17_1", - "PSS0_LOGIC_OUTS17_10", - "PSS0_LOGIC_OUTS17_11", - "PSS0_LOGIC_OUTS17_12", - "PSS0_LOGIC_OUTS17_13", - "PSS0_LOGIC_OUTS17_14", - "PSS0_LOGIC_OUTS17_15", - "PSS0_LOGIC_OUTS17_16", - "PSS0_LOGIC_OUTS17_17", - "PSS0_LOGIC_OUTS17_18", - "PSS0_LOGIC_OUTS17_19", - "PSS0_LOGIC_OUTS17_2", - "PSS0_LOGIC_OUTS17_3", - "PSS0_LOGIC_OUTS17_4", - "PSS0_LOGIC_OUTS17_5", - "PSS0_LOGIC_OUTS17_6", - "PSS0_LOGIC_OUTS17_7", - "PSS0_LOGIC_OUTS17_8", - "PSS0_LOGIC_OUTS17_9", - "PSS0_LOGIC_OUTS18_0", - "PSS0_LOGIC_OUTS18_1", - "PSS0_LOGIC_OUTS18_10", - "PSS0_LOGIC_OUTS18_11", - "PSS0_LOGIC_OUTS18_12", - "PSS0_LOGIC_OUTS18_13", - "PSS0_LOGIC_OUTS18_14", - "PSS0_LOGIC_OUTS18_15", - "PSS0_LOGIC_OUTS18_16", - "PSS0_LOGIC_OUTS18_17", - "PSS0_LOGIC_OUTS18_18", - "PSS0_LOGIC_OUTS18_19", - "PSS0_LOGIC_OUTS18_2", - "PSS0_LOGIC_OUTS18_3", - "PSS0_LOGIC_OUTS18_4", - "PSS0_LOGIC_OUTS18_5", - "PSS0_LOGIC_OUTS18_6", - "PSS0_LOGIC_OUTS18_7", - "PSS0_LOGIC_OUTS18_8", - "PSS0_LOGIC_OUTS18_9", - "PSS0_LOGIC_OUTS19_0", - "PSS0_LOGIC_OUTS19_1", - "PSS0_LOGIC_OUTS19_10", - "PSS0_LOGIC_OUTS19_11", - "PSS0_LOGIC_OUTS19_12", - "PSS0_LOGIC_OUTS19_13", - "PSS0_LOGIC_OUTS19_14", - "PSS0_LOGIC_OUTS19_15", - "PSS0_LOGIC_OUTS19_16", - "PSS0_LOGIC_OUTS19_17", - "PSS0_LOGIC_OUTS19_18", - "PSS0_LOGIC_OUTS19_19", - "PSS0_LOGIC_OUTS19_2", - "PSS0_LOGIC_OUTS19_3", - "PSS0_LOGIC_OUTS19_4", - "PSS0_LOGIC_OUTS19_5", - "PSS0_LOGIC_OUTS19_6", - "PSS0_LOGIC_OUTS19_7", - "PSS0_LOGIC_OUTS19_8", - "PSS0_LOGIC_OUTS19_9", - "PSS0_LOGIC_OUTS1_0", - "PSS0_LOGIC_OUTS1_1", - "PSS0_LOGIC_OUTS1_10", - "PSS0_LOGIC_OUTS1_11", - "PSS0_LOGIC_OUTS1_12", - "PSS0_LOGIC_OUTS1_13", - "PSS0_LOGIC_OUTS1_14", - "PSS0_LOGIC_OUTS1_15", - "PSS0_LOGIC_OUTS1_16", - "PSS0_LOGIC_OUTS1_17", - "PSS0_LOGIC_OUTS1_18", - "PSS0_LOGIC_OUTS1_19", - "PSS0_LOGIC_OUTS1_2", - "PSS0_LOGIC_OUTS1_3", - "PSS0_LOGIC_OUTS1_4", - "PSS0_LOGIC_OUTS1_5", - "PSS0_LOGIC_OUTS1_6", - "PSS0_LOGIC_OUTS1_7", - "PSS0_LOGIC_OUTS1_8", - "PSS0_LOGIC_OUTS1_9", - "PSS0_LOGIC_OUTS20_0", - "PSS0_LOGIC_OUTS20_1", - "PSS0_LOGIC_OUTS20_10", - "PSS0_LOGIC_OUTS20_11", - "PSS0_LOGIC_OUTS20_12", - "PSS0_LOGIC_OUTS20_13", - "PSS0_LOGIC_OUTS20_14", - "PSS0_LOGIC_OUTS20_15", - "PSS0_LOGIC_OUTS20_16", - "PSS0_LOGIC_OUTS20_17", - "PSS0_LOGIC_OUTS20_18", - "PSS0_LOGIC_OUTS20_19", - "PSS0_LOGIC_OUTS20_2", - "PSS0_LOGIC_OUTS20_3", - "PSS0_LOGIC_OUTS20_4", - "PSS0_LOGIC_OUTS20_5", - "PSS0_LOGIC_OUTS20_6", - "PSS0_LOGIC_OUTS20_7", - "PSS0_LOGIC_OUTS20_8", - "PSS0_LOGIC_OUTS20_9", - "PSS0_LOGIC_OUTS21_0", - "PSS0_LOGIC_OUTS21_1", - "PSS0_LOGIC_OUTS21_10", - "PSS0_LOGIC_OUTS21_11", - "PSS0_LOGIC_OUTS21_12", - "PSS0_LOGIC_OUTS21_13", - "PSS0_LOGIC_OUTS21_14", - "PSS0_LOGIC_OUTS21_15", - "PSS0_LOGIC_OUTS21_16", - "PSS0_LOGIC_OUTS21_17", - "PSS0_LOGIC_OUTS21_18", - "PSS0_LOGIC_OUTS21_19", - "PSS0_LOGIC_OUTS21_2", - "PSS0_LOGIC_OUTS21_3", - "PSS0_LOGIC_OUTS21_4", - "PSS0_LOGIC_OUTS21_5", - "PSS0_LOGIC_OUTS21_6", - "PSS0_LOGIC_OUTS21_7", - "PSS0_LOGIC_OUTS21_8", - "PSS0_LOGIC_OUTS21_9", - "PSS0_LOGIC_OUTS22_0", - "PSS0_LOGIC_OUTS22_1", - "PSS0_LOGIC_OUTS22_10", - "PSS0_LOGIC_OUTS22_11", - "PSS0_LOGIC_OUTS22_12", - "PSS0_LOGIC_OUTS22_13", - "PSS0_LOGIC_OUTS22_14", - "PSS0_LOGIC_OUTS22_15", - "PSS0_LOGIC_OUTS22_16", - "PSS0_LOGIC_OUTS22_17", - "PSS0_LOGIC_OUTS22_18", - "PSS0_LOGIC_OUTS22_19", - "PSS0_LOGIC_OUTS22_2", - "PSS0_LOGIC_OUTS22_3", - "PSS0_LOGIC_OUTS22_4", - "PSS0_LOGIC_OUTS22_5", - "PSS0_LOGIC_OUTS22_6", - "PSS0_LOGIC_OUTS22_7", - "PSS0_LOGIC_OUTS22_8", - "PSS0_LOGIC_OUTS22_9", - "PSS0_LOGIC_OUTS23_0", - "PSS0_LOGIC_OUTS23_1", - "PSS0_LOGIC_OUTS23_10", - "PSS0_LOGIC_OUTS23_11", - "PSS0_LOGIC_OUTS23_12", - "PSS0_LOGIC_OUTS23_13", - "PSS0_LOGIC_OUTS23_14", - "PSS0_LOGIC_OUTS23_15", - "PSS0_LOGIC_OUTS23_16", - "PSS0_LOGIC_OUTS23_17", - "PSS0_LOGIC_OUTS23_18", - "PSS0_LOGIC_OUTS23_19", - "PSS0_LOGIC_OUTS23_2", - "PSS0_LOGIC_OUTS23_3", - "PSS0_LOGIC_OUTS23_4", - "PSS0_LOGIC_OUTS23_5", - "PSS0_LOGIC_OUTS23_6", - "PSS0_LOGIC_OUTS23_7", - "PSS0_LOGIC_OUTS23_8", - "PSS0_LOGIC_OUTS23_9", - "PSS0_LOGIC_OUTS2_0", - "PSS0_LOGIC_OUTS2_1", - "PSS0_LOGIC_OUTS2_10", - "PSS0_LOGIC_OUTS2_11", - "PSS0_LOGIC_OUTS2_12", - "PSS0_LOGIC_OUTS2_13", - "PSS0_LOGIC_OUTS2_14", - "PSS0_LOGIC_OUTS2_15", - "PSS0_LOGIC_OUTS2_16", - "PSS0_LOGIC_OUTS2_17", - "PSS0_LOGIC_OUTS2_18", - "PSS0_LOGIC_OUTS2_19", - "PSS0_LOGIC_OUTS2_2", - "PSS0_LOGIC_OUTS2_3", - "PSS0_LOGIC_OUTS2_4", - "PSS0_LOGIC_OUTS2_5", - "PSS0_LOGIC_OUTS2_6", - "PSS0_LOGIC_OUTS2_7", - "PSS0_LOGIC_OUTS2_8", - "PSS0_LOGIC_OUTS2_9", - "PSS0_LOGIC_OUTS3_0", - "PSS0_LOGIC_OUTS3_1", - "PSS0_LOGIC_OUTS3_10", - "PSS0_LOGIC_OUTS3_11", - "PSS0_LOGIC_OUTS3_12", - "PSS0_LOGIC_OUTS3_13", - "PSS0_LOGIC_OUTS3_14", - "PSS0_LOGIC_OUTS3_15", - "PSS0_LOGIC_OUTS3_16", - "PSS0_LOGIC_OUTS3_17", - "PSS0_LOGIC_OUTS3_18", - "PSS0_LOGIC_OUTS3_19", - "PSS0_LOGIC_OUTS3_2", - "PSS0_LOGIC_OUTS3_3", - "PSS0_LOGIC_OUTS3_4", - "PSS0_LOGIC_OUTS3_5", - "PSS0_LOGIC_OUTS3_6", - "PSS0_LOGIC_OUTS3_7", - "PSS0_LOGIC_OUTS3_8", - "PSS0_LOGIC_OUTS3_9", - "PSS0_LOGIC_OUTS4_0", - "PSS0_LOGIC_OUTS4_1", - "PSS0_LOGIC_OUTS4_10", - "PSS0_LOGIC_OUTS4_11", - "PSS0_LOGIC_OUTS4_12", - "PSS0_LOGIC_OUTS4_13", - "PSS0_LOGIC_OUTS4_14", - "PSS0_LOGIC_OUTS4_15", - "PSS0_LOGIC_OUTS4_16", - "PSS0_LOGIC_OUTS4_17", - "PSS0_LOGIC_OUTS4_18", - "PSS0_LOGIC_OUTS4_19", - "PSS0_LOGIC_OUTS4_2", - "PSS0_LOGIC_OUTS4_3", - "PSS0_LOGIC_OUTS4_4", - "PSS0_LOGIC_OUTS4_5", - "PSS0_LOGIC_OUTS4_6", - "PSS0_LOGIC_OUTS4_7", - "PSS0_LOGIC_OUTS4_8", - "PSS0_LOGIC_OUTS4_9", - "PSS0_LOGIC_OUTS5_0", - "PSS0_LOGIC_OUTS5_1", - "PSS0_LOGIC_OUTS5_10", - "PSS0_LOGIC_OUTS5_11", - "PSS0_LOGIC_OUTS5_12", - "PSS0_LOGIC_OUTS5_13", - "PSS0_LOGIC_OUTS5_14", - "PSS0_LOGIC_OUTS5_15", - "PSS0_LOGIC_OUTS5_16", - "PSS0_LOGIC_OUTS5_17", - "PSS0_LOGIC_OUTS5_18", - "PSS0_LOGIC_OUTS5_19", - "PSS0_LOGIC_OUTS5_2", - "PSS0_LOGIC_OUTS5_3", - "PSS0_LOGIC_OUTS5_4", - "PSS0_LOGIC_OUTS5_5", - "PSS0_LOGIC_OUTS5_6", - "PSS0_LOGIC_OUTS5_7", - "PSS0_LOGIC_OUTS5_8", - "PSS0_LOGIC_OUTS5_9", - "PSS0_LOGIC_OUTS6_0", - "PSS0_LOGIC_OUTS6_1", - "PSS0_LOGIC_OUTS6_10", - "PSS0_LOGIC_OUTS6_11", - "PSS0_LOGIC_OUTS6_12", - "PSS0_LOGIC_OUTS6_13", - "PSS0_LOGIC_OUTS6_14", - "PSS0_LOGIC_OUTS6_15", - "PSS0_LOGIC_OUTS6_16", - "PSS0_LOGIC_OUTS6_17", - "PSS0_LOGIC_OUTS6_18", - "PSS0_LOGIC_OUTS6_19", - "PSS0_LOGIC_OUTS6_2", - "PSS0_LOGIC_OUTS6_3", - "PSS0_LOGIC_OUTS6_4", - "PSS0_LOGIC_OUTS6_5", - "PSS0_LOGIC_OUTS6_6", - "PSS0_LOGIC_OUTS6_7", - "PSS0_LOGIC_OUTS6_8", - "PSS0_LOGIC_OUTS6_9", - "PSS0_LOGIC_OUTS7_0", - "PSS0_LOGIC_OUTS7_1", - "PSS0_LOGIC_OUTS7_10", - "PSS0_LOGIC_OUTS7_11", - "PSS0_LOGIC_OUTS7_12", - "PSS0_LOGIC_OUTS7_13", - "PSS0_LOGIC_OUTS7_14", - "PSS0_LOGIC_OUTS7_15", - "PSS0_LOGIC_OUTS7_16", - "PSS0_LOGIC_OUTS7_17", - "PSS0_LOGIC_OUTS7_18", - "PSS0_LOGIC_OUTS7_19", - "PSS0_LOGIC_OUTS7_2", - "PSS0_LOGIC_OUTS7_3", - "PSS0_LOGIC_OUTS7_4", - "PSS0_LOGIC_OUTS7_5", - "PSS0_LOGIC_OUTS7_6", - "PSS0_LOGIC_OUTS7_7", - "PSS0_LOGIC_OUTS7_8", - "PSS0_LOGIC_OUTS7_9", - "PSS0_LOGIC_OUTS8_0", - "PSS0_LOGIC_OUTS8_1", - "PSS0_LOGIC_OUTS8_10", - "PSS0_LOGIC_OUTS8_11", - "PSS0_LOGIC_OUTS8_12", - "PSS0_LOGIC_OUTS8_13", - "PSS0_LOGIC_OUTS8_14", - "PSS0_LOGIC_OUTS8_15", - "PSS0_LOGIC_OUTS8_16", - "PSS0_LOGIC_OUTS8_17", - "PSS0_LOGIC_OUTS8_18", - "PSS0_LOGIC_OUTS8_19", - "PSS0_LOGIC_OUTS8_2", - "PSS0_LOGIC_OUTS8_3", - "PSS0_LOGIC_OUTS8_4", - "PSS0_LOGIC_OUTS8_5", - "PSS0_LOGIC_OUTS8_6", - "PSS0_LOGIC_OUTS8_7", - "PSS0_LOGIC_OUTS8_8", - "PSS0_LOGIC_OUTS8_9", - "PSS0_LOGIC_OUTS9_0", - "PSS0_LOGIC_OUTS9_1", - "PSS0_LOGIC_OUTS9_10", - "PSS0_LOGIC_OUTS9_11", - "PSS0_LOGIC_OUTS9_12", - "PSS0_LOGIC_OUTS9_13", - "PSS0_LOGIC_OUTS9_14", - "PSS0_LOGIC_OUTS9_15", - "PSS0_LOGIC_OUTS9_16", - "PSS0_LOGIC_OUTS9_17", - "PSS0_LOGIC_OUTS9_18", - "PSS0_LOGIC_OUTS9_19", - "PSS0_LOGIC_OUTS9_2", - "PSS0_LOGIC_OUTS9_3", - "PSS0_LOGIC_OUTS9_4", - "PSS0_LOGIC_OUTS9_5", - "PSS0_LOGIC_OUTS9_6", - "PSS0_LOGIC_OUTS9_7", - "PSS0_LOGIC_OUTS9_8", - "PSS0_LOGIC_OUTS9_9", - "PSS1_CLK_B0_0", - "PSS1_CLK_B0_1", - "PSS1_CLK_B0_10", - "PSS1_CLK_B0_11", - "PSS1_CLK_B0_12", - "PSS1_CLK_B0_13", - "PSS1_CLK_B0_14", - "PSS1_CLK_B0_15", - "PSS1_CLK_B0_16", - "PSS1_CLK_B0_17", - "PSS1_CLK_B0_18", - "PSS1_CLK_B0_19", - "PSS1_CLK_B0_2", - "PSS1_CLK_B0_20", - "PSS1_CLK_B0_21", - "PSS1_CLK_B0_22", - "PSS1_CLK_B0_23", - "PSS1_CLK_B0_24", - "PSS1_CLK_B0_25", - "PSS1_CLK_B0_26", - "PSS1_CLK_B0_27", - "PSS1_CLK_B0_28", - "PSS1_CLK_B0_29", - "PSS1_CLK_B0_3", - "PSS1_CLK_B0_30", - "PSS1_CLK_B0_31", - "PSS1_CLK_B0_32", - "PSS1_CLK_B0_33", - "PSS1_CLK_B0_34", - "PSS1_CLK_B0_35", - "PSS1_CLK_B0_36", - "PSS1_CLK_B0_37", - "PSS1_CLK_B0_38", - "PSS1_CLK_B0_39", - "PSS1_CLK_B0_4", - "PSS1_CLK_B0_5", - "PSS1_CLK_B0_6", - "PSS1_CLK_B0_7", - "PSS1_CLK_B0_8", - "PSS1_CLK_B0_9", - "PSS1_CLK_B1_0", - "PSS1_CLK_B1_1", - "PSS1_CLK_B1_10", - "PSS1_CLK_B1_11", - "PSS1_CLK_B1_12", - "PSS1_CLK_B1_13", - "PSS1_CLK_B1_14", - "PSS1_CLK_B1_15", - "PSS1_CLK_B1_16", - "PSS1_CLK_B1_17", - "PSS1_CLK_B1_18", - "PSS1_CLK_B1_19", - "PSS1_CLK_B1_2", - "PSS1_CLK_B1_20", - "PSS1_CLK_B1_21", - "PSS1_CLK_B1_22", - "PSS1_CLK_B1_23", - "PSS1_CLK_B1_24", - "PSS1_CLK_B1_25", - "PSS1_CLK_B1_26", - "PSS1_CLK_B1_27", - "PSS1_CLK_B1_28", - "PSS1_CLK_B1_29", - "PSS1_CLK_B1_3", - "PSS1_CLK_B1_30", - "PSS1_CLK_B1_31", - "PSS1_CLK_B1_32", - "PSS1_CLK_B1_33", - "PSS1_CLK_B1_34", - "PSS1_CLK_B1_35", - "PSS1_CLK_B1_36", - "PSS1_CLK_B1_37", - "PSS1_CLK_B1_38", - "PSS1_CLK_B1_39", - "PSS1_CLK_B1_4", - "PSS1_CLK_B1_5", - "PSS1_CLK_B1_6", - "PSS1_CLK_B1_7", - "PSS1_CLK_B1_8", - "PSS1_CLK_B1_9", - "PSS1_IMUX_B0_0", - "PSS1_IMUX_B0_1", - "PSS1_IMUX_B0_10", - "PSS1_IMUX_B0_11", - "PSS1_IMUX_B0_12", - "PSS1_IMUX_B0_13", - "PSS1_IMUX_B0_14", - "PSS1_IMUX_B0_15", - "PSS1_IMUX_B0_16", - "PSS1_IMUX_B0_17", - "PSS1_IMUX_B0_18", - "PSS1_IMUX_B0_19", - "PSS1_IMUX_B0_2", - "PSS1_IMUX_B0_20", - "PSS1_IMUX_B0_21", - "PSS1_IMUX_B0_22", - "PSS1_IMUX_B0_23", - "PSS1_IMUX_B0_24", - "PSS1_IMUX_B0_25", - "PSS1_IMUX_B0_26", - "PSS1_IMUX_B0_27", - "PSS1_IMUX_B0_28", - "PSS1_IMUX_B0_29", - "PSS1_IMUX_B0_3", - "PSS1_IMUX_B0_30", - "PSS1_IMUX_B0_31", - "PSS1_IMUX_B0_32", - "PSS1_IMUX_B0_33", - "PSS1_IMUX_B0_34", - "PSS1_IMUX_B0_35", - "PSS1_IMUX_B0_36", - "PSS1_IMUX_B0_37", - "PSS1_IMUX_B0_38", - "PSS1_IMUX_B0_39", - "PSS1_IMUX_B0_4", - "PSS1_IMUX_B0_5", - "PSS1_IMUX_B0_6", - "PSS1_IMUX_B0_7", - "PSS1_IMUX_B0_8", - "PSS1_IMUX_B0_9", - "PSS1_IMUX_B10_0", - "PSS1_IMUX_B10_1", - "PSS1_IMUX_B10_10", - "PSS1_IMUX_B10_11", - "PSS1_IMUX_B10_12", - "PSS1_IMUX_B10_13", - "PSS1_IMUX_B10_14", - "PSS1_IMUX_B10_15", - "PSS1_IMUX_B10_16", - "PSS1_IMUX_B10_17", - "PSS1_IMUX_B10_18", - "PSS1_IMUX_B10_19", - "PSS1_IMUX_B10_2", - "PSS1_IMUX_B10_20", - "PSS1_IMUX_B10_21", - "PSS1_IMUX_B10_22", - "PSS1_IMUX_B10_23", - "PSS1_IMUX_B10_24", - "PSS1_IMUX_B10_25", - "PSS1_IMUX_B10_26", - "PSS1_IMUX_B10_27", - "PSS1_IMUX_B10_28", - "PSS1_IMUX_B10_29", - "PSS1_IMUX_B10_3", - "PSS1_IMUX_B10_30", - "PSS1_IMUX_B10_31", - "PSS1_IMUX_B10_32", - "PSS1_IMUX_B10_33", - "PSS1_IMUX_B10_34", - "PSS1_IMUX_B10_35", - "PSS1_IMUX_B10_36", - "PSS1_IMUX_B10_37", - "PSS1_IMUX_B10_38", - "PSS1_IMUX_B10_39", - "PSS1_IMUX_B10_4", - "PSS1_IMUX_B10_5", - "PSS1_IMUX_B10_6", - "PSS1_IMUX_B10_7", - "PSS1_IMUX_B10_8", - "PSS1_IMUX_B10_9", - "PSS1_IMUX_B11_0", - "PSS1_IMUX_B11_1", - "PSS1_IMUX_B11_10", - "PSS1_IMUX_B11_11", - "PSS1_IMUX_B11_12", - "PSS1_IMUX_B11_13", - "PSS1_IMUX_B11_14", - "PSS1_IMUX_B11_15", - "PSS1_IMUX_B11_16", - "PSS1_IMUX_B11_17", - "PSS1_IMUX_B11_18", - "PSS1_IMUX_B11_19", - "PSS1_IMUX_B11_2", - "PSS1_IMUX_B11_20", - "PSS1_IMUX_B11_21", - "PSS1_IMUX_B11_22", - "PSS1_IMUX_B11_23", - "PSS1_IMUX_B11_24", - "PSS1_IMUX_B11_25", - "PSS1_IMUX_B11_26", - "PSS1_IMUX_B11_27", - "PSS1_IMUX_B11_28", - "PSS1_IMUX_B11_29", - "PSS1_IMUX_B11_3", - "PSS1_IMUX_B11_30", - "PSS1_IMUX_B11_31", - "PSS1_IMUX_B11_32", - "PSS1_IMUX_B11_33", - "PSS1_IMUX_B11_34", - "PSS1_IMUX_B11_35", - "PSS1_IMUX_B11_36", - "PSS1_IMUX_B11_37", - "PSS1_IMUX_B11_38", - "PSS1_IMUX_B11_39", - "PSS1_IMUX_B11_4", - "PSS1_IMUX_B11_5", - "PSS1_IMUX_B11_6", - "PSS1_IMUX_B11_7", - "PSS1_IMUX_B11_8", - "PSS1_IMUX_B11_9", - "PSS1_IMUX_B12_0", - "PSS1_IMUX_B12_1", - "PSS1_IMUX_B12_10", - "PSS1_IMUX_B12_11", - "PSS1_IMUX_B12_12", - "PSS1_IMUX_B12_13", - "PSS1_IMUX_B12_14", - "PSS1_IMUX_B12_15", - "PSS1_IMUX_B12_16", - "PSS1_IMUX_B12_17", - "PSS1_IMUX_B12_18", - "PSS1_IMUX_B12_19", - "PSS1_IMUX_B12_2", - "PSS1_IMUX_B12_20", - "PSS1_IMUX_B12_21", - "PSS1_IMUX_B12_22", - "PSS1_IMUX_B12_23", - "PSS1_IMUX_B12_24", - "PSS1_IMUX_B12_25", - "PSS1_IMUX_B12_26", - "PSS1_IMUX_B12_27", - "PSS1_IMUX_B12_28", - "PSS1_IMUX_B12_29", - "PSS1_IMUX_B12_3", - "PSS1_IMUX_B12_30", - "PSS1_IMUX_B12_31", - "PSS1_IMUX_B12_32", - "PSS1_IMUX_B12_33", - "PSS1_IMUX_B12_34", - "PSS1_IMUX_B12_35", - "PSS1_IMUX_B12_36", - "PSS1_IMUX_B12_37", - "PSS1_IMUX_B12_38", - "PSS1_IMUX_B12_39", - "PSS1_IMUX_B12_4", - "PSS1_IMUX_B12_5", - "PSS1_IMUX_B12_6", - "PSS1_IMUX_B12_7", - "PSS1_IMUX_B12_8", - "PSS1_IMUX_B12_9", - "PSS1_IMUX_B13_0", - "PSS1_IMUX_B13_1", - "PSS1_IMUX_B13_10", - "PSS1_IMUX_B13_11", - "PSS1_IMUX_B13_12", - "PSS1_IMUX_B13_13", - "PSS1_IMUX_B13_14", - "PSS1_IMUX_B13_15", - "PSS1_IMUX_B13_16", - "PSS1_IMUX_B13_17", - "PSS1_IMUX_B13_18", - "PSS1_IMUX_B13_19", - "PSS1_IMUX_B13_2", - "PSS1_IMUX_B13_20", - "PSS1_IMUX_B13_21", - "PSS1_IMUX_B13_22", - "PSS1_IMUX_B13_23", - "PSS1_IMUX_B13_24", - "PSS1_IMUX_B13_25", - "PSS1_IMUX_B13_26", - "PSS1_IMUX_B13_27", - "PSS1_IMUX_B13_28", - "PSS1_IMUX_B13_29", - "PSS1_IMUX_B13_3", - "PSS1_IMUX_B13_30", - "PSS1_IMUX_B13_31", - "PSS1_IMUX_B13_32", - "PSS1_IMUX_B13_33", - "PSS1_IMUX_B13_34", - "PSS1_IMUX_B13_35", - "PSS1_IMUX_B13_36", - "PSS1_IMUX_B13_37", - "PSS1_IMUX_B13_38", - "PSS1_IMUX_B13_39", - "PSS1_IMUX_B13_4", - "PSS1_IMUX_B13_5", - "PSS1_IMUX_B13_6", - "PSS1_IMUX_B13_7", - "PSS1_IMUX_B13_8", - "PSS1_IMUX_B13_9", - "PSS1_IMUX_B14_0", - "PSS1_IMUX_B14_1", - "PSS1_IMUX_B14_10", - "PSS1_IMUX_B14_11", - "PSS1_IMUX_B14_12", - "PSS1_IMUX_B14_13", - "PSS1_IMUX_B14_14", - "PSS1_IMUX_B14_15", - "PSS1_IMUX_B14_16", - "PSS1_IMUX_B14_17", - "PSS1_IMUX_B14_18", - "PSS1_IMUX_B14_19", - "PSS1_IMUX_B14_2", - "PSS1_IMUX_B14_20", - "PSS1_IMUX_B14_21", - "PSS1_IMUX_B14_22", - "PSS1_IMUX_B14_23", - "PSS1_IMUX_B14_24", - "PSS1_IMUX_B14_25", - "PSS1_IMUX_B14_26", - "PSS1_IMUX_B14_27", - "PSS1_IMUX_B14_28", - "PSS1_IMUX_B14_29", - "PSS1_IMUX_B14_3", - "PSS1_IMUX_B14_30", - "PSS1_IMUX_B14_31", - "PSS1_IMUX_B14_32", - "PSS1_IMUX_B14_33", - "PSS1_IMUX_B14_34", - "PSS1_IMUX_B14_35", - "PSS1_IMUX_B14_36", - "PSS1_IMUX_B14_37", - "PSS1_IMUX_B14_38", - "PSS1_IMUX_B14_39", - "PSS1_IMUX_B14_4", - "PSS1_IMUX_B14_5", - "PSS1_IMUX_B14_6", - "PSS1_IMUX_B14_7", - "PSS1_IMUX_B14_8", - "PSS1_IMUX_B14_9", - "PSS1_IMUX_B15_0", - "PSS1_IMUX_B15_1", - "PSS1_IMUX_B15_10", - "PSS1_IMUX_B15_11", - "PSS1_IMUX_B15_12", - "PSS1_IMUX_B15_13", - "PSS1_IMUX_B15_14", - "PSS1_IMUX_B15_15", - "PSS1_IMUX_B15_16", - "PSS1_IMUX_B15_17", - "PSS1_IMUX_B15_18", - "PSS1_IMUX_B15_19", - "PSS1_IMUX_B15_2", - "PSS1_IMUX_B15_20", - "PSS1_IMUX_B15_21", - "PSS1_IMUX_B15_22", - "PSS1_IMUX_B15_23", - "PSS1_IMUX_B15_24", - "PSS1_IMUX_B15_25", - "PSS1_IMUX_B15_26", - "PSS1_IMUX_B15_27", - "PSS1_IMUX_B15_28", - "PSS1_IMUX_B15_29", - "PSS1_IMUX_B15_3", - "PSS1_IMUX_B15_30", - "PSS1_IMUX_B15_31", - "PSS1_IMUX_B15_32", - "PSS1_IMUX_B15_33", - "PSS1_IMUX_B15_34", - "PSS1_IMUX_B15_35", - "PSS1_IMUX_B15_36", - "PSS1_IMUX_B15_37", - "PSS1_IMUX_B15_38", - "PSS1_IMUX_B15_39", - "PSS1_IMUX_B15_4", - "PSS1_IMUX_B15_5", - "PSS1_IMUX_B15_6", - "PSS1_IMUX_B15_7", - "PSS1_IMUX_B15_8", - "PSS1_IMUX_B15_9", - "PSS1_IMUX_B16_0", - "PSS1_IMUX_B16_1", - "PSS1_IMUX_B16_10", - "PSS1_IMUX_B16_11", - "PSS1_IMUX_B16_12", - "PSS1_IMUX_B16_13", - "PSS1_IMUX_B16_14", - "PSS1_IMUX_B16_15", - "PSS1_IMUX_B16_16", - "PSS1_IMUX_B16_17", - "PSS1_IMUX_B16_18", - "PSS1_IMUX_B16_19", - "PSS1_IMUX_B16_2", - "PSS1_IMUX_B16_20", - "PSS1_IMUX_B16_21", - "PSS1_IMUX_B16_22", - "PSS1_IMUX_B16_23", - "PSS1_IMUX_B16_24", - "PSS1_IMUX_B16_25", - "PSS1_IMUX_B16_26", - "PSS1_IMUX_B16_27", - "PSS1_IMUX_B16_28", - "PSS1_IMUX_B16_29", - "PSS1_IMUX_B16_3", - "PSS1_IMUX_B16_30", - "PSS1_IMUX_B16_31", - "PSS1_IMUX_B16_32", - "PSS1_IMUX_B16_33", - "PSS1_IMUX_B16_34", - "PSS1_IMUX_B16_35", - "PSS1_IMUX_B16_36", - "PSS1_IMUX_B16_37", - "PSS1_IMUX_B16_38", - "PSS1_IMUX_B16_39", - "PSS1_IMUX_B16_4", - "PSS1_IMUX_B16_5", - "PSS1_IMUX_B16_6", - "PSS1_IMUX_B16_7", - "PSS1_IMUX_B16_8", - "PSS1_IMUX_B16_9", - "PSS1_IMUX_B17_0", - "PSS1_IMUX_B17_1", - "PSS1_IMUX_B17_10", - "PSS1_IMUX_B17_11", - "PSS1_IMUX_B17_12", - "PSS1_IMUX_B17_13", - "PSS1_IMUX_B17_14", - "PSS1_IMUX_B17_15", - "PSS1_IMUX_B17_16", - "PSS1_IMUX_B17_17", - "PSS1_IMUX_B17_18", - "PSS1_IMUX_B17_19", - "PSS1_IMUX_B17_2", - "PSS1_IMUX_B17_20", - "PSS1_IMUX_B17_21", - "PSS1_IMUX_B17_22", - "PSS1_IMUX_B17_23", - "PSS1_IMUX_B17_24", - "PSS1_IMUX_B17_25", - "PSS1_IMUX_B17_26", - "PSS1_IMUX_B17_27", - "PSS1_IMUX_B17_28", - "PSS1_IMUX_B17_29", - "PSS1_IMUX_B17_3", - "PSS1_IMUX_B17_30", - "PSS1_IMUX_B17_31", - "PSS1_IMUX_B17_32", - "PSS1_IMUX_B17_33", - "PSS1_IMUX_B17_34", - "PSS1_IMUX_B17_35", - "PSS1_IMUX_B17_36", - "PSS1_IMUX_B17_37", - "PSS1_IMUX_B17_38", - "PSS1_IMUX_B17_39", - "PSS1_IMUX_B17_4", - "PSS1_IMUX_B17_5", - "PSS1_IMUX_B17_6", - "PSS1_IMUX_B17_7", - "PSS1_IMUX_B17_8", - "PSS1_IMUX_B17_9", - "PSS1_IMUX_B18_0", - "PSS1_IMUX_B18_1", - "PSS1_IMUX_B18_10", - "PSS1_IMUX_B18_11", - "PSS1_IMUX_B18_12", - "PSS1_IMUX_B18_13", - "PSS1_IMUX_B18_14", - "PSS1_IMUX_B18_15", - "PSS1_IMUX_B18_16", - "PSS1_IMUX_B18_17", - "PSS1_IMUX_B18_18", - "PSS1_IMUX_B18_19", - "PSS1_IMUX_B18_2", - "PSS1_IMUX_B18_20", - "PSS1_IMUX_B18_21", - "PSS1_IMUX_B18_22", - "PSS1_IMUX_B18_23", - "PSS1_IMUX_B18_24", - "PSS1_IMUX_B18_25", - "PSS1_IMUX_B18_26", - "PSS1_IMUX_B18_27", - "PSS1_IMUX_B18_28", - "PSS1_IMUX_B18_29", - "PSS1_IMUX_B18_3", - "PSS1_IMUX_B18_30", - "PSS1_IMUX_B18_31", - "PSS1_IMUX_B18_32", - "PSS1_IMUX_B18_33", - "PSS1_IMUX_B18_34", - "PSS1_IMUX_B18_35", - "PSS1_IMUX_B18_36", - "PSS1_IMUX_B18_37", - "PSS1_IMUX_B18_38", - "PSS1_IMUX_B18_39", - "PSS1_IMUX_B18_4", - "PSS1_IMUX_B18_5", - "PSS1_IMUX_B18_6", - "PSS1_IMUX_B18_7", - "PSS1_IMUX_B18_8", - "PSS1_IMUX_B18_9", - "PSS1_IMUX_B19_0", - "PSS1_IMUX_B19_1", - "PSS1_IMUX_B19_10", - "PSS1_IMUX_B19_11", - "PSS1_IMUX_B19_12", - "PSS1_IMUX_B19_13", - "PSS1_IMUX_B19_14", - "PSS1_IMUX_B19_15", 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"PSS1_IMUX_B1_21", - "PSS1_IMUX_B1_22", - "PSS1_IMUX_B1_23", - "PSS1_IMUX_B1_24", - "PSS1_IMUX_B1_25", - "PSS1_IMUX_B1_26", - "PSS1_IMUX_B1_27", - "PSS1_IMUX_B1_28", - "PSS1_IMUX_B1_29", - "PSS1_IMUX_B1_3", - "PSS1_IMUX_B1_30", - "PSS1_IMUX_B1_31", - "PSS1_IMUX_B1_32", - "PSS1_IMUX_B1_33", - "PSS1_IMUX_B1_34", - "PSS1_IMUX_B1_35", - "PSS1_IMUX_B1_36", - "PSS1_IMUX_B1_37", - "PSS1_IMUX_B1_38", - "PSS1_IMUX_B1_39", - "PSS1_IMUX_B1_4", - "PSS1_IMUX_B1_5", - "PSS1_IMUX_B1_6", - "PSS1_IMUX_B1_7", - "PSS1_IMUX_B1_8", - "PSS1_IMUX_B1_9", - "PSS1_IMUX_B20_0", - "PSS1_IMUX_B20_1", - "PSS1_IMUX_B20_10", - "PSS1_IMUX_B20_11", - "PSS1_IMUX_B20_12", - "PSS1_IMUX_B20_13", - "PSS1_IMUX_B20_14", - "PSS1_IMUX_B20_15", - "PSS1_IMUX_B20_16", - "PSS1_IMUX_B20_17", - "PSS1_IMUX_B20_18", - "PSS1_IMUX_B20_19", - "PSS1_IMUX_B20_2", - "PSS1_IMUX_B20_20", - "PSS1_IMUX_B20_21", - "PSS1_IMUX_B20_22", - "PSS1_IMUX_B20_23", - "PSS1_IMUX_B20_24", - "PSS1_IMUX_B20_25", - "PSS1_IMUX_B20_26", - "PSS1_IMUX_B20_27", - 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"PSS1_IMUX_B21_33", - "PSS1_IMUX_B21_34", - "PSS1_IMUX_B21_35", - "PSS1_IMUX_B21_36", - "PSS1_IMUX_B21_37", - "PSS1_IMUX_B21_38", - "PSS1_IMUX_B21_39", - "PSS1_IMUX_B21_4", - "PSS1_IMUX_B21_5", - "PSS1_IMUX_B21_6", - "PSS1_IMUX_B21_7", - "PSS1_IMUX_B21_8", - "PSS1_IMUX_B21_9", - "PSS1_IMUX_B22_0", - "PSS1_IMUX_B22_1", - "PSS1_IMUX_B22_10", - "PSS1_IMUX_B22_11", - "PSS1_IMUX_B22_12", - "PSS1_IMUX_B22_13", - "PSS1_IMUX_B22_14", - "PSS1_IMUX_B22_15", - "PSS1_IMUX_B22_16", - "PSS1_IMUX_B22_17", - "PSS1_IMUX_B22_18", - "PSS1_IMUX_B22_19", - "PSS1_IMUX_B22_2", - "PSS1_IMUX_B22_20", - "PSS1_IMUX_B22_21", - "PSS1_IMUX_B22_22", - "PSS1_IMUX_B22_23", - "PSS1_IMUX_B22_24", - "PSS1_IMUX_B22_25", - "PSS1_IMUX_B22_26", - "PSS1_IMUX_B22_27", - "PSS1_IMUX_B22_28", - "PSS1_IMUX_B22_29", - "PSS1_IMUX_B22_3", - "PSS1_IMUX_B22_30", - "PSS1_IMUX_B22_31", - "PSS1_IMUX_B22_32", - "PSS1_IMUX_B22_33", - "PSS1_IMUX_B22_34", - "PSS1_IMUX_B22_35", - "PSS1_IMUX_B22_36", - "PSS1_IMUX_B22_37", - "PSS1_IMUX_B22_38", - "PSS1_IMUX_B22_39", - "PSS1_IMUX_B22_4", - "PSS1_IMUX_B22_5", - "PSS1_IMUX_B22_6", - "PSS1_IMUX_B22_7", - "PSS1_IMUX_B22_8", - "PSS1_IMUX_B22_9", - "PSS1_IMUX_B23_0", - "PSS1_IMUX_B23_1", - "PSS1_IMUX_B23_10", - "PSS1_IMUX_B23_11", - "PSS1_IMUX_B23_12", - "PSS1_IMUX_B23_13", - "PSS1_IMUX_B23_14", - "PSS1_IMUX_B23_15", - "PSS1_IMUX_B23_16", - "PSS1_IMUX_B23_17", - "PSS1_IMUX_B23_18", - "PSS1_IMUX_B23_19", - "PSS1_IMUX_B23_2", - "PSS1_IMUX_B23_20", - "PSS1_IMUX_B23_21", - "PSS1_IMUX_B23_22", - "PSS1_IMUX_B23_23", - "PSS1_IMUX_B23_24", - "PSS1_IMUX_B23_25", - "PSS1_IMUX_B23_26", - "PSS1_IMUX_B23_27", - "PSS1_IMUX_B23_28", - "PSS1_IMUX_B23_29", - "PSS1_IMUX_B23_3", - "PSS1_IMUX_B23_30", - "PSS1_IMUX_B23_31", - "PSS1_IMUX_B23_32", - "PSS1_IMUX_B23_33", - "PSS1_IMUX_B23_34", - "PSS1_IMUX_B23_35", - "PSS1_IMUX_B23_36", - "PSS1_IMUX_B23_37", - "PSS1_IMUX_B23_38", - "PSS1_IMUX_B23_39", - "PSS1_IMUX_B23_4", - "PSS1_IMUX_B23_5", - "PSS1_IMUX_B23_6", - "PSS1_IMUX_B23_7", - "PSS1_IMUX_B23_8", - "PSS1_IMUX_B23_9", - "PSS1_IMUX_B24_0", - "PSS1_IMUX_B24_1", - "PSS1_IMUX_B24_10", - "PSS1_IMUX_B24_11", - "PSS1_IMUX_B24_12", - "PSS1_IMUX_B24_13", - "PSS1_IMUX_B24_14", - "PSS1_IMUX_B24_15", - "PSS1_IMUX_B24_16", - "PSS1_IMUX_B24_17", - "PSS1_IMUX_B24_18", - "PSS1_IMUX_B24_19", - "PSS1_IMUX_B24_2", - "PSS1_IMUX_B24_20", - "PSS1_IMUX_B24_21", - "PSS1_IMUX_B24_22", - "PSS1_IMUX_B24_23", - "PSS1_IMUX_B24_24", - "PSS1_IMUX_B24_25", - "PSS1_IMUX_B24_26", - "PSS1_IMUX_B24_27", - "PSS1_IMUX_B24_28", - "PSS1_IMUX_B24_29", - "PSS1_IMUX_B24_3", - "PSS1_IMUX_B24_30", - "PSS1_IMUX_B24_31", - "PSS1_IMUX_B24_32", - "PSS1_IMUX_B24_33", - "PSS1_IMUX_B24_34", - "PSS1_IMUX_B24_35", - "PSS1_IMUX_B24_36", - "PSS1_IMUX_B24_37", - "PSS1_IMUX_B24_38", - "PSS1_IMUX_B24_39", - "PSS1_IMUX_B24_4", - "PSS1_IMUX_B24_5", - "PSS1_IMUX_B24_6", - "PSS1_IMUX_B24_7", - "PSS1_IMUX_B24_8", - "PSS1_IMUX_B24_9", - "PSS1_IMUX_B25_0", - "PSS1_IMUX_B25_1", - "PSS1_IMUX_B25_10", - "PSS1_IMUX_B25_11", - "PSS1_IMUX_B25_12", - "PSS1_IMUX_B25_13", - "PSS1_IMUX_B25_14", - "PSS1_IMUX_B25_15", - "PSS1_IMUX_B25_16", - "PSS1_IMUX_B25_17", - "PSS1_IMUX_B25_18", - "PSS1_IMUX_B25_19", - "PSS1_IMUX_B25_2", - "PSS1_IMUX_B25_20", - "PSS1_IMUX_B25_21", - "PSS1_IMUX_B25_22", - "PSS1_IMUX_B25_23", - "PSS1_IMUX_B25_24", - "PSS1_IMUX_B25_25", - "PSS1_IMUX_B25_26", - "PSS1_IMUX_B25_27", - "PSS1_IMUX_B25_28", - "PSS1_IMUX_B25_29", - "PSS1_IMUX_B25_3", - "PSS1_IMUX_B25_30", - "PSS1_IMUX_B25_31", - "PSS1_IMUX_B25_32", - "PSS1_IMUX_B25_33", - "PSS1_IMUX_B25_34", - "PSS1_IMUX_B25_35", - "PSS1_IMUX_B25_36", - "PSS1_IMUX_B25_37", - "PSS1_IMUX_B25_38", - "PSS1_IMUX_B25_39", - "PSS1_IMUX_B25_4", - "PSS1_IMUX_B25_5", - "PSS1_IMUX_B25_6", - "PSS1_IMUX_B25_7", - "PSS1_IMUX_B25_8", - "PSS1_IMUX_B25_9", - "PSS1_IMUX_B26_0", - "PSS1_IMUX_B26_1", - "PSS1_IMUX_B26_10", - "PSS1_IMUX_B26_11", - "PSS1_IMUX_B26_12", - "PSS1_IMUX_B26_13", - "PSS1_IMUX_B26_14", - "PSS1_IMUX_B26_15", - "PSS1_IMUX_B26_16", - "PSS1_IMUX_B26_17", - "PSS1_IMUX_B26_18", - "PSS1_IMUX_B26_19", - "PSS1_IMUX_B26_2", - "PSS1_IMUX_B26_20", - "PSS1_IMUX_B26_21", - "PSS1_IMUX_B26_22", - "PSS1_IMUX_B26_23", - "PSS1_IMUX_B26_24", - "PSS1_IMUX_B26_25", - "PSS1_IMUX_B26_26", - "PSS1_IMUX_B26_27", - "PSS1_IMUX_B26_28", - "PSS1_IMUX_B26_29", - "PSS1_IMUX_B26_3", - "PSS1_IMUX_B26_30", - "PSS1_IMUX_B26_31", - "PSS1_IMUX_B26_32", - "PSS1_IMUX_B26_33", - "PSS1_IMUX_B26_34", - "PSS1_IMUX_B26_35", - "PSS1_IMUX_B26_36", - "PSS1_IMUX_B26_37", - "PSS1_IMUX_B26_38", - "PSS1_IMUX_B26_39", - "PSS1_IMUX_B26_4", - "PSS1_IMUX_B26_5", - "PSS1_IMUX_B26_6", - "PSS1_IMUX_B26_7", - "PSS1_IMUX_B26_8", - "PSS1_IMUX_B26_9", - "PSS1_IMUX_B27_0", - "PSS1_IMUX_B27_1", - "PSS1_IMUX_B27_10", - "PSS1_IMUX_B27_11", - "PSS1_IMUX_B27_12", - "PSS1_IMUX_B27_13", - "PSS1_IMUX_B27_14", - "PSS1_IMUX_B27_15", - "PSS1_IMUX_B27_16", - "PSS1_IMUX_B27_17", - "PSS1_IMUX_B27_18", - "PSS1_IMUX_B27_19", - "PSS1_IMUX_B27_2", - "PSS1_IMUX_B27_20", - "PSS1_IMUX_B27_21", - "PSS1_IMUX_B27_22", - "PSS1_IMUX_B27_23", - "PSS1_IMUX_B27_24", - "PSS1_IMUX_B27_25", - "PSS1_IMUX_B27_26", - "PSS1_IMUX_B27_27", - "PSS1_IMUX_B27_28", - "PSS1_IMUX_B27_29", - "PSS1_IMUX_B27_3", - "PSS1_IMUX_B27_30", - "PSS1_IMUX_B27_31", - "PSS1_IMUX_B27_32", - "PSS1_IMUX_B27_33", - "PSS1_IMUX_B27_34", - "PSS1_IMUX_B27_35", - "PSS1_IMUX_B27_36", - "PSS1_IMUX_B27_37", - "PSS1_IMUX_B27_38", - "PSS1_IMUX_B27_39", - "PSS1_IMUX_B27_4", - "PSS1_IMUX_B27_5", - "PSS1_IMUX_B27_6", - "PSS1_IMUX_B27_7", - "PSS1_IMUX_B27_8", - "PSS1_IMUX_B27_9", - "PSS1_IMUX_B28_0", - "PSS1_IMUX_B28_1", - "PSS1_IMUX_B28_10", - "PSS1_IMUX_B28_11", - "PSS1_IMUX_B28_12", - "PSS1_IMUX_B28_13", - "PSS1_IMUX_B28_14", - "PSS1_IMUX_B28_15", - "PSS1_IMUX_B28_16", - "PSS1_IMUX_B28_17", - "PSS1_IMUX_B28_18", - "PSS1_IMUX_B28_19", - "PSS1_IMUX_B28_2", - "PSS1_IMUX_B28_20", - "PSS1_IMUX_B28_21", - "PSS1_IMUX_B28_22", - "PSS1_IMUX_B28_23", - "PSS1_IMUX_B28_24", - "PSS1_IMUX_B28_25", - "PSS1_IMUX_B28_26", - "PSS1_IMUX_B28_27", - "PSS1_IMUX_B28_28", - "PSS1_IMUX_B28_29", - "PSS1_IMUX_B28_3", - "PSS1_IMUX_B28_30", - "PSS1_IMUX_B28_31", - "PSS1_IMUX_B28_32", - "PSS1_IMUX_B28_33", - "PSS1_IMUX_B28_34", - "PSS1_IMUX_B28_35", - "PSS1_IMUX_B28_36", - "PSS1_IMUX_B28_37", - "PSS1_IMUX_B28_38", - "PSS1_IMUX_B28_39", - "PSS1_IMUX_B28_4", - "PSS1_IMUX_B28_5", - "PSS1_IMUX_B28_6", - "PSS1_IMUX_B28_7", - "PSS1_IMUX_B28_8", - "PSS1_IMUX_B28_9", - "PSS1_IMUX_B29_0", - "PSS1_IMUX_B29_1", - "PSS1_IMUX_B29_10", - "PSS1_IMUX_B29_11", - "PSS1_IMUX_B29_12", - "PSS1_IMUX_B29_13", - "PSS1_IMUX_B29_14", - "PSS1_IMUX_B29_15", - "PSS1_IMUX_B29_16", - "PSS1_IMUX_B29_17", - "PSS1_IMUX_B29_18", - "PSS1_IMUX_B29_19", - "PSS1_IMUX_B29_2", - "PSS1_IMUX_B29_20", - "PSS1_IMUX_B29_21", - "PSS1_IMUX_B29_22", - "PSS1_IMUX_B29_23", - "PSS1_IMUX_B29_24", - "PSS1_IMUX_B29_25", - "PSS1_IMUX_B29_26", - "PSS1_IMUX_B29_27", - "PSS1_IMUX_B29_28", - "PSS1_IMUX_B29_29", - "PSS1_IMUX_B29_3", - "PSS1_IMUX_B29_30", - "PSS1_IMUX_B29_31", - "PSS1_IMUX_B29_32", - "PSS1_IMUX_B29_33", - "PSS1_IMUX_B29_34", - "PSS1_IMUX_B29_35", - "PSS1_IMUX_B29_36", - "PSS1_IMUX_B29_37", - "PSS1_IMUX_B29_38", - "PSS1_IMUX_B29_39", - "PSS1_IMUX_B29_4", - "PSS1_IMUX_B29_5", - "PSS1_IMUX_B29_6", - "PSS1_IMUX_B29_7", - "PSS1_IMUX_B29_8", - "PSS1_IMUX_B29_9", - "PSS1_IMUX_B2_0", - "PSS1_IMUX_B2_1", - "PSS1_IMUX_B2_10", - "PSS1_IMUX_B2_11", - "PSS1_IMUX_B2_12", - "PSS1_IMUX_B2_13", - "PSS1_IMUX_B2_14", - "PSS1_IMUX_B2_15", - "PSS1_IMUX_B2_16", - "PSS1_IMUX_B2_17", - "PSS1_IMUX_B2_18", - "PSS1_IMUX_B2_19", - "PSS1_IMUX_B2_2", - "PSS1_IMUX_B2_20", - "PSS1_IMUX_B2_21", - "PSS1_IMUX_B2_22", - "PSS1_IMUX_B2_23", - "PSS1_IMUX_B2_24", - "PSS1_IMUX_B2_25", - "PSS1_IMUX_B2_26", - "PSS1_IMUX_B2_27", - "PSS1_IMUX_B2_28", - "PSS1_IMUX_B2_29", - "PSS1_IMUX_B2_3", - "PSS1_IMUX_B2_30", - "PSS1_IMUX_B2_31", - "PSS1_IMUX_B2_32", - "PSS1_IMUX_B2_33", - "PSS1_IMUX_B2_34", - "PSS1_IMUX_B2_35", - "PSS1_IMUX_B2_36", - "PSS1_IMUX_B2_37", - "PSS1_IMUX_B2_38", - "PSS1_IMUX_B2_39", - "PSS1_IMUX_B2_4", - "PSS1_IMUX_B2_5", - "PSS1_IMUX_B2_6", - "PSS1_IMUX_B2_7", - "PSS1_IMUX_B2_8", - "PSS1_IMUX_B2_9", - "PSS1_IMUX_B30_0", - "PSS1_IMUX_B30_1", - "PSS1_IMUX_B30_10", - "PSS1_IMUX_B30_11", - "PSS1_IMUX_B30_12", - "PSS1_IMUX_B30_13", - "PSS1_IMUX_B30_14", - "PSS1_IMUX_B30_15", - "PSS1_IMUX_B30_16", - "PSS1_IMUX_B30_17", - "PSS1_IMUX_B30_18", - "PSS1_IMUX_B30_19", - "PSS1_IMUX_B30_2", - "PSS1_IMUX_B30_20", - "PSS1_IMUX_B30_21", - "PSS1_IMUX_B30_22", - "PSS1_IMUX_B30_23", - "PSS1_IMUX_B30_24", - "PSS1_IMUX_B30_25", - "PSS1_IMUX_B30_26", - "PSS1_IMUX_B30_27", - "PSS1_IMUX_B30_28", - "PSS1_IMUX_B30_29", - "PSS1_IMUX_B30_3", - "PSS1_IMUX_B30_30", - "PSS1_IMUX_B30_31", - "PSS1_IMUX_B30_32", - "PSS1_IMUX_B30_33", - "PSS1_IMUX_B30_34", - "PSS1_IMUX_B30_35", - "PSS1_IMUX_B30_36", - "PSS1_IMUX_B30_37", - "PSS1_IMUX_B30_38", - "PSS1_IMUX_B30_39", - "PSS1_IMUX_B30_4", - "PSS1_IMUX_B30_5", - "PSS1_IMUX_B30_6", - "PSS1_IMUX_B30_7", - "PSS1_IMUX_B30_8", - "PSS1_IMUX_B30_9", - "PSS1_IMUX_B31_0", - "PSS1_IMUX_B31_1", - "PSS1_IMUX_B31_10", - "PSS1_IMUX_B31_11", - "PSS1_IMUX_B31_12", - "PSS1_IMUX_B31_13", - "PSS1_IMUX_B31_14", - "PSS1_IMUX_B31_15", - "PSS1_IMUX_B31_16", - "PSS1_IMUX_B31_17", - "PSS1_IMUX_B31_18", - "PSS1_IMUX_B31_19", - "PSS1_IMUX_B31_2", - "PSS1_IMUX_B31_20", - "PSS1_IMUX_B31_21", - "PSS1_IMUX_B31_22", - "PSS1_IMUX_B31_23", - "PSS1_IMUX_B31_24", - "PSS1_IMUX_B31_25", - "PSS1_IMUX_B31_26", - "PSS1_IMUX_B31_27", - "PSS1_IMUX_B31_28", - "PSS1_IMUX_B31_29", - "PSS1_IMUX_B31_3", - "PSS1_IMUX_B31_30", - "PSS1_IMUX_B31_31", - "PSS1_IMUX_B31_32", - "PSS1_IMUX_B31_33", - "PSS1_IMUX_B31_34", - "PSS1_IMUX_B31_35", - "PSS1_IMUX_B31_36", - "PSS1_IMUX_B31_37", - "PSS1_IMUX_B31_38", - "PSS1_IMUX_B31_39", - "PSS1_IMUX_B31_4", - "PSS1_IMUX_B31_5", - "PSS1_IMUX_B31_6", - "PSS1_IMUX_B31_7", - "PSS1_IMUX_B31_8", - "PSS1_IMUX_B31_9", - "PSS1_IMUX_B32_0", - "PSS1_IMUX_B32_1", - "PSS1_IMUX_B32_10", - "PSS1_IMUX_B32_11", - "PSS1_IMUX_B32_12", - "PSS1_IMUX_B32_13", - "PSS1_IMUX_B32_14", - "PSS1_IMUX_B32_15", - "PSS1_IMUX_B32_16", - "PSS1_IMUX_B32_17", - "PSS1_IMUX_B32_18", - "PSS1_IMUX_B32_19", - "PSS1_IMUX_B32_2", - "PSS1_IMUX_B32_20", - "PSS1_IMUX_B32_21", - "PSS1_IMUX_B32_22", - "PSS1_IMUX_B32_23", - "PSS1_IMUX_B32_24", - "PSS1_IMUX_B32_25", - "PSS1_IMUX_B32_26", - "PSS1_IMUX_B32_27", - "PSS1_IMUX_B32_28", - "PSS1_IMUX_B32_29", - "PSS1_IMUX_B32_3", - "PSS1_IMUX_B32_30", - "PSS1_IMUX_B32_31", - "PSS1_IMUX_B32_32", - "PSS1_IMUX_B32_33", - "PSS1_IMUX_B32_34", - "PSS1_IMUX_B32_35", - "PSS1_IMUX_B32_36", - "PSS1_IMUX_B32_37", - "PSS1_IMUX_B32_38", - "PSS1_IMUX_B32_39", - "PSS1_IMUX_B32_4", - "PSS1_IMUX_B32_5", - "PSS1_IMUX_B32_6", - "PSS1_IMUX_B32_7", - "PSS1_IMUX_B32_8", - "PSS1_IMUX_B32_9", - "PSS1_IMUX_B33_0", - "PSS1_IMUX_B33_1", - "PSS1_IMUX_B33_10", - "PSS1_IMUX_B33_11", - "PSS1_IMUX_B33_12", - "PSS1_IMUX_B33_13", - "PSS1_IMUX_B33_14", - "PSS1_IMUX_B33_15", - "PSS1_IMUX_B33_16", - "PSS1_IMUX_B33_17", - "PSS1_IMUX_B33_18", - "PSS1_IMUX_B33_19", - "PSS1_IMUX_B33_2", - "PSS1_IMUX_B33_20", - "PSS1_IMUX_B33_21", - "PSS1_IMUX_B33_22", - "PSS1_IMUX_B33_23", - "PSS1_IMUX_B33_24", - "PSS1_IMUX_B33_25", - "PSS1_IMUX_B33_26", - "PSS1_IMUX_B33_27", - "PSS1_IMUX_B33_28", - "PSS1_IMUX_B33_29", - "PSS1_IMUX_B33_3", - "PSS1_IMUX_B33_30", - "PSS1_IMUX_B33_31", - "PSS1_IMUX_B33_32", - "PSS1_IMUX_B33_33", - "PSS1_IMUX_B33_34", - "PSS1_IMUX_B33_35", - "PSS1_IMUX_B33_36", - "PSS1_IMUX_B33_37", - "PSS1_IMUX_B33_38", - "PSS1_IMUX_B33_39", - "PSS1_IMUX_B33_4", - "PSS1_IMUX_B33_5", - "PSS1_IMUX_B33_6", - "PSS1_IMUX_B33_7", - "PSS1_IMUX_B33_8", - "PSS1_IMUX_B33_9", - "PSS1_IMUX_B34_0", - "PSS1_IMUX_B34_1", - "PSS1_IMUX_B34_10", - "PSS1_IMUX_B34_11", - "PSS1_IMUX_B34_12", - "PSS1_IMUX_B34_13", - "PSS1_IMUX_B34_14", - "PSS1_IMUX_B34_15", - "PSS1_IMUX_B34_16", - "PSS1_IMUX_B34_17", - "PSS1_IMUX_B34_18", - "PSS1_IMUX_B34_19", - "PSS1_IMUX_B34_2", - "PSS1_IMUX_B34_20", - "PSS1_IMUX_B34_21", - "PSS1_IMUX_B34_22", - "PSS1_IMUX_B34_23", - "PSS1_IMUX_B34_24", - "PSS1_IMUX_B34_25", - "PSS1_IMUX_B34_26", - "PSS1_IMUX_B34_27", - "PSS1_IMUX_B34_28", - "PSS1_IMUX_B34_29", - "PSS1_IMUX_B34_3", - "PSS1_IMUX_B34_30", - "PSS1_IMUX_B34_31", - "PSS1_IMUX_B34_32", - "PSS1_IMUX_B34_33", - "PSS1_IMUX_B34_34", - "PSS1_IMUX_B34_35", - "PSS1_IMUX_B34_36", - "PSS1_IMUX_B34_37", - "PSS1_IMUX_B34_38", - "PSS1_IMUX_B34_39", - "PSS1_IMUX_B34_4", - "PSS1_IMUX_B34_5", - "PSS1_IMUX_B34_6", - "PSS1_IMUX_B34_7", - "PSS1_IMUX_B34_8", - "PSS1_IMUX_B34_9", - "PSS1_IMUX_B35_0", - "PSS1_IMUX_B35_1", - "PSS1_IMUX_B35_10", - "PSS1_IMUX_B35_11", - "PSS1_IMUX_B35_12", - "PSS1_IMUX_B35_13", - "PSS1_IMUX_B35_14", - "PSS1_IMUX_B35_15", - "PSS1_IMUX_B35_16", - "PSS1_IMUX_B35_17", - "PSS1_IMUX_B35_18", - "PSS1_IMUX_B35_19", - "PSS1_IMUX_B35_2", - "PSS1_IMUX_B35_20", - "PSS1_IMUX_B35_21", - "PSS1_IMUX_B35_22", - "PSS1_IMUX_B35_23", - "PSS1_IMUX_B35_24", - "PSS1_IMUX_B35_25", - "PSS1_IMUX_B35_26", - "PSS1_IMUX_B35_27", - "PSS1_IMUX_B35_28", - "PSS1_IMUX_B35_29", - "PSS1_IMUX_B35_3", - "PSS1_IMUX_B35_30", - "PSS1_IMUX_B35_31", - "PSS1_IMUX_B35_32", - "PSS1_IMUX_B35_33", - "PSS1_IMUX_B35_34", - "PSS1_IMUX_B35_35", - "PSS1_IMUX_B35_36", - "PSS1_IMUX_B35_37", - "PSS1_IMUX_B35_38", - "PSS1_IMUX_B35_39", - "PSS1_IMUX_B35_4", - "PSS1_IMUX_B35_5", - "PSS1_IMUX_B35_6", - "PSS1_IMUX_B35_7", - "PSS1_IMUX_B35_8", - "PSS1_IMUX_B35_9", - "PSS1_IMUX_B36_0", - "PSS1_IMUX_B36_1", - "PSS1_IMUX_B36_10", - "PSS1_IMUX_B36_11", - "PSS1_IMUX_B36_12", - "PSS1_IMUX_B36_13", - "PSS1_IMUX_B36_14", - "PSS1_IMUX_B36_15", - "PSS1_IMUX_B36_16", - "PSS1_IMUX_B36_17", - "PSS1_IMUX_B36_18", - "PSS1_IMUX_B36_19", - "PSS1_IMUX_B36_2", - "PSS1_IMUX_B36_20", - "PSS1_IMUX_B36_21", - "PSS1_IMUX_B36_22", - "PSS1_IMUX_B36_23", - "PSS1_IMUX_B36_24", - "PSS1_IMUX_B36_25", - "PSS1_IMUX_B36_26", - "PSS1_IMUX_B36_27", - "PSS1_IMUX_B36_28", - "PSS1_IMUX_B36_29", - "PSS1_IMUX_B36_3", - "PSS1_IMUX_B36_30", - "PSS1_IMUX_B36_31", - "PSS1_IMUX_B36_32", - "PSS1_IMUX_B36_33", - "PSS1_IMUX_B36_34", - "PSS1_IMUX_B36_35", - "PSS1_IMUX_B36_36", - "PSS1_IMUX_B36_37", - "PSS1_IMUX_B36_38", - "PSS1_IMUX_B36_39", - "PSS1_IMUX_B36_4", - "PSS1_IMUX_B36_5", - "PSS1_IMUX_B36_6", - "PSS1_IMUX_B36_7", - "PSS1_IMUX_B36_8", - "PSS1_IMUX_B36_9", - "PSS1_IMUX_B37_0", - "PSS1_IMUX_B37_1", - "PSS1_IMUX_B37_10", - "PSS1_IMUX_B37_11", - "PSS1_IMUX_B37_12", - "PSS1_IMUX_B37_13", - "PSS1_IMUX_B37_14", - "PSS1_IMUX_B37_15", - "PSS1_IMUX_B37_16", - "PSS1_IMUX_B37_17", - "PSS1_IMUX_B37_18", - "PSS1_IMUX_B37_19", - "PSS1_IMUX_B37_2", - "PSS1_IMUX_B37_20", - "PSS1_IMUX_B37_21", - "PSS1_IMUX_B37_22", - "PSS1_IMUX_B37_23", - "PSS1_IMUX_B37_24", - "PSS1_IMUX_B37_25", - "PSS1_IMUX_B37_26", - "PSS1_IMUX_B37_27", - "PSS1_IMUX_B37_28", - "PSS1_IMUX_B37_29", - "PSS1_IMUX_B37_3", - "PSS1_IMUX_B37_30", - "PSS1_IMUX_B37_31", - "PSS1_IMUX_B37_32", - "PSS1_IMUX_B37_33", - "PSS1_IMUX_B37_34", - "PSS1_IMUX_B37_35", - "PSS1_IMUX_B37_36", - "PSS1_IMUX_B37_37", - "PSS1_IMUX_B37_38", - "PSS1_IMUX_B37_39", - "PSS1_IMUX_B37_4", - "PSS1_IMUX_B37_5", - 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"PSS1_IMUX_B44_8", - "PSS1_IMUX_B44_9", - "PSS1_IMUX_B45_0", - "PSS1_IMUX_B45_1", - "PSS1_IMUX_B45_10", - "PSS1_IMUX_B45_11", - "PSS1_IMUX_B45_12", - "PSS1_IMUX_B45_13", - "PSS1_IMUX_B45_14", - "PSS1_IMUX_B45_15", - "PSS1_IMUX_B45_16", - "PSS1_IMUX_B45_17", - "PSS1_IMUX_B45_18", - "PSS1_IMUX_B45_19", - "PSS1_IMUX_B45_2", - "PSS1_IMUX_B45_20", - "PSS1_IMUX_B45_21", - "PSS1_IMUX_B45_22", - "PSS1_IMUX_B45_23", - "PSS1_IMUX_B45_24", - "PSS1_IMUX_B45_25", - "PSS1_IMUX_B45_26", - "PSS1_IMUX_B45_27", - "PSS1_IMUX_B45_28", - "PSS1_IMUX_B45_29", - "PSS1_IMUX_B45_3", - "PSS1_IMUX_B45_30", - "PSS1_IMUX_B45_31", - "PSS1_IMUX_B45_32", - "PSS1_IMUX_B45_33", - "PSS1_IMUX_B45_34", - "PSS1_IMUX_B45_35", - "PSS1_IMUX_B45_36", - "PSS1_IMUX_B45_37", - "PSS1_IMUX_B45_38", - "PSS1_IMUX_B45_39", - "PSS1_IMUX_B45_4", - "PSS1_IMUX_B45_5", - "PSS1_IMUX_B45_6", - "PSS1_IMUX_B45_7", - "PSS1_IMUX_B45_8", - "PSS1_IMUX_B45_9", - "PSS1_IMUX_B46_0", - "PSS1_IMUX_B46_1", - "PSS1_IMUX_B46_10", - "PSS1_IMUX_B46_11", - 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"PSS1_IMUX_B5_30", - "PSS1_IMUX_B5_31", - "PSS1_IMUX_B5_32", - "PSS1_IMUX_B5_33", - "PSS1_IMUX_B5_34", - "PSS1_IMUX_B5_35", - "PSS1_IMUX_B5_36", - "PSS1_IMUX_B5_37", - "PSS1_IMUX_B5_38", - "PSS1_IMUX_B5_39", - "PSS1_IMUX_B5_4", - "PSS1_IMUX_B5_5", - "PSS1_IMUX_B5_6", - "PSS1_IMUX_B5_7", - "PSS1_IMUX_B5_8", - "PSS1_IMUX_B5_9", - "PSS1_IMUX_B6_0", - "PSS1_IMUX_B6_1", - "PSS1_IMUX_B6_10", - "PSS1_IMUX_B6_11", - "PSS1_IMUX_B6_12", - "PSS1_IMUX_B6_13", - "PSS1_IMUX_B6_14", - "PSS1_IMUX_B6_15", - "PSS1_IMUX_B6_16", - "PSS1_IMUX_B6_17", - "PSS1_IMUX_B6_18", - "PSS1_IMUX_B6_19", - "PSS1_IMUX_B6_2", - "PSS1_IMUX_B6_20", - "PSS1_IMUX_B6_21", - "PSS1_IMUX_B6_22", - "PSS1_IMUX_B6_23", - "PSS1_IMUX_B6_24", - "PSS1_IMUX_B6_25", - "PSS1_IMUX_B6_26", - "PSS1_IMUX_B6_27", - "PSS1_IMUX_B6_28", - "PSS1_IMUX_B6_29", - "PSS1_IMUX_B6_3", - "PSS1_IMUX_B6_30", - "PSS1_IMUX_B6_31", - "PSS1_IMUX_B6_32", - "PSS1_IMUX_B6_33", - "PSS1_IMUX_B6_34", - "PSS1_IMUX_B6_35", - "PSS1_IMUX_B6_36", - "PSS1_IMUX_B6_37", - "PSS1_IMUX_B6_38", - "PSS1_IMUX_B6_39", - "PSS1_IMUX_B6_4", - "PSS1_IMUX_B6_5", - "PSS1_IMUX_B6_6", - "PSS1_IMUX_B6_7", - "PSS1_IMUX_B6_8", - "PSS1_IMUX_B6_9", - "PSS1_IMUX_B7_0", - "PSS1_IMUX_B7_1", - "PSS1_IMUX_B7_10", - "PSS1_IMUX_B7_11", - "PSS1_IMUX_B7_12", - "PSS1_IMUX_B7_13", - "PSS1_IMUX_B7_14", - "PSS1_IMUX_B7_15", - "PSS1_IMUX_B7_16", - "PSS1_IMUX_B7_17", - "PSS1_IMUX_B7_18", - "PSS1_IMUX_B7_19", - "PSS1_IMUX_B7_2", - "PSS1_IMUX_B7_20", - "PSS1_IMUX_B7_21", - "PSS1_IMUX_B7_22", - "PSS1_IMUX_B7_23", - "PSS1_IMUX_B7_24", - "PSS1_IMUX_B7_25", - "PSS1_IMUX_B7_26", - "PSS1_IMUX_B7_27", - "PSS1_IMUX_B7_28", - "PSS1_IMUX_B7_29", - "PSS1_IMUX_B7_3", - "PSS1_IMUX_B7_30", - "PSS1_IMUX_B7_31", - "PSS1_IMUX_B7_32", - "PSS1_IMUX_B7_33", - "PSS1_IMUX_B7_34", - "PSS1_IMUX_B7_35", - "PSS1_IMUX_B7_36", - "PSS1_IMUX_B7_37", - "PSS1_IMUX_B7_38", - "PSS1_IMUX_B7_39", - "PSS1_IMUX_B7_4", - "PSS1_IMUX_B7_5", - "PSS1_IMUX_B7_6", - "PSS1_IMUX_B7_7", - "PSS1_IMUX_B7_8", - "PSS1_IMUX_B7_9", - "PSS1_IMUX_B8_0", - "PSS1_IMUX_B8_1", - "PSS1_IMUX_B8_10", - "PSS1_IMUX_B8_11", - "PSS1_IMUX_B8_12", - "PSS1_IMUX_B8_13", - "PSS1_IMUX_B8_14", - "PSS1_IMUX_B8_15", - "PSS1_IMUX_B8_16", - "PSS1_IMUX_B8_17", - "PSS1_IMUX_B8_18", - "PSS1_IMUX_B8_19", - "PSS1_IMUX_B8_2", - "PSS1_IMUX_B8_20", - "PSS1_IMUX_B8_21", - "PSS1_IMUX_B8_22", - "PSS1_IMUX_B8_23", - "PSS1_IMUX_B8_24", - "PSS1_IMUX_B8_25", - "PSS1_IMUX_B8_26", - "PSS1_IMUX_B8_27", - "PSS1_IMUX_B8_28", - "PSS1_IMUX_B8_29", - "PSS1_IMUX_B8_3", - "PSS1_IMUX_B8_30", - "PSS1_IMUX_B8_31", - "PSS1_IMUX_B8_32", - "PSS1_IMUX_B8_33", - "PSS1_IMUX_B8_34", - "PSS1_IMUX_B8_35", - "PSS1_IMUX_B8_36", - "PSS1_IMUX_B8_37", - "PSS1_IMUX_B8_38", - "PSS1_IMUX_B8_39", - "PSS1_IMUX_B8_4", - "PSS1_IMUX_B8_5", - "PSS1_IMUX_B8_6", - "PSS1_IMUX_B8_7", - "PSS1_IMUX_B8_8", - "PSS1_IMUX_B8_9", - "PSS1_IMUX_B9_0", - "PSS1_IMUX_B9_1", - "PSS1_IMUX_B9_10", - "PSS1_IMUX_B9_11", - "PSS1_IMUX_B9_12", - "PSS1_IMUX_B9_13", - "PSS1_IMUX_B9_14", - "PSS1_IMUX_B9_15", - "PSS1_IMUX_B9_16", - "PSS1_IMUX_B9_17", - "PSS1_IMUX_B9_18", - "PSS1_IMUX_B9_19", - "PSS1_IMUX_B9_2", - "PSS1_IMUX_B9_20", - "PSS1_IMUX_B9_21", - "PSS1_IMUX_B9_22", - "PSS1_IMUX_B9_23", - "PSS1_IMUX_B9_24", - "PSS1_IMUX_B9_25", - "PSS1_IMUX_B9_26", - "PSS1_IMUX_B9_27", - "PSS1_IMUX_B9_28", - "PSS1_IMUX_B9_29", - "PSS1_IMUX_B9_3", - "PSS1_IMUX_B9_30", - "PSS1_IMUX_B9_31", - "PSS1_IMUX_B9_32", - "PSS1_IMUX_B9_33", - "PSS1_IMUX_B9_34", - "PSS1_IMUX_B9_35", - "PSS1_IMUX_B9_36", - "PSS1_IMUX_B9_37", - "PSS1_IMUX_B9_38", - "PSS1_IMUX_B9_39", - "PSS1_IMUX_B9_4", - "PSS1_IMUX_B9_5", - "PSS1_IMUX_B9_6", - "PSS1_IMUX_B9_7", - "PSS1_IMUX_B9_8", - "PSS1_IMUX_B9_9", - "PSS1_LOGIC_OUTS0_0", - "PSS1_LOGIC_OUTS0_1", - "PSS1_LOGIC_OUTS0_10", - "PSS1_LOGIC_OUTS0_11", - "PSS1_LOGIC_OUTS0_12", - "PSS1_LOGIC_OUTS0_13", - "PSS1_LOGIC_OUTS0_14", - "PSS1_LOGIC_OUTS0_15", - "PSS1_LOGIC_OUTS0_16", - "PSS1_LOGIC_OUTS0_17", - "PSS1_LOGIC_OUTS0_18", - "PSS1_LOGIC_OUTS0_19", - "PSS1_LOGIC_OUTS0_2", - "PSS1_LOGIC_OUTS0_20", - "PSS1_LOGIC_OUTS0_21", - "PSS1_LOGIC_OUTS0_22", - "PSS1_LOGIC_OUTS0_23", - "PSS1_LOGIC_OUTS0_24", - "PSS1_LOGIC_OUTS0_25", - "PSS1_LOGIC_OUTS0_26", - "PSS1_LOGIC_OUTS0_27", - "PSS1_LOGIC_OUTS0_28", - "PSS1_LOGIC_OUTS0_29", - "PSS1_LOGIC_OUTS0_3", - "PSS1_LOGIC_OUTS0_30", - "PSS1_LOGIC_OUTS0_31", - "PSS1_LOGIC_OUTS0_32", - "PSS1_LOGIC_OUTS0_33", - "PSS1_LOGIC_OUTS0_34", - "PSS1_LOGIC_OUTS0_35", - "PSS1_LOGIC_OUTS0_36", - "PSS1_LOGIC_OUTS0_37", - "PSS1_LOGIC_OUTS0_38", - "PSS1_LOGIC_OUTS0_39", - "PSS1_LOGIC_OUTS0_4", - "PSS1_LOGIC_OUTS0_5", - "PSS1_LOGIC_OUTS0_6", - "PSS1_LOGIC_OUTS0_7", - "PSS1_LOGIC_OUTS0_8", - "PSS1_LOGIC_OUTS0_9", - "PSS1_LOGIC_OUTS10_0", - "PSS1_LOGIC_OUTS10_1", - "PSS1_LOGIC_OUTS10_10", - "PSS1_LOGIC_OUTS10_11", - "PSS1_LOGIC_OUTS10_12", - "PSS1_LOGIC_OUTS10_13", - "PSS1_LOGIC_OUTS10_14", - "PSS1_LOGIC_OUTS10_15", - "PSS1_LOGIC_OUTS10_16", - "PSS1_LOGIC_OUTS10_17", - "PSS1_LOGIC_OUTS10_18", - "PSS1_LOGIC_OUTS10_19", - "PSS1_LOGIC_OUTS10_2", - "PSS1_LOGIC_OUTS10_20", - "PSS1_LOGIC_OUTS10_21", - "PSS1_LOGIC_OUTS10_22", - "PSS1_LOGIC_OUTS10_23", - "PSS1_LOGIC_OUTS10_24", - "PSS1_LOGIC_OUTS10_25", - "PSS1_LOGIC_OUTS10_26", - "PSS1_LOGIC_OUTS10_27", - "PSS1_LOGIC_OUTS10_28", - "PSS1_LOGIC_OUTS10_29", - "PSS1_LOGIC_OUTS10_3", - "PSS1_LOGIC_OUTS10_30", - "PSS1_LOGIC_OUTS10_31", - "PSS1_LOGIC_OUTS10_32", - "PSS1_LOGIC_OUTS10_33", - "PSS1_LOGIC_OUTS10_34", - "PSS1_LOGIC_OUTS10_35", - "PSS1_LOGIC_OUTS10_36", - "PSS1_LOGIC_OUTS10_37", - "PSS1_LOGIC_OUTS10_38", - "PSS1_LOGIC_OUTS10_39", - "PSS1_LOGIC_OUTS10_4", - "PSS1_LOGIC_OUTS10_5", - "PSS1_LOGIC_OUTS10_6", - "PSS1_LOGIC_OUTS10_7", - "PSS1_LOGIC_OUTS10_8", - "PSS1_LOGIC_OUTS10_9", - "PSS1_LOGIC_OUTS11_0", - "PSS1_LOGIC_OUTS11_1", - "PSS1_LOGIC_OUTS11_10", - "PSS1_LOGIC_OUTS11_11", - "PSS1_LOGIC_OUTS11_12", - "PSS1_LOGIC_OUTS11_13", - "PSS1_LOGIC_OUTS11_14", - "PSS1_LOGIC_OUTS11_15", - "PSS1_LOGIC_OUTS11_16", - "PSS1_LOGIC_OUTS11_17", - "PSS1_LOGIC_OUTS11_18", - "PSS1_LOGIC_OUTS11_19", - "PSS1_LOGIC_OUTS11_2", - "PSS1_LOGIC_OUTS11_20", - "PSS1_LOGIC_OUTS11_21", - "PSS1_LOGIC_OUTS11_22", - "PSS1_LOGIC_OUTS11_23", - "PSS1_LOGIC_OUTS11_24", - "PSS1_LOGIC_OUTS11_25", - "PSS1_LOGIC_OUTS11_26", - "PSS1_LOGIC_OUTS11_27", - "PSS1_LOGIC_OUTS11_28", - "PSS1_LOGIC_OUTS11_29", - "PSS1_LOGIC_OUTS11_3", - "PSS1_LOGIC_OUTS11_30", - "PSS1_LOGIC_OUTS11_31", - "PSS1_LOGIC_OUTS11_32", - "PSS1_LOGIC_OUTS11_33", - "PSS1_LOGIC_OUTS11_34", - "PSS1_LOGIC_OUTS11_35", - "PSS1_LOGIC_OUTS11_36", - "PSS1_LOGIC_OUTS11_37", - "PSS1_LOGIC_OUTS11_38", - "PSS1_LOGIC_OUTS11_39", - "PSS1_LOGIC_OUTS11_4", - "PSS1_LOGIC_OUTS11_5", - "PSS1_LOGIC_OUTS11_6", - "PSS1_LOGIC_OUTS11_7", - "PSS1_LOGIC_OUTS11_8", - "PSS1_LOGIC_OUTS11_9", - "PSS1_LOGIC_OUTS12_0", - "PSS1_LOGIC_OUTS12_1", - "PSS1_LOGIC_OUTS12_10", - "PSS1_LOGIC_OUTS12_11", - "PSS1_LOGIC_OUTS12_12", - "PSS1_LOGIC_OUTS12_13", - "PSS1_LOGIC_OUTS12_14", - "PSS1_LOGIC_OUTS12_15", - "PSS1_LOGIC_OUTS12_16", - "PSS1_LOGIC_OUTS12_17", - "PSS1_LOGIC_OUTS12_18", - "PSS1_LOGIC_OUTS12_19", - "PSS1_LOGIC_OUTS12_2", - "PSS1_LOGIC_OUTS12_20", - "PSS1_LOGIC_OUTS12_21", - "PSS1_LOGIC_OUTS12_22", - "PSS1_LOGIC_OUTS12_23", - "PSS1_LOGIC_OUTS12_24", - "PSS1_LOGIC_OUTS12_25", - "PSS1_LOGIC_OUTS12_26", - "PSS1_LOGIC_OUTS12_27", - "PSS1_LOGIC_OUTS12_28", - "PSS1_LOGIC_OUTS12_29", - "PSS1_LOGIC_OUTS12_3", - "PSS1_LOGIC_OUTS12_30", - "PSS1_LOGIC_OUTS12_31", - "PSS1_LOGIC_OUTS12_32", - "PSS1_LOGIC_OUTS12_33", - "PSS1_LOGIC_OUTS12_34", - "PSS1_LOGIC_OUTS12_35", - "PSS1_LOGIC_OUTS12_36", - "PSS1_LOGIC_OUTS12_37", - "PSS1_LOGIC_OUTS12_38", - "PSS1_LOGIC_OUTS12_39", - "PSS1_LOGIC_OUTS12_4", - "PSS1_LOGIC_OUTS12_5", - "PSS1_LOGIC_OUTS12_6", - "PSS1_LOGIC_OUTS12_7", - "PSS1_LOGIC_OUTS12_8", - "PSS1_LOGIC_OUTS12_9", - "PSS1_LOGIC_OUTS13_0", - "PSS1_LOGIC_OUTS13_1", - "PSS1_LOGIC_OUTS13_10", - "PSS1_LOGIC_OUTS13_11", - "PSS1_LOGIC_OUTS13_12", - "PSS1_LOGIC_OUTS13_13", - "PSS1_LOGIC_OUTS13_14", - "PSS1_LOGIC_OUTS13_15", - "PSS1_LOGIC_OUTS13_16", - "PSS1_LOGIC_OUTS13_17", - "PSS1_LOGIC_OUTS13_18", - "PSS1_LOGIC_OUTS13_19", - "PSS1_LOGIC_OUTS13_2", - "PSS1_LOGIC_OUTS13_20", - "PSS1_LOGIC_OUTS13_21", - "PSS1_LOGIC_OUTS13_22", - "PSS1_LOGIC_OUTS13_23", - "PSS1_LOGIC_OUTS13_24", - "PSS1_LOGIC_OUTS13_25", - "PSS1_LOGIC_OUTS13_26", - "PSS1_LOGIC_OUTS13_27", - "PSS1_LOGIC_OUTS13_28", - "PSS1_LOGIC_OUTS13_29", - "PSS1_LOGIC_OUTS13_3", - "PSS1_LOGIC_OUTS13_30", - "PSS1_LOGIC_OUTS13_31", - "PSS1_LOGIC_OUTS13_32", - "PSS1_LOGIC_OUTS13_33", - "PSS1_LOGIC_OUTS13_34", - "PSS1_LOGIC_OUTS13_35", - "PSS1_LOGIC_OUTS13_36", - "PSS1_LOGIC_OUTS13_37", - "PSS1_LOGIC_OUTS13_38", - "PSS1_LOGIC_OUTS13_39", - "PSS1_LOGIC_OUTS13_4", - "PSS1_LOGIC_OUTS13_5", - "PSS1_LOGIC_OUTS13_6", - "PSS1_LOGIC_OUTS13_7", - "PSS1_LOGIC_OUTS13_8", - "PSS1_LOGIC_OUTS13_9", - "PSS1_LOGIC_OUTS14_0", - "PSS1_LOGIC_OUTS14_1", - "PSS1_LOGIC_OUTS14_10", - "PSS1_LOGIC_OUTS14_11", - "PSS1_LOGIC_OUTS14_12", - "PSS1_LOGIC_OUTS14_13", - "PSS1_LOGIC_OUTS14_14", - "PSS1_LOGIC_OUTS14_15", - "PSS1_LOGIC_OUTS14_16", - "PSS1_LOGIC_OUTS14_17", - "PSS1_LOGIC_OUTS14_18", - "PSS1_LOGIC_OUTS14_19", - "PSS1_LOGIC_OUTS14_2", - "PSS1_LOGIC_OUTS14_20", - "PSS1_LOGIC_OUTS14_21", - "PSS1_LOGIC_OUTS14_22", - "PSS1_LOGIC_OUTS14_23", - "PSS1_LOGIC_OUTS14_24", - "PSS1_LOGIC_OUTS14_25", - "PSS1_LOGIC_OUTS14_26", - "PSS1_LOGIC_OUTS14_27", - "PSS1_LOGIC_OUTS14_28", - "PSS1_LOGIC_OUTS14_29", - "PSS1_LOGIC_OUTS14_3", - "PSS1_LOGIC_OUTS14_30", - "PSS1_LOGIC_OUTS14_31", - "PSS1_LOGIC_OUTS14_32", - "PSS1_LOGIC_OUTS14_33", - "PSS1_LOGIC_OUTS14_34", - "PSS1_LOGIC_OUTS14_35", - "PSS1_LOGIC_OUTS14_36", - "PSS1_LOGIC_OUTS14_37", - "PSS1_LOGIC_OUTS14_38", - "PSS1_LOGIC_OUTS14_39", - "PSS1_LOGIC_OUTS14_4", - "PSS1_LOGIC_OUTS14_5", - "PSS1_LOGIC_OUTS14_6", - "PSS1_LOGIC_OUTS14_7", - "PSS1_LOGIC_OUTS14_8", - "PSS1_LOGIC_OUTS14_9", - "PSS1_LOGIC_OUTS15_0", - "PSS1_LOGIC_OUTS15_1", - "PSS1_LOGIC_OUTS15_10", - "PSS1_LOGIC_OUTS15_11", - "PSS1_LOGIC_OUTS15_12", - "PSS1_LOGIC_OUTS15_13", - "PSS1_LOGIC_OUTS15_14", - "PSS1_LOGIC_OUTS15_15", - "PSS1_LOGIC_OUTS15_16", - "PSS1_LOGIC_OUTS15_17", - "PSS1_LOGIC_OUTS15_18", - "PSS1_LOGIC_OUTS15_19", - "PSS1_LOGIC_OUTS15_2", - "PSS1_LOGIC_OUTS15_20", - "PSS1_LOGIC_OUTS15_21", - "PSS1_LOGIC_OUTS15_22", - "PSS1_LOGIC_OUTS15_23", - "PSS1_LOGIC_OUTS15_24", - "PSS1_LOGIC_OUTS15_25", - "PSS1_LOGIC_OUTS15_26", - "PSS1_LOGIC_OUTS15_27", - "PSS1_LOGIC_OUTS15_28", - "PSS1_LOGIC_OUTS15_29", - "PSS1_LOGIC_OUTS15_3", - "PSS1_LOGIC_OUTS15_30", - "PSS1_LOGIC_OUTS15_31", - "PSS1_LOGIC_OUTS15_32", - "PSS1_LOGIC_OUTS15_33", - "PSS1_LOGIC_OUTS15_34", - "PSS1_LOGIC_OUTS15_35", - "PSS1_LOGIC_OUTS15_36", - "PSS1_LOGIC_OUTS15_37", - "PSS1_LOGIC_OUTS15_38", - "PSS1_LOGIC_OUTS15_39", - "PSS1_LOGIC_OUTS15_4", - "PSS1_LOGIC_OUTS15_5", - "PSS1_LOGIC_OUTS15_6", - "PSS1_LOGIC_OUTS15_7", - "PSS1_LOGIC_OUTS15_8", - "PSS1_LOGIC_OUTS15_9", - "PSS1_LOGIC_OUTS16_0", - "PSS1_LOGIC_OUTS16_1", - "PSS1_LOGIC_OUTS16_10", - "PSS1_LOGIC_OUTS16_11", - "PSS1_LOGIC_OUTS16_12", - "PSS1_LOGIC_OUTS16_13", - "PSS1_LOGIC_OUTS16_14", - "PSS1_LOGIC_OUTS16_15", - "PSS1_LOGIC_OUTS16_16", - "PSS1_LOGIC_OUTS16_17", - "PSS1_LOGIC_OUTS16_18", - "PSS1_LOGIC_OUTS16_19", - "PSS1_LOGIC_OUTS16_2", - "PSS1_LOGIC_OUTS16_20", - "PSS1_LOGIC_OUTS16_21", - "PSS1_LOGIC_OUTS16_22", - "PSS1_LOGIC_OUTS16_23", - "PSS1_LOGIC_OUTS16_24", - "PSS1_LOGIC_OUTS16_25", - "PSS1_LOGIC_OUTS16_26", - "PSS1_LOGIC_OUTS16_27", - "PSS1_LOGIC_OUTS16_28", - "PSS1_LOGIC_OUTS16_29", - "PSS1_LOGIC_OUTS16_3", - "PSS1_LOGIC_OUTS16_30", - "PSS1_LOGIC_OUTS16_31", - "PSS1_LOGIC_OUTS16_32", - "PSS1_LOGIC_OUTS16_33", - "PSS1_LOGIC_OUTS16_34", - "PSS1_LOGIC_OUTS16_35", - "PSS1_LOGIC_OUTS16_36", - "PSS1_LOGIC_OUTS16_37", - "PSS1_LOGIC_OUTS16_38", - "PSS1_LOGIC_OUTS16_39", - "PSS1_LOGIC_OUTS16_4", - "PSS1_LOGIC_OUTS16_5", - "PSS1_LOGIC_OUTS16_6", - "PSS1_LOGIC_OUTS16_7", - "PSS1_LOGIC_OUTS16_8", - "PSS1_LOGIC_OUTS16_9", - "PSS1_LOGIC_OUTS17_0", - "PSS1_LOGIC_OUTS17_1", - "PSS1_LOGIC_OUTS17_10", - "PSS1_LOGIC_OUTS17_11", - "PSS1_LOGIC_OUTS17_12", - "PSS1_LOGIC_OUTS17_13", - "PSS1_LOGIC_OUTS17_14", - "PSS1_LOGIC_OUTS17_15", - "PSS1_LOGIC_OUTS17_16", - "PSS1_LOGIC_OUTS17_17", - "PSS1_LOGIC_OUTS17_18", - "PSS1_LOGIC_OUTS17_19", - "PSS1_LOGIC_OUTS17_2", - "PSS1_LOGIC_OUTS17_20", - "PSS1_LOGIC_OUTS17_21", - "PSS1_LOGIC_OUTS17_22", - "PSS1_LOGIC_OUTS17_23", - "PSS1_LOGIC_OUTS17_24", - "PSS1_LOGIC_OUTS17_25", - "PSS1_LOGIC_OUTS17_26", - "PSS1_LOGIC_OUTS17_27", - "PSS1_LOGIC_OUTS17_28", - "PSS1_LOGIC_OUTS17_29", - "PSS1_LOGIC_OUTS17_3", - "PSS1_LOGIC_OUTS17_30", - "PSS1_LOGIC_OUTS17_31", - "PSS1_LOGIC_OUTS17_32", - "PSS1_LOGIC_OUTS17_33", - "PSS1_LOGIC_OUTS17_34", - "PSS1_LOGIC_OUTS17_35", - "PSS1_LOGIC_OUTS17_36", - "PSS1_LOGIC_OUTS17_37", - "PSS1_LOGIC_OUTS17_38", - "PSS1_LOGIC_OUTS17_39", - "PSS1_LOGIC_OUTS17_4", - "PSS1_LOGIC_OUTS17_5", - "PSS1_LOGIC_OUTS17_6", - "PSS1_LOGIC_OUTS17_7", - "PSS1_LOGIC_OUTS17_8", - "PSS1_LOGIC_OUTS17_9", - "PSS1_LOGIC_OUTS18_0", - "PSS1_LOGIC_OUTS18_1", - "PSS1_LOGIC_OUTS18_10", - "PSS1_LOGIC_OUTS18_11", - "PSS1_LOGIC_OUTS18_12", - "PSS1_LOGIC_OUTS18_13", - "PSS1_LOGIC_OUTS18_14", - "PSS1_LOGIC_OUTS18_15", - "PSS1_LOGIC_OUTS18_16", - "PSS1_LOGIC_OUTS18_17", - "PSS1_LOGIC_OUTS18_18", - "PSS1_LOGIC_OUTS18_19", - "PSS1_LOGIC_OUTS18_2", - "PSS1_LOGIC_OUTS18_20", - "PSS1_LOGIC_OUTS18_21", - "PSS1_LOGIC_OUTS18_22", - "PSS1_LOGIC_OUTS18_23", - "PSS1_LOGIC_OUTS18_24", - "PSS1_LOGIC_OUTS18_25", - "PSS1_LOGIC_OUTS18_26", - "PSS1_LOGIC_OUTS18_27", - "PSS1_LOGIC_OUTS18_28", - "PSS1_LOGIC_OUTS18_29", - "PSS1_LOGIC_OUTS18_3", - "PSS1_LOGIC_OUTS18_30", - "PSS1_LOGIC_OUTS18_31", - "PSS1_LOGIC_OUTS18_32", - "PSS1_LOGIC_OUTS18_33", - "PSS1_LOGIC_OUTS18_34", - "PSS1_LOGIC_OUTS18_35", - "PSS1_LOGIC_OUTS18_36", - "PSS1_LOGIC_OUTS18_37", - "PSS1_LOGIC_OUTS18_38", - "PSS1_LOGIC_OUTS18_39", - "PSS1_LOGIC_OUTS18_4", - "PSS1_LOGIC_OUTS18_5", - "PSS1_LOGIC_OUTS18_6", - "PSS1_LOGIC_OUTS18_7", - "PSS1_LOGIC_OUTS18_8", - "PSS1_LOGIC_OUTS18_9", - "PSS1_LOGIC_OUTS19_0", - "PSS1_LOGIC_OUTS19_1", - "PSS1_LOGIC_OUTS19_10", - "PSS1_LOGIC_OUTS19_11", - "PSS1_LOGIC_OUTS19_12", - "PSS1_LOGIC_OUTS19_13", - "PSS1_LOGIC_OUTS19_14", - "PSS1_LOGIC_OUTS19_15", - "PSS1_LOGIC_OUTS19_16", - "PSS1_LOGIC_OUTS19_17", - "PSS1_LOGIC_OUTS19_18", - "PSS1_LOGIC_OUTS19_19", - "PSS1_LOGIC_OUTS19_2", - "PSS1_LOGIC_OUTS19_20", - "PSS1_LOGIC_OUTS19_21", - "PSS1_LOGIC_OUTS19_22", - "PSS1_LOGIC_OUTS19_23", - "PSS1_LOGIC_OUTS19_24", - "PSS1_LOGIC_OUTS19_25", - "PSS1_LOGIC_OUTS19_26", - "PSS1_LOGIC_OUTS19_27", - "PSS1_LOGIC_OUTS19_28", - "PSS1_LOGIC_OUTS19_29", - "PSS1_LOGIC_OUTS19_3", - "PSS1_LOGIC_OUTS19_30", - "PSS1_LOGIC_OUTS19_31", - "PSS1_LOGIC_OUTS19_32", - "PSS1_LOGIC_OUTS19_33", - "PSS1_LOGIC_OUTS19_34", - "PSS1_LOGIC_OUTS19_35", - "PSS1_LOGIC_OUTS19_36", - "PSS1_LOGIC_OUTS19_37", - "PSS1_LOGIC_OUTS19_38", - "PSS1_LOGIC_OUTS19_39", - "PSS1_LOGIC_OUTS19_4", - "PSS1_LOGIC_OUTS19_5", - "PSS1_LOGIC_OUTS19_6", - "PSS1_LOGIC_OUTS19_7", - "PSS1_LOGIC_OUTS19_8", - "PSS1_LOGIC_OUTS19_9", - "PSS1_LOGIC_OUTS1_0", - "PSS1_LOGIC_OUTS1_1", - "PSS1_LOGIC_OUTS1_10", - "PSS1_LOGIC_OUTS1_11", - "PSS1_LOGIC_OUTS1_12", - "PSS1_LOGIC_OUTS1_13", - "PSS1_LOGIC_OUTS1_14", - "PSS1_LOGIC_OUTS1_15", - "PSS1_LOGIC_OUTS1_16", - "PSS1_LOGIC_OUTS1_17", - "PSS1_LOGIC_OUTS1_18", - "PSS1_LOGIC_OUTS1_19", - "PSS1_LOGIC_OUTS1_2", - "PSS1_LOGIC_OUTS1_20", - "PSS1_LOGIC_OUTS1_21", - "PSS1_LOGIC_OUTS1_22", - "PSS1_LOGIC_OUTS1_23", - "PSS1_LOGIC_OUTS1_24", - "PSS1_LOGIC_OUTS1_25", - "PSS1_LOGIC_OUTS1_26", - "PSS1_LOGIC_OUTS1_27", - "PSS1_LOGIC_OUTS1_28", - "PSS1_LOGIC_OUTS1_29", - "PSS1_LOGIC_OUTS1_3", - "PSS1_LOGIC_OUTS1_30", - "PSS1_LOGIC_OUTS1_31", - "PSS1_LOGIC_OUTS1_32", - "PSS1_LOGIC_OUTS1_33", - "PSS1_LOGIC_OUTS1_34", - "PSS1_LOGIC_OUTS1_35", - "PSS1_LOGIC_OUTS1_36", - "PSS1_LOGIC_OUTS1_37", - "PSS1_LOGIC_OUTS1_38", - "PSS1_LOGIC_OUTS1_39", - "PSS1_LOGIC_OUTS1_4", - "PSS1_LOGIC_OUTS1_5", - "PSS1_LOGIC_OUTS1_6", - "PSS1_LOGIC_OUTS1_7", - "PSS1_LOGIC_OUTS1_8", - "PSS1_LOGIC_OUTS1_9", - "PSS1_LOGIC_OUTS20_0", - "PSS1_LOGIC_OUTS20_1", - "PSS1_LOGIC_OUTS20_10", - "PSS1_LOGIC_OUTS20_11", - "PSS1_LOGIC_OUTS20_12", - "PSS1_LOGIC_OUTS20_13", - "PSS1_LOGIC_OUTS20_14", - "PSS1_LOGIC_OUTS20_15", - "PSS1_LOGIC_OUTS20_16", - "PSS1_LOGIC_OUTS20_17", - "PSS1_LOGIC_OUTS20_18", - "PSS1_LOGIC_OUTS20_19", - "PSS1_LOGIC_OUTS20_2", - "PSS1_LOGIC_OUTS20_20", - "PSS1_LOGIC_OUTS20_21", - "PSS1_LOGIC_OUTS20_22", - "PSS1_LOGIC_OUTS20_23", - "PSS1_LOGIC_OUTS20_24", - "PSS1_LOGIC_OUTS20_25", - "PSS1_LOGIC_OUTS20_26", - "PSS1_LOGIC_OUTS20_27", - "PSS1_LOGIC_OUTS20_28", - "PSS1_LOGIC_OUTS20_29", - "PSS1_LOGIC_OUTS20_3", - "PSS1_LOGIC_OUTS20_30", - "PSS1_LOGIC_OUTS20_31", - "PSS1_LOGIC_OUTS20_32", - "PSS1_LOGIC_OUTS20_33", - "PSS1_LOGIC_OUTS20_34", - "PSS1_LOGIC_OUTS20_35", - "PSS1_LOGIC_OUTS20_36", - "PSS1_LOGIC_OUTS20_37", - "PSS1_LOGIC_OUTS20_38", - "PSS1_LOGIC_OUTS20_39", - "PSS1_LOGIC_OUTS20_4", - "PSS1_LOGIC_OUTS20_5", - "PSS1_LOGIC_OUTS20_6", - "PSS1_LOGIC_OUTS20_7", - "PSS1_LOGIC_OUTS20_8", - "PSS1_LOGIC_OUTS20_9", - "PSS1_LOGIC_OUTS21_0", - "PSS1_LOGIC_OUTS21_1", - "PSS1_LOGIC_OUTS21_10", - "PSS1_LOGIC_OUTS21_11", - "PSS1_LOGIC_OUTS21_12", - "PSS1_LOGIC_OUTS21_13", - "PSS1_LOGIC_OUTS21_14", - "PSS1_LOGIC_OUTS21_15", - "PSS1_LOGIC_OUTS21_16", - "PSS1_LOGIC_OUTS21_17", - "PSS1_LOGIC_OUTS21_18", - "PSS1_LOGIC_OUTS21_19", - "PSS1_LOGIC_OUTS21_2", - "PSS1_LOGIC_OUTS21_20", - "PSS1_LOGIC_OUTS21_21", - "PSS1_LOGIC_OUTS21_22", - "PSS1_LOGIC_OUTS21_23", - "PSS1_LOGIC_OUTS21_24", - "PSS1_LOGIC_OUTS21_25", - "PSS1_LOGIC_OUTS21_26", - "PSS1_LOGIC_OUTS21_27", - "PSS1_LOGIC_OUTS21_28", - "PSS1_LOGIC_OUTS21_29", - "PSS1_LOGIC_OUTS21_3", - "PSS1_LOGIC_OUTS21_30", - "PSS1_LOGIC_OUTS21_31", - "PSS1_LOGIC_OUTS21_32", - "PSS1_LOGIC_OUTS21_33", - "PSS1_LOGIC_OUTS21_34", - "PSS1_LOGIC_OUTS21_35", - "PSS1_LOGIC_OUTS21_36", - "PSS1_LOGIC_OUTS21_37", - "PSS1_LOGIC_OUTS21_38", - "PSS1_LOGIC_OUTS21_39", - "PSS1_LOGIC_OUTS21_4", - "PSS1_LOGIC_OUTS21_5", - "PSS1_LOGIC_OUTS21_6", - "PSS1_LOGIC_OUTS21_7", - "PSS1_LOGIC_OUTS21_8", - "PSS1_LOGIC_OUTS21_9", - "PSS1_LOGIC_OUTS22_0", - "PSS1_LOGIC_OUTS22_1", - "PSS1_LOGIC_OUTS22_10", - "PSS1_LOGIC_OUTS22_11", - "PSS1_LOGIC_OUTS22_12", - "PSS1_LOGIC_OUTS22_13", - "PSS1_LOGIC_OUTS22_14", - "PSS1_LOGIC_OUTS22_15", - "PSS1_LOGIC_OUTS22_16", - "PSS1_LOGIC_OUTS22_17", - "PSS1_LOGIC_OUTS22_18", - "PSS1_LOGIC_OUTS22_19", - "PSS1_LOGIC_OUTS22_2", - "PSS1_LOGIC_OUTS22_20", - "PSS1_LOGIC_OUTS22_21", - "PSS1_LOGIC_OUTS22_22", - "PSS1_LOGIC_OUTS22_23", - "PSS1_LOGIC_OUTS22_24", - "PSS1_LOGIC_OUTS22_25", - "PSS1_LOGIC_OUTS22_26", - "PSS1_LOGIC_OUTS22_27", - "PSS1_LOGIC_OUTS22_28", - "PSS1_LOGIC_OUTS22_29", - "PSS1_LOGIC_OUTS22_3", - "PSS1_LOGIC_OUTS22_30", - "PSS1_LOGIC_OUTS22_31", - "PSS1_LOGIC_OUTS22_32", - "PSS1_LOGIC_OUTS22_33", - "PSS1_LOGIC_OUTS22_34", - "PSS1_LOGIC_OUTS22_35", - "PSS1_LOGIC_OUTS22_36", - "PSS1_LOGIC_OUTS22_37", - "PSS1_LOGIC_OUTS22_38", - "PSS1_LOGIC_OUTS22_39", - "PSS1_LOGIC_OUTS22_4", - "PSS1_LOGIC_OUTS22_5", - "PSS1_LOGIC_OUTS22_6", - "PSS1_LOGIC_OUTS22_7", - "PSS1_LOGIC_OUTS22_8", - "PSS1_LOGIC_OUTS22_9", - "PSS1_LOGIC_OUTS23_0", - "PSS1_LOGIC_OUTS23_1", - "PSS1_LOGIC_OUTS23_10", - "PSS1_LOGIC_OUTS23_11", - "PSS1_LOGIC_OUTS23_12", - "PSS1_LOGIC_OUTS23_13", - "PSS1_LOGIC_OUTS23_14", - "PSS1_LOGIC_OUTS23_15", - "PSS1_LOGIC_OUTS23_16", - "PSS1_LOGIC_OUTS23_17", - "PSS1_LOGIC_OUTS23_18", - "PSS1_LOGIC_OUTS23_19", - "PSS1_LOGIC_OUTS23_2", - "PSS1_LOGIC_OUTS23_20", - "PSS1_LOGIC_OUTS23_21", - "PSS1_LOGIC_OUTS23_22", - "PSS1_LOGIC_OUTS23_23", - "PSS1_LOGIC_OUTS23_24", - "PSS1_LOGIC_OUTS23_25", - "PSS1_LOGIC_OUTS23_26", - "PSS1_LOGIC_OUTS23_27", - "PSS1_LOGIC_OUTS23_28", - "PSS1_LOGIC_OUTS23_29", - "PSS1_LOGIC_OUTS23_3", - "PSS1_LOGIC_OUTS23_30", - "PSS1_LOGIC_OUTS23_31", - "PSS1_LOGIC_OUTS23_32", - "PSS1_LOGIC_OUTS23_33", - "PSS1_LOGIC_OUTS23_34", - "PSS1_LOGIC_OUTS23_35", - "PSS1_LOGIC_OUTS23_36", - "PSS1_LOGIC_OUTS23_37", - "PSS1_LOGIC_OUTS23_38", - "PSS1_LOGIC_OUTS23_39", - "PSS1_LOGIC_OUTS23_4", - "PSS1_LOGIC_OUTS23_5", - "PSS1_LOGIC_OUTS23_6", - "PSS1_LOGIC_OUTS23_7", - "PSS1_LOGIC_OUTS23_8", - "PSS1_LOGIC_OUTS23_9", - "PSS1_LOGIC_OUTS2_0", - "PSS1_LOGIC_OUTS2_1", - "PSS1_LOGIC_OUTS2_10", - "PSS1_LOGIC_OUTS2_11", - "PSS1_LOGIC_OUTS2_12", - "PSS1_LOGIC_OUTS2_13", - "PSS1_LOGIC_OUTS2_14", - "PSS1_LOGIC_OUTS2_15", - "PSS1_LOGIC_OUTS2_16", - "PSS1_LOGIC_OUTS2_17", - "PSS1_LOGIC_OUTS2_18", - "PSS1_LOGIC_OUTS2_19", - "PSS1_LOGIC_OUTS2_2", - "PSS1_LOGIC_OUTS2_20", - "PSS1_LOGIC_OUTS2_21", - "PSS1_LOGIC_OUTS2_22", - "PSS1_LOGIC_OUTS2_23", - "PSS1_LOGIC_OUTS2_24", - "PSS1_LOGIC_OUTS2_25", - "PSS1_LOGIC_OUTS2_26", - "PSS1_LOGIC_OUTS2_27", - "PSS1_LOGIC_OUTS2_28", - "PSS1_LOGIC_OUTS2_29", - "PSS1_LOGIC_OUTS2_3", - "PSS1_LOGIC_OUTS2_30", - "PSS1_LOGIC_OUTS2_31", - "PSS1_LOGIC_OUTS2_32", - "PSS1_LOGIC_OUTS2_33", - "PSS1_LOGIC_OUTS2_34", - "PSS1_LOGIC_OUTS2_35", - "PSS1_LOGIC_OUTS2_36", - "PSS1_LOGIC_OUTS2_37", - "PSS1_LOGIC_OUTS2_38", - "PSS1_LOGIC_OUTS2_39", - "PSS1_LOGIC_OUTS2_4", - "PSS1_LOGIC_OUTS2_5", - "PSS1_LOGIC_OUTS2_6", - "PSS1_LOGIC_OUTS2_7", - "PSS1_LOGIC_OUTS2_8", - "PSS1_LOGIC_OUTS2_9", - "PSS1_LOGIC_OUTS3_0", - "PSS1_LOGIC_OUTS3_1", - "PSS1_LOGIC_OUTS3_10", - "PSS1_LOGIC_OUTS3_11", - "PSS1_LOGIC_OUTS3_12", - "PSS1_LOGIC_OUTS3_13", - "PSS1_LOGIC_OUTS3_14", - "PSS1_LOGIC_OUTS3_15", - "PSS1_LOGIC_OUTS3_16", - "PSS1_LOGIC_OUTS3_17", - "PSS1_LOGIC_OUTS3_18", - "PSS1_LOGIC_OUTS3_19", - "PSS1_LOGIC_OUTS3_2", - "PSS1_LOGIC_OUTS3_20", - "PSS1_LOGIC_OUTS3_21", - "PSS1_LOGIC_OUTS3_22", - "PSS1_LOGIC_OUTS3_23", - "PSS1_LOGIC_OUTS3_24", - "PSS1_LOGIC_OUTS3_25", - "PSS1_LOGIC_OUTS3_26", - "PSS1_LOGIC_OUTS3_27", - "PSS1_LOGIC_OUTS3_28", - "PSS1_LOGIC_OUTS3_29", - "PSS1_LOGIC_OUTS3_3", - "PSS1_LOGIC_OUTS3_30", - "PSS1_LOGIC_OUTS3_31", - "PSS1_LOGIC_OUTS3_32", - "PSS1_LOGIC_OUTS3_33", - "PSS1_LOGIC_OUTS3_34", - "PSS1_LOGIC_OUTS3_35", - "PSS1_LOGIC_OUTS3_36", - "PSS1_LOGIC_OUTS3_37", - "PSS1_LOGIC_OUTS3_38", - "PSS1_LOGIC_OUTS3_39", - "PSS1_LOGIC_OUTS3_4", - "PSS1_LOGIC_OUTS3_5", - "PSS1_LOGIC_OUTS3_6", - "PSS1_LOGIC_OUTS3_7", - "PSS1_LOGIC_OUTS3_8", - "PSS1_LOGIC_OUTS3_9", - "PSS1_LOGIC_OUTS4_0", - "PSS1_LOGIC_OUTS4_1", - "PSS1_LOGIC_OUTS4_10", - "PSS1_LOGIC_OUTS4_11", - "PSS1_LOGIC_OUTS4_12", - "PSS1_LOGIC_OUTS4_13", - "PSS1_LOGIC_OUTS4_14", - "PSS1_LOGIC_OUTS4_15", - "PSS1_LOGIC_OUTS4_16", - "PSS1_LOGIC_OUTS4_17", - "PSS1_LOGIC_OUTS4_18", - "PSS1_LOGIC_OUTS4_19", - "PSS1_LOGIC_OUTS4_2", - "PSS1_LOGIC_OUTS4_20", - "PSS1_LOGIC_OUTS4_21", - "PSS1_LOGIC_OUTS4_22", - "PSS1_LOGIC_OUTS4_23", - "PSS1_LOGIC_OUTS4_24", - "PSS1_LOGIC_OUTS4_25", - "PSS1_LOGIC_OUTS4_26", - "PSS1_LOGIC_OUTS4_27", - "PSS1_LOGIC_OUTS4_28", - "PSS1_LOGIC_OUTS4_29", - "PSS1_LOGIC_OUTS4_3", - "PSS1_LOGIC_OUTS4_30", - "PSS1_LOGIC_OUTS4_31", - "PSS1_LOGIC_OUTS4_32", - "PSS1_LOGIC_OUTS4_33", - "PSS1_LOGIC_OUTS4_34", - "PSS1_LOGIC_OUTS4_35", - "PSS1_LOGIC_OUTS4_36", - "PSS1_LOGIC_OUTS4_37", - "PSS1_LOGIC_OUTS4_38", - "PSS1_LOGIC_OUTS4_39", - "PSS1_LOGIC_OUTS4_4", - "PSS1_LOGIC_OUTS4_5", - "PSS1_LOGIC_OUTS4_6", - "PSS1_LOGIC_OUTS4_7", - "PSS1_LOGIC_OUTS4_8", - "PSS1_LOGIC_OUTS4_9", - "PSS1_LOGIC_OUTS5_0", - "PSS1_LOGIC_OUTS5_1", - "PSS1_LOGIC_OUTS5_10", - "PSS1_LOGIC_OUTS5_11", - "PSS1_LOGIC_OUTS5_12", - "PSS1_LOGIC_OUTS5_13", - "PSS1_LOGIC_OUTS5_14", - "PSS1_LOGIC_OUTS5_15", - "PSS1_LOGIC_OUTS5_16", - "PSS1_LOGIC_OUTS5_17", - "PSS1_LOGIC_OUTS5_18", - "PSS1_LOGIC_OUTS5_19", - "PSS1_LOGIC_OUTS5_2", - "PSS1_LOGIC_OUTS5_20", - "PSS1_LOGIC_OUTS5_21", - "PSS1_LOGIC_OUTS5_22", - "PSS1_LOGIC_OUTS5_23", - "PSS1_LOGIC_OUTS5_24", - "PSS1_LOGIC_OUTS5_25", - "PSS1_LOGIC_OUTS5_26", - "PSS1_LOGIC_OUTS5_27", - "PSS1_LOGIC_OUTS5_28", - "PSS1_LOGIC_OUTS5_29", - "PSS1_LOGIC_OUTS5_3", - "PSS1_LOGIC_OUTS5_30", - "PSS1_LOGIC_OUTS5_31", - "PSS1_LOGIC_OUTS5_32", - "PSS1_LOGIC_OUTS5_33", - "PSS1_LOGIC_OUTS5_34", - "PSS1_LOGIC_OUTS5_35", - "PSS1_LOGIC_OUTS5_36", - "PSS1_LOGIC_OUTS5_37", - "PSS1_LOGIC_OUTS5_38", - "PSS1_LOGIC_OUTS5_39", - "PSS1_LOGIC_OUTS5_4", - "PSS1_LOGIC_OUTS5_5", - "PSS1_LOGIC_OUTS5_6", - "PSS1_LOGIC_OUTS5_7", - "PSS1_LOGIC_OUTS5_8", - "PSS1_LOGIC_OUTS5_9", - "PSS1_LOGIC_OUTS6_0", - "PSS1_LOGIC_OUTS6_1", - "PSS1_LOGIC_OUTS6_10", - "PSS1_LOGIC_OUTS6_11", - "PSS1_LOGIC_OUTS6_12", - "PSS1_LOGIC_OUTS6_13", - "PSS1_LOGIC_OUTS6_14", - "PSS1_LOGIC_OUTS6_15", - "PSS1_LOGIC_OUTS6_16", - "PSS1_LOGIC_OUTS6_17", - "PSS1_LOGIC_OUTS6_18", - "PSS1_LOGIC_OUTS6_19", - "PSS1_LOGIC_OUTS6_2", - "PSS1_LOGIC_OUTS6_20", - "PSS1_LOGIC_OUTS6_21", - "PSS1_LOGIC_OUTS6_22", - "PSS1_LOGIC_OUTS6_23", - "PSS1_LOGIC_OUTS6_24", - "PSS1_LOGIC_OUTS6_25", - "PSS1_LOGIC_OUTS6_26", - "PSS1_LOGIC_OUTS6_27", - "PSS1_LOGIC_OUTS6_28", - "PSS1_LOGIC_OUTS6_29", - "PSS1_LOGIC_OUTS6_3", - "PSS1_LOGIC_OUTS6_30", - "PSS1_LOGIC_OUTS6_31", - "PSS1_LOGIC_OUTS6_32", - "PSS1_LOGIC_OUTS6_33", - "PSS1_LOGIC_OUTS6_34", - "PSS1_LOGIC_OUTS6_35", - "PSS1_LOGIC_OUTS6_36", - "PSS1_LOGIC_OUTS6_37", - "PSS1_LOGIC_OUTS6_38", - "PSS1_LOGIC_OUTS6_39", - "PSS1_LOGIC_OUTS6_4", - "PSS1_LOGIC_OUTS6_5", - "PSS1_LOGIC_OUTS6_6", - "PSS1_LOGIC_OUTS6_7", - "PSS1_LOGIC_OUTS6_8", - "PSS1_LOGIC_OUTS6_9", - "PSS1_LOGIC_OUTS7_0", - "PSS1_LOGIC_OUTS7_1", - "PSS1_LOGIC_OUTS7_10", - "PSS1_LOGIC_OUTS7_11", - "PSS1_LOGIC_OUTS7_12", - "PSS1_LOGIC_OUTS7_13", - "PSS1_LOGIC_OUTS7_14", - "PSS1_LOGIC_OUTS7_15", - "PSS1_LOGIC_OUTS7_16", - "PSS1_LOGIC_OUTS7_17", - "PSS1_LOGIC_OUTS7_18", - "PSS1_LOGIC_OUTS7_19", - "PSS1_LOGIC_OUTS7_2", - "PSS1_LOGIC_OUTS7_20", - "PSS1_LOGIC_OUTS7_21", - "PSS1_LOGIC_OUTS7_22", - "PSS1_LOGIC_OUTS7_23", - "PSS1_LOGIC_OUTS7_24", - "PSS1_LOGIC_OUTS7_25", - "PSS1_LOGIC_OUTS7_26", - "PSS1_LOGIC_OUTS7_27", - "PSS1_LOGIC_OUTS7_28", - "PSS1_LOGIC_OUTS7_29", - "PSS1_LOGIC_OUTS7_3", - "PSS1_LOGIC_OUTS7_30", - "PSS1_LOGIC_OUTS7_31", - "PSS1_LOGIC_OUTS7_32", - "PSS1_LOGIC_OUTS7_33", - "PSS1_LOGIC_OUTS7_34", - "PSS1_LOGIC_OUTS7_35", - "PSS1_LOGIC_OUTS7_36", - "PSS1_LOGIC_OUTS7_37", - "PSS1_LOGIC_OUTS7_38", - "PSS1_LOGIC_OUTS7_39", - "PSS1_LOGIC_OUTS7_4", - "PSS1_LOGIC_OUTS7_5", - "PSS1_LOGIC_OUTS7_6", - "PSS1_LOGIC_OUTS7_7", - "PSS1_LOGIC_OUTS7_8", - "PSS1_LOGIC_OUTS7_9", - "PSS1_LOGIC_OUTS8_0", - "PSS1_LOGIC_OUTS8_1", - "PSS1_LOGIC_OUTS8_10", - "PSS1_LOGIC_OUTS8_11", - "PSS1_LOGIC_OUTS8_12", - "PSS1_LOGIC_OUTS8_13", - "PSS1_LOGIC_OUTS8_14", - "PSS1_LOGIC_OUTS8_15", - "PSS1_LOGIC_OUTS8_16", - "PSS1_LOGIC_OUTS8_17", - "PSS1_LOGIC_OUTS8_18", - "PSS1_LOGIC_OUTS8_19", - "PSS1_LOGIC_OUTS8_2", - "PSS1_LOGIC_OUTS8_20", - "PSS1_LOGIC_OUTS8_21", - "PSS1_LOGIC_OUTS8_22", - "PSS1_LOGIC_OUTS8_23", - "PSS1_LOGIC_OUTS8_24", - "PSS1_LOGIC_OUTS8_25", - "PSS1_LOGIC_OUTS8_26", - "PSS1_LOGIC_OUTS8_27", - "PSS1_LOGIC_OUTS8_28", - "PSS1_LOGIC_OUTS8_29", - "PSS1_LOGIC_OUTS8_3", - "PSS1_LOGIC_OUTS8_30", - "PSS1_LOGIC_OUTS8_31", - "PSS1_LOGIC_OUTS8_32", - "PSS1_LOGIC_OUTS8_33", - "PSS1_LOGIC_OUTS8_34", - "PSS1_LOGIC_OUTS8_35", - "PSS1_LOGIC_OUTS8_36", - "PSS1_LOGIC_OUTS8_37", - "PSS1_LOGIC_OUTS8_38", - "PSS1_LOGIC_OUTS8_39", - "PSS1_LOGIC_OUTS8_4", - "PSS1_LOGIC_OUTS8_5", - "PSS1_LOGIC_OUTS8_6", - "PSS1_LOGIC_OUTS8_7", - "PSS1_LOGIC_OUTS8_8", - "PSS1_LOGIC_OUTS8_9", - "PSS1_LOGIC_OUTS9_0", - "PSS1_LOGIC_OUTS9_1", - "PSS1_LOGIC_OUTS9_10", - "PSS1_LOGIC_OUTS9_11", - "PSS1_LOGIC_OUTS9_12", - "PSS1_LOGIC_OUTS9_13", - "PSS1_LOGIC_OUTS9_14", - "PSS1_LOGIC_OUTS9_15", - "PSS1_LOGIC_OUTS9_16", - "PSS1_LOGIC_OUTS9_17", - "PSS1_LOGIC_OUTS9_18", - "PSS1_LOGIC_OUTS9_19", - "PSS1_LOGIC_OUTS9_2", - "PSS1_LOGIC_OUTS9_20", - "PSS1_LOGIC_OUTS9_21", - "PSS1_LOGIC_OUTS9_22", - "PSS1_LOGIC_OUTS9_23", - "PSS1_LOGIC_OUTS9_24", - "PSS1_LOGIC_OUTS9_25", - "PSS1_LOGIC_OUTS9_26", - "PSS1_LOGIC_OUTS9_27", - "PSS1_LOGIC_OUTS9_28", - "PSS1_LOGIC_OUTS9_29", - "PSS1_LOGIC_OUTS9_3", - "PSS1_LOGIC_OUTS9_30", - "PSS1_LOGIC_OUTS9_31", - "PSS1_LOGIC_OUTS9_32", - "PSS1_LOGIC_OUTS9_33", - "PSS1_LOGIC_OUTS9_34", - "PSS1_LOGIC_OUTS9_35", - "PSS1_LOGIC_OUTS9_36", - "PSS1_LOGIC_OUTS9_37", - "PSS1_LOGIC_OUTS9_38", - "PSS1_LOGIC_OUTS9_39", - "PSS1_LOGIC_OUTS9_4", - "PSS1_LOGIC_OUTS9_5", - "PSS1_LOGIC_OUTS9_6", - "PSS1_LOGIC_OUTS9_7", - "PSS1_LOGIC_OUTS9_8", - "PSS1_LOGIC_OUTS9_9", - "PSS3_TESTPLLCLKOUT0_IN", - "PSS3_TESTPLLCLKOUT0_OUT", - "PSS3_TESTPLLCLKOUT1_IN", - "PSS3_TESTPLLCLKOUT1_OUT", - "PSS3_TESTPLLCLKOUT2_IN", - "PSS3_TESTPLLCLKOUT2_OUT", - "PSS3_TESTPLLNEWCLK0_IN", - "PSS3_TESTPLLNEWCLK0_OUT", - "PSS3_TESTPLLNEWCLK1_IN", - "PSS3_TESTPLLNEWCLK1_OUT", - "PSS3_TESTPLLNEWCLK2_IN", - "PSS3_TESTPLLNEWCLK2_OUT", - "PSS_BYP_B0_0", - "PSS_BYP_B0_1", - "PSS_BYP_B0_10", - "PSS_BYP_B0_11", - "PSS_BYP_B0_12", - "PSS_BYP_B0_13", - "PSS_BYP_B0_14", - "PSS_BYP_B0_15", - "PSS_BYP_B0_16", - "PSS_BYP_B0_17", - "PSS_BYP_B0_18", - "PSS_BYP_B0_19", - "PSS_BYP_B0_2", - "PSS_BYP_B0_3", - "PSS_BYP_B0_4", - "PSS_BYP_B0_5", - "PSS_BYP_B0_6", - "PSS_BYP_B0_7", - "PSS_BYP_B0_8", - "PSS_BYP_B0_9", - "PSS_BYP_B1_0", - "PSS_BYP_B1_1", - "PSS_BYP_B1_10", - "PSS_BYP_B1_11", - "PSS_BYP_B1_12", - "PSS_BYP_B1_13", - "PSS_BYP_B1_14", - "PSS_BYP_B1_15", - "PSS_BYP_B1_16", - "PSS_BYP_B1_17", - "PSS_BYP_B1_18", - "PSS_BYP_B1_19", - "PSS_BYP_B1_2", - "PSS_BYP_B1_3", - "PSS_BYP_B1_4", - "PSS_BYP_B1_5", - "PSS_BYP_B1_6", - "PSS_BYP_B1_7", - "PSS_BYP_B1_8", - "PSS_BYP_B1_9", - "PSS_BYP_B2_0", - "PSS_BYP_B2_1", - "PSS_BYP_B2_10", - "PSS_BYP_B2_11", - "PSS_BYP_B2_12", - "PSS_BYP_B2_13", - "PSS_BYP_B2_14", - "PSS_BYP_B2_15", - "PSS_BYP_B2_16", - "PSS_BYP_B2_17", - "PSS_BYP_B2_18", - "PSS_BYP_B2_19", - "PSS_BYP_B2_2", - "PSS_BYP_B2_3", - "PSS_BYP_B2_4", - "PSS_BYP_B2_5", - "PSS_BYP_B2_6", - "PSS_BYP_B2_7", - "PSS_BYP_B2_8", - "PSS_BYP_B2_9", - "PSS_BYP_B3_0", - "PSS_BYP_B3_1", - "PSS_BYP_B3_10", - "PSS_BYP_B3_11", - "PSS_BYP_B3_12", - "PSS_BYP_B3_13", - "PSS_BYP_B3_14", - "PSS_BYP_B3_15", - "PSS_BYP_B3_16", - "PSS_BYP_B3_17", - "PSS_BYP_B3_18", - "PSS_BYP_B3_19", - "PSS_BYP_B3_2", - "PSS_BYP_B3_3", - "PSS_BYP_B3_4", - "PSS_BYP_B3_5", - "PSS_BYP_B3_6", - "PSS_BYP_B3_7", - "PSS_BYP_B3_8", - "PSS_BYP_B3_9", - "PSS_BYP_B4_0", - "PSS_BYP_B4_1", - "PSS_BYP_B4_10", - "PSS_BYP_B4_11", - "PSS_BYP_B4_12", - "PSS_BYP_B4_13", - "PSS_BYP_B4_14", - "PSS_BYP_B4_15", - "PSS_BYP_B4_16", - "PSS_BYP_B4_17", - "PSS_BYP_B4_18", - "PSS_BYP_B4_19", - "PSS_BYP_B4_2", - "PSS_BYP_B4_3", - "PSS_BYP_B4_4", - "PSS_BYP_B4_5", - "PSS_BYP_B4_6", - "PSS_BYP_B4_7", - "PSS_BYP_B4_8", - "PSS_BYP_B4_9", - "PSS_BYP_B5_0", - "PSS_BYP_B5_1", - "PSS_BYP_B5_10", - "PSS_BYP_B5_11", - "PSS_BYP_B5_12", - "PSS_BYP_B5_13", - "PSS_BYP_B5_14", - "PSS_BYP_B5_15", - "PSS_BYP_B5_16", - "PSS_BYP_B5_17", - "PSS_BYP_B5_18", - "PSS_BYP_B5_19", - "PSS_BYP_B5_2", - "PSS_BYP_B5_3", - "PSS_BYP_B5_4", - "PSS_BYP_B5_5", - "PSS_BYP_B5_6", - "PSS_BYP_B5_7", - "PSS_BYP_B5_8", - "PSS_BYP_B5_9", - "PSS_BYP_B6_0", - "PSS_BYP_B6_1", - "PSS_BYP_B6_10", - "PSS_BYP_B6_11", - "PSS_BYP_B6_12", - "PSS_BYP_B6_13", - "PSS_BYP_B6_14", - "PSS_BYP_B6_15", - "PSS_BYP_B6_16", - "PSS_BYP_B6_17", - "PSS_BYP_B6_18", - "PSS_BYP_B6_19", - "PSS_BYP_B6_2", - "PSS_BYP_B6_3", - "PSS_BYP_B6_4", - "PSS_BYP_B6_5", - "PSS_BYP_B6_6", - "PSS_BYP_B6_7", - "PSS_BYP_B6_8", - "PSS_BYP_B6_9", - "PSS_BYP_B7_0", - "PSS_BYP_B7_1", - "PSS_BYP_B7_10", - "PSS_BYP_B7_11", - "PSS_BYP_B7_12", - "PSS_BYP_B7_13", - "PSS_BYP_B7_14", - "PSS_BYP_B7_15", - "PSS_BYP_B7_16", - "PSS_BYP_B7_17", - "PSS_BYP_B7_18", - "PSS_BYP_B7_19", - "PSS_BYP_B7_2", - "PSS_BYP_B7_3", - "PSS_BYP_B7_4", - "PSS_BYP_B7_5", - "PSS_BYP_B7_6", - "PSS_BYP_B7_7", - "PSS_BYP_B7_8", - "PSS_BYP_B7_9", - "PSS_CLK_B0_0", - "PSS_CLK_B0_1", - "PSS_CLK_B0_10", - "PSS_CLK_B0_11", - "PSS_CLK_B0_12", - "PSS_CLK_B0_13", - "PSS_CLK_B0_14", - "PSS_CLK_B0_15", - "PSS_CLK_B0_16", - "PSS_CLK_B0_17", - "PSS_CLK_B0_18", - "PSS_CLK_B0_19", - "PSS_CLK_B0_2", - "PSS_CLK_B0_3", - "PSS_CLK_B0_4", - "PSS_CLK_B0_5", - "PSS_CLK_B0_6", - "PSS_CLK_B0_7", - "PSS_CLK_B0_8", - "PSS_CLK_B0_9", - "PSS_CLK_B1_0", - "PSS_CLK_B1_1", - "PSS_CLK_B1_10", - "PSS_CLK_B1_11", - "PSS_CLK_B1_12", - "PSS_CLK_B1_13", - "PSS_CLK_B1_14", - "PSS_CLK_B1_15", - "PSS_CLK_B1_16", - "PSS_CLK_B1_17", - "PSS_CLK_B1_18", - "PSS_CLK_B1_19", - "PSS_CLK_B1_2", - "PSS_CLK_B1_3", - "PSS_CLK_B1_4", - "PSS_CLK_B1_5", - "PSS_CLK_B1_6", - "PSS_CLK_B1_7", - "PSS_CLK_B1_8", - "PSS_CLK_B1_9", - "PSS_CTRL_B0_0", - "PSS_CTRL_B0_1", - "PSS_CTRL_B0_10", - "PSS_CTRL_B0_11", - "PSS_CTRL_B0_12", - "PSS_CTRL_B0_13", - "PSS_CTRL_B0_14", - "PSS_CTRL_B0_15", - "PSS_CTRL_B0_16", - "PSS_CTRL_B0_17", - "PSS_CTRL_B0_18", - "PSS_CTRL_B0_19", - "PSS_CTRL_B0_2", - "PSS_CTRL_B0_3", - "PSS_CTRL_B0_4", - "PSS_CTRL_B0_5", - "PSS_CTRL_B0_6", - "PSS_CTRL_B0_7", - "PSS_CTRL_B0_8", - "PSS_CTRL_B0_9", - "PSS_CTRL_B1_0", - "PSS_CTRL_B1_1", - "PSS_CTRL_B1_10", - "PSS_CTRL_B1_11", - "PSS_CTRL_B1_12", - "PSS_CTRL_B1_13", - "PSS_CTRL_B1_14", - "PSS_CTRL_B1_15", - "PSS_CTRL_B1_16", - "PSS_CTRL_B1_17", - "PSS_CTRL_B1_18", - "PSS_CTRL_B1_19", - "PSS_CTRL_B1_2", - "PSS_CTRL_B1_3", - "PSS_CTRL_B1_4", - "PSS_CTRL_B1_5", - "PSS_CTRL_B1_6", - "PSS_CTRL_B1_7", - "PSS_CTRL_B1_8", - "PSS_CTRL_B1_9", - "PSS_FAN_B0_0", - "PSS_FAN_B0_1", - "PSS_FAN_B0_10", - "PSS_FAN_B0_11", - "PSS_FAN_B0_12", - "PSS_FAN_B0_13", - "PSS_FAN_B0_14", - "PSS_FAN_B0_15", - "PSS_FAN_B0_16", - "PSS_FAN_B0_17", - "PSS_FAN_B0_18", - "PSS_FAN_B0_19", - "PSS_FAN_B0_2", - "PSS_FAN_B0_3", - "PSS_FAN_B0_4", - "PSS_FAN_B0_5", - "PSS_FAN_B0_6", - "PSS_FAN_B0_7", - "PSS_FAN_B0_8", - "PSS_FAN_B0_9", - "PSS_FAN_B1_0", - "PSS_FAN_B1_1", - "PSS_FAN_B1_10", - "PSS_FAN_B1_11", - "PSS_FAN_B1_12", - "PSS_FAN_B1_13", - "PSS_FAN_B1_14", - "PSS_FAN_B1_15", - "PSS_FAN_B1_16", - "PSS_FAN_B1_17", - "PSS_FAN_B1_18", - "PSS_FAN_B1_19", - "PSS_FAN_B1_2", - "PSS_FAN_B1_3", - "PSS_FAN_B1_4", - "PSS_FAN_B1_5", - "PSS_FAN_B1_6", - "PSS_FAN_B1_7", - "PSS_FAN_B1_8", - "PSS_FAN_B1_9", - "PSS_FAN_B2_0", - "PSS_FAN_B2_1", - "PSS_FAN_B2_10", - "PSS_FAN_B2_11", - "PSS_FAN_B2_12", - "PSS_FAN_B2_13", - "PSS_FAN_B2_14", - "PSS_FAN_B2_15", - "PSS_FAN_B2_16", - "PSS_FAN_B2_17", - "PSS_FAN_B2_18", - "PSS_FAN_B2_19", - "PSS_FAN_B2_2", - "PSS_FAN_B2_3", - "PSS_FAN_B2_4", - "PSS_FAN_B2_5", - "PSS_FAN_B2_6", - "PSS_FAN_B2_7", - "PSS_FAN_B2_8", - "PSS_FAN_B2_9", - "PSS_FAN_B3_0", - "PSS_FAN_B3_1", - "PSS_FAN_B3_10", - "PSS_FAN_B3_11", - "PSS_FAN_B3_12", - "PSS_FAN_B3_13", - "PSS_FAN_B3_14", - "PSS_FAN_B3_15", - "PSS_FAN_B3_16", - "PSS_FAN_B3_17", - "PSS_FAN_B3_18", - "PSS_FAN_B3_19", - "PSS_FAN_B3_2", - "PSS_FAN_B3_3", - "PSS_FAN_B3_4", - "PSS_FAN_B3_5", - "PSS_FAN_B3_6", - "PSS_FAN_B3_7", - "PSS_FAN_B3_8", - "PSS_FAN_B3_9", - "PSS_FAN_B4_0", - "PSS_FAN_B4_1", - "PSS_FAN_B4_10", - "PSS_FAN_B4_11", - "PSS_FAN_B4_12", - "PSS_FAN_B4_13", - "PSS_FAN_B4_14", - "PSS_FAN_B4_15", - "PSS_FAN_B4_16", - "PSS_FAN_B4_17", - "PSS_FAN_B4_18", - "PSS_FAN_B4_19", - "PSS_FAN_B4_2", - "PSS_FAN_B4_3", - "PSS_FAN_B4_4", - "PSS_FAN_B4_5", - "PSS_FAN_B4_6", - "PSS_FAN_B4_7", - "PSS_FAN_B4_8", - "PSS_FAN_B4_9", - "PSS_FAN_B5_0", - "PSS_FAN_B5_1", - "PSS_FAN_B5_10", - "PSS_FAN_B5_11", - "PSS_FAN_B5_12", - "PSS_FAN_B5_13", - "PSS_FAN_B5_14", - "PSS_FAN_B5_15", - "PSS_FAN_B5_16", - "PSS_FAN_B5_17", - "PSS_FAN_B5_18", - "PSS_FAN_B5_19", - "PSS_FAN_B5_2", - "PSS_FAN_B5_3", - "PSS_FAN_B5_4", - "PSS_FAN_B5_5", - "PSS_FAN_B5_6", - "PSS_FAN_B5_7", - "PSS_FAN_B5_8", - "PSS_FAN_B5_9", - "PSS_FAN_B6_0", - "PSS_FAN_B6_1", - "PSS_FAN_B6_10", - "PSS_FAN_B6_11", - "PSS_FAN_B6_12", - "PSS_FAN_B6_13", - "PSS_FAN_B6_14", - "PSS_FAN_B6_15", - "PSS_FAN_B6_16", - "PSS_FAN_B6_17", - "PSS_FAN_B6_18", - "PSS_FAN_B6_19", - "PSS_FAN_B6_2", - "PSS_FAN_B6_3", - "PSS_FAN_B6_4", - "PSS_FAN_B6_5", - "PSS_FAN_B6_6", - "PSS_FAN_B6_7", - "PSS_FAN_B6_8", - "PSS_FAN_B6_9", - "PSS_FAN_B7_0", - "PSS_FAN_B7_1", - "PSS_FAN_B7_10", - "PSS_FAN_B7_11", - "PSS_FAN_B7_12", - "PSS_FAN_B7_13", - "PSS_FAN_B7_14", - "PSS_FAN_B7_15", - "PSS_FAN_B7_16", - "PSS_FAN_B7_17", - "PSS_FAN_B7_18", - "PSS_FAN_B7_19", - "PSS_FAN_B7_2", - "PSS_FAN_B7_3", - "PSS_FAN_B7_4", - "PSS_FAN_B7_5", - "PSS_FAN_B7_6", - "PSS_FAN_B7_7", - "PSS_FAN_B7_8", - "PSS_FAN_B7_9", - "PSS_IMUX_B0_0", - "PSS_IMUX_B0_1", - "PSS_IMUX_B0_10", - "PSS_IMUX_B0_11", - "PSS_IMUX_B0_12", - "PSS_IMUX_B0_13", - "PSS_IMUX_B0_14", - "PSS_IMUX_B0_15", - "PSS_IMUX_B0_16", - "PSS_IMUX_B0_17", - "PSS_IMUX_B0_18", - "PSS_IMUX_B0_19", - "PSS_IMUX_B0_2", - "PSS_IMUX_B0_3", - "PSS_IMUX_B0_4", - "PSS_IMUX_B0_5", - "PSS_IMUX_B0_6", - "PSS_IMUX_B0_7", - "PSS_IMUX_B0_8", - "PSS_IMUX_B0_9", - "PSS_IMUX_B10_0", - "PSS_IMUX_B10_1", - "PSS_IMUX_B10_10", - "PSS_IMUX_B10_11", - "PSS_IMUX_B10_12", - "PSS_IMUX_B10_13", - "PSS_IMUX_B10_14", - "PSS_IMUX_B10_15", - "PSS_IMUX_B10_16", - "PSS_IMUX_B10_17", - "PSS_IMUX_B10_18", - "PSS_IMUX_B10_19", - "PSS_IMUX_B10_2", - "PSS_IMUX_B10_3", - "PSS_IMUX_B10_4", - "PSS_IMUX_B10_5", - "PSS_IMUX_B10_6", - "PSS_IMUX_B10_7", - "PSS_IMUX_B10_8", - "PSS_IMUX_B10_9", - "PSS_IMUX_B11_0", - "PSS_IMUX_B11_1", - "PSS_IMUX_B11_10", - "PSS_IMUX_B11_11", - "PSS_IMUX_B11_12", - "PSS_IMUX_B11_13", - "PSS_IMUX_B11_14", - "PSS_IMUX_B11_15", - "PSS_IMUX_B11_16", - "PSS_IMUX_B11_17", - "PSS_IMUX_B11_18", - "PSS_IMUX_B11_19", - "PSS_IMUX_B11_2", - "PSS_IMUX_B11_3", - "PSS_IMUX_B11_4", - "PSS_IMUX_B11_5", - "PSS_IMUX_B11_6", - "PSS_IMUX_B11_7", - "PSS_IMUX_B11_8", - "PSS_IMUX_B11_9", - "PSS_IMUX_B12_0", - "PSS_IMUX_B12_1", - "PSS_IMUX_B12_10", - "PSS_IMUX_B12_11", - "PSS_IMUX_B12_12", - "PSS_IMUX_B12_13", - "PSS_IMUX_B12_14", - "PSS_IMUX_B12_15", - "PSS_IMUX_B12_16", - "PSS_IMUX_B12_17", - "PSS_IMUX_B12_18", - "PSS_IMUX_B12_19", - "PSS_IMUX_B12_2", - "PSS_IMUX_B12_3", - "PSS_IMUX_B12_4", - "PSS_IMUX_B12_5", - "PSS_IMUX_B12_6", - "PSS_IMUX_B12_7", - "PSS_IMUX_B12_8", - "PSS_IMUX_B12_9", - "PSS_IMUX_B13_0", - "PSS_IMUX_B13_1", - "PSS_IMUX_B13_10", - "PSS_IMUX_B13_11", - "PSS_IMUX_B13_12", - "PSS_IMUX_B13_13", - "PSS_IMUX_B13_14", - "PSS_IMUX_B13_15", - "PSS_IMUX_B13_16", - "PSS_IMUX_B13_17", - "PSS_IMUX_B13_18", - "PSS_IMUX_B13_19", - "PSS_IMUX_B13_2", - "PSS_IMUX_B13_3", - "PSS_IMUX_B13_4", - "PSS_IMUX_B13_5", - "PSS_IMUX_B13_6", - "PSS_IMUX_B13_7", - "PSS_IMUX_B13_8", - "PSS_IMUX_B13_9", - "PSS_IMUX_B14_0", - "PSS_IMUX_B14_1", - "PSS_IMUX_B14_10", - "PSS_IMUX_B14_11", - "PSS_IMUX_B14_12", - "PSS_IMUX_B14_13", - "PSS_IMUX_B14_14", - "PSS_IMUX_B14_15", - "PSS_IMUX_B14_16", - "PSS_IMUX_B14_17", - "PSS_IMUX_B14_18", - "PSS_IMUX_B14_19", - "PSS_IMUX_B14_2", - "PSS_IMUX_B14_3", - "PSS_IMUX_B14_4", - "PSS_IMUX_B14_5", - "PSS_IMUX_B14_6", - "PSS_IMUX_B14_7", - "PSS_IMUX_B14_8", - "PSS_IMUX_B14_9", - "PSS_IMUX_B15_0", - "PSS_IMUX_B15_1", - "PSS_IMUX_B15_10", - "PSS_IMUX_B15_11", - "PSS_IMUX_B15_12", - "PSS_IMUX_B15_13", - "PSS_IMUX_B15_14", - "PSS_IMUX_B15_15", - "PSS_IMUX_B15_16", - "PSS_IMUX_B15_17", - "PSS_IMUX_B15_18", - "PSS_IMUX_B15_19", - "PSS_IMUX_B15_2", - "PSS_IMUX_B15_3", - "PSS_IMUX_B15_4", - "PSS_IMUX_B15_5", - "PSS_IMUX_B15_6", - "PSS_IMUX_B15_7", - "PSS_IMUX_B15_8", - "PSS_IMUX_B15_9", - "PSS_IMUX_B16_0", - "PSS_IMUX_B16_1", - "PSS_IMUX_B16_10", - "PSS_IMUX_B16_11", - "PSS_IMUX_B16_12", - "PSS_IMUX_B16_13", - "PSS_IMUX_B16_14", - "PSS_IMUX_B16_15", - "PSS_IMUX_B16_16", - "PSS_IMUX_B16_17", - "PSS_IMUX_B16_18", - "PSS_IMUX_B16_19", - "PSS_IMUX_B16_2", - "PSS_IMUX_B16_3", - "PSS_IMUX_B16_4", - "PSS_IMUX_B16_5", - "PSS_IMUX_B16_6", - "PSS_IMUX_B16_7", - "PSS_IMUX_B16_8", - "PSS_IMUX_B16_9", - "PSS_IMUX_B17_0", - "PSS_IMUX_B17_1", - "PSS_IMUX_B17_10", - "PSS_IMUX_B17_11", - "PSS_IMUX_B17_12", - "PSS_IMUX_B17_13", - "PSS_IMUX_B17_14", - "PSS_IMUX_B17_15", - "PSS_IMUX_B17_16", - "PSS_IMUX_B17_17", - "PSS_IMUX_B17_18", - "PSS_IMUX_B17_19", - "PSS_IMUX_B17_2", - "PSS_IMUX_B17_3", - "PSS_IMUX_B17_4", - "PSS_IMUX_B17_5", - "PSS_IMUX_B17_6", - "PSS_IMUX_B17_7", - "PSS_IMUX_B17_8", - "PSS_IMUX_B17_9", - "PSS_IMUX_B18_0", - "PSS_IMUX_B18_1", - "PSS_IMUX_B18_10", - "PSS_IMUX_B18_11", - "PSS_IMUX_B18_12", - "PSS_IMUX_B18_13", - "PSS_IMUX_B18_14", - "PSS_IMUX_B18_15", - "PSS_IMUX_B18_16", - "PSS_IMUX_B18_17", - "PSS_IMUX_B18_18", - "PSS_IMUX_B18_19", - "PSS_IMUX_B18_2", - "PSS_IMUX_B18_3", - "PSS_IMUX_B18_4", - "PSS_IMUX_B18_5", - "PSS_IMUX_B18_6", - "PSS_IMUX_B18_7", - "PSS_IMUX_B18_8", - "PSS_IMUX_B18_9", - "PSS_IMUX_B19_0", - "PSS_IMUX_B19_1", - "PSS_IMUX_B19_10", - "PSS_IMUX_B19_11", - "PSS_IMUX_B19_12", - "PSS_IMUX_B19_13", - "PSS_IMUX_B19_14", - "PSS_IMUX_B19_15", - "PSS_IMUX_B19_16", - "PSS_IMUX_B19_17", - "PSS_IMUX_B19_18", - "PSS_IMUX_B19_19", - "PSS_IMUX_B19_2", - "PSS_IMUX_B19_3", - "PSS_IMUX_B19_4", - "PSS_IMUX_B19_5", - "PSS_IMUX_B19_6", - "PSS_IMUX_B19_7", - "PSS_IMUX_B19_8", - "PSS_IMUX_B19_9", - "PSS_IMUX_B1_0", - "PSS_IMUX_B1_1", - "PSS_IMUX_B1_10", - "PSS_IMUX_B1_11", - "PSS_IMUX_B1_12", - "PSS_IMUX_B1_13", - "PSS_IMUX_B1_14", - "PSS_IMUX_B1_15", - "PSS_IMUX_B1_16", - "PSS_IMUX_B1_17", - "PSS_IMUX_B1_18", - "PSS_IMUX_B1_19", - "PSS_IMUX_B1_2", - "PSS_IMUX_B1_3", - "PSS_IMUX_B1_4", - "PSS_IMUX_B1_5", - "PSS_IMUX_B1_6", - "PSS_IMUX_B1_7", - "PSS_IMUX_B1_8", - "PSS_IMUX_B1_9", - "PSS_IMUX_B20_0", - "PSS_IMUX_B20_1", - "PSS_IMUX_B20_10", - "PSS_IMUX_B20_11", - "PSS_IMUX_B20_12", - "PSS_IMUX_B20_13", - "PSS_IMUX_B20_14", - "PSS_IMUX_B20_15", - "PSS_IMUX_B20_16", - "PSS_IMUX_B20_17", - "PSS_IMUX_B20_18", - "PSS_IMUX_B20_19", - "PSS_IMUX_B20_2", - "PSS_IMUX_B20_3", - "PSS_IMUX_B20_4", - "PSS_IMUX_B20_5", - "PSS_IMUX_B20_6", - "PSS_IMUX_B20_7", - "PSS_IMUX_B20_8", - "PSS_IMUX_B20_9", - "PSS_IMUX_B21_0", - "PSS_IMUX_B21_1", - "PSS_IMUX_B21_10", - "PSS_IMUX_B21_11", - "PSS_IMUX_B21_12", - "PSS_IMUX_B21_13", - "PSS_IMUX_B21_14", - "PSS_IMUX_B21_15", - "PSS_IMUX_B21_16", - "PSS_IMUX_B21_17", - "PSS_IMUX_B21_18", - "PSS_IMUX_B21_19", - "PSS_IMUX_B21_2", - "PSS_IMUX_B21_3", - "PSS_IMUX_B21_4", - "PSS_IMUX_B21_5", - "PSS_IMUX_B21_6", - "PSS_IMUX_B21_7", - "PSS_IMUX_B21_8", - "PSS_IMUX_B21_9", - "PSS_IMUX_B22_0", - "PSS_IMUX_B22_1", - "PSS_IMUX_B22_10", - "PSS_IMUX_B22_11", - "PSS_IMUX_B22_12", - "PSS_IMUX_B22_13", - "PSS_IMUX_B22_14", - "PSS_IMUX_B22_15", - "PSS_IMUX_B22_16", - "PSS_IMUX_B22_17", - "PSS_IMUX_B22_18", - "PSS_IMUX_B22_19", - "PSS_IMUX_B22_2", - "PSS_IMUX_B22_3", - "PSS_IMUX_B22_4", - "PSS_IMUX_B22_5", - "PSS_IMUX_B22_6", - "PSS_IMUX_B22_7", - "PSS_IMUX_B22_8", - "PSS_IMUX_B22_9", - "PSS_IMUX_B23_0", - "PSS_IMUX_B23_1", - "PSS_IMUX_B23_10", - "PSS_IMUX_B23_11", - "PSS_IMUX_B23_12", - "PSS_IMUX_B23_13", - "PSS_IMUX_B23_14", - "PSS_IMUX_B23_15", - "PSS_IMUX_B23_16", - "PSS_IMUX_B23_17", - "PSS_IMUX_B23_18", - "PSS_IMUX_B23_19", - "PSS_IMUX_B23_2", - "PSS_IMUX_B23_3", - "PSS_IMUX_B23_4", - "PSS_IMUX_B23_5", - "PSS_IMUX_B23_6", - "PSS_IMUX_B23_7", - "PSS_IMUX_B23_8", - "PSS_IMUX_B23_9", - "PSS_IMUX_B24_0", - "PSS_IMUX_B24_1", - "PSS_IMUX_B24_10", - "PSS_IMUX_B24_11", - "PSS_IMUX_B24_12", - "PSS_IMUX_B24_13", - "PSS_IMUX_B24_14", - "PSS_IMUX_B24_15", - "PSS_IMUX_B24_16", - "PSS_IMUX_B24_17", - "PSS_IMUX_B24_18", - "PSS_IMUX_B24_19", - "PSS_IMUX_B24_2", - "PSS_IMUX_B24_3", - "PSS_IMUX_B24_4", - "PSS_IMUX_B24_5", - "PSS_IMUX_B24_6", - "PSS_IMUX_B24_7", - "PSS_IMUX_B24_8", - "PSS_IMUX_B24_9", - "PSS_IMUX_B25_0", - "PSS_IMUX_B25_1", - "PSS_IMUX_B25_10", - "PSS_IMUX_B25_11", - "PSS_IMUX_B25_12", - "PSS_IMUX_B25_13", - "PSS_IMUX_B25_14", - "PSS_IMUX_B25_15", - "PSS_IMUX_B25_16", - "PSS_IMUX_B25_17", - "PSS_IMUX_B25_18", - "PSS_IMUX_B25_19", - "PSS_IMUX_B25_2", - "PSS_IMUX_B25_3", - "PSS_IMUX_B25_4", - "PSS_IMUX_B25_5", - "PSS_IMUX_B25_6", - "PSS_IMUX_B25_7", - "PSS_IMUX_B25_8", - "PSS_IMUX_B25_9", - "PSS_IMUX_B26_0", - "PSS_IMUX_B26_1", - "PSS_IMUX_B26_10", - "PSS_IMUX_B26_11", - "PSS_IMUX_B26_12", - "PSS_IMUX_B26_13", - "PSS_IMUX_B26_14", - "PSS_IMUX_B26_15", - "PSS_IMUX_B26_16", - "PSS_IMUX_B26_17", - "PSS_IMUX_B26_18", - "PSS_IMUX_B26_19", - "PSS_IMUX_B26_2", - "PSS_IMUX_B26_3", - "PSS_IMUX_B26_4", - "PSS_IMUX_B26_5", - "PSS_IMUX_B26_6", - "PSS_IMUX_B26_7", - "PSS_IMUX_B26_8", - "PSS_IMUX_B26_9", - "PSS_IMUX_B27_0", - "PSS_IMUX_B27_1", - "PSS_IMUX_B27_10", - "PSS_IMUX_B27_11", - "PSS_IMUX_B27_12", - "PSS_IMUX_B27_13", - "PSS_IMUX_B27_14", - "PSS_IMUX_B27_15", - "PSS_IMUX_B27_16", - "PSS_IMUX_B27_17", - "PSS_IMUX_B27_18", - "PSS_IMUX_B27_19", - "PSS_IMUX_B27_2", - "PSS_IMUX_B27_3", - "PSS_IMUX_B27_4", - "PSS_IMUX_B27_5", - "PSS_IMUX_B27_6", - "PSS_IMUX_B27_7", - "PSS_IMUX_B27_8", - "PSS_IMUX_B27_9", - "PSS_IMUX_B28_0", - "PSS_IMUX_B28_1", - "PSS_IMUX_B28_10", - "PSS_IMUX_B28_11", - "PSS_IMUX_B28_12", - "PSS_IMUX_B28_13", - "PSS_IMUX_B28_14", - "PSS_IMUX_B28_15", - "PSS_IMUX_B28_16", - "PSS_IMUX_B28_17", - "PSS_IMUX_B28_18", - "PSS_IMUX_B28_19", - "PSS_IMUX_B28_2", - "PSS_IMUX_B28_3", - "PSS_IMUX_B28_4", - "PSS_IMUX_B28_5", - "PSS_IMUX_B28_6", - "PSS_IMUX_B28_7", - "PSS_IMUX_B28_8", - "PSS_IMUX_B28_9", - "PSS_IMUX_B29_0", - "PSS_IMUX_B29_1", - "PSS_IMUX_B29_10", - "PSS_IMUX_B29_11", - "PSS_IMUX_B29_12", - "PSS_IMUX_B29_13", - "PSS_IMUX_B29_14", - "PSS_IMUX_B29_15", - "PSS_IMUX_B29_16", - "PSS_IMUX_B29_17", - "PSS_IMUX_B29_18", - "PSS_IMUX_B29_19", - "PSS_IMUX_B29_2", - "PSS_IMUX_B29_3", - "PSS_IMUX_B29_4", - "PSS_IMUX_B29_5", - "PSS_IMUX_B29_6", - "PSS_IMUX_B29_7", - "PSS_IMUX_B29_8", - "PSS_IMUX_B29_9", - "PSS_IMUX_B2_0", - "PSS_IMUX_B2_1", - "PSS_IMUX_B2_10", - "PSS_IMUX_B2_11", - "PSS_IMUX_B2_12", - "PSS_IMUX_B2_13", - "PSS_IMUX_B2_14", - "PSS_IMUX_B2_15", - "PSS_IMUX_B2_16", - "PSS_IMUX_B2_17", - "PSS_IMUX_B2_18", - "PSS_IMUX_B2_19", - "PSS_IMUX_B2_2", - "PSS_IMUX_B2_3", - "PSS_IMUX_B2_4", - "PSS_IMUX_B2_5", - "PSS_IMUX_B2_6", - "PSS_IMUX_B2_7", - "PSS_IMUX_B2_8", - "PSS_IMUX_B2_9", - "PSS_IMUX_B30_0", - "PSS_IMUX_B30_1", - "PSS_IMUX_B30_10", - "PSS_IMUX_B30_11", - "PSS_IMUX_B30_12", - "PSS_IMUX_B30_13", - "PSS_IMUX_B30_14", - "PSS_IMUX_B30_15", - "PSS_IMUX_B30_16", - "PSS_IMUX_B30_17", - "PSS_IMUX_B30_18", - "PSS_IMUX_B30_19", - "PSS_IMUX_B30_2", - "PSS_IMUX_B30_3", - "PSS_IMUX_B30_4", - "PSS_IMUX_B30_5", - "PSS_IMUX_B30_6", - "PSS_IMUX_B30_7", - "PSS_IMUX_B30_8", - "PSS_IMUX_B30_9", - "PSS_IMUX_B31_0", - "PSS_IMUX_B31_1", - "PSS_IMUX_B31_10", - "PSS_IMUX_B31_11", - "PSS_IMUX_B31_12", - "PSS_IMUX_B31_13", - "PSS_IMUX_B31_14", - "PSS_IMUX_B31_15", - "PSS_IMUX_B31_16", - "PSS_IMUX_B31_17", - "PSS_IMUX_B31_18", - "PSS_IMUX_B31_19", - "PSS_IMUX_B31_2", - "PSS_IMUX_B31_3", - "PSS_IMUX_B31_4", - "PSS_IMUX_B31_5", - "PSS_IMUX_B31_6", - "PSS_IMUX_B31_7", - "PSS_IMUX_B31_8", - "PSS_IMUX_B31_9", - "PSS_IMUX_B32_0", - "PSS_IMUX_B32_1", - "PSS_IMUX_B32_10", - "PSS_IMUX_B32_11", - "PSS_IMUX_B32_12", - "PSS_IMUX_B32_13", - "PSS_IMUX_B32_14", - "PSS_IMUX_B32_15", - "PSS_IMUX_B32_16", - "PSS_IMUX_B32_17", - "PSS_IMUX_B32_18", - "PSS_IMUX_B32_19", - "PSS_IMUX_B32_2", - "PSS_IMUX_B32_3", - "PSS_IMUX_B32_4", - "PSS_IMUX_B32_5", - "PSS_IMUX_B32_6", - "PSS_IMUX_B32_7", - "PSS_IMUX_B32_8", - "PSS_IMUX_B32_9", - "PSS_IMUX_B33_0", - "PSS_IMUX_B33_1", - "PSS_IMUX_B33_10", - "PSS_IMUX_B33_11", - "PSS_IMUX_B33_12", - "PSS_IMUX_B33_13", - "PSS_IMUX_B33_14", - "PSS_IMUX_B33_15", - "PSS_IMUX_B33_16", - "PSS_IMUX_B33_17", - "PSS_IMUX_B33_18", - "PSS_IMUX_B33_19", - "PSS_IMUX_B33_2", - "PSS_IMUX_B33_3", - "PSS_IMUX_B33_4", - "PSS_IMUX_B33_5", - "PSS_IMUX_B33_6", - "PSS_IMUX_B33_7", - "PSS_IMUX_B33_8", - "PSS_IMUX_B33_9", - "PSS_IMUX_B34_0", - "PSS_IMUX_B34_1", - "PSS_IMUX_B34_10", - "PSS_IMUX_B34_11", - "PSS_IMUX_B34_12", - "PSS_IMUX_B34_13", - "PSS_IMUX_B34_14", - "PSS_IMUX_B34_15", - "PSS_IMUX_B34_16", - "PSS_IMUX_B34_17", - "PSS_IMUX_B34_18", - "PSS_IMUX_B34_19", - "PSS_IMUX_B34_2", - "PSS_IMUX_B34_3", - "PSS_IMUX_B34_4", - "PSS_IMUX_B34_5", - "PSS_IMUX_B34_6", - "PSS_IMUX_B34_7", - "PSS_IMUX_B34_8", - "PSS_IMUX_B34_9", - "PSS_IMUX_B35_0", - "PSS_IMUX_B35_1", - "PSS_IMUX_B35_10", - "PSS_IMUX_B35_11", - "PSS_IMUX_B35_12", - "PSS_IMUX_B35_13", - "PSS_IMUX_B35_14", - "PSS_IMUX_B35_15", - "PSS_IMUX_B35_16", - "PSS_IMUX_B35_17", - "PSS_IMUX_B35_18", - "PSS_IMUX_B35_19", - "PSS_IMUX_B35_2", - "PSS_IMUX_B35_3", - "PSS_IMUX_B35_4", - "PSS_IMUX_B35_5", - "PSS_IMUX_B35_6", - "PSS_IMUX_B35_7", - "PSS_IMUX_B35_8", - "PSS_IMUX_B35_9", - "PSS_IMUX_B36_0", - "PSS_IMUX_B36_1", - "PSS_IMUX_B36_10", - "PSS_IMUX_B36_11", - "PSS_IMUX_B36_12", - "PSS_IMUX_B36_13", - "PSS_IMUX_B36_14", - "PSS_IMUX_B36_15", - "PSS_IMUX_B36_16", - "PSS_IMUX_B36_17", - "PSS_IMUX_B36_18", - "PSS_IMUX_B36_19", - "PSS_IMUX_B36_2", - "PSS_IMUX_B36_3", - "PSS_IMUX_B36_4", - "PSS_IMUX_B36_5", - "PSS_IMUX_B36_6", - "PSS_IMUX_B36_7", - "PSS_IMUX_B36_8", - "PSS_IMUX_B36_9", - "PSS_IMUX_B37_0", - "PSS_IMUX_B37_1", - "PSS_IMUX_B37_10", - "PSS_IMUX_B37_11", - "PSS_IMUX_B37_12", - "PSS_IMUX_B37_13", - "PSS_IMUX_B37_14", - "PSS_IMUX_B37_15", - "PSS_IMUX_B37_16", - "PSS_IMUX_B37_17", - "PSS_IMUX_B37_18", - "PSS_IMUX_B37_19", - "PSS_IMUX_B37_2", - "PSS_IMUX_B37_3", - "PSS_IMUX_B37_4", - "PSS_IMUX_B37_5", - "PSS_IMUX_B37_6", - "PSS_IMUX_B37_7", - "PSS_IMUX_B37_8", - "PSS_IMUX_B37_9", - "PSS_IMUX_B38_0", - "PSS_IMUX_B38_1", - "PSS_IMUX_B38_10", - "PSS_IMUX_B38_11", - "PSS_IMUX_B38_12", - "PSS_IMUX_B38_13", - "PSS_IMUX_B38_14", - "PSS_IMUX_B38_15", - "PSS_IMUX_B38_16", - "PSS_IMUX_B38_17", - "PSS_IMUX_B38_18", - "PSS_IMUX_B38_19", - "PSS_IMUX_B38_2", - "PSS_IMUX_B38_3", - "PSS_IMUX_B38_4", - "PSS_IMUX_B38_5", - "PSS_IMUX_B38_6", - "PSS_IMUX_B38_7", - "PSS_IMUX_B38_8", - "PSS_IMUX_B38_9", - "PSS_IMUX_B39_0", - "PSS_IMUX_B39_1", - "PSS_IMUX_B39_10", - "PSS_IMUX_B39_11", - "PSS_IMUX_B39_12", - "PSS_IMUX_B39_13", - "PSS_IMUX_B39_14", - "PSS_IMUX_B39_15", - "PSS_IMUX_B39_16", - "PSS_IMUX_B39_17", - "PSS_IMUX_B39_18", - "PSS_IMUX_B39_19", - "PSS_IMUX_B39_2", - "PSS_IMUX_B39_3", - "PSS_IMUX_B39_4", - "PSS_IMUX_B39_5", - "PSS_IMUX_B39_6", - "PSS_IMUX_B39_7", - "PSS_IMUX_B39_8", - "PSS_IMUX_B39_9", - "PSS_IMUX_B3_0", - "PSS_IMUX_B3_1", - "PSS_IMUX_B3_10", - "PSS_IMUX_B3_11", - "PSS_IMUX_B3_12", - "PSS_IMUX_B3_13", - "PSS_IMUX_B3_14", - "PSS_IMUX_B3_15", - "PSS_IMUX_B3_16", - "PSS_IMUX_B3_17", - "PSS_IMUX_B3_18", - "PSS_IMUX_B3_19", - "PSS_IMUX_B3_2", - "PSS_IMUX_B3_3", - "PSS_IMUX_B3_4", - "PSS_IMUX_B3_5", - "PSS_IMUX_B3_6", - "PSS_IMUX_B3_7", - "PSS_IMUX_B3_8", - "PSS_IMUX_B3_9", - "PSS_IMUX_B40_0", - "PSS_IMUX_B40_1", - "PSS_IMUX_B40_10", - "PSS_IMUX_B40_11", - "PSS_IMUX_B40_12", - "PSS_IMUX_B40_13", - "PSS_IMUX_B40_14", - "PSS_IMUX_B40_15", - "PSS_IMUX_B40_16", - "PSS_IMUX_B40_17", - "PSS_IMUX_B40_18", - "PSS_IMUX_B40_19", - "PSS_IMUX_B40_2", - "PSS_IMUX_B40_3", - "PSS_IMUX_B40_4", - "PSS_IMUX_B40_5", - "PSS_IMUX_B40_6", - "PSS_IMUX_B40_7", - "PSS_IMUX_B40_8", - "PSS_IMUX_B40_9", - "PSS_IMUX_B41_0", - "PSS_IMUX_B41_1", - "PSS_IMUX_B41_10", - "PSS_IMUX_B41_11", - "PSS_IMUX_B41_12", - "PSS_IMUX_B41_13", - "PSS_IMUX_B41_14", - "PSS_IMUX_B41_15", - "PSS_IMUX_B41_16", - "PSS_IMUX_B41_17", - "PSS_IMUX_B41_18", - "PSS_IMUX_B41_19", - "PSS_IMUX_B41_2", - "PSS_IMUX_B41_3", - "PSS_IMUX_B41_4", - "PSS_IMUX_B41_5", - "PSS_IMUX_B41_6", - "PSS_IMUX_B41_7", - "PSS_IMUX_B41_8", - "PSS_IMUX_B41_9", - "PSS_IMUX_B42_0", - "PSS_IMUX_B42_1", - "PSS_IMUX_B42_10", - "PSS_IMUX_B42_11", - "PSS_IMUX_B42_12", - "PSS_IMUX_B42_13", - "PSS_IMUX_B42_14", - "PSS_IMUX_B42_15", - "PSS_IMUX_B42_16", - "PSS_IMUX_B42_17", - "PSS_IMUX_B42_18", - "PSS_IMUX_B42_19", - "PSS_IMUX_B42_2", - "PSS_IMUX_B42_3", - "PSS_IMUX_B42_4", - "PSS_IMUX_B42_5", - "PSS_IMUX_B42_6", - "PSS_IMUX_B42_7", - "PSS_IMUX_B42_8", - "PSS_IMUX_B42_9", - "PSS_IMUX_B43_0", - "PSS_IMUX_B43_1", - "PSS_IMUX_B43_10", - "PSS_IMUX_B43_11", - "PSS_IMUX_B43_12", - "PSS_IMUX_B43_13", - "PSS_IMUX_B43_14", - "PSS_IMUX_B43_15", - "PSS_IMUX_B43_16", - "PSS_IMUX_B43_17", - "PSS_IMUX_B43_18", - "PSS_IMUX_B43_19", - "PSS_IMUX_B43_2", - "PSS_IMUX_B43_3", - "PSS_IMUX_B43_4", - "PSS_IMUX_B43_5", - "PSS_IMUX_B43_6", - "PSS_IMUX_B43_7", - "PSS_IMUX_B43_8", - "PSS_IMUX_B43_9", - "PSS_IMUX_B44_0", - "PSS_IMUX_B44_1", - "PSS_IMUX_B44_10", - "PSS_IMUX_B44_11", - "PSS_IMUX_B44_12", - "PSS_IMUX_B44_13", - "PSS_IMUX_B44_14", - "PSS_IMUX_B44_15", - "PSS_IMUX_B44_16", - "PSS_IMUX_B44_17", - "PSS_IMUX_B44_18", - "PSS_IMUX_B44_19", - "PSS_IMUX_B44_2", - "PSS_IMUX_B44_3", - "PSS_IMUX_B44_4", - "PSS_IMUX_B44_5", - "PSS_IMUX_B44_6", - "PSS_IMUX_B44_7", - "PSS_IMUX_B44_8", - "PSS_IMUX_B44_9", - "PSS_IMUX_B45_0", - "PSS_IMUX_B45_1", - "PSS_IMUX_B45_10", - "PSS_IMUX_B45_11", - "PSS_IMUX_B45_12", - "PSS_IMUX_B45_13", - "PSS_IMUX_B45_14", - "PSS_IMUX_B45_15", - "PSS_IMUX_B45_16", - "PSS_IMUX_B45_17", - "PSS_IMUX_B45_18", - "PSS_IMUX_B45_19", - "PSS_IMUX_B45_2", - "PSS_IMUX_B45_3", - "PSS_IMUX_B45_4", - "PSS_IMUX_B45_5", - "PSS_IMUX_B45_6", - "PSS_IMUX_B45_7", - "PSS_IMUX_B45_8", - "PSS_IMUX_B45_9", - "PSS_IMUX_B46_0", - "PSS_IMUX_B46_1", - "PSS_IMUX_B46_10", - "PSS_IMUX_B46_11", - "PSS_IMUX_B46_12", - "PSS_IMUX_B46_13", - "PSS_IMUX_B46_14", - "PSS_IMUX_B46_15", - "PSS_IMUX_B46_16", - "PSS_IMUX_B46_17", - "PSS_IMUX_B46_18", - "PSS_IMUX_B46_19", - "PSS_IMUX_B46_2", - "PSS_IMUX_B46_3", - "PSS_IMUX_B46_4", - "PSS_IMUX_B46_5", - "PSS_IMUX_B46_6", - "PSS_IMUX_B46_7", - "PSS_IMUX_B46_8", - "PSS_IMUX_B46_9", - "PSS_IMUX_B47_0", - "PSS_IMUX_B47_1", - "PSS_IMUX_B47_10", - "PSS_IMUX_B47_11", - "PSS_IMUX_B47_12", - "PSS_IMUX_B47_13", - "PSS_IMUX_B47_14", - "PSS_IMUX_B47_15", - "PSS_IMUX_B47_16", - "PSS_IMUX_B47_17", - "PSS_IMUX_B47_18", - "PSS_IMUX_B47_19", - "PSS_IMUX_B47_2", - "PSS_IMUX_B47_3", - "PSS_IMUX_B47_4", - "PSS_IMUX_B47_5", - "PSS_IMUX_B47_6", - "PSS_IMUX_B47_7", - "PSS_IMUX_B47_8", - "PSS_IMUX_B47_9", - "PSS_IMUX_B4_0", - "PSS_IMUX_B4_1", - "PSS_IMUX_B4_10", - "PSS_IMUX_B4_11", - "PSS_IMUX_B4_12", - "PSS_IMUX_B4_13", - "PSS_IMUX_B4_14", - "PSS_IMUX_B4_15", - "PSS_IMUX_B4_16", - "PSS_IMUX_B4_17", - "PSS_IMUX_B4_18", - "PSS_IMUX_B4_19", - "PSS_IMUX_B4_2", - "PSS_IMUX_B4_3", - "PSS_IMUX_B4_4", - "PSS_IMUX_B4_5", - "PSS_IMUX_B4_6", - "PSS_IMUX_B4_7", - "PSS_IMUX_B4_8", - "PSS_IMUX_B4_9", - "PSS_IMUX_B5_0", - "PSS_IMUX_B5_1", - "PSS_IMUX_B5_10", - "PSS_IMUX_B5_11", - "PSS_IMUX_B5_12", - "PSS_IMUX_B5_13", - "PSS_IMUX_B5_14", - "PSS_IMUX_B5_15", - "PSS_IMUX_B5_16", - "PSS_IMUX_B5_17", - "PSS_IMUX_B5_18", - "PSS_IMUX_B5_19", - "PSS_IMUX_B5_2", - "PSS_IMUX_B5_3", - "PSS_IMUX_B5_4", - "PSS_IMUX_B5_5", - "PSS_IMUX_B5_6", - "PSS_IMUX_B5_7", - "PSS_IMUX_B5_8", - "PSS_IMUX_B5_9", - "PSS_IMUX_B6_0", - "PSS_IMUX_B6_1", - "PSS_IMUX_B6_10", - "PSS_IMUX_B6_11", - "PSS_IMUX_B6_12", - "PSS_IMUX_B6_13", - "PSS_IMUX_B6_14", - "PSS_IMUX_B6_15", - "PSS_IMUX_B6_16", - "PSS_IMUX_B6_17", - "PSS_IMUX_B6_18", - "PSS_IMUX_B6_19", - "PSS_IMUX_B6_2", - "PSS_IMUX_B6_3", - "PSS_IMUX_B6_4", - "PSS_IMUX_B6_5", - "PSS_IMUX_B6_6", - "PSS_IMUX_B6_7", - "PSS_IMUX_B6_8", - "PSS_IMUX_B6_9", - "PSS_IMUX_B7_0", - "PSS_IMUX_B7_1", - "PSS_IMUX_B7_10", - "PSS_IMUX_B7_11", - "PSS_IMUX_B7_12", - "PSS_IMUX_B7_13", - "PSS_IMUX_B7_14", - "PSS_IMUX_B7_15", - "PSS_IMUX_B7_16", - "PSS_IMUX_B7_17", - "PSS_IMUX_B7_18", - "PSS_IMUX_B7_19", - "PSS_IMUX_B7_2", - "PSS_IMUX_B7_3", - "PSS_IMUX_B7_4", - "PSS_IMUX_B7_5", - "PSS_IMUX_B7_6", - "PSS_IMUX_B7_7", - "PSS_IMUX_B7_8", - "PSS_IMUX_B7_9", - "PSS_IMUX_B8_0", - "PSS_IMUX_B8_1", - "PSS_IMUX_B8_10", - "PSS_IMUX_B8_11", - "PSS_IMUX_B8_12", - "PSS_IMUX_B8_13", - "PSS_IMUX_B8_14", - "PSS_IMUX_B8_15", - "PSS_IMUX_B8_16", - "PSS_IMUX_B8_17", - "PSS_IMUX_B8_18", - "PSS_IMUX_B8_19", - "PSS_IMUX_B8_2", - "PSS_IMUX_B8_3", - "PSS_IMUX_B8_4", - "PSS_IMUX_B8_5", - "PSS_IMUX_B8_6", - "PSS_IMUX_B8_7", - "PSS_IMUX_B8_8", - "PSS_IMUX_B8_9", - "PSS_IMUX_B9_0", - "PSS_IMUX_B9_1", - "PSS_IMUX_B9_10", - "PSS_IMUX_B9_11", - "PSS_IMUX_B9_12", - "PSS_IMUX_B9_13", - "PSS_IMUX_B9_14", - "PSS_IMUX_B9_15", - "PSS_IMUX_B9_16", - "PSS_IMUX_B9_17", - "PSS_IMUX_B9_18", - "PSS_IMUX_B9_19", - "PSS_IMUX_B9_2", - "PSS_IMUX_B9_3", - "PSS_IMUX_B9_4", - "PSS_IMUX_B9_5", - "PSS_IMUX_B9_6", - "PSS_IMUX_B9_7", - "PSS_IMUX_B9_8", - "PSS_IMUX_B9_9", - "PSS_LOGIC_OUTS0_0", - "PSS_LOGIC_OUTS0_1", - "PSS_LOGIC_OUTS0_10", - "PSS_LOGIC_OUTS0_11", - "PSS_LOGIC_OUTS0_12", - "PSS_LOGIC_OUTS0_13", - "PSS_LOGIC_OUTS0_14", - "PSS_LOGIC_OUTS0_15", - "PSS_LOGIC_OUTS0_16", - "PSS_LOGIC_OUTS0_17", - "PSS_LOGIC_OUTS0_18", - "PSS_LOGIC_OUTS0_19", - "PSS_LOGIC_OUTS0_2", - "PSS_LOGIC_OUTS0_3", - "PSS_LOGIC_OUTS0_4", - "PSS_LOGIC_OUTS0_5", - "PSS_LOGIC_OUTS0_6", - "PSS_LOGIC_OUTS0_7", - "PSS_LOGIC_OUTS0_8", - "PSS_LOGIC_OUTS0_9", - "PSS_LOGIC_OUTS10_0", - "PSS_LOGIC_OUTS10_1", - "PSS_LOGIC_OUTS10_10", - "PSS_LOGIC_OUTS10_11", - "PSS_LOGIC_OUTS10_12", - "PSS_LOGIC_OUTS10_13", - "PSS_LOGIC_OUTS10_14", - "PSS_LOGIC_OUTS10_15", - "PSS_LOGIC_OUTS10_16", - "PSS_LOGIC_OUTS10_17", - "PSS_LOGIC_OUTS10_18", - "PSS_LOGIC_OUTS10_19", - "PSS_LOGIC_OUTS10_2", - "PSS_LOGIC_OUTS10_3", - "PSS_LOGIC_OUTS10_4", - "PSS_LOGIC_OUTS10_5", - "PSS_LOGIC_OUTS10_6", - "PSS_LOGIC_OUTS10_7", - "PSS_LOGIC_OUTS10_8", - "PSS_LOGIC_OUTS10_9", - "PSS_LOGIC_OUTS11_0", - "PSS_LOGIC_OUTS11_1", - "PSS_LOGIC_OUTS11_10", - "PSS_LOGIC_OUTS11_11", - "PSS_LOGIC_OUTS11_12", - "PSS_LOGIC_OUTS11_13", - "PSS_LOGIC_OUTS11_14", - "PSS_LOGIC_OUTS11_15", - "PSS_LOGIC_OUTS11_16", - "PSS_LOGIC_OUTS11_17", - "PSS_LOGIC_OUTS11_18", - "PSS_LOGIC_OUTS11_19", - "PSS_LOGIC_OUTS11_2", - "PSS_LOGIC_OUTS11_3", - "PSS_LOGIC_OUTS11_4", - "PSS_LOGIC_OUTS11_5", - "PSS_LOGIC_OUTS11_6", - "PSS_LOGIC_OUTS11_7", - "PSS_LOGIC_OUTS11_8", - "PSS_LOGIC_OUTS11_9", - "PSS_LOGIC_OUTS12_0", - "PSS_LOGIC_OUTS12_1", - "PSS_LOGIC_OUTS12_10", - "PSS_LOGIC_OUTS12_11", - "PSS_LOGIC_OUTS12_12", - "PSS_LOGIC_OUTS12_13", - "PSS_LOGIC_OUTS12_14", - "PSS_LOGIC_OUTS12_15", - "PSS_LOGIC_OUTS12_16", - "PSS_LOGIC_OUTS12_17", - "PSS_LOGIC_OUTS12_18", - "PSS_LOGIC_OUTS12_19", - "PSS_LOGIC_OUTS12_2", - "PSS_LOGIC_OUTS12_3", - "PSS_LOGIC_OUTS12_4", - "PSS_LOGIC_OUTS12_5", - "PSS_LOGIC_OUTS12_6", - "PSS_LOGIC_OUTS12_7", - "PSS_LOGIC_OUTS12_8", - "PSS_LOGIC_OUTS12_9", - "PSS_LOGIC_OUTS13_0", - "PSS_LOGIC_OUTS13_1", - "PSS_LOGIC_OUTS13_10", - "PSS_LOGIC_OUTS13_11", - "PSS_LOGIC_OUTS13_12", - "PSS_LOGIC_OUTS13_13", - "PSS_LOGIC_OUTS13_14", - "PSS_LOGIC_OUTS13_15", - "PSS_LOGIC_OUTS13_16", - "PSS_LOGIC_OUTS13_17", - "PSS_LOGIC_OUTS13_18", - "PSS_LOGIC_OUTS13_19", - "PSS_LOGIC_OUTS13_2", - "PSS_LOGIC_OUTS13_3", - "PSS_LOGIC_OUTS13_4", - "PSS_LOGIC_OUTS13_5", - "PSS_LOGIC_OUTS13_6", - "PSS_LOGIC_OUTS13_7", - "PSS_LOGIC_OUTS13_8", - "PSS_LOGIC_OUTS13_9", - "PSS_LOGIC_OUTS14_0", - "PSS_LOGIC_OUTS14_1", - "PSS_LOGIC_OUTS14_10", - "PSS_LOGIC_OUTS14_11", - "PSS_LOGIC_OUTS14_12", - "PSS_LOGIC_OUTS14_13", - "PSS_LOGIC_OUTS14_14", - "PSS_LOGIC_OUTS14_15", - "PSS_LOGIC_OUTS14_16", - "PSS_LOGIC_OUTS14_17", - "PSS_LOGIC_OUTS14_18", - "PSS_LOGIC_OUTS14_19", - "PSS_LOGIC_OUTS14_2", - "PSS_LOGIC_OUTS14_3", - "PSS_LOGIC_OUTS14_4", - "PSS_LOGIC_OUTS14_5", - "PSS_LOGIC_OUTS14_6", - "PSS_LOGIC_OUTS14_7", - "PSS_LOGIC_OUTS14_8", - "PSS_LOGIC_OUTS14_9", - "PSS_LOGIC_OUTS15_0", - "PSS_LOGIC_OUTS15_1", - "PSS_LOGIC_OUTS15_10", - "PSS_LOGIC_OUTS15_11", - "PSS_LOGIC_OUTS15_12", - "PSS_LOGIC_OUTS15_13", - "PSS_LOGIC_OUTS15_14", - "PSS_LOGIC_OUTS15_15", - "PSS_LOGIC_OUTS15_16", - "PSS_LOGIC_OUTS15_17", - "PSS_LOGIC_OUTS15_18", - "PSS_LOGIC_OUTS15_19", - "PSS_LOGIC_OUTS15_2", - "PSS_LOGIC_OUTS15_3", - "PSS_LOGIC_OUTS15_4", - "PSS_LOGIC_OUTS15_5", - "PSS_LOGIC_OUTS15_6", - "PSS_LOGIC_OUTS15_7", - "PSS_LOGIC_OUTS15_8", - "PSS_LOGIC_OUTS15_9", - "PSS_LOGIC_OUTS16_0", - "PSS_LOGIC_OUTS16_1", - "PSS_LOGIC_OUTS16_10", - "PSS_LOGIC_OUTS16_11", - "PSS_LOGIC_OUTS16_12", - "PSS_LOGIC_OUTS16_13", - "PSS_LOGIC_OUTS16_14", - "PSS_LOGIC_OUTS16_15", - "PSS_LOGIC_OUTS16_16", - "PSS_LOGIC_OUTS16_17", - "PSS_LOGIC_OUTS16_18", - "PSS_LOGIC_OUTS16_19", - "PSS_LOGIC_OUTS16_2", - "PSS_LOGIC_OUTS16_3", - "PSS_LOGIC_OUTS16_4", - "PSS_LOGIC_OUTS16_5", - "PSS_LOGIC_OUTS16_6", - "PSS_LOGIC_OUTS16_7", - "PSS_LOGIC_OUTS16_8", - "PSS_LOGIC_OUTS16_9", - "PSS_LOGIC_OUTS17_0", - "PSS_LOGIC_OUTS17_1", - "PSS_LOGIC_OUTS17_10", - "PSS_LOGIC_OUTS17_11", - "PSS_LOGIC_OUTS17_12", - "PSS_LOGIC_OUTS17_13", - "PSS_LOGIC_OUTS17_14", - "PSS_LOGIC_OUTS17_15", - "PSS_LOGIC_OUTS17_16", - "PSS_LOGIC_OUTS17_17", - "PSS_LOGIC_OUTS17_18", - "PSS_LOGIC_OUTS17_19", - "PSS_LOGIC_OUTS17_2", - "PSS_LOGIC_OUTS17_3", - "PSS_LOGIC_OUTS17_4", - "PSS_LOGIC_OUTS17_5", - "PSS_LOGIC_OUTS17_6", - "PSS_LOGIC_OUTS17_7", - "PSS_LOGIC_OUTS17_8", - "PSS_LOGIC_OUTS17_9", - "PSS_LOGIC_OUTS18_0", - "PSS_LOGIC_OUTS18_1", - "PSS_LOGIC_OUTS18_10", - "PSS_LOGIC_OUTS18_11", - "PSS_LOGIC_OUTS18_12", - "PSS_LOGIC_OUTS18_13", - "PSS_LOGIC_OUTS18_14", - "PSS_LOGIC_OUTS18_15", - "PSS_LOGIC_OUTS18_16", - "PSS_LOGIC_OUTS18_17", - "PSS_LOGIC_OUTS18_18", - "PSS_LOGIC_OUTS18_19", - "PSS_LOGIC_OUTS18_2", - "PSS_LOGIC_OUTS18_3", - "PSS_LOGIC_OUTS18_4", - "PSS_LOGIC_OUTS18_5", - "PSS_LOGIC_OUTS18_6", - "PSS_LOGIC_OUTS18_7", - "PSS_LOGIC_OUTS18_8", - "PSS_LOGIC_OUTS18_9", - "PSS_LOGIC_OUTS19_0", - "PSS_LOGIC_OUTS19_1", - "PSS_LOGIC_OUTS19_10", - "PSS_LOGIC_OUTS19_11", - "PSS_LOGIC_OUTS19_12", - "PSS_LOGIC_OUTS19_13", - "PSS_LOGIC_OUTS19_14", - "PSS_LOGIC_OUTS19_15", - "PSS_LOGIC_OUTS19_16", - "PSS_LOGIC_OUTS19_17", - "PSS_LOGIC_OUTS19_18", - "PSS_LOGIC_OUTS19_19", - "PSS_LOGIC_OUTS19_2", - "PSS_LOGIC_OUTS19_3", - "PSS_LOGIC_OUTS19_4", - "PSS_LOGIC_OUTS19_5", - "PSS_LOGIC_OUTS19_6", - "PSS_LOGIC_OUTS19_7", - "PSS_LOGIC_OUTS19_8", - "PSS_LOGIC_OUTS19_9", - "PSS_LOGIC_OUTS1_0", - "PSS_LOGIC_OUTS1_1", - "PSS_LOGIC_OUTS1_10", - "PSS_LOGIC_OUTS1_11", - "PSS_LOGIC_OUTS1_12", - "PSS_LOGIC_OUTS1_13", - "PSS_LOGIC_OUTS1_14", - "PSS_LOGIC_OUTS1_15", - "PSS_LOGIC_OUTS1_16", - "PSS_LOGIC_OUTS1_17", - "PSS_LOGIC_OUTS1_18", - "PSS_LOGIC_OUTS1_19", - "PSS_LOGIC_OUTS1_2", - "PSS_LOGIC_OUTS1_3", - "PSS_LOGIC_OUTS1_4", - "PSS_LOGIC_OUTS1_5", - "PSS_LOGIC_OUTS1_6", - "PSS_LOGIC_OUTS1_7", - "PSS_LOGIC_OUTS1_8", - "PSS_LOGIC_OUTS1_9", - "PSS_LOGIC_OUTS20_0", - "PSS_LOGIC_OUTS20_1", - "PSS_LOGIC_OUTS20_10", - "PSS_LOGIC_OUTS20_11", - "PSS_LOGIC_OUTS20_12", - "PSS_LOGIC_OUTS20_13", - "PSS_LOGIC_OUTS20_14", - "PSS_LOGIC_OUTS20_15", - "PSS_LOGIC_OUTS20_16", - "PSS_LOGIC_OUTS20_17", - "PSS_LOGIC_OUTS20_18", - "PSS_LOGIC_OUTS20_19", - "PSS_LOGIC_OUTS20_2", - "PSS_LOGIC_OUTS20_3", - "PSS_LOGIC_OUTS20_4", - "PSS_LOGIC_OUTS20_5", - "PSS_LOGIC_OUTS20_6", - "PSS_LOGIC_OUTS20_7", - "PSS_LOGIC_OUTS20_8", - "PSS_LOGIC_OUTS20_9", - "PSS_LOGIC_OUTS21_0", - "PSS_LOGIC_OUTS21_1", - "PSS_LOGIC_OUTS21_10", - "PSS_LOGIC_OUTS21_11", - "PSS_LOGIC_OUTS21_12", - "PSS_LOGIC_OUTS21_13", - "PSS_LOGIC_OUTS21_14", - "PSS_LOGIC_OUTS21_15", - "PSS_LOGIC_OUTS21_16", - "PSS_LOGIC_OUTS21_17", - "PSS_LOGIC_OUTS21_18", - "PSS_LOGIC_OUTS21_19", - "PSS_LOGIC_OUTS21_2", - "PSS_LOGIC_OUTS21_3", - "PSS_LOGIC_OUTS21_4", - "PSS_LOGIC_OUTS21_5", - "PSS_LOGIC_OUTS21_6", - "PSS_LOGIC_OUTS21_7", - "PSS_LOGIC_OUTS21_8", - "PSS_LOGIC_OUTS21_9", - "PSS_LOGIC_OUTS22_0", - "PSS_LOGIC_OUTS22_1", - "PSS_LOGIC_OUTS22_10", - "PSS_LOGIC_OUTS22_11", - "PSS_LOGIC_OUTS22_12", - "PSS_LOGIC_OUTS22_13", - "PSS_LOGIC_OUTS22_14", - "PSS_LOGIC_OUTS22_15", - "PSS_LOGIC_OUTS22_16", - "PSS_LOGIC_OUTS22_17", - "PSS_LOGIC_OUTS22_18", - "PSS_LOGIC_OUTS22_19", - "PSS_LOGIC_OUTS22_2", - "PSS_LOGIC_OUTS22_3", - "PSS_LOGIC_OUTS22_4", - "PSS_LOGIC_OUTS22_5", - "PSS_LOGIC_OUTS22_6", - "PSS_LOGIC_OUTS22_7", - "PSS_LOGIC_OUTS22_8", - "PSS_LOGIC_OUTS22_9", - "PSS_LOGIC_OUTS23_0", - "PSS_LOGIC_OUTS23_1", - "PSS_LOGIC_OUTS23_10", - "PSS_LOGIC_OUTS23_11", - "PSS_LOGIC_OUTS23_12", - "PSS_LOGIC_OUTS23_13", - "PSS_LOGIC_OUTS23_14", - "PSS_LOGIC_OUTS23_15", - "PSS_LOGIC_OUTS23_16", - "PSS_LOGIC_OUTS23_17", - "PSS_LOGIC_OUTS23_18", - "PSS_LOGIC_OUTS23_19", - "PSS_LOGIC_OUTS23_2", - "PSS_LOGIC_OUTS23_3", - "PSS_LOGIC_OUTS23_4", - "PSS_LOGIC_OUTS23_5", - "PSS_LOGIC_OUTS23_6", - "PSS_LOGIC_OUTS23_7", - "PSS_LOGIC_OUTS23_8", - "PSS_LOGIC_OUTS23_9", - "PSS_LOGIC_OUTS2_0", - "PSS_LOGIC_OUTS2_1", - "PSS_LOGIC_OUTS2_10", - "PSS_LOGIC_OUTS2_11", - "PSS_LOGIC_OUTS2_12", - "PSS_LOGIC_OUTS2_13", - "PSS_LOGIC_OUTS2_14", - "PSS_LOGIC_OUTS2_15", - "PSS_LOGIC_OUTS2_16", - "PSS_LOGIC_OUTS2_17", - "PSS_LOGIC_OUTS2_18", - "PSS_LOGIC_OUTS2_19", - "PSS_LOGIC_OUTS2_2", - "PSS_LOGIC_OUTS2_3", - "PSS_LOGIC_OUTS2_4", - "PSS_LOGIC_OUTS2_5", - "PSS_LOGIC_OUTS2_6", - "PSS_LOGIC_OUTS2_7", - "PSS_LOGIC_OUTS2_8", - "PSS_LOGIC_OUTS2_9", - "PSS_LOGIC_OUTS3_0", - "PSS_LOGIC_OUTS3_1", - "PSS_LOGIC_OUTS3_10", - "PSS_LOGIC_OUTS3_11", - "PSS_LOGIC_OUTS3_12", - "PSS_LOGIC_OUTS3_13", - "PSS_LOGIC_OUTS3_14", - "PSS_LOGIC_OUTS3_15", - "PSS_LOGIC_OUTS3_16", - "PSS_LOGIC_OUTS3_17", - "PSS_LOGIC_OUTS3_18", - "PSS_LOGIC_OUTS3_19", - "PSS_LOGIC_OUTS3_2", - "PSS_LOGIC_OUTS3_3", - "PSS_LOGIC_OUTS3_4", - "PSS_LOGIC_OUTS3_5", - "PSS_LOGIC_OUTS3_6", - "PSS_LOGIC_OUTS3_7", - "PSS_LOGIC_OUTS3_8", - "PSS_LOGIC_OUTS3_9", - "PSS_LOGIC_OUTS4_0", - "PSS_LOGIC_OUTS4_1", - "PSS_LOGIC_OUTS4_10", - "PSS_LOGIC_OUTS4_11", - "PSS_LOGIC_OUTS4_12", - "PSS_LOGIC_OUTS4_13", - "PSS_LOGIC_OUTS4_14", - "PSS_LOGIC_OUTS4_15", - "PSS_LOGIC_OUTS4_16", - "PSS_LOGIC_OUTS4_17", - "PSS_LOGIC_OUTS4_18", - "PSS_LOGIC_OUTS4_19", - "PSS_LOGIC_OUTS4_2", - "PSS_LOGIC_OUTS4_3", - "PSS_LOGIC_OUTS4_4", - "PSS_LOGIC_OUTS4_5", - "PSS_LOGIC_OUTS4_6", - "PSS_LOGIC_OUTS4_7", - "PSS_LOGIC_OUTS4_8", - "PSS_LOGIC_OUTS4_9", - "PSS_LOGIC_OUTS5_0", - "PSS_LOGIC_OUTS5_1", - "PSS_LOGIC_OUTS5_10", - "PSS_LOGIC_OUTS5_11", - "PSS_LOGIC_OUTS5_12", - "PSS_LOGIC_OUTS5_13", - "PSS_LOGIC_OUTS5_14", - "PSS_LOGIC_OUTS5_15", - "PSS_LOGIC_OUTS5_16", - "PSS_LOGIC_OUTS5_17", - "PSS_LOGIC_OUTS5_18", - "PSS_LOGIC_OUTS5_19", - "PSS_LOGIC_OUTS5_2", - "PSS_LOGIC_OUTS5_3", - "PSS_LOGIC_OUTS5_4", - "PSS_LOGIC_OUTS5_5", - "PSS_LOGIC_OUTS5_6", - "PSS_LOGIC_OUTS5_7", - "PSS_LOGIC_OUTS5_8", - "PSS_LOGIC_OUTS5_9", - "PSS_LOGIC_OUTS6_0", - "PSS_LOGIC_OUTS6_1", - "PSS_LOGIC_OUTS6_10", - "PSS_LOGIC_OUTS6_11", - "PSS_LOGIC_OUTS6_12", - "PSS_LOGIC_OUTS6_13", - "PSS_LOGIC_OUTS6_14", - "PSS_LOGIC_OUTS6_15", - "PSS_LOGIC_OUTS6_16", - "PSS_LOGIC_OUTS6_17", - "PSS_LOGIC_OUTS6_18", - "PSS_LOGIC_OUTS6_19", - "PSS_LOGIC_OUTS6_2", - "PSS_LOGIC_OUTS6_3", - "PSS_LOGIC_OUTS6_4", - "PSS_LOGIC_OUTS6_5", - "PSS_LOGIC_OUTS6_6", - "PSS_LOGIC_OUTS6_7", - "PSS_LOGIC_OUTS6_8", - "PSS_LOGIC_OUTS6_9", - "PSS_LOGIC_OUTS7_0", - "PSS_LOGIC_OUTS7_1", - "PSS_LOGIC_OUTS7_10", - "PSS_LOGIC_OUTS7_11", - "PSS_LOGIC_OUTS7_12", - "PSS_LOGIC_OUTS7_13", - "PSS_LOGIC_OUTS7_14", - "PSS_LOGIC_OUTS7_15", - "PSS_LOGIC_OUTS7_16", - "PSS_LOGIC_OUTS7_17", - "PSS_LOGIC_OUTS7_18", - "PSS_LOGIC_OUTS7_19", - "PSS_LOGIC_OUTS7_2", - "PSS_LOGIC_OUTS7_3", - "PSS_LOGIC_OUTS7_4", - "PSS_LOGIC_OUTS7_5", - "PSS_LOGIC_OUTS7_6", - "PSS_LOGIC_OUTS7_7", - "PSS_LOGIC_OUTS7_8", - "PSS_LOGIC_OUTS7_9", - "PSS_LOGIC_OUTS8_0", - "PSS_LOGIC_OUTS8_1", - "PSS_LOGIC_OUTS8_10", - "PSS_LOGIC_OUTS8_11", - "PSS_LOGIC_OUTS8_12", - "PSS_LOGIC_OUTS8_13", - "PSS_LOGIC_OUTS8_14", - "PSS_LOGIC_OUTS8_15", - "PSS_LOGIC_OUTS8_16", - "PSS_LOGIC_OUTS8_17", - "PSS_LOGIC_OUTS8_18", - "PSS_LOGIC_OUTS8_19", - "PSS_LOGIC_OUTS8_2", - "PSS_LOGIC_OUTS8_3", - "PSS_LOGIC_OUTS8_4", - "PSS_LOGIC_OUTS8_5", - "PSS_LOGIC_OUTS8_6", - "PSS_LOGIC_OUTS8_7", - "PSS_LOGIC_OUTS8_8", - "PSS_LOGIC_OUTS8_9", - "PSS_LOGIC_OUTS9_0", - "PSS_LOGIC_OUTS9_1", - "PSS_LOGIC_OUTS9_10", - "PSS_LOGIC_OUTS9_11", - "PSS_LOGIC_OUTS9_12", - "PSS_LOGIC_OUTS9_13", - "PSS_LOGIC_OUTS9_14", - "PSS_LOGIC_OUTS9_15", - "PSS_LOGIC_OUTS9_16", - "PSS_LOGIC_OUTS9_17", - "PSS_LOGIC_OUTS9_18", - "PSS_LOGIC_OUTS9_19", - "PSS_LOGIC_OUTS9_2", - "PSS_LOGIC_OUTS9_3", - "PSS_LOGIC_OUTS9_4", - "PSS_LOGIC_OUTS9_5", - "PSS_LOGIC_OUTS9_6", - "PSS_LOGIC_OUTS9_7", - "PSS_LOGIC_OUTS9_8", - "PSS_LOGIC_OUTS9_9" - ] + "wires": { + "PSS0_CLK_B0_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B1_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_IMUX_B0_4": { + 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"10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS6_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS7_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS8_9": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_18": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_19": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_2": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_3": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_4": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_5": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_6": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_7": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_8": { + "cap": "10.823", + "res": "0.000" + }, + "PSS_LOGIC_OUTS9_9": { + "cap": "10.823", + "res": "0.000" + } + } } diff --git a/zynq7/tile_type_PSS4.json b/zynq7/tile_type_PSS4.json index 8d542c2..c5341d8 100644 --- a/zynq7/tile_type_PSS4.json +++ b/zynq7/tile_type_PSS4.json @@ -2,13687 +2,39927 @@ "pips": { "PSS4.PSS0_LOGIC_OUTS0_0->PSS_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_0" }, "PSS4.PSS0_LOGIC_OUTS0_1->PSS_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_1" }, "PSS4.PSS0_LOGIC_OUTS0_10->PSS_LOGIC_OUTS0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_10" }, "PSS4.PSS0_LOGIC_OUTS0_11->PSS_LOGIC_OUTS0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_11" }, "PSS4.PSS0_LOGIC_OUTS0_12->PSS_LOGIC_OUTS0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_12" }, "PSS4.PSS0_LOGIC_OUTS0_13->PSS_LOGIC_OUTS0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_13" }, "PSS4.PSS0_LOGIC_OUTS0_14->PSS_LOGIC_OUTS0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_14" }, "PSS4.PSS0_LOGIC_OUTS0_15->PSS_LOGIC_OUTS0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_15" }, "PSS4.PSS0_LOGIC_OUTS0_16->PSS_LOGIC_OUTS0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_16" }, "PSS4.PSS0_LOGIC_OUTS0_17->PSS_LOGIC_OUTS0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_17" }, "PSS4.PSS0_LOGIC_OUTS0_18->PSS_LOGIC_OUTS0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_18" }, "PSS4.PSS0_LOGIC_OUTS0_19->PSS_LOGIC_OUTS0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_19" }, "PSS4.PSS0_LOGIC_OUTS0_2->PSS_LOGIC_OUTS0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_2" }, "PSS4.PSS0_LOGIC_OUTS0_3->PSS_LOGIC_OUTS0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_3" }, "PSS4.PSS0_LOGIC_OUTS0_4->PSS_LOGIC_OUTS0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_4" }, "PSS4.PSS0_LOGIC_OUTS0_5->PSS_LOGIC_OUTS0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_5" }, "PSS4.PSS0_LOGIC_OUTS0_6->PSS_LOGIC_OUTS0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_6" }, "PSS4.PSS0_LOGIC_OUTS0_7->PSS_LOGIC_OUTS0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_7" }, "PSS4.PSS0_LOGIC_OUTS0_8->PSS_LOGIC_OUTS0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_8" }, "PSS4.PSS0_LOGIC_OUTS0_9->PSS_LOGIC_OUTS0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS0_9" }, "PSS4.PSS0_LOGIC_OUTS10_0->PSS_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_0" }, "PSS4.PSS0_LOGIC_OUTS10_1->PSS_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_1" }, "PSS4.PSS0_LOGIC_OUTS10_10->PSS_LOGIC_OUTS10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_10" }, "PSS4.PSS0_LOGIC_OUTS10_11->PSS_LOGIC_OUTS10_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_11" }, "PSS4.PSS0_LOGIC_OUTS10_12->PSS_LOGIC_OUTS10_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_12" }, 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"delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_15" }, "PSS4.PSS0_LOGIC_OUTS10_16->PSS_LOGIC_OUTS10_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_16" }, "PSS4.PSS0_LOGIC_OUTS10_17->PSS_LOGIC_OUTS10_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_17" }, "PSS4.PSS0_LOGIC_OUTS10_18->PSS_LOGIC_OUTS10_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_18", 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null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_3" }, "PSS4.PSS0_LOGIC_OUTS10_4->PSS_LOGIC_OUTS10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_4" }, "PSS4.PSS0_LOGIC_OUTS10_5->PSS_LOGIC_OUTS10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_5" }, 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"in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_8" }, "PSS4.PSS0_LOGIC_OUTS10_9->PSS_LOGIC_OUTS10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS10_9" }, "PSS4.PSS0_LOGIC_OUTS11_0->PSS_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_0" }, "PSS4.PSS0_LOGIC_OUTS11_1->PSS_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_1" }, "PSS4.PSS0_LOGIC_OUTS11_10->PSS_LOGIC_OUTS11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_10" }, "PSS4.PSS0_LOGIC_OUTS11_11->PSS_LOGIC_OUTS11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_11" }, "PSS4.PSS0_LOGIC_OUTS11_12->PSS_LOGIC_OUTS11_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_12" }, "PSS4.PSS0_LOGIC_OUTS11_13->PSS_LOGIC_OUTS11_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_13" }, "PSS4.PSS0_LOGIC_OUTS11_14->PSS_LOGIC_OUTS11_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_14" }, 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"delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_17" }, "PSS4.PSS0_LOGIC_OUTS11_18->PSS_LOGIC_OUTS11_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_18" }, "PSS4.PSS0_LOGIC_OUTS11_19->PSS_LOGIC_OUTS11_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_19" }, "PSS4.PSS0_LOGIC_OUTS11_2->PSS_LOGIC_OUTS11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_2" }, "PSS4.PSS0_LOGIC_OUTS11_3->PSS_LOGIC_OUTS11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_3" }, "PSS4.PSS0_LOGIC_OUTS11_4->PSS_LOGIC_OUTS11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_4" }, "PSS4.PSS0_LOGIC_OUTS11_5->PSS_LOGIC_OUTS11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_5" }, "PSS4.PSS0_LOGIC_OUTS11_6->PSS_LOGIC_OUTS11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_6" }, "PSS4.PSS0_LOGIC_OUTS11_7->PSS_LOGIC_OUTS11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_7" }, "PSS4.PSS0_LOGIC_OUTS11_8->PSS_LOGIC_OUTS11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_8" }, "PSS4.PSS0_LOGIC_OUTS11_9->PSS_LOGIC_OUTS11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS11_9" }, "PSS4.PSS0_LOGIC_OUTS12_0->PSS_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_0" }, "PSS4.PSS0_LOGIC_OUTS12_1->PSS_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_1" }, "PSS4.PSS0_LOGIC_OUTS12_10->PSS_LOGIC_OUTS12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_10" }, "PSS4.PSS0_LOGIC_OUTS12_11->PSS_LOGIC_OUTS12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_11", "is_directional": "1", + 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null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_14" }, "PSS4.PSS0_LOGIC_OUTS12_15->PSS_LOGIC_OUTS12_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_15" }, "PSS4.PSS0_LOGIC_OUTS12_16->PSS_LOGIC_OUTS12_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_16" }, 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"delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_19" }, "PSS4.PSS0_LOGIC_OUTS12_2->PSS_LOGIC_OUTS12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_2" }, "PSS4.PSS0_LOGIC_OUTS12_3->PSS_LOGIC_OUTS12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_3" }, "PSS4.PSS0_LOGIC_OUTS12_4->PSS_LOGIC_OUTS12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_4", 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+ "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_7" }, "PSS4.PSS0_LOGIC_OUTS12_8->PSS_LOGIC_OUTS12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_8" }, "PSS4.PSS0_LOGIC_OUTS12_9->PSS_LOGIC_OUTS12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS12_9" }, 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+ "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_10" }, "PSS4.PSS0_LOGIC_OUTS13_11->PSS_LOGIC_OUTS13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_11" }, "PSS4.PSS0_LOGIC_OUTS13_12->PSS_LOGIC_OUTS13_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_12" }, "PSS4.PSS0_LOGIC_OUTS13_13->PSS_LOGIC_OUTS13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_13" }, "PSS4.PSS0_LOGIC_OUTS13_14->PSS_LOGIC_OUTS13_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_14" }, "PSS4.PSS0_LOGIC_OUTS13_15->PSS_LOGIC_OUTS13_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_15" }, "PSS4.PSS0_LOGIC_OUTS13_16->PSS_LOGIC_OUTS13_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_16" }, "PSS4.PSS0_LOGIC_OUTS13_17->PSS_LOGIC_OUTS13_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_17" }, "PSS4.PSS0_LOGIC_OUTS13_18->PSS_LOGIC_OUTS13_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_18" }, "PSS4.PSS0_LOGIC_OUTS13_19->PSS_LOGIC_OUTS13_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_19" }, "PSS4.PSS0_LOGIC_OUTS13_2->PSS_LOGIC_OUTS13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_2" }, "PSS4.PSS0_LOGIC_OUTS13_3->PSS_LOGIC_OUTS13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_3" }, "PSS4.PSS0_LOGIC_OUTS13_4->PSS_LOGIC_OUTS13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_4" }, "PSS4.PSS0_LOGIC_OUTS13_5->PSS_LOGIC_OUTS13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_5" }, "PSS4.PSS0_LOGIC_OUTS13_6->PSS_LOGIC_OUTS13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_6" }, "PSS4.PSS0_LOGIC_OUTS13_7->PSS_LOGIC_OUTS13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_7" }, "PSS4.PSS0_LOGIC_OUTS13_8->PSS_LOGIC_OUTS13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_8" }, "PSS4.PSS0_LOGIC_OUTS13_9->PSS_LOGIC_OUTS13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS13_9" }, "PSS4.PSS0_LOGIC_OUTS14_0->PSS_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_0" }, "PSS4.PSS0_LOGIC_OUTS14_1->PSS_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_1" }, "PSS4.PSS0_LOGIC_OUTS14_10->PSS_LOGIC_OUTS14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_10" }, "PSS4.PSS0_LOGIC_OUTS14_11->PSS_LOGIC_OUTS14_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_11" }, "PSS4.PSS0_LOGIC_OUTS14_12->PSS_LOGIC_OUTS14_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_12" }, "PSS4.PSS0_LOGIC_OUTS14_13->PSS_LOGIC_OUTS14_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_13" }, "PSS4.PSS0_LOGIC_OUTS14_14->PSS_LOGIC_OUTS14_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_14" }, "PSS4.PSS0_LOGIC_OUTS14_15->PSS_LOGIC_OUTS14_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_15" }, "PSS4.PSS0_LOGIC_OUTS14_16->PSS_LOGIC_OUTS14_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_16" }, "PSS4.PSS0_LOGIC_OUTS14_17->PSS_LOGIC_OUTS14_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_17" }, "PSS4.PSS0_LOGIC_OUTS14_18->PSS_LOGIC_OUTS14_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_18" }, "PSS4.PSS0_LOGIC_OUTS14_19->PSS_LOGIC_OUTS14_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_19" }, "PSS4.PSS0_LOGIC_OUTS14_2->PSS_LOGIC_OUTS14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_2" }, "PSS4.PSS0_LOGIC_OUTS14_3->PSS_LOGIC_OUTS14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_3" }, "PSS4.PSS0_LOGIC_OUTS14_4->PSS_LOGIC_OUTS14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_4" }, "PSS4.PSS0_LOGIC_OUTS14_5->PSS_LOGIC_OUTS14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_5" }, "PSS4.PSS0_LOGIC_OUTS14_6->PSS_LOGIC_OUTS14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_6" }, "PSS4.PSS0_LOGIC_OUTS14_7->PSS_LOGIC_OUTS14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_7" }, "PSS4.PSS0_LOGIC_OUTS14_8->PSS_LOGIC_OUTS14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_8" }, "PSS4.PSS0_LOGIC_OUTS14_9->PSS_LOGIC_OUTS14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS14_9" }, "PSS4.PSS0_LOGIC_OUTS15_0->PSS_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_0" }, "PSS4.PSS0_LOGIC_OUTS15_1->PSS_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_1" }, "PSS4.PSS0_LOGIC_OUTS15_10->PSS_LOGIC_OUTS15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_10" }, "PSS4.PSS0_LOGIC_OUTS15_11->PSS_LOGIC_OUTS15_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_11" }, "PSS4.PSS0_LOGIC_OUTS15_12->PSS_LOGIC_OUTS15_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_12" }, "PSS4.PSS0_LOGIC_OUTS15_13->PSS_LOGIC_OUTS15_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_13" }, "PSS4.PSS0_LOGIC_OUTS15_14->PSS_LOGIC_OUTS15_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_14" }, "PSS4.PSS0_LOGIC_OUTS15_15->PSS_LOGIC_OUTS15_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_15" }, "PSS4.PSS0_LOGIC_OUTS15_16->PSS_LOGIC_OUTS15_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_16" }, "PSS4.PSS0_LOGIC_OUTS15_17->PSS_LOGIC_OUTS15_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_17" }, "PSS4.PSS0_LOGIC_OUTS15_18->PSS_LOGIC_OUTS15_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_18" }, "PSS4.PSS0_LOGIC_OUTS15_19->PSS_LOGIC_OUTS15_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_19" }, "PSS4.PSS0_LOGIC_OUTS15_2->PSS_LOGIC_OUTS15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_2" }, "PSS4.PSS0_LOGIC_OUTS15_3->PSS_LOGIC_OUTS15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_3" }, "PSS4.PSS0_LOGIC_OUTS15_4->PSS_LOGIC_OUTS15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_4" }, "PSS4.PSS0_LOGIC_OUTS15_5->PSS_LOGIC_OUTS15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_5" }, "PSS4.PSS0_LOGIC_OUTS15_6->PSS_LOGIC_OUTS15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_6" }, "PSS4.PSS0_LOGIC_OUTS15_7->PSS_LOGIC_OUTS15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_7" }, "PSS4.PSS0_LOGIC_OUTS15_8->PSS_LOGIC_OUTS15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_8" }, "PSS4.PSS0_LOGIC_OUTS15_9->PSS_LOGIC_OUTS15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS15_9" }, "PSS4.PSS0_LOGIC_OUTS16_0->PSS_LOGIC_OUTS16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_0" }, "PSS4.PSS0_LOGIC_OUTS16_1->PSS_LOGIC_OUTS16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_1" }, "PSS4.PSS0_LOGIC_OUTS16_10->PSS_LOGIC_OUTS16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_10" }, "PSS4.PSS0_LOGIC_OUTS16_11->PSS_LOGIC_OUTS16_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_11" }, "PSS4.PSS0_LOGIC_OUTS16_12->PSS_LOGIC_OUTS16_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_12" }, "PSS4.PSS0_LOGIC_OUTS16_13->PSS_LOGIC_OUTS16_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_13" }, "PSS4.PSS0_LOGIC_OUTS16_14->PSS_LOGIC_OUTS16_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_14" }, "PSS4.PSS0_LOGIC_OUTS16_15->PSS_LOGIC_OUTS16_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_15" }, "PSS4.PSS0_LOGIC_OUTS16_16->PSS_LOGIC_OUTS16_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_16" }, 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"delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_19" }, "PSS4.PSS0_LOGIC_OUTS16_2->PSS_LOGIC_OUTS16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_2" }, "PSS4.PSS0_LOGIC_OUTS16_3->PSS_LOGIC_OUTS16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_3" }, "PSS4.PSS0_LOGIC_OUTS16_4->PSS_LOGIC_OUTS16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_4", 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+ "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_7" }, "PSS4.PSS0_LOGIC_OUTS16_8->PSS_LOGIC_OUTS16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_8" }, "PSS4.PSS0_LOGIC_OUTS16_9->PSS_LOGIC_OUTS16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS16_9" }, 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+ "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_10" }, "PSS4.PSS0_LOGIC_OUTS17_11->PSS_LOGIC_OUTS17_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_11" }, "PSS4.PSS0_LOGIC_OUTS17_12->PSS_LOGIC_OUTS17_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_12" }, "PSS4.PSS0_LOGIC_OUTS17_13->PSS_LOGIC_OUTS17_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_13" }, "PSS4.PSS0_LOGIC_OUTS17_14->PSS_LOGIC_OUTS17_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_14" }, "PSS4.PSS0_LOGIC_OUTS17_15->PSS_LOGIC_OUTS17_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_15" }, "PSS4.PSS0_LOGIC_OUTS17_16->PSS_LOGIC_OUTS17_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_16" }, "PSS4.PSS0_LOGIC_OUTS17_17->PSS_LOGIC_OUTS17_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_17" }, "PSS4.PSS0_LOGIC_OUTS17_18->PSS_LOGIC_OUTS17_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_18" }, "PSS4.PSS0_LOGIC_OUTS17_19->PSS_LOGIC_OUTS17_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_19" }, "PSS4.PSS0_LOGIC_OUTS17_2->PSS_LOGIC_OUTS17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_2" }, "PSS4.PSS0_LOGIC_OUTS17_3->PSS_LOGIC_OUTS17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_3" }, "PSS4.PSS0_LOGIC_OUTS17_4->PSS_LOGIC_OUTS17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_4" }, "PSS4.PSS0_LOGIC_OUTS17_5->PSS_LOGIC_OUTS17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_5" }, "PSS4.PSS0_LOGIC_OUTS17_6->PSS_LOGIC_OUTS17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_6" }, "PSS4.PSS0_LOGIC_OUTS17_7->PSS_LOGIC_OUTS17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_7" }, "PSS4.PSS0_LOGIC_OUTS17_8->PSS_LOGIC_OUTS17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_8" }, "PSS4.PSS0_LOGIC_OUTS17_9->PSS_LOGIC_OUTS17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS17_9" }, "PSS4.PSS0_LOGIC_OUTS18_0->PSS_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_0" }, "PSS4.PSS0_LOGIC_OUTS18_1->PSS_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_1" }, "PSS4.PSS0_LOGIC_OUTS18_10->PSS_LOGIC_OUTS18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_10" }, "PSS4.PSS0_LOGIC_OUTS18_11->PSS_LOGIC_OUTS18_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_11" }, "PSS4.PSS0_LOGIC_OUTS18_12->PSS_LOGIC_OUTS18_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_12" }, "PSS4.PSS0_LOGIC_OUTS18_13->PSS_LOGIC_OUTS18_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_13" }, "PSS4.PSS0_LOGIC_OUTS18_14->PSS_LOGIC_OUTS18_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_14" }, "PSS4.PSS0_LOGIC_OUTS18_15->PSS_LOGIC_OUTS18_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_15" }, "PSS4.PSS0_LOGIC_OUTS18_16->PSS_LOGIC_OUTS18_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_16" }, "PSS4.PSS0_LOGIC_OUTS18_17->PSS_LOGIC_OUTS18_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_17" }, "PSS4.PSS0_LOGIC_OUTS18_18->PSS_LOGIC_OUTS18_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, 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"0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_3" }, "PSS4.PSS0_LOGIC_OUTS18_4->PSS_LOGIC_OUTS18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_4" }, "PSS4.PSS0_LOGIC_OUTS18_5->PSS_LOGIC_OUTS18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_5" }, "PSS4.PSS0_LOGIC_OUTS18_6->PSS_LOGIC_OUTS18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_6" }, "PSS4.PSS0_LOGIC_OUTS18_7->PSS_LOGIC_OUTS18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_7" }, "PSS4.PSS0_LOGIC_OUTS18_8->PSS_LOGIC_OUTS18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_8" }, "PSS4.PSS0_LOGIC_OUTS18_9->PSS_LOGIC_OUTS18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS18_9" }, "PSS4.PSS0_LOGIC_OUTS19_0->PSS_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_0" }, "PSS4.PSS0_LOGIC_OUTS19_1->PSS_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_1" }, "PSS4.PSS0_LOGIC_OUTS19_10->PSS_LOGIC_OUTS19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_10" }, "PSS4.PSS0_LOGIC_OUTS19_11->PSS_LOGIC_OUTS19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_11" }, "PSS4.PSS0_LOGIC_OUTS19_12->PSS_LOGIC_OUTS19_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_12" }, "PSS4.PSS0_LOGIC_OUTS19_13->PSS_LOGIC_OUTS19_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_13" }, "PSS4.PSS0_LOGIC_OUTS19_14->PSS_LOGIC_OUTS19_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_14" }, "PSS4.PSS0_LOGIC_OUTS19_15->PSS_LOGIC_OUTS19_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_15" }, "PSS4.PSS0_LOGIC_OUTS19_16->PSS_LOGIC_OUTS19_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_16" }, "PSS4.PSS0_LOGIC_OUTS19_17->PSS_LOGIC_OUTS19_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_17" }, "PSS4.PSS0_LOGIC_OUTS19_18->PSS_LOGIC_OUTS19_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_18" }, "PSS4.PSS0_LOGIC_OUTS19_19->PSS_LOGIC_OUTS19_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_19" }, "PSS4.PSS0_LOGIC_OUTS19_2->PSS_LOGIC_OUTS19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_2" }, "PSS4.PSS0_LOGIC_OUTS19_3->PSS_LOGIC_OUTS19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_3" }, "PSS4.PSS0_LOGIC_OUTS19_4->PSS_LOGIC_OUTS19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_4" }, "PSS4.PSS0_LOGIC_OUTS19_5->PSS_LOGIC_OUTS19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_5" }, "PSS4.PSS0_LOGIC_OUTS19_6->PSS_LOGIC_OUTS19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_6" }, "PSS4.PSS0_LOGIC_OUTS19_7->PSS_LOGIC_OUTS19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_7" }, "PSS4.PSS0_LOGIC_OUTS19_8->PSS_LOGIC_OUTS19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_8" }, "PSS4.PSS0_LOGIC_OUTS19_9->PSS_LOGIC_OUTS19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS19_9" }, "PSS4.PSS0_LOGIC_OUTS1_0->PSS_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_0" }, "PSS4.PSS0_LOGIC_OUTS1_1->PSS_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_1" }, "PSS4.PSS0_LOGIC_OUTS1_10->PSS_LOGIC_OUTS1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_10" }, "PSS4.PSS0_LOGIC_OUTS1_11->PSS_LOGIC_OUTS1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_11" }, "PSS4.PSS0_LOGIC_OUTS1_12->PSS_LOGIC_OUTS1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_12" }, "PSS4.PSS0_LOGIC_OUTS1_13->PSS_LOGIC_OUTS1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_13" }, "PSS4.PSS0_LOGIC_OUTS1_14->PSS_LOGIC_OUTS1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_14" }, "PSS4.PSS0_LOGIC_OUTS1_15->PSS_LOGIC_OUTS1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_15" }, "PSS4.PSS0_LOGIC_OUTS1_16->PSS_LOGIC_OUTS1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_16" }, "PSS4.PSS0_LOGIC_OUTS1_17->PSS_LOGIC_OUTS1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_17" }, "PSS4.PSS0_LOGIC_OUTS1_18->PSS_LOGIC_OUTS1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_18" }, "PSS4.PSS0_LOGIC_OUTS1_19->PSS_LOGIC_OUTS1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_19" }, "PSS4.PSS0_LOGIC_OUTS1_2->PSS_LOGIC_OUTS1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_2" }, "PSS4.PSS0_LOGIC_OUTS1_3->PSS_LOGIC_OUTS1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_3" }, "PSS4.PSS0_LOGIC_OUTS1_4->PSS_LOGIC_OUTS1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_4" }, "PSS4.PSS0_LOGIC_OUTS1_5->PSS_LOGIC_OUTS1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_5" }, "PSS4.PSS0_LOGIC_OUTS1_6->PSS_LOGIC_OUTS1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_6" }, "PSS4.PSS0_LOGIC_OUTS1_7->PSS_LOGIC_OUTS1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_7" }, "PSS4.PSS0_LOGIC_OUTS1_8->PSS_LOGIC_OUTS1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_8" }, "PSS4.PSS0_LOGIC_OUTS1_9->PSS_LOGIC_OUTS1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS1_9" }, "PSS4.PSS0_LOGIC_OUTS20_0->PSS_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_0" }, "PSS4.PSS0_LOGIC_OUTS20_1->PSS_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_1" }, "PSS4.PSS0_LOGIC_OUTS20_10->PSS_LOGIC_OUTS20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_10" }, "PSS4.PSS0_LOGIC_OUTS20_11->PSS_LOGIC_OUTS20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_11" }, "PSS4.PSS0_LOGIC_OUTS20_12->PSS_LOGIC_OUTS20_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_12" }, "PSS4.PSS0_LOGIC_OUTS20_13->PSS_LOGIC_OUTS20_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_13" }, "PSS4.PSS0_LOGIC_OUTS20_14->PSS_LOGIC_OUTS20_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_14" }, "PSS4.PSS0_LOGIC_OUTS20_15->PSS_LOGIC_OUTS20_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_15" }, "PSS4.PSS0_LOGIC_OUTS20_16->PSS_LOGIC_OUTS20_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_16" }, "PSS4.PSS0_LOGIC_OUTS20_17->PSS_LOGIC_OUTS20_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_17" }, "PSS4.PSS0_LOGIC_OUTS20_18->PSS_LOGIC_OUTS20_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_18" }, "PSS4.PSS0_LOGIC_OUTS20_19->PSS_LOGIC_OUTS20_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_19" }, "PSS4.PSS0_LOGIC_OUTS20_2->PSS_LOGIC_OUTS20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_2" }, "PSS4.PSS0_LOGIC_OUTS20_3->PSS_LOGIC_OUTS20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_3" }, "PSS4.PSS0_LOGIC_OUTS20_4->PSS_LOGIC_OUTS20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_4" }, "PSS4.PSS0_LOGIC_OUTS20_5->PSS_LOGIC_OUTS20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_5" }, "PSS4.PSS0_LOGIC_OUTS20_6->PSS_LOGIC_OUTS20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_6" }, "PSS4.PSS0_LOGIC_OUTS20_7->PSS_LOGIC_OUTS20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_7" }, "PSS4.PSS0_LOGIC_OUTS20_8->PSS_LOGIC_OUTS20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_8" }, "PSS4.PSS0_LOGIC_OUTS20_9->PSS_LOGIC_OUTS20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS20_9" }, "PSS4.PSS0_LOGIC_OUTS21_0->PSS_LOGIC_OUTS21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_0" }, "PSS4.PSS0_LOGIC_OUTS21_1->PSS_LOGIC_OUTS21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_1" }, "PSS4.PSS0_LOGIC_OUTS21_10->PSS_LOGIC_OUTS21_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_10" }, "PSS4.PSS0_LOGIC_OUTS21_11->PSS_LOGIC_OUTS21_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_11" }, "PSS4.PSS0_LOGIC_OUTS21_12->PSS_LOGIC_OUTS21_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_12" }, "PSS4.PSS0_LOGIC_OUTS21_13->PSS_LOGIC_OUTS21_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_13" }, "PSS4.PSS0_LOGIC_OUTS21_14->PSS_LOGIC_OUTS21_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_14" }, "PSS4.PSS0_LOGIC_OUTS21_15->PSS_LOGIC_OUTS21_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_15" }, "PSS4.PSS0_LOGIC_OUTS21_16->PSS_LOGIC_OUTS21_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_16" }, "PSS4.PSS0_LOGIC_OUTS21_17->PSS_LOGIC_OUTS21_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_17" }, "PSS4.PSS0_LOGIC_OUTS21_18->PSS_LOGIC_OUTS21_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_18" }, "PSS4.PSS0_LOGIC_OUTS21_19->PSS_LOGIC_OUTS21_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_19" }, "PSS4.PSS0_LOGIC_OUTS21_2->PSS_LOGIC_OUTS21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_2" }, "PSS4.PSS0_LOGIC_OUTS21_3->PSS_LOGIC_OUTS21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_3" }, "PSS4.PSS0_LOGIC_OUTS21_4->PSS_LOGIC_OUTS21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_4" }, "PSS4.PSS0_LOGIC_OUTS21_5->PSS_LOGIC_OUTS21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_5" }, "PSS4.PSS0_LOGIC_OUTS21_6->PSS_LOGIC_OUTS21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_6" }, "PSS4.PSS0_LOGIC_OUTS21_7->PSS_LOGIC_OUTS21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_7" }, "PSS4.PSS0_LOGIC_OUTS21_8->PSS_LOGIC_OUTS21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_8" }, "PSS4.PSS0_LOGIC_OUTS21_9->PSS_LOGIC_OUTS21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS21_9" }, "PSS4.PSS0_LOGIC_OUTS22_0->PSS_LOGIC_OUTS22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_0" }, "PSS4.PSS0_LOGIC_OUTS22_1->PSS_LOGIC_OUTS22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_1" }, "PSS4.PSS0_LOGIC_OUTS22_10->PSS_LOGIC_OUTS22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_10" }, "PSS4.PSS0_LOGIC_OUTS22_11->PSS_LOGIC_OUTS22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_11" }, "PSS4.PSS0_LOGIC_OUTS22_12->PSS_LOGIC_OUTS22_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_12" }, "PSS4.PSS0_LOGIC_OUTS22_13->PSS_LOGIC_OUTS22_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_13" }, "PSS4.PSS0_LOGIC_OUTS22_14->PSS_LOGIC_OUTS22_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_14" }, "PSS4.PSS0_LOGIC_OUTS22_15->PSS_LOGIC_OUTS22_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_15" }, "PSS4.PSS0_LOGIC_OUTS22_16->PSS_LOGIC_OUTS22_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_16" }, "PSS4.PSS0_LOGIC_OUTS22_17->PSS_LOGIC_OUTS22_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_17" }, "PSS4.PSS0_LOGIC_OUTS22_18->PSS_LOGIC_OUTS22_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_18" }, "PSS4.PSS0_LOGIC_OUTS22_19->PSS_LOGIC_OUTS22_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_19" }, "PSS4.PSS0_LOGIC_OUTS22_2->PSS_LOGIC_OUTS22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_2" }, "PSS4.PSS0_LOGIC_OUTS22_3->PSS_LOGIC_OUTS22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_3" }, "PSS4.PSS0_LOGIC_OUTS22_4->PSS_LOGIC_OUTS22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_4" }, "PSS4.PSS0_LOGIC_OUTS22_5->PSS_LOGIC_OUTS22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_5" }, "PSS4.PSS0_LOGIC_OUTS22_6->PSS_LOGIC_OUTS22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_6" }, "PSS4.PSS0_LOGIC_OUTS22_7->PSS_LOGIC_OUTS22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_7" }, "PSS4.PSS0_LOGIC_OUTS22_8->PSS_LOGIC_OUTS22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_8" }, "PSS4.PSS0_LOGIC_OUTS22_9->PSS_LOGIC_OUTS22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS22_9" }, "PSS4.PSS0_LOGIC_OUTS23_0->PSS_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_0" }, "PSS4.PSS0_LOGIC_OUTS23_1->PSS_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_1" }, "PSS4.PSS0_LOGIC_OUTS23_10->PSS_LOGIC_OUTS23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_10" }, "PSS4.PSS0_LOGIC_OUTS23_11->PSS_LOGIC_OUTS23_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_11" }, "PSS4.PSS0_LOGIC_OUTS23_12->PSS_LOGIC_OUTS23_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_12" }, "PSS4.PSS0_LOGIC_OUTS23_13->PSS_LOGIC_OUTS23_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_13" }, "PSS4.PSS0_LOGIC_OUTS23_14->PSS_LOGIC_OUTS23_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_14" }, "PSS4.PSS0_LOGIC_OUTS23_15->PSS_LOGIC_OUTS23_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_15" }, "PSS4.PSS0_LOGIC_OUTS23_16->PSS_LOGIC_OUTS23_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_16" }, "PSS4.PSS0_LOGIC_OUTS23_17->PSS_LOGIC_OUTS23_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_17" }, "PSS4.PSS0_LOGIC_OUTS23_18->PSS_LOGIC_OUTS23_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_18" }, "PSS4.PSS0_LOGIC_OUTS23_19->PSS_LOGIC_OUTS23_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_19" }, "PSS4.PSS0_LOGIC_OUTS23_2->PSS_LOGIC_OUTS23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_2" }, "PSS4.PSS0_LOGIC_OUTS23_3->PSS_LOGIC_OUTS23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_3" }, "PSS4.PSS0_LOGIC_OUTS23_4->PSS_LOGIC_OUTS23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_4" }, "PSS4.PSS0_LOGIC_OUTS23_5->PSS_LOGIC_OUTS23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_5" }, "PSS4.PSS0_LOGIC_OUTS23_6->PSS_LOGIC_OUTS23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_6" }, "PSS4.PSS0_LOGIC_OUTS23_7->PSS_LOGIC_OUTS23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_7" }, "PSS4.PSS0_LOGIC_OUTS23_8->PSS_LOGIC_OUTS23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_8" }, "PSS4.PSS0_LOGIC_OUTS23_9->PSS_LOGIC_OUTS23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS23_9" }, "PSS4.PSS0_LOGIC_OUTS2_0->PSS_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_0" }, "PSS4.PSS0_LOGIC_OUTS2_1->PSS_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_1" }, "PSS4.PSS0_LOGIC_OUTS2_10->PSS_LOGIC_OUTS2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_10" }, "PSS4.PSS0_LOGIC_OUTS2_11->PSS_LOGIC_OUTS2_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_11" }, "PSS4.PSS0_LOGIC_OUTS2_12->PSS_LOGIC_OUTS2_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_12" }, "PSS4.PSS0_LOGIC_OUTS2_13->PSS_LOGIC_OUTS2_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_13" }, "PSS4.PSS0_LOGIC_OUTS2_14->PSS_LOGIC_OUTS2_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_14" }, "PSS4.PSS0_LOGIC_OUTS2_15->PSS_LOGIC_OUTS2_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_15" }, "PSS4.PSS0_LOGIC_OUTS2_16->PSS_LOGIC_OUTS2_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_16" }, "PSS4.PSS0_LOGIC_OUTS2_17->PSS_LOGIC_OUTS2_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_17" }, "PSS4.PSS0_LOGIC_OUTS2_18->PSS_LOGIC_OUTS2_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_18" }, "PSS4.PSS0_LOGIC_OUTS2_19->PSS_LOGIC_OUTS2_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_19" }, "PSS4.PSS0_LOGIC_OUTS2_2->PSS_LOGIC_OUTS2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_2" }, "PSS4.PSS0_LOGIC_OUTS2_3->PSS_LOGIC_OUTS2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_3" }, "PSS4.PSS0_LOGIC_OUTS2_4->PSS_LOGIC_OUTS2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_4" }, "PSS4.PSS0_LOGIC_OUTS2_5->PSS_LOGIC_OUTS2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_5" }, "PSS4.PSS0_LOGIC_OUTS2_6->PSS_LOGIC_OUTS2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_6" }, "PSS4.PSS0_LOGIC_OUTS2_7->PSS_LOGIC_OUTS2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_7" }, "PSS4.PSS0_LOGIC_OUTS2_8->PSS_LOGIC_OUTS2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_8" }, "PSS4.PSS0_LOGIC_OUTS2_9->PSS_LOGIC_OUTS2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS2_9" }, "PSS4.PSS0_LOGIC_OUTS3_0->PSS_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_0" }, "PSS4.PSS0_LOGIC_OUTS3_1->PSS_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_1" }, "PSS4.PSS0_LOGIC_OUTS3_10->PSS_LOGIC_OUTS3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_10" }, "PSS4.PSS0_LOGIC_OUTS3_11->PSS_LOGIC_OUTS3_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_11" }, "PSS4.PSS0_LOGIC_OUTS3_12->PSS_LOGIC_OUTS3_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_12" }, "PSS4.PSS0_LOGIC_OUTS3_13->PSS_LOGIC_OUTS3_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_13" }, "PSS4.PSS0_LOGIC_OUTS3_14->PSS_LOGIC_OUTS3_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_14" }, "PSS4.PSS0_LOGIC_OUTS3_15->PSS_LOGIC_OUTS3_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_15" }, "PSS4.PSS0_LOGIC_OUTS3_16->PSS_LOGIC_OUTS3_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_16" }, "PSS4.PSS0_LOGIC_OUTS3_17->PSS_LOGIC_OUTS3_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_17" }, "PSS4.PSS0_LOGIC_OUTS3_18->PSS_LOGIC_OUTS3_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_18" }, "PSS4.PSS0_LOGIC_OUTS3_19->PSS_LOGIC_OUTS3_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_19" }, "PSS4.PSS0_LOGIC_OUTS3_2->PSS_LOGIC_OUTS3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_2" }, "PSS4.PSS0_LOGIC_OUTS3_3->PSS_LOGIC_OUTS3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_3" }, "PSS4.PSS0_LOGIC_OUTS3_4->PSS_LOGIC_OUTS3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_4" }, "PSS4.PSS0_LOGIC_OUTS3_5->PSS_LOGIC_OUTS3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_5" }, "PSS4.PSS0_LOGIC_OUTS3_6->PSS_LOGIC_OUTS3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_6" }, "PSS4.PSS0_LOGIC_OUTS3_7->PSS_LOGIC_OUTS3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_7" }, "PSS4.PSS0_LOGIC_OUTS3_8->PSS_LOGIC_OUTS3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_8" }, "PSS4.PSS0_LOGIC_OUTS3_9->PSS_LOGIC_OUTS3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS3_9" }, "PSS4.PSS0_LOGIC_OUTS4_0->PSS_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_0" }, "PSS4.PSS0_LOGIC_OUTS4_1->PSS_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_1" }, "PSS4.PSS0_LOGIC_OUTS4_10->PSS_LOGIC_OUTS4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_10" }, "PSS4.PSS0_LOGIC_OUTS4_11->PSS_LOGIC_OUTS4_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_11" }, "PSS4.PSS0_LOGIC_OUTS4_12->PSS_LOGIC_OUTS4_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_12" }, "PSS4.PSS0_LOGIC_OUTS4_13->PSS_LOGIC_OUTS4_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_13" }, "PSS4.PSS0_LOGIC_OUTS4_14->PSS_LOGIC_OUTS4_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_14" }, "PSS4.PSS0_LOGIC_OUTS4_15->PSS_LOGIC_OUTS4_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_15" }, "PSS4.PSS0_LOGIC_OUTS4_16->PSS_LOGIC_OUTS4_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_16" }, "PSS4.PSS0_LOGIC_OUTS4_17->PSS_LOGIC_OUTS4_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_17" }, "PSS4.PSS0_LOGIC_OUTS4_18->PSS_LOGIC_OUTS4_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_18" }, "PSS4.PSS0_LOGIC_OUTS4_19->PSS_LOGIC_OUTS4_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_19" }, "PSS4.PSS0_LOGIC_OUTS4_2->PSS_LOGIC_OUTS4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_2" }, "PSS4.PSS0_LOGIC_OUTS4_3->PSS_LOGIC_OUTS4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_3" }, "PSS4.PSS0_LOGIC_OUTS4_4->PSS_LOGIC_OUTS4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_4" }, "PSS4.PSS0_LOGIC_OUTS4_5->PSS_LOGIC_OUTS4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_5" }, "PSS4.PSS0_LOGIC_OUTS4_6->PSS_LOGIC_OUTS4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_6" }, "PSS4.PSS0_LOGIC_OUTS4_7->PSS_LOGIC_OUTS4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_7" }, "PSS4.PSS0_LOGIC_OUTS4_8->PSS_LOGIC_OUTS4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_8" }, "PSS4.PSS0_LOGIC_OUTS4_9->PSS_LOGIC_OUTS4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS4_9" }, "PSS4.PSS0_LOGIC_OUTS5_0->PSS_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_0" }, "PSS4.PSS0_LOGIC_OUTS5_1->PSS_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_1" }, "PSS4.PSS0_LOGIC_OUTS5_10->PSS_LOGIC_OUTS5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_10" }, "PSS4.PSS0_LOGIC_OUTS5_11->PSS_LOGIC_OUTS5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_11" }, "PSS4.PSS0_LOGIC_OUTS5_12->PSS_LOGIC_OUTS5_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_12" }, "PSS4.PSS0_LOGIC_OUTS5_13->PSS_LOGIC_OUTS5_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_13" }, "PSS4.PSS0_LOGIC_OUTS5_14->PSS_LOGIC_OUTS5_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_14" }, "PSS4.PSS0_LOGIC_OUTS5_15->PSS_LOGIC_OUTS5_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_15" }, "PSS4.PSS0_LOGIC_OUTS5_16->PSS_LOGIC_OUTS5_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_16" }, "PSS4.PSS0_LOGIC_OUTS5_17->PSS_LOGIC_OUTS5_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_17" }, "PSS4.PSS0_LOGIC_OUTS5_18->PSS_LOGIC_OUTS5_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_18" }, "PSS4.PSS0_LOGIC_OUTS5_19->PSS_LOGIC_OUTS5_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_19" }, "PSS4.PSS0_LOGIC_OUTS5_2->PSS_LOGIC_OUTS5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_2" }, "PSS4.PSS0_LOGIC_OUTS5_3->PSS_LOGIC_OUTS5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_3" }, "PSS4.PSS0_LOGIC_OUTS5_4->PSS_LOGIC_OUTS5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_4" }, "PSS4.PSS0_LOGIC_OUTS5_5->PSS_LOGIC_OUTS5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_5" }, "PSS4.PSS0_LOGIC_OUTS5_6->PSS_LOGIC_OUTS5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_6" }, "PSS4.PSS0_LOGIC_OUTS5_7->PSS_LOGIC_OUTS5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_7" }, "PSS4.PSS0_LOGIC_OUTS5_8->PSS_LOGIC_OUTS5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_8" }, "PSS4.PSS0_LOGIC_OUTS5_9->PSS_LOGIC_OUTS5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS5_9" }, "PSS4.PSS0_LOGIC_OUTS6_0->PSS_LOGIC_OUTS6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_0" }, "PSS4.PSS0_LOGIC_OUTS6_1->PSS_LOGIC_OUTS6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_1" }, "PSS4.PSS0_LOGIC_OUTS6_10->PSS_LOGIC_OUTS6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_10" }, "PSS4.PSS0_LOGIC_OUTS6_11->PSS_LOGIC_OUTS6_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_11" }, "PSS4.PSS0_LOGIC_OUTS6_12->PSS_LOGIC_OUTS6_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_12" }, "PSS4.PSS0_LOGIC_OUTS6_13->PSS_LOGIC_OUTS6_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_13" }, "PSS4.PSS0_LOGIC_OUTS6_14->PSS_LOGIC_OUTS6_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_14" }, "PSS4.PSS0_LOGIC_OUTS6_15->PSS_LOGIC_OUTS6_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_15" }, "PSS4.PSS0_LOGIC_OUTS6_16->PSS_LOGIC_OUTS6_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_16" }, "PSS4.PSS0_LOGIC_OUTS6_17->PSS_LOGIC_OUTS6_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_17" }, "PSS4.PSS0_LOGIC_OUTS6_18->PSS_LOGIC_OUTS6_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_18" }, "PSS4.PSS0_LOGIC_OUTS6_19->PSS_LOGIC_OUTS6_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_19" }, "PSS4.PSS0_LOGIC_OUTS6_2->PSS_LOGIC_OUTS6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_2" }, "PSS4.PSS0_LOGIC_OUTS6_3->PSS_LOGIC_OUTS6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_3" }, "PSS4.PSS0_LOGIC_OUTS6_4->PSS_LOGIC_OUTS6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_4" }, "PSS4.PSS0_LOGIC_OUTS6_5->PSS_LOGIC_OUTS6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_5" }, "PSS4.PSS0_LOGIC_OUTS6_6->PSS_LOGIC_OUTS6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_6" }, "PSS4.PSS0_LOGIC_OUTS6_7->PSS_LOGIC_OUTS6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_7" }, "PSS4.PSS0_LOGIC_OUTS6_8->PSS_LOGIC_OUTS6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_8" }, "PSS4.PSS0_LOGIC_OUTS6_9->PSS_LOGIC_OUTS6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS6_9" }, "PSS4.PSS0_LOGIC_OUTS7_0->PSS_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_0" }, "PSS4.PSS0_LOGIC_OUTS7_1->PSS_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_1" }, "PSS4.PSS0_LOGIC_OUTS7_10->PSS_LOGIC_OUTS7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_10" }, "PSS4.PSS0_LOGIC_OUTS7_11->PSS_LOGIC_OUTS7_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_11" }, "PSS4.PSS0_LOGIC_OUTS7_12->PSS_LOGIC_OUTS7_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_12" }, "PSS4.PSS0_LOGIC_OUTS7_13->PSS_LOGIC_OUTS7_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_13" }, "PSS4.PSS0_LOGIC_OUTS7_14->PSS_LOGIC_OUTS7_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_14" }, "PSS4.PSS0_LOGIC_OUTS7_15->PSS_LOGIC_OUTS7_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_15" }, "PSS4.PSS0_LOGIC_OUTS7_16->PSS_LOGIC_OUTS7_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_16" }, "PSS4.PSS0_LOGIC_OUTS7_17->PSS_LOGIC_OUTS7_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_17" }, "PSS4.PSS0_LOGIC_OUTS7_18->PSS_LOGIC_OUTS7_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_18" }, "PSS4.PSS0_LOGIC_OUTS7_19->PSS_LOGIC_OUTS7_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_19" }, "PSS4.PSS0_LOGIC_OUTS7_2->PSS_LOGIC_OUTS7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_2" }, "PSS4.PSS0_LOGIC_OUTS7_3->PSS_LOGIC_OUTS7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_3" }, "PSS4.PSS0_LOGIC_OUTS7_4->PSS_LOGIC_OUTS7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_4" }, "PSS4.PSS0_LOGIC_OUTS7_5->PSS_LOGIC_OUTS7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_5" }, "PSS4.PSS0_LOGIC_OUTS7_6->PSS_LOGIC_OUTS7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_6" }, "PSS4.PSS0_LOGIC_OUTS7_7->PSS_LOGIC_OUTS7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_7" }, "PSS4.PSS0_LOGIC_OUTS7_8->PSS_LOGIC_OUTS7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_8" }, "PSS4.PSS0_LOGIC_OUTS7_9->PSS_LOGIC_OUTS7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS7_9" }, "PSS4.PSS0_LOGIC_OUTS8_0->PSS_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_0" }, "PSS4.PSS0_LOGIC_OUTS8_1->PSS_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_1" }, "PSS4.PSS0_LOGIC_OUTS8_10->PSS_LOGIC_OUTS8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_10" }, "PSS4.PSS0_LOGIC_OUTS8_11->PSS_LOGIC_OUTS8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_11" }, "PSS4.PSS0_LOGIC_OUTS8_12->PSS_LOGIC_OUTS8_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_12" }, "PSS4.PSS0_LOGIC_OUTS8_13->PSS_LOGIC_OUTS8_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_13" }, "PSS4.PSS0_LOGIC_OUTS8_14->PSS_LOGIC_OUTS8_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_14" }, "PSS4.PSS0_LOGIC_OUTS8_15->PSS_LOGIC_OUTS8_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_15" }, "PSS4.PSS0_LOGIC_OUTS8_16->PSS_LOGIC_OUTS8_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_16" }, "PSS4.PSS0_LOGIC_OUTS8_17->PSS_LOGIC_OUTS8_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_17" }, "PSS4.PSS0_LOGIC_OUTS8_18->PSS_LOGIC_OUTS8_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_18" }, "PSS4.PSS0_LOGIC_OUTS8_19->PSS_LOGIC_OUTS8_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_19" }, "PSS4.PSS0_LOGIC_OUTS8_2->PSS_LOGIC_OUTS8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_2" }, "PSS4.PSS0_LOGIC_OUTS8_3->PSS_LOGIC_OUTS8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_3" }, "PSS4.PSS0_LOGIC_OUTS8_4->PSS_LOGIC_OUTS8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_4" }, "PSS4.PSS0_LOGIC_OUTS8_5->PSS_LOGIC_OUTS8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_5" }, "PSS4.PSS0_LOGIC_OUTS8_6->PSS_LOGIC_OUTS8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_6" }, "PSS4.PSS0_LOGIC_OUTS8_7->PSS_LOGIC_OUTS8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_7" }, "PSS4.PSS0_LOGIC_OUTS8_8->PSS_LOGIC_OUTS8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_8" }, "PSS4.PSS0_LOGIC_OUTS8_9->PSS_LOGIC_OUTS8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS8_9" }, "PSS4.PSS0_LOGIC_OUTS9_0->PSS_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_0" }, "PSS4.PSS0_LOGIC_OUTS9_1->PSS_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_1" }, "PSS4.PSS0_LOGIC_OUTS9_10->PSS_LOGIC_OUTS9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_10" }, "PSS4.PSS0_LOGIC_OUTS9_11->PSS_LOGIC_OUTS9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_11" }, "PSS4.PSS0_LOGIC_OUTS9_12->PSS_LOGIC_OUTS9_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_12" }, "PSS4.PSS0_LOGIC_OUTS9_13->PSS_LOGIC_OUTS9_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_13" }, "PSS4.PSS0_LOGIC_OUTS9_14->PSS_LOGIC_OUTS9_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_14" }, "PSS4.PSS0_LOGIC_OUTS9_15->PSS_LOGIC_OUTS9_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_15" }, "PSS4.PSS0_LOGIC_OUTS9_16->PSS_LOGIC_OUTS9_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_16" }, "PSS4.PSS0_LOGIC_OUTS9_17->PSS_LOGIC_OUTS9_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_17" }, "PSS4.PSS0_LOGIC_OUTS9_18->PSS_LOGIC_OUTS9_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_18" }, "PSS4.PSS0_LOGIC_OUTS9_19->PSS_LOGIC_OUTS9_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_19" }, "PSS4.PSS0_LOGIC_OUTS9_2->PSS_LOGIC_OUTS9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_2" }, "PSS4.PSS0_LOGIC_OUTS9_3->PSS_LOGIC_OUTS9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_3" }, "PSS4.PSS0_LOGIC_OUTS9_4->PSS_LOGIC_OUTS9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_4" }, "PSS4.PSS0_LOGIC_OUTS9_5->PSS_LOGIC_OUTS9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_5" }, "PSS4.PSS0_LOGIC_OUTS9_6->PSS_LOGIC_OUTS9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_6" }, "PSS4.PSS0_LOGIC_OUTS9_7->PSS_LOGIC_OUTS9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_7" }, "PSS4.PSS0_LOGIC_OUTS9_8->PSS_LOGIC_OUTS9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_8" }, "PSS4.PSS0_LOGIC_OUTS9_9->PSS_LOGIC_OUTS9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS_LOGIC_OUTS9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS0_LOGIC_OUTS9_9" }, "PSS4.PSS_CLK_B0_0->PSS0_CLK_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_0" }, "PSS4.PSS_CLK_B0_1->PSS0_CLK_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_1" }, "PSS4.PSS_CLK_B0_10->PSS0_CLK_B0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_10" }, "PSS4.PSS_CLK_B0_11->PSS0_CLK_B0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_11" }, "PSS4.PSS_CLK_B0_12->PSS0_CLK_B0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_12" }, "PSS4.PSS_CLK_B0_13->PSS0_CLK_B0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_13" }, "PSS4.PSS_CLK_B0_14->PSS0_CLK_B0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_14" }, "PSS4.PSS_CLK_B0_15->PSS0_CLK_B0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_15" }, "PSS4.PSS_CLK_B0_16->PSS0_CLK_B0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_16" }, "PSS4.PSS_CLK_B0_17->PSS0_CLK_B0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_17" }, "PSS4.PSS_CLK_B0_18->PSS0_CLK_B0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_18" }, "PSS4.PSS_CLK_B0_19->PSS0_CLK_B0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_19" }, "PSS4.PSS_CLK_B0_2->PSS0_CLK_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_2" }, "PSS4.PSS_CLK_B0_3->PSS0_CLK_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_3" }, "PSS4.PSS_CLK_B0_4->PSS0_CLK_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_4" }, "PSS4.PSS_CLK_B0_5->PSS0_CLK_B0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_5" }, "PSS4.PSS_CLK_B0_6->PSS0_CLK_B0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_6" }, "PSS4.PSS_CLK_B0_7->PSS0_CLK_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_7" }, "PSS4.PSS_CLK_B0_8->PSS0_CLK_B0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_8" }, "PSS4.PSS_CLK_B0_9->PSS0_CLK_B0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B0_9" }, "PSS4.PSS_CLK_B1_0->PSS0_CLK_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_0" }, "PSS4.PSS_CLK_B1_1->PSS0_CLK_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_1" }, "PSS4.PSS_CLK_B1_10->PSS0_CLK_B1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_10" }, "PSS4.PSS_CLK_B1_11->PSS0_CLK_B1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_11" }, "PSS4.PSS_CLK_B1_12->PSS0_CLK_B1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_12" }, "PSS4.PSS_CLK_B1_13->PSS0_CLK_B1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_13" }, "PSS4.PSS_CLK_B1_14->PSS0_CLK_B1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_14" }, "PSS4.PSS_CLK_B1_15->PSS0_CLK_B1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_15" }, "PSS4.PSS_CLK_B1_16->PSS0_CLK_B1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_16" }, "PSS4.PSS_CLK_B1_17->PSS0_CLK_B1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_17" }, "PSS4.PSS_CLK_B1_18->PSS0_CLK_B1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_18" }, "PSS4.PSS_CLK_B1_19->PSS0_CLK_B1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_19" }, "PSS4.PSS_CLK_B1_2->PSS0_CLK_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_2" }, "PSS4.PSS_CLK_B1_3->PSS0_CLK_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_3" }, "PSS4.PSS_CLK_B1_4->PSS0_CLK_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_4" }, "PSS4.PSS_CLK_B1_5->PSS0_CLK_B1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_5" }, "PSS4.PSS_CLK_B1_6->PSS0_CLK_B1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_6" }, "PSS4.PSS_CLK_B1_7->PSS0_CLK_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_7" }, "PSS4.PSS_CLK_B1_8->PSS0_CLK_B1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_8" }, "PSS4.PSS_CLK_B1_9->PSS0_CLK_B1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_CLK_B1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_CLK_B1_9" }, "PSS4.PSS_IMUX_B0_0->PSS0_IMUX_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_0" }, "PSS4.PSS_IMUX_B0_1->PSS0_IMUX_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_1" }, "PSS4.PSS_IMUX_B0_10->PSS0_IMUX_B0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_10" }, "PSS4.PSS_IMUX_B0_11->PSS0_IMUX_B0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_11" }, "PSS4.PSS_IMUX_B0_12->PSS0_IMUX_B0_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_12" }, "PSS4.PSS_IMUX_B0_13->PSS0_IMUX_B0_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_13" }, "PSS4.PSS_IMUX_B0_14->PSS0_IMUX_B0_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_14" }, "PSS4.PSS_IMUX_B0_15->PSS0_IMUX_B0_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_15" }, "PSS4.PSS_IMUX_B0_16->PSS0_IMUX_B0_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_16" }, "PSS4.PSS_IMUX_B0_17->PSS0_IMUX_B0_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_17" }, "PSS4.PSS_IMUX_B0_18->PSS0_IMUX_B0_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_18" }, "PSS4.PSS_IMUX_B0_19->PSS0_IMUX_B0_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_19" }, "PSS4.PSS_IMUX_B0_2->PSS0_IMUX_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_2" }, "PSS4.PSS_IMUX_B0_3->PSS0_IMUX_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_3" }, "PSS4.PSS_IMUX_B0_4->PSS0_IMUX_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_4" }, "PSS4.PSS_IMUX_B0_5->PSS0_IMUX_B0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_5" }, "PSS4.PSS_IMUX_B0_6->PSS0_IMUX_B0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_6" }, "PSS4.PSS_IMUX_B0_7->PSS0_IMUX_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_7" }, "PSS4.PSS_IMUX_B0_8->PSS0_IMUX_B0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_8" }, "PSS4.PSS_IMUX_B0_9->PSS0_IMUX_B0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B0_9" }, "PSS4.PSS_IMUX_B10_0->PSS0_IMUX_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_0" }, "PSS4.PSS_IMUX_B10_1->PSS0_IMUX_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_1" }, "PSS4.PSS_IMUX_B10_10->PSS0_IMUX_B10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_10" }, "PSS4.PSS_IMUX_B10_11->PSS0_IMUX_B10_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_11" }, "PSS4.PSS_IMUX_B10_12->PSS0_IMUX_B10_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_12" }, "PSS4.PSS_IMUX_B10_13->PSS0_IMUX_B10_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_13" }, "PSS4.PSS_IMUX_B10_14->PSS0_IMUX_B10_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_14" }, "PSS4.PSS_IMUX_B10_15->PSS0_IMUX_B10_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_15" }, "PSS4.PSS_IMUX_B10_16->PSS0_IMUX_B10_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_16" }, "PSS4.PSS_IMUX_B10_17->PSS0_IMUX_B10_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_17" }, "PSS4.PSS_IMUX_B10_18->PSS0_IMUX_B10_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_18" }, "PSS4.PSS_IMUX_B10_19->PSS0_IMUX_B10_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_19" }, "PSS4.PSS_IMUX_B10_2->PSS0_IMUX_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_2" }, "PSS4.PSS_IMUX_B10_3->PSS0_IMUX_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_3" }, "PSS4.PSS_IMUX_B10_4->PSS0_IMUX_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_4" }, "PSS4.PSS_IMUX_B10_5->PSS0_IMUX_B10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_5" }, "PSS4.PSS_IMUX_B10_6->PSS0_IMUX_B10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_6" }, "PSS4.PSS_IMUX_B10_7->PSS0_IMUX_B10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_7" }, "PSS4.PSS_IMUX_B10_8->PSS0_IMUX_B10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_8" }, "PSS4.PSS_IMUX_B10_9->PSS0_IMUX_B10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B10_9" }, "PSS4.PSS_IMUX_B11_0->PSS0_IMUX_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_0" }, "PSS4.PSS_IMUX_B11_1->PSS0_IMUX_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_1" }, "PSS4.PSS_IMUX_B11_10->PSS0_IMUX_B11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_10" }, "PSS4.PSS_IMUX_B11_11->PSS0_IMUX_B11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_11" }, "PSS4.PSS_IMUX_B11_12->PSS0_IMUX_B11_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_12" }, "PSS4.PSS_IMUX_B11_13->PSS0_IMUX_B11_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_13" }, "PSS4.PSS_IMUX_B11_14->PSS0_IMUX_B11_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_14" }, "PSS4.PSS_IMUX_B11_15->PSS0_IMUX_B11_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_15" }, "PSS4.PSS_IMUX_B11_16->PSS0_IMUX_B11_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_16" }, "PSS4.PSS_IMUX_B11_17->PSS0_IMUX_B11_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_17" }, "PSS4.PSS_IMUX_B11_18->PSS0_IMUX_B11_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_18" }, "PSS4.PSS_IMUX_B11_19->PSS0_IMUX_B11_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_19" }, "PSS4.PSS_IMUX_B11_2->PSS0_IMUX_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_2" }, "PSS4.PSS_IMUX_B11_3->PSS0_IMUX_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_3" }, "PSS4.PSS_IMUX_B11_4->PSS0_IMUX_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_4" }, "PSS4.PSS_IMUX_B11_5->PSS0_IMUX_B11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_5" }, "PSS4.PSS_IMUX_B11_6->PSS0_IMUX_B11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_6" }, "PSS4.PSS_IMUX_B11_7->PSS0_IMUX_B11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_7" }, "PSS4.PSS_IMUX_B11_8->PSS0_IMUX_B11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_8" }, "PSS4.PSS_IMUX_B11_9->PSS0_IMUX_B11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B11_9" }, "PSS4.PSS_IMUX_B12_0->PSS0_IMUX_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_0" }, "PSS4.PSS_IMUX_B12_1->PSS0_IMUX_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_1" }, "PSS4.PSS_IMUX_B12_10->PSS0_IMUX_B12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_10" }, "PSS4.PSS_IMUX_B12_11->PSS0_IMUX_B12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_11" }, "PSS4.PSS_IMUX_B12_12->PSS0_IMUX_B12_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_12" }, "PSS4.PSS_IMUX_B12_13->PSS0_IMUX_B12_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_13" }, "PSS4.PSS_IMUX_B12_14->PSS0_IMUX_B12_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_14" }, "PSS4.PSS_IMUX_B12_15->PSS0_IMUX_B12_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_15" }, "PSS4.PSS_IMUX_B12_16->PSS0_IMUX_B12_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_16" }, "PSS4.PSS_IMUX_B12_17->PSS0_IMUX_B12_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_17" }, "PSS4.PSS_IMUX_B12_18->PSS0_IMUX_B12_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_18" }, "PSS4.PSS_IMUX_B12_19->PSS0_IMUX_B12_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_19" }, "PSS4.PSS_IMUX_B12_2->PSS0_IMUX_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_2" }, "PSS4.PSS_IMUX_B12_3->PSS0_IMUX_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_3" }, "PSS4.PSS_IMUX_B12_4->PSS0_IMUX_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_4" }, "PSS4.PSS_IMUX_B12_5->PSS0_IMUX_B12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_5" }, "PSS4.PSS_IMUX_B12_6->PSS0_IMUX_B12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_6" }, "PSS4.PSS_IMUX_B12_7->PSS0_IMUX_B12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_7" }, "PSS4.PSS_IMUX_B12_8->PSS0_IMUX_B12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_8" }, "PSS4.PSS_IMUX_B12_9->PSS0_IMUX_B12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B12_9" }, "PSS4.PSS_IMUX_B13_0->PSS0_IMUX_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_0" }, "PSS4.PSS_IMUX_B13_1->PSS0_IMUX_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_1" }, "PSS4.PSS_IMUX_B13_10->PSS0_IMUX_B13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_10" }, "PSS4.PSS_IMUX_B13_11->PSS0_IMUX_B13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_11" }, "PSS4.PSS_IMUX_B13_12->PSS0_IMUX_B13_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_12" }, "PSS4.PSS_IMUX_B13_13->PSS0_IMUX_B13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_13" }, "PSS4.PSS_IMUX_B13_14->PSS0_IMUX_B13_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_14" }, "PSS4.PSS_IMUX_B13_15->PSS0_IMUX_B13_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_15" }, "PSS4.PSS_IMUX_B13_16->PSS0_IMUX_B13_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_16" }, "PSS4.PSS_IMUX_B13_17->PSS0_IMUX_B13_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_17" }, "PSS4.PSS_IMUX_B13_18->PSS0_IMUX_B13_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_18" }, "PSS4.PSS_IMUX_B13_19->PSS0_IMUX_B13_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_19" }, "PSS4.PSS_IMUX_B13_2->PSS0_IMUX_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_2" }, "PSS4.PSS_IMUX_B13_3->PSS0_IMUX_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_3" }, "PSS4.PSS_IMUX_B13_4->PSS0_IMUX_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_4" }, "PSS4.PSS_IMUX_B13_5->PSS0_IMUX_B13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_5" }, "PSS4.PSS_IMUX_B13_6->PSS0_IMUX_B13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_6" }, "PSS4.PSS_IMUX_B13_7->PSS0_IMUX_B13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_7" }, "PSS4.PSS_IMUX_B13_8->PSS0_IMUX_B13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_8" }, "PSS4.PSS_IMUX_B13_9->PSS0_IMUX_B13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B13_9" }, "PSS4.PSS_IMUX_B14_0->PSS0_IMUX_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_0" }, "PSS4.PSS_IMUX_B14_1->PSS0_IMUX_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_1" }, "PSS4.PSS_IMUX_B14_10->PSS0_IMUX_B14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_10" }, "PSS4.PSS_IMUX_B14_11->PSS0_IMUX_B14_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_11" }, "PSS4.PSS_IMUX_B14_12->PSS0_IMUX_B14_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_12" }, "PSS4.PSS_IMUX_B14_13->PSS0_IMUX_B14_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_13" }, "PSS4.PSS_IMUX_B14_14->PSS0_IMUX_B14_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_14" }, "PSS4.PSS_IMUX_B14_15->PSS0_IMUX_B14_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_15" }, "PSS4.PSS_IMUX_B14_16->PSS0_IMUX_B14_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_16" }, "PSS4.PSS_IMUX_B14_17->PSS0_IMUX_B14_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_17" }, "PSS4.PSS_IMUX_B14_18->PSS0_IMUX_B14_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_18" }, "PSS4.PSS_IMUX_B14_19->PSS0_IMUX_B14_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_19" }, "PSS4.PSS_IMUX_B14_2->PSS0_IMUX_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_2" }, "PSS4.PSS_IMUX_B14_3->PSS0_IMUX_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_3" }, "PSS4.PSS_IMUX_B14_4->PSS0_IMUX_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_4" }, "PSS4.PSS_IMUX_B14_5->PSS0_IMUX_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_5" }, "PSS4.PSS_IMUX_B14_6->PSS0_IMUX_B14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_6" }, "PSS4.PSS_IMUX_B14_7->PSS0_IMUX_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_7" }, "PSS4.PSS_IMUX_B14_8->PSS0_IMUX_B14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_8" }, "PSS4.PSS_IMUX_B14_9->PSS0_IMUX_B14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B14_9" }, "PSS4.PSS_IMUX_B15_0->PSS0_IMUX_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_0" }, "PSS4.PSS_IMUX_B15_1->PSS0_IMUX_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_1" }, "PSS4.PSS_IMUX_B15_10->PSS0_IMUX_B15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_10" }, "PSS4.PSS_IMUX_B15_11->PSS0_IMUX_B15_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_11" }, "PSS4.PSS_IMUX_B15_12->PSS0_IMUX_B15_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_12" }, "PSS4.PSS_IMUX_B15_13->PSS0_IMUX_B15_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_13" }, "PSS4.PSS_IMUX_B15_14->PSS0_IMUX_B15_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_14" }, "PSS4.PSS_IMUX_B15_15->PSS0_IMUX_B15_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_15" }, "PSS4.PSS_IMUX_B15_16->PSS0_IMUX_B15_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_16" }, "PSS4.PSS_IMUX_B15_17->PSS0_IMUX_B15_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_17" }, "PSS4.PSS_IMUX_B15_18->PSS0_IMUX_B15_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_18" }, "PSS4.PSS_IMUX_B15_19->PSS0_IMUX_B15_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_19" }, "PSS4.PSS_IMUX_B15_2->PSS0_IMUX_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_2" }, "PSS4.PSS_IMUX_B15_3->PSS0_IMUX_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_3" }, "PSS4.PSS_IMUX_B15_4->PSS0_IMUX_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_4" }, "PSS4.PSS_IMUX_B15_5->PSS0_IMUX_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_5" }, "PSS4.PSS_IMUX_B15_6->PSS0_IMUX_B15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_6" }, "PSS4.PSS_IMUX_B15_7->PSS0_IMUX_B15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_7" }, "PSS4.PSS_IMUX_B15_8->PSS0_IMUX_B15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_8" }, "PSS4.PSS_IMUX_B15_9->PSS0_IMUX_B15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B15_9" }, "PSS4.PSS_IMUX_B16_0->PSS0_IMUX_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_0" }, "PSS4.PSS_IMUX_B16_1->PSS0_IMUX_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_1" }, "PSS4.PSS_IMUX_B16_10->PSS0_IMUX_B16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_10" }, "PSS4.PSS_IMUX_B16_11->PSS0_IMUX_B16_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_11" }, "PSS4.PSS_IMUX_B16_12->PSS0_IMUX_B16_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_12" }, "PSS4.PSS_IMUX_B16_13->PSS0_IMUX_B16_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_13" }, "PSS4.PSS_IMUX_B16_14->PSS0_IMUX_B16_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_14" }, "PSS4.PSS_IMUX_B16_15->PSS0_IMUX_B16_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_15" }, "PSS4.PSS_IMUX_B16_16->PSS0_IMUX_B16_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_16" }, "PSS4.PSS_IMUX_B16_17->PSS0_IMUX_B16_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_17" }, "PSS4.PSS_IMUX_B16_18->PSS0_IMUX_B16_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_18" }, "PSS4.PSS_IMUX_B16_19->PSS0_IMUX_B16_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_19" }, "PSS4.PSS_IMUX_B16_2->PSS0_IMUX_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_2" }, "PSS4.PSS_IMUX_B16_3->PSS0_IMUX_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_3" }, "PSS4.PSS_IMUX_B16_4->PSS0_IMUX_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_4" }, "PSS4.PSS_IMUX_B16_5->PSS0_IMUX_B16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_5" }, "PSS4.PSS_IMUX_B16_6->PSS0_IMUX_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_6" }, "PSS4.PSS_IMUX_B16_7->PSS0_IMUX_B16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_7" }, "PSS4.PSS_IMUX_B16_8->PSS0_IMUX_B16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_8" }, "PSS4.PSS_IMUX_B16_9->PSS0_IMUX_B16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B16_9" }, "PSS4.PSS_IMUX_B17_0->PSS0_IMUX_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_0" }, "PSS4.PSS_IMUX_B17_1->PSS0_IMUX_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_1" }, "PSS4.PSS_IMUX_B17_10->PSS0_IMUX_B17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_10" }, "PSS4.PSS_IMUX_B17_11->PSS0_IMUX_B17_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_11" }, "PSS4.PSS_IMUX_B17_12->PSS0_IMUX_B17_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_12" }, "PSS4.PSS_IMUX_B17_13->PSS0_IMUX_B17_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_13" }, "PSS4.PSS_IMUX_B17_14->PSS0_IMUX_B17_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_14" }, "PSS4.PSS_IMUX_B17_15->PSS0_IMUX_B17_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_15" }, "PSS4.PSS_IMUX_B17_16->PSS0_IMUX_B17_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_16" }, "PSS4.PSS_IMUX_B17_17->PSS0_IMUX_B17_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_17" }, "PSS4.PSS_IMUX_B17_18->PSS0_IMUX_B17_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_18" }, "PSS4.PSS_IMUX_B17_19->PSS0_IMUX_B17_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_19" }, "PSS4.PSS_IMUX_B17_2->PSS0_IMUX_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_2" }, "PSS4.PSS_IMUX_B17_3->PSS0_IMUX_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_3" }, "PSS4.PSS_IMUX_B17_4->PSS0_IMUX_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_4" }, "PSS4.PSS_IMUX_B17_5->PSS0_IMUX_B17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_5" }, "PSS4.PSS_IMUX_B17_6->PSS0_IMUX_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_6" }, "PSS4.PSS_IMUX_B17_7->PSS0_IMUX_B17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_7" }, "PSS4.PSS_IMUX_B17_8->PSS0_IMUX_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_8" }, "PSS4.PSS_IMUX_B17_9->PSS0_IMUX_B17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B17_9" }, "PSS4.PSS_IMUX_B18_0->PSS0_IMUX_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_0" }, "PSS4.PSS_IMUX_B18_1->PSS0_IMUX_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_1" }, "PSS4.PSS_IMUX_B18_10->PSS0_IMUX_B18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_10" }, "PSS4.PSS_IMUX_B18_11->PSS0_IMUX_B18_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_11" }, "PSS4.PSS_IMUX_B18_12->PSS0_IMUX_B18_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_12" }, "PSS4.PSS_IMUX_B18_13->PSS0_IMUX_B18_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_13" }, "PSS4.PSS_IMUX_B18_14->PSS0_IMUX_B18_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_14" }, "PSS4.PSS_IMUX_B18_15->PSS0_IMUX_B18_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_15" }, "PSS4.PSS_IMUX_B18_16->PSS0_IMUX_B18_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_16" }, "PSS4.PSS_IMUX_B18_17->PSS0_IMUX_B18_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_17" }, "PSS4.PSS_IMUX_B18_18->PSS0_IMUX_B18_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_18" }, "PSS4.PSS_IMUX_B18_19->PSS0_IMUX_B18_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_19" }, "PSS4.PSS_IMUX_B18_2->PSS0_IMUX_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_2" }, "PSS4.PSS_IMUX_B18_3->PSS0_IMUX_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_3" }, "PSS4.PSS_IMUX_B18_4->PSS0_IMUX_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_4" }, "PSS4.PSS_IMUX_B18_5->PSS0_IMUX_B18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_5" }, "PSS4.PSS_IMUX_B18_6->PSS0_IMUX_B18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_6" }, "PSS4.PSS_IMUX_B18_7->PSS0_IMUX_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_7" }, "PSS4.PSS_IMUX_B18_8->PSS0_IMUX_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_8" }, "PSS4.PSS_IMUX_B18_9->PSS0_IMUX_B18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B18_9" }, "PSS4.PSS_IMUX_B19_0->PSS0_IMUX_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_0" }, "PSS4.PSS_IMUX_B19_1->PSS0_IMUX_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_1" }, "PSS4.PSS_IMUX_B19_10->PSS0_IMUX_B19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_10" }, "PSS4.PSS_IMUX_B19_11->PSS0_IMUX_B19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_11" }, "PSS4.PSS_IMUX_B19_12->PSS0_IMUX_B19_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_12" }, "PSS4.PSS_IMUX_B19_13->PSS0_IMUX_B19_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_13" }, "PSS4.PSS_IMUX_B19_14->PSS0_IMUX_B19_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_14" }, "PSS4.PSS_IMUX_B19_15->PSS0_IMUX_B19_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_15" }, "PSS4.PSS_IMUX_B19_16->PSS0_IMUX_B19_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_16" }, "PSS4.PSS_IMUX_B19_17->PSS0_IMUX_B19_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_17" }, "PSS4.PSS_IMUX_B19_18->PSS0_IMUX_B19_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_18" }, "PSS4.PSS_IMUX_B19_19->PSS0_IMUX_B19_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_19" }, "PSS4.PSS_IMUX_B19_2->PSS0_IMUX_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_2" }, "PSS4.PSS_IMUX_B19_3->PSS0_IMUX_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_3" }, "PSS4.PSS_IMUX_B19_4->PSS0_IMUX_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_4" }, "PSS4.PSS_IMUX_B19_5->PSS0_IMUX_B19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_5" }, "PSS4.PSS_IMUX_B19_6->PSS0_IMUX_B19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_6" }, "PSS4.PSS_IMUX_B19_7->PSS0_IMUX_B19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_7" }, "PSS4.PSS_IMUX_B19_8->PSS0_IMUX_B19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_8" }, "PSS4.PSS_IMUX_B19_9->PSS0_IMUX_B19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B19_9" }, "PSS4.PSS_IMUX_B1_0->PSS0_IMUX_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_0" }, "PSS4.PSS_IMUX_B1_1->PSS0_IMUX_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_1" }, "PSS4.PSS_IMUX_B1_10->PSS0_IMUX_B1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_10" }, "PSS4.PSS_IMUX_B1_11->PSS0_IMUX_B1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_11" }, "PSS4.PSS_IMUX_B1_12->PSS0_IMUX_B1_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_12" }, "PSS4.PSS_IMUX_B1_13->PSS0_IMUX_B1_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_13" }, "PSS4.PSS_IMUX_B1_14->PSS0_IMUX_B1_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_14" }, "PSS4.PSS_IMUX_B1_15->PSS0_IMUX_B1_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_15" }, "PSS4.PSS_IMUX_B1_16->PSS0_IMUX_B1_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_16" }, "PSS4.PSS_IMUX_B1_17->PSS0_IMUX_B1_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_17" }, "PSS4.PSS_IMUX_B1_18->PSS0_IMUX_B1_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_18" }, "PSS4.PSS_IMUX_B1_19->PSS0_IMUX_B1_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_19" }, "PSS4.PSS_IMUX_B1_2->PSS0_IMUX_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_2" }, "PSS4.PSS_IMUX_B1_3->PSS0_IMUX_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_3" }, "PSS4.PSS_IMUX_B1_4->PSS0_IMUX_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_4" }, "PSS4.PSS_IMUX_B1_5->PSS0_IMUX_B1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_5" }, "PSS4.PSS_IMUX_B1_6->PSS0_IMUX_B1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_6" }, "PSS4.PSS_IMUX_B1_7->PSS0_IMUX_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_7" }, "PSS4.PSS_IMUX_B1_8->PSS0_IMUX_B1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_8" }, "PSS4.PSS_IMUX_B1_9->PSS0_IMUX_B1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B1_9" }, "PSS4.PSS_IMUX_B20_0->PSS0_IMUX_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_0" }, "PSS4.PSS_IMUX_B20_1->PSS0_IMUX_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_1" }, "PSS4.PSS_IMUX_B20_10->PSS0_IMUX_B20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_10" }, "PSS4.PSS_IMUX_B20_11->PSS0_IMUX_B20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_11" }, "PSS4.PSS_IMUX_B20_12->PSS0_IMUX_B20_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_12" }, "PSS4.PSS_IMUX_B20_13->PSS0_IMUX_B20_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_13" }, "PSS4.PSS_IMUX_B20_14->PSS0_IMUX_B20_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_14" }, "PSS4.PSS_IMUX_B20_15->PSS0_IMUX_B20_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_15" }, "PSS4.PSS_IMUX_B20_16->PSS0_IMUX_B20_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_16" }, "PSS4.PSS_IMUX_B20_17->PSS0_IMUX_B20_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_17" }, "PSS4.PSS_IMUX_B20_18->PSS0_IMUX_B20_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_18" }, "PSS4.PSS_IMUX_B20_19->PSS0_IMUX_B20_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_19" }, "PSS4.PSS_IMUX_B20_2->PSS0_IMUX_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_2" }, "PSS4.PSS_IMUX_B20_3->PSS0_IMUX_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_3" }, "PSS4.PSS_IMUX_B20_4->PSS0_IMUX_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_4" }, "PSS4.PSS_IMUX_B20_5->PSS0_IMUX_B20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_5" }, "PSS4.PSS_IMUX_B20_6->PSS0_IMUX_B20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_6" }, "PSS4.PSS_IMUX_B20_7->PSS0_IMUX_B20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_7" }, "PSS4.PSS_IMUX_B20_8->PSS0_IMUX_B20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_8" }, "PSS4.PSS_IMUX_B20_9->PSS0_IMUX_B20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B20_9" }, "PSS4.PSS_IMUX_B21_0->PSS0_IMUX_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_0" }, "PSS4.PSS_IMUX_B21_1->PSS0_IMUX_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_1" }, "PSS4.PSS_IMUX_B21_10->PSS0_IMUX_B21_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_10" }, "PSS4.PSS_IMUX_B21_11->PSS0_IMUX_B21_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_11" }, "PSS4.PSS_IMUX_B21_12->PSS0_IMUX_B21_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_12" }, "PSS4.PSS_IMUX_B21_13->PSS0_IMUX_B21_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_13" }, "PSS4.PSS_IMUX_B21_14->PSS0_IMUX_B21_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_14" }, "PSS4.PSS_IMUX_B21_15->PSS0_IMUX_B21_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_15" }, "PSS4.PSS_IMUX_B21_16->PSS0_IMUX_B21_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_16" }, "PSS4.PSS_IMUX_B21_17->PSS0_IMUX_B21_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_17" }, "PSS4.PSS_IMUX_B21_18->PSS0_IMUX_B21_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_18" }, "PSS4.PSS_IMUX_B21_19->PSS0_IMUX_B21_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_19" }, "PSS4.PSS_IMUX_B21_2->PSS0_IMUX_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_2" }, "PSS4.PSS_IMUX_B21_3->PSS0_IMUX_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_3" }, "PSS4.PSS_IMUX_B21_4->PSS0_IMUX_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_4" }, "PSS4.PSS_IMUX_B21_5->PSS0_IMUX_B21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_5" }, "PSS4.PSS_IMUX_B21_6->PSS0_IMUX_B21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_6" }, "PSS4.PSS_IMUX_B21_7->PSS0_IMUX_B21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_7" }, "PSS4.PSS_IMUX_B21_8->PSS0_IMUX_B21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_8" }, "PSS4.PSS_IMUX_B21_9->PSS0_IMUX_B21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B21_9" }, "PSS4.PSS_IMUX_B22_0->PSS0_IMUX_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_0" }, "PSS4.PSS_IMUX_B22_1->PSS0_IMUX_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_1" }, "PSS4.PSS_IMUX_B22_10->PSS0_IMUX_B22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_10" }, "PSS4.PSS_IMUX_B22_11->PSS0_IMUX_B22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_11" }, "PSS4.PSS_IMUX_B22_12->PSS0_IMUX_B22_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_12" }, "PSS4.PSS_IMUX_B22_13->PSS0_IMUX_B22_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_13" }, "PSS4.PSS_IMUX_B22_14->PSS0_IMUX_B22_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_14" }, "PSS4.PSS_IMUX_B22_15->PSS0_IMUX_B22_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_15" }, "PSS4.PSS_IMUX_B22_16->PSS0_IMUX_B22_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_16" }, "PSS4.PSS_IMUX_B22_17->PSS0_IMUX_B22_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_17" }, "PSS4.PSS_IMUX_B22_18->PSS0_IMUX_B22_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_18" }, "PSS4.PSS_IMUX_B22_19->PSS0_IMUX_B22_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_19" }, "PSS4.PSS_IMUX_B22_2->PSS0_IMUX_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_2" }, "PSS4.PSS_IMUX_B22_3->PSS0_IMUX_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_3" }, "PSS4.PSS_IMUX_B22_4->PSS0_IMUX_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_4" }, "PSS4.PSS_IMUX_B22_5->PSS0_IMUX_B22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_5" }, "PSS4.PSS_IMUX_B22_6->PSS0_IMUX_B22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_6" }, "PSS4.PSS_IMUX_B22_7->PSS0_IMUX_B22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_7" }, "PSS4.PSS_IMUX_B22_8->PSS0_IMUX_B22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_8" }, "PSS4.PSS_IMUX_B22_9->PSS0_IMUX_B22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B22_9" }, "PSS4.PSS_IMUX_B23_0->PSS0_IMUX_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_0" }, "PSS4.PSS_IMUX_B23_1->PSS0_IMUX_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_1" }, "PSS4.PSS_IMUX_B23_10->PSS0_IMUX_B23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_10" }, "PSS4.PSS_IMUX_B23_11->PSS0_IMUX_B23_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_11" }, "PSS4.PSS_IMUX_B23_12->PSS0_IMUX_B23_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_12" }, "PSS4.PSS_IMUX_B23_13->PSS0_IMUX_B23_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_13" }, "PSS4.PSS_IMUX_B23_14->PSS0_IMUX_B23_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_14" }, "PSS4.PSS_IMUX_B23_15->PSS0_IMUX_B23_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_15" }, "PSS4.PSS_IMUX_B23_16->PSS0_IMUX_B23_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_16" }, "PSS4.PSS_IMUX_B23_17->PSS0_IMUX_B23_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_17" }, "PSS4.PSS_IMUX_B23_18->PSS0_IMUX_B23_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_18" }, "PSS4.PSS_IMUX_B23_19->PSS0_IMUX_B23_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_19" }, "PSS4.PSS_IMUX_B23_2->PSS0_IMUX_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_2" }, "PSS4.PSS_IMUX_B23_3->PSS0_IMUX_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_3" }, "PSS4.PSS_IMUX_B23_4->PSS0_IMUX_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_4" }, "PSS4.PSS_IMUX_B23_5->PSS0_IMUX_B23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_5" }, "PSS4.PSS_IMUX_B23_6->PSS0_IMUX_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_6" }, "PSS4.PSS_IMUX_B23_7->PSS0_IMUX_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_7" }, "PSS4.PSS_IMUX_B23_8->PSS0_IMUX_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_8" }, "PSS4.PSS_IMUX_B23_9->PSS0_IMUX_B23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B23_9" }, "PSS4.PSS_IMUX_B24_0->PSS0_IMUX_B24_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_0" }, "PSS4.PSS_IMUX_B24_1->PSS0_IMUX_B24_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_1" }, "PSS4.PSS_IMUX_B24_10->PSS0_IMUX_B24_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_10" }, "PSS4.PSS_IMUX_B24_11->PSS0_IMUX_B24_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_11" }, "PSS4.PSS_IMUX_B24_12->PSS0_IMUX_B24_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_12" }, "PSS4.PSS_IMUX_B24_13->PSS0_IMUX_B24_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_13" }, "PSS4.PSS_IMUX_B24_14->PSS0_IMUX_B24_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_14" }, "PSS4.PSS_IMUX_B24_15->PSS0_IMUX_B24_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_15" }, "PSS4.PSS_IMUX_B24_16->PSS0_IMUX_B24_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_16" }, "PSS4.PSS_IMUX_B24_17->PSS0_IMUX_B24_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_17" }, "PSS4.PSS_IMUX_B24_18->PSS0_IMUX_B24_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_18" }, "PSS4.PSS_IMUX_B24_19->PSS0_IMUX_B24_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_19" }, "PSS4.PSS_IMUX_B24_2->PSS0_IMUX_B24_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_2" }, "PSS4.PSS_IMUX_B24_3->PSS0_IMUX_B24_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_3" }, "PSS4.PSS_IMUX_B24_4->PSS0_IMUX_B24_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_4" }, "PSS4.PSS_IMUX_B24_5->PSS0_IMUX_B24_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_5" }, "PSS4.PSS_IMUX_B24_6->PSS0_IMUX_B24_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_6" }, "PSS4.PSS_IMUX_B24_7->PSS0_IMUX_B24_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_7" }, "PSS4.PSS_IMUX_B24_8->PSS0_IMUX_B24_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_8" }, "PSS4.PSS_IMUX_B24_9->PSS0_IMUX_B24_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B24_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B24_9" }, "PSS4.PSS_IMUX_B25_0->PSS0_IMUX_B25_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_0" }, "PSS4.PSS_IMUX_B25_1->PSS0_IMUX_B25_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_1" }, "PSS4.PSS_IMUX_B25_10->PSS0_IMUX_B25_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_10" }, "PSS4.PSS_IMUX_B25_11->PSS0_IMUX_B25_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_11" }, "PSS4.PSS_IMUX_B25_12->PSS0_IMUX_B25_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_12" }, "PSS4.PSS_IMUX_B25_13->PSS0_IMUX_B25_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_13" }, "PSS4.PSS_IMUX_B25_14->PSS0_IMUX_B25_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_14" }, "PSS4.PSS_IMUX_B25_15->PSS0_IMUX_B25_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_15" }, "PSS4.PSS_IMUX_B25_16->PSS0_IMUX_B25_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_16" }, "PSS4.PSS_IMUX_B25_17->PSS0_IMUX_B25_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_17" }, "PSS4.PSS_IMUX_B25_18->PSS0_IMUX_B25_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_18" }, "PSS4.PSS_IMUX_B25_19->PSS0_IMUX_B25_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_19" }, "PSS4.PSS_IMUX_B25_2->PSS0_IMUX_B25_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_2" }, "PSS4.PSS_IMUX_B25_3->PSS0_IMUX_B25_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_3" }, "PSS4.PSS_IMUX_B25_4->PSS0_IMUX_B25_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_4" }, "PSS4.PSS_IMUX_B25_5->PSS0_IMUX_B25_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_5" }, "PSS4.PSS_IMUX_B25_6->PSS0_IMUX_B25_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_6" }, "PSS4.PSS_IMUX_B25_7->PSS0_IMUX_B25_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_7" }, "PSS4.PSS_IMUX_B25_8->PSS0_IMUX_B25_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_8" }, "PSS4.PSS_IMUX_B25_9->PSS0_IMUX_B25_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B25_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B25_9" }, "PSS4.PSS_IMUX_B26_0->PSS0_IMUX_B26_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_0" }, "PSS4.PSS_IMUX_B26_1->PSS0_IMUX_B26_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_1" }, "PSS4.PSS_IMUX_B26_10->PSS0_IMUX_B26_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_10" }, "PSS4.PSS_IMUX_B26_11->PSS0_IMUX_B26_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_11" }, "PSS4.PSS_IMUX_B26_12->PSS0_IMUX_B26_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_12" }, "PSS4.PSS_IMUX_B26_13->PSS0_IMUX_B26_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_13" }, "PSS4.PSS_IMUX_B26_14->PSS0_IMUX_B26_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_14" }, "PSS4.PSS_IMUX_B26_15->PSS0_IMUX_B26_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_15" }, "PSS4.PSS_IMUX_B26_16->PSS0_IMUX_B26_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_16" }, "PSS4.PSS_IMUX_B26_17->PSS0_IMUX_B26_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_17" }, "PSS4.PSS_IMUX_B26_18->PSS0_IMUX_B26_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_18" }, "PSS4.PSS_IMUX_B26_19->PSS0_IMUX_B26_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_19" }, "PSS4.PSS_IMUX_B26_2->PSS0_IMUX_B26_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_2" }, "PSS4.PSS_IMUX_B26_3->PSS0_IMUX_B26_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_3" }, "PSS4.PSS_IMUX_B26_4->PSS0_IMUX_B26_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_4" }, "PSS4.PSS_IMUX_B26_5->PSS0_IMUX_B26_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_5" }, "PSS4.PSS_IMUX_B26_6->PSS0_IMUX_B26_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_6" }, "PSS4.PSS_IMUX_B26_7->PSS0_IMUX_B26_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_7" }, "PSS4.PSS_IMUX_B26_8->PSS0_IMUX_B26_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_8" }, "PSS4.PSS_IMUX_B26_9->PSS0_IMUX_B26_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B26_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B26_9" }, "PSS4.PSS_IMUX_B27_0->PSS0_IMUX_B27_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_0" }, "PSS4.PSS_IMUX_B27_1->PSS0_IMUX_B27_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_1" }, "PSS4.PSS_IMUX_B27_10->PSS0_IMUX_B27_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_10" }, "PSS4.PSS_IMUX_B27_11->PSS0_IMUX_B27_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_11" }, "PSS4.PSS_IMUX_B27_12->PSS0_IMUX_B27_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_12" }, "PSS4.PSS_IMUX_B27_13->PSS0_IMUX_B27_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_13" }, "PSS4.PSS_IMUX_B27_14->PSS0_IMUX_B27_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_14" }, "PSS4.PSS_IMUX_B27_15->PSS0_IMUX_B27_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_15" }, "PSS4.PSS_IMUX_B27_16->PSS0_IMUX_B27_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_16" }, "PSS4.PSS_IMUX_B27_17->PSS0_IMUX_B27_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_17" }, "PSS4.PSS_IMUX_B27_18->PSS0_IMUX_B27_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_18" }, "PSS4.PSS_IMUX_B27_19->PSS0_IMUX_B27_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_19" }, "PSS4.PSS_IMUX_B27_2->PSS0_IMUX_B27_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_2" }, "PSS4.PSS_IMUX_B27_3->PSS0_IMUX_B27_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_3" }, "PSS4.PSS_IMUX_B27_4->PSS0_IMUX_B27_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_4" }, "PSS4.PSS_IMUX_B27_5->PSS0_IMUX_B27_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_5" }, "PSS4.PSS_IMUX_B27_6->PSS0_IMUX_B27_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_6" }, "PSS4.PSS_IMUX_B27_7->PSS0_IMUX_B27_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_7" }, "PSS4.PSS_IMUX_B27_8->PSS0_IMUX_B27_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_8" }, "PSS4.PSS_IMUX_B27_9->PSS0_IMUX_B27_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B27_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B27_9" }, "PSS4.PSS_IMUX_B28_0->PSS0_IMUX_B28_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_0" }, "PSS4.PSS_IMUX_B28_1->PSS0_IMUX_B28_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_1" }, "PSS4.PSS_IMUX_B28_10->PSS0_IMUX_B28_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_10" }, "PSS4.PSS_IMUX_B28_11->PSS0_IMUX_B28_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_11" }, "PSS4.PSS_IMUX_B28_12->PSS0_IMUX_B28_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_12" }, "PSS4.PSS_IMUX_B28_13->PSS0_IMUX_B28_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_13" }, "PSS4.PSS_IMUX_B28_14->PSS0_IMUX_B28_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_14" }, "PSS4.PSS_IMUX_B28_15->PSS0_IMUX_B28_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_15" }, "PSS4.PSS_IMUX_B28_16->PSS0_IMUX_B28_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_16" }, "PSS4.PSS_IMUX_B28_17->PSS0_IMUX_B28_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_17" }, "PSS4.PSS_IMUX_B28_18->PSS0_IMUX_B28_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_18" }, "PSS4.PSS_IMUX_B28_19->PSS0_IMUX_B28_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_19" }, "PSS4.PSS_IMUX_B28_2->PSS0_IMUX_B28_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_2" }, "PSS4.PSS_IMUX_B28_3->PSS0_IMUX_B28_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_3" }, "PSS4.PSS_IMUX_B28_4->PSS0_IMUX_B28_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_4" }, "PSS4.PSS_IMUX_B28_5->PSS0_IMUX_B28_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_5" }, "PSS4.PSS_IMUX_B28_6->PSS0_IMUX_B28_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_6" }, "PSS4.PSS_IMUX_B28_7->PSS0_IMUX_B28_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_7" }, "PSS4.PSS_IMUX_B28_8->PSS0_IMUX_B28_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_8" }, "PSS4.PSS_IMUX_B28_9->PSS0_IMUX_B28_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B28_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B28_9" }, "PSS4.PSS_IMUX_B29_0->PSS0_IMUX_B29_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_0" }, "PSS4.PSS_IMUX_B29_1->PSS0_IMUX_B29_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_1" }, "PSS4.PSS_IMUX_B29_10->PSS0_IMUX_B29_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_10" }, "PSS4.PSS_IMUX_B29_11->PSS0_IMUX_B29_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_11" }, "PSS4.PSS_IMUX_B29_12->PSS0_IMUX_B29_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_12" }, "PSS4.PSS_IMUX_B29_13->PSS0_IMUX_B29_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_13" }, "PSS4.PSS_IMUX_B29_14->PSS0_IMUX_B29_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_14" }, "PSS4.PSS_IMUX_B29_15->PSS0_IMUX_B29_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_15" }, "PSS4.PSS_IMUX_B29_16->PSS0_IMUX_B29_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_16" }, "PSS4.PSS_IMUX_B29_17->PSS0_IMUX_B29_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_17" }, "PSS4.PSS_IMUX_B29_18->PSS0_IMUX_B29_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_18" }, "PSS4.PSS_IMUX_B29_19->PSS0_IMUX_B29_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_19" }, "PSS4.PSS_IMUX_B29_2->PSS0_IMUX_B29_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_2" }, "PSS4.PSS_IMUX_B29_3->PSS0_IMUX_B29_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_3" }, "PSS4.PSS_IMUX_B29_4->PSS0_IMUX_B29_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_4" }, "PSS4.PSS_IMUX_B29_5->PSS0_IMUX_B29_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_5" }, "PSS4.PSS_IMUX_B29_6->PSS0_IMUX_B29_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_6" }, "PSS4.PSS_IMUX_B29_7->PSS0_IMUX_B29_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_7" }, "PSS4.PSS_IMUX_B29_8->PSS0_IMUX_B29_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_8" }, "PSS4.PSS_IMUX_B29_9->PSS0_IMUX_B29_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B29_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B29_9" }, "PSS4.PSS_IMUX_B2_0->PSS0_IMUX_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_0" }, "PSS4.PSS_IMUX_B2_1->PSS0_IMUX_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_1" }, "PSS4.PSS_IMUX_B2_10->PSS0_IMUX_B2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_10" }, "PSS4.PSS_IMUX_B2_11->PSS0_IMUX_B2_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_11" }, "PSS4.PSS_IMUX_B2_12->PSS0_IMUX_B2_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_12" }, "PSS4.PSS_IMUX_B2_13->PSS0_IMUX_B2_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_13" }, "PSS4.PSS_IMUX_B2_14->PSS0_IMUX_B2_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_14" }, "PSS4.PSS_IMUX_B2_15->PSS0_IMUX_B2_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_15" }, "PSS4.PSS_IMUX_B2_16->PSS0_IMUX_B2_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_16" }, "PSS4.PSS_IMUX_B2_17->PSS0_IMUX_B2_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_17" }, "PSS4.PSS_IMUX_B2_18->PSS0_IMUX_B2_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_18" }, "PSS4.PSS_IMUX_B2_19->PSS0_IMUX_B2_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_19" }, "PSS4.PSS_IMUX_B2_2->PSS0_IMUX_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_2" }, "PSS4.PSS_IMUX_B2_3->PSS0_IMUX_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_3" }, "PSS4.PSS_IMUX_B2_4->PSS0_IMUX_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_4" }, "PSS4.PSS_IMUX_B2_5->PSS0_IMUX_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_5" }, "PSS4.PSS_IMUX_B2_6->PSS0_IMUX_B2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_6" }, "PSS4.PSS_IMUX_B2_7->PSS0_IMUX_B2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_7" }, "PSS4.PSS_IMUX_B2_8->PSS0_IMUX_B2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_8" }, "PSS4.PSS_IMUX_B2_9->PSS0_IMUX_B2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B2_9" }, "PSS4.PSS_IMUX_B30_0->PSS0_IMUX_B30_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_0" }, "PSS4.PSS_IMUX_B30_1->PSS0_IMUX_B30_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_1" }, "PSS4.PSS_IMUX_B30_10->PSS0_IMUX_B30_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_10" }, "PSS4.PSS_IMUX_B30_11->PSS0_IMUX_B30_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_11" }, "PSS4.PSS_IMUX_B30_12->PSS0_IMUX_B30_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_12" }, "PSS4.PSS_IMUX_B30_13->PSS0_IMUX_B30_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_13" }, "PSS4.PSS_IMUX_B30_14->PSS0_IMUX_B30_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_14" }, "PSS4.PSS_IMUX_B30_15->PSS0_IMUX_B30_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_15" }, "PSS4.PSS_IMUX_B30_16->PSS0_IMUX_B30_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_16" }, "PSS4.PSS_IMUX_B30_17->PSS0_IMUX_B30_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_17" }, "PSS4.PSS_IMUX_B30_18->PSS0_IMUX_B30_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_18" }, "PSS4.PSS_IMUX_B30_19->PSS0_IMUX_B30_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_19" }, "PSS4.PSS_IMUX_B30_2->PSS0_IMUX_B30_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_2" }, "PSS4.PSS_IMUX_B30_3->PSS0_IMUX_B30_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_3" }, "PSS4.PSS_IMUX_B30_4->PSS0_IMUX_B30_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_4" }, "PSS4.PSS_IMUX_B30_5->PSS0_IMUX_B30_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_5" }, "PSS4.PSS_IMUX_B30_6->PSS0_IMUX_B30_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_6" }, "PSS4.PSS_IMUX_B30_7->PSS0_IMUX_B30_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_7" }, "PSS4.PSS_IMUX_B30_8->PSS0_IMUX_B30_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_8" }, "PSS4.PSS_IMUX_B30_9->PSS0_IMUX_B30_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B30_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B30_9" }, "PSS4.PSS_IMUX_B31_0->PSS0_IMUX_B31_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_0" }, "PSS4.PSS_IMUX_B31_1->PSS0_IMUX_B31_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_1" }, "PSS4.PSS_IMUX_B31_10->PSS0_IMUX_B31_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_10" }, "PSS4.PSS_IMUX_B31_11->PSS0_IMUX_B31_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_11" }, "PSS4.PSS_IMUX_B31_12->PSS0_IMUX_B31_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_12" }, "PSS4.PSS_IMUX_B31_13->PSS0_IMUX_B31_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_13" }, "PSS4.PSS_IMUX_B31_14->PSS0_IMUX_B31_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_14" }, "PSS4.PSS_IMUX_B31_15->PSS0_IMUX_B31_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_15" }, "PSS4.PSS_IMUX_B31_16->PSS0_IMUX_B31_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_16" }, "PSS4.PSS_IMUX_B31_17->PSS0_IMUX_B31_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_17" }, "PSS4.PSS_IMUX_B31_18->PSS0_IMUX_B31_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_18" }, "PSS4.PSS_IMUX_B31_19->PSS0_IMUX_B31_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_19" }, "PSS4.PSS_IMUX_B31_2->PSS0_IMUX_B31_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_2" }, "PSS4.PSS_IMUX_B31_3->PSS0_IMUX_B31_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_3" }, "PSS4.PSS_IMUX_B31_4->PSS0_IMUX_B31_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_4" }, "PSS4.PSS_IMUX_B31_5->PSS0_IMUX_B31_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_5" }, "PSS4.PSS_IMUX_B31_6->PSS0_IMUX_B31_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_6" }, "PSS4.PSS_IMUX_B31_7->PSS0_IMUX_B31_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_7" }, "PSS4.PSS_IMUX_B31_8->PSS0_IMUX_B31_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_8" }, "PSS4.PSS_IMUX_B31_9->PSS0_IMUX_B31_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B31_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B31_9" }, "PSS4.PSS_IMUX_B32_0->PSS0_IMUX_B32_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_0" }, "PSS4.PSS_IMUX_B32_1->PSS0_IMUX_B32_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_1" }, "PSS4.PSS_IMUX_B32_10->PSS0_IMUX_B32_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_10" }, "PSS4.PSS_IMUX_B32_11->PSS0_IMUX_B32_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_11" }, "PSS4.PSS_IMUX_B32_12->PSS0_IMUX_B32_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_12" }, "PSS4.PSS_IMUX_B32_13->PSS0_IMUX_B32_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_13" }, "PSS4.PSS_IMUX_B32_14->PSS0_IMUX_B32_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_14" }, "PSS4.PSS_IMUX_B32_15->PSS0_IMUX_B32_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_15" }, "PSS4.PSS_IMUX_B32_16->PSS0_IMUX_B32_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_16" }, "PSS4.PSS_IMUX_B32_17->PSS0_IMUX_B32_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_17" }, "PSS4.PSS_IMUX_B32_18->PSS0_IMUX_B32_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_18" }, "PSS4.PSS_IMUX_B32_19->PSS0_IMUX_B32_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_19" }, "PSS4.PSS_IMUX_B32_2->PSS0_IMUX_B32_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_2" }, "PSS4.PSS_IMUX_B32_3->PSS0_IMUX_B32_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_3" }, "PSS4.PSS_IMUX_B32_4->PSS0_IMUX_B32_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_4" }, "PSS4.PSS_IMUX_B32_5->PSS0_IMUX_B32_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_5" }, "PSS4.PSS_IMUX_B32_6->PSS0_IMUX_B32_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_6" }, "PSS4.PSS_IMUX_B32_7->PSS0_IMUX_B32_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_7" }, "PSS4.PSS_IMUX_B32_8->PSS0_IMUX_B32_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_8" }, "PSS4.PSS_IMUX_B32_9->PSS0_IMUX_B32_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B32_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B32_9" }, "PSS4.PSS_IMUX_B33_0->PSS0_IMUX_B33_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_0" }, "PSS4.PSS_IMUX_B33_1->PSS0_IMUX_B33_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_1" }, "PSS4.PSS_IMUX_B33_10->PSS0_IMUX_B33_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_10" }, "PSS4.PSS_IMUX_B33_11->PSS0_IMUX_B33_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_11" }, "PSS4.PSS_IMUX_B33_12->PSS0_IMUX_B33_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_12" }, "PSS4.PSS_IMUX_B33_13->PSS0_IMUX_B33_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_13" }, "PSS4.PSS_IMUX_B33_14->PSS0_IMUX_B33_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_14" }, "PSS4.PSS_IMUX_B33_15->PSS0_IMUX_B33_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_15" }, "PSS4.PSS_IMUX_B33_16->PSS0_IMUX_B33_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_16" }, "PSS4.PSS_IMUX_B33_17->PSS0_IMUX_B33_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_17" }, "PSS4.PSS_IMUX_B33_18->PSS0_IMUX_B33_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_18" }, "PSS4.PSS_IMUX_B33_19->PSS0_IMUX_B33_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_19" }, "PSS4.PSS_IMUX_B33_2->PSS0_IMUX_B33_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_2" }, "PSS4.PSS_IMUX_B33_3->PSS0_IMUX_B33_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_3" }, "PSS4.PSS_IMUX_B33_4->PSS0_IMUX_B33_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_4" }, "PSS4.PSS_IMUX_B33_5->PSS0_IMUX_B33_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_5" }, "PSS4.PSS_IMUX_B33_6->PSS0_IMUX_B33_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_6" }, "PSS4.PSS_IMUX_B33_7->PSS0_IMUX_B33_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_7" }, "PSS4.PSS_IMUX_B33_8->PSS0_IMUX_B33_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_8" }, "PSS4.PSS_IMUX_B33_9->PSS0_IMUX_B33_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B33_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B33_9" }, "PSS4.PSS_IMUX_B34_0->PSS0_IMUX_B34_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_0" }, "PSS4.PSS_IMUX_B34_1->PSS0_IMUX_B34_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_1" }, "PSS4.PSS_IMUX_B34_10->PSS0_IMUX_B34_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_10" }, "PSS4.PSS_IMUX_B34_11->PSS0_IMUX_B34_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_11" }, "PSS4.PSS_IMUX_B34_12->PSS0_IMUX_B34_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_12" }, "PSS4.PSS_IMUX_B34_13->PSS0_IMUX_B34_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_13" }, "PSS4.PSS_IMUX_B34_14->PSS0_IMUX_B34_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_14" }, "PSS4.PSS_IMUX_B34_15->PSS0_IMUX_B34_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_15" }, "PSS4.PSS_IMUX_B34_16->PSS0_IMUX_B34_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_16" }, "PSS4.PSS_IMUX_B34_17->PSS0_IMUX_B34_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_17" }, "PSS4.PSS_IMUX_B34_18->PSS0_IMUX_B34_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_18" }, "PSS4.PSS_IMUX_B34_19->PSS0_IMUX_B34_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_19" }, "PSS4.PSS_IMUX_B34_2->PSS0_IMUX_B34_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_2" }, "PSS4.PSS_IMUX_B34_3->PSS0_IMUX_B34_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_3" }, "PSS4.PSS_IMUX_B34_4->PSS0_IMUX_B34_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_4" }, "PSS4.PSS_IMUX_B34_5->PSS0_IMUX_B34_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_5" }, "PSS4.PSS_IMUX_B34_6->PSS0_IMUX_B34_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_6" }, "PSS4.PSS_IMUX_B34_7->PSS0_IMUX_B34_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_7" }, "PSS4.PSS_IMUX_B34_8->PSS0_IMUX_B34_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_8" }, "PSS4.PSS_IMUX_B34_9->PSS0_IMUX_B34_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B34_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B34_9" }, "PSS4.PSS_IMUX_B35_0->PSS0_IMUX_B35_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_0" }, "PSS4.PSS_IMUX_B35_1->PSS0_IMUX_B35_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_1" }, "PSS4.PSS_IMUX_B35_10->PSS0_IMUX_B35_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_10" }, "PSS4.PSS_IMUX_B35_11->PSS0_IMUX_B35_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_11" }, "PSS4.PSS_IMUX_B35_12->PSS0_IMUX_B35_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_12" }, "PSS4.PSS_IMUX_B35_13->PSS0_IMUX_B35_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_13" }, "PSS4.PSS_IMUX_B35_14->PSS0_IMUX_B35_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_14" }, "PSS4.PSS_IMUX_B35_15->PSS0_IMUX_B35_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_15" }, "PSS4.PSS_IMUX_B35_16->PSS0_IMUX_B35_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_16" }, "PSS4.PSS_IMUX_B35_17->PSS0_IMUX_B35_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_17" }, "PSS4.PSS_IMUX_B35_18->PSS0_IMUX_B35_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_18" }, "PSS4.PSS_IMUX_B35_19->PSS0_IMUX_B35_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_19" }, "PSS4.PSS_IMUX_B35_2->PSS0_IMUX_B35_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_2" }, "PSS4.PSS_IMUX_B35_3->PSS0_IMUX_B35_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_3" }, "PSS4.PSS_IMUX_B35_4->PSS0_IMUX_B35_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_4" }, "PSS4.PSS_IMUX_B35_5->PSS0_IMUX_B35_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_5" }, "PSS4.PSS_IMUX_B35_6->PSS0_IMUX_B35_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_6" }, "PSS4.PSS_IMUX_B35_7->PSS0_IMUX_B35_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_7" }, "PSS4.PSS_IMUX_B35_8->PSS0_IMUX_B35_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_8" }, "PSS4.PSS_IMUX_B35_9->PSS0_IMUX_B35_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B35_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B35_9" }, "PSS4.PSS_IMUX_B36_0->PSS0_IMUX_B36_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_0" }, "PSS4.PSS_IMUX_B36_1->PSS0_IMUX_B36_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_1" }, "PSS4.PSS_IMUX_B36_10->PSS0_IMUX_B36_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_10" }, "PSS4.PSS_IMUX_B36_11->PSS0_IMUX_B36_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_11" }, "PSS4.PSS_IMUX_B36_12->PSS0_IMUX_B36_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_12" }, "PSS4.PSS_IMUX_B36_13->PSS0_IMUX_B36_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_13" }, "PSS4.PSS_IMUX_B36_14->PSS0_IMUX_B36_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_14" }, "PSS4.PSS_IMUX_B36_15->PSS0_IMUX_B36_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_15" }, "PSS4.PSS_IMUX_B36_16->PSS0_IMUX_B36_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_16" }, "PSS4.PSS_IMUX_B36_17->PSS0_IMUX_B36_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_17" }, "PSS4.PSS_IMUX_B36_18->PSS0_IMUX_B36_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_18" }, "PSS4.PSS_IMUX_B36_19->PSS0_IMUX_B36_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_19" }, "PSS4.PSS_IMUX_B36_2->PSS0_IMUX_B36_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_2" }, "PSS4.PSS_IMUX_B36_3->PSS0_IMUX_B36_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_3" }, "PSS4.PSS_IMUX_B36_4->PSS0_IMUX_B36_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_4" }, "PSS4.PSS_IMUX_B36_5->PSS0_IMUX_B36_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_5" }, "PSS4.PSS_IMUX_B36_6->PSS0_IMUX_B36_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_6" }, "PSS4.PSS_IMUX_B36_7->PSS0_IMUX_B36_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_7" }, "PSS4.PSS_IMUX_B36_8->PSS0_IMUX_B36_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_8" }, "PSS4.PSS_IMUX_B36_9->PSS0_IMUX_B36_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B36_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B36_9" }, "PSS4.PSS_IMUX_B37_0->PSS0_IMUX_B37_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_0" }, "PSS4.PSS_IMUX_B37_1->PSS0_IMUX_B37_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_1" }, "PSS4.PSS_IMUX_B37_10->PSS0_IMUX_B37_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_10" }, "PSS4.PSS_IMUX_B37_11->PSS0_IMUX_B37_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_11" }, "PSS4.PSS_IMUX_B37_12->PSS0_IMUX_B37_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_12" }, "PSS4.PSS_IMUX_B37_13->PSS0_IMUX_B37_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_13" }, "PSS4.PSS_IMUX_B37_14->PSS0_IMUX_B37_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_14" }, "PSS4.PSS_IMUX_B37_15->PSS0_IMUX_B37_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_15" }, "PSS4.PSS_IMUX_B37_16->PSS0_IMUX_B37_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_16" }, "PSS4.PSS_IMUX_B37_17->PSS0_IMUX_B37_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_17" }, "PSS4.PSS_IMUX_B37_18->PSS0_IMUX_B37_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_18" }, "PSS4.PSS_IMUX_B37_19->PSS0_IMUX_B37_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_19" }, "PSS4.PSS_IMUX_B37_2->PSS0_IMUX_B37_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_2" }, "PSS4.PSS_IMUX_B37_3->PSS0_IMUX_B37_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_3" }, "PSS4.PSS_IMUX_B37_4->PSS0_IMUX_B37_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_4" }, "PSS4.PSS_IMUX_B37_5->PSS0_IMUX_B37_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_5" }, "PSS4.PSS_IMUX_B37_6->PSS0_IMUX_B37_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_6" }, "PSS4.PSS_IMUX_B37_7->PSS0_IMUX_B37_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_7" }, "PSS4.PSS_IMUX_B37_8->PSS0_IMUX_B37_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_8" }, "PSS4.PSS_IMUX_B37_9->PSS0_IMUX_B37_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B37_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B37_9" }, "PSS4.PSS_IMUX_B38_0->PSS0_IMUX_B38_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_0" }, "PSS4.PSS_IMUX_B38_1->PSS0_IMUX_B38_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_1" }, "PSS4.PSS_IMUX_B38_10->PSS0_IMUX_B38_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_10" }, "PSS4.PSS_IMUX_B38_11->PSS0_IMUX_B38_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_11" }, "PSS4.PSS_IMUX_B38_12->PSS0_IMUX_B38_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_12" }, "PSS4.PSS_IMUX_B38_13->PSS0_IMUX_B38_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_13" }, "PSS4.PSS_IMUX_B38_14->PSS0_IMUX_B38_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_14" }, "PSS4.PSS_IMUX_B38_15->PSS0_IMUX_B38_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_15" }, "PSS4.PSS_IMUX_B38_16->PSS0_IMUX_B38_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_16" }, "PSS4.PSS_IMUX_B38_17->PSS0_IMUX_B38_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_17" }, "PSS4.PSS_IMUX_B38_18->PSS0_IMUX_B38_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_18" }, "PSS4.PSS_IMUX_B38_19->PSS0_IMUX_B38_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_19" }, "PSS4.PSS_IMUX_B38_2->PSS0_IMUX_B38_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_2" }, "PSS4.PSS_IMUX_B38_3->PSS0_IMUX_B38_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_3" }, "PSS4.PSS_IMUX_B38_4->PSS0_IMUX_B38_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_4" }, "PSS4.PSS_IMUX_B38_5->PSS0_IMUX_B38_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_5" }, "PSS4.PSS_IMUX_B38_6->PSS0_IMUX_B38_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_6" }, "PSS4.PSS_IMUX_B38_7->PSS0_IMUX_B38_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_7" }, "PSS4.PSS_IMUX_B38_8->PSS0_IMUX_B38_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_8" }, "PSS4.PSS_IMUX_B38_9->PSS0_IMUX_B38_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B38_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B38_9" }, "PSS4.PSS_IMUX_B39_0->PSS0_IMUX_B39_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_0" }, "PSS4.PSS_IMUX_B39_1->PSS0_IMUX_B39_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_1" }, "PSS4.PSS_IMUX_B39_10->PSS0_IMUX_B39_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_10" }, "PSS4.PSS_IMUX_B39_11->PSS0_IMUX_B39_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_11" }, "PSS4.PSS_IMUX_B39_12->PSS0_IMUX_B39_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_12" }, "PSS4.PSS_IMUX_B39_13->PSS0_IMUX_B39_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_13" }, "PSS4.PSS_IMUX_B39_14->PSS0_IMUX_B39_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_14" }, "PSS4.PSS_IMUX_B39_15->PSS0_IMUX_B39_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_15" }, "PSS4.PSS_IMUX_B39_16->PSS0_IMUX_B39_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_16" }, "PSS4.PSS_IMUX_B39_17->PSS0_IMUX_B39_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_17" }, "PSS4.PSS_IMUX_B39_18->PSS0_IMUX_B39_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_18" }, "PSS4.PSS_IMUX_B39_19->PSS0_IMUX_B39_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_19" }, "PSS4.PSS_IMUX_B39_2->PSS0_IMUX_B39_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_2" }, "PSS4.PSS_IMUX_B39_3->PSS0_IMUX_B39_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_3" }, "PSS4.PSS_IMUX_B39_4->PSS0_IMUX_B39_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_4" }, "PSS4.PSS_IMUX_B39_5->PSS0_IMUX_B39_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_5" }, "PSS4.PSS_IMUX_B39_6->PSS0_IMUX_B39_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_6" }, "PSS4.PSS_IMUX_B39_7->PSS0_IMUX_B39_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_7" }, "PSS4.PSS_IMUX_B39_8->PSS0_IMUX_B39_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_8" }, "PSS4.PSS_IMUX_B39_9->PSS0_IMUX_B39_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B39_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B39_9" }, "PSS4.PSS_IMUX_B3_0->PSS0_IMUX_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_0" }, "PSS4.PSS_IMUX_B3_1->PSS0_IMUX_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_1" }, "PSS4.PSS_IMUX_B3_10->PSS0_IMUX_B3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_10" }, "PSS4.PSS_IMUX_B3_11->PSS0_IMUX_B3_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_11" }, "PSS4.PSS_IMUX_B3_12->PSS0_IMUX_B3_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_12" }, "PSS4.PSS_IMUX_B3_13->PSS0_IMUX_B3_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_13" }, "PSS4.PSS_IMUX_B3_14->PSS0_IMUX_B3_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_14" }, "PSS4.PSS_IMUX_B3_15->PSS0_IMUX_B3_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_15" }, "PSS4.PSS_IMUX_B3_16->PSS0_IMUX_B3_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_16" }, "PSS4.PSS_IMUX_B3_17->PSS0_IMUX_B3_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_17" }, "PSS4.PSS_IMUX_B3_18->PSS0_IMUX_B3_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_18" }, "PSS4.PSS_IMUX_B3_19->PSS0_IMUX_B3_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_19" }, "PSS4.PSS_IMUX_B3_2->PSS0_IMUX_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_2" }, "PSS4.PSS_IMUX_B3_3->PSS0_IMUX_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_3" }, "PSS4.PSS_IMUX_B3_4->PSS0_IMUX_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_4" }, "PSS4.PSS_IMUX_B3_5->PSS0_IMUX_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_5" }, "PSS4.PSS_IMUX_B3_6->PSS0_IMUX_B3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_6" }, "PSS4.PSS_IMUX_B3_7->PSS0_IMUX_B3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_7" }, "PSS4.PSS_IMUX_B3_8->PSS0_IMUX_B3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_8" }, "PSS4.PSS_IMUX_B3_9->PSS0_IMUX_B3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B3_9" }, "PSS4.PSS_IMUX_B40_0->PSS0_IMUX_B40_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_0" }, "PSS4.PSS_IMUX_B40_1->PSS0_IMUX_B40_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_1" }, "PSS4.PSS_IMUX_B40_10->PSS0_IMUX_B40_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_10" }, "PSS4.PSS_IMUX_B40_11->PSS0_IMUX_B40_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_11" }, "PSS4.PSS_IMUX_B40_12->PSS0_IMUX_B40_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_12" }, "PSS4.PSS_IMUX_B40_13->PSS0_IMUX_B40_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_13" }, "PSS4.PSS_IMUX_B40_14->PSS0_IMUX_B40_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_14" }, "PSS4.PSS_IMUX_B40_15->PSS0_IMUX_B40_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_15" }, "PSS4.PSS_IMUX_B40_16->PSS0_IMUX_B40_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_16" }, "PSS4.PSS_IMUX_B40_17->PSS0_IMUX_B40_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_17" }, "PSS4.PSS_IMUX_B40_18->PSS0_IMUX_B40_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_18" }, "PSS4.PSS_IMUX_B40_19->PSS0_IMUX_B40_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_19" }, "PSS4.PSS_IMUX_B40_2->PSS0_IMUX_B40_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_2" }, "PSS4.PSS_IMUX_B40_3->PSS0_IMUX_B40_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_3" }, "PSS4.PSS_IMUX_B40_4->PSS0_IMUX_B40_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_4" }, "PSS4.PSS_IMUX_B40_5->PSS0_IMUX_B40_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_5" }, "PSS4.PSS_IMUX_B40_6->PSS0_IMUX_B40_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_6" }, "PSS4.PSS_IMUX_B40_7->PSS0_IMUX_B40_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_7" }, "PSS4.PSS_IMUX_B40_8->PSS0_IMUX_B40_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_8" }, "PSS4.PSS_IMUX_B40_9->PSS0_IMUX_B40_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B40_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B40_9" }, "PSS4.PSS_IMUX_B41_0->PSS0_IMUX_B41_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_0" }, "PSS4.PSS_IMUX_B41_1->PSS0_IMUX_B41_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_1" }, "PSS4.PSS_IMUX_B41_10->PSS0_IMUX_B41_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_10" }, "PSS4.PSS_IMUX_B41_11->PSS0_IMUX_B41_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_11" }, "PSS4.PSS_IMUX_B41_12->PSS0_IMUX_B41_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_12" }, "PSS4.PSS_IMUX_B41_13->PSS0_IMUX_B41_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_13" }, "PSS4.PSS_IMUX_B41_14->PSS0_IMUX_B41_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_14" }, "PSS4.PSS_IMUX_B41_15->PSS0_IMUX_B41_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_15" }, "PSS4.PSS_IMUX_B41_16->PSS0_IMUX_B41_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_16" }, "PSS4.PSS_IMUX_B41_17->PSS0_IMUX_B41_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_17" }, "PSS4.PSS_IMUX_B41_18->PSS0_IMUX_B41_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_18" }, "PSS4.PSS_IMUX_B41_19->PSS0_IMUX_B41_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_19" }, "PSS4.PSS_IMUX_B41_2->PSS0_IMUX_B41_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_2" }, "PSS4.PSS_IMUX_B41_3->PSS0_IMUX_B41_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_3" }, "PSS4.PSS_IMUX_B41_4->PSS0_IMUX_B41_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_4" }, "PSS4.PSS_IMUX_B41_5->PSS0_IMUX_B41_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_5" }, "PSS4.PSS_IMUX_B41_6->PSS0_IMUX_B41_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_6" }, "PSS4.PSS_IMUX_B41_7->PSS0_IMUX_B41_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_7" }, "PSS4.PSS_IMUX_B41_8->PSS0_IMUX_B41_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_8" }, "PSS4.PSS_IMUX_B41_9->PSS0_IMUX_B41_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B41_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B41_9" }, "PSS4.PSS_IMUX_B42_0->PSS0_IMUX_B42_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_0" }, "PSS4.PSS_IMUX_B42_1->PSS0_IMUX_B42_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_1" }, "PSS4.PSS_IMUX_B42_10->PSS0_IMUX_B42_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_10" }, "PSS4.PSS_IMUX_B42_11->PSS0_IMUX_B42_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_11" }, "PSS4.PSS_IMUX_B42_12->PSS0_IMUX_B42_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_12" }, "PSS4.PSS_IMUX_B42_13->PSS0_IMUX_B42_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_13" }, "PSS4.PSS_IMUX_B42_14->PSS0_IMUX_B42_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_14" }, "PSS4.PSS_IMUX_B42_15->PSS0_IMUX_B42_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_15" }, "PSS4.PSS_IMUX_B42_16->PSS0_IMUX_B42_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_16" }, "PSS4.PSS_IMUX_B42_17->PSS0_IMUX_B42_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_17" }, "PSS4.PSS_IMUX_B42_18->PSS0_IMUX_B42_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_18" }, "PSS4.PSS_IMUX_B42_19->PSS0_IMUX_B42_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_19" }, "PSS4.PSS_IMUX_B42_2->PSS0_IMUX_B42_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_2" }, "PSS4.PSS_IMUX_B42_3->PSS0_IMUX_B42_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_3" }, "PSS4.PSS_IMUX_B42_4->PSS0_IMUX_B42_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_4" }, "PSS4.PSS_IMUX_B42_5->PSS0_IMUX_B42_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_5" }, "PSS4.PSS_IMUX_B42_6->PSS0_IMUX_B42_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_6" }, "PSS4.PSS_IMUX_B42_7->PSS0_IMUX_B42_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_7" }, "PSS4.PSS_IMUX_B42_8->PSS0_IMUX_B42_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_8" }, "PSS4.PSS_IMUX_B42_9->PSS0_IMUX_B42_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B42_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B42_9" }, "PSS4.PSS_IMUX_B43_0->PSS0_IMUX_B43_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_0" }, "PSS4.PSS_IMUX_B43_1->PSS0_IMUX_B43_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_1" }, "PSS4.PSS_IMUX_B43_10->PSS0_IMUX_B43_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_10" }, "PSS4.PSS_IMUX_B43_11->PSS0_IMUX_B43_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_11" }, "PSS4.PSS_IMUX_B43_12->PSS0_IMUX_B43_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_12" }, "PSS4.PSS_IMUX_B43_13->PSS0_IMUX_B43_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_13" }, "PSS4.PSS_IMUX_B43_14->PSS0_IMUX_B43_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_14" }, "PSS4.PSS_IMUX_B43_15->PSS0_IMUX_B43_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_15" }, "PSS4.PSS_IMUX_B43_16->PSS0_IMUX_B43_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_16" }, "PSS4.PSS_IMUX_B43_17->PSS0_IMUX_B43_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_17" }, "PSS4.PSS_IMUX_B43_18->PSS0_IMUX_B43_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_18" }, "PSS4.PSS_IMUX_B43_19->PSS0_IMUX_B43_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_19" }, "PSS4.PSS_IMUX_B43_2->PSS0_IMUX_B43_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_2" }, "PSS4.PSS_IMUX_B43_3->PSS0_IMUX_B43_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_3" }, "PSS4.PSS_IMUX_B43_4->PSS0_IMUX_B43_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_4" }, "PSS4.PSS_IMUX_B43_5->PSS0_IMUX_B43_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_5" }, "PSS4.PSS_IMUX_B43_6->PSS0_IMUX_B43_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_6" }, "PSS4.PSS_IMUX_B43_7->PSS0_IMUX_B43_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_7" }, "PSS4.PSS_IMUX_B43_8->PSS0_IMUX_B43_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_8" }, "PSS4.PSS_IMUX_B43_9->PSS0_IMUX_B43_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B43_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B43_9" }, "PSS4.PSS_IMUX_B44_0->PSS0_IMUX_B44_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_0" }, "PSS4.PSS_IMUX_B44_1->PSS0_IMUX_B44_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_1" }, "PSS4.PSS_IMUX_B44_10->PSS0_IMUX_B44_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_10" }, "PSS4.PSS_IMUX_B44_11->PSS0_IMUX_B44_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_11" }, "PSS4.PSS_IMUX_B44_12->PSS0_IMUX_B44_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_12" }, "PSS4.PSS_IMUX_B44_13->PSS0_IMUX_B44_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_13" }, "PSS4.PSS_IMUX_B44_14->PSS0_IMUX_B44_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_14" }, "PSS4.PSS_IMUX_B44_15->PSS0_IMUX_B44_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_15" }, "PSS4.PSS_IMUX_B44_16->PSS0_IMUX_B44_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_16" }, "PSS4.PSS_IMUX_B44_17->PSS0_IMUX_B44_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_17" }, "PSS4.PSS_IMUX_B44_18->PSS0_IMUX_B44_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_18" }, "PSS4.PSS_IMUX_B44_19->PSS0_IMUX_B44_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_19" }, "PSS4.PSS_IMUX_B44_2->PSS0_IMUX_B44_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_2" }, "PSS4.PSS_IMUX_B44_3->PSS0_IMUX_B44_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_3" }, "PSS4.PSS_IMUX_B44_4->PSS0_IMUX_B44_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_4" }, "PSS4.PSS_IMUX_B44_5->PSS0_IMUX_B44_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_5" }, "PSS4.PSS_IMUX_B44_6->PSS0_IMUX_B44_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_6" }, "PSS4.PSS_IMUX_B44_7->PSS0_IMUX_B44_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_7" }, "PSS4.PSS_IMUX_B44_8->PSS0_IMUX_B44_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_8" }, "PSS4.PSS_IMUX_B44_9->PSS0_IMUX_B44_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B44_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B44_9" }, "PSS4.PSS_IMUX_B45_0->PSS0_IMUX_B45_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_0" }, "PSS4.PSS_IMUX_B45_1->PSS0_IMUX_B45_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_1" }, "PSS4.PSS_IMUX_B45_10->PSS0_IMUX_B45_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_10" }, "PSS4.PSS_IMUX_B45_11->PSS0_IMUX_B45_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_11" }, "PSS4.PSS_IMUX_B45_12->PSS0_IMUX_B45_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_12" }, "PSS4.PSS_IMUX_B45_13->PSS0_IMUX_B45_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_13" }, "PSS4.PSS_IMUX_B45_14->PSS0_IMUX_B45_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_14" }, "PSS4.PSS_IMUX_B45_15->PSS0_IMUX_B45_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_15" }, "PSS4.PSS_IMUX_B45_16->PSS0_IMUX_B45_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_16" }, "PSS4.PSS_IMUX_B45_17->PSS0_IMUX_B45_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_17" }, "PSS4.PSS_IMUX_B45_18->PSS0_IMUX_B45_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_18" }, "PSS4.PSS_IMUX_B45_19->PSS0_IMUX_B45_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_19" }, "PSS4.PSS_IMUX_B45_2->PSS0_IMUX_B45_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_2" }, "PSS4.PSS_IMUX_B45_3->PSS0_IMUX_B45_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_3" }, "PSS4.PSS_IMUX_B45_4->PSS0_IMUX_B45_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_4" }, "PSS4.PSS_IMUX_B45_5->PSS0_IMUX_B45_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_5" }, "PSS4.PSS_IMUX_B45_6->PSS0_IMUX_B45_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_6" }, "PSS4.PSS_IMUX_B45_7->PSS0_IMUX_B45_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_7" }, "PSS4.PSS_IMUX_B45_8->PSS0_IMUX_B45_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_8" }, "PSS4.PSS_IMUX_B45_9->PSS0_IMUX_B45_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B45_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B45_9" }, "PSS4.PSS_IMUX_B46_0->PSS0_IMUX_B46_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_0" }, "PSS4.PSS_IMUX_B46_1->PSS0_IMUX_B46_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_1" }, "PSS4.PSS_IMUX_B46_10->PSS0_IMUX_B46_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_10" }, "PSS4.PSS_IMUX_B46_11->PSS0_IMUX_B46_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_11" }, "PSS4.PSS_IMUX_B46_12->PSS0_IMUX_B46_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_12" }, "PSS4.PSS_IMUX_B46_13->PSS0_IMUX_B46_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_13" }, "PSS4.PSS_IMUX_B46_14->PSS0_IMUX_B46_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_14" }, "PSS4.PSS_IMUX_B46_15->PSS0_IMUX_B46_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_15" }, "PSS4.PSS_IMUX_B46_16->PSS0_IMUX_B46_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_16" }, "PSS4.PSS_IMUX_B46_17->PSS0_IMUX_B46_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_17" }, "PSS4.PSS_IMUX_B46_18->PSS0_IMUX_B46_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_18" }, "PSS4.PSS_IMUX_B46_19->PSS0_IMUX_B46_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_19" }, "PSS4.PSS_IMUX_B46_2->PSS0_IMUX_B46_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_2" }, "PSS4.PSS_IMUX_B46_3->PSS0_IMUX_B46_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_3" }, "PSS4.PSS_IMUX_B46_4->PSS0_IMUX_B46_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_4" }, "PSS4.PSS_IMUX_B46_5->PSS0_IMUX_B46_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_5" }, "PSS4.PSS_IMUX_B46_6->PSS0_IMUX_B46_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_6" }, "PSS4.PSS_IMUX_B46_7->PSS0_IMUX_B46_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_7" }, "PSS4.PSS_IMUX_B46_8->PSS0_IMUX_B46_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_8" }, "PSS4.PSS_IMUX_B46_9->PSS0_IMUX_B46_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B46_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B46_9" }, "PSS4.PSS_IMUX_B47_0->PSS0_IMUX_B47_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_0" }, "PSS4.PSS_IMUX_B47_1->PSS0_IMUX_B47_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_1" }, "PSS4.PSS_IMUX_B47_10->PSS0_IMUX_B47_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_10" }, "PSS4.PSS_IMUX_B47_11->PSS0_IMUX_B47_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_11" }, "PSS4.PSS_IMUX_B47_12->PSS0_IMUX_B47_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_12" }, "PSS4.PSS_IMUX_B47_13->PSS0_IMUX_B47_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_13" }, "PSS4.PSS_IMUX_B47_14->PSS0_IMUX_B47_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_14" }, "PSS4.PSS_IMUX_B47_15->PSS0_IMUX_B47_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_15" }, "PSS4.PSS_IMUX_B47_16->PSS0_IMUX_B47_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_16" }, "PSS4.PSS_IMUX_B47_17->PSS0_IMUX_B47_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_17" }, "PSS4.PSS_IMUX_B47_18->PSS0_IMUX_B47_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_18" }, "PSS4.PSS_IMUX_B47_19->PSS0_IMUX_B47_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_19" }, "PSS4.PSS_IMUX_B47_2->PSS0_IMUX_B47_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_2" }, "PSS4.PSS_IMUX_B47_3->PSS0_IMUX_B47_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_3" }, "PSS4.PSS_IMUX_B47_4->PSS0_IMUX_B47_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_4" }, "PSS4.PSS_IMUX_B47_5->PSS0_IMUX_B47_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_5" }, "PSS4.PSS_IMUX_B47_6->PSS0_IMUX_B47_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_6" }, "PSS4.PSS_IMUX_B47_7->PSS0_IMUX_B47_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_7" }, "PSS4.PSS_IMUX_B47_8->PSS0_IMUX_B47_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_8" }, "PSS4.PSS_IMUX_B47_9->PSS0_IMUX_B47_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B47_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B47_9" }, "PSS4.PSS_IMUX_B4_0->PSS0_IMUX_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_0" }, "PSS4.PSS_IMUX_B4_1->PSS0_IMUX_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_1" }, "PSS4.PSS_IMUX_B4_10->PSS0_IMUX_B4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_10" }, "PSS4.PSS_IMUX_B4_11->PSS0_IMUX_B4_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_11" }, "PSS4.PSS_IMUX_B4_12->PSS0_IMUX_B4_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_12" }, "PSS4.PSS_IMUX_B4_13->PSS0_IMUX_B4_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_13" }, "PSS4.PSS_IMUX_B4_14->PSS0_IMUX_B4_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_14" }, "PSS4.PSS_IMUX_B4_15->PSS0_IMUX_B4_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_15" }, "PSS4.PSS_IMUX_B4_16->PSS0_IMUX_B4_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_16" }, "PSS4.PSS_IMUX_B4_17->PSS0_IMUX_B4_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_17" }, "PSS4.PSS_IMUX_B4_18->PSS0_IMUX_B4_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_18" }, "PSS4.PSS_IMUX_B4_19->PSS0_IMUX_B4_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_19" }, "PSS4.PSS_IMUX_B4_2->PSS0_IMUX_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_2" }, "PSS4.PSS_IMUX_B4_3->PSS0_IMUX_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_3" }, "PSS4.PSS_IMUX_B4_4->PSS0_IMUX_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_4" }, "PSS4.PSS_IMUX_B4_5->PSS0_IMUX_B4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_5" }, "PSS4.PSS_IMUX_B4_6->PSS0_IMUX_B4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_6" }, "PSS4.PSS_IMUX_B4_7->PSS0_IMUX_B4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_7" }, "PSS4.PSS_IMUX_B4_8->PSS0_IMUX_B4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_8" }, "PSS4.PSS_IMUX_B4_9->PSS0_IMUX_B4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B4_9" }, "PSS4.PSS_IMUX_B5_0->PSS0_IMUX_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_0" }, "PSS4.PSS_IMUX_B5_1->PSS0_IMUX_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_1" }, "PSS4.PSS_IMUX_B5_10->PSS0_IMUX_B5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_10" }, "PSS4.PSS_IMUX_B5_11->PSS0_IMUX_B5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_11" }, "PSS4.PSS_IMUX_B5_12->PSS0_IMUX_B5_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_12" }, "PSS4.PSS_IMUX_B5_13->PSS0_IMUX_B5_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_13" }, "PSS4.PSS_IMUX_B5_14->PSS0_IMUX_B5_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_14" }, "PSS4.PSS_IMUX_B5_15->PSS0_IMUX_B5_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_15" }, "PSS4.PSS_IMUX_B5_16->PSS0_IMUX_B5_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_16" }, "PSS4.PSS_IMUX_B5_17->PSS0_IMUX_B5_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_17" }, "PSS4.PSS_IMUX_B5_18->PSS0_IMUX_B5_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_18" }, "PSS4.PSS_IMUX_B5_19->PSS0_IMUX_B5_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_19" }, "PSS4.PSS_IMUX_B5_2->PSS0_IMUX_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_2" }, "PSS4.PSS_IMUX_B5_3->PSS0_IMUX_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_3" }, "PSS4.PSS_IMUX_B5_4->PSS0_IMUX_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_4" }, "PSS4.PSS_IMUX_B5_5->PSS0_IMUX_B5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_5" }, "PSS4.PSS_IMUX_B5_6->PSS0_IMUX_B5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_6" }, "PSS4.PSS_IMUX_B5_7->PSS0_IMUX_B5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_7" }, "PSS4.PSS_IMUX_B5_8->PSS0_IMUX_B5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_8" }, "PSS4.PSS_IMUX_B5_9->PSS0_IMUX_B5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B5_9" }, "PSS4.PSS_IMUX_B6_0->PSS0_IMUX_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_0" }, "PSS4.PSS_IMUX_B6_1->PSS0_IMUX_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_1" }, "PSS4.PSS_IMUX_B6_10->PSS0_IMUX_B6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_10" }, "PSS4.PSS_IMUX_B6_11->PSS0_IMUX_B6_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_11" }, "PSS4.PSS_IMUX_B6_12->PSS0_IMUX_B6_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_12" }, "PSS4.PSS_IMUX_B6_13->PSS0_IMUX_B6_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_13" }, "PSS4.PSS_IMUX_B6_14->PSS0_IMUX_B6_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_14" }, "PSS4.PSS_IMUX_B6_15->PSS0_IMUX_B6_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_15" }, "PSS4.PSS_IMUX_B6_16->PSS0_IMUX_B6_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_16" }, "PSS4.PSS_IMUX_B6_17->PSS0_IMUX_B6_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_17" }, "PSS4.PSS_IMUX_B6_18->PSS0_IMUX_B6_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_18" }, "PSS4.PSS_IMUX_B6_19->PSS0_IMUX_B6_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_19" }, "PSS4.PSS_IMUX_B6_2->PSS0_IMUX_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_2" }, "PSS4.PSS_IMUX_B6_3->PSS0_IMUX_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_3" }, "PSS4.PSS_IMUX_B6_4->PSS0_IMUX_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_4" }, "PSS4.PSS_IMUX_B6_5->PSS0_IMUX_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_5" }, "PSS4.PSS_IMUX_B6_6->PSS0_IMUX_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_6" }, "PSS4.PSS_IMUX_B6_7->PSS0_IMUX_B6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_7" }, "PSS4.PSS_IMUX_B6_8->PSS0_IMUX_B6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_8" }, "PSS4.PSS_IMUX_B6_9->PSS0_IMUX_B6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B6_9" }, "PSS4.PSS_IMUX_B7_0->PSS0_IMUX_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_0" }, "PSS4.PSS_IMUX_B7_1->PSS0_IMUX_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_1" }, "PSS4.PSS_IMUX_B7_10->PSS0_IMUX_B7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_10" }, "PSS4.PSS_IMUX_B7_11->PSS0_IMUX_B7_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_11" }, "PSS4.PSS_IMUX_B7_12->PSS0_IMUX_B7_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_12" }, "PSS4.PSS_IMUX_B7_13->PSS0_IMUX_B7_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_13" }, "PSS4.PSS_IMUX_B7_14->PSS0_IMUX_B7_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_14" }, "PSS4.PSS_IMUX_B7_15->PSS0_IMUX_B7_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_15" }, "PSS4.PSS_IMUX_B7_16->PSS0_IMUX_B7_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_16" }, "PSS4.PSS_IMUX_B7_17->PSS0_IMUX_B7_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_17" }, "PSS4.PSS_IMUX_B7_18->PSS0_IMUX_B7_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_18" }, "PSS4.PSS_IMUX_B7_19->PSS0_IMUX_B7_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_19" }, "PSS4.PSS_IMUX_B7_2->PSS0_IMUX_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_2" }, "PSS4.PSS_IMUX_B7_3->PSS0_IMUX_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_3" }, "PSS4.PSS_IMUX_B7_4->PSS0_IMUX_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_4" }, "PSS4.PSS_IMUX_B7_5->PSS0_IMUX_B7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_5" }, "PSS4.PSS_IMUX_B7_6->PSS0_IMUX_B7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_6" }, "PSS4.PSS_IMUX_B7_7->PSS0_IMUX_B7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_7" }, "PSS4.PSS_IMUX_B7_8->PSS0_IMUX_B7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_8" }, "PSS4.PSS_IMUX_B7_9->PSS0_IMUX_B7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B7_9" }, "PSS4.PSS_IMUX_B8_0->PSS0_IMUX_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_0" }, "PSS4.PSS_IMUX_B8_1->PSS0_IMUX_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_1" }, "PSS4.PSS_IMUX_B8_10->PSS0_IMUX_B8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_10" }, "PSS4.PSS_IMUX_B8_11->PSS0_IMUX_B8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_11" }, "PSS4.PSS_IMUX_B8_12->PSS0_IMUX_B8_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_12" }, "PSS4.PSS_IMUX_B8_13->PSS0_IMUX_B8_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_13" }, "PSS4.PSS_IMUX_B8_14->PSS0_IMUX_B8_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_14" }, "PSS4.PSS_IMUX_B8_15->PSS0_IMUX_B8_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_15" }, "PSS4.PSS_IMUX_B8_16->PSS0_IMUX_B8_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_16" }, "PSS4.PSS_IMUX_B8_17->PSS0_IMUX_B8_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_17" }, "PSS4.PSS_IMUX_B8_18->PSS0_IMUX_B8_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_18" }, "PSS4.PSS_IMUX_B8_19->PSS0_IMUX_B8_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_19" }, "PSS4.PSS_IMUX_B8_2->PSS0_IMUX_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_2" }, "PSS4.PSS_IMUX_B8_3->PSS0_IMUX_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_3" }, "PSS4.PSS_IMUX_B8_4->PSS0_IMUX_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_4" }, "PSS4.PSS_IMUX_B8_5->PSS0_IMUX_B8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_5" }, "PSS4.PSS_IMUX_B8_6->PSS0_IMUX_B8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_6" }, "PSS4.PSS_IMUX_B8_7->PSS0_IMUX_B8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_7" }, "PSS4.PSS_IMUX_B8_8->PSS0_IMUX_B8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_8" }, "PSS4.PSS_IMUX_B8_9->PSS0_IMUX_B8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B8_9" }, "PSS4.PSS_IMUX_B9_0->PSS0_IMUX_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_0" }, "PSS4.PSS_IMUX_B9_1->PSS0_IMUX_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_1" }, "PSS4.PSS_IMUX_B9_10->PSS0_IMUX_B9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_10" }, "PSS4.PSS_IMUX_B9_11->PSS0_IMUX_B9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_11" }, "PSS4.PSS_IMUX_B9_12->PSS0_IMUX_B9_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_12" }, "PSS4.PSS_IMUX_B9_13->PSS0_IMUX_B9_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_13" }, "PSS4.PSS_IMUX_B9_14->PSS0_IMUX_B9_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_14" }, "PSS4.PSS_IMUX_B9_15->PSS0_IMUX_B9_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_15" }, "PSS4.PSS_IMUX_B9_16->PSS0_IMUX_B9_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_16" }, "PSS4.PSS_IMUX_B9_17->PSS0_IMUX_B9_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_17" }, "PSS4.PSS_IMUX_B9_18->PSS0_IMUX_B9_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_18" }, "PSS4.PSS_IMUX_B9_19->PSS0_IMUX_B9_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_19" }, "PSS4.PSS_IMUX_B9_2->PSS0_IMUX_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_2" }, "PSS4.PSS_IMUX_B9_3->PSS0_IMUX_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_3" }, "PSS4.PSS_IMUX_B9_4->PSS0_IMUX_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_4" }, "PSS4.PSS_IMUX_B9_5->PSS0_IMUX_B9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_5" }, "PSS4.PSS_IMUX_B9_6->PSS0_IMUX_B9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_6" }, "PSS4.PSS_IMUX_B9_7->PSS0_IMUX_B9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_7" }, "PSS4.PSS_IMUX_B9_8->PSS0_IMUX_B9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_8" }, "PSS4.PSS_IMUX_B9_9->PSS0_IMUX_B9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PSS0_IMUX_B9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PSS_IMUX_B9_9" } }, "sites": [], "tile_type": "PSS4", - "wires": [ - "PSS0_CLK_B0_0", - "PSS0_CLK_B0_1", - "PSS0_CLK_B0_10", - "PSS0_CLK_B0_11", - "PSS0_CLK_B0_12", - "PSS0_CLK_B0_13", - "PSS0_CLK_B0_14", - "PSS0_CLK_B0_15", - "PSS0_CLK_B0_16", - "PSS0_CLK_B0_17", - "PSS0_CLK_B0_18", - "PSS0_CLK_B0_19", - "PSS0_CLK_B0_2", - "PSS0_CLK_B0_3", - "PSS0_CLK_B0_4", - "PSS0_CLK_B0_5", - "PSS0_CLK_B0_6", - "PSS0_CLK_B0_7", - "PSS0_CLK_B0_8", - "PSS0_CLK_B0_9", - "PSS0_CLK_B1_0", - "PSS0_CLK_B1_1", - "PSS0_CLK_B1_10", - "PSS0_CLK_B1_11", - "PSS0_CLK_B1_12", - "PSS0_CLK_B1_13", - "PSS0_CLK_B1_14", - "PSS0_CLK_B1_15", - "PSS0_CLK_B1_16", - "PSS0_CLK_B1_17", - "PSS0_CLK_B1_18", - "PSS0_CLK_B1_19", - "PSS0_CLK_B1_2", - "PSS0_CLK_B1_3", - "PSS0_CLK_B1_4", - "PSS0_CLK_B1_5", - "PSS0_CLK_B1_6", - "PSS0_CLK_B1_7", - "PSS0_CLK_B1_8", - "PSS0_CLK_B1_9", - "PSS0_IMUX_B0_0", - "PSS0_IMUX_B0_1", - "PSS0_IMUX_B0_10", - "PSS0_IMUX_B0_11", - "PSS0_IMUX_B0_12", - "PSS0_IMUX_B0_13", - "PSS0_IMUX_B0_14", - "PSS0_IMUX_B0_15", - "PSS0_IMUX_B0_16", - "PSS0_IMUX_B0_17", - "PSS0_IMUX_B0_18", - "PSS0_IMUX_B0_19", - "PSS0_IMUX_B0_2", - "PSS0_IMUX_B0_3", - "PSS0_IMUX_B0_4", - "PSS0_IMUX_B0_5", - "PSS0_IMUX_B0_6", - "PSS0_IMUX_B0_7", - "PSS0_IMUX_B0_8", - "PSS0_IMUX_B0_9", - "PSS0_IMUX_B10_0", - "PSS0_IMUX_B10_1", - "PSS0_IMUX_B10_10", - "PSS0_IMUX_B10_11", - "PSS0_IMUX_B10_12", - "PSS0_IMUX_B10_13", - "PSS0_IMUX_B10_14", - "PSS0_IMUX_B10_15", - "PSS0_IMUX_B10_16", - "PSS0_IMUX_B10_17", - "PSS0_IMUX_B10_18", - "PSS0_IMUX_B10_19", - "PSS0_IMUX_B10_2", - "PSS0_IMUX_B10_3", - "PSS0_IMUX_B10_4", - "PSS0_IMUX_B10_5", - "PSS0_IMUX_B10_6", - "PSS0_IMUX_B10_7", - "PSS0_IMUX_B10_8", - "PSS0_IMUX_B10_9", - "PSS0_IMUX_B11_0", - "PSS0_IMUX_B11_1", - "PSS0_IMUX_B11_10", - "PSS0_IMUX_B11_11", - "PSS0_IMUX_B11_12", - "PSS0_IMUX_B11_13", - "PSS0_IMUX_B11_14", - "PSS0_IMUX_B11_15", - "PSS0_IMUX_B11_16", - "PSS0_IMUX_B11_17", - "PSS0_IMUX_B11_18", - "PSS0_IMUX_B11_19", - "PSS0_IMUX_B11_2", - "PSS0_IMUX_B11_3", - "PSS0_IMUX_B11_4", - "PSS0_IMUX_B11_5", - "PSS0_IMUX_B11_6", - "PSS0_IMUX_B11_7", - "PSS0_IMUX_B11_8", - "PSS0_IMUX_B11_9", - "PSS0_IMUX_B12_0", - "PSS0_IMUX_B12_1", - "PSS0_IMUX_B12_10", - "PSS0_IMUX_B12_11", - "PSS0_IMUX_B12_12", - "PSS0_IMUX_B12_13", - "PSS0_IMUX_B12_14", - "PSS0_IMUX_B12_15", - "PSS0_IMUX_B12_16", - "PSS0_IMUX_B12_17", - "PSS0_IMUX_B12_18", - "PSS0_IMUX_B12_19", - "PSS0_IMUX_B12_2", - "PSS0_IMUX_B12_3", - "PSS0_IMUX_B12_4", - "PSS0_IMUX_B12_5", - "PSS0_IMUX_B12_6", - "PSS0_IMUX_B12_7", - "PSS0_IMUX_B12_8", - "PSS0_IMUX_B12_9", - "PSS0_IMUX_B13_0", - "PSS0_IMUX_B13_1", - "PSS0_IMUX_B13_10", - "PSS0_IMUX_B13_11", - "PSS0_IMUX_B13_12", - "PSS0_IMUX_B13_13", - "PSS0_IMUX_B13_14", - "PSS0_IMUX_B13_15", - "PSS0_IMUX_B13_16", - "PSS0_IMUX_B13_17", - "PSS0_IMUX_B13_18", - "PSS0_IMUX_B13_19", - "PSS0_IMUX_B13_2", - "PSS0_IMUX_B13_3", - "PSS0_IMUX_B13_4", - "PSS0_IMUX_B13_5", - "PSS0_IMUX_B13_6", - "PSS0_IMUX_B13_7", - "PSS0_IMUX_B13_8", - "PSS0_IMUX_B13_9", - "PSS0_IMUX_B14_0", - "PSS0_IMUX_B14_1", - "PSS0_IMUX_B14_10", - "PSS0_IMUX_B14_11", - "PSS0_IMUX_B14_12", - "PSS0_IMUX_B14_13", - "PSS0_IMUX_B14_14", - "PSS0_IMUX_B14_15", - "PSS0_IMUX_B14_16", - "PSS0_IMUX_B14_17", - "PSS0_IMUX_B14_18", - "PSS0_IMUX_B14_19", - "PSS0_IMUX_B14_2", - "PSS0_IMUX_B14_3", - "PSS0_IMUX_B14_4", - "PSS0_IMUX_B14_5", - "PSS0_IMUX_B14_6", - "PSS0_IMUX_B14_7", - "PSS0_IMUX_B14_8", - "PSS0_IMUX_B14_9", - "PSS0_IMUX_B15_0", - "PSS0_IMUX_B15_1", - "PSS0_IMUX_B15_10", - "PSS0_IMUX_B15_11", - "PSS0_IMUX_B15_12", - "PSS0_IMUX_B15_13", - "PSS0_IMUX_B15_14", - "PSS0_IMUX_B15_15", - "PSS0_IMUX_B15_16", - "PSS0_IMUX_B15_17", - "PSS0_IMUX_B15_18", - "PSS0_IMUX_B15_19", - "PSS0_IMUX_B15_2", - "PSS0_IMUX_B15_3", - "PSS0_IMUX_B15_4", - "PSS0_IMUX_B15_5", - "PSS0_IMUX_B15_6", - "PSS0_IMUX_B15_7", - "PSS0_IMUX_B15_8", - "PSS0_IMUX_B15_9", - "PSS0_IMUX_B16_0", - "PSS0_IMUX_B16_1", - "PSS0_IMUX_B16_10", - "PSS0_IMUX_B16_11", - "PSS0_IMUX_B16_12", - "PSS0_IMUX_B16_13", - "PSS0_IMUX_B16_14", - "PSS0_IMUX_B16_15", - "PSS0_IMUX_B16_16", - "PSS0_IMUX_B16_17", - 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"PSS0_IMUX_B39_8", - "PSS0_IMUX_B39_9", - "PSS0_IMUX_B3_0", - "PSS0_IMUX_B3_1", - "PSS0_IMUX_B3_10", - "PSS0_IMUX_B3_11", - "PSS0_IMUX_B3_12", - "PSS0_IMUX_B3_13", - "PSS0_IMUX_B3_14", - "PSS0_IMUX_B3_15", - "PSS0_IMUX_B3_16", - "PSS0_IMUX_B3_17", - "PSS0_IMUX_B3_18", - "PSS0_IMUX_B3_19", - "PSS0_IMUX_B3_2", - "PSS0_IMUX_B3_3", - "PSS0_IMUX_B3_4", - "PSS0_IMUX_B3_5", - "PSS0_IMUX_B3_6", - "PSS0_IMUX_B3_7", - "PSS0_IMUX_B3_8", - "PSS0_IMUX_B3_9", - "PSS0_IMUX_B40_0", - "PSS0_IMUX_B40_1", - "PSS0_IMUX_B40_10", - "PSS0_IMUX_B40_11", - "PSS0_IMUX_B40_12", - "PSS0_IMUX_B40_13", - "PSS0_IMUX_B40_14", - "PSS0_IMUX_B40_15", - "PSS0_IMUX_B40_16", - "PSS0_IMUX_B40_17", - "PSS0_IMUX_B40_18", - "PSS0_IMUX_B40_19", - "PSS0_IMUX_B40_2", - "PSS0_IMUX_B40_3", - "PSS0_IMUX_B40_4", - "PSS0_IMUX_B40_5", - "PSS0_IMUX_B40_6", - "PSS0_IMUX_B40_7", - "PSS0_IMUX_B40_8", - "PSS0_IMUX_B40_9", - "PSS0_IMUX_B41_0", - "PSS0_IMUX_B41_1", - "PSS0_IMUX_B41_10", - "PSS0_IMUX_B41_11", - "PSS0_IMUX_B41_12", - "PSS0_IMUX_B41_13", - "PSS0_IMUX_B41_14", - "PSS0_IMUX_B41_15", - "PSS0_IMUX_B41_16", - "PSS0_IMUX_B41_17", - "PSS0_IMUX_B41_18", - "PSS0_IMUX_B41_19", - "PSS0_IMUX_B41_2", - "PSS0_IMUX_B41_3", - "PSS0_IMUX_B41_4", - "PSS0_IMUX_B41_5", - "PSS0_IMUX_B41_6", - "PSS0_IMUX_B41_7", - "PSS0_IMUX_B41_8", - "PSS0_IMUX_B41_9", - "PSS0_IMUX_B42_0", - "PSS0_IMUX_B42_1", - "PSS0_IMUX_B42_10", - "PSS0_IMUX_B42_11", - "PSS0_IMUX_B42_12", - "PSS0_IMUX_B42_13", - "PSS0_IMUX_B42_14", - "PSS0_IMUX_B42_15", - "PSS0_IMUX_B42_16", - "PSS0_IMUX_B42_17", - "PSS0_IMUX_B42_18", - "PSS0_IMUX_B42_19", - "PSS0_IMUX_B42_2", - "PSS0_IMUX_B42_3", - "PSS0_IMUX_B42_4", - "PSS0_IMUX_B42_5", - "PSS0_IMUX_B42_6", - "PSS0_IMUX_B42_7", - "PSS0_IMUX_B42_8", - "PSS0_IMUX_B42_9", - "PSS0_IMUX_B43_0", - "PSS0_IMUX_B43_1", - "PSS0_IMUX_B43_10", - "PSS0_IMUX_B43_11", - "PSS0_IMUX_B43_12", - "PSS0_IMUX_B43_13", - "PSS0_IMUX_B43_14", - "PSS0_IMUX_B43_15", - "PSS0_IMUX_B43_16", - "PSS0_IMUX_B43_17", - "PSS0_IMUX_B43_18", - "PSS0_IMUX_B43_19", - "PSS0_IMUX_B43_2", - "PSS0_IMUX_B43_3", - "PSS0_IMUX_B43_4", - "PSS0_IMUX_B43_5", - "PSS0_IMUX_B43_6", - "PSS0_IMUX_B43_7", - "PSS0_IMUX_B43_8", - "PSS0_IMUX_B43_9", - "PSS0_IMUX_B44_0", - "PSS0_IMUX_B44_1", - "PSS0_IMUX_B44_10", - "PSS0_IMUX_B44_11", - "PSS0_IMUX_B44_12", - "PSS0_IMUX_B44_13", - "PSS0_IMUX_B44_14", - "PSS0_IMUX_B44_15", - "PSS0_IMUX_B44_16", - "PSS0_IMUX_B44_17", - "PSS0_IMUX_B44_18", - "PSS0_IMUX_B44_19", - "PSS0_IMUX_B44_2", - "PSS0_IMUX_B44_3", - "PSS0_IMUX_B44_4", - "PSS0_IMUX_B44_5", - "PSS0_IMUX_B44_6", - "PSS0_IMUX_B44_7", - "PSS0_IMUX_B44_8", - "PSS0_IMUX_B44_9", - "PSS0_IMUX_B45_0", - "PSS0_IMUX_B45_1", - "PSS0_IMUX_B45_10", - "PSS0_IMUX_B45_11", - "PSS0_IMUX_B45_12", - "PSS0_IMUX_B45_13", - "PSS0_IMUX_B45_14", - "PSS0_IMUX_B45_15", - "PSS0_IMUX_B45_16", - "PSS0_IMUX_B45_17", - "PSS0_IMUX_B45_18", - "PSS0_IMUX_B45_19", - "PSS0_IMUX_B45_2", - "PSS0_IMUX_B45_3", - "PSS0_IMUX_B45_4", - "PSS0_IMUX_B45_5", - "PSS0_IMUX_B45_6", - "PSS0_IMUX_B45_7", - "PSS0_IMUX_B45_8", - "PSS0_IMUX_B45_9", - "PSS0_IMUX_B46_0", - "PSS0_IMUX_B46_1", - "PSS0_IMUX_B46_10", - "PSS0_IMUX_B46_11", - "PSS0_IMUX_B46_12", - "PSS0_IMUX_B46_13", - "PSS0_IMUX_B46_14", - "PSS0_IMUX_B46_15", - "PSS0_IMUX_B46_16", - "PSS0_IMUX_B46_17", - "PSS0_IMUX_B46_18", - "PSS0_IMUX_B46_19", - "PSS0_IMUX_B46_2", - "PSS0_IMUX_B46_3", - "PSS0_IMUX_B46_4", - "PSS0_IMUX_B46_5", - "PSS0_IMUX_B46_6", - "PSS0_IMUX_B46_7", - "PSS0_IMUX_B46_8", - "PSS0_IMUX_B46_9", - "PSS0_IMUX_B47_0", - "PSS0_IMUX_B47_1", - "PSS0_IMUX_B47_10", - "PSS0_IMUX_B47_11", - "PSS0_IMUX_B47_12", - "PSS0_IMUX_B47_13", - "PSS0_IMUX_B47_14", - "PSS0_IMUX_B47_15", - "PSS0_IMUX_B47_16", - "PSS0_IMUX_B47_17", - "PSS0_IMUX_B47_18", - "PSS0_IMUX_B47_19", - "PSS0_IMUX_B47_2", - "PSS0_IMUX_B47_3", - "PSS0_IMUX_B47_4", - "PSS0_IMUX_B47_5", - "PSS0_IMUX_B47_6", - "PSS0_IMUX_B47_7", - "PSS0_IMUX_B47_8", - "PSS0_IMUX_B47_9", - "PSS0_IMUX_B4_0", - "PSS0_IMUX_B4_1", - "PSS0_IMUX_B4_10", - "PSS0_IMUX_B4_11", - "PSS0_IMUX_B4_12", - "PSS0_IMUX_B4_13", - "PSS0_IMUX_B4_14", - "PSS0_IMUX_B4_15", - "PSS0_IMUX_B4_16", - "PSS0_IMUX_B4_17", - "PSS0_IMUX_B4_18", - "PSS0_IMUX_B4_19", - "PSS0_IMUX_B4_2", - "PSS0_IMUX_B4_3", - "PSS0_IMUX_B4_4", - "PSS0_IMUX_B4_5", - "PSS0_IMUX_B4_6", - "PSS0_IMUX_B4_7", - "PSS0_IMUX_B4_8", - "PSS0_IMUX_B4_9", - "PSS0_IMUX_B5_0", - "PSS0_IMUX_B5_1", - "PSS0_IMUX_B5_10", - "PSS0_IMUX_B5_11", - "PSS0_IMUX_B5_12", - "PSS0_IMUX_B5_13", - "PSS0_IMUX_B5_14", - "PSS0_IMUX_B5_15", - "PSS0_IMUX_B5_16", - "PSS0_IMUX_B5_17", - "PSS0_IMUX_B5_18", - "PSS0_IMUX_B5_19", - "PSS0_IMUX_B5_2", - "PSS0_IMUX_B5_3", - "PSS0_IMUX_B5_4", - "PSS0_IMUX_B5_5", - "PSS0_IMUX_B5_6", - "PSS0_IMUX_B5_7", - "PSS0_IMUX_B5_8", - "PSS0_IMUX_B5_9", - "PSS0_IMUX_B6_0", - "PSS0_IMUX_B6_1", - "PSS0_IMUX_B6_10", - "PSS0_IMUX_B6_11", - "PSS0_IMUX_B6_12", - "PSS0_IMUX_B6_13", - "PSS0_IMUX_B6_14", - "PSS0_IMUX_B6_15", - "PSS0_IMUX_B6_16", - "PSS0_IMUX_B6_17", - "PSS0_IMUX_B6_18", - "PSS0_IMUX_B6_19", - "PSS0_IMUX_B6_2", - "PSS0_IMUX_B6_3", - "PSS0_IMUX_B6_4", - "PSS0_IMUX_B6_5", - "PSS0_IMUX_B6_6", - "PSS0_IMUX_B6_7", - "PSS0_IMUX_B6_8", - "PSS0_IMUX_B6_9", - "PSS0_IMUX_B7_0", - "PSS0_IMUX_B7_1", - "PSS0_IMUX_B7_10", - "PSS0_IMUX_B7_11", - "PSS0_IMUX_B7_12", - "PSS0_IMUX_B7_13", - "PSS0_IMUX_B7_14", - "PSS0_IMUX_B7_15", - "PSS0_IMUX_B7_16", - "PSS0_IMUX_B7_17", - "PSS0_IMUX_B7_18", - "PSS0_IMUX_B7_19", - "PSS0_IMUX_B7_2", - "PSS0_IMUX_B7_3", - "PSS0_IMUX_B7_4", - "PSS0_IMUX_B7_5", - "PSS0_IMUX_B7_6", - "PSS0_IMUX_B7_7", - "PSS0_IMUX_B7_8", - "PSS0_IMUX_B7_9", - "PSS0_IMUX_B8_0", - "PSS0_IMUX_B8_1", - "PSS0_IMUX_B8_10", - "PSS0_IMUX_B8_11", - "PSS0_IMUX_B8_12", - "PSS0_IMUX_B8_13", - "PSS0_IMUX_B8_14", - "PSS0_IMUX_B8_15", - "PSS0_IMUX_B8_16", - "PSS0_IMUX_B8_17", - "PSS0_IMUX_B8_18", - "PSS0_IMUX_B8_19", - "PSS0_IMUX_B8_2", - "PSS0_IMUX_B8_3", - "PSS0_IMUX_B8_4", - "PSS0_IMUX_B8_5", - "PSS0_IMUX_B8_6", - "PSS0_IMUX_B8_7", - "PSS0_IMUX_B8_8", - "PSS0_IMUX_B8_9", - "PSS0_IMUX_B9_0", - "PSS0_IMUX_B9_1", - "PSS0_IMUX_B9_10", - "PSS0_IMUX_B9_11", - "PSS0_IMUX_B9_12", - "PSS0_IMUX_B9_13", - "PSS0_IMUX_B9_14", - "PSS0_IMUX_B9_15", - "PSS0_IMUX_B9_16", - "PSS0_IMUX_B9_17", - "PSS0_IMUX_B9_18", - "PSS0_IMUX_B9_19", - "PSS0_IMUX_B9_2", - "PSS0_IMUX_B9_3", - "PSS0_IMUX_B9_4", - "PSS0_IMUX_B9_5", - "PSS0_IMUX_B9_6", - "PSS0_IMUX_B9_7", - "PSS0_IMUX_B9_8", - "PSS0_IMUX_B9_9", - "PSS0_LOGIC_OUTS0_0", - "PSS0_LOGIC_OUTS0_1", - "PSS0_LOGIC_OUTS0_10", - "PSS0_LOGIC_OUTS0_11", - "PSS0_LOGIC_OUTS0_12", - "PSS0_LOGIC_OUTS0_13", - "PSS0_LOGIC_OUTS0_14", - "PSS0_LOGIC_OUTS0_15", - "PSS0_LOGIC_OUTS0_16", - "PSS0_LOGIC_OUTS0_17", - "PSS0_LOGIC_OUTS0_18", - "PSS0_LOGIC_OUTS0_19", - "PSS0_LOGIC_OUTS0_2", - "PSS0_LOGIC_OUTS0_3", - "PSS0_LOGIC_OUTS0_4", - "PSS0_LOGIC_OUTS0_5", - "PSS0_LOGIC_OUTS0_6", - "PSS0_LOGIC_OUTS0_7", - "PSS0_LOGIC_OUTS0_8", - "PSS0_LOGIC_OUTS0_9", - "PSS0_LOGIC_OUTS10_0", - "PSS0_LOGIC_OUTS10_1", - "PSS0_LOGIC_OUTS10_10", - "PSS0_LOGIC_OUTS10_11", - "PSS0_LOGIC_OUTS10_12", - "PSS0_LOGIC_OUTS10_13", - "PSS0_LOGIC_OUTS10_14", - "PSS0_LOGIC_OUTS10_15", - "PSS0_LOGIC_OUTS10_16", - "PSS0_LOGIC_OUTS10_17", - "PSS0_LOGIC_OUTS10_18", - "PSS0_LOGIC_OUTS10_19", - "PSS0_LOGIC_OUTS10_2", - "PSS0_LOGIC_OUTS10_3", - "PSS0_LOGIC_OUTS10_4", - "PSS0_LOGIC_OUTS10_5", - "PSS0_LOGIC_OUTS10_6", - "PSS0_LOGIC_OUTS10_7", - "PSS0_LOGIC_OUTS10_8", - "PSS0_LOGIC_OUTS10_9", - "PSS0_LOGIC_OUTS11_0", - "PSS0_LOGIC_OUTS11_1", - "PSS0_LOGIC_OUTS11_10", - "PSS0_LOGIC_OUTS11_11", - "PSS0_LOGIC_OUTS11_12", - "PSS0_LOGIC_OUTS11_13", - "PSS0_LOGIC_OUTS11_14", - "PSS0_LOGIC_OUTS11_15", - "PSS0_LOGIC_OUTS11_16", - "PSS0_LOGIC_OUTS11_17", - "PSS0_LOGIC_OUTS11_18", - "PSS0_LOGIC_OUTS11_19", - "PSS0_LOGIC_OUTS11_2", - "PSS0_LOGIC_OUTS11_3", - "PSS0_LOGIC_OUTS11_4", - "PSS0_LOGIC_OUTS11_5", - "PSS0_LOGIC_OUTS11_6", - "PSS0_LOGIC_OUTS11_7", - "PSS0_LOGIC_OUTS11_8", - "PSS0_LOGIC_OUTS11_9", - "PSS0_LOGIC_OUTS12_0", - "PSS0_LOGIC_OUTS12_1", - "PSS0_LOGIC_OUTS12_10", - "PSS0_LOGIC_OUTS12_11", - "PSS0_LOGIC_OUTS12_12", - "PSS0_LOGIC_OUTS12_13", - "PSS0_LOGIC_OUTS12_14", - "PSS0_LOGIC_OUTS12_15", - "PSS0_LOGIC_OUTS12_16", - "PSS0_LOGIC_OUTS12_17", - "PSS0_LOGIC_OUTS12_18", - "PSS0_LOGIC_OUTS12_19", - "PSS0_LOGIC_OUTS12_2", - "PSS0_LOGIC_OUTS12_3", - "PSS0_LOGIC_OUTS12_4", - "PSS0_LOGIC_OUTS12_5", - "PSS0_LOGIC_OUTS12_6", - "PSS0_LOGIC_OUTS12_7", - "PSS0_LOGIC_OUTS12_8", - "PSS0_LOGIC_OUTS12_9", - "PSS0_LOGIC_OUTS13_0", - "PSS0_LOGIC_OUTS13_1", - "PSS0_LOGIC_OUTS13_10", - "PSS0_LOGIC_OUTS13_11", - "PSS0_LOGIC_OUTS13_12", - "PSS0_LOGIC_OUTS13_13", - "PSS0_LOGIC_OUTS13_14", - "PSS0_LOGIC_OUTS13_15", - "PSS0_LOGIC_OUTS13_16", - "PSS0_LOGIC_OUTS13_17", - "PSS0_LOGIC_OUTS13_18", - "PSS0_LOGIC_OUTS13_19", - "PSS0_LOGIC_OUTS13_2", - "PSS0_LOGIC_OUTS13_3", - "PSS0_LOGIC_OUTS13_4", - "PSS0_LOGIC_OUTS13_5", - "PSS0_LOGIC_OUTS13_6", - "PSS0_LOGIC_OUTS13_7", - "PSS0_LOGIC_OUTS13_8", - "PSS0_LOGIC_OUTS13_9", - "PSS0_LOGIC_OUTS14_0", - "PSS0_LOGIC_OUTS14_1", - "PSS0_LOGIC_OUTS14_10", - "PSS0_LOGIC_OUTS14_11", - "PSS0_LOGIC_OUTS14_12", - "PSS0_LOGIC_OUTS14_13", - "PSS0_LOGIC_OUTS14_14", - "PSS0_LOGIC_OUTS14_15", - "PSS0_LOGIC_OUTS14_16", - "PSS0_LOGIC_OUTS14_17", - "PSS0_LOGIC_OUTS14_18", - "PSS0_LOGIC_OUTS14_19", - "PSS0_LOGIC_OUTS14_2", - "PSS0_LOGIC_OUTS14_3", - "PSS0_LOGIC_OUTS14_4", - "PSS0_LOGIC_OUTS14_5", - "PSS0_LOGIC_OUTS14_6", - "PSS0_LOGIC_OUTS14_7", - "PSS0_LOGIC_OUTS14_8", - "PSS0_LOGIC_OUTS14_9", - "PSS0_LOGIC_OUTS15_0", - "PSS0_LOGIC_OUTS15_1", - "PSS0_LOGIC_OUTS15_10", - "PSS0_LOGIC_OUTS15_11", - "PSS0_LOGIC_OUTS15_12", - "PSS0_LOGIC_OUTS15_13", - "PSS0_LOGIC_OUTS15_14", - "PSS0_LOGIC_OUTS15_15", - "PSS0_LOGIC_OUTS15_16", - "PSS0_LOGIC_OUTS15_17", - "PSS0_LOGIC_OUTS15_18", - "PSS0_LOGIC_OUTS15_19", - "PSS0_LOGIC_OUTS15_2", - "PSS0_LOGIC_OUTS15_3", - "PSS0_LOGIC_OUTS15_4", - "PSS0_LOGIC_OUTS15_5", - "PSS0_LOGIC_OUTS15_6", - "PSS0_LOGIC_OUTS15_7", - "PSS0_LOGIC_OUTS15_8", - "PSS0_LOGIC_OUTS15_9", - "PSS0_LOGIC_OUTS16_0", - "PSS0_LOGIC_OUTS16_1", - "PSS0_LOGIC_OUTS16_10", - "PSS0_LOGIC_OUTS16_11", - "PSS0_LOGIC_OUTS16_12", - "PSS0_LOGIC_OUTS16_13", - "PSS0_LOGIC_OUTS16_14", - "PSS0_LOGIC_OUTS16_15", - "PSS0_LOGIC_OUTS16_16", - "PSS0_LOGIC_OUTS16_17", - "PSS0_LOGIC_OUTS16_18", - "PSS0_LOGIC_OUTS16_19", - "PSS0_LOGIC_OUTS16_2", - "PSS0_LOGIC_OUTS16_3", - "PSS0_LOGIC_OUTS16_4", - "PSS0_LOGIC_OUTS16_5", - "PSS0_LOGIC_OUTS16_6", - "PSS0_LOGIC_OUTS16_7", - "PSS0_LOGIC_OUTS16_8", - "PSS0_LOGIC_OUTS16_9", - "PSS0_LOGIC_OUTS17_0", - "PSS0_LOGIC_OUTS17_1", - "PSS0_LOGIC_OUTS17_10", - "PSS0_LOGIC_OUTS17_11", - "PSS0_LOGIC_OUTS17_12", - "PSS0_LOGIC_OUTS17_13", - "PSS0_LOGIC_OUTS17_14", - "PSS0_LOGIC_OUTS17_15", - "PSS0_LOGIC_OUTS17_16", - "PSS0_LOGIC_OUTS17_17", - "PSS0_LOGIC_OUTS17_18", - "PSS0_LOGIC_OUTS17_19", - "PSS0_LOGIC_OUTS17_2", - "PSS0_LOGIC_OUTS17_3", - "PSS0_LOGIC_OUTS17_4", - "PSS0_LOGIC_OUTS17_5", - "PSS0_LOGIC_OUTS17_6", - "PSS0_LOGIC_OUTS17_7", - "PSS0_LOGIC_OUTS17_8", - "PSS0_LOGIC_OUTS17_9", - "PSS0_LOGIC_OUTS18_0", - "PSS0_LOGIC_OUTS18_1", - "PSS0_LOGIC_OUTS18_10", - "PSS0_LOGIC_OUTS18_11", - "PSS0_LOGIC_OUTS18_12", - "PSS0_LOGIC_OUTS18_13", - "PSS0_LOGIC_OUTS18_14", - "PSS0_LOGIC_OUTS18_15", - "PSS0_LOGIC_OUTS18_16", - "PSS0_LOGIC_OUTS18_17", - "PSS0_LOGIC_OUTS18_18", - "PSS0_LOGIC_OUTS18_19", - "PSS0_LOGIC_OUTS18_2", - "PSS0_LOGIC_OUTS18_3", - "PSS0_LOGIC_OUTS18_4", - "PSS0_LOGIC_OUTS18_5", - "PSS0_LOGIC_OUTS18_6", - "PSS0_LOGIC_OUTS18_7", - "PSS0_LOGIC_OUTS18_8", - "PSS0_LOGIC_OUTS18_9", - "PSS0_LOGIC_OUTS19_0", - "PSS0_LOGIC_OUTS19_1", - "PSS0_LOGIC_OUTS19_10", - "PSS0_LOGIC_OUTS19_11", - "PSS0_LOGIC_OUTS19_12", - "PSS0_LOGIC_OUTS19_13", - "PSS0_LOGIC_OUTS19_14", - "PSS0_LOGIC_OUTS19_15", - "PSS0_LOGIC_OUTS19_16", - "PSS0_LOGIC_OUTS19_17", - "PSS0_LOGIC_OUTS19_18", - "PSS0_LOGIC_OUTS19_19", - "PSS0_LOGIC_OUTS19_2", - "PSS0_LOGIC_OUTS19_3", - "PSS0_LOGIC_OUTS19_4", - "PSS0_LOGIC_OUTS19_5", - "PSS0_LOGIC_OUTS19_6", - "PSS0_LOGIC_OUTS19_7", - "PSS0_LOGIC_OUTS19_8", - "PSS0_LOGIC_OUTS19_9", - "PSS0_LOGIC_OUTS1_0", - "PSS0_LOGIC_OUTS1_1", - "PSS0_LOGIC_OUTS1_10", - "PSS0_LOGIC_OUTS1_11", - "PSS0_LOGIC_OUTS1_12", - "PSS0_LOGIC_OUTS1_13", - "PSS0_LOGIC_OUTS1_14", - "PSS0_LOGIC_OUTS1_15", - "PSS0_LOGIC_OUTS1_16", - "PSS0_LOGIC_OUTS1_17", - "PSS0_LOGIC_OUTS1_18", - "PSS0_LOGIC_OUTS1_19", - "PSS0_LOGIC_OUTS1_2", - "PSS0_LOGIC_OUTS1_3", - "PSS0_LOGIC_OUTS1_4", - "PSS0_LOGIC_OUTS1_5", - "PSS0_LOGIC_OUTS1_6", - "PSS0_LOGIC_OUTS1_7", - "PSS0_LOGIC_OUTS1_8", - "PSS0_LOGIC_OUTS1_9", - "PSS0_LOGIC_OUTS20_0", - "PSS0_LOGIC_OUTS20_1", - "PSS0_LOGIC_OUTS20_10", - "PSS0_LOGIC_OUTS20_11", - "PSS0_LOGIC_OUTS20_12", - "PSS0_LOGIC_OUTS20_13", - "PSS0_LOGIC_OUTS20_14", - "PSS0_LOGIC_OUTS20_15", - "PSS0_LOGIC_OUTS20_16", - "PSS0_LOGIC_OUTS20_17", - "PSS0_LOGIC_OUTS20_18", - "PSS0_LOGIC_OUTS20_19", - "PSS0_LOGIC_OUTS20_2", - "PSS0_LOGIC_OUTS20_3", - "PSS0_LOGIC_OUTS20_4", - "PSS0_LOGIC_OUTS20_5", - "PSS0_LOGIC_OUTS20_6", - "PSS0_LOGIC_OUTS20_7", - "PSS0_LOGIC_OUTS20_8", - "PSS0_LOGIC_OUTS20_9", - "PSS0_LOGIC_OUTS21_0", - "PSS0_LOGIC_OUTS21_1", - "PSS0_LOGIC_OUTS21_10", - "PSS0_LOGIC_OUTS21_11", - "PSS0_LOGIC_OUTS21_12", - "PSS0_LOGIC_OUTS21_13", - "PSS0_LOGIC_OUTS21_14", - "PSS0_LOGIC_OUTS21_15", - "PSS0_LOGIC_OUTS21_16", - "PSS0_LOGIC_OUTS21_17", - "PSS0_LOGIC_OUTS21_18", - "PSS0_LOGIC_OUTS21_19", - "PSS0_LOGIC_OUTS21_2", - "PSS0_LOGIC_OUTS21_3", - "PSS0_LOGIC_OUTS21_4", - "PSS0_LOGIC_OUTS21_5", - "PSS0_LOGIC_OUTS21_6", - "PSS0_LOGIC_OUTS21_7", - "PSS0_LOGIC_OUTS21_8", - "PSS0_LOGIC_OUTS21_9", - "PSS0_LOGIC_OUTS22_0", - "PSS0_LOGIC_OUTS22_1", - "PSS0_LOGIC_OUTS22_10", - "PSS0_LOGIC_OUTS22_11", - "PSS0_LOGIC_OUTS22_12", - "PSS0_LOGIC_OUTS22_13", - "PSS0_LOGIC_OUTS22_14", - "PSS0_LOGIC_OUTS22_15", - "PSS0_LOGIC_OUTS22_16", - "PSS0_LOGIC_OUTS22_17", - "PSS0_LOGIC_OUTS22_18", - "PSS0_LOGIC_OUTS22_19", - "PSS0_LOGIC_OUTS22_2", - "PSS0_LOGIC_OUTS22_3", - "PSS0_LOGIC_OUTS22_4", - "PSS0_LOGIC_OUTS22_5", - "PSS0_LOGIC_OUTS22_6", - "PSS0_LOGIC_OUTS22_7", - "PSS0_LOGIC_OUTS22_8", - "PSS0_LOGIC_OUTS22_9", - "PSS0_LOGIC_OUTS23_0", - "PSS0_LOGIC_OUTS23_1", - "PSS0_LOGIC_OUTS23_10", - "PSS0_LOGIC_OUTS23_11", - "PSS0_LOGIC_OUTS23_12", - "PSS0_LOGIC_OUTS23_13", - "PSS0_LOGIC_OUTS23_14", - "PSS0_LOGIC_OUTS23_15", - "PSS0_LOGIC_OUTS23_16", - "PSS0_LOGIC_OUTS23_17", - "PSS0_LOGIC_OUTS23_18", - "PSS0_LOGIC_OUTS23_19", - "PSS0_LOGIC_OUTS23_2", - "PSS0_LOGIC_OUTS23_3", - "PSS0_LOGIC_OUTS23_4", - "PSS0_LOGIC_OUTS23_5", - "PSS0_LOGIC_OUTS23_6", - "PSS0_LOGIC_OUTS23_7", - "PSS0_LOGIC_OUTS23_8", - "PSS0_LOGIC_OUTS23_9", - "PSS0_LOGIC_OUTS2_0", - "PSS0_LOGIC_OUTS2_1", - "PSS0_LOGIC_OUTS2_10", - "PSS0_LOGIC_OUTS2_11", - "PSS0_LOGIC_OUTS2_12", - "PSS0_LOGIC_OUTS2_13", - "PSS0_LOGIC_OUTS2_14", - "PSS0_LOGIC_OUTS2_15", - "PSS0_LOGIC_OUTS2_16", - "PSS0_LOGIC_OUTS2_17", - "PSS0_LOGIC_OUTS2_18", - "PSS0_LOGIC_OUTS2_19", - "PSS0_LOGIC_OUTS2_2", - "PSS0_LOGIC_OUTS2_3", - "PSS0_LOGIC_OUTS2_4", - "PSS0_LOGIC_OUTS2_5", - "PSS0_LOGIC_OUTS2_6", - "PSS0_LOGIC_OUTS2_7", - "PSS0_LOGIC_OUTS2_8", - "PSS0_LOGIC_OUTS2_9", - "PSS0_LOGIC_OUTS3_0", - "PSS0_LOGIC_OUTS3_1", - "PSS0_LOGIC_OUTS3_10", - "PSS0_LOGIC_OUTS3_11", - "PSS0_LOGIC_OUTS3_12", - "PSS0_LOGIC_OUTS3_13", - "PSS0_LOGIC_OUTS3_14", - "PSS0_LOGIC_OUTS3_15", - "PSS0_LOGIC_OUTS3_16", - "PSS0_LOGIC_OUTS3_17", - "PSS0_LOGIC_OUTS3_18", - "PSS0_LOGIC_OUTS3_19", - "PSS0_LOGIC_OUTS3_2", - "PSS0_LOGIC_OUTS3_3", - "PSS0_LOGIC_OUTS3_4", - "PSS0_LOGIC_OUTS3_5", - "PSS0_LOGIC_OUTS3_6", - "PSS0_LOGIC_OUTS3_7", - "PSS0_LOGIC_OUTS3_8", - "PSS0_LOGIC_OUTS3_9", - "PSS0_LOGIC_OUTS4_0", - "PSS0_LOGIC_OUTS4_1", - "PSS0_LOGIC_OUTS4_10", - "PSS0_LOGIC_OUTS4_11", - "PSS0_LOGIC_OUTS4_12", - "PSS0_LOGIC_OUTS4_13", - "PSS0_LOGIC_OUTS4_14", - "PSS0_LOGIC_OUTS4_15", - "PSS0_LOGIC_OUTS4_16", - "PSS0_LOGIC_OUTS4_17", - "PSS0_LOGIC_OUTS4_18", - "PSS0_LOGIC_OUTS4_19", - "PSS0_LOGIC_OUTS4_2", - "PSS0_LOGIC_OUTS4_3", - "PSS0_LOGIC_OUTS4_4", - "PSS0_LOGIC_OUTS4_5", - "PSS0_LOGIC_OUTS4_6", - "PSS0_LOGIC_OUTS4_7", - "PSS0_LOGIC_OUTS4_8", - "PSS0_LOGIC_OUTS4_9", - "PSS0_LOGIC_OUTS5_0", - "PSS0_LOGIC_OUTS5_1", - "PSS0_LOGIC_OUTS5_10", - "PSS0_LOGIC_OUTS5_11", - "PSS0_LOGIC_OUTS5_12", - "PSS0_LOGIC_OUTS5_13", - "PSS0_LOGIC_OUTS5_14", - "PSS0_LOGIC_OUTS5_15", - "PSS0_LOGIC_OUTS5_16", - "PSS0_LOGIC_OUTS5_17", - "PSS0_LOGIC_OUTS5_18", - "PSS0_LOGIC_OUTS5_19", - "PSS0_LOGIC_OUTS5_2", - "PSS0_LOGIC_OUTS5_3", - "PSS0_LOGIC_OUTS5_4", - "PSS0_LOGIC_OUTS5_5", - "PSS0_LOGIC_OUTS5_6", - "PSS0_LOGIC_OUTS5_7", - "PSS0_LOGIC_OUTS5_8", - "PSS0_LOGIC_OUTS5_9", - "PSS0_LOGIC_OUTS6_0", - "PSS0_LOGIC_OUTS6_1", - "PSS0_LOGIC_OUTS6_10", - "PSS0_LOGIC_OUTS6_11", - "PSS0_LOGIC_OUTS6_12", - "PSS0_LOGIC_OUTS6_13", - "PSS0_LOGIC_OUTS6_14", - "PSS0_LOGIC_OUTS6_15", - "PSS0_LOGIC_OUTS6_16", - "PSS0_LOGIC_OUTS6_17", - "PSS0_LOGIC_OUTS6_18", - "PSS0_LOGIC_OUTS6_19", - "PSS0_LOGIC_OUTS6_2", - "PSS0_LOGIC_OUTS6_3", - "PSS0_LOGIC_OUTS6_4", - "PSS0_LOGIC_OUTS6_5", - "PSS0_LOGIC_OUTS6_6", - "PSS0_LOGIC_OUTS6_7", - "PSS0_LOGIC_OUTS6_8", - "PSS0_LOGIC_OUTS6_9", - "PSS0_LOGIC_OUTS7_0", - "PSS0_LOGIC_OUTS7_1", - "PSS0_LOGIC_OUTS7_10", - "PSS0_LOGIC_OUTS7_11", - "PSS0_LOGIC_OUTS7_12", - "PSS0_LOGIC_OUTS7_13", - "PSS0_LOGIC_OUTS7_14", - "PSS0_LOGIC_OUTS7_15", - "PSS0_LOGIC_OUTS7_16", - "PSS0_LOGIC_OUTS7_17", - "PSS0_LOGIC_OUTS7_18", - "PSS0_LOGIC_OUTS7_19", - "PSS0_LOGIC_OUTS7_2", - "PSS0_LOGIC_OUTS7_3", - "PSS0_LOGIC_OUTS7_4", - "PSS0_LOGIC_OUTS7_5", - "PSS0_LOGIC_OUTS7_6", - "PSS0_LOGIC_OUTS7_7", - "PSS0_LOGIC_OUTS7_8", - "PSS0_LOGIC_OUTS7_9", - "PSS0_LOGIC_OUTS8_0", - "PSS0_LOGIC_OUTS8_1", - "PSS0_LOGIC_OUTS8_10", - "PSS0_LOGIC_OUTS8_11", - "PSS0_LOGIC_OUTS8_12", - "PSS0_LOGIC_OUTS8_13", - "PSS0_LOGIC_OUTS8_14", - "PSS0_LOGIC_OUTS8_15", - "PSS0_LOGIC_OUTS8_16", - "PSS0_LOGIC_OUTS8_17", - "PSS0_LOGIC_OUTS8_18", - "PSS0_LOGIC_OUTS8_19", - "PSS0_LOGIC_OUTS8_2", - "PSS0_LOGIC_OUTS8_3", - "PSS0_LOGIC_OUTS8_4", - "PSS0_LOGIC_OUTS8_5", - "PSS0_LOGIC_OUTS8_6", - "PSS0_LOGIC_OUTS8_7", - "PSS0_LOGIC_OUTS8_8", - "PSS0_LOGIC_OUTS8_9", - "PSS0_LOGIC_OUTS9_0", - "PSS0_LOGIC_OUTS9_1", - "PSS0_LOGIC_OUTS9_10", - "PSS0_LOGIC_OUTS9_11", - "PSS0_LOGIC_OUTS9_12", - "PSS0_LOGIC_OUTS9_13", - "PSS0_LOGIC_OUTS9_14", - "PSS0_LOGIC_OUTS9_15", - "PSS0_LOGIC_OUTS9_16", - "PSS0_LOGIC_OUTS9_17", - "PSS0_LOGIC_OUTS9_18", - "PSS0_LOGIC_OUTS9_19", - "PSS0_LOGIC_OUTS9_2", - "PSS0_LOGIC_OUTS9_3", - "PSS0_LOGIC_OUTS9_4", - "PSS0_LOGIC_OUTS9_5", - "PSS0_LOGIC_OUTS9_6", - "PSS0_LOGIC_OUTS9_7", - "PSS0_LOGIC_OUTS9_8", - "PSS0_LOGIC_OUTS9_9", - "PSS_BYP_B0_0", - "PSS_BYP_B0_1", - "PSS_BYP_B0_10", - "PSS_BYP_B0_11", - "PSS_BYP_B0_12", - "PSS_BYP_B0_13", - "PSS_BYP_B0_14", - "PSS_BYP_B0_15", - "PSS_BYP_B0_16", - "PSS_BYP_B0_17", - "PSS_BYP_B0_18", - "PSS_BYP_B0_19", - "PSS_BYP_B0_2", - "PSS_BYP_B0_3", - "PSS_BYP_B0_4", - "PSS_BYP_B0_5", - "PSS_BYP_B0_6", - "PSS_BYP_B0_7", - "PSS_BYP_B0_8", - "PSS_BYP_B0_9", - "PSS_BYP_B1_0", - "PSS_BYP_B1_1", - "PSS_BYP_B1_10", - "PSS_BYP_B1_11", - "PSS_BYP_B1_12", - "PSS_BYP_B1_13", - "PSS_BYP_B1_14", - "PSS_BYP_B1_15", - "PSS_BYP_B1_16", - "PSS_BYP_B1_17", - "PSS_BYP_B1_18", - "PSS_BYP_B1_19", - "PSS_BYP_B1_2", - "PSS_BYP_B1_3", - "PSS_BYP_B1_4", - "PSS_BYP_B1_5", - "PSS_BYP_B1_6", - "PSS_BYP_B1_7", - "PSS_BYP_B1_8", - "PSS_BYP_B1_9", - "PSS_BYP_B2_0", - "PSS_BYP_B2_1", - "PSS_BYP_B2_10", - "PSS_BYP_B2_11", - "PSS_BYP_B2_12", - "PSS_BYP_B2_13", - "PSS_BYP_B2_14", - "PSS_BYP_B2_15", - "PSS_BYP_B2_16", - "PSS_BYP_B2_17", - "PSS_BYP_B2_18", - "PSS_BYP_B2_19", - "PSS_BYP_B2_2", - "PSS_BYP_B2_3", - "PSS_BYP_B2_4", - "PSS_BYP_B2_5", - "PSS_BYP_B2_6", - "PSS_BYP_B2_7", - "PSS_BYP_B2_8", - "PSS_BYP_B2_9", - "PSS_BYP_B3_0", - "PSS_BYP_B3_1", - "PSS_BYP_B3_10", - "PSS_BYP_B3_11", - "PSS_BYP_B3_12", - "PSS_BYP_B3_13", - "PSS_BYP_B3_14", - "PSS_BYP_B3_15", - "PSS_BYP_B3_16", - "PSS_BYP_B3_17", - "PSS_BYP_B3_18", - "PSS_BYP_B3_19", - "PSS_BYP_B3_2", - "PSS_BYP_B3_3", - "PSS_BYP_B3_4", - "PSS_BYP_B3_5", - "PSS_BYP_B3_6", - "PSS_BYP_B3_7", - "PSS_BYP_B3_8", - "PSS_BYP_B3_9", - "PSS_BYP_B4_0", - "PSS_BYP_B4_1", - "PSS_BYP_B4_10", - "PSS_BYP_B4_11", - "PSS_BYP_B4_12", - "PSS_BYP_B4_13", - "PSS_BYP_B4_14", - "PSS_BYP_B4_15", - "PSS_BYP_B4_16", - "PSS_BYP_B4_17", - "PSS_BYP_B4_18", - "PSS_BYP_B4_19", - "PSS_BYP_B4_2", - "PSS_BYP_B4_3", - "PSS_BYP_B4_4", - "PSS_BYP_B4_5", - "PSS_BYP_B4_6", - "PSS_BYP_B4_7", - "PSS_BYP_B4_8", - "PSS_BYP_B4_9", - "PSS_BYP_B5_0", - "PSS_BYP_B5_1", - "PSS_BYP_B5_10", - "PSS_BYP_B5_11", - "PSS_BYP_B5_12", - "PSS_BYP_B5_13", - "PSS_BYP_B5_14", - "PSS_BYP_B5_15", - "PSS_BYP_B5_16", - "PSS_BYP_B5_17", - "PSS_BYP_B5_18", - "PSS_BYP_B5_19", - "PSS_BYP_B5_2", - "PSS_BYP_B5_3", - "PSS_BYP_B5_4", - "PSS_BYP_B5_5", - "PSS_BYP_B5_6", - "PSS_BYP_B5_7", - "PSS_BYP_B5_8", - "PSS_BYP_B5_9", - "PSS_BYP_B6_0", - "PSS_BYP_B6_1", - "PSS_BYP_B6_10", - "PSS_BYP_B6_11", - "PSS_BYP_B6_12", - "PSS_BYP_B6_13", - "PSS_BYP_B6_14", - "PSS_BYP_B6_15", - "PSS_BYP_B6_16", - "PSS_BYP_B6_17", - "PSS_BYP_B6_18", - "PSS_BYP_B6_19", - "PSS_BYP_B6_2", - "PSS_BYP_B6_3", - "PSS_BYP_B6_4", - "PSS_BYP_B6_5", - "PSS_BYP_B6_6", - "PSS_BYP_B6_7", - "PSS_BYP_B6_8", - "PSS_BYP_B6_9", - "PSS_BYP_B7_0", - "PSS_BYP_B7_1", - "PSS_BYP_B7_10", - "PSS_BYP_B7_11", - "PSS_BYP_B7_12", - "PSS_BYP_B7_13", - "PSS_BYP_B7_14", - "PSS_BYP_B7_15", - "PSS_BYP_B7_16", - "PSS_BYP_B7_17", - "PSS_BYP_B7_18", - "PSS_BYP_B7_19", - "PSS_BYP_B7_2", - "PSS_BYP_B7_3", - "PSS_BYP_B7_4", - "PSS_BYP_B7_5", - "PSS_BYP_B7_6", - "PSS_BYP_B7_7", - "PSS_BYP_B7_8", - "PSS_BYP_B7_9", - "PSS_CLK_B0_0", - "PSS_CLK_B0_1", - "PSS_CLK_B0_10", - "PSS_CLK_B0_11", - "PSS_CLK_B0_12", - "PSS_CLK_B0_13", - "PSS_CLK_B0_14", - "PSS_CLK_B0_15", - "PSS_CLK_B0_16", - "PSS_CLK_B0_17", - "PSS_CLK_B0_18", - "PSS_CLK_B0_19", - "PSS_CLK_B0_2", - "PSS_CLK_B0_3", - "PSS_CLK_B0_4", - "PSS_CLK_B0_5", - "PSS_CLK_B0_6", - "PSS_CLK_B0_7", - "PSS_CLK_B0_8", - "PSS_CLK_B0_9", - "PSS_CLK_B1_0", - "PSS_CLK_B1_1", - "PSS_CLK_B1_10", - "PSS_CLK_B1_11", - "PSS_CLK_B1_12", - "PSS_CLK_B1_13", - "PSS_CLK_B1_14", - "PSS_CLK_B1_15", - "PSS_CLK_B1_16", - "PSS_CLK_B1_17", - "PSS_CLK_B1_18", - "PSS_CLK_B1_19", - "PSS_CLK_B1_2", - "PSS_CLK_B1_3", - "PSS_CLK_B1_4", - "PSS_CLK_B1_5", - "PSS_CLK_B1_6", - "PSS_CLK_B1_7", - "PSS_CLK_B1_8", - "PSS_CLK_B1_9", - "PSS_CTRL_B0_0", - "PSS_CTRL_B0_1", - "PSS_CTRL_B0_10", - "PSS_CTRL_B0_11", - "PSS_CTRL_B0_12", - "PSS_CTRL_B0_13", - "PSS_CTRL_B0_14", - "PSS_CTRL_B0_15", - "PSS_CTRL_B0_16", - "PSS_CTRL_B0_17", - "PSS_CTRL_B0_18", - "PSS_CTRL_B0_19", - "PSS_CTRL_B0_2", - "PSS_CTRL_B0_3", - "PSS_CTRL_B0_4", - "PSS_CTRL_B0_5", - "PSS_CTRL_B0_6", - "PSS_CTRL_B0_7", - "PSS_CTRL_B0_8", - "PSS_CTRL_B0_9", - "PSS_CTRL_B1_0", - "PSS_CTRL_B1_1", - "PSS_CTRL_B1_10", - "PSS_CTRL_B1_11", - "PSS_CTRL_B1_12", - "PSS_CTRL_B1_13", - "PSS_CTRL_B1_14", - "PSS_CTRL_B1_15", - "PSS_CTRL_B1_16", - "PSS_CTRL_B1_17", - "PSS_CTRL_B1_18", - "PSS_CTRL_B1_19", - "PSS_CTRL_B1_2", - "PSS_CTRL_B1_3", - "PSS_CTRL_B1_4", - "PSS_CTRL_B1_5", - "PSS_CTRL_B1_6", - "PSS_CTRL_B1_7", - "PSS_CTRL_B1_8", - "PSS_CTRL_B1_9", - "PSS_FAN_B0_0", - "PSS_FAN_B0_1", - "PSS_FAN_B0_10", - "PSS_FAN_B0_11", - "PSS_FAN_B0_12", - "PSS_FAN_B0_13", - "PSS_FAN_B0_14", - "PSS_FAN_B0_15", - "PSS_FAN_B0_16", - "PSS_FAN_B0_17", - "PSS_FAN_B0_18", - "PSS_FAN_B0_19", - "PSS_FAN_B0_2", - "PSS_FAN_B0_3", - "PSS_FAN_B0_4", - "PSS_FAN_B0_5", - "PSS_FAN_B0_6", - "PSS_FAN_B0_7", - "PSS_FAN_B0_8", - "PSS_FAN_B0_9", - "PSS_FAN_B1_0", - "PSS_FAN_B1_1", - "PSS_FAN_B1_10", - "PSS_FAN_B1_11", - "PSS_FAN_B1_12", - "PSS_FAN_B1_13", - "PSS_FAN_B1_14", - "PSS_FAN_B1_15", - "PSS_FAN_B1_16", - "PSS_FAN_B1_17", - "PSS_FAN_B1_18", - "PSS_FAN_B1_19", - "PSS_FAN_B1_2", - "PSS_FAN_B1_3", - "PSS_FAN_B1_4", - "PSS_FAN_B1_5", - "PSS_FAN_B1_6", - "PSS_FAN_B1_7", - "PSS_FAN_B1_8", - "PSS_FAN_B1_9", - "PSS_FAN_B2_0", - "PSS_FAN_B2_1", - "PSS_FAN_B2_10", - "PSS_FAN_B2_11", - "PSS_FAN_B2_12", - "PSS_FAN_B2_13", - "PSS_FAN_B2_14", - "PSS_FAN_B2_15", - "PSS_FAN_B2_16", - "PSS_FAN_B2_17", - "PSS_FAN_B2_18", - "PSS_FAN_B2_19", - "PSS_FAN_B2_2", - "PSS_FAN_B2_3", - "PSS_FAN_B2_4", - "PSS_FAN_B2_5", - "PSS_FAN_B2_6", - "PSS_FAN_B2_7", - "PSS_FAN_B2_8", - "PSS_FAN_B2_9", - "PSS_FAN_B3_0", - "PSS_FAN_B3_1", - "PSS_FAN_B3_10", - "PSS_FAN_B3_11", - "PSS_FAN_B3_12", - "PSS_FAN_B3_13", - "PSS_FAN_B3_14", - "PSS_FAN_B3_15", - "PSS_FAN_B3_16", - "PSS_FAN_B3_17", - "PSS_FAN_B3_18", - "PSS_FAN_B3_19", - "PSS_FAN_B3_2", - "PSS_FAN_B3_3", - "PSS_FAN_B3_4", - "PSS_FAN_B3_5", - "PSS_FAN_B3_6", - "PSS_FAN_B3_7", - "PSS_FAN_B3_8", - "PSS_FAN_B3_9", - "PSS_FAN_B4_0", - "PSS_FAN_B4_1", - "PSS_FAN_B4_10", - "PSS_FAN_B4_11", - "PSS_FAN_B4_12", - "PSS_FAN_B4_13", - "PSS_FAN_B4_14", - "PSS_FAN_B4_15", - "PSS_FAN_B4_16", - "PSS_FAN_B4_17", - "PSS_FAN_B4_18", - "PSS_FAN_B4_19", - "PSS_FAN_B4_2", - "PSS_FAN_B4_3", - "PSS_FAN_B4_4", - "PSS_FAN_B4_5", - "PSS_FAN_B4_6", - "PSS_FAN_B4_7", - "PSS_FAN_B4_8", - "PSS_FAN_B4_9", - "PSS_FAN_B5_0", - "PSS_FAN_B5_1", - "PSS_FAN_B5_10", - "PSS_FAN_B5_11", - "PSS_FAN_B5_12", - "PSS_FAN_B5_13", - "PSS_FAN_B5_14", - "PSS_FAN_B5_15", - "PSS_FAN_B5_16", - "PSS_FAN_B5_17", - "PSS_FAN_B5_18", - "PSS_FAN_B5_19", - "PSS_FAN_B5_2", - "PSS_FAN_B5_3", - "PSS_FAN_B5_4", - "PSS_FAN_B5_5", - "PSS_FAN_B5_6", - "PSS_FAN_B5_7", - "PSS_FAN_B5_8", - "PSS_FAN_B5_9", - "PSS_FAN_B6_0", - "PSS_FAN_B6_1", - "PSS_FAN_B6_10", - "PSS_FAN_B6_11", - "PSS_FAN_B6_12", - "PSS_FAN_B6_13", - "PSS_FAN_B6_14", - "PSS_FAN_B6_15", - "PSS_FAN_B6_16", - "PSS_FAN_B6_17", - "PSS_FAN_B6_18", - "PSS_FAN_B6_19", - "PSS_FAN_B6_2", - "PSS_FAN_B6_3", - "PSS_FAN_B6_4", - "PSS_FAN_B6_5", - "PSS_FAN_B6_6", - "PSS_FAN_B6_7", - "PSS_FAN_B6_8", - "PSS_FAN_B6_9", - "PSS_FAN_B7_0", - "PSS_FAN_B7_1", - "PSS_FAN_B7_10", - "PSS_FAN_B7_11", - "PSS_FAN_B7_12", - "PSS_FAN_B7_13", - "PSS_FAN_B7_14", - "PSS_FAN_B7_15", - "PSS_FAN_B7_16", - "PSS_FAN_B7_17", - "PSS_FAN_B7_18", - "PSS_FAN_B7_19", - "PSS_FAN_B7_2", - "PSS_FAN_B7_3", - "PSS_FAN_B7_4", - "PSS_FAN_B7_5", - "PSS_FAN_B7_6", - "PSS_FAN_B7_7", - "PSS_FAN_B7_8", - "PSS_FAN_B7_9", - "PSS_IMUX_B0_0", - "PSS_IMUX_B0_1", - "PSS_IMUX_B0_10", - "PSS_IMUX_B0_11", - "PSS_IMUX_B0_12", - "PSS_IMUX_B0_13", - "PSS_IMUX_B0_14", - "PSS_IMUX_B0_15", - "PSS_IMUX_B0_16", - "PSS_IMUX_B0_17", - "PSS_IMUX_B0_18", - "PSS_IMUX_B0_19", - "PSS_IMUX_B0_2", - "PSS_IMUX_B0_3", - "PSS_IMUX_B0_4", - "PSS_IMUX_B0_5", - "PSS_IMUX_B0_6", - "PSS_IMUX_B0_7", - "PSS_IMUX_B0_8", - "PSS_IMUX_B0_9", - "PSS_IMUX_B10_0", - "PSS_IMUX_B10_1", - "PSS_IMUX_B10_10", - "PSS_IMUX_B10_11", - "PSS_IMUX_B10_12", - "PSS_IMUX_B10_13", - "PSS_IMUX_B10_14", - "PSS_IMUX_B10_15", - "PSS_IMUX_B10_16", - "PSS_IMUX_B10_17", - "PSS_IMUX_B10_18", - "PSS_IMUX_B10_19", - "PSS_IMUX_B10_2", - "PSS_IMUX_B10_3", - "PSS_IMUX_B10_4", - "PSS_IMUX_B10_5", - "PSS_IMUX_B10_6", - "PSS_IMUX_B10_7", - "PSS_IMUX_B10_8", - "PSS_IMUX_B10_9", - "PSS_IMUX_B11_0", - "PSS_IMUX_B11_1", - "PSS_IMUX_B11_10", - "PSS_IMUX_B11_11", - "PSS_IMUX_B11_12", - "PSS_IMUX_B11_13", - "PSS_IMUX_B11_14", - "PSS_IMUX_B11_15", - "PSS_IMUX_B11_16", - "PSS_IMUX_B11_17", - "PSS_IMUX_B11_18", - "PSS_IMUX_B11_19", - "PSS_IMUX_B11_2", - "PSS_IMUX_B11_3", - "PSS_IMUX_B11_4", - "PSS_IMUX_B11_5", - "PSS_IMUX_B11_6", - "PSS_IMUX_B11_7", - "PSS_IMUX_B11_8", - "PSS_IMUX_B11_9", - "PSS_IMUX_B12_0", - "PSS_IMUX_B12_1", - "PSS_IMUX_B12_10", - "PSS_IMUX_B12_11", - "PSS_IMUX_B12_12", - "PSS_IMUX_B12_13", - "PSS_IMUX_B12_14", - "PSS_IMUX_B12_15", - "PSS_IMUX_B12_16", - "PSS_IMUX_B12_17", - "PSS_IMUX_B12_18", - "PSS_IMUX_B12_19", - "PSS_IMUX_B12_2", - "PSS_IMUX_B12_3", - "PSS_IMUX_B12_4", - "PSS_IMUX_B12_5", - "PSS_IMUX_B12_6", - "PSS_IMUX_B12_7", - "PSS_IMUX_B12_8", - "PSS_IMUX_B12_9", - "PSS_IMUX_B13_0", - "PSS_IMUX_B13_1", - "PSS_IMUX_B13_10", - "PSS_IMUX_B13_11", - "PSS_IMUX_B13_12", - "PSS_IMUX_B13_13", - "PSS_IMUX_B13_14", - "PSS_IMUX_B13_15", - "PSS_IMUX_B13_16", - "PSS_IMUX_B13_17", - "PSS_IMUX_B13_18", - "PSS_IMUX_B13_19", - "PSS_IMUX_B13_2", - "PSS_IMUX_B13_3", - "PSS_IMUX_B13_4", - "PSS_IMUX_B13_5", - "PSS_IMUX_B13_6", - "PSS_IMUX_B13_7", - "PSS_IMUX_B13_8", - "PSS_IMUX_B13_9", - "PSS_IMUX_B14_0", - "PSS_IMUX_B14_1", - "PSS_IMUX_B14_10", - "PSS_IMUX_B14_11", - "PSS_IMUX_B14_12", - "PSS_IMUX_B14_13", - "PSS_IMUX_B14_14", - "PSS_IMUX_B14_15", - "PSS_IMUX_B14_16", - "PSS_IMUX_B14_17", - "PSS_IMUX_B14_18", - "PSS_IMUX_B14_19", - "PSS_IMUX_B14_2", - "PSS_IMUX_B14_3", - "PSS_IMUX_B14_4", - "PSS_IMUX_B14_5", - "PSS_IMUX_B14_6", - "PSS_IMUX_B14_7", - "PSS_IMUX_B14_8", - "PSS_IMUX_B14_9", - "PSS_IMUX_B15_0", - "PSS_IMUX_B15_1", - "PSS_IMUX_B15_10", - "PSS_IMUX_B15_11", - "PSS_IMUX_B15_12", - "PSS_IMUX_B15_13", - "PSS_IMUX_B15_14", - "PSS_IMUX_B15_15", - "PSS_IMUX_B15_16", - "PSS_IMUX_B15_17", - "PSS_IMUX_B15_18", - "PSS_IMUX_B15_19", - "PSS_IMUX_B15_2", - "PSS_IMUX_B15_3", - "PSS_IMUX_B15_4", - "PSS_IMUX_B15_5", - "PSS_IMUX_B15_6", - "PSS_IMUX_B15_7", - "PSS_IMUX_B15_8", - "PSS_IMUX_B15_9", - "PSS_IMUX_B16_0", - "PSS_IMUX_B16_1", - "PSS_IMUX_B16_10", - "PSS_IMUX_B16_11", - "PSS_IMUX_B16_12", - "PSS_IMUX_B16_13", - "PSS_IMUX_B16_14", - "PSS_IMUX_B16_15", - "PSS_IMUX_B16_16", - "PSS_IMUX_B16_17", - "PSS_IMUX_B16_18", - "PSS_IMUX_B16_19", - "PSS_IMUX_B16_2", - "PSS_IMUX_B16_3", - "PSS_IMUX_B16_4", - "PSS_IMUX_B16_5", - "PSS_IMUX_B16_6", - "PSS_IMUX_B16_7", - "PSS_IMUX_B16_8", - "PSS_IMUX_B16_9", - "PSS_IMUX_B17_0", - "PSS_IMUX_B17_1", - "PSS_IMUX_B17_10", - "PSS_IMUX_B17_11", - "PSS_IMUX_B17_12", - "PSS_IMUX_B17_13", - "PSS_IMUX_B17_14", - "PSS_IMUX_B17_15", - "PSS_IMUX_B17_16", - "PSS_IMUX_B17_17", - "PSS_IMUX_B17_18", - "PSS_IMUX_B17_19", - "PSS_IMUX_B17_2", - "PSS_IMUX_B17_3", - "PSS_IMUX_B17_4", - "PSS_IMUX_B17_5", - "PSS_IMUX_B17_6", - "PSS_IMUX_B17_7", - "PSS_IMUX_B17_8", - "PSS_IMUX_B17_9", - "PSS_IMUX_B18_0", - "PSS_IMUX_B18_1", - "PSS_IMUX_B18_10", - "PSS_IMUX_B18_11", - "PSS_IMUX_B18_12", - "PSS_IMUX_B18_13", - "PSS_IMUX_B18_14", - "PSS_IMUX_B18_15", - "PSS_IMUX_B18_16", - "PSS_IMUX_B18_17", - "PSS_IMUX_B18_18", - "PSS_IMUX_B18_19", - "PSS_IMUX_B18_2", - "PSS_IMUX_B18_3", - "PSS_IMUX_B18_4", - "PSS_IMUX_B18_5", - "PSS_IMUX_B18_6", - "PSS_IMUX_B18_7", - "PSS_IMUX_B18_8", - "PSS_IMUX_B18_9", - "PSS_IMUX_B19_0", - "PSS_IMUX_B19_1", - "PSS_IMUX_B19_10", - "PSS_IMUX_B19_11", - "PSS_IMUX_B19_12", - "PSS_IMUX_B19_13", - "PSS_IMUX_B19_14", - "PSS_IMUX_B19_15", - "PSS_IMUX_B19_16", - "PSS_IMUX_B19_17", - "PSS_IMUX_B19_18", - "PSS_IMUX_B19_19", - "PSS_IMUX_B19_2", - "PSS_IMUX_B19_3", - "PSS_IMUX_B19_4", - "PSS_IMUX_B19_5", - "PSS_IMUX_B19_6", - "PSS_IMUX_B19_7", - "PSS_IMUX_B19_8", - "PSS_IMUX_B19_9", - "PSS_IMUX_B1_0", - "PSS_IMUX_B1_1", - "PSS_IMUX_B1_10", - "PSS_IMUX_B1_11", - "PSS_IMUX_B1_12", - "PSS_IMUX_B1_13", - "PSS_IMUX_B1_14", - "PSS_IMUX_B1_15", - "PSS_IMUX_B1_16", - "PSS_IMUX_B1_17", - "PSS_IMUX_B1_18", - "PSS_IMUX_B1_19", - "PSS_IMUX_B1_2", - "PSS_IMUX_B1_3", - "PSS_IMUX_B1_4", - "PSS_IMUX_B1_5", - "PSS_IMUX_B1_6", - "PSS_IMUX_B1_7", - "PSS_IMUX_B1_8", - "PSS_IMUX_B1_9", - "PSS_IMUX_B20_0", - "PSS_IMUX_B20_1", - "PSS_IMUX_B20_10", - "PSS_IMUX_B20_11", - "PSS_IMUX_B20_12", - "PSS_IMUX_B20_13", - "PSS_IMUX_B20_14", - "PSS_IMUX_B20_15", - "PSS_IMUX_B20_16", - "PSS_IMUX_B20_17", - "PSS_IMUX_B20_18", - "PSS_IMUX_B20_19", - "PSS_IMUX_B20_2", - "PSS_IMUX_B20_3", - "PSS_IMUX_B20_4", - "PSS_IMUX_B20_5", - "PSS_IMUX_B20_6", - "PSS_IMUX_B20_7", - "PSS_IMUX_B20_8", - "PSS_IMUX_B20_9", - "PSS_IMUX_B21_0", - "PSS_IMUX_B21_1", - "PSS_IMUX_B21_10", - "PSS_IMUX_B21_11", - "PSS_IMUX_B21_12", - "PSS_IMUX_B21_13", - "PSS_IMUX_B21_14", - "PSS_IMUX_B21_15", - "PSS_IMUX_B21_16", - "PSS_IMUX_B21_17", - "PSS_IMUX_B21_18", - "PSS_IMUX_B21_19", - "PSS_IMUX_B21_2", - "PSS_IMUX_B21_3", - "PSS_IMUX_B21_4", - "PSS_IMUX_B21_5", - "PSS_IMUX_B21_6", - "PSS_IMUX_B21_7", - "PSS_IMUX_B21_8", - "PSS_IMUX_B21_9", - "PSS_IMUX_B22_0", - "PSS_IMUX_B22_1", - "PSS_IMUX_B22_10", - "PSS_IMUX_B22_11", - "PSS_IMUX_B22_12", - "PSS_IMUX_B22_13", - "PSS_IMUX_B22_14", - "PSS_IMUX_B22_15", - "PSS_IMUX_B22_16", - "PSS_IMUX_B22_17", - "PSS_IMUX_B22_18", - "PSS_IMUX_B22_19", - "PSS_IMUX_B22_2", - "PSS_IMUX_B22_3", - "PSS_IMUX_B22_4", - "PSS_IMUX_B22_5", - "PSS_IMUX_B22_6", - "PSS_IMUX_B22_7", - "PSS_IMUX_B22_8", - "PSS_IMUX_B22_9", - "PSS_IMUX_B23_0", - "PSS_IMUX_B23_1", - "PSS_IMUX_B23_10", - "PSS_IMUX_B23_11", - "PSS_IMUX_B23_12", - "PSS_IMUX_B23_13", - "PSS_IMUX_B23_14", - "PSS_IMUX_B23_15", - "PSS_IMUX_B23_16", - "PSS_IMUX_B23_17", - "PSS_IMUX_B23_18", - "PSS_IMUX_B23_19", - "PSS_IMUX_B23_2", - "PSS_IMUX_B23_3", - "PSS_IMUX_B23_4", - "PSS_IMUX_B23_5", - "PSS_IMUX_B23_6", - "PSS_IMUX_B23_7", - "PSS_IMUX_B23_8", - "PSS_IMUX_B23_9", - "PSS_IMUX_B24_0", - "PSS_IMUX_B24_1", - "PSS_IMUX_B24_10", - "PSS_IMUX_B24_11", - "PSS_IMUX_B24_12", - "PSS_IMUX_B24_13", - "PSS_IMUX_B24_14", - "PSS_IMUX_B24_15", - "PSS_IMUX_B24_16", - "PSS_IMUX_B24_17", - "PSS_IMUX_B24_18", - "PSS_IMUX_B24_19", - "PSS_IMUX_B24_2", - "PSS_IMUX_B24_3", - "PSS_IMUX_B24_4", - "PSS_IMUX_B24_5", - "PSS_IMUX_B24_6", - "PSS_IMUX_B24_7", - "PSS_IMUX_B24_8", - "PSS_IMUX_B24_9", - "PSS_IMUX_B25_0", - "PSS_IMUX_B25_1", - "PSS_IMUX_B25_10", - "PSS_IMUX_B25_11", - "PSS_IMUX_B25_12", - "PSS_IMUX_B25_13", - "PSS_IMUX_B25_14", - "PSS_IMUX_B25_15", - "PSS_IMUX_B25_16", - "PSS_IMUX_B25_17", - "PSS_IMUX_B25_18", - "PSS_IMUX_B25_19", - "PSS_IMUX_B25_2", - "PSS_IMUX_B25_3", - "PSS_IMUX_B25_4", - "PSS_IMUX_B25_5", - "PSS_IMUX_B25_6", - "PSS_IMUX_B25_7", - "PSS_IMUX_B25_8", - "PSS_IMUX_B25_9", - "PSS_IMUX_B26_0", - "PSS_IMUX_B26_1", - "PSS_IMUX_B26_10", - "PSS_IMUX_B26_11", - "PSS_IMUX_B26_12", - "PSS_IMUX_B26_13", - "PSS_IMUX_B26_14", - "PSS_IMUX_B26_15", - "PSS_IMUX_B26_16", - "PSS_IMUX_B26_17", - "PSS_IMUX_B26_18", - "PSS_IMUX_B26_19", - "PSS_IMUX_B26_2", - "PSS_IMUX_B26_3", - "PSS_IMUX_B26_4", - "PSS_IMUX_B26_5", - "PSS_IMUX_B26_6", - "PSS_IMUX_B26_7", - "PSS_IMUX_B26_8", - "PSS_IMUX_B26_9", - "PSS_IMUX_B27_0", - "PSS_IMUX_B27_1", - "PSS_IMUX_B27_10", - "PSS_IMUX_B27_11", - "PSS_IMUX_B27_12", - "PSS_IMUX_B27_13", - "PSS_IMUX_B27_14", - "PSS_IMUX_B27_15", - "PSS_IMUX_B27_16", - "PSS_IMUX_B27_17", - "PSS_IMUX_B27_18", - "PSS_IMUX_B27_19", - "PSS_IMUX_B27_2", - "PSS_IMUX_B27_3", - "PSS_IMUX_B27_4", - "PSS_IMUX_B27_5", - "PSS_IMUX_B27_6", - "PSS_IMUX_B27_7", - "PSS_IMUX_B27_8", - "PSS_IMUX_B27_9", - "PSS_IMUX_B28_0", - "PSS_IMUX_B28_1", - "PSS_IMUX_B28_10", - "PSS_IMUX_B28_11", - "PSS_IMUX_B28_12", - "PSS_IMUX_B28_13", - "PSS_IMUX_B28_14", - "PSS_IMUX_B28_15", - "PSS_IMUX_B28_16", - "PSS_IMUX_B28_17", - "PSS_IMUX_B28_18", - "PSS_IMUX_B28_19", - "PSS_IMUX_B28_2", - "PSS_IMUX_B28_3", - "PSS_IMUX_B28_4", - "PSS_IMUX_B28_5", - "PSS_IMUX_B28_6", - "PSS_IMUX_B28_7", - "PSS_IMUX_B28_8", - "PSS_IMUX_B28_9", - "PSS_IMUX_B29_0", - "PSS_IMUX_B29_1", - "PSS_IMUX_B29_10", - "PSS_IMUX_B29_11", - "PSS_IMUX_B29_12", - "PSS_IMUX_B29_13", - "PSS_IMUX_B29_14", - "PSS_IMUX_B29_15", - "PSS_IMUX_B29_16", - "PSS_IMUX_B29_17", - "PSS_IMUX_B29_18", - "PSS_IMUX_B29_19", - "PSS_IMUX_B29_2", - "PSS_IMUX_B29_3", - "PSS_IMUX_B29_4", - "PSS_IMUX_B29_5", - "PSS_IMUX_B29_6", - "PSS_IMUX_B29_7", - "PSS_IMUX_B29_8", - "PSS_IMUX_B29_9", - "PSS_IMUX_B2_0", - "PSS_IMUX_B2_1", - "PSS_IMUX_B2_10", - "PSS_IMUX_B2_11", - "PSS_IMUX_B2_12", - "PSS_IMUX_B2_13", - "PSS_IMUX_B2_14", - "PSS_IMUX_B2_15", - "PSS_IMUX_B2_16", - "PSS_IMUX_B2_17", - "PSS_IMUX_B2_18", - "PSS_IMUX_B2_19", - "PSS_IMUX_B2_2", - "PSS_IMUX_B2_3", - "PSS_IMUX_B2_4", - "PSS_IMUX_B2_5", - "PSS_IMUX_B2_6", - "PSS_IMUX_B2_7", - "PSS_IMUX_B2_8", - "PSS_IMUX_B2_9", - "PSS_IMUX_B30_0", - "PSS_IMUX_B30_1", - "PSS_IMUX_B30_10", - "PSS_IMUX_B30_11", - "PSS_IMUX_B30_12", - "PSS_IMUX_B30_13", - "PSS_IMUX_B30_14", - "PSS_IMUX_B30_15", - "PSS_IMUX_B30_16", - "PSS_IMUX_B30_17", - "PSS_IMUX_B30_18", - "PSS_IMUX_B30_19", - "PSS_IMUX_B30_2", - "PSS_IMUX_B30_3", - "PSS_IMUX_B30_4", - "PSS_IMUX_B30_5", - "PSS_IMUX_B30_6", - "PSS_IMUX_B30_7", - "PSS_IMUX_B30_8", - "PSS_IMUX_B30_9", - "PSS_IMUX_B31_0", - "PSS_IMUX_B31_1", - "PSS_IMUX_B31_10", - "PSS_IMUX_B31_11", - "PSS_IMUX_B31_12", - "PSS_IMUX_B31_13", - "PSS_IMUX_B31_14", - "PSS_IMUX_B31_15", - "PSS_IMUX_B31_16", - "PSS_IMUX_B31_17", - "PSS_IMUX_B31_18", - "PSS_IMUX_B31_19", - "PSS_IMUX_B31_2", - "PSS_IMUX_B31_3", - "PSS_IMUX_B31_4", - "PSS_IMUX_B31_5", - "PSS_IMUX_B31_6", - "PSS_IMUX_B31_7", - "PSS_IMUX_B31_8", - "PSS_IMUX_B31_9", - "PSS_IMUX_B32_0", - "PSS_IMUX_B32_1", - "PSS_IMUX_B32_10", - "PSS_IMUX_B32_11", - "PSS_IMUX_B32_12", - "PSS_IMUX_B32_13", - "PSS_IMUX_B32_14", - "PSS_IMUX_B32_15", - "PSS_IMUX_B32_16", - "PSS_IMUX_B32_17", - "PSS_IMUX_B32_18", - "PSS_IMUX_B32_19", - "PSS_IMUX_B32_2", - "PSS_IMUX_B32_3", - "PSS_IMUX_B32_4", - "PSS_IMUX_B32_5", - "PSS_IMUX_B32_6", - "PSS_IMUX_B32_7", - "PSS_IMUX_B32_8", - "PSS_IMUX_B32_9", - "PSS_IMUX_B33_0", - "PSS_IMUX_B33_1", - "PSS_IMUX_B33_10", - "PSS_IMUX_B33_11", - "PSS_IMUX_B33_12", - "PSS_IMUX_B33_13", - "PSS_IMUX_B33_14", - "PSS_IMUX_B33_15", - "PSS_IMUX_B33_16", - "PSS_IMUX_B33_17", - "PSS_IMUX_B33_18", - "PSS_IMUX_B33_19", - "PSS_IMUX_B33_2", - "PSS_IMUX_B33_3", - "PSS_IMUX_B33_4", - "PSS_IMUX_B33_5", - "PSS_IMUX_B33_6", - "PSS_IMUX_B33_7", - "PSS_IMUX_B33_8", - "PSS_IMUX_B33_9", - "PSS_IMUX_B34_0", - "PSS_IMUX_B34_1", - "PSS_IMUX_B34_10", - "PSS_IMUX_B34_11", - "PSS_IMUX_B34_12", - "PSS_IMUX_B34_13", - "PSS_IMUX_B34_14", - "PSS_IMUX_B34_15", - "PSS_IMUX_B34_16", - "PSS_IMUX_B34_17", - "PSS_IMUX_B34_18", - "PSS_IMUX_B34_19", - "PSS_IMUX_B34_2", - "PSS_IMUX_B34_3", - "PSS_IMUX_B34_4", - "PSS_IMUX_B34_5", - "PSS_IMUX_B34_6", - "PSS_IMUX_B34_7", - "PSS_IMUX_B34_8", - "PSS_IMUX_B34_9", - "PSS_IMUX_B35_0", - "PSS_IMUX_B35_1", - "PSS_IMUX_B35_10", - "PSS_IMUX_B35_11", - "PSS_IMUX_B35_12", - "PSS_IMUX_B35_13", - "PSS_IMUX_B35_14", - "PSS_IMUX_B35_15", - "PSS_IMUX_B35_16", - "PSS_IMUX_B35_17", - "PSS_IMUX_B35_18", - "PSS_IMUX_B35_19", - "PSS_IMUX_B35_2", - "PSS_IMUX_B35_3", - "PSS_IMUX_B35_4", - "PSS_IMUX_B35_5", - "PSS_IMUX_B35_6", - "PSS_IMUX_B35_7", - "PSS_IMUX_B35_8", - "PSS_IMUX_B35_9", - "PSS_IMUX_B36_0", - "PSS_IMUX_B36_1", - "PSS_IMUX_B36_10", - "PSS_IMUX_B36_11", - "PSS_IMUX_B36_12", - "PSS_IMUX_B36_13", - "PSS_IMUX_B36_14", - "PSS_IMUX_B36_15", - "PSS_IMUX_B36_16", - "PSS_IMUX_B36_17", - "PSS_IMUX_B36_18", - "PSS_IMUX_B36_19", - "PSS_IMUX_B36_2", - "PSS_IMUX_B36_3", - "PSS_IMUX_B36_4", - "PSS_IMUX_B36_5", - "PSS_IMUX_B36_6", - "PSS_IMUX_B36_7", - "PSS_IMUX_B36_8", - "PSS_IMUX_B36_9", - "PSS_IMUX_B37_0", - "PSS_IMUX_B37_1", - "PSS_IMUX_B37_10", - "PSS_IMUX_B37_11", - "PSS_IMUX_B37_12", - "PSS_IMUX_B37_13", - "PSS_IMUX_B37_14", - "PSS_IMUX_B37_15", - "PSS_IMUX_B37_16", - "PSS_IMUX_B37_17", - "PSS_IMUX_B37_18", - "PSS_IMUX_B37_19", - "PSS_IMUX_B37_2", - "PSS_IMUX_B37_3", - "PSS_IMUX_B37_4", - "PSS_IMUX_B37_5", - "PSS_IMUX_B37_6", - "PSS_IMUX_B37_7", - "PSS_IMUX_B37_8", - "PSS_IMUX_B37_9", - "PSS_IMUX_B38_0", - "PSS_IMUX_B38_1", - "PSS_IMUX_B38_10", - "PSS_IMUX_B38_11", - "PSS_IMUX_B38_12", - "PSS_IMUX_B38_13", - "PSS_IMUX_B38_14", - "PSS_IMUX_B38_15", - "PSS_IMUX_B38_16", - "PSS_IMUX_B38_17", - "PSS_IMUX_B38_18", - "PSS_IMUX_B38_19", - "PSS_IMUX_B38_2", - "PSS_IMUX_B38_3", - "PSS_IMUX_B38_4", - "PSS_IMUX_B38_5", - "PSS_IMUX_B38_6", - "PSS_IMUX_B38_7", - "PSS_IMUX_B38_8", - "PSS_IMUX_B38_9", - "PSS_IMUX_B39_0", - "PSS_IMUX_B39_1", - "PSS_IMUX_B39_10", - "PSS_IMUX_B39_11", - "PSS_IMUX_B39_12", - "PSS_IMUX_B39_13", - "PSS_IMUX_B39_14", - "PSS_IMUX_B39_15", - "PSS_IMUX_B39_16", - "PSS_IMUX_B39_17", - "PSS_IMUX_B39_18", - "PSS_IMUX_B39_19", - "PSS_IMUX_B39_2", - "PSS_IMUX_B39_3", - "PSS_IMUX_B39_4", - "PSS_IMUX_B39_5", - "PSS_IMUX_B39_6", - "PSS_IMUX_B39_7", - "PSS_IMUX_B39_8", - "PSS_IMUX_B39_9", - "PSS_IMUX_B3_0", - "PSS_IMUX_B3_1", - "PSS_IMUX_B3_10", - "PSS_IMUX_B3_11", - "PSS_IMUX_B3_12", - "PSS_IMUX_B3_13", - "PSS_IMUX_B3_14", - "PSS_IMUX_B3_15", - "PSS_IMUX_B3_16", - "PSS_IMUX_B3_17", - "PSS_IMUX_B3_18", - "PSS_IMUX_B3_19", - "PSS_IMUX_B3_2", - "PSS_IMUX_B3_3", - "PSS_IMUX_B3_4", - "PSS_IMUX_B3_5", - "PSS_IMUX_B3_6", - "PSS_IMUX_B3_7", - "PSS_IMUX_B3_8", - "PSS_IMUX_B3_9", - "PSS_IMUX_B40_0", - "PSS_IMUX_B40_1", - "PSS_IMUX_B40_10", - "PSS_IMUX_B40_11", - "PSS_IMUX_B40_12", - "PSS_IMUX_B40_13", - "PSS_IMUX_B40_14", - "PSS_IMUX_B40_15", - "PSS_IMUX_B40_16", - "PSS_IMUX_B40_17", - "PSS_IMUX_B40_18", - "PSS_IMUX_B40_19", - "PSS_IMUX_B40_2", - "PSS_IMUX_B40_3", - "PSS_IMUX_B40_4", - "PSS_IMUX_B40_5", - "PSS_IMUX_B40_6", - "PSS_IMUX_B40_7", - "PSS_IMUX_B40_8", - "PSS_IMUX_B40_9", - "PSS_IMUX_B41_0", - "PSS_IMUX_B41_1", - "PSS_IMUX_B41_10", - "PSS_IMUX_B41_11", - "PSS_IMUX_B41_12", - "PSS_IMUX_B41_13", - "PSS_IMUX_B41_14", - "PSS_IMUX_B41_15", - "PSS_IMUX_B41_16", - "PSS_IMUX_B41_17", - "PSS_IMUX_B41_18", - "PSS_IMUX_B41_19", - "PSS_IMUX_B41_2", - "PSS_IMUX_B41_3", - "PSS_IMUX_B41_4", - "PSS_IMUX_B41_5", - "PSS_IMUX_B41_6", - "PSS_IMUX_B41_7", - "PSS_IMUX_B41_8", - "PSS_IMUX_B41_9", - "PSS_IMUX_B42_0", - "PSS_IMUX_B42_1", - "PSS_IMUX_B42_10", - "PSS_IMUX_B42_11", - "PSS_IMUX_B42_12", - "PSS_IMUX_B42_13", - "PSS_IMUX_B42_14", - "PSS_IMUX_B42_15", - "PSS_IMUX_B42_16", - "PSS_IMUX_B42_17", - "PSS_IMUX_B42_18", - "PSS_IMUX_B42_19", - "PSS_IMUX_B42_2", - "PSS_IMUX_B42_3", - "PSS_IMUX_B42_4", - "PSS_IMUX_B42_5", - "PSS_IMUX_B42_6", - "PSS_IMUX_B42_7", - "PSS_IMUX_B42_8", - "PSS_IMUX_B42_9", - "PSS_IMUX_B43_0", - "PSS_IMUX_B43_1", - "PSS_IMUX_B43_10", - "PSS_IMUX_B43_11", - "PSS_IMUX_B43_12", - "PSS_IMUX_B43_13", - "PSS_IMUX_B43_14", - "PSS_IMUX_B43_15", - "PSS_IMUX_B43_16", - "PSS_IMUX_B43_17", - "PSS_IMUX_B43_18", - "PSS_IMUX_B43_19", - "PSS_IMUX_B43_2", - "PSS_IMUX_B43_3", - "PSS_IMUX_B43_4", - "PSS_IMUX_B43_5", - "PSS_IMUX_B43_6", - "PSS_IMUX_B43_7", - "PSS_IMUX_B43_8", - "PSS_IMUX_B43_9", - "PSS_IMUX_B44_0", - "PSS_IMUX_B44_1", - "PSS_IMUX_B44_10", - "PSS_IMUX_B44_11", - "PSS_IMUX_B44_12", - "PSS_IMUX_B44_13", - "PSS_IMUX_B44_14", - "PSS_IMUX_B44_15", - "PSS_IMUX_B44_16", - "PSS_IMUX_B44_17", - "PSS_IMUX_B44_18", - "PSS_IMUX_B44_19", - "PSS_IMUX_B44_2", - "PSS_IMUX_B44_3", - "PSS_IMUX_B44_4", - "PSS_IMUX_B44_5", - "PSS_IMUX_B44_6", - "PSS_IMUX_B44_7", - "PSS_IMUX_B44_8", - "PSS_IMUX_B44_9", - "PSS_IMUX_B45_0", - "PSS_IMUX_B45_1", - "PSS_IMUX_B45_10", - "PSS_IMUX_B45_11", - "PSS_IMUX_B45_12", - "PSS_IMUX_B45_13", - "PSS_IMUX_B45_14", - "PSS_IMUX_B45_15", - "PSS_IMUX_B45_16", - "PSS_IMUX_B45_17", - "PSS_IMUX_B45_18", - "PSS_IMUX_B45_19", - "PSS_IMUX_B45_2", - "PSS_IMUX_B45_3", - "PSS_IMUX_B45_4", - "PSS_IMUX_B45_5", - "PSS_IMUX_B45_6", - "PSS_IMUX_B45_7", - "PSS_IMUX_B45_8", - "PSS_IMUX_B45_9", - "PSS_IMUX_B46_0", - "PSS_IMUX_B46_1", - "PSS_IMUX_B46_10", - "PSS_IMUX_B46_11", - "PSS_IMUX_B46_12", - "PSS_IMUX_B46_13", - "PSS_IMUX_B46_14", - "PSS_IMUX_B46_15", - "PSS_IMUX_B46_16", - "PSS_IMUX_B46_17", - "PSS_IMUX_B46_18", - "PSS_IMUX_B46_19", - "PSS_IMUX_B46_2", - "PSS_IMUX_B46_3", - "PSS_IMUX_B46_4", - "PSS_IMUX_B46_5", - "PSS_IMUX_B46_6", - "PSS_IMUX_B46_7", - "PSS_IMUX_B46_8", - "PSS_IMUX_B46_9", - "PSS_IMUX_B47_0", - "PSS_IMUX_B47_1", - "PSS_IMUX_B47_10", - "PSS_IMUX_B47_11", - "PSS_IMUX_B47_12", - "PSS_IMUX_B47_13", - "PSS_IMUX_B47_14", - "PSS_IMUX_B47_15", - "PSS_IMUX_B47_16", - "PSS_IMUX_B47_17", - "PSS_IMUX_B47_18", - "PSS_IMUX_B47_19", - "PSS_IMUX_B47_2", - "PSS_IMUX_B47_3", - "PSS_IMUX_B47_4", - "PSS_IMUX_B47_5", - "PSS_IMUX_B47_6", - "PSS_IMUX_B47_7", - "PSS_IMUX_B47_8", - "PSS_IMUX_B47_9", - "PSS_IMUX_B4_0", - "PSS_IMUX_B4_1", - "PSS_IMUX_B4_10", - "PSS_IMUX_B4_11", - "PSS_IMUX_B4_12", - "PSS_IMUX_B4_13", - "PSS_IMUX_B4_14", - "PSS_IMUX_B4_15", - "PSS_IMUX_B4_16", - "PSS_IMUX_B4_17", - "PSS_IMUX_B4_18", - "PSS_IMUX_B4_19", - "PSS_IMUX_B4_2", - "PSS_IMUX_B4_3", - "PSS_IMUX_B4_4", - "PSS_IMUX_B4_5", - "PSS_IMUX_B4_6", - "PSS_IMUX_B4_7", - "PSS_IMUX_B4_8", - "PSS_IMUX_B4_9", - "PSS_IMUX_B5_0", - "PSS_IMUX_B5_1", - "PSS_IMUX_B5_10", - "PSS_IMUX_B5_11", - "PSS_IMUX_B5_12", - "PSS_IMUX_B5_13", - "PSS_IMUX_B5_14", - "PSS_IMUX_B5_15", - "PSS_IMUX_B5_16", - "PSS_IMUX_B5_17", - "PSS_IMUX_B5_18", - "PSS_IMUX_B5_19", - "PSS_IMUX_B5_2", - "PSS_IMUX_B5_3", - "PSS_IMUX_B5_4", - "PSS_IMUX_B5_5", - "PSS_IMUX_B5_6", - "PSS_IMUX_B5_7", - "PSS_IMUX_B5_8", - "PSS_IMUX_B5_9", - "PSS_IMUX_B6_0", - "PSS_IMUX_B6_1", - "PSS_IMUX_B6_10", - "PSS_IMUX_B6_11", - "PSS_IMUX_B6_12", - "PSS_IMUX_B6_13", - "PSS_IMUX_B6_14", - "PSS_IMUX_B6_15", - "PSS_IMUX_B6_16", - "PSS_IMUX_B6_17", - "PSS_IMUX_B6_18", - "PSS_IMUX_B6_19", - "PSS_IMUX_B6_2", - "PSS_IMUX_B6_3", - "PSS_IMUX_B6_4", - "PSS_IMUX_B6_5", - "PSS_IMUX_B6_6", - "PSS_IMUX_B6_7", - "PSS_IMUX_B6_8", - "PSS_IMUX_B6_9", - "PSS_IMUX_B7_0", - "PSS_IMUX_B7_1", - "PSS_IMUX_B7_10", - "PSS_IMUX_B7_11", - "PSS_IMUX_B7_12", - "PSS_IMUX_B7_13", - "PSS_IMUX_B7_14", - "PSS_IMUX_B7_15", - "PSS_IMUX_B7_16", - "PSS_IMUX_B7_17", - "PSS_IMUX_B7_18", - "PSS_IMUX_B7_19", - "PSS_IMUX_B7_2", - "PSS_IMUX_B7_3", - "PSS_IMUX_B7_4", - "PSS_IMUX_B7_5", - "PSS_IMUX_B7_6", - "PSS_IMUX_B7_7", - "PSS_IMUX_B7_8", - "PSS_IMUX_B7_9", - "PSS_IMUX_B8_0", - "PSS_IMUX_B8_1", - "PSS_IMUX_B8_10", - "PSS_IMUX_B8_11", - "PSS_IMUX_B8_12", - "PSS_IMUX_B8_13", - "PSS_IMUX_B8_14", - "PSS_IMUX_B8_15", - "PSS_IMUX_B8_16", - "PSS_IMUX_B8_17", - "PSS_IMUX_B8_18", - "PSS_IMUX_B8_19", - "PSS_IMUX_B8_2", - "PSS_IMUX_B8_3", - "PSS_IMUX_B8_4", - "PSS_IMUX_B8_5", - "PSS_IMUX_B8_6", - "PSS_IMUX_B8_7", - "PSS_IMUX_B8_8", - "PSS_IMUX_B8_9", - "PSS_IMUX_B9_0", - "PSS_IMUX_B9_1", - "PSS_IMUX_B9_10", - "PSS_IMUX_B9_11", - "PSS_IMUX_B9_12", - "PSS_IMUX_B9_13", - "PSS_IMUX_B9_14", - "PSS_IMUX_B9_15", - "PSS_IMUX_B9_16", - "PSS_IMUX_B9_17", - "PSS_IMUX_B9_18", - "PSS_IMUX_B9_19", - "PSS_IMUX_B9_2", - "PSS_IMUX_B9_3", - "PSS_IMUX_B9_4", - "PSS_IMUX_B9_5", - "PSS_IMUX_B9_6", - "PSS_IMUX_B9_7", - "PSS_IMUX_B9_8", - "PSS_IMUX_B9_9", - "PSS_LOGIC_OUTS0_0", - "PSS_LOGIC_OUTS0_1", - "PSS_LOGIC_OUTS0_10", - "PSS_LOGIC_OUTS0_11", - "PSS_LOGIC_OUTS0_12", - "PSS_LOGIC_OUTS0_13", - "PSS_LOGIC_OUTS0_14", - "PSS_LOGIC_OUTS0_15", - "PSS_LOGIC_OUTS0_16", - "PSS_LOGIC_OUTS0_17", - "PSS_LOGIC_OUTS0_18", - "PSS_LOGIC_OUTS0_19", - "PSS_LOGIC_OUTS0_2", - "PSS_LOGIC_OUTS0_3", - "PSS_LOGIC_OUTS0_4", - "PSS_LOGIC_OUTS0_5", - "PSS_LOGIC_OUTS0_6", - "PSS_LOGIC_OUTS0_7", - "PSS_LOGIC_OUTS0_8", - "PSS_LOGIC_OUTS0_9", - "PSS_LOGIC_OUTS10_0", - "PSS_LOGIC_OUTS10_1", - "PSS_LOGIC_OUTS10_10", - "PSS_LOGIC_OUTS10_11", - "PSS_LOGIC_OUTS10_12", - "PSS_LOGIC_OUTS10_13", - "PSS_LOGIC_OUTS10_14", - "PSS_LOGIC_OUTS10_15", - "PSS_LOGIC_OUTS10_16", - "PSS_LOGIC_OUTS10_17", - "PSS_LOGIC_OUTS10_18", - "PSS_LOGIC_OUTS10_19", - "PSS_LOGIC_OUTS10_2", - "PSS_LOGIC_OUTS10_3", - "PSS_LOGIC_OUTS10_4", - "PSS_LOGIC_OUTS10_5", - "PSS_LOGIC_OUTS10_6", - "PSS_LOGIC_OUTS10_7", - "PSS_LOGIC_OUTS10_8", - "PSS_LOGIC_OUTS10_9", - "PSS_LOGIC_OUTS11_0", - "PSS_LOGIC_OUTS11_1", - "PSS_LOGIC_OUTS11_10", - "PSS_LOGIC_OUTS11_11", - "PSS_LOGIC_OUTS11_12", - "PSS_LOGIC_OUTS11_13", - "PSS_LOGIC_OUTS11_14", - "PSS_LOGIC_OUTS11_15", - "PSS_LOGIC_OUTS11_16", - "PSS_LOGIC_OUTS11_17", - "PSS_LOGIC_OUTS11_18", - "PSS_LOGIC_OUTS11_19", - "PSS_LOGIC_OUTS11_2", - "PSS_LOGIC_OUTS11_3", - "PSS_LOGIC_OUTS11_4", - "PSS_LOGIC_OUTS11_5", - "PSS_LOGIC_OUTS11_6", - "PSS_LOGIC_OUTS11_7", - "PSS_LOGIC_OUTS11_8", - "PSS_LOGIC_OUTS11_9", - "PSS_LOGIC_OUTS12_0", - "PSS_LOGIC_OUTS12_1", - "PSS_LOGIC_OUTS12_10", - "PSS_LOGIC_OUTS12_11", - "PSS_LOGIC_OUTS12_12", - "PSS_LOGIC_OUTS12_13", - "PSS_LOGIC_OUTS12_14", - "PSS_LOGIC_OUTS12_15", - "PSS_LOGIC_OUTS12_16", - "PSS_LOGIC_OUTS12_17", - "PSS_LOGIC_OUTS12_18", - "PSS_LOGIC_OUTS12_19", - "PSS_LOGIC_OUTS12_2", - "PSS_LOGIC_OUTS12_3", - "PSS_LOGIC_OUTS12_4", - "PSS_LOGIC_OUTS12_5", - "PSS_LOGIC_OUTS12_6", - "PSS_LOGIC_OUTS12_7", - "PSS_LOGIC_OUTS12_8", - "PSS_LOGIC_OUTS12_9", - "PSS_LOGIC_OUTS13_0", - "PSS_LOGIC_OUTS13_1", - "PSS_LOGIC_OUTS13_10", - "PSS_LOGIC_OUTS13_11", - "PSS_LOGIC_OUTS13_12", - "PSS_LOGIC_OUTS13_13", - "PSS_LOGIC_OUTS13_14", - "PSS_LOGIC_OUTS13_15", - "PSS_LOGIC_OUTS13_16", - "PSS_LOGIC_OUTS13_17", - "PSS_LOGIC_OUTS13_18", - "PSS_LOGIC_OUTS13_19", - "PSS_LOGIC_OUTS13_2", - "PSS_LOGIC_OUTS13_3", - "PSS_LOGIC_OUTS13_4", - "PSS_LOGIC_OUTS13_5", - "PSS_LOGIC_OUTS13_6", - "PSS_LOGIC_OUTS13_7", - "PSS_LOGIC_OUTS13_8", - "PSS_LOGIC_OUTS13_9", - "PSS_LOGIC_OUTS14_0", - "PSS_LOGIC_OUTS14_1", - "PSS_LOGIC_OUTS14_10", - "PSS_LOGIC_OUTS14_11", - "PSS_LOGIC_OUTS14_12", - "PSS_LOGIC_OUTS14_13", - "PSS_LOGIC_OUTS14_14", - "PSS_LOGIC_OUTS14_15", - "PSS_LOGIC_OUTS14_16", - "PSS_LOGIC_OUTS14_17", - "PSS_LOGIC_OUTS14_18", - "PSS_LOGIC_OUTS14_19", - "PSS_LOGIC_OUTS14_2", - "PSS_LOGIC_OUTS14_3", - "PSS_LOGIC_OUTS14_4", - "PSS_LOGIC_OUTS14_5", - "PSS_LOGIC_OUTS14_6", - "PSS_LOGIC_OUTS14_7", - "PSS_LOGIC_OUTS14_8", - "PSS_LOGIC_OUTS14_9", - "PSS_LOGIC_OUTS15_0", - "PSS_LOGIC_OUTS15_1", - "PSS_LOGIC_OUTS15_10", - "PSS_LOGIC_OUTS15_11", - "PSS_LOGIC_OUTS15_12", - "PSS_LOGIC_OUTS15_13", - "PSS_LOGIC_OUTS15_14", - "PSS_LOGIC_OUTS15_15", - "PSS_LOGIC_OUTS15_16", - "PSS_LOGIC_OUTS15_17", - "PSS_LOGIC_OUTS15_18", - "PSS_LOGIC_OUTS15_19", - "PSS_LOGIC_OUTS15_2", - "PSS_LOGIC_OUTS15_3", - "PSS_LOGIC_OUTS15_4", - "PSS_LOGIC_OUTS15_5", - "PSS_LOGIC_OUTS15_6", - "PSS_LOGIC_OUTS15_7", - "PSS_LOGIC_OUTS15_8", - "PSS_LOGIC_OUTS15_9", - "PSS_LOGIC_OUTS16_0", - "PSS_LOGIC_OUTS16_1", - "PSS_LOGIC_OUTS16_10", - "PSS_LOGIC_OUTS16_11", - "PSS_LOGIC_OUTS16_12", - "PSS_LOGIC_OUTS16_13", - "PSS_LOGIC_OUTS16_14", - "PSS_LOGIC_OUTS16_15", - "PSS_LOGIC_OUTS16_16", - "PSS_LOGIC_OUTS16_17", - "PSS_LOGIC_OUTS16_18", - "PSS_LOGIC_OUTS16_19", - "PSS_LOGIC_OUTS16_2", - "PSS_LOGIC_OUTS16_3", - "PSS_LOGIC_OUTS16_4", - "PSS_LOGIC_OUTS16_5", - "PSS_LOGIC_OUTS16_6", - "PSS_LOGIC_OUTS16_7", - "PSS_LOGIC_OUTS16_8", - "PSS_LOGIC_OUTS16_9", - "PSS_LOGIC_OUTS17_0", - "PSS_LOGIC_OUTS17_1", - "PSS_LOGIC_OUTS17_10", - "PSS_LOGIC_OUTS17_11", - "PSS_LOGIC_OUTS17_12", - "PSS_LOGIC_OUTS17_13", - "PSS_LOGIC_OUTS17_14", - "PSS_LOGIC_OUTS17_15", - "PSS_LOGIC_OUTS17_16", - "PSS_LOGIC_OUTS17_17", - "PSS_LOGIC_OUTS17_18", - "PSS_LOGIC_OUTS17_19", - "PSS_LOGIC_OUTS17_2", - "PSS_LOGIC_OUTS17_3", - "PSS_LOGIC_OUTS17_4", - "PSS_LOGIC_OUTS17_5", - "PSS_LOGIC_OUTS17_6", - "PSS_LOGIC_OUTS17_7", - "PSS_LOGIC_OUTS17_8", - "PSS_LOGIC_OUTS17_9", - "PSS_LOGIC_OUTS18_0", - "PSS_LOGIC_OUTS18_1", - "PSS_LOGIC_OUTS18_10", - "PSS_LOGIC_OUTS18_11", - "PSS_LOGIC_OUTS18_12", - "PSS_LOGIC_OUTS18_13", - "PSS_LOGIC_OUTS18_14", - "PSS_LOGIC_OUTS18_15", - "PSS_LOGIC_OUTS18_16", - "PSS_LOGIC_OUTS18_17", - "PSS_LOGIC_OUTS18_18", - "PSS_LOGIC_OUTS18_19", - "PSS_LOGIC_OUTS18_2", - "PSS_LOGIC_OUTS18_3", - "PSS_LOGIC_OUTS18_4", - "PSS_LOGIC_OUTS18_5", - "PSS_LOGIC_OUTS18_6", - "PSS_LOGIC_OUTS18_7", - "PSS_LOGIC_OUTS18_8", - "PSS_LOGIC_OUTS18_9", - "PSS_LOGIC_OUTS19_0", - "PSS_LOGIC_OUTS19_1", - "PSS_LOGIC_OUTS19_10", - "PSS_LOGIC_OUTS19_11", - "PSS_LOGIC_OUTS19_12", - "PSS_LOGIC_OUTS19_13", - "PSS_LOGIC_OUTS19_14", - "PSS_LOGIC_OUTS19_15", - "PSS_LOGIC_OUTS19_16", - "PSS_LOGIC_OUTS19_17", - "PSS_LOGIC_OUTS19_18", - "PSS_LOGIC_OUTS19_19", - "PSS_LOGIC_OUTS19_2", - "PSS_LOGIC_OUTS19_3", - "PSS_LOGIC_OUTS19_4", - "PSS_LOGIC_OUTS19_5", - "PSS_LOGIC_OUTS19_6", - "PSS_LOGIC_OUTS19_7", - "PSS_LOGIC_OUTS19_8", - "PSS_LOGIC_OUTS19_9", - "PSS_LOGIC_OUTS1_0", - "PSS_LOGIC_OUTS1_1", - "PSS_LOGIC_OUTS1_10", - "PSS_LOGIC_OUTS1_11", - "PSS_LOGIC_OUTS1_12", - "PSS_LOGIC_OUTS1_13", - "PSS_LOGIC_OUTS1_14", - "PSS_LOGIC_OUTS1_15", - "PSS_LOGIC_OUTS1_16", - "PSS_LOGIC_OUTS1_17", - "PSS_LOGIC_OUTS1_18", - "PSS_LOGIC_OUTS1_19", - "PSS_LOGIC_OUTS1_2", - "PSS_LOGIC_OUTS1_3", - "PSS_LOGIC_OUTS1_4", - "PSS_LOGIC_OUTS1_5", - "PSS_LOGIC_OUTS1_6", - "PSS_LOGIC_OUTS1_7", - "PSS_LOGIC_OUTS1_8", - "PSS_LOGIC_OUTS1_9", - "PSS_LOGIC_OUTS20_0", - "PSS_LOGIC_OUTS20_1", - "PSS_LOGIC_OUTS20_10", - "PSS_LOGIC_OUTS20_11", - "PSS_LOGIC_OUTS20_12", - "PSS_LOGIC_OUTS20_13", - "PSS_LOGIC_OUTS20_14", - "PSS_LOGIC_OUTS20_15", - "PSS_LOGIC_OUTS20_16", - "PSS_LOGIC_OUTS20_17", - "PSS_LOGIC_OUTS20_18", - "PSS_LOGIC_OUTS20_19", - "PSS_LOGIC_OUTS20_2", - "PSS_LOGIC_OUTS20_3", - "PSS_LOGIC_OUTS20_4", - "PSS_LOGIC_OUTS20_5", - "PSS_LOGIC_OUTS20_6", - "PSS_LOGIC_OUTS20_7", - "PSS_LOGIC_OUTS20_8", - "PSS_LOGIC_OUTS20_9", - "PSS_LOGIC_OUTS21_0", - "PSS_LOGIC_OUTS21_1", - "PSS_LOGIC_OUTS21_10", - "PSS_LOGIC_OUTS21_11", - "PSS_LOGIC_OUTS21_12", - "PSS_LOGIC_OUTS21_13", - "PSS_LOGIC_OUTS21_14", - "PSS_LOGIC_OUTS21_15", - "PSS_LOGIC_OUTS21_16", - "PSS_LOGIC_OUTS21_17", - "PSS_LOGIC_OUTS21_18", - "PSS_LOGIC_OUTS21_19", - "PSS_LOGIC_OUTS21_2", - "PSS_LOGIC_OUTS21_3", - "PSS_LOGIC_OUTS21_4", - "PSS_LOGIC_OUTS21_5", - "PSS_LOGIC_OUTS21_6", - "PSS_LOGIC_OUTS21_7", - "PSS_LOGIC_OUTS21_8", - "PSS_LOGIC_OUTS21_9", - "PSS_LOGIC_OUTS22_0", - "PSS_LOGIC_OUTS22_1", - "PSS_LOGIC_OUTS22_10", - "PSS_LOGIC_OUTS22_11", - "PSS_LOGIC_OUTS22_12", - "PSS_LOGIC_OUTS22_13", - "PSS_LOGIC_OUTS22_14", - "PSS_LOGIC_OUTS22_15", - "PSS_LOGIC_OUTS22_16", - "PSS_LOGIC_OUTS22_17", - "PSS_LOGIC_OUTS22_18", - "PSS_LOGIC_OUTS22_19", - "PSS_LOGIC_OUTS22_2", - "PSS_LOGIC_OUTS22_3", - "PSS_LOGIC_OUTS22_4", - "PSS_LOGIC_OUTS22_5", - "PSS_LOGIC_OUTS22_6", - "PSS_LOGIC_OUTS22_7", - "PSS_LOGIC_OUTS22_8", - "PSS_LOGIC_OUTS22_9", - "PSS_LOGIC_OUTS23_0", - "PSS_LOGIC_OUTS23_1", - "PSS_LOGIC_OUTS23_10", - "PSS_LOGIC_OUTS23_11", - "PSS_LOGIC_OUTS23_12", - "PSS_LOGIC_OUTS23_13", - "PSS_LOGIC_OUTS23_14", - "PSS_LOGIC_OUTS23_15", - "PSS_LOGIC_OUTS23_16", - "PSS_LOGIC_OUTS23_17", - "PSS_LOGIC_OUTS23_18", - "PSS_LOGIC_OUTS23_19", - "PSS_LOGIC_OUTS23_2", - "PSS_LOGIC_OUTS23_3", - "PSS_LOGIC_OUTS23_4", - "PSS_LOGIC_OUTS23_5", - "PSS_LOGIC_OUTS23_6", - "PSS_LOGIC_OUTS23_7", - "PSS_LOGIC_OUTS23_8", - "PSS_LOGIC_OUTS23_9", - "PSS_LOGIC_OUTS2_0", - "PSS_LOGIC_OUTS2_1", - "PSS_LOGIC_OUTS2_10", - "PSS_LOGIC_OUTS2_11", - "PSS_LOGIC_OUTS2_12", - "PSS_LOGIC_OUTS2_13", - "PSS_LOGIC_OUTS2_14", - "PSS_LOGIC_OUTS2_15", - "PSS_LOGIC_OUTS2_16", - "PSS_LOGIC_OUTS2_17", - "PSS_LOGIC_OUTS2_18", - "PSS_LOGIC_OUTS2_19", - "PSS_LOGIC_OUTS2_2", - "PSS_LOGIC_OUTS2_3", - "PSS_LOGIC_OUTS2_4", - "PSS_LOGIC_OUTS2_5", - "PSS_LOGIC_OUTS2_6", - "PSS_LOGIC_OUTS2_7", - "PSS_LOGIC_OUTS2_8", - "PSS_LOGIC_OUTS2_9", - "PSS_LOGIC_OUTS3_0", - "PSS_LOGIC_OUTS3_1", - "PSS_LOGIC_OUTS3_10", - "PSS_LOGIC_OUTS3_11", - "PSS_LOGIC_OUTS3_12", - "PSS_LOGIC_OUTS3_13", - "PSS_LOGIC_OUTS3_14", - "PSS_LOGIC_OUTS3_15", - "PSS_LOGIC_OUTS3_16", - "PSS_LOGIC_OUTS3_17", - "PSS_LOGIC_OUTS3_18", - "PSS_LOGIC_OUTS3_19", - "PSS_LOGIC_OUTS3_2", - "PSS_LOGIC_OUTS3_3", - "PSS_LOGIC_OUTS3_4", - "PSS_LOGIC_OUTS3_5", - "PSS_LOGIC_OUTS3_6", - "PSS_LOGIC_OUTS3_7", - "PSS_LOGIC_OUTS3_8", - "PSS_LOGIC_OUTS3_9", - "PSS_LOGIC_OUTS4_0", - "PSS_LOGIC_OUTS4_1", - "PSS_LOGIC_OUTS4_10", - "PSS_LOGIC_OUTS4_11", - "PSS_LOGIC_OUTS4_12", - "PSS_LOGIC_OUTS4_13", - "PSS_LOGIC_OUTS4_14", - "PSS_LOGIC_OUTS4_15", - "PSS_LOGIC_OUTS4_16", - "PSS_LOGIC_OUTS4_17", - "PSS_LOGIC_OUTS4_18", - "PSS_LOGIC_OUTS4_19", - "PSS_LOGIC_OUTS4_2", - "PSS_LOGIC_OUTS4_3", - "PSS_LOGIC_OUTS4_4", - "PSS_LOGIC_OUTS4_5", - "PSS_LOGIC_OUTS4_6", - "PSS_LOGIC_OUTS4_7", - "PSS_LOGIC_OUTS4_8", - "PSS_LOGIC_OUTS4_9", - "PSS_LOGIC_OUTS5_0", - "PSS_LOGIC_OUTS5_1", - "PSS_LOGIC_OUTS5_10", - "PSS_LOGIC_OUTS5_11", - "PSS_LOGIC_OUTS5_12", - "PSS_LOGIC_OUTS5_13", - "PSS_LOGIC_OUTS5_14", - "PSS_LOGIC_OUTS5_15", - "PSS_LOGIC_OUTS5_16", - "PSS_LOGIC_OUTS5_17", - "PSS_LOGIC_OUTS5_18", - "PSS_LOGIC_OUTS5_19", - "PSS_LOGIC_OUTS5_2", - "PSS_LOGIC_OUTS5_3", - "PSS_LOGIC_OUTS5_4", - "PSS_LOGIC_OUTS5_5", - "PSS_LOGIC_OUTS5_6", - "PSS_LOGIC_OUTS5_7", - "PSS_LOGIC_OUTS5_8", - "PSS_LOGIC_OUTS5_9", - "PSS_LOGIC_OUTS6_0", - "PSS_LOGIC_OUTS6_1", - "PSS_LOGIC_OUTS6_10", - "PSS_LOGIC_OUTS6_11", - "PSS_LOGIC_OUTS6_12", - "PSS_LOGIC_OUTS6_13", - "PSS_LOGIC_OUTS6_14", - "PSS_LOGIC_OUTS6_15", - "PSS_LOGIC_OUTS6_16", - "PSS_LOGIC_OUTS6_17", - "PSS_LOGIC_OUTS6_18", - "PSS_LOGIC_OUTS6_19", - "PSS_LOGIC_OUTS6_2", - "PSS_LOGIC_OUTS6_3", - "PSS_LOGIC_OUTS6_4", - "PSS_LOGIC_OUTS6_5", - "PSS_LOGIC_OUTS6_6", - "PSS_LOGIC_OUTS6_7", - "PSS_LOGIC_OUTS6_8", - "PSS_LOGIC_OUTS6_9", - "PSS_LOGIC_OUTS7_0", - "PSS_LOGIC_OUTS7_1", - "PSS_LOGIC_OUTS7_10", - "PSS_LOGIC_OUTS7_11", - "PSS_LOGIC_OUTS7_12", - "PSS_LOGIC_OUTS7_13", - "PSS_LOGIC_OUTS7_14", - "PSS_LOGIC_OUTS7_15", - "PSS_LOGIC_OUTS7_16", - "PSS_LOGIC_OUTS7_17", - "PSS_LOGIC_OUTS7_18", - "PSS_LOGIC_OUTS7_19", - "PSS_LOGIC_OUTS7_2", - "PSS_LOGIC_OUTS7_3", - "PSS_LOGIC_OUTS7_4", - "PSS_LOGIC_OUTS7_5", - "PSS_LOGIC_OUTS7_6", - "PSS_LOGIC_OUTS7_7", - "PSS_LOGIC_OUTS7_8", - "PSS_LOGIC_OUTS7_9", - "PSS_LOGIC_OUTS8_0", - "PSS_LOGIC_OUTS8_1", - "PSS_LOGIC_OUTS8_10", - "PSS_LOGIC_OUTS8_11", - "PSS_LOGIC_OUTS8_12", - "PSS_LOGIC_OUTS8_13", - "PSS_LOGIC_OUTS8_14", - "PSS_LOGIC_OUTS8_15", - "PSS_LOGIC_OUTS8_16", - "PSS_LOGIC_OUTS8_17", - "PSS_LOGIC_OUTS8_18", - "PSS_LOGIC_OUTS8_19", - "PSS_LOGIC_OUTS8_2", - "PSS_LOGIC_OUTS8_3", - "PSS_LOGIC_OUTS8_4", - "PSS_LOGIC_OUTS8_5", - "PSS_LOGIC_OUTS8_6", - "PSS_LOGIC_OUTS8_7", - "PSS_LOGIC_OUTS8_8", - "PSS_LOGIC_OUTS8_9", - "PSS_LOGIC_OUTS9_0", - "PSS_LOGIC_OUTS9_1", - "PSS_LOGIC_OUTS9_10", - "PSS_LOGIC_OUTS9_11", - "PSS_LOGIC_OUTS9_12", - "PSS_LOGIC_OUTS9_13", - "PSS_LOGIC_OUTS9_14", - "PSS_LOGIC_OUTS9_15", - "PSS_LOGIC_OUTS9_16", - "PSS_LOGIC_OUTS9_17", - "PSS_LOGIC_OUTS9_18", - "PSS_LOGIC_OUTS9_19", - "PSS_LOGIC_OUTS9_2", - "PSS_LOGIC_OUTS9_3", - "PSS_LOGIC_OUTS9_4", - "PSS_LOGIC_OUTS9_5", - "PSS_LOGIC_OUTS9_6", - "PSS_LOGIC_OUTS9_7", - "PSS_LOGIC_OUTS9_8", - "PSS_LOGIC_OUTS9_9" - ] + "wires": { + "PSS0_CLK_B0_0": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_1": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_10": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_11": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_12": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_13": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_14": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_15": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_16": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_17": { + "cap": "10.823", + "res": "0.000" + }, + "PSS0_CLK_B0_18": { + "cap": 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"RIOB33.IOB_DIFFO_OUT0->IOB_DIFFO_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_DIFFO_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_DIFFO_OUT0" }, "RIOB33.IOB_O0->>IOB_O_OUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOB_O_OUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOB_O0" }, "RIOB33.IOB_O_OUT0->IOB_O_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_O_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_O_OUT0" }, "RIOB33.IOB_PADOUT0->IOB_DIFFI_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_DIFFI_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_PADOUT0" }, "RIOB33.IOB_PADOUT0->RIOB_MONITOR_P": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOB_MONITOR_P", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_PADOUT0" }, "RIOB33.IOB_PADOUT1->IOB_DIFFI_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_DIFFI_IN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_PADOUT1" }, "RIOB33.IOB_PADOUT1->RIOB_MONITOR_N": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOB_MONITOR_N", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_PADOUT1" }, "RIOB33.IOB_T0->>IOB_T_OUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOB_T_OUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOB_T0" }, "RIOB33.IOB_T_OUT0->IOB_T_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_T_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_T_OUT0" } }, @@ -69,23 +188,176 @@ "name": "X0Y0", "prefix": "IOB", "site_pins": { - "DIFFI_IN": "IOB_DIFFI_IN1", - "DIFFO_IN": "IOB_DIFFO_IN1", - "DIFFO_OUT": "IOB_DIFFO_OUT1", - "DIFF_TERM_INT_EN": "IOB_DIFF_TERM_INT_EN", - "I": "IOB_IBUF1", - "IBUFDISABLE": "IOB_IBUF_DISABLE1", - "INTERMDISABLE": "LIOB_IN_TERM1", - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_0", - "O": "IOB_O1", - "O_IN": "IOB_O_IN1", - "O_OUT": "IOB_O_OUT1", - "PADOUT": "IOB_PADOUT1", - "PD_INT_EN": "IOB_PD_INT_EN_0", - "PU_INT_EN": "IOB_PU_INT_EN_0", - "T": "IOB_T1", - "T_IN": "IOB_T_IN1", - "T_OUT": "IOB_T_OUT1" + "DIFFI_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DIFFI_IN1" + }, + "DIFFO_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DIFFO_IN1" + }, + "DIFFO_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_DIFFO_OUT1" + }, + "DIFF_TERM_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DIFF_TERM_INT_EN" + }, + "I": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_IBUF1" + }, + "IBUFDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_IBUF_DISABLE1" + }, + "INTERMDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOB_IN_TERM1" + }, + "KEEPER_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_KEEPER_INT_EN_0" + }, + "O": { + "cap": "0.001", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "IOB_O1" + }, + "O_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_O_IN1" + }, + "O_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_O_OUT1" + }, + "PADOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_PADOUT1" + }, + "PD_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PD_INT_EN_0" + }, + "PU_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PU_INT_EN_0" + }, + "T": { + "cap": "0.001", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "IOB_T1" + }, + "T_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_T_IN1" + }, + "T_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_T_OUT1" + } }, "type": "IOB33S", "x_coord": 0, @@ -95,23 +367,140 @@ "name": "X0Y1", "prefix": "IOB", "site_pins": { - "DIFFI_IN": "IOB_DIFFI_IN0", + "DIFFI_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DIFFI_IN0" + }, "DIFFO_IN": null, - "DIFFO_OUT": "IOB_DIFFO_OUT0", + "DIFFO_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_DIFFO_OUT0" + }, "DIFF_TERM_INT_EN": null, - "I": "IOB_IBUF0", - "IBUFDISABLE": "IOB_IBUF_DISABLE0", - "INTERMDISABLE": "LIOB_IN_TERM0", - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", - "O": "IOB_O0", + "I": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_IBUF0" + }, + "IBUFDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_IBUF_DISABLE0" + }, + "INTERMDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOB_IN_TERM0" + }, + "KEEPER_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_KEEPER_INT_EN_1" + }, + "O": { + "cap": "0.001", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "IOB_O0" + }, "O_IN": null, - "O_OUT": "IOB_O_OUT0", - "PADOUT": "IOB_PADOUT0", - "PD_INT_EN": "IOB_PD_INT_EN_1", - "PU_INT_EN": "IOB_PU_INT_EN_1", - "T": "IOB_T0", + "O_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_O_OUT0" + }, + "PADOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_PADOUT0" + }, + "PD_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PD_INT_EN_1" + }, + "PU_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PU_INT_EN_1" + }, + "T": { + "cap": "0.001", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "IOB_T0" + }, "T_IN": null, - "T_OUT": "IOB_T_OUT0" + "T_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_T_OUT0" + } }, "type": "IOB33M", "x_coord": 0, @@ -119,290 +508,1034 @@ } ], "tile_type": "RIOB33", - "wires": [ - "IOB_DIFFI_IN0", - "IOB_DIFFI_IN1", - "IOB_DIFFO_IN0", - "IOB_DIFFO_IN1", - "IOB_DIFFO_OUT0", - "IOB_DIFFO_OUT1", - "IOB_DIFF_TERM_INT_EN", - "IOB_DIFF_TERM_INT_EN_STUB", - "IOB_IBUF0", - "IOB_IBUF1", - "IOB_IBUF_DISABLE0", - "IOB_IBUF_DISABLE1", - "IOB_KEEPER_INT_EN_0", - "IOB_KEEPER_INT_EN_1", - "IOB_O0", - "IOB_O1", - "IOB_O_IN0", - "IOB_O_IN1", - "IOB_O_OUT0", - "IOB_O_OUT1", - "IOB_PADOUT0", - "IOB_PADOUT1", - "IOB_PD_INT_EN_0", - "IOB_PD_INT_EN_1", - "IOB_PU_INT_EN_0", - "IOB_PU_INT_EN_1", - "IOB_T0", - "IOB_T1", - "IOB_T_IN0", - "IOB_T_IN1", - "IOB_T_OUT0", - "IOB_T_OUT1", - "LIOB_IN_TERM0", - "LIOB_IN_TERM1", - "RIOB_EE2A0_0", - "RIOB_EE2A0_1", - "RIOB_EE2A1_0", - "RIOB_EE2A1_1", - "RIOB_EE2A2_0", - "RIOB_EE2A2_1", - "RIOB_EE2A3_0", - "RIOB_EE2A3_1", - "RIOB_EE2BEG0_0", - "RIOB_EE2BEG0_1", - "RIOB_EE2BEG1_0", - "RIOB_EE2BEG1_1", - "RIOB_EE2BEG2_0", - "RIOB_EE2BEG2_1", - "RIOB_EE2BEG3_0", - "RIOB_EE2BEG3_1", - "RIOB_EE4A0_0", - "RIOB_EE4A0_1", - "RIOB_EE4A1_0", - "RIOB_EE4A1_1", - "RIOB_EE4A2_0", - "RIOB_EE4A2_1", - "RIOB_EE4A3_0", - "RIOB_EE4A3_1", - "RIOB_EE4B0_0", - "RIOB_EE4B0_1", - "RIOB_EE4B1_0", - "RIOB_EE4B1_1", - "RIOB_EE4B2_0", - "RIOB_EE4B2_1", - "RIOB_EE4B3_0", - "RIOB_EE4B3_1", - "RIOB_EE4BEG0_0", - "RIOB_EE4BEG0_1", - "RIOB_EE4BEG1_0", - "RIOB_EE4BEG1_1", - "RIOB_EE4BEG2_0", - "RIOB_EE4BEG2_1", - "RIOB_EE4BEG3_0", - "RIOB_EE4BEG3_1", - "RIOB_EE4C0_0", - "RIOB_EE4C0_1", - "RIOB_EE4C1_0", - "RIOB_EE4C1_1", - "RIOB_EE4C2_0", - "RIOB_EE4C2_1", - "RIOB_EE4C3_0", - "RIOB_EE4C3_1", - "RIOB_EL1BEG0_0", - "RIOB_EL1BEG0_1", - "RIOB_EL1BEG1_0", - "RIOB_EL1BEG1_1", - "RIOB_EL1BEG2_0", - "RIOB_EL1BEG2_1", - "RIOB_EL1BEG3_0", - "RIOB_EL1BEG3_1", - "RIOB_ER1BEG0_0", - "RIOB_ER1BEG0_1", - "RIOB_ER1BEG1_0", - "RIOB_ER1BEG1_1", - "RIOB_ER1BEG2_0", - "RIOB_ER1BEG2_1", - "RIOB_ER1BEG3_0", - "RIOB_ER1BEG3_1", - "RIOB_LH10_0", - "RIOB_LH10_1", - "RIOB_LH11_0", - "RIOB_LH11_1", - "RIOB_LH12_0", - "RIOB_LH12_1", - "RIOB_LH1_0", - "RIOB_LH1_1", - "RIOB_LH2_0", - "RIOB_LH2_1", - "RIOB_LH3_0", - "RIOB_LH3_1", - "RIOB_LH4_0", - "RIOB_LH4_1", - "RIOB_LH5_0", - "RIOB_LH5_1", - "RIOB_LH6_0", - "RIOB_LH6_1", - "RIOB_LH7_0", - "RIOB_LH7_1", - "RIOB_LH8_0", - "RIOB_LH8_1", - "RIOB_LH9_0", - "RIOB_LH9_1", - "RIOB_MONITOR_N", - "RIOB_MONITOR_P", - "RIOB_NE2A0_0", - "RIOB_NE2A0_1", - "RIOB_NE2A1_0", - "RIOB_NE2A1_1", - "RIOB_NE2A2_0", - "RIOB_NE2A2_1", - "RIOB_NE2A3_0", - "RIOB_NE2A3_1", - "RIOB_NE4BEG0_0", - "RIOB_NE4BEG0_1", - "RIOB_NE4BEG1_0", - "RIOB_NE4BEG1_1", - "RIOB_NE4BEG2_0", - "RIOB_NE4BEG2_1", - "RIOB_NE4BEG3_0", - "RIOB_NE4BEG3_1", - "RIOB_NE4C0_0", - "RIOB_NE4C0_1", - "RIOB_NE4C1_0", - "RIOB_NE4C1_1", - "RIOB_NE4C2_0", - "RIOB_NE4C2_1", - "RIOB_NE4C3_0", - "RIOB_NE4C3_1", - "RIOB_NW2A0_0", - "RIOB_NW2A0_1", - "RIOB_NW2A1_0", - "RIOB_NW2A1_1", - "RIOB_NW2A2_0", - "RIOB_NW2A2_1", - "RIOB_NW2A3_0", - "RIOB_NW2A3_1", - "RIOB_NW4A0_0", - "RIOB_NW4A0_1", - "RIOB_NW4A1_0", - "RIOB_NW4A1_1", - "RIOB_NW4A2_0", - "RIOB_NW4A2_1", - "RIOB_NW4A3_0", - "RIOB_NW4A3_1", - "RIOB_NW4END0_0", - "RIOB_NW4END0_1", - "RIOB_NW4END1_0", - "RIOB_NW4END1_1", - "RIOB_NW4END2_0", - "RIOB_NW4END2_1", - "RIOB_NW4END3_0", - "RIOB_NW4END3_1", - "RIOB_SE2A0_0", - "RIOB_SE2A0_1", - "RIOB_SE2A1_0", - "RIOB_SE2A1_1", - "RIOB_SE2A2_0", - "RIOB_SE2A2_1", - "RIOB_SE2A3_0", - "RIOB_SE2A3_1", - "RIOB_SE4BEG0_0", - "RIOB_SE4BEG0_1", - "RIOB_SE4BEG1_0", - "RIOB_SE4BEG1_1", - "RIOB_SE4BEG2_0", - "RIOB_SE4BEG2_1", - "RIOB_SE4BEG3_0", - "RIOB_SE4BEG3_1", - "RIOB_SE4C0_0", - "RIOB_SE4C0_1", - "RIOB_SE4C1_0", - "RIOB_SE4C1_1", - "RIOB_SE4C2_0", - "RIOB_SE4C2_1", - "RIOB_SE4C3_0", - "RIOB_SE4C3_1", - "RIOB_SW2A0_0", - "RIOB_SW2A0_1", - "RIOB_SW2A1_0", - "RIOB_SW2A1_1", - "RIOB_SW2A2_0", - "RIOB_SW2A2_1", - "RIOB_SW2A3_0", - "RIOB_SW2A3_1", - "RIOB_SW4A0_0", - "RIOB_SW4A0_1", - "RIOB_SW4A1_0", - "RIOB_SW4A1_1", - "RIOB_SW4A2_0", - "RIOB_SW4A2_1", - "RIOB_SW4A3_0", - "RIOB_SW4A3_1", - "RIOB_SW4END0_0", - "RIOB_SW4END0_1", - "RIOB_SW4END1_0", - "RIOB_SW4END1_1", - "RIOB_SW4END2_0", - "RIOB_SW4END2_1", - "RIOB_SW4END3_0", - "RIOB_SW4END3_1", - "RIOB_WL1END0_0", - "RIOB_WL1END0_1", - "RIOB_WL1END1_0", - "RIOB_WL1END1_1", - "RIOB_WL1END2_0", - "RIOB_WL1END2_1", - "RIOB_WL1END3_0", - "RIOB_WL1END3_1", - "RIOB_WR1END0_0", - "RIOB_WR1END0_1", - "RIOB_WR1END1_0", - "RIOB_WR1END1_1", - "RIOB_WR1END2_0", - "RIOB_WR1END2_1", - "RIOB_WR1END3_0", - "RIOB_WR1END3_1", - "RIOB_WW2A0_0", - "RIOB_WW2A0_1", - "RIOB_WW2A1_0", - "RIOB_WW2A1_1", - "RIOB_WW2A2_0", - "RIOB_WW2A2_1", - "RIOB_WW2A3_0", - "RIOB_WW2A3_1", - "RIOB_WW2END0_0", - "RIOB_WW2END0_1", - "RIOB_WW2END1_0", - "RIOB_WW2END1_1", - "RIOB_WW2END2_0", - "RIOB_WW2END2_1", - "RIOB_WW2END3_0", - "RIOB_WW2END3_1", - "RIOB_WW4A0_0", - "RIOB_WW4A0_1", - "RIOB_WW4A1_0", - "RIOB_WW4A1_1", - "RIOB_WW4A2_0", - "RIOB_WW4A2_1", - "RIOB_WW4A3_0", - "RIOB_WW4A3_1", - "RIOB_WW4B0_0", - "RIOB_WW4B0_1", - "RIOB_WW4B1_0", - "RIOB_WW4B1_1", - "RIOB_WW4B2_0", - "RIOB_WW4B2_1", - "RIOB_WW4B3_0", - "RIOB_WW4B3_1", - "RIOB_WW4C0_0", - "RIOB_WW4C0_1", - "RIOB_WW4C1_0", - "RIOB_WW4C1_1", - "RIOB_WW4C2_0", - "RIOB_WW4C2_1", - "RIOB_WW4C3_0", - "RIOB_WW4C3_1", - "RIOB_WW4END0_0", - "RIOB_WW4END0_1", - "RIOB_WW4END1_0", - "RIOB_WW4END1_1", - "RIOB_WW4END2_0", - "RIOB_WW4END2_1", - "RIOB_WW4END3_0", - "RIOB_WW4END3_1" - ] + "wires": { + "IOB_DIFFI_IN0": null, + "IOB_DIFFI_IN1": null, + "IOB_DIFFO_IN0": null, + "IOB_DIFFO_IN1": null, + "IOB_DIFFO_OUT0": null, + "IOB_DIFFO_OUT1": null, + "IOB_DIFF_TERM_INT_EN": null, + "IOB_DIFF_TERM_INT_EN_STUB": null, + "IOB_IBUF0": null, + "IOB_IBUF1": null, + "IOB_IBUF_DISABLE0": null, + "IOB_IBUF_DISABLE1": null, + "IOB_KEEPER_INT_EN_0": null, + "IOB_KEEPER_INT_EN_1": null, + "IOB_O0": null, + "IOB_O1": null, + "IOB_O_IN0": null, + "IOB_O_IN1": null, + "IOB_O_OUT0": null, + "IOB_O_OUT1": null, + "IOB_PADOUT0": null, + "IOB_PADOUT1": null, + "IOB_PD_INT_EN_0": null, + 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"150.000", + "res": "1024.400" + }, + "RIOB_WR1END1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WR1END1_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WR1END2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WR1END2_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WR1END3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WR1END3_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2A0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2A0_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2A1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2A1_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2A2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2A2_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2A3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2A3_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2END0_0": { + "cap": "150.000", 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"1024.400" + }, + "RIOB_WW4B0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4B0_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4B1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4B1_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4B2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4B2_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4B3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4B3_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4C0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4C0_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4C1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4C1_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4C2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4C2_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4C3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4C3_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4END0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4END0_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4END1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4END1_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4END2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4END2_1": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4END3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4END3_1": { + "cap": "150.000", + "res": "1024.400" + } + } } diff --git a/zynq7/tile_type_RIOB33_SING.json b/zynq7/tile_type_RIOB33_SING.json index 2d401ef..d751ab1 100644 --- a/zynq7/tile_type_RIOB33_SING.json +++ b/zynq7/tile_type_RIOB33_SING.json @@ -7,21 +7,129 @@ "site_pins": { "DIFFI_IN": null, "DIFFO_IN": null, - "DIFFO_OUT": "IOB_DIFFO_OUT0", + "DIFFO_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_DIFFO_OUT0" + }, "DIFF_TERM_INT_EN": null, - "I": "IOB_IBUF0", - "IBUFDISABLE": "IOB_IBUF_DISABLE0", - "INTERMDISABLE": "LIOB_IN_TERM0", - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", - "O": "IOB_O0", + "I": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_IBUF0" + }, + "IBUFDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_IBUF_DISABLE0" + }, + "INTERMDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOB_IN_TERM0" + }, + "KEEPER_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_KEEPER_INT_EN_1" + }, + "O": { + "cap": "0.001", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "IOB_O0" + }, "O_IN": null, - "O_OUT": "IOB_O_OUT0", - "PADOUT": "IOB_PADOUT0", - "PD_INT_EN": "IOB_PD_INT_EN_1", - "PU_INT_EN": "IOB_PU_INT_EN_1", - "T": "IOB_T0", + "O_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_O_OUT0" + }, + "PADOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_PADOUT0" + }, + "PD_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PD_INT_EN_1" + }, + "PU_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PU_INT_EN_1" + }, + "T": { + "cap": "0.001", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "IOB_T0" + }, "T_IN": null, - "T_OUT": "IOB_T_OUT0" + "T_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_T_OUT0" + } }, "type": "IOB33", "x_coord": 0, @@ -29,147 +137,519 @@ } ], "tile_type": "RIOB33_SING", - "wires": [ - "IOB_DIFFI_IN0", - "IOB_DIFFO_IN0", - "IOB_DIFFO_OUT0", - "IOB_DIFF_TERM_INT_EN_STUB", - "IOB_IBUF0", - "IOB_IBUF_DISABLE0", - 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"RIOB_NE2A0_0", - "RIOB_NE2A1_0", - "RIOB_NE2A2_0", - "RIOB_NE2A3_0", - "RIOB_NE4BEG0_0", - "RIOB_NE4BEG1_0", - "RIOB_NE4BEG2_0", - "RIOB_NE4BEG3_0", - "RIOB_NE4C0_0", - "RIOB_NE4C1_0", - "RIOB_NE4C2_0", - "RIOB_NE4C3_0", - "RIOB_NW2A0_0", - "RIOB_NW2A1_0", - "RIOB_NW2A2_0", - "RIOB_NW2A3_0", - "RIOB_NW4A0_0", - "RIOB_NW4A1_0", - "RIOB_NW4A2_0", - "RIOB_NW4A3_0", - "RIOB_NW4END0_0", - "RIOB_NW4END1_0", - "RIOB_NW4END2_0", - "RIOB_NW4END3_0", - "RIOB_SE2A0_0", - "RIOB_SE2A1_0", - "RIOB_SE2A2_0", - "RIOB_SE2A3_0", - "RIOB_SE4BEG0_0", - "RIOB_SE4BEG1_0", - "RIOB_SE4BEG2_0", - "RIOB_SE4BEG3_0", - "RIOB_SE4C0_0", - "RIOB_SE4C1_0", - "RIOB_SE4C2_0", - "RIOB_SE4C3_0", - "RIOB_SW2A0_0", - "RIOB_SW2A1_0", - "RIOB_SW2A2_0", - "RIOB_SW2A3_0", - "RIOB_SW4A0_0", - "RIOB_SW4A1_0", - "RIOB_SW4A2_0", - "RIOB_SW4A3_0", - "RIOB_SW4END0_0", - "RIOB_SW4END1_0", - "RIOB_SW4END2_0", - "RIOB_SW4END3_0", - "RIOB_WL1END0_0", - "RIOB_WL1END1_0", - "RIOB_WL1END2_0", - "RIOB_WL1END3_0", - "RIOB_WR1END0_0", - "RIOB_WR1END1_0", - "RIOB_WR1END2_0", - "RIOB_WR1END3_0", - "RIOB_WW2A0_0", - "RIOB_WW2A1_0", - "RIOB_WW2A2_0", - "RIOB_WW2A3_0", - "RIOB_WW2END0_0", - "RIOB_WW2END1_0", - "RIOB_WW2END2_0", - "RIOB_WW2END3_0", - "RIOB_WW4A0_0", - "RIOB_WW4A1_0", - "RIOB_WW4A2_0", - "RIOB_WW4A3_0", - "RIOB_WW4B0_0", - "RIOB_WW4B1_0", - "RIOB_WW4B2_0", - "RIOB_WW4B3_0", - "RIOB_WW4C0_0", - "RIOB_WW4C1_0", - "RIOB_WW4C2_0", - "RIOB_WW4C3_0", - "RIOB_WW4END0_0", - "RIOB_WW4END1_0", - "RIOB_WW4END2_0", - "RIOB_WW4END3_0" - ] + "wires": { + "IOB_DIFFI_IN0": null, + "IOB_DIFFO_IN0": null, + "IOB_DIFFO_OUT0": null, + "IOB_DIFF_TERM_INT_EN_STUB": null, + "IOB_IBUF0": null, + "IOB_IBUF_DISABLE0": null, + "IOB_KEEPER_INT_EN_1": null, + "IOB_O0": null, + "IOB_O_IN0": null, + "IOB_O_OUT0": null, + "IOB_PADOUT0": null, + "IOB_PD_INT_EN_1": null, + "IOB_PU_INT_EN_1": null, + "IOB_T0": null, + "IOB_T_IN0": null, + "IOB_T_OUT0": null, + "LIOB_IN_TERM0": null, + "RIOB_EE2A0_0": { + "cap": "150.000", + "res": "1024.400" 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"RIOB_ER1BEG3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_LH10_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH11_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH12_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH1_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH2_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH3_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH4_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH5_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH6_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH7_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH8_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH9_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_NE2A0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NE2A1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NE2A2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NE2A3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NE4BEG0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NE4BEG1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NE4BEG2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NE4BEG3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NE4C0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NE4C1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NE4C2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NE4C3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NW2A0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NW2A1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NW2A2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NW2A3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NW4A0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NW4A1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NW4A2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NW4A3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NW4END0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NW4END1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NW4END2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_NW4END3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SE2A0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SE2A1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SE2A2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SE2A3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SE4BEG0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SE4BEG1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SE4BEG2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SE4BEG3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SE4C0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SE4C1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SE4C2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SE4C3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SW2A0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SW2A1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SW2A2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SW2A3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SW4A0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SW4A1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SW4A2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SW4A3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SW4END0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SW4END1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SW4END2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_SW4END3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WL1END0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WL1END1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WL1END2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WL1END3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WR1END0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WR1END1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WR1END2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WR1END3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2A0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2A1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2A2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2A3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2END0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2END1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2END2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW2END3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4A0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4A1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4A2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4A3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4B0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4B1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4B2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4B3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4C0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4C1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4C2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4C3_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4END0_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4END1_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4END2_0": { + "cap": "150.000", + "res": "1024.400" + }, + "RIOB_WW4END3_0": { + "cap": "150.000", + "res": "1024.400" + } + } } diff --git a/zynq7/tile_type_RIOI3.json b/zynq7/tile_type_RIOI3.json index ceb8fe6..0b82c03 100644 --- a/zynq7/tile_type_RIOI3.json +++ b/zynq7/tile_type_RIOI3.json @@ -2,2949 +2,10160 @@ "pips": { "RIOI3.IOI_BYP3_0->IOI_IMUX_RC0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI3.IOI_BYP3_1->IOI_IMUX_RC3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI3.IOI_BYP4_0->IOI_IMUX_RC1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI3.IOI_BYP4_1->IOI_IMUX_RC2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI3.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_0" }, "RIOI3.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_1" }, "RIOI3.IOI_BYP7_0->RIOI3_IDELAY1_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY1_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_0" }, "RIOI3.IOI_BYP7_1->RIOI3_IDELAY0_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY0_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_1" }, "RIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "RIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "RIOI3.IOI_CLK1_0->IOI_IDELAY1_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "RIOI3.IOI_CLK1_1->IOI_IDELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_1" }, "RIOI3.IOI_CTRL0_0->IOI_OLOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_0" }, "RIOI3.IOI_CTRL0_1->IOI_OLOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_1" }, "RIOI3.IOI_CTRL1_0->IOI_ILOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_0" }, "RIOI3.IOI_CTRL1_1->IOI_ILOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_1" }, "RIOI3.IOI_FAN4_0->RIOI3_IDELAY1_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY1_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_0" }, "RIOI3.IOI_FAN4_1->RIOI3_IDELAY0_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY0_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_1" }, "RIOI3.IOI_FAN5_0->RIOI3_IDELAY1_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY1_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_0" }, "RIOI3.IOI_FAN5_1->RIOI3_IDELAY0_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY0_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_1" }, "RIOI3.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "RIOI3.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "RIOI3.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "RIOI3.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "RIOI3.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "RIOI3.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT0" }, "RIOI3.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT1" }, "RIOI3.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT2" }, "RIOI3.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT3" }, "RIOI3.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT4" }, "RIOI3.IOI_IDELAYCTRL_DNPULSEOUT->IOI_LOGIC_OUTS13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_DNPULSEOUT" }, "RIOI3.IOI_IDELAYCTRL_OUTN1->IOI_LOGIC_OUTS13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_OUTN1" }, "RIOI3.IOI_IDELAYCTRL_OUTN65->IOI_LOGIC_OUTS16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_OUTN65" }, "RIOI3.IOI_IDELAYCTRL_RDY->IOI_LOGIC_OUTS22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_RDY" }, "RIOI3.IOI_IDELAYCTRL_UPPULSEOUT->IOI_LOGIC_OUTS16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_UPPULSEOUT" }, "RIOI3.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC0_O" }, "RIOI3.IOI_ILOGIC0_O->RIOI_I2GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_I2GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_O" }, "RIOI3.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q1" }, "RIOI3.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q2" }, "RIOI3.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q3" }, "RIOI3.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q4" }, "RIOI3.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q5" }, "RIOI3.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q6" }, "RIOI3.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q7" }, "RIOI3.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q8" }, "RIOI3.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC1_O" }, "RIOI3.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q1" }, "RIOI3.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q2" }, "RIOI3.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q3" }, "RIOI3.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q4" }, "RIOI3.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q5" }, "RIOI3.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q6" }, "RIOI3.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q7" }, "RIOI3.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q8" }, "RIOI3.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_0" }, "RIOI3.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_1" }, "RIOI3.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_0" }, "RIOI3.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_1" }, "RIOI3.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_0" }, "RIOI3.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_1" }, "RIOI3.IOI_IMUX13_0->IOI_OLOGIC1_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_0" }, "RIOI3.IOI_IMUX13_1->IOI_OLOGIC0_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_1" }, "RIOI3.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_0" }, "RIOI3.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_1" }, "RIOI3.IOI_IMUX15_0->IOI_OLOGIC1_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_0" }, "RIOI3.IOI_IMUX15_1->IOI_OLOGIC0_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_1" }, "RIOI3.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_0" }, "RIOI3.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_1" }, "RIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "RIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "RIOI3.IOI_IMUX21_0->IOI_OLOGIC1_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_0" }, "RIOI3.IOI_IMUX21_1->IOI_OLOGIC0_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_1" }, "RIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "RIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "RIOI3.IOI_IMUX24_0->IOI_IDELAYCTRL_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAYCTRL_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX24_0" }, "RIOI3.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_0" }, "RIOI3.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_1" }, "RIOI3.IOI_IMUX26_0->IOI_IDELAY1_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_0" }, "RIOI3.IOI_IMUX26_1->IOI_IDELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_1" }, "RIOI3.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_0" }, "RIOI3.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_1" }, "RIOI3.IOI_IMUX30_0->IOI_IDELAY1_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_0" }, "RIOI3.IOI_IMUX30_1->IOI_IDELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_1" }, "RIOI3.IOI_IMUX31_0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI3.IOI_IMUX31_0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI3.IOI_IMUX31_1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "RIOI3.IOI_IMUX31_1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "RIOI3.IOI_IMUX32_0->IOI_IDELAY1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_0" }, "RIOI3.IOI_IMUX32_1->IOI_IDELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_1" }, "RIOI3.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_0" }, "RIOI3.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_1" }, "RIOI3.IOI_IMUX34_0->IOI_OLOGIC1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_0" }, "RIOI3.IOI_IMUX34_1->IOI_OLOGIC0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_1" }, "RIOI3.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_0" }, "RIOI3.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_1" }, "RIOI3.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_0" }, "RIOI3.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_1" }, "RIOI3.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_0" }, "RIOI3.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_1" }, "RIOI3.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_0" }, "RIOI3.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_1" }, "RIOI3.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_0" }, "RIOI3.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_1" }, "RIOI3.IOI_IMUX40_0->IOI_OLOGIC1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_0" }, "RIOI3.IOI_IMUX40_1->IOI_OLOGIC0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_1" }, "RIOI3.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_0" }, "RIOI3.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_1" }, "RIOI3.IOI_IMUX42_0->IOI_OLOGIC1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_0" }, "RIOI3.IOI_IMUX42_1->IOI_OLOGIC0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_1" }, "RIOI3.IOI_IMUX43_0->IOI_OLOGIC1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_0" }, "RIOI3.IOI_IMUX43_1->IOI_OLOGIC0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_1" }, "RIOI3.IOI_IMUX44_0->IOI_OLOGIC1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_0" }, "RIOI3.IOI_IMUX44_1->IOI_OLOGIC0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_1" }, "RIOI3.IOI_IMUX45_0->IOI_OLOGIC1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_0" }, "RIOI3.IOI_IMUX45_1->IOI_OLOGIC0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_1" }, "RIOI3.IOI_IMUX46_0->IOI_OLOGIC1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_0" }, "RIOI3.IOI_IMUX46_1->IOI_OLOGIC0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_1" }, "RIOI3.IOI_IMUX47_0->IOI_OLOGIC1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_0" }, "RIOI3.IOI_IMUX47_1->IOI_OLOGIC0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_1" }, "RIOI3.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_0" }, "RIOI3.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_1" }, "RIOI3.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_0" }, "RIOI3.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_1" }, "RIOI3.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_0" }, "RIOI3.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_1" }, "RIOI3.IOI_IMUX7_0->IOI_OLOGIC1_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_0" }, "RIOI3.IOI_IMUX7_1->IOI_OLOGIC0_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_1" }, "RIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI3.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI3.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_0" }, "RIOI3.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_1" }, "RIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3.IOI_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3.IOI_IOCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3.IOI_IOCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3.IOI_IOCLK0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3.IOI_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3.IOI_IOCLK1->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3.IOI_IOCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3.IOI_IOCLK1->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3.IOI_IOCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3.IOI_IOCLK2->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", 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"delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", 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"in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + 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"in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + 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"0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, 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"0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI3.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI3.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "RIOI3.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "RIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI3.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI3.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI3.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC0_IOCLKGLITCH" }, "RIOI3.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI3.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI3.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "RIOI3.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "RIOI3.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC1_IOCLKGLITCH" }, "RIOI3.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "RIOI3.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "RIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI3.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV" }, 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"dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK_0" }, "RIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90" }, "RIOI3.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0" }, "RIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, "RIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, "RIOI3.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0" }, "RIOI3.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0" }, "RIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK_0" }, "RIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK_0" }, "RIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK_0" }, "RIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK_0" }, "RIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "RIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "RIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "RIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "RIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "RIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ 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"in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "RIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "RIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "RIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": 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"delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "RIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "RIOI3.IOI_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "RIOI3.IOI_RCLK_FORIO3->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "RIOI3.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_TBYTEIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_TBYTEIN" }, "RIOI3.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_TBYTEIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_TBYTEIN" }, "RIOI3.RIOI_I0->RIOI_IDELAY0_IDATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IDATAIN", "is_directional": "1", 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"is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_I1" }, "RIOI3.RIOI_IBUF0->RIOI_I0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_I0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_IBUF0" }, "RIOI3.RIOI_IBUF1->RIOI_I1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_I1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_IBUF1" }, "RIOI3.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_DDLY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_IDELAY0_DATAOUT" }, "RIOI3.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.243", + "0.305", + "0.755", + "0.815" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_IDELAY0_DATAOUT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.243", + "0.305", + "0.755", + "0.815" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_IDELAY0_IDATAIN" }, "RIOI3.RIOI_IDELAY1_DATAOUT->RIOI_ILOGIC1_DDLY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_DDLY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_IDELAY1_DATAOUT" }, "RIOI3.RIOI_IDELAY1_IDATAIN->>RIOI_IDELAY1_DATAOUT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.243", + "0.305", + "0.755", + "0.815" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_IDELAY1_DATAOUT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.243", + "0.305", + "0.755", + "0.815" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_IDELAY1_IDATAIN" }, "RIOI3.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.054", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.054", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC0_D" }, "RIOI3.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.055", + "0.120", + "0.138" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.055", + "0.120", + "0.138" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC0_DDLY" }, "RIOI3.RIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.054", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.054", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC1_D" }, "RIOI3.RIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.055", + "0.120", + "0.138" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.055", + "0.120", + "0.138" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC1_DDLY" }, "RIOI3.RIOI_ISOUT10->RIOI_ISIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ISIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_ISOUT10" }, "RIOI3.RIOI_ISOUT20->RIOI_ISIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ISIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_ISOUT20" }, "RIOI3.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_OFB" }, "RIOI3.RIOI_OLOGIC0_OQ->>RIOI_O0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_O0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_OQ" }, "RIOI3.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_OQ" }, "RIOI3.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB" }, "RIOI3.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI3.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI3.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" }, "RIOI3.RIOI_OLOGIC0_TQ->>RIOI_T0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_T0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" }, "RIOI3.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_OFB" }, "RIOI3.RIOI_OLOGIC1_OQ->>RIOI_O1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_O1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_OQ" }, "RIOI3.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_OQ" }, "RIOI3.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB" }, "RIOI3.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB_LOCAL" }, "RIOI3.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB_LOCAL" }, "RIOI3.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_TQ" }, "RIOI3.RIOI_OLOGIC1_TQ->>RIOI_T1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_T1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_TQ" }, "RIOI3.RIOI_OSOUT11->RIOI_OSIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OSIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OSOUT11" }, "RIOI3.RIOI_OSOUT21->RIOI_OSIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OSIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OSOUT21" } }, @@ -2953,39 +10164,309 @@ "name": "X0Y0", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC1_CLK", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "D1": "IOI_OLOGIC1_D1", - "D2": "IOI_OLOGIC1_D2", - "D3": "IOI_OLOGIC1_D3", - "D4": "IOI_OLOGIC1_D4", - "D5": "IOI_OLOGIC1_D5", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D8": "IOI_OLOGIC1_D8", - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "OCE": "IOI_OLOGIC1_OCE", - "OFB": "RIOI_OLOGIC1_OFB", - "OQ": "RIOI_OLOGIC1_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_OQ" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_OSOUT11", - "SHIFTOUT2": "RIOI_OSOUT21", - "SR": "IOI_OLOGIC1_SR", - "T1": "IOI_OLOGIC1_T1", - "T2": "IOI_OLOGIC1_T2", - "T3": "IOI_OLOGIC1_T3", - "T4": "IOI_OLOGIC1_T4", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "TCE": "IOI_OLOGIC1_TCE", - "TFB": "RIOI_OLOGIC1_TFB", - "TQ": "RIOI_OLOGIC1_TQ" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -2995,37 +10476,307 @@ "name": "X0Y0", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "CE1": "IOI_ILOGIC1_CE1", - "CE2": "IOI_ILOGIC1_CE2", - "CLK": "IOI_ILOGIC1_CLK", - "CLKB": "IOI_ILOGIC1_CLKB", - "CLKDIV": "IOI_ILOGIC1_CLKDIV", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "D": "RIOI_ILOGIC1_D", - "DDLY": "RIOI_ILOGIC1_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "O": "IOI_ILOGIC1_O", - "OCLK": "IOI_ILOGIC1_OCLK", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "OFB": "RIOI_ILOGIC1_OFB", - "Q1": "IOI_ILOGIC1_Q1", - "Q2": "IOI_ILOGIC1_Q2", - "Q3": "IOI_ILOGIC1_Q3", - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q6": "IOI_ILOGIC1_Q6", - "Q7": "IOI_ILOGIC1_Q7", - "Q8": "IOI_ILOGIC1_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC1_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q8" + }, "REV": null, - "SHIFTIN1": "RIOI_ISIN11", - "SHIFTIN2": "RIOI_ISIN21", - "SHIFTOUT1": "RIOI_ISOUT11", - "SHIFTOUT2": "RIOI_ISOUT21", - "SR": "IOI_ILOGIC1_SR", - "TFB": "RIOI_ILOGIC1_TFB" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ISIN11" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ISIN21" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -3035,39 +10786,327 @@ "name": "X0Y1", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC0_CLK", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "D1": "IOI_OLOGIC0_D1", - "D2": "IOI_OLOGIC0_D2", - "D3": "IOI_OLOGIC0_D3", - "D4": "IOI_OLOGIC0_D4", - "D5": "IOI_OLOGIC0_D5", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D8": "IOI_OLOGIC0_D8", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "OCE": "IOI_OLOGIC0_OCE", - "OFB": "RIOI_OLOGIC0_OFB", - "OQ": "RIOI_OLOGIC0_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OQ" + }, "REV": null, - "SHIFTIN1": "RIOI_OSIN10", - "SHIFTIN2": "RIOI_OSIN20", - "SHIFTOUT1": "RIOI_OSOUT10", - "SHIFTOUT2": "RIOI_OSOUT20", - "SR": "IOI_OLOGIC0_SR", - "T1": "IOI_OLOGIC0_T1", - "T2": "IOI_OLOGIC0_T2", - "T3": "IOI_OLOGIC0_T3", - "T4": "IOI_OLOGIC0_T4", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "TCE": "IOI_OLOGIC0_TCE", - "TFB": "RIOI_OLOGIC0_TFB", - "TQ": "RIOI_OLOGIC0_TQ" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OSIN10" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OSIN20" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -3077,37 +11116,289 @@ "name": "X0Y1", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "CE1": "IOI_ILOGIC0_CE1", - "CE2": "IOI_ILOGIC0_CE2", - "CLK": "IOI_ILOGIC0_CLK", - "CLKB": "IOI_ILOGIC0_CLKB", - "CLKDIV": "IOI_ILOGIC0_CLKDIV", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "D": "RIOI_ILOGIC0_D", - "DDLY": "RIOI_ILOGIC0_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "O": "IOI_ILOGIC0_O", - "OCLK": "IOI_ILOGIC0_OCLK", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "OFB": "RIOI_ILOGIC0_OFB", - "Q1": "IOI_ILOGIC0_Q1", - "Q2": "IOI_ILOGIC0_Q2", - "Q3": "IOI_ILOGIC0_Q3", - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q6": "IOI_ILOGIC0_Q6", - "Q7": "IOI_ILOGIC0_Q7", - "Q8": "IOI_ILOGIC0_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC0_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q8" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_ISOUT10", - "SHIFTOUT2": "RIOI_ISOUT20", - "SR": "IOI_ILOGIC0_SR", - "TFB": "RIOI_ILOGIC0_TFB" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -3117,29 +11408,236 @@ "name": "X0Y0", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY1_C", - "CE": "IOI_IDELAY1_CE", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY1_DATAIN", - "DATAOUT": "RIOI_IDELAY1_DATAOUT", - "IDATAIN": "RIOI_IDELAY1_IDATAIN", - "IFDLY0": "RIOI3_IDELAY1_IFDLY0", - "IFDLY1": "RIOI3_IDELAY1_IFDLY1", - "IFDLY2": "RIOI3_IDELAY1_IFDLY2", - "INC": "IOI_IDELAY1_INC", - "LD": "IOI_IDELAY1_LD", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "REGRST": "IOI_IDELAY1_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY1_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY1_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY1_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY1_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -3149,29 +11647,236 @@ "name": "X0Y1", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY0_C", - "CE": "IOI_IDELAY0_CE", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY0_DATAIN", - "DATAOUT": "RIOI_IDELAY0_DATAOUT", - "IDATAIN": "RIOI_IDELAY0_IDATAIN", - "IFDLY0": "RIOI3_IDELAY0_IFDLY0", - "IFDLY1": "RIOI3_IDELAY0_IFDLY1", - "IFDLY2": "RIOI3_IDELAY0_IFDLY2", - "INC": "IOI_IDELAY0_INC", - "LD": "IOI_IDELAY0_LD", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "REGRST": "IOI_IDELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY0_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY0_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY0_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY0_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -3179,750 +11884,750 @@ } ], "tile_type": "RIOI3", - "wires": [ - "IOI_BLOCK_OUTS0_0", - "IOI_BLOCK_OUTS0_1", - "IOI_BLOCK_OUTS1_0", - "IOI_BLOCK_OUTS1_1", - "IOI_BLOCK_OUTS2_0", - "IOI_BLOCK_OUTS2_1", - "IOI_BLOCK_OUTS3_0", - "IOI_BLOCK_OUTS3_1", - "IOI_BYP0_0", - "IOI_BYP0_1", - "IOI_BYP1_0", - "IOI_BYP1_1", - "IOI_BYP2_0", - "IOI_BYP2_1", - "IOI_BYP3_0", - "IOI_BYP3_1", - "IOI_BYP4_0", - "IOI_BYP4_1", - "IOI_BYP5_0", - "IOI_BYP5_1", - "IOI_BYP6_0", - "IOI_BYP6_1", - "IOI_BYP7_0", - "IOI_BYP7_1", - "IOI_CLK0_0", - "IOI_CLK0_1", - "IOI_CLK1_0", - "IOI_CLK1_1", - "IOI_CTRL0_0", - "IOI_CTRL0_1", - "IOI_CTRL1_0", - "IOI_CTRL1_1", - "IOI_DCI_DCIDONE", - "IOI_DCI_TSTCLK", - "IOI_DCI_TSTHLN", - "IOI_DCI_TSTHLP", - "IOI_DCI_TSTRST", - "IOI_DCI_TSTRST0", - "IOI_EE2A0_0", - "IOI_EE2A0_1", - "IOI_EE2A1_0", - "IOI_EE2A1_1", - "IOI_EE2A2_0", - "IOI_EE2A2_1", - "IOI_EE2A3_0", - "IOI_EE2A3_1", - "IOI_EE2BEG0_0", - "IOI_EE2BEG0_1", - "IOI_EE2BEG1_0", - "IOI_EE2BEG1_1", - "IOI_EE2BEG2_0", - "IOI_EE2BEG2_1", - "IOI_EE2BEG3_0", - "IOI_EE2BEG3_1", - "IOI_EE4A0_0", - "IOI_EE4A0_1", - "IOI_EE4A1_0", - "IOI_EE4A1_1", - "IOI_EE4A2_0", - "IOI_EE4A2_1", - "IOI_EE4A3_0", - "IOI_EE4A3_1", - "IOI_EE4B0_0", - "IOI_EE4B0_1", - "IOI_EE4B1_0", - "IOI_EE4B1_1", - "IOI_EE4B2_0", - "IOI_EE4B2_1", - "IOI_EE4B3_0", - "IOI_EE4B3_1", - "IOI_EE4BEG0_0", - "IOI_EE4BEG0_1", - "IOI_EE4BEG1_0", - "IOI_EE4BEG1_1", - "IOI_EE4BEG2_0", - "IOI_EE4BEG2_1", - "IOI_EE4BEG3_0", - "IOI_EE4BEG3_1", - "IOI_EE4C0_0", - "IOI_EE4C0_1", - "IOI_EE4C1_0", - "IOI_EE4C1_1", - "IOI_EE4C2_0", - "IOI_EE4C2_1", - "IOI_EE4C3_0", - "IOI_EE4C3_1", - "IOI_EL1BEG0_0", - "IOI_EL1BEG0_1", - "IOI_EL1BEG1_0", - "IOI_EL1BEG1_1", - "IOI_EL1BEG2_0", - "IOI_EL1BEG2_1", - "IOI_EL1BEG3_0", - "IOI_EL1BEG3_1", - "IOI_ER1BEG0_0", - "IOI_ER1BEG0_1", - "IOI_ER1BEG1_0", - "IOI_ER1BEG1_1", - "IOI_ER1BEG2_0", - "IOI_ER1BEG2_1", - "IOI_ER1BEG3_0", - "IOI_ER1BEG3_1", - "IOI_FAN0_0", - "IOI_FAN0_1", - "IOI_FAN1_0", - "IOI_FAN1_1", - "IOI_FAN2_0", - "IOI_FAN2_1", - "IOI_FAN3_0", - "IOI_FAN3_1", - "IOI_FAN4_0", - "IOI_FAN4_1", - "IOI_FAN5_0", - "IOI_FAN5_1", - "IOI_FAN6_0", - "IOI_FAN6_1", - "IOI_FAN7_0", - "IOI_FAN7_1", - "IOI_IDELAY0_C", - "IOI_IDELAY0_CE", - "IOI_IDELAY0_CINVCTRL", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_IDELAY0_DATAIN", - "IOI_IDELAY0_INC", - "IOI_IDELAY0_LD", - "IOI_IDELAY0_LDPIPEEN", - "IOI_IDELAY0_REGRST", - "IOI_IDELAY1_C", - "IOI_IDELAY1_CE", - "IOI_IDELAY1_CINVCTRL", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT0", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_IDELAY1_DATAIN", - "IOI_IDELAY1_INC", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_LDPIPEEN", - "IOI_IDELAY1_REGRST", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IDELAYCTRL_OUTN1", - "IOI_IDELAYCTRL_OUTN65", - "IOI_IDELAYCTRL_RDY", - "IOI_IDELAYCTRL_RST", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_ILOGIC0_BITSLIP", - "IOI_ILOGIC0_CE1", - "IOI_ILOGIC0_CE2", - "IOI_ILOGIC0_CLK", - "IOI_ILOGIC0_CLKB", - "IOI_ILOGIC0_CLKDIV", - "IOI_ILOGIC0_CLKDIVP", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_ILOGIC0_O", - "IOI_ILOGIC0_OCLK", - "IOI_ILOGIC0_OCLKB", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_Q2", - "IOI_ILOGIC0_Q3", - "IOI_ILOGIC0_Q4", - "IOI_ILOGIC0_Q5", - "IOI_ILOGIC0_Q6", - "IOI_ILOGIC0_Q7", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC0_REV", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC1_BITSLIP", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC1_CE2", - "IOI_ILOGIC1_CLK", - "IOI_ILOGIC1_CLKB", - "IOI_ILOGIC1_CLKDIV", - "IOI_ILOGIC1_CLKDIVP", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_ILOGIC1_O", - "IOI_ILOGIC1_OCLK", - "IOI_ILOGIC1_OCLKB", - "IOI_ILOGIC1_Q1", - "IOI_ILOGIC1_Q2", - "IOI_ILOGIC1_Q3", - "IOI_ILOGIC1_Q4", - "IOI_ILOGIC1_Q5", - "IOI_ILOGIC1_Q6", - "IOI_ILOGIC1_Q7", - "IOI_ILOGIC1_Q8", - "IOI_ILOGIC1_REV", - "IOI_ILOGIC1_SR", - "IOI_IMUX0_0", - "IOI_IMUX0_1", - "IOI_IMUX10_0", - "IOI_IMUX10_1", - "IOI_IMUX11_0", - "IOI_IMUX11_1", - "IOI_IMUX12_0", - "IOI_IMUX12_1", - "IOI_IMUX13_0", - "IOI_IMUX13_1", - "IOI_IMUX14_0", - "IOI_IMUX14_1", - "IOI_IMUX15_0", - "IOI_IMUX15_1", - "IOI_IMUX16_0", - "IOI_IMUX16_1", - "IOI_IMUX17_0", - "IOI_IMUX17_1", - "IOI_IMUX18_0", - "IOI_IMUX18_1", - "IOI_IMUX19_0", - "IOI_IMUX19_1", - "IOI_IMUX1_0", - "IOI_IMUX1_1", - "IOI_IMUX20_0", - "IOI_IMUX20_1", - "IOI_IMUX21_0", - "IOI_IMUX21_1", - "IOI_IMUX22_0", - "IOI_IMUX22_1", - "IOI_IMUX23_0", - "IOI_IMUX23_1", - "IOI_IMUX24_0", - "IOI_IMUX24_1", - "IOI_IMUX25_0", - "IOI_IMUX25_1", - "IOI_IMUX26_0", - "IOI_IMUX26_1", - "IOI_IMUX27_0", - "IOI_IMUX27_1", - "IOI_IMUX28_0", - "IOI_IMUX28_1", - "IOI_IMUX29_0", - "IOI_IMUX29_1", - "IOI_IMUX2_0", - "IOI_IMUX2_1", - "IOI_IMUX30_0", - "IOI_IMUX30_1", - "IOI_IMUX31_0", - "IOI_IMUX31_1", - "IOI_IMUX32_0", - "IOI_IMUX32_1", - "IOI_IMUX33_0", - "IOI_IMUX33_1", - "IOI_IMUX34_0", - "IOI_IMUX34_1", - "IOI_IMUX35_0", - "IOI_IMUX35_1", - "IOI_IMUX36_0", - "IOI_IMUX36_1", - "IOI_IMUX37_0", - "IOI_IMUX37_1", - "IOI_IMUX38_0", - "IOI_IMUX38_1", - "IOI_IMUX39_0", - "IOI_IMUX39_1", - "IOI_IMUX3_0", - "IOI_IMUX3_1", - "IOI_IMUX40_0", - "IOI_IMUX40_1", - "IOI_IMUX41_0", - "IOI_IMUX41_1", - "IOI_IMUX42_0", - "IOI_IMUX42_1", - "IOI_IMUX43_0", - "IOI_IMUX43_1", - "IOI_IMUX44_0", - "IOI_IMUX44_1", - "IOI_IMUX45_0", - "IOI_IMUX45_1", - "IOI_IMUX46_0", - "IOI_IMUX46_1", - "IOI_IMUX47_0", - "IOI_IMUX47_1", - "IOI_IMUX4_0", - "IOI_IMUX4_1", - "IOI_IMUX5_0", - "IOI_IMUX5_1", - "IOI_IMUX6_0", - "IOI_IMUX6_1", - "IOI_IMUX7_0", - "IOI_IMUX7_1", - "IOI_IMUX8_0", - "IOI_IMUX8_1", - "IOI_IMUX9_0", - "IOI_IMUX9_1", - "IOI_IMUX_RC0", - "IOI_IMUX_RC1", - "IOI_IMUX_RC2", - "IOI_IMUX_RC3", - "IOI_INT_DCI_EN", - "IOI_IOCLK0", - "IOI_IOCLK1", - "IOI_IOCLK2", - "IOI_IOCLK3", - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK5", - "IOI_LH10_0", - "IOI_LH10_1", - "IOI_LH11_0", - "IOI_LH11_1", - "IOI_LH12_0", - "IOI_LH12_1", - "IOI_LH1_0", - "IOI_LH1_1", - "IOI_LH2_0", - "IOI_LH2_1", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_LH4_0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_LH5_1", - "IOI_LH6_0", - "IOI_LH6_1", - "IOI_LH7_0", - "IOI_LH7_1", - "IOI_LH8_0", - "IOI_LH8_1", - "IOI_LH9_0", - "IOI_LH9_1", - "IOI_LOGIC_OUTS0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_LOGIC_OUTS10_0", - "IOI_LOGIC_OUTS10_1", - "IOI_LOGIC_OUTS11_0", - "IOI_LOGIC_OUTS11_1", - "IOI_LOGIC_OUTS12_0", - "IOI_LOGIC_OUTS12_1", - "IOI_LOGIC_OUTS13_0", - "IOI_LOGIC_OUTS13_1", - "IOI_LOGIC_OUTS14_0", - "IOI_LOGIC_OUTS14_1", - "IOI_LOGIC_OUTS15_0", - "IOI_LOGIC_OUTS15_1", - "IOI_LOGIC_OUTS16_0", - "IOI_LOGIC_OUTS16_1", - "IOI_LOGIC_OUTS17_0", - "IOI_LOGIC_OUTS17_1", - "IOI_LOGIC_OUTS18_0", - "IOI_LOGIC_OUTS18_1", - "IOI_LOGIC_OUTS19_0", - "IOI_LOGIC_OUTS19_1", - "IOI_LOGIC_OUTS1_0", - "IOI_LOGIC_OUTS1_1", - "IOI_LOGIC_OUTS20_0", - "IOI_LOGIC_OUTS20_1", - "IOI_LOGIC_OUTS21_0", - "IOI_LOGIC_OUTS21_1", - "IOI_LOGIC_OUTS22_0", - "IOI_LOGIC_OUTS22_1", - "IOI_LOGIC_OUTS23_0", - "IOI_LOGIC_OUTS23_1", - "IOI_LOGIC_OUTS2_0", - "IOI_LOGIC_OUTS2_1", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS3_1", - "IOI_LOGIC_OUTS4_0", - "IOI_LOGIC_OUTS4_1", - "IOI_LOGIC_OUTS5_0", - "IOI_LOGIC_OUTS5_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LOGIC_OUTS6_1", - "IOI_LOGIC_OUTS7_0", - "IOI_LOGIC_OUTS7_1", - "IOI_LOGIC_OUTS8_0", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS9_0", - "IOI_LOGIC_OUTS9_1", - "IOI_MONITOR_N", - "IOI_MONITOR_P", - "IOI_NE2A0_0", - "IOI_NE2A0_1", - "IOI_NE2A1_0", - "IOI_NE2A1_1", - "IOI_NE2A2_0", - "IOI_NE2A2_1", - "IOI_NE2A3_0", - "IOI_NE2A3_1", - "IOI_NE4BEG0_0", - "IOI_NE4BEG0_1", - "IOI_NE4BEG1_0", - "IOI_NE4BEG1_1", - "IOI_NE4BEG2_0", - "IOI_NE4BEG2_1", - "IOI_NE4BEG3_0", - "IOI_NE4BEG3_1", - "IOI_NE4C0_0", - "IOI_NE4C0_1", - "IOI_NE4C1_0", - "IOI_NE4C1_1", - "IOI_NE4C2_0", - "IOI_NE4C2_1", - "IOI_NE4C3_0", - "IOI_NE4C3_1", - "IOI_NW2A0_0", - "IOI_NW2A0_1", - "IOI_NW2A1_0", - "IOI_NW2A1_1", - "IOI_NW2A2_0", - "IOI_NW2A2_1", - "IOI_NW2A3_0", - "IOI_NW2A3_1", - "IOI_NW4A0_0", - "IOI_NW4A0_1", - "IOI_NW4A1_0", - "IOI_NW4A1_1", - "IOI_NW4A2_0", - "IOI_NW4A2_1", - "IOI_NW4A3_0", - "IOI_NW4A3_1", - "IOI_NW4END0_0", - "IOI_NW4END0_1", - "IOI_NW4END1_0", - "IOI_NW4END1_1", - "IOI_NW4END2_0", - "IOI_NW4END2_1", - "IOI_NW4END3_0", - "IOI_NW4END3_1", - "IOI_OCLKM_0", - "IOI_OCLKM_1", - "IOI_OCLK_0", - "IOI_OCLK_1", - "IOI_ODELAY0_C", - "IOI_ODELAY0_CE", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY0_CLKIN", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ODELAY0_INC", - "IOI_ODELAY0_LD", - "IOI_ODELAY0_LDPIPEEN", - "IOI_ODELAY0_REGRST", - "IOI_ODELAY1_C", - "IOI_ODELAY1_CE", - "IOI_ODELAY1_CINVCTRL", - "IOI_ODELAY1_CLKIN", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_ODELAY1_CNTVALUEIN1", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_ODELAY1_CNTVALUEOUT0", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_ODELAY1_CNTVALUEOUT2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_ODELAY1_INC", - "IOI_ODELAY1_LD", - "IOI_ODELAY1_LDPIPEEN", - "IOI_ODELAY1_REGRST", - "IOI_OLOGIC0_CLK", - "IOI_OLOGIC0_CLKB", - "IOI_OLOGIC0_CLKDIV", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_OLOGIC0_D1", - "IOI_OLOGIC0_D2", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_D4", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_D6", - "IOI_OLOGIC0_D7", - "IOI_OLOGIC0_D8", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_OCE", - "IOI_OLOGIC0_REV", - "IOI_OLOGIC0_SR", - "IOI_OLOGIC0_T1", - "IOI_OLOGIC0_T2", - "IOI_OLOGIC0_T3", - "IOI_OLOGIC0_T4", - "IOI_OLOGIC0_TBYTEIN", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_CLK", - "IOI_OLOGIC1_CLKB", - "IOI_OLOGIC1_CLKDIV", - "IOI_OLOGIC1_CLKDIVB", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_OLOGIC1_D1", - "IOI_OLOGIC1_D2", - "IOI_OLOGIC1_D3", - "IOI_OLOGIC1_D4", - "IOI_OLOGIC1_D5", - "IOI_OLOGIC1_D6", - "IOI_OLOGIC1_D7", - "IOI_OLOGIC1_D8", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_OLOGIC1_OCE", - "IOI_OLOGIC1_REV", - "IOI_OLOGIC1_SR", - "IOI_OLOGIC1_T1", - "IOI_OLOGIC1_T2", - "IOI_OLOGIC1_T3", - "IOI_OLOGIC1_T4", - "IOI_OLOGIC1_TBYTEIN", - "IOI_OLOGIC1_TBYTEOUT", - "IOI_OLOGIC1_TCE", - "IOI_PHASER_TO_IO_ICLK", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_PHASER_TO_IO_OCLK", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_PHASER_TO_IO_OCLK_0", - "IOI_RCLK_DIV_CE0", - "IOI_RCLK_DIV_CE1", - "IOI_RCLK_DIV_CE2", - "IOI_RCLK_DIV_CE2_1", - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1", - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1", - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_RCLK_DIV_CLR2", - "IOI_RCLK_DIV_CLR3", - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO3", - "IOI_SE2A0_0", - "IOI_SE2A0_1", - "IOI_SE2A1_0", - "IOI_SE2A1_1", - "IOI_SE2A2_0", - "IOI_SE2A2_1", - "IOI_SE2A3_0", - "IOI_SE2A3_1", - "IOI_SE4BEG0_0", - "IOI_SE4BEG0_1", - "IOI_SE4BEG1_0", - "IOI_SE4BEG1_1", - "IOI_SE4BEG2_0", - "IOI_SE4BEG2_1", - "IOI_SE4BEG3_0", - "IOI_SE4BEG3_1", - "IOI_SE4C0_0", - "IOI_SE4C0_1", - "IOI_SE4C1_0", - "IOI_SE4C1_1", - "IOI_SE4C2_0", - "IOI_SE4C2_1", - "IOI_SE4C3_0", - "IOI_SE4C3_1", - "IOI_SW2A0_0", - "IOI_SW2A0_1", - "IOI_SW2A1_0", - "IOI_SW2A1_1", - "IOI_SW2A2_0", - "IOI_SW2A2_1", - "IOI_SW2A3_0", - "IOI_SW2A3_1", - "IOI_SW4A0_0", - "IOI_SW4A0_1", - "IOI_SW4A1_0", - "IOI_SW4A1_1", - "IOI_SW4A2_0", - "IOI_SW4A2_1", - "IOI_SW4A3_0", - "IOI_SW4A3_1", - "IOI_SW4END0_0", - "IOI_SW4END0_1", - "IOI_SW4END1_0", - "IOI_SW4END1_1", - "IOI_SW4END2_0", - "IOI_SW4END2_1", - "IOI_SW4END3_0", - "IOI_SW4END3_1", - "IOI_TBYTEIN", - "IOI_WL1END0_0", - "IOI_WL1END0_1", - "IOI_WL1END1_0", - "IOI_WL1END1_1", - "IOI_WL1END2_0", - "IOI_WL1END2_1", - "IOI_WL1END3_0", - "IOI_WL1END3_1", - "IOI_WR1END0_0", - "IOI_WR1END0_1", - "IOI_WR1END1_0", - "IOI_WR1END1_1", - "IOI_WR1END2_0", - "IOI_WR1END2_1", - "IOI_WR1END3_0", - "IOI_WR1END3_1", - "IOI_WW2A0_0", - "IOI_WW2A0_1", - "IOI_WW2A1_0", - "IOI_WW2A1_1", - "IOI_WW2A2_0", - "IOI_WW2A2_1", - "IOI_WW2A3_0", - "IOI_WW2A3_1", - "IOI_WW2END0_0", - "IOI_WW2END0_1", - "IOI_WW2END1_0", - "IOI_WW2END1_1", - "IOI_WW2END2_0", - "IOI_WW2END2_1", - "IOI_WW2END3_0", - "IOI_WW2END3_1", - "IOI_WW4A0_0", - "IOI_WW4A0_1", - "IOI_WW4A1_0", - "IOI_WW4A1_1", - "IOI_WW4A2_0", - "IOI_WW4A2_1", - "IOI_WW4A3_0", - "IOI_WW4A3_1", - "IOI_WW4B0_0", - "IOI_WW4B0_1", - "IOI_WW4B1_0", - "IOI_WW4B1_1", - "IOI_WW4B2_0", - "IOI_WW4B2_1", - "IOI_WW4B3_0", - "IOI_WW4B3_1", - "IOI_WW4C0_0", - "IOI_WW4C0_1", - "IOI_WW4C1_0", - "IOI_WW4C1_1", - "IOI_WW4C2_0", - "IOI_WW4C2_1", - "IOI_WW4C3_0", - "IOI_WW4C3_1", - "IOI_WW4END0_0", - "IOI_WW4END0_1", - "IOI_WW4END1_0", - "IOI_WW4END1_1", - "IOI_WW4END2_0", - "IOI_WW4END2_1", - "IOI_WW4END3_0", - "IOI_WW4END3_1", - "RIOI3_IDELAY0_IFDLY0", - "RIOI3_IDELAY0_IFDLY1", - "RIOI3_IDELAY0_IFDLY2", - "RIOI3_IDELAY1_IFDLY0", - "RIOI3_IDELAY1_IFDLY1", - "RIOI3_IDELAY1_IFDLY2", - "RIOI_DCI_T_TERM0", - "RIOI_DCI_T_TERM1", - "RIOI_DIFF_TERM_INT_EN", - "RIOI_I0", - "RIOI_I1", - "RIOI_I2GCLK_BOT1", - "RIOI_I2GCLK_TOP0", - "RIOI_I2GCLK_TOP1", - "RIOI_IBUF0", - "RIOI_IBUF1", - "RIOI_IBUF_DISABLE0", - "RIOI_IBUF_DISABLE1", - "RIOI_IDELAY0_DATAOUT", - "RIOI_IDELAY0_IDATAIN", - "RIOI_IDELAY1_DATAOUT", - "RIOI_IDELAY1_IDATAIN", - "RIOI_ILOGIC0_D", - "RIOI_ILOGIC0_DDLY", - "RIOI_ILOGIC0_OFB", - "RIOI_ILOGIC0_TFB", - "RIOI_ILOGIC1_D", - "RIOI_ILOGIC1_DDLY", - "RIOI_ILOGIC1_OFB", - "RIOI_ILOGIC1_TFB", - "RIOI_ISIN10", - "RIOI_ISIN11", - "RIOI_ISIN20", - "RIOI_ISIN21", - "RIOI_ISOUT10", - "RIOI_ISOUT11", - "RIOI_ISOUT20", - "RIOI_ISOUT21", - "RIOI_KEEPER_INT_EN_0", - "RIOI_KEEPER_INT_EN_1", - "RIOI_O0", - "RIOI_O1", - "RIOI_ODELAY0_DATAOUT", - "RIOI_ODELAY0_ODATAIN", - "RIOI_ODELAY0_OFDLY0", - "RIOI_ODELAY0_OFDLY1", - "RIOI_ODELAY0_OFDLY2", - "RIOI_ODELAY1_DATAOUT", - "RIOI_ODELAY1_ODATAIN", - "RIOI_ODELAY1_OFDLY0", - "RIOI_ODELAY1_OFDLY1", - "RIOI_ODELAY1_OFDLY2", - "RIOI_OLOGIC0_CLKDIVF", - "RIOI_OLOGIC0_OFB", - "RIOI_OLOGIC0_OQ", - "RIOI_OLOGIC0_TFB", - "RIOI_OLOGIC0_TFB_LOCAL", - "RIOI_OLOGIC0_TQ", - "RIOI_OLOGIC1_CLKDIVF", - "RIOI_OLOGIC1_OFB", - "RIOI_OLOGIC1_OQ", - "RIOI_OLOGIC1_TFB", - "RIOI_OLOGIC1_TFB_LOCAL", - "RIOI_OLOGIC1_TQ", - "RIOI_OSIN10", - "RIOI_OSIN11", - "RIOI_OSIN20", - "RIOI_OSIN21", - "RIOI_OSOUT10", - "RIOI_OSOUT11", - "RIOI_OSOUT20", - "RIOI_OSOUT21", - "RIOI_PD_INT_EN_0", - "RIOI_PD_INT_EN_1", - "RIOI_PU_INT_EN_0", - "RIOI_PU_INT_EN_1", - "RIOI_T0", - "RIOI_T1" - ] + "wires": { + "IOI_BLOCK_OUTS0_0": null, + "IOI_BLOCK_OUTS0_1": null, + "IOI_BLOCK_OUTS1_0": null, + "IOI_BLOCK_OUTS1_1": null, + "IOI_BLOCK_OUTS2_0": null, + "IOI_BLOCK_OUTS2_1": null, + "IOI_BLOCK_OUTS3_0": null, + "IOI_BLOCK_OUTS3_1": null, + "IOI_BYP0_0": null, + "IOI_BYP0_1": null, + "IOI_BYP1_0": null, + "IOI_BYP1_1": null, + "IOI_BYP2_0": null, + "IOI_BYP2_1": null, + "IOI_BYP3_0": null, + "IOI_BYP3_1": null, + "IOI_BYP4_0": null, + "IOI_BYP4_1": null, + "IOI_BYP5_0": null, + "IOI_BYP5_1": null, + "IOI_BYP6_0": null, + "IOI_BYP6_1": null, + "IOI_BYP7_0": null, + "IOI_BYP7_1": null, + "IOI_CLK0_0": null, + "IOI_CLK0_1": null, + "IOI_CLK1_0": null, + "IOI_CLK1_1": null, + "IOI_CTRL0_0": null, + "IOI_CTRL0_1": null, + "IOI_CTRL1_0": null, + "IOI_CTRL1_1": null, + "IOI_DCI_DCIDONE": null, + "IOI_DCI_TSTCLK": null, + "IOI_DCI_TSTHLN": null, + "IOI_DCI_TSTHLP": null, + "IOI_DCI_TSTRST": null, + "IOI_DCI_TSTRST0": null, + "IOI_EE2A0_0": null, + "IOI_EE2A0_1": null, + "IOI_EE2A1_0": null, + "IOI_EE2A1_1": null, + "IOI_EE2A2_0": null, + "IOI_EE2A2_1": null, + "IOI_EE2A3_0": null, + "IOI_EE2A3_1": null, + "IOI_EE2BEG0_0": null, + "IOI_EE2BEG0_1": null, + "IOI_EE2BEG1_0": null, + "IOI_EE2BEG1_1": null, + "IOI_EE2BEG2_0": null, + "IOI_EE2BEG2_1": null, + "IOI_EE2BEG3_0": null, + "IOI_EE2BEG3_1": null, + "IOI_EE4A0_0": null, + "IOI_EE4A0_1": null, + "IOI_EE4A1_0": null, + "IOI_EE4A1_1": null, + "IOI_EE4A2_0": null, + "IOI_EE4A2_1": null, + "IOI_EE4A3_0": null, + "IOI_EE4A3_1": null, + "IOI_EE4B0_0": null, + "IOI_EE4B0_1": null, + "IOI_EE4B1_0": null, + "IOI_EE4B1_1": null, + "IOI_EE4B2_0": null, + "IOI_EE4B2_1": null, + "IOI_EE4B3_0": null, + "IOI_EE4B3_1": null, + "IOI_EE4BEG0_0": null, + "IOI_EE4BEG0_1": null, + "IOI_EE4BEG1_0": null, + "IOI_EE4BEG1_1": null, + "IOI_EE4BEG2_0": null, + "IOI_EE4BEG2_1": null, + "IOI_EE4BEG3_0": null, + "IOI_EE4BEG3_1": null, + "IOI_EE4C0_0": null, + "IOI_EE4C0_1": null, + "IOI_EE4C1_0": null, + "IOI_EE4C1_1": null, + "IOI_EE4C2_0": null, + "IOI_EE4C2_1": null, + "IOI_EE4C3_0": null, + "IOI_EE4C3_1": null, + "IOI_EL1BEG0_0": null, + "IOI_EL1BEG0_1": null, + "IOI_EL1BEG1_0": null, + "IOI_EL1BEG1_1": null, + "IOI_EL1BEG2_0": null, + "IOI_EL1BEG2_1": null, + "IOI_EL1BEG3_0": null, + "IOI_EL1BEG3_1": null, + "IOI_ER1BEG0_0": null, + "IOI_ER1BEG0_1": null, + "IOI_ER1BEG1_0": null, + "IOI_ER1BEG1_1": null, + "IOI_ER1BEG2_0": null, + "IOI_ER1BEG2_1": null, + "IOI_ER1BEG3_0": null, + "IOI_ER1BEG3_1": null, + "IOI_FAN0_0": null, + "IOI_FAN0_1": null, + "IOI_FAN1_0": null, + "IOI_FAN1_1": null, + "IOI_FAN2_0": null, + "IOI_FAN2_1": null, + "IOI_FAN3_0": null, + "IOI_FAN3_1": null, + "IOI_FAN4_0": null, + "IOI_FAN4_1": null, + "IOI_FAN5_0": null, + "IOI_FAN5_1": null, + "IOI_FAN6_0": null, + "IOI_FAN6_1": null, + "IOI_FAN7_0": null, + "IOI_FAN7_1": null, + "IOI_IDELAY0_C": null, + "IOI_IDELAY0_CE": null, + "IOI_IDELAY0_CINVCTRL": null, + "IOI_IDELAY0_CNTVALUEIN0": null, + "IOI_IDELAY0_CNTVALUEIN1": null, + "IOI_IDELAY0_CNTVALUEIN2": null, + "IOI_IDELAY0_CNTVALUEIN3": null, + "IOI_IDELAY0_CNTVALUEIN4": null, + "IOI_IDELAY0_CNTVALUEOUT0": null, + "IOI_IDELAY0_CNTVALUEOUT1": null, + "IOI_IDELAY0_CNTVALUEOUT2": null, + "IOI_IDELAY0_CNTVALUEOUT3": null, + "IOI_IDELAY0_CNTVALUEOUT4": null, + "IOI_IDELAY0_DATAIN": null, + "IOI_IDELAY0_INC": null, + "IOI_IDELAY0_LD": null, + "IOI_IDELAY0_LDPIPEEN": null, + "IOI_IDELAY0_REGRST": null, + "IOI_IDELAY1_C": null, + "IOI_IDELAY1_CE": null, + "IOI_IDELAY1_CINVCTRL": null, + "IOI_IDELAY1_CNTVALUEIN0": null, + "IOI_IDELAY1_CNTVALUEIN1": null, + "IOI_IDELAY1_CNTVALUEIN2": null, + "IOI_IDELAY1_CNTVALUEIN3": null, + "IOI_IDELAY1_CNTVALUEIN4": null, + "IOI_IDELAY1_CNTVALUEOUT0": null, + "IOI_IDELAY1_CNTVALUEOUT1": null, + "IOI_IDELAY1_CNTVALUEOUT2": null, + "IOI_IDELAY1_CNTVALUEOUT3": null, + "IOI_IDELAY1_CNTVALUEOUT4": null, + "IOI_IDELAY1_DATAIN": null, + "IOI_IDELAY1_INC": null, + "IOI_IDELAY1_LD": null, + "IOI_IDELAY1_LDPIPEEN": null, + "IOI_IDELAY1_REGRST": null, + "IOI_IDELAYCTRL_DNPULSEOUT": null, + "IOI_IDELAYCTRL_OUTN1": null, + "IOI_IDELAYCTRL_OUTN65": null, + "IOI_IDELAYCTRL_RDY": null, + "IOI_IDELAYCTRL_RST": null, + "IOI_IDELAYCTRL_UPPULSEOUT": null, + "IOI_ILOGIC0_BITSLIP": null, + "IOI_ILOGIC0_CE1": null, + "IOI_ILOGIC0_CE2": null, + "IOI_ILOGIC0_CLK": null, + "IOI_ILOGIC0_CLKB": null, + "IOI_ILOGIC0_CLKDIV": null, + "IOI_ILOGIC0_CLKDIVP": null, + "IOI_ILOGIC0_DYNCLKDIVPSEL": null, + "IOI_ILOGIC0_DYNCLKDIVSEL": null, + "IOI_ILOGIC0_DYNCLKSEL": null, + "IOI_ILOGIC0_O": null, + "IOI_ILOGIC0_OCLK": null, + "IOI_ILOGIC0_OCLKB": null, + "IOI_ILOGIC0_Q1": null, + "IOI_ILOGIC0_Q2": null, + "IOI_ILOGIC0_Q3": null, + "IOI_ILOGIC0_Q4": null, + "IOI_ILOGIC0_Q5": null, + "IOI_ILOGIC0_Q6": null, + "IOI_ILOGIC0_Q7": null, + "IOI_ILOGIC0_Q8": null, + "IOI_ILOGIC0_REV": null, + "IOI_ILOGIC0_SR": null, + "IOI_ILOGIC1_BITSLIP": null, + "IOI_ILOGIC1_CE1": null, + "IOI_ILOGIC1_CE2": null, + "IOI_ILOGIC1_CLK": null, + "IOI_ILOGIC1_CLKB": null, + "IOI_ILOGIC1_CLKDIV": null, + "IOI_ILOGIC1_CLKDIVP": null, + "IOI_ILOGIC1_DYNCLKDIVPSEL": null, + "IOI_ILOGIC1_DYNCLKDIVSEL": null, + "IOI_ILOGIC1_DYNCLKSEL": null, + "IOI_ILOGIC1_O": null, + "IOI_ILOGIC1_OCLK": null, + "IOI_ILOGIC1_OCLKB": null, + "IOI_ILOGIC1_Q1": null, + "IOI_ILOGIC1_Q2": null, + "IOI_ILOGIC1_Q3": null, + "IOI_ILOGIC1_Q4": null, + "IOI_ILOGIC1_Q5": null, + "IOI_ILOGIC1_Q6": null, + "IOI_ILOGIC1_Q7": null, + "IOI_ILOGIC1_Q8": null, + "IOI_ILOGIC1_REV": null, + "IOI_ILOGIC1_SR": null, + "IOI_IMUX0_0": null, + "IOI_IMUX0_1": null, + "IOI_IMUX10_0": null, + "IOI_IMUX10_1": null, + "IOI_IMUX11_0": null, + "IOI_IMUX11_1": null, + "IOI_IMUX12_0": null, + "IOI_IMUX12_1": null, + "IOI_IMUX13_0": null, + "IOI_IMUX13_1": null, + "IOI_IMUX14_0": null, + "IOI_IMUX14_1": null, + "IOI_IMUX15_0": null, + "IOI_IMUX15_1": null, + "IOI_IMUX16_0": null, + "IOI_IMUX16_1": null, + "IOI_IMUX17_0": null, + "IOI_IMUX17_1": null, + "IOI_IMUX18_0": null, + "IOI_IMUX18_1": null, + "IOI_IMUX19_0": null, + "IOI_IMUX19_1": null, + "IOI_IMUX1_0": null, + "IOI_IMUX1_1": null, + "IOI_IMUX20_0": null, + "IOI_IMUX20_1": null, + "IOI_IMUX21_0": null, + "IOI_IMUX21_1": null, + "IOI_IMUX22_0": null, + "IOI_IMUX22_1": null, + "IOI_IMUX23_0": null, + "IOI_IMUX23_1": null, + "IOI_IMUX24_0": null, + "IOI_IMUX24_1": null, + "IOI_IMUX25_0": null, + "IOI_IMUX25_1": null, + "IOI_IMUX26_0": null, + "IOI_IMUX26_1": null, + "IOI_IMUX27_0": null, + "IOI_IMUX27_1": null, + "IOI_IMUX28_0": null, + "IOI_IMUX28_1": null, + "IOI_IMUX29_0": null, + "IOI_IMUX29_1": null, + "IOI_IMUX2_0": null, + "IOI_IMUX2_1": null, + "IOI_IMUX30_0": null, + "IOI_IMUX30_1": null, + "IOI_IMUX31_0": null, + "IOI_IMUX31_1": null, + "IOI_IMUX32_0": null, + "IOI_IMUX32_1": null, + "IOI_IMUX33_0": null, + "IOI_IMUX33_1": null, + "IOI_IMUX34_0": null, + "IOI_IMUX34_1": null, + "IOI_IMUX35_0": null, + "IOI_IMUX35_1": null, + "IOI_IMUX36_0": null, + "IOI_IMUX36_1": null, + "IOI_IMUX37_0": null, + "IOI_IMUX37_1": null, + "IOI_IMUX38_0": null, + "IOI_IMUX38_1": null, + "IOI_IMUX39_0": null, + "IOI_IMUX39_1": null, + "IOI_IMUX3_0": null, + "IOI_IMUX3_1": null, + "IOI_IMUX40_0": null, + "IOI_IMUX40_1": null, + "IOI_IMUX41_0": null, + "IOI_IMUX41_1": null, + "IOI_IMUX42_0": null, + "IOI_IMUX42_1": null, + "IOI_IMUX43_0": null, + "IOI_IMUX43_1": null, + "IOI_IMUX44_0": null, + "IOI_IMUX44_1": null, + "IOI_IMUX45_0": null, + "IOI_IMUX45_1": null, + "IOI_IMUX46_0": null, + "IOI_IMUX46_1": null, + "IOI_IMUX47_0": null, + "IOI_IMUX47_1": null, + "IOI_IMUX4_0": null, + "IOI_IMUX4_1": null, + "IOI_IMUX5_0": null, + "IOI_IMUX5_1": null, + "IOI_IMUX6_0": null, + "IOI_IMUX6_1": null, + "IOI_IMUX7_0": null, + "IOI_IMUX7_1": null, + "IOI_IMUX8_0": null, + "IOI_IMUX8_1": null, + "IOI_IMUX9_0": null, + "IOI_IMUX9_1": null, + "IOI_IMUX_RC0": null, + "IOI_IMUX_RC1": null, + "IOI_IMUX_RC2": null, + "IOI_IMUX_RC3": null, + "IOI_INT_DCI_EN": null, + "IOI_IOCLK0": null, + "IOI_IOCLK1": null, + "IOI_IOCLK2": null, + "IOI_IOCLK3": null, + "IOI_LEAF_GCLK0": null, + "IOI_LEAF_GCLK1": null, + "IOI_LEAF_GCLK2": null, + "IOI_LEAF_GCLK3": null, + "IOI_LEAF_GCLK4": null, + "IOI_LEAF_GCLK5": null, + "IOI_LH10_0": null, + "IOI_LH10_1": null, + "IOI_LH11_0": null, + "IOI_LH11_1": null, + "IOI_LH12_0": null, + "IOI_LH12_1": null, + "IOI_LH1_0": null, + "IOI_LH1_1": null, + "IOI_LH2_0": null, + "IOI_LH2_1": null, + "IOI_LH3_0": null, + "IOI_LH3_1": null, + "IOI_LH4_0": null, + "IOI_LH4_1": null, + "IOI_LH5_0": null, + "IOI_LH5_1": null, + "IOI_LH6_0": null, + "IOI_LH6_1": null, + "IOI_LH7_0": null, + "IOI_LH7_1": null, + "IOI_LH8_0": null, + "IOI_LH8_1": null, + "IOI_LH9_0": null, + "IOI_LH9_1": null, + "IOI_LOGIC_OUTS0_0": null, + "IOI_LOGIC_OUTS0_1": null, + "IOI_LOGIC_OUTS10_0": null, + "IOI_LOGIC_OUTS10_1": null, + "IOI_LOGIC_OUTS11_0": null, + "IOI_LOGIC_OUTS11_1": null, + "IOI_LOGIC_OUTS12_0": null, + "IOI_LOGIC_OUTS12_1": null, + "IOI_LOGIC_OUTS13_0": null, + "IOI_LOGIC_OUTS13_1": null, + "IOI_LOGIC_OUTS14_0": null, + "IOI_LOGIC_OUTS14_1": null, + "IOI_LOGIC_OUTS15_0": null, + "IOI_LOGIC_OUTS15_1": null, + "IOI_LOGIC_OUTS16_0": null, + "IOI_LOGIC_OUTS16_1": null, + "IOI_LOGIC_OUTS17_0": null, + "IOI_LOGIC_OUTS17_1": null, + "IOI_LOGIC_OUTS18_0": null, + "IOI_LOGIC_OUTS18_1": null, + "IOI_LOGIC_OUTS19_0": null, + "IOI_LOGIC_OUTS19_1": null, + "IOI_LOGIC_OUTS1_0": null, + "IOI_LOGIC_OUTS1_1": null, + "IOI_LOGIC_OUTS20_0": null, + "IOI_LOGIC_OUTS20_1": null, + "IOI_LOGIC_OUTS21_0": null, + "IOI_LOGIC_OUTS21_1": null, + "IOI_LOGIC_OUTS22_0": null, + "IOI_LOGIC_OUTS22_1": null, + "IOI_LOGIC_OUTS23_0": null, + "IOI_LOGIC_OUTS23_1": null, + "IOI_LOGIC_OUTS2_0": null, + "IOI_LOGIC_OUTS2_1": null, + "IOI_LOGIC_OUTS3_0": null, + "IOI_LOGIC_OUTS3_1": null, + "IOI_LOGIC_OUTS4_0": null, + "IOI_LOGIC_OUTS4_1": null, + "IOI_LOGIC_OUTS5_0": null, + "IOI_LOGIC_OUTS5_1": null, + "IOI_LOGIC_OUTS6_0": null, + "IOI_LOGIC_OUTS6_1": null, + "IOI_LOGIC_OUTS7_0": null, + "IOI_LOGIC_OUTS7_1": null, + "IOI_LOGIC_OUTS8_0": null, + "IOI_LOGIC_OUTS8_1": null, + "IOI_LOGIC_OUTS9_0": null, + "IOI_LOGIC_OUTS9_1": null, + "IOI_MONITOR_N": null, + "IOI_MONITOR_P": null, + "IOI_NE2A0_0": null, + "IOI_NE2A0_1": null, + "IOI_NE2A1_0": null, + "IOI_NE2A1_1": null, + "IOI_NE2A2_0": null, + "IOI_NE2A2_1": null, + "IOI_NE2A3_0": null, + "IOI_NE2A3_1": null, + "IOI_NE4BEG0_0": null, + "IOI_NE4BEG0_1": null, + "IOI_NE4BEG1_0": null, + "IOI_NE4BEG1_1": null, + "IOI_NE4BEG2_0": null, + "IOI_NE4BEG2_1": null, + "IOI_NE4BEG3_0": null, + "IOI_NE4BEG3_1": null, + "IOI_NE4C0_0": null, + "IOI_NE4C0_1": null, + "IOI_NE4C1_0": null, + "IOI_NE4C1_1": null, + "IOI_NE4C2_0": null, + "IOI_NE4C2_1": null, + "IOI_NE4C3_0": null, + "IOI_NE4C3_1": null, + "IOI_NW2A0_0": null, + "IOI_NW2A0_1": null, + "IOI_NW2A1_0": null, + "IOI_NW2A1_1": null, + "IOI_NW2A2_0": null, + "IOI_NW2A2_1": null, + "IOI_NW2A3_0": null, + "IOI_NW2A3_1": null, + "IOI_NW4A0_0": null, + "IOI_NW4A0_1": null, + "IOI_NW4A1_0": null, + "IOI_NW4A1_1": null, + "IOI_NW4A2_0": null, + "IOI_NW4A2_1": null, + "IOI_NW4A3_0": null, + "IOI_NW4A3_1": null, + "IOI_NW4END0_0": null, + "IOI_NW4END0_1": null, + "IOI_NW4END1_0": null, + "IOI_NW4END1_1": null, + "IOI_NW4END2_0": null, + "IOI_NW4END2_1": null, + "IOI_NW4END3_0": null, + "IOI_NW4END3_1": null, + "IOI_OCLKM_0": null, + "IOI_OCLKM_1": null, + "IOI_OCLK_0": null, + "IOI_OCLK_1": null, + "IOI_ODELAY0_C": null, + "IOI_ODELAY0_CE": null, + "IOI_ODELAY0_CINVCTRL": null, + "IOI_ODELAY0_CLKIN": null, + "IOI_ODELAY0_CNTVALUEIN0": null, + "IOI_ODELAY0_CNTVALUEIN1": null, + "IOI_ODELAY0_CNTVALUEIN2": null, + "IOI_ODELAY0_CNTVALUEIN3": null, + "IOI_ODELAY0_CNTVALUEIN4": null, + "IOI_ODELAY0_CNTVALUEOUT0": null, + "IOI_ODELAY0_CNTVALUEOUT1": null, + "IOI_ODELAY0_CNTVALUEOUT2": null, + "IOI_ODELAY0_CNTVALUEOUT3": null, + "IOI_ODELAY0_CNTVALUEOUT4": null, + "IOI_ODELAY0_INC": null, + "IOI_ODELAY0_LD": null, + "IOI_ODELAY0_LDPIPEEN": null, + "IOI_ODELAY0_REGRST": null, + "IOI_ODELAY1_C": null, + "IOI_ODELAY1_CE": null, + "IOI_ODELAY1_CINVCTRL": null, + "IOI_ODELAY1_CLKIN": null, + "IOI_ODELAY1_CNTVALUEIN0": null, + "IOI_ODELAY1_CNTVALUEIN1": null, + "IOI_ODELAY1_CNTVALUEIN2": null, + "IOI_ODELAY1_CNTVALUEIN3": null, + "IOI_ODELAY1_CNTVALUEIN4": null, + "IOI_ODELAY1_CNTVALUEOUT0": null, + "IOI_ODELAY1_CNTVALUEOUT1": null, + "IOI_ODELAY1_CNTVALUEOUT2": null, + "IOI_ODELAY1_CNTVALUEOUT3": null, + "IOI_ODELAY1_CNTVALUEOUT4": null, + "IOI_ODELAY1_INC": null, + "IOI_ODELAY1_LD": null, + "IOI_ODELAY1_LDPIPEEN": null, + "IOI_ODELAY1_REGRST": null, + "IOI_OLOGIC0_CLK": null, + "IOI_OLOGIC0_CLKB": null, + "IOI_OLOGIC0_CLKDIV": null, + "IOI_OLOGIC0_CLKDIVB": null, + "IOI_OLOGIC0_CLKDIVFB": null, + "IOI_OLOGIC0_D1": null, + "IOI_OLOGIC0_D2": null, + "IOI_OLOGIC0_D3": null, + "IOI_OLOGIC0_D4": null, + "IOI_OLOGIC0_D5": null, + "IOI_OLOGIC0_D6": null, + "IOI_OLOGIC0_D7": null, + "IOI_OLOGIC0_D8": null, + "IOI_OLOGIC0_IOCLKGLITCH": null, + "IOI_OLOGIC0_OCE": null, + "IOI_OLOGIC0_REV": null, + "IOI_OLOGIC0_SR": null, + "IOI_OLOGIC0_T1": null, + "IOI_OLOGIC0_T2": null, + "IOI_OLOGIC0_T3": null, + "IOI_OLOGIC0_T4": null, + "IOI_OLOGIC0_TBYTEIN": null, + "IOI_OLOGIC0_TBYTEOUT": null, + "IOI_OLOGIC0_TCE": null, + "IOI_OLOGIC1_CLK": null, + "IOI_OLOGIC1_CLKB": null, + "IOI_OLOGIC1_CLKDIV": null, + "IOI_OLOGIC1_CLKDIVB": null, + "IOI_OLOGIC1_CLKDIVFB": null, + "IOI_OLOGIC1_D1": null, + "IOI_OLOGIC1_D2": null, + "IOI_OLOGIC1_D3": null, + "IOI_OLOGIC1_D4": null, + "IOI_OLOGIC1_D5": null, + "IOI_OLOGIC1_D6": null, + "IOI_OLOGIC1_D7": null, + "IOI_OLOGIC1_D8": null, + "IOI_OLOGIC1_IOCLKGLITCH": null, + "IOI_OLOGIC1_OCE": null, + "IOI_OLOGIC1_REV": null, + "IOI_OLOGIC1_SR": null, + "IOI_OLOGIC1_T1": null, + "IOI_OLOGIC1_T2": null, + "IOI_OLOGIC1_T3": null, + "IOI_OLOGIC1_T4": null, + "IOI_OLOGIC1_TBYTEIN": null, + "IOI_OLOGIC1_TBYTEOUT": null, + "IOI_OLOGIC1_TCE": null, + "IOI_PHASER_TO_IO_ICLK": null, + "IOI_PHASER_TO_IO_ICLKDIV": null, + "IOI_PHASER_TO_IO_ICLKDIV_0": null, + "IOI_PHASER_TO_IO_ICLK_0": null, + "IOI_PHASER_TO_IO_OCLK": null, + "IOI_PHASER_TO_IO_OCLK1X_90": null, + "IOI_PHASER_TO_IO_OCLK1X_90_0": null, + "IOI_PHASER_TO_IO_OCLKDIV": null, + "IOI_PHASER_TO_IO_OCLKDIV_0": null, + "IOI_PHASER_TO_IO_OCLK_0": null, + "IOI_RCLK_DIV_CE0": null, + "IOI_RCLK_DIV_CE1": null, + "IOI_RCLK_DIV_CE2": null, + "IOI_RCLK_DIV_CE2_1": null, + "IOI_RCLK_DIV_CE3": null, + "IOI_RCLK_DIV_CE3_1": null, + "IOI_RCLK_DIV_CLR0": null, + "IOI_RCLK_DIV_CLR0_1": null, + "IOI_RCLK_DIV_CLR1": null, + "IOI_RCLK_DIV_CLR1_1": null, + "IOI_RCLK_DIV_CLR2": null, + "IOI_RCLK_DIV_CLR3": null, + "IOI_RCLK_FORIO0": null, + "IOI_RCLK_FORIO1": null, + "IOI_RCLK_FORIO2": null, + "IOI_RCLK_FORIO3": null, + "IOI_SE2A0_0": null, + "IOI_SE2A0_1": null, + "IOI_SE2A1_0": null, + "IOI_SE2A1_1": null, + "IOI_SE2A2_0": null, + "IOI_SE2A2_1": null, + "IOI_SE2A3_0": null, + "IOI_SE2A3_1": null, + "IOI_SE4BEG0_0": null, + "IOI_SE4BEG0_1": null, + "IOI_SE4BEG1_0": null, + "IOI_SE4BEG1_1": null, + "IOI_SE4BEG2_0": null, + "IOI_SE4BEG2_1": null, + "IOI_SE4BEG3_0": null, + "IOI_SE4BEG3_1": null, + "IOI_SE4C0_0": null, + "IOI_SE4C0_1": null, + "IOI_SE4C1_0": null, + "IOI_SE4C1_1": null, + "IOI_SE4C2_0": null, + "IOI_SE4C2_1": null, + "IOI_SE4C3_0": null, + "IOI_SE4C3_1": null, + "IOI_SW2A0_0": null, + "IOI_SW2A0_1": null, + "IOI_SW2A1_0": null, + "IOI_SW2A1_1": null, + "IOI_SW2A2_0": null, + "IOI_SW2A2_1": null, + "IOI_SW2A3_0": null, + "IOI_SW2A3_1": null, + "IOI_SW4A0_0": null, + "IOI_SW4A0_1": null, + "IOI_SW4A1_0": null, + "IOI_SW4A1_1": null, + "IOI_SW4A2_0": null, + "IOI_SW4A2_1": null, + "IOI_SW4A3_0": null, + "IOI_SW4A3_1": null, + "IOI_SW4END0_0": null, + "IOI_SW4END0_1": null, + "IOI_SW4END1_0": null, + "IOI_SW4END1_1": null, + "IOI_SW4END2_0": null, + "IOI_SW4END2_1": null, + "IOI_SW4END3_0": null, + "IOI_SW4END3_1": null, + "IOI_TBYTEIN": null, + "IOI_WL1END0_0": null, + "IOI_WL1END0_1": null, + "IOI_WL1END1_0": null, + "IOI_WL1END1_1": null, + "IOI_WL1END2_0": null, + "IOI_WL1END2_1": null, + "IOI_WL1END3_0": null, + "IOI_WL1END3_1": null, + "IOI_WR1END0_0": null, + "IOI_WR1END0_1": null, + "IOI_WR1END1_0": null, + "IOI_WR1END1_1": null, + "IOI_WR1END2_0": null, + "IOI_WR1END2_1": null, + "IOI_WR1END3_0": null, + "IOI_WR1END3_1": null, + "IOI_WW2A0_0": null, + "IOI_WW2A0_1": null, + "IOI_WW2A1_0": null, + "IOI_WW2A1_1": null, + "IOI_WW2A2_0": null, + "IOI_WW2A2_1": null, + "IOI_WW2A3_0": null, + "IOI_WW2A3_1": null, + "IOI_WW2END0_0": null, + "IOI_WW2END0_1": null, + "IOI_WW2END1_0": null, + "IOI_WW2END1_1": null, + "IOI_WW2END2_0": null, + "IOI_WW2END2_1": null, + "IOI_WW2END3_0": null, + "IOI_WW2END3_1": null, + "IOI_WW4A0_0": null, + "IOI_WW4A0_1": null, + "IOI_WW4A1_0": null, + "IOI_WW4A1_1": null, + "IOI_WW4A2_0": null, + "IOI_WW4A2_1": null, + "IOI_WW4A3_0": null, + "IOI_WW4A3_1": null, + "IOI_WW4B0_0": null, + "IOI_WW4B0_1": null, + "IOI_WW4B1_0": null, + "IOI_WW4B1_1": null, + "IOI_WW4B2_0": null, + "IOI_WW4B2_1": null, + "IOI_WW4B3_0": null, + "IOI_WW4B3_1": null, + "IOI_WW4C0_0": null, + "IOI_WW4C0_1": null, + "IOI_WW4C1_0": null, + "IOI_WW4C1_1": null, + "IOI_WW4C2_0": null, + "IOI_WW4C2_1": null, + "IOI_WW4C3_0": null, + "IOI_WW4C3_1": null, + "IOI_WW4END0_0": null, + "IOI_WW4END0_1": null, + "IOI_WW4END1_0": null, + "IOI_WW4END1_1": null, + "IOI_WW4END2_0": null, + "IOI_WW4END2_1": null, + "IOI_WW4END3_0": null, + "IOI_WW4END3_1": null, + "RIOI3_IDELAY0_IFDLY0": null, + "RIOI3_IDELAY0_IFDLY1": null, + "RIOI3_IDELAY0_IFDLY2": null, + "RIOI3_IDELAY1_IFDLY0": null, + "RIOI3_IDELAY1_IFDLY1": null, + "RIOI3_IDELAY1_IFDLY2": null, + "RIOI_DCI_T_TERM0": null, + "RIOI_DCI_T_TERM1": null, + "RIOI_DIFF_TERM_INT_EN": null, + "RIOI_I0": null, + "RIOI_I1": null, + "RIOI_I2GCLK_BOT1": null, + "RIOI_I2GCLK_TOP0": null, + "RIOI_I2GCLK_TOP1": null, + "RIOI_IBUF0": null, + "RIOI_IBUF1": null, + "RIOI_IBUF_DISABLE0": null, + "RIOI_IBUF_DISABLE1": null, + "RIOI_IDELAY0_DATAOUT": null, + "RIOI_IDELAY0_IDATAIN": null, + "RIOI_IDELAY1_DATAOUT": null, + "RIOI_IDELAY1_IDATAIN": null, + "RIOI_ILOGIC0_D": null, + "RIOI_ILOGIC0_DDLY": null, + "RIOI_ILOGIC0_OFB": null, + "RIOI_ILOGIC0_TFB": null, + "RIOI_ILOGIC1_D": null, + "RIOI_ILOGIC1_DDLY": null, + "RIOI_ILOGIC1_OFB": null, + "RIOI_ILOGIC1_TFB": null, + "RIOI_ISIN10": null, + "RIOI_ISIN11": null, + "RIOI_ISIN20": null, + "RIOI_ISIN21": null, + "RIOI_ISOUT10": null, + "RIOI_ISOUT11": null, + "RIOI_ISOUT20": null, + "RIOI_ISOUT21": null, + "RIOI_KEEPER_INT_EN_0": null, + "RIOI_KEEPER_INT_EN_1": null, + "RIOI_O0": null, + "RIOI_O1": null, + "RIOI_ODELAY0_DATAOUT": null, + "RIOI_ODELAY0_ODATAIN": null, + "RIOI_ODELAY0_OFDLY0": null, + "RIOI_ODELAY0_OFDLY1": null, + "RIOI_ODELAY0_OFDLY2": null, + "RIOI_ODELAY1_DATAOUT": null, + "RIOI_ODELAY1_ODATAIN": null, + "RIOI_ODELAY1_OFDLY0": null, + "RIOI_ODELAY1_OFDLY1": null, + "RIOI_ODELAY1_OFDLY2": null, + "RIOI_OLOGIC0_CLKDIVF": null, + "RIOI_OLOGIC0_OFB": null, + "RIOI_OLOGIC0_OQ": null, + "RIOI_OLOGIC0_TFB": null, + "RIOI_OLOGIC0_TFB_LOCAL": null, + "RIOI_OLOGIC0_TQ": null, + "RIOI_OLOGIC1_CLKDIVF": null, + "RIOI_OLOGIC1_OFB": null, + "RIOI_OLOGIC1_OQ": null, + "RIOI_OLOGIC1_TFB": null, + "RIOI_OLOGIC1_TFB_LOCAL": null, + "RIOI_OLOGIC1_TQ": null, + "RIOI_OSIN10": null, + "RIOI_OSIN11": null, + "RIOI_OSIN20": null, + "RIOI_OSIN21": null, + "RIOI_OSOUT10": null, + "RIOI_OSOUT11": null, + "RIOI_OSOUT20": null, + "RIOI_OSOUT21": null, + "RIOI_PD_INT_EN_0": null, + "RIOI_PD_INT_EN_1": null, + "RIOI_PU_INT_EN_0": null, + "RIOI_PU_INT_EN_1": null, + "RIOI_T0": null, + "RIOI_T1": null + } } diff --git a/zynq7/tile_type_RIOI3_SING.json b/zynq7/tile_type_RIOI3_SING.json index a2db2eb..e347358 100644 --- a/zynq7/tile_type_RIOI3_SING.json +++ b/zynq7/tile_type_RIOI3_SING.json @@ -2,1395 +2,4854 @@ "pips": { "RIOI3_SING.IOI_BYP6_0->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_0" }, "RIOI3_SING.IOI_BYP7_0->RIOI3_IDELAY0_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY0_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_0" }, "RIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI3_SING.IOI_CLK1_0->IOI_IDELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "RIOI3_SING.IOI_CTRL0_0->IOI_OLOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_0" }, "RIOI3_SING.IOI_CTRL1_0->IOI_ILOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_0" }, "RIOI3_SING.IOI_FAN4_0->RIOI3_IDELAY0_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY0_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_0" }, "RIOI3_SING.IOI_FAN5_0->RIOI3_IDELAY0_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY0_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_0" }, "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "RIOI3_SING.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "RIOI3_SING.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC0_O" }, "RIOI3_SING.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q1" }, "RIOI3_SING.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q2" }, "RIOI3_SING.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q3" }, "RIOI3_SING.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q4" }, "RIOI3_SING.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q5" }, "RIOI3_SING.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q6" }, "RIOI3_SING.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q7" }, "RIOI3_SING.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q8" }, "RIOI3_SING.IOI_IMUX0_0->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_0" }, "RIOI3_SING.IOI_IMUX10_0->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_0" }, "RIOI3_SING.IOI_IMUX12_0->IOI_IDELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_0" }, "RIOI3_SING.IOI_IMUX13_0->IOI_OLOGIC0_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_0" }, "RIOI3_SING.IOI_IMUX14_0->IOI_ILOGIC0_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_0" }, "RIOI3_SING.IOI_IMUX15_0->IOI_OLOGIC0_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_0" }, "RIOI3_SING.IOI_IMUX1_0->IOI_OLOGIC0_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_0" }, "RIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI3_SING.IOI_IMUX21_0->IOI_OLOGIC0_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_0" }, "RIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI3_SING.IOI_IMUX25_0->IOI_IDELAY0_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_0" }, "RIOI3_SING.IOI_IMUX26_0->IOI_IDELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_0" }, "RIOI3_SING.IOI_IMUX29_0->IOI_OLOGIC0_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_0" }, "RIOI3_SING.IOI_IMUX30_0->IOI_IDELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_0" }, "RIOI3_SING.IOI_IMUX31_0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI3_SING.IOI_IMUX31_0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI3_SING.IOI_IMUX32_0->IOI_IDELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_0" }, "RIOI3_SING.IOI_IMUX33_0->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_0" }, "RIOI3_SING.IOI_IMUX34_0->IOI_OLOGIC0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_0" }, "RIOI3_SING.IOI_IMUX35_0->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_0" }, "RIOI3_SING.IOI_IMUX36_0->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_0" }, "RIOI3_SING.IOI_IMUX37_0->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_0" }, "RIOI3_SING.IOI_IMUX38_0->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_0" }, "RIOI3_SING.IOI_IMUX39_0->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_0" }, "RIOI3_SING.IOI_IMUX40_0->IOI_OLOGIC0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_0" }, "RIOI3_SING.IOI_IMUX41_0->IOI_IDELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_0" }, "RIOI3_SING.IOI_IMUX42_0->IOI_OLOGIC0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_0" }, "RIOI3_SING.IOI_IMUX43_0->IOI_OLOGIC0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_0" }, "RIOI3_SING.IOI_IMUX44_0->IOI_OLOGIC0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_0" }, "RIOI3_SING.IOI_IMUX45_0->IOI_OLOGIC0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_0" }, "RIOI3_SING.IOI_IMUX46_0->IOI_OLOGIC0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_0" }, "RIOI3_SING.IOI_IMUX47_0->IOI_OLOGIC0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_0" }, "RIOI3_SING.IOI_IMUX4_0->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_0" }, "RIOI3_SING.IOI_IMUX5_0->IOI_ILOGIC0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_0" }, "RIOI3_SING.IOI_IMUX6_0->RIOI_DCI_T_TERM0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_0" }, "RIOI3_SING.IOI_IMUX7_0->IOI_OLOGIC0_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_0" }, "RIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3_SING.IOI_IMUX8_0->IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3_SING.IOI_IMUX8_0->RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3_SING.IOI_IMUX9_0->RIOI_IBUF_DISABLE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_0" }, "RIOI3_SING.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI3_SING.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3_SING.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI3_SING.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI3_SING.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC0_IOCLKGLITCH" }, "RIOI3_SING.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI3_SING.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI3_SING.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV" }, "RIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3_SING.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90" }, "RIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, "RIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, "RIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK0" }, "RIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK0" }, "RIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK0" }, "RIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK0" }, "RIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK1" }, "RIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK1" }, "RIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK1" }, "RIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK1" }, "RIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK2" }, "RIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK2" }, "RIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK2" }, "RIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK2" }, "RIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK3" }, "RIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK3" }, "RIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK3" }, "RIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK3" }, "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI3_SING.IOI_SING_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI3_SING.IOI_SING_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI3_SING.IOI_SING_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI3_SING.IOI_SING_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI3_SING.IOI_SING_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "RIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + 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"is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": 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"IOI_SING_RCLK_FORIO2" }, "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "RIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "RIOI3_SING.IOI_SING_RCLK_FORIO2->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI3_SING.IOI_SING_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI3_SING.IOI_SING_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_TBYTEIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_TBYTEIN" }, "RIOI3_SING.RIOI_I0->RIOI_IDELAY0_IDATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IDATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_I0" }, "RIOI3_SING.RIOI_I0->RIOI_ILOGIC0_D": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_D", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_I0" }, "RIOI3_SING.RIOI_IBUF0->RIOI_I0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_I0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_IBUF0" }, "RIOI3_SING.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_DDLY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_IDELAY0_DATAOUT" }, "RIOI3_SING.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.243", + "0.305", + "0.755", + "0.815" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_IDELAY0_DATAOUT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.243", + "0.305", + "0.755", + "0.815" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_IDELAY0_IDATAIN" }, "RIOI3_SING.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.054", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.054", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC0_D" }, "RIOI3_SING.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.055", + "0.120", + "0.138" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.055", + "0.120", + "0.138" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC0_DDLY" }, "RIOI3_SING.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_OFB" }, "RIOI3_SING.RIOI_OLOGIC0_OQ->>RIOI_O0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_O0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_OQ" }, "RIOI3_SING.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_OQ" }, "RIOI3_SING.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB" }, "RIOI3_SING.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI3_SING.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI3_SING.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" }, "RIOI3_SING.RIOI_OLOGIC0_TQ->>RIOI_T0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_T0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" } }, @@ -1399,39 +4858,309 @@ "name": "X0Y0", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC0_CLK", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "D1": "IOI_OLOGIC0_D1", - "D2": "IOI_OLOGIC0_D2", - "D3": "IOI_OLOGIC0_D3", - "D4": "IOI_OLOGIC0_D4", - "D5": "IOI_OLOGIC0_D5", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D8": "IOI_OLOGIC0_D8", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "OCE": "IOI_OLOGIC0_OCE", - "OFB": "RIOI_OLOGIC0_OFB", - "OQ": "RIOI_OLOGIC0_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OQ" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_OSOUT10", - "SHIFTOUT2": "RIOI_OSOUT20", - "SR": "IOI_OLOGIC0_SR", - "T1": "IOI_OLOGIC0_T1", - "T2": "IOI_OLOGIC0_T2", - "T3": "IOI_OLOGIC0_T3", - "T4": "IOI_OLOGIC0_T4", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "TCE": "IOI_OLOGIC0_TCE", - "TFB": "RIOI_OLOGIC0_TFB", - "TQ": "RIOI_OLOGIC0_TQ" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -1441,37 +5170,289 @@ "name": "X0Y0", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "CE1": "IOI_ILOGIC0_CE1", - "CE2": "IOI_ILOGIC0_CE2", - "CLK": "IOI_ILOGIC0_CLK", - "CLKB": "IOI_ILOGIC0_CLKB", - "CLKDIV": "IOI_ILOGIC0_CLKDIV", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "D": "RIOI_ILOGIC0_D", - "DDLY": "RIOI_ILOGIC0_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "O": "IOI_ILOGIC0_O", - "OCLK": "IOI_ILOGIC0_OCLK", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "OFB": "RIOI_ILOGIC0_OFB", - "Q1": "IOI_ILOGIC0_Q1", - "Q2": "IOI_ILOGIC0_Q2", - "Q3": "IOI_ILOGIC0_Q3", - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q6": "IOI_ILOGIC0_Q6", - "Q7": "IOI_ILOGIC0_Q7", - "Q8": "IOI_ILOGIC0_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC0_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q8" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_ISOUT10", - "SHIFTOUT2": "RIOI_ISOUT20", - "SR": "IOI_ILOGIC0_SR", - "TFB": "RIOI_ILOGIC0_TFB" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -1481,29 +5462,236 @@ "name": "X0Y0", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY0_C", - "CE": "IOI_IDELAY0_CE", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY0_DATAIN", - "DATAOUT": "RIOI_IDELAY0_DATAOUT", - "IDATAIN": "RIOI_IDELAY0_IDATAIN", - "IFDLY0": "RIOI3_IDELAY0_IFDLY0", - "IFDLY1": "RIOI3_IDELAY0_IFDLY1", - "IFDLY2": "RIOI3_IDELAY0_IFDLY2", - "INC": "IOI_IDELAY0_INC", - "LD": "IOI_IDELAY0_LD", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "REGRST": "IOI_IDELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY0_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY0_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY0_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY0_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -1511,368 +5699,368 @@ } ], "tile_type": "RIOI3_SING", - "wires": [ - "IOI_BLOCK_OUTS0_0", - "IOI_BLOCK_OUTS1_0", - "IOI_BLOCK_OUTS2_0", - "IOI_BLOCK_OUTS3_0", - "IOI_BYP0_0", - "IOI_BYP1_0", - "IOI_BYP2_0", - "IOI_BYP3_0", - "IOI_BYP4_0", - "IOI_BYP5_0", - "IOI_BYP6_0", - "IOI_BYP7_0", - "IOI_CLK0_0", - "IOI_CLK1_0", - "IOI_CTRL0_0", - "IOI_CTRL1_0", - "IOI_EE2A0_0", - "IOI_EE2A1_0", - "IOI_EE2A2_0", - "IOI_EE2A3_0", - "IOI_EE2BEG0_0", - "IOI_EE2BEG1_0", - "IOI_EE2BEG2_0", - "IOI_EE2BEG3_0", - "IOI_EE4A0_0", - "IOI_EE4A1_0", - "IOI_EE4A2_0", - "IOI_EE4A3_0", - "IOI_EE4B0_0", - "IOI_EE4B1_0", - "IOI_EE4B2_0", - "IOI_EE4B3_0", - "IOI_EE4BEG0_0", - "IOI_EE4BEG1_0", - "IOI_EE4BEG2_0", - "IOI_EE4BEG3_0", - "IOI_EE4C0_0", - "IOI_EE4C1_0", - "IOI_EE4C2_0", - "IOI_EE4C3_0", - "IOI_EL1BEG0_0", - "IOI_EL1BEG1_0", - "IOI_EL1BEG2_0", - "IOI_EL1BEG3_0", - "IOI_ER1BEG0_0", - "IOI_ER1BEG1_0", - "IOI_ER1BEG2_0", - "IOI_ER1BEG3_0", - "IOI_FAN0_0", - "IOI_FAN1_0", - "IOI_FAN2_0", - "IOI_FAN3_0", - "IOI_FAN4_0", - "IOI_FAN5_0", - "IOI_FAN6_0", - "IOI_FAN7_0", - "IOI_IDELAY0_C", - "IOI_IDELAY0_CE", - "IOI_IDELAY0_CINVCTRL", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_IDELAY0_DATAIN", - "IOI_IDELAY0_INC", - "IOI_IDELAY0_LD", - "IOI_IDELAY0_LDPIPEEN", - "IOI_IDELAY0_REGRST", - "IOI_ILOGIC0_BITSLIP", - "IOI_ILOGIC0_CE1", - "IOI_ILOGIC0_CE2", - "IOI_ILOGIC0_CLK", - "IOI_ILOGIC0_CLKB", - "IOI_ILOGIC0_CLKDIV", - "IOI_ILOGIC0_CLKDIVP", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_ILOGIC0_O", - "IOI_ILOGIC0_OCLK", - "IOI_ILOGIC0_OCLKB", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_Q2", - "IOI_ILOGIC0_Q3", - "IOI_ILOGIC0_Q4", - "IOI_ILOGIC0_Q5", - "IOI_ILOGIC0_Q6", - "IOI_ILOGIC0_Q7", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC0_REV", - "IOI_ILOGIC0_SR", - "IOI_IMUX0_0", - "IOI_IMUX10_0", - "IOI_IMUX11_0", - "IOI_IMUX12_0", - "IOI_IMUX13_0", - "IOI_IMUX14_0", - "IOI_IMUX15_0", - "IOI_IMUX16_0", - "IOI_IMUX17_0", - "IOI_IMUX18_0", - "IOI_IMUX19_0", - "IOI_IMUX1_0", - "IOI_IMUX20_0", - "IOI_IMUX21_0", - "IOI_IMUX22_0", - "IOI_IMUX23_0", - "IOI_IMUX24_0", - "IOI_IMUX25_0", - "IOI_IMUX26_0", - "IOI_IMUX27_0", - "IOI_IMUX28_0", - "IOI_IMUX29_0", - "IOI_IMUX2_0", - "IOI_IMUX30_0", - "IOI_IMUX31_0", - "IOI_IMUX32_0", - "IOI_IMUX33_0", - "IOI_IMUX34_0", - "IOI_IMUX35_0", - "IOI_IMUX36_0", - "IOI_IMUX37_0", - "IOI_IMUX38_0", - "IOI_IMUX39_0", - "IOI_IMUX3_0", - "IOI_IMUX40_0", - "IOI_IMUX41_0", - "IOI_IMUX42_0", - "IOI_IMUX43_0", - "IOI_IMUX44_0", - "IOI_IMUX45_0", - "IOI_IMUX46_0", - "IOI_IMUX47_0", - "IOI_IMUX4_0", - "IOI_IMUX5_0", - "IOI_IMUX6_0", - "IOI_IMUX7_0", - "IOI_IMUX8_0", - "IOI_IMUX9_0", - "IOI_LH10_0", - "IOI_LH11_0", - "IOI_LH12_0", - "IOI_LH1_0", - "IOI_LH2_0", - "IOI_LH3_0", - "IOI_LH4_0", - "IOI_LH5_0", - "IOI_LH6_0", - "IOI_LH7_0", - "IOI_LH8_0", - "IOI_LH9_0", - "IOI_LOGIC_OUTS0_0", - "IOI_LOGIC_OUTS10_0", - "IOI_LOGIC_OUTS11_0", - "IOI_LOGIC_OUTS12_0", - "IOI_LOGIC_OUTS13_0", - "IOI_LOGIC_OUTS14_0", - "IOI_LOGIC_OUTS15_0", - "IOI_LOGIC_OUTS16_0", - "IOI_LOGIC_OUTS17_0", - "IOI_LOGIC_OUTS18_0", - "IOI_LOGIC_OUTS19_0", - "IOI_LOGIC_OUTS1_0", - "IOI_LOGIC_OUTS20_0", - "IOI_LOGIC_OUTS21_0", - "IOI_LOGIC_OUTS22_0", - "IOI_LOGIC_OUTS23_0", - "IOI_LOGIC_OUTS2_0", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS4_0", - "IOI_LOGIC_OUTS5_0", - "IOI_LOGIC_OUTS6_0", - "IOI_LOGIC_OUTS7_0", - "IOI_LOGIC_OUTS8_0", - "IOI_LOGIC_OUTS9_0", - "IOI_NE2A0_0", - "IOI_NE2A1_0", - "IOI_NE2A2_0", - "IOI_NE2A3_0", - "IOI_NE4BEG0_0", - "IOI_NE4BEG1_0", - "IOI_NE4BEG2_0", - "IOI_NE4BEG3_0", - "IOI_NE4C0_0", - "IOI_NE4C1_0", - "IOI_NE4C2_0", - "IOI_NE4C3_0", - "IOI_NW2A0_0", - "IOI_NW2A1_0", - "IOI_NW2A2_0", - "IOI_NW2A3_0", - "IOI_NW4A0_0", - "IOI_NW4A1_0", - "IOI_NW4A2_0", - "IOI_NW4A3_0", - "IOI_NW4END0_0", - "IOI_NW4END1_0", - "IOI_NW4END2_0", - "IOI_NW4END3_0", - "IOI_OCLKM_0", - "IOI_OCLK_0", - "IOI_ODELAY0_C", - "IOI_ODELAY0_CE", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY0_CLKIN", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ODELAY0_INC", - "IOI_ODELAY0_LD", - "IOI_ODELAY0_LDPIPEEN", - "IOI_ODELAY0_REGRST", - "IOI_OLOGIC0_CLK", - "IOI_OLOGIC0_CLKB", - "IOI_OLOGIC0_CLKDIV", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_OLOGIC0_D1", - "IOI_OLOGIC0_D2", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_D4", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_D6", - "IOI_OLOGIC0_D7", - "IOI_OLOGIC0_D8", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_OCE", - "IOI_OLOGIC0_REV", - "IOI_OLOGIC0_SR", - "IOI_OLOGIC0_T1", - "IOI_OLOGIC0_T2", - "IOI_OLOGIC0_T3", - "IOI_OLOGIC0_T4", - "IOI_OLOGIC0_TBYTEIN", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_OLOGIC0_TCE", - "IOI_PHASER_TO_IO_ICLK", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_PHASER_TO_IO_OCLK", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_SE2A0_0", - "IOI_SE2A1_0", - "IOI_SE2A2_0", - "IOI_SE2A3_0", - "IOI_SE4BEG0_0", - "IOI_SE4BEG1_0", - "IOI_SE4BEG2_0", - "IOI_SE4BEG3_0", - "IOI_SE4C0_0", - "IOI_SE4C1_0", - "IOI_SE4C2_0", - "IOI_SE4C3_0", - "IOI_SING_IOCLK0", - "IOI_SING_IOCLK1", - "IOI_SING_IOCLK2", - "IOI_SING_IOCLK3", - "IOI_SING_LEAF_GCLK0", - "IOI_SING_LEAF_GCLK1", - "IOI_SING_LEAF_GCLK2", - "IOI_SING_LEAF_GCLK3", - "IOI_SING_LEAF_GCLK4", - "IOI_SING_LEAF_GCLK5", - "IOI_SING_RCLK_FORIO0", - "IOI_SING_RCLK_FORIO1", - "IOI_SING_RCLK_FORIO2", - "IOI_SING_RCLK_FORIO3", - "IOI_SING_TBYTEIN", - "IOI_SW2A0_0", - "IOI_SW2A1_0", - "IOI_SW2A2_0", - "IOI_SW2A3_0", - "IOI_SW4A0_0", - "IOI_SW4A1_0", - "IOI_SW4A2_0", - "IOI_SW4A3_0", - "IOI_SW4END0_0", - "IOI_SW4END1_0", - "IOI_SW4END2_0", - "IOI_SW4END3_0", - "IOI_WL1END0_0", - "IOI_WL1END1_0", - "IOI_WL1END2_0", - "IOI_WL1END3_0", - "IOI_WR1END0_0", - "IOI_WR1END1_0", - "IOI_WR1END2_0", - "IOI_WR1END3_0", - "IOI_WW2A0_0", - "IOI_WW2A1_0", - "IOI_WW2A2_0", - "IOI_WW2A3_0", - "IOI_WW2END0_0", - "IOI_WW2END1_0", - "IOI_WW2END2_0", - "IOI_WW2END3_0", - "IOI_WW4A0_0", - "IOI_WW4A1_0", - "IOI_WW4A2_0", - "IOI_WW4A3_0", - "IOI_WW4B0_0", - "IOI_WW4B1_0", - "IOI_WW4B2_0", - "IOI_WW4B3_0", - "IOI_WW4C0_0", - "IOI_WW4C1_0", - "IOI_WW4C2_0", - "IOI_WW4C3_0", - "IOI_WW4END0_0", - "IOI_WW4END1_0", - "IOI_WW4END2_0", - "IOI_WW4END3_0", - "RIOI3_IDELAY0_IFDLY0", - "RIOI3_IDELAY0_IFDLY1", - "RIOI3_IDELAY0_IFDLY2", - "RIOI_DCI_T_TERM0", - "RIOI_I0", - "RIOI_IBUF0", - "RIOI_IBUF_DISABLE0", - "RIOI_IDELAY0_DATAOUT", - "RIOI_IDELAY0_IDATAIN", - "RIOI_ILOGIC0_D", - "RIOI_ILOGIC0_DDLY", - "RIOI_ILOGIC0_OFB", - "RIOI_ILOGIC0_TFB", - "RIOI_ISIN10", - "RIOI_ISIN20", - "RIOI_ISOUT10", - "RIOI_ISOUT20", - "RIOI_KEEPER_INT_EN_1", - "RIOI_O0", - "RIOI_ODELAY0_DATAOUT", - "RIOI_ODELAY0_ODATAIN", - "RIOI_ODELAY0_OFDLY0", - "RIOI_ODELAY0_OFDLY1", - "RIOI_ODELAY0_OFDLY2", - "RIOI_OLOGIC0_CLKDIVF", - "RIOI_OLOGIC0_OFB", - "RIOI_OLOGIC0_OQ", - "RIOI_OLOGIC0_TFB", - "RIOI_OLOGIC0_TFB_LOCAL", - "RIOI_OLOGIC0_TQ", - "RIOI_OSIN10", - "RIOI_OSIN20", - "RIOI_OSOUT10", - "RIOI_OSOUT20", - "RIOI_PD_INT_EN_1", - "RIOI_PU_INT_EN_1", - "RIOI_T0" - ] + "wires": { + "IOI_BLOCK_OUTS0_0": null, + "IOI_BLOCK_OUTS1_0": null, + "IOI_BLOCK_OUTS2_0": null, + "IOI_BLOCK_OUTS3_0": null, + "IOI_BYP0_0": null, + "IOI_BYP1_0": null, + "IOI_BYP2_0": null, + "IOI_BYP3_0": null, + "IOI_BYP4_0": null, + "IOI_BYP5_0": null, + "IOI_BYP6_0": null, + "IOI_BYP7_0": null, + "IOI_CLK0_0": null, + "IOI_CLK1_0": null, + "IOI_CTRL0_0": null, + "IOI_CTRL1_0": null, + "IOI_EE2A0_0": null, + "IOI_EE2A1_0": null, + "IOI_EE2A2_0": null, + "IOI_EE2A3_0": null, + "IOI_EE2BEG0_0": null, + "IOI_EE2BEG1_0": null, + "IOI_EE2BEG2_0": null, + "IOI_EE2BEG3_0": null, + "IOI_EE4A0_0": null, + "IOI_EE4A1_0": null, + "IOI_EE4A2_0": null, + "IOI_EE4A3_0": null, + "IOI_EE4B0_0": null, + "IOI_EE4B1_0": null, + "IOI_EE4B2_0": null, + "IOI_EE4B3_0": null, + "IOI_EE4BEG0_0": null, + "IOI_EE4BEG1_0": null, + "IOI_EE4BEG2_0": null, + "IOI_EE4BEG3_0": null, + "IOI_EE4C0_0": null, + "IOI_EE4C1_0": null, + "IOI_EE4C2_0": null, + "IOI_EE4C3_0": null, + "IOI_EL1BEG0_0": null, + "IOI_EL1BEG1_0": null, + "IOI_EL1BEG2_0": null, + "IOI_EL1BEG3_0": null, + "IOI_ER1BEG0_0": null, + "IOI_ER1BEG1_0": null, + "IOI_ER1BEG2_0": null, + "IOI_ER1BEG3_0": null, + "IOI_FAN0_0": null, + "IOI_FAN1_0": null, + "IOI_FAN2_0": null, + "IOI_FAN3_0": null, + "IOI_FAN4_0": null, + "IOI_FAN5_0": null, + "IOI_FAN6_0": null, + "IOI_FAN7_0": null, + "IOI_IDELAY0_C": null, + "IOI_IDELAY0_CE": null, + "IOI_IDELAY0_CINVCTRL": null, + "IOI_IDELAY0_CNTVALUEIN0": null, + "IOI_IDELAY0_CNTVALUEIN1": null, + "IOI_IDELAY0_CNTVALUEIN2": null, + "IOI_IDELAY0_CNTVALUEIN3": null, + "IOI_IDELAY0_CNTVALUEIN4": null, + "IOI_IDELAY0_CNTVALUEOUT0": null, + "IOI_IDELAY0_CNTVALUEOUT1": null, + "IOI_IDELAY0_CNTVALUEOUT2": null, + "IOI_IDELAY0_CNTVALUEOUT3": null, + "IOI_IDELAY0_CNTVALUEOUT4": null, + "IOI_IDELAY0_DATAIN": null, + "IOI_IDELAY0_INC": null, + "IOI_IDELAY0_LD": null, + "IOI_IDELAY0_LDPIPEEN": null, + "IOI_IDELAY0_REGRST": null, + "IOI_ILOGIC0_BITSLIP": null, + "IOI_ILOGIC0_CE1": null, + "IOI_ILOGIC0_CE2": null, + "IOI_ILOGIC0_CLK": null, + "IOI_ILOGIC0_CLKB": null, + "IOI_ILOGIC0_CLKDIV": null, + "IOI_ILOGIC0_CLKDIVP": null, + "IOI_ILOGIC0_DYNCLKDIVPSEL": null, + "IOI_ILOGIC0_DYNCLKDIVSEL": null, + "IOI_ILOGIC0_DYNCLKSEL": null, + "IOI_ILOGIC0_O": null, + "IOI_ILOGIC0_OCLK": null, + "IOI_ILOGIC0_OCLKB": null, + "IOI_ILOGIC0_Q1": null, + "IOI_ILOGIC0_Q2": null, + "IOI_ILOGIC0_Q3": null, + "IOI_ILOGIC0_Q4": null, + "IOI_ILOGIC0_Q5": null, + "IOI_ILOGIC0_Q6": null, + "IOI_ILOGIC0_Q7": null, + "IOI_ILOGIC0_Q8": null, + "IOI_ILOGIC0_REV": null, + "IOI_ILOGIC0_SR": null, + "IOI_IMUX0_0": null, + "IOI_IMUX10_0": null, + "IOI_IMUX11_0": null, + "IOI_IMUX12_0": null, + "IOI_IMUX13_0": null, + "IOI_IMUX14_0": null, + "IOI_IMUX15_0": null, + "IOI_IMUX16_0": null, + "IOI_IMUX17_0": null, + "IOI_IMUX18_0": null, + "IOI_IMUX19_0": null, + "IOI_IMUX1_0": null, + "IOI_IMUX20_0": null, + "IOI_IMUX21_0": null, + "IOI_IMUX22_0": null, + "IOI_IMUX23_0": null, + "IOI_IMUX24_0": null, + "IOI_IMUX25_0": null, + "IOI_IMUX26_0": null, + "IOI_IMUX27_0": null, + "IOI_IMUX28_0": null, + "IOI_IMUX29_0": null, + "IOI_IMUX2_0": null, + "IOI_IMUX30_0": null, + "IOI_IMUX31_0": null, + "IOI_IMUX32_0": null, + "IOI_IMUX33_0": null, + "IOI_IMUX34_0": null, + "IOI_IMUX35_0": null, + "IOI_IMUX36_0": null, + "IOI_IMUX37_0": null, + "IOI_IMUX38_0": null, + "IOI_IMUX39_0": null, + "IOI_IMUX3_0": null, + "IOI_IMUX40_0": null, + "IOI_IMUX41_0": null, + "IOI_IMUX42_0": null, + "IOI_IMUX43_0": null, + "IOI_IMUX44_0": null, + "IOI_IMUX45_0": null, + "IOI_IMUX46_0": null, + "IOI_IMUX47_0": null, + "IOI_IMUX4_0": null, + "IOI_IMUX5_0": null, + "IOI_IMUX6_0": null, + "IOI_IMUX7_0": null, + "IOI_IMUX8_0": null, + "IOI_IMUX9_0": null, + "IOI_LH10_0": null, + "IOI_LH11_0": null, + "IOI_LH12_0": null, + "IOI_LH1_0": null, + "IOI_LH2_0": null, + "IOI_LH3_0": null, + "IOI_LH4_0": null, + "IOI_LH5_0": null, + "IOI_LH6_0": null, + "IOI_LH7_0": null, + "IOI_LH8_0": null, + "IOI_LH9_0": null, + "IOI_LOGIC_OUTS0_0": null, + "IOI_LOGIC_OUTS10_0": null, + "IOI_LOGIC_OUTS11_0": null, + "IOI_LOGIC_OUTS12_0": null, + "IOI_LOGIC_OUTS13_0": null, + "IOI_LOGIC_OUTS14_0": null, + "IOI_LOGIC_OUTS15_0": null, + "IOI_LOGIC_OUTS16_0": null, + "IOI_LOGIC_OUTS17_0": null, + "IOI_LOGIC_OUTS18_0": null, + "IOI_LOGIC_OUTS19_0": null, + "IOI_LOGIC_OUTS1_0": null, + "IOI_LOGIC_OUTS20_0": null, + "IOI_LOGIC_OUTS21_0": null, + "IOI_LOGIC_OUTS22_0": null, + "IOI_LOGIC_OUTS23_0": null, + "IOI_LOGIC_OUTS2_0": null, + "IOI_LOGIC_OUTS3_0": null, + "IOI_LOGIC_OUTS4_0": null, + "IOI_LOGIC_OUTS5_0": null, + "IOI_LOGIC_OUTS6_0": null, + "IOI_LOGIC_OUTS7_0": null, + "IOI_LOGIC_OUTS8_0": null, + "IOI_LOGIC_OUTS9_0": null, + "IOI_NE2A0_0": null, + "IOI_NE2A1_0": null, + "IOI_NE2A2_0": null, + "IOI_NE2A3_0": null, + "IOI_NE4BEG0_0": null, + "IOI_NE4BEG1_0": null, + "IOI_NE4BEG2_0": null, + "IOI_NE4BEG3_0": null, + "IOI_NE4C0_0": null, + "IOI_NE4C1_0": null, + "IOI_NE4C2_0": null, + "IOI_NE4C3_0": null, + "IOI_NW2A0_0": null, + "IOI_NW2A1_0": null, + "IOI_NW2A2_0": null, + "IOI_NW2A3_0": null, + "IOI_NW4A0_0": null, + "IOI_NW4A1_0": null, + "IOI_NW4A2_0": null, + "IOI_NW4A3_0": null, + "IOI_NW4END0_0": null, + "IOI_NW4END1_0": null, + "IOI_NW4END2_0": null, + "IOI_NW4END3_0": null, + "IOI_OCLKM_0": null, + "IOI_OCLK_0": null, + "IOI_ODELAY0_C": null, + "IOI_ODELAY0_CE": null, + "IOI_ODELAY0_CINVCTRL": null, + "IOI_ODELAY0_CLKIN": null, + "IOI_ODELAY0_CNTVALUEIN0": null, + "IOI_ODELAY0_CNTVALUEIN1": null, + "IOI_ODELAY0_CNTVALUEIN2": null, + "IOI_ODELAY0_CNTVALUEIN3": null, + "IOI_ODELAY0_CNTVALUEIN4": null, + "IOI_ODELAY0_CNTVALUEOUT0": null, + "IOI_ODELAY0_CNTVALUEOUT1": null, + "IOI_ODELAY0_CNTVALUEOUT2": null, + "IOI_ODELAY0_CNTVALUEOUT3": null, + "IOI_ODELAY0_CNTVALUEOUT4": null, + "IOI_ODELAY0_INC": null, + "IOI_ODELAY0_LD": null, + "IOI_ODELAY0_LDPIPEEN": null, + "IOI_ODELAY0_REGRST": null, + "IOI_OLOGIC0_CLK": null, + "IOI_OLOGIC0_CLKB": null, + "IOI_OLOGIC0_CLKDIV": null, + "IOI_OLOGIC0_CLKDIVB": null, + "IOI_OLOGIC0_CLKDIVFB": null, + "IOI_OLOGIC0_D1": null, + "IOI_OLOGIC0_D2": null, + "IOI_OLOGIC0_D3": null, + "IOI_OLOGIC0_D4": null, + "IOI_OLOGIC0_D5": null, + "IOI_OLOGIC0_D6": null, + "IOI_OLOGIC0_D7": null, + "IOI_OLOGIC0_D8": null, + "IOI_OLOGIC0_IOCLKGLITCH": null, + "IOI_OLOGIC0_OCE": null, + "IOI_OLOGIC0_REV": null, + "IOI_OLOGIC0_SR": null, + "IOI_OLOGIC0_T1": null, + "IOI_OLOGIC0_T2": null, + "IOI_OLOGIC0_T3": null, + "IOI_OLOGIC0_T4": null, + "IOI_OLOGIC0_TBYTEIN": null, + "IOI_OLOGIC0_TBYTEOUT": null, + "IOI_OLOGIC0_TCE": null, + "IOI_PHASER_TO_IO_ICLK": null, + "IOI_PHASER_TO_IO_ICLKDIV": null, + "IOI_PHASER_TO_IO_OCLK": null, + "IOI_PHASER_TO_IO_OCLK1X_90": null, + "IOI_PHASER_TO_IO_OCLKDIV": null, + "IOI_SE2A0_0": null, + "IOI_SE2A1_0": null, + "IOI_SE2A2_0": null, + "IOI_SE2A3_0": null, + "IOI_SE4BEG0_0": null, + "IOI_SE4BEG1_0": null, + "IOI_SE4BEG2_0": null, + "IOI_SE4BEG3_0": null, + "IOI_SE4C0_0": null, + "IOI_SE4C1_0": null, + "IOI_SE4C2_0": null, + "IOI_SE4C3_0": null, + "IOI_SING_IOCLK0": null, + "IOI_SING_IOCLK1": null, + "IOI_SING_IOCLK2": null, + "IOI_SING_IOCLK3": null, + "IOI_SING_LEAF_GCLK0": null, + "IOI_SING_LEAF_GCLK1": null, + "IOI_SING_LEAF_GCLK2": null, + "IOI_SING_LEAF_GCLK3": null, + "IOI_SING_LEAF_GCLK4": null, + "IOI_SING_LEAF_GCLK5": null, + "IOI_SING_RCLK_FORIO0": null, + "IOI_SING_RCLK_FORIO1": null, + "IOI_SING_RCLK_FORIO2": null, + "IOI_SING_RCLK_FORIO3": null, + "IOI_SING_TBYTEIN": null, + "IOI_SW2A0_0": null, + "IOI_SW2A1_0": null, + "IOI_SW2A2_0": null, + "IOI_SW2A3_0": null, + "IOI_SW4A0_0": null, + "IOI_SW4A1_0": null, + "IOI_SW4A2_0": null, + "IOI_SW4A3_0": null, + "IOI_SW4END0_0": null, + "IOI_SW4END1_0": null, + "IOI_SW4END2_0": null, + "IOI_SW4END3_0": null, + "IOI_WL1END0_0": null, + "IOI_WL1END1_0": null, + "IOI_WL1END2_0": null, + "IOI_WL1END3_0": null, + "IOI_WR1END0_0": null, + "IOI_WR1END1_0": null, + "IOI_WR1END2_0": null, + "IOI_WR1END3_0": null, + "IOI_WW2A0_0": null, + "IOI_WW2A1_0": null, + "IOI_WW2A2_0": null, + "IOI_WW2A3_0": null, + "IOI_WW2END0_0": null, + "IOI_WW2END1_0": null, + "IOI_WW2END2_0": null, + "IOI_WW2END3_0": null, + "IOI_WW4A0_0": null, + "IOI_WW4A1_0": null, + "IOI_WW4A2_0": null, + "IOI_WW4A3_0": null, + "IOI_WW4B0_0": null, + "IOI_WW4B1_0": null, + "IOI_WW4B2_0": null, + "IOI_WW4B3_0": null, + "IOI_WW4C0_0": null, + "IOI_WW4C1_0": null, + "IOI_WW4C2_0": null, + "IOI_WW4C3_0": null, + "IOI_WW4END0_0": null, + "IOI_WW4END1_0": null, + "IOI_WW4END2_0": null, + "IOI_WW4END3_0": null, + "RIOI3_IDELAY0_IFDLY0": null, + "RIOI3_IDELAY0_IFDLY1": null, + "RIOI3_IDELAY0_IFDLY2": null, + "RIOI_DCI_T_TERM0": null, + "RIOI_I0": null, + "RIOI_IBUF0": null, + "RIOI_IBUF_DISABLE0": null, + "RIOI_IDELAY0_DATAOUT": null, + "RIOI_IDELAY0_IDATAIN": null, + "RIOI_ILOGIC0_D": null, + "RIOI_ILOGIC0_DDLY": null, + "RIOI_ILOGIC0_OFB": null, + "RIOI_ILOGIC0_TFB": null, + "RIOI_ISIN10": null, + "RIOI_ISIN20": null, + "RIOI_ISOUT10": null, + "RIOI_ISOUT20": null, + "RIOI_KEEPER_INT_EN_1": null, + "RIOI_O0": null, + "RIOI_ODELAY0_DATAOUT": null, + "RIOI_ODELAY0_ODATAIN": null, + "RIOI_ODELAY0_OFDLY0": null, + "RIOI_ODELAY0_OFDLY1": null, + "RIOI_ODELAY0_OFDLY2": null, + "RIOI_OLOGIC0_CLKDIVF": null, + "RIOI_OLOGIC0_OFB": null, + "RIOI_OLOGIC0_OQ": null, + "RIOI_OLOGIC0_TFB": null, + "RIOI_OLOGIC0_TFB_LOCAL": null, + "RIOI_OLOGIC0_TQ": null, + "RIOI_OSIN10": null, + "RIOI_OSIN20": null, + "RIOI_OSOUT10": null, + "RIOI_OSOUT20": null, + "RIOI_PD_INT_EN_1": null, + "RIOI_PU_INT_EN_1": null, + "RIOI_T0": null + } } diff --git a/zynq7/tile_type_RIOI3_TBYTESRC.json b/zynq7/tile_type_RIOI3_TBYTESRC.json index 08ca72e..a88299f 100644 --- a/zynq7/tile_type_RIOI3_TBYTESRC.json +++ b/zynq7/tile_type_RIOI3_TBYTESRC.json @@ -2,2914 +2,10080 @@ "pips": { "RIOI3_TBYTESRC.IOI_BYP3_0->IOI_IMUX_RC0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI3_TBYTESRC.IOI_BYP3_1->IOI_IMUX_RC3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI3_TBYTESRC.IOI_BYP4_0->IOI_IMUX_RC1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI3_TBYTESRC.IOI_BYP4_1->IOI_IMUX_RC2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI3_TBYTESRC.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_0" }, "RIOI3_TBYTESRC.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_1" }, "RIOI3_TBYTESRC.IOI_BYP7_0->RIOI3_IDELAY1_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY1_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_0" }, "RIOI3_TBYTESRC.IOI_BYP7_1->RIOI3_IDELAY0_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY0_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_1" }, "RIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "RIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "RIOI3_TBYTESRC.IOI_CLK1_0->IOI_IDELAY1_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "RIOI3_TBYTESRC.IOI_CLK1_1->IOI_IDELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_1" }, "RIOI3_TBYTESRC.IOI_CTRL0_0->IOI_OLOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_0" }, "RIOI3_TBYTESRC.IOI_CTRL0_1->IOI_OLOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_1" }, "RIOI3_TBYTESRC.IOI_CTRL1_0->IOI_ILOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_0" }, "RIOI3_TBYTESRC.IOI_CTRL1_1->IOI_ILOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_1" }, "RIOI3_TBYTESRC.IOI_FAN4_0->RIOI3_IDELAY1_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY1_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_0" }, "RIOI3_TBYTESRC.IOI_FAN4_1->RIOI3_IDELAY0_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY0_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_1" }, "RIOI3_TBYTESRC.IOI_FAN5_0->RIOI3_IDELAY1_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY1_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_0" }, "RIOI3_TBYTESRC.IOI_FAN5_1->RIOI3_IDELAY0_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY0_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_1" }, "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "RIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT0" }, "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT1" }, "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT2" }, "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT3" }, "RIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT4" }, "RIOI3_TBYTESRC.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC0_O" }, "RIOI3_TBYTESRC.IOI_ILOGIC0_O->RIOI_I2GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_I2GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_O" }, "RIOI3_TBYTESRC.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q1" }, "RIOI3_TBYTESRC.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q2" }, "RIOI3_TBYTESRC.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q3" }, "RIOI3_TBYTESRC.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q4" }, "RIOI3_TBYTESRC.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q5" }, "RIOI3_TBYTESRC.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q6" }, "RIOI3_TBYTESRC.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q7" }, "RIOI3_TBYTESRC.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q8" }, "RIOI3_TBYTESRC.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC1_O" }, "RIOI3_TBYTESRC.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q1" }, "RIOI3_TBYTESRC.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q2" }, "RIOI3_TBYTESRC.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q3" }, "RIOI3_TBYTESRC.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q4" }, "RIOI3_TBYTESRC.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q5" }, "RIOI3_TBYTESRC.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q6" }, "RIOI3_TBYTESRC.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q7" }, "RIOI3_TBYTESRC.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q8" }, "RIOI3_TBYTESRC.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_0" }, "RIOI3_TBYTESRC.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_1" }, "RIOI3_TBYTESRC.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_0" }, "RIOI3_TBYTESRC.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_1" }, "RIOI3_TBYTESRC.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_0" }, "RIOI3_TBYTESRC.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_1" }, "RIOI3_TBYTESRC.IOI_IMUX13_0->IOI_OLOGIC1_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_0" }, "RIOI3_TBYTESRC.IOI_IMUX13_1->IOI_OLOGIC0_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_1" }, "RIOI3_TBYTESRC.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_0" }, "RIOI3_TBYTESRC.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_1" }, "RIOI3_TBYTESRC.IOI_IMUX15_0->IOI_OLOGIC1_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_0" }, "RIOI3_TBYTESRC.IOI_IMUX15_1->IOI_OLOGIC0_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_1" }, "RIOI3_TBYTESRC.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_0" }, "RIOI3_TBYTESRC.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_1" }, "RIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "RIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "RIOI3_TBYTESRC.IOI_IMUX21_0->IOI_OLOGIC1_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_0" }, "RIOI3_TBYTESRC.IOI_IMUX21_1->IOI_OLOGIC0_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_1" }, "RIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "RIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "RIOI3_TBYTESRC.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_0" }, "RIOI3_TBYTESRC.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_1" }, "RIOI3_TBYTESRC.IOI_IMUX26_0->IOI_IDELAY1_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_0" }, "RIOI3_TBYTESRC.IOI_IMUX26_1->IOI_IDELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_1" }, "RIOI3_TBYTESRC.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_0" }, "RIOI3_TBYTESRC.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_1" }, "RIOI3_TBYTESRC.IOI_IMUX30_0->IOI_IDELAY1_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_0" }, "RIOI3_TBYTESRC.IOI_IMUX30_1->IOI_IDELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_1" }, "RIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "RIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "RIOI3_TBYTESRC.IOI_IMUX32_0->IOI_IDELAY1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_0" }, "RIOI3_TBYTESRC.IOI_IMUX32_1->IOI_IDELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_1" }, "RIOI3_TBYTESRC.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_0" }, "RIOI3_TBYTESRC.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_1" }, "RIOI3_TBYTESRC.IOI_IMUX34_0->IOI_OLOGIC1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_0" }, "RIOI3_TBYTESRC.IOI_IMUX34_1->IOI_OLOGIC0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_1" }, "RIOI3_TBYTESRC.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_0" }, "RIOI3_TBYTESRC.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_1" }, "RIOI3_TBYTESRC.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_0" }, "RIOI3_TBYTESRC.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_1" }, "RIOI3_TBYTESRC.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_0" }, "RIOI3_TBYTESRC.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_1" }, "RIOI3_TBYTESRC.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_0" }, "RIOI3_TBYTESRC.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_1" }, "RIOI3_TBYTESRC.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_0" }, "RIOI3_TBYTESRC.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_1" }, "RIOI3_TBYTESRC.IOI_IMUX40_0->IOI_OLOGIC1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_0" }, "RIOI3_TBYTESRC.IOI_IMUX40_1->IOI_OLOGIC0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_1" }, "RIOI3_TBYTESRC.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_0" }, "RIOI3_TBYTESRC.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_1" }, "RIOI3_TBYTESRC.IOI_IMUX42_0->IOI_OLOGIC1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_0" }, "RIOI3_TBYTESRC.IOI_IMUX42_1->IOI_OLOGIC0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_1" }, "RIOI3_TBYTESRC.IOI_IMUX43_0->IOI_OLOGIC1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_0" }, "RIOI3_TBYTESRC.IOI_IMUX43_1->IOI_OLOGIC0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_1" }, "RIOI3_TBYTESRC.IOI_IMUX44_0->IOI_OLOGIC1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_0" }, "RIOI3_TBYTESRC.IOI_IMUX44_1->IOI_OLOGIC0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_1" }, "RIOI3_TBYTESRC.IOI_IMUX45_0->IOI_OLOGIC1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_0" }, "RIOI3_TBYTESRC.IOI_IMUX45_1->IOI_OLOGIC0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_1" }, "RIOI3_TBYTESRC.IOI_IMUX46_0->IOI_OLOGIC1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_0" }, "RIOI3_TBYTESRC.IOI_IMUX46_1->IOI_OLOGIC0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_1" }, "RIOI3_TBYTESRC.IOI_IMUX47_0->IOI_OLOGIC1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_0" }, "RIOI3_TBYTESRC.IOI_IMUX47_1->IOI_OLOGIC0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_1" }, "RIOI3_TBYTESRC.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_0" }, "RIOI3_TBYTESRC.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_1" }, "RIOI3_TBYTESRC.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_0" }, "RIOI3_TBYTESRC.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_1" }, "RIOI3_TBYTESRC.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_0" }, "RIOI3_TBYTESRC.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_1" }, "RIOI3_TBYTESRC.IOI_IMUX7_0->IOI_OLOGIC1_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_0" }, "RIOI3_TBYTESRC.IOI_IMUX7_1->IOI_OLOGIC0_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_1" }, "RIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3_TBYTESRC.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI3_TBYTESRC.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI3_TBYTESRC.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_0" }, "RIOI3_TBYTESRC.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_1" }, "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { 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"delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, 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+ "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, 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"src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + 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"src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTESRC.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTESRC.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI3_TBYTESRC.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI3_TBYTESRC.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "RIOI3_TBYTESRC.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "RIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI3_TBYTESRC.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI3_TBYTESRC.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI3_TBYTESRC.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC0_IOCLKGLITCH" }, "RIOI3_TBYTESRC.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI3_TBYTESRC.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI3_TBYTESRC.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "RIOI3_TBYTESRC.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "RIOI3_TBYTESRC.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC1_IOCLKGLITCH" }, "RIOI3_TBYTESRC.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "RIOI3_TBYTESRC.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "RIOI3_TBYTESRC.IOI_OLOGIC1_TBYTEOUT->>IOI_TBYTEIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "IOI_TBYTEIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "IOI_OLOGIC1_TBYTEOUT" }, "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV" }, "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0" }, "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK_0" }, "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK_0" }, "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": 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}, "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "RIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + 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"in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IDATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_I0" }, "RIOI3_TBYTESRC.RIOI_I0->RIOI_ILOGIC0_D": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_D", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_I0" }, "RIOI3_TBYTESRC.RIOI_I1->RIOI_IDELAY1_IDATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY1_IDATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_I1" }, "RIOI3_TBYTESRC.RIOI_I1->RIOI_ILOGIC1_D": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_D", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_I1" }, "RIOI3_TBYTESRC.RIOI_IBUF0->RIOI_I0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_I0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_IBUF0" }, "RIOI3_TBYTESRC.RIOI_IBUF1->RIOI_I1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_I1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_IBUF1" }, "RIOI3_TBYTESRC.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_DDLY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_IDELAY0_DATAOUT" }, "RIOI3_TBYTESRC.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.243", + "0.305", + "0.755", + "0.815" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_IDELAY0_DATAOUT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.243", + "0.305", + "0.755", + "0.815" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_IDELAY0_IDATAIN" }, "RIOI3_TBYTESRC.RIOI_IDELAY1_DATAOUT->RIOI_ILOGIC1_DDLY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_DDLY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_IDELAY1_DATAOUT" }, "RIOI3_TBYTESRC.RIOI_IDELAY1_IDATAIN->>RIOI_IDELAY1_DATAOUT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.243", + "0.305", + "0.755", + "0.815" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_IDELAY1_DATAOUT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.243", + "0.305", + "0.755", + "0.815" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_IDELAY1_IDATAIN" }, "RIOI3_TBYTESRC.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.054", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.054", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC0_D" }, "RIOI3_TBYTESRC.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.055", + "0.120", + "0.138" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.055", + "0.120", + "0.138" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC0_DDLY" }, "RIOI3_TBYTESRC.RIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.054", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.054", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC1_D" }, "RIOI3_TBYTESRC.RIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.055", + "0.120", + "0.138" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.055", + "0.120", + "0.138" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC1_DDLY" }, "RIOI3_TBYTESRC.RIOI_ISOUT10->RIOI_ISIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ISIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_ISOUT10" }, "RIOI3_TBYTESRC.RIOI_ISOUT20->RIOI_ISIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ISIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_ISOUT20" }, "RIOI3_TBYTESRC.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_OFB" }, "RIOI3_TBYTESRC.RIOI_OLOGIC0_OQ->>RIOI_O0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_O0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_OQ" }, "RIOI3_TBYTESRC.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_OQ" }, "RIOI3_TBYTESRC.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB" }, "RIOI3_TBYTESRC.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI3_TBYTESRC.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI3_TBYTESRC.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" }, "RIOI3_TBYTESRC.RIOI_OLOGIC0_TQ->>RIOI_T0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_T0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" }, "RIOI3_TBYTESRC.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_OFB" }, "RIOI3_TBYTESRC.RIOI_OLOGIC1_OQ->>RIOI_O1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_O1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_OQ" }, "RIOI3_TBYTESRC.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_OQ" }, "RIOI3_TBYTESRC.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB" }, "RIOI3_TBYTESRC.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB_LOCAL" }, "RIOI3_TBYTESRC.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB_LOCAL" }, "RIOI3_TBYTESRC.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_TQ" }, "RIOI3_TBYTESRC.RIOI_OLOGIC1_TQ->>RIOI_T1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_T1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_TQ" }, "RIOI3_TBYTESRC.RIOI_OSOUT11->RIOI_OSIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OSIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OSOUT11" }, "RIOI3_TBYTESRC.RIOI_OSOUT21->RIOI_OSIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OSIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OSOUT21" } }, @@ -2918,39 +10084,309 @@ "name": "X0Y0", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC1_CLK", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "D1": "IOI_OLOGIC1_D1", - "D2": "IOI_OLOGIC1_D2", - "D3": "IOI_OLOGIC1_D3", - "D4": "IOI_OLOGIC1_D4", - "D5": "IOI_OLOGIC1_D5", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D8": "IOI_OLOGIC1_D8", - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "OCE": "IOI_OLOGIC1_OCE", - "OFB": "RIOI_OLOGIC1_OFB", - "OQ": "RIOI_OLOGIC1_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_OQ" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_OSOUT11", - "SHIFTOUT2": "RIOI_OSOUT21", - "SR": "IOI_OLOGIC1_SR", - "T1": "IOI_OLOGIC1_T1", - "T2": "IOI_OLOGIC1_T2", - "T3": "IOI_OLOGIC1_T3", - "T4": "IOI_OLOGIC1_T4", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "TCE": "IOI_OLOGIC1_TCE", - "TFB": "RIOI_OLOGIC1_TFB", - "TQ": "RIOI_OLOGIC1_TQ" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -2960,37 +10396,307 @@ "name": "X0Y0", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "CE1": "IOI_ILOGIC1_CE1", - "CE2": "IOI_ILOGIC1_CE2", - "CLK": "IOI_ILOGIC1_CLK", - "CLKB": "IOI_ILOGIC1_CLKB", - "CLKDIV": "IOI_ILOGIC1_CLKDIV", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "D": "RIOI_ILOGIC1_D", - "DDLY": "RIOI_ILOGIC1_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "O": "IOI_ILOGIC1_O", - "OCLK": "IOI_ILOGIC1_OCLK", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "OFB": "RIOI_ILOGIC1_OFB", - "Q1": "IOI_ILOGIC1_Q1", - "Q2": "IOI_ILOGIC1_Q2", - "Q3": "IOI_ILOGIC1_Q3", - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q6": "IOI_ILOGIC1_Q6", - "Q7": "IOI_ILOGIC1_Q7", - "Q8": "IOI_ILOGIC1_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC1_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q8" + }, "REV": null, - "SHIFTIN1": "RIOI_ISIN11", - "SHIFTIN2": "RIOI_ISIN21", - "SHIFTOUT1": "RIOI_ISOUT11", - "SHIFTOUT2": "RIOI_ISOUT21", - "SR": "IOI_ILOGIC1_SR", - "TFB": "RIOI_ILOGIC1_TFB" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ISIN11" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ISIN21" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -3000,39 +10706,327 @@ "name": "X0Y1", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC0_CLK", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "D1": "IOI_OLOGIC0_D1", - "D2": "IOI_OLOGIC0_D2", - "D3": "IOI_OLOGIC0_D3", - "D4": "IOI_OLOGIC0_D4", - "D5": "IOI_OLOGIC0_D5", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D8": "IOI_OLOGIC0_D8", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "OCE": "IOI_OLOGIC0_OCE", - "OFB": "RIOI_OLOGIC0_OFB", - "OQ": "RIOI_OLOGIC0_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OQ" + }, "REV": null, - "SHIFTIN1": "RIOI_OSIN10", - "SHIFTIN2": "RIOI_OSIN20", - "SHIFTOUT1": "RIOI_OSOUT10", - "SHIFTOUT2": "RIOI_OSOUT20", - "SR": "IOI_OLOGIC0_SR", - "T1": "IOI_OLOGIC0_T1", - "T2": "IOI_OLOGIC0_T2", - "T3": "IOI_OLOGIC0_T3", - "T4": "IOI_OLOGIC0_T4", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "TCE": "IOI_OLOGIC0_TCE", - "TFB": "RIOI_OLOGIC0_TFB", - "TQ": "RIOI_OLOGIC0_TQ" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OSIN10" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OSIN20" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -3042,37 +11036,289 @@ "name": "X0Y1", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "CE1": "IOI_ILOGIC0_CE1", - "CE2": "IOI_ILOGIC0_CE2", - "CLK": "IOI_ILOGIC0_CLK", - "CLKB": "IOI_ILOGIC0_CLKB", - "CLKDIV": "IOI_ILOGIC0_CLKDIV", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "D": "RIOI_ILOGIC0_D", - "DDLY": "RIOI_ILOGIC0_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "O": "IOI_ILOGIC0_O", - "OCLK": "IOI_ILOGIC0_OCLK", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "OFB": "RIOI_ILOGIC0_OFB", - "Q1": "IOI_ILOGIC0_Q1", - "Q2": "IOI_ILOGIC0_Q2", - "Q3": "IOI_ILOGIC0_Q3", - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q6": "IOI_ILOGIC0_Q6", - "Q7": "IOI_ILOGIC0_Q7", - "Q8": "IOI_ILOGIC0_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC0_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q8" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_ISOUT10", - "SHIFTOUT2": "RIOI_ISOUT20", - "SR": "IOI_ILOGIC0_SR", - "TFB": "RIOI_ILOGIC0_TFB" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -3082,29 +11328,236 @@ "name": "X0Y0", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY1_C", - "CE": "IOI_IDELAY1_CE", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY1_DATAIN", - "DATAOUT": "RIOI_IDELAY1_DATAOUT", - "IDATAIN": "RIOI_IDELAY1_IDATAIN", - "IFDLY0": "RIOI3_IDELAY1_IFDLY0", - "IFDLY1": "RIOI3_IDELAY1_IFDLY1", - "IFDLY2": "RIOI3_IDELAY1_IFDLY2", - "INC": "IOI_IDELAY1_INC", - "LD": "IOI_IDELAY1_LD", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "REGRST": "IOI_IDELAY1_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY1_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY1_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY1_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY1_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -3114,29 +11567,236 @@ "name": "X0Y1", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY0_C", - "CE": "IOI_IDELAY0_CE", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY0_DATAIN", - "DATAOUT": "RIOI_IDELAY0_DATAOUT", - "IDATAIN": "RIOI_IDELAY0_IDATAIN", - "IFDLY0": "RIOI3_IDELAY0_IFDLY0", - "IFDLY1": "RIOI3_IDELAY0_IFDLY1", - "IFDLY2": "RIOI3_IDELAY0_IFDLY2", - "INC": "IOI_IDELAY0_INC", - "LD": "IOI_IDELAY0_LD", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "REGRST": "IOI_IDELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY0_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY0_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY0_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY0_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -3144,750 +11804,750 @@ } ], "tile_type": "RIOI3_TBYTESRC", - "wires": [ - "IOI_BLOCK_OUTS0_0", - "IOI_BLOCK_OUTS0_1", - "IOI_BLOCK_OUTS1_0", - "IOI_BLOCK_OUTS1_1", - "IOI_BLOCK_OUTS2_0", - "IOI_BLOCK_OUTS2_1", - "IOI_BLOCK_OUTS3_0", - "IOI_BLOCK_OUTS3_1", - "IOI_BYP0_0", - "IOI_BYP0_1", - "IOI_BYP1_0", - "IOI_BYP1_1", - "IOI_BYP2_0", - "IOI_BYP2_1", - "IOI_BYP3_0", - "IOI_BYP3_1", - "IOI_BYP4_0", - "IOI_BYP4_1", - "IOI_BYP5_0", - "IOI_BYP5_1", - "IOI_BYP6_0", - "IOI_BYP6_1", - "IOI_BYP7_0", - "IOI_BYP7_1", - "IOI_CLK0_0", - "IOI_CLK0_1", - "IOI_CLK1_0", - "IOI_CLK1_1", - "IOI_CTRL0_0", - "IOI_CTRL0_1", - "IOI_CTRL1_0", - "IOI_CTRL1_1", - "IOI_DCI_DCIDONE", - "IOI_DCI_TSTCLK", - "IOI_DCI_TSTHLN", - "IOI_DCI_TSTHLP", - "IOI_DCI_TSTRST", - "IOI_DCI_TSTRST0", - "IOI_EE2A0_0", - "IOI_EE2A0_1", - "IOI_EE2A1_0", - "IOI_EE2A1_1", - "IOI_EE2A2_0", - "IOI_EE2A2_1", - "IOI_EE2A3_0", - "IOI_EE2A3_1", - "IOI_EE2BEG0_0", - "IOI_EE2BEG0_1", - "IOI_EE2BEG1_0", - "IOI_EE2BEG1_1", - "IOI_EE2BEG2_0", - "IOI_EE2BEG2_1", - "IOI_EE2BEG3_0", - "IOI_EE2BEG3_1", - "IOI_EE4A0_0", - "IOI_EE4A0_1", - "IOI_EE4A1_0", - "IOI_EE4A1_1", - "IOI_EE4A2_0", - "IOI_EE4A2_1", - "IOI_EE4A3_0", - "IOI_EE4A3_1", - "IOI_EE4B0_0", - "IOI_EE4B0_1", - "IOI_EE4B1_0", - "IOI_EE4B1_1", - "IOI_EE4B2_0", - "IOI_EE4B2_1", - "IOI_EE4B3_0", - "IOI_EE4B3_1", - "IOI_EE4BEG0_0", - "IOI_EE4BEG0_1", - "IOI_EE4BEG1_0", - "IOI_EE4BEG1_1", - "IOI_EE4BEG2_0", - "IOI_EE4BEG2_1", - "IOI_EE4BEG3_0", - "IOI_EE4BEG3_1", - "IOI_EE4C0_0", - "IOI_EE4C0_1", - "IOI_EE4C1_0", - "IOI_EE4C1_1", - "IOI_EE4C2_0", - "IOI_EE4C2_1", - "IOI_EE4C3_0", - "IOI_EE4C3_1", - "IOI_EL1BEG0_0", - "IOI_EL1BEG0_1", - "IOI_EL1BEG1_0", - "IOI_EL1BEG1_1", - "IOI_EL1BEG2_0", - "IOI_EL1BEG2_1", - "IOI_EL1BEG3_0", - "IOI_EL1BEG3_1", - "IOI_ER1BEG0_0", - "IOI_ER1BEG0_1", - "IOI_ER1BEG1_0", - "IOI_ER1BEG1_1", - "IOI_ER1BEG2_0", - "IOI_ER1BEG2_1", - "IOI_ER1BEG3_0", - "IOI_ER1BEG3_1", - "IOI_FAN0_0", - "IOI_FAN0_1", - "IOI_FAN1_0", - "IOI_FAN1_1", - "IOI_FAN2_0", - "IOI_FAN2_1", - "IOI_FAN3_0", - "IOI_FAN3_1", - "IOI_FAN4_0", - "IOI_FAN4_1", - "IOI_FAN5_0", - "IOI_FAN5_1", - "IOI_FAN6_0", - "IOI_FAN6_1", - "IOI_FAN7_0", - "IOI_FAN7_1", - "IOI_IDELAY0_C", - "IOI_IDELAY0_CE", - "IOI_IDELAY0_CINVCTRL", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_IDELAY0_DATAIN", - "IOI_IDELAY0_INC", - "IOI_IDELAY0_LD", - "IOI_IDELAY0_LDPIPEEN", - "IOI_IDELAY0_REGRST", - "IOI_IDELAY1_C", - "IOI_IDELAY1_CE", - "IOI_IDELAY1_CINVCTRL", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT0", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_IDELAY1_DATAIN", - "IOI_IDELAY1_INC", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_LDPIPEEN", - "IOI_IDELAY1_REGRST", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IDELAYCTRL_OUTN1", - "IOI_IDELAYCTRL_OUTN65", - "IOI_IDELAYCTRL_RDY", - "IOI_IDELAYCTRL_RST", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_ILOGIC0_BITSLIP", - "IOI_ILOGIC0_CE1", - "IOI_ILOGIC0_CE2", - "IOI_ILOGIC0_CLK", - "IOI_ILOGIC0_CLKB", - "IOI_ILOGIC0_CLKDIV", - "IOI_ILOGIC0_CLKDIVP", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_ILOGIC0_O", - "IOI_ILOGIC0_OCLK", - "IOI_ILOGIC0_OCLKB", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_Q2", - "IOI_ILOGIC0_Q3", - "IOI_ILOGIC0_Q4", - "IOI_ILOGIC0_Q5", - "IOI_ILOGIC0_Q6", - "IOI_ILOGIC0_Q7", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC0_REV", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC1_BITSLIP", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC1_CE2", - "IOI_ILOGIC1_CLK", - "IOI_ILOGIC1_CLKB", - "IOI_ILOGIC1_CLKDIV", - "IOI_ILOGIC1_CLKDIVP", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_ILOGIC1_O", - "IOI_ILOGIC1_OCLK", - "IOI_ILOGIC1_OCLKB", - "IOI_ILOGIC1_Q1", - "IOI_ILOGIC1_Q2", - "IOI_ILOGIC1_Q3", - "IOI_ILOGIC1_Q4", - "IOI_ILOGIC1_Q5", - "IOI_ILOGIC1_Q6", - "IOI_ILOGIC1_Q7", - "IOI_ILOGIC1_Q8", - "IOI_ILOGIC1_REV", - "IOI_ILOGIC1_SR", - "IOI_IMUX0_0", - "IOI_IMUX0_1", - "IOI_IMUX10_0", - "IOI_IMUX10_1", - "IOI_IMUX11_0", - "IOI_IMUX11_1", - "IOI_IMUX12_0", - "IOI_IMUX12_1", - "IOI_IMUX13_0", - "IOI_IMUX13_1", - "IOI_IMUX14_0", - "IOI_IMUX14_1", - "IOI_IMUX15_0", - "IOI_IMUX15_1", - "IOI_IMUX16_0", - "IOI_IMUX16_1", - "IOI_IMUX17_0", - "IOI_IMUX17_1", - "IOI_IMUX18_0", - "IOI_IMUX18_1", - "IOI_IMUX19_0", - "IOI_IMUX19_1", - "IOI_IMUX1_0", - "IOI_IMUX1_1", - "IOI_IMUX20_0", - "IOI_IMUX20_1", - "IOI_IMUX21_0", - "IOI_IMUX21_1", - "IOI_IMUX22_0", - "IOI_IMUX22_1", - "IOI_IMUX23_0", - "IOI_IMUX23_1", - "IOI_IMUX24_0", - "IOI_IMUX24_1", - "IOI_IMUX25_0", - "IOI_IMUX25_1", - "IOI_IMUX26_0", - "IOI_IMUX26_1", - "IOI_IMUX27_0", - "IOI_IMUX27_1", - "IOI_IMUX28_0", - "IOI_IMUX28_1", - "IOI_IMUX29_0", - "IOI_IMUX29_1", - "IOI_IMUX2_0", - "IOI_IMUX2_1", - "IOI_IMUX30_0", - "IOI_IMUX30_1", - "IOI_IMUX31_0", - "IOI_IMUX31_1", - "IOI_IMUX32_0", - "IOI_IMUX32_1", - "IOI_IMUX33_0", - "IOI_IMUX33_1", - "IOI_IMUX34_0", - "IOI_IMUX34_1", - "IOI_IMUX35_0", - "IOI_IMUX35_1", - "IOI_IMUX36_0", - "IOI_IMUX36_1", - "IOI_IMUX37_0", - "IOI_IMUX37_1", - "IOI_IMUX38_0", - "IOI_IMUX38_1", - "IOI_IMUX39_0", - "IOI_IMUX39_1", - "IOI_IMUX3_0", - "IOI_IMUX3_1", - "IOI_IMUX40_0", - "IOI_IMUX40_1", - "IOI_IMUX41_0", - "IOI_IMUX41_1", - "IOI_IMUX42_0", - "IOI_IMUX42_1", - "IOI_IMUX43_0", - "IOI_IMUX43_1", - "IOI_IMUX44_0", - "IOI_IMUX44_1", - "IOI_IMUX45_0", - "IOI_IMUX45_1", - "IOI_IMUX46_0", - "IOI_IMUX46_1", - "IOI_IMUX47_0", - "IOI_IMUX47_1", - "IOI_IMUX4_0", - "IOI_IMUX4_1", - "IOI_IMUX5_0", - "IOI_IMUX5_1", - "IOI_IMUX6_0", - "IOI_IMUX6_1", - "IOI_IMUX7_0", - "IOI_IMUX7_1", - "IOI_IMUX8_0", - "IOI_IMUX8_1", - "IOI_IMUX9_0", - "IOI_IMUX9_1", - "IOI_IMUX_RC0", - "IOI_IMUX_RC1", - "IOI_IMUX_RC2", - "IOI_IMUX_RC3", - "IOI_INT_DCI_EN", - "IOI_IOCLK0", - "IOI_IOCLK1", - "IOI_IOCLK2", - "IOI_IOCLK3", - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK5", - "IOI_LH10_0", - "IOI_LH10_1", - "IOI_LH11_0", - "IOI_LH11_1", - "IOI_LH12_0", - "IOI_LH12_1", - "IOI_LH1_0", - "IOI_LH1_1", - "IOI_LH2_0", - "IOI_LH2_1", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_LH4_0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_LH5_1", - "IOI_LH6_0", - "IOI_LH6_1", - "IOI_LH7_0", - "IOI_LH7_1", - "IOI_LH8_0", - "IOI_LH8_1", - "IOI_LH9_0", - "IOI_LH9_1", - "IOI_LOGIC_OUTS0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_LOGIC_OUTS10_0", - "IOI_LOGIC_OUTS10_1", - "IOI_LOGIC_OUTS11_0", - "IOI_LOGIC_OUTS11_1", - "IOI_LOGIC_OUTS12_0", - "IOI_LOGIC_OUTS12_1", - "IOI_LOGIC_OUTS13_0", - "IOI_LOGIC_OUTS13_1", - "IOI_LOGIC_OUTS14_0", - "IOI_LOGIC_OUTS14_1", - "IOI_LOGIC_OUTS15_0", - "IOI_LOGIC_OUTS15_1", - "IOI_LOGIC_OUTS16_0", - "IOI_LOGIC_OUTS16_1", - "IOI_LOGIC_OUTS17_0", - "IOI_LOGIC_OUTS17_1", - "IOI_LOGIC_OUTS18_0", - "IOI_LOGIC_OUTS18_1", - "IOI_LOGIC_OUTS19_0", - "IOI_LOGIC_OUTS19_1", - "IOI_LOGIC_OUTS1_0", - "IOI_LOGIC_OUTS1_1", - "IOI_LOGIC_OUTS20_0", - "IOI_LOGIC_OUTS20_1", - "IOI_LOGIC_OUTS21_0", - "IOI_LOGIC_OUTS21_1", - "IOI_LOGIC_OUTS22_0", - "IOI_LOGIC_OUTS22_1", - "IOI_LOGIC_OUTS23_0", - "IOI_LOGIC_OUTS23_1", - "IOI_LOGIC_OUTS2_0", - "IOI_LOGIC_OUTS2_1", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS3_1", - "IOI_LOGIC_OUTS4_0", - "IOI_LOGIC_OUTS4_1", - "IOI_LOGIC_OUTS5_0", - "IOI_LOGIC_OUTS5_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LOGIC_OUTS6_1", - "IOI_LOGIC_OUTS7_0", - "IOI_LOGIC_OUTS7_1", - "IOI_LOGIC_OUTS8_0", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS9_0", - "IOI_LOGIC_OUTS9_1", - "IOI_MONITOR_N", - "IOI_MONITOR_P", - "IOI_NE2A0_0", - "IOI_NE2A0_1", - "IOI_NE2A1_0", - "IOI_NE2A1_1", - "IOI_NE2A2_0", - "IOI_NE2A2_1", - "IOI_NE2A3_0", - "IOI_NE2A3_1", - "IOI_NE4BEG0_0", - "IOI_NE4BEG0_1", - "IOI_NE4BEG1_0", - "IOI_NE4BEG1_1", - "IOI_NE4BEG2_0", - "IOI_NE4BEG2_1", - "IOI_NE4BEG3_0", - "IOI_NE4BEG3_1", - "IOI_NE4C0_0", - "IOI_NE4C0_1", - "IOI_NE4C1_0", - "IOI_NE4C1_1", - "IOI_NE4C2_0", - "IOI_NE4C2_1", - "IOI_NE4C3_0", - "IOI_NE4C3_1", - "IOI_NW2A0_0", - "IOI_NW2A0_1", - "IOI_NW2A1_0", - "IOI_NW2A1_1", - "IOI_NW2A2_0", - "IOI_NW2A2_1", - "IOI_NW2A3_0", - "IOI_NW2A3_1", - "IOI_NW4A0_0", - "IOI_NW4A0_1", - "IOI_NW4A1_0", - "IOI_NW4A1_1", - "IOI_NW4A2_0", - "IOI_NW4A2_1", - "IOI_NW4A3_0", - "IOI_NW4A3_1", - "IOI_NW4END0_0", - "IOI_NW4END0_1", - "IOI_NW4END1_0", - "IOI_NW4END1_1", - "IOI_NW4END2_0", - "IOI_NW4END2_1", - "IOI_NW4END3_0", - "IOI_NW4END3_1", - "IOI_OCLKM_0", - "IOI_OCLKM_1", - "IOI_OCLK_0", - "IOI_OCLK_1", - "IOI_ODELAY0_C", - "IOI_ODELAY0_CE", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY0_CLKIN", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ODELAY0_INC", - "IOI_ODELAY0_LD", - "IOI_ODELAY0_LDPIPEEN", - "IOI_ODELAY0_REGRST", - "IOI_ODELAY1_C", - "IOI_ODELAY1_CE", - "IOI_ODELAY1_CINVCTRL", - "IOI_ODELAY1_CLKIN", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_ODELAY1_CNTVALUEIN1", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_ODELAY1_CNTVALUEOUT0", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_ODELAY1_CNTVALUEOUT2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_ODELAY1_INC", - "IOI_ODELAY1_LD", - "IOI_ODELAY1_LDPIPEEN", - "IOI_ODELAY1_REGRST", - "IOI_OLOGIC0_CLK", - "IOI_OLOGIC0_CLKB", - "IOI_OLOGIC0_CLKDIV", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_OLOGIC0_D1", - "IOI_OLOGIC0_D2", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_D4", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_D6", - "IOI_OLOGIC0_D7", - "IOI_OLOGIC0_D8", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_OCE", - "IOI_OLOGIC0_REV", - "IOI_OLOGIC0_SR", - "IOI_OLOGIC0_T1", - "IOI_OLOGIC0_T2", - "IOI_OLOGIC0_T3", - "IOI_OLOGIC0_T4", - "IOI_OLOGIC0_TBYTEIN", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_CLK", - "IOI_OLOGIC1_CLKB", - "IOI_OLOGIC1_CLKDIV", - "IOI_OLOGIC1_CLKDIVB", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_OLOGIC1_D1", - "IOI_OLOGIC1_D2", - "IOI_OLOGIC1_D3", - "IOI_OLOGIC1_D4", - "IOI_OLOGIC1_D5", - "IOI_OLOGIC1_D6", - "IOI_OLOGIC1_D7", - "IOI_OLOGIC1_D8", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_OLOGIC1_OCE", - "IOI_OLOGIC1_REV", - "IOI_OLOGIC1_SR", - "IOI_OLOGIC1_T1", - "IOI_OLOGIC1_T2", - "IOI_OLOGIC1_T3", - "IOI_OLOGIC1_T4", - "IOI_OLOGIC1_TBYTEIN", - "IOI_OLOGIC1_TBYTEOUT", - "IOI_OLOGIC1_TCE", - "IOI_PHASER_TO_IO_ICLK", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_PHASER_TO_IO_OCLK", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_PHASER_TO_IO_OCLK_0", - "IOI_RCLK_DIV_CE0", - "IOI_RCLK_DIV_CE1", - "IOI_RCLK_DIV_CE2", - "IOI_RCLK_DIV_CE2_1", - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1", - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1", - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_RCLK_DIV_CLR2", - "IOI_RCLK_DIV_CLR3", - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO3", - "IOI_SE2A0_0", - "IOI_SE2A0_1", - "IOI_SE2A1_0", - "IOI_SE2A1_1", - "IOI_SE2A2_0", - "IOI_SE2A2_1", - "IOI_SE2A3_0", - "IOI_SE2A3_1", - "IOI_SE4BEG0_0", - "IOI_SE4BEG0_1", - "IOI_SE4BEG1_0", - "IOI_SE4BEG1_1", - "IOI_SE4BEG2_0", - "IOI_SE4BEG2_1", - "IOI_SE4BEG3_0", - "IOI_SE4BEG3_1", - "IOI_SE4C0_0", - "IOI_SE4C0_1", - "IOI_SE4C1_0", - "IOI_SE4C1_1", - "IOI_SE4C2_0", - "IOI_SE4C2_1", - "IOI_SE4C3_0", - "IOI_SE4C3_1", - "IOI_SW2A0_0", - "IOI_SW2A0_1", - "IOI_SW2A1_0", - "IOI_SW2A1_1", - "IOI_SW2A2_0", - "IOI_SW2A2_1", - "IOI_SW2A3_0", - "IOI_SW2A3_1", - "IOI_SW4A0_0", - "IOI_SW4A0_1", - "IOI_SW4A1_0", - "IOI_SW4A1_1", - "IOI_SW4A2_0", - "IOI_SW4A2_1", - "IOI_SW4A3_0", - "IOI_SW4A3_1", - "IOI_SW4END0_0", - "IOI_SW4END0_1", - "IOI_SW4END1_0", - "IOI_SW4END1_1", - "IOI_SW4END2_0", - "IOI_SW4END2_1", - "IOI_SW4END3_0", - "IOI_SW4END3_1", - "IOI_TBYTEIN", - "IOI_WL1END0_0", - "IOI_WL1END0_1", - "IOI_WL1END1_0", - "IOI_WL1END1_1", - "IOI_WL1END2_0", - "IOI_WL1END2_1", - "IOI_WL1END3_0", - "IOI_WL1END3_1", - "IOI_WR1END0_0", - "IOI_WR1END0_1", - "IOI_WR1END1_0", - "IOI_WR1END1_1", - "IOI_WR1END2_0", - "IOI_WR1END2_1", - "IOI_WR1END3_0", - "IOI_WR1END3_1", - "IOI_WW2A0_0", - "IOI_WW2A0_1", - "IOI_WW2A1_0", - "IOI_WW2A1_1", - "IOI_WW2A2_0", - "IOI_WW2A2_1", - "IOI_WW2A3_0", - "IOI_WW2A3_1", - "IOI_WW2END0_0", - "IOI_WW2END0_1", - "IOI_WW2END1_0", - "IOI_WW2END1_1", - "IOI_WW2END2_0", - "IOI_WW2END2_1", - "IOI_WW2END3_0", - "IOI_WW2END3_1", - "IOI_WW4A0_0", - "IOI_WW4A0_1", - "IOI_WW4A1_0", - "IOI_WW4A1_1", - "IOI_WW4A2_0", - "IOI_WW4A2_1", - "IOI_WW4A3_0", - "IOI_WW4A3_1", - "IOI_WW4B0_0", - "IOI_WW4B0_1", - "IOI_WW4B1_0", - "IOI_WW4B1_1", - "IOI_WW4B2_0", - "IOI_WW4B2_1", - "IOI_WW4B3_0", - "IOI_WW4B3_1", - "IOI_WW4C0_0", - "IOI_WW4C0_1", - "IOI_WW4C1_0", - "IOI_WW4C1_1", - "IOI_WW4C2_0", - "IOI_WW4C2_1", - "IOI_WW4C3_0", - "IOI_WW4C3_1", - "IOI_WW4END0_0", - "IOI_WW4END0_1", - "IOI_WW4END1_0", - "IOI_WW4END1_1", - "IOI_WW4END2_0", - "IOI_WW4END2_1", - "IOI_WW4END3_0", - "IOI_WW4END3_1", - "RIOI3_IDELAY0_IFDLY0", - "RIOI3_IDELAY0_IFDLY1", - "RIOI3_IDELAY0_IFDLY2", - "RIOI3_IDELAY1_IFDLY0", - "RIOI3_IDELAY1_IFDLY1", - "RIOI3_IDELAY1_IFDLY2", - "RIOI_DCI_T_TERM0", - "RIOI_DCI_T_TERM1", - "RIOI_DIFF_TERM_INT_EN", - "RIOI_I0", - "RIOI_I1", - "RIOI_I2GCLK_BOT1", - "RIOI_I2GCLK_TOP0", - "RIOI_I2GCLK_TOP1", - "RIOI_IBUF0", - "RIOI_IBUF1", - "RIOI_IBUF_DISABLE0", - "RIOI_IBUF_DISABLE1", - "RIOI_IDELAY0_DATAOUT", - "RIOI_IDELAY0_IDATAIN", - "RIOI_IDELAY1_DATAOUT", - "RIOI_IDELAY1_IDATAIN", - "RIOI_ILOGIC0_D", - "RIOI_ILOGIC0_DDLY", - "RIOI_ILOGIC0_OFB", - "RIOI_ILOGIC0_TFB", - "RIOI_ILOGIC1_D", - "RIOI_ILOGIC1_DDLY", - "RIOI_ILOGIC1_OFB", - "RIOI_ILOGIC1_TFB", - "RIOI_ISIN10", - "RIOI_ISIN11", - "RIOI_ISIN20", - "RIOI_ISIN21", - "RIOI_ISOUT10", - "RIOI_ISOUT11", - "RIOI_ISOUT20", - "RIOI_ISOUT21", - "RIOI_KEEPER_INT_EN_0", - "RIOI_KEEPER_INT_EN_1", - "RIOI_O0", - "RIOI_O1", - "RIOI_ODELAY0_DATAOUT", - "RIOI_ODELAY0_ODATAIN", - "RIOI_ODELAY0_OFDLY0", - "RIOI_ODELAY0_OFDLY1", - "RIOI_ODELAY0_OFDLY2", - "RIOI_ODELAY1_DATAOUT", - "RIOI_ODELAY1_ODATAIN", - "RIOI_ODELAY1_OFDLY0", - "RIOI_ODELAY1_OFDLY1", - "RIOI_ODELAY1_OFDLY2", - "RIOI_OLOGIC0_CLKDIVF", - "RIOI_OLOGIC0_OFB", - "RIOI_OLOGIC0_OQ", - "RIOI_OLOGIC0_TFB", - "RIOI_OLOGIC0_TFB_LOCAL", - "RIOI_OLOGIC0_TQ", - "RIOI_OLOGIC1_CLKDIVF", - "RIOI_OLOGIC1_OFB", - "RIOI_OLOGIC1_OQ", - "RIOI_OLOGIC1_TFB", - "RIOI_OLOGIC1_TFB_LOCAL", - "RIOI_OLOGIC1_TQ", - "RIOI_OSIN10", - "RIOI_OSIN11", - "RIOI_OSIN20", - "RIOI_OSIN21", - "RIOI_OSOUT10", - "RIOI_OSOUT11", - "RIOI_OSOUT20", - "RIOI_OSOUT21", - "RIOI_PD_INT_EN_0", - "RIOI_PD_INT_EN_1", - "RIOI_PU_INT_EN_0", - "RIOI_PU_INT_EN_1", - "RIOI_T0", - "RIOI_T1" - ] + "wires": { + "IOI_BLOCK_OUTS0_0": null, + "IOI_BLOCK_OUTS0_1": null, + "IOI_BLOCK_OUTS1_0": null, + "IOI_BLOCK_OUTS1_1": null, + "IOI_BLOCK_OUTS2_0": null, + "IOI_BLOCK_OUTS2_1": null, + "IOI_BLOCK_OUTS3_0": null, + "IOI_BLOCK_OUTS3_1": null, + "IOI_BYP0_0": null, + "IOI_BYP0_1": null, + "IOI_BYP1_0": null, + "IOI_BYP1_1": null, + "IOI_BYP2_0": null, + "IOI_BYP2_1": null, + "IOI_BYP3_0": null, + "IOI_BYP3_1": null, + "IOI_BYP4_0": null, + "IOI_BYP4_1": null, + "IOI_BYP5_0": null, + "IOI_BYP5_1": null, + "IOI_BYP6_0": null, + "IOI_BYP6_1": null, + "IOI_BYP7_0": null, + "IOI_BYP7_1": null, + "IOI_CLK0_0": null, + "IOI_CLK0_1": null, + "IOI_CLK1_0": null, + "IOI_CLK1_1": null, + "IOI_CTRL0_0": null, + "IOI_CTRL0_1": null, + "IOI_CTRL1_0": null, + "IOI_CTRL1_1": null, + "IOI_DCI_DCIDONE": null, + "IOI_DCI_TSTCLK": null, + "IOI_DCI_TSTHLN": null, + "IOI_DCI_TSTHLP": null, + "IOI_DCI_TSTRST": null, + "IOI_DCI_TSTRST0": null, + "IOI_EE2A0_0": null, + "IOI_EE2A0_1": null, + "IOI_EE2A1_0": null, + "IOI_EE2A1_1": null, + "IOI_EE2A2_0": null, + "IOI_EE2A2_1": null, + "IOI_EE2A3_0": null, + "IOI_EE2A3_1": null, + "IOI_EE2BEG0_0": null, + "IOI_EE2BEG0_1": null, + "IOI_EE2BEG1_0": null, + "IOI_EE2BEG1_1": null, + "IOI_EE2BEG2_0": null, + "IOI_EE2BEG2_1": null, + "IOI_EE2BEG3_0": null, + "IOI_EE2BEG3_1": null, + "IOI_EE4A0_0": null, + "IOI_EE4A0_1": null, + "IOI_EE4A1_0": null, + "IOI_EE4A1_1": null, + "IOI_EE4A2_0": null, + "IOI_EE4A2_1": null, + "IOI_EE4A3_0": null, + "IOI_EE4A3_1": null, + "IOI_EE4B0_0": null, + "IOI_EE4B0_1": null, + "IOI_EE4B1_0": null, + "IOI_EE4B1_1": null, + "IOI_EE4B2_0": null, + "IOI_EE4B2_1": null, + "IOI_EE4B3_0": null, + "IOI_EE4B3_1": null, + "IOI_EE4BEG0_0": null, + "IOI_EE4BEG0_1": null, + "IOI_EE4BEG1_0": null, + "IOI_EE4BEG1_1": null, + "IOI_EE4BEG2_0": null, + "IOI_EE4BEG2_1": null, + "IOI_EE4BEG3_0": null, + "IOI_EE4BEG3_1": null, + "IOI_EE4C0_0": null, + "IOI_EE4C0_1": null, + "IOI_EE4C1_0": null, + "IOI_EE4C1_1": null, + "IOI_EE4C2_0": null, + "IOI_EE4C2_1": null, + "IOI_EE4C3_0": null, + "IOI_EE4C3_1": null, + "IOI_EL1BEG0_0": null, + "IOI_EL1BEG0_1": null, + "IOI_EL1BEG1_0": null, + "IOI_EL1BEG1_1": null, + "IOI_EL1BEG2_0": null, + "IOI_EL1BEG2_1": null, + "IOI_EL1BEG3_0": null, + "IOI_EL1BEG3_1": null, + "IOI_ER1BEG0_0": null, + "IOI_ER1BEG0_1": null, + "IOI_ER1BEG1_0": null, + "IOI_ER1BEG1_1": null, + "IOI_ER1BEG2_0": null, + "IOI_ER1BEG2_1": null, + "IOI_ER1BEG3_0": null, + "IOI_ER1BEG3_1": null, + "IOI_FAN0_0": null, + "IOI_FAN0_1": null, + "IOI_FAN1_0": null, + "IOI_FAN1_1": null, + "IOI_FAN2_0": null, + "IOI_FAN2_1": null, + "IOI_FAN3_0": null, + "IOI_FAN3_1": null, + "IOI_FAN4_0": null, + "IOI_FAN4_1": null, + "IOI_FAN5_0": null, + "IOI_FAN5_1": null, + "IOI_FAN6_0": null, + "IOI_FAN6_1": null, + "IOI_FAN7_0": null, + "IOI_FAN7_1": null, + "IOI_IDELAY0_C": null, + "IOI_IDELAY0_CE": null, + "IOI_IDELAY0_CINVCTRL": null, + "IOI_IDELAY0_CNTVALUEIN0": null, + "IOI_IDELAY0_CNTVALUEIN1": null, + "IOI_IDELAY0_CNTVALUEIN2": null, + "IOI_IDELAY0_CNTVALUEIN3": null, + "IOI_IDELAY0_CNTVALUEIN4": null, + "IOI_IDELAY0_CNTVALUEOUT0": null, + "IOI_IDELAY0_CNTVALUEOUT1": null, + "IOI_IDELAY0_CNTVALUEOUT2": null, + "IOI_IDELAY0_CNTVALUEOUT3": null, + "IOI_IDELAY0_CNTVALUEOUT4": null, + "IOI_IDELAY0_DATAIN": null, + "IOI_IDELAY0_INC": null, + "IOI_IDELAY0_LD": null, + "IOI_IDELAY0_LDPIPEEN": null, + "IOI_IDELAY0_REGRST": null, + "IOI_IDELAY1_C": null, + "IOI_IDELAY1_CE": null, + "IOI_IDELAY1_CINVCTRL": null, + "IOI_IDELAY1_CNTVALUEIN0": null, + "IOI_IDELAY1_CNTVALUEIN1": null, + "IOI_IDELAY1_CNTVALUEIN2": null, + "IOI_IDELAY1_CNTVALUEIN3": null, + "IOI_IDELAY1_CNTVALUEIN4": null, + "IOI_IDELAY1_CNTVALUEOUT0": null, + "IOI_IDELAY1_CNTVALUEOUT1": null, + "IOI_IDELAY1_CNTVALUEOUT2": null, + "IOI_IDELAY1_CNTVALUEOUT3": null, + "IOI_IDELAY1_CNTVALUEOUT4": null, + "IOI_IDELAY1_DATAIN": null, + "IOI_IDELAY1_INC": null, + "IOI_IDELAY1_LD": null, + "IOI_IDELAY1_LDPIPEEN": null, + "IOI_IDELAY1_REGRST": null, + "IOI_IDELAYCTRL_DNPULSEOUT": null, + "IOI_IDELAYCTRL_OUTN1": null, + "IOI_IDELAYCTRL_OUTN65": null, + "IOI_IDELAYCTRL_RDY": null, + "IOI_IDELAYCTRL_RST": null, + "IOI_IDELAYCTRL_UPPULSEOUT": null, + "IOI_ILOGIC0_BITSLIP": null, + "IOI_ILOGIC0_CE1": null, + "IOI_ILOGIC0_CE2": null, + "IOI_ILOGIC0_CLK": null, + "IOI_ILOGIC0_CLKB": null, + "IOI_ILOGIC0_CLKDIV": null, + "IOI_ILOGIC0_CLKDIVP": null, + "IOI_ILOGIC0_DYNCLKDIVPSEL": null, + "IOI_ILOGIC0_DYNCLKDIVSEL": null, + "IOI_ILOGIC0_DYNCLKSEL": null, + "IOI_ILOGIC0_O": null, + "IOI_ILOGIC0_OCLK": null, + "IOI_ILOGIC0_OCLKB": null, + "IOI_ILOGIC0_Q1": null, + "IOI_ILOGIC0_Q2": null, + "IOI_ILOGIC0_Q3": null, + "IOI_ILOGIC0_Q4": null, + "IOI_ILOGIC0_Q5": null, + "IOI_ILOGIC0_Q6": null, + "IOI_ILOGIC0_Q7": null, + "IOI_ILOGIC0_Q8": null, + "IOI_ILOGIC0_REV": null, + "IOI_ILOGIC0_SR": null, + "IOI_ILOGIC1_BITSLIP": null, + "IOI_ILOGIC1_CE1": null, + "IOI_ILOGIC1_CE2": null, + "IOI_ILOGIC1_CLK": null, + "IOI_ILOGIC1_CLKB": null, + "IOI_ILOGIC1_CLKDIV": null, + "IOI_ILOGIC1_CLKDIVP": null, + "IOI_ILOGIC1_DYNCLKDIVPSEL": null, + "IOI_ILOGIC1_DYNCLKDIVSEL": null, + "IOI_ILOGIC1_DYNCLKSEL": null, + "IOI_ILOGIC1_O": null, + "IOI_ILOGIC1_OCLK": null, + "IOI_ILOGIC1_OCLKB": null, + "IOI_ILOGIC1_Q1": null, + "IOI_ILOGIC1_Q2": null, + "IOI_ILOGIC1_Q3": null, + "IOI_ILOGIC1_Q4": null, + "IOI_ILOGIC1_Q5": null, + "IOI_ILOGIC1_Q6": null, + "IOI_ILOGIC1_Q7": null, + "IOI_ILOGIC1_Q8": null, + "IOI_ILOGIC1_REV": null, + "IOI_ILOGIC1_SR": null, + "IOI_IMUX0_0": null, + "IOI_IMUX0_1": null, + "IOI_IMUX10_0": null, + "IOI_IMUX10_1": null, + "IOI_IMUX11_0": null, + "IOI_IMUX11_1": null, + "IOI_IMUX12_0": null, + "IOI_IMUX12_1": null, + "IOI_IMUX13_0": null, + "IOI_IMUX13_1": null, + "IOI_IMUX14_0": null, + "IOI_IMUX14_1": null, + "IOI_IMUX15_0": null, + "IOI_IMUX15_1": null, + "IOI_IMUX16_0": null, + "IOI_IMUX16_1": null, + "IOI_IMUX17_0": null, + "IOI_IMUX17_1": null, + "IOI_IMUX18_0": null, + "IOI_IMUX18_1": null, + "IOI_IMUX19_0": null, + "IOI_IMUX19_1": null, + "IOI_IMUX1_0": null, + "IOI_IMUX1_1": null, + "IOI_IMUX20_0": null, + "IOI_IMUX20_1": null, + "IOI_IMUX21_0": null, + "IOI_IMUX21_1": null, + "IOI_IMUX22_0": null, + "IOI_IMUX22_1": null, + "IOI_IMUX23_0": null, + "IOI_IMUX23_1": null, + "IOI_IMUX24_0": null, + "IOI_IMUX24_1": null, + "IOI_IMUX25_0": null, + "IOI_IMUX25_1": null, + "IOI_IMUX26_0": null, + "IOI_IMUX26_1": null, + "IOI_IMUX27_0": null, + "IOI_IMUX27_1": null, + "IOI_IMUX28_0": null, + "IOI_IMUX28_1": null, + "IOI_IMUX29_0": null, + "IOI_IMUX29_1": null, + "IOI_IMUX2_0": null, + "IOI_IMUX2_1": null, + "IOI_IMUX30_0": null, + "IOI_IMUX30_1": null, + "IOI_IMUX31_0": null, + "IOI_IMUX31_1": null, + "IOI_IMUX32_0": null, + "IOI_IMUX32_1": null, + "IOI_IMUX33_0": null, + "IOI_IMUX33_1": null, + "IOI_IMUX34_0": null, + "IOI_IMUX34_1": null, + "IOI_IMUX35_0": null, + "IOI_IMUX35_1": null, + "IOI_IMUX36_0": null, + "IOI_IMUX36_1": null, + "IOI_IMUX37_0": null, + "IOI_IMUX37_1": null, + "IOI_IMUX38_0": null, + "IOI_IMUX38_1": null, + "IOI_IMUX39_0": null, + "IOI_IMUX39_1": null, + "IOI_IMUX3_0": null, + "IOI_IMUX3_1": null, + "IOI_IMUX40_0": null, + "IOI_IMUX40_1": null, + "IOI_IMUX41_0": null, + "IOI_IMUX41_1": null, + "IOI_IMUX42_0": null, + "IOI_IMUX42_1": null, + "IOI_IMUX43_0": null, + "IOI_IMUX43_1": null, + "IOI_IMUX44_0": null, + "IOI_IMUX44_1": null, + "IOI_IMUX45_0": null, + "IOI_IMUX45_1": null, + "IOI_IMUX46_0": null, + "IOI_IMUX46_1": null, + "IOI_IMUX47_0": null, + "IOI_IMUX47_1": null, + "IOI_IMUX4_0": null, + "IOI_IMUX4_1": null, + "IOI_IMUX5_0": null, + "IOI_IMUX5_1": null, + "IOI_IMUX6_0": null, + "IOI_IMUX6_1": null, + "IOI_IMUX7_0": null, + "IOI_IMUX7_1": null, + "IOI_IMUX8_0": null, + "IOI_IMUX8_1": null, + "IOI_IMUX9_0": null, + "IOI_IMUX9_1": null, + "IOI_IMUX_RC0": null, + "IOI_IMUX_RC1": null, + "IOI_IMUX_RC2": null, + "IOI_IMUX_RC3": null, + "IOI_INT_DCI_EN": null, + "IOI_IOCLK0": null, + "IOI_IOCLK1": null, + "IOI_IOCLK2": null, + "IOI_IOCLK3": null, + "IOI_LEAF_GCLK0": null, + "IOI_LEAF_GCLK1": null, + "IOI_LEAF_GCLK2": null, + "IOI_LEAF_GCLK3": null, + "IOI_LEAF_GCLK4": null, + "IOI_LEAF_GCLK5": null, + "IOI_LH10_0": null, + "IOI_LH10_1": null, + "IOI_LH11_0": null, + "IOI_LH11_1": null, + "IOI_LH12_0": null, + "IOI_LH12_1": null, + "IOI_LH1_0": null, + "IOI_LH1_1": null, + "IOI_LH2_0": null, + "IOI_LH2_1": null, + "IOI_LH3_0": null, + "IOI_LH3_1": null, + "IOI_LH4_0": null, + "IOI_LH4_1": null, + "IOI_LH5_0": null, + "IOI_LH5_1": null, + "IOI_LH6_0": null, + "IOI_LH6_1": null, + "IOI_LH7_0": null, + "IOI_LH7_1": null, + "IOI_LH8_0": null, + "IOI_LH8_1": null, + "IOI_LH9_0": null, + "IOI_LH9_1": null, + "IOI_LOGIC_OUTS0_0": null, + "IOI_LOGIC_OUTS0_1": null, + "IOI_LOGIC_OUTS10_0": null, + "IOI_LOGIC_OUTS10_1": null, + "IOI_LOGIC_OUTS11_0": null, + "IOI_LOGIC_OUTS11_1": null, + "IOI_LOGIC_OUTS12_0": null, + "IOI_LOGIC_OUTS12_1": null, + "IOI_LOGIC_OUTS13_0": null, + "IOI_LOGIC_OUTS13_1": null, + "IOI_LOGIC_OUTS14_0": null, + "IOI_LOGIC_OUTS14_1": null, + "IOI_LOGIC_OUTS15_0": null, + "IOI_LOGIC_OUTS15_1": null, + "IOI_LOGIC_OUTS16_0": null, + "IOI_LOGIC_OUTS16_1": null, + "IOI_LOGIC_OUTS17_0": null, + "IOI_LOGIC_OUTS17_1": null, + "IOI_LOGIC_OUTS18_0": null, + "IOI_LOGIC_OUTS18_1": null, + "IOI_LOGIC_OUTS19_0": null, + "IOI_LOGIC_OUTS19_1": null, + "IOI_LOGIC_OUTS1_0": null, + "IOI_LOGIC_OUTS1_1": null, + "IOI_LOGIC_OUTS20_0": null, + "IOI_LOGIC_OUTS20_1": null, + "IOI_LOGIC_OUTS21_0": null, + "IOI_LOGIC_OUTS21_1": null, + "IOI_LOGIC_OUTS22_0": null, + "IOI_LOGIC_OUTS22_1": null, + "IOI_LOGIC_OUTS23_0": null, + "IOI_LOGIC_OUTS23_1": null, + "IOI_LOGIC_OUTS2_0": null, + "IOI_LOGIC_OUTS2_1": null, + "IOI_LOGIC_OUTS3_0": null, + "IOI_LOGIC_OUTS3_1": null, + "IOI_LOGIC_OUTS4_0": null, + "IOI_LOGIC_OUTS4_1": null, + "IOI_LOGIC_OUTS5_0": null, + "IOI_LOGIC_OUTS5_1": null, + "IOI_LOGIC_OUTS6_0": null, + "IOI_LOGIC_OUTS6_1": null, + "IOI_LOGIC_OUTS7_0": null, + "IOI_LOGIC_OUTS7_1": null, + "IOI_LOGIC_OUTS8_0": null, + "IOI_LOGIC_OUTS8_1": null, + "IOI_LOGIC_OUTS9_0": null, + "IOI_LOGIC_OUTS9_1": null, + "IOI_MONITOR_N": null, + "IOI_MONITOR_P": null, + "IOI_NE2A0_0": null, + "IOI_NE2A0_1": null, + "IOI_NE2A1_0": null, + "IOI_NE2A1_1": null, + "IOI_NE2A2_0": null, + "IOI_NE2A2_1": null, + "IOI_NE2A3_0": null, + "IOI_NE2A3_1": null, + "IOI_NE4BEG0_0": null, + "IOI_NE4BEG0_1": null, + "IOI_NE4BEG1_0": null, + "IOI_NE4BEG1_1": null, + "IOI_NE4BEG2_0": null, + "IOI_NE4BEG2_1": null, + "IOI_NE4BEG3_0": null, + "IOI_NE4BEG3_1": null, + "IOI_NE4C0_0": null, + "IOI_NE4C0_1": null, + "IOI_NE4C1_0": null, + "IOI_NE4C1_1": null, + "IOI_NE4C2_0": null, + "IOI_NE4C2_1": null, + "IOI_NE4C3_0": null, + "IOI_NE4C3_1": null, + "IOI_NW2A0_0": null, + "IOI_NW2A0_1": null, + "IOI_NW2A1_0": null, + "IOI_NW2A1_1": null, + "IOI_NW2A2_0": null, + "IOI_NW2A2_1": null, + "IOI_NW2A3_0": null, + "IOI_NW2A3_1": null, + "IOI_NW4A0_0": null, + "IOI_NW4A0_1": null, + "IOI_NW4A1_0": null, + "IOI_NW4A1_1": null, + "IOI_NW4A2_0": null, + "IOI_NW4A2_1": null, + "IOI_NW4A3_0": null, + "IOI_NW4A3_1": null, + "IOI_NW4END0_0": null, + "IOI_NW4END0_1": null, + "IOI_NW4END1_0": null, + "IOI_NW4END1_1": null, + "IOI_NW4END2_0": null, + "IOI_NW4END2_1": null, + "IOI_NW4END3_0": null, + "IOI_NW4END3_1": null, + "IOI_OCLKM_0": null, + "IOI_OCLKM_1": null, + "IOI_OCLK_0": null, + "IOI_OCLK_1": null, + "IOI_ODELAY0_C": null, + "IOI_ODELAY0_CE": null, + "IOI_ODELAY0_CINVCTRL": null, + "IOI_ODELAY0_CLKIN": null, + "IOI_ODELAY0_CNTVALUEIN0": null, + "IOI_ODELAY0_CNTVALUEIN1": null, + "IOI_ODELAY0_CNTVALUEIN2": null, + "IOI_ODELAY0_CNTVALUEIN3": null, + "IOI_ODELAY0_CNTVALUEIN4": null, + "IOI_ODELAY0_CNTVALUEOUT0": null, + "IOI_ODELAY0_CNTVALUEOUT1": null, + "IOI_ODELAY0_CNTVALUEOUT2": null, + "IOI_ODELAY0_CNTVALUEOUT3": null, + "IOI_ODELAY0_CNTVALUEOUT4": null, + "IOI_ODELAY0_INC": null, + "IOI_ODELAY0_LD": null, + "IOI_ODELAY0_LDPIPEEN": null, + "IOI_ODELAY0_REGRST": null, + "IOI_ODELAY1_C": null, + "IOI_ODELAY1_CE": null, + "IOI_ODELAY1_CINVCTRL": null, + "IOI_ODELAY1_CLKIN": null, + "IOI_ODELAY1_CNTVALUEIN0": null, + "IOI_ODELAY1_CNTVALUEIN1": null, + "IOI_ODELAY1_CNTVALUEIN2": null, + "IOI_ODELAY1_CNTVALUEIN3": null, + "IOI_ODELAY1_CNTVALUEIN4": null, + "IOI_ODELAY1_CNTVALUEOUT0": null, + "IOI_ODELAY1_CNTVALUEOUT1": null, + "IOI_ODELAY1_CNTVALUEOUT2": null, + "IOI_ODELAY1_CNTVALUEOUT3": null, + "IOI_ODELAY1_CNTVALUEOUT4": null, + "IOI_ODELAY1_INC": null, + "IOI_ODELAY1_LD": null, + "IOI_ODELAY1_LDPIPEEN": null, + "IOI_ODELAY1_REGRST": null, + "IOI_OLOGIC0_CLK": null, + "IOI_OLOGIC0_CLKB": null, + "IOI_OLOGIC0_CLKDIV": null, + "IOI_OLOGIC0_CLKDIVB": null, + "IOI_OLOGIC0_CLKDIVFB": null, + "IOI_OLOGIC0_D1": null, + "IOI_OLOGIC0_D2": null, + "IOI_OLOGIC0_D3": null, + "IOI_OLOGIC0_D4": null, + "IOI_OLOGIC0_D5": null, + "IOI_OLOGIC0_D6": null, + "IOI_OLOGIC0_D7": null, + "IOI_OLOGIC0_D8": null, + "IOI_OLOGIC0_IOCLKGLITCH": null, + "IOI_OLOGIC0_OCE": null, + "IOI_OLOGIC0_REV": null, + "IOI_OLOGIC0_SR": null, + "IOI_OLOGIC0_T1": null, + "IOI_OLOGIC0_T2": null, + "IOI_OLOGIC0_T3": null, + "IOI_OLOGIC0_T4": null, + "IOI_OLOGIC0_TBYTEIN": null, + "IOI_OLOGIC0_TBYTEOUT": null, + "IOI_OLOGIC0_TCE": null, + "IOI_OLOGIC1_CLK": null, + "IOI_OLOGIC1_CLKB": null, + "IOI_OLOGIC1_CLKDIV": null, + "IOI_OLOGIC1_CLKDIVB": null, + "IOI_OLOGIC1_CLKDIVFB": null, + "IOI_OLOGIC1_D1": null, + "IOI_OLOGIC1_D2": null, + "IOI_OLOGIC1_D3": null, + "IOI_OLOGIC1_D4": null, + "IOI_OLOGIC1_D5": null, + "IOI_OLOGIC1_D6": null, + "IOI_OLOGIC1_D7": null, + "IOI_OLOGIC1_D8": null, + "IOI_OLOGIC1_IOCLKGLITCH": null, + "IOI_OLOGIC1_OCE": null, + "IOI_OLOGIC1_REV": null, + "IOI_OLOGIC1_SR": null, + "IOI_OLOGIC1_T1": null, + "IOI_OLOGIC1_T2": null, + "IOI_OLOGIC1_T3": null, + "IOI_OLOGIC1_T4": null, + "IOI_OLOGIC1_TBYTEIN": null, + "IOI_OLOGIC1_TBYTEOUT": null, + "IOI_OLOGIC1_TCE": null, + "IOI_PHASER_TO_IO_ICLK": null, + "IOI_PHASER_TO_IO_ICLKDIV": null, + "IOI_PHASER_TO_IO_ICLKDIV_0": null, + "IOI_PHASER_TO_IO_ICLK_0": null, + "IOI_PHASER_TO_IO_OCLK": null, + "IOI_PHASER_TO_IO_OCLK1X_90": null, + "IOI_PHASER_TO_IO_OCLK1X_90_0": null, + "IOI_PHASER_TO_IO_OCLKDIV": null, + "IOI_PHASER_TO_IO_OCLKDIV_0": null, + "IOI_PHASER_TO_IO_OCLK_0": null, + "IOI_RCLK_DIV_CE0": null, + "IOI_RCLK_DIV_CE1": null, + "IOI_RCLK_DIV_CE2": null, + "IOI_RCLK_DIV_CE2_1": null, + "IOI_RCLK_DIV_CE3": null, + "IOI_RCLK_DIV_CE3_1": null, + "IOI_RCLK_DIV_CLR0": null, + "IOI_RCLK_DIV_CLR0_1": null, + "IOI_RCLK_DIV_CLR1": null, + "IOI_RCLK_DIV_CLR1_1": null, + "IOI_RCLK_DIV_CLR2": null, + "IOI_RCLK_DIV_CLR3": null, + "IOI_RCLK_FORIO0": null, + "IOI_RCLK_FORIO1": null, + "IOI_RCLK_FORIO2": null, + "IOI_RCLK_FORIO3": null, + "IOI_SE2A0_0": null, + "IOI_SE2A0_1": null, + "IOI_SE2A1_0": null, + "IOI_SE2A1_1": null, + "IOI_SE2A2_0": null, + "IOI_SE2A2_1": null, + "IOI_SE2A3_0": null, + "IOI_SE2A3_1": null, + "IOI_SE4BEG0_0": null, + "IOI_SE4BEG0_1": null, + "IOI_SE4BEG1_0": null, + "IOI_SE4BEG1_1": null, + "IOI_SE4BEG2_0": null, + "IOI_SE4BEG2_1": null, + "IOI_SE4BEG3_0": null, + "IOI_SE4BEG3_1": null, + "IOI_SE4C0_0": null, + "IOI_SE4C0_1": null, + "IOI_SE4C1_0": null, + "IOI_SE4C1_1": null, + "IOI_SE4C2_0": null, + "IOI_SE4C2_1": null, + "IOI_SE4C3_0": null, + "IOI_SE4C3_1": null, + "IOI_SW2A0_0": null, + "IOI_SW2A0_1": null, + "IOI_SW2A1_0": null, + "IOI_SW2A1_1": null, + "IOI_SW2A2_0": null, + "IOI_SW2A2_1": null, + "IOI_SW2A3_0": null, + "IOI_SW2A3_1": null, + "IOI_SW4A0_0": null, + "IOI_SW4A0_1": null, + "IOI_SW4A1_0": null, + "IOI_SW4A1_1": null, + "IOI_SW4A2_0": null, + "IOI_SW4A2_1": null, + "IOI_SW4A3_0": null, + "IOI_SW4A3_1": null, + "IOI_SW4END0_0": null, + "IOI_SW4END0_1": null, + "IOI_SW4END1_0": null, + "IOI_SW4END1_1": null, + "IOI_SW4END2_0": null, + "IOI_SW4END2_1": null, + "IOI_SW4END3_0": null, + "IOI_SW4END3_1": null, + "IOI_TBYTEIN": null, + "IOI_WL1END0_0": null, + "IOI_WL1END0_1": null, + "IOI_WL1END1_0": null, + "IOI_WL1END1_1": null, + "IOI_WL1END2_0": null, + "IOI_WL1END2_1": null, + "IOI_WL1END3_0": null, + "IOI_WL1END3_1": null, + "IOI_WR1END0_0": null, + "IOI_WR1END0_1": null, + "IOI_WR1END1_0": null, + "IOI_WR1END1_1": null, + "IOI_WR1END2_0": null, + "IOI_WR1END2_1": null, + "IOI_WR1END3_0": null, + "IOI_WR1END3_1": null, + "IOI_WW2A0_0": null, + "IOI_WW2A0_1": null, + "IOI_WW2A1_0": null, + "IOI_WW2A1_1": null, + "IOI_WW2A2_0": null, + "IOI_WW2A2_1": null, + "IOI_WW2A3_0": null, + "IOI_WW2A3_1": null, + "IOI_WW2END0_0": null, + "IOI_WW2END0_1": null, + "IOI_WW2END1_0": null, + "IOI_WW2END1_1": null, + "IOI_WW2END2_0": null, + "IOI_WW2END2_1": null, + "IOI_WW2END3_0": null, + "IOI_WW2END3_1": null, + "IOI_WW4A0_0": null, + "IOI_WW4A0_1": null, + "IOI_WW4A1_0": null, + "IOI_WW4A1_1": null, + "IOI_WW4A2_0": null, + "IOI_WW4A2_1": null, + "IOI_WW4A3_0": null, + "IOI_WW4A3_1": null, + "IOI_WW4B0_0": null, + "IOI_WW4B0_1": null, + "IOI_WW4B1_0": null, + "IOI_WW4B1_1": null, + "IOI_WW4B2_0": null, + "IOI_WW4B2_1": null, + "IOI_WW4B3_0": null, + "IOI_WW4B3_1": null, + "IOI_WW4C0_0": null, + "IOI_WW4C0_1": null, + "IOI_WW4C1_0": null, + "IOI_WW4C1_1": null, + "IOI_WW4C2_0": null, + "IOI_WW4C2_1": null, + "IOI_WW4C3_0": null, + "IOI_WW4C3_1": null, + "IOI_WW4END0_0": null, + "IOI_WW4END0_1": null, + "IOI_WW4END1_0": null, + "IOI_WW4END1_1": null, + "IOI_WW4END2_0": null, + "IOI_WW4END2_1": null, + "IOI_WW4END3_0": null, + "IOI_WW4END3_1": null, + "RIOI3_IDELAY0_IFDLY0": null, + "RIOI3_IDELAY0_IFDLY1": null, + "RIOI3_IDELAY0_IFDLY2": null, + "RIOI3_IDELAY1_IFDLY0": null, + "RIOI3_IDELAY1_IFDLY1": null, + "RIOI3_IDELAY1_IFDLY2": null, + "RIOI_DCI_T_TERM0": null, + "RIOI_DCI_T_TERM1": null, + "RIOI_DIFF_TERM_INT_EN": null, + "RIOI_I0": null, + "RIOI_I1": null, + "RIOI_I2GCLK_BOT1": null, + "RIOI_I2GCLK_TOP0": null, + "RIOI_I2GCLK_TOP1": null, + "RIOI_IBUF0": null, + "RIOI_IBUF1": null, + "RIOI_IBUF_DISABLE0": null, + "RIOI_IBUF_DISABLE1": null, + "RIOI_IDELAY0_DATAOUT": null, + "RIOI_IDELAY0_IDATAIN": null, + "RIOI_IDELAY1_DATAOUT": null, + "RIOI_IDELAY1_IDATAIN": null, + "RIOI_ILOGIC0_D": null, + "RIOI_ILOGIC0_DDLY": null, + "RIOI_ILOGIC0_OFB": null, + "RIOI_ILOGIC0_TFB": null, + "RIOI_ILOGIC1_D": null, + "RIOI_ILOGIC1_DDLY": null, + "RIOI_ILOGIC1_OFB": null, + "RIOI_ILOGIC1_TFB": null, + "RIOI_ISIN10": null, + "RIOI_ISIN11": null, + "RIOI_ISIN20": null, + "RIOI_ISIN21": null, + "RIOI_ISOUT10": null, + "RIOI_ISOUT11": null, + "RIOI_ISOUT20": null, + "RIOI_ISOUT21": null, + "RIOI_KEEPER_INT_EN_0": null, + "RIOI_KEEPER_INT_EN_1": null, + "RIOI_O0": null, + "RIOI_O1": null, + "RIOI_ODELAY0_DATAOUT": null, + "RIOI_ODELAY0_ODATAIN": null, + "RIOI_ODELAY0_OFDLY0": null, + "RIOI_ODELAY0_OFDLY1": null, + "RIOI_ODELAY0_OFDLY2": null, + "RIOI_ODELAY1_DATAOUT": null, + "RIOI_ODELAY1_ODATAIN": null, + "RIOI_ODELAY1_OFDLY0": null, + "RIOI_ODELAY1_OFDLY1": null, + "RIOI_ODELAY1_OFDLY2": null, + "RIOI_OLOGIC0_CLKDIVF": null, + "RIOI_OLOGIC0_OFB": null, + "RIOI_OLOGIC0_OQ": null, + "RIOI_OLOGIC0_TFB": null, + "RIOI_OLOGIC0_TFB_LOCAL": null, + "RIOI_OLOGIC0_TQ": null, + "RIOI_OLOGIC1_CLKDIVF": null, + "RIOI_OLOGIC1_OFB": null, + "RIOI_OLOGIC1_OQ": null, + "RIOI_OLOGIC1_TFB": null, + "RIOI_OLOGIC1_TFB_LOCAL": null, + "RIOI_OLOGIC1_TQ": null, + "RIOI_OSIN10": null, + "RIOI_OSIN11": null, + "RIOI_OSIN20": null, + "RIOI_OSIN21": null, + "RIOI_OSOUT10": null, + "RIOI_OSOUT11": null, + "RIOI_OSOUT20": null, + "RIOI_OSOUT21": null, + "RIOI_PD_INT_EN_0": null, + "RIOI_PD_INT_EN_1": null, + "RIOI_PU_INT_EN_0": null, + "RIOI_PU_INT_EN_1": null, + "RIOI_T0": null, + "RIOI_T1": null + } } diff --git a/zynq7/tile_type_RIOI3_TBYTETERM.json b/zynq7/tile_type_RIOI3_TBYTETERM.json index 42aee13..d0dea79 100644 --- a/zynq7/tile_type_RIOI3_TBYTETERM.json +++ b/zynq7/tile_type_RIOI3_TBYTETERM.json @@ -2,2900 +2,10034 @@ "pips": { "RIOI3_TBYTETERM.IOI_BYP3_0->IOI_IMUX_RC0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI3_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI3_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI3_TBYTETERM.IOI_BYP3_1->IOI_IMUX_RC3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI3_TBYTETERM.IOI_BYP4_0->IOI_IMUX_RC1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI3_TBYTETERM.IOI_BYP4_1->IOI_IMUX_RC2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI3_TBYTETERM.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_0" }, "RIOI3_TBYTETERM.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_1" }, "RIOI3_TBYTETERM.IOI_BYP7_0->RIOI3_IDELAY1_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY1_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_0" }, "RIOI3_TBYTETERM.IOI_BYP7_1->RIOI3_IDELAY0_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY0_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_1" }, "RIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "RIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "RIOI3_TBYTETERM.IOI_CLK1_0->IOI_IDELAY1_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "RIOI3_TBYTETERM.IOI_CLK1_1->IOI_IDELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_1" }, "RIOI3_TBYTETERM.IOI_CTRL0_0->IOI_OLOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_0" }, "RIOI3_TBYTETERM.IOI_CTRL0_1->IOI_OLOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_1" }, "RIOI3_TBYTETERM.IOI_CTRL1_0->IOI_ILOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_0" }, "RIOI3_TBYTETERM.IOI_CTRL1_1->IOI_ILOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_1" }, "RIOI3_TBYTETERM.IOI_FAN4_0->RIOI3_IDELAY1_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY1_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_0" }, "RIOI3_TBYTETERM.IOI_FAN4_1->RIOI3_IDELAY0_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY0_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_1" }, "RIOI3_TBYTETERM.IOI_FAN5_0->RIOI3_IDELAY1_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY1_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_0" }, "RIOI3_TBYTETERM.IOI_FAN5_1->RIOI3_IDELAY0_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI3_IDELAY0_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_1" }, "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "RIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT0" }, "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT1" }, "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT2" }, "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT3" }, "RIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT4" }, "RIOI3_TBYTETERM.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC0_O" }, "RIOI3_TBYTETERM.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q1" }, "RIOI3_TBYTETERM.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q2" }, "RIOI3_TBYTETERM.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q3" }, "RIOI3_TBYTETERM.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q4" }, "RIOI3_TBYTETERM.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q5" }, "RIOI3_TBYTETERM.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q6" }, "RIOI3_TBYTETERM.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q7" }, "RIOI3_TBYTETERM.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q8" }, "RIOI3_TBYTETERM.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.004", + "0.015", + "0.027", + "0.030" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC1_O" }, "RIOI3_TBYTETERM.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q1" }, "RIOI3_TBYTETERM.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q2" }, "RIOI3_TBYTETERM.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q3" }, "RIOI3_TBYTETERM.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q4" }, "RIOI3_TBYTETERM.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q5" }, "RIOI3_TBYTETERM.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q6" }, "RIOI3_TBYTETERM.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q7" }, "RIOI3_TBYTETERM.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q8" }, "RIOI3_TBYTETERM.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_0" }, "RIOI3_TBYTETERM.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_1" }, "RIOI3_TBYTETERM.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_0" }, "RIOI3_TBYTETERM.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_1" }, "RIOI3_TBYTETERM.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_0" }, "RIOI3_TBYTETERM.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_1" }, "RIOI3_TBYTETERM.IOI_IMUX13_0->IOI_OLOGIC1_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_0" }, "RIOI3_TBYTETERM.IOI_IMUX13_1->IOI_OLOGIC0_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_1" }, "RIOI3_TBYTETERM.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_0" }, "RIOI3_TBYTETERM.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_1" }, "RIOI3_TBYTETERM.IOI_IMUX15_0->IOI_OLOGIC1_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_0" }, "RIOI3_TBYTETERM.IOI_IMUX15_1->IOI_OLOGIC0_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_1" }, "RIOI3_TBYTETERM.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_0" }, "RIOI3_TBYTETERM.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_1" }, "RIOI3_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI3_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "RIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "RIOI3_TBYTETERM.IOI_IMUX21_0->IOI_OLOGIC1_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_0" }, "RIOI3_TBYTETERM.IOI_IMUX21_1->IOI_OLOGIC0_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_1" }, "RIOI3_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI3_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "RIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "RIOI3_TBYTETERM.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_0" }, "RIOI3_TBYTETERM.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_1" }, "RIOI3_TBYTETERM.IOI_IMUX26_0->IOI_IDELAY1_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_0" }, "RIOI3_TBYTETERM.IOI_IMUX26_1->IOI_IDELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_1" }, "RIOI3_TBYTETERM.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_0" }, "RIOI3_TBYTETERM.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_1" }, "RIOI3_TBYTETERM.IOI_IMUX30_0->IOI_IDELAY1_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_0" }, "RIOI3_TBYTETERM.IOI_IMUX30_1->IOI_IDELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_1" }, "RIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "RIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "RIOI3_TBYTETERM.IOI_IMUX32_0->IOI_IDELAY1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_0" }, "RIOI3_TBYTETERM.IOI_IMUX32_1->IOI_IDELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_1" }, "RIOI3_TBYTETERM.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_0" }, "RIOI3_TBYTETERM.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_1" }, "RIOI3_TBYTETERM.IOI_IMUX34_0->IOI_OLOGIC1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_0" }, "RIOI3_TBYTETERM.IOI_IMUX34_1->IOI_OLOGIC0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_1" }, "RIOI3_TBYTETERM.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_0" }, "RIOI3_TBYTETERM.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_1" }, "RIOI3_TBYTETERM.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_0" }, "RIOI3_TBYTETERM.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_1" }, "RIOI3_TBYTETERM.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_0" }, "RIOI3_TBYTETERM.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_1" }, "RIOI3_TBYTETERM.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_0" }, "RIOI3_TBYTETERM.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_1" }, "RIOI3_TBYTETERM.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_0" }, "RIOI3_TBYTETERM.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_1" }, "RIOI3_TBYTETERM.IOI_IMUX40_0->IOI_OLOGIC1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_0" }, "RIOI3_TBYTETERM.IOI_IMUX40_1->IOI_OLOGIC0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_1" }, "RIOI3_TBYTETERM.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_0" }, "RIOI3_TBYTETERM.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_1" }, "RIOI3_TBYTETERM.IOI_IMUX42_0->IOI_OLOGIC1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_0" }, "RIOI3_TBYTETERM.IOI_IMUX42_1->IOI_OLOGIC0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_1" }, "RIOI3_TBYTETERM.IOI_IMUX43_0->IOI_OLOGIC1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_0" }, "RIOI3_TBYTETERM.IOI_IMUX43_1->IOI_OLOGIC0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_1" }, "RIOI3_TBYTETERM.IOI_IMUX44_0->IOI_OLOGIC1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_0" }, "RIOI3_TBYTETERM.IOI_IMUX44_1->IOI_OLOGIC0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_1" }, "RIOI3_TBYTETERM.IOI_IMUX45_0->IOI_OLOGIC1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_0" }, "RIOI3_TBYTETERM.IOI_IMUX45_1->IOI_OLOGIC0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_1" }, "RIOI3_TBYTETERM.IOI_IMUX46_0->IOI_OLOGIC1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_0" }, "RIOI3_TBYTETERM.IOI_IMUX46_1->IOI_OLOGIC0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_1" }, "RIOI3_TBYTETERM.IOI_IMUX47_0->IOI_OLOGIC1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_0" }, "RIOI3_TBYTETERM.IOI_IMUX47_1->IOI_OLOGIC0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_1" }, "RIOI3_TBYTETERM.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_0" }, "RIOI3_TBYTETERM.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_1" }, "RIOI3_TBYTETERM.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_0" }, "RIOI3_TBYTETERM.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_1" }, "RIOI3_TBYTETERM.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_0" }, "RIOI3_TBYTETERM.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_1" }, "RIOI3_TBYTETERM.IOI_IMUX7_0->IOI_OLOGIC1_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_0" }, "RIOI3_TBYTETERM.IOI_IMUX7_1->IOI_OLOGIC0_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_1" }, "RIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3_TBYTETERM.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI3_TBYTETERM.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.123", + "0.142", + "0.386", + "0.393" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI3_TBYTETERM.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_0" }, "RIOI3_TBYTETERM.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_1" }, "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { 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"is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": 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"res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_OCLK_0": { "can_invert": "0", + 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"in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, 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"is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK4->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.079", + "0.083" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI3_TBYTETERM.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI3_TBYTETERM.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI3_TBYTETERM.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "RIOI3_TBYTETERM.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "RIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI3_TBYTETERM.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI3_TBYTETERM.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI3_TBYTETERM.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC0_IOCLKGLITCH" }, "RIOI3_TBYTETERM.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI3_TBYTETERM.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI3_TBYTETERM.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "RIOI3_TBYTETERM.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.331", + "0.999", + "1.156" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "RIOI3_TBYTETERM.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC1_IOCLKGLITCH" }, "RIOI3_TBYTETERM.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "RIOI3_TBYTETERM.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.350", + "0.403", + "0.958", + "1.102" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK_0" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK_0" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, "RIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.029", + "0.032", + "0.085", + "0.092" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, 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"is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.055", + "0.120", + "0.138" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC0_DDLY" }, "RIOI3_TBYTETERM.RIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.054", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.054", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC1_D" }, "RIOI3_TBYTETERM.RIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.055", + "0.120", + "0.138" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.055", + "0.120", + "0.138" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC1_DDLY" }, "RIOI3_TBYTETERM.RIOI_ISOUT10->RIOI_ISIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ISIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_ISOUT10" }, "RIOI3_TBYTETERM.RIOI_ISOUT20->RIOI_ISIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ISIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_ISOUT20" }, "RIOI3_TBYTETERM.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": 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"RIOI3_TBYTETERM.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB" }, "RIOI3_TBYTETERM.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI3_TBYTETERM.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI3_TBYTETERM.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" }, "RIOI3_TBYTETERM.RIOI_OLOGIC0_TQ->>RIOI_T0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_T0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" }, "RIOI3_TBYTETERM.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_OFB" }, "RIOI3_TBYTETERM.RIOI_OLOGIC1_OQ->>RIOI_O1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_O1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_OQ" }, "RIOI3_TBYTETERM.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_OQ" }, "RIOI3_TBYTETERM.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB" }, "RIOI3_TBYTETERM.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB_LOCAL" }, "RIOI3_TBYTETERM.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB_LOCAL" }, "RIOI3_TBYTETERM.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.055", + "0.063", + "0.165", + "0.199" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_TQ" }, "RIOI3_TBYTETERM.RIOI_OLOGIC1_TQ->>RIOI_T1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_T1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_TQ" }, "RIOI3_TBYTETERM.RIOI_OSOUT11->RIOI_OSIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OSIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OSOUT11" }, "RIOI3_TBYTETERM.RIOI_OSOUT21->RIOI_OSIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OSIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OSOUT21" } }, @@ -2904,39 +10038,309 @@ "name": "X0Y0", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC1_CLK", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "D1": "IOI_OLOGIC1_D1", - "D2": "IOI_OLOGIC1_D2", - "D3": "IOI_OLOGIC1_D3", - "D4": "IOI_OLOGIC1_D4", - "D5": "IOI_OLOGIC1_D5", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D8": "IOI_OLOGIC1_D8", - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "OCE": "IOI_OLOGIC1_OCE", - "OFB": "RIOI_OLOGIC1_OFB", - "OQ": "RIOI_OLOGIC1_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_OQ" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_OSOUT11", - "SHIFTOUT2": "RIOI_OSOUT21", - "SR": "IOI_OLOGIC1_SR", - "T1": "IOI_OLOGIC1_T1", - "T2": "IOI_OLOGIC1_T2", - "T3": "IOI_OLOGIC1_T3", - "T4": "IOI_OLOGIC1_T4", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "TCE": "IOI_OLOGIC1_TCE", - "TFB": "RIOI_OLOGIC1_TFB", - "TQ": "RIOI_OLOGIC1_TQ" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -2946,37 +10350,307 @@ "name": "X0Y0", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "CE1": "IOI_ILOGIC1_CE1", - "CE2": "IOI_ILOGIC1_CE2", - "CLK": "IOI_ILOGIC1_CLK", - "CLKB": "IOI_ILOGIC1_CLKB", - "CLKDIV": "IOI_ILOGIC1_CLKDIV", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "D": "RIOI_ILOGIC1_D", - "DDLY": "RIOI_ILOGIC1_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "O": "IOI_ILOGIC1_O", - "OCLK": "IOI_ILOGIC1_OCLK", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "OFB": "RIOI_ILOGIC1_OFB", - "Q1": "IOI_ILOGIC1_Q1", - "Q2": "IOI_ILOGIC1_Q2", - "Q3": "IOI_ILOGIC1_Q3", - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q6": "IOI_ILOGIC1_Q6", - "Q7": "IOI_ILOGIC1_Q7", - "Q8": "IOI_ILOGIC1_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC1_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q8" + }, "REV": null, - "SHIFTIN1": "RIOI_ISIN11", - "SHIFTIN2": "RIOI_ISIN21", - "SHIFTOUT1": "RIOI_ISOUT11", - "SHIFTOUT2": "RIOI_ISOUT21", - "SR": "IOI_ILOGIC1_SR", - "TFB": "RIOI_ILOGIC1_TFB" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ISIN11" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ISIN21" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -2986,39 +10660,327 @@ "name": "X0Y1", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC0_CLK", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "D1": "IOI_OLOGIC0_D1", - "D2": "IOI_OLOGIC0_D2", - "D3": "IOI_OLOGIC0_D3", - "D4": "IOI_OLOGIC0_D4", - "D5": "IOI_OLOGIC0_D5", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D8": "IOI_OLOGIC0_D8", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "OCE": "IOI_OLOGIC0_OCE", - "OFB": "RIOI_OLOGIC0_OFB", - "OQ": "RIOI_OLOGIC0_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OQ" + }, "REV": null, - "SHIFTIN1": "RIOI_OSIN10", - "SHIFTIN2": "RIOI_OSIN20", - "SHIFTOUT1": "RIOI_OSOUT10", - "SHIFTOUT2": "RIOI_OSOUT20", - "SR": "IOI_OLOGIC0_SR", - "T1": "IOI_OLOGIC0_T1", - "T2": "IOI_OLOGIC0_T2", - "T3": "IOI_OLOGIC0_T3", - "T4": "IOI_OLOGIC0_T4", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "TCE": "IOI_OLOGIC0_TCE", - "TFB": "RIOI_OLOGIC0_TFB", - "TQ": "RIOI_OLOGIC0_TQ" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OSIN10" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OSIN20" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -3028,37 +10990,289 @@ "name": "X0Y1", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "CE1": "IOI_ILOGIC0_CE1", - "CE2": "IOI_ILOGIC0_CE2", - "CLK": "IOI_ILOGIC0_CLK", - "CLKB": "IOI_ILOGIC0_CLKB", - "CLKDIV": "IOI_ILOGIC0_CLKDIV", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "D": "RIOI_ILOGIC0_D", - "DDLY": "RIOI_ILOGIC0_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "O": "IOI_ILOGIC0_O", - "OCLK": "IOI_ILOGIC0_OCLK", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "OFB": "RIOI_ILOGIC0_OFB", - "Q1": "IOI_ILOGIC0_Q1", - "Q2": "IOI_ILOGIC0_Q2", - "Q3": "IOI_ILOGIC0_Q3", - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q6": "IOI_ILOGIC0_Q6", - "Q7": "IOI_ILOGIC0_Q7", - "Q8": "IOI_ILOGIC0_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC0_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q8" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_ISOUT10", - "SHIFTOUT2": "RIOI_ISOUT20", - "SR": "IOI_ILOGIC0_SR", - "TFB": "RIOI_ILOGIC0_TFB" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -3068,29 +11282,236 @@ "name": "X0Y0", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY1_C", - "CE": "IOI_IDELAY1_CE", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY1_DATAIN", - "DATAOUT": "RIOI_IDELAY1_DATAOUT", - "IDATAIN": "RIOI_IDELAY1_IDATAIN", - "IFDLY0": "RIOI3_IDELAY1_IFDLY0", - "IFDLY1": "RIOI3_IDELAY1_IFDLY1", - "IFDLY2": "RIOI3_IDELAY1_IFDLY2", - "INC": "IOI_IDELAY1_INC", - "LD": "IOI_IDELAY1_LD", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "REGRST": "IOI_IDELAY1_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY1_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY1_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY1_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY1_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -3100,29 +11521,236 @@ "name": "X0Y1", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY0_C", - "CE": "IOI_IDELAY0_CE", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY0_DATAIN", - "DATAOUT": "RIOI_IDELAY0_DATAOUT", - "IDATAIN": "RIOI_IDELAY0_IDATAIN", - "IFDLY0": "RIOI3_IDELAY0_IFDLY0", - "IFDLY1": "RIOI3_IDELAY0_IFDLY1", - "IFDLY2": "RIOI3_IDELAY0_IFDLY2", - "INC": "IOI_IDELAY0_INC", - "LD": "IOI_IDELAY0_LD", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "REGRST": "IOI_IDELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY0_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY0_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY0_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI3_IDELAY0_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -3130,750 +11758,750 @@ } ], "tile_type": "RIOI3_TBYTETERM", - "wires": [ - "IOI_BLOCK_OUTS0_0", - "IOI_BLOCK_OUTS0_1", - "IOI_BLOCK_OUTS1_0", - "IOI_BLOCK_OUTS1_1", - "IOI_BLOCK_OUTS2_0", - "IOI_BLOCK_OUTS2_1", - "IOI_BLOCK_OUTS3_0", - "IOI_BLOCK_OUTS3_1", - "IOI_BYP0_0", - "IOI_BYP0_1", - "IOI_BYP1_0", - "IOI_BYP1_1", - "IOI_BYP2_0", - "IOI_BYP2_1", - "IOI_BYP3_0", - "IOI_BYP3_1", - "IOI_BYP4_0", - "IOI_BYP4_1", - "IOI_BYP5_0", - "IOI_BYP5_1", - "IOI_BYP6_0", - "IOI_BYP6_1", - "IOI_BYP7_0", - "IOI_BYP7_1", - "IOI_CLK0_0", - "IOI_CLK0_1", - "IOI_CLK1_0", - "IOI_CLK1_1", - "IOI_CTRL0_0", - "IOI_CTRL0_1", - "IOI_CTRL1_0", - "IOI_CTRL1_1", - "IOI_DCI_DCIDONE", - "IOI_DCI_TSTCLK", - "IOI_DCI_TSTHLN", - "IOI_DCI_TSTHLP", - "IOI_DCI_TSTRST", - "IOI_DCI_TSTRST0", - "IOI_EE2A0_0", - "IOI_EE2A0_1", - "IOI_EE2A1_0", - "IOI_EE2A1_1", - "IOI_EE2A2_0", - "IOI_EE2A2_1", - "IOI_EE2A3_0", - "IOI_EE2A3_1", - "IOI_EE2BEG0_0", - "IOI_EE2BEG0_1", - "IOI_EE2BEG1_0", - "IOI_EE2BEG1_1", - "IOI_EE2BEG2_0", - "IOI_EE2BEG2_1", - "IOI_EE2BEG3_0", - "IOI_EE2BEG3_1", - "IOI_EE4A0_0", - "IOI_EE4A0_1", - "IOI_EE4A1_0", - "IOI_EE4A1_1", - "IOI_EE4A2_0", - "IOI_EE4A2_1", - "IOI_EE4A3_0", - "IOI_EE4A3_1", - "IOI_EE4B0_0", - "IOI_EE4B0_1", - "IOI_EE4B1_0", - "IOI_EE4B1_1", - "IOI_EE4B2_0", - "IOI_EE4B2_1", - "IOI_EE4B3_0", - "IOI_EE4B3_1", - "IOI_EE4BEG0_0", - "IOI_EE4BEG0_1", - "IOI_EE4BEG1_0", - "IOI_EE4BEG1_1", - "IOI_EE4BEG2_0", - "IOI_EE4BEG2_1", - "IOI_EE4BEG3_0", - "IOI_EE4BEG3_1", - "IOI_EE4C0_0", - "IOI_EE4C0_1", - "IOI_EE4C1_0", - "IOI_EE4C1_1", - "IOI_EE4C2_0", - "IOI_EE4C2_1", - "IOI_EE4C3_0", - "IOI_EE4C3_1", - "IOI_EL1BEG0_0", - "IOI_EL1BEG0_1", - "IOI_EL1BEG1_0", - "IOI_EL1BEG1_1", - "IOI_EL1BEG2_0", - "IOI_EL1BEG2_1", - "IOI_EL1BEG3_0", - "IOI_EL1BEG3_1", - "IOI_ER1BEG0_0", - "IOI_ER1BEG0_1", - "IOI_ER1BEG1_0", - "IOI_ER1BEG1_1", - "IOI_ER1BEG2_0", - "IOI_ER1BEG2_1", - "IOI_ER1BEG3_0", - "IOI_ER1BEG3_1", - "IOI_FAN0_0", - "IOI_FAN0_1", - "IOI_FAN1_0", - "IOI_FAN1_1", - "IOI_FAN2_0", - "IOI_FAN2_1", - "IOI_FAN3_0", - "IOI_FAN3_1", - "IOI_FAN4_0", - "IOI_FAN4_1", - "IOI_FAN5_0", - "IOI_FAN5_1", - "IOI_FAN6_0", - "IOI_FAN6_1", - "IOI_FAN7_0", - "IOI_FAN7_1", - "IOI_IDELAY0_C", - "IOI_IDELAY0_CE", - "IOI_IDELAY0_CINVCTRL", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_IDELAY0_DATAIN", - "IOI_IDELAY0_INC", - "IOI_IDELAY0_LD", - "IOI_IDELAY0_LDPIPEEN", - "IOI_IDELAY0_REGRST", - "IOI_IDELAY1_C", - "IOI_IDELAY1_CE", - "IOI_IDELAY1_CINVCTRL", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT0", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_IDELAY1_DATAIN", - "IOI_IDELAY1_INC", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_LDPIPEEN", - "IOI_IDELAY1_REGRST", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IDELAYCTRL_OUTN1", - "IOI_IDELAYCTRL_OUTN65", - "IOI_IDELAYCTRL_RDY", - "IOI_IDELAYCTRL_RST", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_ILOGIC0_BITSLIP", - "IOI_ILOGIC0_CE1", - "IOI_ILOGIC0_CE2", - "IOI_ILOGIC0_CLK", - "IOI_ILOGIC0_CLKB", - "IOI_ILOGIC0_CLKDIV", - "IOI_ILOGIC0_CLKDIVP", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_ILOGIC0_O", - "IOI_ILOGIC0_OCLK", - "IOI_ILOGIC0_OCLKB", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_Q2", - "IOI_ILOGIC0_Q3", - "IOI_ILOGIC0_Q4", - "IOI_ILOGIC0_Q5", - "IOI_ILOGIC0_Q6", - "IOI_ILOGIC0_Q7", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC0_REV", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC1_BITSLIP", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC1_CE2", - "IOI_ILOGIC1_CLK", - "IOI_ILOGIC1_CLKB", - "IOI_ILOGIC1_CLKDIV", - "IOI_ILOGIC1_CLKDIVP", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_ILOGIC1_O", - "IOI_ILOGIC1_OCLK", - "IOI_ILOGIC1_OCLKB", - "IOI_ILOGIC1_Q1", - "IOI_ILOGIC1_Q2", - "IOI_ILOGIC1_Q3", - "IOI_ILOGIC1_Q4", - "IOI_ILOGIC1_Q5", - "IOI_ILOGIC1_Q6", - "IOI_ILOGIC1_Q7", - "IOI_ILOGIC1_Q8", - "IOI_ILOGIC1_REV", - "IOI_ILOGIC1_SR", - "IOI_IMUX0_0", - "IOI_IMUX0_1", - "IOI_IMUX10_0", - "IOI_IMUX10_1", - "IOI_IMUX11_0", - "IOI_IMUX11_1", - "IOI_IMUX12_0", - "IOI_IMUX12_1", - "IOI_IMUX13_0", - "IOI_IMUX13_1", - "IOI_IMUX14_0", - "IOI_IMUX14_1", - "IOI_IMUX15_0", - "IOI_IMUX15_1", - "IOI_IMUX16_0", - "IOI_IMUX16_1", - "IOI_IMUX17_0", - "IOI_IMUX17_1", - "IOI_IMUX18_0", - "IOI_IMUX18_1", - "IOI_IMUX19_0", - "IOI_IMUX19_1", - "IOI_IMUX1_0", - "IOI_IMUX1_1", - "IOI_IMUX20_0", - "IOI_IMUX20_1", - "IOI_IMUX21_0", - "IOI_IMUX21_1", - "IOI_IMUX22_0", - "IOI_IMUX22_1", - "IOI_IMUX23_0", - "IOI_IMUX23_1", - "IOI_IMUX24_0", - "IOI_IMUX24_1", - "IOI_IMUX25_0", - "IOI_IMUX25_1", - "IOI_IMUX26_0", - "IOI_IMUX26_1", - "IOI_IMUX27_0", - "IOI_IMUX27_1", - "IOI_IMUX28_0", - "IOI_IMUX28_1", - "IOI_IMUX29_0", - "IOI_IMUX29_1", - "IOI_IMUX2_0", - "IOI_IMUX2_1", - "IOI_IMUX30_0", - "IOI_IMUX30_1", - "IOI_IMUX31_0", - "IOI_IMUX31_1", - "IOI_IMUX32_0", - "IOI_IMUX32_1", - "IOI_IMUX33_0", - "IOI_IMUX33_1", - "IOI_IMUX34_0", - "IOI_IMUX34_1", - "IOI_IMUX35_0", - "IOI_IMUX35_1", - "IOI_IMUX36_0", - "IOI_IMUX36_1", - "IOI_IMUX37_0", - "IOI_IMUX37_1", - "IOI_IMUX38_0", - "IOI_IMUX38_1", - "IOI_IMUX39_0", - "IOI_IMUX39_1", - "IOI_IMUX3_0", - "IOI_IMUX3_1", - "IOI_IMUX40_0", - "IOI_IMUX40_1", - "IOI_IMUX41_0", - "IOI_IMUX41_1", - "IOI_IMUX42_0", - "IOI_IMUX42_1", - "IOI_IMUX43_0", - "IOI_IMUX43_1", - "IOI_IMUX44_0", - "IOI_IMUX44_1", - "IOI_IMUX45_0", - "IOI_IMUX45_1", - "IOI_IMUX46_0", - "IOI_IMUX46_1", - "IOI_IMUX47_0", - "IOI_IMUX47_1", - "IOI_IMUX4_0", - "IOI_IMUX4_1", - "IOI_IMUX5_0", - "IOI_IMUX5_1", - "IOI_IMUX6_0", - "IOI_IMUX6_1", - "IOI_IMUX7_0", - "IOI_IMUX7_1", - "IOI_IMUX8_0", - "IOI_IMUX8_1", - "IOI_IMUX9_0", - "IOI_IMUX9_1", - "IOI_IMUX_RC0", - "IOI_IMUX_RC1", - "IOI_IMUX_RC2", - "IOI_IMUX_RC3", - "IOI_INT_DCI_EN", - "IOI_IOCLK0", - "IOI_IOCLK1", - "IOI_IOCLK2", - "IOI_IOCLK3", - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK5", - "IOI_LH10_0", - "IOI_LH10_1", - "IOI_LH11_0", - "IOI_LH11_1", - "IOI_LH12_0", - "IOI_LH12_1", - "IOI_LH1_0", - "IOI_LH1_1", - "IOI_LH2_0", - "IOI_LH2_1", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_LH4_0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_LH5_1", - "IOI_LH6_0", - "IOI_LH6_1", - "IOI_LH7_0", - "IOI_LH7_1", - "IOI_LH8_0", - "IOI_LH8_1", - "IOI_LH9_0", - "IOI_LH9_1", - "IOI_LOGIC_OUTS0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_LOGIC_OUTS10_0", - "IOI_LOGIC_OUTS10_1", - "IOI_LOGIC_OUTS11_0", - "IOI_LOGIC_OUTS11_1", - "IOI_LOGIC_OUTS12_0", - "IOI_LOGIC_OUTS12_1", - "IOI_LOGIC_OUTS13_0", - "IOI_LOGIC_OUTS13_1", - "IOI_LOGIC_OUTS14_0", - "IOI_LOGIC_OUTS14_1", - "IOI_LOGIC_OUTS15_0", - "IOI_LOGIC_OUTS15_1", - "IOI_LOGIC_OUTS16_0", - "IOI_LOGIC_OUTS16_1", - "IOI_LOGIC_OUTS17_0", - "IOI_LOGIC_OUTS17_1", - "IOI_LOGIC_OUTS18_0", - "IOI_LOGIC_OUTS18_1", - "IOI_LOGIC_OUTS19_0", - "IOI_LOGIC_OUTS19_1", - "IOI_LOGIC_OUTS1_0", - "IOI_LOGIC_OUTS1_1", - "IOI_LOGIC_OUTS20_0", - "IOI_LOGIC_OUTS20_1", - "IOI_LOGIC_OUTS21_0", - "IOI_LOGIC_OUTS21_1", - "IOI_LOGIC_OUTS22_0", - "IOI_LOGIC_OUTS22_1", - "IOI_LOGIC_OUTS23_0", - "IOI_LOGIC_OUTS23_1", - "IOI_LOGIC_OUTS2_0", - "IOI_LOGIC_OUTS2_1", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS3_1", - "IOI_LOGIC_OUTS4_0", - "IOI_LOGIC_OUTS4_1", - "IOI_LOGIC_OUTS5_0", - "IOI_LOGIC_OUTS5_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LOGIC_OUTS6_1", - "IOI_LOGIC_OUTS7_0", - "IOI_LOGIC_OUTS7_1", - "IOI_LOGIC_OUTS8_0", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS9_0", - "IOI_LOGIC_OUTS9_1", - "IOI_MONITOR_N", - "IOI_MONITOR_P", - "IOI_NE2A0_0", - "IOI_NE2A0_1", - "IOI_NE2A1_0", - "IOI_NE2A1_1", - "IOI_NE2A2_0", - "IOI_NE2A2_1", - "IOI_NE2A3_0", - "IOI_NE2A3_1", - "IOI_NE4BEG0_0", - "IOI_NE4BEG0_1", - "IOI_NE4BEG1_0", - "IOI_NE4BEG1_1", - "IOI_NE4BEG2_0", - "IOI_NE4BEG2_1", - "IOI_NE4BEG3_0", - "IOI_NE4BEG3_1", - "IOI_NE4C0_0", - "IOI_NE4C0_1", - "IOI_NE4C1_0", - "IOI_NE4C1_1", - "IOI_NE4C2_0", - "IOI_NE4C2_1", - "IOI_NE4C3_0", - "IOI_NE4C3_1", - "IOI_NW2A0_0", - "IOI_NW2A0_1", - "IOI_NW2A1_0", - "IOI_NW2A1_1", - "IOI_NW2A2_0", - "IOI_NW2A2_1", - "IOI_NW2A3_0", - "IOI_NW2A3_1", - "IOI_NW4A0_0", - "IOI_NW4A0_1", - "IOI_NW4A1_0", - "IOI_NW4A1_1", - "IOI_NW4A2_0", - "IOI_NW4A2_1", - "IOI_NW4A3_0", - "IOI_NW4A3_1", - "IOI_NW4END0_0", - "IOI_NW4END0_1", - "IOI_NW4END1_0", - "IOI_NW4END1_1", - "IOI_NW4END2_0", - "IOI_NW4END2_1", - "IOI_NW4END3_0", - "IOI_NW4END3_1", - "IOI_OCLKM_0", - "IOI_OCLKM_1", - "IOI_OCLK_0", - "IOI_OCLK_1", - "IOI_ODELAY0_C", - "IOI_ODELAY0_CE", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY0_CLKIN", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ODELAY0_INC", - "IOI_ODELAY0_LD", - "IOI_ODELAY0_LDPIPEEN", - "IOI_ODELAY0_REGRST", - "IOI_ODELAY1_C", - "IOI_ODELAY1_CE", - "IOI_ODELAY1_CINVCTRL", - "IOI_ODELAY1_CLKIN", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_ODELAY1_CNTVALUEIN1", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_ODELAY1_CNTVALUEOUT0", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_ODELAY1_CNTVALUEOUT2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_ODELAY1_INC", - "IOI_ODELAY1_LD", - "IOI_ODELAY1_LDPIPEEN", - "IOI_ODELAY1_REGRST", - "IOI_OLOGIC0_CLK", - "IOI_OLOGIC0_CLKB", - "IOI_OLOGIC0_CLKDIV", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_OLOGIC0_D1", - "IOI_OLOGIC0_D2", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_D4", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_D6", - "IOI_OLOGIC0_D7", - "IOI_OLOGIC0_D8", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_OCE", - "IOI_OLOGIC0_REV", - "IOI_OLOGIC0_SR", - "IOI_OLOGIC0_T1", - "IOI_OLOGIC0_T2", - "IOI_OLOGIC0_T3", - "IOI_OLOGIC0_T4", - "IOI_OLOGIC0_TBYTEIN", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_CLK", - "IOI_OLOGIC1_CLKB", - "IOI_OLOGIC1_CLKDIV", - "IOI_OLOGIC1_CLKDIVB", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_OLOGIC1_D1", - "IOI_OLOGIC1_D2", - "IOI_OLOGIC1_D3", - "IOI_OLOGIC1_D4", - "IOI_OLOGIC1_D5", - "IOI_OLOGIC1_D6", - "IOI_OLOGIC1_D7", - "IOI_OLOGIC1_D8", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_OLOGIC1_OCE", - "IOI_OLOGIC1_REV", - "IOI_OLOGIC1_SR", - "IOI_OLOGIC1_T1", - "IOI_OLOGIC1_T2", - "IOI_OLOGIC1_T3", - "IOI_OLOGIC1_T4", - "IOI_OLOGIC1_TBYTEIN", - "IOI_OLOGIC1_TBYTEOUT", - "IOI_OLOGIC1_TCE", - "IOI_PHASER_TO_IO_ICLK", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_PHASER_TO_IO_OCLK", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_PHASER_TO_IO_OCLK_0", - "IOI_RCLK_DIV_CE0", - "IOI_RCLK_DIV_CE1", - "IOI_RCLK_DIV_CE2", - "IOI_RCLK_DIV_CE2_1", - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1", - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1", - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_RCLK_DIV_CLR2", - "IOI_RCLK_DIV_CLR3", - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO3", - "IOI_SE2A0_0", - "IOI_SE2A0_1", - "IOI_SE2A1_0", - "IOI_SE2A1_1", - "IOI_SE2A2_0", - "IOI_SE2A2_1", - "IOI_SE2A3_0", - "IOI_SE2A3_1", - "IOI_SE4BEG0_0", - "IOI_SE4BEG0_1", - "IOI_SE4BEG1_0", - "IOI_SE4BEG1_1", - "IOI_SE4BEG2_0", - "IOI_SE4BEG2_1", - "IOI_SE4BEG3_0", - "IOI_SE4BEG3_1", - "IOI_SE4C0_0", - "IOI_SE4C0_1", - "IOI_SE4C1_0", - "IOI_SE4C1_1", - "IOI_SE4C2_0", - "IOI_SE4C2_1", - "IOI_SE4C3_0", - "IOI_SE4C3_1", - "IOI_SW2A0_0", - "IOI_SW2A0_1", - "IOI_SW2A1_0", - "IOI_SW2A1_1", - "IOI_SW2A2_0", - "IOI_SW2A2_1", - "IOI_SW2A3_0", - "IOI_SW2A3_1", - "IOI_SW4A0_0", - "IOI_SW4A0_1", - "IOI_SW4A1_0", - "IOI_SW4A1_1", - "IOI_SW4A2_0", - "IOI_SW4A2_1", - "IOI_SW4A3_0", - "IOI_SW4A3_1", - "IOI_SW4END0_0", - "IOI_SW4END0_1", - "IOI_SW4END1_0", - "IOI_SW4END1_1", - "IOI_SW4END2_0", - "IOI_SW4END2_1", - "IOI_SW4END3_0", - "IOI_SW4END3_1", - "IOI_TBYTEIN_TERM", - "IOI_WL1END0_0", - "IOI_WL1END0_1", - "IOI_WL1END1_0", - "IOI_WL1END1_1", - "IOI_WL1END2_0", - "IOI_WL1END2_1", - "IOI_WL1END3_0", - "IOI_WL1END3_1", - "IOI_WR1END0_0", - "IOI_WR1END0_1", - "IOI_WR1END1_0", - "IOI_WR1END1_1", - "IOI_WR1END2_0", - "IOI_WR1END2_1", - "IOI_WR1END3_0", - "IOI_WR1END3_1", - "IOI_WW2A0_0", - "IOI_WW2A0_1", - "IOI_WW2A1_0", - "IOI_WW2A1_1", - "IOI_WW2A2_0", - "IOI_WW2A2_1", - "IOI_WW2A3_0", - "IOI_WW2A3_1", - "IOI_WW2END0_0", - "IOI_WW2END0_1", - "IOI_WW2END1_0", - "IOI_WW2END1_1", - "IOI_WW2END2_0", - "IOI_WW2END2_1", - "IOI_WW2END3_0", - "IOI_WW2END3_1", - "IOI_WW4A0_0", - "IOI_WW4A0_1", - "IOI_WW4A1_0", - "IOI_WW4A1_1", - "IOI_WW4A2_0", - "IOI_WW4A2_1", - "IOI_WW4A3_0", - "IOI_WW4A3_1", - "IOI_WW4B0_0", - "IOI_WW4B0_1", - "IOI_WW4B1_0", - "IOI_WW4B1_1", - "IOI_WW4B2_0", - "IOI_WW4B2_1", - "IOI_WW4B3_0", - "IOI_WW4B3_1", - "IOI_WW4C0_0", - "IOI_WW4C0_1", - "IOI_WW4C1_0", - "IOI_WW4C1_1", - "IOI_WW4C2_0", - "IOI_WW4C2_1", - "IOI_WW4C3_0", - "IOI_WW4C3_1", - "IOI_WW4END0_0", - "IOI_WW4END0_1", - "IOI_WW4END1_0", - "IOI_WW4END1_1", - "IOI_WW4END2_0", - "IOI_WW4END2_1", - "IOI_WW4END3_0", - "IOI_WW4END3_1", - "RIOI3_IDELAY0_IFDLY0", - "RIOI3_IDELAY0_IFDLY1", - "RIOI3_IDELAY0_IFDLY2", - "RIOI3_IDELAY1_IFDLY0", - "RIOI3_IDELAY1_IFDLY1", - "RIOI3_IDELAY1_IFDLY2", - "RIOI_DCI_T_TERM0", - "RIOI_DCI_T_TERM1", - "RIOI_DIFF_TERM_INT_EN", - "RIOI_I0", - "RIOI_I1", - "RIOI_I2GCLK_BOT1", - "RIOI_I2GCLK_TOP0", - "RIOI_I2GCLK_TOP1", - "RIOI_IBUF0", - "RIOI_IBUF1", - "RIOI_IBUF_DISABLE0", - "RIOI_IBUF_DISABLE1", - "RIOI_IDELAY0_DATAOUT", - "RIOI_IDELAY0_IDATAIN", - "RIOI_IDELAY1_DATAOUT", - "RIOI_IDELAY1_IDATAIN", - "RIOI_ILOGIC0_D", - "RIOI_ILOGIC0_DDLY", - "RIOI_ILOGIC0_OFB", - "RIOI_ILOGIC0_TFB", - "RIOI_ILOGIC1_D", - "RIOI_ILOGIC1_DDLY", - "RIOI_ILOGIC1_OFB", - "RIOI_ILOGIC1_TFB", - "RIOI_ISIN10", - "RIOI_ISIN11", - "RIOI_ISIN20", - "RIOI_ISIN21", - "RIOI_ISOUT10", - "RIOI_ISOUT11", - "RIOI_ISOUT20", - "RIOI_ISOUT21", - "RIOI_KEEPER_INT_EN_0", - "RIOI_KEEPER_INT_EN_1", - "RIOI_O0", - "RIOI_O1", - "RIOI_ODELAY0_DATAOUT", - "RIOI_ODELAY0_ODATAIN", - "RIOI_ODELAY0_OFDLY0", - "RIOI_ODELAY0_OFDLY1", - "RIOI_ODELAY0_OFDLY2", - "RIOI_ODELAY1_DATAOUT", - "RIOI_ODELAY1_ODATAIN", - "RIOI_ODELAY1_OFDLY0", - "RIOI_ODELAY1_OFDLY1", - "RIOI_ODELAY1_OFDLY2", - "RIOI_OLOGIC0_CLKDIVF", - "RIOI_OLOGIC0_OFB", - "RIOI_OLOGIC0_OQ", - "RIOI_OLOGIC0_TFB", - "RIOI_OLOGIC0_TFB_LOCAL", - "RIOI_OLOGIC0_TQ", - "RIOI_OLOGIC1_CLKDIVF", - "RIOI_OLOGIC1_OFB", - "RIOI_OLOGIC1_OQ", - "RIOI_OLOGIC1_TFB", - "RIOI_OLOGIC1_TFB_LOCAL", - "RIOI_OLOGIC1_TQ", - "RIOI_OSIN10", - "RIOI_OSIN11", - "RIOI_OSIN20", - "RIOI_OSIN21", - "RIOI_OSOUT10", - "RIOI_OSOUT11", - "RIOI_OSOUT20", - "RIOI_OSOUT21", - "RIOI_PD_INT_EN_0", - "RIOI_PD_INT_EN_1", - "RIOI_PU_INT_EN_0", - "RIOI_PU_INT_EN_1", - "RIOI_T0", - "RIOI_T1" - ] + "wires": { + "IOI_BLOCK_OUTS0_0": null, + "IOI_BLOCK_OUTS0_1": null, + "IOI_BLOCK_OUTS1_0": null, + "IOI_BLOCK_OUTS1_1": null, + "IOI_BLOCK_OUTS2_0": null, + "IOI_BLOCK_OUTS2_1": null, + "IOI_BLOCK_OUTS3_0": null, + "IOI_BLOCK_OUTS3_1": null, + "IOI_BYP0_0": null, + "IOI_BYP0_1": null, + "IOI_BYP1_0": null, + "IOI_BYP1_1": null, + "IOI_BYP2_0": null, + "IOI_BYP2_1": null, + "IOI_BYP3_0": null, + "IOI_BYP3_1": null, + "IOI_BYP4_0": null, + "IOI_BYP4_1": null, + "IOI_BYP5_0": null, + "IOI_BYP5_1": null, + "IOI_BYP6_0": null, + "IOI_BYP6_1": null, + "IOI_BYP7_0": null, + "IOI_BYP7_1": null, + "IOI_CLK0_0": null, + "IOI_CLK0_1": null, + "IOI_CLK1_0": null, + "IOI_CLK1_1": null, + "IOI_CTRL0_0": null, + "IOI_CTRL0_1": null, + "IOI_CTRL1_0": null, + "IOI_CTRL1_1": null, + "IOI_DCI_DCIDONE": null, + "IOI_DCI_TSTCLK": null, + "IOI_DCI_TSTHLN": null, + "IOI_DCI_TSTHLP": null, + "IOI_DCI_TSTRST": null, + "IOI_DCI_TSTRST0": null, + "IOI_EE2A0_0": null, + "IOI_EE2A0_1": null, + "IOI_EE2A1_0": null, + "IOI_EE2A1_1": null, + "IOI_EE2A2_0": null, + "IOI_EE2A2_1": null, + "IOI_EE2A3_0": null, + "IOI_EE2A3_1": null, + "IOI_EE2BEG0_0": null, + "IOI_EE2BEG0_1": null, + "IOI_EE2BEG1_0": null, + "IOI_EE2BEG1_1": null, + "IOI_EE2BEG2_0": null, + "IOI_EE2BEG2_1": null, + "IOI_EE2BEG3_0": null, + "IOI_EE2BEG3_1": null, + "IOI_EE4A0_0": null, + "IOI_EE4A0_1": null, + "IOI_EE4A1_0": null, + "IOI_EE4A1_1": null, + "IOI_EE4A2_0": null, + "IOI_EE4A2_1": null, + "IOI_EE4A3_0": null, + "IOI_EE4A3_1": null, + "IOI_EE4B0_0": null, + "IOI_EE4B0_1": null, + "IOI_EE4B1_0": null, + "IOI_EE4B1_1": null, + "IOI_EE4B2_0": null, + "IOI_EE4B2_1": null, + "IOI_EE4B3_0": null, + "IOI_EE4B3_1": null, + "IOI_EE4BEG0_0": null, + "IOI_EE4BEG0_1": null, + "IOI_EE4BEG1_0": null, + "IOI_EE4BEG1_1": null, + "IOI_EE4BEG2_0": null, + "IOI_EE4BEG2_1": null, + "IOI_EE4BEG3_0": null, + "IOI_EE4BEG3_1": null, + "IOI_EE4C0_0": null, + "IOI_EE4C0_1": null, + "IOI_EE4C1_0": null, + "IOI_EE4C1_1": null, + "IOI_EE4C2_0": null, + "IOI_EE4C2_1": null, + "IOI_EE4C3_0": null, + "IOI_EE4C3_1": null, + "IOI_EL1BEG0_0": null, + "IOI_EL1BEG0_1": null, + "IOI_EL1BEG1_0": null, + "IOI_EL1BEG1_1": null, + "IOI_EL1BEG2_0": null, + "IOI_EL1BEG2_1": null, + "IOI_EL1BEG3_0": null, + "IOI_EL1BEG3_1": null, + "IOI_ER1BEG0_0": null, + "IOI_ER1BEG0_1": null, + "IOI_ER1BEG1_0": null, + "IOI_ER1BEG1_1": null, + "IOI_ER1BEG2_0": null, + "IOI_ER1BEG2_1": null, + "IOI_ER1BEG3_0": null, + "IOI_ER1BEG3_1": null, + "IOI_FAN0_0": null, + "IOI_FAN0_1": null, + "IOI_FAN1_0": null, + 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"IOI_ODELAY1_LDPIPEEN": null, + "IOI_ODELAY1_REGRST": null, + "IOI_OLOGIC0_CLK": null, + "IOI_OLOGIC0_CLKB": null, + "IOI_OLOGIC0_CLKDIV": null, + "IOI_OLOGIC0_CLKDIVB": null, + "IOI_OLOGIC0_CLKDIVFB": null, + "IOI_OLOGIC0_D1": null, + "IOI_OLOGIC0_D2": null, + "IOI_OLOGIC0_D3": null, + "IOI_OLOGIC0_D4": null, + "IOI_OLOGIC0_D5": null, + "IOI_OLOGIC0_D6": null, + "IOI_OLOGIC0_D7": null, + "IOI_OLOGIC0_D8": null, + "IOI_OLOGIC0_IOCLKGLITCH": null, + "IOI_OLOGIC0_OCE": null, + "IOI_OLOGIC0_REV": null, + "IOI_OLOGIC0_SR": null, + "IOI_OLOGIC0_T1": null, + "IOI_OLOGIC0_T2": null, + "IOI_OLOGIC0_T3": null, + "IOI_OLOGIC0_T4": null, + "IOI_OLOGIC0_TBYTEIN": null, + "IOI_OLOGIC0_TBYTEOUT": null, + "IOI_OLOGIC0_TCE": null, + "IOI_OLOGIC1_CLK": null, + "IOI_OLOGIC1_CLKB": null, + "IOI_OLOGIC1_CLKDIV": null, + "IOI_OLOGIC1_CLKDIVB": null, + "IOI_OLOGIC1_CLKDIVFB": null, + "IOI_OLOGIC1_D1": null, + "IOI_OLOGIC1_D2": null, + "IOI_OLOGIC1_D3": null, + "IOI_OLOGIC1_D4": null, + "IOI_OLOGIC1_D5": null, + "IOI_OLOGIC1_D6": null, + "IOI_OLOGIC1_D7": null, + "IOI_OLOGIC1_D8": null, + "IOI_OLOGIC1_IOCLKGLITCH": null, + "IOI_OLOGIC1_OCE": null, + "IOI_OLOGIC1_REV": null, + "IOI_OLOGIC1_SR": null, + "IOI_OLOGIC1_T1": null, + "IOI_OLOGIC1_T2": null, + "IOI_OLOGIC1_T3": null, + "IOI_OLOGIC1_T4": null, + "IOI_OLOGIC1_TBYTEIN": null, + "IOI_OLOGIC1_TBYTEOUT": null, + "IOI_OLOGIC1_TCE": null, + "IOI_PHASER_TO_IO_ICLK": null, + "IOI_PHASER_TO_IO_ICLKDIV": null, + "IOI_PHASER_TO_IO_ICLKDIV_0": null, + "IOI_PHASER_TO_IO_ICLK_0": null, + "IOI_PHASER_TO_IO_OCLK": null, + "IOI_PHASER_TO_IO_OCLK1X_90": null, + "IOI_PHASER_TO_IO_OCLK1X_90_0": null, + "IOI_PHASER_TO_IO_OCLKDIV": null, + "IOI_PHASER_TO_IO_OCLKDIV_0": null, + "IOI_PHASER_TO_IO_OCLK_0": null, + "IOI_RCLK_DIV_CE0": null, + "IOI_RCLK_DIV_CE1": null, + "IOI_RCLK_DIV_CE2": null, + "IOI_RCLK_DIV_CE2_1": null, + "IOI_RCLK_DIV_CE3": null, + "IOI_RCLK_DIV_CE3_1": null, + "IOI_RCLK_DIV_CLR0": null, + "IOI_RCLK_DIV_CLR0_1": null, + "IOI_RCLK_DIV_CLR1": null, + "IOI_RCLK_DIV_CLR1_1": null, + "IOI_RCLK_DIV_CLR2": null, + "IOI_RCLK_DIV_CLR3": null, + "IOI_RCLK_FORIO0": null, + "IOI_RCLK_FORIO1": null, + "IOI_RCLK_FORIO2": null, + "IOI_RCLK_FORIO3": null, + "IOI_SE2A0_0": null, + "IOI_SE2A0_1": null, + "IOI_SE2A1_0": null, + "IOI_SE2A1_1": null, + "IOI_SE2A2_0": null, + "IOI_SE2A2_1": null, + "IOI_SE2A3_0": null, + "IOI_SE2A3_1": null, + "IOI_SE4BEG0_0": null, + "IOI_SE4BEG0_1": null, + "IOI_SE4BEG1_0": null, + "IOI_SE4BEG1_1": null, + "IOI_SE4BEG2_0": null, + "IOI_SE4BEG2_1": null, + "IOI_SE4BEG3_0": null, + "IOI_SE4BEG3_1": null, + "IOI_SE4C0_0": null, + "IOI_SE4C0_1": null, + "IOI_SE4C1_0": null, + "IOI_SE4C1_1": null, + "IOI_SE4C2_0": null, + "IOI_SE4C2_1": null, + "IOI_SE4C3_0": null, + "IOI_SE4C3_1": null, + "IOI_SW2A0_0": null, + "IOI_SW2A0_1": null, + "IOI_SW2A1_0": null, + "IOI_SW2A1_1": null, + "IOI_SW2A2_0": null, + "IOI_SW2A2_1": null, + "IOI_SW2A3_0": null, + "IOI_SW2A3_1": null, + "IOI_SW4A0_0": null, + "IOI_SW4A0_1": null, + "IOI_SW4A1_0": null, + "IOI_SW4A1_1": null, + "IOI_SW4A2_0": null, + "IOI_SW4A2_1": null, + "IOI_SW4A3_0": null, + "IOI_SW4A3_1": null, + "IOI_SW4END0_0": null, + "IOI_SW4END0_1": null, + "IOI_SW4END1_0": null, + "IOI_SW4END1_1": null, + "IOI_SW4END2_0": null, + "IOI_SW4END2_1": null, + "IOI_SW4END3_0": null, + "IOI_SW4END3_1": null, + "IOI_TBYTEIN_TERM": null, + "IOI_WL1END0_0": null, + "IOI_WL1END0_1": null, + "IOI_WL1END1_0": null, + "IOI_WL1END1_1": null, + "IOI_WL1END2_0": null, + "IOI_WL1END2_1": null, + "IOI_WL1END3_0": null, + "IOI_WL1END3_1": null, + "IOI_WR1END0_0": null, + "IOI_WR1END0_1": null, + "IOI_WR1END1_0": null, + "IOI_WR1END1_1": null, + "IOI_WR1END2_0": null, + "IOI_WR1END2_1": null, + "IOI_WR1END3_0": null, + "IOI_WR1END3_1": null, + "IOI_WW2A0_0": null, + "IOI_WW2A0_1": null, + "IOI_WW2A1_0": null, + "IOI_WW2A1_1": null, + "IOI_WW2A2_0": null, + "IOI_WW2A2_1": null, + "IOI_WW2A3_0": null, + "IOI_WW2A3_1": null, + "IOI_WW2END0_0": null, + "IOI_WW2END0_1": null, + "IOI_WW2END1_0": null, + "IOI_WW2END1_1": null, + "IOI_WW2END2_0": null, + "IOI_WW2END2_1": null, + "IOI_WW2END3_0": null, + "IOI_WW2END3_1": null, + "IOI_WW4A0_0": null, + "IOI_WW4A0_1": null, + "IOI_WW4A1_0": null, + "IOI_WW4A1_1": null, + "IOI_WW4A2_0": null, + "IOI_WW4A2_1": null, + "IOI_WW4A3_0": null, + "IOI_WW4A3_1": null, + "IOI_WW4B0_0": null, + "IOI_WW4B0_1": null, + "IOI_WW4B1_0": null, + "IOI_WW4B1_1": null, + "IOI_WW4B2_0": null, + "IOI_WW4B2_1": null, + "IOI_WW4B3_0": null, + "IOI_WW4B3_1": null, + "IOI_WW4C0_0": null, + "IOI_WW4C0_1": null, + "IOI_WW4C1_0": null, + "IOI_WW4C1_1": null, + "IOI_WW4C2_0": null, + "IOI_WW4C2_1": null, + "IOI_WW4C3_0": null, + "IOI_WW4C3_1": null, + "IOI_WW4END0_0": null, + "IOI_WW4END0_1": null, + "IOI_WW4END1_0": null, + "IOI_WW4END1_1": null, + "IOI_WW4END2_0": null, + "IOI_WW4END2_1": null, + "IOI_WW4END3_0": null, + "IOI_WW4END3_1": null, + "RIOI3_IDELAY0_IFDLY0": null, + "RIOI3_IDELAY0_IFDLY1": null, + "RIOI3_IDELAY0_IFDLY2": null, + "RIOI3_IDELAY1_IFDLY0": null, + "RIOI3_IDELAY1_IFDLY1": null, + "RIOI3_IDELAY1_IFDLY2": null, + "RIOI_DCI_T_TERM0": null, + "RIOI_DCI_T_TERM1": null, + "RIOI_DIFF_TERM_INT_EN": null, + "RIOI_I0": null, + "RIOI_I1": null, + "RIOI_I2GCLK_BOT1": null, + "RIOI_I2GCLK_TOP0": null, + "RIOI_I2GCLK_TOP1": null, + "RIOI_IBUF0": null, + "RIOI_IBUF1": null, + "RIOI_IBUF_DISABLE0": null, + "RIOI_IBUF_DISABLE1": null, + "RIOI_IDELAY0_DATAOUT": null, + "RIOI_IDELAY0_IDATAIN": null, + "RIOI_IDELAY1_DATAOUT": null, + "RIOI_IDELAY1_IDATAIN": null, + "RIOI_ILOGIC0_D": null, + "RIOI_ILOGIC0_DDLY": null, + "RIOI_ILOGIC0_OFB": null, + "RIOI_ILOGIC0_TFB": null, + "RIOI_ILOGIC1_D": null, + "RIOI_ILOGIC1_DDLY": null, + "RIOI_ILOGIC1_OFB": null, + "RIOI_ILOGIC1_TFB": null, + "RIOI_ISIN10": null, + "RIOI_ISIN11": null, + "RIOI_ISIN20": null, + "RIOI_ISIN21": null, + "RIOI_ISOUT10": null, + "RIOI_ISOUT11": null, + "RIOI_ISOUT20": null, + "RIOI_ISOUT21": null, + "RIOI_KEEPER_INT_EN_0": null, + "RIOI_KEEPER_INT_EN_1": null, + "RIOI_O0": null, + "RIOI_O1": null, + "RIOI_ODELAY0_DATAOUT": null, + "RIOI_ODELAY0_ODATAIN": null, + "RIOI_ODELAY0_OFDLY0": null, + "RIOI_ODELAY0_OFDLY1": null, + "RIOI_ODELAY0_OFDLY2": null, + "RIOI_ODELAY1_DATAOUT": null, + "RIOI_ODELAY1_ODATAIN": null, + "RIOI_ODELAY1_OFDLY0": null, + "RIOI_ODELAY1_OFDLY1": null, + "RIOI_ODELAY1_OFDLY2": null, + "RIOI_OLOGIC0_CLKDIVF": null, + "RIOI_OLOGIC0_OFB": null, + "RIOI_OLOGIC0_OQ": null, + "RIOI_OLOGIC0_TFB": null, + "RIOI_OLOGIC0_TFB_LOCAL": null, + "RIOI_OLOGIC0_TQ": null, + "RIOI_OLOGIC1_CLKDIVF": null, + "RIOI_OLOGIC1_OFB": null, + "RIOI_OLOGIC1_OQ": null, + "RIOI_OLOGIC1_TFB": null, + "RIOI_OLOGIC1_TFB_LOCAL": null, + "RIOI_OLOGIC1_TQ": null, + "RIOI_OSIN10": null, + "RIOI_OSIN11": null, + "RIOI_OSIN20": null, + "RIOI_OSIN21": null, + "RIOI_OSOUT10": null, + "RIOI_OSOUT11": null, + "RIOI_OSOUT20": null, + "RIOI_OSOUT21": null, + "RIOI_PD_INT_EN_0": null, + "RIOI_PD_INT_EN_1": null, + "RIOI_PU_INT_EN_0": null, + "RIOI_PU_INT_EN_1": null, + "RIOI_T0": null, + "RIOI_T1": null + } } diff --git a/zynq7/tile_type_R_TERM_INT.json b/zynq7/tile_type_R_TERM_INT.json index 67209e5..498c25b 100644 --- a/zynq7/tile_type_R_TERM_INT.json +++ b/zynq7/tile_type_R_TERM_INT.json @@ -2,172 +2,358 @@ "pips": {}, "sites": [], "tile_type": "R_TERM_INT", - "wires": [ - "L_TERM_INT_DQS_IOTOPHASER", - "L_TERM_INT_PHASER_TO_IO_ICLK", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV", - "L_TERM_INT_PHASER_TO_IO_OCLK", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV", - "R_TERM_INT_LH0", - "R_TERM_INT_LH1", - "R_TERM_INT_LH2", - "R_TERM_INT_LH3", - "R_TERM_INT_LH4", - "R_TERM_INT_LH5", - "R_TERM_INT_NW2A0", - "R_TERM_INT_NW2A1", - "R_TERM_INT_NW2A2", - "R_TERM_INT_NW2A3", - "R_TERM_INT_NW4A0", - "R_TERM_INT_NW4A1", - "R_TERM_INT_NW4A2", - "R_TERM_INT_NW4A3", - "R_TERM_INT_NW4END0", - "R_TERM_INT_NW4END1", - "R_TERM_INT_NW4END2", - "R_TERM_INT_NW4END3", - "R_TERM_INT_SW2A0", - "R_TERM_INT_SW2A1", - "R_TERM_INT_SW2A2", - "R_TERM_INT_SW2A3", - "R_TERM_INT_SW4A0", - "R_TERM_INT_SW4A1", - "R_TERM_INT_SW4A2", - "R_TERM_INT_SW4A3", - "R_TERM_INT_SW4END0", - "R_TERM_INT_SW4END1", - "R_TERM_INT_SW4END2", - "R_TERM_INT_SW4END3", - "R_TERM_INT_WL1END0", - "R_TERM_INT_WL1END1", - "R_TERM_INT_WL1END2", - "R_TERM_INT_WL1END3", - "R_TERM_INT_WR1END0", - "R_TERM_INT_WR1END1", - "R_TERM_INT_WR1END2", - "R_TERM_INT_WR1END3", - "R_TERM_INT_WW2A0", - "R_TERM_INT_WW2A1", - "R_TERM_INT_WW2A2", - "R_TERM_INT_WW2A3", - "R_TERM_INT_WW2END0", - "R_TERM_INT_WW2END1", - "R_TERM_INT_WW2END2", - "R_TERM_INT_WW2END3", - "R_TERM_INT_WW4A0", - "R_TERM_INT_WW4A1", - "R_TERM_INT_WW4A2", - "R_TERM_INT_WW4A3", - "R_TERM_INT_WW4B0", - "R_TERM_INT_WW4B1", - "R_TERM_INT_WW4B2", - "R_TERM_INT_WW4B3", - "R_TERM_INT_WW4C0", - "R_TERM_INT_WW4C1", - "R_TERM_INT_WW4C2", - "R_TERM_INT_WW4C3", - "R_TERM_INT_WW4END0", - "R_TERM_INT_WW4END1", - "R_TERM_INT_WW4END2", - "R_TERM_INT_WW4END3", - "TERM_INT_BLOCK_OUTS_L_B0", - "TERM_INT_BLOCK_OUTS_L_B1", - "TERM_INT_BLOCK_OUTS_L_B2", - "TERM_INT_BLOCK_OUTS_L_B3", - "TERM_INT_BYP0", - "TERM_INT_BYP1", - "TERM_INT_BYP2", - "TERM_INT_BYP3", - "TERM_INT_BYP4", - "TERM_INT_BYP5", - "TERM_INT_BYP6", - "TERM_INT_BYP7", - "TERM_INT_CLK0", - "TERM_INT_CLK1", - "TERM_INT_CTRL0", - "TERM_INT_CTRL1", - "TERM_INT_FAN0", - "TERM_INT_FAN1", - "TERM_INT_FAN2", - "TERM_INT_FAN3", - "TERM_INT_FAN4", - "TERM_INT_FAN5", - "TERM_INT_FAN6", - "TERM_INT_FAN7", - "TERM_INT_IMUX0", - "TERM_INT_IMUX1", - "TERM_INT_IMUX10", - "TERM_INT_IMUX11", - "TERM_INT_IMUX12", - "TERM_INT_IMUX13", - "TERM_INT_IMUX14", - "TERM_INT_IMUX15", - "TERM_INT_IMUX16", - "TERM_INT_IMUX17", - "TERM_INT_IMUX18", - "TERM_INT_IMUX19", - "TERM_INT_IMUX2", - "TERM_INT_IMUX20", - "TERM_INT_IMUX21", - "TERM_INT_IMUX22", - "TERM_INT_IMUX23", - "TERM_INT_IMUX24", - "TERM_INT_IMUX25", - "TERM_INT_IMUX26", - "TERM_INT_IMUX27", - "TERM_INT_IMUX28", - "TERM_INT_IMUX29", - "TERM_INT_IMUX3", - "TERM_INT_IMUX30", - "TERM_INT_IMUX31", - "TERM_INT_IMUX32", - "TERM_INT_IMUX33", - "TERM_INT_IMUX34", - "TERM_INT_IMUX35", - "TERM_INT_IMUX36", - "TERM_INT_IMUX37", - "TERM_INT_IMUX38", - "TERM_INT_IMUX39", - "TERM_INT_IMUX4", - "TERM_INT_IMUX40", - "TERM_INT_IMUX41", - "TERM_INT_IMUX42", - "TERM_INT_IMUX43", - "TERM_INT_IMUX44", - "TERM_INT_IMUX45", - "TERM_INT_IMUX46", - "TERM_INT_IMUX47", - "TERM_INT_IMUX5", - "TERM_INT_IMUX6", - "TERM_INT_IMUX7", - "TERM_INT_IMUX8", - "TERM_INT_IMUX9", - "TERM_INT_LOGIC_OUTS_L_B0", - "TERM_INT_LOGIC_OUTS_L_B1", - "TERM_INT_LOGIC_OUTS_L_B10", - "TERM_INT_LOGIC_OUTS_L_B11", - "TERM_INT_LOGIC_OUTS_L_B12", - "TERM_INT_LOGIC_OUTS_L_B13", - "TERM_INT_LOGIC_OUTS_L_B14", - "TERM_INT_LOGIC_OUTS_L_B15", - "TERM_INT_LOGIC_OUTS_L_B16", - "TERM_INT_LOGIC_OUTS_L_B17", - "TERM_INT_LOGIC_OUTS_L_B18", - "TERM_INT_LOGIC_OUTS_L_B19", - "TERM_INT_LOGIC_OUTS_L_B2", - "TERM_INT_LOGIC_OUTS_L_B20", - "TERM_INT_LOGIC_OUTS_L_B21", - "TERM_INT_LOGIC_OUTS_L_B22", - "TERM_INT_LOGIC_OUTS_L_B23", - "TERM_INT_LOGIC_OUTS_L_B3", - "TERM_INT_LOGIC_OUTS_L_B4", - "TERM_INT_LOGIC_OUTS_L_B5", - "TERM_INT_LOGIC_OUTS_L_B6", - "TERM_INT_LOGIC_OUTS_L_B7", - "TERM_INT_LOGIC_OUTS_L_B8", - "TERM_INT_LOGIC_OUTS_L_B9", - "TERM_INT_MONITOR_N", - "TERM_INT_MONITOR_P" - ] + "wires": { + "L_TERM_INT_DQS_IOTOPHASER": null, + "L_TERM_INT_PHASER_TO_IO_ICLK": null, + "L_TERM_INT_PHASER_TO_IO_ICLKDIV": null, + "L_TERM_INT_PHASER_TO_IO_OCLK": null, + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90": null, + "L_TERM_INT_PHASER_TO_IO_OCLKDIV": null, + "R_TERM_INT_LH0": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH1": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH2": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH3": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH4": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH5": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_NW2A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW2A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW2A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW2A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW2A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW2A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW2A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW2A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WL1END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WL1END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WL1END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WL1END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WR1END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WR1END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WR1END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WR1END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4B0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4B1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4B2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4B3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4C0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4C1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4C2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4C3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4END3": { + "cap": "4.200", + "res": "87.290" + }, + "TERM_INT_BLOCK_OUTS_L_B0": null, + "TERM_INT_BLOCK_OUTS_L_B1": null, + "TERM_INT_BLOCK_OUTS_L_B2": null, + "TERM_INT_BLOCK_OUTS_L_B3": null, + "TERM_INT_BYP0": null, + "TERM_INT_BYP1": null, + "TERM_INT_BYP2": null, + "TERM_INT_BYP3": null, + "TERM_INT_BYP4": null, + "TERM_INT_BYP5": null, + "TERM_INT_BYP6": null, + "TERM_INT_BYP7": null, + "TERM_INT_CLK0": null, + "TERM_INT_CLK1": null, + "TERM_INT_CTRL0": null, + "TERM_INT_CTRL1": null, + "TERM_INT_FAN0": null, + "TERM_INT_FAN1": null, + "TERM_INT_FAN2": null, + "TERM_INT_FAN3": null, + "TERM_INT_FAN4": null, + "TERM_INT_FAN5": null, + "TERM_INT_FAN6": null, + "TERM_INT_FAN7": null, + "TERM_INT_IMUX0": null, + "TERM_INT_IMUX1": null, + "TERM_INT_IMUX10": null, + "TERM_INT_IMUX11": null, + "TERM_INT_IMUX12": null, + "TERM_INT_IMUX13": null, + "TERM_INT_IMUX14": null, + "TERM_INT_IMUX15": null, + "TERM_INT_IMUX16": null, + "TERM_INT_IMUX17": null, + "TERM_INT_IMUX18": null, + "TERM_INT_IMUX19": null, + "TERM_INT_IMUX2": null, + "TERM_INT_IMUX20": null, + "TERM_INT_IMUX21": null, + "TERM_INT_IMUX22": null, + "TERM_INT_IMUX23": null, + "TERM_INT_IMUX24": null, + "TERM_INT_IMUX25": null, + "TERM_INT_IMUX26": null, + "TERM_INT_IMUX27": null, + "TERM_INT_IMUX28": null, + "TERM_INT_IMUX29": null, + "TERM_INT_IMUX3": null, + "TERM_INT_IMUX30": null, + "TERM_INT_IMUX31": null, + "TERM_INT_IMUX32": null, + "TERM_INT_IMUX33": null, + "TERM_INT_IMUX34": null, + "TERM_INT_IMUX35": null, + "TERM_INT_IMUX36": null, + "TERM_INT_IMUX37": null, + "TERM_INT_IMUX38": null, + "TERM_INT_IMUX39": null, + "TERM_INT_IMUX4": null, + "TERM_INT_IMUX40": null, + "TERM_INT_IMUX41": null, + "TERM_INT_IMUX42": null, + "TERM_INT_IMUX43": null, + "TERM_INT_IMUX44": null, + "TERM_INT_IMUX45": null, + "TERM_INT_IMUX46": null, + "TERM_INT_IMUX47": null, + "TERM_INT_IMUX5": null, + "TERM_INT_IMUX6": null, + "TERM_INT_IMUX7": null, + "TERM_INT_IMUX8": null, + "TERM_INT_IMUX9": null, + "TERM_INT_LOGIC_OUTS_L_B0": null, + "TERM_INT_LOGIC_OUTS_L_B1": null, + "TERM_INT_LOGIC_OUTS_L_B10": null, + "TERM_INT_LOGIC_OUTS_L_B11": null, + "TERM_INT_LOGIC_OUTS_L_B12": null, + "TERM_INT_LOGIC_OUTS_L_B13": null, + "TERM_INT_LOGIC_OUTS_L_B14": null, + "TERM_INT_LOGIC_OUTS_L_B15": null, + "TERM_INT_LOGIC_OUTS_L_B16": null, + "TERM_INT_LOGIC_OUTS_L_B17": null, + "TERM_INT_LOGIC_OUTS_L_B18": null, + "TERM_INT_LOGIC_OUTS_L_B19": null, + "TERM_INT_LOGIC_OUTS_L_B2": null, + "TERM_INT_LOGIC_OUTS_L_B20": null, + "TERM_INT_LOGIC_OUTS_L_B21": null, + "TERM_INT_LOGIC_OUTS_L_B22": null, + "TERM_INT_LOGIC_OUTS_L_B23": null, + "TERM_INT_LOGIC_OUTS_L_B3": null, + "TERM_INT_LOGIC_OUTS_L_B4": null, + "TERM_INT_LOGIC_OUTS_L_B5": null, + "TERM_INT_LOGIC_OUTS_L_B6": null, + "TERM_INT_LOGIC_OUTS_L_B7": null, + "TERM_INT_LOGIC_OUTS_L_B8": null, + "TERM_INT_LOGIC_OUTS_L_B9": null, + "TERM_INT_MONITOR_N": null, + "TERM_INT_MONITOR_P": null + } } diff --git a/zynq7/tile_type_TERM_CMT.json b/zynq7/tile_type_TERM_CMT.json index 3790f7c..c640568 100644 --- a/zynq7/tile_type_TERM_CMT.json +++ b/zynq7/tile_type_TERM_CMT.json @@ -2,10 +2,10 @@ "pips": {}, "sites": [], "tile_type": "TERM_CMT", - "wires": [ - "TERM_CMT_FREQ_REF_NS0", - "TERM_CMT_FREQ_REF_NS1", - "TERM_CMT_FREQ_REF_NS2", - "TERM_CMT_FREQ_REF_NS3" - ] + "wires": { + "TERM_CMT_FREQ_REF_NS0": null, + "TERM_CMT_FREQ_REF_NS1": null, + "TERM_CMT_FREQ_REF_NS2": null, + "TERM_CMT_FREQ_REF_NS3": null + } } diff --git a/zynq7/tile_type_T_TERM_INT.json b/zynq7/tile_type_T_TERM_INT.json index 57ff508..0e326d9 100644 --- a/zynq7/tile_type_T_TERM_INT.json +++ b/zynq7/tile_type_T_TERM_INT.json @@ -2,123 +2,213 @@ "pips": {}, "sites": [], "tile_type": "T_TERM_INT", - "wires": [ - "T_TERM_INT_UTURN_LV_R16", - "T_TERM_INT_UTURN_LV_R17", - "T_TERM_INT_UTURN_LV_R2", - "T_TERM_INT_UTURN_LV_R3", - "T_TERM_INT_UTURN_LV_R4", - "T_TERM_INT_UTURN_LV_R5", - "T_TERM_INT_UTURN_LV_R6", - "T_TERM_INT_UTURN_LV_R7", - "T_TERM_INT_UTURN_LV_R9", - "T_TERM_UTURN_INT_ER1BEG_S0", - "T_TERM_UTURN_INT_ER1END3", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", - "T_TERM_UTURN_INT_LVB0", - "T_TERM_UTURN_INT_LVB1", - "T_TERM_UTURN_INT_LVB2", - "T_TERM_UTURN_INT_LVB3", - "T_TERM_UTURN_INT_LVB4", - "T_TERM_UTURN_INT_LVB5", - "T_TERM_UTURN_INT_LVB_L0", - "T_TERM_UTURN_INT_LVB_L1", - "T_TERM_UTURN_INT_LVB_L2", - "T_TERM_UTURN_INT_LVB_L3", - "T_TERM_UTURN_INT_LVB_L4", - "T_TERM_UTURN_INT_LVB_L5", - "T_TERM_UTURN_INT_LV_L16", - "T_TERM_UTURN_INT_LV_L17", - "T_TERM_UTURN_INT_LV_L2", - "T_TERM_UTURN_INT_LV_L3", - "T_TERM_UTURN_INT_LV_L4", - "T_TERM_UTURN_INT_LV_L5", - "T_TERM_UTURN_INT_LV_L6", - "T_TERM_UTURN_INT_LV_L7", - "T_TERM_UTURN_INT_LV_L9", - "T_TERM_UTURN_INT_SE2A0", - "T_TERM_UTURN_INT_SE2A1", - "T_TERM_UTURN_INT_SE2A2", - "T_TERM_UTURN_INT_SE2A3", - "T_TERM_UTURN_INT_SE6B0", - "T_TERM_UTURN_INT_SE6B1", - "T_TERM_UTURN_INT_SE6B2", - "T_TERM_UTURN_INT_SE6B3", - "T_TERM_UTURN_INT_SE6C0", - "T_TERM_UTURN_INT_SE6C1", - "T_TERM_UTURN_INT_SE6C2", - "T_TERM_UTURN_INT_SE6C3", - "T_TERM_UTURN_INT_SE6D0", - "T_TERM_UTURN_INT_SE6D1", - "T_TERM_UTURN_INT_SE6D2", - "T_TERM_UTURN_INT_SE6D3", - "T_TERM_UTURN_INT_SE6E0", - "T_TERM_UTURN_INT_SE6E1", - "T_TERM_UTURN_INT_SE6E2", - "T_TERM_UTURN_INT_SE6E3", - "T_TERM_UTURN_INT_SL1END0", - "T_TERM_UTURN_INT_SL1END1", - "T_TERM_UTURN_INT_SL1END2", - "T_TERM_UTURN_INT_SL1END3", - "T_TERM_UTURN_INT_SR1END1", - "T_TERM_UTURN_INT_SR1END2", - "T_TERM_UTURN_INT_SR1END3", - "T_TERM_UTURN_INT_SS2A0", - "T_TERM_UTURN_INT_SS2A1", - "T_TERM_UTURN_INT_SS2A2", - "T_TERM_UTURN_INT_SS2A3", - "T_TERM_UTURN_INT_SS2END0", - "T_TERM_UTURN_INT_SS2END1", - "T_TERM_UTURN_INT_SS2END2", - "T_TERM_UTURN_INT_SS2END3", - "T_TERM_UTURN_INT_SS6A0", - "T_TERM_UTURN_INT_SS6A1", - "T_TERM_UTURN_INT_SS6A2", - "T_TERM_UTURN_INT_SS6A3", - "T_TERM_UTURN_INT_SS6B0", - "T_TERM_UTURN_INT_SS6B1", - "T_TERM_UTURN_INT_SS6B2", - "T_TERM_UTURN_INT_SS6B3", - "T_TERM_UTURN_INT_SS6C0", - "T_TERM_UTURN_INT_SS6C1", - "T_TERM_UTURN_INT_SS6C2", - "T_TERM_UTURN_INT_SS6C3", - "T_TERM_UTURN_INT_SS6D0", - "T_TERM_UTURN_INT_SS6D1", - "T_TERM_UTURN_INT_SS6D2", - "T_TERM_UTURN_INT_SS6D3", - "T_TERM_UTURN_INT_SS6E0", - "T_TERM_UTURN_INT_SS6E1", - "T_TERM_UTURN_INT_SS6E2", - "T_TERM_UTURN_INT_SS6E3", - "T_TERM_UTURN_INT_SS6END0", - "T_TERM_UTURN_INT_SS6END1", - "T_TERM_UTURN_INT_SS6END2", - "T_TERM_UTURN_INT_SS6END3", - "T_TERM_UTURN_INT_SW2A0", - "T_TERM_UTURN_INT_SW2A1", - "T_TERM_UTURN_INT_SW2A2", - "T_TERM_UTURN_INT_SW2A3", - "T_TERM_UTURN_INT_SW6B0", - "T_TERM_UTURN_INT_SW6B1", - "T_TERM_UTURN_INT_SW6B2", - "T_TERM_UTURN_INT_SW6B3", - "T_TERM_UTURN_INT_SW6C0", - "T_TERM_UTURN_INT_SW6C1", - "T_TERM_UTURN_INT_SW6C2", - "T_TERM_UTURN_INT_SW6C3", - "T_TERM_UTURN_INT_SW6D0", - "T_TERM_UTURN_INT_SW6D1", - "T_TERM_UTURN_INT_SW6D2", - "T_TERM_UTURN_INT_SW6D3", - "T_TERM_UTURN_INT_SW6E0", - "T_TERM_UTURN_INT_SW6E1", - "T_TERM_UTURN_INT_SW6E2", - "T_TERM_UTURN_INT_SW6E3", - "T_TERM_UTURN_INT_WR1BEG_S0", - "T_TERM_UTURN_INT_WR1END_S1_0" - ] + "wires": { + "T_TERM_INT_UTURN_LV_R16": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_INT_UTURN_LV_R17": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_INT_UTURN_LV_R2": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_INT_UTURN_LV_R3": { + "cap": "13.000", + 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b/zynq7/tile_type_VBRK.json index c0d12e3..dee41c6 100644 --- a/zynq7/tile_type_VBRK.json +++ b/zynq7/tile_type_VBRK.json @@ -2,132 +2,495 @@ "pips": {}, "sites": [], "tile_type": "VBRK", - "wires": [ - "VBRK_EE2A0", - "VBRK_EE2A1", - "VBRK_EE2A2", - "VBRK_EE2A3", - "VBRK_EE2BEG0", - "VBRK_EE2BEG1", - "VBRK_EE2BEG2", - "VBRK_EE2BEG3", - "VBRK_EE4A0", - "VBRK_EE4A1", - "VBRK_EE4A2", - "VBRK_EE4A3", - "VBRK_EE4B0", - "VBRK_EE4B1", - "VBRK_EE4B2", - "VBRK_EE4B3", - "VBRK_EE4BEG0", - "VBRK_EE4BEG1", - "VBRK_EE4BEG2", - "VBRK_EE4BEG3", - "VBRK_EE4C0", - "VBRK_EE4C1", - "VBRK_EE4C2", - "VBRK_EE4C3", - "VBRK_EL1BEG0", - "VBRK_EL1BEG1", - "VBRK_EL1BEG2", - "VBRK_EL1BEG3", - "VBRK_ER1BEG0", - "VBRK_ER1BEG1", - "VBRK_ER1BEG2", - "VBRK_ER1BEG3", - "VBRK_LH1", - "VBRK_LH10", - "VBRK_LH11", - "VBRK_LH12", - "VBRK_LH2", - "VBRK_LH3", - "VBRK_LH4", - "VBRK_LH5", - "VBRK_LH6", - "VBRK_LH7", - "VBRK_LH8", - "VBRK_LH9", - "VBRK_MONITOR_N", - "VBRK_MONITOR_P", - "VBRK_NE2A0", - "VBRK_NE2A1", - "VBRK_NE2A2", - "VBRK_NE2A3", - "VBRK_NE4BEG0", - "VBRK_NE4BEG1", - "VBRK_NE4BEG2", - "VBRK_NE4BEG3", - "VBRK_NE4C0", - "VBRK_NE4C1", - "VBRK_NE4C2", - "VBRK_NE4C3", - "VBRK_NW2A0", - "VBRK_NW2A1", - "VBRK_NW2A2", - "VBRK_NW2A3", - "VBRK_NW4A0", - "VBRK_NW4A1", - "VBRK_NW4A2", - "VBRK_NW4A3", - "VBRK_NW4END0", - "VBRK_NW4END1", - "VBRK_NW4END2", - "VBRK_NW4END3", - "VBRK_SE2A0", - "VBRK_SE2A1", - "VBRK_SE2A2", - "VBRK_SE2A3", - "VBRK_SE4BEG0", - "VBRK_SE4BEG1", - "VBRK_SE4BEG2", - "VBRK_SE4BEG3", - "VBRK_SE4C0", - "VBRK_SE4C1", - "VBRK_SE4C2", - "VBRK_SE4C3", - "VBRK_SW2A0", - "VBRK_SW2A1", - "VBRK_SW2A2", - "VBRK_SW2A3", - "VBRK_SW4A0", - "VBRK_SW4A1", - "VBRK_SW4A2", - "VBRK_SW4A3", - "VBRK_SW4END0", - "VBRK_SW4END1", - "VBRK_SW4END2", - "VBRK_SW4END3", - "VBRK_WL1END0", - "VBRK_WL1END1", - "VBRK_WL1END2", - "VBRK_WL1END3", - "VBRK_WR1END0", - "VBRK_WR1END1", - "VBRK_WR1END2", - "VBRK_WR1END3", - "VBRK_WW2A0", - "VBRK_WW2A1", - "VBRK_WW2A2", - "VBRK_WW2A3", - "VBRK_WW2END0", - "VBRK_WW2END1", - "VBRK_WW2END2", - "VBRK_WW2END3", - "VBRK_WW4A0", - "VBRK_WW4A1", - "VBRK_WW4A2", - "VBRK_WW4A3", - "VBRK_WW4B0", - "VBRK_WW4B1", - "VBRK_WW4B2", - "VBRK_WW4B3", - "VBRK_WW4C0", - "VBRK_WW4C1", - "VBRK_WW4C2", - "VBRK_WW4C3", - "VBRK_WW4END0", - "VBRK_WW4END1", - "VBRK_WW4END2", - "VBRK_WW4END3" - ] + "wires": { + "VBRK_EE2A0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_EE2A1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_EE2A2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_EE2A3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_EE2BEG0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_EE2BEG1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_EE2BEG2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_EE2BEG3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_EE4A0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_EE4A1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_EE4A2": { + "cap": "1.620", + "res": "12.110" + }, + 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}, + "VBRK_NE2A2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NE2A3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NE4BEG0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NE4BEG1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NE4BEG2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NE4BEG3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NE4C0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NE4C1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NE4C2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NE4C3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NW2A0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NW2A1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NW2A2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NW2A3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NW4A0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NW4A1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NW4A2": { + "cap": "1.620", + "res": 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"VFRAME_BLOCK_OUTS_B2", - "VFRAME_BLOCK_OUTS_B3", - "VFRAME_BYP0", - "VFRAME_BYP1", - "VFRAME_BYP2", - "VFRAME_BYP3", - "VFRAME_BYP4", - "VFRAME_BYP5", - "VFRAME_BYP6", - "VFRAME_BYP7", - "VFRAME_CLK0", - "VFRAME_CLK1", - "VFRAME_CTRL0", - "VFRAME_CTRL1", - "VFRAME_EE2A0", - "VFRAME_EE2A1", - "VFRAME_EE2A2", - "VFRAME_EE2A3", - "VFRAME_EE2BEG0", - "VFRAME_EE2BEG1", - "VFRAME_EE2BEG2", - "VFRAME_EE2BEG3", - "VFRAME_EE4A0", - "VFRAME_EE4A1", - "VFRAME_EE4A2", - "VFRAME_EE4A3", - "VFRAME_EE4B0", - "VFRAME_EE4B1", - "VFRAME_EE4B2", - "VFRAME_EE4B3", - "VFRAME_EE4BEG0", - "VFRAME_EE4BEG1", - "VFRAME_EE4BEG2", - "VFRAME_EE4BEG3", - "VFRAME_EE4C0", - "VFRAME_EE4C1", - "VFRAME_EE4C2", - "VFRAME_EE4C3", - "VFRAME_EL1BEG0", - "VFRAME_EL1BEG1", - "VFRAME_EL1BEG2", - "VFRAME_EL1BEG3", - "VFRAME_ER1BEG0", - "VFRAME_ER1BEG1", - "VFRAME_ER1BEG2", - "VFRAME_ER1BEG3", - "VFRAME_FAN0", - "VFRAME_FAN1", - "VFRAME_FAN2", - "VFRAME_FAN3", - "VFRAME_FAN4", - "VFRAME_FAN5", - "VFRAME_FAN6", - "VFRAME_FAN7", - "VFRAME_IMUX0", - "VFRAME_IMUX1", - "VFRAME_IMUX10", - "VFRAME_IMUX11", - "VFRAME_IMUX12", - "VFRAME_IMUX13", - "VFRAME_IMUX14", - "VFRAME_IMUX15", - "VFRAME_IMUX16", - "VFRAME_IMUX17", - "VFRAME_IMUX18", - "VFRAME_IMUX19", - "VFRAME_IMUX2", - "VFRAME_IMUX20", - "VFRAME_IMUX21", - "VFRAME_IMUX22", - "VFRAME_IMUX23", - "VFRAME_IMUX24", - "VFRAME_IMUX25", - "VFRAME_IMUX26", - "VFRAME_IMUX27", - "VFRAME_IMUX28", - "VFRAME_IMUX29", - "VFRAME_IMUX3", - "VFRAME_IMUX30", - "VFRAME_IMUX31", - "VFRAME_IMUX32", - "VFRAME_IMUX33", - "VFRAME_IMUX34", - "VFRAME_IMUX35", - "VFRAME_IMUX36", - "VFRAME_IMUX37", - "VFRAME_IMUX38", - "VFRAME_IMUX39", - "VFRAME_IMUX4", - "VFRAME_IMUX40", - "VFRAME_IMUX41", - "VFRAME_IMUX42", - "VFRAME_IMUX43", - "VFRAME_IMUX44", - "VFRAME_IMUX45", - "VFRAME_IMUX46", - "VFRAME_IMUX47", - "VFRAME_IMUX5", - "VFRAME_IMUX6", - "VFRAME_IMUX7", - "VFRAME_IMUX8", - "VFRAME_IMUX9", - "VFRAME_LH1", - "VFRAME_LH10", - "VFRAME_LH11", - "VFRAME_LH12", - "VFRAME_LH2", - "VFRAME_LH3", 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"VFRAME_NE4C3", - "VFRAME_NW2A0", - "VFRAME_NW2A1", - "VFRAME_NW2A2", - "VFRAME_NW2A3", - "VFRAME_NW4A0", - "VFRAME_NW4A1", - "VFRAME_NW4A2", - "VFRAME_NW4A3", - "VFRAME_NW4END0", - "VFRAME_NW4END1", - "VFRAME_NW4END2", - "VFRAME_NW4END3", - "VFRAME_SE2A0", - "VFRAME_SE2A1", - "VFRAME_SE2A2", - "VFRAME_SE2A3", - "VFRAME_SE4BEG0", - "VFRAME_SE4BEG1", - "VFRAME_SE4BEG2", - "VFRAME_SE4BEG3", - "VFRAME_SE4C0", - "VFRAME_SE4C1", - "VFRAME_SE4C2", - "VFRAME_SE4C3", - "VFRAME_SW2A0", - "VFRAME_SW2A1", - "VFRAME_SW2A2", - "VFRAME_SW2A3", - "VFRAME_SW4A0", - "VFRAME_SW4A1", - "VFRAME_SW4A2", - "VFRAME_SW4A3", - "VFRAME_SW4END0", - "VFRAME_SW4END1", - "VFRAME_SW4END2", - "VFRAME_SW4END3", - "VFRAME_WL1END0", - "VFRAME_WL1END1", - "VFRAME_WL1END2", - "VFRAME_WL1END3", - "VFRAME_WR1END0", - "VFRAME_WR1END1", - "VFRAME_WR1END2", - "VFRAME_WR1END3", - "VFRAME_WW2A0", - "VFRAME_WW2A1", - "VFRAME_WW2A2", - "VFRAME_WW2A3", - "VFRAME_WW2END0", - "VFRAME_WW2END1", - "VFRAME_WW2END2", - "VFRAME_WW2END3", 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"VFRAME_SW2A2": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_SW2A3": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_SW4A0": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_SW4A1": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_SW4A2": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_SW4A3": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_SW4END0": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_SW4END1": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_SW4END2": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_SW4END3": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WL1END0": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WL1END1": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WL1END2": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WL1END3": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WR1END0": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WR1END1": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WR1END2": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WR1END3": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW2A0": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW2A1": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW2A2": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW2A3": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW2END0": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW2END1": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW2END2": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW2END3": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4A0": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4A1": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4A2": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4A3": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4B0": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4B1": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4B2": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4B3": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4C0": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4C1": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4C2": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4C3": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4END0": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4END1": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4END2": { + "cap": "5.840", + "res": "43.670" + }, + "VFRAME_WW4END3": { + "cap": "5.840", + "res": "43.670" + } + } } diff --git a/zynq7/tilegrid.json b/zynq7/tilegrid.json index 739671b..0c77fc8 100644 --- a/zynq7/tilegrid.json +++ b/zynq7/tilegrid.json @@ -4513,7 +4513,14 @@ "type": "CFG_CENTER_BOT" }, "CFG_CENTER_MID_X67Y32": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00401100", + "frames": 30, + "offset": 0, + "words": 101 + } + }, "grid_x": 67, "grid_y": 72, "sites": { diff --git a/zynq7/timings/CMT_TOP_L_LOWER_B.sdf b/zynq7/timings/CMT_TOP_L_LOWER_B.sdf index 7c94cb9..ff5265d 100644 --- a/zynq7/timings/CMT_TOP_L_LOWER_B.sdf +++ b/zynq7/timings/CMT_TOP_L_LOWER_B.sdf @@ -79,6 +79,86 @@ ) ) ) + (CELL + (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_BUF_IN") + (INSTANCE MMCME2_ADV) + (DELAY + (ABSOLUTE + (IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240)) + (IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240)) + ) + ) + ) + (CELL + (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_EXTERNAL") + (INSTANCE MMCME2_ADV) + (DELAY + (ABSOLUTE + (IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000)) + (IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000)) + ) + ) + ) + (CELL + (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_INTERNAL") + (INSTANCE MMCME2_ADV) + (DELAY + (ABSOLUTE + (IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088)) + (IOPATH COMPENSATION CLKOUT4 (0.050::0.053)(0.083::0.088)) + ) + ) + ) + (CELL + (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_FALSE_ZHOLD") + (INSTANCE MMCME2_ADV) + (DELAY + (ABSOLUTE + (IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000)) + (IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000)) + ) + ) + ) + (CELL + (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_BUF_IN") + (INSTANCE MMCME2_ADV) + (DELAY + (ABSOLUTE + (IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240)) + (IOPATH COMPENSATION CLKOUT4 (0.255::-0.260)(0.433::-0.240)) + ) + ) + ) + (CELL + (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_EXTERNAL") + (INSTANCE MMCME2_ADV) + (DELAY + (ABSOLUTE + (IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000)) + (IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000)) + ) + ) + ) + (CELL + (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_INTERNAL") + (INSTANCE MMCME2_ADV) + (DELAY + (ABSOLUTE + (IOPATH COMPENSATION CLKOUT4 (0.263::0.279)(0.492::0.522)) + (IOPATH COMPENSATION CLKOUT4 (0.263::0.279)(0.492::0.522)) + ) + ) + ) + (CELL + (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_CLKOUT4_CASCADE_TRUE_ZHOLD") + (INSTANCE MMCME2_ADV) + (DELAY + (ABSOLUTE + (IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000)) + (IOPATH COMPENSATION CLKOUT4 (0.000::0.000)(0.000::0.000)) + ) + ) + ) (CELL (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_EXTERNAL") (INSTANCE MMCME2_ADV) @@ -111,46 +191,6 @@ ) ) ) - (CELL - (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_BUF_IN") - (INSTANCE MMCME2_ADV) - (DELAY - (ABSOLUTE - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240)) - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240)) - ) - ) - ) - (CELL - (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_EXTERNAL") - (INSTANCE MMCME2_ADV) - (DELAY - (ABSOLUTE - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000)) - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000)) - ) - ) - ) - (CELL - (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_INTERNAL") - (INSTANCE MMCME2_ADV) - (DELAY - (ABSOLUTE - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.050::0.053)(0.083::0.088)) - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.050::0.053)(0.083::0.088)) - ) - ) - ) - (CELL - (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_FALSE_COMPENSATION_ZHOLD") - (INSTANCE MMCME2_ADV) - (DELAY - (ABSOLUTE - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000)) - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000)) - ) - ) - ) (CELL (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_INTERNAL") (INSTANCE MMCME2_ADV) @@ -183,46 +223,6 @@ ) ) ) - (CELL - (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_BUF_IN") - (INSTANCE MMCME2_ADV) - (DELAY - (ABSOLUTE - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240)) - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.255::-0.260)(0.433::-0.240)) - ) - ) - ) - (CELL - (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_EXTERNAL") - (INSTANCE MMCME2_ADV) - (DELAY - (ABSOLUTE - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000)) - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000)) - ) - ) - ) - (CELL - (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_INTERNAL") - (INSTANCE MMCME2_ADV) - (DELAY - (ABSOLUTE - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.263::0.279)(0.492::0.522)) - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.263::0.279)(0.492::0.522)) - ) - ) - ) - (CELL - (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_TRUE_COMPENSATION_ZHOLD") - (INSTANCE MMCME2_ADV) - (DELAY - (ABSOLUTE - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000)) - (IOPATH CLKOUT4_CASCADE CLKOUT4 (0.000::0.000)(0.000::0.000)) - ) - ) - ) (CELL (CELLTYPE "MMCME2_ADV_MMCME2_ADVMMCME2_ADV_ZHOLD") (INSTANCE MMCME2_ADV) diff --git a/zynq7/timings/RIOI3.sdf b/zynq7/timings/RIOI3.sdf index 2deb4e9..e2758ff 100644 --- a/zynq7/timings/RIOI3.sdf +++ b/zynq7/timings/RIOI3.sdf @@ -109,6 +109,13 @@ (SETUP D (posedge CK) (0.091::0.105)) ) ) + (CELL + (CELLTYPE "ILOGICE3_IFF_HOLD") + (INSTANCE ILOGICE3) + (TIMINGCHECK + (REMOVAL SR (posedge CK) (-0.409::-0.357)) + ) + ) (CELL (CELLTYPE "ILOGICE3_IFF_LAT") (INSTANCE ILOGICE3) @@ -149,10 +156,10 @@ ) ) (CELL - (CELLTYPE "ILOGICE3_IFF_REMOV") + (CELLTYPE "ILOGICE3_IFF_RECOV") (INSTANCE ILOGICE3) (TIMINGCHECK - (HOLD SR (posedge CK) (-0.409::-0.357)) + (SETUP SR (posedge CK) (0.518::0.596)) ) ) (CELL @@ -167,13 +174,6 @@ ) ) ) - (CELL - (CELLTYPE "ILOGICE3_IFF_SETUP") - (INSTANCE ILOGICE3) - (TIMINGCHECK - (RECOVERY SR (posedge CK) (0.518::0.596)) - ) - ) (CELL (CELLTYPE "SELMUX2_1") (INSTANCE ILOGICE3) diff --git a/zynq7/timings/RIOI3_SING.sdf b/zynq7/timings/RIOI3_SING.sdf index 2deb4e9..e2758ff 100644 --- a/zynq7/timings/RIOI3_SING.sdf +++ b/zynq7/timings/RIOI3_SING.sdf @@ -109,6 +109,13 @@ (SETUP D (posedge CK) (0.091::0.105)) ) ) + (CELL + (CELLTYPE "ILOGICE3_IFF_HOLD") + (INSTANCE ILOGICE3) + (TIMINGCHECK + (REMOVAL SR (posedge CK) (-0.409::-0.357)) + ) + ) (CELL (CELLTYPE "ILOGICE3_IFF_LAT") (INSTANCE ILOGICE3) @@ -149,10 +156,10 @@ ) ) (CELL - (CELLTYPE "ILOGICE3_IFF_REMOV") + (CELLTYPE "ILOGICE3_IFF_RECOV") (INSTANCE ILOGICE3) (TIMINGCHECK - (HOLD SR (posedge CK) (-0.409::-0.357)) + (SETUP SR (posedge CK) (0.518::0.596)) ) ) (CELL @@ -167,13 +174,6 @@ ) ) ) - (CELL - (CELLTYPE "ILOGICE3_IFF_SETUP") - (INSTANCE ILOGICE3) - (TIMINGCHECK - (RECOVERY SR (posedge CK) (0.518::0.596)) - ) - ) (CELL (CELLTYPE "SELMUX2_1") (INSTANCE ILOGICE3) diff --git a/zynq7/timings/RIOI3_TBYTESRC.sdf b/zynq7/timings/RIOI3_TBYTESRC.sdf index 2deb4e9..e2758ff 100644 --- a/zynq7/timings/RIOI3_TBYTESRC.sdf +++ b/zynq7/timings/RIOI3_TBYTESRC.sdf @@ -109,6 +109,13 @@ (SETUP D (posedge CK) (0.091::0.105)) ) ) + (CELL + (CELLTYPE "ILOGICE3_IFF_HOLD") + (INSTANCE ILOGICE3) + (TIMINGCHECK + (REMOVAL SR (posedge CK) (-0.409::-0.357)) + ) + ) (CELL (CELLTYPE "ILOGICE3_IFF_LAT") (INSTANCE ILOGICE3) @@ -149,10 +156,10 @@ ) ) (CELL - (CELLTYPE "ILOGICE3_IFF_REMOV") + (CELLTYPE "ILOGICE3_IFF_RECOV") (INSTANCE ILOGICE3) (TIMINGCHECK - (HOLD SR (posedge CK) (-0.409::-0.357)) + (SETUP SR (posedge CK) (0.518::0.596)) ) ) (CELL @@ -167,13 +174,6 @@ ) ) ) - (CELL - (CELLTYPE "ILOGICE3_IFF_SETUP") - (INSTANCE ILOGICE3) - (TIMINGCHECK - (RECOVERY SR (posedge CK) (0.518::0.596)) - ) - ) (CELL (CELLTYPE "SELMUX2_1") (INSTANCE ILOGICE3) diff --git a/zynq7/timings/RIOI3_TBYTETERM.sdf b/zynq7/timings/RIOI3_TBYTETERM.sdf index 2deb4e9..e2758ff 100644 --- a/zynq7/timings/RIOI3_TBYTETERM.sdf +++ b/zynq7/timings/RIOI3_TBYTETERM.sdf @@ -109,6 +109,13 @@ (SETUP D (posedge CK) (0.091::0.105)) ) ) + (CELL + (CELLTYPE "ILOGICE3_IFF_HOLD") + (INSTANCE ILOGICE3) + (TIMINGCHECK + (REMOVAL SR (posedge CK) (-0.409::-0.357)) + ) + ) (CELL (CELLTYPE "ILOGICE3_IFF_LAT") (INSTANCE ILOGICE3) @@ -149,10 +156,10 @@ ) ) (CELL - (CELLTYPE "ILOGICE3_IFF_REMOV") + (CELLTYPE "ILOGICE3_IFF_RECOV") (INSTANCE ILOGICE3) (TIMINGCHECK - (HOLD SR (posedge CK) (-0.409::-0.357)) + (SETUP SR (posedge CK) (0.518::0.596)) ) ) (CELL @@ -167,13 +174,6 @@ ) ) ) - (CELL - (CELLTYPE "ILOGICE3_IFF_SETUP") - (INSTANCE ILOGICE3) - (TIMINGCHECK - (RECOVERY SR (posedge CK) (0.518::0.596)) - ) - ) (CELL (CELLTYPE "SELMUX2_1") (INSTANCE ILOGICE3) diff --git a/zynq7/timings/slicel.sdf b/zynq7/timings/slicel.sdf index e260de0..d17246b 100644 --- a/zynq7/timings/slicel.sdf +++ b/zynq7/timings/slicel.sdf @@ -1,24 +1,197 @@ - (DELAYFILE (SDFVERSION "3.0") (TIMESCALE 1ps) + (CELL + (CELLTYPE "CARRY4") + (INSTANCE SLICEL) + (DELAY + (ABSOLUTE + (IOPATH CIN CO0 (0.076::0.1)(0.206::0.271)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN CO1 (0.045::0.056)(0.127::0.157)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN CO2 (0.065::0.081)(0.184::0.228)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN CO3 (0.039::0.049)(0.092::0.114)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN O0 (0.054::0.08)(0.15::0.222)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN O1 (0.091::0.113)(0.269::0.334)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN O2 (0.065::0.081)(0.192::0.239)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN O3 (0.09::0.112)(0.252::0.313)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT CO0 (0.165::0.206)(0.432::0.536)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT CO1 (0.144::0.18)(0.398::0.494)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT CO2 (0.169::0.21)(0.477::0.592)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT CO3 (0.173::0.215)(0.467::0.58)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O0 (0.147::0.183)(0.388::0.482)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O1 (0.176::0.219)(0.482::0.598)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O2 (0.167::0.208)(0.471::0.584)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O3 (0.19::0.236)(0.518::0.642)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S0 CO0 (0.089::0.118)(0.258::0.34)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S0 CO1 (0.118::0.156)(0.329::0.433)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S0 CO2 (0.144::0.19)(0.389::0.512)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S0 CO3 (0.142::0.187)(0.386::0.508)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S0 O0 (0.06::0.079)(0.17::0.223)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S0 O1 (0.096::0.127)(0.304::0.4)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S0 O2 (0.136::0.18)(0.398::0.523)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S0 O3 (0.156::0.206)(0.442::0.582)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S1 CO1 (0.126::0.166)(0.356::0.469)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S1 CO2 (0.153::0.202)(0.417::0.548)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S1 CO3 (0.146::0.192)(0.401::0.528)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S1 O1 (0.056::0.074)(0.156::0.205)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S1 O2 (0.143::0.189)(0.424::0.558)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S1 O3 (0.163::0.215)(0.47::0.618)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S2 CO2 (0.072::0.095)(0.222::0.292)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S2 CO3 (0.106::0.14)(0.286::0.376)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S2 O2 (0.057::0.075)(0.171::0.226)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S2 O3 (0.09::0.119)(0.251::0.33)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S3 CO3 (0.106::0.14)(0.289::0.38)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH S3 O3 (0.054::0.071)(0.172::0.227)) + ) + ) + ) (CELL (CELLTYPE "CARRY4_AX") (INSTANCE SLICEL) (DELAY (ABSOLUTE - (IOPATH DI0 CO2 (0.16::0.199)(0.435::0.54)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 O2 (0.157::0.196)(0.448::0.556)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 O3 (0.178::0.222)(0.496::0.615)) + (IOPATH DI0 CO0 (0.112::0.139)(0.306::0.379)) ) ) (DELAY @@ -26,6 +199,11 @@ (IOPATH DI0 CO1 (0.134::0.166)(0.375::0.465)) ) ) + (DELAY + (ABSOLUTE + (IOPATH DI0 CO2 (0.16::0.199)(0.435::0.54)) + ) + ) (DELAY (ABSOLUTE (IOPATH DI0 CO3 (0.161::0.201)(0.424::0.526)) @@ -38,7 +216,80 @@ ) (DELAY (ABSOLUTE - (IOPATH DI0 CO0 (0.112::0.139)(0.306::0.379)) + (IOPATH DI0 O2 (0.157::0.196)(0.448::0.556)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI0 O3 (0.178::0.222)(0.496::0.615)) + ) + ) + ) + (CELL + (CELLTYPE "CARRY4_AX_LBOTH") + (INSTANCE SLICEL) + (DELAY + (ABSOLUTE + (IOPATH DI0 CO0 (0.123::0.153)(0.343::0.425)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI0 CO1 (0.142::0.177)(0.393::0.487)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI0 CO2 (0.17::0.211)(0.456::0.566)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI0 O1 (0.131::0.163)(0.338::0.42)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI0 O2 (0.16::0.2)(0.462::0.573)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI0 O3 (0.182::0.227)(0.511::0.633)) + ) + ) + ) + (CELL + (CELLTYPE "CARRY4_AX_LFF") + (INSTANCE SLICEL) + (DELAY + (ABSOLUTE + (IOPATH DI0 CO0 (0.113::0.14)(0.301::0.374)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI0 CO1 (0.134::0.166)(0.373::0.462)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI0 CO2 (0.158::0.197)(0.432::0.536)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI0 O1 (0.124::0.154)(0.328::0.407)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI0 O2 (0.157::0.196)(0.448::0.556)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI0 O3 (0.177::0.22)(0.496::0.615)) ) ) ) @@ -57,7 +308,7 @@ ) (DELAY (ABSOLUTE - (IOPATH DI1 O3 (0.167::0.208)(0.481::0.596)) + (IOPATH DI1 CO3 (0.147::0.183)(0.409::0.507)) ) ) (DELAY @@ -67,386 +318,7 @@ ) (DELAY (ABSOLUTE - (IOPATH DI1 CO3 (0.147::0.183)(0.409::0.507)) - ) - ) - ) - (CELL - (CELLTYPE "SELMUX2_1") - (INSTANCE SLICEL/F7BMUX) - (DELAY - (ABSOLUTE - (IOPATH 1 OUT (0.065::0.081)(0.18::0.223)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 OUT (0.093::0.115)(0.239::0.296)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH 0 OUT (0.062::0.077)(0.175::0.217)) - ) - ) - ) - (CELL - (CELLTYPE "SELMUX2_1") - (INSTANCE SLICEL/F7AMUX) - (DELAY - (ABSOLUTE - (IOPATH 1 OUT (0.055::0.069)(0.156::0.193)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 OUT (0.085::0.106)(0.222::0.276)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH 0 OUT (0.053::0.067)(0.153::0.19)) - ) - ) - ) - (CELL - (CELLTYPE "SELMUX2_1") - (INSTANCE SLICEL/F8MUX) - (DELAY - (ABSOLUTE - (IOPATH 1 OUT (0.019::0.024)(0.076::0.094)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 OUT (0.08::0.1)(0.22::0.273)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH 0 OUT (0.023::0.028)(0.083::0.104)) - ) - ) - ) - (CELL - (CELLTYPE "LUT6") - (INSTANCE SLICEL/B6LUT) - (DELAY - (ABSOLUTE - (IOPATH A6 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A1 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A5 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A3 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A2 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A4 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - ) - (CELL - (CELLTYPE "LUT6") - (INSTANCE SLICEL/D6LUT) - (DELAY - (ABSOLUTE - (IOPATH A6 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A1 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A5 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A3 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A2 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A4 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - ) - (CELL - (CELLTYPE "LUT6") - (INSTANCE SLICEL/A6LUT) - (DELAY - (ABSOLUTE - (IOPATH A6 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A1 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A5 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A3 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A2 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A4 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - ) - (CELL - (CELLTYPE "LUT6") - (INSTANCE SLICEL/C6LUT) - (DELAY - (ABSOLUTE - (IOPATH A6 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A1 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A5 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A3 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A2 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A4 O6 (0.045::0.056)(0.1::0.124)) - ) - ) - ) - (CELL - (CELLTYPE "REG_INIT_FF_QL") - (INSTANCE SLICEL) - (TIMINGCHECK - (RECOVERY SR (posedge CLK) (0.326::0.404)) - ) - (TIMINGCHECK - (REMOVAL SR (posedge CLK) (-0.305::-0.248)) - ) - ) - (CELL - (CELLTYPE "FF_INIT_QL") - (INSTANCE SLICEL) - (TIMINGCHECK - (RECOVERY SR (posedge CLK) (0.326::0.404)) - ) - (TIMINGCHECK - (REMOVAL SR (posedge CLK) (-0.305::-0.248)) - ) - ) - (CELL - (CELLTYPE "FF_INIT_QH") - (INSTANCE SLICEL) - (TIMINGCHECK - (RECOVERY SR (posedge CLK) (0.288::0.358)) - ) - (TIMINGCHECK - (REMOVAL SR (posedge CLK) (-0.305::-0.248)) - ) - ) - (CELL - (CELLTYPE "REG_INIT_LAT_LOGIC_AND") - (INSTANCE SLICEL) - (DELAY - (ABSOLUTE - (IOPATH D Q (0.073::0.092)(0.213::0.264)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH SR Q (0.164::0.204)(0.638::0.791)) - ) - ) - ) - (CELL - (CELLTYPE "CARRY4_CX_LFF") - (INSTANCE SLICEL) - (DELAY - (ABSOLUTE - (IOPATH DI2 CO2 (0.099::0.124)(0.286::0.354)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI2 O3 (0.127::0.158)(0.354::0.439)) - ) - ) - ) - (CELL - (CELLTYPE "REG_INIT_FF") - (INSTANCE SLICEL) - (TIMINGCHECK - (HOLD INIT (posedge CLK) (-0.074::-0.06)) - ) - (TIMINGCHECK - (SETUP DIN (posedge CLK) (-0.055::-0.045)) - ) - (TIMINGCHECK - (HOLD DIN (posedge CLK) (0.194::0.241)) - ) - (TIMINGCHECK - (HOLD CE (posedge CLK) (-0.011::-0.009)) - ) - (DELAY - (ABSOLUTE - (IOPATH CLK Q (0.112::0.139)(0.274::0.34)) - ) - ) - (TIMINGCHECK - (SETUP INIT (posedge CLK) (0.345::0.428)) - ) - (TIMINGCHECK - (SETUP CE (posedge CLK) (0.088::0.109)) - ) - ) - (CELL - (CELLTYPE "REG_INIT_LAT") - (INSTANCE SLICEL) - (DELAY - (ABSOLUTE - (IOPATH CE Q (0.13::0.162)(0.409::0.507)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH D Q (0.073::0.092)(0.213::0.264)) - ) - ) - (TIMINGCHECK - (SETUP DIN (posedge CLK) (-0.068::-0.056)) - ) - (DELAY - (ABSOLUTE - (IOPATH CLK Q (0.129::0.16)(0.357::0.443)) - ) - ) - (TIMINGCHECK - (HOLD DIN (posedge CLK) (0.194::0.241)) - ) - ) - (CELL - (CELLTYPE "CARRY4_AX_LFF") - (INSTANCE SLICEL) - (DELAY - (ABSOLUTE - (IOPATH DI0 CO2 (0.158::0.197)(0.432::0.536)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 O2 (0.157::0.196)(0.448::0.556)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 O3 (0.177::0.22)(0.496::0.615)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 CO1 (0.134::0.166)(0.373::0.462)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 O1 (0.124::0.154)(0.328::0.407)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 CO0 (0.113::0.14)(0.301::0.374)) - ) - ) - ) - (CELL - (CELLTYPE "CARRY4_CX") - (INSTANCE SLICEL) - (DELAY - (ABSOLUTE - (IOPATH DI2 CO2 (0.099::0.124)(0.287::0.356)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI2 O3 (0.127::0.158)(0.353::0.438)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI2 CO3 (0.117::0.146)(0.321::0.398)) - ) - ) - ) - (CELL - (CELLTYPE "REG_INIT_LAT_LOGIC_OR") - (INSTANCE SLICEL) - (DELAY - (ABSOLUTE - (IOPATH D Q (0.073::0.092)(0.213::0.264)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH SR Q (0.164::0.204)(0.638::0.791)) - ) - ) - ) - (CELL - (CELLTYPE "CARRY4_DX") - (INSTANCE SLICEL) - (DELAY - (ABSOLUTE - (IOPATH DI3 CO3 (0.113::0.14)(0.31::0.385)) + (IOPATH DI1 O3 (0.167::0.208)(0.481::0.596)) ) ) ) @@ -498,6 +370,25 @@ ) ) ) + (CELL + (CELLTYPE "CARRY4_CX") + (INSTANCE SLICEL) + (DELAY + (ABSOLUTE + (IOPATH DI2 CO2 (0.099::0.124)(0.287::0.356)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI2 CO3 (0.117::0.146)(0.321::0.398)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI2 O3 (0.127::0.158)(0.353::0.438)) + ) + ) + ) (CELL (CELLTYPE "CARRY4_CX_LBOTH") (INSTANCE SLICEL) @@ -513,127 +404,36 @@ ) ) (CELL - (CELLTYPE "CARRY4_LFF") + (CELLTYPE "CARRY4_CX_LFF") (INSTANCE SLICEL) (DELAY (ABSOLUTE - (IOPATH CYINIT CO1 (0.144::0.18)(0.395::0.491)) + (IOPATH DI2 CO2 (0.099::0.124)(0.286::0.354)) ) ) (DELAY (ABSOLUTE - (IOPATH CIN O0 (0.055::0.081)(0.151::0.223)) + (IOPATH DI2 O3 (0.127::0.158)(0.354::0.439)) ) ) + ) + (CELL + (CELLTYPE "CARRY4_DX") + (INSTANCE SLICEL) (DELAY (ABSOLUTE - (IOPATH CIN CO0 (0.076::0.1)(0.204::0.268)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O1 (0.175::0.218)(0.482::0.598)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O3 (0.189::0.235)(0.516::0.64)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO2 (0.168::0.209)(0.474::0.589)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O3 (0.09::0.112)(0.25::0.311)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O0 (0.148::0.184)(0.385::0.477)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO2 (0.064::0.08)(0.183::0.227)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO1 (0.044::0.055)(0.125::0.155)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O2 (0.167::0.208)(0.468::0.581)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O1 (0.09::0.112)(0.269::0.334)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O2 (0.065::0.081)(0.192::0.239)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO0 (0.165::0.206)(0.429::0.532)) + (IOPATH DI3 CO3 (0.113::0.14)(0.31::0.385)) ) ) ) (CELL (CELLTYPE "CARRY4_LBOTH") (INSTANCE SLICEL) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO1 (0.152::0.189)(0.426::0.529)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O0 (0.057::0.085)(0.159::0.235)) - ) - ) (DELAY (ABSOLUTE (IOPATH CIN CO0 (0.086::0.113)(0.223::0.293)) ) ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O1 (0.183::0.228)(0.494::0.613)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O3 (0.194::0.241)(0.53::0.657)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO2 (0.18::0.224)(0.497::0.617)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O3 (0.092::0.114)(0.265::0.329)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O0 (0.152::0.189)(0.395::0.491)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO2 (0.075::0.094)(0.201::0.25)) - ) - ) (DELAY (ABSOLUTE (IOPATH CIN CO1 (0.052::0.064)(0.143::0.178)) @@ -641,7 +441,12 @@ ) (DELAY (ABSOLUTE - (IOPATH CYINIT O2 (0.172::0.214)(0.483::0.6)) + (IOPATH CIN CO2 (0.075::0.094)(0.201::0.25)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN O0 (0.057::0.085)(0.159::0.235)) ) ) (DELAY @@ -654,43 +459,127 @@ (IOPATH CIN O2 (0.07::0.087)(0.206::0.256)) ) ) + (DELAY + (ABSOLUTE + (IOPATH CIN O3 (0.092::0.114)(0.265::0.329)) + ) + ) (DELAY (ABSOLUTE (IOPATH CYINIT CO0 (0.177::0.22)(0.466::0.578)) ) ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT CO1 (0.152::0.189)(0.426::0.529)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT CO2 (0.18::0.224)(0.497::0.617)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O0 (0.152::0.189)(0.395::0.491)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O1 (0.183::0.228)(0.494::0.613)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O2 (0.172::0.214)(0.483::0.6)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O3 (0.194::0.241)(0.53::0.657)) + ) + ) + ) + (CELL + (CELLTYPE "CARRY4_LFF") + (INSTANCE SLICEL) + (DELAY + (ABSOLUTE + (IOPATH CIN CO0 (0.076::0.1)(0.204::0.268)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN CO1 (0.044::0.055)(0.125::0.155)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN CO2 (0.064::0.08)(0.183::0.227)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN O0 (0.055::0.081)(0.151::0.223)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN O1 (0.09::0.112)(0.269::0.334)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN O2 (0.065::0.081)(0.192::0.239)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN O3 (0.09::0.112)(0.25::0.311)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT CO0 (0.165::0.206)(0.429::0.532)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT CO1 (0.144::0.18)(0.395::0.491)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT CO2 (0.168::0.209)(0.474::0.589)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O0 (0.148::0.184)(0.385::0.477)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O1 (0.175::0.218)(0.482::0.598)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O2 (0.167::0.208)(0.468::0.581)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O3 (0.189::0.235)(0.516::0.64)) + ) + ) ) (CELL (CELLTYPE "CARRY4_O5") (INSTANCE SLICEL) (DELAY (ABSOLUTE - (IOPATH DI1 CO1 (0.092::0.122)(0.286::0.376)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI2 CO2 (0.071::0.094)(0.219::0.289)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 O1 (0.094::0.124)(0.256::0.337)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 CO3 (0.129::0.171)(0.346::0.456)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI2 CO3 (0.088::0.116)(0.246::0.324)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI1 O2 (0.11::0.146)(0.358::0.471)) + (IOPATH DI0 CO0 (0.085::0.112)(0.25::0.329)) ) ) (DELAY @@ -698,16 +587,6 @@ (IOPATH DI0 CO1 (0.103::0.136)(0.301::0.396)) ) ) - (DELAY - (ABSOLUTE - (IOPATH DI0 O3 (0.143::0.189)(0.414::0.545)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI1 O3 (0.131::0.174)(0.404::0.532)) - ) - ) (DELAY (ABSOLUTE (IOPATH DI0 CO2 (0.129::0.171)(0.36::0.474)) @@ -715,12 +594,12 @@ ) (DELAY (ABSOLUTE - (IOPATH DI1 CO2 (0.118::0.156)(0.349::0.459)) + (IOPATH DI0 CO3 (0.129::0.171)(0.346::0.456)) ) ) (DELAY (ABSOLUTE - (IOPATH DI3 CO3 (0.088::0.116)(0.248::0.327)) + (IOPATH DI0 O1 (0.094::0.124)(0.256::0.337)) ) ) (DELAY @@ -730,7 +609,42 @@ ) (DELAY (ABSOLUTE - (IOPATH DI0 CO0 (0.085::0.112)(0.25::0.329)) + (IOPATH DI0 O3 (0.143::0.189)(0.414::0.545)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI1 CO1 (0.092::0.122)(0.286::0.376)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI1 CO2 (0.118::0.156)(0.349::0.459)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI1 CO3 (0.115::0.152)(0.336::0.443)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI1 O2 (0.11::0.146)(0.358::0.471)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI1 O3 (0.131::0.174)(0.404::0.532)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI2 CO2 (0.071::0.094)(0.219::0.289)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH DI2 CO3 (0.088::0.116)(0.246::0.324)) ) ) (DELAY @@ -740,41 +654,7 @@ ) (DELAY (ABSOLUTE - (IOPATH DI1 CO3 (0.115::0.152)(0.336::0.443)) - ) - ) - ) - (CELL - (CELLTYPE "CARRY4_AX_LBOTH") - (INSTANCE SLICEL) - (DELAY - (ABSOLUTE - (IOPATH DI0 CO2 (0.17::0.211)(0.456::0.566)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 O2 (0.16::0.2)(0.462::0.573)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 O3 (0.182::0.227)(0.511::0.633)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 CO1 (0.142::0.177)(0.393::0.487)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 O1 (0.131::0.163)(0.338::0.42)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 CO0 (0.123::0.153)(0.343::0.425)) + (IOPATH DI3 CO3 (0.088::0.116)(0.248::0.327)) ) ) ) @@ -782,28 +662,327 @@ (CELLTYPE "FF_INIT") (INSTANCE SLICEL) (TIMINGCHECK - (HOLD INIT (posedge CLK) (-0.074::-0.06)) - ) - (TIMINGCHECK - (SETUP DIN (posedge CLK) (-0.057::-0.046)) + (HOLD CE (posedge CLK) (-0.011::-0.009)) ) (TIMINGCHECK (HOLD DIN (posedge CLK) (0.181::0.225)) ) (TIMINGCHECK - (HOLD CE (posedge CLK) (-0.011::-0.009)) + (HOLD INIT (posedge CLK) (-0.074::-0.06)) ) (DELAY (ABSOLUTE (IOPATH CLK Q (0.099::0.124)(0.244::0.303)) ) ) + (TIMINGCHECK + (SETUP CE (posedge CLK) (0.088::0.109)) + ) + (TIMINGCHECK + (SETUP DIN (posedge CLK) (-0.057::-0.046)) + ) (TIMINGCHECK (SETUP INIT (posedge CLK) (0.345::0.428)) ) + ) + (CELL + (CELLTYPE "FF_INIT_QH") + (INSTANCE SLICEL) + (TIMINGCHECK + (RECOVERY SR (posedge CLK) (0.288::0.358)) + ) + (TIMINGCHECK + (REMOVAL SR (posedge CLK) (-0.305::-0.248)) + ) + ) + (CELL + (CELLTYPE "FF_INIT_QL") + (INSTANCE SLICEL) + (TIMINGCHECK + (RECOVERY SR (posedge CLK) (0.326::0.404)) + ) + (TIMINGCHECK + (REMOVAL SR (posedge CLK) (-0.305::-0.248)) + ) + ) + (CELL + (CELLTYPE "LUT5") + (INSTANCE SLICEL/A5LUT) + (DELAY + (ABSOLUTE + (IOPATH A1 O5 (0.044::0.055)(0.122::0.152)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A2 O5 (0.044::0.055)(0.122::0.152)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A3 O5 (0.042::0.052)(0.121::0.15)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A4 O5 (0.046::0.057)(0.121::0.15)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A5 O5 (0.048::0.06)(0.095::0.118)) + ) + ) + ) + (CELL + (CELLTYPE "LUT5") + (INSTANCE SLICEL/B5LUT) + (DELAY + (ABSOLUTE + (IOPATH A1 O5 (0.045::0.056)(0.122::0.152)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A2 O5 (0.043::0.054)(0.122::0.152)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A3 O5 (0.043::0.053)(0.122::0.152)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A4 O5 (0.045::0.056)(0.121::0.15)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A5 O5 (0.049::0.061)(0.096::0.119)) + ) + ) + ) + (CELL + (CELLTYPE "LUT5") + (INSTANCE SLICEL/C5LUT) + (DELAY + (ABSOLUTE + (IOPATH A1 O5 (0.044::0.055)(0.124::0.154)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A2 O5 (0.043::0.053)(0.124::0.154)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A3 O5 (0.042::0.052)(0.123::0.153)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A4 O5 (0.045::0.056)(0.123::0.153)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A5 O5 (0.051::0.063)(0.097::0.12)) + ) + ) + ) + (CELL + (CELLTYPE "LUT5") + (INSTANCE SLICEL/D5LUT) + (DELAY + (ABSOLUTE + (IOPATH A1 O5 (0.044::0.055)(0.12::0.149)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A2 O5 (0.043::0.054)(0.121::0.15)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A3 O5 (0.042::0.052)(0.12::0.149)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A4 O5 (0.044::0.055)(0.12::0.149)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A5 O5 (0.049::0.061)(0.094::0.117)) + ) + ) + ) + (CELL + (CELLTYPE "LUT6") + (INSTANCE SLICEL/A6LUT) + (DELAY + (ABSOLUTE + (IOPATH A1 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A2 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A3 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A4 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A5 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A6 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + ) + (CELL + (CELLTYPE "LUT6") + (INSTANCE SLICEL/B6LUT) + (DELAY + (ABSOLUTE + (IOPATH A1 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A2 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A3 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A4 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A5 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A6 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + ) + (CELL + (CELLTYPE "LUT6") + (INSTANCE SLICEL/C6LUT) + (DELAY + (ABSOLUTE + (IOPATH A1 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A2 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A3 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A4 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A5 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A6 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + ) + (CELL + (CELLTYPE "LUT6") + (INSTANCE SLICEL/D6LUT) + (DELAY + (ABSOLUTE + (IOPATH A1 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A2 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A3 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A4 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A5 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A6 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + ) + (CELL + (CELLTYPE "REG_INIT_FF") + (INSTANCE SLICEL) + (TIMINGCHECK + (HOLD CE (posedge CLK) (-0.011::-0.009)) + ) + (TIMINGCHECK + (HOLD DIN (posedge CLK) (0.194::0.241)) + ) + (TIMINGCHECK + (HOLD INIT (posedge CLK) (-0.074::-0.06)) + ) + (DELAY + (ABSOLUTE + (IOPATH CLK Q (0.112::0.139)(0.274::0.34)) + ) + ) (TIMINGCHECK (SETUP CE (posedge CLK) (0.088::0.109)) ) + (TIMINGCHECK + (SETUP DIN (posedge CLK) (-0.055::-0.045)) + ) + (TIMINGCHECK + (SETUP INIT (posedge CLK) (0.345::0.428)) + ) ) (CELL (CELLTYPE "REG_INIT_FF_QH") @@ -816,302 +995,122 @@ ) ) (CELL - (CELLTYPE "CARRY4") + (CELLTYPE "REG_INIT_FF_QL") + (INSTANCE SLICEL) + (TIMINGCHECK + (RECOVERY SR (posedge CLK) (0.326::0.404)) + ) + (TIMINGCHECK + (REMOVAL SR (posedge CLK) (-0.305::-0.248)) + ) + ) + (CELL + (CELLTYPE "REG_INIT_LAT") + (INSTANCE SLICEL) + (TIMINGCHECK + (HOLD DIN (posedge CLK) (0.194::0.241)) + ) + (DELAY + (ABSOLUTE + (IOPATH CE Q (0.13::0.162)(0.409::0.507)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CLK Q (0.129::0.16)(0.357::0.443)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH D Q (0.073::0.092)(0.213::0.264)) + ) + ) + (TIMINGCHECK + (SETUP DIN (posedge CLK) (-0.068::-0.056)) + ) + ) + (CELL + (CELLTYPE "REG_INIT_LAT_LOGIC_AND") (INSTANCE SLICEL) (DELAY (ABSOLUTE - (IOPATH CYINIT CO1 (0.144::0.18)(0.398::0.494)) + (IOPATH D Q (0.073::0.092)(0.213::0.264)) ) ) (DELAY (ABSOLUTE - (IOPATH CIN CO2 (0.065::0.081)(0.184::0.228)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 O0 (0.06::0.079)(0.17::0.223)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO3 (0.039::0.049)(0.092::0.114)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O3 (0.19::0.236)(0.518::0.642)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO2 (0.169::0.21)(0.477::0.592)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O0 (0.147::0.183)(0.388::0.482)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S1 CO3 (0.146::0.192)(0.401::0.528)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S2 CO3 (0.106::0.14)(0.286::0.376)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 CO3 (0.142::0.187)(0.386::0.508)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO3 (0.173::0.215)(0.467::0.58)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 O3 (0.156::0.206)(0.442::0.582)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S2 CO2 (0.072::0.095)(0.222::0.292)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S1 O2 (0.143::0.189)(0.424::0.558)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O2 (0.167::0.208)(0.471::0.584)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S1 CO1 (0.126::0.166)(0.356::0.469)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S3 O3 (0.054::0.071)(0.172::0.227)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 CO0 (0.089::0.118)(0.258::0.34)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S2 O2 (0.057::0.075)(0.171::0.226)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S1 CO2 (0.153::0.202)(0.417::0.548)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 CO1 (0.118::0.156)(0.329::0.433)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO0 (0.165::0.206)(0.432::0.536)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 O2 (0.136::0.18)(0.398::0.523)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 CO2 (0.144::0.19)(0.389::0.512)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O0 (0.054::0.08)(0.15::0.222)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O3 (0.09::0.112)(0.252::0.313)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO0 (0.076::0.1)(0.206::0.271)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S1 O1 (0.056::0.074)(0.156::0.205)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S1 O3 (0.163::0.215)(0.47::0.618)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO1 (0.045::0.056)(0.127::0.157)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S3 CO3 (0.106::0.14)(0.289::0.38)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O1 (0.091::0.113)(0.269::0.334)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O1 (0.176::0.219)(0.482::0.598)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O2 (0.065::0.081)(0.192::0.239)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 O1 (0.096::0.127)(0.304::0.4)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S2 O3 (0.09::0.119)(0.251::0.33)) + (IOPATH SR Q (0.164::0.204)(0.638::0.791)) ) ) ) (CELL - (CELLTYPE "LUT5") - (INSTANCE SLICEL/A5LUT) + (CELLTYPE "REG_INIT_LAT_LOGIC_OR") + (INSTANCE SLICEL) (DELAY (ABSOLUTE - (IOPATH A2 O5 (0.044::0.055)(0.122::0.152)) + (IOPATH D Q (0.073::0.092)(0.213::0.264)) ) ) (DELAY (ABSOLUTE - (IOPATH A1 O5 (0.044::0.055)(0.122::0.152)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A4 O5 (0.046::0.057)(0.121::0.15)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A5 O5 (0.048::0.06)(0.095::0.118)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A3 O5 (0.042::0.052)(0.121::0.15)) + (IOPATH SR Q (0.164::0.204)(0.638::0.791)) ) ) ) (CELL - (CELLTYPE "LUT5") - (INSTANCE SLICEL/B5LUT) + (CELLTYPE "SELMUX2_1") + (INSTANCE SLICEL/F7AMUX) (DELAY (ABSOLUTE - (IOPATH A2 O5 (0.043::0.054)(0.122::0.152)) + (IOPATH 0 OUT (0.053::0.067)(0.153::0.19)) ) ) (DELAY (ABSOLUTE - (IOPATH A1 O5 (0.045::0.056)(0.122::0.152)) + (IOPATH 1 OUT (0.055::0.069)(0.156::0.193)) ) ) (DELAY (ABSOLUTE - (IOPATH A4 O5 (0.045::0.056)(0.121::0.15)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A5 O5 (0.049::0.061)(0.096::0.119)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A3 O5 (0.043::0.053)(0.122::0.152)) + (IOPATH S0 OUT (0.085::0.106)(0.222::0.276)) ) ) ) (CELL - (CELLTYPE "LUT5") - (INSTANCE SLICEL/C5LUT) + (CELLTYPE "SELMUX2_1") + (INSTANCE SLICEL/F7BMUX) (DELAY (ABSOLUTE - (IOPATH A2 O5 (0.043::0.053)(0.124::0.154)) + (IOPATH 0 OUT (0.062::0.077)(0.175::0.217)) ) ) (DELAY (ABSOLUTE - (IOPATH A1 O5 (0.044::0.055)(0.124::0.154)) + (IOPATH 1 OUT (0.065::0.081)(0.18::0.223)) ) ) (DELAY (ABSOLUTE - (IOPATH A4 O5 (0.045::0.056)(0.123::0.153)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A5 O5 (0.051::0.063)(0.097::0.12)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A3 O5 (0.042::0.052)(0.123::0.153)) + (IOPATH S0 OUT (0.093::0.115)(0.239::0.296)) ) ) ) (CELL - (CELLTYPE "LUT5") - (INSTANCE SLICEL/D5LUT) + (CELLTYPE "SELMUX2_1") + (INSTANCE SLICEL/F8MUX) (DELAY (ABSOLUTE - (IOPATH A2 O5 (0.043::0.054)(0.121::0.15)) + (IOPATH 0 OUT (0.023::0.028)(0.083::0.104)) ) ) (DELAY (ABSOLUTE - (IOPATH A1 O5 (0.044::0.055)(0.12::0.149)) + (IOPATH 1 OUT (0.019::0.024)(0.076::0.094)) ) ) (DELAY (ABSOLUTE - (IOPATH A4 O5 (0.044::0.055)(0.12::0.149)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A5 O5 (0.049::0.061)(0.094::0.117)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH A3 O5 (0.042::0.052)(0.12::0.149)) + (IOPATH S0 OUT (0.08::0.1)(0.22::0.273)) ) ) ) diff --git a/zynq7/timings/slicem.sdf b/zynq7/timings/slicem.sdf index 3b4efd1..b4392c9 100644 --- a/zynq7/timings/slicem.sdf +++ b/zynq7/timings/slicem.sdf @@ -1,46 +1,918 @@ - (DELAYFILE (SDFVERSION "3.0") (TIMESCALE 1ps) (CELL - (CELLTYPE "REG_INIT_LAT") + (CELLTYPE "CARRY4") + (INSTANCE SLICEM) + (DELAY + (ABSOLUTE + (IOPATH CIN CO0 (0.073::0.097)(0.193::0.254)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN CO1 (0.045::0.056)(0.127::0.157)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN CO2 (0.066::0.082)(0.185::0.229)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN CO3 (0.04::0.05)(0.094::0.117)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN O0 (0.053::0.079)(0.148::0.219)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN O1 (0.09::0.112)(0.26::0.323)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN O2 (0.066::0.082)(0.192::0.239)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CIN O3 (0.092::0.114)(0.254::0.315)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT CO0 (0.172::0.214)(0.453::0.561)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT CO1 (0.15::0.187)(0.412::0.511)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT CO2 (0.175::0.217)(0.49::0.608)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT CO3 (0.179::0.223)(0.48::0.595)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O0 (0.158::0.197)(0.411::0.51)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH CYINIT O1 (0.185::0.23)(0.508::0.63)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH 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(0.439::0.547)(1.19::1.476)) + ) + ) + (TIMINGCHECK + (SETUP DI1 (posedge CLK) (0.126::0.156)) + ) + ) (CELL (CELLTYPE "LUT_OR_MEM5SHFREG") (INSTANCE SLICEM/C5LUT) @@ -89,570 +976,464 @@ ) ) (CELL - (CELLTYPE "LUT_OR_MEM5SHFREG") + (CELLTYPE "LUT_OR_MEM6LRAM") (INSTANCE SLICEM) (TIMINGCHECK - (SETUP WE (posedge CLK) (0.514::0.638)) + (HOLD WA1 (posedge CLK) (0.728::0.538)) ) + (TIMINGCHECK + (HOLD WA2 (posedge CLK) (0.745::0.572)) + ) + (TIMINGCHECK + (HOLD WA3 (posedge CLK) (0.579::0.46)) + ) + (TIMINGCHECK + (HOLD WA4 (posedge CLK) (0.507::0.411)) + ) + (TIMINGCHECK + (HOLD WA5 (posedge CLK) (0.332::0.314)) + ) + (TIMINGCHECK + (HOLD WA6 (posedge CLK) (0.213::0.244)) + ) + (TIMINGCHECK + (HOLD WA7 (posedge CLK) (0.184::0.228)) + ) + (TIMINGCHECK + (HOLD WA8 (posedge CLK) (0.199::0.247)) + ) + (TIMINGCHECK + (HOLD WE (posedge CLK) (0.008::0.01)) + ) + (TIMINGCHECK + (SETUP WA1 (posedge CLK) (0.184::0.066)) + ) + (TIMINGCHECK + (SETUP WA2 (posedge CLK) (0.181::0.068)) + ) + (TIMINGCHECK + (SETUP WA3 (posedge CLK) (0.214::0.147)) + ) + (TIMINGCHECK + (SETUP WA4 (posedge CLK) (0.248::0.208)) + ) + (TIMINGCHECK + (SETUP WA5 (posedge CLK) (0.236::0.245)) + ) + (TIMINGCHECK + (SETUP WA6 (posedge CLK) (0.302::0.362)) + ) + (TIMINGCHECK + (SETUP WA7 (posedge CLK) (0.496::0.616)) + ) + (TIMINGCHECK + (SETUP WA8 (posedge CLK) (0.511::0.633)) + ) + (TIMINGCHECK + (SETUP WE (posedge CLK) (0.527::0.654)) + ) + ) + (CELL + (CELLTYPE "LUT_OR_MEM6LRAM") + (INSTANCE SLICEM/A6LUT) + (TIMINGCHECK + (HOLD DI1 (posedge CLK) (0.155::0.192)) + ) + (TIMINGCHECK + (HOLD DI2 (posedge CLK) (0.098::0.122)) + ) + (DELAY + (ABSOLUTE + (IOPATH A1 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A2 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A3 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A4 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + (ABSOLUTE + (IOPATH A5 O6 (0.045::0.056)(0.1::0.124)) + ) + ) + (DELAY + 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(0.175::0.217)(0.49::0.608)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S1 O1 (0.057::0.075)(0.16::0.21)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 O2 (0.135::0.178)(0.395::0.52)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO3 (0.179::0.223)(0.48::0.595)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S1 CO3 (0.143::0.189)(0.39::0.513)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O2 (0.173::0.215)(0.485::0.602)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O1 (0.185::0.23)(0.508::0.63)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S2 CO3 (0.102::0.134)(0.272::0.358)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O0 (0.158::0.197)(0.411::0.51)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S2 CO2 (0.072::0.096)(0.225::0.296)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 CO1 (0.118::0.156)(0.33::0.434)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO1 (0.045::0.056)(0.127::0.157)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO0 (0.172::0.214)(0.453::0.561)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O1 (0.09::0.112)(0.26::0.323)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 O3 (0.155::0.205)(0.444::0.584)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO0 (0.073::0.097)(0.193::0.254)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 CO0 (0.087::0.115)(0.258::0.34)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O2 (0.066::0.082)(0.192::0.239)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S3 CO3 (0.1::0.132)(0.269::0.354)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S1 O3 (0.163::0.215)(0.474::0.623)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH S0 CO3 (0.135::0.179)(0.372::0.489)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O0 (0.053::0.079)(0.148::0.219)) - ) + (TIMINGCHECK + (SETUP DI2 (posedge CLK) (0.143::0.178)) ) ) (CELL - (CELLTYPE "CARRY4_CX_LBOTH") - (INSTANCE SLICEM) + (CELLTYPE "LUT_OR_MEM6SHFREG") + (INSTANCE SLICEM/C6LUT) + (TIMINGCHECK + (HOLD DI1 (posedge CLK) (0.058::0.072)) + ) + (TIMINGCHECK + (HOLD DI2 (posedge CLK) (0.062::0.077)) + ) (DELAY (ABSOLUTE - (IOPATH DI2 CO2 (0.108::0.134)(0.315::0.391)) + (IOPATH CLK MC31 (0.285::0.355)(0.784::0.972)) ) ) (DELAY (ABSOLUTE - (IOPATH DI2 O3 (0.132::0.164)(0.373::0.463)) + (IOPATH CLK O6 (0.436::0.543)(1.169::1.45)) ) ) + (TIMINGCHECK + (SETUP DI1 (posedge CLK) (0.117::0.145)) + ) + (TIMINGCHECK + (SETUP DI2 (posedge CLK) (0.116::0.144)) + ) ) (CELL - (CELLTYPE "CARRY4_BX_LFF") - (INSTANCE SLICEM) + (CELLTYPE "LUT_OR_MEM6SHFREG") + (INSTANCE SLICEM/D6LUT) + (TIMINGCHECK + (HOLD DI1 (posedge CLK) (0.217::0.269)) + ) + (TIMINGCHECK + (HOLD DI2 (posedge CLK) (0.091::0.112)) + ) (DELAY (ABSOLUTE - (IOPATH DI1 O2 (0.149::0.185)(0.44::0.546)) + (IOPATH CLK MC31 (0.286::0.357)(0.788::0.978)) ) ) (DELAY (ABSOLUTE - (IOPATH DI1 CO1 (0.124::0.155)(0.364::0.451)) + (IOPATH CLK O6 (0.438::0.545)(1.174::1.456)) ) ) - (DELAY - (ABSOLUTE - (IOPATH DI1 CO2 (0.15::0.187)(0.426::0.529)) - ) + (TIMINGCHECK + (SETUP DI1 (posedge CLK) (-0.04::-0.033)) ) - (DELAY - (ABSOLUTE - (IOPATH DI1 O3 (0.17::0.212)(0.492::0.61)) - ) - ) - ) - (CELL - (CELLTYPE "CARRY4_AX") - (INSTANCE SLICEM) - (DELAY - (ABSOLUTE - (IOPATH DI0 O2 (0.164::0.204)(0.467::0.579)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 CO2 (0.167::0.208)(0.454::0.564)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 O3 (0.187::0.233)(0.518::0.642)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 O1 (0.129::0.161)(0.34::0.422)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 CO0 (0.117::0.146)(0.317::0.393)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 CO3 (0.169::0.21)(0.444::0.55)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH DI0 CO1 (0.141::0.176)(0.394::0.488)) - ) - ) - ) - (CELL - (CELLTYPE "CARRY4_LBOTH") - (INSTANCE SLICEM) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O1 (0.191::0.238)(0.519::0.644)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O0 (0.161::0.201)(0.419::0.52)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O3 (0.094::0.116)(0.267::0.331)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO1 (0.051::0.063)(0.144::0.179)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO0 (0.184::0.229)(0.476::0.591)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO2 (0.075::0.094)(0.203::0.252)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O1 (0.097::0.121)(0.272::0.337)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O3 (0.201::0.251)(0.547::0.678)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO0 (0.084::0.111)(0.214::0.281)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O2 (0.072::0.089)(0.206::0.256)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO2 (0.185::0.23)(0.51::0.632)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O2 (0.178::0.222)(0.495::0.614)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO1 (0.156::0.194)(0.44::0.546)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O0 (0.057::0.084)(0.157::0.232)) - ) + (TIMINGCHECK + (SETUP DI2 (posedge CLK) (0.133::0.165)) ) ) (CELL (CELLTYPE "REG_INIT_FF") (INSTANCE SLICEM) + (TIMINGCHECK + (HOLD CE (posedge CLK) (-0.007::-0.005)) + ) (TIMINGCHECK (HOLD DIN (posedge CLK) (0.211::0.262)) ) + (TIMINGCHECK + (HOLD INIT (posedge CLK) (-0.05::-0.041)) + ) (DELAY (ABSOLUTE (IOPATH CLK Q (0.118::0.147)(0.292::0.362)) ) ) (TIMINGCHECK - (HOLD INIT (posedge CLK) (-0.05::-0.041)) - ) - (TIMINGCHECK - (HOLD CE (posedge CLK) (-0.007::-0.005)) + (SETUP CE (posedge CLK) (0.088::0.109)) ) (TIMINGCHECK (SETUP DIN (posedge CLK) (-0.074::-0.06)) ) - (TIMINGCHECK - (SETUP CE (posedge CLK) (0.088::0.109)) - ) (TIMINGCHECK (SETUP INIT (posedge CLK) (0.445::0.552)) ) ) (CELL - (CELLTYPE "CARRY4_LFF") + (CELLTYPE "REG_INIT_FF_QH") (INSTANCE SLICEM) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O1 (0.184::0.229)(0.509::0.631)) - ) + (TIMINGCHECK + (RECOVERY SR (posedge CLK) (0.314::0.389)) ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O0 (0.158::0.197)(0.41::0.509)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O3 (0.091::0.113)(0.253::0.314)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO1 (0.045::0.056)(0.125::0.155)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO0 (0.172::0.214)(0.45::0.558)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO2 (0.064::0.08)(0.184::0.228)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O1 (0.089::0.111)(0.26::0.323)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O3 (0.196::0.244)(0.533::0.662)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN CO0 (0.073::0.097)(0.19::0.25)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O2 (0.066::0.082)(0.192::0.239)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO2 (0.173::0.215)(0.489::0.606)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT O2 (0.172::0.214)(0.482::0.598)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CYINIT CO1 (0.15::0.187)(0.409::0.508)) - ) - ) - (DELAY - (ABSOLUTE - (IOPATH CIN O0 (0.053::0.079)(0.147::0.218)) - ) + (TIMINGCHECK + (REMOVAL SR (posedge CLK) (-0.292::-0.238)) ) ) (CELL - (CELLTYPE "CARRY4_DX") + (CELLTYPE "REG_INIT_FF_QL") (INSTANCE SLICEM) - (DELAY - (ABSOLUTE - (IOPATH DI3 CO3 (0.117::0.146)(0.319::0.396)) - ) + (TIMINGCHECK + (RECOVERY SR (posedge CLK) (0.279::0.347)) + ) + (TIMINGCHECK + (REMOVAL SR (posedge CLK) (-0.285::-0.232)) ) ) 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